Re: [Intel-gfx] [PATCH v5 3/3] PM/runtime:Replace jiffies based accounting with ktime based accounting
On Mon, 21 Jan 2019 at 23:53, Rafael J. Wysocki wrote: > > On Mon, Jan 21, 2019 at 4:17 PM Vincent Guittot > wrote: > > > > On Fri, 18 Jan 2019 at 13:08, Guenter Roeck wrote: > > > > > > On 1/18/19 3:05 AM, Rafael J. Wysocki wrote: > > > > On Fri, Jan 18, 2019 at 11:53 AM Vincent Guittot > > > > wrote: > > > >> > > > >> On Fri, 18 Jan 2019 at 11:42, Vincent Guittot > > > >> wrote: > > > >>> > > > >>> Hi Guenter, > > > >>> > > > >>> Le Thursday 17 Jan 2019 à 14:16:28 (-0800), Guenter Roeck a écrit : > > > On Fri, Dec 21, 2018 at 11:33:56AM +0100, Vincent Guittot wrote: > > > > From: Thara Gopinath > > > > > > > > This patch replaces jiffies based accounting for runtime_active_time > > > > and runtime_suspended_time with ktime base accounting. This makes > > > > the > > > > runtime debug counters inline with genpd and other pm subsytems > > > > which > > > > uses ktime based accounting. > > > > > > > > timekeeping is initialized before pm_runtime_init() so ktime_get() > > > > will > > > > be ready before first call. In fact, timekeeping_init() is called > > > > early > > > > in start_kernel() which is way before driver_init() (and that's when > > > > devices can start to be initialized) called from rest_init() via > > > > kernel_init_freeable() and do_basic_setup(). > > > > > > > This is not (always) correct. My qemu "collie" boot test fails with > > > this > > > patch applied. Reverting the patch fixes the problem. Bisect log > > > attached. > > > > > > >>> > > > >>> Can you try the patch below ? > > > >>> ktime_get_mono_fast_ns() has the advantage of being init with dummy > > > >>> clock so > > > >>> it can be used at early_init. > > > >> > > > >> Another possibility would be delay the init of the gpiochip > > > > > > > > Well, right. > > > > > > > > Initializing devices before timekeeping doesn't feel particularly > > > > robust from the design perspective. > > > > > > > > How exactly does that happen? > > > > > > > > > > With an added 'initialized' flag and backtrace into the timekeeping code, > > > with the change suggested earlier applied: > > > > > > [ cut here ] > > > WARNING: CPU: 0 PID: 0 at kernel/time/timekeeping.c:453 > > > ktime_get_mono_fast_ns+0x114/0x12c > > > Timekeeping not initialized > > > CPU: 0 PID: 0 Comm: swapper Not tainted 5.0.0-rc2-next-20190117-dirty #2 > > > Hardware name: Sharp-Collie > > > Backtrace: > > > [] (dump_backtrace) from [] (show_stack+0x18/0x1c) > > > r7:0009 r6: r5:c065ba90 r4:c06d3e54 > > > [] (show_stack) from [] (dump_stack+0x20/0x28) > > > [] (dump_stack) from [] (__warn+0xcc/0xf4) > > > [] (__warn) from [] (warn_slowpath_fmt+0x4c/0x6c) > > > r8:df407b08 r7: r6:c0c01550 r5:c065bad8 r4:c06dd028 > > > [] (warn_slowpath_fmt) from [] > > > (ktime_get_mono_fast_ns+0x114/0x12c) > > > r3: r2:c065bad8 > > > r5: r4:df407b08 > > > [] (ktime_get_mono_fast_ns) from [] > > > (pm_runtime_init+0x38/0xb8) > > > r9:c06c9a5c r8:df407b08 r7: r6:c0c01550 r5: r4:df407b08 > > > [] (pm_runtime_init) from [] > > > (device_initialize+0xb0/0xec) > > > r7: r6:c0c01550 r5: r4:df407b08 > > > [] (device_initialize) from [] > > > (gpiochip_add_data_with_key+0x9c/0x884) > > > r7: r6:c06fca34 r5: r4: > > > [] (gpiochip_add_data_with_key) from [] > > > (sa1100_init_gpio+0x40/0x98) > > > r10:dfffcd60 r9:c06c9a5c r8:c06dd020 r7:c06dd028 r6: r5: > > > r4:c06fca34 > > > [] (sa1100_init_gpio) from [] > > > (sa1100_init_irq+0x2c/0x3c) > > > r7:c06dd028 r6: r5:c0713300 r4:c06e1070 > > > [] (sa1100_init_irq) from [] (init_IRQ+0x20/0x28) > > > r5:c0713300 r4: > > > [] (init_IRQ) from [] (start_kernel+0x254/0x4cc) > > > [] (start_kernel) from [<>] ( (null)) > > > r10:717f r9:6901b119 r8:c100 r7:0092 r6:313d r5:0053 > > > r4:c06a7330 > > > ---[ end trace 91e1bd00dd7cce32 ]--- > > > > Does it means that only the pm_runtime_init is done before > > timekeeping_init() but no update_pm_runtime_accounting() ? > > This platform calls device_initialize(), via sa1100_init_irq(), from > init_IRQ() which is in the start_kernel() code path before > timekeeping_init(). That's the initialization of structure fields > alone. > > Runtime PM really cannot be used legitimately before driver_init(), > because it needs bus types to be there at least. > > > In this case, we can keep using ktimeçget in > > update_pm_runtime_accounting() and find a solution to deal with > > early_call of pm_runtime_init() > > Given the above, I think that initializing accounting_timestamp in > pm_runtime_init() to anything different from 0 is a mistake. I agree > > Note that update_pm_runtime_accounting() ignores the delta value if > power.disable_depth is not zero anyway, so it really should be > sufficient to update
[Intel-gfx] ✓ Fi.CI.IGT: success for Define MOCS table for Icelake (rev2)
== Series Details ==
Series: Define MOCS table for Icelake (rev2)
URL : https://patchwork.freedesktop.org/series/54070/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459_full -> Patchwork_12002_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12002_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> FAIL [fdo#108597]
* igt@kms_cursor_crc@cursor-64x21-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166]
- shard-apl: PASS -> FAIL [fdo#103166]
Possible fixes
* igt@kms_busy@extended-pageflip-hang-oldfb-render-b:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-128x42-random:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-untiled:
- shard-snb: {SKIP} [fdo#109271] -> PASS +3
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: FAIL -> PASS
* igt@kms_setmode@basic:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
- shard-kbl: FAIL [fdo#99912] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_12002
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12002: d4f7316f00e20115e8fb29d92d2d80bba89a7b45 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12002/
___
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: Re-enable fastset by default
On 08-01-19 17:08, Maarten Lankhorst wrote: Now that we've solved the backlight issue, I think it's time to enable this again by default. We've enabled it in the past, but backlight issues prevented us from enabling it by default. Our hardware readout is pretty complete, and with all of the connector state moved to atomic I'm hoping we finally have enough capability to re-enable fastset by default. Signed-off-by: Maarten Lankhorst Reviewed-by: Hans de Goede --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 6efcf330bdab..7dd71bc85106 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -66,7 +66,7 @@ struct drm_printer; /* leave bools at the end to not create holes */ \ param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \ param(bool, enable_hangcheck, true) \ - param(bool, fastboot, false) \ + param(bool, fastboot, true) \ param(bool, prefault_disable, false) \ param(bool, load_detect_test, false) \ param(bool, force_reset_modeset_test, false) \ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915/backlight: Fix backlight takeover on LPT, v3.
On 08-01-19 17:08, Maarten Lankhorst wrote:
On lynxpoint the bios sometimes sets up the backlight using the CPU
display, but the driver expects using the PWM PCH override register.
Read the value from the CPU register, then convert it to the other
units by converting from the old duty cycle, to freq, to the new units.
This value is then programmed in the override register, after which
we set the override and disable the CPU display control. This allows
us to switch the source without flickering, and make the backlight
controls work in the driver.
Changes since v1:
- Read BLC_PWM_CPU_CTL2 to cpu_ctl2.
- Clean up cpu_mode if slightly.
- Always disable BLM_PWM_ENABLE in cpu_ctl2.
Changes since v2:
- Simplify cpu_mode handling (Jani)
Signed-off-by: Maarten Lankhorst
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108225
Cc: Basil Eric Rabi
Cc: Hans de Goede
Cc: Tolga Cakir
Cc: Ville Syrjälä
Tested-by: Tolga Cakir
Cc: Jani Nikula
Reviewed-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_panel.c | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f71b33cf1c97..1c9ef54d58fe 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1493,8 +1493,8 @@ static int lpt_setup_backlight(struct intel_connector
*connector, enum pipe unus
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_panel *panel = >panel;
- u32 pch_ctl1, pch_ctl2, val;
- bool alt;
+ u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;
+ bool alt, cpu_mode;
if (HAS_PCH_LPT(dev_priv))
alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
@@ -1508,6 +1508,8 @@ static int lpt_setup_backlight(struct intel_connector
*connector, enum pipe unus
pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
panel->backlight.max = pch_ctl2 >> 16;
+ cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
+
if (!panel->backlight.max)
panel->backlight.max = get_backlight_max_vbt(connector);
@@ -1516,12 +1518,28 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus
panel->backlight.min = get_backlight_min_vbt(connector);
- val = lpt_get_backlight(connector);
+ panel->backlight.enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE;
+
+ cpu_mode = panel->backlight.enabled && HAS_PCH_LPT(dev_priv) &&
+ !(pch_ctl1 & BLM_PCH_OVERRIDE_ENABLE) &&
+ (cpu_ctl2 & BLM_PWM_ENABLE);
+ if (cpu_mode)
+ val = pch_get_backlight(connector);
+ else
+ val = lpt_get_backlight(connector);
val = intel_panel_compute_brightness(connector, val);
panel->backlight.level = clamp(val, panel->backlight.min,
panel->backlight.max);
- panel->backlight.enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE;
+ if (cpu_mode) {
+ DRM_DEBUG_KMS("CPU backlight register was enabled, switching to PCH
override\n");
+
+ /* Write converted CPU PWM value to PCH override register */
+ lpt_set_backlight(connector->base.state,
panel->backlight.level);
+ I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 |
BLM_PCH_OVERRIDE_ENABLE);
+
+ I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 & ~BLM_PWM_ENABLE);
+ }
return 0;
}
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915: Enable fastset for non-boot modesets.
On 08-01-19 17:08, Maarten Lankhorst wrote:
Now that our state comparison functions are pretty complete, we should
enable fastset by default when a modeset can be avoided. Even if we're
not completely certain about the inherited state, we can be certain
after the first modeset that our sw state matches the hw state.
There is one testcase explicitly testing fastset,
kms_panel_fitting.atomic-fastset but other testcases do so indirectly
because most tests don't clean up the display during exit, or otherwise
indirectly preserve mode by doing igt_display_reset or inheriting during
init.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Hans de Goede
Cc: Daniel Vetter
Reviewed-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_display.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 696e6f5680df..f8cbdd50fa38 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11671,6 +11671,11 @@ intel_pipe_config_compare(struct drm_i915_private
*dev_priv,
(current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
&&
!(pipe_config->base.mode.private_flags &
I915_MODE_FLAG_INHERITED);
+ if (fixup_inherited && !i915_modparams.fastboot) {
+ drm_dbg(DRM_UT_KMS, "initial modeset and fastboot not set\n");
+ ret = false;
+ }
+
#define PIPE_CONF_CHECK_X(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_err(adjust, __stringify(name), \
@@ -12694,8 +12699,7 @@ static int intel_atomic_check(struct drm_device *dev,
return ret;
}
- if (i915_modparams.fastboot &&
- intel_pipe_config_compare(dev_priv,
+ if (intel_pipe_config_compare(dev_priv,
to_intel_crtc_state(old_crtc_state),
pipe_config, true)) {
crtc_state->mode_changed = false;
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Define MOCS table for Icelake (rev2)
== Series Details ==
Series: Define MOCS table for Icelake (rev2)
URL : https://patchwork.freedesktop.org/series/54070/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459 -> Patchwork_12002
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/54070/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_12002 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:DMESG-FAIL [fdo#108735] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u2}:FAIL [fdo#103167] -> PASS
* igt@pm_rpm@module-reload:
- {fi-icl-u2}:DMESG-WARN [fdo#108654] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (47 -> 41)
--
Additional (1): fi-glk-j4005
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_12002
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12002: d4f7316f00e20115e8fb29d92d2d80bba89a7b45 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d4f7316f00e2 drm/i915/icl: Define MOCS table for Icelake
9ace3442d5cf drm/i915: cache number of MOCS entries
c0f65453147a drm/i915: keep track of used entries in MOCS table
75c2a9d1ab5d drm/i915: use a macro to define MOCS entries
d732afcb4803 drm/i915/skl: Rework MOCS tables to keep common part in a define
392416ee2864 drm/i915: Simplify MOCS table definition
42a8e03cdfa2 drm/i915: initialize unused MOCS entries to PTE
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12002/
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Define MOCS table for Icelake (rev2)
== Series Details == Series: Define MOCS table for Icelake (rev2) URL : https://patchwork.freedesktop.org/series/54070/ State : warning == Summary == $ dim checkpatch origin/drm-tip 42a8e03cdfa2 drm/i915: initialize unused MOCS entries to PTE 392416ee2864 drm/i915: Simplify MOCS table definition d732afcb4803 drm/i915/skl: Rework MOCS tables to keep common part in a define 75c2a9d1ab5d drm/i915: use a macro to define MOCS entries -:63: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #63: FILE: drivers/gpu/drm/i915/intel_mocs.c:111: + MOCS_ENTRY(I915_MOCS_CACHED,LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3), + L3_3_WB) -:76: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #76: FILE: drivers/gpu/drm/i915/intel_mocs.c:118: + MOCS_ENTRY(I915_MOCS_CACHED,LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3), + L3_3_WB) total: 0 errors, 0 warnings, 2 checks, 60 lines checked c0f65453147a drm/i915: keep track of used entries in MOCS table 9ace3442d5cf drm/i915: cache number of MOCS entries d4f7316f00e2 drm/i915/icl: Define MOCS table for Icelake -:92: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #92: FILE: drivers/gpu/drm/i915/intel_mocs.c:131: +#define GEN11_MOCS_ENTRIES \ + /* Base - Uncached (Deprecated) */ \ + MOCS_ENTRY(I915_MOCS_UNCACHED, LE_1_UC | LE_TC_1_LLC, \ + L3_1_UC), \ + /* Base - L3 + LeCC:PAT (Deprecated) */ \ + MOCS_ENTRY(I915_MOCS_PTE, LE_0_PAGETABLE | LE_TC_1_LLC, \ + L3_3_WB), \ + /* Base - L3 + LLC */ \ + MOCS_ENTRY(2, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_3_WB), \ + /* Base - Uncached */ \ + MOCS_ENTRY(3, LE_1_UC | LE_TC_1_LLC, \ + L3_1_UC), \ + /* Base - L3 */ \ + MOCS_ENTRY(4, LE_1_UC | LE_TC_1_LLC, \ + L3_3_WB), \ + /* Base - LLC */ \ + MOCS_ENTRY(5, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_1_UC), \ + /* Age 0 - LLC */ \ + MOCS_ENTRY(6, LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \ + L3_1_UC), \ + /* Age 0 - L3 + LLC */ \ + MOCS_ENTRY(7, LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \ + L3_3_WB), \ + /* Age: Don't Chg. - LLC */ \ + MOCS_ENTRY(8, LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \ + L3_1_UC), \ + /* Age: Don't Chg. - L3 + LLC */ \ + MOCS_ENTRY(9, LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \ + L3_3_WB), \ + /* No AOM - LLC */ \ + MOCS_ENTRY(10, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \ + L3_1_UC), \ + /* No AOM - L3 + LLC */ \ + MOCS_ENTRY(11, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \ + L3_3_WB), \ + /* No AOM; Age 0 - LLC */ \ + MOCS_ENTRY(12, LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \ + L3_1_UC), \ + /* No AOM; Age 0 - L3 + LLC */ \ + MOCS_ENTRY(13, LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \ + L3_3_WB), \ + /* No AOM; Age:DC - LLC */ \ + MOCS_ENTRY(14, LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ + L3_1_UC), \ + /* No AOM; Age:DC - L3 + LLC */ \ + MOCS_ENTRY(15, LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ + L3_3_WB), \ + /* Self-Snoop - L3 + LLC */ \ + MOCS_ENTRY(18, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \ + L3_3_WB), \ + /* Skip Caching - L3 + LLC(12.5%) */ \ + MOCS_ENTRY(19, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \ + L3_3_WB), \ + /* Skip Caching - L3 + LLC(25%) */ \ + MOCS_ENTRY(20, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \ + L3_3_WB), \ + /* Skip Caching - L3 + LLC(50%) */ \ + MOCS_ENTRY(21, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \ + L3_3_WB), \ + /* Skip Caching - L3 + LLC(75%) */ \ + MOCS_ENTRY(22, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \ + L3_3_WB), \ + /* Skip Caching - L3 + LLC(87.5%) */ \ + MOCS_ENTRY(23, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \ + L3_3_WB), \ + /* HW Reserved - SW program but never use */ \ + MOCS_ENTRY(62, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_1_UC), \ + /* HW Reserved - SW program but never use */ \ + MOCS_ENTRY(63, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \ + L3_1_UC), \ + total: 1 errors, 0 warnings, 0 checks, 142 lines checked ___ Intel-gfx mailing list
[Intel-gfx] [PATCH v8 6/7] drm/i915: cache number of MOCS entries
Instead of checking the gen number every time we need to know the max
number of entries, just save it into the table struct so we don't need
extra branches throughout the code. This will be useful for Ice Lake
that has 64 rather than 62 defined entries. Ice Lake changes will be
added in a follow up.
v2: make size and n_entries `unsigned int` and introduce changes as a
pre-work for the Ice Lake changes (Tvrtko)
Suggested-by: Tvrtko Ursulin
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_mocs.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index af2ae2f396ae..716f3f6f2966 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -32,7 +32,8 @@ struct drm_i915_mocs_entry {
};
struct drm_i915_mocs_table {
- u32 size;
+ unsigned int size;
+ unsigned int n_entries;
const struct drm_i915_mocs_entry *table;
};
@@ -140,10 +141,12 @@ static bool get_mocs_settings(struct drm_i915_private
*dev_priv,
if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
IS_ICELAKE(dev_priv)) {
table->size = ARRAY_SIZE(skylake_mocs_table);
+ table->n_entries = GEN9_NUM_MOCS_ENTRIES;
table->table = skylake_mocs_table;
result = true;
} else if (IS_GEN9_LP(dev_priv)) {
table->size = ARRAY_SIZE(broxton_mocs_table);
+ table->n_entries = GEN9_NUM_MOCS_ENTRIES;
table->table = broxton_mocs_table;
result = true;
} else {
@@ -202,8 +205,6 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
if (!get_mocs_settings(dev_priv, ))
return;
- GEM_BUG_ON(table.size > GEN9_NUM_MOCS_ENTRIES);
-
/* Set unused values to PTE */
unused_value = table.table[I915_MOCS_PTE].control_value;
@@ -215,7 +216,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
}
/* All remaining entries are also unused */
- for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
+ for (; index < table.n_entries; index++)
I915_WRITE(mocs_register(engine->id, index), unused_value);
}
@@ -237,17 +238,17 @@ static int emit_mocs_control_table(struct i915_request
*rq,
u32 unused_value;
u32 *cs;
- if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
+ if (GEM_WARN_ON(table->size > table->n_entries))
return -ENODEV;
/* Set unused values to PTE */
unused_value = table->table[I915_MOCS_PTE].control_value;
- cs = intel_ring_begin(rq, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
+ cs = intel_ring_begin(rq, 2 + 2 * table->n_entries);
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES);
+ *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries);
for (index = 0; index < table->size; index++) {
u32 value = table->table[index].used ?
@@ -258,7 +259,7 @@ static int emit_mocs_control_table(struct i915_request *rq,
}
/* All remaining entries are also unused */
- for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
+ for (; index < table->n_entries; index++) {
*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
*cs++ = unused_value;
}
@@ -294,17 +295,17 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
unsigned int i, unused_index;
u32 *cs;
- if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
+ if (GEM_WARN_ON(table->size > table->n_entries))
return -ENODEV;
/* Set unused values to PTE */
unused_index = I915_MOCS_PTE;
- cs = intel_ring_begin(rq, 2 + GEN9_NUM_MOCS_ENTRIES);
+ cs = intel_ring_begin(rq, 2 + table->n_entries);
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2);
+ *cs++ = MI_LOAD_REGISTER_IMM(table->n_entries / 2);
for (i = 0; i < table->size / 2; i++) {
u16 low = table->table[2 * i].used ?
@@ -327,7 +328,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
}
/* All remaining entries are also unused */
- for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
+ for (; i < table->n_entries / 2; i++) {
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
*cs++ = l3cc_combine(table, unused_index, unused_index);
}
@@ -384,7 +385,7 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private
*dev_priv)
}
/* Now set the rest of the table to PTE */
- for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++)
+ for (; i < table.n_entries / 2; i++)
I915_WRITE(GEN9_LNCFCMOCS(i),
[Intel-gfx] [PATCH v8 4/7] drm/i915: use a macro to define MOCS entries
Let's use a macro to make tables smaller and at the same time allow us
to add fields that apply to all entries in future.
For the sake of readability, I'm calling an exception on 80 chars limit.
Lines are aligned for easy comparison of the entry values.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_mocs.c | 39 +++
1 file changed, 14 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index c7a2a8d81d90..faae2eefc5cc 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -71,6 +71,12 @@ struct drm_i915_mocs_table {
#define L3_2_RESERVED _L3_CACHEABILITY(2)
#define L3_3_WB_L3_CACHEABILITY(3)
+#define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
+ [__idx] = { \
+ .control_value = __control_value, \
+ .l3cc_value = __l3cc_value, \
+ }
+
/*
* MOCS tables
*
@@ -93,40 +99,23 @@ struct drm_i915_mocs_table {
* may only be updated incrementally by adding entries at the
* end.
*/
-
#define GEN9_MOCS_ENTRIES \
- [I915_MOCS_UNCACHED] = { \
- /* 0x0009 */ \
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, \
- /* 0x0010 */ \
- .l3cc_value = L3_1_UC, \
- }, \
- [I915_MOCS_PTE] = { \
- /* 0x0038 */ \
- .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC |
LE_LRUM(3), \
- /* 0x0030 */ \
- .l3cc_value = L3_3_WB, \
- }
+ MOCS_ENTRY(I915_MOCS_UNCACHED, LE_1_UC | LE_TC_2_LLC_ELLC, \
+ L3_1_UC), \
+ MOCS_ENTRY(I915_MOCS_PTE, LE_0_PAGETABLE | LE_TC_2_LLC_ELLC |
LE_LRUM(3), \
+ L3_3_WB) \
static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
GEN9_MOCS_ENTRIES,
- [I915_MOCS_CACHED] = {
- /* 0x003b */
- .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value = L3_3_WB,
- },
+ MOCS_ENTRY(I915_MOCS_CACHED,LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+ L3_3_WB)
};
/* NOTE: the LE_TGT_CACHE is not used on Broxton */
static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
GEN9_MOCS_ENTRIES,
- [I915_MOCS_CACHED] = {
- /* 0x0039 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value = L3_3_WB,
- },
+ MOCS_ENTRY(I915_MOCS_CACHED,LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+ L3_3_WB)
};
/**
--
2.20.0
___
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[Intel-gfx] [PATCH v8 1/7] drm/i915: initialize unused MOCS entries to PTE
Instead of initializing them to uncached, let's set them to PTE for
kernel tracking. While at it do some minor adjustments to comments and
coding style.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_mocs.c | 56 +--
1 file changed, 23 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index e976c5ce5479..0d6b94a239d6 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -85,10 +85,7 @@ struct drm_i915_mocs_table {
*
* Entries not part of the following tables are undefined as far as
* userspace is concerned and shouldn't be relied upon. For the time
- * being they will be implicitly initialized to the strictest caching
- * configuration (uncached) to guarantee forwards compatibility with
- * userspace programs written against more recent kernels providing
- * additional MOCS entries.
+ * being they will be initialized to PTE.
*
* NOTE: These tables MUST start with being uncached and the length
* MUST be less than 63 as the last two registers are reserved
@@ -249,16 +246,13 @@ void intel_mocs_init_engine(struct intel_engine_cs
*engine)
table.table[index].control_value);
/*
-* Ok, now set the unused entries to uncached. These entries
-* are officially undefined and no contract for the contents
-* and settings is given for these entries.
-*
-* Entry 0 in the table is uncached - so we are just writing
-* that value to all the used entries.
+* Now set the unused entries to PTE. These entries are officially
+* undefined and no contract for the contents and settings is given
+* for these entries.
*/
for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
I915_WRITE(mocs_register(engine->id, index),
- table.table[0].control_value);
+ table.table[I915_MOCS_PTE].control_value);
}
/**
@@ -293,16 +287,13 @@ static int emit_mocs_control_table(struct i915_request
*rq,
}
/*
-* Ok, now set the unused entries to uncached. These entries
-* are officially undefined and no contract for the contents
-* and settings is given for these entries.
-*
-* Entry 0 in the table is uncached - so we are just writing
-* that value to all the used entries.
+* Now set the unused entries to PTE. These entries are officially
+* undefined and no contract for the contents and settings is given
+* for these entries.
*/
for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
- *cs++ = table->table[0].control_value;
+ *cs++ = table->table[I915_MOCS_PTE].control_value;
}
*cs++ = MI_NOOP;
@@ -345,7 +336,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
*cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2);
- for (i = 0; i < table->size/2; i++) {
+ for (i = 0; i < table->size / 2; i++) {
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
*cs++ = l3cc_combine(table, 2 * i, 2 * i + 1);
}
@@ -353,18 +344,18 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
if (table->size & 0x01) {
/* Odd table size - 1 left over */
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
- *cs++ = l3cc_combine(table, 2 * i, 0);
+ *cs++ = l3cc_combine(table, 2 * i, I915_MOCS_PTE);
i++;
}
/*
-* Now set the rest of the table to uncached - use entry 0 as
-* this will be uncached. Leave the last pair uninitialised as
-* they are reserved by the hardware.
+* Now set the unused entries to PTE. These entries are officially
+* undefined and no contract for the contents and settings is given
+* for these entries.
*/
for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
- *cs++ = l3cc_combine(table, 0, 0);
+ *cs++ = l3cc_combine(table, I915_MOCS_PTE, I915_MOCS_PTE);
}
*cs++ = MI_NOOP;
@@ -395,22 +386,21 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private
*dev_priv)
if (!get_mocs_settings(dev_priv, ))
return;
- for (i = 0; i < table.size/2; i++)
- I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(, 2*i, 2*i+1));
+ for (i = 0; i < table.size / 2; i++)
+ I915_WRITE(GEN9_LNCFCMOCS(i),
+ l3cc_combine(, 2 * i, 2 * i + 1));
/* Odd table size - 1 left over */
if (table.size & 0x01) {
- I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(, 2*i, 0));
+
[Intel-gfx] [PATCH v8 3/7] drm/i915/skl: Rework MOCS tables to keep common part in a define
From: Tomasz Lis
The MOCS tables are going to be very similar across platforms.
To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.
v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
to MOCS_ENTRIES. (Joonas)
v3 (Lucas):
- Fix indentation
- Rebase on rework done by additional patch
- Remove define for or-ing flags as it made the table more complex by
requiring zeroed values to be passed
- Do not embed comma in the macro, so to treat that just as another
item and please source code formatting tools
Signed-off-by: Tomasz Lis
Suggested-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_mocs.c | 57 ++-
1 file changed, 25 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index 4ea80bb7dcc8..c7a2a8d81d90 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -93,46 +93,39 @@ struct drm_i915_mocs_table {
* may only be updated incrementally by adding entries at the
* end.
*/
+
+#define GEN9_MOCS_ENTRIES \
+ [I915_MOCS_UNCACHED] = { \
+ /* 0x0009 */ \
+ .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, \
+ /* 0x0010 */ \
+ .l3cc_value = L3_1_UC, \
+ }, \
+ [I915_MOCS_PTE] = { \
+ /* 0x0038 */ \
+ .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC |
LE_LRUM(3), \
+ /* 0x0030 */ \
+ .l3cc_value = L3_3_WB, \
+ }
+
static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
- [I915_MOCS_UNCACHED] = {
- /* 0x0009 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
- /* 0x0010 */
- .l3cc_value =L3_1_UC,
- },
- [I915_MOCS_PTE] = {
- /* 0x0038 */
- .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value =L3_3_WB,
- },
+ GEN9_MOCS_ENTRIES,
[I915_MOCS_CACHED] = {
- /* 0x003b */
- .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value = L3_3_WB,
+ /* 0x003b */
+ .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+ /* 0x0030 */
+ .l3cc_value = L3_3_WB,
},
};
/* NOTE: the LE_TGT_CACHE is not used on Broxton */
static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
- [I915_MOCS_UNCACHED] = {
- /* 0x0009 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
- /* 0x0010 */
- .l3cc_value = L3_1_UC,
- },
- [I915_MOCS_PTE] = {
- /* 0x0038 */
- .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value = L3_3_WB,
- },
+ GEN9_MOCS_ENTRIES,
[I915_MOCS_CACHED] = {
- /* 0x0039 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value = L3_3_WB,
+ /* 0x0039 */
+ .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+ /* 0x0030 */
+ .l3cc_value = L3_3_WB,
},
};
--
2.20.0
___
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[Intel-gfx] [PATCH v8 7/7] drm/i915/icl: Define MOCS table for Icelake
From: Tomasz Lis
The table has been unified across OSes to minimize virtualization overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Meaning of each entry is now explained in bspec, and user mode clients
are expected to know what each entry means. The 3 entries used for previous
platforms are still compatible with their legacy definitions, but that is
not guaranteed to be true for future platforms.
v2: Fixed SCC values, improved commit comment (Daniele)
v3: Improved MOCS table comment (Daniele)
v4: Moved new entries below gen9 ones. Put common entries into
definition to be used in multiple arrays. (Lucas)
v5: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
to MOCS_ENTRIES. Switched LE_CoS to upper case. (Joonas)
v6: Removed definitions of reserved entries. (Michal)
Increased limit of entries sent to the hardware on gen11+.
v7: Simplify table as done for previou gens (Lucas)
v8: Rebase on cached number of entries per-platform and use new
MOCS_ENTRY() macro (Lucas)
BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis
Reviewed-by: Daniele Ceraolo Spurio
Reviewed-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_mocs.c | 107 +++---
1 file changed, 98 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index 716f3f6f2966..3afd8c30cacc 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -46,6 +46,8 @@ struct drm_i915_mocs_table {
#define LE_SCC(value) ((value) << 8)
#define LE_PFM(value) ((value) << 11)
#define LE_SCF(value) ((value) << 14)
+#define LE_COS(value) ((value) << 15)
+#define LE_SSE(value) ((value) << 17)
/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
#define L3_ESC(value) ((value) << 0)
@@ -54,6 +56,7 @@ struct drm_i915_mocs_table {
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
+#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
/* (e)LLC caching options */
#define LE_0_PAGETABLE _LE_CACHEABILITY(0)
@@ -89,18 +92,22 @@ struct drm_i915_mocs_table {
* LNCFCMOCS0 - LNCFCMOCS32 registers.
*
* These tables are intended to be kept reasonably consistent across
- * platforms. However some of the fields are not applicable to all of
- * them.
+ * HW platforms, and for ICL+, be identical across OSes. To achieve
+ * that, for Icelake and above, list of entries is published as part
+ * of bspec.
*
* Entries not part of the following tables are undefined as far as
* userspace is concerned and shouldn't be relied upon. For the time
* being they will be initialized to PTE.
*
- * NOTE: These tables MUST start with being uncached and the length
- * MUST be less than 63 as the last two registers are reserved
- * by the hardware. These tables are part of the kernel ABI and
- * may only be updated incrementally by adding entries at the
- * end.
+ * The last two entries are reserved by the hardware. For ICL+ they
+ * should be initialized according to bspec and never used, for older
+ * platforms they should never be written to.
+ *
+ * NOTE: These tables are part of bspec and defined as part of hardware
+ * interface for ICL+. For older platforms, they are part of kernel
+ * ABI. It is expected that existing entries will remain constant
+ * and the tables will only be updated by adding new entries.
*/
#define GEN9_MOCS_ENTRIES \
MOCS_ENTRY(I915_MOCS_UNCACHED, LE_1_UC | LE_TC_2_LLC_ELLC, \
@@ -121,6 +128,84 @@ static const struct drm_i915_mocs_entry
broxton_mocs_table[] = {
L3_3_WB)
};
+#define GEN11_MOCS_ENTRIES \
+ /* Base - Uncached (Deprecated) */ \
+ MOCS_ENTRY(I915_MOCS_UNCACHED, LE_1_UC | LE_TC_1_LLC, \
+ L3_1_UC), \
+ /* Base - L3 + LeCC:PAT (Deprecated) */ \
+ MOCS_ENTRY(I915_MOCS_PTE, LE_0_PAGETABLE | LE_TC_1_LLC, \
+ L3_3_WB), \
+ /* Base - L3 + LLC */ \
+ MOCS_ENTRY(2, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_3_WB), \
+ /* Base - Uncached */ \
+ MOCS_ENTRY(3, LE_1_UC | LE_TC_1_LLC, \
+ L3_1_UC), \
+ /* Base - L3 */ \
+ MOCS_ENTRY(4, LE_1_UC | LE_TC_1_LLC, \
+ L3_3_WB), \
+ /* Base - LLC */ \
+ MOCS_ENTRY(5, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_1_UC), \
+ /* Age 0 - LLC */ \
+ MOCS_ENTRY(6, LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
+ L3_1_UC), \
+ /* Age 0 -
[Intel-gfx] [PATCH v8 5/7] drm/i915: keep track of used entries in MOCS table
Instead of considering we have defined entries for any index in the
table, let's keep track of the ones we explicitly defined. This will
allow Gen 11 to have it's new table defined in which we have holes of
undefined entries.
Repeated comments about the meaning of undefined entries were removed
since they are overly verbose and copy-pasted in several functions: now
the definition is in the top only.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_mocs.c | 88 ---
1 file changed, 57 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index faae2eefc5cc..af2ae2f396ae 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -28,6 +28,7 @@
struct drm_i915_mocs_entry {
u32 control_value;
u16 l3cc_value;
+ u16 used;
};
struct drm_i915_mocs_table {
@@ -75,6 +76,7 @@ struct drm_i915_mocs_table {
[__idx] = { \
.control_value = __control_value, \
.l3cc_value = __l3cc_value, \
+ .used = 1, \
}
/*
@@ -195,24 +197,26 @@ void intel_mocs_init_engine(struct intel_engine_cs
*engine)
struct drm_i915_private *dev_priv = engine->i915;
struct drm_i915_mocs_table table;
unsigned int index;
+ u32 unused_value;
if (!get_mocs_settings(dev_priv, ))
return;
GEM_BUG_ON(table.size > GEN9_NUM_MOCS_ENTRIES);
- for (index = 0; index < table.size; index++)
- I915_WRITE(mocs_register(engine->id, index),
- table.table[index].control_value);
+ /* Set unused values to PTE */
+ unused_value = table.table[I915_MOCS_PTE].control_value;
- /*
-* Now set the unused entries to PTE. These entries are officially
-* undefined and no contract for the contents and settings is given
-* for these entries.
-*/
+ for (index = 0; index < table.size; index++) {
+ u32 value = table.table[index].used ?
+ table.table[index].control_value : unused_value;
+
+ I915_WRITE(mocs_register(engine->id, index), value);
+ }
+
+ /* All remaining entries are also unused */
for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
- I915_WRITE(mocs_register(engine->id, index),
- table.table[I915_MOCS_PTE].control_value);
+ I915_WRITE(mocs_register(engine->id, index), unused_value);
}
/**
@@ -230,11 +234,15 @@ static int emit_mocs_control_table(struct i915_request
*rq,
{
enum intel_engine_id engine = rq->engine->id;
unsigned int index;
+ u32 unused_value;
u32 *cs;
if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
return -ENODEV;
+ /* Set unused values to PTE */
+ unused_value = table->table[I915_MOCS_PTE].control_value;
+
cs = intel_ring_begin(rq, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -242,18 +250,17 @@ static int emit_mocs_control_table(struct i915_request
*rq,
*cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES);
for (index = 0; index < table->size; index++) {
+ u32 value = table->table[index].used ?
+ table->table[index].control_value : unused_value;
+
*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
- *cs++ = table->table[index].control_value;
+ *cs++ = value;
}
- /*
-* Now set the unused entries to PTE. These entries are officially
-* undefined and no contract for the contents and settings is given
-* for these entries.
-*/
+ /* All remaining entries are also unused */
for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
- *cs++ = table->table[I915_MOCS_PTE].control_value;
+ *cs++ = unused_value;
}
*cs++ = MI_NOOP;
@@ -284,12 +291,15 @@ static inline u32 l3cc_combine(const struct
drm_i915_mocs_table *table,
static int emit_mocs_l3cc_table(struct i915_request *rq,
const struct drm_i915_mocs_table *table)
{
- unsigned int i;
+ unsigned int i, unused_index;
u32 *cs;
if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
return -ENODEV;
+ /* Set unused values to PTE */
+ unused_index = I915_MOCS_PTE;
+
cs = intel_ring_begin(rq, 2 + GEN9_NUM_MOCS_ENTRIES);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -297,25 +307,29 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
*cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2);
for (i = 0; i < table->size / 2; i++) {
+ u16 low = table->table[2 *
[Intel-gfx] [PATCH v8 0/7] Define MOCS table for Icelake
This reworks v7 of the series (https://patchwork.freedesktop.org/series/54070/) to handle the comments there and some more of my own. Changes: - Initialize undefined entries to PTE rather than uncached (suggested by Chris) - Add a new macro to define MOCS entries: this allows to make the table more readable and to implicitly mark entries that are defined - Minor improvements to "drm/i915: cache number of MOCS entries" (suggested by Tvrtko) - Reorder patches to avoid unneeded changes (suggested by Tvrtko) Lucas De Marchi (5): drm/i915: initialize unused MOCS entries to PTE drm/i915: Simplify MOCS table definition drm/i915: use a macro to define MOCS entries drm/i915: keep track of used entries in MOCS table drm/i915: cache number of MOCS entries Tomasz Lis (2): drm/i915/skl: Rework MOCS tables to keep common part in a define drm/i915/icl: Define MOCS table for Icelake drivers/gpu/drm/i915/intel_mocs.c | 356 ++ 1 file changed, 211 insertions(+), 145 deletions(-) -- 2.20.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 2/7] drm/i915: Simplify MOCS table definition
Make the defines for LE and L3 caching options to contain the shifts and
remove the zeros from the tables as shifting zeros always result in
zero.
Starting from Ice Lake the MOCS table is defined in the spec and
contains all entries. So to simplify checking the table with the values
set in code, the value is now part of the macro name. This allows to
still give the most used option and sensible name, but also to easily
cross check the table from the spec for gen >= 11.
By removing the zeros we avoid maintaining a huge table since the one
from spec contains many more entries. The new table for Ice Lake will
be added by other patches, this only reformats the table.
While at it also fix the indentation.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_mocs.c | 80 +++
1 file changed, 29 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index 0d6b94a239d6..4ea80bb7dcc8 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -36,8 +36,8 @@ struct drm_i915_mocs_table {
};
/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
-#define LE_CACHEABILITY(value) ((value) << 0)
-#define LE_TGT_CACHE(value)((value) << 2)
+#define _LE_CACHEABILITY(value)((value) << 0)
+#define _LE_TGT_CACHE(value) ((value) << 2)
#define LE_LRUM(value) ((value) << 4)
#define LE_AOM(value) ((value) << 6)
#define LE_RSC(value) ((value) << 7)
@@ -48,28 +48,28 @@ struct drm_i915_mocs_table {
/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
#define L3_ESC(value) ((value) << 0)
#define L3_SCC(value) ((value) << 1)
-#define L3_CACHEABILITY(value) ((value) << 4)
+#define _L3_CACHEABILITY(value)((value) << 4)
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
/* (e)LLC caching options */
-#define LE_PAGETABLE 0
-#define LE_UC 1
-#define LE_WT 2
-#define LE_WB 3
-
-/* L3 caching options */
-#define L3_DIRECT 0
-#define L3_UC 1
-#define L3_RESERVED2
-#define L3_WB 3
+#define LE_0_PAGETABLE _LE_CACHEABILITY(0)
+#define LE_1_UC_LE_CACHEABILITY(1)
+#define LE_2_WT_LE_CACHEABILITY(2)
+#define LE_3_WB_LE_CACHEABILITY(3)
/* Target cache */
-#define LE_TC_PAGETABLE0
-#define LE_TC_LLC 1
-#define LE_TC_LLC_ELLC 2
-#define LE_TC_LLC_ELLC_ALT 3
+#define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
+#define LE_TC_1_LLC_LE_TGT_CACHE(1)
+#define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
+#define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
+
+/* L3 caching options */
+#define L3_0_DIRECT_L3_CACHEABILITY(0)
+#define L3_1_UC_L3_CACHEABILITY(1)
+#define L3_2_RESERVED _L3_CACHEABILITY(2)
+#define L3_3_WB_L3_CACHEABILITY(3)
/*
* MOCS tables
@@ -96,31 +96,21 @@ struct drm_i915_mocs_table {
static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
[I915_MOCS_UNCACHED] = {
/* 0x0009 */
- .control_value = LE_CACHEABILITY(LE_UC) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
-
+ .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
/* 0x0010 */
- .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+ .l3cc_value =L3_1_UC,
},
[I915_MOCS_PTE] = {
/* 0x0038 */
- .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
+ .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
/* 0x0030 */
- .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ .l3cc_value =L3_3_WB,
},
[I915_MOCS_CACHED] = {
/* 0x003b */
- .control_value = LE_CACHEABILITY(LE_WB) |
- LE_TGT_CACHE(LE_TC_LLC_ELLC) |
- LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
- LE_PFM(0) | LE_SCF(0),
+ .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
/* 0x0030 */
- .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+ .l3cc_value = L3_3_WB,
},
};
@@ -128,33 +118,21 @@ static const struct drm_i915_mocs_entry
skylake_mocs_table[] = {
static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
[I915_MOCS_UNCACHED] = {
/*
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/34] drm/i915/execlists: Mark up priority boost on preemption
== Series Details ==
Series: series starting with [01/34] drm/i915/execlists: Mark up priority boost
on preemption
URL : https://patchwork.freedesktop.org/series/55528/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5459_full -> Patchwork_12001_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12001_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12001_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12001_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_switch@basic-all-heavy:
- shard-snb: PASS -> DMESG-FAIL
* igt@gem_exec_await@wide-all:
- shard-hsw: PASS -> FAIL +3
- shard-snb: PASS -> FAIL +2
* igt@gem_mmap_gtt@hang:
- shard-kbl: PASS -> FAIL
- shard-apl: PASS -> FAIL
Known issues
Here are the changes found in Patchwork_12001_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@reset-stress:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> FAIL [fdo#108597]
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_cursor_legacy@pipe-a-single-move:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_flip@dpms-vs-vblank-race:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard-glk: PASS -> FAIL [fdo#103166] +2
Possible fixes
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-hsw: DMESG-WARN [fdo#107956] -> PASS +5
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: DMESG-WARN [fdo#107956] -> PASS +3
* igt@kms_busy@extended-pageflip-hang-oldfb-render-b:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-glk: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-untiled:
- shard-snb: {SKIP} [fdo#109271] -> PASS +4
* igt@kms_plane@pixel-format-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk: FAIL [fdo#108145] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: FAIL -> PASS
Warnings
* igt@kms_setmode@basic:
- shard-apl: INCOMPLETE [fdo#103927] -> FAIL [fdo#99912]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
[Intel-gfx] ✓ Fi.CI.IGT: success for dma-buf: Enhance dma-fence tracing
== Series Details ==
Series: dma-buf: Enhance dma-fence tracing
URL : https://patchwork.freedesktop.org/series/55531/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459_full -> Patchwork_12000_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12000_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> FAIL [fdo#108597]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166]
Possible fixes
* igt@kms_busy@extended-pageflip-hang-oldfb-render-b:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-untiled:
- shard-snb: {SKIP} [fdo#109271] -> PASS +4
* igt@kms_plane@pixel-format-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: FAIL -> PASS
* igt@kms_setmode@basic:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_12000
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12000: e620fc0f05f3e1ebf6b1fb1488e7d2fb38930404 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12000/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/34] drm/i915/execlists: Mark up priority boost on preemption
== Series Details ==
Series: series starting with [01/34] drm/i915/execlists: Mark up priority boost
on preemption
URL : https://patchwork.freedesktop.org/series/55528/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459 -> Patchwork_12001
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55528/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12001:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@runner@aborted}:
- fi-bxt-j4205: NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_12001 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:DMESG-FAIL [fdo#108735] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u2}:FAIL [fdo#103167] -> PASS
* igt@pm_rpm@module-reload:
- {fi-icl-u2}:DMESG-WARN [fdo#108654] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (47 -> 42)
--
Additional (1): fi-glk-j4005
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_12001
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12001: 6cedf9409751062b0d231b0f22dad0cf0d9d3f1d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6cedf9409751 drm/i915: Replace global_seqno with a hangcheck heartbeat seqno
2befa074162f drm/i915: Prioritise non-busywait semaphore workloads
f557fb2f2149 drm/i915: Use HW semaphores for inter-engine synchronisation on
gen8+
4c26f95d5c56 drm/i915/execlists: Refactor out can_merge_rq()
6a7f5b9d1dfc drm/i915: Keep timeline HWSP allocated until the system is idle
09c15d6b8399 drm/i915: Drop fake breadcrumb irq
9534b50448fe drm/i915: Replace global breadcrumbs with per-context interrupt
tracking
063e9cd8eb0a drm/i915: Remove the intel_engine_notify tracepoint
6671fcc878bd drm/i915: Identify active requests
4daf132957fc drm/i915: Track active timelines
daf8d943452d drm/i915: Track the context's seqno in its own timeline HWSP
5f0f0c9295ff drm/i915: Share per-timeline HWSP using a slab suballocator
74aa9e1fc5b3 drm/i915: Allocate a status page for each timeline
d2f9c373370e drm/i915: Enlarge vma->pin_count
e817b79ab8b6 drm/i915: Introduce concept of per-timeline (context) HWSP
744111bb6c5e drm/i915: Tidy common test_bit probing of i915_request->fence.flags
b048cc2c6473 drm/i915/selftests: Use common mock_engine::advance
25604144be52 drm/i915: Move list of timelines under its own lock
f2c29c8ca52c drm/i915: Always allocate an object/vma for the HWSP
ef26f0a3b3db drm/i915: Move vma lookup to its own lock
3e5e7f676feb drm/i915: Pull VM lists under the VM mutex.
4f90b7cb5b32 drm/i915: Stop tracking MRU activity on VMA
789901576adf drm/i915: Issue engine resets onto idle engines
faf113b5e213 drm/i915/selftests: Trim struct_mutex duration for set-wedged
selftest
f6dd5893f7b8 drm/i915: Remove GPU reset dependence on struct_mutex
00695a093e1f drm/i915/guc: Disable global reset
912b47059d6e drm/i915: Make all GPU resets atomic
82cdc06b4a39 drm/i915: Refactor out intel_context_init()
525322709fa3 drm/i915/selftests: Create a clean GGTT for vma/gtt selftesting
424a90dd6d68 drm/i915/selftests: Track evict objects explicitly
fd236ee5650b drm/i915/selftests: Refactor common live_test framework
58648274db42 drm/i915: Show all
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/34] drm/i915/execlists: Mark up priority boost on preemption
== Series Details == Series: series starting with [01/34] drm/i915/execlists: Mark up priority boost on preemption URL : https://patchwork.freedesktop.org/series/55528/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Mark up priority boost on preemption +drivers/gpu/drm/i915/intel_ringbuffer.h:602:23: warning: expression using sizeof(void) Commit: drm/i915/execlists: Suppress preempting self Okay! Commit: drm/i915: Show all active engines on hangcheck Okay! Commit: drm/i915/selftests: Refactor common live_test framework +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/selftests: Track evict objects explicitly Okay! Commit: drm/i915/selftests: Create a clean GGTT for vma/gtt selftesting Okay! Commit: drm/i915: Refactor out intel_context_init() Okay! Commit: drm/i915: Make all GPU resets atomic Okay! Commit: drm/i915/guc: Disable global reset Okay! Commit: drm/i915: Remove GPU reset dependence on struct_mutex -drivers/gpu/drm/i915/selftests/../i915_drv.h:3546:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3541:16: warning: expression using sizeof(void) Commit: drm/i915/selftests: Trim struct_mutex duration for set-wedged selftest Okay! Commit: drm/i915: Issue engine resets onto idle engines Okay! Commit: drm/i915: Stop tracking MRU activity on VMA Okay! Commit: drm/i915: Pull VM lists under the VM mutex. Okay! Commit: drm/i915: Move vma lookup to its own lock Okay! Commit: drm/i915: Always allocate an object/vma for the HWSP Okay! Commit: drm/i915: Move list of timelines under its own lock -drivers/gpu/drm/i915/selftests/../i915_drv.h:3541:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3544:16: warning: expression using sizeof(void) Commit: drm/i915/selftests: Use common mock_engine::advance Okay! Commit: drm/i915: Tidy common test_bit probing of i915_request->fence.flags Okay! Commit: drm/i915: Introduce concept of per-timeline (context) HWSP Okay! Commit: drm/i915: Enlarge vma->pin_count Okay! Commit: drm/i915: Allocate a status page for each timeline +./include/linux/mm.h:619:13: error: not a function +./include/linux/mm.h:619:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/mm.h:619:13: warning: call with no type! Commit: drm/i915: Share per-timeline HWSP using a slab suballocator -drivers/gpu/drm/i915/selftests/../i915_drv.h:3544:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_timeline.c:89:38: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_timeline.c:89:38: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_timeline.c:92:44: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_timeline.c:92:44: warning: expression using sizeof(void) +./include/linux/slab.h:664:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:664:13: warning: call with no type! Commit: drm/i915: Track the context's seqno in its own timeline HWSP Okay! Commit: drm/i915: Track active timelines Okay! Commit: drm/i915: Identify active requests Okay! Commit: drm/i915: Remove the intel_engine_notify tracepoint Okay! Commit: drm/i915: Replace global breadcrumbs with per-context interrupt tracking +drivers/gpu/drm/i915/selftests/i915_request.c:284:40: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_request.c:284:40: warning: expression using sizeof(void) -./include/linux/mm.h:619:13: error: not a function -./include/linux/mm.h:619:13: error: not a function -./include/linux/mm.h:619:13: error: undefined identifier '__builtin_mul_overflow' -./include/linux/mm.h:619:13: warning: call with no type! +./include/linux/slab.h:664:13: error: not a function +./include/linux/slab.h:664:13: error: not a function Commit: drm/i915: Drop fake breadcrumb irq Okay! Commit: drm/i915: Keep timeline HWSP allocated until the system is idle -drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3550:16: warning: expression using sizeof(void) Commit: drm/i915/execlists: Refactor out can_merge_rq() Okay! Commit: drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ Okay! Commit: drm/i915: Prioritise non-busywait semaphore workloads Okay! Commit: drm/i915: Replace global_seqno with a hangcheck heartbeat seqno Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/34] drm/i915/execlists: Mark up priority boost on preemption
== Series Details ==
Series: series starting with [01/34] drm/i915/execlists: Mark up priority boost
on preemption
URL : https://patchwork.freedesktop.org/series/55528/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
096d4f120d3e drm/i915/execlists: Mark up priority boost on preemption
85c9694f46a4 drm/i915/execlists: Suppress preempting self
-:18: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#18:
References: a2bf92e8cc16 ("drm/i915/execlists: Avoid kicking priority on the
current context")
-:18: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit a2bf92e8cc16
("drm/i915/execlists: Avoid kicking priority on the current context")'
#18:
References: a2bf92e8cc16 ("drm/i915/execlists: Avoid kicking priority on the
current context")
total: 1 errors, 1 warnings, 0 checks, 92 lines checked
58648274db42 drm/i915: Show all active engines on hangcheck
fd236ee5650b drm/i915/selftests: Refactor common live_test framework
-:435: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#435:
new file mode 100644
-:440: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#440: FILE: drivers/gpu/drm/i915/selftests/igt_live_test.c:1:
+/*
-:531: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#531: FILE: drivers/gpu/drm/i915/selftests/igt_live_test.h:1:
+/*
total: 0 errors, 3 warnings, 0 checks, 496 lines checked
424a90dd6d68 drm/i915/selftests: Track evict objects explicitly
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
References: 71fc448c1aaf ("drm/i915/selftests: Make evict tolerant of foreign
objects")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 71fc448c1aaf
("drm/i915/selftests: Make evict tolerant of foreign objects")'
#12:
References: 71fc448c1aaf ("drm/i915/selftests: Make evict tolerant of foreign
objects")
total: 1 errors, 1 warnings, 0 checks, 256 lines checked
525322709fa3 drm/i915/selftests: Create a clean GGTT for vma/gtt selftesting
-:393: WARNING:LONG_LINE: line over 100 characters
#393: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:265:
+ VALID(0, PIN_GLOBAL | PIN_MAPPABLE | PIN_OFFSET_FIXED |
(ggtt->mappable_end - 4096)),
-:416: WARNING:LONG_LINE: line over 100 characters
#416: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:280:
+ INVALID(8192, PIN_GLOBAL | PIN_MAPPABLE | PIN_OFFSET_FIXED |
(ggtt->mappable_end - 4096)),
-:435: WARNING:LONG_LINE: line over 100 characters
#435: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:294:
+ NOSPACE(8192, PIN_GLOBAL | PIN_MAPPABLE | PIN_OFFSET_BIAS |
(ggtt->mappable_end - 4096)),
total: 0 errors, 3 warnings, 0 checks, 520 lines checked
82cdc06b4a39 drm/i915: Refactor out intel_context_init()
912b47059d6e drm/i915: Make all GPU resets atomic
-:24: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.txt
#24: FILE: drivers/gpu/drm/i915/i915_reset.c:147:
+ udelay(50);
-:30: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.txt
#30: FILE: drivers/gpu/drm/i915/i915_reset.c:152:
+ udelay(50);
total: 0 errors, 0 warnings, 2 checks, 111 lines checked
00695a093e1f drm/i915/guc: Disable global reset
f6dd5893f7b8 drm/i915: Remove GPU reset dependence on struct_mutex
-:878: WARNING:MEMORY_BARRIER: memory barrier without comment
#878: FILE: drivers/gpu/drm/i915/i915_reset.c:692:
+ smp_store_mb(i915->gpu_error.restart, NULL);
-:1031: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its
#endif
#1031: FILE: drivers/gpu/drm/i915/i915_reset.c:920:
+#if 0
-:1302: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield. Prefer bool
bitfields as unsigned int or u<8|16|32>
#1302: FILE: drivers/gpu/drm/i915/intel_hangcheck.c:35:
+ bool wedged:1;
-:1303: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield. Prefer bool
bitfields as unsigned int or u<8|16|32>
#1303: FILE: drivers/gpu/drm/i915/intel_hangcheck.c:36:
+ bool stalled:1;
total: 0 errors, 4 warnings, 0 checks, 1729 lines checked
faf113b5e213 drm/i915/selftests: Trim struct_mutex duration for set-wedged
selftest
789901576adf drm/i915: Issue engine resets onto idle engines
4f90b7cb5b32 drm/i915: Stop tracking MRU activity on VMA
3e5e7f676feb drm/i915: Pull VM lists under the VM mutex.
ef26f0a3b3db drm/i915: Move vma lookup to its own lock
-:161: WARNING:USE_SPINLOCK_T: struct spinlock should be spinlock_t
#161: FILE: drivers/gpu/drm/i915/i915_gem_object.h:94:
+ struct spinlock lock;
total: 0 errors, 1 warnings, 0 checks, 290 lines checked
f2c29c8ca52c drm/i915: Always allocate an object/vma for the HWSP
25604144be52
[Intel-gfx] ✓ Fi.CI.BAT: success for dma-buf: Enhance dma-fence tracing
== Series Details ==
Series: dma-buf: Enhance dma-fence tracing
URL : https://patchwork.freedesktop.org/series/55531/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459 -> Patchwork_12000
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55531/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12000 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: PASS -> FAIL [fdo#108767]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:DMESG-FAIL [fdo#108735] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u2}:FAIL [fdo#103167] -> PASS
* igt@pm_rpm@module-reload:
- {fi-icl-u2}:DMESG-WARN [fdo#108654] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (47 -> 41)
--
Additional (1): fi-glk-j4005
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-pnv-d510 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_12000
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12000: e620fc0f05f3e1ebf6b1fb1488e7d2fb38930404 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e620fc0f05f3 dma-buf: Enhance dma-fence tracing
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12000/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-buf: Enhance dma-fence tracing
== Series Details ==
Series: dma-buf: Enhance dma-fence tracing
URL : https://patchwork.freedesktop.org/series/55531/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e620fc0f05f3 dma-buf: Enhance dma-fence tracing
-:461: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'e' - possible side-effects?
#461: FILE: drivers/gpu/drm/i915/intel_ringbuffer.h:582:
+#define i915_trace_hwid(e) ((e)->uabi_class << 16 | (e)->instance)
-:532: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#532: FILE: include/trace/events/dma_fence.h:70:
+ TP_STRUCT__entry(
-:538: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#538: FILE: include/trace/events/dma_fence.h:76:
+ TP_fast_assign(
-:552: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#552: FILE: include/trace/events/dma_fence.h:90:
+ TP_STRUCT__entry(
-:556: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#556: FILE: include/trace/events/dma_fence.h:94:
+ TP_fast_assign(
-:569: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#569: FILE: include/trace/events/dma_fence.h:107:
+ TP_STRUCT__entry(
-:574: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#574: FILE: include/trace/events/dma_fence.h:112:
+ TP_fast_assign(
-:583: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#583: FILE: include/trace/events/dma_fence.h:121:
+TRACE_EVENT(dma_fence_init,
+ TP_PROTO(struct dma_fence *fence),
-:612: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#612: FILE: include/trace/events/dma_fence.h:190:
+ TP_STRUCT__entry(
-:619: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#619: FILE: include/trace/events/dma_fence.h:197:
+ TP_fast_assign(
-:635: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#635: FILE: include/trace/events/dma_fence.h:213:
+ TP_STRUCT__entry(
-:641: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#641: FILE: include/trace/events/dma_fence.h:219:
+ TP_fast_assign(
-:655: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#655: FILE: include/trace/events/dma_fence.h:233:
+ TP_STRUCT__entry(
-:661: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#661: FILE: include/trace/events/dma_fence.h:239:
+ TP_fast_assign(
total: 0 errors, 0 warnings, 14 checks, 546 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/34] drm/i915/selftests: Use common mock_engine::advance
Replace the open-coding of advance with a call instead.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/mock_engine.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c
b/drivers/gpu/drm/i915/selftests/mock_engine.c
index 968a7e139a67..386dfa7e2d5c 100644
--- a/drivers/gpu/drm/i915/selftests/mock_engine.c
+++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
@@ -67,11 +67,10 @@ static struct mock_request *first_request(struct
mock_engine *engine)
link);
}
-static void advance(struct mock_engine *engine,
- struct mock_request *request)
+static void advance(struct mock_request *request)
{
list_del_init(>link);
- mock_seqno_advance(>base, request->base.global_seqno);
+ mock_seqno_advance(request->base.engine, request->base.global_seqno);
}
static void hw_delay_complete(struct timer_list *t)
@@ -84,7 +83,7 @@ static void hw_delay_complete(struct timer_list *t)
/* Timer fired, first request is complete */
request = first_request(engine);
if (request)
- advance(engine, request);
+ advance(request);
/*
* Also immediately signal any subsequent 0-delay requests, but
@@ -96,7 +95,7 @@ static void hw_delay_complete(struct timer_list *t)
break;
}
- advance(engine, request);
+ advance(request);
}
spin_unlock(>hw_lock);
@@ -180,7 +179,7 @@ static void mock_submit_request(struct i915_request
*request)
if (mock->delay)
mod_timer(>hw_delay, jiffies + mock->delay);
else
- advance(engine, mock);
+ advance(mock);
}
spin_unlock_irq(>hw_lock);
}
@@ -240,10 +239,8 @@ void mock_engine_flush(struct intel_engine_cs *engine)
del_timer_sync(>hw_delay);
spin_lock_irq(>hw_lock);
- list_for_each_entry_safe(request, rn, >hw_queue, link) {
- list_del_init(>link);
- mock_seqno_advance(>base, request->base.global_seqno);
- }
+ list_for_each_entry_safe(request, rn, >hw_queue, link)
+ advance(request);
spin_unlock_irq(>hw_lock);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/34] drm/i915: Issue engine resets onto idle engines
Always perform the requested reset, even if we believe the engine is
idle. Presumably there was a reason the caller wanted the reset, and in
the near future we lose the easy tracking for whether the engine is
idle.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_reset.c | 4
.../gpu/drm/i915/selftests/intel_hangcheck.c | 22 +--
2 files changed, 6 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 064fc6da1512..d44b095e2860 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -1063,10 +1063,6 @@ int i915_reset_engine(struct intel_engine_cs *engine,
const char *msg)
GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >flags));
- if (i915_seqno_passed(intel_engine_get_seqno(engine),
- intel_engine_last_submit(engine)))
- return 0;
-
reset_prepare_engine(engine);
if (msg)
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 8025c7e0bf6c..2c38ea5892d9 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -449,8 +449,6 @@ static int __igt_reset_engine(struct drm_i915_private
*i915, bool active)
set_bit(I915_RESET_ENGINE + id, >gpu_error.flags);
do {
- u32 seqno = intel_engine_get_seqno(engine);
-
if (active) {
struct i915_request *rq;
@@ -479,8 +477,6 @@ static int __igt_reset_engine(struct drm_i915_private
*i915, bool active)
break;
}
- GEM_BUG_ON(!rq->global_seqno);
- seqno = rq->global_seqno - 1;
i915_request_put(rq);
}
@@ -496,11 +492,10 @@ static int __igt_reset_engine(struct drm_i915_private
*i915, bool active)
break;
}
- reset_engine_count += active;
if (i915_reset_engine_count(>gpu_error, engine) !=
- reset_engine_count) {
- pr_err("%s engine reset %srecorded!\n",
- engine->name, active ? "not " : "");
+ ++reset_engine_count) {
+ pr_err("%s engine reset not recorded!\n",
+ engine->name);
err = -EINVAL;
break;
}
@@ -728,7 +723,6 @@ static int __igt_reset_engines(struct drm_i915_private
*i915,
set_bit(I915_RESET_ENGINE + id, >gpu_error.flags);
do {
- u32 seqno = intel_engine_get_seqno(engine);
struct i915_request *rq = NULL;
if (flags & TEST_ACTIVE) {
@@ -756,9 +750,6 @@ static int __igt_reset_engines(struct drm_i915_private
*i915,
err = -EIO;
break;
}
-
- GEM_BUG_ON(!rq->global_seqno);
- seqno = rq->global_seqno - 1;
}
err = i915_reset_engine(engine, NULL);
@@ -795,10 +786,9 @@ static int __igt_reset_engines(struct drm_i915_private
*i915,
reported = i915_reset_engine_count(>gpu_error, engine);
reported -= threads[engine->id].resets;
- if (reported != (flags & TEST_ACTIVE ? count : 0)) {
- pr_err("i915_reset_engine(%s:%s): reset %lu times, but
reported %lu, expected %lu reported\n",
- engine->name, test_name, count, reported,
- (flags & TEST_ACTIVE ? count : 0));
+ if (reported != count) {
+ pr_err("i915_reset_engine(%s:%s): reset %lu times, but
reported %lu\n",
+ engine->name, test_name, count, reported);
if (!err)
err = -EINVAL;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/34] drm/i915/selftests: Create a clean GGTT for vma/gtt selftesting
Some tests (e.g. igt_vma_pin1) presume that we have a completely clean
GGTT so that it can probe boundaries without fear that something is
already allocated there. However, the mock device is starting to get
complicated and following similar rules to the live device, i.e. we
can't guarantee that i915->ggtt remains clean, so create a temporary
address_space equivalent to the mock ggtt for the purpose.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 108 +++---
drivers/gpu/drm/i915/selftests/i915_vma.c | 77 +++--
.../gpu/drm/i915/selftests/mock_gem_device.c | 4 +-
drivers/gpu/drm/i915/selftests/mock_gtt.c | 9 +-
drivers/gpu/drm/i915/selftests/mock_gtt.h | 4 +-
5 files changed, 114 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index fea8ab14e79d..06bde4a273cb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1267,27 +1267,35 @@ static int exercise_mock(struct drm_i915_private *i915,
static int igt_mock_fill(void *arg)
{
- return exercise_mock(arg, fill_hole);
+ struct i915_ggtt *ggtt = arg;
+
+ return exercise_mock(ggtt->vm.i915, fill_hole);
}
static int igt_mock_walk(void *arg)
{
- return exercise_mock(arg, walk_hole);
+ struct i915_ggtt *ggtt = arg;
+
+ return exercise_mock(ggtt->vm.i915, walk_hole);
}
static int igt_mock_pot(void *arg)
{
- return exercise_mock(arg, pot_hole);
+ struct i915_ggtt *ggtt = arg;
+
+ return exercise_mock(ggtt->vm.i915, pot_hole);
}
static int igt_mock_drunk(void *arg)
{
- return exercise_mock(arg, drunk_hole);
+ struct i915_ggtt *ggtt = arg;
+
+ return exercise_mock(ggtt->vm.i915, drunk_hole);
}
static int igt_gtt_reserve(void *arg)
{
- struct drm_i915_private *i915 = arg;
+ struct i915_ggtt *ggtt = arg;
struct drm_i915_gem_object *obj, *on;
LIST_HEAD(objects);
u64 total;
@@ -1300,11 +1308,12 @@ static int igt_gtt_reserve(void *arg)
/* Start by filling the GGTT */
for (total = 0;
-total + 2*I915_GTT_PAGE_SIZE <= i915->ggtt.vm.total;
-total += 2*I915_GTT_PAGE_SIZE) {
+total + 2 * I915_GTT_PAGE_SIZE <= ggtt->vm.total;
+total += 2 * I915_GTT_PAGE_SIZE) {
struct i915_vma *vma;
- obj = i915_gem_object_create_internal(i915, 2*PAGE_SIZE);
+ obj = i915_gem_object_create_internal(ggtt->vm.i915,
+ 2 * PAGE_SIZE);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
goto out;
@@ -1318,20 +1327,20 @@ static int igt_gtt_reserve(void *arg)
list_add(>st_link, );
- vma = i915_vma_instance(obj, >ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, >vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto out;
}
- err = i915_gem_gtt_reserve(>ggtt.vm, >node,
+ err = i915_gem_gtt_reserve(>vm, >node,
obj->base.size,
total,
obj->cache_level,
0);
if (err) {
pr_err("i915_gem_gtt_reserve (pass 1) failed at
%llu/%llu with err=%d\n",
- total, i915->ggtt.vm.total, err);
+ total, ggtt->vm.total, err);
goto out;
}
track_vma_bind(vma);
@@ -1349,11 +1358,12 @@ static int igt_gtt_reserve(void *arg)
/* Now we start forcing evictions */
for (total = I915_GTT_PAGE_SIZE;
-total + 2*I915_GTT_PAGE_SIZE <= i915->ggtt.vm.total;
-total += 2*I915_GTT_PAGE_SIZE) {
+total + 2 * I915_GTT_PAGE_SIZE <= ggtt->vm.total;
+total += 2 * I915_GTT_PAGE_SIZE) {
struct i915_vma *vma;
- obj = i915_gem_object_create_internal(i915, 2*PAGE_SIZE);
+ obj = i915_gem_object_create_internal(ggtt->vm.i915,
+ 2 * PAGE_SIZE);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
goto out;
@@ -1367,20 +1377,20 @@ static int igt_gtt_reserve(void *arg)
list_add(>st_link, );
- vma = i915_vma_instance(obj, >ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, >vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto out;
}
- err = i915_gem_gtt_reserve(>ggtt.vm, >node,
[Intel-gfx] [PATCH 19/34] drm/i915: Tidy common test_bit probing of i915_request->fence.flags
A repeated pattern is to test the signaled bit of our
request->fence.flags. Make this an inline to shorten a few lines and
remove unnecessary line continuations.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 3 +--
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/i915_request.h | 5 +
drivers/gpu/drm/i915/intel_breadcrumbs.c | 3 +--
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +--
7 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1abfc3fa76ad..5fd5080c4ccb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1182,8 +1182,7 @@ static void notify_ring(struct intel_engine_cs *engine)
struct i915_request *waiter = wait->request;
if (waiter &&
- !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
- >fence.flags) &&
+ !i915_request_signaled(waiter) &&
intel_wait_check_request(wait, waiter))
rq = i915_request_get(waiter);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 80232de8e2be..2721a356368f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -198,7 +198,7 @@ static void __retire_engine_request(struct intel_engine_cs
*engine,
spin_unlock(>timeline.lock);
spin_lock(>lock);
- if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags))
+ if (!i915_request_signaled(rq))
dma_fence_signal_locked(>fence);
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
intel_engine_cancel_signaling(rq);
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index d014b0605445..c0f084ca4f29 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -280,6 +280,11 @@ long i915_request_wait(struct i915_request *rq,
#define I915_WAIT_ALL BIT(3) /* used by i915_gem_object_wait() */
#define I915_WAIT_FOR_IDLE_BOOST BIT(4)
+static inline bool i915_request_signaled(const struct i915_request *rq)
+{
+ return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags);
+}
+
static inline bool intel_engine_has_started(struct intel_engine_cs *engine,
u32 seqno);
static inline bool intel_engine_has_completed(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 4fad93fe3678..b58915b8708b 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -631,8 +631,7 @@ static int intel_breadcrumbs_signaler(void *arg)
rq->signaling.wait.seqno = 0;
__list_del_entry(>signaling.link);
- if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
- >fence.flags)) {
+ if (!i915_request_signaled(rq)) {
list_add_tail(>signaling.link,
);
i915_request_get(rq);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index bc65d8006e16..464dd309fa99 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -855,7 +855,7 @@ static void execlists_cancel_requests(struct
intel_engine_cs *engine)
list_for_each_entry(rq, >timeline.requests, link) {
GEM_BUG_ON(!rq->global_seqno);
- if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags))
+ if (i915_request_signaled(rq))
continue;
dma_fence_set_error(>fence, -EIO);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b63afa3a221..fdc28a3d2936 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6662,7 +6662,7 @@ void gen6_rps_boost(struct i915_request *rq,
if (!rps->enabled)
return;
- if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags))
+ if (i915_request_signaled(rq))
return;
/* Serializes with i915_request_retire() */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 66dc8e2fa353..bc620ae297b4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -876,8 +876,7 @@ static void cancel_requests(struct intel_engine_cs *engine)
list_for_each_entry(request, >timeline.requests, link)
[Intel-gfx] [PATCH 20/34] drm/i915: Introduce concept of per-timeline (context) HWSP
Supplement the per-engine HWSP with a per-timeline HWSP. That is a
per-request pointer through which we can check a local seqno,
abstracting away the presumption of a global seqno. In this first step,
we point each request back into the engine's HWSP so everything
continues to work with the global timeline.
v2: s/i915_request_hwsp/hwsp_seqno/ to emphasis that this is the current
HW value and that we are accessing it via i915_request merely as a
convenience.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 16 ++
drivers/gpu/drm/i915/i915_request.h | 45 -
drivers/gpu/drm/i915/intel_lrc.c| 9 --
3 files changed, 55 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 2721a356368f..d61e86c6a1d1 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -182,10 +182,11 @@ static void free_capture_list(struct i915_request
*request)
static void __retire_engine_request(struct intel_engine_cs *engine,
struct i915_request *rq)
{
- GEM_TRACE("%s(%s) fence %llx:%lld, global=%d, current %d\n",
+ GEM_TRACE("%s(%s) fence %llx:%lld, global=%d, current %d:%d\n",
__func__, engine->name,
rq->fence.context, rq->fence.seqno,
rq->global_seqno,
+ hwsp_seqno(rq),
intel_engine_get_seqno(engine));
GEM_BUG_ON(!i915_request_completed(rq));
@@ -244,10 +245,11 @@ static void i915_request_retire(struct i915_request
*request)
{
struct i915_gem_active *active, *next;
- GEM_TRACE("%s fence %llx:%lld, global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld, global=%d, current %d:%d\n",
request->engine->name,
request->fence.context, request->fence.seqno,
request->global_seqno,
+ hwsp_seqno(request),
intel_engine_get_seqno(request->engine));
lockdep_assert_held(>i915->drm.struct_mutex);
@@ -307,10 +309,11 @@ void i915_request_retire_upto(struct i915_request *rq)
struct intel_ring *ring = rq->ring;
struct i915_request *tmp;
- GEM_TRACE("%s fence %llx:%lld, global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld, global=%d, current %d:%d\n",
rq->engine->name,
rq->fence.context, rq->fence.seqno,
rq->global_seqno,
+ hwsp_seqno(rq),
intel_engine_get_seqno(rq->engine));
lockdep_assert_held(>i915->drm.struct_mutex);
@@ -355,10 +358,11 @@ void __i915_request_submit(struct i915_request *request)
struct intel_engine_cs *engine = request->engine;
u32 seqno;
- GEM_TRACE("%s fence %llx:%lld -> global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld -> global=%d, current %d:%d\n",
engine->name,
request->fence.context, request->fence.seqno,
engine->timeline.seqno + 1,
+ hwsp_seqno(request),
intel_engine_get_seqno(engine));
GEM_BUG_ON(!irqs_disabled());
@@ -405,10 +409,11 @@ void __i915_request_unsubmit(struct i915_request *request)
{
struct intel_engine_cs *engine = request->engine;
- GEM_TRACE("%s fence %llx:%lld <- global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld <- global=%d, current %d:%d\n",
engine->name,
request->fence.context, request->fence.seqno,
request->global_seqno,
+ hwsp_seqno(request),
intel_engine_get_seqno(engine));
GEM_BUG_ON(!irqs_disabled());
@@ -616,6 +621,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->ring = ce->ring;
rq->timeline = ce->ring->timeline;
GEM_BUG_ON(rq->timeline == >timeline);
+ rq->hwsp_seqno = >status_page.addr[I915_GEM_HWS_INDEX];
spin_lock_init(>lock);
dma_fence_init(>fence,
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index c0f084ca4f29..ade010fe6e26 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -130,6 +130,13 @@ struct i915_request {
struct i915_sched_node sched;
struct i915_dependency dep;
+ /*
+* A convenience pointer to the current breadcrumb value stored in
+* the HW status page (or our timeline's local equivalent). The full
+* path would be rq->hw_context->ring->timeline->hwsp_seqno.
+*/
+ const u32 *hwsp_seqno;
+
/**
* GEM sequence number associated with this request on the
* global execution timeline. It is zero when the request is not
@@ -285,11 +292,6 @@ static inline bool
[Intel-gfx] [PATCH 07/34] drm/i915: Refactor out intel_context_init()
Prior to adding a third instance of intel_context_init() and extending
the information stored therewithin, refactor out the common assignments.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 7 ++-
drivers/gpu/drm/i915/i915_gem_context.h | 8
drivers/gpu/drm/i915/selftests/mock_context.c | 7 ++-
3 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5933adbe3d99..fae68c4c4683 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -338,11 +338,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
ctx->i915 = dev_priv;
ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
- for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
- struct intel_context *ce = >__engine[n];
-
- ce->gem_context = ctx;
- }
+ for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++)
+ intel_context_init(>__engine[n], ctx, dev_priv->engine[n]);
INIT_RADIX_TREE(>handles_vma, GFP_KERNEL);
INIT_LIST_HEAD(>handles_list);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index f6d870b1f73e..47d82ce7ba6a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -364,4 +364,12 @@ static inline void i915_gem_context_put(struct
i915_gem_context *ctx)
kref_put(>ref, i915_gem_context_release);
}
+static inline void
+intel_context_init(struct intel_context *ce,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine)
+{
+ ce->gem_context = ctx;
+}
+
#endif /* !__I915_GEM_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/selftests/mock_context.c
b/drivers/gpu/drm/i915/selftests/mock_context.c
index d937bdff26f9..b646cdcdd602 100644
--- a/drivers/gpu/drm/i915/selftests/mock_context.c
+++ b/drivers/gpu/drm/i915/selftests/mock_context.c
@@ -45,11 +45,8 @@ mock_context(struct drm_i915_private *i915,
INIT_LIST_HEAD(>handles_list);
INIT_LIST_HEAD(>hw_id_link);
- for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
- struct intel_context *ce = >__engine[n];
-
- ce->gem_context = ctx;
- }
+ for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++)
+ intel_context_init(>__engine[n], ctx, i915->engine[n]);
ret = i915_gem_context_pin_hw_id(ctx);
if (ret < 0)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] dma-buf: Enhance dma-fence tracing
Rather than every backend and GPU driver reinventing the same wheel for
user level debugging of HW execution, the common dma-fence framework
should include the tracing infrastructure required for most client API
level flow visualisation.
With these common dma-fence level tracepoints, the userspace tools can
establish a detailed view of the client <-> HW flow across different
kernels. There is a strong ask to have this available, so that the
userspace developer can effectively assess if they're doing a good job
about feeding the beast of a GPU hardware.
In the case of needing to look into more fine-grained details of how
kernel internals work towards the goal of feeding the beast, the tools
may optionally amend the dma-fence tracing information with the driver
implementation specific. But for such cases, the tools should have a
graceful degradation in case the expected extra tracepoints have
changed or their format differs from the expected, as the kernel
implementation internals are not expected to stay the same.
It is important to distinguish between tracing for the purpose of client
flow visualisation and tracing for the purpose of low-level kernel
debugging. The latter is highly implementation specific, tied to
a particular HW and driver, whereas the former addresses a common goal
of user level tracing and likely a common set of userspace tools.
Having made the distinction that these tracepoints will be consumed for
client API tooling, we raise the spectre of tracepoint ABI stability. It
is hoped that by defining a common set of dma-fence tracepoints, we avoid
the pitfall of exposing low level details and so restrict ourselves only
to the high level flow that is applicable to all drivers and hardware.
Thus the reserved guarantee that this set of tracepoints will be stable
(with the emphasis on depicting client <-> HW flow as opposed to
driver <-> HW).
In terms of specific changes to the dma-fence tracing, we remove the
emission of the strings for every tracepoint (reserving them for
dma_fence_init for cases where they have unique dma_fence_ops, and
preferring to have descriptors for the whole fence context). strings do
not pack as well into the ftrace ringbuffer and we would prefer to
reduce the amount of indirect callbacks required for frequent tracepoint
emission.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Alex Deucher
Cc: "Christian König"
Cc: Eric Anholt
Cc: Pierre-Loup Griffais
Cc: Michael Sartain
Cc: Steven Rostedt
---
drivers/dma-buf/dma-fence.c | 9 +-
drivers/gpu/drm/i915/i915_gem_clflush.c | 5 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 1 -
drivers/gpu/drm/i915/i915_request.c | 16 +-
drivers/gpu/drm/i915/i915_timeline.c| 5 +
drivers/gpu/drm/i915/i915_trace.h | 134 ---
drivers/gpu/drm/i915/intel_guc_submission.c | 10 ++
drivers/gpu/drm/i915/intel_lrc.c| 6 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +
include/trace/events/dma_fence.h| 177 +++-
10 files changed, 214 insertions(+), 151 deletions(-)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 3aa8733f832a..5c93ed34b1ff 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -27,8 +27,15 @@
#define CREATE_TRACE_POINTS
#include
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_context_create);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_context_destroy);
+
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_await);
EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_execute_start);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_execute_end);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_wait_start);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_wait_end);
static DEFINE_SPINLOCK(dma_fence_stub_lock);
static struct dma_fence dma_fence_stub;
diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c
b/drivers/gpu/drm/i915/i915_gem_clflush.c
index 8e74c23cbd91..435c1303ecc8 100644
--- a/drivers/gpu/drm/i915/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/i915_gem_clflush.c
@@ -22,6 +22,8 @@
*
*/
+#include
+
#include "i915_drv.h"
#include "intel_frontbuffer.h"
#include "i915_gem_clflush.h"
@@ -73,6 +75,7 @@ static void i915_clflush_work(struct work_struct *work)
struct clflush *clflush = container_of(work, typeof(*clflush), work);
struct drm_i915_gem_object *obj = clflush->obj;
+ trace_dma_fence_execute_start(>dma, smp_processor_id());
if (i915_gem_object_pin_pages(obj)) {
DRM_ERROR("Failed to acquire obj->pages for clflushing\n");
goto out;
@@ -83,6 +86,7 @@ static void i915_clflush_work(struct work_struct *work)
i915_gem_object_unpin_pages(obj);
out:
+ trace_dma_fence_execute_end(>dma, smp_processor_id());
i915_gem_object_put(obj);
dma_fence_signal(>dma);
@@ -97,6 +101,7 @@ i915_clflush_notify(struct
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm: Add debug prints for the various object lookup errors
== Series Details ==
Series: series starting with [1/3] drm: Add debug prints for the various object
lookup errors
URL : https://patchwork.freedesktop.org/series/55524/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5459_full -> Patchwork_11999_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_11999_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11999_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11999_full:
### IGT changes ###
Possible regressions
* igt@kms_atomic@atomic_invalid_params:
- shard-apl: PASS -> FAIL +1
- shard-kbl: PASS -> FAIL +1
- shard-hsw: PASS -> FAIL +1
* igt@kms_properties@invalid-properties-legacy:
- shard-glk: PASS -> FAIL +1
- shard-snb: PASS -> FAIL +1
Known issues
Here are the changes found in Patchwork_11999_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> FAIL [fdo#108597]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166]
Possible fixes
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-glk: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_busy@extended-pageflip-hang-oldfb-render-b:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_cursor_crc@cursor-128x42-random:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-untiled:
- shard-snb: {SKIP} [fdo#109271] -> PASS +3
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: FAIL -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-apl: DMESG-FAIL [fdo#108950] -> PASS
Warnings
* igt@i915_suspend@shrink:
- shard-glk: DMESG-WARN [fdo#109244] -> INCOMPLETE [fdo#103359] /
[fdo#106886] / [k.org#198133]
* igt@kms_setmode@basic:
- shard-apl: INCOMPLETE [fdo#103927] -> FAIL [fdo#99912]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_11999
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11999: c2f89ad288cec5fdfd56a00db73e29559f57e19e @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11999/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Re: [Intel-gfx] [PATCH v5 3/3] PM/runtime:Replace jiffies based accounting with ktime based accounting
On Mon, Jan 21, 2019 at 4:17 PM Vincent Guittot wrote: > > On Fri, 18 Jan 2019 at 13:08, Guenter Roeck wrote: > > > > On 1/18/19 3:05 AM, Rafael J. Wysocki wrote: > > > On Fri, Jan 18, 2019 at 11:53 AM Vincent Guittot > > > wrote: > > >> > > >> On Fri, 18 Jan 2019 at 11:42, Vincent Guittot > > >> wrote: > > >>> > > >>> Hi Guenter, > > >>> > > >>> Le Thursday 17 Jan 2019 à 14:16:28 (-0800), Guenter Roeck a écrit : > > On Fri, Dec 21, 2018 at 11:33:56AM +0100, Vincent Guittot wrote: > > > From: Thara Gopinath > > > > > > This patch replaces jiffies based accounting for runtime_active_time > > > and runtime_suspended_time with ktime base accounting. This makes the > > > runtime debug counters inline with genpd and other pm subsytems which > > > uses ktime based accounting. > > > > > > timekeeping is initialized before pm_runtime_init() so ktime_get() > > > will > > > be ready before first call. In fact, timekeeping_init() is called > > > early > > > in start_kernel() which is way before driver_init() (and that's when > > > devices can start to be initialized) called from rest_init() via > > > kernel_init_freeable() and do_basic_setup(). > > > > > This is not (always) correct. My qemu "collie" boot test fails with > > this > > patch applied. Reverting the patch fixes the problem. Bisect log > > attached. > > > > >>> > > >>> Can you try the patch below ? > > >>> ktime_get_mono_fast_ns() has the advantage of being init with dummy > > >>> clock so > > >>> it can be used at early_init. > > >> > > >> Another possibility would be delay the init of the gpiochip > > > > > > Well, right. > > > > > > Initializing devices before timekeeping doesn't feel particularly > > > robust from the design perspective. > > > > > > How exactly does that happen? > > > > > > > With an added 'initialized' flag and backtrace into the timekeeping code, > > with the change suggested earlier applied: > > > > [ cut here ] > > WARNING: CPU: 0 PID: 0 at kernel/time/timekeeping.c:453 > > ktime_get_mono_fast_ns+0x114/0x12c > > Timekeeping not initialized > > CPU: 0 PID: 0 Comm: swapper Not tainted 5.0.0-rc2-next-20190117-dirty #2 > > Hardware name: Sharp-Collie > > Backtrace: > > [] (dump_backtrace) from [] (show_stack+0x18/0x1c) > > r7:0009 r6: r5:c065ba90 r4:c06d3e54 > > [] (show_stack) from [] (dump_stack+0x20/0x28) > > [] (dump_stack) from [] (__warn+0xcc/0xf4) > > [] (__warn) from [] (warn_slowpath_fmt+0x4c/0x6c) > > r8:df407b08 r7: r6:c0c01550 r5:c065bad8 r4:c06dd028 > > [] (warn_slowpath_fmt) from [] > > (ktime_get_mono_fast_ns+0x114/0x12c) > > r3: r2:c065bad8 > > r5: r4:df407b08 > > [] (ktime_get_mono_fast_ns) from [] > > (pm_runtime_init+0x38/0xb8) > > r9:c06c9a5c r8:df407b08 r7: r6:c0c01550 r5: r4:df407b08 > > [] (pm_runtime_init) from [] > > (device_initialize+0xb0/0xec) > > r7: r6:c0c01550 r5: r4:df407b08 > > [] (device_initialize) from [] > > (gpiochip_add_data_with_key+0x9c/0x884) > > r7: r6:c06fca34 r5: r4: > > [] (gpiochip_add_data_with_key) from [] > > (sa1100_init_gpio+0x40/0x98) > > r10:dfffcd60 r9:c06c9a5c r8:c06dd020 r7:c06dd028 r6: r5: > > r4:c06fca34 > > [] (sa1100_init_gpio) from [] > > (sa1100_init_irq+0x2c/0x3c) > > r7:c06dd028 r6: r5:c0713300 r4:c06e1070 > > [] (sa1100_init_irq) from [] (init_IRQ+0x20/0x28) > > r5:c0713300 r4: > > [] (init_IRQ) from [] (start_kernel+0x254/0x4cc) > > [] (start_kernel) from [<>] ( (null)) > > r10:717f r9:6901b119 r8:c100 r7:0092 r6:313d r5:0053 > > r4:c06a7330 > > ---[ end trace 91e1bd00dd7cce32 ]--- > > Does it means that only the pm_runtime_init is done before > timekeeping_init() but no update_pm_runtime_accounting() ? This platform calls device_initialize(), via sa1100_init_irq(), from init_IRQ() which is in the start_kernel() code path before timekeeping_init(). That's the initialization of structure fields alone. Runtime PM really cannot be used legitimately before driver_init(), because it needs bus types to be there at least. > In this case, we can keep using ktimeçget in > update_pm_runtime_accounting() and find a solution to deal with > early_call of pm_runtime_init() Given the above, I think that initializing accounting_timestamp in pm_runtime_init() to anything different from 0 is a mistake. Note that update_pm_runtime_accounting() ignores the delta value if power.disable_depth is not zero anyway, so it really should be sufficient to update accounting_timestamp when enabling runtime PM - and I'm not sure why it is not updated in pm_runtime_enable() for that matter (that looks like a bug to me). ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 30/34] drm/i915: Keep timeline HWSP allocated until the system is idle
Quoting Chris Wilson (2019-01-21 22:37:13) > Quoting Chris Wilson (2019-01-21 22:21:13) > > In preparation for enabling HW semaphores, we need to keep in flight > > timeline HWSP alive until the entire system is idle, as any other > > timeline active on the GPU may still refer back to the already retired > > timeline. We both have to delay recycling available cachelines and > > unpinning old HWSP until the next idle point (i.e. on parking). > > > > That we have to keep the HWSP alive for external references on HW raises > > an interesting conundrum. On a busy system, we may never see a global > > idle point, essentially meaning the resource will be leaking until we > > are forced to sleep. What we need is a set of RCU primitives for the GPU! > > This should also help mitigate the resource starvation issues > > promulgating from keeping all logical state pinned until idle (instead > > of as currently handled until the next context switch). > > I was resisting adding all the i915_vma_move_to_active() thinking that > it was overkill, but perhaps that is exactly what I mean by > rcu_read_lock(). Hmm. More so that I was trying to avoid having to keep > moving the HWSP from one request to the next (for the write lock), but > that should be for the normal case covered by the context pinning > itself, and for the realloc we can add a write lock to the next rq. Also because that mechanism is guarded by the struct_mutex and I have an aversion to struct_mutex... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/34] drm/i915: Stop tracking MRU activity on VMA
Our goal is to remove struct_mutex and replace it with fine grained
locking. One of the thorny issues is our eviction logic for reclaiming
space for an execbuffer (or GTT mmaping, among a few other examples).
While eviction itself is easy to move under a per-VM mutex, performing
the activity tracking is less agreeable. One solution is not to do any
MRU tracking and do a simple coarse evaluation during eviction of
active/inactive, with a loose temporal ordering of last
insertion/evaluation. That keeps all the locking constrained to when we
are manipulating the VM itself, neatly avoiding the tricky handling of
possible recursive locking during execbuf and elsewhere.
Note that discarding the MRU is unlikely to impact upon our efficiency
to reclaim VM space (where we think a LRU model is best) as our
current strategy is to use random idle replacement first before doing
a search, and over time the use of softpinned 48b per-ppGTT is growing
(thereby eliminating any need to perform any eviction searches, in
theory at least).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 10 +--
drivers/gpu/drm/i915/i915_gem_evict.c | 71 ---
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 26 +--
drivers/gpu/drm/i915/i915_gem_shrinker.c | 8 ++-
drivers/gpu/drm/i915/i915_gem_stolen.c| 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 37 +-
drivers/gpu/drm/i915/i915_vma.c | 9 +--
.../gpu/drm/i915/selftests/i915_gem_evict.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
10 files changed, 84 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d20b42386c3c..f45186ddb236 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -253,10 +253,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void
*data,
pinned = ggtt->vm.reserved;
mutex_lock(>struct_mutex);
- list_for_each_entry(vma, >vm.active_list, vm_link)
- if (i915_vma_is_pinned(vma))
- pinned += vma->node.size;
- list_for_each_entry(vma, >vm.inactive_list, vm_link)
+ list_for_each_entry(vma, >vm.bound_list, vm_link)
if (i915_vma_is_pinned(vma))
pinned += vma->node.size;
mutex_unlock(>struct_mutex);
@@ -1539,13 +1536,10 @@ static void i915_gem_object_bump_inactive_ggtt(struct
drm_i915_gem_object *obj)
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
for_each_ggtt_vma(vma, obj) {
- if (i915_vma_is_active(vma))
- continue;
-
if (!drm_mm_node_allocated(>node))
continue;
- list_move_tail(>vm_link, >vm->inactive_list);
+ list_move_tail(>vm_link, >vm->bound_list);
}
i915 = to_i915(obj->base.dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index f6855401f247..5cfe4b75e7d6 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -126,14 +126,10 @@ i915_gem_evict_something(struct i915_address_space *vm,
struct drm_i915_private *dev_priv = vm->i915;
struct drm_mm_scan scan;
struct list_head eviction_list;
- struct list_head *phases[] = {
- >inactive_list,
- >active_list,
- NULL,
- }, **phase;
struct i915_vma *vma, *next;
struct drm_mm_node *node;
enum drm_mm_insert_mode mode;
+ struct i915_vma *active;
int ret;
lockdep_assert_held(>i915->drm.struct_mutex);
@@ -169,17 +165,46 @@ i915_gem_evict_something(struct i915_address_space *vm,
*/
if (!(flags & PIN_NONBLOCK))
i915_retire_requests(dev_priv);
- else
- phases[1] = NULL;
search_again:
+ active = NULL;
INIT_LIST_HEAD(_list);
- phase = phases;
- do {
- list_for_each_entry(vma, *phase, vm_link)
- if (mark_free(, vma, flags, _list))
- goto found;
- } while (*++phase);
+ list_for_each_entry_safe(vma, next, >bound_list, vm_link) {
+ /*
+* We keep this list in a rough least-recently scanned order
+* of active elements (inactive elements are cheap to reap).
+* New entries are added to the end, and we move anything we
+* scan to the end. The assumption is that the working set
+* of applications is either steady state (and thanks to the
+* userspace bo cache it almost always is) or volatile and
+* frequently replaced after a frame, which are self-evicting!
+* Given that assumption, the MRU order of
[Intel-gfx] [PATCH 02/34] drm/i915/execlists: Suppress preempting self
In order to avoid preempting ourselves, we currently refuse to schedule
the tasklet if we reschedule an inflight context. However, this glosses
over a few issues such as what happens after a CS completion event and
we then preempt the newly executing context with itself, or if something
else causes a tasklet_schedule triggering the same evaluation to
preempt the active context with itself.
To avoid the extra complications, after deciding that we have
potentially queued a request with higher priority than the currently
executing request, inspect the head of the queue to see if it is indeed
higher priority from another context.
References: a2bf92e8cc16 ("drm/i915/execlists: Avoid kicking priority on the
current context")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_scheduler.c | 20 ++
drivers/gpu/drm/i915/intel_lrc.c | 29 ++-
2 files changed, 44 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 340faea6c08a..fb5d953430e5 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -239,6 +239,18 @@ sched_lock_engine(struct i915_sched_node *node, struct
intel_engine_cs *locked)
return engine;
}
+static bool inflight(const struct i915_request *rq,
+const struct intel_engine_cs *engine)
+{
+ const struct i915_request *active;
+
+ if (!rq->global_seqno)
+ return false;
+
+ active = port_request(engine->execlists.port);
+ return active->hw_context == rq->hw_context;
+}
+
static void __i915_schedule(struct i915_request *rq,
const struct i915_sched_attr *attr)
{
@@ -328,6 +340,7 @@ static void __i915_schedule(struct i915_request *rq,
INIT_LIST_HEAD(>dfs_link);
engine = sched_lock_engine(node, engine);
+ lockdep_assert_held(>timeline.lock);
/* Recheck after acquiring the engine->timeline.lock */
if (prio <= node->attr.priority || node_signaled(node))
@@ -356,17 +369,16 @@ static void __i915_schedule(struct i915_request *rq,
if (prio <= engine->execlists.queue_priority)
continue;
+ engine->execlists.queue_priority = prio;
+
/*
* If we are already the currently executing context, don't
* bother evaluating if we should preempt ourselves.
*/
- if (node_to_request(node)->global_seqno &&
-
i915_seqno_passed(port_request(engine->execlists.port)->global_seqno,
- node_to_request(node)->global_seqno))
+ if (inflight(node_to_request(node), engine))
continue;
/* Defer (tasklet) submission until after all of our updates. */
- engine->execlists.queue_priority = prio;
tasklet_hi_schedule(>execlists.tasklet);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b74f25420683..28d183439952 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -190,6 +190,30 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
!i915_request_completed(last));
}
+static inline bool check_preempt(const struct intel_engine_cs *engine,
+const struct i915_request *rq)
+{
+ const struct intel_context *ctx = rq->hw_context;
+ const int prio = rq_prio(rq);
+ struct rb_node *rb;
+ int idx;
+
+ list_for_each_entry_continue(rq, >timeline.requests, link) {
+ GEM_BUG_ON(rq->hw_context == ctx);
+ if (rq_prio(rq) > prio)
+ return true;
+ }
+
+ rb = rb_first_cached(>execlists.queue);
+ if (!rb)
+ return false;
+
+ priolist_for_each_request(rq, to_priolist(rb), idx)
+ return rq->hw_context != ctx && rq_prio(rq) > prio;
+
+ return false;
+}
+
/*
* The context descriptor encodes various attributes of a context,
* including its GTT address and some flags. Because it's fairly
@@ -580,7 +604,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
return;
- if (need_preempt(engine, last, execlists->queue_priority)) {
+ if (need_preempt(engine, last, execlists->queue_priority) &&
+ check_preempt(engine, last)) {
inject_preempt_context(engine);
return;
}
@@ -872,6 +897,8 @@ static void process_csb(struct intel_engine_cs *engine)
const u32 * const buf = execlists->csb_status;
u8 head, tail;
+
Re: [Intel-gfx] [PATCH 30/34] drm/i915: Keep timeline HWSP allocated until the system is idle
Quoting Chris Wilson (2019-01-21 22:21:13) > In preparation for enabling HW semaphores, we need to keep in flight > timeline HWSP alive until the entire system is idle, as any other > timeline active on the GPU may still refer back to the already retired > timeline. We both have to delay recycling available cachelines and > unpinning old HWSP until the next idle point (i.e. on parking). > > That we have to keep the HWSP alive for external references on HW raises > an interesting conundrum. On a busy system, we may never see a global > idle point, essentially meaning the resource will be leaking until we > are forced to sleep. What we need is a set of RCU primitives for the GPU! > This should also help mitigate the resource starvation issues > promulgating from keeping all logical state pinned until idle (instead > of as currently handled until the next context switch). I was resisting adding all the i915_vma_move_to_active() thinking that it was overkill, but perhaps that is exactly what I mean by rcu_read_lock(). Hmm. More so that I was trying to avoid having to keep moving the HWSP from one request to the next (for the write lock), but that should be for the normal case covered by the context pinning itself, and for the realloc we can add a write lock to the next rq. How does that help? Good question. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 31/34] drm/i915/execlists: Refactor out can_merge_rq()
In the next patch, we add another user that wants to check whether
requests can be merge into a single HW execution, and in the future we
want to add more conditions under which requests from the same context
cannot be merge. In preparation, extract out can_merge_rq().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0a2d53f19625..3d8fffa1b6dc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -511,6 +511,17 @@ static bool can_merge_ctx(const struct intel_context *prev,
return true;
}
+static bool can_merge_rq(const struct i915_request *prev,
+const struct i915_request *next)
+{
+ GEM_BUG_ON(need_preempt(prev->engine, prev, rq_prio(next)));
+
+ if (!can_merge_ctx(prev->hw_context, next->hw_context))
+ return false;
+
+ return true;
+}
+
static void port_assign(struct execlist_port *port, struct i915_request *rq)
{
GEM_BUG_ON(rq == port_request(port));
@@ -662,9 +673,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
int i;
priolist_for_each_request_consume(rq, rn, p, i) {
- GEM_BUG_ON(last &&
- need_preempt(engine, last, rq_prio(rq)));
-
/*
* Can we combine this request with the current port?
* It has to be the same context/ringbuffer and not
@@ -676,8 +684,10 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* second request, and so we never need to tell the
* hardware about the first.
*/
- if (last &&
- !can_merge_ctx(rq->hw_context, last->hw_context)) {
+ if (last && !can_merge_rq(last, rq)) {
+ if (last->hw_context == rq->hw_context)
+ goto done;
+
/*
* If we are on the second port and cannot
* combine this request with the last, then we
@@ -697,7 +707,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
ctx_single_port_submission(rq->hw_context))
goto done;
- GEM_BUG_ON(last->hw_context == rq->hw_context);
if (submit)
port_assign(port, last);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 23/34] drm/i915: Share per-timeline HWSP using a slab suballocator
If we restrict ourselves to only using a cacheline for each timeline's
HWSP (we could go smaller, but want to avoid needless polluting
cachelines on different engines between different contexts), then we can
suballocate a single 4k page into 64 different timeline HWSP. By
treating each fresh allocation as a slab of 64 entries, we can keep it
around for the next 64 allocation attempts until we need to refresh the
slab cache.
John Harrison noted the issue of fragmentation leading to the same worst
case performance of one page per timeline as before, which can be
mitigated by adopting a freelist.
v2: Keep all partially allocated HWSP on a freelist
This is still without migration, so it is possible for the system to end
up with each timeline in its own page, but we ensure that no new
allocation would needless allocate a fresh page!
v3: Throw a selftest at the allocator to try and catch invalid cacheline
reuse.
Signed-off-by: Chris Wilson
Cc: John Harrison
---
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_timeline.c | 117 ---
drivers/gpu/drm/i915/i915_timeline.h | 1 +
drivers/gpu/drm/i915/i915_vma.h | 12 ++
drivers/gpu/drm/i915/selftests/i915_random.c | 33 -
drivers/gpu/drm/i915/selftests/i915_random.h | 3 +
.../gpu/drm/i915/selftests/i915_timeline.c| 140 ++
7 files changed, 282 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 364067f811f7..c00eaf2889fb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1978,6 +1978,10 @@ struct drm_i915_private {
struct i915_gt_timelines {
struct mutex mutex; /* protects list, tainted by GPU */
struct list_head list;
+
+ /* Pack multiple timelines' seqnos into the same page */
+ spinlock_t hwsp_lock;
+ struct list_head hwsp_free_list;
} timelines;
struct list_head active_rings;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 8d5792311a8f..69ee33dfa340 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -9,6 +9,12 @@
#include "i915_timeline.h"
#include "i915_syncmap.h"
+struct i915_timeline_hwsp {
+ struct i915_vma *vma;
+ struct list_head free_link;
+ u64 free_bitmap;
+};
+
static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
{
struct drm_i915_gem_object *obj;
@@ -27,28 +33,92 @@ static struct i915_vma *__hwsp_alloc(struct
drm_i915_private *i915)
return vma;
}
-static int hwsp_alloc(struct i915_timeline *timeline)
+static struct i915_vma *
+hwsp_alloc(struct i915_timeline *timeline, int *offset)
{
- struct i915_vma *vma;
+ struct drm_i915_private *i915 = timeline->i915;
+ struct i915_gt_timelines *gt = >gt.timelines;
+ struct i915_timeline_hwsp *hwsp;
+ int cacheline;
- vma = __hwsp_alloc(timeline->i915);
- if (IS_ERR(vma))
- return PTR_ERR(vma);
+ BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
- timeline->hwsp_ggtt = vma;
- timeline->hwsp_offset = 0;
+ spin_lock(>hwsp_lock);
- return 0;
+ /* hwsp_free_list only contains HWSP that have available cachelines */
+ hwsp = list_first_entry_or_null(>hwsp_free_list,
+ typeof(*hwsp), free_link);
+ if (!hwsp) {
+ struct i915_vma *vma;
+
+ spin_unlock(>hwsp_lock);
+
+ hwsp = kmalloc(sizeof(*hwsp), GFP_KERNEL);
+ if (!hwsp)
+ return ERR_PTR(-ENOMEM);
+
+ vma = __hwsp_alloc(i915);
+ if (IS_ERR(vma)) {
+ kfree(hwsp);
+ return vma;
+ }
+
+ vma->private = hwsp;
+ hwsp->vma = vma;
+ hwsp->free_bitmap = ~0ull;
+
+ spin_lock(>hwsp_lock);
+ list_add(>free_link, >hwsp_free_list);
+ }
+
+ GEM_BUG_ON(!hwsp->free_bitmap);
+ cacheline = __ffs64(hwsp->free_bitmap);
+ hwsp->free_bitmap &= ~BIT_ULL(cacheline);
+ if (!hwsp->free_bitmap)
+ list_del(>free_link);
+
+ spin_unlock(>hwsp_lock);
+
+ GEM_BUG_ON(hwsp->vma->private != hwsp);
+
+ *offset = cacheline * CACHELINE_BYTES;
+ return hwsp->vma;
+}
+
+static void hwsp_free(struct i915_timeline *timeline)
+{
+ struct i915_gt_timelines *gt = >i915->gt.timelines;
+ struct i915_timeline_hwsp *hwsp;
+
+ hwsp = i915_timeline_hwsp(timeline);
+ if (!hwsp) /* leave global HWSP alone! */
+ return;
+
+ spin_lock(>hwsp_lock);
+
+ /* As a cacheline becomes available, publish
[Intel-gfx] [PATCH 17/34] drm/i915: Move list of timelines under its own lock
Currently, the list of timelines is serialised by the struct_mutex, but
to alleviate difficulties with using that mutex in future, move the
list management under its own dedicated mutex.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_gem.c | 103 ++
drivers/gpu/drm/i915/i915_reset.c | 8 +-
drivers/gpu/drm/i915/i915_timeline.c | 38 ++-
drivers/gpu/drm/i915/i915_timeline.h | 3 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 7 +-
.../gpu/drm/i915/selftests/mock_timeline.c| 3 +-
7 files changed, 109 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 59a7e90113d7..364067f811f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1975,7 +1975,10 @@ struct drm_i915_private {
void (*resume)(struct drm_i915_private *);
void (*cleanup_engine)(struct intel_engine_cs *engine);
- struct list_head timelines;
+ struct i915_gt_timelines {
+ struct mutex mutex; /* protects list, tainted by GPU */
+ struct list_head list;
+ } timelines;
struct list_head active_rings;
struct list_head closed_vma;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 15acd052da46..761714448ff3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3222,33 +3222,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
return ret;
}
-static long wait_for_timeline(struct i915_timeline *tl,
- unsigned int flags, long timeout)
-{
- struct i915_request *rq;
-
- rq = i915_gem_active_get_unlocked(>last_request);
- if (!rq)
- return timeout;
-
- /*
-* "Race-to-idle".
-*
-* Switching to the kernel context is often used a synchronous
-* step prior to idling, e.g. in suspend for flushing all
-* current operations to memory before sleeping. These we
-* want to complete as quickly as possible to avoid prolonged
-* stalls, so allow the gpu to boost to maximum clocks.
-*/
- if (flags & I915_WAIT_FOR_IDLE_BOOST)
- gen6_rps_boost(rq, NULL);
-
- timeout = i915_request_wait(rq, flags, timeout);
- i915_request_put(rq);
-
- return timeout;
-}
-
static int wait_for_engines(struct drm_i915_private *i915)
{
if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) {
@@ -3262,6 +3235,52 @@ static int wait_for_engines(struct drm_i915_private
*i915)
return 0;
}
+static long
+wait_for_timelines(struct drm_i915_private *i915,
+ unsigned int flags, long timeout)
+{
+ struct i915_gt_timelines *gt = >gt.timelines;
+ struct i915_timeline *tl;
+
+ if (!READ_ONCE(i915->gt.active_requests))
+ return timeout;
+
+ mutex_lock(>mutex);
+ list_for_each_entry(tl, >list, link) {
+ struct i915_request *rq;
+
+ rq = i915_gem_active_get_unlocked(>last_request);
+ if (!rq)
+ continue;
+
+ mutex_unlock(>mutex);
+
+ /*
+* "Race-to-idle".
+*
+* Switching to the kernel context is often used a synchronous
+* step prior to idling, e.g. in suspend for flushing all
+* current operations to memory before sleeping. These we
+* want to complete as quickly as possible to avoid prolonged
+* stalls, so allow the gpu to boost to maximum clocks.
+*/
+ if (flags & I915_WAIT_FOR_IDLE_BOOST)
+ gen6_rps_boost(rq, NULL);
+
+ timeout = i915_request_wait(rq, flags, timeout);
+ i915_request_put(rq);
+ if (timeout < 0)
+ return timeout;
+
+ /* restart after reacquiring the lock */
+ mutex_lock(>mutex);
+ tl = list_entry(>list, typeof(*tl), link);
+ }
+ mutex_unlock(>mutex);
+
+ return timeout;
+}
+
int i915_gem_wait_for_idle(struct drm_i915_private *i915,
unsigned int flags, long timeout)
{
@@ -3273,17 +3292,15 @@ int i915_gem_wait_for_idle(struct drm_i915_private
*i915,
if (!READ_ONCE(i915->gt.awake))
return 0;
+ timeout = wait_for_timelines(i915, flags, timeout);
+ if (timeout < 0)
+ return timeout;
+
if (flags & I915_WAIT_LOCKED) {
- struct i915_timeline *tl;
int err;
lockdep_assert_held(>drm.struct_mutex);
-
[Intel-gfx] [PATCH 05/34] drm/i915/selftests: Track evict objects explicitly
During review of commit 71fc448c1aaf ("drm/i915/selftests: Make evict
tolerant of foreign objects"), Matthew mentioned it would be better if
we explicitly tracked the objects we created. We have an obj->st_link
hook for this purpose, so add the corresponding list of objects and
reduce our loops to only consider our own list.
References: 71fc448c1aaf ("drm/i915/selftests: Make evict tolerant of foreign
objects")
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_gem_evict.c | 114 +-
1 file changed, 55 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 543d618c152b..d0553bc69705 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -29,25 +29,21 @@
#include "mock_drm.h"
#include "mock_gem_device.h"
-static int populate_ggtt(struct drm_i915_private *i915)
+static void quirk_add(struct drm_i915_gem_object *obj,
+ struct list_head *objects)
+{
+ /* quirk is only for live tiled objects, use it to declare ownership */
+ GEM_BUG_ON(obj->mm.quirked);
+ obj->mm.quirked = true;
+ list_add(>st_link, objects);
+}
+
+static int populate_ggtt(struct drm_i915_private *i915,
+struct list_head *objects)
{
- struct drm_i915_gem_object *obj, *on;
- unsigned long expected_unbound, expected_bound;
unsigned long unbound, bound, count;
+ struct drm_i915_gem_object *obj;
u64 size;
- int err;
-
- expected_unbound = 0;
- list_for_each_entry(obj, >mm.unbound_list, mm.link) {
- i915_gem_object_get(obj);
- expected_unbound++;
- }
-
- expected_bound = 0;
- list_for_each_entry(obj, >mm.bound_list, mm.link) {
- i915_gem_object_get(obj);
- expected_bound++;
- }
count = 0;
for (size = 0;
@@ -56,38 +52,36 @@ static int populate_ggtt(struct drm_i915_private *i915)
struct i915_vma *vma;
obj = i915_gem_object_create_internal(i915, I915_GTT_PAGE_SIZE);
- if (IS_ERR(obj)) {
- err = PTR_ERR(obj);
- goto cleanup;
- }
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ quirk_add(obj, objects);
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
- if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto cleanup;
- }
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
count++;
}
unbound = 0;
list_for_each_entry(obj, >mm.unbound_list, mm.link)
- unbound++;
- if (unbound != expected_unbound) {
- pr_err("%s: Found %lu objects unbound, expected %lu!\n",
- __func__, unbound, expected_unbound);
- err = -EINVAL;
- goto cleanup;
+ if (obj->mm.quirked)
+ unbound++;
+ if (unbound) {
+ pr_err("%s: Found %lu objects unbound, expected %u!\n",
+ __func__, unbound, 0);
+ return -EINVAL;
}
bound = 0;
list_for_each_entry(obj, >mm.bound_list, mm.link)
- bound++;
- if (bound != expected_bound + count) {
+ if (obj->mm.quirked)
+ bound++;
+ if (bound != count) {
pr_err("%s: Found %lu objects bound, expected %lu!\n",
- __func__, bound, expected_bound + count);
- err = -EINVAL;
- goto cleanup;
+ __func__, bound, count);
+ return -EINVAL;
}
if (list_empty(>ggtt.vm.inactive_list)) {
@@ -96,15 +90,6 @@ static int populate_ggtt(struct drm_i915_private *i915)
}
return 0;
-
-cleanup:
- list_for_each_entry_safe(obj, on, >mm.unbound_list, mm.link)
- i915_gem_object_put(obj);
-
- list_for_each_entry_safe(obj, on, >mm.bound_list, mm.link)
- i915_gem_object_put(obj);
-
- return err;
}
static void unpin_ggtt(struct drm_i915_private *i915)
@@ -112,18 +97,20 @@ static void unpin_ggtt(struct drm_i915_private *i915)
struct i915_vma *vma;
list_for_each_entry(vma, >ggtt.vm.inactive_list, vm_link)
- i915_vma_unpin(vma);
+ if (vma->obj->mm.quirked)
+ i915_vma_unpin(vma);
}
-static void cleanup_objects(struct drm_i915_private *i915)
+static void cleanup_objects(struct drm_i915_private *i915,
+ struct list_head *list)
{
struct drm_i915_gem_object *obj, *on;
- list_for_each_entry_safe(obj, on, >mm.unbound_list, mm.link)
-
[Intel-gfx] [PATCH 25/34] drm/i915: Track active timelines
Now that we pin timelines around use, we have a clearly defined lifetime
and convenient points at which we can track only the active timelines.
This allows us to reduce the list iteration to only consider those
active timelines and not all.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 4 +--
drivers/gpu/drm/i915/i915_reset.c| 2 +-
drivers/gpu/drm/i915/i915_timeline.c | 39 ++--
4 files changed, 29 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c00eaf2889fb..5577e0e1034f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1977,7 +1977,7 @@ struct drm_i915_private {
struct i915_gt_timelines {
struct mutex mutex; /* protects list, tainted by GPU */
- struct list_head list;
+ struct list_head active_list;
/* Pack multiple timelines' seqnos into the same page */
spinlock_t hwsp_lock;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4e0de22f0166..9c499edb4c13 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3246,7 +3246,7 @@ wait_for_timelines(struct drm_i915_private *i915,
return timeout;
mutex_lock(>mutex);
- list_for_each_entry(tl, >list, link) {
+ list_for_each_entry(tl, >active_list, link) {
struct i915_request *rq;
rq = i915_gem_active_get_unlocked(>last_request);
@@ -3274,7 +3274,7 @@ wait_for_timelines(struct drm_i915_private *i915,
/* restart after reacquiring the lock */
mutex_lock(>mutex);
- tl = list_entry(>list, typeof(*tl), link);
+ tl = list_entry(>active_list, typeof(*tl), link);
}
mutex_unlock(>mutex);
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 09edf488f711..9b9169508139 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -852,7 +852,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
* No more can be submitted until we reset the wedged bit.
*/
mutex_lock(>gt.timelines.mutex);
- list_for_each_entry(tl, >gt.timelines.list, link) {
+ list_for_each_entry(tl, >gt.timelines.active_list, link) {
struct i915_request *rq;
long timeout;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 69ee33dfa340..007348b1b469 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -117,7 +117,6 @@ int i915_timeline_init(struct drm_i915_private *i915,
const char *name,
struct i915_vma *hwsp)
{
- struct i915_gt_timelines *gt = >gt.timelines;
void *vaddr;
/*
@@ -161,10 +160,6 @@ int i915_timeline_init(struct drm_i915_private *i915,
i915_syncmap_init(>sync);
- mutex_lock(>mutex);
- list_add(>link, >list);
- mutex_unlock(>mutex);
-
return 0;
}
@@ -173,7 +168,7 @@ void i915_timelines_init(struct drm_i915_private *i915)
struct i915_gt_timelines *gt = >gt.timelines;
mutex_init(>mutex);
- INIT_LIST_HEAD(>list);
+ INIT_LIST_HEAD(>active_list);
spin_lock_init(>hwsp_lock);
INIT_LIST_HEAD(>hwsp_free_list);
@@ -182,6 +177,24 @@ void i915_timelines_init(struct drm_i915_private *i915)
i915_gem_shrinker_taints_mutex(i915, >mutex);
}
+static void timeline_active(struct i915_timeline *tl)
+{
+ struct i915_gt_timelines *gt = >i915->gt.timelines;
+
+ mutex_lock(>mutex);
+ list_add(>link, >active_list);
+ mutex_unlock(>mutex);
+}
+
+static void timeline_inactive(struct i915_timeline *tl)
+{
+ struct i915_gt_timelines *gt = >i915->gt.timelines;
+
+ mutex_lock(>mutex);
+ list_del(>link);
+ mutex_unlock(>mutex);
+}
+
/**
* i915_timelines_park - called when the driver idles
* @i915: the drm_i915_private device
@@ -198,7 +211,7 @@ void i915_timelines_park(struct drm_i915_private *i915)
struct i915_timeline *timeline;
mutex_lock(>mutex);
- list_for_each_entry(timeline, >list, link) {
+ list_for_each_entry(timeline, >active_list, link) {
/*
* All known fences are completed so we can scrap
* the current sync point tracking and start afresh,
@@ -212,15 +225,9 @@ void i915_timelines_park(struct drm_i915_private *i915)
void i915_timeline_fini(struct i915_timeline *timeline)
{
- struct i915_gt_timelines *gt = >i915->gt.timelines;
-
GEM_BUG_ON(timeline->pin_count);
GEM_BUG_ON(!list_empty(>requests));
-
[Intel-gfx] [PATCH 26/34] drm/i915: Identify active requests
To allow requests to forgo a common execution timeline, one question we
need to be able to answer is "is this request running?". To track
whether a request has started on HW, we can emit a breadcrumb at the
beginning of the request and check its timeline's HWSP to see if the
breadcrumb has advanced past the start of this request. (This is in
contrast to the global timeline where we need only ask if we are on the
global timeline and if the timeline has advanced past the end of the
previous request.)
There is still confusion from a preempted request, which has already
started but relinquished the HW to a high priority request. For the
common case, this discrepancy should be negligible. However, for
identification of hung requests, knowing which one was running at the
time of the hang will be much more important.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +++
drivers/gpu/drm/i915/i915_request.c | 9 ++--
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_timeline.c | 1 +
drivers/gpu/drm/i915/i915_timeline.h | 2 +
drivers/gpu/drm/i915/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/intel_lrc.c | 47
drivers/gpu/drm/i915/intel_ringbuffer.c | 43 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 6 ++-
drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
10 files changed, 86 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index f250109e1f66..defe7d60bb88 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1976,6 +1976,12 @@ static int eb_submit(struct i915_execbuffer *eb)
return err;
}
+ if (eb->engine->emit_init_breadcrumb) {
+ err = eb->engine->emit_init_breadcrumb(eb->request);
+ if (err)
+ return err;
+ }
+
err = eb->engine->emit_bb_start(eb->request,
eb->batch->node.start +
eb->batch_start_offset,
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index bb2885f1dc1e..0a8a2a1bf55d 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -333,6 +333,7 @@ void i915_request_retire_upto(struct i915_request *rq)
static u32 timeline_get_seqno(struct i915_timeline *tl)
{
+ tl->seqno += tl->has_initial_breadcrumb;
return ++tl->seqno;
}
@@ -382,8 +383,8 @@ void __i915_request_submit(struct i915_request *request)
intel_engine_enable_signaling(request, false);
spin_unlock(>lock);
- engine->emit_breadcrumb(request,
- request->ring->vaddr + request->postfix);
+ engine->emit_fini_breadcrumb(request,
+request->ring->vaddr + request->postfix);
/* Transfer from per-context onto the global per-engine timeline */
move_to_timeline(request, >timeline);
@@ -657,7 +658,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
* around inside i915_request_add() there is sufficient space at
* the beginning of the ring as well.
*/
- rq->reserved_space = 2 * engine->emit_breadcrumb_sz * sizeof(u32);
+ rq->reserved_space = 2 * engine->emit_fini_breadcrumb_sz * sizeof(u32);
/*
* Record the position of the start of the request so that
@@ -908,7 +909,7 @@ void i915_request_add(struct i915_request *request)
* GPU processing the request, we never over-estimate the
* position of the ring's HEAD.
*/
- cs = intel_ring_begin(request, engine->emit_breadcrumb_sz);
+ cs = intel_ring_begin(request, engine->emit_fini_breadcrumb_sz);
GEM_BUG_ON(IS_ERR(cs));
request->postfix = intel_ring_offset(request, cs);
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 96c586d6ff4d..340d6216791c 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -344,6 +344,7 @@ static inline bool i915_request_started(const struct
i915_request *rq)
if (i915_request_signaled(rq))
return true;
+ /* Remember: started but may have since been preempted! */
return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno - 1);
}
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 007348b1b469..7bc9164733bc 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -132,6 +132,7 @@ int i915_timeline_init(struct drm_i915_private *i915,
timeline->i915 = i915;
timeline->name = name;
timeline->pin_count = 0;
+
[Intel-gfx] [PATCH 11/34] drm/i915/selftests: Trim struct_mutex duration for set-wedged selftest
Trim the struct_mutex hold and exclude the call to i915_gem_set_wedged() as a reminder that it must be callable without struct_mutex held. Signed-off-by: Chris Wilson Cc: Michal Wajdeczko Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 67431355cd6e..8025c7e0bf6c 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -389,16 +389,16 @@ static int igt_wedged_reset(void *arg) /* Check that we can recover a wedged device with a GPU reset */ igt_global_reset_lock(i915); - mutex_lock(>drm.struct_mutex); wakeref = intel_runtime_pm_get(i915); i915_gem_set_wedged(i915); - GEM_BUG_ON(!i915_terminally_wedged(>gpu_error)); + mutex_lock(>drm.struct_mutex); + GEM_BUG_ON(!i915_terminally_wedged(>gpu_error)); i915_reset(i915, ALL_ENGINES, NULL); + mutex_unlock(>drm.struct_mutex); intel_runtime_pm_put(i915, wakeref); - mutex_unlock(>drm.struct_mutex); igt_global_reset_unlock(i915); return i915_terminally_wedged(>gpu_error) ? -EIO : 0; @@ -1675,6 +1675,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) wakeref = intel_runtime_pm_get(i915); saved_hangcheck = fetch_and_zero(_modparams.enable_hangcheck); + drain_delayed_work(>gpu_error.hangcheck_work); /* flush param */ err = i915_subtests(tests, i915); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/34] drm/i915: Pull VM lists under the VM mutex.
A starting point to counter the pervasive struct_mutex. For the goal of
avoiding (or at least blocking under them!) global locks during user
request submission, a simple but important step is being able to manage
each clients GTT separately. For which, we want to replace using the
struct_mutex as the guard for all things GTT/VM and switch instead to a
specific mutex inside i915_address_space.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 14 --
drivers/gpu/drm/i915/i915_gem_evict.c | 2 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +--
drivers/gpu/drm/i915/i915_gem_shrinker.c| 4
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 ++
drivers/gpu/drm/i915/i915_vma.c | 11 +++
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 3 +++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
8 files changed, 46 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f45186ddb236..538fa5404603 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -245,18 +245,19 @@ int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = _priv->ggtt;
+ struct i915_ggtt *ggtt = _i915(dev)->ggtt;
struct drm_i915_gem_get_aperture *args = data;
struct i915_vma *vma;
u64 pinned;
+ mutex_lock(>vm.mutex);
+
pinned = ggtt->vm.reserved;
- mutex_lock(>struct_mutex);
list_for_each_entry(vma, >vm.bound_list, vm_link)
if (i915_vma_is_pinned(vma))
pinned += vma->node.size;
- mutex_unlock(>struct_mutex);
+
+ mutex_unlock(>vm.mutex);
args->aper_size = ggtt->vm.total;
args->aper_available_size = args->aper_size - pinned;
@@ -1529,20 +1530,21 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void
*data,
static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *i915;
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct list_head *list;
struct i915_vma *vma;
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+ mutex_lock(>ggtt.vm.mutex);
for_each_ggtt_vma(vma, obj) {
if (!drm_mm_node_allocated(>node))
continue;
list_move_tail(>vm_link, >vm->bound_list);
}
+ mutex_unlock(>ggtt.vm.mutex);
- i915 = to_i915(obj->base.dev);
spin_lock(>mm.obj_lock);
list = obj->bind_count ? >mm.bound_list : >mm.unbound_list;
list_move_tail(>mm.link, list);
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 5cfe4b75e7d6..dc137701acb8 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -432,6 +432,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
}
INIT_LIST_HEAD(_list);
+ mutex_lock(>mutex);
list_for_each_entry(vma, >bound_list, vm_link) {
if (i915_vma_is_pinned(vma))
continue;
@@ -439,6 +440,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
__i915_vma_pin(vma);
list_add(>evict_link, _list);
}
+ mutex_unlock(>mutex);
ret = 0;
list_for_each_entry_safe(vma, next, _list, evict_link) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2ad9070a54c1..49b00996a15e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1931,7 +1931,10 @@ static struct i915_vma *pd_vma_create(struct
gen6_hw_ppgtt *ppgtt, int size)
vma->ggtt_view.type = I915_GGTT_VIEW_ROTATED; /* prevent fencing */
INIT_LIST_HEAD(>obj_link);
+
+ mutex_lock(>vm->mutex);
list_add(>vm_link, >vm->unbound_list);
+ mutex_unlock(>vm->mutex);
return vma;
}
@@ -3504,9 +3507,10 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
i915_check_and_clear_faults(dev_priv);
+ mutex_lock(>vm.mutex);
+
/* First fill our portion of the GTT with scratch pages */
ggtt->vm.clear_range(>vm, 0, ggtt->vm.total);
-
ggtt->vm.closed = true; /* skip rewriting PTE on VMA unbind */
/* clflush objects bound into the GGTT and rebind them. */
@@ -3516,19 +3520,26 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
if (!(vma->flags & I915_VMA_GLOBAL_BIND))
continue;
+ mutex_unlock(>vm.mutex);
+
if (!i915_vma_unbind(vma))
- continue;
+ goto lock;
[Intel-gfx] [PATCH 15/34] drm/i915: Move vma lookup to its own lock
Remove the struct_mutex requirement for looking up the vma for an
object.
v2: Highlight how the race for duplicate vma creation is resolved on
reacquiring the lock with a short comment.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_gem.c | 33 +++-
drivers/gpu/drm/i915/i915_gem_object.h| 45 +---
drivers/gpu/drm/i915/i915_vma.c | 66 ---
drivers/gpu/drm/i915/i915_vma.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 4 +-
6 files changed, 98 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3ec369980d40..2a6e4044f25b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -159,14 +159,14 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
if (obj->base.name)
seq_printf(m, " (name: %d)", obj->base.name);
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (i915_vma_is_pinned(vma))
pin_count++;
}
seq_printf(m, " (pinned x %d)", pin_count);
if (obj->pin_global)
seq_printf(m, " (global)");
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (!drm_mm_node_allocated(>node))
continue;
@@ -322,7 +322,7 @@ static int per_file_stats(int id, void *ptr, void *data)
if (obj->base.name || obj->base.dma_buf)
stats->shared += obj->base.size;
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (!drm_mm_node_allocated(>node))
continue;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 538fa5404603..15acd052da46 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -437,15 +437,19 @@ int i915_gem_object_unbind(struct drm_i915_gem_object
*obj)
if (ret)
return ret;
- while ((vma = list_first_entry_or_null(>vma_list,
- struct i915_vma,
- obj_link))) {
+ spin_lock(>vma.lock);
+ while (!ret && (vma = list_first_entry_or_null(>vma.list,
+ struct i915_vma,
+ obj_link))) {
list_move_tail(>obj_link, _in_list);
+ spin_unlock(>vma.lock);
+
ret = i915_vma_unbind(vma);
- if (ret)
- break;
+
+ spin_lock(>vma.lock);
}
- list_splice(_in_list, >vma_list);
+ list_splice(_in_list, >vma.list);
+ spin_unlock(>vma.lock);
return ret;
}
@@ -3489,7 +3493,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
* reading an invalid PTE on older architectures.
*/
restart:
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (!drm_mm_node_allocated(>node))
continue;
@@ -3567,7 +3571,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
*/
}
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (!drm_mm_node_allocated(>node))
continue;
@@ -3577,7 +3581,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
}
}
- list_for_each_entry(vma, >vma_list, obj_link)
+ list_for_each_entry(vma, >vma.list, obj_link)
vma->node.color = cache_level;
i915_gem_object_set_cache_coherency(obj, cache_level);
obj->cache_dirty = true; /* Always invalidate stale cachelines */
@@ -4153,7 +4157,9 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
{
mutex_init(>mm.lock);
- INIT_LIST_HEAD(>vma_list);
+ spin_lock_init(>vma.lock);
+ INIT_LIST_HEAD(>vma.list);
+
INIT_LIST_HEAD(>lut_list);
INIT_LIST_HEAD(>batch_pool_link);
@@ -4319,14 +4325,13 @@ static void __i915_gem_free_objects(struct
drm_i915_private *i915,
mutex_lock(>drm.struct_mutex);
GEM_BUG_ON(i915_gem_object_is_active(obj));
- list_for_each_entry_safe(vma, vn,
->vma_list, obj_link) {
+ list_for_each_entry_safe(vma, vn, >vma.list,
[Intel-gfx] [PATCH 34/34] drm/i915: Replace global_seqno with a hangcheck heartbeat seqno
To determine whether an engine has 'struck', we simply check whether or
not is still on the same seqno for several seconds. To keep this simple
mechanism intact over the loss of a global seqno, we can simply add a
new global heartbeat seqno instead. As we cannot know the sequence in
which requests will then be completed, we use a primitive random number
generator instead (with a cycle long enough to not matter over an
interval of a few thousand requests between hangcheck samples).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 ---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++--
drivers/gpu/drm/i915/intel_hangcheck.c | 6 +++---
drivers/gpu/drm/i915/intel_lrc.c| 19 +++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 19 -
6 files changed, 67 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c2aaf010c3d1..16a9384de478 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1297,7 +1297,7 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
with_intel_runtime_pm(dev_priv, wakeref) {
for_each_engine(engine, dev_priv, id) {
acthd[id] = intel_engine_get_active_head(engine);
- seqno[id] = intel_engine_get_seqno(engine);
+ seqno[id] = intel_engine_get_hangcheck_seqno(engine);
}
intel_engine_get_instdone(dev_priv->engine[RCS], );
@@ -1317,8 +1317,9 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
for_each_engine(engine, dev_priv, id) {
seq_printf(m, "%s:\n", engine->name);
seq_printf(m, "\tseqno = %x [current %x, last %x], %dms ago\n",
- engine->hangcheck.seqno, seqno[id],
- intel_engine_last_submit(engine),
+ engine->hangcheck.last_seqno,
+ seqno[id],
+ engine->hangcheck.next_seqno,
jiffies_to_msecs(jiffies -
engine->hangcheck.action_timestamp));
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1d9157bf96ae..f631ad23a702 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1439,10 +1439,11 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (i915_terminally_wedged(>i915->gpu_error))
drm_printf(m, "*** WEDGED ***\n");
- drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n",
+ drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x/%x [%d ms]\n",
intel_engine_get_seqno(engine),
intel_engine_last_submit(engine),
- engine->hangcheck.seqno,
+ engine->hangcheck.last_seqno,
+ engine->hangcheck.next_seqno,
jiffies_to_msecs(jiffies -
engine->hangcheck.action_timestamp));
drm_printf(m, "\tReset count: %d (global %d)\n",
i915_reset_engine_count(error, engine),
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c
b/drivers/gpu/drm/i915/intel_hangcheck.c
index a219c796e56d..e04b2560369e 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -133,21 +133,21 @@ static void hangcheck_load_sample(struct intel_engine_cs
*engine,
struct hangcheck *hc)
{
hc->acthd = intel_engine_get_active_head(engine);
- hc->seqno = intel_engine_get_seqno(engine);
+ hc->seqno = intel_engine_get_hangcheck_seqno(engine);
}
static void hangcheck_store_sample(struct intel_engine_cs *engine,
const struct hangcheck *hc)
{
engine->hangcheck.acthd = hc->acthd;
- engine->hangcheck.seqno = hc->seqno;
+ engine->hangcheck.last_seqno = hc->seqno;
}
static enum intel_engine_hangcheck_action
hangcheck_get_action(struct intel_engine_cs *engine,
const struct hangcheck *hc)
{
- if (engine->hangcheck.seqno != hc->seqno)
+ if (engine->hangcheck.last_seqno != hc->seqno)
return ENGINE_ACTIVE_SEQNO;
if (intel_engine_is_idle(engine))
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b59cfec1d5d4..2864a9f542aa 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -178,6 +178,12 @@ static inline u32 intel_hws_seqno_address(struct
intel_engine_cs *engine)
I915_GEM_HWS_INDEX_ADDR);
}
+static inline u32 intel_hws_hangcheck_address(struct intel_engine_cs *engine)
+{
+ return (i915_ggtt_offset(engine->status_page.vma)
[Intel-gfx] [PATCH 28/34] drm/i915: Replace global breadcrumbs with per-context interrupt tracking
A few years ago, see commit 688e6c725816 ("drm/i915: Slaughter the
thundering i915_wait_request herd"), the issue of handling multiple
clients waiting in parallel was brought to our attention. The
requirement was that every client should be woken immediately upon its
request being signaled, without incurring any cpu overhead.
To handle certain fragility of our hw meant that we could not do a
simple check inside the irq handler (some generations required almost
unbounded delays before we could be sure of seqno coherency) and so
request completion checking required delegation.
Before commit 688e6c725816, the solution was simple. Every client waking
on a request would be woken on every interrupt and each would do a
heavyweight check to see if their request was complete. Commit
688e6c725816 introduced an rbtree so that only the earliest waiter on
the global timeline would woken, and would wake the next and so on.
(Along with various complications to handle requests being reordered
along the global timeline, and also a requirement for kthread to provide
a delegate for fence signaling that had no process context.)
The global rbtree depends on knowing the execution timeline (and global
seqno). Without knowing that order, we must instead check all contexts
queued to the HW to see which may have advanced. We trim that list by
only checking queued contexts that are being waited on, but still we
keep a list of all active contexts and their active signalers that we
inspect from inside the irq handler. By moving the waiters onto the fence
signal list, we can combine the client wakeup with the dma_fence
signaling (a dramatic reduction in complexity, but does require the HW
being coherent, the seqno must be visible from the cpu before the
interrupt is raised - we keep a timer backup just in case).
Having previously fixed all the issues with irq-seqno serialisation (by
inserting delays onto the GPU after each request instead of random delays
on the CPU after each interrupt), we can rely on the seqno state to
perfom direct wakeups from the interrupt handler. This allows us to
preserve our single context switch behaviour of the current routine,
with the only downside that we lose the RT priority sorting of wakeups.
In general, direct wakeup latency of multiple clients is about the same
(about 10% better in most cases) with a reduction in total CPU time spent
in the waiter (about 20-50% depending on gen). Average herd behaviour is
improved, but at the cost of not delegating wakeups on task_prio.
References: 688e6c725816 ("drm/i915: Slaughter the thundering i915_wait_request
herd")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 28 +-
drivers/gpu/drm/i915/i915_gem_context.h | 5 +
drivers/gpu/drm/i915/i915_gpu_error.c | 73 --
drivers/gpu/drm/i915/i915_gpu_error.h | 8 -
drivers/gpu/drm/i915/i915_irq.c | 87 +-
drivers/gpu/drm/i915/i915_request.c | 128 +--
drivers/gpu/drm/i915/i915_request.h | 22 +-
drivers/gpu/drm/i915/i915_reset.c | 13 +-
drivers/gpu/drm/i915/intel_breadcrumbs.c | 797 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 34 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 95 +--
.../drm/i915/selftests/i915_mock_selftests.h | 1 -
drivers/gpu/drm/i915/selftests/i915_request.c | 398 +
drivers/gpu/drm/i915/selftests/igt_spinner.c | 5 -
.../drm/i915/selftests/intel_breadcrumbs.c| 470 ---
.../gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/selftests/lib_sw_fence.c | 54 ++
drivers/gpu/drm/i915/selftests/lib_sw_fence.h | 3 +
drivers/gpu/drm/i915/selftests/mock_engine.c | 16 +-
drivers/gpu/drm/i915/selftests/mock_engine.h | 6 -
21 files changed, 774 insertions(+), 1477 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2a6e4044f25b..d7764e62e9b4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1315,29 +1315,16 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
for_each_engine(engine, dev_priv, id) {
- struct intel_breadcrumbs *b = >breadcrumbs;
- struct rb_node *rb;
-
seq_printf(m, "%s:\n", engine->name);
seq_printf(m, "\tseqno = %x [current %x, last %x], %dms ago\n",
engine->hangcheck.seqno, seqno[id],
intel_engine_last_submit(engine),
jiffies_to_msecs(jiffies -
engine->hangcheck.action_timestamp));
- seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
-
[Intel-gfx] [PATCH 27/34] drm/i915: Remove the intel_engine_notify tracepoint
The global seqno is defunct and so we have no meaningful indicator of
forward progress for an engine. You need to listen to the request
signaling tracepoints instead.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 2 --
drivers/gpu/drm/i915/i915_trace.h | 25 -
2 files changed, 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5fd5080c4ccb..71d11dc2c235 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1209,8 +1209,6 @@ static void notify_ring(struct intel_engine_cs *engine)
wake_up_process(tsk);
rcu_read_unlock();
-
- trace_intel_engine_notify(engine, wait);
}
static void vlv_c0_read(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 33d90eca9cdd..cb5bc65d575d 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -750,31 +750,6 @@ trace_i915_request_out(struct i915_request *rq)
#endif
#endif
-TRACE_EVENT(intel_engine_notify,
- TP_PROTO(struct intel_engine_cs *engine, bool waiters),
- TP_ARGS(engine, waiters),
-
- TP_STRUCT__entry(
-__field(u32, dev)
-__field(u16, class)
-__field(u16, instance)
-__field(u32, seqno)
-__field(bool, waiters)
-),
-
- TP_fast_assign(
- __entry->dev = engine->i915->drm.primary->index;
- __entry->class = engine->uabi_class;
- __entry->instance = engine->instance;
- __entry->seqno = intel_engine_get_seqno(engine);
- __entry->waiters = waiters;
- ),
-
- TP_printk("dev=%u, engine=%u:%u, seqno=%u, waiters=%u",
- __entry->dev, __entry->class, __entry->instance,
- __entry->seqno, __entry->waiters)
-);
-
DEFINE_EVENT(i915_request, i915_request_retire,
TP_PROTO(struct i915_request *rq),
TP_ARGS(rq)
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/34] drm/i915/execlists: Mark up priority boost on preemption
Record the priority boost we giving to the preempted client or else we
may end up in a situation where the priority queue no longer matches the
request priority order and so we can end up in an infinite loop of
preempting the same pair of requests.
Fixes: e9eaf82d97a2 ("drm/i915: Priority boost for waiting clients")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c0a42afaf177..b74f25420683 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -302,6 +302,7 @@ static void __unwind_incomplete_requests(struct
intel_engine_cs *engine)
*/
if (!(prio & I915_PRIORITY_NEWCLIENT)) {
prio |= I915_PRIORITY_NEWCLIENT;
+ active->sched.attr.priority = prio;
list_move_tail(>sched.link,
i915_sched_lookup_priolist(engine, prio));
}
@@ -625,6 +626,9 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
int i;
priolist_for_each_request_consume(rq, rn, p, i) {
+ GEM_BUG_ON(last &&
+ need_preempt(engine, last, rq_prio(rq)));
+
/*
* Can we combine this request with the current port?
* It has to be the same context/ringbuffer and not
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 24/34] drm/i915: Track the context's seqno in its own timeline HWSP
Now that we have allocated ourselves a cacheline to store a breadcrumb,
we can emit a write from the GPU into the timeline's HWSP of the
per-context seqno as we complete each request. This drops the mirroring
of the per-engine HWSP and allows each context to operate independently.
We do not need to unwind the per-context timeline, and so requests are
always consistent with the timeline breadcrumb, greatly simplifying the
completion checks as we no longer need to be concerned about the
global_seqno changing mid check.
One complication though is that we have to be wary that the request may
outlive the HWSP and so avoid touching the potentially danging pointer
after we have retired the fence. We also have to guard our access of the
HWSP with RCU, the release of the obj->mm.pages should already be RCU-safe.
At this point, we are emitting both per-context and global seqno and
still using the single per-engine execution timeline for resolving
interrupts.
v2: s/fake_complete/mark_complete/
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 3 +-
drivers/gpu/drm/i915/i915_request.h | 30 +++
drivers/gpu/drm/i915/i915_reset.c| 1 +
drivers/gpu/drm/i915/i915_vma.h | 6 ++
drivers/gpu/drm/i915/intel_engine_cs.c | 7 +-
drivers/gpu/drm/i915/intel_lrc.c | 35 +---
drivers/gpu/drm/i915/intel_ringbuffer.c | 88 +++-
drivers/gpu/drm/i915/selftests/mock_engine.c | 20 -
9 files changed, 132 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 761714448ff3..4e0de22f0166 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2890,7 +2890,7 @@ i915_gem_find_active_request(struct intel_engine_cs
*engine)
*/
spin_lock_irqsave(>timeline.lock, flags);
list_for_each_entry(request, >timeline.requests, link) {
- if (__i915_request_completed(request, request->global_seqno))
+ if (i915_request_completed(request))
continue;
active = request;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index d61e86c6a1d1..bb2885f1dc1e 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -199,6 +199,7 @@ static void __retire_engine_request(struct intel_engine_cs
*engine,
spin_unlock(>timeline.lock);
spin_lock(>lock);
+ i915_request_mark_complete(rq);
if (!i915_request_signaled(rq))
dma_fence_signal_locked(>fence);
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
@@ -621,7 +622,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->ring = ce->ring;
rq->timeline = ce->ring->timeline;
GEM_BUG_ON(rq->timeline == >timeline);
- rq->hwsp_seqno = >status_page.addr[I915_GEM_HWS_INDEX];
+ rq->hwsp_seqno = rq->timeline->hwsp_seqno;
spin_lock_init(>lock);
dma_fence_init(>fence,
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index ade010fe6e26..96c586d6ff4d 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -289,6 +289,7 @@ long i915_request_wait(struct i915_request *rq,
static inline bool i915_request_signaled(const struct i915_request *rq)
{
+ /* The request may live longer than its HWSP, so check flags first! */
return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags);
}
@@ -340,32 +341,23 @@ static inline u32 hwsp_seqno(const struct i915_request
*rq)
*/
static inline bool i915_request_started(const struct i915_request *rq)
{
- u32 seqno;
-
- seqno = i915_request_global_seqno(rq);
- if (!seqno) /* not yet submitted to HW */
- return false;
+ if (i915_request_signaled(rq))
+ return true;
- return i915_seqno_passed(hwsp_seqno(rq), seqno - 1);
-}
-
-static inline bool
-__i915_request_completed(const struct i915_request *rq, u32 seqno)
-{
- GEM_BUG_ON(!seqno);
- return i915_seqno_passed(hwsp_seqno(rq), seqno) &&
- seqno == i915_request_global_seqno(rq);
+ return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno - 1);
}
static inline bool i915_request_completed(const struct i915_request *rq)
{
- u32 seqno;
+ if (i915_request_signaled(rq))
+ return true;
- seqno = i915_request_global_seqno(rq);
- if (!seqno)
- return false;
+ return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno);
+}
- return __i915_request_completed(rq, seqno);
+static inline void i915_request_mark_complete(struct i915_request *rq)
+{
+ rq->hwsp_seqno = (u32 *)>fence.seqno; /* decouple from HWSP */
}
void
[Intel-gfx] [PATCH 30/34] drm/i915: Keep timeline HWSP allocated until the system is idle
In preparation for enabling HW semaphores, we need to keep in flight
timeline HWSP alive until the entire system is idle, as any other
timeline active on the GPU may still refer back to the already retired
timeline. We both have to delay recycling available cachelines and
unpinning old HWSP until the next idle point (i.e. on parking).
That we have to keep the HWSP alive for external references on HW raises
an interesting conundrum. On a busy system, we may never see a global
idle point, essentially meaning the resource will be leaking until we
are forced to sleep. What we need is a set of RCU primitives for the GPU!
This should also help mitigate the resource starvation issues
promulgating from keeping all logical state pinned until idle (instead
of as currently handled until the next context switch).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_request.c | 34 ---
drivers/gpu/drm/i915/i915_timeline.c | 127 ---
drivers/gpu/drm/i915/i915_timeline.h | 1 +
4 files changed, 133 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5577e0e1034f..7ca701cf9086 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1981,7 +1981,9 @@ struct drm_i915_private {
/* Pack multiple timelines' seqnos into the same page */
spinlock_t hwsp_lock;
+ struct list_head hwsp_pin_list;
struct list_head hwsp_free_list;
+ struct list_head hwsp_dead_list;
} timelines;
struct list_head active_rings;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index cca437ac8a7e..099c6f994b99 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -331,12 +331,6 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
-static u32 timeline_get_seqno(struct i915_timeline *tl)
-{
- tl->seqno += tl->has_initial_breadcrumb;
- return ++tl->seqno;
-}
-
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -538,8 +532,10 @@ struct i915_request *
i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context
*ctx)
{
struct drm_i915_private *i915 = engine->i915;
- struct i915_request *rq;
struct intel_context *ce;
+ struct i915_timeline *tl;
+ struct i915_request *rq;
+ u32 seqno;
int ret;
lockdep_assert_held(>drm.struct_mutex);
@@ -614,7 +610,15 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
}
}
- rq->rcustate = get_state_synchronize_rcu();
+ tl = ce->ring->timeline;
+ GEM_BUG_ON(tl == >timeline);
+ ret = i915_timeline_get_seqno(tl, );
+ if (ret)
+ goto err_free;
+
+ spin_lock_init(>lock);
+ dma_fence_init(>fence, _fence_ops, >lock,
+ tl->fence_context, seqno);
INIT_LIST_HEAD(>active_list);
rq->i915 = i915;
@@ -622,16 +626,9 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->gem_context = ctx;
rq->hw_context = ce;
rq->ring = ce->ring;
- rq->timeline = ce->ring->timeline;
- GEM_BUG_ON(rq->timeline == >timeline);
- rq->hwsp_seqno = rq->timeline->hwsp_seqno;
-
- spin_lock_init(>lock);
- dma_fence_init(>fence,
- _fence_ops,
- >lock,
- rq->timeline->fence_context,
- timeline_get_seqno(rq->timeline));
+ rq->timeline = tl;
+ rq->hwsp_seqno = tl->hwsp_seqno;
+ rq->rcustate = get_state_synchronize_rcu();
/* We bump the ref for the fence chain */
i915_sw_fence_init(_request_get(rq)->submit, submit_notify);
@@ -688,6 +685,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
GEM_BUG_ON(!list_empty(>sched.signalers_list));
GEM_BUG_ON(!list_empty(>sched.waiters_list));
+err_free:
kmem_cache_free(i915->requests, rq);
err_unreserve:
unreserve_gt(i915);
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 7bc9164733bc..a0bbc993048b 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -11,8 +11,11 @@
struct i915_timeline_hwsp {
struct i915_vma *vma;
+ struct list_head pin_link;
struct list_head free_link;
+ struct list_head dead_link;
u64 free_bitmap;
+ u64 dead_bitmap;
};
static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
@@ -33,8 +36,7 @@ static struct i915_vma *__hwsp_alloc(struct
[Intel-gfx] [PATCH 33/34] drm/i915: Prioritise non-busywait semaphore workloads
We don't want to busywait on the GPU if we have other work to do. If we
give non-busywaiting workloads higher (initial) priority than workloads
that require a busywait, we will prioritise work that is ready to run
immediately.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 3 +++
drivers/gpu/drm/i915/i915_scheduler.h | 7 ---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index b7554a399c39..815386581f1a 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1096,6 +1096,9 @@ void i915_request_add(struct i915_request *request)
if (engine->schedule) {
struct i915_sched_attr attr = request->gem_context->sched;
+ if (!request->sched.semaphore)
+ attr.priority |= I915_PRIORITY_NOSEMAPHORE;
+
/*
* Boost priorities to new clients (new request flows).
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index d764cf10536f..7f194a8db785 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -24,14 +24,15 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 2
+#define I915_USER_PRIORITY_SHIFT 3
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-#define I915_PRIORITY_WAIT ((u8)BIT(0))
-#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_WAIT ((u8)BIT(0))
+#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2))
struct i915_sched_attr {
/**
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 32/34] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
Having introduced per-context seqno, we know have a means to identity
progress across the system without feel of rollback as befell the
global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
advance of submission safe in the knowledge that our target seqno and
address is stable.
However, since we are telling the GPU to busy-spin on the target address
until it matches the signaling seqno, we only want to do so when we are
sure that busy-spin will be completed quickly. To achieve this we only
submit the request to HW once the signaler is itself executing (modulo
preemption causing us to wait longer), and we only do so for default and
above priority requests (so that idle priority tasks never themselves
hog the GPU waiting for others).
But what AB-BA deadlocks? If you remove B, there can be no deadlock...
The issue is that with a deep ELSP queue, we can queue up a pair of
AB-BA on different engines, thus forming a classic mutual exclusion
deadlock. We side-step that issue by restricting the queue depth to
avoid having multiple semaphores in flight and so we only ever take one
set of locks at a time.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 139 +-
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_scheduler.c | 1 +
drivers/gpu/drm/i915/i915_scheduler.h | 1 +
drivers/gpu/drm/i915/i915_sw_fence.c | 4 +-
drivers/gpu/drm/i915/i915_sw_fence.h | 3 +
drivers/gpu/drm/i915/intel_gpu_commands.h | 5 +
drivers/gpu/drm/i915/intel_lrc.c | 13 +-
8 files changed, 163 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 099c6f994b99..b7554a399c39 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -22,8 +22,9 @@
*
*/
-#include
#include
+#include
+#include
#include
#include
#include
@@ -331,6 +332,66 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
+struct execute_cb {
+ struct list_head link;
+ struct irq_work work;
+ struct i915_sw_fence *fence;
+};
+
+static void irq_execute_cb(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ i915_sw_fence_complete(cb->fence);
+ kfree(cb);
+}
+
+static void __notify_execute_cb(struct i915_request *rq)
+{
+ struct execute_cb *cb;
+
+ lockdep_assert_held(>lock);
+
+ if (list_empty(>execute_cb))
+ return;
+
+ list_for_each_entry(cb, >execute_cb, link)
+ irq_work_queue(>work);
+
+ INIT_LIST_HEAD(>execute_cb);
+}
+
+static int
+i915_request_await_execution(struct i915_request *rq,
+struct i915_request *signal,
+gfp_t gfp)
+{
+ struct execute_cb *cb;
+ unsigned long flags;
+
+ if (test_bit(I915_FENCE_FLAG_ACTIVE, >fence.flags))
+ return 0;
+
+ cb = kmalloc(sizeof(*cb), gfp);
+ if (!cb)
+ return -ENOMEM;
+
+ cb->fence = >submit;
+ i915_sw_fence_await(cb->fence);
+ init_irq_work(>work, irq_execute_cb);
+
+ spin_lock_irqsave(>lock, flags);
+ if (test_bit(I915_FENCE_FLAG_ACTIVE, >fence.flags)) {
+ i915_sw_fence_complete(cb->fence);
+ kfree(cb);
+ } else {
+ list_add_tail(>link, >execute_cb);
+ }
+ spin_unlock_irqrestore(>lock, flags);
+
+ return 0;
+}
+
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -377,6 +438,7 @@ void __i915_request_submit(struct i915_request *request)
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags) &&
!intel_engine_enable_signaling(request))
intel_engine_queue_breadcrumbs(engine);
+ __notify_execute_cb(request);
spin_unlock(>lock);
engine->emit_fini_breadcrumb(request,
@@ -621,6 +683,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
tl->fence_context, seqno);
INIT_LIST_HEAD(>active_list);
+ INIT_LIST_HEAD(>execute_cb);
rq->i915 = i915;
rq->engine = engine;
rq->gem_context = ctx;
@@ -693,6 +756,77 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
return ERR_PTR(ret);
}
+static int
+emit_semaphore_wait(struct i915_request *to,
+ struct i915_request *from,
+ gfp_t gfp)
+{
+ u32 *cs;
+
+ GEM_BUG_ON(i915_timeline_is_global(from->timeline));
+ GEM_BUG_ON(!from->timeline->has_initial_breadcrumb);
+
+ /*
+* If we know our signaling request has started, we know that it
+* must, at least, have passed its initial breadcrumb and that its
+* seqno can only
[Intel-gfx] [PATCH 10/34] drm/i915: Remove GPU reset dependence on struct_mutex
Now that the submission backends are controlled via their own spinlocks,
with a wave of a magic wand we can lift the struct_mutex requirement
around GPU reset. That is we allow the submission frontend (userspace)
to keep on submitting while we process the GPU reset as we can suspend
the backend independently.
The major change is around the backoff/handoff strategy for performing
the reset. With no mutex deadlock, we no longer have to coordinate with
any waiter, and just perform the reset immediately.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 38 +-
drivers/gpu/drm/i915/i915_drv.h | 5 -
drivers/gpu/drm/i915/i915_gem.c | 18 +-
drivers/gpu/drm/i915/i915_gem_fence_reg.h | 1 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 104 +++--
drivers/gpu/drm/i915/i915_gpu_error.h | 28 +-
drivers/gpu/drm/i915/i915_request.c | 47 ---
drivers/gpu/drm/i915/i915_reset.c | 397 --
drivers/gpu/drm/i915/i915_reset.h | 3 +
drivers/gpu/drm/i915/intel_engine_cs.c| 6 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 5 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 28 +-
drivers/gpu/drm/i915/intel_lrc.c | 92 ++--
drivers/gpu/drm/i915/intel_overlay.c | 2 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 91 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 17 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 57 +--
.../drm/i915/selftests/intel_workarounds.c| 3 -
.../gpu/drm/i915/selftests/mock_gem_device.c | 4 +-
20 files changed, 393 insertions(+), 554 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 24d6d4ce14ef..3ec369980d40 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1284,8 +1284,6 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
seq_puts(m, "Wedged\n");
if (test_bit(I915_RESET_BACKOFF, _priv->gpu_error.flags))
seq_puts(m, "Reset in progress: struct_mutex backoff\n");
- if (test_bit(I915_RESET_HANDOFF, _priv->gpu_error.flags))
- seq_puts(m, "Reset in progress: reset handoff to waiter\n");
if (waitqueue_active(_priv->gpu_error.wait_queue))
seq_puts(m, "Waiter holding struct mutex\n");
if (waitqueue_active(_priv->gpu_error.reset_queue))
@@ -1321,15 +1319,15 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
struct rb_node *rb;
seq_printf(m, "%s:\n", engine->name);
- seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
+ seq_printf(m, "\tseqno = %x [current %x, last %x], %dms ago\n",
engine->hangcheck.seqno, seqno[id],
- intel_engine_last_submit(engine));
- seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s,
wedged? %s\n",
+ intel_engine_last_submit(engine),
+ jiffies_to_msecs(jiffies -
+
engine->hangcheck.action_timestamp));
+ seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
yesno(intel_engine_has_waiter(engine)),
yesno(test_bit(engine->id,
-
_priv->gpu_error.missed_irq_rings)),
- yesno(engine->hangcheck.stalled),
- yesno(engine->hangcheck.wedged));
+
_priv->gpu_error.missed_irq_rings)));
spin_lock_irq(>rb_lock);
for (rb = rb_first(>waiters); rb; rb = rb_next(rb)) {
@@ -1343,11 +1341,6 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
(long long)engine->hangcheck.acthd,
(long long)acthd[id]);
- seq_printf(m, "\taction = %s(%d) %d ms ago\n",
- hangcheck_action_to_str(engine->hangcheck.action),
- engine->hangcheck.action,
- jiffies_to_msecs(jiffies -
-
engine->hangcheck.action_timestamp));
if (engine->id == RCS) {
seq_puts(m, "\tinstdone read =\n");
@@ -3886,8 +3879,6 @@ static int
i915_wedged_set(void *data, u64 val)
{
struct drm_i915_private *i915 = data;
- struct intel_engine_cs *engine;
- unsigned int tmp;
/*
* There is no safeguard against this debugfs entry colliding
@@ -3900,18 +3891,8 @@ i915_wedged_set(void *data, u64 val)
if (i915_reset_backoff(>gpu_error))
return -EAGAIN;
-
[Intel-gfx] [PATCH 22/34] drm/i915: Allocate a status page for each timeline
Allocate a page for use as a status page by a group of timelines, as we
only need a dword of storage for each (rounded up to the cacheline for
safety) we can pack multiple timelines into the same page. Each timeline
will then be able to track its own HW seqno.
v2: Reuse the common per-engine HWSP for the solitary ringbuffer
timeline, so that we do not have to emit (using per-gen specialised
vfuncs) the breadcrumb into the distinct timeline HWSP and instead can
keep on using the common MI_STORE_DWORD_INDEX. However, to maintain the
sleight-of-hand for the global/per-context seqno switchover, we will
store both temporarily (and so use a custom offset for the shared timeline
HWSP until the switch over).
v3: Keep things simple and allocate a page for each timeline, page
sharing comes next.
v4: I was caught repeating the same MI_STORE_DWORD_IMM over and over
again in selftests.
v5: And caught red handed copying create timeline + check.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_timeline.c | 121 ++-
drivers/gpu/drm/i915/i915_timeline.h | 21 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 64 ++--
drivers/gpu/drm/i915/intel_lrc.c | 22 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_mock_selftests.h | 2 +-
.../gpu/drm/i915/selftests/i915_timeline.c| 326 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 14 +-
10 files changed, 535 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 84550f17d3df..8d5792311a8f 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -9,28 +9,78 @@
#include "i915_timeline.h"
#include "i915_syncmap.h"
-void i915_timeline_init(struct drm_i915_private *i915,
- struct i915_timeline *timeline,
- const char *name)
+static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
+
+ vma = i915_vma_instance(obj, >ggtt.vm, NULL);
+ if (IS_ERR(vma))
+ i915_gem_object_put(obj);
+
+ return vma;
+}
+
+static int hwsp_alloc(struct i915_timeline *timeline)
+{
+ struct i915_vma *vma;
+
+ vma = __hwsp_alloc(timeline->i915);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ timeline->hwsp_ggtt = vma;
+ timeline->hwsp_offset = 0;
+
+ return 0;
+}
+
+int i915_timeline_init(struct drm_i915_private *i915,
+ struct i915_timeline *timeline,
+ const char *name,
+ struct i915_vma *global_hwsp)
{
struct i915_gt_timelines *gt = >gt.timelines;
+ void *vaddr;
+ int err;
/*
* Ideally we want a set of engines on a single leaf as we expect
* to mostly be tracking synchronisation between engines. It is not
* a huge issue if this is not the case, but we may want to mitigate
* any page crossing penalties if they become an issue.
+*
+* Called during early_init before we know how many engines there are.
*/
BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
timeline->i915 = i915;
timeline->name = name;
+ timeline->pin_count = 0;
+
+ if (global_hwsp) {
+ timeline->hwsp_ggtt = i915_vma_get(global_hwsp);
+ timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR;
+ } else {
+ err = hwsp_alloc(timeline);
+ if (err)
+ return err;
+ }
- mutex_lock(>mutex);
- list_add(>link, >list);
- mutex_unlock(>mutex);
+ vaddr = i915_gem_object_pin_map(timeline->hwsp_ggtt->obj, I915_MAP_WB);
+ if (IS_ERR(vaddr)) {
+ i915_vma_put(timeline->hwsp_ggtt);
+ return PTR_ERR(vaddr);
+ }
- /* Called during early_init before we know how many engines there are */
+ timeline->hwsp_seqno =
+ memset(vaddr + timeline->hwsp_offset, 0, CACHELINE_BYTES);
timeline->fence_context = dma_fence_context_alloc(1);
@@ -40,6 +90,12 @@ void i915_timeline_init(struct drm_i915_private *i915,
INIT_LIST_HEAD(>requests);
i915_syncmap_init(>sync);
+
+ mutex_lock(>mutex);
+ list_add(>link, >list);
+ mutex_unlock(>mutex);
+
+ return 0;
}
void i915_timelines_init(struct drm_i915_private *i915)
@@ -85,6 +141,7 @@ void i915_timeline_fini(struct i915_timeline *timeline)
{
struct
[Intel-gfx] [PATCH 29/34] drm/i915: Drop fake breadcrumb irq
Missed breadcrumb detection is defunct due to the tight coupling with
dma_fence signaling and the myriad ways we may signal fences from
everywhere but from an interrupt, i.e. we frequently signal a fence
before we even see its interrupt. This means that even if we miss an
interrupt for a fence, it still is signaled before our breadcrumb
hangcheck fires, so simplify the breadcrumb hangchecking by moving it
into the GPU hangcheck and forgo fake interrupts.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 93 ---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 -
drivers/gpu/drm/i915/i915_gpu_error.h | 5 -
drivers/gpu/drm/i915/intel_breadcrumbs.c | 147 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 2 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 -
.../gpu/drm/i915/selftests/igt_live_test.c| 7 -
7 files changed, 5 insertions(+), 256 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d7764e62e9b4..c2aaf010c3d1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1321,9 +1321,6 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
intel_engine_last_submit(engine),
jiffies_to_msecs(jiffies -
engine->hangcheck.action_timestamp));
- seq_printf(m, "\tfake irq active? %s\n",
- yesno(test_bit(engine->id,
-
_priv->gpu_error.missed_irq_rings)));
seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
(long long)engine->hangcheck.acthd,
@@ -3874,94 +3871,6 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
-static int
-fault_irq_set(struct drm_i915_private *i915,
- unsigned long *irq,
- unsigned long val)
-{
- int err;
-
- err = mutex_lock_interruptible(>drm.struct_mutex);
- if (err)
- return err;
-
- err = i915_gem_wait_for_idle(i915,
-I915_WAIT_LOCKED |
-I915_WAIT_INTERRUPTIBLE,
-MAX_SCHEDULE_TIMEOUT);
- if (err)
- goto err_unlock;
-
- *irq = val;
- mutex_unlock(>drm.struct_mutex);
-
- /* Flush idle worker to disarm irq */
- drain_delayed_work(>gt.idle_work);
-
- return 0;
-
-err_unlock:
- mutex_unlock(>drm.struct_mutex);
- return err;
-}
-
-static int
-i915_ring_missed_irq_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
-
- *val = dev_priv->gpu_error.missed_irq_rings;
- return 0;
-}
-
-static int
-i915_ring_missed_irq_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- return fault_irq_set(i915, >gpu_error.missed_irq_rings, val);
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
- i915_ring_missed_irq_get, i915_ring_missed_irq_set,
- "0x%08llx\n");
-
-static int
-i915_ring_test_irq_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
-
- *val = dev_priv->gpu_error.test_irq_rings;
-
- return 0;
-}
-
-static int
-i915_ring_test_irq_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- /* GuC keeps the user interrupt permanently enabled for submission */
- if (USES_GUC_SUBMISSION(i915))
- return -ENODEV;
-
- /*
-* From icl, we can no longer individually mask interrupt generation
-* from each engine.
-*/
- if (INTEL_GEN(i915) >= 11)
- return -ENODEV;
-
- val &= INTEL_INFO(i915)->ring_mask;
- DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
-
- return fault_irq_set(i915, >gpu_error.test_irq_rings, val);
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
- i915_ring_test_irq_get, i915_ring_test_irq_set,
- "0x%08llx\n");
-
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIREBIT(2)
@@ -4724,8 +4633,6 @@ static const struct i915_debugfs_files {
} i915_debugfs_files[] = {
{"i915_wedged", _wedged_fops},
{"i915_cache_sharing", _cache_sharing_fops},
- {"i915_ring_missed_irq", _ring_missed_irq_fops},
- {"i915_ring_test_irq", _ring_test_irq_fops},
{"i915_gem_drop_caches", _drop_caches_fops},
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
{"i915_error_state", _error_state_fops},
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 825572127029..0584c8dfa6ae 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++
[Intel-gfx] [PATCH 09/34] drm/i915/guc: Disable global reset
The guc (and huc) currently inexcruitably depend on struct_mutex for
device reinitialisation from inside the reset, and indeed taking any
mutex here is verboten (as we must be able to reset from underneath any
of our mutexes). That makes recovering the guc unviable without, for
example, reserving contiguous vma space and pages for it to use.
The plan to re-enable global reset for the GuC centres around reusing the
WOPM reserved space at the top of the aperture (that we know we can
populate a contiguous range large enough to dma xfer the fw image).
In the meantime, hopefully no one even notices as the device-reset is
only used as a backup to the per-engine resets for handling GPU hangs.
Signed-off-by: Chris Wilson
Acked-by: Mika Kuoppala
Acked-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_reset.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index b9d0ea70361c..2961c21d9420 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -590,6 +590,9 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned
int engine_mask)
bool intel_has_gpu_reset(struct drm_i915_private *i915)
{
+ if (USES_GUC(i915))
+ return false;
+
return intel_get_gpu_reset(i915);
}
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/34] drm/i915/selftests: Refactor common live_test framework
Before adding yet another copy of struct live_test and its handler,
refactor the existing code into a common framework for live selftests.
For many live selftests, we want to know if the GPU hung or otherwise
misbehaved during the execution of the test (beyond any infraction in
the behaviour under test), live_test provides this by comparing the
GPU state before and after, alerting if it unexpectedly changed (e.g.
the reset counter changed). It also ensures that the GPU is idle before
and after the test, so that residual code running on the GPU is flushed
before testing.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/selftests/i915_gem_context.c | 103 +++---
drivers/gpu/drm/i915/selftests/i915_request.c | 86 +++
.../gpu/drm/i915/selftests/igt_live_test.c| 85 +++
.../gpu/drm/i915/selftests/igt_live_test.h| 35 ++
5 files changed, 147 insertions(+), 163 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/igt_live_test.c
create mode 100644 drivers/gpu/drm/i915/selftests/igt_live_test.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 65ed00db..f050759686ca 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -167,6 +167,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/i915_random.o \
selftests/i915_selftest.o \
selftests/igt_flush_test.o \
+ selftests/igt_live_test.o \
selftests/igt_reset.o \
selftests/igt_spinner.o
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 4cba50679607..e2c1f0bc2abe 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -27,6 +27,7 @@
#include "../i915_selftest.h"
#include "i915_random.h"
#include "igt_flush_test.h"
+#include "igt_live_test.h"
#include "mock_drm.h"
#include "mock_gem_device.h"
@@ -34,84 +35,6 @@
#define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))
-struct live_test {
- struct drm_i915_private *i915;
- const char *func;
- const char *name;
-
- unsigned int reset_global;
- unsigned int reset_engine[I915_NUM_ENGINES];
-};
-
-static int begin_live_test(struct live_test *t,
- struct drm_i915_private *i915,
- const char *func,
- const char *name)
-{
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- int err;
-
- t->i915 = i915;
- t->func = func;
- t->name = name;
-
- err = i915_gem_wait_for_idle(i915,
-I915_WAIT_LOCKED,
-MAX_SCHEDULE_TIMEOUT);
- if (err) {
- pr_err("%s(%s): failed to idle before, with err=%d!",
- func, name, err);
- return err;
- }
-
- i915->gpu_error.missed_irq_rings = 0;
- t->reset_global = i915_reset_count(>gpu_error);
-
- for_each_engine(engine, i915, id)
- t->reset_engine[id] =
- i915_reset_engine_count(>gpu_error, engine);
-
- return 0;
-}
-
-static int end_live_test(struct live_test *t)
-{
- struct drm_i915_private *i915 = t->i915;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- if (igt_flush_test(i915, I915_WAIT_LOCKED))
- return -EIO;
-
- if (t->reset_global != i915_reset_count(>gpu_error)) {
- pr_err("%s(%s): GPU was reset %d times!\n",
- t->func, t->name,
- i915_reset_count(>gpu_error) - t->reset_global);
- return -EIO;
- }
-
- for_each_engine(engine, i915, id) {
- if (t->reset_engine[id] ==
- i915_reset_engine_count(>gpu_error, engine))
- continue;
-
- pr_err("%s(%s): engine '%s' was reset %d times!\n",
- t->func, t->name, engine->name,
- i915_reset_engine_count(>gpu_error, engine) -
- t->reset_engine[id]);
- return -EIO;
- }
-
- if (i915->gpu_error.missed_irq_rings) {
- pr_err("%s(%s): Missed interrupts on engines %lx\n",
- t->func, t->name, i915->gpu_error.missed_irq_rings);
- return -EIO;
- }
-
- return 0;
-}
-
static int live_nop_switch(void *arg)
{
const unsigned int nctx = 1024;
@@ -120,8 +43,8 @@ static int live_nop_switch(void *arg)
struct i915_gem_context **ctx;
enum intel_engine_id id;
intel_wakeref_t wakeref;
+ struct igt_live_test t;
struct drm_file *file;
- struct live_test t;
unsigned long n;
int err = -ENODEV;
@@ -185,7 +108,7 @@ static int live_nop_switch(void *arg)
[Intel-gfx] [PATCH 08/34] drm/i915: Make all GPU resets atomic
In preparation for the next few commits, make resetting the GPU atomic.
Currently, we have prepared gen6+ for atomic resetting of individual
engines, but now there is a requirement to perform the whole device
level reset (just the register poking) from inside an atomic context.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reset.c | 50 +--
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 342d9ee42601..b9d0ea70361c 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -144,14 +144,14 @@ static int i915_do_reset(struct drm_i915_private *i915,
/* Assert reset for at least 20 usec, and wait for acknowledgement. */
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
- usleep_range(50, 200);
- err = wait_for(i915_in_reset(pdev), 500);
+ udelay(50);
+ err = wait_for_atomic(i915_in_reset(pdev), 50);
/* Clear the reset request. */
pci_write_config_byte(pdev, I915_GDRST, 0);
- usleep_range(50, 200);
+ udelay(50);
if (!err)
- err = wait_for(!i915_in_reset(pdev), 500);
+ err = wait_for_atomic(!i915_in_reset(pdev), 50);
return err;
}
@@ -171,7 +171,7 @@ static int g33_do_reset(struct drm_i915_private *i915,
struct pci_dev *pdev = i915->drm.pdev;
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
- return wait_for(g4x_reset_complete(pdev), 500);
+ return wait_for_atomic(g4x_reset_complete(pdev), 50);
}
static int g4x_do_reset(struct drm_i915_private *dev_priv,
@@ -182,13 +182,13 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
int ret;
/* WaVcpClkGateDisableForMediaReset:ctg,elk */
- I915_WRITE(VDECCLK_GATE_D,
- I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
- POSTING_READ(VDECCLK_GATE_D);
+ I915_WRITE_FW(VDECCLK_GATE_D,
+ I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ_FW(VDECCLK_GATE_D);
pci_write_config_byte(pdev, I915_GDRST,
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
- ret = wait_for(g4x_reset_complete(pdev), 500);
+ ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
DRM_DEBUG_DRIVER("Wait for media reset failed\n");
goto out;
@@ -196,7 +196,7 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
pci_write_config_byte(pdev, I915_GDRST,
GRDOM_RENDER | GRDOM_RESET_ENABLE);
- ret = wait_for(g4x_reset_complete(pdev), 500);
+ ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
@@ -205,9 +205,9 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
out:
pci_write_config_byte(pdev, I915_GDRST, 0);
- I915_WRITE(VDECCLK_GATE_D,
- I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
- POSTING_READ(VDECCLK_GATE_D);
+ I915_WRITE_FW(VDECCLK_GATE_D,
+ I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ_FW(VDECCLK_GATE_D);
return ret;
}
@@ -218,27 +218,29 @@ static int ironlake_do_reset(struct drm_i915_private
*dev_priv,
{
int ret;
- I915_WRITE(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
- ret = intel_wait_for_register(dev_priv,
- ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
- 500);
+ I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ ILK_GRDOM_RESET_ENABLE, 0,
+ 5000, 0,
+ NULL);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
}
- I915_WRITE(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
- ret = intel_wait_for_register(dev_priv,
- ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
- 500);
+ I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ ILK_GRDOM_RESET_ENABLE, 0,
+ 5000, 0,
+ NULL);
if (ret) {
DRM_DEBUG_DRIVER("Wait for media reset failed\n");
goto out;
}
out:
- I915_WRITE(ILK_GDSR, 0);
- POSTING_READ(ILK_GDSR);
+
[Intel-gfx] HWSP for HW semaphores
I extended the HWSP implementation to consider the impact of using it for HW semaphores, one of the end goals of per-context seqno. That opens up an interesting problem in that we need to keep the HWSP around until all external GPU references to it are retired. For simplicity, this is until the GPU is next idle, but Tvrtko suggested the likelihood of that happening on a busy system is slight and those busy systems are also more likely to run into resource contentions issues as well. That was a can of worms I was hoping to ignore until later, as one of the simplifications for removing the global_seqno was that we could simply keep all resources pinned until idle, a full GC. With a full GC being forced if we ever starved. Far more graceful is that if we did a more incremental GC, and combined with the case of tracking external references we would end up with a read-copy-update mechanism... Anyway this series shows off HW semaphores for inter-engine synchronisation and should also extend easily to unordered work queuing unto the GuC. I need the fence primitives for the next (well, older!) series... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/34] drm/i915: Always allocate an object/vma for the HWSP
Currently we only allocate an object and vma if we are using a GGTT
virtual HWSP, and a plain struct page for a physical HWSP. For
convenience later on with global timelines, it will be useful to always
have the status page being tracked by a struct i915_vma. Make it so.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_engine_cs.c | 109 ++-
drivers/gpu/drm/i915/intel_guc_submission.c | 6 +
drivers/gpu/drm/i915/intel_lrc.c | 12 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 21 +++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +---
drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
6 files changed, 93 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index fc52737751e7..4b4b7358c482 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -506,27 +506,61 @@ void intel_engine_setup_common(struct intel_engine_cs
*engine)
static void cleanup_status_page(struct intel_engine_cs *engine)
{
+ struct i915_vma *vma;
+
/* Prevent writes into HWSP after returning the page to the system */
intel_engine_set_hwsp_writemask(engine, ~0u);
- if (HWS_NEEDS_PHYSICAL(engine->i915)) {
- void *addr = fetch_and_zero(>status_page.page_addr);
+ vma = fetch_and_zero(>status_page.vma);
+ if (!vma)
+ return;
- __free_page(virt_to_page(addr));
- }
+ if (!HWS_NEEDS_PHYSICAL(engine->i915))
+ i915_vma_unpin(vma);
+
+ i915_gem_object_unpin_map(vma->obj);
+ __i915_gem_object_release_unless_active(vma->obj);
+}
+
+static int pin_ggtt_status_page(struct intel_engine_cs *engine,
+ struct i915_vma *vma)
+{
+ unsigned int flags;
+
+ flags = PIN_GLOBAL;
+ if (!HAS_LLC(engine->i915))
+ /*
+* On g33, we cannot place HWS above 256MiB, so
+* restrict its pinning to the low mappable arena.
+* Though this restriction is not documented for
+* gen4, gen5, or byt, they also behave similarly
+* and hang if the HWS is placed at the top of the
+* GTT. To generalise, it appears that all !llc
+* platforms have issues with us placing the HWS
+* above the mappable region (even though we never
+* actually map it).
+*/
+ flags |= PIN_MAPPABLE;
+ else
+ flags |= PIN_HIGH;
- i915_vma_unpin_and_release(>status_page.vma,
- I915_VMA_RELEASE_MAP);
+ return i915_vma_pin(vma, 0, 0, flags);
}
static int init_status_page(struct intel_engine_cs *engine)
{
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- unsigned int flags;
void *vaddr;
int ret;
+ /*
+* Though the HWS register does support 36bit addresses, historically
+* we have had hangs and corruption reported due to wild writes if
+* the HWS is placed above 4G. We only allow objects to be allocated
+* in GFP_DMA32 for i965, and no earlier physical address users had
+* access to more than 4G.
+*/
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
if (IS_ERR(obj)) {
DRM_ERROR("Failed to allocate status page\n");
@@ -543,61 +577,30 @@ static int init_status_page(struct intel_engine_cs
*engine)
goto err;
}
- flags = PIN_GLOBAL;
- if (!HAS_LLC(engine->i915))
- /* On g33, we cannot place HWS above 256MiB, so
-* restrict its pinning to the low mappable arena.
-* Though this restriction is not documented for
-* gen4, gen5, or byt, they also behave similarly
-* and hang if the HWS is placed at the top of the
-* GTT. To generalise, it appears that all !llc
-* platforms have issues with us placing the HWS
-* above the mappable region (even though we never
-* actually map it).
-*/
- flags |= PIN_MAPPABLE;
- else
- flags |= PIN_HIGH;
- ret = i915_vma_pin(vma, 0, 0, flags);
- if (ret)
- goto err;
-
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
ret = PTR_ERR(vaddr);
- goto err_unpin;
+ goto err;
}
+ engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
engine->status_page.vma = vma;
- engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
- engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
+
+ if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
+ ret =
[Intel-gfx] [PATCH 03/34] drm/i915: Show all active engines on hangcheck
This turns out to be quite useful if one happens to be debugging
semaphore deadlocks.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_hangcheck.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c
b/drivers/gpu/drm/i915/intel_hangcheck.c
index 7dc11fcb13de..741441daae32 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -195,10 +195,6 @@ static void hangcheck_accumulate_sample(struct
intel_engine_cs *engine,
break;
case ENGINE_DEAD:
- if (GEM_SHOW_DEBUG()) {
- struct drm_printer p = drm_debug_printer("hangcheck");
- intel_engine_dump(engine, , "%s\n", engine->name);
- }
break;
default:
@@ -285,6 +281,17 @@ static void i915_hangcheck_elapsed(struct work_struct
*work)
wedged |= intel_engine_flag(engine);
}
+ if (GEM_SHOW_DEBUG() && (hung | stuck)) {
+ struct drm_printer p = drm_debug_printer("hangcheck");
+
+ for_each_engine(engine, dev_priv, id) {
+ if (intel_engine_is_idle(engine))
+ continue;
+
+ intel_engine_dump(engine, , "%s\n", engine->name);
+ }
+ }
+
if (wedged) {
dev_err(dev_priv->drm.dev,
"GPU recovery timed out,"
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 21/34] drm/i915: Enlarge vma->pin_count
Previously we only accommodated having a vma pinned by a small number of
users, with the maximum being pinned for use by the display engine. As
such, we used a small bitfield only large enough to allow the vma to
be pinned twice (for back/front buffers) in each scanout plane. Keeping
the maximum permissible pin_count small allows us to quickly catch a
potential leak. However, as we want to split a 4096B page into 64
different cachelines and pin each cacheline for use by a different
timeline, we will exceed the current maximum permissible vma->pin_count
and so time has come to enlarge it.
Whilst we are here, try to pull together the similar bits:
Address/layout specification:
- bias, mappable, zone_4g: address limit specifiers
- fixed: address override, limits still apply though
- high: not strictly an address limit, but an address direction to search
Search controls:
- nonblock, nonfault, noevict
v2: Rewrite the guideline comment on bit consumption.
Signed-off-by: Chris Wilson
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 26 -
drivers/gpu/drm/i915/i915_vma.h | 45 +++--
2 files changed, 42 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index bd679c8c56dd..03ade71b8d9a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -642,19 +642,19 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
/* Flags used by pin/bind */
#define PIN_NONBLOCK BIT_ULL(0)
-#define PIN_MAPPABLE BIT_ULL(1)
-#define PIN_ZONE_4GBIT_ULL(2)
-#define PIN_NONFAULT BIT_ULL(3)
-#define PIN_NOEVICTBIT_ULL(4)
-
-#define PIN_MBZBIT_ULL(5) /* I915_VMA_PIN_OVERFLOW */
-#define PIN_GLOBAL BIT_ULL(6) /* I915_VMA_GLOBAL_BIND */
-#define PIN_USER BIT_ULL(7) /* I915_VMA_LOCAL_BIND */
-#define PIN_UPDATE BIT_ULL(8)
-
-#define PIN_HIGH BIT_ULL(9)
-#define PIN_OFFSET_BIASBIT_ULL(10)
-#define PIN_OFFSET_FIXED BIT_ULL(11)
+#define PIN_NONFAULT BIT_ULL(1)
+#define PIN_NOEVICTBIT_ULL(2)
+#define PIN_MAPPABLE BIT_ULL(3)
+#define PIN_ZONE_4GBIT_ULL(4)
+#define PIN_HIGH BIT_ULL(5)
+#define PIN_OFFSET_BIASBIT_ULL(6)
+#define PIN_OFFSET_FIXED BIT_ULL(7)
+
+#define PIN_MBZBIT_ULL(8) /* I915_VMA_PIN_OVERFLOW */
+#define PIN_GLOBAL BIT_ULL(9) /* I915_VMA_GLOBAL_BIND */
+#define PIN_USER BIT_ULL(10) /* I915_VMA_LOCAL_BIND */
+#define PIN_UPDATE BIT_ULL(11)
+
#define PIN_OFFSET_MASK(-I915_GTT_PAGE_SIZE)
#endif
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 7252abc73d3e..5793abe509a2 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -71,29 +71,42 @@ struct i915_vma {
unsigned int open_count;
unsigned long flags;
/**
-* How many users have pinned this object in GTT space. The following
-* users can each hold at most one reference: pwrite/pread, execbuffer
-* (objects are not allowed multiple times for the same batchbuffer),
-* and the framebuffer code. When switching/pageflipping, the
-* framebuffer code has at most two buffers pinned per crtc.
+* How many users have pinned this object in GTT space.
*
-* In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
-* bits with absolutely no headroom. So use 4 bits.
+* This is a tightly bound, fairly small number of users, so we
+* stuff inside the flags field so that we can both check for overflow
+* and detect a no-op i915_vma_pin() in a single check, while also
+* pinning the vma.
+*
+* The worst case display setup would have the same vma pinned for
+* use on each plane on each crtc, while also building the next atomic
+* state and holding a pin for the length of the cleanup queue. In the
+* future, the flip queue may be increased from 1.
+* Estimated worst case: 3 [qlen] * 4 [max crtcs] * 7 [max planes] = 84
+*
+* For GEM, the number of concurrent users for pwrite/pread is
+* unbounded. For execbuffer, it is currently one but will in future
+* be extended to allow multiple clients to pin vma concurrently.
+*
+* We also use suballocated pages, with each suballocation claiming
+* its own pin on the shared vma. At present, this is limited to
+* exclusive cachelines of a single page, so a maximum of 64 possible
+* users.
*/
-#define I915_VMA_PIN_MASK 0xf
-#define I915_VMA_PIN_OVERFLOW BIT(5)
+#define I915_VMA_PIN_MASK 0xff
+#define I915_VMA_PIN_OVERFLOW BIT(8)
/**
Re: [Intel-gfx] [PATCH] drm: Split out drm_probe_helper.h
Hi Daniel et al. > > > > Yeah the drm_crtc_helper.h header is a bit the miniature drmP.h for legacy > > kms drivers. Just removing it from all the atomic drivers caused lots of > > fallout, I expect even more if you entirely remove the includes it has. > > Maybe a todo, care to pls create that patch since it's your idea? > > The main reason I bailed out initially was that this would create > small changes to several otherwise seldomly touched files. > And then we would later come and remove drmP.h - so lots of > small but incremental changes to the same otherwise seldomly > edited files. > And the job was only partially done. > > I will try to experiment with an approach where I clean up the > include/drm/*.h files a little (like suggested above, +delete drmP.h > and maybe a bit more). > > Then to try on a driver by driver basis to make it build with a > cleaned set of include files. > I hope that the cleaned up driver can still build without the > cleaned header files so the changes can be submitted piecemal. > > Will do so with an eye on the lesser maintained drivers to try it > out to avoid creating too much chrunch for others. I have now a few patches queued, but the result is not too pretty. I did the following: - For all files in include/drm/*.h the set of include files were adjusted to the minimum number of files required to make them build without any other files included first. Created one .c file for each .h file. Then included the .h file and adjusted to the minimal set of include files. In the process a lot of forwards were added. - Deleted drmP.h - Fixed build of a few drivers: sti, tilcdc, gma500, tve200, via Some observations: - Killing all the includes not needed in the headers files results in a a lot of extra changes. Examples: drm_modseset_helper_vtables.h is no longer included by anyone, so needs to be added in many files drm_atomic_state_helper.h is no longer included by anyone so likewise needs to be added in many files - It is very tedious to do this properly. The process I followed was: - delete / comment out all include files - add back the obvious from a quick scan of the code - build - fix - build - fix - build - fix ... - next file... - The result is errorprone as only the allyesconfig + allmodconfig variants are tested. But reallife configurations are more diverse. Current diffstat: 111 files changed, 771 insertions(+), 401 deletions(-) This is for the 5 drivers alone and not the header cleanup. So long story short - this is not good and not the way forward. I will try to come up with a few improvements to make the headers files selfcontained, but restricted to the changes that add forwards/include to avoid the chrunch in all the drivers. And then post for review a few patches to clean up some headers. If the cleanup gets a go I will try to persuade the introduction of these. This will include, but will not be limited to, the above mentioned drm_crtc_helper.h header file. For now too much time was already spent on this, so it is at the moment pushed back on my TODO list. This mail serve also as a kind of "where had I left", when/if I pick this up again. If there are anyone that knows some tooling that can help in the process of adjusting the header files I am all ears. Sam ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Don't use the second dbuf slice on icl
== Series Details ==
Series: drm/i915: Don't use the second dbuf slice on icl
URL : https://patchwork.freedesktop.org/series/55517/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459_full -> Patchwork_11998_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_11998_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> FAIL [fdo#108597]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_vblank@pipe-b-wait-idle-hang:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@sw_sync@sync_busy_fork:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
Possible fixes
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-glk: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_busy@extended-pageflip-hang-oldfb-render-b:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-128x42-random:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-untiled:
- shard-snb: {SKIP} [fdo#109271] -> PASS +3
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: FAIL -> PASS
* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS
Warnings
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-glk: DMESG-FAIL [fdo#105763] / [fdo#106538] -> FAIL
[fdo#109381]
* igt@kms_setmode@basic:
- shard-apl: INCOMPLETE [fdo#103927] -> FAIL [fdo#99912]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109381]: https://bugs.freedesktop.org/show_bug.cgi?id=109381
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_11998
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11998: 143de466f6895ec4ef9b983a358045ded1703a37 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11998/
___
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Re: [Intel-gfx] [PATCH 5/6] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
On Tue, 15 Jan 2019 15:47:32 +0100,
Joonas Lahtinen wrote:
>
> From: Tvrtko Ursulin
>
> We want to allow userspace to reconfigure the subslice configuration on a
> per context basis.
>
> This is required for the functional requirement of shutting down non-VME
> enabled sub-slices on Gen11 parts.
>
> To do so, we expose a context parameter to allow adjustment of the RPCS
> register stored within the context image (and currently not accessible via
> LRI).
>
> If the context is adjusted before first use or whilst idle, the adjustment
> is for "free"; otherwise if the context is active we queue a request to do
> so (using the kernel context), following all other activity by that
> context, which is also marked as barrier for all following submission
> against the same context.
>
> Since the overhead of device re-configuration during context switching can
> be significant, especially in multi-context workloads, we limit this new
> uAPI to only support the Gen11 VME use case. In this use case either the
> device is fully enabled, and exactly one slice and half of the subslices
> are enabled.
>
> Example usage:
>
> struct drm_i915_gem_context_param_sseu sseu = { };
> struct drm_i915_gem_context_param arg =
> { .param = I915_CONTEXT_PARAM_SSEU,
> .ctx_id = gem_context_create(fd),
> .size = sizeof(sseu),
> .value = to_user_pointer()
> };
>
> /* Query device defaults. */
> gem_context_get_param(fd, );
>
> /* Set VME configuration on a 1x6x8 part. */
> sseu.slice_mask = 0x1;
> sseu.subslice_mask = 0xe0;
> gem_context_set_param(fd, );
>
> v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
>
> v3: Add ability to program this per engine (Chris)
>
> v4: Move most get_sseu() into i915_gem_context.c (Lionel)
>
> v5: Validate sseu configuration against the device's capabilities (Lionel)
>
> v6: Change context powergating settings through MI_SDM on kernel context
> (Chris)
>
> v7: Synchronize the requests following a powergating setting change using a
> global
> dependency (Chris)
> Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
> Disable RPCS configuration setting for non capable users (Lionel/Tvrtko)
>
> v8: s/union intel_sseu/struct intel_sseu/ (Lionel)
> s/dev_priv/i915/ (Tvrtko)
> Change uapi class/instance fields to u16 (Tvrtko)
> Bump mask fields to 64bits (Lionel)
> Don't return EPERM when dynamic sseu is disabled (Tvrtko)
>
> v9: Import context image into kernel context's ppgtt only when
> reconfiguring powergated slice/subslices (Chris)
> Use aliasing ppgtt when needed (Michel)
>
> Tvrtko Ursulin:
>
> v10:
> * Update for upstream changes.
> * Request submit needs a RPM reference.
> * Reject on !FULL_PPGTT for simplicity.
> * Pull out get/set param to helpers for readability and less indent.
> * Use i915_request_await_dma_fence in add_global_barrier to skip waits
>on the same timeline and avoid GEM_BUG_ON.
> * No need to explicitly assign a NULL pointer to engine in legacy mode.
> * No need to move gen8_make_rpcs up.
> * Factored out global barrier as prep patch.
> * Allow to only CAP_SYS_ADMIN if !Gen11.
>
> v11:
> * Remove engine vfunc in favour of local helper. (Chris Wilson)
> * Stop retiring requests before updates since it is not needed
>(Chris Wilson)
> * Implement direct CPU update path for idle contexts. (Chris Wilson)
> * Left side dependency needs only be on the same context timeline.
>(Chris Wilson)
> * It is sufficient to order the timeline. (Chris Wilson)
> * Reject !RCS configuration attempts with -ENODEV for now.
>
> v12:
> * Rebase for make_rpcs.
>
> v13:
> * Centralize SSEU normalization to make_rpcs.
> * Type width checking (uAPI <-> implementation).
> * Gen11 restrictions uAPI checks.
> * Gen11 subslice count differences handling.
> Chris Wilson:
> * args->size handling fixes.
> * Update context image from GGTT.
> * Postpone context image update to pinning.
> * Use i915_gem_active_raw instead of last_request_on_engine.
>
> v14:
> * Add activity tracker on intel_context to fix the lifetime issues
>and simplify the code. (Chris Wilson)
>
> v15:
> * Fix context pin leak if no space in ring by simplifying the
>context pinning sequence.
>
> v16:
> * Rebase for context get/set param locking changes.
> * Just -ENODEV on !Gen11. (Joonas)
>
> v17:
> * Fix one Gen11 subslice enablement rule.
> * Handle error from i915_sw_fence_await_sw_fence_gfp. (Chris Wilson)
>
> v18:
> * Update commit message. (Joonas)
> * Restrict uAPI to VME use case. (Joonas)
>
> v19:
> * Rebase.
>
> v20:
> * Rebase for ce->active_tracker.
>
> v21:
> * Rebase for IS_GEN changes.
>
> v22:
> * Reserve uAPI for flags straight away. (Chris Wilson)
>
> v23:
> * Rebase for RUNTIME_INFO.
>
> v24:
> * Added some headline docs for the uapi usage.
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm: Add debug prints for the various object lookup errors
== Series Details ==
Series: series starting with [1/3] drm: Add debug prints for the various object
lookup errors
URL : https://patchwork.freedesktop.org/series/55524/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459 -> Patchwork_11999
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55524/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11999 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182] +1
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u2}:FAIL [fdo#103167] -> PASS
* igt@pm_rpm@module-reload:
- {fi-icl-u2}:DMESG-WARN [fdo#108654] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (47 -> 40)
--
Additional (1): fi-glk-j4005
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-blb-e6850 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_11999
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11999: c2f89ad288cec5fdfd56a00db73e29559f57e19e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c2f89ad288ce drm: Add a debug print for drm_modeset_backoff()
0afa713ff7c7 drm: Sync errno values for property lookup errors
d613e645aae2 drm: Add debug prints for the various object lookup errors
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11999/
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Refactor out intel_context_init()
== Series Details ==
Series: drm/i915: Refactor out intel_context_init()
URL : https://patchwork.freedesktop.org/series/55516/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459_full -> Patchwork_11997_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_11997_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-apl: NOTRUN -> FAIL [fdo#103158]
* igt@gem_pwrite@display:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> FAIL [fdo#108597]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-glk: PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538]
Possible fixes
* igt@kms_busy@extended-pageflip-hang-oldfb-render-b:
- shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-untiled:
- shard-snb: {SKIP} [fdo#109271] -> PASS +4
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: FAIL -> PASS
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
Warnings
* igt@kms_setmode@basic:
- shard-apl: INCOMPLETE [fdo#103927] -> FAIL [fdo#99912]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_11997
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11997: 6c06b073a570d5920e5a743878fb468c9a195871 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11997/
___
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[Intel-gfx] [PATCH 3/3] drm: Add a debug print for drm_modeset_backoff()
From: Ville Syrjälä
Logs can get confusing when some operations are done multiple times
due to the ww mutex backoff. Add a debug print into
drm_modeset_backoff() so that at least the reason for the odd
looking logs will be obvious.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_modeset_lock.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_modeset_lock.c
b/drivers/gpu/drm/drm_modeset_lock.c
index 81dd11901ffd..1277ff18d993 100644
--- a/drivers/gpu/drm/drm_modeset_lock.c
+++ b/drivers/gpu/drm/drm_modeset_lock.c
@@ -295,6 +295,8 @@ int drm_modeset_backoff(struct drm_modeset_acquire_ctx *ctx)
{
struct drm_modeset_lock *contended = ctx->contended;
+ DRM_DEBUG_KMS("Retrying to avoid deadlock\n");
+
ctx->contended = NULL;
if (WARN_ON(!contended))
--
2.19.2
___
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[Intel-gfx] [PATCH 1/3] drm: Add debug prints for the various object lookup errors
From: Ville Syrjälä
Only some of the drm mode object lookups have a corresponding debug
print for the lookup failure. That makes logs a bit hard to parse
when you can't see where the bad object ID is being used. Add a bunch
more debug prints, and unify their appearance.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic_uapi.c | 5 +
drivers/gpu/drm/drm_color_mgmt.c | 8 ++--
drivers/gpu/drm/drm_connector.c | 5 -
drivers/gpu/drm/drm_crtc.c| 12 +++-
drivers/gpu/drm/drm_encoder.c | 4 +++-
drivers/gpu/drm/drm_framebuffer.c | 4 +++-
drivers/gpu/drm/drm_mode_object.c | 17 ++---
drivers/gpu/drm/drm_plane.c | 13 +
drivers/gpu/drm/drm_property.c| 12 +---
drivers/gpu/drm/drm_vblank.c | 8 ++--
10 files changed, 66 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 9a1f41adfc67..06390307e5a3 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -1321,11 +1321,14 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
obj = drm_mode_object_find(dev, file_priv, obj_id,
DRM_MODE_OBJECT_ANY);
if (!obj) {
+ DRM_DEBUG_ATOMIC("Unknown object ID %d\n", obj_id);
ret = -ENOENT;
goto out;
}
if (!obj->properties) {
+ DRM_DEBUG_ATOMIC("Object ID %d has no properties\n",
+obj_id);
drm_mode_object_put(obj);
ret = -ENOENT;
goto out;
@@ -1352,6 +1355,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
prop = drm_mode_obj_find_prop_id(obj, prop_id);
if (!prop) {
+ DRM_DEBUG_ATOMIC("Unknown property ID %d\n",
+prop_id);
drm_mode_object_put(obj);
ret = -ENOENT;
goto out;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 07dcf47daafe..a99ee15b8328 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -245,8 +245,10 @@ int drm_mode_gamma_set_ioctl(struct drm_device *dev,
return -EOPNOTSUPP;
crtc = drm_crtc_find(dev, file_priv, crtc_lut->crtc_id);
- if (!crtc)
+ if (!crtc) {
+ DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_lut->crtc_id);
return -ENOENT;
+ }
if (crtc->funcs->gamma_set == NULL)
return -ENOSYS;
@@ -313,8 +315,10 @@ int drm_mode_gamma_get_ioctl(struct drm_device *dev,
return -EOPNOTSUPP;
crtc = drm_crtc_find(dev, file_priv, crtc_lut->crtc_id);
- if (!crtc)
+ if (!crtc) {
+ DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_lut->crtc_id);
return -ENOENT;
+ }
/* memcpy into gamma store */
if (crtc_lut->gamma_size != crtc->gamma_size)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 847539645558..8745eb132fd4 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1952,8 +1952,11 @@ int drm_mode_getconnector(struct drm_device *dev, void
*data,
memset(_mode, 0, sizeof(struct drm_mode_modeinfo));
connector = drm_connector_lookup(dev, file_priv,
out_resp->connector_id);
- if (!connector)
+ if (!connector) {
+ DRM_DEBUG_KMS("Unknown connector ID %d\n",
+ out_resp->connector_id);
return -ENOENT;
+ }
drm_connector_for_each_possible_encoder(connector, encoder, i)
encoders_count++;
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 7dabbaf033a1..e5f234ffcd23 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -369,8 +369,10 @@ int drm_mode_getcrtc(struct drm_device *dev,
return -EOPNOTSUPP;
crtc = drm_crtc_find(dev, file_priv, crtc_resp->crtc_id);
- if (!crtc)
+ if (!crtc) {
+ DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_resp->crtc_id);
return -ENOENT;
+ }
plane = crtc->primary;
@@ -586,8 +588,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
} else {
fb = drm_framebuffer_lookup(dev, file_priv,
crtc_req->fb_id);
if (!fb) {
- DRM_DEBUG_KMS("Unknown FB ID%d\n",
- crtc_req->fb_id);
+ DRM_DEBUG_KMS("Unknown FB ID %d\n",
+ crtc_req->fb_id);
[Intel-gfx] [PATCH 2/3] drm: Sync errno values for property lookup errors
From: Ville Syrjälä
Use ENOENT consistently for the case where the requested property
isn't found, and EINVAL for the case where the object has no
properties whatsoever. Currenrly these are handled differently
in the atomic and legacy codepaths.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic_uapi.c | 2 +-
drivers/gpu/drm/drm_mode_object.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 06390307e5a3..2a54f826cf65 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -1330,7 +1330,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
DRM_DEBUG_ATOMIC("Object ID %d has no properties\n",
obj_id);
drm_mode_object_put(obj);
- ret = -ENOENT;
+ ret = -EINVAL;
goto out;
}
diff --git a/drivers/gpu/drm/drm_mode_object.c
b/drivers/gpu/drm/drm_mode_object.c
index e8dac94d576d..31730d935842 100644
--- a/drivers/gpu/drm/drm_mode_object.c
+++ b/drivers/gpu/drm/drm_mode_object.c
@@ -527,6 +527,7 @@ int drm_mode_obj_set_property_ioctl(struct drm_device *dev,
void *data,
property = drm_mode_obj_find_prop_id(arg_obj, arg->prop_id);
if (!property) {
DRM_DEBUG_KMS("Unknown property ID %d\n", arg->prop_id);
+ ret = -ENOENT;
goto out_unref;
}
--
2.19.2
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: rename has_edp_a() to intel_pch_has_edp_a()
On Mon, Jan 21, 2019 at 04:21:34PM +0200, Jani Nikula wrote:
> Clarify that the name is specific to PCH platforms.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 6960004fdc94..32270d7b71b9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14231,7 +14231,7 @@ static int intel_encoder_clones(struct intel_encoder
> *encoder)
> return index_mask;
> }
>
> -static bool has_edp_a(struct drm_i915_private *dev_priv)
> +static bool intel_pch_has_edp_a(struct drm_i915_private *dev_priv)
Hmm. The port is on the CPU though. The function name reads more like
it's looking for port A on the PCH now. ilk_has_edp_a() maybe?
> {
> if (!IS_MOBILE(dev_priv))
> return false;
> @@ -14385,7 +14385,7 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>
> dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
>
> - if (has_edp_a(dev_priv))
> + if (intel_pch_has_edp_a(dev_priv))
> intel_dp_init(dev_priv, DP_A, PORT_A);
>
> if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
> --
> 2.20.1
>
> ___
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/tv: only call intel_tv_init() on platforms that might have TV
On Mon, Jan 21, 2019 at 04:21:33PM +0200, Jani Nikula wrote:
> With most platforms not having TV support, only call intel_tv_init() on
> platforms that might actually have TV, specifically gens 3 and 4.
>
> This puts intel_tv_init() more in line with the rest of the outputs, and
> makes it slightly easier for the uninitiated to figure out which
> platforms actually have what.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4207ee0b83ce..6960004fdc94 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14501,6 +14501,9 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>
> if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
> intel_dp_init(dev_priv, DP_D, PORT_D);
> +
> + if (SUPPORTS_TV(dev_priv))
> + intel_tv_init(dev_priv);
Since PNV was split into its own thing I think this could actually
be replaced with IS_MOBILE().
Either way
Reviewed-by: Ville Syrjälä
> } else if (IS_GEN(dev_priv, 2)) {
> if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
> intel_lvds_init(dev_priv);
> @@ -14511,9 +14514,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_dvo_init(dev_priv);
> }
>
> - if (SUPPORTS_TV(dev_priv))
> - intel_tv_init(dev_priv);
> -
> intel_psr_init(dev_priv);
>
> for_each_intel_encoder(_priv->drm, encoder) {
> --
> 2.20.1
>
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Re: [Intel-gfx] [PATCH 3/5] drm/i915/lvds: nuke intel_lvds_supported()
On Mon, Jan 21, 2019 at 04:21:32PM +0200, Jani Nikula wrote:
> Now that intel_lvds_init() is only called for platforms that might have
> LVDS, move the remaining checks to intel_setup_outputs(), again similar
> to other outputs, and remove the overlapping checks.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 --
> drivers/gpu/drm/i915/intel_lvds.c| 23 ---
> 2 files changed, 4 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4b5704a87934..4207ee0b83ce 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14464,7 +14464,8 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
Had to read the earlier patch twice to make sure we're not leaving
ibx/cpt/ppt or pnv behind.
> } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
> bool found = false;
>
> - intel_lvds_init(dev_priv);
> + if (IS_MOBILE(dev_priv))
> + intel_lvds_init(dev_priv);
>
> if (dev_priv->vbt.int_crt_support)
> intel_crt_init(dev_priv);
> @@ -14501,7 +14502,8 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
> intel_dp_init(dev_priv, DP_D, PORT_D);
> } else if (IS_GEN(dev_priv, 2)) {
> - intel_lvds_init(dev_priv);
> + if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
aka. IS_I85X()
Reviewed-by: Ville Syrjälä
> + intel_lvds_init(dev_priv);
>
> if (dev_priv->vbt.int_crt_support)
> intel_crt_init(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
> b/drivers/gpu/drm/i915/intel_lvds.c
> index 46a5dfd5cdf7..815ed463d9c5 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -798,26 +798,6 @@ static bool compute_is_dual_link_lvds(struct
> intel_lvds_encoder *lvds_encoder)
> return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
> }
>
> -static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
> -{
> - /*
> - * With the introduction of the PCH we gained a dedicated
> - * LVDS presence pin, use it.
> - */
> - if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
> - return true;
> -
> - /*
> - * Otherwise LVDS was only attached to mobile products,
> - * except for the inglorious 830gm
> - */
> - if (INTEL_GEN(dev_priv) <= 4 &&
> - IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
> - return true;
> -
> - return false;
> -}
> -
> /**
> * intel_lvds_init - setup LVDS connectors on this device
> * @dev_priv: i915 device
> @@ -842,9 +822,6 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
> u8 pin;
> u32 allowed_scalers;
>
> - if (!intel_lvds_supported(dev_priv))
> - return;
> -
> /* Skip init on machines we know falsely report LVDS */
> if (dmi_check_system(intel_no_lvds)) {
> WARN(!dev_priv->vbt.int_lvds_support,
> --
> 2.20.1
>
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/lvds: only call intel_lvds_init() on platforms that might have LVDS
On Mon, Jan 21, 2019 at 04:21:31PM +0200, Jani Nikula wrote:
> With new platforms not having LVDS support, only call intel_lvds_init()
> on platforms that might actually have LVDS. Move the comment about eDP
> init to the PCH block where it's relevant.
>
> This puts intel_lvds_init() more in line with the rest of the outputs,
> and makes it slightly easier for the uninitiated to figure out which
> platforms actually have what.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 20 +---
> 1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e8bc297c60ab..4b5704a87934 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14310,13 +14310,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - /*
> - * intel_edp_init_connector() depends on this completing first, to
> - * prevent the registeration of both eDP and LVDS and the incorrect
> - * sharing of the PPS.
> - */
> - intel_lvds_init(dev_priv);
> -
> if (IS_ICELAKE(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> @@ -14380,6 +14373,13 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> int found;
>
> + /*
> + * intel_edp_init_connector() depends on this completing first,
> + * to prevent the registration of both eDP and LVDS and the
> + * incorrect sharing of the PPS.
> + */
> + intel_lvds_init(dev_priv);
> +
> if (dev_priv->vbt.int_crt_support)
> intel_crt_init(dev_priv);
>
> @@ -14457,11 +14457,15 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>
> vlv_dsi_init(dev_priv);
> } else if (IS_PINEVIEW(dev_priv)) {
> + intel_lvds_init(dev_priv);
> +
> if (dev_priv->vbt.int_crt_support)
> intel_crt_init(dev_priv);
> } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
> bool found = false;
>
> + intel_lvds_init(dev_priv);
> +
> if (dev_priv->vbt.int_crt_support)
> intel_crt_init(dev_priv);
>
> @@ -14497,6 +14501,8 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
> intel_dp_init(dev_priv, DP_D, PORT_D);
> } else if (IS_GEN(dev_priv, 2)) {
> + intel_lvds_init(dev_priv);
> +
> if (dev_priv->vbt.int_crt_support)
> intel_crt_init(dev_priv);
>
> --
> 2.20.1
>
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/crt: split out intel_crt_present() to platform specific setup
On Mon, Jan 21, 2019 at 04:21:30PM +0200, Jani Nikula wrote:
> With new platforms not having CRT support and most conditions in
> intel_crt_present() being specific to DDI, split out the CRT
> initialization to platform specific blocks in the if ladder. Add new
> Pineview block for this.
>
> This puts intel_crt_init() more in line with the rest of the outputs,
> and makes it slightly easier for the uninitiated to figure out which
> platforms actually have what.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 37 ++--
> 1 file changed, 24 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 2fa9f4aec08e..e8bc297c60ab 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14245,23 +14245,17 @@ static bool has_edp_a(struct drm_i915_private
> *dev_priv)
> return true;
> }
>
> -static bool intel_crt_present(struct drm_i915_private *dev_priv)
> +static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
> {
> - if (INTEL_GEN(dev_priv) >= 9)
> - return false;
We should probably keep this in case the vbt is bonkers.
> -
> if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
> return false;
>
> - if (IS_CHERRYVIEW(dev_priv))
> - return false;
> -
> if (HAS_PCH_LPT_H(dev_priv) &&
> I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
> return false;
>
> /* DDI E can't be used if DDI A requires 4 lanes */
> - if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
> + if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
> return false;
>
> if (!dev_priv->vbt.int_crt_support)
> @@ -14323,9 +14317,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>*/
> intel_lvds_init(dev_priv);
>
> - if (intel_crt_present(dev_priv))
> - intel_crt_init(dev_priv);
> -
> if (IS_ICELAKE(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> @@ -14354,6 +14345,9 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> } else if (HAS_DDI(dev_priv)) {
> int found;
>
> + if (intel_ddi_crt_present(dev_priv))
> + intel_crt_init(dev_priv);
> +
> /*
>* Haswell uses DDI functions to detect digital outputs.
>* On SKL pre-D0 the strap isn't connected, so we assume
> @@ -14385,6 +14379,10 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> int found;
> +
> + if (dev_priv->vbt.int_crt_support)
> + intel_crt_init(dev_priv);
> +
> dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
>
> if (has_edp_a(dev_priv))
> @@ -14413,6 +14411,9 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> bool has_edp, has_port;
>
> + if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
> + intel_crt_init(dev_priv);
> +
> /*
>* The DP_DETECTED bit is the latched state of the DDC
>* SDA pin at boot. However since eDP doesn't require DDC
> @@ -14455,9 +14456,15 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> }
>
> vlv_dsi_init(dev_priv);
> - } else if (!IS_GEN(dev_priv, 2) && !IS_PINEVIEW(dev_priv)) {
> + } else if (IS_PINEVIEW(dev_priv)) {
> + if (dev_priv->vbt.int_crt_support)
> + intel_crt_init(dev_priv);
> + } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
> bool found = false;
>
> + if (dev_priv->vbt.int_crt_support)
> + intel_crt_init(dev_priv);
> +
> if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
> DRM_DEBUG_KMS("probing SDVOB\n");
> found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
> @@ -14489,8 +14496,12 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>
> if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
> intel_dp_init(dev_priv, DP_D, PORT_D);
> - } else if (IS_GEN(dev_priv, 2))
> + } else if (IS_GEN(dev_priv, 2)) {
> + if (dev_priv->vbt.int_crt_support)
> + intel_crt_init(dev_priv);
int_crt_support is always true for pre-vlv/pre-hsw so we could
skip the check in most of these cases. Either way is fine by me.
With the gen9 stuff sorted this is
Reviewed-by: Ville Syrjälä
> +
> intel_dvo_init(dev_priv);
> + }
>
>
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/crt: split out intel_crt_present() to platform specific setup
== Series Details ==
Series: series starting with [1/5] drm/i915/crt: split out intel_crt_present()
to platform specific setup
URL : https://patchwork.freedesktop.org/series/55513/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5458_full -> Patchwork_11996_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_11996_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-external:
- shard-glk: PASS -> FAIL [fdo#105957]
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
Possible fixes
* igt@gem_ctx_isolation@vecs0-s3:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@gem_exec_reuse@contexts:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-snb: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-apl: DMESG-FAIL [fdo#108950] -> PASS
* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105957]: https://bugs.freedesktop.org/show_bug.cgi?id=105957
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5458 -> Patchwork_11996
CI_DRM_5458: 74ec7792af09018594097356ddc79d87cb9504f9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4779: d4199510374514489b1ab56e3416f53f6c1d6291 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11996: 668fb89873712da0211716fc5371e7b7ed7a0fc0 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11996/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't use the second dbuf slice on icl
== Series Details ==
Series: drm/i915: Don't use the second dbuf slice on icl
URL : https://patchwork.freedesktop.org/series/55517/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459 -> Patchwork_11998
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55517/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11998 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:DMESG-FAIL [fdo#108735] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u2}:FAIL [fdo#103167] -> PASS
* igt@pm_rpm@module-reload:
- {fi-icl-u2}:DMESG-WARN [fdo#108654] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (47 -> 42)
--
Additional (1): fi-glk-j4005
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_11998
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11998: 143de466f6895ec4ef9b983a358045ded1703a37 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
143de466f689 drm/i915: Don't use the second dbuf slice on icl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11998/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Refactor out intel_context_init()
== Series Details ==
Series: drm/i915: Refactor out intel_context_init()
URL : https://patchwork.freedesktop.org/series/55516/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5459 -> Patchwork_11997
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55516/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11997 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6700hq: PASS -> DMESG-WARN [fdo#105998]
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:DMESG-FAIL [fdo#108735] -> PASS
* igt@pm_rpm@module-reload:
- {fi-icl-u2}:DMESG-WARN [fdo#108654] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (47 -> 41)
--
Additional (1): fi-glk-j4005
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-gdg-551 fi-pnv-d510 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5459 -> Patchwork_11997
CI_DRM_5459: 0f693a275dd91391b476ada7481cf08f4fe610aa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4780: 1c1612bdc36b44a704095e7b0ba5542818ce793f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11997: 6c06b073a570d5920e5a743878fb468c9a195871 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6c06b073a570 drm/i915: Refactor out intel_context_init()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11997/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Don't use the second dbuf slice on icl
== Series Details ==
Series: drm/i915: Don't use the second dbuf slice on icl
URL : https://patchwork.freedesktop.org/series/55517/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
143de466f689 drm/i915: Don't use the second dbuf slice on icl
-:40: CHECK:CAMELCASE: Avoid CamelCase:
#40: FILE: drivers/gpu/drm/i915/intel_pm.c:3837:
+ if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
total: 0 errors, 0 warnings, 1 checks, 23 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp: use DRM_DEBUG_DP() instead of drm_dbg for logging
== Series Details ==
Series: drm/dp: use DRM_DEBUG_DP() instead of drm_dbg for logging
URL : https://patchwork.freedesktop.org/series/55509/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5458_full -> Patchwork_11995_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_11995_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +3
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
Possible fixes
* igt@gem_exec_reuse@contexts:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-glk: FAIL [fdo#103232] -> PASS
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS
* igt@perf_pmu@rc6:
- shard-kbl: {SKIP} [fdo#109271] -> PASS
Warnings
* igt@i915_suspend@shrink:
- shard-glk: DMESG-WARN [fdo#109244] -> INCOMPLETE [fdo#103359] /
[fdo#106886] / [k.org#198133]
* igt@kms_chamelium@hdmi-crc-xrgb1555:
- shard-apl: {SKIP} [fdo#109271] -> INCOMPLETE [fdo#103927]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5458 -> Patchwork_11995
CI_DRM_5458: 74ec7792af09018594097356ddc79d87cb9504f9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4779: d4199510374514489b1ab56e3416f53f6c1d6291 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11995: 5d56af8c2a5594ae50970ed730e478cd85227c37 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11995/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/crt: split out intel_crt_present() to platform specific setup
== Series Details ==
Series: series starting with [1/5] drm/i915/crt: split out intel_crt_present()
to platform specific setup
URL : https://patchwork.freedesktop.org/series/55513/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5458 -> Patchwork_11996
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55513/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11996 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362] +1
* igt@pm_rpm@basic-rte:
- fi-byt-j1900: PASS -> FAIL [fdo#108800]
Possible fixes
* igt@i915_module_load@reload-no-display:
- fi-bwr-2160:INCOMPLETE -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (46 -> 43)
--
Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
Build changes
-
* Linux: CI_DRM_5458 -> Patchwork_11996
CI_DRM_5458: 74ec7792af09018594097356ddc79d87cb9504f9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4779: d4199510374514489b1ab56e3416f53f6c1d6291 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11996: 668fb89873712da0211716fc5371e7b7ed7a0fc0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
668fb8987371 drm/i915: rename has_edp_a() to intel_pch_has_edp_a()
25029515ae52 drm/i915/tv: only call intel_tv_init() on platforms that might
have TV
fcb78959a800 drm/i915/lvds: nuke intel_lvds_supported()
63516b14cceb drm/i915/lvds: only call intel_lvds_init() on platforms that might
have LVDS
999884307e02 drm/i915/crt: split out intel_crt_present() to platform specific
setup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11996/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix dinq debug build
== Series Details ==
Series: drm/i915: Fix dinq debug build
URL : https://patchwork.freedesktop.org/series/55506/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5458_full -> Patchwork_11994_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11994_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@runner@aborted}:
- shard-snb: NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_11994_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-snb: PASS -> DMESG-WARN [fdo#107469]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
Possible fixes
* igt@gem_ctx_isolation@vecs0-s3:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@gem_exec_reuse@contexts:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS +3
* igt@kms_setmode@basic:
- shard-hsw: FAIL [fdo#99912] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107469]: https://bugs.freedesktop.org/show_bug.cgi?id=107469
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5458 -> Patchwork_11994
CI_DRM_5458: 74ec7792af09018594097356ddc79d87cb9504f9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4779: d4199510374514489b1ab56e3416f53f6c1d6291 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11994: d4080854535df509b35efa474e69d12671821a23 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11994/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Don't use the second dbuf slice on icl
From: Ville Syrjälä
The code managing the dbuf slices is borked and needs some
real work to fix. In the meantime let's just stop using the
second slice.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b63afa3a221..1e41c899ffe2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3618,7 +3618,8 @@ static u8 intel_enabled_dbuf_slices_num(struct
drm_i915_private *dev_priv)
enabled_slices = 1;
/* Gen prior to GEN11 have only one DBuf slice */
- if (INTEL_GEN(dev_priv) < 11)
+ /* FIXME dbuf slice code is broken: see intel_get_ddb_size() */
+ if (1 || INTEL_GEN(dev_priv) < 11)
return enabled_slices;
if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
@@ -3827,8 +3828,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private
*dev_priv,
/*
* 12GB/s is maximum BW supported by single DBuf slice.
+*
+* FIXME dbuf slice code is broken:
+* - must wait for planes to stop using the slice before powering it off
+* - plane straddling both slices is illegal in multi-pipe scenarios
+* - should validate we stay within the hw bandwidth limits
*/
- if (num_active > 1 || total_data_bw >= GBps(12)) {
+ if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
ddb->enabled_slices = 2;
} else {
ddb->enabled_slices = 1;
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dsi: Adjust crtc_clock for burst_mode_ratio
Hi, On 21-01-19 15:26, Hans de Goede wrote: Hi, On 15-01-19 16:00, Ville Syrjälä wrote: On Sat, Dec 01, 2018 at 12:31:47PM +0100, Hans de Goede wrote: On devices with a burst_mode_ratio which is not 100 (1:1), the pclk will have a different value then drm_display_mode.clock . On a Prowise PT301 tablet where vbt.lfp_lvds_vbt_mode.clock is 66100 and burst_mode_ratio is 130 this leads to the following errors: [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 66100, found 86458) [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 66100, found 86458) [drm:pipe_config_err [i915]] *ERROR* mismatch in port_clock (expected 66100, found 86458) This commit makes intel_dsi_compute_config() set pipe_config.adjusted_mode.crtc_clock, taking the burst_mode_ratio into account fixing this. Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/vlv_dsi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c index c21cbfa9653c..d72ccf557a9c 100644 --- a/drivers/gpu/drm/i915/vlv_dsi.c +++ b/drivers/gpu/drm/i915/vlv_dsi.c @@ -347,6 +347,10 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, return false; } + adjusted_mode->crtc_clock = + DIV_ROUND_UP(adjusted_mode->crtc_clock * + intel_dsi->burst_mode_ratio, 100); Hmm. Won't this cause incorrect refresh rate to be used in eg. vblank timestmap calculations? I guess so. Note that this patch does not change any values actually written to the hardware. It seems that devices which actually use the burst mode are quite rare (this is the first one encounter in probably over 40 different byt/cht devices I've tested). I've a feeling that the entire pipeline is actually running at the higher rate and that the framerate really is 30% higher. Looking at the code, it seems that what a burst_mode_ratio of 130'does is make all the values in the "modeline" except for the visual area 30% larger, which means that we are probably already messing up the vblank calculations anyways, since using either the uncorrected or the corrected clock is wrong when using htotal from the original modeline, as looking at txbyteclkhs we will use bigger values for all drm_display_mode values except for the active region. I think that the right way to deal with this is to isolate the burst_ratio handling to intel_dsi_vbt.c and adjust the modeline coming from the VBT by multiplying the clock and all timing parameters (except h/vdisplay) there by the burst_ratio and then recalculating h/vtotal. This should lead to getting the vblank timestamp stuff right and allows removing of burst_mode_ratio from all code except for the vbt code. If that is too invasive, given that this setup is quite rate, then I suggest we just go with this patch. My main concern is fixing the WARN_ON. This patch successfully does that. OTOH if the pipe is really fetching data at the higher burst rate then we should rather want to calculate the watermarks/cdclk based on that higher rate. Right, the more I think about this, the more I believe calculating a new modeline correcting for burst_ratio inside the vbt code and dropping burst_mode_ratio handling everywhere else is the right thing to do. Regards, Hans p.s. The 4th patch in this series is independent of the others, it fixes a small bug (not freeing a resource) in an exit error path which I noticed. It would be great if someone can review the 4th patch then I can push that one too and then this patch will be the only unmerged patch from this series. Regards, Hans ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: switch to kernel types
== Series Details ==
Series: drm/i915/gvt: switch to kernel types
URL : https://patchwork.freedesktop.org/series/55503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5458_full -> Patchwork_11993_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_11993_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_atomic_interruptible@universal-setplane-primary:
- shard-kbl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +4
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-kbl: PASS -> DMESG-FAIL [fdo#103232] / [fdo#103558] /
[fdo#105602]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +3
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
Possible fixes
* igt@gem_exec_reuse@contexts:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-glk: FAIL [fdo#103232] -> PASS
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-apl: DMESG-FAIL [fdo#108950] -> PASS
Warnings
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-glk: DMESG-FAIL [fdo#105763] / [fdo#106538] -> FAIL
[fdo#109381]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109381]: https://bugs.freedesktop.org/show_bug.cgi?id=109381
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5458 -> Patchwork_11993
CI_DRM_5458: 74ec7792af09018594097356ddc79d87cb9504f9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4779: d4199510374514489b1ab56e3416f53f6c1d6291 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11993: 65ac07a754799ac1b91daae24db602479bd7d6f7 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11993/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
[Intel-gfx] [PATCH] drm/i915: Refactor out intel_context_init()
Prior to adding a third instance of intel_context_init() and extending
the information stored therewithin, refactor out the common assignments.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 7 ++-
drivers/gpu/drm/i915/i915_gem_context.h | 8
drivers/gpu/drm/i915/selftests/mock_context.c | 7 ++-
3 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5933adbe3d99..fae68c4c4683 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -338,11 +338,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
ctx->i915 = dev_priv;
ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
- for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
- struct intel_context *ce = >__engine[n];
-
- ce->gem_context = ctx;
- }
+ for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++)
+ intel_context_init(>__engine[n], ctx, dev_priv->engine[n]);
INIT_RADIX_TREE(>handles_vma, GFP_KERNEL);
INIT_LIST_HEAD(>handles_list);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index f6d870b1f73e..47d82ce7ba6a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -364,4 +364,12 @@ static inline void i915_gem_context_put(struct
i915_gem_context *ctx)
kref_put(>ref, i915_gem_context_release);
}
+static inline void
+intel_context_init(struct intel_context *ce,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine)
+{
+ ce->gem_context = ctx;
+}
+
#endif /* !__I915_GEM_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/selftests/mock_context.c
b/drivers/gpu/drm/i915/selftests/mock_context.c
index d937bdff26f9..b646cdcdd602 100644
--- a/drivers/gpu/drm/i915/selftests/mock_context.c
+++ b/drivers/gpu/drm/i915/selftests/mock_context.c
@@ -45,11 +45,8 @@ mock_context(struct drm_i915_private *i915,
INIT_LIST_HEAD(>handles_list);
INIT_LIST_HEAD(>hw_id_link);
- for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
- struct intel_context *ce = >__engine[n];
-
- ce->gem_context = ctx;
- }
+ for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++)
+ intel_context_init(>__engine[n], ctx, i915->engine[n]);
ret = i915_gem_context_pin_hw_id(ctx);
if (ret < 0)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915/execlists: Mark up priority boost on preemption
== Series Details ==
Series: series starting with [1/6] drm/i915/execlists: Mark up priority boost
on preemption
URL : https://patchwork.freedesktop.org/series/55501/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5458_full -> Patchwork_11992_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_11992_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_flip@modeset-vs-vblank-race:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-glk: PASS -> FAIL [fdo#108145]
Possible fixes
* igt@gem_exec_reuse@contexts:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-64x64-random:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@perf_pmu@rc6:
- shard-kbl: {SKIP} [fdo#109271] -> PASS
Warnings
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
- shard-glk: DMESG-WARN [fdo#107956] -> INCOMPLETE [fdo#103359] /
[k.org#198133]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5458 -> Patchwork_11992
CI_DRM_5458: 74ec7792af09018594097356ddc79d87cb9504f9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4779: d4199510374514489b1ab56e3416f53f6c1d6291 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11992: b13142d34267c6f987dd40debd5e7f861e0a3437 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11992/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH v5 3/3] PM/runtime:Replace jiffies based accounting with ktime based accounting
On 1/21/19 7:17 AM, Vincent Guittot wrote: On Fri, 18 Jan 2019 at 13:08, Guenter Roeck wrote: On 1/18/19 3:05 AM, Rafael J. Wysocki wrote: On Fri, Jan 18, 2019 at 11:53 AM Vincent Guittot wrote: On Fri, 18 Jan 2019 at 11:42, Vincent Guittot wrote: Hi Guenter, Le Thursday 17 Jan 2019 à 14:16:28 (-0800), Guenter Roeck a écrit : On Fri, Dec 21, 2018 at 11:33:56AM +0100, Vincent Guittot wrote: From: Thara Gopinath This patch replaces jiffies based accounting for runtime_active_time and runtime_suspended_time with ktime base accounting. This makes the runtime debug counters inline with genpd and other pm subsytems which uses ktime based accounting. timekeeping is initialized before pm_runtime_init() so ktime_get() will be ready before first call. In fact, timekeeping_init() is called early in start_kernel() which is way before driver_init() (and that's when devices can start to be initialized) called from rest_init() via kernel_init_freeable() and do_basic_setup(). This is not (always) correct. My qemu "collie" boot test fails with this patch applied. Reverting the patch fixes the problem. Bisect log attached. Can you try the patch below ? ktime_get_mono_fast_ns() has the advantage of being init with dummy clock so it can be used at early_init. Another possibility would be delay the init of the gpiochip Well, right. Initializing devices before timekeeping doesn't feel particularly robust from the design perspective. How exactly does that happen? With an added 'initialized' flag and backtrace into the timekeeping code, with the change suggested earlier applied: [ cut here ] WARNING: CPU: 0 PID: 0 at kernel/time/timekeeping.c:453 ktime_get_mono_fast_ns+0x114/0x12c Timekeeping not initialized CPU: 0 PID: 0 Comm: swapper Not tainted 5.0.0-rc2-next-20190117-dirty #2 Hardware name: Sharp-Collie Backtrace: [] (dump_backtrace) from [] (show_stack+0x18/0x1c) r7:0009 r6: r5:c065ba90 r4:c06d3e54 [] (show_stack) from [] (dump_stack+0x20/0x28) [] (dump_stack) from [] (__warn+0xcc/0xf4) [] (__warn) from [] (warn_slowpath_fmt+0x4c/0x6c) r8:df407b08 r7: r6:c0c01550 r5:c065bad8 r4:c06dd028 [] (warn_slowpath_fmt) from [] (ktime_get_mono_fast_ns+0x114/0x12c) r3: r2:c065bad8 r5: r4:df407b08 [] (ktime_get_mono_fast_ns) from [] (pm_runtime_init+0x38/0xb8) r9:c06c9a5c r8:df407b08 r7: r6:c0c01550 r5: r4:df407b08 [] (pm_runtime_init) from [] (device_initialize+0xb0/0xec) r7: r6:c0c01550 r5: r4:df407b08 [] (device_initialize) from [] (gpiochip_add_data_with_key+0x9c/0x884) r7: r6:c06fca34 r5: r4: [] (gpiochip_add_data_with_key) from [] (sa1100_init_gpio+0x40/0x98) r10:dfffcd60 r9:c06c9a5c r8:c06dd020 r7:c06dd028 r6: r5: r4:c06fca34 [] (sa1100_init_gpio) from [] (sa1100_init_irq+0x2c/0x3c) r7:c06dd028 r6: r5:c0713300 r4:c06e1070 [] (sa1100_init_irq) from [] (init_IRQ+0x20/0x28) r5:c0713300 r4: [] (init_IRQ) from [] (start_kernel+0x254/0x4cc) [] (start_kernel) from [<>] ( (null)) r10:717f r9:6901b119 r8:c100 r7:0092 r6:313d r5:0053 r4:c06a7330 ---[ end trace 91e1bd00dd7cce32 ]--- Does it means that only the pm_runtime_init is done before timekeeping_init() but no update_pm_runtime_accounting() ? In this case, we can keep using ktimeçget in update_pm_runtime_accounting() and find a solution to deal with early_call of pm_runtime_init() For this platform that is correct. I can't answer for the generic case. Guenter ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 3/3] PM/runtime:Replace jiffies based accounting with ktime based accounting
On Fri, 18 Jan 2019 at 13:08, Guenter Roeck wrote: > > On 1/18/19 3:05 AM, Rafael J. Wysocki wrote: > > On Fri, Jan 18, 2019 at 11:53 AM Vincent Guittot > > wrote: > >> > >> On Fri, 18 Jan 2019 at 11:42, Vincent Guittot > >> wrote: > >>> > >>> Hi Guenter, > >>> > >>> Le Thursday 17 Jan 2019 à 14:16:28 (-0800), Guenter Roeck a écrit : > On Fri, Dec 21, 2018 at 11:33:56AM +0100, Vincent Guittot wrote: > > From: Thara Gopinath > > > > This patch replaces jiffies based accounting for runtime_active_time > > and runtime_suspended_time with ktime base accounting. This makes the > > runtime debug counters inline with genpd and other pm subsytems which > > uses ktime based accounting. > > > > timekeeping is initialized before pm_runtime_init() so ktime_get() will > > be ready before first call. In fact, timekeeping_init() is called early > > in start_kernel() which is way before driver_init() (and that's when > > devices can start to be initialized) called from rest_init() via > > kernel_init_freeable() and do_basic_setup(). > > > This is not (always) correct. My qemu "collie" boot test fails with this > patch applied. Reverting the patch fixes the problem. Bisect log > attached. > > >>> > >>> Can you try the patch below ? > >>> ktime_get_mono_fast_ns() has the advantage of being init with dummy clock > >>> so > >>> it can be used at early_init. > >> > >> Another possibility would be delay the init of the gpiochip > > > > Well, right. > > > > Initializing devices before timekeeping doesn't feel particularly > > robust from the design perspective. > > > > How exactly does that happen? > > > > With an added 'initialized' flag and backtrace into the timekeeping code, > with the change suggested earlier applied: > > [ cut here ] > WARNING: CPU: 0 PID: 0 at kernel/time/timekeeping.c:453 > ktime_get_mono_fast_ns+0x114/0x12c > Timekeeping not initialized > CPU: 0 PID: 0 Comm: swapper Not tainted 5.0.0-rc2-next-20190117-dirty #2 > Hardware name: Sharp-Collie > Backtrace: > [] (dump_backtrace) from [] (show_stack+0x18/0x1c) > r7:0009 r6: r5:c065ba90 r4:c06d3e54 > [] (show_stack) from [] (dump_stack+0x20/0x28) > [] (dump_stack) from [] (__warn+0xcc/0xf4) > [] (__warn) from [] (warn_slowpath_fmt+0x4c/0x6c) > r8:df407b08 r7: r6:c0c01550 r5:c065bad8 r4:c06dd028 > [] (warn_slowpath_fmt) from [] > (ktime_get_mono_fast_ns+0x114/0x12c) > r3: r2:c065bad8 > r5: r4:df407b08 > [] (ktime_get_mono_fast_ns) from [] > (pm_runtime_init+0x38/0xb8) > r9:c06c9a5c r8:df407b08 r7: r6:c0c01550 r5: r4:df407b08 > [] (pm_runtime_init) from [] (device_initialize+0xb0/0xec) > r7: r6:c0c01550 r5: r4:df407b08 > [] (device_initialize) from [] > (gpiochip_add_data_with_key+0x9c/0x884) > r7: r6:c06fca34 r5: r4: > [] (gpiochip_add_data_with_key) from [] > (sa1100_init_gpio+0x40/0x98) > r10:dfffcd60 r9:c06c9a5c r8:c06dd020 r7:c06dd028 r6: r5: > r4:c06fca34 > [] (sa1100_init_gpio) from [] (sa1100_init_irq+0x2c/0x3c) > r7:c06dd028 r6: r5:c0713300 r4:c06e1070 > [] (sa1100_init_irq) from [] (init_IRQ+0x20/0x28) > r5:c0713300 r4: > [] (init_IRQ) from [] (start_kernel+0x254/0x4cc) > [] (start_kernel) from [<>] ( (null)) > r10:717f r9:6901b119 r8:c100 r7:0092 r6:313d r5:0053 > r4:c06a7330 > ---[ end trace 91e1bd00dd7cce32 ]--- Does it means that only the pm_runtime_init is done before timekeeping_init() but no update_pm_runtime_accounting() ? In this case, we can keep using ktimeçget in update_pm_runtime_accounting() and find a solution to deal with early_call of pm_runtime_init() Vincent > > Guenter ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/dp: use DRM_DEBUG_DP() instead of drm_dbg for logging
On Mon, Jan 21, 2019 at 01:27:58PM +0200, Jani Nikula wrote:
> We have a wrapper for a reason.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_dp_helper.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 26835d174939..4def0bface85 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -194,11 +194,11 @@ drm_dp_dump_access(const struct drm_dp_aux *aux,
> const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
>
> if (ret > 0)
> - drm_dbg(DRM_UT_DP, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
> - aux->name, offset, arrow, ret, min(ret, 20), buffer);
> + DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
> + aux->name, offset, arrow, ret, min(ret, 20),
> buffer);
> else
> - drm_dbg(DRM_UT_DP, "%s: 0x%05x AUX %s (ret=%3d)\n",
> - aux->name, offset, arrow, ret);
> + DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
> + aux->name, offset, arrow, ret);
> }
>
> /**
> --
> 2.20.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel
___
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Re: [Intel-gfx] [PATCH xf86-video-intel] sna/uxa: Fix colormap handling at screen depth 30. (v2)
On Sun, Jan 20, 2019 at 08:45:18PM +0100, Mario Kleiner wrote: > On Mon, Oct 15, 2018 at 6:21 PM Ville Syrjälä > wrote: > > > On Tue, Jun 12, 2018 at 06:20:35PM +0200, Mario Kleiner wrote: > > > The various clut handling functions like a setup > > > consistent with the x-screen color depth. Otherwise > > > we observe improper sampling in the gamma tables > > > at depth 30. > > > > > > Therefore replace hard-coded bitsPerRGB = 8 by actual > > > bits per channel scrn->rgbBits. Also use this for call > > > to xf86HandleColormaps(). > > > > > > Tested for uxa and sna at depths 8, 16, 24 and 30 on > > > IvyBridge, and tested at depth 24 and 30 that xgamma > > > and gamma table animations work, and with measurement > > > equipment to make sure identity gamma ramps actually > > > are identity mappings at the output. > > > > > > v2: Also deal with X-Server 1.19 and earlier, which as of > > > v1.19.6 lack a fix to color palette handling and can > > > not deal with depths/bpc > 24/8 bpc. On < 1.20 we skip > > > xf86HandleColormaps() setup at > 8 bpc. This disables > > > color palette handling on such servers at > 8 bpc, but > > > still keeps RandR gamma table handling intact. > > > > > > Tested on 1.19.6 and 1.20.0 to do the right thing. > > > > > > Signed-off-by: Mario Kleiner > > > > Forgot this didn't get applied. It did make sense to me at the > > time when I was looking at the explosions with depth 30. > > Still seems to do the trick on 1.19, and redshit still works > > so > > > > Reviewed-by: Ville Syrjälä > > > > > Thanks Ville! > > Now it just needs to get merged, please. Chris? > > One last missing piece is support for 1024 slot gamma tables in i965-kms, > or gamma table bypass for such high bit depth framebuffers to make them > actually useful. Ville, i think you mentioned working on that around spring > last year? Kernel bits for gamma table bypass are on the list: https://patchwork.freedesktop.org/series/55081/ Apart from that I've not had any real time to work on it. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/backlight: Restore backlight on resume, v3.
Hi,
On 08-01-19 17:08, Maarten Lankhorst wrote:
Restore our saved values for backlight. This way even with fastset on
S4 resume we will correctly restore the backlight to the active values.
Changes since v1:
- Call enable_backlight() when backlight.level is set. On suspend
backlight.enabled is always cleared, this makes it not a good
indicator. Also check for crtc->state->active.
Changes since v2:
- Use the new update_pipe() callback to run this on resume as well.
Signed-off-by: Maarten Lankhorst
Cc: Tolga Cakir
Cc: Basil Eric Rabi
Cc: Hans de Goede
Cc: Ville Syrjälä
Reported-by: Ville Syrjälä
Signed-off-by: Maarten Lankhorst
Entire series looks good to me:
Reviewed-by: Hans de Goede
Regards,
Hans
p.s.
I'll also reply to the other 4 patches to get the Rev-by on all patches in
patchwork.
---
drivers/gpu/drm/i915/icl_dsi.c | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c| 1 +
drivers/gpu/drm/i915/intel_drv.h | 3 ++
drivers/gpu/drm/i915/intel_lvds.c | 1 +
drivers/gpu/drm/i915/intel_panel.c | 49 +++---
drivers/gpu/drm/i915/vlv_dsi.c | 1 +
7 files changed, 47 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 4dd793b78996..3f92881600c5 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1378,6 +1378,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->disable = gen11_dsi_disable;
encoder->port = port;
encoder->get_config = gen11_dsi_get_config;
+ encoder->update_pipe = intel_panel_update_backlight;
encoder->compute_config = gen11_dsi_compute_config;
encoder->get_hw_state = gen11_dsi_get_hw_state;
encoder->type = INTEL_OUTPUT_DSI;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2d6ed990a232..d32865dc44e8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3548,6 +3548,8 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
*encoder,
intel_psr_enable(intel_dp, crtc_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
+
+ intel_panel_update_backlight(encoder, crtc_state, conn_state);
}
static void intel_ddi_update_pipe(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 62fd11540942..0cbacdc70b07 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6981,6 +6981,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->compute_config = intel_dp_compute_config;
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
+ intel_encoder->update_pipe = intel_panel_update_backlight;
intel_encoder->suspend = intel_dp_encoder_suspend;
if (IS_CHERRYVIEW(dev_priv)) {
intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1a11c2beb7f3..0a6fb42e2086 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2023,6 +2023,9 @@ int intel_panel_setup_backlight(struct drm_connector
*connector,
enum pipe pipe);
void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_panel_update_backlight(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
void intel_panel_disable_backlight(const struct drm_connector_state
*old_conn_state);
extern struct drm_display_mode *intel_find_panel_downclock(
struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index b85e195f7c8a..189693b4c5e8 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -909,6 +909,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
}
intel_encoder->get_hw_state = intel_lvds_get_hw_state;
intel_encoder->get_config = intel_lvds_get_config;
+ intel_encoder->update_pipe = intel_panel_update_backlight;
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector_attach_encoder(intel_connector, intel_encoder);
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index ee3e0842d542..f71b33cf1c97 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1087,20 +1087,11 @@ static void pwm_enable_backlight(const struct
intel_crtc_state *crtc_state,
intel_panel_actually_set_backlight(conn_state,
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dsi: Adjust crtc_clock for burst_mode_ratio
Hi, On 15-01-19 16:00, Ville Syrjälä wrote: On Sat, Dec 01, 2018 at 12:31:47PM +0100, Hans de Goede wrote: On devices with a burst_mode_ratio which is not 100 (1:1), the pclk will have a different value then drm_display_mode.clock . On a Prowise PT301 tablet where vbt.lfp_lvds_vbt_mode.clock is 66100 and burst_mode_ratio is 130 this leads to the following errors: [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 66100, found 86458) [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 66100, found 86458) [drm:pipe_config_err [i915]] *ERROR* mismatch in port_clock (expected 66100, found 86458) This commit makes intel_dsi_compute_config() set pipe_config.adjusted_mode.crtc_clock, taking the burst_mode_ratio into account fixing this. Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/vlv_dsi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c index c21cbfa9653c..d72ccf557a9c 100644 --- a/drivers/gpu/drm/i915/vlv_dsi.c +++ b/drivers/gpu/drm/i915/vlv_dsi.c @@ -347,6 +347,10 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, return false; } + adjusted_mode->crtc_clock = + DIV_ROUND_UP(adjusted_mode->crtc_clock * +intel_dsi->burst_mode_ratio, 100); Hmm. Won't this cause incorrect refresh rate to be used in eg. vblank timestmap calculations? I guess so. Note that this patch does not change any values actually written to the hardware. It seems that devices which actually use the burst mode are quite rare (this is the first one encounter in probably over 40 different byt/cht devices I've tested). I've a feeling that the entire pipeline is actually running at the higher rate and that the framerate really is 30% higher. Looking at the code, it seems that what a burst_mode_ratio of 130'does is make all the values in the "modeline" except for the visual area 30% larger, which means that we are probably already messing up the vblank calculations anyways, since using either the uncorrected or the corrected clock is wrong when using htotal from the original modeline, as looking at txbyteclkhs we will use bigger values for all drm_display_mode values except for the active region. I think that the right way to deal with this is to isolate the burst_ratio handling to intel_dsi_vbt.c and adjust the modeline coming from the VBT by multiplying the clock and all timing parameters (except h/vdisplay) there by the burst_ratio and then recalculating h/vtotal. This should lead to getting the vblank timestamp stuff right and allows removing of burst_mode_ratio from all code except for the vbt code. If that is too invasive, given that this setup is quite rate, then I suggest we just go with this patch. My main concern is fixing the WARN_ON. This patch successfully does that. OTOH if the pipe is really fetching data at the higher burst rate then we should rather want to calculate the watermarks/cdclk based on that higher rate. Right, the more I think about this, the more I believe calculating a new modeline correcting for burst_ratio inside the vbt code and dropping burst_mode_ratio handling everywhere else is the right thing to do. Regards, Hans ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915/lvds: nuke intel_lvds_supported()
Now that intel_lvds_init() is only called for platforms that might have
LVDS, move the remaining checks to intel_setup_outputs(), again similar
to other outputs, and remove the overlapping checks.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 6 --
drivers/gpu/drm/i915/intel_lvds.c| 23 ---
2 files changed, 4 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4b5704a87934..4207ee0b83ce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14464,7 +14464,8 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
} else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
bool found = false;
- intel_lvds_init(dev_priv);
+ if (IS_MOBILE(dev_priv))
+ intel_lvds_init(dev_priv);
if (dev_priv->vbt.int_crt_support)
intel_crt_init(dev_priv);
@@ -14501,7 +14502,8 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
intel_dp_init(dev_priv, DP_D, PORT_D);
} else if (IS_GEN(dev_priv, 2)) {
- intel_lvds_init(dev_priv);
+ if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
+ intel_lvds_init(dev_priv);
if (dev_priv->vbt.int_crt_support)
intel_crt_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 46a5dfd5cdf7..815ed463d9c5 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -798,26 +798,6 @@ static bool compute_is_dual_link_lvds(struct
intel_lvds_encoder *lvds_encoder)
return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
}
-static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
-{
- /*
-* With the introduction of the PCH we gained a dedicated
-* LVDS presence pin, use it.
-*/
- if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
- return true;
-
- /*
-* Otherwise LVDS was only attached to mobile products,
-* except for the inglorious 830gm
-*/
- if (INTEL_GEN(dev_priv) <= 4 &&
- IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
- return true;
-
- return false;
-}
-
/**
* intel_lvds_init - setup LVDS connectors on this device
* @dev_priv: i915 device
@@ -842,9 +822,6 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
u8 pin;
u32 allowed_scalers;
- if (!intel_lvds_supported(dev_priv))
- return;
-
/* Skip init on machines we know falsely report LVDS */
if (dmi_check_system(intel_no_lvds)) {
WARN(!dev_priv->vbt.int_lvds_support,
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915/lvds: only call intel_lvds_init() on platforms that might have LVDS
With new platforms not having LVDS support, only call intel_lvds_init()
on platforms that might actually have LVDS. Move the comment about eDP
init to the PCH block where it's relevant.
This puts intel_lvds_init() more in line with the rest of the outputs,
and makes it slightly easier for the uninitiated to figure out which
platforms actually have what.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e8bc297c60ab..4b5704a87934 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14310,13 +14310,6 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- /*
-* intel_edp_init_connector() depends on this completing first, to
-* prevent the registeration of both eDP and LVDS and the incorrect
-* sharing of the PPS.
-*/
- intel_lvds_init(dev_priv);
-
if (IS_ICELAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
@@ -14380,6 +14373,13 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
} else if (HAS_PCH_SPLIT(dev_priv)) {
int found;
+ /*
+* intel_edp_init_connector() depends on this completing first,
+* to prevent the registration of both eDP and LVDS and the
+* incorrect sharing of the PPS.
+*/
+ intel_lvds_init(dev_priv);
+
if (dev_priv->vbt.int_crt_support)
intel_crt_init(dev_priv);
@@ -14457,11 +14457,15 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
vlv_dsi_init(dev_priv);
} else if (IS_PINEVIEW(dev_priv)) {
+ intel_lvds_init(dev_priv);
+
if (dev_priv->vbt.int_crt_support)
intel_crt_init(dev_priv);
} else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
bool found = false;
+ intel_lvds_init(dev_priv);
+
if (dev_priv->vbt.int_crt_support)
intel_crt_init(dev_priv);
@@ -14497,6 +14501,8 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
intel_dp_init(dev_priv, DP_D, PORT_D);
} else if (IS_GEN(dev_priv, 2)) {
+ intel_lvds_init(dev_priv);
+
if (dev_priv->vbt.int_crt_support)
intel_crt_init(dev_priv);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: rename has_edp_a() to intel_pch_has_edp_a()
Clarify that the name is specific to PCH platforms.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6960004fdc94..32270d7b71b9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14231,7 +14231,7 @@ static int intel_encoder_clones(struct intel_encoder
*encoder)
return index_mask;
}
-static bool has_edp_a(struct drm_i915_private *dev_priv)
+static bool intel_pch_has_edp_a(struct drm_i915_private *dev_priv)
{
if (!IS_MOBILE(dev_priv))
return false;
@@ -14385,7 +14385,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
- if (has_edp_a(dev_priv))
+ if (intel_pch_has_edp_a(dev_priv))
intel_dp_init(dev_priv, DP_A, PORT_A);
if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915/tv: only call intel_tv_init() on platforms that might have TV
With most platforms not having TV support, only call intel_tv_init() on
platforms that might actually have TV, specifically gens 3 and 4.
This puts intel_tv_init() more in line with the rest of the outputs, and
makes it slightly easier for the uninitiated to figure out which
platforms actually have what.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4207ee0b83ce..6960004fdc94 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14501,6 +14501,9 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
intel_dp_init(dev_priv, DP_D, PORT_D);
+
+ if (SUPPORTS_TV(dev_priv))
+ intel_tv_init(dev_priv);
} else if (IS_GEN(dev_priv, 2)) {
if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
intel_lvds_init(dev_priv);
@@ -14511,9 +14514,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_dvo_init(dev_priv);
}
- if (SUPPORTS_TV(dev_priv))
- intel_tv_init(dev_priv);
-
intel_psr_init(dev_priv);
for_each_intel_encoder(_priv->drm, encoder) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915/crt: split out intel_crt_present() to platform specific setup
With new platforms not having CRT support and most conditions in
intel_crt_present() being specific to DDI, split out the CRT
initialization to platform specific blocks in the if ladder. Add new
Pineview block for this.
This puts intel_crt_init() more in line with the rest of the outputs,
and makes it slightly easier for the uninitiated to figure out which
platforms actually have what.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 37 ++--
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2fa9f4aec08e..e8bc297c60ab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14245,23 +14245,17 @@ static bool has_edp_a(struct drm_i915_private
*dev_priv)
return true;
}
-static bool intel_crt_present(struct drm_i915_private *dev_priv)
+static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 9)
- return false;
-
if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
return false;
- if (IS_CHERRYVIEW(dev_priv))
- return false;
-
if (HAS_PCH_LPT_H(dev_priv) &&
I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
return false;
/* DDI E can't be used if DDI A requires 4 lanes */
- if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
+ if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
return false;
if (!dev_priv->vbt.int_crt_support)
@@ -14323,9 +14317,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
*/
intel_lvds_init(dev_priv);
- if (intel_crt_present(dev_priv))
- intel_crt_init(dev_priv);
-
if (IS_ICELAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
@@ -14354,6 +14345,9 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
} else if (HAS_DDI(dev_priv)) {
int found;
+ if (intel_ddi_crt_present(dev_priv))
+ intel_crt_init(dev_priv);
+
/*
* Haswell uses DDI functions to detect digital outputs.
* On SKL pre-D0 the strap isn't connected, so we assume
@@ -14385,6 +14379,10 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
} else if (HAS_PCH_SPLIT(dev_priv)) {
int found;
+
+ if (dev_priv->vbt.int_crt_support)
+ intel_crt_init(dev_priv);
+
dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
if (has_edp_a(dev_priv))
@@ -14413,6 +14411,9 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
bool has_edp, has_port;
+ if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
+ intel_crt_init(dev_priv);
+
/*
* The DP_DETECTED bit is the latched state of the DDC
* SDA pin at boot. However since eDP doesn't require DDC
@@ -14455,9 +14456,15 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
}
vlv_dsi_init(dev_priv);
- } else if (!IS_GEN(dev_priv, 2) && !IS_PINEVIEW(dev_priv)) {
+ } else if (IS_PINEVIEW(dev_priv)) {
+ if (dev_priv->vbt.int_crt_support)
+ intel_crt_init(dev_priv);
+ } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
bool found = false;
+ if (dev_priv->vbt.int_crt_support)
+ intel_crt_init(dev_priv);
+
if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
DRM_DEBUG_KMS("probing SDVOB\n");
found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
@@ -14489,8 +14496,12 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
intel_dp_init(dev_priv, DP_D, PORT_D);
- } else if (IS_GEN(dev_priv, 2))
+ } else if (IS_GEN(dev_priv, 2)) {
+ if (dev_priv->vbt.int_crt_support)
+ intel_crt_init(dev_priv);
+
intel_dvo_init(dev_priv);
+ }
if (SUPPORTS_TV(dev_priv))
intel_tv_init(dev_priv);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [drm-intel:drm-intel-next-queued 2/2] drivers/gpu//drm/i915/i915_reset.c:689:13: error: format '%lld' expects argument of type 'long long int', but argument 5 has type 'unsigned int'
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: 9f58892ea9962002399132fd3f40c6a273f8d9e1
commit: 9f58892ea9962002399132fd3f40c6a273f8d9e1 [2/2] drm/i915: Pull all the
reset functionality together into i915_reset.c
config: i386-randconfig-x007-201903 (attached as .config)
compiler: gcc-8 (Debian 8.2.0-14) 8.2.0
reproduce:
git checkout 9f58892ea9962002399132fd3f40c6a273f8d9e1
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
In file included from include/linux/sched/mm.h:5,
from drivers/gpu//drm/i915/i915_reset.c:7:
drivers/gpu//drm/i915/i915_reset.c: In function 'reset_request':
>> drivers/gpu//drm/i915/i915_reset.c:689:13: error: format '%lld' expects
>> argument of type 'long long int', but argument 5 has type 'unsigned int'
>> [-Werror=format=]
GEM_TRACE("%s pardoned global=%d (fence %llx:%lld), current %d\n",
^~~
drivers/gpu//drm/i915/i915_reset.c:691:25:
rq->fence.context, rq->fence.seqno,
~~~
include/linux/kernel.h:683:33: note: in definition of macro
'__trace_printk_check_format'
trace_printk_check_format(fmt, ##args); \
^~~
include/linux/kernel.h:720:3: note: in expansion of macro 'do_trace_printk'
do_trace_printk(fmt, ##__VA_ARGS__); \
^~~
drivers/gpu//drm/i915/i915_gem.h:66:24: note: in expansion of macro
'trace_printk'
#define GEM_TRACE(...) trace_printk(__VA_ARGS__)
^~~~
drivers/gpu//drm/i915/i915_reset.c:689:3: note: in expansion of macro
'GEM_TRACE'
GEM_TRACE("%s pardoned global=%d (fence %llx:%lld), current %d\n",
^
drivers/gpu//drm/i915/i915_reset.c:689:13: error: format '%lld' expects
argument of type 'long long int', but argument 6 has type 'unsigned int'
[-Werror=format=]
GEM_TRACE("%s pardoned global=%d (fence %llx:%lld), current %d\n",
^~~
drivers/gpu//drm/i915/i915_reset.c:691:25:
rq->fence.context, rq->fence.seqno,
~~~
include/linux/kernel.h:736:29: note: in definition of macro 'do_trace_printk'
__trace_printk(_THIS_IP_, fmt, ##args); \
^~~
drivers/gpu//drm/i915/i915_gem.h:66:24: note: in expansion of macro
'trace_printk'
#define GEM_TRACE(...) trace_printk(__VA_ARGS__)
^~~~
drivers/gpu//drm/i915/i915_reset.c:689:3: note: in expansion of macro
'GEM_TRACE'
GEM_TRACE("%s pardoned global=%d (fence %llx:%lld), current %d\n",
^
drivers/gpu//drm/i915/i915_reset.c: In function 'nop_submit_request':
drivers/gpu//drm/i915/i915_reset.c:804:12: error: format '%lld' expects
argument of type 'long long int', but argument 4 has type 'unsigned int'
[-Werror=format=]
GEM_TRACE("%s fence %llx:%lld -> -EIO\n",
^~
drivers/gpu//drm/i915/i915_reset.c:806:29:
request->fence.context, request->fence.seqno);
include/linux/kernel.h:683:33: note: in definition of macro
'__trace_printk_check_format'
trace_printk_check_format(fmt, ##args); \
^~~
include/linux/kernel.h:720:3: note: in expansion of macro 'do_trace_printk'
do_trace_printk(fmt, ##__VA_ARGS__); \
^~~
drivers/gpu//drm/i915/i915_gem.h:66:24: note: in expansion of macro
'trace_printk'
#define GEM_TRACE(...) trace_printk(__VA_ARGS__)
^~~~
drivers/gpu//drm/i915/i915_reset.c:804:2: note: in expansion of macro
'GEM_TRACE'
GEM_TRACE("%s fence %llx:%lld -> -EIO\n",
^
drivers/gpu//drm/i915/i915_reset.c:804:12: error: format '%lld' expects
argument of type 'long long int', but argument 5 has type 'unsigned int'
[-Werror=format=]
GEM_TRACE("%s fence %llx:%lld -> -EIO\n",
^~
drivers/gpu//drm/i915/i915_reset.c:806:29:
request->fence.context, request->fence.seqno);
include/linux/kernel.h:736:29: note: in definition of macro 'do_trace_printk'
__trace_printk(_THIS_IP_, fmt, ##args); \
^~~
drivers/gpu//drm/i915/i915_gem.h:66:24: note: in expansion of macro
'trace_printk'
#define GEM_TRACE(...) trace_printk(__VA_ARGS__)
^~~~
drivers/gpu//drm/i915/i915_reset.c:804:2: note: in expansion of macro
'GEM_TRACE'
GEM_TRACE("%s fence %llx:%lld -> -EIO\n",
^
cc1: all warnings being treated as errors
vim +689 drivers/gpu//drm/i915/i915_reset.c
659
660
Re: [Intel-gfx] [PATCH 5/6] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
On 15.1.2019 16.47, Joonas Lahtinen wrote:
> From: Tvrtko Ursulin
>
> We want to allow userspace to reconfigure the subslice configuration on a
> per context basis.
>
> This is required for the functional requirement of shutting down non-VME
> enabled sub-slices on Gen11 parts.
>
> To do so, we expose a context parameter to allow adjustment of the RPCS
> register stored within the context image (and currently not accessible via
> LRI).
>
> If the context is adjusted before first use or whilst idle, the adjustment
> is for "free"; otherwise if the context is active we queue a request to do
> so (using the kernel context), following all other activity by that
> context, which is also marked as barrier for all following submission
> against the same context.
>
> Since the overhead of device re-configuration during context switching can
> be significant, especially in multi-context workloads, we limit this new
> uAPI to only support the Gen11 VME use case. In this use case either the
> device is fully enabled, and exactly one slice and half of the subslices
> are enabled.
>
> Example usage:
>
> struct drm_i915_gem_context_param_sseu sseu = { };
> struct drm_i915_gem_context_param arg =
> { .param = I915_CONTEXT_PARAM_SSEU,
> .ctx_id = gem_context_create(fd),
> .size = sizeof(sseu),
> .value = to_user_pointer()
> };
>
> /* Query device defaults. */
> gem_context_get_param(fd, );
>
> /* Set VME configuration on a 1x6x8 part. */
> sseu.slice_mask = 0x1;
> sseu.subslice_mask = 0xe0;
> gem_context_set_param(fd, );
>
> v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
>
> v3: Add ability to program this per engine (Chris)
>
> v4: Move most get_sseu() into i915_gem_context.c (Lionel)
>
> v5: Validate sseu configuration against the device's capabilities (Lionel)
>
> v6: Change context powergating settings through MI_SDM on kernel context
> (Chris)
>
> v7: Synchronize the requests following a powergating setting change using a
> global
> dependency (Chris)
> Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
> Disable RPCS configuration setting for non capable users (Lionel/Tvrtko)
>
> v8: s/union intel_sseu/struct intel_sseu/ (Lionel)
> s/dev_priv/i915/ (Tvrtko)
> Change uapi class/instance fields to u16 (Tvrtko)
> Bump mask fields to 64bits (Lionel)
> Don't return EPERM when dynamic sseu is disabled (Tvrtko)
>
> v9: Import context image into kernel context's ppgtt only when
> reconfiguring powergated slice/subslices (Chris)
> Use aliasing ppgtt when needed (Michel)
>
> Tvrtko Ursulin:
>
> v10:
> * Update for upstream changes.
> * Request submit needs a RPM reference.
> * Reject on !FULL_PPGTT for simplicity.
> * Pull out get/set param to helpers for readability and less indent.
> * Use i915_request_await_dma_fence in add_global_barrier to skip waits
>on the same timeline and avoid GEM_BUG_ON.
> * No need to explicitly assign a NULL pointer to engine in legacy mode.
> * No need to move gen8_make_rpcs up.
> * Factored out global barrier as prep patch.
> * Allow to only CAP_SYS_ADMIN if !Gen11.
>
> v11:
> * Remove engine vfunc in favour of local helper. (Chris Wilson)
> * Stop retiring requests before updates since it is not needed
>(Chris Wilson)
> * Implement direct CPU update path for idle contexts. (Chris Wilson)
> * Left side dependency needs only be on the same context timeline.
>(Chris Wilson)
> * It is sufficient to order the timeline. (Chris Wilson)
> * Reject !RCS configuration attempts with -ENODEV for now.
>
> v12:
> * Rebase for make_rpcs.
>
> v13:
> * Centralize SSEU normalization to make_rpcs.
> * Type width checking (uAPI <-> implementation).
> * Gen11 restrictions uAPI checks.
> * Gen11 subslice count differences handling.
> Chris Wilson:
> * args->size handling fixes.
> * Update context image from GGTT.
> * Postpone context image update to pinning.
> * Use i915_gem_active_raw instead of last_request_on_engine.
>
> v14:
> * Add activity tracker on intel_context to fix the lifetime issues
>and simplify the code. (Chris Wilson)
>
> v15:
> * Fix context pin leak if no space in ring by simplifying the
>context pinning sequence.
>
> v16:
> * Rebase for context get/set param locking changes.
> * Just -ENODEV on !Gen11. (Joonas)
>
> v17:
> * Fix one Gen11 subslice enablement rule.
> * Handle error from i915_sw_fence_await_sw_fence_gfp. (Chris Wilson)
>
> v18:
> * Update commit message. (Joonas)
> * Restrict uAPI to VME use case. (Joonas)
>
> v19:
> * Rebase.
>
> v20:
> * Rebase for ce->active_tracker.
>
> v21:
> * Rebase for IS_GEN changes.
>
> v22:
> * Reserve uAPI for flags straight away. (Chris Wilson)
>
> v23:
> * Rebase for RUNTIME_INFO.
>
> v24:
> * Added some headline docs for the uapi usage. (Joonas/Chris)
>
>
