Re: [Intel-gfx] [PATCH 19/26] drm/qxl: Use drm_fb_helper_fill_info
On Thu, Jan 24, 2019 at 05:58:24PM +0100, Daniel Vetter wrote: > This should not result in any changes. I'd love to merge https://patchwork.freedesktop.org/series/53951/ instead (which will -- among other things -- switch qxl over to the generic fbdev emulation and remove the code you are patching here). Anyone willing to review? Dave? thanks, Gerd ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/33] drm/i915/execlists: Move RPCS setup to context pin
== Series Details ==
Series: series starting with [01/33] drm/i915/execlists: Move RPCS setup to
context pin
URL : https://patchwork.freedesktop.org/series/55708/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5478 -> Patchwork_12035
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12035 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12035, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55708/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12035:
### IGT changes ###
Possible regressions
* igt@gem_ctx_create@basic-files:
- fi-cfl-guc: PASS -> DMESG-WARN
- fi-kbl-guc: PASS -> DMESG-WARN
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ringfill@basic-default-fd:
- {fi-icl-u3}:PASS -> INCOMPLETE
- {fi-icl-u2}:PASS -> INCOMPLETE
Known issues
Here are the changes found in Patchwork_12035 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: PASS -> FAIL [fdo#108767]
* igt@pm_rpm@module-reload:
- fi-hsw-4770:NOTRUN -> INCOMPLETE [fdo#107807]
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: PASS -> FAIL [fdo#104008]
Possible fixes
* igt@i915_module_load@reload:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:DMESG-FAIL [fdo#108735] -> PASS
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (44 -> 40)
--
Additional (1): fi-hsw-4770
Missing(5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-pnv-d510
Build changes
-
* Linux: CI_DRM_5478 -> Patchwork_12035
CI_DRM_5478: c6308f6a6b019fbea6c4179e2668f1e38b673eab @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4790: dcdf4b04e16312f8f52ad389388d834f9d74b8f0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12035: 008bb53558465c1b58c4be2368a7e206943a1dff @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
008bb5355846 drm/i915: Prioritise non-busywait semaphore workloads
a8ca508c4233 drm/i915: Use HW semaphores for inter-engine synchronisation on
gen8+
1ed416939ae4 drm/i915/execlists: Refactor out can_merge_rq()
3b1ab1239de6 drm/i915: Keep timeline HWSP allocated until the system is idle
174f53eceb3f drm/i915: Implement an "idle" barrier
a265ac2617cc drm/i915: Drop fake breadcrumb irq
e94b3cd6cc75 drm/i915: Replace global breadcrumbs with per-context interrupt
tracking
cf16be448222 drm/i915: Remove the intel_engine_notify tracepoint
67501f1cc318 drm/i915: Identify active requests
083196e5154c drm/i915: Track active timelines
4bd03fef836a drm/i915: Track the context's seqno in its own timeline HWSP
9b0e47a0b162 drm/i915: Share per-timeline HWSP using a slab suballocator
83d209a5ffec drm/i915: Allocate a status page for each timeline
2d8b70963a93 drm/i915: Enlarge vma->pin_count
5263a04ba167 drm/i915: Introduce concept of per-timeline (context) HWSP
ca873c95645e drm/i915: Move list of timelines under its own lock
a2ba7cb66608 drm/i915: Add timeline barrier support
56860703e5fd drm/i915: Always
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/33] drm/i915/execlists: Move RPCS setup to context pin
== Series Details == Series: series starting with [01/33] drm/i915/execlists: Move RPCS setup to context pin URL : https://patchwork.freedesktop.org/series/55708/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Move RPCS setup to context pin Okay! Commit: drm/i915: Measure the required reserved size for request emission Okay! Commit: drm/i915: Remove manual breadcumb counting Okay! Commit: drm/i915: Compute the HWS offsets explicitly Okay! Commit: drm/i915/execlists: Suppress preempting self -drivers/gpu/drm/i915/intel_ringbuffer.h:602:23: warning: expression using sizeof(void) Commit: drm/i915/execlists: Suppress redundant preemption Okay! Commit: drm/i915/selftests: Apply a subtest filter Okay! Commit: drm/i915: Make all GPU resets atomic Okay! Commit: drm/i915/guc: Disable global reset Okay! Commit: drm/i915: Remove GPU reset dependence on struct_mutex -drivers/gpu/drm/i915/selftests/../i915_drv.h:3546:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3541:16: warning: expression using sizeof(void) Commit: drm/i915/selftests: Trim struct_mutex duration for set-wedged selftest Okay! Commit: drm/i915: Issue engine resets onto idle engines Okay! Commit: drm/i915: Stop tracking MRU activity on VMA Okay! Commit: drm/i915: Pull VM lists under the VM mutex. Okay! Commit: drm/i915: Move vma lookup to its own lock Okay! Commit: drm/i915: Always allocate an object/vma for the HWSP Okay! Commit: drm/i915: Add timeline barrier support Okay! Commit: drm/i915: Move list of timelines under its own lock -drivers/gpu/drm/i915/selftests/../i915_drv.h:3541:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3544:16: warning: expression using sizeof(void) Commit: drm/i915: Introduce concept of per-timeline (context) HWSP Okay! Commit: drm/i915: Enlarge vma->pin_count Okay! Commit: drm/i915: Allocate a status page for each timeline +./include/linux/mm.h:619:13: error: not a function +./include/linux/mm.h:619:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/mm.h:619:13: warning: call with no type! Commit: drm/i915: Share per-timeline HWSP using a slab suballocator -drivers/gpu/drm/i915/selftests/../i915_drv.h:3544:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_timeline.c:89:38: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_timeline.c:89:38: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_timeline.c:92:44: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_timeline.c:92:44: warning: expression using sizeof(void) +./include/linux/slab.h:664:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:664:13: warning: call with no type! Commit: drm/i915: Track the context's seqno in its own timeline HWSP Okay! Commit: drm/i915: Track active timelines Okay! Commit: drm/i915: Identify active requests Okay! Commit: drm/i915: Remove the intel_engine_notify tracepoint Okay! Commit: drm/i915: Replace global breadcrumbs with per-context interrupt tracking +drivers/gpu/drm/i915/selftests/i915_request.c:280:40: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_request.c:280:40: warning: expression using sizeof(void) -./include/linux/mm.h:619:13: error: not a function -./include/linux/mm.h:619:13: error: not a function -./include/linux/mm.h:619:13: error: undefined identifier '__builtin_mul_overflow' -./include/linux/mm.h:619:13: warning: call with no type! +./include/linux/slab.h:664:13: error: not a function +./include/linux/slab.h:664:13: error: not a function Commit: drm/i915: Drop fake breadcrumb irq Okay! Commit: drm/i915: Implement an "idle" barrier -drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3553:16: warning: expression using sizeof(void) Commit: drm/i915: Keep timeline HWSP allocated until the system is idle Okay! Commit: drm/i915/execlists: Refactor out can_merge_rq() Okay! Commit: drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ Okay! Commit: drm/i915: Prioritise non-busywait semaphore workloads Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/33] drm/i915/execlists: Move RPCS setup to context pin
== Series Details ==
Series: series starting with [01/33] drm/i915/execlists: Move RPCS setup to
context pin
URL : https://patchwork.freedesktop.org/series/55708/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6abb3bdb8c37 drm/i915/execlists: Move RPCS setup to context pin
44e01a9b8ba3 drm/i915: Measure the required reserved size for request emission
a8be5f976f88 drm/i915: Remove manual breadcumb counting
b4de6f7897c8 drm/i915: Compute the HWS offsets explicitly
2ba1c33378f9 drm/i915/execlists: Suppress preempting self
-:22: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#22:
References: a2bf92e8cc16 ("drm/i915/execlists: Avoid kicking priority on the
current context")
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit a2bf92e8cc16
("drm/i915/execlists: Avoid kicking priority on the current context")'
#22:
References: a2bf92e8cc16 ("drm/i915/execlists: Avoid kicking priority on the
current context")
total: 1 errors, 1 warnings, 0 checks, 156 lines checked
d23882a69bf8 drm/i915/execlists: Suppress redundant preemption
f6a7e760a383 drm/i915/selftests: Apply a subtest filter
6a91ea6fd2c7 drm/i915: Make all GPU resets atomic
-:33: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.txt
#33: FILE: drivers/gpu/drm/i915/i915_reset.c:149:
+ udelay(50);
-:39: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.txt
#39: FILE: drivers/gpu/drm/i915/i915_reset.c:154:
+ udelay(50);
total: 0 errors, 0 warnings, 2 checks, 176 lines checked
6955a17b590b drm/i915/guc: Disable global reset
0e46060a69ff drm/i915: Remove GPU reset dependence on struct_mutex
-:1279: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield. Prefer bool
bitfields as unsigned int or u<8|16|32>
#1279: FILE: drivers/gpu/drm/i915/intel_hangcheck.c:35:
+ bool wedged:1;
-:1280: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield. Prefer bool
bitfields as unsigned int or u<8|16|32>
#1280: FILE: drivers/gpu/drm/i915/intel_hangcheck.c:36:
+ bool stalled:1;
total: 0 errors, 2 warnings, 0 checks, 1705 lines checked
4f8bac3aae86 drm/i915/selftests: Trim struct_mutex duration for set-wedged
selftest
54d87f290739 drm/i915: Issue engine resets onto idle engines
ceab76765075 drm/i915: Stop tracking MRU activity on VMA
0f21396816a4 drm/i915: Pull VM lists under the VM mutex.
fdb647847171 drm/i915: Move vma lookup to its own lock
-:161: WARNING:USE_SPINLOCK_T: struct spinlock should be spinlock_t
#161: FILE: drivers/gpu/drm/i915/i915_gem_object.h:94:
+ struct spinlock lock;
total: 0 errors, 1 warnings, 0 checks, 290 lines checked
56860703e5fd drm/i915: Always allocate an object/vma for the HWSP
a2ba7cb66608 drm/i915: Add timeline barrier support
ca873c95645e drm/i915: Move list of timelines under its own lock
5263a04ba167 drm/i915: Introduce concept of per-timeline (context) HWSP
2d8b70963a93 drm/i915: Enlarge vma->pin_count
83d209a5ffec drm/i915: Allocate a status page for each timeline
9b0e47a0b162 drm/i915: Share per-timeline HWSP using a slab suballocator
-:79: CHECK:SPACING: No space is necessary after a cast
#79: FILE: drivers/gpu/drm/i915/i915_timeline.c:43:
+ BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
total: 0 errors, 0 warnings, 1 checks, 415 lines checked
4bd03fef836a drm/i915: Track the context's seqno in its own timeline HWSP
083196e5154c drm/i915: Track active timelines
67501f1cc318 drm/i915: Identify active requests
cf16be448222 drm/i915: Remove the intel_engine_notify tracepoint
e94b3cd6cc75 drm/i915: Replace global breadcrumbs with per-context interrupt
tracking
-:18: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 688e6c725816 ("drm/i915:
Slaughter the thundering i915_wait_request herd")'
#18:
Before commit 688e6c725816, the solution was simple. Every client waking
-:21: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 688e6c725816 ("drm/i915:
Slaughter the thundering i915_wait_request herd")'
#21:
688e6c725816 introduced an rbtree so that only the earliest waiter on
-:55: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#55:
References: 688e6c725816 ("drm/i915: Slaughter the thundering i915_wait_request
herd")
-:55: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 688e6c725816 ("drm/i915:
Slaughter the thundering i915_wait_request herd")'
#55:
References: 688e6c725816 ("drm/i915: Slaughter the thundering i915_wait_request
herd")
-:2179: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
i915_gem_context *' should also have an identifier name
#2179: FILE:
[Intel-gfx] [PATCH 15/33] drm/i915: Move vma lookup to its own lock
Remove the struct_mutex requirement for looking up the vma for an
object.
v2: Highlight how the race for duplicate vma creation is resolved on
reacquiring the lock with a short comment.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_gem.c | 33 +++-
drivers/gpu/drm/i915/i915_gem_object.h| 45 +---
drivers/gpu/drm/i915/i915_vma.c | 66 ---
drivers/gpu/drm/i915/i915_vma.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 4 +-
6 files changed, 98 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3b995f9fdc06..b64f758803f3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -160,14 +160,14 @@ describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj)
obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
if (obj->base.name)
seq_printf(m, " (name: %d)", obj->base.name);
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (i915_vma_is_pinned(vma))
pin_count++;
}
seq_printf(m, " (pinned x %d)", pin_count);
if (obj->pin_global)
seq_printf(m, " (global)");
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (!drm_mm_node_allocated(>node))
continue;
@@ -323,7 +323,7 @@ static int per_file_stats(int id, void *ptr, void *data)
if (obj->base.name || obj->base.dma_buf)
stats->shared += obj->base.size;
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (!drm_mm_node_allocated(>node))
continue;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 111a047a45b7..653c7ba4c69f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -439,15 +439,19 @@ int i915_gem_object_unbind(struct drm_i915_gem_object
*obj)
if (ret)
return ret;
- while ((vma = list_first_entry_or_null(>vma_list,
- struct i915_vma,
- obj_link))) {
+ spin_lock(>vma.lock);
+ while (!ret && (vma = list_first_entry_or_null(>vma.list,
+ struct i915_vma,
+ obj_link))) {
list_move_tail(>obj_link, _in_list);
+ spin_unlock(>vma.lock);
+
ret = i915_vma_unbind(vma);
- if (ret)
- break;
+
+ spin_lock(>vma.lock);
}
- list_splice(_in_list, >vma_list);
+ list_splice(_in_list, >vma.list);
+ spin_unlock(>vma.lock);
return ret;
}
@@ -3491,7 +3495,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
* reading an invalid PTE on older architectures.
*/
restart:
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (!drm_mm_node_allocated(>node))
continue;
@@ -3569,7 +3573,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
*/
}
- list_for_each_entry(vma, >vma_list, obj_link) {
+ list_for_each_entry(vma, >vma.list, obj_link) {
if (!drm_mm_node_allocated(>node))
continue;
@@ -3579,7 +3583,7 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
}
}
- list_for_each_entry(vma, >vma_list, obj_link)
+ list_for_each_entry(vma, >vma.list, obj_link)
vma->node.color = cache_level;
i915_gem_object_set_cache_coherency(obj, cache_level);
obj->cache_dirty = true; /* Always invalidate stale cachelines */
@@ -4155,7 +4159,9 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
{
mutex_init(>mm.lock);
- INIT_LIST_HEAD(>vma_list);
+ spin_lock_init(>vma.lock);
+ INIT_LIST_HEAD(>vma.list);
+
INIT_LIST_HEAD(>lut_list);
INIT_LIST_HEAD(>batch_pool_link);
@@ -4321,14 +4327,13 @@ static void __i915_gem_free_objects(struct
drm_i915_private *i915,
mutex_lock(>drm.struct_mutex);
GEM_BUG_ON(i915_gem_object_is_active(obj));
- list_for_each_entry_safe(vma, vn,
->vma_list, obj_link) {
+ list_for_each_entry_safe(vma, vn, >vma.list,
[Intel-gfx] [PATCH 20/33] drm/i915: Enlarge vma->pin_count
Previously we only accommodated having a vma pinned by a small number of
users, with the maximum being pinned for use by the display engine. As
such, we used a small bitfield only large enough to allow the vma to
be pinned twice (for back/front buffers) in each scanout plane. Keeping
the maximum permissible pin_count small allows us to quickly catch a
potential leak. However, as we want to split a 4096B page into 64
different cachelines and pin each cacheline for use by a different
timeline, we will exceed the current maximum permissible vma->pin_count
and so time has come to enlarge it.
Whilst we are here, try to pull together the similar bits:
Address/layout specification:
- bias, mappable, zone_4g: address limit specifiers
- fixed: address override, limits still apply though
- high: not strictly an address limit, but an address direction to search
Search controls:
- nonblock, nonfault, noevict
v2: Rewrite the guideline comment on bit consumption.
Signed-off-by: Chris Wilson
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 26 -
drivers/gpu/drm/i915/i915_vma.h | 45 +++--
2 files changed, 42 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index bd679c8c56dd..03ade71b8d9a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -642,19 +642,19 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
/* Flags used by pin/bind */
#define PIN_NONBLOCK BIT_ULL(0)
-#define PIN_MAPPABLE BIT_ULL(1)
-#define PIN_ZONE_4GBIT_ULL(2)
-#define PIN_NONFAULT BIT_ULL(3)
-#define PIN_NOEVICTBIT_ULL(4)
-
-#define PIN_MBZBIT_ULL(5) /* I915_VMA_PIN_OVERFLOW */
-#define PIN_GLOBAL BIT_ULL(6) /* I915_VMA_GLOBAL_BIND */
-#define PIN_USER BIT_ULL(7) /* I915_VMA_LOCAL_BIND */
-#define PIN_UPDATE BIT_ULL(8)
-
-#define PIN_HIGH BIT_ULL(9)
-#define PIN_OFFSET_BIASBIT_ULL(10)
-#define PIN_OFFSET_FIXED BIT_ULL(11)
+#define PIN_NONFAULT BIT_ULL(1)
+#define PIN_NOEVICTBIT_ULL(2)
+#define PIN_MAPPABLE BIT_ULL(3)
+#define PIN_ZONE_4GBIT_ULL(4)
+#define PIN_HIGH BIT_ULL(5)
+#define PIN_OFFSET_BIASBIT_ULL(6)
+#define PIN_OFFSET_FIXED BIT_ULL(7)
+
+#define PIN_MBZBIT_ULL(8) /* I915_VMA_PIN_OVERFLOW */
+#define PIN_GLOBAL BIT_ULL(9) /* I915_VMA_GLOBAL_BIND */
+#define PIN_USER BIT_ULL(10) /* I915_VMA_LOCAL_BIND */
+#define PIN_UPDATE BIT_ULL(11)
+
#define PIN_OFFSET_MASK(-I915_GTT_PAGE_SIZE)
#endif
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 7252abc73d3e..5793abe509a2 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -71,29 +71,42 @@ struct i915_vma {
unsigned int open_count;
unsigned long flags;
/**
-* How many users have pinned this object in GTT space. The following
-* users can each hold at most one reference: pwrite/pread, execbuffer
-* (objects are not allowed multiple times for the same batchbuffer),
-* and the framebuffer code. When switching/pageflipping, the
-* framebuffer code has at most two buffers pinned per crtc.
+* How many users have pinned this object in GTT space.
*
-* In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
-* bits with absolutely no headroom. So use 4 bits.
+* This is a tightly bound, fairly small number of users, so we
+* stuff inside the flags field so that we can both check for overflow
+* and detect a no-op i915_vma_pin() in a single check, while also
+* pinning the vma.
+*
+* The worst case display setup would have the same vma pinned for
+* use on each plane on each crtc, while also building the next atomic
+* state and holding a pin for the length of the cleanup queue. In the
+* future, the flip queue may be increased from 1.
+* Estimated worst case: 3 [qlen] * 4 [max crtcs] * 7 [max planes] = 84
+*
+* For GEM, the number of concurrent users for pwrite/pread is
+* unbounded. For execbuffer, it is currently one but will in future
+* be extended to allow multiple clients to pin vma concurrently.
+*
+* We also use suballocated pages, with each suballocation claiming
+* its own pin on the shared vma. At present, this is limited to
+* exclusive cachelines of a single page, so a maximum of 64 possible
+* users.
*/
-#define I915_VMA_PIN_MASK 0xf
-#define I915_VMA_PIN_OVERFLOW BIT(5)
+#define I915_VMA_PIN_MASK 0xff
+#define I915_VMA_PIN_OVERFLOW BIT(8)
/**
[Intel-gfx] [PATCH 12/33] drm/i915: Issue engine resets onto idle engines
Always perform the requested reset, even if we believe the engine is
idle. Presumably there was a reason the caller wanted the reset, and in
the near future we lose the easy tracking for whether the engine is
idle.
Signed-off-by: Chris Wilson
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_reset.c | 4
.../gpu/drm/i915/selftests/intel_hangcheck.c | 22 +--
2 files changed, 6 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index c01acc832518..7299b4f0d6d7 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -1067,10 +1067,6 @@ int i915_reset_engine(struct intel_engine_cs *engine,
const char *msg)
GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >flags));
- if (i915_seqno_passed(intel_engine_get_seqno(engine),
- intel_engine_last_submit(engine)))
- return 0;
-
reset_prepare_engine(engine);
if (msg)
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 8025c7e0bf6c..2c38ea5892d9 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -449,8 +449,6 @@ static int __igt_reset_engine(struct drm_i915_private
*i915, bool active)
set_bit(I915_RESET_ENGINE + id, >gpu_error.flags);
do {
- u32 seqno = intel_engine_get_seqno(engine);
-
if (active) {
struct i915_request *rq;
@@ -479,8 +477,6 @@ static int __igt_reset_engine(struct drm_i915_private
*i915, bool active)
break;
}
- GEM_BUG_ON(!rq->global_seqno);
- seqno = rq->global_seqno - 1;
i915_request_put(rq);
}
@@ -496,11 +492,10 @@ static int __igt_reset_engine(struct drm_i915_private
*i915, bool active)
break;
}
- reset_engine_count += active;
if (i915_reset_engine_count(>gpu_error, engine) !=
- reset_engine_count) {
- pr_err("%s engine reset %srecorded!\n",
- engine->name, active ? "not " : "");
+ ++reset_engine_count) {
+ pr_err("%s engine reset not recorded!\n",
+ engine->name);
err = -EINVAL;
break;
}
@@ -728,7 +723,6 @@ static int __igt_reset_engines(struct drm_i915_private
*i915,
set_bit(I915_RESET_ENGINE + id, >gpu_error.flags);
do {
- u32 seqno = intel_engine_get_seqno(engine);
struct i915_request *rq = NULL;
if (flags & TEST_ACTIVE) {
@@ -756,9 +750,6 @@ static int __igt_reset_engines(struct drm_i915_private
*i915,
err = -EIO;
break;
}
-
- GEM_BUG_ON(!rq->global_seqno);
- seqno = rq->global_seqno - 1;
}
err = i915_reset_engine(engine, NULL);
@@ -795,10 +786,9 @@ static int __igt_reset_engines(struct drm_i915_private
*i915,
reported = i915_reset_engine_count(>gpu_error, engine);
reported -= threads[engine->id].resets;
- if (reported != (flags & TEST_ACTIVE ? count : 0)) {
- pr_err("i915_reset_engine(%s:%s): reset %lu times, but
reported %lu, expected %lu reported\n",
- engine->name, test_name, count, reported,
- (flags & TEST_ACTIVE ? count : 0));
+ if (reported != count) {
+ pr_err("i915_reset_engine(%s:%s): reset %lu times, but
reported %lu\n",
+ engine->name, test_name, count, reported);
if (!err)
err = -EINVAL;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 26/33] drm/i915: Remove the intel_engine_notify tracepoint
The global seqno is defunct and so we have no meaningful indicator of
forward progress for an engine. You need to listen to the request
signaling tracepoints instead.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 2 --
drivers/gpu/drm/i915/i915_trace.h | 25 -
2 files changed, 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7e56611b3d60..bedac6c14928 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1211,8 +1211,6 @@ static void notify_ring(struct intel_engine_cs *engine)
wake_up_process(tsk);
rcu_read_unlock();
-
- trace_intel_engine_notify(engine, wait);
}
static void vlv_c0_read(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 43da14f08dc0..eab313c3163c 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -752,31 +752,6 @@ trace_i915_request_out(struct i915_request *rq)
#endif
#endif
-TRACE_EVENT(intel_engine_notify,
- TP_PROTO(struct intel_engine_cs *engine, bool waiters),
- TP_ARGS(engine, waiters),
-
- TP_STRUCT__entry(
-__field(u32, dev)
-__field(u16, class)
-__field(u16, instance)
-__field(u32, seqno)
-__field(bool, waiters)
-),
-
- TP_fast_assign(
- __entry->dev = engine->i915->drm.primary->index;
- __entry->class = engine->uabi_class;
- __entry->instance = engine->instance;
- __entry->seqno = intel_engine_get_seqno(engine);
- __entry->waiters = waiters;
- ),
-
- TP_printk("dev=%u, engine=%u:%u, seqno=%u, waiters=%u",
- __entry->dev, __entry->class, __entry->instance,
- __entry->seqno, __entry->waiters)
-);
-
DEFINE_EVENT(i915_request, i915_request_retire,
TP_PROTO(struct i915_request *rq),
TP_ARGS(rq)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/33] drm/i915: Stop tracking MRU activity on VMA
Our goal is to remove struct_mutex and replace it with fine grained
locking. One of the thorny issues is our eviction logic for reclaiming
space for an execbuffer (or GTT mmaping, among a few other examples).
While eviction itself is easy to move under a per-VM mutex, performing
the activity tracking is less agreeable. One solution is not to do any
MRU tracking and do a simple coarse evaluation during eviction of
active/inactive, with a loose temporal ordering of last
insertion/evaluation. That keeps all the locking constrained to when we
are manipulating the VM itself, neatly avoiding the tricky handling of
possible recursive locking during execbuf and elsewhere.
Note that discarding the MRU (currently implemented as a pair of lists,
to avoid scanning the active list for a NONBLOCKING search) is unlikely
to impact upon our efficiency to reclaim VM space (where we think a LRU
model is best) as our current strategy is to use random idle replacement
first before doing a search, and over time the use of softpinned 48b
per-ppGTT is growing (thereby eliminating any need to perform any eviction
searches, in theory at least) with the remaining users being found on
much older devices (gen2-gen6).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 10 +--
drivers/gpu/drm/i915/i915_gem_evict.c | 71 ---
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 26 +--
drivers/gpu/drm/i915/i915_gem_shrinker.c | 8 ++-
drivers/gpu/drm/i915/i915_gem_stolen.c| 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 37 +-
drivers/gpu/drm/i915/i915_vma.c | 9 +--
.../gpu/drm/i915/selftests/i915_gem_evict.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
10 files changed, 84 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index dcbe644869b3..12a0a80bc989 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -255,10 +255,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void
*data,
pinned = ggtt->vm.reserved;
mutex_lock(>struct_mutex);
- list_for_each_entry(vma, >vm.active_list, vm_link)
- if (i915_vma_is_pinned(vma))
- pinned += vma->node.size;
- list_for_each_entry(vma, >vm.inactive_list, vm_link)
+ list_for_each_entry(vma, >vm.bound_list, vm_link)
if (i915_vma_is_pinned(vma))
pinned += vma->node.size;
mutex_unlock(>struct_mutex);
@@ -1541,13 +1538,10 @@ static void i915_gem_object_bump_inactive_ggtt(struct
drm_i915_gem_object *obj)
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
for_each_ggtt_vma(vma, obj) {
- if (i915_vma_is_active(vma))
- continue;
-
if (!drm_mm_node_allocated(>node))
continue;
- list_move_tail(>vm_link, >vm->inactive_list);
+ list_move_tail(>vm_link, >vm->bound_list);
}
i915 = to_i915(obj->base.dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index f6855401f247..5cfe4b75e7d6 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -126,14 +126,10 @@ i915_gem_evict_something(struct i915_address_space *vm,
struct drm_i915_private *dev_priv = vm->i915;
struct drm_mm_scan scan;
struct list_head eviction_list;
- struct list_head *phases[] = {
- >inactive_list,
- >active_list,
- NULL,
- }, **phase;
struct i915_vma *vma, *next;
struct drm_mm_node *node;
enum drm_mm_insert_mode mode;
+ struct i915_vma *active;
int ret;
lockdep_assert_held(>i915->drm.struct_mutex);
@@ -169,17 +165,46 @@ i915_gem_evict_something(struct i915_address_space *vm,
*/
if (!(flags & PIN_NONBLOCK))
i915_retire_requests(dev_priv);
- else
- phases[1] = NULL;
search_again:
+ active = NULL;
INIT_LIST_HEAD(_list);
- phase = phases;
- do {
- list_for_each_entry(vma, *phase, vm_link)
- if (mark_free(, vma, flags, _list))
- goto found;
- } while (*++phase);
+ list_for_each_entry_safe(vma, next, >bound_list, vm_link) {
+ /*
+* We keep this list in a rough least-recently scanned order
+* of active elements (inactive elements are cheap to reap).
+* New entries are added to the end, and we move anything we
+* scan to the end. The assumption is that the working set
+* of applications is either steady state (and thanks to the
+* userspace bo cache
[Intel-gfx] [PATCH 10/33] drm/i915: Remove GPU reset dependence on struct_mutex
Now that the submission backends are controlled via their own spinlocks,
with a wave of a magic wand we can lift the struct_mutex requirement
around GPU reset. That is we allow the submission frontend (userspace)
to keep on submitting while we process the GPU reset as we can suspend
the backend independently.
The major change is around the backoff/handoff strategy for performing
the reset. With no mutex deadlock, we no longer have to coordinate with
any waiter, and just perform the reset immediately.
Testcase: igt/gem_mmap_gtt/hang # regresses
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 38 +-
drivers/gpu/drm/i915/i915_drv.h | 5 -
drivers/gpu/drm/i915/i915_gem.c | 18 +-
drivers/gpu/drm/i915/i915_gem_fence_reg.h | 1 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 104 +++--
drivers/gpu/drm/i915/i915_gpu_error.h | 28 +-
drivers/gpu/drm/i915/i915_request.c | 47 ---
drivers/gpu/drm/i915/i915_reset.c | 383 --
drivers/gpu/drm/i915/i915_reset.h | 3 +
drivers/gpu/drm/i915/intel_engine_cs.c| 6 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 5 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 28 +-
drivers/gpu/drm/i915/intel_lrc.c | 91 ++---
drivers/gpu/drm/i915/intel_overlay.c | 2 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 91 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 17 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 57 +--
.../drm/i915/selftests/intel_workarounds.c| 3 -
.../gpu/drm/i915/selftests/mock_gem_device.c | 4 +-
20 files changed, 395 insertions(+), 537 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e80903114ca8..3b995f9fdc06 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1285,8 +1285,6 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
seq_puts(m, "Wedged\n");
if (test_bit(I915_RESET_BACKOFF, _priv->gpu_error.flags))
seq_puts(m, "Reset in progress: struct_mutex backoff\n");
- if (test_bit(I915_RESET_HANDOFF, _priv->gpu_error.flags))
- seq_puts(m, "Reset in progress: reset handoff to waiter\n");
if (waitqueue_active(_priv->gpu_error.wait_queue))
seq_puts(m, "Waiter holding struct mutex\n");
if (waitqueue_active(_priv->gpu_error.reset_queue))
@@ -1322,15 +1320,15 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
struct rb_node *rb;
seq_printf(m, "%s:\n", engine->name);
- seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
+ seq_printf(m, "\tseqno = %x [current %x, last %x], %dms ago\n",
engine->hangcheck.seqno, seqno[id],
- intel_engine_last_submit(engine));
- seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s,
wedged? %s\n",
+ intel_engine_last_submit(engine),
+ jiffies_to_msecs(jiffies -
+
engine->hangcheck.action_timestamp));
+ seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
yesno(intel_engine_has_waiter(engine)),
yesno(test_bit(engine->id,
-
_priv->gpu_error.missed_irq_rings)),
- yesno(engine->hangcheck.stalled),
- yesno(engine->hangcheck.wedged));
+
_priv->gpu_error.missed_irq_rings)));
spin_lock_irq(>rb_lock);
for (rb = rb_first(>waiters); rb; rb = rb_next(rb)) {
@@ -1344,11 +1342,6 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
(long long)engine->hangcheck.acthd,
(long long)acthd[id]);
- seq_printf(m, "\taction = %s(%d) %d ms ago\n",
- hangcheck_action_to_str(engine->hangcheck.action),
- engine->hangcheck.action,
- jiffies_to_msecs(jiffies -
-
engine->hangcheck.action_timestamp));
if (engine->id == RCS) {
seq_puts(m, "\tinstdone read =\n");
@@ -3912,8 +3905,6 @@ static int
i915_wedged_set(void *data, u64 val)
{
struct drm_i915_private *i915 = data;
- struct intel_engine_cs *engine;
- unsigned int tmp;
/*
* There is no safeguard against this debugfs entry colliding
@@ -3926,18 +3917,8 @@ i915_wedged_set(void *data, u64 val)
if
[Intel-gfx] [PATCH 03/33] drm/i915: Remove manual breadcumb counting
Now that we know we measure the size of the engine->emit_breadcrumb()
correctly, we can remove the previous manual counting.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 4 ++--
drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++
drivers/gpu/drm/i915/intel_lrc.c| 4
drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
5 files changed, 11 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f941e40fd373..ddc35e9dc0c0 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -650,7 +650,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
* around inside i915_request_add() there is sufficient space at
* the beginning of the ring as well.
*/
- rq->reserved_space = 2 * engine->emit_breadcrumb_sz * sizeof(u32);
+ rq->reserved_space = 2 * engine->emit_breadcrumb_dw * sizeof(u32);
/*
* Record the position of the start of the request so that
@@ -901,7 +901,7 @@ void i915_request_add(struct i915_request *request)
* GPU processing the request, we never over-estimate the
* position of the ring's HEAD.
*/
- cs = intel_ring_begin(request, engine->emit_breadcrumb_sz);
+ cs = intel_ring_begin(request, engine->emit_breadcrumb_dw);
GEM_BUG_ON(IS_ERR(cs));
request->postfix = intel_ring_offset(request, cs);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 883ba208d1c2..235a2d70d671 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -611,7 +611,7 @@ struct measure_breadcrumb {
u32 cs[1024];
};
-static int measure_breadcrumb_sz(struct intel_engine_cs *engine)
+static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
{
struct measure_breadcrumb *frame;
unsigned int dw;
@@ -637,7 +637,6 @@ static int measure_breadcrumb_sz(struct intel_engine_cs
*engine)
frame->rq.timeline = >timeline;
dw = engine->emit_breadcrumb(>rq, frame->cs) - frame->cs;
- GEM_BUG_ON(dw != engine->emit_breadcrumb_sz);
i915_timeline_fini(>timeline);
kfree(frame);
@@ -698,11 +697,11 @@ int intel_engine_init_common(struct intel_engine_cs
*engine)
if (ret)
goto err_breadcrumbs;
- ret = measure_breadcrumb_sz(engine);
+ ret = measure_breadcrumb_dw(engine);
if (ret < 0)
goto err_status_page;
- engine->emit_breadcrumb_sz = ret;
+ engine->emit_breadcrumb_dw = ret;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d2299425cf2f..5551dd2ec0e6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2075,7 +2075,6 @@ static u32 *gen8_emit_breadcrumb(struct i915_request
*request, u32 *cs)
return gen8_emit_wa_tail(request, cs);
}
-static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
static u32 *gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
{
@@ -2099,7 +2098,6 @@ static u32 *gen8_emit_breadcrumb_rcs(struct i915_request
*request, u32 *cs)
return gen8_emit_wa_tail(request, cs);
}
-static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
static int gen8_init_rcs_context(struct i915_request *rq)
{
@@ -2192,7 +2190,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
engine->emit_flush = gen8_emit_flush;
engine->emit_breadcrumb = gen8_emit_breadcrumb;
- engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
engine->set_default_submission = intel_execlists_set_default_submission;
@@ -2298,7 +2295,6 @@ int logical_render_ring_init(struct intel_engine_cs
*engine)
engine->init_context = gen8_init_rcs_context;
engine->emit_flush = gen8_emit_flush_render;
engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
- engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
ret = logical_ring_init(engine);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 107c4934e2fa..09c90475168a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -330,7 +330,6 @@ static u32 *gen6_rcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
return cs;
}
-static const int gen6_rcs_emit_breadcrumb_sz = 14;
static int
gen7_render_ring_cs_stall_wa(struct i915_request *rq)
@@ -432,7 +431,6 @@ static u32 *gen7_rcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
return cs;
}
-static const int gen7_rcs_emit_breadcrumb_sz = 6;
static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
{
@@ -446,7
[Intel-gfx] [PATCH 17/33] drm/i915: Add timeline barrier support
From: Tvrtko Ursulin
Timeline barrier allows serialization between different timelines.
After calling i915_timeline_set_barrier with a request, all following
submissions on this timeline will be set up as depending on this request,
or barrier. Once the barrier has been completed it automatically gets
cleared and things continue as normal.
This facility will be used by the upcoming context SSEU code.
v2:
* Assert barrier has been retired on timeline_fini. (Chris Wilson)
* Fix mock_timeline.
v3:
* Improved comment language. (Chris Wilson)
v4:
* Maintain ordering with previous barriers set on the timeline.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 17 ++
drivers/gpu/drm/i915/i915_timeline.c | 21 ++
drivers/gpu/drm/i915/i915_timeline.h | 22 +++
.../gpu/drm/i915/selftests/mock_timeline.c| 1 +
4 files changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f4241a17e2ad..894b32258340 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -517,6 +517,19 @@ i915_request_alloc_slow(struct intel_context *ce)
return kmem_cache_alloc(ce->gem_context->i915->requests, GFP_KERNEL);
}
+static int add_barrier(struct i915_request *rq, struct i915_gem_active *active)
+{
+ struct i915_request *barrier =
+ i915_gem_active_raw(active, >i915->drm.struct_mutex);
+
+ return barrier ? i915_request_await_dma_fence(rq, >fence) : 0;
+}
+
+static int add_timeline_barrier(struct i915_request *rq)
+{
+ return add_barrier(rq, >timeline->barrier);
+}
+
/**
* i915_request_alloc - allocate a request structure
*
@@ -660,6 +673,10 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
*/
rq->head = rq->ring->emit;
+ ret = add_timeline_barrier(rq);
+ if (ret)
+ goto err_unwind;
+
ret = engine->request_alloc(rq);
if (ret)
goto err_unwind;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 4667cc08c416..6d5774cb8504 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -33,6 +33,7 @@ void i915_timeline_init(struct drm_i915_private *i915,
spin_lock_init(>lock);
+ init_request_active(>barrier, NULL);
init_request_active(>last_request, NULL);
INIT_LIST_HEAD(>requests);
@@ -69,6 +70,7 @@ void i915_timelines_park(struct drm_i915_private *i915)
void i915_timeline_fini(struct i915_timeline *timeline)
{
GEM_BUG_ON(!list_empty(>requests));
+ GEM_BUG_ON(i915_gem_active_isset(>barrier));
i915_syncmap_free(>sync);
@@ -90,6 +92,25 @@ i915_timeline_create(struct drm_i915_private *i915, const
char *name)
return timeline;
}
+int i915_timeline_set_barrier(struct i915_timeline *tl, struct i915_request
*rq)
+{
+ struct i915_request *old;
+ int err;
+
+ lockdep_assert_held(>i915->drm.struct_mutex);
+
+ /* Must maintain ordering wrt existing barriers */
+ old = i915_gem_active_raw(>barrier, >i915->drm.struct_mutex);
+ if (old) {
+ err = i915_request_await_dma_fence(rq, >fence);
+ if (err)
+ return err;
+ }
+
+ i915_gem_active_set(>barrier, rq);
+ return 0;
+}
+
void __i915_timeline_free(struct kref *kref)
{
struct i915_timeline *timeline =
diff --git a/drivers/gpu/drm/i915/i915_timeline.h
b/drivers/gpu/drm/i915/i915_timeline.h
index 38c1e15e927a..c8d7117bb205 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -64,6 +64,16 @@ struct i915_timeline {
*/
struct i915_syncmap *sync;
+ /**
+* Barrier provides the ability to serialize ordering between different
+* timelines.
+*
+* Users can call i915_timeline_set_barrier which will make all
+* subsequent submissions to this timeline be executed only after the
+* barrier has been completed.
+*/
+ struct i915_gem_active barrier;
+
struct list_head link;
const char *name;
@@ -136,4 +146,16 @@ static inline bool i915_timeline_sync_is_later(struct
i915_timeline *tl,
void i915_timelines_park(struct drm_i915_private *i915);
+/**
+ * i915_timeline_set_barrier - orders submission between different timelines
+ * @timeline: timeline to set the barrier on
+ * @rq: request after which new submissions can proceed
+ *
+ * Sets the passed in request as the serialization point for all subsequent
+ * submissions on @timeline. Subsequent requests will not be submitted to GPU
+ * until the barrier has been completed.
+ */
+int i915_timeline_set_barrier(struct
[Intel-gfx] [PATCH 05/33] drm/i915/execlists: Suppress preempting self
In order to avoid preempting ourselves, we currently refuse to schedule
the tasklet if we reschedule an inflight context. However, this glosses
over a few issues such as what happens after a CS completion event and
we then preempt the newly executing context with itself, or if something
else causes a tasklet_schedule triggering the same evaluation to
preempt the active context with itself.
To avoid the extra complications, after deciding that we have
potentially queued a request with higher priority than the currently
executing request, inspect the head of the queue to see if it is indeed
higher priority from another context.
v2: We can simplify a bunch of tests based on the knowledge that PI will
ensure that earlier requests along the same context will have the highest
priority.
References: a2bf92e8cc16 ("drm/i915/execlists: Avoid kicking priority on the
current context")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_scheduler.c | 20 --
drivers/gpu/drm/i915/intel_lrc.c | 91 ---
2 files changed, 100 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 340faea6c08a..fb5d953430e5 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -239,6 +239,18 @@ sched_lock_engine(struct i915_sched_node *node, struct
intel_engine_cs *locked)
return engine;
}
+static bool inflight(const struct i915_request *rq,
+const struct intel_engine_cs *engine)
+{
+ const struct i915_request *active;
+
+ if (!rq->global_seqno)
+ return false;
+
+ active = port_request(engine->execlists.port);
+ return active->hw_context == rq->hw_context;
+}
+
static void __i915_schedule(struct i915_request *rq,
const struct i915_sched_attr *attr)
{
@@ -328,6 +340,7 @@ static void __i915_schedule(struct i915_request *rq,
INIT_LIST_HEAD(>dfs_link);
engine = sched_lock_engine(node, engine);
+ lockdep_assert_held(>timeline.lock);
/* Recheck after acquiring the engine->timeline.lock */
if (prio <= node->attr.priority || node_signaled(node))
@@ -356,17 +369,16 @@ static void __i915_schedule(struct i915_request *rq,
if (prio <= engine->execlists.queue_priority)
continue;
+ engine->execlists.queue_priority = prio;
+
/*
* If we are already the currently executing context, don't
* bother evaluating if we should preempt ourselves.
*/
- if (node_to_request(node)->global_seqno &&
-
i915_seqno_passed(port_request(engine->execlists.port)->global_seqno,
- node_to_request(node)->global_seqno))
+ if (inflight(node_to_request(node), engine))
continue;
/* Defer (tasklet) submission until after all of our updates. */
- engine->execlists.queue_priority = prio;
tasklet_hi_schedule(>execlists.tasklet);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5551dd2ec0e6..37defd14c198 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -181,13 +181,89 @@ static inline int rq_prio(const struct i915_request *rq)
return rq->sched.attr.priority;
}
+static int queue_prio(const struct intel_engine_execlists *execlists)
+{
+ struct i915_priolist *p;
+ struct rb_node *rb;
+
+ rb = rb_first_cached(>queue);
+ if (!rb)
+ return INT_MIN;
+
+ /*
+* As the priolist[] are inverted, with the highest priority in [0],
+* we have to flip the index value to become priority.
+*/
+ p = to_priolist(rb);
+ return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
+}
+
static inline bool need_preempt(const struct intel_engine_cs *engine,
- const struct i915_request *last,
- int prio)
+ const struct i915_request *rq,
+ int q_prio)
{
- return (intel_engine_has_preemption(engine) &&
- __execlists_need_preempt(prio, rq_prio(last)) &&
- !i915_request_completed(last));
+ const struct intel_context *ctx = rq->hw_context;
+ const int last_prio = rq_prio(rq);
+
+ if (!intel_engine_has_preemption(engine))
+ return false;
+
+ if (i915_request_completed(rq))
+ return false;
+
+ /*
+* Check if the current queue_priority merits a preemption attempt.
+*
+* However, the queue_priority is a mere hint that we may need to
+* preempt. If that hint is
[Intel-gfx] [PATCH 07/33] drm/i915/selftests: Apply a subtest filter
In bringup on simulated HW even rudimentary tests are slow, and so many
may fail that we want to be able to filter out the noise to focus on the
specific problem. Even just the tests groups provided for igt is not
specific enough, and we would like to isolate one particular subtest
(and probably subsubtests!). For simplicity, allow the user to provide a
command line parameter such as
i915.st_filter=i915_timeline_mock_selftests/igt_sync
to restrict ourselves to only running on subtest. The exact name to use
is given during a normal run, highlighted as an error if it failed,
debug otherwise. The test group is optional, and then all subtests are
compared for an exact match with the filter (most subtests have unique
names). The filter can be negated, e.g. i915.st_filter=!igt_sync and
then all tests but those that match will be run. More than one match can
be supplied separated by a comma, e.g.
i915.st_filter=igt_vma_create,igt_vma_pin1
to only run those specified, or
i915.st_filter=!igt_vma_create,!igt_vma_pin1
to run all but those named. Mixing a blacklist and whitelist will only
execute those subtests matching the whitelist so long as they are
previously excluded in the blacklist.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_selftest.h | 1 +
.../gpu/drm/i915/selftests/i915_selftest.c| 44 +++
2 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_selftest.h
b/drivers/gpu/drm/i915/i915_selftest.h
index a73472dd12fd..207e21b478f2 100644
--- a/drivers/gpu/drm/i915/i915_selftest.h
+++ b/drivers/gpu/drm/i915/i915_selftest.h
@@ -31,6 +31,7 @@ struct i915_selftest {
unsigned long timeout_jiffies;
unsigned int timeout_ms;
unsigned int random_seed;
+ char *filter;
int mock;
int live;
};
diff --git a/drivers/gpu/drm/i915/selftests/i915_selftest.c
b/drivers/gpu/drm/i915/selftests/i915_selftest.c
index 86c54ea37f48..1b174ac65ff9 100644
--- a/drivers/gpu/drm/i915/selftests/i915_selftest.c
+++ b/drivers/gpu/drm/i915/selftests/i915_selftest.c
@@ -197,6 +197,46 @@ int i915_live_selftests(struct pci_dev *pdev)
return 0;
}
+static bool apply_subtest_filter(const char *caller, const char *name)
+{
+ char *filter, *sep, *tok;
+ bool result = true;
+
+ filter = kstrdup(i915_selftest.filter, GFP_KERNEL);
+ for (sep = filter; (tok = strsep(, ","));) {
+ bool allow = true;
+ char *sl;
+
+ if (*tok == '!') {
+ allow = false;
+ tok++;
+ }
+
+ sl = strchr(tok, '/');
+ if (sl) {
+ *sl++ = '\0';
+ if (strcmp(tok, caller)) {
+ if (allow)
+ result = false;
+ continue;
+ }
+ tok = sl;
+ }
+
+ if (strcmp(tok, name)) {
+ if (allow)
+ result = false;
+ continue;
+ }
+
+ result = allow;
+ break;
+ }
+ kfree(filter);
+
+ return result;
+}
+
int __i915_subtests(const char *caller,
const struct i915_subtest *st,
unsigned int count,
@@ -209,6 +249,9 @@ int __i915_subtests(const char *caller,
if (signal_pending(current))
return -EINTR;
+ if (!apply_subtest_filter(caller, st->name))
+ continue;
+
pr_debug(DRIVER_NAME ": Running %s/%s\n", caller, st->name);
GEM_TRACE("Running %s/%s\n", caller, st->name);
@@ -244,6 +287,7 @@ bool __igt_timeout(unsigned long timeout, const char *fmt,
...)
module_param_named(st_random_seed, i915_selftest.random_seed, uint, 0400);
module_param_named(st_timeout, i915_selftest.timeout_ms, uint, 0400);
+module_param_named(st_filter, i915_selftest.filter, charp, 0400);
module_param_named_unsafe(mock_selftests, i915_selftest.mock, int, 0400);
MODULE_PARM_DESC(mock_selftests, "Run selftests before loading, using mock
hardware (0:disabled [default], 1:run tests then load driver, -1:run tests then
exit module)");
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 23/33] drm/i915: Track the context's seqno in its own timeline HWSP
Now that we have allocated ourselves a cacheline to store a breadcrumb,
we can emit a write from the GPU into the timeline's HWSP of the
per-context seqno as we complete each request. This drops the mirroring
of the per-engine HWSP and allows each context to operate independently.
We do not need to unwind the per-context timeline, and so requests are
always consistent with the timeline breadcrumb, greatly simplifying the
completion checks as we no longer need to be concerned about the
global_seqno changing mid check.
One complication though is that we have to be wary that the request may
outlive the HWSP and so avoid touching the potentially danging pointer
after we have retired the fence. We also have to guard our access of the
HWSP with RCU, the release of the obj->mm.pages should already be RCU-safe.
At this point, we are emitting both per-context and global seqno and
still using the single per-engine execution timeline for resolving
interrupts.
v2: s/fake_complete/mark_complete/
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 3 +-
drivers/gpu/drm/i915/i915_request.h | 30 +++-
drivers/gpu/drm/i915/i915_reset.c| 1 +
drivers/gpu/drm/i915/i915_vma.h | 6 ++
drivers/gpu/drm/i915/intel_engine_cs.c | 15 +++-
drivers/gpu/drm/i915/intel_lrc.c | 31 +---
drivers/gpu/drm/i915/intel_ringbuffer.c | 76 +++-
drivers/gpu/drm/i915/selftests/mock_engine.c | 19 -
9 files changed, 131 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d68f3fdd8a8e..1bd724d663d9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2892,7 +2892,7 @@ i915_gem_find_active_request(struct intel_engine_cs
*engine)
*/
spin_lock_irqsave(>timeline.lock, flags);
list_for_each_entry(request, >timeline.requests, link) {
- if (__i915_request_completed(request, request->global_seqno))
+ if (i915_request_completed(request))
continue;
active = request;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 79eb1957cf99..cdbdbcff28ec 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -199,6 +199,7 @@ static void __retire_engine_request(struct intel_engine_cs
*engine,
spin_unlock(>timeline.lock);
spin_lock(>lock);
+ i915_request_mark_complete(rq);
if (!i915_request_signaled(rq))
dma_fence_signal_locked(>fence);
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
@@ -634,7 +635,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->ring = ce->ring;
rq->timeline = ce->ring->timeline;
GEM_BUG_ON(rq->timeline == >timeline);
- rq->hwsp_seqno = >status_page.addr[I915_GEM_HWS_INDEX];
+ rq->hwsp_seqno = rq->timeline->hwsp_seqno;
spin_lock_init(>lock);
dma_fence_init(>fence,
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index ade010fe6e26..96c586d6ff4d 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -289,6 +289,7 @@ long i915_request_wait(struct i915_request *rq,
static inline bool i915_request_signaled(const struct i915_request *rq)
{
+ /* The request may live longer than its HWSP, so check flags first! */
return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags);
}
@@ -340,32 +341,23 @@ static inline u32 hwsp_seqno(const struct i915_request
*rq)
*/
static inline bool i915_request_started(const struct i915_request *rq)
{
- u32 seqno;
-
- seqno = i915_request_global_seqno(rq);
- if (!seqno) /* not yet submitted to HW */
- return false;
+ if (i915_request_signaled(rq))
+ return true;
- return i915_seqno_passed(hwsp_seqno(rq), seqno - 1);
-}
-
-static inline bool
-__i915_request_completed(const struct i915_request *rq, u32 seqno)
-{
- GEM_BUG_ON(!seqno);
- return i915_seqno_passed(hwsp_seqno(rq), seqno) &&
- seqno == i915_request_global_seqno(rq);
+ return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno - 1);
}
static inline bool i915_request_completed(const struct i915_request *rq)
{
- u32 seqno;
+ if (i915_request_signaled(rq))
+ return true;
- seqno = i915_request_global_seqno(rq);
- if (!seqno)
- return false;
+ return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno);
+}
- return __i915_request_completed(rq, seqno);
+static inline void i915_request_mark_complete(struct i915_request *rq)
+{
+ rq->hwsp_seqno = (u32 *)>fence.seqno; /* decouple
[Intel-gfx] [PATCH 02/33] drm/i915: Measure the required reserved size for request emission
Instead of tediously and fragilely counting up the number of dwords
required to emit the breadcrumb to seal a request, fake a request and
measure it automatically once during engine setup.
The downside is that this requires a fair amount of mocking to create a
proper breadcrumb. Still, should be less error prone in future as the
breadcrumb size fluctuates!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 49
drivers/gpu/drm/i915/intel_lrc.c | 12 +++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 24 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 4 +-
5 files changed, 77 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 2f3c71f6d313..883ba208d1c2 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -604,6 +604,47 @@ static void __intel_context_unpin(struct i915_gem_context
*ctx,
intel_context_unpin(to_intel_context(ctx, engine));
}
+struct measure_breadcrumb {
+ struct i915_request rq;
+ struct i915_timeline timeline;
+ struct intel_ring ring;
+ u32 cs[1024];
+};
+
+static int measure_breadcrumb_sz(struct intel_engine_cs *engine)
+{
+ struct measure_breadcrumb *frame;
+ unsigned int dw;
+
+ GEM_BUG_ON(!engine->i915->gt.scratch);
+
+ frame = kzalloc(sizeof(*frame), GFP_KERNEL);
+ if (!frame)
+ return -ENOMEM;
+
+ i915_timeline_init(engine->i915, >timeline, engine->name);
+
+ frame->ring.timeline = >timeline;
+ frame->ring.vaddr = frame->cs;
+ frame->ring.size = sizeof(frame->cs);
+ frame->ring.effective_size = frame->ring.size;
+ frame->ring.space = frame->ring.size - 8;
+ INIT_LIST_HEAD(>ring.request_list);
+
+ frame->rq.i915 = engine->i915;
+ frame->rq.engine = engine;
+ frame->rq.ring = >ring;
+ frame->rq.timeline = >timeline;
+
+ dw = engine->emit_breadcrumb(>rq, frame->cs) - frame->cs;
+ GEM_BUG_ON(dw != engine->emit_breadcrumb_sz);
+
+ i915_timeline_fini(>timeline);
+ kfree(frame);
+
+ return dw;
+}
+
/**
* intel_engines_init_common - initialize cengine state which might require hw
access
* @engine: Engine to initialize.
@@ -657,8 +698,16 @@ int intel_engine_init_common(struct intel_engine_cs
*engine)
if (ret)
goto err_breadcrumbs;
+ ret = measure_breadcrumb_sz(engine);
+ if (ret < 0)
+ goto err_status_page;
+
+ engine->emit_breadcrumb_sz = ret;
+
return 0;
+err_status_page:
+ cleanup_status_page(engine);
err_breadcrumbs:
intel_engine_fini_breadcrumbs(engine);
err_unpin_preempt:
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9155cc675924..d2299425cf2f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2051,15 +2051,17 @@ static int gen8_emit_flush_render(struct i915_request
*request,
* used as a workaround for not being allowed to do lite
* restore with HEAD==TAIL (WaIdleLiteRestore).
*/
-static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
+static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
{
/* Ensure there's always at least one preemption point per-request. */
*cs++ = MI_ARB_CHECK;
*cs++ = MI_NOOP;
request->wa_tail = intel_ring_offset(request, cs);
+
+ return cs;
}
-static void gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
+static u32 *gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
{
/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
@@ -2071,11 +2073,11 @@ static void gen8_emit_breadcrumb(struct i915_request
*request, u32 *cs)
request->tail = intel_ring_offset(request, cs);
assert_ring_tail_valid(request->ring, request->tail);
- gen8_emit_wa_tail(request, cs);
+ return gen8_emit_wa_tail(request, cs);
}
static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
-static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
+static u32 *gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
{
/* We're using qword write, seqno should be aligned to 8 bytes. */
BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
@@ -2095,7 +2097,7 @@ static void gen8_emit_breadcrumb_rcs(struct i915_request
*request, u32 *cs)
request->tail = intel_ring_offset(request, cs);
assert_ring_tail_valid(request->ring, request->tail);
- gen8_emit_wa_tail(request, cs);
+ return gen8_emit_wa_tail(request, cs);
}
static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
[Intel-gfx] [PATCH 22/33] drm/i915: Share per-timeline HWSP using a slab suballocator
If we restrict ourselves to only using a cacheline for each timeline's
HWSP (we could go smaller, but want to avoid needless polluting
cachelines on different engines between different contexts), then we can
suballocate a single 4k page into 64 different timeline HWSP. By
treating each fresh allocation as a slab of 64 entries, we can keep it
around for the next 64 allocation attempts until we need to refresh the
slab cache.
John Harrison noted the issue of fragmentation leading to the same worst
case performance of one page per timeline as before, which can be
mitigated by adopting a freelist.
v2: Keep all partially allocated HWSP on a freelist
This is still without migration, so it is possible for the system to end
up with each timeline in its own page, but we ensure that no new
allocation would needless allocate a fresh page!
v3: Throw a selftest at the allocator to try and catch invalid cacheline
reuse.
Signed-off-by: Chris Wilson
Cc: John Harrison
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_timeline.c | 116 ---
drivers/gpu/drm/i915/i915_timeline.h | 1 +
drivers/gpu/drm/i915/i915_vma.h | 12 ++
drivers/gpu/drm/i915/selftests/i915_random.c | 33 -
drivers/gpu/drm/i915/selftests/i915_random.h | 3 +
.../gpu/drm/i915/selftests/i915_timeline.c| 140 ++
7 files changed, 281 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8a181b455197..6a051381f535 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1978,6 +1978,10 @@ struct drm_i915_private {
struct i915_gt_timelines {
struct mutex mutex; /* protects list, tainted by GPU */
struct list_head list;
+
+ /* Pack multiple timelines' seqnos into the same page */
+ spinlock_t hwsp_lock;
+ struct list_head hwsp_free_list;
} timelines;
struct list_head active_rings;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 5b5f9dacfce9..95c689826c8c 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -9,6 +9,12 @@
#include "i915_timeline.h"
#include "i915_syncmap.h"
+struct i915_timeline_hwsp {
+ struct i915_vma *vma;
+ struct list_head free_link;
+ u64 free_bitmap;
+};
+
static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
{
struct drm_i915_gem_object *obj;
@@ -27,28 +33,91 @@ static struct i915_vma *__hwsp_alloc(struct
drm_i915_private *i915)
return vma;
}
-static int hwsp_alloc(struct i915_timeline *timeline)
+static struct i915_vma *hwsp_alloc(struct i915_timeline *timeline, int *offset)
{
- struct i915_vma *vma;
+ struct drm_i915_private *i915 = timeline->i915;
+ struct i915_gt_timelines *gt = >gt.timelines;
+ struct i915_timeline_hwsp *hwsp;
+ int cacheline;
- vma = __hwsp_alloc(timeline->i915);
- if (IS_ERR(vma))
- return PTR_ERR(vma);
+ BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
- timeline->hwsp_ggtt = vma;
- timeline->hwsp_offset = 0;
+ spin_lock(>hwsp_lock);
- return 0;
+ /* hwsp_free_list only contains HWSP that have available cachelines */
+ hwsp = list_first_entry_or_null(>hwsp_free_list,
+ typeof(*hwsp), free_link);
+ if (!hwsp) {
+ struct i915_vma *vma;
+
+ spin_unlock(>hwsp_lock);
+
+ hwsp = kmalloc(sizeof(*hwsp), GFP_KERNEL);
+ if (!hwsp)
+ return ERR_PTR(-ENOMEM);
+
+ vma = __hwsp_alloc(i915);
+ if (IS_ERR(vma)) {
+ kfree(hwsp);
+ return vma;
+ }
+
+ vma->private = hwsp;
+ hwsp->vma = vma;
+ hwsp->free_bitmap = ~0ull;
+
+ spin_lock(>hwsp_lock);
+ list_add(>free_link, >hwsp_free_list);
+ }
+
+ GEM_BUG_ON(!hwsp->free_bitmap);
+ cacheline = __ffs64(hwsp->free_bitmap);
+ hwsp->free_bitmap &= ~BIT_ULL(cacheline);
+ if (!hwsp->free_bitmap)
+ list_del(>free_link);
+
+ spin_unlock(>hwsp_lock);
+
+ GEM_BUG_ON(hwsp->vma->private != hwsp);
+
+ *offset = cacheline * CACHELINE_BYTES;
+ return hwsp->vma;
+}
+
+static void hwsp_free(struct i915_timeline *timeline)
+{
+ struct i915_gt_timelines *gt = >i915->gt.timelines;
+ struct i915_timeline_hwsp *hwsp;
+
+ hwsp = i915_timeline_hwsp(timeline);
+ if (!hwsp) /* leave global HWSP alone! */
+ return;
+
+ spin_lock(>hwsp_lock);
+
+ /* As a cacheline
[Intel-gfx] [PATCH 14/33] drm/i915: Pull VM lists under the VM mutex.
A starting point to counter the pervasive struct_mutex. For the goal of
avoiding (or at least blocking under them!) global locks during user
request submission, a simple but important step is being able to manage
each clients GTT separately. For which, we want to replace using the
struct_mutex as the guard for all things GTT/VM and switch instead to a
specific mutex inside i915_address_space.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 14 --
drivers/gpu/drm/i915/i915_gem_evict.c | 2 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +--
drivers/gpu/drm/i915/i915_gem_shrinker.c| 4
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 ++
drivers/gpu/drm/i915/i915_vma.c | 11 +++
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 3 +++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
8 files changed, 46 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 12a0a80bc989..111a047a45b7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -247,18 +247,19 @@ int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = _priv->ggtt;
+ struct i915_ggtt *ggtt = _i915(dev)->ggtt;
struct drm_i915_gem_get_aperture *args = data;
struct i915_vma *vma;
u64 pinned;
+ mutex_lock(>vm.mutex);
+
pinned = ggtt->vm.reserved;
- mutex_lock(>struct_mutex);
list_for_each_entry(vma, >vm.bound_list, vm_link)
if (i915_vma_is_pinned(vma))
pinned += vma->node.size;
- mutex_unlock(>struct_mutex);
+
+ mutex_unlock(>vm.mutex);
args->aper_size = ggtt->vm.total;
args->aper_available_size = args->aper_size - pinned;
@@ -1531,20 +1532,21 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void
*data,
static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *i915;
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct list_head *list;
struct i915_vma *vma;
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+ mutex_lock(>ggtt.vm.mutex);
for_each_ggtt_vma(vma, obj) {
if (!drm_mm_node_allocated(>node))
continue;
list_move_tail(>vm_link, >vm->bound_list);
}
+ mutex_unlock(>ggtt.vm.mutex);
- i915 = to_i915(obj->base.dev);
spin_lock(>mm.obj_lock);
list = obj->bind_count ? >mm.bound_list : >mm.unbound_list;
list_move_tail(>mm.link, list);
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 5cfe4b75e7d6..dc137701acb8 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -432,6 +432,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
}
INIT_LIST_HEAD(_list);
+ mutex_lock(>mutex);
list_for_each_entry(vma, >bound_list, vm_link) {
if (i915_vma_is_pinned(vma))
continue;
@@ -439,6 +440,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm)
__i915_vma_pin(vma);
list_add(>evict_link, _list);
}
+ mutex_unlock(>mutex);
ret = 0;
list_for_each_entry_safe(vma, next, _list, evict_link) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2ad9070a54c1..49b00996a15e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1931,7 +1931,10 @@ static struct i915_vma *pd_vma_create(struct
gen6_hw_ppgtt *ppgtt, int size)
vma->ggtt_view.type = I915_GGTT_VIEW_ROTATED; /* prevent fencing */
INIT_LIST_HEAD(>obj_link);
+
+ mutex_lock(>vm->mutex);
list_add(>vm_link, >vm->unbound_list);
+ mutex_unlock(>vm->mutex);
return vma;
}
@@ -3504,9 +3507,10 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
i915_check_and_clear_faults(dev_priv);
+ mutex_lock(>vm.mutex);
+
/* First fill our portion of the GTT with scratch pages */
ggtt->vm.clear_range(>vm, 0, ggtt->vm.total);
-
ggtt->vm.closed = true; /* skip rewriting PTE on VMA unbind */
/* clflush objects bound into the GGTT and rebind them. */
@@ -3516,19 +3520,26 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
if (!(vma->flags & I915_VMA_GLOBAL_BIND))
continue;
+ mutex_unlock(>vm.mutex);
+
if (!i915_vma_unbind(vma))
- continue;
+
[Intel-gfx] [PATCH 09/33] drm/i915/guc: Disable global reset
The guc (and huc) currently inexcruitably depend on struct_mutex for
device reinitialisation from inside the reset, and indeed taking any
mutex here is verboten (as we must be able to reset from underneath any
of our mutexes). That makes recovering the guc unviable without, for
example, reserving contiguous vma space and pages for it to use.
The plan to re-enable global reset for the GuC centres around reusing the
WOPM reserved space at the top of the aperture (that we know we can
populate a contiguous range large enough to dma xfer the fw image).
In the meantime, hopefully no one even notices as the device-reset is
only used as a backup to the per-engine resets for handling GPU hangs.
Signed-off-by: Chris Wilson
Acked-by: Mika Kuoppala
Acked-by: Daniele Ceraolo Spurio
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_reset.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 2f840858572c..33408c4e6358 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -574,6 +574,9 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned
int engine_mask)
bool intel_has_gpu_reset(struct drm_i915_private *i915)
{
+ if (USES_GUC(i915))
+ return false;
+
return intel_get_gpu_reset(i915);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 25/33] drm/i915: Identify active requests
To allow requests to forgo a common execution timeline, one question we
need to be able to answer is "is this request running?". To track
whether a request has started on HW, we can emit a breadcrumb at the
beginning of the request and check its timeline's HWSP to see if the
breadcrumb has advanced past the start of this request. (This is in
contrast to the global timeline where we need only ask if we are on the
global timeline and if the timeline has advanced past the end of the
previous request.)
There is still confusion from a preempted request, which has already
started but relinquished the HW to a high priority request. For the
common case, this discrepancy should be negligible. However, for
identification of hung requests, knowing which one was running at the
time of the hang will be much more important.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 ++
drivers/gpu/drm/i915/i915_request.c | 10 ++---
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_timeline.c | 1 +
drivers/gpu/drm/i915/i915_timeline.h | 2 +
drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++--
drivers/gpu/drm/i915/intel_lrc.c | 39 +---
drivers/gpu/drm/i915/intel_ringbuffer.c | 25 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 +++-
drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
11 files changed, 85 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 05627000b77d..101a0f644787 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2895,6 +2895,9 @@ i915_gem_find_active_request(struct intel_engine_cs
*engine)
if (i915_request_completed(request))
continue;
+ if (!i915_request_started(request))
+ break;
+
active = request;
break;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index f250109e1f66..8eedf7cac493 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1976,6 +1976,18 @@ static int eb_submit(struct i915_execbuffer *eb)
return err;
}
+ /*
+* After we completed waiting for other engines (using HW semaphores)
+* then we can signal that this request/batch is ready to run. This
+* allows us to determine if the batch is still waiting on the GPU
+* or actually running by checking the breadcrumb.
+*/
+ if (eb->engine->emit_init_breadcrumb) {
+ err = eb->engine->emit_init_breadcrumb(eb->request);
+ if (err)
+ return err;
+ }
+
err = eb->engine->emit_bb_start(eb->request,
eb->batch->node.start +
eb->batch_start_offset,
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index cdbdbcff28ec..2171df2d3019 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -333,7 +333,7 @@ void i915_request_retire_upto(struct i915_request *rq)
static u32 timeline_get_seqno(struct i915_timeline *tl)
{
- return ++tl->seqno;
+ return tl->seqno += 1 + tl->has_initial_breadcrumb;
}
static void move_to_timeline(struct i915_request *request,
@@ -382,8 +382,8 @@ void __i915_request_submit(struct i915_request *request)
intel_engine_enable_signaling(request, false);
spin_unlock(>lock);
- engine->emit_breadcrumb(request,
- request->ring->vaddr + request->postfix);
+ engine->emit_fini_breadcrumb(request,
+request->ring->vaddr + request->postfix);
/* Transfer from per-context onto the global per-engine timeline */
move_to_timeline(request, >timeline);
@@ -670,7 +670,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
* around inside i915_request_add() there is sufficient space at
* the beginning of the ring as well.
*/
- rq->reserved_space = 2 * engine->emit_breadcrumb_dw * sizeof(u32);
+ rq->reserved_space = 2 * engine->emit_fini_breadcrumb_dw * sizeof(u32);
/*
* Record the position of the start of the request so that
@@ -925,7 +925,7 @@ void i915_request_add(struct i915_request *request)
* GPU processing the request, we never over-estimate the
* position of the ring's HEAD.
*/
- cs = intel_ring_begin(request, engine->emit_breadcrumb_dw);
+ cs = intel_ring_begin(request, engine->emit_fini_breadcrumb_dw);
[Intel-gfx] [PATCH 01/33] drm/i915/execlists: Move RPCS setup to context pin
From: Tvrtko Ursulin
Configuring RPCS in context image just before pin is sufficient and will
come extra handy in one of the following patches.
v2:
* Split image setup a bit differently. (Chris Wilson)
v3:
* Update context image after reset as well - otherwise the application
of pinned default state clears the RPCS.
v4:
* Use local variable throughout the function. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Cc: Chris Wilson
Reviewed-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_lrc.c | 45
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8aa8a4862543..9155cc675924 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1173,6 +1173,24 @@ static int __context_pin(struct i915_gem_context *ctx,
struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
+static u32 make_rpcs(struct drm_i915_private *dev_priv);
+
+static void
+__execlists_update_reg_state(struct intel_engine_cs *engine,
+struct intel_context *ce)
+{
+ u32 *regs = ce->lrc_reg_state;
+ struct intel_ring *ring = ce->ring;
+
+ regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma);
+ regs[CTX_RING_HEAD + 1] = ring->head;
+ regs[CTX_RING_TAIL + 1] = ring->tail;
+
+ /* RPCS */
+ if (engine->class == RENDER_CLASS)
+ regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915);
+}
+
static struct intel_context *
__execlists_context_pin(struct intel_engine_cs *engine,
struct i915_gem_context *ctx,
@@ -1211,10 +1229,8 @@ __execlists_context_pin(struct intel_engine_cs *engine,
GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
- i915_ggtt_offset(ce->ring->vma);
- ce->lrc_reg_state[CTX_RING_HEAD + 1] = ce->ring->head;
- ce->lrc_reg_state[CTX_RING_TAIL + 1] = ce->ring->tail;
+
+ __execlists_update_reg_state(engine, ce);
ce->state->obj->pin_global++;
i915_gem_context_get(ctx);
@@ -1838,14 +1854,14 @@ static void execlists_reset(struct intel_engine_cs
*engine,
engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
engine->context_size - PAGE_SIZE);
}
- execlists_init_reg_state(regs,
-request->gem_context, engine, request->ring);
/* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
- regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
-
request->ring->head = intel_ring_wrap(request->ring, request->postfix);
- regs[CTX_RING_HEAD + 1] = request->ring->head;
+
+ execlists_init_reg_state(regs, request->gem_context, engine,
+request->ring);
+
+ __execlists_update_reg_state(engine, request->hw_context);
intel_ring_update_space(request->ring);
@@ -2534,8 +2550,7 @@ static void execlists_init_reg_state(u32 *regs,
if (rcs) {
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
- CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
- make_rpcs(dev_priv));
+ CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
i915_oa_init_reg_state(engine, ctx, regs);
}
@@ -2696,12 +2711,8 @@ void intel_lr_context_resume(struct drm_i915_private
*i915)
intel_ring_reset(ce->ring, 0);
- if (ce->pin_count) { /* otherwise done in context_pin */
- u32 *regs = ce->lrc_reg_state;
-
- regs[CTX_RING_HEAD + 1] = ce->ring->head;
- regs[CTX_RING_TAIL + 1] = ce->ring->tail;
- }
+ if (ce->pin_count) /* otherwise done in context_pin */
+ __execlists_update_reg_state(engine, ce);
}
}
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/33] drm/i915: Always allocate an object/vma for the HWSP
Currently we only allocate an object and vma if we are using a GGTT
virtual HWSP, and a plain struct page for a physical HWSP. For
convenience later on with global timelines, it will be useful to always
have the status page being tracked by a struct i915_vma. Make it so.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_engine_cs.c | 109 ++-
drivers/gpu/drm/i915/intel_guc_submission.c | 6 +
drivers/gpu/drm/i915/intel_lrc.c | 12 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 21 +++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +---
drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
6 files changed, 93 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 815a05fe0e1e..c1dc1769e337 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -506,27 +506,61 @@ void intel_engine_setup_common(struct intel_engine_cs
*engine)
static void cleanup_status_page(struct intel_engine_cs *engine)
{
+ struct i915_vma *vma;
+
/* Prevent writes into HWSP after returning the page to the system */
intel_engine_set_hwsp_writemask(engine, ~0u);
- if (HWS_NEEDS_PHYSICAL(engine->i915)) {
- void *addr = fetch_and_zero(>status_page.page_addr);
+ vma = fetch_and_zero(>status_page.vma);
+ if (!vma)
+ return;
- __free_page(virt_to_page(addr));
- }
+ if (!HWS_NEEDS_PHYSICAL(engine->i915))
+ i915_vma_unpin(vma);
+
+ i915_gem_object_unpin_map(vma->obj);
+ __i915_gem_object_release_unless_active(vma->obj);
+}
+
+static int pin_ggtt_status_page(struct intel_engine_cs *engine,
+ struct i915_vma *vma)
+{
+ unsigned int flags;
+
+ flags = PIN_GLOBAL;
+ if (!HAS_LLC(engine->i915))
+ /*
+* On g33, we cannot place HWS above 256MiB, so
+* restrict its pinning to the low mappable arena.
+* Though this restriction is not documented for
+* gen4, gen5, or byt, they also behave similarly
+* and hang if the HWS is placed at the top of the
+* GTT. To generalise, it appears that all !llc
+* platforms have issues with us placing the HWS
+* above the mappable region (even though we never
+* actually map it).
+*/
+ flags |= PIN_MAPPABLE;
+ else
+ flags |= PIN_HIGH;
- i915_vma_unpin_and_release(>status_page.vma,
- I915_VMA_RELEASE_MAP);
+ return i915_vma_pin(vma, 0, 0, flags);
}
static int init_status_page(struct intel_engine_cs *engine)
{
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- unsigned int flags;
void *vaddr;
int ret;
+ /*
+* Though the HWS register does support 36bit addresses, historically
+* we have had hangs and corruption reported due to wild writes if
+* the HWS is placed above 4G. We only allow objects to be allocated
+* in GFP_DMA32 for i965, and no earlier physical address users had
+* access to more than 4G.
+*/
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
if (IS_ERR(obj)) {
DRM_ERROR("Failed to allocate status page\n");
@@ -543,61 +577,30 @@ static int init_status_page(struct intel_engine_cs
*engine)
goto err;
}
- flags = PIN_GLOBAL;
- if (!HAS_LLC(engine->i915))
- /* On g33, we cannot place HWS above 256MiB, so
-* restrict its pinning to the low mappable arena.
-* Though this restriction is not documented for
-* gen4, gen5, or byt, they also behave similarly
-* and hang if the HWS is placed at the top of the
-* GTT. To generalise, it appears that all !llc
-* platforms have issues with us placing the HWS
-* above the mappable region (even though we never
-* actually map it).
-*/
- flags |= PIN_MAPPABLE;
- else
- flags |= PIN_HIGH;
- ret = i915_vma_pin(vma, 0, 0, flags);
- if (ret)
- goto err;
-
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
ret = PTR_ERR(vaddr);
- goto err_unpin;
+ goto err;
}
+ engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
engine->status_page.vma = vma;
- engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
- engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
+
+ if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
+ ret =
[Intel-gfx] [PATCH 19/33] drm/i915: Introduce concept of per-timeline (context) HWSP
Supplement the per-engine HWSP with a per-timeline HWSP. That is a
per-request pointer through which we can check a local seqno,
abstracting away the presumption of a global seqno. In this first step,
we point each request back into the engine's HWSP so everything
continues to work with the global timeline.
v2: s/i915_request_hwsp/hwsp_seqno/ to emphasis that this is the current
HW value and that we are accessing it via i915_request merely as a
convenience.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_request.c | 16 ++
drivers/gpu/drm/i915/i915_request.h | 45 -
drivers/gpu/drm/i915/intel_lrc.c| 9 --
3 files changed, 55 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 894b32258340..79eb1957cf99 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -182,10 +182,11 @@ static void free_capture_list(struct i915_request
*request)
static void __retire_engine_request(struct intel_engine_cs *engine,
struct i915_request *rq)
{
- GEM_TRACE("%s(%s) fence %llx:%lld, global=%d, current %d\n",
+ GEM_TRACE("%s(%s) fence %llx:%lld, global=%d, current %d:%d\n",
__func__, engine->name,
rq->fence.context, rq->fence.seqno,
rq->global_seqno,
+ hwsp_seqno(rq),
intel_engine_get_seqno(engine));
GEM_BUG_ON(!i915_request_completed(rq));
@@ -244,10 +245,11 @@ static void i915_request_retire(struct i915_request
*request)
{
struct i915_gem_active *active, *next;
- GEM_TRACE("%s fence %llx:%lld, global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld, global=%d, current %d:%d\n",
request->engine->name,
request->fence.context, request->fence.seqno,
request->global_seqno,
+ hwsp_seqno(request),
intel_engine_get_seqno(request->engine));
lockdep_assert_held(>i915->drm.struct_mutex);
@@ -307,10 +309,11 @@ void i915_request_retire_upto(struct i915_request *rq)
struct intel_ring *ring = rq->ring;
struct i915_request *tmp;
- GEM_TRACE("%s fence %llx:%lld, global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld, global=%d, current %d:%d\n",
rq->engine->name,
rq->fence.context, rq->fence.seqno,
rq->global_seqno,
+ hwsp_seqno(rq),
intel_engine_get_seqno(rq->engine));
lockdep_assert_held(>i915->drm.struct_mutex);
@@ -355,10 +358,11 @@ void __i915_request_submit(struct i915_request *request)
struct intel_engine_cs *engine = request->engine;
u32 seqno;
- GEM_TRACE("%s fence %llx:%lld -> global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld -> global=%d, current %d:%d\n",
engine->name,
request->fence.context, request->fence.seqno,
engine->timeline.seqno + 1,
+ hwsp_seqno(request),
intel_engine_get_seqno(engine));
GEM_BUG_ON(!irqs_disabled());
@@ -405,10 +409,11 @@ void __i915_request_unsubmit(struct i915_request *request)
{
struct intel_engine_cs *engine = request->engine;
- GEM_TRACE("%s fence %llx:%lld <- global=%d, current %d\n",
+ GEM_TRACE("%s fence %llx:%lld <- global=%d, current %d:%d\n",
engine->name,
request->fence.context, request->fence.seqno,
request->global_seqno,
+ hwsp_seqno(request),
intel_engine_get_seqno(engine));
GEM_BUG_ON(!irqs_disabled());
@@ -629,6 +634,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->ring = ce->ring;
rq->timeline = ce->ring->timeline;
GEM_BUG_ON(rq->timeline == >timeline);
+ rq->hwsp_seqno = >status_page.addr[I915_GEM_HWS_INDEX];
spin_lock_init(>lock);
dma_fence_init(>fence,
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index c0f084ca4f29..ade010fe6e26 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -130,6 +130,13 @@ struct i915_request {
struct i915_sched_node sched;
struct i915_dependency dep;
+ /*
+* A convenience pointer to the current breadcrumb value stored in
+* the HW status page (or our timeline's local equivalent). The full
+* path would be rq->hw_context->ring->timeline->hwsp_seqno.
+*/
+ const u32 *hwsp_seqno;
+
/**
* GEM sequence number associated with this request on the
* global execution timeline. It is zero when the request is not
@@ -285,11 +292,6 @@
[Intel-gfx] [PATCH 28/33] drm/i915: Drop fake breadcrumb irq
Missed breadcrumb detection is defunct due to the tight coupling with
dma_fence signaling and the myriad ways we may signal fences from
everywhere but from an interrupt, i.e. we frequently signal a fence
before we even see its interrupt. This means that even if we miss an
interrupt for a fence, it still is signaled before our breadcrumb
hangcheck fires, so simplify the breadcrumb hangchecking by moving it
into the GPU hangcheck and forgo fake interrupts.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 93 ---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 -
drivers/gpu/drm/i915/i915_gpu_error.h | 5 -
drivers/gpu/drm/i915/intel_breadcrumbs.c | 147 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 2 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 -
.../gpu/drm/i915/selftests/igt_live_test.c| 7 -
7 files changed, 5 insertions(+), 256 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e0ca3987eed6..fb216ce8dd60 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1322,9 +1322,6 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
intel_engine_last_submit(engine),
jiffies_to_msecs(jiffies -
engine->hangcheck.action_timestamp));
- seq_printf(m, "\tfake irq active? %s\n",
- yesno(test_bit(engine->id,
-
_priv->gpu_error.missed_irq_rings)));
seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
(long long)engine->hangcheck.acthd,
@@ -3900,94 +3897,6 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
-static int
-fault_irq_set(struct drm_i915_private *i915,
- unsigned long *irq,
- unsigned long val)
-{
- int err;
-
- err = mutex_lock_interruptible(>drm.struct_mutex);
- if (err)
- return err;
-
- err = i915_gem_wait_for_idle(i915,
-I915_WAIT_LOCKED |
-I915_WAIT_INTERRUPTIBLE,
-MAX_SCHEDULE_TIMEOUT);
- if (err)
- goto err_unlock;
-
- *irq = val;
- mutex_unlock(>drm.struct_mutex);
-
- /* Flush idle worker to disarm irq */
- drain_delayed_work(>gt.idle_work);
-
- return 0;
-
-err_unlock:
- mutex_unlock(>drm.struct_mutex);
- return err;
-}
-
-static int
-i915_ring_missed_irq_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
-
- *val = dev_priv->gpu_error.missed_irq_rings;
- return 0;
-}
-
-static int
-i915_ring_missed_irq_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- return fault_irq_set(i915, >gpu_error.missed_irq_rings, val);
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
- i915_ring_missed_irq_get, i915_ring_missed_irq_set,
- "0x%08llx\n");
-
-static int
-i915_ring_test_irq_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
-
- *val = dev_priv->gpu_error.test_irq_rings;
-
- return 0;
-}
-
-static int
-i915_ring_test_irq_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- /* GuC keeps the user interrupt permanently enabled for submission */
- if (USES_GUC_SUBMISSION(i915))
- return -ENODEV;
-
- /*
-* From icl, we can no longer individually mask interrupt generation
-* from each engine.
-*/
- if (INTEL_GEN(i915) >= 11)
- return -ENODEV;
-
- val &= INTEL_INFO(i915)->ring_mask;
- DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
-
- return fault_irq_set(i915, >gpu_error.test_irq_rings, val);
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
- i915_ring_test_irq_get, i915_ring_test_irq_set,
- "0x%08llx\n");
-
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIREBIT(2)
@@ -4750,8 +4659,6 @@ static const struct i915_debugfs_files {
} i915_debugfs_files[] = {
{"i915_wedged", _wedged_fops},
{"i915_cache_sharing", _cache_sharing_fops},
- {"i915_ring_missed_irq", _ring_missed_irq_fops},
- {"i915_ring_test_irq", _ring_test_irq_fops},
{"i915_gem_drop_caches", _drop_caches_fops},
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
{"i915_error_state", _error_state_fops},
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 420b94341433..965356c460ce 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++
[Intel-gfx] [PATCH 24/33] drm/i915: Track active timelines
Now that we pin timelines around use, we have a clearly defined lifetime
and convenient points at which we can track only the active timelines.
This allows us to reduce the list iteration to only consider those
active timelines and not all.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 4 +--
drivers/gpu/drm/i915/i915_reset.c| 2 +-
drivers/gpu/drm/i915/i915_timeline.c | 39 ++--
4 files changed, 29 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6a051381f535..d072f3369ee1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1977,7 +1977,7 @@ struct drm_i915_private {
struct i915_gt_timelines {
struct mutex mutex; /* protects list, tainted by GPU */
- struct list_head list;
+ struct list_head active_list;
/* Pack multiple timelines' seqnos into the same page */
spinlock_t hwsp_lock;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1bd724d663d9..05627000b77d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3248,7 +3248,7 @@ wait_for_timelines(struct drm_i915_private *i915,
return timeout;
mutex_lock(>mutex);
- list_for_each_entry(tl, >list, link) {
+ list_for_each_entry(tl, >active_list, link) {
struct i915_request *rq;
rq = i915_gem_active_get_unlocked(>last_request);
@@ -3276,7 +3276,7 @@ wait_for_timelines(struct drm_i915_private *i915,
/* restart after reacquiring the lock */
mutex_lock(>mutex);
- tl = list_entry(>list, typeof(*tl), link);
+ tl = list_entry(>active_list, typeof(*tl), link);
}
mutex_unlock(>mutex);
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index e88691da60c0..c3861a0219a9 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -856,7 +856,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
* No more can be submitted until we reset the wedged bit.
*/
mutex_lock(>gt.timelines.mutex);
- list_for_each_entry(tl, >gt.timelines.list, link) {
+ list_for_each_entry(tl, >gt.timelines.active_list, link) {
struct i915_request *rq;
long timeout;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 95c689826c8c..548c99bbf126 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -116,7 +116,6 @@ int i915_timeline_init(struct drm_i915_private *i915,
const char *name,
struct i915_vma *hwsp)
{
- struct i915_gt_timelines *gt = >gt.timelines;
void *vaddr;
/*
@@ -161,10 +160,6 @@ int i915_timeline_init(struct drm_i915_private *i915,
i915_syncmap_init(>sync);
- mutex_lock(>mutex);
- list_add(>link, >list);
- mutex_unlock(>mutex);
-
return 0;
}
@@ -173,7 +168,7 @@ void i915_timelines_init(struct drm_i915_private *i915)
struct i915_gt_timelines *gt = >gt.timelines;
mutex_init(>mutex);
- INIT_LIST_HEAD(>list);
+ INIT_LIST_HEAD(>active_list);
spin_lock_init(>hwsp_lock);
INIT_LIST_HEAD(>hwsp_free_list);
@@ -182,6 +177,24 @@ void i915_timelines_init(struct drm_i915_private *i915)
i915_gem_shrinker_taints_mutex(i915, >mutex);
}
+static void timeline_add_to_active(struct i915_timeline *tl)
+{
+ struct i915_gt_timelines *gt = >i915->gt.timelines;
+
+ mutex_lock(>mutex);
+ list_add(>link, >active_list);
+ mutex_unlock(>mutex);
+}
+
+static void timeline_remove_from_active(struct i915_timeline *tl)
+{
+ struct i915_gt_timelines *gt = >i915->gt.timelines;
+
+ mutex_lock(>mutex);
+ list_del(>link);
+ mutex_unlock(>mutex);
+}
+
/**
* i915_timelines_park - called when the driver idles
* @i915: the drm_i915_private device
@@ -198,7 +211,7 @@ void i915_timelines_park(struct drm_i915_private *i915)
struct i915_timeline *timeline;
mutex_lock(>mutex);
- list_for_each_entry(timeline, >list, link) {
+ list_for_each_entry(timeline, >active_list, link) {
/*
* All known fences are completed so we can scrap
* the current sync point tracking and start afresh,
@@ -212,16 +225,10 @@ void i915_timelines_park(struct drm_i915_private *i915)
void i915_timeline_fini(struct i915_timeline *timeline)
{
- struct i915_gt_timelines *gt = >i915->gt.timelines;
-
GEM_BUG_ON(timeline->pin_count);
[Intel-gfx] [PATCH 04/33] drm/i915: Compute the HWS offsets explicitly
Simplify by using sizeof(u32) to convert from the index inside the HWSP to the byte offset. This has the advantage of not only being shorter (and so not upsetting checkpatch!) but that it matches use where we are writing to byte addresses using other commands than MI_STORE_DWORD_IMM. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_guc_submission.c | 4 ++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 10 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index ab1c49b106f2..349ae5844f24 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -666,7 +666,7 @@ static void complete_preempt_context(struct intel_engine_cs *engine) execlists_unwind_incomplete_requests(execlists); wait_for_guc_preempt_report(engine); - intel_write_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX, 0); + intel_write_status_page(engine, I915_GEM_HWS_PREEMPT, 0); } /** @@ -824,7 +824,7 @@ static void guc_submission_tasklet(unsigned long data) } if (execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT) && - intel_read_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX) == + intel_read_status_page(engine, I915_GEM_HWS_PREEMPT) == GUC_PREEMPT_FINISHED) complete_preempt_context(engine); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 0834e91d4ace..5ad46c2fbc0f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -716,11 +716,11 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) * The area from dword 0x30 to 0x3ff is available for driver usage. */ #define I915_GEM_HWS_INDEX 0x30 -#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) -#define I915_GEM_HWS_PREEMPT_INDEX 0x32 -#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT_INDEX << MI_STORE_DWORD_INDEX_SHIFT) -#define I915_GEM_HWS_SCRATCH_INDEX 0x40 -#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) +#define I915_GEM_HWS_INDEX_ADDR(I915_GEM_HWS_INDEX * sizeof(u32)) +#define I915_GEM_HWS_PREEMPT 0x32 +#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32)) +#define I915_GEM_HWS_SCRATCH 0x40 +#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32)) #define I915_HWS_CSB_BUF0_INDEX0x10 #define I915_HWS_CSB_WRITE_INDEX 0x1f -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 29/33] drm/i915: Implement an "idle" barrier
We have a number of tasks that we like to run when idle and parking the
GPU into a powersaving mode. A few of those tasks are using the global
idle point as a convenient moment when all previous execution has been
required (and so we know that the GPU is not still touching random
user memory). However, on a busy system we are unlikely to see global
idle points, and would prefer a much more incremental system of being
able to retire after all current execution has completed.
Enter the idle barrier and idle tasks.
To determine a point in the future when all current tasks are complete,
we schedule a new low priority request that will be executed after all
current work is complete, and by imposing a barrier before all future
work. We therefore know we retire that barrier, the GPU is no longer
touching any memory released before the barrier was submitting allowing
us to run a set of idle tasks clear of any dangling GPU references.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_gem.c | 90
drivers/gpu/drm/i915/i915_request.c | 9 +++
drivers/gpu/drm/i915/i915_timeline.c | 3 +
4 files changed, 107 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d072f3369ee1..5ca77e2e53fb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2021,6 +2021,9 @@ struct drm_i915_private {
*/
struct delayed_work idle_work;
+ struct i915_gem_active idle_barrier;
+ struct list_head idle_tasks;
+
ktime_t last_init_time;
struct i915_vma *scratch;
@@ -3040,6 +3043,8 @@ void i915_gem_fini(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
unsigned int flags, long timeout);
+void i915_gem_add_idle_task(struct drm_i915_private *i915,
+ struct i915_gem_active *idle);
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 101a0f644787..0a8bcf6e7098 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -141,6 +141,15 @@ int i915_mutex_lock_interruptible(struct drm_device *dev)
return 0;
}
+static void call_idle_tasks(struct list_head *tasks)
+{
+ struct i915_gem_active *tsk, *tn;
+
+ list_for_each_entry_safe(tsk, tn, tasks, link)
+ tsk->retire(tsk, NULL);
+ INIT_LIST_HEAD(tasks);
+}
+
static u32 __i915_gem_park(struct drm_i915_private *i915)
{
intel_wakeref_t wakeref;
@@ -169,6 +178,8 @@ static u32 __i915_gem_park(struct drm_i915_private *i915)
*/
synchronize_irq(i915->drm.irq);
+ call_idle_tasks(>gt.idle_tasks);
+
intel_engines_park(i915);
i915_timelines_park(i915);
@@ -2906,6 +2917,81 @@ i915_gem_find_active_request(struct intel_engine_cs
*engine)
return active;
}
+static void idle_barrier(struct drm_i915_private *i915)
+{
+ struct i915_gt_timelines *gt = >gt.timelines;
+ struct i915_timeline *tl;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (list_empty(>gt.idle_tasks))
+ return;
+
+ if (!i915->gt.active_requests) {
+ call_idle_tasks(>gt.idle_tasks);
+ return;
+ }
+
+ /* Keep just one idle barrier in flight, amalgamating tasks instead */
+ if (i915_gem_active_isset(>gt.idle_barrier))
+ return;
+
+ GEM_TRACE("adding idle barrier\n");
+
+ rq = i915_request_alloc(i915->engine[RCS], i915->kernel_context);
+ if (IS_ERR(rq))
+ return;
+
+ /* run after all current requests have executed, but before any new */
+ mutex_lock(>mutex);
+ list_for_each_entry(tl, >active_list, link) {
+ struct i915_request *last;
+
+ if (tl == rq->timeline)
+ continue;
+
+ err = i915_timeline_set_barrier(tl, rq);
+ if (err == -EEXIST)
+ continue;
+ if (err)
+ break;
+
+ last = i915_gem_active_raw(>last_request,
+ >drm.struct_mutex);
+ if (!last)
+ continue;
+
+ mutex_unlock(>mutex); /* allocation ahead! */
+ err = i915_request_await_dma_fence(rq, >fence);
+ mutex_lock(>mutex);
+ if (err)
+ break;
+
+ /* restart after reacquiring the lock */
+ tl = list_entry(>active_list, typeof(*tl),
[Intel-gfx] [PATCH 06/33] drm/i915/execlists: Suppress redundant preemption
On unwinding the active request we give it a small (limited to internal
priority levels) boost to prevent it from being gazumped a second time.
However, this means that it can be promoted to above the request that
triggered the preemption request, causing a preempt-to-idle cycle for no
change. We can avoid this if we take the boost into account when
checking if the preemption request is valid.
v2: After preemption the active request will be after the preemptee if
they end up with equal priority.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 39
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 37defd14c198..6cef458f6b43 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -163,6 +163,8 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
+#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
+
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
struct intel_context *ce);
@@ -181,6 +183,34 @@ static inline int rq_prio(const struct i915_request *rq)
return rq->sched.attr.priority;
}
+static inline int active_prio(const struct i915_request *rq)
+{
+ int prio = rq_prio(rq);
+
+ /*
+* On unwinding the active request, we give it a priority bump
+* equivalent to a freshly submitted request. This protects it from
+* being gazumped again, but it would be preferable if we didn't
+* let it be gazumped in the first place!
+*
+* See __unwind_incomplete_requests()
+*/
+ if ((prio & ACTIVE_PRIORITY) != ACTIVE_PRIORITY &&
+ i915_request_started(rq)) {
+ /*
+* After preemption, we insert the active request at the
+* end of the new priority level. This means that we will be
+* _lower_ priority than the preemptee all things equal (and
+* so the preemption is valid), so adjust our comparison
+* accordingly.
+*/
+ prio |= ACTIVE_PRIORITY;
+ prio--;
+ }
+
+ return prio;
+}
+
static int queue_prio(const struct intel_engine_execlists *execlists)
{
struct i915_priolist *p;
@@ -203,7 +233,7 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
int q_prio)
{
const struct intel_context *ctx = rq->hw_context;
- const int last_prio = rq_prio(rq);
+ int last_prio;
if (!intel_engine_has_preemption(engine))
return false;
@@ -218,6 +248,7 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
* preempt. If that hint is stale or we may be trying to preempt
* ourselves, ignore the request.
*/
+ last_prio = active_prio(rq);
if (!__execlists_need_preempt(q_prio, last_prio))
return false;
@@ -344,7 +375,7 @@ static void __unwind_incomplete_requests(struct
intel_engine_cs *engine)
{
struct i915_request *rq, *rn, *active = NULL;
struct list_head *uninitialized_var(pl);
- int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
+ int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
lockdep_assert_held(>timeline.lock);
@@ -376,8 +407,8 @@ static void __unwind_incomplete_requests(struct
intel_engine_cs *engine)
* stream, so give it the equivalent small priority bump to prevent
* it being gazumped a second time by another peer.
*/
- if (!(prio & I915_PRIORITY_NEWCLIENT)) {
- prio |= I915_PRIORITY_NEWCLIENT;
+ if ((prio & ACTIVE_PRIORITY) != ACTIVE_PRIORITY) {
+ prio |= ACTIVE_PRIORITY;
active->sched.attr.priority = prio;
list_move_tail(>sched.link,
i915_sched_lookup_priolist(engine, prio));
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 32/33] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
Having introduced per-context seqno, we know have a means to identity
progress across the system without feel of rollback as befell the
global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
advance of submission safe in the knowledge that our target seqno and
address is stable.
However, since we are telling the GPU to busy-spin on the target address
until it matches the signaling seqno, we only want to do so when we are
sure that busy-spin will be completed quickly. To achieve this we only
submit the request to HW once the signaler is itself executing (modulo
preemption causing us to wait longer), and we only do so for default and
above priority requests (so that idle priority tasks never themselves
hog the GPU waiting for others).
But what AB-BA deadlocks? If you remove B, there can be no deadlock...
The issue is that with a deep ELSP queue, we can queue up a pair of
AB-BA on different engines, thus forming a classic mutual exclusion
deadlock. We side-step that issue by restricting the queue depth to
avoid having multiple semaphores in flight and so we only ever take one
set of locks at a time.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 149 +-
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_scheduler.c | 1 +
drivers/gpu/drm/i915/i915_scheduler.h | 1 +
drivers/gpu/drm/i915/i915_sw_fence.c | 4 +-
drivers/gpu/drm/i915/i915_sw_fence.h | 3 +
drivers/gpu/drm/i915/intel_gpu_commands.h | 5 +
drivers/gpu/drm/i915/intel_lrc.c | 14 +-
8 files changed, 174 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 690fb4eb6d15..a4318d9a6f34 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -22,8 +22,9 @@
*
*/
-#include
#include
+#include
+#include
#include
#include
#include
@@ -331,6 +332,76 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
+struct execute_cb {
+ struct list_head link;
+ struct irq_work work;
+ struct i915_sw_fence *fence;
+};
+
+static void irq_execute_cb(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ i915_sw_fence_complete(cb->fence);
+ kfree(cb);
+}
+
+static void __notify_execute_cb(struct i915_request *rq)
+{
+ struct execute_cb *cb;
+
+ lockdep_assert_held(>lock);
+
+ if (list_empty(>execute_cb))
+ return;
+
+ list_for_each_entry(cb, >execute_cb, link)
+ irq_work_queue(>work);
+
+ /*
+* XXX Rollback on __i915_request_unsubmit()
+*
+* In the future, perhaps when we have an active time-slicing scheduler,
+* it will be interesting to unsubmit parallel execution and remove
+* busywaits from the GPU until their master is restarted. This is
+* quite hairy, we have to carefully rollback the fence and do a
+* preempt-to-idle cycle on the target engine, all the while the
+* master execute_cb may refire.
+*/
+ INIT_LIST_HEAD(>execute_cb);
+}
+
+static int
+i915_request_await_execution(struct i915_request *rq,
+struct i915_request *signal,
+gfp_t gfp)
+{
+ struct execute_cb *cb;
+ unsigned long flags;
+
+ if (test_bit(I915_FENCE_FLAG_ACTIVE, >fence.flags))
+ return 0;
+
+ cb = kmalloc(sizeof(*cb), gfp);
+ if (!cb)
+ return -ENOMEM;
+
+ cb->fence = >submit;
+ i915_sw_fence_await(cb->fence);
+ init_irq_work(>work, irq_execute_cb);
+
+ spin_lock_irqsave(>lock, flags);
+ if (test_bit(I915_FENCE_FLAG_ACTIVE, >fence.flags)) {
+ i915_sw_fence_complete(cb->fence);
+ kfree(cb);
+ } else {
+ list_add_tail(>link, >execute_cb);
+ }
+ spin_unlock_irqrestore(>lock, flags);
+
+ return 0;
+}
+
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -377,6 +448,7 @@ void __i915_request_submit(struct i915_request *request)
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags) &&
!i915_request_enable_breadcrumb(request))
intel_engine_queue_breadcrumbs(engine);
+ __notify_execute_cb(request);
spin_unlock(>lock);
engine->emit_fini_breadcrumb(request,
@@ -639,6 +711,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
tl->fence_context, seqno);
INIT_LIST_HEAD(>active_list);
+ INIT_LIST_HEAD(>execute_cb);
rq->i915 = i915;
rq->engine = engine;
rq->gem_context = ctx;
@@ -719,6 +792,77 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
[Intel-gfx] [PATCH 11/33] drm/i915/selftests: Trim struct_mutex duration for set-wedged selftest
Trim the struct_mutex hold and exclude the call to i915_gem_set_wedged() as a reminder that it must be callable without struct_mutex held. Signed-off-by: Chris Wilson Cc: Michal Wajdeczko Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 67431355cd6e..8025c7e0bf6c 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -389,16 +389,16 @@ static int igt_wedged_reset(void *arg) /* Check that we can recover a wedged device with a GPU reset */ igt_global_reset_lock(i915); - mutex_lock(>drm.struct_mutex); wakeref = intel_runtime_pm_get(i915); i915_gem_set_wedged(i915); - GEM_BUG_ON(!i915_terminally_wedged(>gpu_error)); + mutex_lock(>drm.struct_mutex); + GEM_BUG_ON(!i915_terminally_wedged(>gpu_error)); i915_reset(i915, ALL_ENGINES, NULL); + mutex_unlock(>drm.struct_mutex); intel_runtime_pm_put(i915, wakeref); - mutex_unlock(>drm.struct_mutex); igt_global_reset_unlock(i915); return i915_terminally_wedged(>gpu_error) ? -EIO : 0; @@ -1675,6 +1675,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) wakeref = intel_runtime_pm_get(i915); saved_hangcheck = fetch_and_zero(_modparams.enable_hangcheck); + drain_delayed_work(>gpu_error.hangcheck_work); /* flush param */ err = i915_subtests(tests, i915); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 33/33] drm/i915: Prioritise non-busywait semaphore workloads
We don't want to busywait on the GPU if we have other work to do. If we
give non-busywaiting workloads higher (initial) priority than workloads
that require a busywait, we will prioritise work that is ready to run
immediately.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 3 +++
drivers/gpu/drm/i915/i915_scheduler.h | 7 ---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index a4318d9a6f34..5bda7356773c 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1132,6 +1132,9 @@ void i915_request_add(struct i915_request *request)
if (engine->schedule) {
struct i915_sched_attr attr = request->gem_context->sched;
+ if (!request->sched.semaphore)
+ attr.priority |= I915_PRIORITY_NOSEMAPHORE;
+
/*
* Boost priorities to new clients (new request flows).
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index d764cf10536f..7f194a8db785 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -24,14 +24,15 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 2
+#define I915_USER_PRIORITY_SHIFT 3
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-#define I915_PRIORITY_WAIT ((u8)BIT(0))
-#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_WAIT ((u8)BIT(0))
+#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2))
struct i915_sched_attr {
/**
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 113d6fa8b190..0be09ceb6c7c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,7 +164,7 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
-#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
+#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT | I915_PRIORITY_NOSEMAPHORE)
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
--
2.20.1
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[Intel-gfx] [PATCH 21/33] drm/i915: Allocate a status page for each timeline
Allocate a page for use as a status page by a group of timelines, as we
only need a dword of storage for each (rounded up to the cacheline for
safety) we can pack multiple timelines into the same page. Each timeline
will then be able to track its own HW seqno.
v2: Reuse the common per-engine HWSP for the solitary ringbuffer
timeline, so that we do not have to emit (using per-gen specialised
vfuncs) the breadcrumb into the distinct timeline HWSP and instead can
keep on using the common MI_STORE_DWORD_INDEX. However, to maintain the
sleight-of-hand for the global/per-context seqno switchover, we will
store both temporarily (and so use a custom offset for the shared timeline
HWSP until the switch over).
v3: Keep things simple and allocate a page for each timeline, page
sharing comes next.
v4: I was caught repeating the same MI_STORE_DWORD_IMM over and over
again in selftests.
v5: And caught red handed copying create timeline + check.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_timeline.c | 121 ++-
drivers/gpu/drm/i915/i915_timeline.h | 21 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 76 ++--
drivers/gpu/drm/i915/intel_lrc.c | 22 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 6 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_mock_selftests.h | 2 +-
.../gpu/drm/i915/selftests/i915_timeline.c| 326 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 14 +-
10 files changed, 543 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 79ab03a0fdfe..5b5f9dacfce9 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -9,28 +9,78 @@
#include "i915_timeline.h"
#include "i915_syncmap.h"
-void i915_timeline_init(struct drm_i915_private *i915,
- struct i915_timeline *timeline,
- const char *name)
+static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
+
+ vma = i915_vma_instance(obj, >ggtt.vm, NULL);
+ if (IS_ERR(vma))
+ i915_gem_object_put(obj);
+
+ return vma;
+}
+
+static int hwsp_alloc(struct i915_timeline *timeline)
+{
+ struct i915_vma *vma;
+
+ vma = __hwsp_alloc(timeline->i915);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ timeline->hwsp_ggtt = vma;
+ timeline->hwsp_offset = 0;
+
+ return 0;
+}
+
+int i915_timeline_init(struct drm_i915_private *i915,
+ struct i915_timeline *timeline,
+ const char *name,
+ struct i915_vma *global_hwsp)
{
struct i915_gt_timelines *gt = >gt.timelines;
+ void *vaddr;
+ int err;
/*
* Ideally we want a set of engines on a single leaf as we expect
* to mostly be tracking synchronisation between engines. It is not
* a huge issue if this is not the case, but we may want to mitigate
* any page crossing penalties if they become an issue.
+*
+* Called during early_init before we know how many engines there are.
*/
BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
timeline->i915 = i915;
timeline->name = name;
+ timeline->pin_count = 0;
- mutex_lock(>mutex);
- list_add(>link, >list);
- mutex_unlock(>mutex);
+ if (global_hwsp) {
+ timeline->hwsp_ggtt = i915_vma_get(global_hwsp);
+ timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR;
+ } else {
+ err = hwsp_alloc(timeline);
+ if (err)
+ return err;
+ }
+
+ vaddr = i915_gem_object_pin_map(timeline->hwsp_ggtt->obj, I915_MAP_WB);
+ if (IS_ERR(vaddr)) {
+ i915_vma_put(timeline->hwsp_ggtt);
+ return PTR_ERR(vaddr);
+ }
- /* Called during early_init before we know how many engines there are */
+ timeline->hwsp_seqno =
+ memset(vaddr + timeline->hwsp_offset, 0, CACHELINE_BYTES);
timeline->fence_context = dma_fence_context_alloc(1);
@@ -41,6 +91,12 @@ void i915_timeline_init(struct drm_i915_private *i915,
INIT_LIST_HEAD(>requests);
i915_syncmap_init(>sync);
+
+ mutex_lock(>mutex);
+ list_add(>link, >list);
+ mutex_unlock(>mutex);
+
+ return 0;
}
void i915_timelines_init(struct drm_i915_private *i915)
@@ -86,6 +142,7 @@ void i915_timeline_fini(struct i915_timeline *timeline)
{
struct
[Intel-gfx] [PATCH 31/33] drm/i915/execlists: Refactor out can_merge_rq()
In the next patch, we add another user that wants to check whether
requests can be merge into a single HW execution, and in the future we
want to add more conditions under which requests from the same context
cannot be merge. In preparation, extract out can_merge_rq().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cbf20273e9f8..151e4ae48ea0 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -284,12 +284,11 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
}
__maybe_unused static inline bool
-assert_priority_queue(const struct intel_engine_execlists *execlists,
- const struct i915_request *prev,
+assert_priority_queue(const struct i915_request *prev,
const struct i915_request *next)
{
- if (!prev)
- return true;
+ const struct intel_engine_execlists *execlists =
+ >engine->execlists;
/*
* Without preemption, the prev may refer to the still active element
@@ -594,6 +593,17 @@ static bool can_merge_ctx(const struct intel_context *prev,
return true;
}
+static bool can_merge_rq(const struct i915_request *prev,
+const struct i915_request *next)
+{
+ GEM_BUG_ON(!assert_priority_queue(prev, next));
+
+ if (!can_merge_ctx(prev->hw_context, next->hw_context))
+ return false;
+
+ return true;
+}
+
static void port_assign(struct execlist_port *port, struct i915_request *rq)
{
GEM_BUG_ON(rq == port_request(port));
@@ -744,8 +754,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
int i;
priolist_for_each_request_consume(rq, rn, p, i) {
- GEM_BUG_ON(!assert_priority_queue(execlists, last, rq));
-
/*
* Can we combine this request with the current port?
* It has to be the same context/ringbuffer and not
@@ -757,8 +765,10 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* second request, and so we never need to tell the
* hardware about the first.
*/
- if (last &&
- !can_merge_ctx(rq->hw_context, last->hw_context)) {
+ if (last && !can_merge_rq(last, rq)) {
+ if (last->hw_context == rq->hw_context)
+ goto done;
+
/*
* If we are on the second port and cannot
* combine this request with the last, then we
@@ -778,7 +788,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
ctx_single_port_submission(rq->hw_context))
goto done;
- GEM_BUG_ON(last->hw_context == rq->hw_context);
if (submit)
port_assign(port, last);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/33] drm/i915: Make all GPU resets atomic
In preparation for the next few commits, make resetting the GPU atomic.
Currently, we have prepared gen6+ for atomic resetting of individual
engines, but now there is a requirement to perform the whole device
level reset (just the register poking) from inside an atomic context.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reset.c | 90 ++-
1 file changed, 39 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c
b/drivers/gpu/drm/i915/i915_reset.c
index 342d9ee42601..2f840858572c 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -12,6 +12,8 @@
#include "intel_guc.h"
+#define RESET_MAX_RETRIES 3
+
static void engine_skip_context(struct i915_request *rq)
{
struct intel_engine_cs *engine = rq->engine;
@@ -144,14 +146,14 @@ static int i915_do_reset(struct drm_i915_private *i915,
/* Assert reset for at least 20 usec, and wait for acknowledgement. */
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
- usleep_range(50, 200);
- err = wait_for(i915_in_reset(pdev), 500);
+ udelay(50);
+ err = wait_for_atomic(i915_in_reset(pdev), 50);
/* Clear the reset request. */
pci_write_config_byte(pdev, I915_GDRST, 0);
- usleep_range(50, 200);
+ udelay(50);
if (!err)
- err = wait_for(!i915_in_reset(pdev), 500);
+ err = wait_for_atomic(!i915_in_reset(pdev), 50);
return err;
}
@@ -171,7 +173,7 @@ static int g33_do_reset(struct drm_i915_private *i915,
struct pci_dev *pdev = i915->drm.pdev;
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
- return wait_for(g4x_reset_complete(pdev), 500);
+ return wait_for_atomic(g4x_reset_complete(pdev), 50);
}
static int g4x_do_reset(struct drm_i915_private *dev_priv,
@@ -182,13 +184,13 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
int ret;
/* WaVcpClkGateDisableForMediaReset:ctg,elk */
- I915_WRITE(VDECCLK_GATE_D,
- I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
- POSTING_READ(VDECCLK_GATE_D);
+ I915_WRITE_FW(VDECCLK_GATE_D,
+ I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ_FW(VDECCLK_GATE_D);
pci_write_config_byte(pdev, I915_GDRST,
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
- ret = wait_for(g4x_reset_complete(pdev), 500);
+ ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
DRM_DEBUG_DRIVER("Wait for media reset failed\n");
goto out;
@@ -196,7 +198,7 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
pci_write_config_byte(pdev, I915_GDRST,
GRDOM_RENDER | GRDOM_RESET_ENABLE);
- ret = wait_for(g4x_reset_complete(pdev), 500);
+ ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
@@ -205,9 +207,9 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv,
out:
pci_write_config_byte(pdev, I915_GDRST, 0);
- I915_WRITE(VDECCLK_GATE_D,
- I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
- POSTING_READ(VDECCLK_GATE_D);
+ I915_WRITE_FW(VDECCLK_GATE_D,
+ I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ_FW(VDECCLK_GATE_D);
return ret;
}
@@ -218,27 +220,29 @@ static int ironlake_do_reset(struct drm_i915_private
*dev_priv,
{
int ret;
- I915_WRITE(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
- ret = intel_wait_for_register(dev_priv,
- ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
- 500);
+ I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ ILK_GRDOM_RESET_ENABLE, 0,
+ 5000, 0,
+ NULL);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
}
- I915_WRITE(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
- ret = intel_wait_for_register(dev_priv,
- ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
- 500);
+ I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ ILK_GRDOM_RESET_ENABLE, 0,
+ 5000, 0,
+ NULL);
if (ret) {
[Intel-gfx] [PATCH 30/33] drm/i915: Keep timeline HWSP allocated until the system is idle
In preparation for enabling HW semaphores, we need to keep in flight
timeline HWSP alive until the entire system is idle, as any other
timeline active on the GPU may still refer back to the already retired
timeline. We both have to delay recycling available cachelines and
unpinning old HWSP until the next idle point (i.e. on parking).
That we have to keep the HWSP alive for external references on HW raises
an interesting conundrum. On a busy system, we may never see a global
idle point, essentially meaning the resource will be leaking until we
are forced to sleep. What we need is a set of RCU primitives for the GPU!
This should also help mitigate the resource starvation issues
promulgating from keeping all logical state pinned until idle (instead
of as currently handled until the next context switch).
v2: Use idle barriers to free stale HWSP as soon as all current requests
are idle, rather than rely on the system reaching a global idle point.
(Tvrtko)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 33
drivers/gpu/drm/i915/i915_timeline.c | 118 +++
drivers/gpu/drm/i915/i915_timeline.h | 1 +
3 files changed, 121 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index b397155fe8a7..690fb4eb6d15 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -331,11 +331,6 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
-static u32 timeline_get_seqno(struct i915_timeline *tl)
-{
- return tl->seqno += 1 + tl->has_initial_breadcrumb;
-}
-
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -555,8 +550,10 @@ struct i915_request *
i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context
*ctx)
{
struct drm_i915_private *i915 = engine->i915;
- struct i915_request *rq;
struct intel_context *ce;
+ struct i915_timeline *tl;
+ struct i915_request *rq;
+ u32 seqno;
int ret;
lockdep_assert_held(>drm.struct_mutex);
@@ -631,7 +628,15 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
}
}
- rq->rcustate = get_state_synchronize_rcu();
+ tl = ce->ring->timeline;
+ GEM_BUG_ON(tl == >timeline);
+ ret = i915_timeline_get_seqno(tl, );
+ if (ret)
+ goto err_free;
+
+ spin_lock_init(>lock);
+ dma_fence_init(>fence, _fence_ops, >lock,
+ tl->fence_context, seqno);
INIT_LIST_HEAD(>active_list);
rq->i915 = i915;
@@ -639,16 +644,9 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->gem_context = ctx;
rq->hw_context = ce;
rq->ring = ce->ring;
- rq->timeline = ce->ring->timeline;
- GEM_BUG_ON(rq->timeline == >timeline);
- rq->hwsp_seqno = rq->timeline->hwsp_seqno;
-
- spin_lock_init(>lock);
- dma_fence_init(>fence,
- _fence_ops,
- >lock,
- rq->timeline->fence_context,
- timeline_get_seqno(rq->timeline));
+ rq->timeline = tl;
+ rq->hwsp_seqno = tl->hwsp_seqno;
+ rq->rcustate = get_state_synchronize_rcu();
/* We bump the ref for the fence chain */
i915_sw_fence_init(_request_get(rq)->submit, submit_notify);
@@ -713,6 +711,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
GEM_BUG_ON(!list_empty(>sched.signalers_list));
GEM_BUG_ON(!list_empty(>sched.waiters_list));
+err_free:
kmem_cache_free(i915->requests, rq);
err_unreserve:
unreserve_gt(i915);
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 60b2e1c3abf4..ef5484931ad5 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -10,8 +10,9 @@
#include "i915_syncmap.h"
struct i915_timeline_hwsp {
- struct i915_vma *vma;
+ struct i915_gt_timelines *gt;
struct list_head free_link;
+ struct i915_vma *vma;
u64 free_bitmap;
};
@@ -65,6 +66,7 @@ static struct i915_vma *hwsp_alloc(struct i915_timeline
*timeline, int *offset)
vma->private = hwsp;
hwsp->vma = vma;
hwsp->free_bitmap = ~0ull;
+ hwsp->gt = gt;
spin_lock(>hwsp_lock);
list_add(>free_link, >hwsp_free_list);
@@ -84,14 +86,9 @@ static struct i915_vma *hwsp_alloc(struct i915_timeline
*timeline, int *offset)
return hwsp->vma;
}
-static void hwsp_free(struct i915_timeline *timeline)
+static void __idle_hwsp_free(struct i915_timeline_hwsp *hwsp, int offset)
{
- struct i915_gt_timelines *gt = >i915->gt.timelines;
-
[Intel-gfx] [PATCH 18/33] drm/i915: Move list of timelines under its own lock
Currently, the list of timelines is serialised by the struct_mutex, but
to alleviate difficulties with using that mutex in future, move the
list management under its own dedicated mutex.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_gem.c | 103 ++
drivers/gpu/drm/i915/i915_reset.c | 8 +-
drivers/gpu/drm/i915/i915_timeline.c | 38 ++-
drivers/gpu/drm/i915/i915_timeline.h | 3 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 7 +-
.../gpu/drm/i915/selftests/mock_timeline.c| 3 +-
7 files changed, 109 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0133d1da3d3c..8a181b455197 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1975,7 +1975,10 @@ struct drm_i915_private {
void (*resume)(struct drm_i915_private *);
void (*cleanup_engine)(struct intel_engine_cs *engine);
- struct list_head timelines;
+ struct i915_gt_timelines {
+ struct mutex mutex; /* protects list, tainted by GPU */
+ struct list_head list;
+ } timelines;
struct list_head active_rings;
struct list_head closed_vma;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 653c7ba4c69f..d68f3fdd8a8e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3224,33 +3224,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
return ret;
}
-static long wait_for_timeline(struct i915_timeline *tl,
- unsigned int flags, long timeout)
-{
- struct i915_request *rq;
-
- rq = i915_gem_active_get_unlocked(>last_request);
- if (!rq)
- return timeout;
-
- /*
-* "Race-to-idle".
-*
-* Switching to the kernel context is often used a synchronous
-* step prior to idling, e.g. in suspend for flushing all
-* current operations to memory before sleeping. These we
-* want to complete as quickly as possible to avoid prolonged
-* stalls, so allow the gpu to boost to maximum clocks.
-*/
- if (flags & I915_WAIT_FOR_IDLE_BOOST)
- gen6_rps_boost(rq, NULL);
-
- timeout = i915_request_wait(rq, flags, timeout);
- i915_request_put(rq);
-
- return timeout;
-}
-
static int wait_for_engines(struct drm_i915_private *i915)
{
if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) {
@@ -3264,6 +3237,52 @@ static int wait_for_engines(struct drm_i915_private
*i915)
return 0;
}
+static long
+wait_for_timelines(struct drm_i915_private *i915,
+ unsigned int flags, long timeout)
+{
+ struct i915_gt_timelines *gt = >gt.timelines;
+ struct i915_timeline *tl;
+
+ if (!READ_ONCE(i915->gt.active_requests))
+ return timeout;
+
+ mutex_lock(>mutex);
+ list_for_each_entry(tl, >list, link) {
+ struct i915_request *rq;
+
+ rq = i915_gem_active_get_unlocked(>last_request);
+ if (!rq)
+ continue;
+
+ mutex_unlock(>mutex);
+
+ /*
+* "Race-to-idle".
+*
+* Switching to the kernel context is often used a synchronous
+* step prior to idling, e.g. in suspend for flushing all
+* current operations to memory before sleeping. These we
+* want to complete as quickly as possible to avoid prolonged
+* stalls, so allow the gpu to boost to maximum clocks.
+*/
+ if (flags & I915_WAIT_FOR_IDLE_BOOST)
+ gen6_rps_boost(rq, NULL);
+
+ timeout = i915_request_wait(rq, flags, timeout);
+ i915_request_put(rq);
+ if (timeout < 0)
+ return timeout;
+
+ /* restart after reacquiring the lock */
+ mutex_lock(>mutex);
+ tl = list_entry(>list, typeof(*tl), link);
+ }
+ mutex_unlock(>mutex);
+
+ return timeout;
+}
+
int i915_gem_wait_for_idle(struct drm_i915_private *i915,
unsigned int flags, long timeout)
{
@@ -3275,17 +3294,15 @@ int i915_gem_wait_for_idle(struct drm_i915_private
*i915,
if (!READ_ONCE(i915->gt.awake))
return 0;
+ timeout = wait_for_timelines(i915, flags, timeout);
+ if (timeout < 0)
+ return timeout;
+
if (flags & I915_WAIT_LOCKED) {
- struct i915_timeline *tl;
int err;
lockdep_assert_held(>drm.struct_mutex);
-
[Intel-gfx] [PATCH 27/33] drm/i915: Replace global breadcrumbs with per-context interrupt tracking
A few years ago, see commit 688e6c725816 ("drm/i915: Slaughter the
thundering i915_wait_request herd"), the issue of handling multiple
clients waiting in parallel was brought to our attention. The
requirement was that every client should be woken immediately upon its
request being signaled, without incurring any cpu overhead.
To handle certain fragility of our hw meant that we could not do a
simple check inside the irq handler (some generations required almost
unbounded delays before we could be sure of seqno coherency) and so
request completion checking required delegation.
Before commit 688e6c725816, the solution was simple. Every client waking
on a request would be woken on every interrupt and each would do a
heavyweight check to see if their request was complete. Commit
688e6c725816 introduced an rbtree so that only the earliest waiter on
the global timeline would woken, and would wake the next and so on.
(Along with various complications to handle requests being reordered
along the global timeline, and also a requirement for kthread to provide
a delegate for fence signaling that had no process context.)
The global rbtree depends on knowing the execution timeline (and global
seqno). Without knowing that order, we must instead check all contexts
queued to the HW to see which may have advanced. We trim that list by
only checking queued contexts that are being waited on, but still we
keep a list of all active contexts and their active signalers that we
inspect from inside the irq handler. By moving the waiters onto the fence
signal list, we can combine the client wakeup with the dma_fence
signaling (a dramatic reduction in complexity, but does require the HW
being coherent, the seqno must be visible from the cpu before the
interrupt is raised - we keep a timer backup just in case).
Having previously fixed all the issues with irq-seqno serialisation (by
inserting delays onto the GPU after each request instead of random delays
on the CPU after each interrupt), we can rely on the seqno state to
perfom direct wakeups from the interrupt handler. This allows us to
preserve our single context switch behaviour of the current routine,
with the only downside that we lose the RT priority sorting of wakeups.
In general, direct wakeup latency of multiple clients is about the same
(about 10% better in most cases) with a reduction in total CPU time spent
in the waiter (about 20-50% depending on gen). Average herd behaviour is
improved, but at the cost of not delegating wakeups on task_prio.
v2: Capture fence signaling state for error state and add comments to
warm even the most cold of hearts.
v3: Check if the request is still active before busywaiting
v4: Reduce the amount of pointer misdirection with list_for_each_safe
and using a local i915_request variable inside the loops
References: 688e6c725816 ("drm/i915: Slaughter the thundering i915_wait_request
herd")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 28 +-
drivers/gpu/drm/i915/i915_gem_context.c | 3 +
drivers/gpu/drm/i915/i915_gem_context.h | 2 +
drivers/gpu/drm/i915/i915_gpu_error.c | 83 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 9 +-
drivers/gpu/drm/i915/i915_irq.c | 88 +-
drivers/gpu/drm/i915/i915_request.c | 140 +--
drivers/gpu/drm/i915/i915_request.h | 72 +-
drivers/gpu/drm/i915/i915_reset.c | 13 +-
drivers/gpu/drm/i915/intel_breadcrumbs.c | 818 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 35 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 94 +-
.../drm/i915/selftests/i915_mock_selftests.h | 1 -
drivers/gpu/drm/i915/selftests/i915_request.c | 420 +
drivers/gpu/drm/i915/selftests/igt_spinner.c | 5 -
.../drm/i915/selftests/intel_breadcrumbs.c| 470 --
.../gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/selftests/lib_sw_fence.c | 54 ++
drivers/gpu/drm/i915/selftests/lib_sw_fence.h | 3 +
drivers/gpu/drm/i915/selftests/mock_engine.c | 17 +-
drivers/gpu/drm/i915/selftests/mock_engine.h | 6 -
22 files changed, 886 insertions(+), 1483 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b64f758803f3..e0ca3987eed6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1316,29 +1316,16 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
for_each_engine(engine, dev_priv, id) {
- struct intel_breadcrumbs *b = >breadcrumbs;
- struct rb_node *rb;
-
seq_printf(m, "%s:\n", engine->name);
seq_printf(m, "\tseqno = %x [current %x, last %x], %dms
Re: [Intel-gfx] linux-next: Fixes tag needs some work in the drm-intel-fixes tree
Hi, On Fri, 25 Jan 2019 01:21:26 + "Li, Weinan Z" wrote: > > I am not sure about the problem. The commit id "0cce2823ed37" is just > for the patch of "drm/i915/gvt: Refine error handling for > prepare_execlist_workload". Is there any other problems I missed? Its just that the subject line of that commit has a space after the ':', but the copy of that subject line in the Fixes tag omitted that space. This is not a big issue, my script just pointed it out. Its not worth doing anything about it, just take a bit more care in the future. -- Cheers, Stephen Rothwell pgpZ_gkRc342M.pgp Description: OpenPGP digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-next: Fixes tag needs some work in the drm-intel-fixes tree
Thank Stephen.
I am not sure about the problem. The commit id "0cce2823ed37" is just for the
patch of "drm/i915/gvt: Refine error handling for prepare_execlist_workload".
Is there any other problems I missed?
Regards.
-Weinan
> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Thursday, January 24, 2019 7:33 PM
> To: Stephen Rothwell ; Daniel Vetter
> ; Joonas Lahtinen ;
> Vivi, Rodrigo ; Intel Graphics
> ; DRI
> Cc: Linux Next Mailing List ; Linux Kernel
> Mailing List
> ; Li, Weinan Z ; Zhenyu
> Wang
> Subject: Re: linux-next: Fixes tag needs some work in the drm-intel-fixes tree
>
> On Thu, 24 Jan 2019, Stephen Rothwell wrote:
> > Hi all,
> >
> > In commit
> >
> > 0f7555121609 ("drm/i915/gvt: release shadow batch buffer and wa_ctx
> > before destroy one workload")
> >
> > Fixes tag
> >
> > Fixes: 0cce2823ed37 ("drm/i915/gvt/kvmgt:Refine error handling for
> > prepare_execlist_workload")
> >
> > has these problem(s):
> >
> > - Subject does not match target commit subject
> >
> > Just some whitespace.
>
> Thanks for the report. The commit being referenced seems to be the right one,
> though, so I don't think I'm going to force push to fix this.
>
> BR,
> Jani.
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [RFC] drm/i915/dp: Preliminary support for 2 pipe 1 port mode for 5K@120
On Thu, Jan 24, 2019 at 12:23:45PM +0100, Maarten Lankhorst wrote:
> Op 23-01-2019 om 18:31 schreef Matt Roper:
> > On Tue, Jan 22, 2019 at 01:12:07PM -0800, Manasi Navare wrote:
> >> On Gen 11 platform, to enable resolutions like 5K@120 where
> >> the pixel clock is greater than pipe pixel rate, we need to split it across
> >> 2 pipes and enable it using DSC and big joiner. In order to support this
> >> dual pipe single port mode, we need to link two crtcs involved in this
> >> ganged mode.
> >>
> >> This patch is a RFC patch that links two crtcs using linked_crtc pointer
> >> in intel_crtc_state and slave to indicate if the crtc is a master or slave.
> >> Here the HW necessitates the first CRTC to be the master CRTC through which
> >> the final output will be driven and the next consecutive CRTC should be
> >> slave crtc.
> >>
> >> This is currently not tested, but I wanted to get some inputs on this
> >> approach.
> >> The idea is to follow the same approach used in Ganged plane mode for NV12
> >> planes.
> >>
> >> Suggested-by: Maarten Lankhorst ,
> >> Matt Roper
> >> Cc: Ville Syrjälä
> >> Cc: Matt Roper
> >> Cc: Maarten Lankhorst
> >> Signed-off-by: Manasi Navare
> > Looks like the right general approach of using slave/master. I agree
> > with Ville and Maarten's feedback as well.
> >
> > The other thing we're going to need to worry about is dealing with all
> > the planes on the two crtc's. Suppose we have a userspace-visible state
> > of:
> >
> >Pipe A: off
> >Pipe B: 5000x2000@120 (using round numbers to make example simpler)
> > Plane 0: RGB32: pos (0,0), width=5000, height=2000
> > Plane 1: RGB32: pos (100,100), width=100, height=100
> > Plane 2: RGB32: pos (4800,1800), width=100, height=100
> > Plane 3: RGB32: pos (0,0), width=3000, height=2000
> > Plane 4: NV12: pos (2000,0), width=1000, height=2000
> > Plane 5: off
> > Plane 6: off
> >Pipe C: off
> >
> > this means that we need to grab extra planes on the other CRTC and
> > adjust their size, position, and/or surface offsets accordingly. So the
> > internal driver state that we actually program into the hardware needs
> > to be something like:
> >
> >Pipe A: off
> >Pipe B: 2500x1000 (master)
> > Plane 0: pos (0,0), width=2500, height=2000
> > Plane 1: pos (100,100), width=100, height=100
> > Plane 2: off
> > Plane 3: pos (0, 0), width=2500, height=2000
> > Plane 4{UV}: pos (2000, 0), width=500, height=2000
> > Plane 5{Y}: pos (2000, 0), width=500, height=2000
> > Plane 6: off
> >Pipe C: 2500x1000 (slave)
> > Plane 0: pos (0,0), offset=(2500,0), width=2500, height=2000
> > Plane 1: off
> > Plane 2: pos (2300,1800), width=100, height=100
> > Plane 3: pos (0, 0), offset=(2500, 0), width=500, height=2000
> > Plane 4{UV}: pos (0, 0), offset=(500,0), width=500, height=2000
> > Plane 5{Y}: pos (0, 0), offset=(500,0), width=500, height=2000
> > Plane 6: off
> >
> > So I think Ville is right; we're going to need to really copy a lot of
> > the userspace-facing state data into our own internal state structures
> > so that we can do the various adjustments on it. As you can see above
> > there are cases (2pi1po + nv12) where a single userspace plane request
> > translates into us programming four different sets of plane register
> > values.
>
> Yeah I fear you're right.
> Lets see, we would need to sanitize the driver big time..
>
>
> struct drm_crtc_state {
> struct drm_crtc *crtc;
> bool enable;
> bool active;
> bool planes_changed : 1;
> bool mode_changed : 1;
> bool active_changed : 1;
> bool connectors_changed : 1;
> bool zpos_changed : 1; // unused
> bool color_mgmt_changed : 1;
> bool no_vblank : 1; //unused
> u32 plane_mask;
> u32 connector_mask;
> u32 encoder_mask;
> struct drm_display_mode adjusted_mode;
> struct drm_display_mode mode;
> struct drm_property_blob *mode_blob;
> struct drm_property_blob *degamma_lut;
> struct drm_property_blob *ctm;
> struct drm_property_blob *gamma_lut;
> u32 target_vblank; // unused
> u32 pageflip_flags; // unused
> struct drm_pending_vblank_event *event;
> struct drm_crtc_commit *commit;
> struct drm_atomic_state *state;
> };
>
> First the good, it looks like we can safely re-use the following in the
> slave, without affecting userspace:
> struct drm_crtc * crtc;
> u32 last_vblank_count; // ignored in i915
> struct drm_display_mode adjusted_mode; // sort of handled by core, but on
> disable we can write our own mode here
> struct drm_pending_vblank_event * event; // handled by core
> struct drm_atomic_state * state; // handled by core
Okay so these above fields can be part of the drm_crtc_uapi_state as suggested
by Ville. So that these exposed to the userspace
do not change irrespective of master-slave behaviour and can be just used to
configure master_crtc and
Re: [Intel-gfx] [PATCH 4/4] drm/i915/psr: Add HBR3 support
On Tue, 2019-01-22 at 14:42 -0800, Dhinakaran Pandiyan wrote:
> On Wed, 2019-01-16 at 15:43 -0800, José Roberto de Souza wrote:
> > If the sink and source supports HBR3, TP4 should be used as link
> > training pattern.
> > For PSR2 there is no register to set and enable TP4 but according
> > to
> > eDP spec TP3 is still a training pattern acceptable for HBR3
> > panels.
> >
> Sounds like TP3 and TP4 are used only with PSR1, please document that
> in the commit message.
The line above is not enough?
> > Cc: Manasi Navare
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: José Roberto de Souza
> > ---
> >
> > Still trying to understand how PSR1 was working on ICL while
> > sending
> > TP4 to a panel that only supports HBR2.
>
> That's a good point, along with that please find out what Bit 11:
> "TPS4
> Control" does. I'd like us get these questions answered, if possible,
> before merging this series.
So according to eDP spec, DPCD 00071h, bit 0 - Link Training
Requirement of Sink on PSR Exit when Main-Link is OFF documentation:
"New to eDP v1.4, PSR2 Only: This bit is “Don’t Care” for devices
that support PSR2 because Fast Sleep/Wake support is required
for those devices."
So for sinks thats supports alpm is not necessary send the training
patterns, so it was sending TPS4 but sync was just ignoring it that is
why it was working on ICL.
But I guess is better for us to keep sending training patterns for now,
after a couple of kernel releases we could think in remove it.
I'm still looking for a panel without alpm to test if the current code
would break PSR on ICL.
>
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_dp_link_training.c | 2 +-
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_psr.c | 24 ++-
> > --
> > --
> > 4 files changed, 21 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 5faca634ee70..1e792309a79e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4162,6 +4162,7 @@ enum {
> > #define EDP_PSR_TP1_TP3_SEL (1 << 11)
> > #define EDP_PSR_CRC_ENABLE (1 << 10) /*
> > BDW+ */
> > #define EDP_PSR_TP2_TP3_TIME_SHIFT (8)
> > +#define EDP_PSR_TP4_TIME_SHIFT (6) /* ICL+ */
> > #define EDP_PSR_TP1_TIME_SHIFT (4)
> > #define EDP_PSR_IDLE_FRAME_SHIFT 0
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > index 30be0e39bd5f..3e9798a5498c 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > @@ -238,7 +238,7 @@ intel_dp_link_training_clock_recovery(struct
> > intel_dp *intel_dp)
> > * or for 1.4 devices that support it, training Pattern 3 for HBR2
> > * or 1.2 devices that support it, Training Pattern 2 otherwise.
> > */
> > -static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
> > +u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
> > {
> > bool source_tps3, sink_tps3, source_tps4, sink_tps4;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index e5a436c33307..fc3e6ae92276 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1807,6 +1807,7 @@ int
> > intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> > int link_rate, uint8_t
> > lane_count);
> > void intel_dp_start_link_train(struct intel_dp *intel_dp);
> > void intel_dp_stop_link_train(struct intel_dp *intel_dp);
> > +u32 intel_dp_training_pattern(struct intel_dp *intel_dp);
> > int intel_dp_retrain_link(struct intel_encoder *encoder,
> > struct drm_modeset_acquire_ctx *ctx);
> > void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 2fc537fb6e78..b0525940e5e9 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -440,6 +440,7 @@ static void hsw_activate_psr1(struct intel_dp
> > *intel_dp)
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > u32 max_sleep_time = 0x1f;
> > u32 val = EDP_PSR_ENABLE;
> > + u32 tp;
> >
> > /* Let's use 6 as the minimum to cover all known cases
> > including the
> > * off-by-one issue that HW has in some cases.
> > @@ -460,13 +461,24 @@ static void hsw_activate_psr1(struct intel_dp
> > *intel_dp)
> > val |= EDP_PSR_LINK_STANDBY;
> >
> > val |= dev_priv->vbt.psr.tp1_wakeup_time <<
> > EDP_PSR_TP1_TIME_SHIFT;
> > - val |= dev_priv->vbt.psr.tp2_tp3_tp4_wakeup_time <<
> > EDP_PSR_TP2_TP3_TIME_SHIFT;
> >
> > - if
Re: [Intel-gfx] [PATCH 5/6] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
Quoting Tvrtko Ursulin (2019-01-24 11:42:02)
> +static int gen8_emit_rpcs_config(struct i915_request *rq,
> +struct intel_context *ce,
> +struct intel_sseu sseu)
> +{
> + u64 offset;
> + u32 *cs;
> +
> + cs = intel_ring_begin(rq, 4);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + offset = ce->state->node.start +
Noted that we can do
u32 offset = i915_ggtt_offset(ce->state);
and chain all the asserts that this is indeed GGTT.
> + LRC_STATE_PN * PAGE_SIZE +
> + (CTX_R_PWR_CLK_STATE + 1) * 4;
> +
> + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> + *cs++ = lower_32_bits(offset);
> + *cs++ = upper_32_bits(offset);
> + *cs++ = gen8_make_rpcs(rq->i915, );
> +
> + intel_ring_advance(rq, cs);
> +
> + return 0;
> +}
> +
> +static int
> +gen8_modify_rpcs_gpu(struct intel_context *ce,
> +struct intel_engine_cs *engine,
> +struct intel_sseu sseu)
> +{
> + struct drm_i915_private *i915 = engine->i915;
> + struct i915_request *rq, *prev;
> + intel_wakeref_t wakeref;
> + int ret;
> +
> + GEM_BUG_ON(!ce->pin_count);
> +
> + lockdep_assert_held(>drm.struct_mutex);
> +
> + /* Submitting requests etc needs the hw awake. */
> + wakeref = intel_runtime_pm_get(i915);
> +
> + rq = i915_request_alloc(engine, i915->kernel_context);
> + if (IS_ERR(rq)) {
> + ret = PTR_ERR(rq);
> + goto out_put;
> + }
> +
> + /* Queue this switch after all other activity by this context. */
> + prev = i915_gem_active_raw(>ring->timeline->last_request,
> + >drm.struct_mutex);
> + if (prev && !i915_request_completed(prev)) {
> + ret = i915_sw_fence_await_sw_fence_gfp(>submit,
> + >submit,
> + I915_FENCE_GFP);
Looking back at this, this function is a bit on the lowlevel side for
us. You have to look carefully at the construction to be sure that both
rq and prev are on the same engine (which isn't available from the
immediate function parameters)
I suggest we use the more friendly
ret = i915_request_await_dma_fence(rq, >fence);
if (ret)
goto out_add;
The downside is that we add the timeline sync points, which we don't
ever expect to benefit from (except maybe on errors).
> + if (ret < 0)
> + goto out_add;
> + }
> +
> + ret = gen8_emit_rpcs_config(rq, ce, sseu);
> + if (ret)
> + goto out_add;
> +
> + /* Order all following requests to be after. */
> + i915_timeline_set_barrier(ce->ring->timeline, rq);
I've made this return an error, beware. :)
> +
> + /*
> +* Guarantee context image and the timeline remains pinned until the
> +* modifying request is retired by setting the ce activity tracker.
> +*
> +* But we only need to take one pin on the account of it. Or in other
> +* words transfer the pinned ce object to tracked active request.
> +*/
> + if (!i915_gem_active_isset(>active_tracker))
> + __intel_context_pin(ce);
> + i915_gem_active_set(>active_tracker, rq);
> +
> +out_add:
> + i915_request_add(rq);
> +out_put:
> + intel_runtime_pm_put(i915, wakeref);
> +
> + return ret;
> +}
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Re: [Intel-gfx] [PATCH v2 1/6] drm/i915: Add a new "remapped" gtt_view
Quoting Ville Syrjälä (2019-01-15 13:43:41) > On Mon, Jan 14, 2019 at 09:55:10AM +, Tvrtko Ursulin wrote: > > > > On 11/01/2019 19:46, Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > > > To overcome display engine stride limits we'll want to remap the > > > pages in the GTT. To that end we need a new gtt_view type which > > > is just like the "rotated" type except not rotated. > > > > I think I asked this before, so sorry if you also answered it - what > > about rotated setups which go over display engine stride limits? > > We already have the code to do the rotated mapping. > > > > > > v2: Use intel_remapped_plane_info base type > > > s/unused/unused_mbz/ (Chris) > > > Separate BUILD_BUG_ON()s (Chris) > > > Use I915_GTT_PAGE_SIZE (Chris) > > > v3: Use i915_gem_object_get_dma_address() (Chris) > > > Trim the sg (Tvrtko) > > > v4: Actually trim this time. Limit the max length > > > to one row of pages to keep things simple > > > > > > Cc: Chris Wilson > > > Cc: Tvrtko Ursulin > > > Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 2/8] drm/i915/selftests: Add mock selftest for remapped vmas
Quoting Ville Syrjala (2019-01-24 18:58:02) > From: Ville Syrjälä > > Extend the rotated vma mock selftest to cover remapped vmas as > well. > > TODO: reindent the loops I guess? Left like this for now to > ease review Probably leave it as is for the moment. Looks like we need to split the loops up into their functions for us to be able to recover enough columns. Not a task worth holding up this series for. > v2: Include the vma type in the error message (Chris) > v3: Deal with trimmed sg > v4: Drop leftover debugs > > Cc: Chris Wilson > Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 3/8] drm/i915/selftests: Add live vma selftest
Quoting Ville Syrjala (2019-01-24 19:11:57) > From: Ville Syrjälä > > Add a live selftest to excercise rotated/remapped vmas. We simply > write through the rotated/remapped vma, and confirm that the data > appears in the right page when read through the normal vma. > > Not sure what the fallout of making all rotated/remapped vmas > mappable/fenceable would be, hence I just hacked it in the test. > > v2: Grab rpm reference (Chris) > GEM_BUG_ON(view.type not as expected) (Chris) > Allow CAN_FENCE for rotated/remapped vmas (Chris) > Update intel_plane_uses_fence() to ask for a fence > only for normal vmas on gen4+ > v3: Deal with intel_wakeref_t > v4: Rebase > > Cc: Chris Wilson > Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] treewide: Lift switch variables out of switches
On Wednesday, January 23, 2019 6:04 AM, Kees Cook wrote
>
> Variables declared in a switch statement before any case statements
> cannot be initialized, so move all instances out of the switches.
> After this, future always-initialized stack variables will work
> and not throw warnings like this:
>
> fs/fcntl.c: In function ‘send_sigio_to_task’:
> fs/fcntl.c:738:13: warning: statement will never be executed
> [-Wswitch-unreachable]
>siginfo_t si;
> ^~
>
> Signed-off-by: Kees Cook
Reviewed by: Edwin Zimmerman
> ---
> arch/x86/xen/enlighten_pv.c | 7 ---
> drivers/char/pcmcia/cm4000_cs.c | 2 +-
> drivers/char/ppdev.c | 20 ---
> drivers/gpu/drm/drm_edid.c| 4 ++--
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> drivers/net/ethernet/intel/e1000/e1000_main.c | 3 ++-
> drivers/tty/n_tty.c | 3 +--
> drivers/usb/gadget/udc/net2280.c | 5 ++---
> fs/fcntl.c| 3 ++-
> mm/shmem.c| 5 +++--
> net/core/skbuff.c | 4 ++--
> net/ipv6/ip6_gre.c| 4 ++--
> net/ipv6/ip6_tunnel.c | 4 ++--
> net/openvswitch/flow_netlink.c| 7 +++
> security/tomoyo/common.c | 3 ++-
> security/tomoyo/condition.c | 7 ---
> security/tomoyo/util.c| 4 ++--
> 18 files changed, 45 insertions(+), 46 deletions(-)
>
> diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
> index c54a493e139a..a79d4b548a08 100644
> --- a/arch/x86/xen/enlighten_pv.c
> +++ b/arch/x86/xen/enlighten_pv.c
> @@ -907,14 +907,15 @@ static u64 xen_read_msr_safe(unsigned int msr, int *err)
> static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
> {
> int ret;
> +#ifdef CONFIG_X86_64
> + unsigned which;
> + u64 base;
> +#endif
>
> ret = 0;
>
> switch (msr) {
> #ifdef CONFIG_X86_64
> - unsigned which;
> - u64 base;
> -
> case MSR_FS_BASE: which = SEGBASE_FS; goto set;
> case MSR_KERNEL_GS_BASE:which = SEGBASE_GS_USER; goto set;
> case MSR_GS_BASE: which = SEGBASE_GS_KERNEL; goto set;
> diff --git a/drivers/char/pcmcia/cm4000_cs.c b/drivers/char/pcmcia/cm4000_cs.c
> index 7a4eb86aedac..7211dc0e6f4f 100644
> --- a/drivers/char/pcmcia/cm4000_cs.c
> +++ b/drivers/char/pcmcia/cm4000_cs.c
> @@ -663,6 +663,7 @@ static void monitor_card(struct timer_list *t)
> {
> struct cm4000_dev *dev = from_timer(dev, t, timer);
> unsigned int iobase = dev->p_dev->resource[0]->start;
> + unsigned char flags0;
> unsigned short s;
> struct ptsreq ptsreq;
> int i, atrc;
> @@ -731,7 +732,6 @@ static void monitor_card(struct timer_list *t)
> }
>
> switch (dev->mstate) {
> - unsigned char flags0;
> case M_CARDOFF:
> DEBUGP(4, dev, "M_CARDOFF\n");
> flags0 = inb(REG_FLAGS0(iobase));
> diff --git a/drivers/char/ppdev.c b/drivers/char/ppdev.c
> index 1ae77b41050a..d77c97e4f996 100644
> --- a/drivers/char/ppdev.c
> +++ b/drivers/char/ppdev.c
> @@ -359,14 +359,19 @@ static int pp_do_ioctl(struct file *file, unsigned int
> cmd, unsigned long arg)
> struct pp_struct *pp = file->private_data;
> struct parport *port;
> void __user *argp = (void __user *)arg;
> + struct ieee1284_info *info;
> + unsigned char reg;
> + unsigned char mask;
> + int mode;
> + s32 time32[2];
> + s64 time64[2];
> + struct timespec64 ts;
> + int ret;
>
> /* First handle the cases that don't take arguments. */
> switch (cmd) {
> case PPCLAIM:
> {
> - struct ieee1284_info *info;
> - int ret;
> -
> if (pp->flags & PP_CLAIMED) {
> dev_dbg(>pdev->dev, "you've already got it!\n");
> return -EINVAL;
> @@ -517,15 +522,6 @@ static int pp_do_ioctl(struct file *file, unsigned int
> cmd, unsigned long arg)
>
> port = pp->pdev->port;
> switch (cmd) {
> - struct ieee1284_info *info;
> - unsigned char reg;
> - unsigned char mask;
> - int mode;
> - s32 time32[2];
> - s64 time64[2];
> - struct timespec64 ts;
> - int ret;
> -
> case PPRSTATUS:
> reg = parport_read_status(port);
> if (copy_to_user(argp, , sizeof(reg)))
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index b506e3622b08..8f93956c1628 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -3942,12 +3942,12 @@ static void
Re: [Intel-gfx] [PATCH] drm/i915: Enable fastboot by default on Skylake and newer
On Thu, Jan 24, 2019 at 02:01:14PM +0100, Maarten Lankhorst wrote:
> From: Hans de Goede
>
> We really want to have fastboot enabled by default to avoid an ugly
> modeset during boot.
>
> Rather then enabling it everywhere, lets start with enabling it on
> Skylake and newer.
>
> Signed-off-by: Hans de Goede
> Signed-off-by: Maarten Lankhorst
I believe at this point you both addressed all of my concerns.
And CI is happy. Let's give a try ;)
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_params.c | 6 --
> drivers/gpu/drm/i915/i915_params.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 11 ++-
> 3 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 9f0539bdaa39..b5be0abbba35 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -97,8 +97,10 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
>
> i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
>
> -i915_param_named(fastboot, bool, 0600,
> - "Try to skip unnecessary mode sets at boot time (default: false)");
> +i915_param_named(fastboot, int, 0600,
> + "Try to skip unnecessary mode sets at boot time "
> + "(0=disabled, 1=enabled) "
> + "Default: -1 (use per-chip default)");
>
> i915_param_named_unsafe(prefault_disable, bool, 0600,
> "Disable page prefaulting for pread/pwrite/reloc (default:false). "
> diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_params.h
> index 6efcf330bdab..3f14e9881a0d 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -63,10 +63,10 @@ struct drm_printer;
> param(int, edp_vswing, 0) \
> param(int, reset, 2) \
> param(unsigned int, inject_load_failure, 0) \
> + param(int, fastboot, -1) \
> /* leave bools at the end to not create holes */ \
> param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \
> param(bool, enable_hangcheck, true) \
> - param(bool, fastboot, false) \
> param(bool, prefault_disable, false) \
> param(bool, load_detect_test, false) \
> param(bool, force_reset_modeset_test, false) \
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 36c1126cbc85..097e46819d3a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11690,6 +11690,15 @@ pipe_config_err(bool adjust, const char *name, const
> char *format, ...)
> va_end(args);
> }
>
> +static bool fastboot_enabled(struct drm_i915_private *dev_priv)
> +{
> + if (i915_modparams.fastboot != -1)
> + return i915_modparams.fastboot;
> +
> + /* Enable fastboot by default on Skylake and newer */
> + return INTEL_GEN(dev_priv) >= 9;
> +}
> +
> static bool
> intel_pipe_config_compare(struct drm_i915_private *dev_priv,
> struct intel_crtc_state *current_config,
> @@ -11701,7 +11710,7 @@ intel_pipe_config_compare(struct drm_i915_private
> *dev_priv,
> (current_config->base.mode.private_flags &
> I915_MODE_FLAG_INHERITED) &&
> !(pipe_config->base.mode.private_flags &
> I915_MODE_FLAG_INHERITED);
>
> - if (fixup_inherited && !i915_modparams.fastboot) {
> + if (fixup_inherited && !fastboot_enabled(dev_priv)) {
> DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
> ret = false;
> }
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Per context dynamic (sub)slice power-gating (rev18)
== Series Details == Series: Per context dynamic (sub)slice power-gating (rev18) URL : https://patchwork.freedesktop.org/series/48194/ State : failure == Summary == CALLscripts/checksyscalls.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/i915_timeline.o In file included from ./arch/x86/include/asm/bug.h:83:0, from ./include/linux/bug.h:5, from ./include/linux/mmdebug.h:5, from ./include/linux/gfp.h:5, from ./include/linux/slab.h:15, from ./include/linux/io-mapping.h:22, from drivers/gpu/drm/i915/i915_drv.h:36, from drivers/gpu/drm/i915/i915_timeline.c:7: drivers/gpu/drm/i915/i915_timeline.c: In function ‘i915_timeline_set_barrier’: drivers/gpu/drm/i915/i915_timeline.c:102:25: error: ‘struct i915_timeline’ has no member named ‘i915’ lockdep_assert_held(>i915->drm.struct_mutex); ^ ./include/asm-generic/bug.h:131:25: note: in definition of macro ‘WARN’ int __ret_warn_on = !!(condition);\ ^ ./include/linux/lockdep.h:366:3: note: in expansion of macro ‘WARN_ON’ WARN_ON(debug_locks && !lockdep_is_held(l)); \ ^~~ ./include/linux/lockdep.h:366:27: note: in expansion of macro ‘lockdep_is_held’ WARN_ON(debug_locks && !lockdep_is_held(l)); \ ^~~ drivers/gpu/drm/i915/i915_timeline.c:102:2: note: in expansion of macro ‘lockdep_assert_held’ lockdep_assert_held(>i915->drm.struct_mutex); ^~~ drivers/gpu/drm/i915/i915_timeline.c:105:45: error: ‘struct i915_timeline’ has no member named ‘i915’ old = i915_gem_active_raw(>barrier, >i915->drm.struct_mutex); ^~ scripts/Makefile.build:276: recipe for target 'drivers/gpu/drm/i915/i915_timeline.o' failed make[4]: *** [drivers/gpu/drm/i915/i915_timeline.o] Error 1 scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:492: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1043: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915: Add timeline barrier support
From: Tvrtko Ursulin
Timeline barrier allows serialization between different timelines.
After calling i915_timeline_set_barrier with a request, all following
submissions on this timeline will be set up as depending on this request,
or barrier. Once the barrier has been completed it automatically gets
cleared and things continue as normal.
This facility will be used by the upcoming context SSEU code.
v2:
* Assert barrier has been retired on timeline_fini. (Chris Wilson)
* Fix mock_timeline.
v3:
* Improved comment language. (Chris Wilson)
v4:
* Maintain ordering with previous barriers set on the timeline.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 13 +++
drivers/gpu/drm/i915/i915_timeline.c | 23 +++
drivers/gpu/drm/i915/i915_timeline.h | 22 ++
.../gpu/drm/i915/selftests/mock_timeline.c| 2 ++
4 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f941e40fd373..ea659c620461 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -517,6 +517,15 @@ i915_request_alloc_slow(struct intel_context *ce)
return kmem_cache_alloc(ce->gem_context->i915->requests, GFP_KERNEL);
}
+static int add_timeline_barrier(struct i915_request *rq)
+{
+ struct i915_request *barrier =
+ i915_gem_active_raw(>timeline->barrier,
+ >i915->drm.struct_mutex);
+
+ return barrier ? i915_request_await_dma_fence(rq, >fence) : 0;
+}
+
/**
* i915_request_alloc - allocate a request structure
*
@@ -660,6 +669,10 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
*/
rq->head = rq->ring->emit;
+ ret = add_timeline_barrier(rq);
+ if (ret)
+ goto err_unwind;
+
ret = engine->request_alloc(rq);
if (ret)
goto err_unwind;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 4667cc08c416..46327500e8cd 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -37,6 +37,8 @@ void i915_timeline_init(struct drm_i915_private *i915,
INIT_LIST_HEAD(>requests);
i915_syncmap_init(>sync);
+
+ init_request_active(>barrier, NULL);
}
/**
@@ -69,6 +71,7 @@ void i915_timelines_park(struct drm_i915_private *i915)
void i915_timeline_fini(struct i915_timeline *timeline)
{
GEM_BUG_ON(!list_empty(>requests));
+ GEM_BUG_ON(i915_gem_active_isset(>barrier));
i915_syncmap_free(>sync);
@@ -90,6 +93,26 @@ i915_timeline_create(struct drm_i915_private *i915, const
char *name)
return timeline;
}
+int i915_timeline_set_barrier(struct i915_timeline *tl,
+ struct i915_request *rq)
+{
+ struct i915_request *old;
+ int err;
+
+ lockdep_assert_held(>i915->drm.struct_mutex);
+
+ /* Must maintain ordering wrt existing barriers */
+ old = i915_gem_active_raw(>barrier, >i915->drm.struct_mutex);
+ if (old) {
+ err = i915_request_await_dma_fence(rq, >fence);
+ if (err)
+ return err;
+ }
+
+ i915_gem_active_set(>barrier, rq);
+ return 0;
+}
+
void __i915_timeline_free(struct kref *kref)
{
struct i915_timeline *timeline =
diff --git a/drivers/gpu/drm/i915/i915_timeline.h
b/drivers/gpu/drm/i915/i915_timeline.h
index 38c1e15e927a..c8d7117bb205 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -64,6 +64,16 @@ struct i915_timeline {
*/
struct i915_syncmap *sync;
+ /**
+* Barrier provides the ability to serialize ordering between different
+* timelines.
+*
+* Users can call i915_timeline_set_barrier which will make all
+* subsequent submissions to this timeline be executed only after the
+* barrier has been completed.
+*/
+ struct i915_gem_active barrier;
+
struct list_head link;
const char *name;
@@ -136,4 +146,16 @@ static inline bool i915_timeline_sync_is_later(struct
i915_timeline *tl,
void i915_timelines_park(struct drm_i915_private *i915);
+/**
+ * i915_timeline_set_barrier - orders submission between different timelines
+ * @timeline: timeline to set the barrier on
+ * @rq: request after which new submissions can proceed
+ *
+ * Sets the passed in request as the serialization point for all subsequent
+ * submissions on @timeline. Subsequent requests will not be submitted to GPU
+ * until the barrier has been completed.
+ */
+int i915_timeline_set_barrier(struct i915_timeline *timeline,
+ struct i915_request *rq);
+
#endif
diff --git
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: GTT remapping for display (rev7)
== Series Details ==
Series: drm/i915: GTT remapping for display (rev7)
URL : https://patchwork.freedesktop.org/series/55415/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5475_full -> Patchwork_12033_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12033_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-glk: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +4
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@all-pipes-single-bo:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1
- shard-apl: PASS -> FAIL [fdo#103166] +2
Possible fixes
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-apl: FAIL [fdo#106641] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: FAIL [fdo#103232] -> PASS +4
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-glk: FAIL [fdo#108948] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS +2
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109381] -> PASS
- shard-glk: DMESG-FAIL [fdo#105763] / [fdo#106538] -> PASS
- shard-apl: DMESG-FAIL [fdo#108950] -> PASS
* igt@kms_setmode@basic:
- shard-hsw: FAIL [fdo#99912] -> PASS
* igt@pm_rpm@system-suspend:
- shard-glk: FAIL [fdo#103375] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109381]: https://bugs.freedesktop.org/show_bug.cgi?id=109381
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5475 -> Patchwork_12033
CI_DRM_5475: 9ced33eacb10c4ec1f03010d6efd9f21c6cf3ef7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4788: 3f77380fabd4083f9857daa6cd454d0937077901 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12033: e35f319439521868732c6a8a1502fcc2b86385fc @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12033/
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/icl: use tc_port in MG_PLL macros
Em qui, 2019-01-24 às 10:52 -0800, Lucas De Marchi escreveu:
> On Wed, Jan 23, 2019 at 05:15:26PM -0800, Paulo Zanoni wrote:
> > Em qui, 2019-01-17 às 12:21 -0800, Lucas De Marchi escreveu:
> > > Fix the TODO leftover in the code by changing the argument in MG_PLL
> > > macros. The MG_PLL ids used to access the register values can be
> > > converted from tc_port rather than port.
> > >
> >
> > An explanation on why the new model is better would be amazing. It may
> > be obvious to you, but it's not to other people.
>
> What about:
>
> All these registers can use the TC port to calculate the right offsets
> because they are only available for TC ports. The range (PORT_C onwards)
> may not be stable and change from platform to platform. So by using the
> TC id directly we avoid having to check for the platform in the "leaf
> functions" and thus passing dev_priv around.
Works for me. Thanks.
>
>
> >
> > > The helper functions were also renamed to use "tc" as prefix to make
> > > them more generic.
> > >
> > > Signed-off-by: Lucas De Marchi
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 52 +-
> > > drivers/gpu/drm/i915/intel_ddi.c | 7 ++-
> > > drivers/gpu/drm/i915/intel_display.c | 3 +-
> > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 79 +--
> > > drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
> > > 5 files changed, 72 insertions(+), 71 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 9a1340cfda6c..de209e0fdc01 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -9545,7 +9545,7 @@ enum skl_power_gate {
> > > #define _MG_PLL3_ENABLE 0x46038
> > > #define _MG_PLL4_ENABLE 0x4603C
> > > /* Bits are the same as DPLL0_ENABLE */
> > > -#define MG_PLL_ENABLE(port) _MMIO_PORT((port) - PORT_C,
> > > _MG_PLL1_ENABLE, \
> > > +#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
> > > _MG_PLL2_ENABLE)
> > >
> > > #define _MG_REFCLKIN_CTL_PORT1 0x16892C
> > > @@ -9554,9 +9554,9 @@ enum skl_power_gate {
> > > #define _MG_REFCLKIN_CTL_PORT4 0x16B92C
> > > #define MG_REFCLKIN_CTL_OD_2_MUX(x)((x) << 8)
> > > #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
> > > -#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
> > > - _MG_REFCLKIN_CTL_PORT1, \
> > > - _MG_REFCLKIN_CTL_PORT2)
> > > +#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
> > > + _MG_REFCLKIN_CTL_PORT1, \
> > > + _MG_REFCLKIN_CTL_PORT2)
> > >
> > > #define _MG_CLKTOP2_CORECLKCTL1_PORT10x1688D8
> > > #define _MG_CLKTOP2_CORECLKCTL1_PORT20x1698D8
> > > @@ -9566,9 +9566,9 @@ enum skl_power_gate {
> > > #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
> > > #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
> > > #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
> > > -#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
> > > - _MG_CLKTOP2_CORECLKCTL1_PORT1, \
> > > - _MG_CLKTOP2_CORECLKCTL1_PORT2)
> > > +#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
> > > +
> > > _MG_CLKTOP2_CORECLKCTL1_PORT1, \
> > > +
> > > _MG_CLKTOP2_CORECLKCTL1_PORT2)
> > >
> > > #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
> > > #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
> > > @@ -9586,9 +9586,9 @@ enum skl_power_gate {
> > > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
> > > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
> > > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
> > > -#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
> > > - _MG_CLKTOP2_HSCLKCTL_PORT1, \
> > > - _MG_CLKTOP2_HSCLKCTL_PORT2)
> > > +#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
> > > + _MG_CLKTOP2_HSCLKCTL_PORT1, \
> > > + _MG_CLKTOP2_HSCLKCTL_PORT2)
> > >
> > > #define _MG_PLL_DIV0_PORT1 0x168A00
> > > #define _MG_PLL_DIV0_PORT2 0x169A00
> > > @@ -9600,8 +9600,8 @@ enum skl_power_gate {
> > > #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
> > > #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
> > > #define
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: GTT remapping for display (rev7)
== Series Details ==
Series: drm/i915: GTT remapping for display (rev7)
URL : https://patchwork.freedesktop.org/series/55415/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5475 -> Patchwork_12033
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/55415/revisions/7/mbox/
Known issues
Here are the changes found in Patchwork_12033 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:PASS -> DMESG-FAIL [fdo#108735]
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: PASS -> DMESG-FAIL [fdo#103841]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-6700k2: PASS -> FAIL [fdo#103841] / [fdo#108767]
- fi-kbl-7567u: PASS -> FAIL [fdo#103841] / [fdo#108767]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@pm_rpm@basic-rte:
- fi-byt-j1900: PASS -> FAIL [fdo#108800]
Possible fixes
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (45 -> 41)
--
Missing(4): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
Build changes
-
* Linux: CI_DRM_5475 -> Patchwork_12033
CI_DRM_5475: 9ced33eacb10c4ec1f03010d6efd9f21c6cf3ef7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4788: 3f77380fabd4083f9857daa6cd454d0937077901 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12033: e35f319439521868732c6a8a1502fcc2b86385fc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e35f31943952 hack: align dumb buffer stride to 4k to allow for gtt remapping
a0fc50b1d3bf hack: drm/i915: Always remap gtt
9044b091f79e drm/i915: Bump gen7+ fb size limits to 16kx16k
77a6058e039f drm/i915: Bump gen4+ fb stride limit to 256KiB
a31fbb99b1ce drm/i915: Overcome display engine stride limits via GTT remapping
b4401cf43d11 drm/i915/selftests: Add live vma selftest
2264b41f8fa4 drm/i915/selftests: Add mock selftest for remapped vmas
02b1fe191700 drm/i915: Add a new "remapped" gtt_view
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12033/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: GTT remapping for display (rev7)
== Series Details == Series: drm/i915: GTT remapping for display (rev7) URL : https://patchwork.freedesktop.org/series/55415/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Add a new "remapped" gtt_view +drivers/gpu/drm/i915/i915_gem_gtt.c:3637:34: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:3637:34: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3546:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3550:16: warning: expression using sizeof(void) Commit: drm/i915/selftests: Add mock selftest for remapped vmas Okay! Commit: drm/i915/selftests: Add live vma selftest Okay! Commit: drm/i915: Overcome display engine stride limits via GTT remapping Okay! Commit: drm/i915: Bump gen4+ fb stride limit to 256KiB Okay! Commit: drm/i915: Bump gen7+ fb size limits to 16kx16k Okay! Commit: hack: drm/i915: Always remap gtt Okay! Commit: hack: align dumb buffer stride to 4k to allow for gtt remapping Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev7)
== Series Details ==
Series: drm/i915: GTT remapping for display (rev7)
URL : https://patchwork.freedesktop.org/series/55415/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
02b1fe191700 drm/i915: Add a new "remapped" gtt_view
-:96: CHECK:LINE_SPACING: Please don't use multiple blank lines
#96: FILE: drivers/gpu/drm/i915/i915_gem.c:5687:
+
+
-:244: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#244: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:195:
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned
int));
^
total: 0 errors, 0 warnings, 2 checks, 286 lines checked
2264b41f8fa4 drm/i915/selftests: Add mock selftest for remapped vmas
-:75: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#75: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:436:
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
^
-:91: CHECK:LINE_SPACING: Please don't use multiple blank lines
#91: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:452:
+
+
-:127: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (8, 8)
#127: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:506:
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
-:171: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code
refactoring
#171: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:576:
+ if (view.type ==
I915_GGTT_VIEW_ROTATED)
-:172: WARNING:LONG_LINE: line over 100 characters
#172: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:577:
+ sg =
assert_rotated(obj, , n, sg);
-:173: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code
refactoring
#173: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:578:
+ else
-:174: WARNING:LONG_LINE: line over 100 characters
#174: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:579:
+ sg =
assert_remapped(obj, , n, sg);
total: 0 errors, 5 warnings, 2 checks, 165 lines checked
b4401cf43d11 drm/i915/selftests: Add live vma selftest
a31fbb99b1ce drm/i915: Overcome display engine stride limits via GTT remapping
77a6058e039f drm/i915: Bump gen4+ fb stride limit to 256KiB
-:40: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#40: FILE: drivers/gpu/drm/i915/intel_display.c:2480:
+ return 256*1024;
^
total: 0 errors, 0 warnings, 1 checks, 15 lines checked
9044b091f79e drm/i915: Bump gen7+ fb size limits to 16kx16k
a0fc50b1d3bf hack: drm/i915: Always remap gtt
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:21: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 1 errors, 1 warnings, 0 checks, 9 lines checked
e35f31943952 hack: align dumb buffer stride to 4k to allow for gtt remapping
-:10: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate
one
-:26: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 1 errors, 1 warnings, 0 checks, 13 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 7/8] hack: drm/i915: Always remap gtt
From: Ville Syrjälä v2: Rebase due to can_remap() --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c6f59bfb4744..c720891b31c9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2562,6 +2562,9 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) if (!intel_plane_can_remap(plane_state)) return false; + /* HACK: always remap */ + return true; + /* FIXME other color planes? */ stride = intel_fb_pitch(fb, 0, rotation); max_stride = plane->max_stride(plane, fb->format->format, -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display (rev6)
== Series Details == Series: drm/i915: GTT remapping for display (rev6) URL : https://patchwork.freedesktop.org/series/55415/ State : failure == Summary == Applying: drm/i915: Add a new "remapped" gtt_view Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_debugfs.c M drivers/gpu/drm/i915/i915_drv.h M drivers/gpu/drm/i915/i915_gem.c M drivers/gpu/drm/i915/intel_display.c M drivers/gpu/drm/i915/intel_drv.h M drivers/gpu/drm/i915/selftests/i915_vma.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/selftests/i915_vma.c Auto-merging drivers/gpu/drm/i915/intel_drv.h Auto-merging drivers/gpu/drm/i915/intel_display.c Auto-merging drivers/gpu/drm/i915/i915_gem.c Auto-merging drivers/gpu/drm/i915/i915_drv.h Auto-merging drivers/gpu/drm/i915/i915_debugfs.c Applying: drm/i915/selftests: Add mock selftest for remapped vmas Applying: drm/i915/selftests: Add live vma selftest Applying: drm/i915: Overcome display engine stride limits via GTT remapping Applying: drm/i915: Bump gen4+ fb stride limit to 256KiB Applying: drm/i915: Bump gen7+ fb size limits to 16kx16k Applying: hack: drm/i915: Always remap gtt Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_display.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_display.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_display.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0007 hack: drm/i915: Always remap gtt When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 3/8] drm/i915/selftests: Add live vma selftest
From: Ville Syrjälä
Add a live selftest to excercise rotated/remapped vmas. We simply
write through the rotated/remapped vma, and confirm that the data
appears in the right page when read through the normal vma.
Not sure what the fallout of making all rotated/remapped vmas
mappable/fenceable would be, hence I just hacked it in the test.
v2: Grab rpm reference (Chris)
GEM_BUG_ON(view.type not as expected) (Chris)
Allow CAN_FENCE for rotated/remapped vmas (Chris)
Update intel_plane_uses_fence() to ask for a fence
only for normal vmas on gen4+
v3: Deal with intel_wakeref_t
v4: Rebase
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_vma.c | 8 -
drivers/gpu/drm/i915/intel_display.c | 4 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 142 ++
4 files changed, 146 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 9a039c36dc0c..865290751633 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -463,14 +463,6 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- /*
-* Explicitly disable for rotated VMA since the display does not
-* need the fence and the VMA is not accessible to other users.
-*/
- if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
- vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
- return;
-
fenceable = (vma->node.size >= vma->fence_size &&
IS_ALIGNED(vma->node.start, vma->fence_alignment));
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 84efbf892c65..17c7edee9584 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2027,7 +2027,9 @@ static bool intel_plane_uses_fence(const struct
intel_plane_state *plane_state)
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
+ return INTEL_GEN(dev_priv) < 4 ||
+ (plane->has_fbc &&
+plane_state->view.type == I915_GGTT_VIEW_NORMAL);
}
struct i915_vma *
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a15713cae3b3..095e25e92a36 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -15,6 +15,7 @@ selftest(workarounds, intel_workarounds_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(dmabuf, i915_gem_dmabuf_live_selftests)
+selftest(vma, i915_vma_live_selftests)
selftest(coherency, i915_gem_coherency_live_selftests)
selftest(gtt, i915_gem_gtt_live_selftests)
selftest(gem, i915_gem_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 653a9b6c514e..d8fa169e2775 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -828,3 +828,145 @@ int i915_vma_mock_selftests(void)
return err;
}
+
+static int igt_vma_remapped_gtt(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ const struct intel_remapped_plane_info planes[] = {
+ { .width = 1, .height = 1, .stride = 1 },
+ { .width = 2, .height = 2, .stride = 2 },
+ { .width = 4, .height = 4, .stride = 4 },
+ { .width = 8, .height = 8, .stride = 8 },
+
+ { .width = 3, .height = 5, .stride = 3 },
+ { .width = 3, .height = 5, .stride = 4 },
+ { .width = 3, .height = 5, .stride = 5 },
+
+ { .width = 5, .height = 3, .stride = 5 },
+ { .width = 5, .height = 3, .stride = 7 },
+ { .width = 5, .height = 3, .stride = 9 },
+
+ { .width = 4, .height = 6, .stride = 6 },
+ { .width = 6, .height = 4, .stride = 6 },
+ { }
+ }, *p;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
+ struct drm_i915_gem_object *obj;
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ mutex_lock(>drm.struct_mutex);
+
+ wakeref = intel_runtime_pm_get(i915);
+
+ for (t = types; *t; t++) {
+ for (p = planes; p->width; p++) {
+ struct i915_ggtt_view view = {
+
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display (rev5)
== Series Details == Series: drm/i915: GTT remapping for display (rev5) URL : https://patchwork.freedesktop.org/series/55415/ State : failure == Summary == Applying: drm/i915: Add a new "remapped" gtt_view Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_debugfs.c M drivers/gpu/drm/i915/i915_drv.h M drivers/gpu/drm/i915/i915_gem.c M drivers/gpu/drm/i915/intel_display.c M drivers/gpu/drm/i915/intel_drv.h M drivers/gpu/drm/i915/selftests/i915_vma.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/selftests/i915_vma.c Auto-merging drivers/gpu/drm/i915/intel_drv.h Auto-merging drivers/gpu/drm/i915/intel_display.c Auto-merging drivers/gpu/drm/i915/i915_gem.c Auto-merging drivers/gpu/drm/i915/i915_drv.h Auto-merging drivers/gpu/drm/i915/i915_debugfs.c Applying: drm/i915/selftests: Add mock selftest for remapped vmas Applying: drm/i915/selftests: Add live vma selftest Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_display.c M drivers/gpu/drm/i915/selftests/i915_vma.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/selftests/i915_vma.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/selftests/i915_vma.c Auto-merging drivers/gpu/drm/i915/intel_display.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0003 drm/i915/selftests: Add live vma selftest When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB
From: Ville Syrjälä
With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just pick the limit to match the render
engine max stride (256KiB).
No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no
remapping on gen2/3 due extra complications from fence alignment
and gen2 2KiB GTT tile size. Also no real benefit since the
display engine limits already match the other limits.
v2: Rebase due to is_ccs_modifier()
v3: Tweak the comment and commit msg
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3713b6f1796e..e0cf43336b62 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2470,6 +2470,15 @@ static
u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier)
{
+ /*
+* Arbitrary limit for gen4+ chosen to match the
+* render engine max stride.
+*
+* The new CCS hash mode makes remapping impossible
+*/
+ if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier))
+ return 256*1024;
+
return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
}
--
2.19.2
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 4/8] drm/i915: Overcome display engine stride limits via GTT remapping
From: Ville Syrjälä
The display engine stride limits are getting in our way. On SKL+
we are limited to 8k pixels, which is easily exceeded with three
4k displays. To overcome this limitation we can remap the pages
in the GTT to provide the display engine with a view of memory
with a smaller stride.
The code is mostly already there as We already play tricks with
the plane surface address and x/y offsets.
A few caveats apply:
* linear buffers need the fb stride to be page aligned, as
otherwise the remapped lines wouldn't start at the same
spot
* compressed buffers can't be remapped due to the new
ccs hash mode causing the virtual address of the pages
to affect the interpretation of the compressed data. IIRC
the old hash was limited to the low 12 bits so if we were
using that mode we could remap. As it stands we just refuse
to remapp with compressed fbs.
* no remapping gen2/3 as we'd need a fence for the remapped
vma, which we currently don't have. Need to deal with the
fence POT requirements, and do something about the gen2
gtt page size vs tile size difference
v2: Rebase due to is_ccs_modifier()
Fix up the skl+ stride_mult mess
memset() the gtt_view because otherwise we could leave
junk in plane[1] when going from 2 plane to 1 plane format
v3: intel_check_plane_stride() was split out
v4: Drop the aligned viewport stuff, it was meant for ccs which
can't be remapped anyway
v5: Introduce intel_plane_can_remap()
Reorder the code so that plane_state->view gets filled
even for invisible planes, otherwise we'd keep using
stale values and could explode during remapping. The new
logic never remaps invisible planes since we don't have
a viewport, and instead pins the full fb instead
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 393 +--
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_sprite.c | 34 ++-
3 files changed, 334 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 17c7edee9584..3713b6f1796e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1865,7 +1865,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
- return cpp;
+ return intel_tile_size(dev_priv);
case I915_FORMAT_MOD_X_TILED:
if (IS_GEN(dev_priv, 2))
return 128;
@@ -1908,11 +1908,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 1;
- else
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
}
/* Return the tile dimensions in pixel units */
@@ -2170,16 +2167,8 @@ void intel_add_fb_offsets(int *x, int *y,
int color_plane)
{
- const struct intel_framebuffer *intel_fb =
to_intel_framebuffer(state->base.fb);
- unsigned int rotation = state->base.rotation;
-
- if (drm_rotation_90_or_270(rotation)) {
- *x += intel_fb->rotated[color_plane].x;
- *y += intel_fb->rotated[color_plane].y;
- } else {
- *x += intel_fb->normal[color_plane].x;
- *y += intel_fb->normal[color_plane].y;
- }
+ *x += state->color_plane[color_plane].x;
+ *y += state->color_plane[color_plane].y;
}
static u32 intel_adjust_tile_offset(int *x, int *y,
@@ -2459,6 +2448,119 @@ bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
+static
+u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ struct intel_crtc *crtc;
+ struct intel_plane *plane;
+
+ /*
+* We assume the primary plane for pipe A has
+* the highest stride limits of them all.
+*/
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ plane = to_intel_plane(crtc->base.primary);
+
+ return plane->max_stride(plane, pixel_format, modifier,
+DRM_MODE_ROTATE_0);
+}
+
+static
+u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+}
+
+static u32
+intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(fb->dev);
+
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+
[Intel-gfx] [PATCH v4 2/8] drm/i915/selftests: Add mock selftest for remapped vmas
From: Ville Syrjälä
Extend the rotated vma mock selftest to cover remapped vmas as
well.
TODO: reindent the loops I guess? Left like this for now to
ease review
v2: Include the vma type in the error message (Chris)
v3: Deal with trimmed sg
v4: Drop leftover debugs
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/selftests/i915_vma.c | 98 +--
1 file changed, 90 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 06bbed7920b9..653a9b6c514e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -59,7 +59,7 @@ static bool assert_vma(struct i915_vma *vma,
static struct i915_vma *
checked_vma_instance(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
-struct i915_ggtt_view *view)
+const struct i915_ggtt_view *view)
{
struct i915_vma *vma;
bool ok = true;
@@ -397,13 +397,74 @@ assert_rotated(struct drm_i915_gem_object *obj,
return sg;
}
+static unsigned long remapped_index(const struct intel_remapped_info *r,
+ unsigned int n,
+ unsigned int x,
+ unsigned int y)
+{
+ return (r->plane[n].stride * y +
+ r->plane[n].offset + x);
+}
+
+static struct scatterlist *
+assert_remapped(struct drm_i915_gem_object *obj,
+ const struct intel_remapped_info *r, unsigned int n,
+ struct scatterlist *sg)
+{
+ unsigned int x, y;
+ unsigned int left = 0;
+ unsigned int offset;
+
+ for (y = 0; y < r->plane[n].height; y++) {
+ for (x = 0; x < r->plane[n].width; x++) {
+ unsigned long src_idx;
+ dma_addr_t src;
+
+ if (!sg) {
+ pr_err("Invalid sg table: too short at plane
%d, (%d, %d)!\n",
+ n, x, y);
+ return ERR_PTR(-EINVAL);
+ }
+ if (!left) {
+ offset = 0;
+ left = sg_dma_len(sg);
+ }
+
+ src_idx = remapped_index(r, n, x, y);
+ src = i915_gem_object_get_dma_address(obj, src_idx);
+
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
+ pr_err("Invalid sg.length, found %d, expected
%lu for remapped page (%d, %d) [src index %lu]\n",
+ sg_dma_len(sg), PAGE_SIZE,
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (sg_dma_address(sg) + offset != src) {
+ pr_err("Invalid address for remapped page (%d,
%d) [src index %lu]\n",
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ left -= PAGE_SIZE;
+ offset += PAGE_SIZE;
+
+
+ if (!left)
+ sg = sg_next(sg);
+ }
+ }
+
+ return sg;
+}
+
static unsigned int rotated_size(const struct intel_remapped_plane_info *a,
const struct intel_remapped_plane_info *b)
{
return a->width * a->height + b->width * b->height;
}
-static int igt_vma_rotate(void *arg)
+static int igt_vma_rotate_remap(void *arg)
{
struct i915_ggtt *ggtt = arg;
struct i915_address_space *vm = >vm;
@@ -426,6 +487,11 @@ static int igt_vma_rotate(void *arg)
{ .width = 6, .height = 4, .stride = 6 },
{ }
}, *a, *b;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
const unsigned int max_pages = 64;
int err = -ENOMEM;
@@ -437,6 +503,7 @@ static int igt_vma_rotate(void *arg)
if (IS_ERR(obj))
goto out;
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
for (b = planes + ARRAY_SIZE(planes); b-- != planes; ) {
struct i915_ggtt_view view;
@@ -447,7 +514,7 @@ static int igt_vma_rotate(void *arg)
GEM_BUG_ON(max_offset > max_pages);
max_offset = max_pages - max_offset;
- view.type = I915_GGTT_VIEW_ROTATED;
+ view.type = *t;
view.rotated.plane[0] = *a;
view.rotated.plane[1] = *b;
@@ -468,14 +535,23 @@ static int igt_vma_rotate(void *arg)
Re: [Intel-gfx] [PATCH 1/5] drm/i915/icl: use tc_port in MG_PLL macros
On Wed, Jan 23, 2019 at 05:15:26PM -0800, Paulo Zanoni wrote:
Em qui, 2019-01-17 às 12:21 -0800, Lucas De Marchi escreveu:
Fix the TODO leftover in the code by changing the argument in MG_PLL
macros. The MG_PLL ids used to access the register values can be
converted from tc_port rather than port.
An explanation on why the new model is better would be amazing. It may
be obvious to you, but it's not to other people.
What about:
All these registers can use the TC port to calculate the right offsets
because they are only available for TC ports. The range (PORT_C onwards)
may not be stable and change from platform to platform. So by using the
TC id directly we avoid having to check for the platform in the "leaf
functions" and thus passing dev_priv around.
The helper functions were also renamed to use "tc" as prefix to make
them more generic.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 52 +-
drivers/gpu/drm/i915/intel_ddi.c | 7 ++-
drivers/gpu/drm/i915/intel_display.c | 3 +-
drivers/gpu/drm/i915/intel_dpll_mgr.c | 79 +--
drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
5 files changed, 72 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a1340cfda6c..de209e0fdc01 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9545,7 +9545,7 @@ enum skl_power_gate {
#define _MG_PLL3_ENABLE0x46038
#define _MG_PLL4_ENABLE0x4603C
/* Bits are the same as DPLL0_ENABLE */
-#define MG_PLL_ENABLE(port)_MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
+#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
_MG_PLL2_ENABLE)
#define _MG_REFCLKIN_CTL_PORT1 0x16892C
@@ -9554,9 +9554,9 @@ enum skl_power_gate {
#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
#define MG_REFCLKIN_CTL_OD_2_MUX_MASK(0x7 << 8)
-#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
-_MG_REFCLKIN_CTL_PORT1, \
-_MG_REFCLKIN_CTL_PORT2)
+#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
+ _MG_REFCLKIN_CTL_PORT1, \
+ _MG_REFCLKIN_CTL_PORT2)
#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
@@ -9566,9 +9566,9 @@ enum skl_power_gate {
#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
-#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
- _MG_CLKTOP2_CORECLKCTL1_PORT1, \
- _MG_CLKTOP2_CORECLKCTL1_PORT2)
+#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
+
_MG_CLKTOP2_CORECLKCTL1_PORT1, \
+
_MG_CLKTOP2_CORECLKCTL1_PORT2)
#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
@@ -9586,9 +9586,9 @@ enum skl_power_gate {
#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT8
#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
-#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
-_MG_CLKTOP2_HSCLKCTL_PORT1, \
-_MG_CLKTOP2_HSCLKCTL_PORT2)
+#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
+ _MG_CLKTOP2_HSCLKCTL_PORT1, \
+ _MG_CLKTOP2_HSCLKCTL_PORT2)
#define _MG_PLL_DIV0_PORT1 0x168A00
#define _MG_PLL_DIV0_PORT2 0x169A00
@@ -9600,8 +9600,8 @@ enum skl_power_gate {
#define MG_PLL_DIV0_FBDIV_FRAC(x)((x) << 8)
#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
-#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \
-_MG_PLL_DIV0_PORT2)
+#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
+ _MG_PLL_DIV0_PORT2)
#define _MG_PLL_DIV1_PORT1 0x168A04
#define _MG_PLL_DIV1_PORT2 0x169A04
@@ -9615,8 +9615,8 @@ enum skl_power_gate {
#define
Re: [Intel-gfx] [PATCH] dma-buf: Enhance dma-fence tracing
Chris Wilson writes: > Quoting Koenig, Christian (2019-01-22 08:49:30) >> Am 22.01.19 um 00:20 schrieb Chris Wilson: >> > Rather than every backend and GPU driver reinventing the same wheel for >> > user level debugging of HW execution, the common dma-fence framework >> > should include the tracing infrastructure required for most client API >> > level flow visualisation. >> > >> > With these common dma-fence level tracepoints, the userspace tools can >> > establish a detailed view of the client <-> HW flow across different >> > kernels. There is a strong ask to have this available, so that the >> > userspace developer can effectively assess if they're doing a good job >> > about feeding the beast of a GPU hardware. >> > >> > In the case of needing to look into more fine-grained details of how >> > kernel internals work towards the goal of feeding the beast, the tools >> > may optionally amend the dma-fence tracing information with the driver >> > implementation specific. But for such cases, the tools should have a >> > graceful degradation in case the expected extra tracepoints have >> > changed or their format differs from the expected, as the kernel >> > implementation internals are not expected to stay the same. >> > >> > It is important to distinguish between tracing for the purpose of client >> > flow visualisation and tracing for the purpose of low-level kernel >> > debugging. The latter is highly implementation specific, tied to >> > a particular HW and driver, whereas the former addresses a common goal >> > of user level tracing and likely a common set of userspace tools. >> > Having made the distinction that these tracepoints will be consumed for >> > client API tooling, we raise the spectre of tracepoint ABI stability. It >> > is hoped that by defining a common set of dma-fence tracepoints, we avoid >> > the pitfall of exposing low level details and so restrict ourselves only >> > to the high level flow that is applicable to all drivers and hardware. >> > Thus the reserved guarantee that this set of tracepoints will be stable >> > (with the emphasis on depicting client <-> HW flow as opposed to >> > driver <-> HW). >> > >> > In terms of specific changes to the dma-fence tracing, we remove the >> > emission of the strings for every tracepoint (reserving them for >> > dma_fence_init for cases where they have unique dma_fence_ops, and >> > preferring to have descriptors for the whole fence context). strings do >> > not pack as well into the ftrace ringbuffer and we would prefer to >> > reduce the amount of indirect callbacks required for frequent tracepoint >> > emission. >> > >> > Signed-off-by: Chris Wilson >> > Cc: Joonas Lahtinen >> > Cc: Tvrtko Ursulin >> > Cc: Alex Deucher >> > Cc: "Christian König" >> > Cc: Eric Anholt >> > Cc: Pierre-Loup Griffais >> > Cc: Michael Sartain >> > Cc: Steven Rostedt >> >> In general yes please! If possible please separate out the changes to >> the common dma_fence infrastructure from the i915 changes. > > Sure, I was just stressing the impact: remove some randomly placed > internal debugging tracepoints, try to define useful ones instead :) > > On the list of things to do was to convert at least 2 other drivers > (I was thinking nouveau/msm for simplicity, vc4 for a simpler > introduction to drm_sched than amdgpu) over to be sure we have the right > tracepoints. v3d is using gpu-scheduler, and I'd love to see it using some shared tracepoints -- I put in some of what we'd need for visualization, but I haven't actually built visualization yet so I'm not sure it's good enough. vc4 isn't using gpu-scheduler yet. I'm interested in it -- there's the user qpu pipeline that we should expose, but supporting another pipeline without the shared scheduler is no fun. signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 29/34] drm/i915: Drop fake breadcrumb irq
Quoting Tvrtko Ursulin (2019-01-24 17:55:20)
>
> On 21/01/2019 22:21, Chris Wilson wrote:
> > Missed breadcrumb detection is defunct due to the tight coupling with
>
> How it is defunct.. oh because there is no irq_count any more... could
> you describe the transition from irq_count to irq_fired and then to
> nothing briefly?
We don't have an independent intel_wait to distinguish irq completions
from dma_fence_signals. Everytime we call dma_fence_signal() we think we
saw an interrupt, and we complete fences very often before we see
interrupts... And then our test completely fails to setup the machine to
detect the missed breadcrumb as the requests get completed by anything
but the missed breadcrumb timer.
> > dma_fence signaling and the myriad ways we may signal fences from
> > everywhere but from an interrupt, i.e. we frequently signal a fence
> > before we even see its interrupt. This means that even if we miss an
> > interrupt for a fence, it still is signaled before our breadcrumb
> > hangcheck fires, so simplify the breadcrumb hangchecking by moving it
> > into the GPU hangcheck and forgo fake interrupts.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 93 ---
> > drivers/gpu/drm/i915/i915_gpu_error.c | 2 -
> > drivers/gpu/drm/i915/i915_gpu_error.h | 5 -
> > drivers/gpu/drm/i915/intel_breadcrumbs.c | 147 +-
> > drivers/gpu/drm/i915/intel_hangcheck.c| 2 +
> > drivers/gpu/drm/i915/intel_ringbuffer.h | 5 -
> > .../gpu/drm/i915/selftests/igt_live_test.c| 7 -
> > 7 files changed, 5 insertions(+), 256 deletions(-)
>
> With this balance of insertions and deletions I cannot decide if this is
> easy or hard to review.
>
> IGT uses intel_detect_and_clear_missed_interrupts a lot. What is the
> plan there?
They are defunct. They no longer detect anything useful from the
previous patch, this just makes it official. igt has been prepped for
the loss of the debugfs.
Without this patch we get false positives from i915_missed_interrupt
instead.
I've tried and failed to replace the detection in an acceptable manner,
without a separate irq completion tracker it seems hopeless.
> > diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c
> > b/drivers/gpu/drm/i915/intel_hangcheck.c
> > index 5662d6fed523..a219c796e56d 100644
> > --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> > +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> > @@ -275,6 +275,8 @@ static void i915_hangcheck_elapsed(struct work_struct
> > *work)
> > for_each_engine(engine, dev_priv, id) {
> > struct hangcheck hc;
> >
> > + intel_engine_signal_breadcrumbs(engine);
> > +
>
> Sounds fine. So only downside is detecting missed interrupts gets
> slower. But in practice they don't happen often?
In practice, no missed interrupts. *touch wood*
That was why fixing gen5-gen7 beforehand was so important.
Having a signal here and in retire_work, means that in the worst case
everything updates once a second. Enough for users to be able to
complain. But more than likely every frame update will flush the earlier
requests anyway, hence why we couldn't detect missed breadcrumbs in igt
in the first place.
-Chris
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Re: [Intel-gfx] [PATCH 09/26] drm/ast: Use drm_fb_helper_fill_info
Hi Daniel.
On Thu, Jan 24, 2019 at 05:58:14PM +0100, Daniel Vetter wrote:
> Should not result in any changes.
>
> Signed-off-by: Daniel Vetter
> Cc: Dave Airlie
> Cc: Junwei Zhang
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: Daniel Vetter
> Cc: Sean Paul
> Cc: YueHaibing
> Cc: Sam Bobroff
> ---
> drivers/gpu/drm/ast/ast_drv.h | 2 +-
> drivers/gpu/drm/ast/ast_fb.c | 7 +--
> 2 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
> index bfc65040dfcb..ffce4608e0c5 100644
> --- a/drivers/gpu/drm/ast/ast_drv.h
> +++ b/drivers/gpu/drm/ast/ast_drv.h
> @@ -259,7 +259,7 @@ struct ast_framebuffer {
> };
>
> struct ast_fbdev {
> - struct drm_fb_helper helper;
> + struct drm_fb_helper helper; /* must be first */
Again in the category "I do not know the code",
but I failed to see whay "struct drm_fb_helper" have to be first.
I saw no ugly cast or similar when browsign the code, but I
must have missed something?
Sam
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Re: [Intel-gfx] [PATCH 29/34] drm/i915: Drop fake breadcrumb irq
On 21/01/2019 22:21, Chris Wilson wrote:
Missed breadcrumb detection is defunct due to the tight coupling with
How it is defunct.. oh because there is no irq_count any more... could
you describe the transition from irq_count to irq_fired and then to
nothing briefly?
dma_fence signaling and the myriad ways we may signal fences from
everywhere but from an interrupt, i.e. we frequently signal a fence
before we even see its interrupt. This means that even if we miss an
interrupt for a fence, it still is signaled before our breadcrumb
hangcheck fires, so simplify the breadcrumb hangchecking by moving it
into the GPU hangcheck and forgo fake interrupts.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 93 ---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 -
drivers/gpu/drm/i915/i915_gpu_error.h | 5 -
drivers/gpu/drm/i915/intel_breadcrumbs.c | 147 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 2 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 -
.../gpu/drm/i915/selftests/igt_live_test.c| 7 -
7 files changed, 5 insertions(+), 256 deletions(-)
With this balance of insertions and deletions I cannot decide if this is
easy or hard to review.
IGT uses intel_detect_and_clear_missed_interrupts a lot. What is the
plan there?
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d7764e62e9b4..c2aaf010c3d1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1321,9 +1321,6 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
intel_engine_last_submit(engine),
jiffies_to_msecs(jiffies -
engine->hangcheck.action_timestamp));
- seq_printf(m, "\tfake irq active? %s\n",
- yesno(test_bit(engine->id,
-
_priv->gpu_error.missed_irq_rings)));
seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
(long long)engine->hangcheck.acthd,
@@ -3874,94 +3871,6 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
-static int
-fault_irq_set(struct drm_i915_private *i915,
- unsigned long *irq,
- unsigned long val)
-{
- int err;
-
- err = mutex_lock_interruptible(>drm.struct_mutex);
- if (err)
- return err;
-
- err = i915_gem_wait_for_idle(i915,
-I915_WAIT_LOCKED |
-I915_WAIT_INTERRUPTIBLE,
-MAX_SCHEDULE_TIMEOUT);
- if (err)
- goto err_unlock;
-
- *irq = val;
- mutex_unlock(>drm.struct_mutex);
-
- /* Flush idle worker to disarm irq */
- drain_delayed_work(>gt.idle_work);
-
- return 0;
-
-err_unlock:
- mutex_unlock(>drm.struct_mutex);
- return err;
-}
-
-static int
-i915_ring_missed_irq_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
-
- *val = dev_priv->gpu_error.missed_irq_rings;
- return 0;
-}
-
-static int
-i915_ring_missed_irq_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- return fault_irq_set(i915, >gpu_error.missed_irq_rings, val);
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
- i915_ring_missed_irq_get, i915_ring_missed_irq_set,
- "0x%08llx\n");
-
-static int
-i915_ring_test_irq_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
-
- *val = dev_priv->gpu_error.test_irq_rings;
-
- return 0;
-}
-
-static int
-i915_ring_test_irq_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- /* GuC keeps the user interrupt permanently enabled for submission */
- if (USES_GUC_SUBMISSION(i915))
- return -ENODEV;
-
- /*
-* From icl, we can no longer individually mask interrupt generation
-* from each engine.
-*/
- if (INTEL_GEN(i915) >= 11)
- return -ENODEV;
-
- val &= INTEL_INFO(i915)->ring_mask;
- DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
-
- return fault_irq_set(i915, >gpu_error.test_irq_rings, val);
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
- i915_ring_test_irq_get, i915_ring_test_irq_set,
- "0x%08llx\n");
-
#define DROP_UNBOUND BIT(0)
#define DROP_BOUNDBIT(1)
#define DROP_RETIRE BIT(2)
@@ -4724,8 +4633,6 @@ static const struct i915_debugfs_files {
} i915_debugfs_files[] = {
{"i915_wedged", _wedged_fops},
{"i915_cache_sharing", _cache_sharing_fops},
- {"i915_ring_missed_irq", _ring_missed_irq_fops},
Re: [Intel-gfx] [PATCH 06/26] drm/fb_helper: set info->par in fill_info()
Hi Daniel. On Thu, Jan 24, 2019 at 05:58:11PM +0100, Daniel Vetter wrote: > The fbdev emulation helpers pretty much assume that this is set. > Let's do it for everyone. I do not know this code at all. But I failed to follow the code from the patch description. It do not give _me_ a clue why the assignment is removed from drm_fb_helper_generic_probe(). But it may be obvious for people that actually know this. > > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/drm_fb_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c > index 20969c05a9e3..cbe7fda3f8af 100644 > --- a/drivers/gpu/drm/drm_fb_helper.c > +++ b/drivers/gpu/drm/drm_fb_helper.c > @@ -2126,6 +2126,7 @@ void drm_fb_helper_fill_info(struct fb_info *info, > drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); > drm_fb_helper_fill_var(info, fb_helper, fb->width, fb->height); > > + info->par = fb_helper; > snprintf(info->fix.id, sizeof(info->fix.id), "%sdrmfb", >fb_helper->dev->driver->name); > > @@ -3177,7 +3178,6 @@ int drm_fb_helper_generic_probe(struct drm_fb_helper > *fb_helper, > if (IS_ERR(fbi)) > return PTR_ERR(fbi); > > - fbi->par = fb_helper; > fbi->fbops = _fbdev_fb_ops; > fbi->screen_size = fb->height * fb->pitches[0]; > fbi->fix.smem_len = fbi->screen_size; Sam ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/26] drm/fb-helper: Add fill_info() functions
Den 24.01.2019 17.58, skrev Daniel Vetter:
> The fbdev split between fix and var information is kinda
> pointless for drm drivers since everything is fixed: The fbdev
> emulation doesn't support changing modes at all.
>
> Create a new simplified helper and use it in the generic fbdev
> helper code. Follow-up patches will beef it up more and roll
> it out to all drivers.
>
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_fb_helper.c | 27 +--
> include/drm/drm_fb_helper.h | 1 +
> 2 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index 5eaccd202f4f..34c4ed378796 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -2105,6 +2105,30 @@ void drm_fb_helper_fill_var(struct fb_info *info,
> struct drm_fb_helper *fb_helpe
> }
> EXPORT_SYMBOL(drm_fb_helper_fill_var);
>
> +/**
> + * drm_fb_helper_fill_info - initializes fbdev information
> + * @info: fbdev instance to set up
> + * @fb_helper: fb helper instance to use as template
> + *
> + *
> + * Sets up the variable and fixed fbdev metainformation from the given fb
> helper
> + * instance and the drm framebuffer allocated in _fb_helper.fb.
> + *
> + * Drivers should call this (or their equivalent setup code) from their
> + * _fb_helper_funcs.fb_probe callback after having allocated the fbdev
> + * backing storage framebuffer.
> + */
> +void drm_fb_helper_fill_info(struct fb_info *info,
No need to pass in fb_info it's available as fb_helper->fbdev. Set by
drm_fb_helper_alloc_fbi().
> + struct drm_fb_helper *fb_helper)
> +{
> + struct drm_framebuffer *fb = fb_helper->fb;
> +
> + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
> + drm_fb_helper_fill_var(info, fb_helper, fb->width, fb->height);
AFAIU fb->width/height can be different from sizes->fb_width/fb_height
when there's double/triple buffering. I belive you need to use the sizes
values here.
Noralf.
> +
> +}
> +EXPORT_SYMBOL(drm_fb_helper_fill_info);
> +
> static int drm_fb_helper_probe_connector_modes(struct drm_fb_helper
> *fb_helper,
> uint32_t maxX,
> uint32_t maxY)
> @@ -3163,8 +3187,7 @@ int drm_fb_helper_generic_probe(struct drm_fb_helper
> *fb_helper,
> #endif
> strcpy(fbi->fix.id, "DRM emulated");
>
> - drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->format->depth);
> - drm_fb_helper_fill_var(fbi, fb_helper, sizes->fb_width,
> sizes->fb_height);
> + drm_fb_helper_fill_info(fbi, fb_helper);
>
> if (fb->funcs->dirty) {
> struct fb_ops *fbops;
> diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
> index bb9acea61369..e8d92724f472 100644
> --- a/include/drm/drm_fb_helper.h
> +++ b/include/drm/drm_fb_helper.h
> @@ -292,6 +292,7 @@ void drm_fb_helper_fill_var(struct fb_info *info, struct
> drm_fb_helper *fb_helpe
> uint32_t fb_width, uint32_t fb_height);
> void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,
> uint32_t depth);
> +void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper
> *fb_helper);
>
> void drm_fb_helper_unlink_fbi(struct drm_fb_helper *fb_helper);
>
>
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Re: [Intel-gfx] [PATCH 02/26] drm: Switch DRIVER_ flags to an enum
Hi Daniel. > + > + /** > + * @DRIVER_HAVE_DMA: > + * > + * Driver supports DMA, the userspace DMA API will be supported. Only > + * for legacy drivers. Do not use. > + */ > + DRIVER_HAVE_DMA = BIT(4), What about grouping all the "legacy, do not use" flags in the bottom. Maybe counting backwards. Then one does not have "noise" in-between when trying to rad and understand the relevant flags for a new driver. Unless I am mistaken nothing should break because we change the bit for a certain function, but I see you kept the current order thus the current vlaues. > @@ -662,7 +766,7 @@ static inline bool drm_dev_is_unplugged(struct drm_device > *dev) > * @feature: feature flag > * > * This checks @dev for driver features, see _driver.driver_features, > - * _device.driver_features, and the various DRIVER_\* flags. > + * _device.driver_features, and the various drm_driver_feature > flags. > * > * Returns true if the @feature is supported, false otherwise. > */ Thanks for fixing this - I had a patch floating to do the same. But this fix is better than what I did. With or without a change in ordering you can add: Reviewed-by: Sam Ravnborg ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/26] drm/fb-helper: set fbi->fix.id in fill_info()
On Thu, Jan 24, 2019 at 5:58 PM Daniel Vetter wrote:
>
> Looking at the oldest/most popular drivers ${driver}drmfb seems to be
> the standard, except i915.ko went with "inteldrmfb". I guess renaming
> that for consistency won't hurt, it definitely confused me when I
> started with kms 10 years ago.
>
> I hope this never became uapi ... worst case drivers can overwrite it
> after having called fill_info().
>
> Signed-off-by: Daniel Vetter
Since subsequent patches change this for some drivers later on in the
series, here's the exhaustive list of where all fix.id is used:
- /proc/fb which prints the minor number and fix.id name.
- per-fb sysfs name file
- getfix ioctl, which is used by fbset only to print out the name when
dumping information
- lots and lots of places in dmesg, anytime anything happens with an
fbdev really
I think minimal to 0 chances that changing this will screw up a config
script or something, since outside of informational message it's not
used by anything to identify which fbdev maps to which minor. After
all the last fbset release is from 1999, and that predates even devfs
I think.
I'll add the above to the commit message when merging/resending.
Thanks to Ilia for pointing out.
-Daniel
> ---
> drivers/gpu/drm/drm_fb_helper.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index 34c4ed378796..20969c05a9e3 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -2126,6 +2126,9 @@ void drm_fb_helper_fill_info(struct fb_info *info,
> drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
> drm_fb_helper_fill_var(info, fb_helper, fb->width, fb->height);
>
> + snprintf(info->fix.id, sizeof(info->fix.id), "%sdrmfb",
> +fb_helper->dev->driver->name);
> +
> }
> EXPORT_SYMBOL(drm_fb_helper_fill_info);
>
> @@ -3185,8 +3188,6 @@ int drm_fb_helper_generic_probe(struct drm_fb_helper
> *fb_helper,
> fbi->fix.smem_start =
> page_to_phys(virt_to_page(fbi->screen_buffer));
> #endif
> - strcpy(fbi->fix.id, "DRM emulated");
> -
> drm_fb_helper_fill_info(fbi, fb_helper);
>
> if (fb->funcs->dirty) {
> --
> 2.20.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 31/38] drm/i915: Allow contexts to share a single timeline across all engines
On 18/01/2019 14:01, Chris Wilson wrote:
Previously, our view has been always to run the engines independently
within a context. (Multiple engines happened before we had contexts and
timelines, so they always operated independently and that behaviour
persisted into contexts.) However, at the user level the context often
represents a single timeline (e.g. GL contexts) and userspace must
ensure that the individual engines are serialised to present that
ordering to the client (or forgot about this detail entirely and hope no
one notices - a fair ploy if the client can only directly control one
engine themselves ;)
In the next patch, we will want to construct a set of engines that
operate as one, that have a single timeline interwoven between them, to
present a single virtual engine to the user. (They submit to the virtual
engine, then we decide which engine to execute on based.)
To that end, we want to be able to create contexts which have a single
timeline (fence context) shared between all engines, rather than multiple
timelines.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 33 +---
drivers/gpu/drm/i915/i915_gem_context.h | 3 ++
drivers/gpu/drm/i915/i915_request.c | 10 -
drivers/gpu/drm/i915/i915_request.h | 5 ++-
drivers/gpu/drm/i915/i915_sw_fence.c | 39 ---
drivers/gpu/drm/i915/i915_sw_fence.h | 13 ++-
drivers/gpu/drm/i915/intel_lrc.c | 5 ++-
.../gpu/drm/i915/selftests/i915_gem_context.c | 17
drivers/gpu/drm/i915/selftests/mock_context.c | 2 +-
include/uapi/drm/i915_drm.h | 1 +
10 files changed, 103 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index ec5e3e1c6402..e28be242399d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -225,6 +225,9 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
ce->ops->destroy(ce);
}
+ if (ctx->timeline)
+ i915_timeline_put(ctx->timeline);
+
kfree(ctx->name);
put_pid(ctx->pid);
@@ -425,12 +428,17 @@ static void __set_ppgtt(struct i915_gem_context *ctx,
static struct i915_gem_context *
i915_gem_create_context(struct drm_i915_private *dev_priv,
- struct drm_i915_file_private *file_priv)
+ struct drm_i915_file_private *file_priv,
+ unsigned int flags)
{
struct i915_gem_context *ctx;
lockdep_assert_held(_priv->drm.struct_mutex);
+ if (flags & I915_GEM_CONTEXT_SINGLE_TIMELINE &&
+ !HAS_EXECLISTS(dev_priv))
+ return ERR_PTR(-EINVAL);
+
/* Reap the most stale context */
contexts_free_first(dev_priv);
@@ -453,6 +461,18 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
i915_ppgtt_put(ppgtt);
}
+ if (flags & I915_GEM_CONTEXT_SINGLE_TIMELINE) {
+ struct i915_timeline *timeline;
+
+ timeline = i915_timeline_create(dev_priv, ctx->name, NULL);
+ if (IS_ERR(timeline)) {
+ __destroy_hw_context(ctx, file_priv);
+ return ERR_CAST(timeline);
+ }
+
+ ctx->timeline = timeline;
+ }
+
trace_i915_context_create(ctx);
return ctx;
@@ -481,7 +501,7 @@ i915_gem_context_create_gvt(struct drm_device *dev)
if (ret)
return ERR_PTR(ret);
- ctx = i915_gem_create_context(to_i915(dev), NULL);
+ ctx = i915_gem_create_context(to_i915(dev), NULL, 0);
if (IS_ERR(ctx))
goto out;
@@ -517,7 +537,7 @@ i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
struct i915_gem_context *ctx;
int err;
- ctx = i915_gem_create_context(i915, NULL);
+ ctx = i915_gem_create_context(i915, NULL, 0);
if (IS_ERR(ctx))
return ctx;
@@ -638,7 +658,7 @@ int i915_gem_context_open(struct drm_i915_private *i915,
idr_init_base(_priv->vm_idr, 1);
mutex_lock(>drm.struct_mutex);
- ctx = i915_gem_create_context(i915, file_priv);
+ ctx = i915_gem_create_context(i915, file_priv, 0);
mutex_unlock(>drm.struct_mutex);
if (IS_ERR(ctx)) {
idr_destroy(_priv->context_idr);
@@ -992,7 +1012,8 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
if (!DRIVER_CAPS(dev_priv)->has_logical_contexts)
return -ENODEV;
- if (args->flags)
+ if (args->flags &
+ ~(I915_GEM_CONTEXT_SINGLE_TIMELINE))
return -EINVAL;
if (client_is_banned(file_priv)) {
@@ -1007,7 +1028,7 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
if (ret)
return ret;
-
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Measure the required reserved size for request emission
== Series Details ==
Series: series starting with [1/3] drm/i915: Measure the required reserved size
for request emission
URL : https://patchwork.freedesktop.org/series/55684/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5475_full -> Patchwork_12028_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12028_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_color@pipe-a-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +5
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166]
Possible fixes
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-apl: FAIL [fdo#106641] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: FAIL [fdo#103232] -> PASS +4
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@pm_rpm@system-suspend:
- shard-glk: FAIL [fdo#103375] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5475 -> Patchwork_12028
CI_DRM_5475: 9ced33eacb10c4ec1f03010d6efd9f21c6cf3ef7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4788: 3f77380fabd4083f9857daa6cd454d0937077901 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12028: 873a9b8fccad5de50ed65c2ac2c4ff12f7a09cc7 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12028/
___
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[Intel-gfx] [PATCH 00/26] some cleanups, mostly around fbdev emulation
Hi all,
Flushing out my "I got bored over holidays" queue. A bit of docs, a bit of
simplication and a bunch of fbdev helper refactor. Review and comments
very much appreciated.
Cheers, Daniel
Daniel Vetter (26):
drm/irq: Don't check for DRIVER_HAVE_IRQ in drm_irq_(un)install
drm: Switch DRIVER_ flags to an enum
drm/irq: Ditch DRIVER_IRQ_SHARED
drm/fb-helper: Add fill_info() functions
drm/fb-helper: set fbi->fix.id in fill_info()
drm/fb_helper: set info->par in fill_info()
drm/amdgpu: Use drm_fb_helper_fill_info
drm/armada: Use drm_fb_helper_fill_info
drm/ast: Use drm_fb_helper_fill_info
drm/cirrus: Use drm_fb_helper_fill_info
drm/exynos: Use drm_fb_helper_fill_info
drm/gma500: Use drm_fb_helper_fill_info
drm/hibmc: Use drm_fb_helper_fill_info
drm/i915: Use drm_fb_helper_fill_info
drm/mga200g: Use drm_fb_helper_fill_info
drm/bochs: Use drm_fb_helper_fill_info
drm/nouveau: Use drm_fb_helper_fill_info
drm/omap: Use drm_fb_helper_fill_info
drm/qxl: Use drm_fb_helper_fill_info
drm/radeon: Use drm_fb_helper_fill_info
drm/rockchip: Use drm_fb_helper_fill_info
drm/qxl: Use drm_fb_helper_fill_info
drm/udl: Use drm_fb_helper_fill_info
staging/vboxvideo: Use drm_fb_helper_fill_info
drm/fb-helper: Unexport fill_{var,info}
drm/: Don't set FBINFO_(FLAG_)DEFAULT
Documentation/gpu/drm-internals.rst | 62 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 24 ++--
drivers/gpu/drm/arm/hdlcd_drv.c | 2 +-
drivers/gpu/drm/armada/armada_fbdev.c | 6 +-
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_fb.c | 7 +-
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 2 +-
drivers/gpu/drm/cirrus/cirrus_drv.h | 2 +-
drivers/gpu/drm/cirrus/cirrus_fbdev.c | 8 +-
drivers/gpu/drm/drm_fb_helper.c | 72 +-
drivers/gpu/drm/drm_irq.c | 10 +-
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 5 +-
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 2 +-
drivers/gpu/drm/gma500/framebuffer.c | 8 +-
drivers/gpu/drm/gma500/framebuffer.h | 2 +-
drivers/gpu/drm/gma500/psb_drv.c | 3 +-
.../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 2 +-
.../gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c | 9 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_fbdev.c| 7 +-
drivers/gpu/drm/meson/meson_drv.c | 2 +-
drivers/gpu/drm/mga/mga_drv.c | 2 +-
drivers/gpu/drm/mgag200/mgag200_drv.h | 2 +-
drivers/gpu/drm/mgag200/mgag200_fb.c | 8 +-
drivers/gpu/drm/msm/msm_drv.c | 3 +-
drivers/gpu/drm/msm/msm_fbdev.c | 6 +-
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 3 +-
drivers/gpu/drm/nouveau/nouveau_fbcon.c | 11 +-
drivers/gpu/drm/nouveau/nouveau_fbcon.h | 2 +-
drivers/gpu/drm/omapdrm/omap_fbdev.c | 6 +-
drivers/gpu/drm/qxl/qxl_drv.c | 1 -
drivers/gpu/drm/qxl/qxl_fb.c | 9 +-
drivers/gpu/drm/r128/r128_drv.c | 2 +-
drivers/gpu/drm/radeon/radeon_drv.c | 4 +-
drivers/gpu/drm/radeon/radeon_fb.c| 10 +-
drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 5 +-
drivers/gpu/drm/shmobile/shmob_drm_drv.c | 2 +-
drivers/gpu/drm/tegra/fb.c| 5 +-
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 +-
drivers/gpu/drm/udl/udl_fb.c | 7 +-
drivers/gpu/drm/vc4/vc4_drv.c | 1 -
drivers/gpu/drm/via/via_drv.c | 3 +-
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 2 +-
drivers/staging/vboxvideo/vbox_drv.c | 3 +-
drivers/staging/vboxvideo/vbox_fb.c | 8 +-
include/drm/drm_drv.h | 128 +++---
include/drm/drm_fb_helper.h | 5 +-
48 files changed, 200 insertions(+), 281 deletions(-)
--
2.20.1
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[Intel-gfx] [PATCH 17/26] drm/nouveau: Use drm_fb_helper_fill_info
This changes the fb name from "nouveaufb" to "nouveaudrmfb".
Aside: I wonder whether the in_interrupt() check is good enough for
the nouveau acceleration. Cargo-cult says drm_can_sleep() is needed,
which isn't actually working if you pick a .config without PREEMPT.
For the generic fbdev defio support we've gone with offloading
everything to a worker. For the non-accel callbacks (set_par, blank
and friends) checking for oops_in_progress is good enough to catch all
the evil calling contexts.
Signed-off-by: Daniel Vetter
Cc: Ben Skeggs
Cc: nouv...@lists.freedesktop.org
---
drivers/gpu/drm/nouveau/nouveau_fbcon.c | 7 +--
drivers/gpu/drm/nouveau/nouveau_fbcon.h | 2 +-
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 67572408d9ae..3a3d454b65e3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -366,12 +366,9 @@ nouveau_fbcon_create(struct drm_fb_helper *helper,
goto out_unlock;
}
- info->par = fbcon;
-
/* setup helper */
fbcon->helper.fb = >base;
- strcpy(info->fix.id, "nouveaufb");
if (!chan)
info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_DISABLED;
else
@@ -386,9 +383,7 @@ nouveau_fbcon_create(struct drm_fb_helper *helper,
info->screen_base = nvbo_kmap_obj_iovirtual(fb->nvbo);
info->screen_size = fb->nvbo->bo.mem.num_pages << PAGE_SHIFT;
- drm_fb_helper_fill_fix(info, fb->base.pitches[0],
- fb->base.format->depth);
- drm_fb_helper_fill_var(info, >helper, sizes->fb_width,
sizes->fb_height);
+ drm_fb_helper_fill_info(info, >helper);
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index db9d52047ef8..73a7eeba3973 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -32,7 +32,7 @@
#include "nouveau_display.h"
struct nouveau_fbdev {
- struct drm_fb_helper helper;
+ struct drm_fb_helper helper; /* must be first */
unsigned int saved_flags;
struct nvif_object surf2d;
struct nvif_object clip;
--
2.20.1
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[Intel-gfx] [PATCH 15/26] drm/mga200g: Use drm_fb_helper_fill_info
Should not result in any changes.
Signed-off-by: Daniel Vetter
Cc: Dave Airlie
Cc: Alex Deucher
Cc: "Christian König"
Cc: Junwei Zhang
Cc: Daniel Vetter
---
drivers/gpu/drm/mgag200/mgag200_drv.h | 2 +-
drivers/gpu/drm/mgag200/mgag200_fb.c | 8 +---
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h
b/drivers/gpu/drm/mgag200/mgag200_drv.h
index 0aaedc554879..71a235c2d848 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.h
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.h
@@ -113,7 +113,7 @@ struct mga_framebuffer {
};
struct mga_fbdev {
- struct drm_fb_helper helper;
+ struct drm_fb_helper helper; /* must be first */
struct mga_framebuffer mfb;
void *sysram;
int size;
diff --git a/drivers/gpu/drm/mgag200/mgag200_fb.c
b/drivers/gpu/drm/mgag200/mgag200_fb.c
index 6893934b26c0..cbb6afbb4ab6 100644
--- a/drivers/gpu/drm/mgag200/mgag200_fb.c
+++ b/drivers/gpu/drm/mgag200/mgag200_fb.c
@@ -195,8 +195,6 @@ static int mgag200fb_create(struct drm_fb_helper *helper,
goto err_alloc_fbi;
}
- info->par = mfbdev;
-
ret = mgag200_framebuffer_init(dev, >mfb, _cmd, gobj);
if (ret)
goto err_alloc_fbi;
@@ -209,17 +207,13 @@ static int mgag200fb_create(struct drm_fb_helper *helper,
/* setup helper */
mfbdev->helper.fb = fb;
- strcpy(info->fix.id, "mgadrmfb");
-
info->fbops = _ops;
/* setup aperture base/size for vesafb takeover */
info->apertures->ranges[0].base = mdev->dev->mode_config.fb_base;
info->apertures->ranges[0].size = mdev->mc.vram_size;
- drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
- drm_fb_helper_fill_var(info, >helper, sizes->fb_width,
- sizes->fb_height);
+ drm_fb_helper_fill_info(info, >helper);
info->screen_base = sysram;
info->screen_size = size;
--
2.20.1
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[Intel-gfx] [PATCH 02/26] drm: Switch DRIVER_ flags to an enum
And move the documenation we alreay have into kerneldoc, plus a bit of
polish while at it.
FIXME: Updates for drm_driver.driver_features are missing, need to get
Sam's patches landed first.
Signed-off-by: Daniel Vetter
---
Documentation/gpu/drm-internals.rst | 62 -
include/drm/drm_drv.h | 138
2 files changed, 121 insertions(+), 79 deletions(-)
diff --git a/Documentation/gpu/drm-internals.rst
b/Documentation/gpu/drm-internals.rst
index 2caf21effd28..3ae23a5454ac 100644
--- a/Documentation/gpu/drm-internals.rst
+++ b/Documentation/gpu/drm-internals.rst
@@ -39,68 +39,6 @@ sections.
Driver Information
--
-Driver Features
-~~~
-
-Drivers inform the DRM core about their requirements and supported
-features by setting appropriate flags in the driver_features field.
-Since those flags influence the DRM core behaviour since registration
-time, most of them must be set to registering the :c:type:`struct
-drm_driver ` instance.
-
-u32 driver_features;
-
-DRIVER_USE_AGP
-Driver uses AGP interface, the DRM core will manage AGP resources.
-
-DRIVER_LEGACY
-Denote a legacy driver using shadow attach. Don't use.
-
-DRIVER_KMS_LEGACY_CONTEXT
-Used only by nouveau for backwards compatibility with existing userspace.
-Don't use.
-
-DRIVER_PCI_DMA
-Driver is capable of PCI DMA, mapping of PCI DMA buffers to
-userspace will be enabled. Deprecated.
-
-DRIVER_SG
-Driver can perform scatter/gather DMA, allocation and mapping of
-scatter/gather buffers will be enabled. Deprecated.
-
-DRIVER_HAVE_DMA
-Driver supports DMA, the userspace DMA API will be supported.
-Deprecated.
-
-DRIVER_HAVE_IRQ; DRIVER_IRQ_SHARED
-DRIVER_HAVE_IRQ indicates whether the driver has an IRQ handler
-managed by the DRM Core. The core will support simple IRQ handler
-installation when the flag is set. The installation process is
-described in ?.
-
-DRIVER_IRQ_SHARED indicates whether the device & handler support
-shared IRQs (note that this is required of PCI drivers).
-
-DRIVER_GEM
-Driver use the GEM memory manager.
-
-DRIVER_MODESET
-Driver supports mode setting interfaces (KMS).
-
-DRIVER_PRIME
-Driver implements DRM PRIME buffer sharing.
-
-DRIVER_RENDER
-Driver supports dedicated render nodes.
-
-DRIVER_ATOMIC
-Driver supports atomic properties. In this case the driver must
-implement appropriate obj->atomic_get_property() vfuncs for any
-modeset objects with driver specific properties.
-
-DRIVER_SYNCOBJ
-Driver support drm sync objects.
-
Major, Minor and Patchlevel
~~~
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index 35af23f5fa0d..fbbcd2887ea8 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -41,21 +41,120 @@ struct drm_display_mode;
struct drm_mode_create_dumb;
struct drm_printer;
-/* driver capabilities and requirements mask */
-#define DRIVER_USE_AGP 0x1
-#define DRIVER_LEGACY 0x2
-#define DRIVER_PCI_DMA 0x8
-#define DRIVER_SG 0x10
-#define DRIVER_HAVE_DMA0x20
-#define DRIVER_HAVE_IRQ0x40
-#define DRIVER_IRQ_SHARED 0x80
-#define DRIVER_GEM 0x1000
-#define DRIVER_MODESET 0x2000
-#define DRIVER_PRIME 0x4000
-#define DRIVER_RENDER 0x8000
-#define DRIVER_ATOMIC 0x1
-#define DRIVER_KMS_LEGACY_CONTEXT 0x2
-#define DRIVER_SYNCOBJ 0x4
+/**
+ * enum drm_driver_feature - feature flags
+ *
+ * See _driver.driver_features, drm_device.driver_features and
+ * drm_core_check_feature().
+ */
+enum drm_driver_feature {
+ /**
+* @DRIVER_USE_AGP:
+*
+* Set up DRM AGP support, see drm_agp_init(), the DRM core will manage
+* AGP resources. New drivers don't need this.
+*/
+ DRIVER_USE_AGP = BIT(0),
+ /**
+* @DRIVER_LEGACY:
+*
+* Denote a legacy driver using shadow attach. Do not use.
+*/
+ DRIVER_LEGACY = BIT(1),
+ /**
+* @DRIVER_PCI_DMA:
+*
+* Driver is capable of PCI DMA, mapping of PCI DMA buffers to userspace
+* will be enabled. Only for legacy drivers. Do not use.
+*/
+ DRIVER_PCI_DMA = BIT(2),
+ /**
+* @DRIVER_SG:
+*
+* Driver can perform scatter/gather DMA, allocation and mapping of
+* scatter/gather buffers will be enabled. Only for legacy drivers. Do
+* not use.
+*/
+ DRIVER_SG = BIT(3),
+
+ /**
+* @DRIVER_HAVE_DMA:
+*
+* Driver supports DMA, the userspace DMA API will be supported. Only
+* for legacy drivers. Do not use.
+*/
+
[Intel-gfx] ✗ Fi.CI.BAT: failure for some cleanups, mostly around fbdev emulation
== Series Details == Series: some cleanups, mostly around fbdev emulation URL : https://patchwork.freedesktop.org/series/55690/ State : failure == Summary == Applying: drm/irq: Don't check for DRIVER_HAVE_IRQ in drm_irq_(un)install Applying: drm: Switch DRIVER_ flags to an enum Applying: drm/irq: Ditch DRIVER_IRQ_SHARED Applying: drm/fb-helper: Add fill_info() functions Applying: drm/fb-helper: set fbi->fix.id in fill_info() Applying: drm/fb_helper: set info->par in fill_info() Applying: drm/amdgpu: Use drm_fb_helper_fill_info Using index info to reconstruct a base tree... M drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c CONFLICT (content): Merge conflict in drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0007 drm/amdgpu: Use drm_fb_helper_fill_info When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/26] drm/amdgpu: Use drm_fb_helper_fill_info
Should not cause any changes.
Signed-off-by: Daniel Vetter
Cc: Alex Deucher
Cc: "Christian König"
Cc: Samuel Li
Cc: "Michel Dänzer"
Cc: Huang Rui
Cc: Junwei Zhang
Cc: Daniel Vetter
Cc: Daniel Stone
Cc: Shirish S
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 24890d8f9ee4..dd37170af42b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -49,12 +49,11 @@
static int
amdgpufb_open(struct fb_info *info, int user)
{
- struct amdgpu_fbdev *rfbdev = info->par;
- struct amdgpu_device *adev = rfbdev->adev;
- int ret = pm_runtime_get_sync(adev->ddev->dev);
+ struct drm_fb_helper *fb_helper = info->par;
+ int ret = pm_runtime_get_sync(fb_helper->dev->dev);
if (ret < 0 && ret != -EACCES) {
- pm_runtime_mark_last_busy(adev->ddev->dev);
- pm_runtime_put_autosuspend(adev->ddev->dev);
+ pm_runtime_mark_last_busy(fb_helper->dev->dev);
+ pm_runtime_put_autosuspend(fb_helper->dev->dev);
return ret;
}
return 0;
@@ -63,11 +62,10 @@ amdgpufb_open(struct fb_info *info, int user)
static int
amdgpufb_release(struct fb_info *info, int user)
{
- struct amdgpu_fbdev *rfbdev = info->par;
- struct amdgpu_device *adev = rfbdev->adev;
+ struct drm_fb_helper *fb_helper = info->par;
- pm_runtime_mark_last_busy(adev->ddev->dev);
- pm_runtime_put_autosuspend(adev->ddev->dev);
+ pm_runtime_mark_last_busy(fb_helper->dev->dev);
+ pm_runtime_put_autosuspend(fb_helper->dev->dev);
return 0;
}
@@ -233,8 +231,6 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
goto out;
}
- info->par = rfbdev;
-
ret = amdgpu_display_framebuffer_init(adev->ddev, >rfb,
_cmd, gobj);
if (ret) {
@@ -247,10 +243,6 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
/* setup helper */
rfbdev->helper.fb = fb;
- strcpy(info->fix.id, "amdgpudrmfb");
-
- drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
-
info->fbops = _ops;
tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
@@ -259,7 +251,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
info->screen_base = amdgpu_bo_kptr(abo);
info->screen_size = amdgpu_bo_size(abo);
- drm_fb_helper_fill_var(info, >helper, sizes->fb_width,
sizes->fb_height);
+ drm_fb_helper_fill_info(info, >helper);
/* setup aperture base/size for vesafb takeover */
info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
--
2.20.1
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[Intel-gfx] [PATCH 14/26] drm/i915: Use drm_fb_helper_fill_info
This changes the fb name from "inteldrmfb" to "i915drmfb". Signed-off-by: Daniel Vetter Cc: Jani Nikula Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org --- drivers/gpu/drm/i915/intel_fbdev.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index f37d2aee24f5..29800fdcf830 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -235,12 +235,8 @@ static int intelfb_create(struct drm_fb_helper *helper, goto out_unpin; } - info->par = helper; - ifbdev->helper.fb = fb; - strcpy(info->fix.id, "inteldrmfb"); - info->fbops = _ops; /* setup aperture base/size for vesafb takeover */ @@ -259,8 +255,7 @@ static int intelfb_create(struct drm_fb_helper *helper, info->screen_base = vaddr; info->screen_size = vma->node.size; - drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); - drm_fb_helper_fill_var(info, >helper, sizes->fb_width, sizes->fb_height); + drm_fb_helper_fill_info(info, >helper); /* If the object is shmemfs backed, it will have given us zeroed pages. * If the object is stolen however, it will be full of whatever -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/26] drm/fb-helper: set fbi->fix.id in fill_info()
Looking at the oldest/most popular drivers ${driver}drmfb seems to be
the standard, except i915.ko went with "inteldrmfb". I guess renaming
that for consistency won't hurt, it definitely confused me when I
started with kms 10 years ago.
I hope this never became uapi ... worst case drivers can overwrite it
after having called fill_info().
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_fb_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 34c4ed378796..20969c05a9e3 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2126,6 +2126,9 @@ void drm_fb_helper_fill_info(struct fb_info *info,
drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
drm_fb_helper_fill_var(info, fb_helper, fb->width, fb->height);
+ snprintf(info->fix.id, sizeof(info->fix.id), "%sdrmfb",
+fb_helper->dev->driver->name);
+
}
EXPORT_SYMBOL(drm_fb_helper_fill_info);
@@ -3185,8 +3188,6 @@ int drm_fb_helper_generic_probe(struct drm_fb_helper
*fb_helper,
fbi->fix.smem_start =
page_to_phys(virt_to_page(fbi->screen_buffer));
#endif
- strcpy(fbi->fix.id, "DRM emulated");
-
drm_fb_helper_fill_info(fbi, fb_helper);
if (fb->funcs->dirty) {
--
2.20.1
___
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[Intel-gfx] [PATCH 16/26] drm/bochs: Use drm_fb_helper_fill_info
This will change the fb name from "msm" to "msmdrmfb". Signed-off-by: Daniel Vetter Cc: Rob Clark Cc: linux-arm-...@vger.kernel.org Cc: freedr...@lists.freedesktop.org --- drivers/gpu/drm/msm/msm_fbdev.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c index c03e860ba737..29f71ae1f634 100644 --- a/drivers/gpu/drm/msm/msm_fbdev.c +++ b/drivers/gpu/drm/msm/msm_fbdev.c @@ -122,13 +122,9 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, fbdev->fb = fb; helper->fb = fb; - fbi->par = helper; fbi->fbops = _fb_ops; - strcpy(fbi->fix.id, "msm"); - - drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->format->depth); - drm_fb_helper_fill_var(fbi, helper, sizes->fb_width, sizes->fb_height); + drm_fb_helper_fill_info(fbi, helper); dev->mode_config.fb_base = paddr; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/26] drm/irq: Ditch DRIVER_IRQ_SHARED
This is only used by drm_irq_install(), which is an optional helper.
And the right choice is to set it for all pci devices, and not for
everything else.
Any driver with special needs should just use request_irq() directly,
and there's plenty of drivers doing that already.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
drivers/gpu/drm/drm_irq.c | 4 ++--
drivers/gpu/drm/gma500/psb_drv.c| 3 +--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/mga/mga_drv.c | 2 +-
drivers/gpu/drm/qxl/qxl_drv.c | 1 -
drivers/gpu/drm/r128/r128_drv.c | 2 +-
drivers/gpu/drm/radeon/radeon_drv.c | 4 +---
drivers/gpu/drm/via/via_drv.c | 3 +--
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 2 +-
drivers/staging/vboxvideo/vbox_drv.c| 3 +--
include/drm/drm_drv.h | 24 +++-
12 files changed, 18 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 22502417c18c..a1bb3773087b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1189,7 +1189,7 @@ amdgpu_get_crtc_scanout_position(struct drm_device *dev,
unsigned int pipe,
static struct drm_driver kms_driver = {
.driver_features =
DRIVER_USE_AGP | DRIVER_ATOMIC |
- DRIVER_IRQ_SHARED | DRIVER_GEM |
+ DRIVER_GEM |
DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
.load = amdgpu_driver_load_kms,
.open = amdgpu_driver_open_kms,
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index c5babb3e4752..9bd8908d5fd8 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -120,8 +120,8 @@ int drm_irq_install(struct drm_device *dev, int irq)
if (dev->driver->irq_preinstall)
dev->driver->irq_preinstall(dev);
- /* Install handler */
- if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED))
+ /* PCI devices require shared interrupts. */
+ if (dev->pdev)
sh_flags = IRQF_SHARED;
ret = request_irq(irq, dev->driver->irq_handler,
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c
index 7cf14aeb1c28..eefaf4daff2b 100644
--- a/drivers/gpu/drm/gma500/psb_drv.c
+++ b/drivers/gpu/drm/gma500/psb_drv.c
@@ -468,8 +468,7 @@ static const struct file_operations psb_gem_fops = {
};
static struct drm_driver driver = {
- .driver_features = DRIVER_IRQ_SHARED | \
- DRIVER_MODESET | DRIVER_GEM,
+ .driver_features = DRIVER_MODESET | DRIVER_GEM,
.load = psb_driver_load,
.unload = psb_driver_unload,
.lastclose = drm_fb_helper_lastclose,
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 550cfb945942..a7aaa1ac4c99 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -3010,7 +3010,7 @@ static struct drm_driver driver = {
* deal with them for Intel hardware.
*/
.driver_features =
- DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
+ DRIVER_GEM | DRIVER_PRIME |
DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
.release = i915_driver_release,
.open = i915_driver_open,
diff --git a/drivers/gpu/drm/mga/mga_drv.c b/drivers/gpu/drm/mga/mga_drv.c
index 1aad27813c23..6e1d1054ad06 100644
--- a/drivers/gpu/drm/mga/mga_drv.c
+++ b/drivers/gpu/drm/mga/mga_drv.c
@@ -57,7 +57,7 @@ static const struct file_operations mga_driver_fops = {
static struct drm_driver driver = {
.driver_features =
DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_LEGACY |
- DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED,
+ DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ,
.dev_priv_size = sizeof(drm_mga_buf_priv_t),
.load = mga_driver_load,
.unload = mga_driver_unload,
diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c
index 44daac129205..d856615bdb50 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.c
+++ b/drivers/gpu/drm/qxl/qxl_drv.c
@@ -243,7 +243,6 @@ static struct pci_driver qxl_pci_driver = {
static struct drm_driver qxl_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
- DRIVER_IRQ_SHARED |
DRIVER_ATOMIC,
.dumb_create = qxl_mode_dumb_create,
diff --git a/drivers/gpu/drm/r128/r128_drv.c b/drivers/gpu/drm/r128/r128_drv.c
index 0d2b7e42b3a7..4b1a505ab353 100644
--- a/drivers/gpu/drm/r128/r128_drv.c
+++ b/drivers/gpu/drm/r128/r128_drv.c
@@ -57,7 +57,7 @@ static const struct file_operations r128_driver_fops = {
static struct drm_driver driver = {
.driver_features =
DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_LEGACY |
- DRIVER_HAVE_DMA |
[Intel-gfx] [PATCH 11/26] drm/exynos: Use drm_fb_helper_fill_info
This will give the exynos fbdev a name! Signed-off-by: Daniel Vetter Cc: Inki Dae Cc: Joonyoung Shim Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: linux-arm-ker...@lists.infradead.org Cc: linux-samsung-...@vger.kernel.org --- drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c index f057082a9b30..b2018961b9cf 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c @@ -87,12 +87,10 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper, return PTR_ERR(fbi); } - fbi->par = helper; fbi->flags = FBINFO_FLAG_DEFAULT; fbi->fbops = _drm_fb_ops; - drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->format->depth); - drm_fb_helper_fill_var(fbi, helper, sizes->fb_width, sizes->fb_height); + drm_fb_helper_fill_info(fbi, helper); nr_pages = exynos_gem->size >> PAGE_SHIFT; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/26] drm/irq: Don't check for DRIVER_HAVE_IRQ in drm_irq_(un)install
If a non-legacy driver calls these it's valid to assume there is
interrupt support. The flag is really only needed for legacy drivers.
Also remove all the flag usage from non-legacy drivers.
Signed-off-by: Daniel Vetter
Cc: linux-arm-ker...@lists.infradead.org
Cc: intel-gfx@lists.freedesktop.org
Cc: linux-amlo...@lists.infradead.org
Cc: linux-arm-...@vger.kernel.org
Cc: freedr...@lists.freedesktop.org
Cc: virtualizat...@lists.linux-foundation.org
Cc: spice-de...@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
Cc: linux-renesas-...@vger.kernel.org
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
drivers/gpu/drm/arm/hdlcd_drv.c | 2 +-
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 2 +-
drivers/gpu/drm/drm_irq.c| 6 --
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c| 2 +-
drivers/gpu/drm/gma500/psb_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/meson/meson_drv.c| 2 +-
drivers/gpu/drm/msm/msm_drv.c| 3 +--
drivers/gpu/drm/mxsfb/mxsfb_drv.c| 3 +--
drivers/gpu/drm/qxl/qxl_drv.c| 2 +-
drivers/gpu/drm/radeon/radeon_drv.c | 2 +-
drivers/gpu/drm/shmobile/shmob_drm_drv.c | 2 +-
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 +-
drivers/gpu/drm/vc4/vc4_drv.c| 1 -
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 2 +-
drivers/staging/vboxvideo/vbox_drv.c | 2 +-
17 files changed, 15 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0c22bae0c736..22502417c18c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1189,7 +1189,7 @@ amdgpu_get_crtc_scanout_position(struct drm_device *dev,
unsigned int pipe,
static struct drm_driver kms_driver = {
.driver_features =
DRIVER_USE_AGP | DRIVER_ATOMIC |
- DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
+ DRIVER_IRQ_SHARED | DRIVER_GEM |
DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
.load = amdgpu_driver_load_kms,
.open = amdgpu_driver_open_kms,
diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c
index e68935b80917..8fc0b884c428 100644
--- a/drivers/gpu/drm/arm/hdlcd_drv.c
+++ b/drivers/gpu/drm/arm/hdlcd_drv.c
@@ -229,7 +229,7 @@ static int hdlcd_debugfs_init(struct drm_minor *minor)
DEFINE_DRM_GEM_CMA_FOPS(fops);
static struct drm_driver hdlcd_driver = {
- .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
+ .driver_features = DRIVER_GEM |
DRIVER_MODESET | DRIVER_PRIME |
DRIVER_ATOMIC,
.irq_handler = hdlcd_irq,
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
index 034a91112098..0be13eceedba 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
@@ -720,7 +720,7 @@ static void atmel_hlcdc_dc_irq_uninstall(struct drm_device
*dev)
DEFINE_DRM_GEM_CMA_FOPS(fops);
static struct drm_driver atmel_hlcdc_dc_driver = {
- .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
+ .driver_features = DRIVER_GEM |
DRIVER_MODESET | DRIVER_PRIME |
DRIVER_ATOMIC,
.irq_handler = atmel_hlcdc_dc_irq_handler,
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 45a07652fa00..c5babb3e4752 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -103,9 +103,6 @@ int drm_irq_install(struct drm_device *dev, int irq)
int ret;
unsigned long sh_flags = 0;
- if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
- return -EOPNOTSUPP;
-
if (irq == 0)
return -EINVAL;
@@ -174,9 +171,6 @@ int drm_irq_uninstall(struct drm_device *dev)
bool irq_enabled;
int i;
- if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
- return -EOPNOTSUPP;
-
irq_enabled = dev->irq_enabled;
dev->irq_enabled = false;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 54ace3436605..dfc73aade325 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -137,7 +137,7 @@ static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
DEFINE_DRM_GEM_CMA_FOPS(fsl_dcu_drm_fops);
static struct drm_driver fsl_dcu_drm_driver = {
- .driver_features= DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET
+ .driver_features= DRIVER_GEM | DRIVER_MODESET
| DRIVER_PRIME | DRIVER_ATOMIC,
.load = fsl_dcu_load,
.unload = fsl_dcu_unload,
diff --git a/drivers/gpu/drm/gma500/psb_drv.c
[Intel-gfx] [PATCH 21/26] drm/rockchip: Use drm_fb_helper_fill_info
This will set an fb name for the first time! Signed-off-by: Daniel Vetter Cc: Sandy Huang Cc: "Heiko Stübner" Cc: linux-arm-ker...@lists.infradead.org Cc: linux-rockc...@lists.infradead.org --- drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c index 7bd3b89022be..d12164878e05 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c @@ -90,13 +90,11 @@ static int rockchip_drm_fbdev_create(struct drm_fb_helper *helper, goto out; } - fbi->par = helper; fbi->flags = FBINFO_FLAG_DEFAULT; fbi->fbops = _drm_fbdev_ops; fb = helper->fb; - drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->format->depth); - drm_fb_helper_fill_var(fbi, helper, sizes->fb_width, sizes->fb_height); + drm_fb_helper_fill_info(fbi, helper); offset = fbi->var.xoffset * bytes_per_pixel; offset += fbi->var.yoffset * fb->pitches[0]; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 25/26] drm/fb-helper: Unexport fill_{var,info}
Not used by drivers anymore.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_fb_helper.c | 38 +
include/drm/drm_fb_helper.h | 4
2 files changed, 5 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index cbe7fda3f8af..9c38c48ba3aa 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2037,21 +2037,8 @@ static int drm_fb_helper_single_fb_probe(struct
drm_fb_helper *fb_helper,
return 0;
}
-/**
- * drm_fb_helper_fill_fix - initializes fixed fbdev information
- * @info: fbdev registered by the helper
- * @pitch: desired pitch
- * @depth: desired depth
- *
- * Helper to fill in the fixed fbdev information useful for a non-accelerated
- * fbdev emulations. Drivers which support acceleration methods which impose
- * additional constraints need to set up their own limits.
- *
- * Drivers should call this (or their equivalent setup code) from their
- * _fb_helper_funcs.fb_probe callback.
- */
-void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,
- uint32_t depth)
+static void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,
+ uint32_t depth)
{
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = depth == 8 ? FB_VISUAL_PSEUDOCOLOR :
@@ -2066,24 +2053,10 @@ void drm_fb_helper_fill_fix(struct fb_info *info,
uint32_t pitch,
info->fix.line_length = pitch;
}
-EXPORT_SYMBOL(drm_fb_helper_fill_fix);
-/**
- * drm_fb_helper_fill_var - initalizes variable fbdev information
- * @info: fbdev instance to set up
- * @fb_helper: fb helper instance to use as template
- * @fb_width: desired fb width
- * @fb_height: desired fb height
- *
- * Sets up the variable fbdev metainformation from the given fb helper instance
- * and the drm framebuffer allocated in _fb_helper.fb.
- *
- * Drivers should call this (or their equivalent setup code) from their
- * _fb_helper_funcs.fb_probe callback after having allocated the fbdev
- * backing storage framebuffer.
- */
-void drm_fb_helper_fill_var(struct fb_info *info, struct drm_fb_helper
*fb_helper,
- uint32_t fb_width, uint32_t fb_height)
+static void drm_fb_helper_fill_var(struct fb_info *info,
+ struct drm_fb_helper *fb_helper,
+ uint32_t fb_width, uint32_t fb_height)
{
struct drm_framebuffer *fb = fb_helper->fb;
@@ -2103,7 +2076,6 @@ void drm_fb_helper_fill_var(struct fb_info *info, struct
drm_fb_helper *fb_helpe
info->var.xres = fb_width;
info->var.yres = fb_height;
}
-EXPORT_SYMBOL(drm_fb_helper_fill_var);
/**
* drm_fb_helper_fill_info - initializes fbdev information
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index e8d92724f472..9c2f924d67c5 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -288,10 +288,6 @@ int drm_fb_helper_restore_fbdev_mode_unlocked(struct
drm_fb_helper *fb_helper);
struct fb_info *drm_fb_helper_alloc_fbi(struct drm_fb_helper *fb_helper);
void drm_fb_helper_unregister_fbi(struct drm_fb_helper *fb_helper);
-void drm_fb_helper_fill_var(struct fb_info *info, struct drm_fb_helper
*fb_helper,
- uint32_t fb_width, uint32_t fb_height);
-void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,
- uint32_t depth);
void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper
*fb_helper);
void drm_fb_helper_unlink_fbi(struct drm_fb_helper *fb_helper);
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 26/26] drm/: Don't set FBINFO_(FLAG_)DEFAULT
It's 0.
Signed-off-by: Daniel Vetter
Cc: Inki Dae
Cc: Joonyoung Shim
Cc: Seung-Woo Kim
Cc: Kyungmin Park
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Cc: Patrik Jakobsson
Cc: Ben Skeggs
Cc: Sandy Huang
Cc: "Heiko Stübner"
Cc: Thierry Reding
Cc: Jonathan Hunter
Cc: Hans de Goede
Cc: Greg Kroah-Hartman
Cc: Daniel Vetter
Cc: Bartlomiej Zolnierkiewicz
Cc: Alexander Kapshuk
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-samsung-...@vger.kernel.org
Cc: nouv...@lists.freedesktop.org
Cc: linux-rockc...@lists.infradead.org
Cc: linux-te...@vger.kernel.org
---
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 1 -
drivers/gpu/drm/gma500/framebuffer.c | 1 -
drivers/gpu/drm/nouveau/nouveau_fbcon.c | 4 ++--
drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 1 -
drivers/gpu/drm/tegra/fb.c| 1 -
5 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index b2018961b9cf..00bfcd28e589 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -87,7 +87,6 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper
*helper,
return PTR_ERR(fbi);
}
- fbi->flags = FBINFO_FLAG_DEFAULT;
fbi->fbops = _drm_fb_ops;
drm_fb_helper_fill_info(fbi, helper);
diff --git a/drivers/gpu/drm/gma500/framebuffer.c
b/drivers/gpu/drm/gma500/framebuffer.c
index c7a5c29f9a69..3b59dbadfa63 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -401,7 +401,6 @@ static int psbfb_create(struct psb_fbdev *fbdev,
fbdev->psb_fb_helper.fb = fb;
- info->flags = FBINFO_DEFAULT;
if (dev_priv->ops->accel_2d && pitch_lines > 8) /* 2D engine */
info->fbops = _ops;
else if (gtt_roll) {/* GTT rolling seems best */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 3a3d454b65e3..1136ee26005f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -370,9 +370,9 @@ nouveau_fbcon_create(struct drm_fb_helper *helper,
fbcon->helper.fb = >base;
if (!chan)
- info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_DISABLED;
+ info->flags = FBINFO_HWACCEL_DISABLED;
else
- info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
+ info->flags = FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_IMAGEBLIT;
info->fbops = _fbcon_sw_ops;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
index d12164878e05..fed7d7698164 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
@@ -90,7 +90,6 @@ static int rockchip_drm_fbdev_create(struct drm_fb_helper
*helper,
goto out;
}
- fbi->flags = FBINFO_FLAG_DEFAULT;
fbi->fbops = _drm_fbdev_ops;
fb = helper->fb;
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
index 82348ddd0b83..ea82184073bd 100644
--- a/drivers/gpu/drm/tegra/fb.c
+++ b/drivers/gpu/drm/tegra/fb.c
@@ -255,7 +255,6 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper,
helper->fb = fb;
helper->fbdev = info;
- info->flags = FBINFO_FLAG_DEFAULT;
info->fbops = _fb_ops;
drm_fb_helper_fill_info(info, helper);
--
2.20.1
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[Intel-gfx] [PATCH 23/26] drm/udl: Use drm_fb_helper_fill_info
This should not result in any changes.
Signed-off-by: Daniel Vetter
Cc: Dave Airlie
Cc: Sean Paul
Cc: Mikulas Patocka
Cc: Daniel Vetter
Cc: Greg Kroah-Hartman
Cc: Emil Lundmark
---
drivers/gpu/drm/udl/udl_fb.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c
index dd9ffded223b..3e4804895d2e 100644
--- a/drivers/gpu/drm/udl/udl_fb.c
+++ b/drivers/gpu/drm/udl/udl_fb.c
@@ -32,7 +32,7 @@ module_param(fb_bpp, int, S_IWUSR | S_IRUSR | S_IWGRP |
S_IRGRP);
module_param(fb_defio, int, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
struct udl_fbdev {
- struct drm_fb_helper helper;
+ struct drm_fb_helper helper; /* must be first */
struct udl_framebuffer ufb;
int fb_count;
};
@@ -402,15 +402,12 @@ static int udlfb_create(struct drm_fb_helper *helper,
ufbdev->helper.fb = fb;
- strcpy(info->fix.id, "udldrmfb");
-
info->screen_base = ufbdev->ufb.obj->vmapping;
info->fix.smem_len = size;
info->fix.smem_start = (unsigned long)ufbdev->ufb.obj->vmapping;
info->fbops = _ops;
- drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
- drm_fb_helper_fill_var(info, >helper, sizes->fb_width,
sizes->fb_height);
+ drm_fb_helper_fill_info(info, >helper);
DRM_DEBUG_KMS("allocated %dx%d vmal %p\n",
fb->width, fb->height,
--
2.20.1
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[Intel-gfx] [PATCH 24/26] staging/vboxvideo: Use drm_fb_helper_fill_info
This should not result in any changes. v2: Rebase over vbox changes - vbox gained it's own line to fill fix.id. Signed-off-by: Daniel Vetter Cc: Greg Kroah-Hartman Cc: Hans de Goede Cc: Daniel Vetter Cc: Alexander Kapshuk Cc: Bartlomiej Zolnierkiewicz --- drivers/staging/vboxvideo/vbox_fb.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/staging/vboxvideo/vbox_fb.c b/drivers/staging/vboxvideo/vbox_fb.c index 397496cf0bdf..1da4cb7647b8 100644 --- a/drivers/staging/vboxvideo/vbox_fb.c +++ b/drivers/staging/vboxvideo/vbox_fb.c @@ -88,13 +88,9 @@ int vboxfb_create(struct drm_fb_helper *helper, if (IS_ERR(info->screen_base)) return PTR_ERR(info->screen_base); - info->par = helper; - fb = >afb.base; helper->fb = fb; - strcpy(info->fix.id, "vboxdrmfb"); - info->fbops = _ops; /* @@ -104,9 +100,7 @@ int vboxfb_create(struct drm_fb_helper *helper, info->apertures->ranges[0].base = pci_resource_start(pdev, 0); info->apertures->ranges[0].size = pci_resource_len(pdev, 0); - drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); - drm_fb_helper_fill_var(info, helper, sizes->fb_width, - sizes->fb_height); + drm_fb_helper_fill_info(info, helper); gpu_addr = vbox_bo_gpu_offset(bo); info->fix.smem_start = info->apertures->ranges[0].base + gpu_addr; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 22/26] drm/qxl: Use drm_fb_helper_fill_info
Another driver that didn't set fbinfo->fix.id before. Signed-off-by: Daniel Vetter Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-te...@vger.kernel.org --- drivers/gpu/drm/tegra/fb.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 5ee48a6bb3ad..82348ddd0b83 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -255,12 +255,10 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper, helper->fb = fb; helper->fbdev = info; - info->par = helper; info->flags = FBINFO_FLAG_DEFAULT; info->fbops = _fb_ops; - drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); - drm_fb_helper_fill_var(info, helper, fb->width, fb->height); + drm_fb_helper_fill_info(info, helper); offset = info->var.xoffset * bytes_per_pixel + info->var.yoffset * fb->pitches[0]; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/26] drm/qxl: Use drm_fb_helper_fill_info
This should not result in any changes.
Signed-off-by: Daniel Vetter
Cc: Dave Airlie
Cc: Gerd Hoffmann
Cc: virtualizat...@lists.linux-foundation.org
Cc: spice-de...@lists.freedesktop.org
---
drivers/gpu/drm/qxl/qxl_fb.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/qxl/qxl_fb.c b/drivers/gpu/drm/qxl/qxl_fb.c
index d028471597ef..22dc9a7a643b 100644
--- a/drivers/gpu/drm/qxl/qxl_fb.c
+++ b/drivers/gpu/drm/qxl/qxl_fb.c
@@ -219,8 +219,6 @@ static int qxlfb_create(struct drm_fb_helper *helper,
goto out_unref;
}
- info->par = helper;
-
fb = drm_gem_fbdev_fb_create(>ddev, sizes, 64, gobj,
_fb_funcs);
if (IS_ERR(fb)) {
@@ -232,10 +230,6 @@ static int qxlfb_create(struct drm_fb_helper *helper,
/* setup helper with fb data */
qdev->fb_helper.fb = fb;
- strcpy(info->fix.id, "qxldrmfb");
-
- drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
-
info->fbops = _ops;
/*
@@ -247,8 +241,7 @@ static int qxlfb_create(struct drm_fb_helper *helper,
info->screen_base = shadow;
info->screen_size = gobj->size;
- drm_fb_helper_fill_var(info, >fb_helper, sizes->fb_width,
- sizes->fb_height);
+ drm_fb_helper_fill_info(info, >fb_helper);
/* setup aperture base/size for vesafb takeover */
info->apertures->ranges[0].base = qdev->ddev.mode_config.fb_base;
--
2.20.1
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[Intel-gfx] [PATCH 12/26] drm/gma500: Use drm_fb_helper_fill_info
This will change the fb name from "psbdrmfb" to "gma500drmfb".
Signed-off-by: Daniel Vetter
Cc: Patrik Jakobsson
---
drivers/gpu/drm/gma500/framebuffer.c | 7 +--
drivers/gpu/drm/gma500/framebuffer.h | 2 +-
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/gma500/framebuffer.c
b/drivers/gpu/drm/gma500/framebuffer.c
index adefae58b5fc..c7a5c29f9a69 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -389,7 +389,6 @@ static int psbfb_create(struct psb_fbdev *fbdev,
ret = PTR_ERR(info);
goto out;
}
- info->par = fbdev;
mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
@@ -402,9 +401,6 @@ static int psbfb_create(struct psb_fbdev *fbdev,
fbdev->psb_fb_helper.fb = fb;
- drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
- strcpy(info->fix.id, "psbdrmfb");
-
info->flags = FBINFO_DEFAULT;
if (dev_priv->ops->accel_2d && pitch_lines > 8) /* 2D engine */
info->fbops = _ops;
@@ -428,8 +424,7 @@ static int psbfb_create(struct psb_fbdev *fbdev,
info->apertures->ranges[0].size = dev_priv->gtt.stolen_size;
}
- drm_fb_helper_fill_var(info, >psb_fb_helper,
- sizes->fb_width, sizes->fb_height);
+ drm_fb_helper_fill_info(info, >psb_fb_helper);
info->fix.mmio_start = pci_resource_start(dev->pdev, 0);
info->fix.mmio_len = pci_resource_len(dev->pdev, 0);
diff --git a/drivers/gpu/drm/gma500/framebuffer.h
b/drivers/gpu/drm/gma500/framebuffer.h
index 23dc3c5f8f0d..e8e6357f033b 100644
--- a/drivers/gpu/drm/gma500/framebuffer.h
+++ b/drivers/gpu/drm/gma500/framebuffer.h
@@ -34,7 +34,7 @@ struct psb_framebuffer {
};
struct psb_fbdev {
- struct drm_fb_helper psb_fb_helper;
+ struct drm_fb_helper psb_fb_helper; /* must be first */
struct psb_framebuffer pfb;
};
--
2.20.1
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[Intel-gfx] [PATCH 20/26] drm/radeon: Use drm_fb_helper_fill_info
This should not result in any changes.
Signed-off-by: Daniel Vetter
Cc: Alex Deucher
Cc: "Christian König"
Cc: "David (ChunMing) Zhou"
Cc: amd-...@lists.freedesktop.org
---
drivers/gpu/drm/radeon/radeon_fb.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c
b/drivers/gpu/drm/radeon/radeon_fb.c
index d50bff20f7de..31523a02039d 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -42,7 +42,7 @@
* the helper contains a pointer to radeon framebuffer baseclass.
*/
struct radeon_fbdev {
- struct drm_fb_helper helper;
+ struct drm_fb_helper helper; /* must be first */
struct drm_framebuffer fb;
struct radeon_device *rdev;
};
@@ -247,8 +247,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
/* radeon resume is fragile and needs a vt switch to help it along */
info->skip_vt_switch = false;
- info->par = rfbdev;
-
ret = radeon_framebuffer_init(rdev->ddev, >fb, _cmd, gobj);
if (ret) {
DRM_ERROR("failed to initialize framebuffer %d\n", ret);
@@ -262,10 +260,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
- strcpy(info->fix.id, "radeondrmfb");
-
- drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
-
info->fbops = _ops;
tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
@@ -274,7 +268,7 @@ static int radeonfb_create(struct drm_fb_helper *helper,
info->screen_base = rbo->kptr;
info->screen_size = radeon_bo_size(rbo);
- drm_fb_helper_fill_var(info, >helper, sizes->fb_width,
sizes->fb_height);
+ drm_fb_helper_fill_info(info, >helper);
/* setup aperture base/size for vesafb takeover */
info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
--
2.20.1
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[Intel-gfx] [PATCH 18/26] drm/omap: Use drm_fb_helper_fill_info
This changes the fb name from "omapdrm" to "omapdrmfb". Signed-off-by: Daniel Vetter Cc: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_fbdev.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/omap_fbdev.c b/drivers/gpu/drm/omapdrm/omap_fbdev.c index 851c59f07eb1..16d8d6217f72 100644 --- a/drivers/gpu/drm/omapdrm/omap_fbdev.c +++ b/drivers/gpu/drm/omapdrm/omap_fbdev.c @@ -183,13 +183,9 @@ static int omap_fbdev_create(struct drm_fb_helper *helper, fbdev->fb = fb; helper->fb = fb; - fbi->par = helper; fbi->fbops = _fb_ops; - strcpy(fbi->fix.id, MODULE_NAME); - - drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->format->depth); - drm_fb_helper_fill_var(fbi, helper, sizes->fb_width, sizes->fb_height); + drm_fb_helper_fill_info(fbi, helper); dev->mode_config.fb_base = dma_addr; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/26] drm/hibmc: Use drm_fb_helper_fill_info
Should not result in any changes.
Signed-off-by: Daniel Vetter
Cc: Alex Deucher
Cc: Junwei Zhang
Cc: Xinliang Liu
Cc: "Christian König"
Cc: Ajit Negi
Cc: Souptick Joarder
Cc: Daniel Vetter
Cc: John Garry
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 2 +-
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c | 9 +
2 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h
b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h
index 3c168ae77b0c..0a381c22de26 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h
@@ -31,7 +31,7 @@ struct hibmc_framebuffer {
};
struct hibmc_fbdev {
- struct drm_fb_helper helper;
+ struct drm_fb_helper helper; /* must be first */
struct hibmc_framebuffer *fb;
int size;
};
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c
b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c
index de9d7cc97e44..620fca7e2cdc 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c
@@ -116,8 +116,6 @@ static int hibmc_drm_fb_create(struct drm_fb_helper *helper,
goto out_release_fbi;
}
- info->par = hi_fbdev;
-
hi_fbdev->fb = hibmc_framebuffer_init(priv->dev, _cmd, gobj);
if (IS_ERR(hi_fbdev->fb)) {
ret = PTR_ERR(hi_fbdev->fb);
@@ -129,14 +127,9 @@ static int hibmc_drm_fb_create(struct drm_fb_helper
*helper,
priv->fbdev->size = size;
hi_fbdev->helper.fb = _fbdev->fb->fb;
- strcpy(info->fix.id, "hibmcdrmfb");
-
info->fbops = _drm_fb_ops;
- drm_fb_helper_fill_fix(info, hi_fbdev->fb->fb.pitches[0],
- hi_fbdev->fb->fb.format->depth);
- drm_fb_helper_fill_var(info, >fbdev->helper, sizes->fb_width,
- sizes->fb_height);
+ drm_fb_helper_fill_info(info, >fbdev->helper);
info->screen_base = bo->kmap.virtual;
info->screen_size = size;
--
2.20.1
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[Intel-gfx] [PATCH 09/26] drm/ast: Use drm_fb_helper_fill_info
Should not result in any changes.
Signed-off-by: Daniel Vetter
Cc: Dave Airlie
Cc: Junwei Zhang
Cc: Alex Deucher
Cc: "Christian König"
Cc: Daniel Vetter
Cc: Sean Paul
Cc: YueHaibing
Cc: Sam Bobroff
---
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_fb.c | 7 +--
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
index bfc65040dfcb..ffce4608e0c5 100644
--- a/drivers/gpu/drm/ast/ast_drv.h
+++ b/drivers/gpu/drm/ast/ast_drv.h
@@ -259,7 +259,7 @@ struct ast_framebuffer {
};
struct ast_fbdev {
- struct drm_fb_helper helper;
+ struct drm_fb_helper helper; /* must be first */
struct ast_framebuffer afb;
void *sysram;
int size;
diff --git a/drivers/gpu/drm/ast/ast_fb.c b/drivers/gpu/drm/ast/ast_fb.c
index 2c9f8dd9733a..c3d00be69749 100644
--- a/drivers/gpu/drm/ast/ast_fb.c
+++ b/drivers/gpu/drm/ast/ast_fb.c
@@ -217,8 +217,6 @@ static int astfb_create(struct drm_fb_helper *helper,
ret = PTR_ERR(info);
goto out;
}
- info->par = afbdev;
-
ret = ast_framebuffer_init(dev, >afb, _cmd, gobj);
if (ret)
goto out;
@@ -229,15 +227,12 @@ static int astfb_create(struct drm_fb_helper *helper,
fb = >afb.base;
afbdev->helper.fb = fb;
- strcpy(info->fix.id, "astdrmfb");
-
info->fbops = _ops;
info->apertures->ranges[0].base = pci_resource_start(dev->pdev, 0);
info->apertures->ranges[0].size = pci_resource_len(dev->pdev, 0);
- drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
- drm_fb_helper_fill_var(info, >helper, sizes->fb_width,
sizes->fb_height);
+ drm_fb_helper_fill_info(info, >helper);
info->screen_base = sysram;
info->screen_size = size;
--
2.20.1
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[Intel-gfx] [PATCH 10/26] drm/cirrus: Use drm_fb_helper_fill_info
Should not result in any changes.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/cirrus/cirrus_drv.h | 2 +-
drivers/gpu/drm/cirrus/cirrus_fbdev.c | 8 +---
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.h
b/drivers/gpu/drm/cirrus/cirrus_drv.h
index f2b2e0d169fa..915709739257 100644
--- a/drivers/gpu/drm/cirrus/cirrus_drv.h
+++ b/drivers/gpu/drm/cirrus/cirrus_drv.h
@@ -143,7 +143,7 @@ struct cirrus_device {
struct cirrus_fbdev {
- struct drm_fb_helper helper;
+ struct drm_fb_helper helper; /* must be first */
struct drm_framebuffer *gfb;
void *sysram;
int size;
diff --git a/drivers/gpu/drm/cirrus/cirrus_fbdev.c
b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
index 39df62acac69..a2e69c1df53e 100644
--- a/drivers/gpu/drm/cirrus/cirrus_fbdev.c
+++ b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
@@ -195,8 +195,6 @@ static int cirrusfb_create(struct drm_fb_helper *helper,
goto err_vfree;
}
- info->par = gfbdev;
-
fb = kzalloc(sizeof(*fb), GFP_KERNEL);
if (!fb) {
ret = -ENOMEM;
@@ -214,13 +212,9 @@ static int cirrusfb_create(struct drm_fb_helper *helper,
/* setup helper */
gfbdev->helper.fb = fb;
- strcpy(info->fix.id, "cirrusdrmfb");
-
info->fbops = _ops;
- drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
- drm_fb_helper_fill_var(info, >helper, sizes->fb_width,
- sizes->fb_height);
+ drm_fb_helper_fill_info(info, >helper);
/* setup aperture base/size for vesafb takeover */
info->apertures->ranges[0].base = cdev->dev->mode_config.fb_base;
--
2.20.1
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[Intel-gfx] [PATCH 06/26] drm/fb_helper: set info->par in fill_info()
The fbdev emulation helpers pretty much assume that this is set. Let's do it for everyone. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_fb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 20969c05a9e3..cbe7fda3f8af 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -2126,6 +2126,7 @@ void drm_fb_helper_fill_info(struct fb_info *info, drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); drm_fb_helper_fill_var(info, fb_helper, fb->width, fb->height); + info->par = fb_helper; snprintf(info->fix.id, sizeof(info->fix.id), "%sdrmfb", fb_helper->dev->driver->name); @@ -3177,7 +3178,6 @@ int drm_fb_helper_generic_probe(struct drm_fb_helper *fb_helper, if (IS_ERR(fbi)) return PTR_ERR(fbi); - fbi->par = fb_helper; fbi->fbops = _fbdev_fb_ops; fbi->screen_size = fb->height * fb->pitches[0]; fbi->fix.smem_len = fbi->screen_size; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/26] drm/armada: Use drm_fb_helper_fill_info
Only changes the name of the fb from "armada-drmfb" to armadafb.
Signed-off-by: Daniel Vetter
Cc: Russell King
---
drivers/gpu/drm/armada/armada_fbdev.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/armada/armada_fbdev.c
b/drivers/gpu/drm/armada/armada_fbdev.c
index 8d23700848df..73d1dc53c4f4 100644
--- a/drivers/gpu/drm/armada/armada_fbdev.c
+++ b/drivers/gpu/drm/armada/armada_fbdev.c
@@ -78,8 +78,6 @@ static int armada_fbdev_create(struct drm_fb_helper *fbh,
goto err_fballoc;
}
- strlcpy(info->fix.id, "armada-drmfb", sizeof(info->fix.id));
- info->par = fbh;
info->fbops = _fb_ops;
info->fix.smem_start = obj->phys_addr;
info->fix.smem_len = obj->obj.size;
@@ -87,9 +85,7 @@ static int armada_fbdev_create(struct drm_fb_helper *fbh,
info->screen_base = ptr;
fbh->fb = >fb;
- drm_fb_helper_fill_fix(info, dfb->fb.pitches[0],
- dfb->fb.format->depth);
- drm_fb_helper_fill_var(info, fbh, sizes->fb_width, sizes->fb_height);
+ drm_fb_helper_fill_info(info, fbh);
DRM_DEBUG_KMS("allocated %dx%d %dbpp fb: 0x%08llx\n",
dfb->fb.width, dfb->fb.height, dfb->fb.format->cpp[0] * 8,
--
2.20.1
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[Intel-gfx] [PATCH 04/26] drm/fb-helper: Add fill_info() functions
The fbdev split between fix and var information is kinda
pointless for drm drivers since everything is fixed: The fbdev
emulation doesn't support changing modes at all.
Create a new simplified helper and use it in the generic fbdev
helper code. Follow-up patches will beef it up more and roll
it out to all drivers.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_fb_helper.c | 27 +--
include/drm/drm_fb_helper.h | 1 +
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 5eaccd202f4f..34c4ed378796 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2105,6 +2105,30 @@ void drm_fb_helper_fill_var(struct fb_info *info, struct
drm_fb_helper *fb_helpe
}
EXPORT_SYMBOL(drm_fb_helper_fill_var);
+/**
+ * drm_fb_helper_fill_info - initializes fbdev information
+ * @info: fbdev instance to set up
+ * @fb_helper: fb helper instance to use as template
+ *
+ *
+ * Sets up the variable and fixed fbdev metainformation from the given fb
helper
+ * instance and the drm framebuffer allocated in _fb_helper.fb.
+ *
+ * Drivers should call this (or their equivalent setup code) from their
+ * _fb_helper_funcs.fb_probe callback after having allocated the fbdev
+ * backing storage framebuffer.
+ */
+void drm_fb_helper_fill_info(struct fb_info *info,
+struct drm_fb_helper *fb_helper)
+{
+ struct drm_framebuffer *fb = fb_helper->fb;
+
+ drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
+ drm_fb_helper_fill_var(info, fb_helper, fb->width, fb->height);
+
+}
+EXPORT_SYMBOL(drm_fb_helper_fill_info);
+
static int drm_fb_helper_probe_connector_modes(struct drm_fb_helper *fb_helper,
uint32_t maxX,
uint32_t maxY)
@@ -3163,8 +3187,7 @@ int drm_fb_helper_generic_probe(struct drm_fb_helper
*fb_helper,
#endif
strcpy(fbi->fix.id, "DRM emulated");
- drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->format->depth);
- drm_fb_helper_fill_var(fbi, fb_helper, sizes->fb_width,
sizes->fb_height);
+ drm_fb_helper_fill_info(fbi, fb_helper);
if (fb->funcs->dirty) {
struct fb_ops *fbops;
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index bb9acea61369..e8d92724f472 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -292,6 +292,7 @@ void drm_fb_helper_fill_var(struct fb_info *info, struct
drm_fb_helper *fb_helpe
uint32_t fb_width, uint32_t fb_height);
void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,
uint32_t depth);
+void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper
*fb_helper);
void drm_fb_helper_unlink_fbi(struct drm_fb_helper *fb_helper);
--
2.20.1
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