[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cfl: Adding another PCI Device ID. (rev2)
== Series Details ==
Series: drm/i915/cfl: Adding another PCI Device ID. (rev2)
URL : https://patchwork.freedesktop.org/series/56075/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5526_full -> Patchwork_12121_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12121_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-apl: NOTRUN -> FAIL [fdo#103158] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145]
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-glk: PASS -> FAIL [fdo#103232] +3
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_flip@flip-vs-absolute-wf_vblank:
- shard-hsw: PASS -> DMESG-FAIL [fdo#102614]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: PASS -> FAIL [fdo#103167] +4
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-apl: NOTRUN -> FAIL [fdo#103166] +2
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> FAIL [fdo#100047]
Possible fixes
* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
- shard-glk: FAIL [fdo#103232] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard-glk: FAIL [fdo#103166] -> PASS +3
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: {SKIP} [fdo#109271] -> PASS
Warnings
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
- shard-apl: DMESG-FAIL [fdo#103558] / [fdo#105602] / [fdo#108145]
-> FAIL [fdo#108145]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106510]: https://bugs.freedesktop.org/show_bug.cgi?id=106510
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5526 -> Patchwork_12121
CI_DRM_5526: 482f9674140cbe8fddb18714bb95028cd9bfc1d1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4803: 973367176b61e81b5ca811620adb0467f6570aec @
git://anongit.freedesktop.org/xor
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cfl: Adding another PCI Device ID. (rev2)
== Series Details ==
Series: drm/i915/cfl: Adding another PCI Device ID. (rev2)
URL : https://patchwork.freedesktop.org/series/56075/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5526 -> Patchwork_12121
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56075/revisions/2/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12121:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-y}: NOTRUN -> {SKIP} +1
Known issues
Here are the changes found in Patchwork_12121 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182] +1
* igt@pm_rpm@basic-rte:
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
Possible fixes
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109528]: https://bugs.freedesktop.org/show_bug.cgi?id=109528
[fdo#109530]: https://bugs.freedesktop.org/show_bug.cgi?id=109530
Participating hosts (48 -> 45)
--
Additional (2): fi-icl-y fi-ivb-3520m
Missing(5): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-byt-squawks
fi-bsw-cyan
Build changes
-
* Linux: CI_DRM_5526 -> Patchwork_12121
CI_DRM_5526: 482f9674140cbe8fddb18714bb95028cd9bfc1d1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4803: 973367176b61e81b5ca811620adb0467f6570aec @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12121: d78761758c424a6340bdbf94eb12201623e4a8b4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d78761758c42 drm/i915/cfl: Adding another PCI Device ID.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12121/
___
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[Intel-gfx] [PATCH v3 0/4] drm/dp_mst: Fix regressions from new atomic VCPI helpers
This fixes the extra issues I discovered upstream after the introduction of my rework of the atomic VCPI helpers that occur during suspend/resume. This time around, we use a slightly different but much less complicated approach for fixing said issues. Cc: Daniel Vetter Lyude Paul (4): drm/dp_mst: Fix unbalanced malloc ref in drm_dp_mst_deallocate_vcpi() drm/dp_mst: Remove port validation in drm_dp_atomic_find_vcpi_slots() drm/atomic: Add drm_atomic_state->duplicated drm/nouveau: Move PBN and VCPI allocation into nv50_head_atom drivers/gpu/drm/drm_atomic_helper.c | 10 +++- drivers/gpu/drm/drm_dp_mst_topology.c | 32 + drivers/gpu/drm/i915/intel_dp_mst.c | 17 + drivers/gpu/drm/nouveau/dispnv50/atom.h | 6 + drivers/gpu/drm/nouveau/dispnv50/disp.c | 31 ++-- drivers/gpu/drm/nouveau/dispnv50/head.c | 1 + include/drm/drm_atomic.h| 9 +++ 7 files changed, 66 insertions(+), 40 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/4] drm/dp_mst: Remove port validation in drm_dp_atomic_find_vcpi_slots()
Since we now have an easy way of refcounting drm_dp_mst_port structs and
safely accessing their contents, there isn't any good reason to keep
validating ports here. It doesn't prevent us from performing modesets on
branch devices that have been removed either, and we already disallow
enabling new displays on unregistered connectors in
update_connector_routing() in drm_atomic_check_modeset(). All it does is
cause us to have to make weird special exceptions in our atomic
modesetting code. So, get rid of it entirely.
Signed-off-by: Lyude Paul
Fixes: eceae1472467 ("drm/dp_mst: Start tracking per-port VCPI allocations")
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_dp_mst_topology.c | 12 ++--
drivers/gpu/drm/i915/intel_dp_mst.c | 17 ++---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
3 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index abb0ea8ba9d9..4325e1518286 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3117,10 +3117,6 @@ int drm_dp_atomic_find_vcpi_slots(struct
drm_atomic_state *state,
if (IS_ERR(topology_state))
return PTR_ERR(topology_state);
- port = drm_dp_mst_topology_get_port_validated(mgr, port);
- if (port == NULL)
- return -EINVAL;
-
/* Find the current allocation for this port, if any */
list_for_each_entry(pos, &topology_state->vcpis, next) {
if (pos->port == port) {
@@ -3153,10 +3149,8 @@ int drm_dp_atomic_find_vcpi_slots(struct
drm_atomic_state *state,
/* Add the new allocation to the state */
if (!vcpi) {
vcpi = kzalloc(sizeof(*vcpi), GFP_KERNEL);
- if (!vcpi) {
- ret = -ENOMEM;
- goto out;
- }
+ if (!vcpi)
+ return -ENOMEM;
drm_dp_mst_get_port_malloc(port);
vcpi->port = port;
@@ -3165,8 +3159,6 @@ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state
*state,
vcpi->vcpi = req_slots;
ret = req_slots;
-out:
- drm_dp_mst_topology_put_port(port);
return ret;
}
EXPORT_SYMBOL(drm_dp_atomic_find_vcpi_slots);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index cdb83d294cdd..fb67cd931117 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -80,17 +80,12 @@ static int intel_dp_mst_compute_config(struct intel_encoder
*encoder,
mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);
pipe_config->pbn = mst_pbn;
- /* Zombie connectors can't have VCPI slots */
- if (!drm_connector_is_unregistered(connector)) {
- slots = drm_dp_atomic_find_vcpi_slots(state,
- &intel_dp->mst_mgr,
- port,
- mst_pbn);
- if (slots < 0) {
- DRM_DEBUG_KMS("failed finding vcpi slots:%d\n",
- slots);
- return slots;
- }
+ slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, port,
+ mst_pbn);
+ if (slots < 0) {
+ DRM_DEBUG_KMS("failed finding vcpi slots:%d\n",
+ slots);
+ return slots;
}
intel_link_compute_m_n(bpp, lane_count,
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 2e8a5fd9b262..60d858c2f2ce 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -771,8 +771,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock,
bpp);
- if (drm_atomic_crtc_needs_modeset(crtc_state) &&
- !drm_connector_is_unregistered(connector)) {
+ if (drm_atomic_crtc_needs_modeset(crtc_state)) {
slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
mstc->port, mstc->pbn);
if (slots < 0)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cfl: Adding another PCI Device ID.
On Fri, 2019-02-01 at 15:50 -0800, Rodrigo Vivi wrote:
> While cross checking PCI IDs from Intel Media SDK
> and kernel Dmitry noticed this gap. So we checked the
> spec and this new ID had been recently added.
>
> v2: Adding new H_GT1 entry to i915_pci.c (Jose)
>
Reviewed-by: José Roberto de Souza
> Reported-by: Dmitry Rogozhkin
> Cc: Dmitry Rogozhkin
> Cc: José Roberto de Souza
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h | 4
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index 17f5a605b0b3..5d05572c9ff4 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -713,6 +713,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
> INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
> INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
> + INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
> INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
> INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
> INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index df72be7e8b88..d2fad7b0fcf6 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -394,6 +394,9 @@
> INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
>
> /* CFL H */
> +#define INTEL_CFL_H_GT1_IDS(info) \
> + INTEL_VGA_DEVICE(0x3E9C, info)
> +
> #define INTEL_CFL_H_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
> INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
> @@ -426,6 +429,7 @@
> #define INTEL_CFL_IDS(info) \
> INTEL_CFL_S_GT1_IDS(info), \
> INTEL_CFL_S_GT2_IDS(info), \
> + INTEL_CFL_H_GT1_IDS(info), \
> INTEL_CFL_H_GT2_IDS(info), \
> INTEL_CFL_U_GT2_IDS(info), \
> INTEL_CFL_U_GT3_IDS(info), \
signature.asc
Description: This is a digitally signed message part
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/cfl: Adding another PCI Device ID. (rev2)
== Series Details == Series: drm/i915/cfl: Adding another PCI Device ID. (rev2) URL : https://patchwork.freedesktop.org/series/56075/ State : warning == Summary == $ dim checkpatch origin/drm-tip d78761758c42 drm/i915/cfl: Adding another PCI Device ID. -:15: WARNING:BAD_SIGN_OFF: email address 'Dmitry Rogozhkin' might be better as 'Dmitry Rogozhkin ' #15: Reported-by: Dmitry Rogozhkin -:16: WARNING:BAD_SIGN_OFF: email address 'Dmitry Rogozhkin' might be better as 'Dmitry Rogozhkin ' #16: Cc: Dmitry Rogozhkin total: 0 errors, 2 warnings, 0 checks, 23 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/cfl: Adding another PCI Device ID.
While cross checking PCI IDs from Intel Media SDK
and kernel Dmitry noticed this gap. So we checked the
spec and this new ID had been recently added.
v2: Adding new H_GT1 entry to i915_pci.c (Jose)
Reported-by: Dmitry Rogozhkin
Cc: Dmitry Rogozhkin
Cc: José Roberto de Souza
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 17f5a605b0b3..5d05572c9ff4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -713,6 +713,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index df72be7e8b88..d2fad7b0fcf6 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -394,6 +394,9 @@
INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
/* CFL H */
+#define INTEL_CFL_H_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E9C, info)
+
#define INTEL_CFL_H_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
@@ -426,6 +429,7 @@
#define INTEL_CFL_IDS(info) \
INTEL_CFL_S_GT1_IDS(info), \
INTEL_CFL_S_GT2_IDS(info), \
+ INTEL_CFL_H_GT1_IDS(info), \
INTEL_CFL_H_GT2_IDS(info), \
INTEL_CFL_U_GT2_IDS(info), \
INTEL_CFL_U_GT3_IDS(info), \
--
2.20.1
___
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Re: [Intel-gfx] [PATCH v2 RESEND 2/2] drm/i915/icl: Implement half float formats
Ville Syrjälä wrote:
> > @@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
> >DRM_FORMAT_NV12,
> > };
> >
> > +static const uint32_t icl_hdr_plane_formats[] = {
>
> Please switch to u32 & co. We recently had a mass conversion in the
> driver.
Will do. Looks like the CI caught that too.
> > static const u64 skl_plane_format_modifiers_noccs[] = {
> >I915_FORMAT_MOD_Yf_TILED,
> >I915_FORMAT_MOD_Y_TILED,
> > @@ -1917,6 +1958,10 @@ static bool skl_plane_format_mod_supported(struct
> > drm_plane *_plane,
> >return true;
> >/* fall through */
> >case DRM_FORMAT_C8:
> > + case DRM_FORMAT_XBGR16161616F:
> > + case DRM_FORMAT_ABGR16161616F:
> > + case DRM_FORMAT_XRGB16161616F:
> > + case DRM_FORMAT_ARGB16161616F:
> >if (modifier == DRM_FORMAT_MOD_LINEAR ||
> >modifier == I915_FORMAT_MOD_X_TILED ||
> >modifier == I915_FORMAT_MOD_Y_TILED)
> > @@ -2053,11 +2098,21 @@ skl_universal_plane_create(struct drm_i915_private
> > *dev_priv,
> >plane->update_slave = icl_update_slave;
> >
> >if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
> > - formats = skl_planar_formats;
> > - num_formats = ARRAY_SIZE(skl_planar_formats);
> > + if (INTEL_GEN(dev_priv) > 10 && plane_id < PLANE_SPRITE2) {
>
> is_hdr_plane() is around now, please use it.
I don't think I can use icl_is_hdr_plane here without some refactoring. It
requires the plane->base to be initialized through drm_universal_plane_init,
which depends on formats/num_formats pointers to be already set.
Thanks,
Kevin
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Revoke mmaps and prevent access to fence registers across reset
Hi Chris,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20190131]
[cannot apply to v5.0-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Revoke-mmaps-and-prevent-access-to-fence-registers-across-reset/20190201-043323
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/i915_reset.c:1304:5: sparse: warning: context imbalance
>> in 'i915_reset_lock' - different lock contexts for basic block
>> drivers/gpu/drm/i915/i915_reset.c:1325:6: sparse: warning: context imbalance
>> in 'i915_reset_unlock' - unexpected unlock
vim +/i915_reset_lock +1304 drivers/gpu/drm/i915/i915_reset.c
1303
> 1304 int i915_reset_lock(struct drm_i915_private *i915)
1305 {
1306 int srcu;
1307
1308 rcu_read_lock();
1309 while (test_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags)) {
1310 rcu_read_unlock();
1311
1312 if
(wait_event_interruptible(i915->gpu_error.reset_queue,
1313
!test_bit(I915_RESET_BACKOFF,
1314
&i915->gpu_error.flags)))
1315 return -EINTR;
1316
1317 rcu_read_lock();
1318 }
1319 srcu = srcu_read_lock(&i915->gpu_error.srcu);
1320 rcu_read_unlock();
1321
1322 return srcu;
1323 }
1324
> 1325 void i915_reset_unlock(struct drm_i915_private *i915, int tag)
1326 {
1327 srcu_read_unlock(&i915->gpu_error.srcu, tag);
1328 }
1329
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
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Re: [Intel-gfx] [PATCH v2 RESEND 2/2] drm/i915/icl: Implement half float formats
On Fri, Feb 01, 2019 at 09:43:40AM -0800, Kevin Strasser wrote:
> 64 bpp half float formats are supported on hdr planes only and are subject
> to the following restrictions:
> * 90/270 rotation not supported
> * Yf Tiling not supported
> * Frame Buffer Compression not supported
> * Color Keying not supported
>
> v2:
> - Drop handling pixel normalize register
> - Don't use icl_is_hdr_plane too early
>
> Signed-off-by: Kevin Strasser
> Cc: Uma Shankar
> Cc: Shashank Sharma
> Cc: Ville Syrjälä
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: dri-de...@lists.freedesktop.org
> ---
> drivers/gpu/drm/i915/intel_display.c | 22
> drivers/gpu/drm/i915/intel_sprite.c | 67
>
> 2 files changed, 83 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a6d8985..f413ccd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2668,6 +2668,18 @@ int skl_format_to_fourcc(int format, bool rgb_order,
> bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_XRGB_16161616F:
> + if (rgb_order) {
> + if (alpha)
> + return DRM_FORMAT_ABGR16161616F;
> + else
> + return DRM_FORMAT_XBGR16161616F;
> + } else {
> + if (alpha)
> + return DRM_FORMAT_ARGB16161616F;
> + else
> + return DRM_FORMAT_XRGB16161616F;
> + }
> default:
> case PLANE_CTL_FORMAT_XRGB_:
> if (rgb_order) {
> @@ -3566,6 +3578,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> + return PLANE_CTL_FORMAT_XRGB_16161616F;
> default:
> MISSING_CASE(pixel_format);
> }
> @@ -5069,6 +5087,10 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
> 0x%x\n",
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index cd42e81..97f9d05 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1450,8 +1450,6 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> /*
>* 90/270 is not allowed with RGB64 16:16:16:16 and
>* Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
> - * TBD: Add RGB64 case once its added in supported format
> - * list.
>*/
> switch (fb->format->format) {
> case DRM_FORMAT_RGB565:
> @@ -1459,6 +1457,10 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> break;
> /* fall through */
> case DRM_FORMAT_C8:
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> DRM_DEBUG_KMS("Unsupported pixel format %s for
> 90/270!\n",
> drm_get_format_name(fb->format->format,
> &format_name));
> @@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
> DRM_FORMAT_NV12,
> };
>
> +static const uint32_t icl_hdr_plane_formats[] = {
Please switch to u32 & co. We recently had a mass conversion in the
driver.
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB,
> + DRM_FORMAT_XBGR,
> + DRM_FORMAT_ARGB,
> + DRM_FORMAT_ABGR,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
I just noticed that icl should also support alpha for 10bpc. But that's
not relevant for this patch.
> + DRM_FORMAT_XRGB16161616F,
> + DRM_FORMAT_XBGR16161616F,
> + DRM_FORMAT_ARGB16161616F,
> + DRM_FORMAT_ABGR16161616F,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_F
Re: [Intel-gfx] [PATCH v2 RESEND 1/2] drm/fourcc: Add 64 bpp half float formats
On Fri, Feb 01, 2019 at 09:43:39AM -0800, Kevin Strasser wrote:
> Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
> formatted in IEEE-754 half-precision float (binary16) 1:5:10
> MSb-sign:exponent:fraction form.
>
> This patch attempts to address the feedback provided when 2 of these
> formats were previosly proposed:
> https://patchwork.kernel.org/patch/10072545/
>
> v2:
> - Fixed cpp (Ville)
> - Added detail pixel formatting (Ville)
> - Ordered formats in header (Ville)
>
> Signed-off-by: Kevin Strasser
> Cc: Tina Zhang
> Cc: Uma Shankar
> Cc: Shashank Sharma
> Cc: Ville Syrjälä
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: dri-de...@lists.freedesktop.org
This lgtm:
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_fourcc.c | 4
> include/uapi/drm/drm_fourcc.h | 11 +++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index d90ee03..c866452 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32
> format)
> { .format = DRM_FORMAT_ABGR,.depth = 32,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true
> },
> { .format = DRM_FORMAT_RGBA,.depth = 32,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true
> },
> { .format = DRM_FORMAT_BGRA,.depth = 32,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true
> },
> + { .format = DRM_FORMAT_XRGB16161616F, .depth = 48,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> + { .format = DRM_FORMAT_XBGR16161616F, .depth = 48,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> + { .format = DRM_FORMAT_ARGB16161616F, .depth = 64,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true
> },
> + { .format = DRM_FORMAT_ABGR16161616F, .depth = 64,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true
> },
> { .format = DRM_FORMAT_RGB888_A8, .depth = 32,
> .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true
> },
> { .format = DRM_FORMAT_BGR888_A8, .depth = 32,
> .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true
> },
> { .format = DRM_FORMAT_XRGB_A8, .depth = 32,
> .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true
> },
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 91d08a2..c516b40 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -144,6 +144,17 @@ extern "C" {
> #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /*
> [31:0] R:G:B:A 10:10:10:2 little endian */
> #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /*
> [31:0] B:G:R:A 10:10:10:2 little endian */
>
> +/*
> + * Floating point 64bpp RGB
> + * IEEE 754-2008 binary16 half-precision float
> + * [15:0] sign:exponent:mantissa 1:5:10
> + */
> +#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0]
> x:R:G:B 16:16:16:16 little endian */
> +#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0]
> x:B:G:R 16:16:16:16 little endian */
> +
> +#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0]
> A:R:G:B 16:16:16:16 little endian */
> +#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0]
> A:B:G:R 16:16:16:16 little endian */
> +
> /* packed YCbCr */
> #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /*
> [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
> #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /*
> [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
> --
> 2.7.4
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.IGT: success for Support 64 bpp half float formats (rev3)
== Series Details ==
Series: Support 64 bpp half float formats (rev3)
URL : https://patchwork.freedesktop.org/series/53212/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5526_full -> Patchwork_12120_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12120_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-apl: NOTRUN -> FAIL [fdo#103158] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145]
* igt@kms_color@pipe-a-legacy-gamma:
- shard-apl: NOTRUN -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-glk: PASS -> FAIL [fdo#103232] +4
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: PASS -> DMESG-FAIL [fdo#103232] / [fdo#103558] /
[fdo#105602]
* igt@kms_flip@dpms-vs-vblank-race:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-apl: NOTRUN -> FAIL [fdo#103166] +2
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-a-query-forked-busy-hang:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +7
* igt@kms_vblank@pipe-b-query-forked-hang:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
Possible fixes
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +2
- shard-glk: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: FAIL [fdo#105454] / [fdo#106509] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: {SKIP} [fdo#109271] -> PASS
Warnings
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
- shard-apl: DMESG-FAIL [fdo#103558] / [fdo#105602] / [fdo#108145]
-> FAIL [fdo#108145]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#106510]: https://bugs.freedesktop.org/show_bug.cgi?id=106510
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hos
Re: [Intel-gfx] [v10 2/3] drm: Add DP colorspace property
On Wed, Jan 30, 2019 at 06:24:25PM +0530, Uma Shankar wrote:
> This patch adds a DP colorspace property, enabling
> userspace to switch to various supported colorspaces.
> This will help enable BT2020 along with other colorspaces.
>
> v2: Addressed Maarten and Ville's review comments. Enhanced
> the colorspace enum to incorporate both HDMI and DP supported
> colorspaces. Also, added a default option for colorspace.
>
> v3: Split the changes to have separate colorspace property for
> DP and HDMI.
>
> v4: Addressed Chris and Ville's review comments, and created a
> common colorspace property for DP and HDMI, filtered the list
> based on the colorspaces supported by the respective protocol
> standard.
>
> v5: Merged the DP handling along with platform colorspace
> handling as per Shashank's comments.
>
> v6: Reverted to old design of exposing all colorspaces to
> userspace as per Ville's review comment
>
> v7: Fixed sparse warnings, updated the RB from Maarten and Jani's ack.
>
> Signed-off-by: Uma Shankar
> Acked-by: Jani Nikula
> Reviewed-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/drm_connector.c | 31 +++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index ed10dd9..b331be8 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -850,6 +850,29 @@ int drm_display_info_set_bus_formats(struct
> drm_display_info *info,
> { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
> };
>
> +static const struct drm_prop_enum_list dp_colorspaces[] = {
> + /* For Default case, driver will set the colorspace */
> + { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
> + /* Standard Definition Colorimetry based on CEA 861 */
> + { DRM_MODE_COLORIMETRY_ITU_601, "ITU_601" },
> + { DRM_MODE_COLORIMETRY_ITU_709, "ITU_709" },
What's with the duplicated 601/709 values? I think in the HDMI verison
you had only these ones here. Maybe we want to actually state explicitly
that they are for YCbCr, if only to be consistent with the
BT2020 values.
> + /* Standard Definition Colorimetry based on IEC 61966-2-4 */
> + { DRM_MODE_COLORIMETRY_XV_YCC_601, "XV_YCC_601" },
> + /* High Definition Colorimetry based on IEC 61966-2-4 */
> + { DRM_MODE_COLORIMETRY_XV_YCC_709, "XV_YCC_709" },
> + /* Colorimetry based on IEC 61966-2-5 */
> + { DRM_MODE_COLORIMETRY_OPRGB, "opRGB" },
> + /* DP MSA Colorimetry */
> + { DRM_MODE_DP_COLORIMETRY_Y_CBCR_ITU_601, "YCBCR_ITU_601" },
> + { DRM_MODE_DP_COLORIMETRY_Y_CBCR_ITU_709, "YCBCR_ITU_709" },
> + { DRM_MODE_DP_COLORIMETRY_SRGB, "sRGB" },
> + { DRM_MODE_DP_COLORIMETRY_RGB_WIDE_GAMUT, "RGB Wide Gamut" },
> + { DRM_MODE_DP_COLORIMETRY_SCRGB, "scRGB" },
> + { DRM_MODE_DP_COLORIMETRY_DCI_P3, "DCI-P3" },
> + { DRM_MODE_DP_COLORIMETRY_CUSTOM_COLOR_PROFILE, "Custom Profile" },
I don't think we want this last one since we don't implement anything
that could transmit the custom profile.
The MSA bits are have "CEA RGB" which we probably want to keep hidden
since it seems to be just a poorly specced limited range vs. full range
knob, and we already have a mechanism for that. The Y-only and RAW I
guess we can skip. Not sure anyone would ever have use for those.
> +};
> +
> +
> /**
> * DOC: standard connector properties
> *
> @@ -1611,6 +1634,14 @@ int drm_mode_create_colorspace_property(struct
> drm_connector *connector)
> ARRAY_SIZE(hdmi_colorspaces));
> if (!prop)
> return -ENOMEM;
> + } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
> +connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
> {
> + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
> + "Colorspace", dp_colorspaces,
> + ARRAY_SIZE(dp_colorspaces));
> +
> + if (!prop)
> + return -ENOMEM;
> } else {
> DRM_DEBUG_KMS("Colorspace property not supported\n");
> return 0;
> --
> 1.9.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel
___
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Re: [Intel-gfx] [PATCH] drm/i915: Allow normal clients to always preempt idle priority clients
On 01/31/2019 05:42 PM, Chris Wilson wrote:
When first enabling preemption, we hesitated from making it a free-for-all
where every higher priority client would force a preempt-to-idle cycle
and take over from all lower priority clients. We hesitated because we
were uncertain just how well preemption would work in practice, whether
the preemption latency itself would detract from the latency gains for
higher priority tasks and whether it would work at all. Since
introducing preemption, we have been enabling it for more common tasks,
even giving normal clients a small preemptive boost when they first
start (to aide fairness and improve interactivity). Now lets take one
step further and give permission for all normal (priority:0) clients to
preempt any idle (priority:<0) task so that users running long compute
jobs do not overly impact other jobs (i.e. their desktop) and the system
remains responsive under such idle loads.
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between submission
ports")
References: b16c765122f9 ("drm/i915: Priority boost for new clients")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Cc: "Bloomfield, Jon"
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/intel_ringbuffer.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 34d0a148e664..983ad1e7914d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -592,7 +592,20 @@ intel_engine_has_preemption(const struct intel_engine_cs
*engine)
static inline bool __execlists_need_preempt(int prio, int last)
{
- return prio > max(0, last);
+ /*
+* Allow preemption of low -> normal -> high, but we do
+* not allow low priority tasks to preempt other low priority
+* tasks under the impression that latency for low priority
+* tasks does not matter (as much as background throughput),
+* so kiss.
+*
+* More naturally we would write
+* prio >= max(0, last);
+* except that we wish to prevent triggering preemption at the same
+* priority level: the task that is running should remain running
+* to preserve FIFO ordering of dependencies.
+*/
+ return prio > max(I915_PRIORITY_NORMAL - 1, last);
}
static inline void
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Re: [Intel-gfx] [v10 3/3] drm/i915: Attach colorspace property and enable modeset
On Wed, Jan 30, 2019 at 06:24:26PM +0530, Uma Shankar wrote:
> This patch attaches the colorspace connector property to the
> hdmi connector. Based on colorspace change, modeset will be
> triggered to switch to new colorspace.
>
> Based on colorspace property value create an infoframe
> with appropriate colorspace. This can be used to send an
> infoframe packet with proper colorspace value set which
> will help to enable wider color gamut like BT2020 on sink.
>
> This patch attaches and enables HDMI colorspace, DP will be
> taken care separately.
>
> v2: Merged the changes of creating infoframe as well to this
> patch as per Maarten's suggestion.
>
> v3: Addressed review comments from Shashank. Separated HDMI
> and DP colorspaces as suggested by Ville and Maarten.
>
> v4: Addressed Chris and Ville's review comments, and created a
> common colorspace property for DP and HDMI, filtered the list
> based on the colorspaces supported by the respective protocol
> standard. Handle the default case properly.
>
> v5: Merged the DP handling along with platform colorspace
> handling as per Shashank's comments.
>
> v6: Reverted to old design of exposing all colorspaces to
> userspace as per Ville's review comment
>
> v7: Fixed a checkpatch complaint, Addressed Maarten' review
> comment, updated the RB from Maarten and Jani's ack.
>
> Signed-off-by: Uma Shankar
> Acked-by: Jani Nikula
> Reviewed-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_atomic.c| 1 +
> drivers/gpu/drm/i915/intel_connector.c | 8
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_hdmi.c | 25 +
> 4 files changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> b/drivers/gpu/drm/i915/intel_atomic.c
> index 16263ad..a4bb906 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -124,6 +124,7 @@ int intel_digital_connector_atomic_check(struct
> drm_connector *conn,
>*/
> if (new_conn_state->force_audio != old_conn_state->force_audio ||
> new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
> + new_conn_state->base.colorspace != old_conn_state->base.colorspace
> ||
> new_conn_state->base.picture_aspect_ratio !=
> old_conn_state->base.picture_aspect_ratio ||
> new_conn_state->base.content_type !=
> old_conn_state->base.content_type ||
> new_conn_state->base.scaling_mode !=
> old_conn_state->base.scaling_mode)
> diff --git a/drivers/gpu/drm/i915/intel_connector.c
> b/drivers/gpu/drm/i915/intel_connector.c
> index ee16758..8352d0b 100644
> --- a/drivers/gpu/drm/i915/intel_connector.c
> +++ b/drivers/gpu/drm/i915/intel_connector.c
> @@ -265,3 +265,11 @@ int intel_ddc_get_modes(struct drm_connector *connector,
> connector->dev->mode_config.aspect_ratio_property,
> DRM_MODE_PICTURE_ASPECT_NONE);
> }
> +
> +void
> +intel_attach_colorspace_property(struct drm_connector *connector)
> +{
> + if (!drm_mode_create_colorspace_property(connector))
> + drm_object_attach_property(&connector->base,
> +connector->colorspace_property, 0);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 85b913e..5178a9a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1783,6 +1783,7 @@ int intel_connector_update_modes(struct drm_connector
> *connector,
> void intel_attach_force_audio_property(struct drm_connector *connector);
> void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
> void intel_attach_aspect_ratio_property(struct drm_connector *connector);
> +void intel_attach_colorspace_property(struct drm_connector *connector);
>
> /* intel_csr.c */
> void intel_csr_ucode_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 97a98e1..5c5009d 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -498,6 +498,24 @@ static void intel_hdmi_set_avi_infoframe(struct
> intel_encoder *encoder,
> else
> frame.avi.colorspace = HDMI_COLORSPACE_RGB;
>
> + if (conn_state->colorspace == DRM_MODE_COLORIMETRY_DEFAULT) {
> + /* Set ITU 709 as default for HDMI */
> + frame.avi.colorimetry = DRM_MODE_COLORIMETRY_ITU_709;
Default should map to NONE.
> + } else if (conn_state->colorspace < DRM_MODE_COLORIMETRY_XV_YCC_601) {
> + frame.avi.colorimetry = conn_state->colorspace;
> + } else {
> + frame.avi.colorimetry = HDMI_COLORIMETRY_EXTENDED;
> + /*
> + * Starting from extended list where COLORIMETRY_XV_YCC_601
> + * is the first extended mode and its value is 0 as per HDMI
> + * specification.
>
Re: [Intel-gfx] [v10 1/3] drm: Add HDMI colorspace property
On Wed, Jan 30, 2019 at 06:24:24PM +0530, Uma Shankar wrote:
> Create a new connector property to program colorspace to sink
> devices. Modern sink devices support more than 1 type of
> colorspace like 601, 709, BT2020 etc. This helps to switch
> based on content type which is to be displayed. The decision
> lies with compositors as to in which scenarios, a particular
> colorspace will be picked.
>
> This will be helpful mostly to switch to higher gamut colorspaces
> like BT2020 when the media content is encoded as BT2020. Thereby
> giving a good visual experience to users.
>
> The expectation from userspace is that it should parse the EDID
> and get supported colorspaces. Use this property and switch to the
> one supported. Sink supported colorspaces should be retrieved by
> userspace from EDID and driver will not explicitly expose them.
>
> Basically the expectation from userspace is:
> - Set up CRTC DEGAMMA/CTM/GAMMA to convert to some sink
>colorspace
> - Set this new property to let the sink know what it
>converted the CRTC output to.
>
> v2: Addressed Maarten and Ville's review comments. Enhanced
> the colorspace enum to incorporate both HDMI and DP supported
> colorspaces. Also, added a default option for colorspace.
>
> v3: Removed Adobe references from enum definitions as per
> Ville, Hans Verkuil and Jonas Karlman suggestions. Changed
> Default to an unset state where driver will assign the colorspace
> is not chosen by user, suggested by Ville and Maarten. Addressed
> other misc review comments from Maarten. Split the changes to
> have separate colorspace property for DP and HDMI.
>
> v4: Addressed Chris and Ville's review comments, and created a
> common colorspace property for DP and HDMI, filtered the list
> based on the colorspaces supported by the respective protocol
> standard.
>
> v5: Made the property creation helper accept enum list based on
> platform capabilties as suggested by Shashank. Consolidated HDMI
> and DP property creation in the common helper.
>
> v6: Addressed Shashank's review comments.
>
> v7: Added defines instead of enum in uapi as per Brian Starkey's
> suggestion in order to go with string matching at userspace. Updated
> the commit message to add more details as well kernel docs.
>
> v8: Addressed Maarten's review comments.
>
> v9: Removed macro defines from uapi as per Brian Starkey and Daniel
> Stone's comments and moved to drm include file. Moved back to older
> design with exposing all HDMI colorspaces to userspace since infoframe
> capability is there even on legacy platforms, as per Ville's review
> comments.
>
> v10: Fixed sparse warnings, updated the RB from Maarten and Jani's ack.
>
> Signed-off-by: Uma Shankar
> Acked-by: Jani Nikula
> Reviewed-by: Shashank Sharma
> Reviewed-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 4 +++
> drivers/gpu/drm/drm_connector.c | 75
> +++
> include/drm/drm_connector.h | 46
> 3 files changed, 125 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 9a1f41a..9b5d44f 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -746,6 +746,8 @@ static int drm_atomic_connector_set_property(struct
> drm_connector *connector,
> return -EINVAL;
> }
> state->content_protection = val;
> + } else if (property == connector->colorspace_property) {
> + state->colorspace = val;
> } else if (property == config->writeback_fb_id_property) {
> struct drm_framebuffer *fb = drm_framebuffer_lookup(dev, NULL,
> val);
> int ret = drm_atomic_set_writeback_fb_for_connector(state, fb);
> @@ -814,6 +816,8 @@ static int drm_atomic_connector_set_property(struct
> drm_connector *connector,
> *val = state->picture_aspect_ratio;
> } else if (property == config->content_type_property) {
> *val = state->content_type;
> + } else if (property == connector->colorspace_property) {
> + *val = state->colorspace;
> } else if (property == connector->scaling_mode_property) {
> *val = state->scaling_mode;
> } else if (property == connector->content_protection_property) {
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 8475396..ed10dd9 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -826,6 +826,30 @@ int drm_display_info_set_bus_formats(struct
> drm_display_info *info,
> };
> DRM_ENUM_NAME_FN(drm_get_content_protection_name, drm_cp_enum_list)
>
> +static const struct drm_prop_enum_list hdmi_colorspaces[] = {
> + /* For Default case, driver will set the colorspace */
> + { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
> + /* Standard Definition Colorimetry based on CEA 861 */
> + { D
[Intel-gfx] ✓ Fi.CI.BAT: success for Support 64 bpp half float formats (rev3)
== Series Details ==
Series: Support 64 bpp half float formats (rev3)
URL : https://patchwork.freedesktop.org/series/53212/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5526 -> Patchwork_12120
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53212/revisions/3/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12120:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-y}: NOTRUN -> {SKIP} +1
Known issues
Here are the changes found in Patchwork_12120 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
Possible fixes
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109528]: https://bugs.freedesktop.org/show_bug.cgi?id=109528
[fdo#109530]: https://bugs.freedesktop.org/show_bug.cgi?id=109530
Participating hosts (48 -> 44)
--
Additional (2): fi-icl-y fi-ivb-3520m
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-skl-guc fi-byt-squawks
fi-bsw-cyan fi-snb-2600
Build changes
-
* Linux: CI_DRM_5526 -> Patchwork_12120
CI_DRM_5526: 482f9674140cbe8fddb18714bb95028cd9bfc1d1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4803: 973367176b61e81b5ca811620adb0467f6570aec @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12120: 076507575effcb745ac8e08f84601405fe1a2915 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
076507575eff drm/i915/icl: Implement half float formats
bb513dd0a6fe drm/fourcc: Add 64 bpp half float formats
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12120/
___
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Re: [Intel-gfx] [PATCH] drm/i915/cfl: Adding another PCI Device ID.
On Thu, 2019-01-31 at 21:38 -0800, Rodrigo Vivi wrote: > While cross checking PCI IDs from Intel Media SDK > and kernel Dmitry noticed this gap. So we checked the > spec and this new ID had been recently added. > > Reported-by: Dmitry Rogozhkin > Cc: Dmitry Rogozhkin > Cc: José Roberto de Souza > Signed-off-by: Rodrigo Vivi > --- > include/drm/i915_pciids.h | 4 > 1 file changed, 4 insertions(+) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index df72be7e8b88..d2fad7b0fcf6 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -394,6 +394,9 @@ > INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ > > /* CFL H */ > +#define INTEL_CFL_H_GT1_IDS(info) \ > + INTEL_VGA_DEVICE(0x3E9C, info) > + > #define INTEL_CFL_H_GT2_IDS(info) \ > INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ > INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ > @@ -426,6 +429,7 @@ > #define INTEL_CFL_IDS(info) \ > INTEL_CFL_S_GT1_IDS(info), \ > INTEL_CFL_S_GT2_IDS(info), \ > + INTEL_CFL_H_GT1_IDS(info), \ > INTEL_CFL_H_GT2_IDS(info), \ > INTEL_CFL_U_GT2_IDS(info), \ > INTEL_CFL_U_GT3_IDS(info), \ Missing add INTEL_CFL_H_GT1_IDS to pciidlist in i915_pci.c signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev3)
== Series Details ==
Series: Support 64 bpp half float formats (rev3)
URL : https://patchwork.freedesktop.org/series/53212/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bb513dd0a6fe drm/fourcc: Add 64 bpp half float formats
-:39: WARNING:LONG_LINE: line over 100 characters
#39: FILE: drivers/gpu/drm/drm_fourcc.c:201:
+ { .format = DRM_FORMAT_XRGB16161616F, .depth = 48,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
-:40: WARNING:LONG_LINE: line over 100 characters
#40: FILE: drivers/gpu/drm/drm_fourcc.c:202:
+ { .format = DRM_FORMAT_XBGR16161616F, .depth = 48,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
-:41: WARNING:LONG_LINE: line over 100 characters
#41: FILE: drivers/gpu/drm/drm_fourcc.c:203:
+ { .format = DRM_FORMAT_ARGB16161616F, .depth = 64,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
-:42: WARNING:LONG_LINE: line over 100 characters
#42: FILE: drivers/gpu/drm/drm_fourcc.c:204:
+ { .format = DRM_FORMAT_ABGR16161616F, .depth = 64,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
-:59: WARNING:LONG_LINE_COMMENT: line over 100 characters
#59: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0]
x:R:G:B 16:16:16:16 little endian */
-:60: WARNING:LONG_LINE_COMMENT: line over 100 characters
#60: FILE: include/uapi/drm/drm_fourcc.h:153:
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0]
x:B:G:R 16:16:16:16 little endian */
-:62: WARNING:LONG_LINE_COMMENT: line over 100 characters
#62: FILE: include/uapi/drm/drm_fourcc.h:155:
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0]
A:R:G:B 16:16:16:16 little endian */
-:63: WARNING:LONG_LINE_COMMENT: line over 100 characters
#63: FILE: include/uapi/drm/drm_fourcc.h:156:
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0]
A:B:G:R 16:16:16:16 little endian */
total: 0 errors, 8 warnings, 0 checks, 27 lines checked
076507575eff drm/i915/icl: Implement half float formats
-:103: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#103: FILE: drivers/gpu/drm/i915/intel_sprite.c:1779:
+static const uint32_t icl_hdr_plane_formats[] = {
-:122: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#122: FILE: drivers/gpu/drm/i915/intel_sprite.c:1798:
+static const uint32_t icl_hdr_planar_formats[] = {
total: 0 errors, 0 warnings, 2 checks, 138 lines checked
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Re: [Intel-gfx] [PATCH v4.1 0/3] CRTC background color
On Fri, Feb 01, 2019 at 06:13:48PM +0100, Daniel Vetter wrote: > On Wed, Jan 30, 2019 at 03:48:50PM -0800, Matt Roper wrote: > > On Wed, Jan 30, 2019 at 09:57:10PM +0100, Daniel Vetter wrote: > > > On Wed, Jan 30, 2019 at 10:56:26AM -0800, Matt Roper wrote: > > > > On Wed, Jan 30, 2019 at 10:51:19AM -0800, Matt Roper wrote: > > > > > Previous patch series was here: > > > > > > > > > > https://lists.freedesktop.org/archives/dri-devel/2018-December/201949.html > > > > > > > > > > I'm told the ChromeOS userspace code to make use of the background > > > > > color > > > > > has been reviewed and is ready for use: > > > > > * https://chromium-review.googlesource.com/c/chromium/src/+/1278858 > > > > > * https://chromium-review.googlesource.com/c/chromium/src/+/1278858 > > > > > > > > Woops, the second link here should have been to > > > > > > > > > > > > https://chromium-review.googlesource.com/c/chromiumos/platform/drm-tests/+/1241436 > > > > > > > > which I believe is some unit tests to go along with the main userspace > > > > code. > > > > > > Do we have this as igts too? > > > -Daniel > > > > Yeah, I posted it along with some of the earlier revisions of the > > series, but haven't reposted the latest copy lately. I'll check and see > > if it needs a rebase and then post it shortly. > > > > Unfortunately the IGT isn't as useful as I'd like it to be since the > > CRC's for a plane filled with a solid color never come up the same as a > > pure background color (at least on the APL platform I'm using). I can > > run the IGT in interactive mode and the colors seem identical to visual > > inspection, but the CRC values never agree, so I've disabled the CRC > > comparison in the test for now. I'm not sure if this is related to the > > other blending quirks of gen9; it will be interesting to see if the > > CRC's match on an Icelake or something. > > Please don't do that, we need to know when stuff doesn't work. Also, igt > (at least for more generic stuff like this) shouldn't be bent to exactly > match intel hw bugs. > > And yes if the blending is generally broken on gen9 then I'd be surprised > if they managed to not screw it up for the background color. Usually > backgroun color works as if it's a separate additional plane that you > blend the others with. > -Daniel +igt-dev list So looking at the bspec closer, it sounds like it might not actually be valid for us to take a DMUX (pipe) CRC of just the background color. The bspec for gen9+ states "The DMUX CRC should only be enabled when the pipe, and one or more planes in the pipe are enabled." which implies that just using the background color (which is always on) isn't sufficient. I'll uncomment the CRC check when we actually push the test so that it can still be used on non-Intel platforms that don't have this restriction. Should we just make the test skip on the relevant i915 platforms, or should we do something else to mark the test as an expected failure due to hardware? Matt > > > FWIW, I've mmap'd the Cairo-generated plane framebuffer and verified > > that it contains exactly the pixel values we'd expect (so it's not a > > matter of bad roundoff in Cairo), and I've tried flipping both 8bpc and > > 10bpc pixel formats (to match the background color's 10 bits per > > component), but nothing seems to make the CRC's match. :-( > > > > > > Matt > > > > > > > > > > > > > > > > > Matt > > > > > > > > > > > > > > So I think ABI-wise we've met the userspace consumer requirements to > > > > > upstream this; we just need to get reviews on the two i915-specific > > > > > patches and a clean CI report. > > > > > > > > > > v4.1 is identical to v4 aside from a rebase onto the latest drm-tip. > > > > > > > > > > > > > > > Matt Roper (3): > > > > > drm/i915: Force background color to black for gen9+ (v2) > > > > > drm: Add CRTC background color property (v4) > > > > > drm/i915/gen9+: Add support for pipe background color (v4) > > > > > > > > > > drivers/gpu/drm/drm_atomic_uapi.c| 4 > > > > > drivers/gpu/drm/drm_blend.c | 27 +++--- > > > > > drivers/gpu/drm/drm_mode_config.c| 6 + > > > > > drivers/gpu/drm/i915/i915_debugfs.c | 9 > > > > > drivers/gpu/drm/i915/i915_reg.h | 6 + > > > > > drivers/gpu/drm/i915/intel_display.c | 43 > > > > > > > > > > include/drm/drm_blend.h | 1 + > > > > > include/drm/drm_crtc.h | 12 ++ > > > > > include/drm/drm_mode_config.h| 5 + > > > > > include/uapi/drm/drm_mode.h | 28 +++ > > > > > 10 files changed, 138 insertions(+), 3 deletions(-) > > > > > > > > > > -- > > > > > 2.14.5 > > > > > > > > > > > > > -- > > > > Matt Roper > > > > Graphics Software Engineer > > > > IoTG Platform Enabling & Development > > > > Intel Corporation > > > > (916) 356-2795 > > > > __
Re: [Intel-gfx] [PATCH v2 2/4] drm/dp_mst: Remove port validation in drm_dp_atomic_find_vcpi_slots()
On Thu, Jan 31, 2019 at 08:14:49PM -0500, Lyude Paul wrote:
> Since we now have an easy way of refcounting drm_dp_mst_port structs and
> safely accessing their contents, there isn't any good reason to keep
> validating ports here. It doesn't prevent us from performing modesets on
> branch devices that have been removed either, and we already disallow
> enabling new displays on unregistered connectors in
> update_connector_routing() in drm_atomic_check_modeset(). All it does is
> cause us to have to make weird special exceptions in our atomic
> modesetting code. So, get rid of it entirely.
>
> Signed-off-by: Lyude Paul
> Fixes: eceae1472467 ("drm/dp_mst: Start tracking per-port VCPI allocations")
> Cc: Daniel Vetter
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 12 ++--
> drivers/gpu/drm/i915/intel_dp_mst.c | 17 ++---
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
> 3 files changed, 9 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index abb0ea8ba9d9..4325e1518286 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3117,10 +3117,6 @@ int drm_dp_atomic_find_vcpi_slots(struct
> drm_atomic_state *state,
> if (IS_ERR(topology_state))
> return PTR_ERR(topology_state);
>
> - port = drm_dp_mst_topology_get_port_validated(mgr, port);
> - if (port == NULL)
> - return -EINVAL;
> -
> /* Find the current allocation for this port, if any */
> list_for_each_entry(pos, &topology_state->vcpis, next) {
> if (pos->port == port) {
Also noticed that the WARN_ON() return -EINVAL; here gets fixed with this
patch.
Reviewed-by: Daniel Vetter
> @@ -3153,10 +3149,8 @@ int drm_dp_atomic_find_vcpi_slots(struct
> drm_atomic_state *state,
> /* Add the new allocation to the state */
> if (!vcpi) {
> vcpi = kzalloc(sizeof(*vcpi), GFP_KERNEL);
> - if (!vcpi) {
> - ret = -ENOMEM;
> - goto out;
> - }
> + if (!vcpi)
> + return -ENOMEM;
>
> drm_dp_mst_get_port_malloc(port);
> vcpi->port = port;
> @@ -3165,8 +3159,6 @@ int drm_dp_atomic_find_vcpi_slots(struct
> drm_atomic_state *state,
> vcpi->vcpi = req_slots;
>
> ret = req_slots;
> -out:
> - drm_dp_mst_topology_put_port(port);
> return ret;
> }
> EXPORT_SYMBOL(drm_dp_atomic_find_vcpi_slots);
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index cdb83d294cdd..fb67cd931117 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -80,17 +80,12 @@ static int intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
> mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);
> pipe_config->pbn = mst_pbn;
>
> - /* Zombie connectors can't have VCPI slots */
> - if (!drm_connector_is_unregistered(connector)) {
> - slots = drm_dp_atomic_find_vcpi_slots(state,
> - &intel_dp->mst_mgr,
> - port,
> - mst_pbn);
> - if (slots < 0) {
> - DRM_DEBUG_KMS("failed finding vcpi slots:%d\n",
> - slots);
> - return slots;
> - }
> + slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, port,
> + mst_pbn);
> + if (slots < 0) {
> + DRM_DEBUG_KMS("failed finding vcpi slots:%d\n",
> + slots);
> + return slots;
> }
>
> intel_link_compute_m_n(bpp, lane_count,
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index 2e8a5fd9b262..60d858c2f2ce 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -771,8 +771,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
> mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock,
>bpp);
>
> - if (drm_atomic_crtc_needs_modeset(crtc_state) &&
> - !drm_connector_is_unregistered(connector)) {
> + if (drm_atomic_crtc_needs_modeset(crtc_state)) {
> slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr,
> mstc->port, mstc->pbn);
> if (slots < 0)
> --
> 2.20.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✓ Fi.CI.IGT: success for DC states igt tests patch series
== Series Details ==
Series: DC states igt tests patch series
URL : https://patchwork.freedesktop.org/series/56093/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5525_full -> IGTPW_2335_full
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56093/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in IGTPW_2335_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@pm_dc@dc5-dpms}:
- shard-apl: NOTRUN -> FAIL
* {igt@pm_dc@dc6-dpms}:
- shard-kbl: NOTRUN -> FAIL
Known issues
Here are the changes found in IGTPW_2335_full that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_eio@reset-stress:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540] / [fdo#109482]
* igt@kms_atomic_transition@plane-all-transition:
- shard-kbl: PASS -> DMESG-FAIL [fdo#103558] / [fdo#105602] /
[fdo#109225]
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-apl: PASS -> FAIL [fdo#106641]
- shard-glk: PASS -> FAIL [fdo#106641]
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-kbl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: PASS -> FAIL [fdo#103232] +4
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-glk: PASS -> FAIL [fdo#103232] +2
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-xtiled:
- shard-kbl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-kbl: PASS -> FAIL [fdo#103167] +1
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: PASS -> FAIL [fdo#103167] +4
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948] +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-kbl: PASS -> FAIL [fdo#103166] +1
* igt@kms_vblank@crtc-id:
- shard-kbl: PASS -> DMESG-WARN [fdo#103313] / [fdo#103558] /
[fdo#105602] +3
Possible fixes
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: FAIL [fdo#106510] / [fdo#108145] -> PASS
* igt@kms_color@pipe-b-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS +1
- shard-kbl: FAIL [fdo#108147] -> PASS +1
* igt@kms_color@pipe-b-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-kbl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS +1
- shard-kbl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-glk: FAIL [fdo#103167] / [fdo#105682] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +4
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-glk: FAIL [fdo#103166] -> PASS +7
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-kbl: FAIL [fdo#103166] -> PASS +3
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
Warnings
* igt@i915_suspend@shrink:
- shard-snb: INCOMPLETE [fdo
Re: [Intel-gfx] [PATCH v6 1/5] staging/vboxvideo: prepare for drmP.h removal from drm_modeset_helper.h
On Fri, Feb 01, 2019 at 06:37:49PM +0100, Daniel Vetter wrote: > On Sat, Jan 26, 2019 at 01:25:23PM +0100, Sam Ravnborg wrote: > > The use of drmP.h is discouraged and removal of it from > > drm_modeset_helper.h caused vboxvideo to fail to build. > > > > This patch introduce the necessary fixes to prepare for the > > drmP.h removal from drm_modeset_helper.h. > > > > In the files touched sort the include files > > > > Build tested on x86 and arm allmodconfig / allyesconfig. > > > > Signed-off-by: Sam Ravnborg > > Cc: Greg Kroah-Hartman > > Cc: Hans de Goede > > Cc: Daniel Vetter > > Hi Greg, > > Ack for merging this through drm-misc? I think we've defacto-maintained > vboxvideo in drm anyway this release ... Sorry, feel free to just always take this type of stuff without my ack, I can merge around you if I ever have any problems. Acked-by: Greg Kroah-Hartman ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 RESEND 1/2] drm/fourcc: Add 64 bpp half float formats
Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
formatted in IEEE-754 half-precision float (binary16) 1:5:10
MSb-sign:exponent:fraction form.
This patch attempts to address the feedback provided when 2 of these
formats were previosly proposed:
https://patchwork.kernel.org/patch/10072545/
v2:
- Fixed cpp (Ville)
- Added detail pixel formatting (Ville)
- Ordered formats in header (Ville)
Signed-off-by: Kevin Strasser
Cc: Tina Zhang
Cc: Uma Shankar
Cc: Shashank Sharma
Cc: Ville Syrjälä
Cc: David Airlie
Cc: Daniel Vetter
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_fourcc.c | 4
include/uapi/drm/drm_fourcc.h | 11 +++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03..c866452 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_ABGR,.depth = 32,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGBA,.depth = 32,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGRA,.depth = 32,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_XRGB16161616F, .depth = 48,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XBGR16161616F, .depth = 48,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_ARGB16161616F, .depth = 64,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR16161616F, .depth = 64,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGB888_A8, .depth = 32,
.num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGR888_A8, .depth = 32,
.num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_XRGB_A8, .depth = 32,
.num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 91d08a2..c516b40 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -144,6 +144,17 @@ extern "C" {
#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0]
R:G:B:A 10:10:10:2 little endian */
#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0]
B:G:R:A 10:10:10:2 little endian */
+/*
+ * Floating point 64bpp RGB
+ * IEEE 754-2008 binary16 half-precision float
+ * [15:0] sign:exponent:mantissa 1:5:10
+ */
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0]
x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0]
x:B:G:R 16:16:16:16 little endian */
+
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0]
A:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0]
A:B:G:R 16:16:16:16 little endian */
+
/* packed YCbCr */
#define DRM_FORMAT_YUYVfourcc_code('Y', 'U', 'Y', 'V') /*
[31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
#define DRM_FORMAT_YVYUfourcc_code('Y', 'V', 'Y', 'U') /*
[31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
--
2.7.4
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[Intel-gfx] [PATCH v2 RESEND 2/2] drm/i915/icl: Implement half float formats
64 bpp half float formats are supported on hdr planes only and are subject
to the following restrictions:
* 90/270 rotation not supported
* Yf Tiling not supported
* Frame Buffer Compression not supported
* Color Keying not supported
v2:
- Drop handling pixel normalize register
- Don't use icl_is_hdr_plane too early
Signed-off-by: Kevin Strasser
Cc: Uma Shankar
Cc: Shashank Sharma
Cc: Ville Syrjälä
Cc: David Airlie
Cc: Daniel Vetter
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/i915/intel_display.c | 22
drivers/gpu/drm/i915/intel_sprite.c | 67
2 files changed, 83 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a6d8985..f413ccd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2668,6 +2668,18 @@ int skl_format_to_fourcc(int format, bool rgb_order,
bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XRGB_16161616F:
+ if (rgb_order) {
+ if (alpha)
+ return DRM_FORMAT_ABGR16161616F;
+ else
+ return DRM_FORMAT_XBGR16161616F;
+ } else {
+ if (alpha)
+ return DRM_FORMAT_ARGB16161616F;
+ else
+ return DRM_FORMAT_XRGB16161616F;
+ }
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3566,6 +3578,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ return PLANE_CTL_FORMAT_XRGB_16161616F;
default:
MISSING_CASE(pixel_format);
}
@@ -5069,6 +5087,10 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cd42e81..97f9d05 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1450,8 +1450,6 @@ static int skl_plane_check_fb(const struct
intel_crtc_state *crtc_state,
/*
* 90/270 is not allowed with RGB64 16:16:16:16 and
* Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
-* TBD: Add RGB64 case once its added in supported format
-* list.
*/
switch (fb->format->format) {
case DRM_FORMAT_RGB565:
@@ -1459,6 +1457,10 @@ static int skl_plane_check_fb(const struct
intel_crtc_state *crtc_state,
break;
/* fall through */
case DRM_FORMAT_C8:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_ABGR16161616F:
DRM_DEBUG_KMS("Unsupported pixel format %s for
90/270!\n",
drm_get_format_name(fb->format->format,
&format_name));
@@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static const uint32_t icl_hdr_plane_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
+ DRM_FORMAT_ARGB16161616F,
+ DRM_FORMAT_ABGR16161616F,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+};
+
+static const uint32_t icl_hdr_planar_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DR
[Intel-gfx] [PATCH v2 RESEND 0/2] Support 64 bpp half float formats
This series defines new formats and adds implementation to the i915 driver. Since posting v1 I have removed the pixel normalize property, as it's not needed for basic functionality. Also, I have been working on adding support to userspace, but we can't land any patches until drm_fourcc.h has been updated here. I have submitted a series to Mesa to make use of the RGBA ordered formats: https://patchwork.freedesktop.org/series/54759/ My igt branch is reworked to drop usage of pixel normalize and includes use of f16c intrinsics to speed up conversion: https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commits/fp16 I also have a libdrm branch with fp16 coverage added to modetest: https://gitlab.freedesktop.org/strassek/drm/commits/fp16 To serve as a smoke test of the whole stack I have a modified version of kmscube: https://gitlab.freedesktop.org/strassek/kmscube/commits/fp16 Kevin Strasser (2): drm/fourcc: Add 64 bpp half float formats drm/i915/icl: Implement half float formats drivers/gpu/drm/drm_fourcc.c | 4 +++ drivers/gpu/drm/i915/intel_display.c | 22 drivers/gpu/drm/i915/intel_sprite.c | 67 include/uapi/drm/drm_fourcc.h| 11 ++ 4 files changed, 98 insertions(+), 6 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 1/5] staging/vboxvideo: prepare for drmP.h removal from drm_modeset_helper.h
On Sat, Jan 26, 2019 at 01:25:23PM +0100, Sam Ravnborg wrote: > The use of drmP.h is discouraged and removal of it from > drm_modeset_helper.h caused vboxvideo to fail to build. > > This patch introduce the necessary fixes to prepare for the > drmP.h removal from drm_modeset_helper.h. > > In the files touched sort the include files > > Build tested on x86 and arm allmodconfig / allyesconfig. > > Signed-off-by: Sam Ravnborg > Cc: Greg Kroah-Hartman > Cc: Hans de Goede > Cc: Daniel Vetter Hi Greg, Ack for merging this through drm-misc? I think we've defacto-maintained vboxvideo in drm anyway this release ... -Daniel > --- > drivers/staging/vboxvideo/vbox_drv.c | 6 +- > drivers/staging/vboxvideo/vbox_fb.c | 18 ++ > drivers/staging/vboxvideo/vbox_mode.c | 5 - > 3 files changed, 19 insertions(+), 10 deletions(-) > > diff --git a/drivers/staging/vboxvideo/vbox_drv.c > b/drivers/staging/vboxvideo/vbox_drv.c > index cc6532d8c2fa..d1b0d7b4886a 100644 > --- a/drivers/staging/vboxvideo/vbox_drv.c > +++ b/drivers/staging/vboxvideo/vbox_drv.c > @@ -7,11 +7,15 @@ > * Michael Thayer* Hans de Goede > */ > -#include > #include > +#include > +#include > #include > > #include > +#include > +#include > +#include > > #include "vbox_drv.h" > > diff --git a/drivers/staging/vboxvideo/vbox_fb.c > b/drivers/staging/vboxvideo/vbox_fb.c > index 397496cf0bdf..83a04afd1766 100644 > --- a/drivers/staging/vboxvideo/vbox_fb.c > +++ b/drivers/staging/vboxvideo/vbox_fb.c > @@ -6,20 +6,22 @@ > * Authors: Dave Airlie > * Michael Thayer*/ > -#include > -#include > -#include > -#include > -#include > -#include > -#include > #include > +#include > #include > #include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > > #include > -#include > #include > +#include > +#include > > #include "vbox_drv.h" > #include "vboxvideo.h" > diff --git a/drivers/staging/vboxvideo/vbox_mode.c > b/drivers/staging/vboxvideo/vbox_mode.c > index 1aaff02c07ff..213551394495 100644 > --- a/drivers/staging/vboxvideo/vbox_mode.c > +++ b/drivers/staging/vboxvideo/vbox_mode.c > @@ -10,14 +10,17 @@ > * Hans de Goede > */ > #include > + > #include > #include > +#include > #include > #include > +#include > > +#include "hgsmi_channels.h" > #include "vbox_drv.h" > #include "vboxvideo.h" > -#include "hgsmi_channels.h" > > /* > * Set a graphics mode. Poke any required values into registers, do an HGSMI > -- > 2.12.0 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Avoid uninterruptible spinning in debugfs
Quoting Tvrtko Ursulin (2019-02-01 17:29:45)
>
> On 01/02/2019 10:52, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 4067eeaee78a..e47d53e9b634 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -4499,13 +4499,17 @@ int i915_gem_suspend(struct drm_i915_private *i915)
> > mutex_unlock(&i915->drm.struct_mutex);
> > i915_reset_flush(i915);
> >
> > - drain_delayed_work(&i915->gt.retire_work);
> > -
> > /*
> >* As the idle_work is rearming if it detects a race, play safe and
> >* repeat the flush until it is definitely idle.
> >*/
> > - drain_delayed_work(&i915->gt.idle_work);
> > + if (drain_delayed_work_state(&i915->gt.retire_work,
> > + TASK_INTERRUPTIBLE) ||
> > + drain_delayed_work_state(&i915->gt.idle_work,
> > + TASK_INTERRUPTIBLE)) {
> > + ret = -EINTR;
> > + goto err_unlock;
> > + }
>
> I'm no suspend expert but it sounds unexpected there would be signals
> involved in the process. Does it have an userspace component? We don't
> bother with interruptible mutex on this path either.
You wouldn't believe what users get up to! And they then file a bug
report that they interrupted suspend and it said EINTR...
> > diff --git a/drivers/gpu/drm/i915/i915_utils.h
> > b/drivers/gpu/drm/i915/i915_utils.h
> > index fcc751aa1ea8..6866b85e4239 100644
> > --- a/drivers/gpu/drm/i915/i915_utils.h
> > +++ b/drivers/gpu/drm/i915/i915_utils.h
> > @@ -25,6 +25,8 @@
> > #ifndef __I915_UTILS_H
> > #define __I915_UTILS_H
> >
> > +#include
> > +
> > #undef WARN_ON
> > /* Many gcc seem to no see through this and fall over :( */
> > #if 0
> > @@ -148,12 +150,22 @@ static inline void __list_del_many(struct list_head
> > *head,
> >* by requeueing itself. Note, that if the worker never cancels itself,
> >* we will spin forever.
> >*/
> > -static inline void drain_delayed_work(struct delayed_work *dw)
> > +
> > +static inline int drain_delayed_work_state(struct delayed_work *dw, int
> > state)
> > {
> > do {
> > - while (flush_delayed_work(dw))
> > - ;
> > + do {
> > + if (signal_pending_state(state, current))
> > + return -EINTR;
> > + } while (flush_delayed_work(dw));
> > } while (delayed_work_pending(dw));
> > +
> > + return 0;
> > +}
> > +
> > +static inline void drain_delayed_work(struct delayed_work *dw)
> > +{
> > + drain_delayed_work_state(dw, 0);
>
> 0 would be TASK_RUNNING. signal_pending_state bails out in this case so
> that's good.
The same trick is used in mutex_lock_(interruptible|killable) to map
onto a common handler for mutex_lock, so I don't think its unintentional
;)
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Avoid uninterruptible spinning in debugfs
On 01/02/2019 10:52, Chris Wilson wrote:
If we get caught in a kernel bug, we may never idle. Let the user regain
control of their system^Wterminal by responding to SIGINT!
v2: Push the signal checking into the loop around flush_work.
Reported-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c| 14 --
drivers/gpu/drm/i915/i915_gem.c| 10 +++---
drivers/gpu/drm/i915/i915_utils.h | 18 +++---
.../gpu/drm/i915/selftests/i915_gem_context.c | 5 -
4 files changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f3fa31d840f5..44fa34f4ebbc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3945,12 +3945,14 @@ i915_drop_caches_set(void *data, u64 val)
i915_gem_shrink_all(i915);
fs_reclaim_release(GFP_KERNEL);
- if (val & DROP_IDLE) {
- do {
- if (READ_ONCE(i915->gt.active_requests))
- flush_delayed_work(&i915->gt.retire_work);
- drain_delayed_work(&i915->gt.idle_work);
- } while (READ_ONCE(i915->gt.awake));
+ if (val & DROP_IDLE && READ_ONCE(i915->gt.awake)) {
+ if (drain_delayed_work_state(&i915->gt.retire_work,
+TASK_INTERRUPTIBLE) ||
+ drain_delayed_work_state(&i915->gt.idle_work,
+TASK_INTERRUPTIBLE)) {
+ ret = -EINTR;
+ goto out;
+ }
Shrinker remains only killable so still not Ctrl-C in all cases here.
Don't know, not hot not cold. Will re-think it next week.
}
if (val & DROP_FREED)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4067eeaee78a..e47d53e9b634 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4499,13 +4499,17 @@ int i915_gem_suspend(struct drm_i915_private *i915)
mutex_unlock(&i915->drm.struct_mutex);
i915_reset_flush(i915);
- drain_delayed_work(&i915->gt.retire_work);
-
/*
* As the idle_work is rearming if it detects a race, play safe and
* repeat the flush until it is definitely idle.
*/
- drain_delayed_work(&i915->gt.idle_work);
+ if (drain_delayed_work_state(&i915->gt.retire_work,
+TASK_INTERRUPTIBLE) ||
+ drain_delayed_work_state(&i915->gt.idle_work,
+TASK_INTERRUPTIBLE)) {
+ ret = -EINTR;
+ goto err_unlock;
+ }
I'm no suspend expert but it sounds unexpected there would be signals
involved in the process. Does it have an userspace component? We don't
bother with interruptible mutex on this path either.
/*
* Assert that we successfully flushed all the work and
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index fcc751aa1ea8..6866b85e4239 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -25,6 +25,8 @@
#ifndef __I915_UTILS_H
#define __I915_UTILS_H
+#include
+
#undef WARN_ON
/* Many gcc seem to no see through this and fall over :( */
#if 0
@@ -148,12 +150,22 @@ static inline void __list_del_many(struct list_head *head,
* by requeueing itself. Note, that if the worker never cancels itself,
* we will spin forever.
*/
-static inline void drain_delayed_work(struct delayed_work *dw)
+
+static inline int drain_delayed_work_state(struct delayed_work *dw, int state)
{
do {
- while (flush_delayed_work(dw))
- ;
+ do {
+ if (signal_pending_state(state, current))
+ return -EINTR;
+ } while (flush_delayed_work(dw));
} while (delayed_work_pending(dw));
+
+ return 0;
+}
+
+static inline void drain_delayed_work(struct delayed_work *dw)
+{
+ drain_delayed_work_state(dw, 0);
0 would be TASK_RUNNING. signal_pending_state bails out in this case so
that's good.
}
static inline const char *yesno(bool v)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 2b423128002c..a87998b90bf6 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -1686,8 +1686,11 @@ static int __igt_switch_to_kernel_context(struct
drm_i915_private *i915,
/* XXX Bonus points for proving we are the kernel context! */
mutex_unlock(&i915->drm.struct_mutex);
- drain_delayed_work(&i915->gt.idle_work);
+ err = drain_delayed_work_state(&i915->
Re: [Intel-gfx] [PATCH v4.1 0/3] CRTC background color
On Wed, Jan 30, 2019 at 03:48:50PM -0800, Matt Roper wrote: > On Wed, Jan 30, 2019 at 09:57:10PM +0100, Daniel Vetter wrote: > > On Wed, Jan 30, 2019 at 10:56:26AM -0800, Matt Roper wrote: > > > On Wed, Jan 30, 2019 at 10:51:19AM -0800, Matt Roper wrote: > > > > Previous patch series was here: > > > > > > > > https://lists.freedesktop.org/archives/dri-devel/2018-December/201949.html > > > > > > > > I'm told the ChromeOS userspace code to make use of the background color > > > > has been reviewed and is ready for use: > > > > * https://chromium-review.googlesource.com/c/chromium/src/+/1278858 > > > > * https://chromium-review.googlesource.com/c/chromium/src/+/1278858 > > > > > > Woops, the second link here should have been to > > > > > > > > > https://chromium-review.googlesource.com/c/chromiumos/platform/drm-tests/+/1241436 > > > > > > which I believe is some unit tests to go along with the main userspace > > > code. > > > > Do we have this as igts too? > > -Daniel > > Yeah, I posted it along with some of the earlier revisions of the > series, but haven't reposted the latest copy lately. I'll check and see > if it needs a rebase and then post it shortly. > > Unfortunately the IGT isn't as useful as I'd like it to be since the > CRC's for a plane filled with a solid color never come up the same as a > pure background color (at least on the APL platform I'm using). I can > run the IGT in interactive mode and the colors seem identical to visual > inspection, but the CRC values never agree, so I've disabled the CRC > comparison in the test for now. I'm not sure if this is related to the > other blending quirks of gen9; it will be interesting to see if the > CRC's match on an Icelake or something. Please don't do that, we need to know when stuff doesn't work. Also, igt (at least for more generic stuff like this) shouldn't be bent to exactly match intel hw bugs. And yes if the blending is generally broken on gen9 then I'd be surprised if they managed to not screw it up for the background color. Usually backgroun color works as if it's a separate additional plane that you blend the others with. -Daniel > FWIW, I've mmap'd the Cairo-generated plane framebuffer and verified > that it contains exactly the pixel values we'd expect (so it's not a > matter of bad roundoff in Cairo), and I've tried flipping both 8bpc and > 10bpc pixel formats (to match the background color's 10 bits per > component), but nothing seems to make the CRC's match. :-( > > > Matt > > > > > > > > > > > > Matt > > > > > > > > > > > So I think ABI-wise we've met the userspace consumer requirements to > > > > upstream this; we just need to get reviews on the two i915-specific > > > > patches and a clean CI report. > > > > > > > > v4.1 is identical to v4 aside from a rebase onto the latest drm-tip. > > > > > > > > > > > > Matt Roper (3): > > > > drm/i915: Force background color to black for gen9+ (v2) > > > > drm: Add CRTC background color property (v4) > > > > drm/i915/gen9+: Add support for pipe background color (v4) > > > > > > > > drivers/gpu/drm/drm_atomic_uapi.c| 4 > > > > drivers/gpu/drm/drm_blend.c | 27 +++--- > > > > drivers/gpu/drm/drm_mode_config.c| 6 + > > > > drivers/gpu/drm/i915/i915_debugfs.c | 9 > > > > drivers/gpu/drm/i915/i915_reg.h | 6 + > > > > drivers/gpu/drm/i915/intel_display.c | 43 > > > > > > > > include/drm/drm_blend.h | 1 + > > > > include/drm/drm_crtc.h | 12 ++ > > > > include/drm/drm_mode_config.h| 5 + > > > > include/uapi/drm/drm_mode.h | 28 +++ > > > > 10 files changed, 138 insertions(+), 3 deletions(-) > > > > > > > > -- > > > > 2.14.5 > > > > > > > > > > -- > > > Matt Roper > > > Graphics Software Engineer > > > IoTG Platform Enabling & Development > > > Intel Corporation > > > (916) 356-2795 > > > ___ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > http://blog.ffwll.ch > > -- > Matt Roper > Graphics Software Engineer > IoTG Platform Enabling & Development > Intel Corporation > (916) 356-2795 -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-next
On Fri, Feb 01, 2019 at 02:15:23PM +0800, Zhenyu Wang wrote: > > Hi, > > This should be last gvt-next pull for this round, which adds VFIO edid > region support in GVT, VM manager can use this to specify custom EDID > for VM, which can be used for e.g UI resize, etc. Pulled, thanks > > p.s, Next week will be chinese new year, so team will be offline then. Happy New Year! > > Thanks. > -- > The following changes since commit 2e679d48f38c378650db403b4ba2248adf0691b2: > > drm/i915/gvt: switch to kernel types (2019-01-23 13:56:14 +0800) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux.git tags/gvt-next-2019-02-01 > > for you to fetch changes up to 39c68e87bc50a71bcfe93582d9b0673ef30db418: > > drm/i915/gvt: add VFIO EDID region (2019-01-31 11:41:25 +0800) > > > gvt-next-2019-02-01 > > - new VFIO EDID region support (Henry) > > > Hang Yuan (3): > drm/i915/gvt: add functions to get default resolution > drm/i915/gvt: add hotplug emulation > drm/i915/gvt: add VFIO EDID region > > drivers/gpu/drm/i915/gvt/display.c | 31 > drivers/gpu/drm/i915/gvt/display.h | 37 +++-- > drivers/gpu/drm/i915/gvt/gvt.c | 1 + > drivers/gpu/drm/i915/gvt/gvt.h | 3 + > drivers/gpu/drm/i915/gvt/hypercall.h | 1 + > drivers/gpu/drm/i915/gvt/kvmgt.c | 143 > +++ > drivers/gpu/drm/i915/gvt/mpt.h | 17 + > drivers/gpu/drm/i915/gvt/vgpu.c | 6 ++ > 8 files changed, 233 insertions(+), 6 deletions(-) > > > -- > Open Source Technology Center, Intel ltd. > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Set ->connectors_changed to force HDCP updates
== Series Details ==
Series: drm/i915: Set ->connectors_changed to force HDCP updates
URL : https://patchwork.freedesktop.org/series/56089/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5525_full -> Patchwork_12119_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12119_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-contexts-10ms:
- shard-glk: PASS -> FAIL [fdo#107799]
* igt@kms_addfb_basic@invalid-set-prop:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@pm_rpm@gem-execbuf-stress:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
Possible fixes
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-b-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-glk: FAIL [fdo#103166] -> PASS +3
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
Warnings
* igt@i915_suspend@shrink:
- shard-snb: INCOMPLETE [fdo#105411] / [fdo#106886] -> DMESG-WARN
[fdo#109244]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-hsw: DMESG-WARN [fdo#107956] -> INCOMPLETE [fdo#103540]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107799]: https://bugs.freedesktop.org/show_bug.cgi?id=107799
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5525 -> Patchwork_12119
CI_DRM_5525: 6d10b00ff86e70c4590724262c30ec8388174d38 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4803: 973367176b61e81b5ca811620adb0467f6570aec @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12119: e2f23aecb4c1880f1cf45025c6d68bc3513fcbfc @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12119/
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for DC states igt tests patch series
== Series Details ==
Series: DC states igt tests patch series
URL : https://patchwork.freedesktop.org/series/56093/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5525 -> IGTPW_2335
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56093/revisions/1/mbox/
Known issues
Here are the changes found in IGTPW_2335 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (49 -> 45)
--
Additional (1): fi-cfl-8109u
Missing(5): fi-kbl-7567u fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600
Build changes
-
* IGT: IGT_4803 -> IGTPW_2335
CI_DRM_5525: 6d10b00ff86e70c4590724262c30ec8388174d38 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2335: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2335/
IGT_4803: 973367176b61e81b5ca811620adb0467f6570aec @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@pm_dc@dc5-dpms
+igt@pm_dc@dc5-psr
+igt@pm_dc@dc6-dpms
+igt@pm_dc@dc6-psr
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2335/
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v4 4/5] tests/pm_dc: Added test for DC5 during DPMS
From: Jyoti Yadav
Added new subtest for DC5 entry during DPMS on/off cycle.
During DPMS on/off cycle DC5 counter is incremented.
v2: Rename the subtest with meaningful name.
v3: Rebased.
v4: Addressed review comments.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/pm_dc.c | 32
1 file changed, 32 insertions(+)
diff --git a/tests/pm_dc.c b/tests/pm_dc.c
index ea612a7..05f1363 100644
--- a/tests/pm_dc.c
+++ b/tests/pm_dc.c
@@ -164,6 +164,29 @@ static void test_dc_state_psr(data_t *data, int dc_flag)
check_dc_counter(data->drm_fd, dc_flag, dc_counter_before_psr);
}
+static void dpms_off_on(data_t *data)
+{
+ for (int i = 0; i < data->display.n_outputs; i++) {
+ kmstest_set_connector_dpms(data->drm_fd,
data->display.outputs[i].config.connector,
+ DRM_MODE_DPMS_OFF);
+ }
+ igt_assert(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED));
+ for (int i = 0; i < data->display.n_outputs; i++) {
+ kmstest_set_connector_dpms(data->drm_fd,
data->display.outputs[i].config.connector,
+ DRM_MODE_DPMS_ON);
+ }
+ igt_assert(igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_ACTIVE));
+}
+
+static void test_dc_state_dpms(data_t *data, int dc_flag)
+{
+ uint32_t dc_counter;
+
+ dc_counter = read_dc_counter(data->drm_fd, dc_flag);
+ dpms_off_on(data);
+ check_dc_counter(data->drm_fd, dc_flag, dc_counter);
+}
+
int main(int argc, char *argv[])
{
bool has_runtime_pm;
@@ -209,6 +232,15 @@ int main(int argc, char *argv[])
test_dc_state_psr(&data, CHECK_DC6);
cleanup(&data);
}
+
+ igt_subtest("dc5-dpms") {
+ /* Check DC5 counter is available for the platform.
+* Skip the test if counter is not available.
+*/
+ read_dc_counter(data.drm_fd, CHECK_DC5);
+ test_dc_state_dpms(&data, CHECK_DC5);
+ }
+
igt_fixture {
close(data.debugfs_fd);
display_fini(&data);
--
2.7.4
___
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[Intel-gfx] [PATCH i-g-t v4 2/5] tests/pm_dc: Added new test to verify Display C States
From: Jyoti Yadav
Currently this test validates DC5 upon PSR entry for supported platforms.
Added new file for compilation inside Makefile and Meson.
v2: Used the debugfs entry for DC counters instead of Registers.
Used shorter names for variables.
Introduced timeout to read DC counters.
v3: one second timeout is introduced to read DC counters.
Skip the subtest if counters are not available for that platform.
v4: Rebased, addressed the review comment and spell correction.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/Makefile.sources | 1 +
tests/meson.build | 1 +
tests/pm_dc.c | 205 +
3 files changed, 207 insertions(+)
create mode 100644 tests/pm_dc.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 34b7e44..07b9787 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -80,6 +80,7 @@ TESTS_progs = \
pm_lpsp \
pm_rc6_residency \
pm_rpm \
+ pm_dc \
pm_rps \
pm_sseu \
prime_busy \
diff --git a/tests/meson.build b/tests/meson.build
index 25b4614..3070a3e 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -66,6 +66,7 @@ test_progs = [
'pm_lpsp',
'pm_rc6_residency',
'pm_rpm',
+ 'pm_dc',
'pm_rps',
'pm_sseu',
'prime_busy',
diff --git a/tests/pm_dc.c b/tests/pm_dc.c
new file mode 100644
index 000..d59be94
--- /dev/null
+++ b/tests/pm_dc.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "igt_sysfs.h"
+#include "igt_psr.h"
+#include
+#include
+#include
+#include
+#include "intel_bufmgr.h"
+#include "intel_io.h"
+#include "limits.h"
+
+
+typedef struct {
+ int drm_fd;
+ int debugfs_fd;
+ uint32_t devid;
+ igt_display_t display;
+ struct igt_fb fb_white;
+ enum psr_mode op_psr_mode;
+ drmModeModeInfo *mode;
+ igt_output_t *output;
+} data_t;
+
+/* DC State Flags */
+#define CHECK_DC5 1
+#define CHECK_DC6 2
+
+static void setup_output(data_t *data)
+{
+ igt_display_t *display = &data->display;
+ igt_output_t *output;
+ enum pipe pipe;
+
+ for_each_pipe_with_valid_output(display, pipe, output) {
+ drmModeConnectorPtr c = output->config.connector;
+
+ if (c->connector_type != DRM_MODE_CONNECTOR_eDP)
+ continue;
+
+ igt_output_set_pipe(output, pipe);
+ data->output = output;
+ data->mode = igt_output_get_mode(output);
+
+ return;
+ }
+}
+
+static void display_fini(data_t *data)
+{
+ igt_display_fini(&data->display);
+}
+
+static bool edp_psr_sink_support(data_t *data)
+{
+ char buf[512];
+
+ igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
+buf, sizeof(buf));
+
+ return strstr(buf, "Sink_Support: yes\n");
+}
+
+static void cleanup(data_t *data)
+{
+ igt_plane_t *primary;
+
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+ igt_plane_set_fb(primary, NULL);
+ igt_display_commit(&data->display);
+ igt_remove_fb(data->drm_fd, &data->fb_white);
+}
+
+static void setup_primary(data_t *data)
+{
+ igt_plane_t *primary;
+
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+ igt_plane_set_fb(primary, NULL);
+ igt_create_color_fb(data->drm_fd,
+ data->mode->hdisplay, data->mode->vdisplay,
+ DRM_FORMAT_XRGB,
+ LOCAL_I915_FORMAT_MOD_X_TILED,
+ 1.0, 1.0, 1.0,
+
[Intel-gfx] [PATCH i-g-t v4 5/5] tests/pm_dc: Added test for DC6 during DPMS
From: Jyoti Yadav
Added new subtest for DC6 entry during DPMS on/off cycle.
During DPMS on/off cycle DC6 counter is incremented.
v2: Renamed the subtest name.
v3: Rebased.
v4: Rebased and address review comment.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/pm_dc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/pm_dc.c b/tests/pm_dc.c
index 05f1363..244665d 100644
--- a/tests/pm_dc.c
+++ b/tests/pm_dc.c
@@ -241,6 +241,15 @@ int main(int argc, char *argv[])
test_dc_state_dpms(&data, CHECK_DC5);
}
+ igt_subtest("dc6-dpms") {
+ /* Check DC6 counter is available for the platform.
+* Skip the test if counter is not available.
+*/
+ read_dc_counter(data.drm_fd, CHECK_DC6);
+ test_dc_state_dpms(&data, CHECK_DC6);
+ //cleanup(&data);
+ }
+
igt_fixture {
close(data.debugfs_fd);
display_fini(&data);
--
2.7.4
___
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[Intel-gfx] [PATCH i-g-t v4 3/5] tests/pm_dc: Added test for DC6 during PSR
From: Jyoti Yadav
This patch add subtest to check DC6 entry on PSR for the supported
platforms.
v2: Rename the subtest with more meaningful name.
v3: Rebased.
v4: Rebased and addressed review comment.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/pm_dc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/tests/pm_dc.c b/tests/pm_dc.c
index d59be94..ea612a7 100644
--- a/tests/pm_dc.c
+++ b/tests/pm_dc.c
@@ -196,6 +196,19 @@ int main(int argc, char *argv[])
test_dc_state_psr(&data, CHECK_DC5);
cleanup(&data);
}
+
+ igt_subtest("dc6-psr") {
+ data.op_psr_mode = PSR_MODE_1;
+ psr_enable(data.debugfs_fd, data.op_psr_mode);
+ igt_require_f(edp_psr_sink_support(&data),
+ "Sink does not support PSR\n");
+ /* Check DC6 counter is available for the platform.
+* Skip the test if counter is not available.
+*/
+ read_dc_counter(data.drm_fd, CHECK_DC6);
+ test_dc_state_psr(&data, CHECK_DC6);
+ cleanup(&data);
+ }
igt_fixture {
close(data.debugfs_fd);
display_fini(&data);
--
2.7.4
___
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[Intel-gfx] [PATCH i-g-t v4 1/5] lib/igt_pm: Moves Dmc_loaded() function into library
From: Jyoti Yadav
It will be used by new test pm_dc.c which will validate Display C States.
So moving the same to igt_pm library.
v2: Simplify the comment section.
v3: Remove . from the subject line.
v4: Rebased and addressed the review comments.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
lib/igt_pm.c | 28
lib/igt_pm.h | 1 +
tests/pm_rpm.c | 17 +
3 files changed, 30 insertions(+), 16 deletions(-)
diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 4902723..8b87c58 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -38,6 +38,7 @@
#include "drmtest.h"
#include "igt_pm.h"
#include "igt_aux.h"
+#include "igt_sysfs.h"
/**
* SECTION:igt_pm
@@ -620,3 +621,30 @@ bool igt_wait_for_pm_status(enum igt_runtime_pm_status
status)
{
return igt_wait(igt_get_runtime_pm_status() == status, 1, 100);
}
+
+/**
+ * dmc_loaded:
+ * @debugfs: fd to the debugfs dir.
+
+ * Check whether DMC FW is loaded or not. DMC FW is require for few Display C
+ * states like DC5 and DC6. FW does the Context Save and Restore during Display
+ * C States entry and exit.
+ *
+ * Returns:
+ * True if DMC FW is loaded otherwise false.
+ */
+bool igt_pm_dmc_loaded(int debugfs)
+{
+ igt_require(debugfs != -1);
+ char buf[15];
+ int len;
+
+ len = igt_sysfs_read(debugfs, "i915_dmc_info", buf, sizeof(buf) - 1);
+ if (len < 0)
+ return true; /* no CSR support, no DMC requirement */
+
+ buf[len] = '\0';
+
+ igt_info("DMC: %s\n", buf);
+ return strstr(buf, "fw loaded: yes");
+}
diff --git a/lib/igt_pm.h b/lib/igt_pm.h
index 10cc679..70d2380 100644
--- a/lib/igt_pm.h
+++ b/lib/igt_pm.h
@@ -50,5 +50,6 @@ bool igt_setup_runtime_pm(void);
void igt_restore_runtime_pm(void);
enum igt_runtime_pm_status igt_get_runtime_pm_status(void);
bool igt_wait_for_pm_status(enum igt_runtime_pm_status status);
+bool igt_pm_dmc_loaded(int debugfs);
#endif /* IGT_PM_H */
diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
index be296f5..2d7cb5e 100644
--- a/tests/pm_rpm.c
+++ b/tests/pm_rpm.c
@@ -710,21 +710,6 @@ static void setup_pc8(void)
has_pc8 = true;
}
-static bool dmc_loaded(void)
-{
- char buf[15];
- int len;
-
- len = igt_sysfs_read(debugfs, "i915_dmc_info", buf, sizeof(buf) - 1);
- if (len < 0)
- return true; /* no CSR support, no DMC requirement */
-
- buf[len] = '\0';
-
- igt_info("DMC: %s\n", buf);
- return strstr(buf, "fw loaded: yes");
-}
-
static void dump_file(int dir, const char *filename)
{
char *contents;
@@ -761,7 +746,7 @@ static bool setup_environment(void)
igt_info("Runtime PM support: %d\n", has_runtime_pm);
igt_info("PC8 residency support: %d\n", has_pc8);
igt_require(has_runtime_pm);
- igt_require(dmc_loaded());
+ igt_require(igt_pm_dmc_loaded(debugfs));
out:
disable_all_screens(&ms_data);
--
2.7.4
___
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[Intel-gfx] [PATCH i-g-t v4 0/5] DC states igt tests patch series
This patch series adds new tests to validate Display C states. DC states like DC5 and DC6 are validated during PSR entry/exit and during DPMS on/off cycle. Sending new revision of patch series after addressing review comments. Jyoti Yadav (5): lib/igt_pm: Moves Dmc_loaded() function into library tests/pm_dc: Added new test to verify Display C States tests/pm_dc: Added test for DC6 during PSR tests/pm_dc: Added test for DC5 during DPMS tests/pm_dc: Added test for DC6 during DPMS lib/igt_pm.c | 28 ++ lib/igt_pm.h | 1 + tests/Makefile.sources | 1 + tests/meson.build | 1 + tests/pm_dc.c | 259 + tests/pm_rpm.c | 17 +--- 6 files changed, 291 insertions(+), 16 deletions(-) create mode 100644 tests/pm_dc.c -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Set ->connectors_changed to force HDCP updates
== Series Details ==
Series: drm/i915: Set ->connectors_changed to force HDCP updates
URL : https://patchwork.freedesktop.org/series/56089/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5525 -> Patchwork_12119
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56089/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12119 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> WARN [fdo#109380]
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: PASS -> FAIL [fdo#109485]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (49 -> 43)
--
Additional (1): fi-cfl-8109u
Missing(7): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
fi-gdg-551 fi-icl-u3 fi-ivb-3520m
Build changes
-
* Linux: CI_DRM_5525 -> Patchwork_12119
CI_DRM_5525: 6d10b00ff86e70c4590724262c30ec8388174d38 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4803: 973367176b61e81b5ca811620adb0467f6570aec @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12119: e2f23aecb4c1880f1cf45025c6d68bc3513fcbfc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e2f23aecb4c1 drm/i915: Set ->connectors_changed to force HDCP updates
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12119/
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Delay hotplug sequence for TC ports
Hi Jose,
On Wed, Jan 23, 2019 at 10:51:35AM -0800, José Roberto de Souza wrote:
> Some unpowered USB type-c dongles requires some time to power on
> before being able to process aux channel transactions.
>
> It was not a problem for older platforms because there was a hardware
> bridge between DDI/DP ports and type-c controller adding a implicit
> delay that hid this issue but ICL have type-c controllers integrated
> to the SOC, causing sinks to not be detected.
>
> So here it test if DP type-c port is responsive before proceed with
> hotplug sequence, it try 5 times with a 150ms of delay between tries
> before giving up.
nice root-causing/reverse engineering of this issue.
What you add here is in practice software polling. Since we have already
a mechanism for that (drm_kms_helper_poll_enable()), I think the better
approach would be to use that, switching that on/off as needed,
similarly to how you enable/disable tc_wa_work in this patch. Sure the
default kms polling time is 10s, not sure if that's even a problem,
given that we are talking about a workaround for broken TypeC dongles
(an up to 750ms latency is not acceptable for sure).
An other, simpler alternative would be to just msleep(), possibly in a
loop retrying the probe. We have quite a few things ahead to fix in the
TypeC code, so adding some complicated WA like this here feels like an
early micro optimization. Especially, since I don't consider HPD
processing a critical fast path (if you do the msleep() outside of
important locks).
Yet another approach would be to take Ville's HPD injection patchset [1]
and use that here and everywhere else in our driver in place of calling
the kms poll code. That would also provide us with a way to have some
IGT test to exercise the driver's HPD processing in general.
--Imre
[1] git://github.com/vsyrjala/linux.git vlv_chv_gpio_hpd_irq
>
> If unpowered TBT dongles shows up in the market this approach should
> be extended to TBT ports too.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_ddi.c | 4 +
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> drivers/gpu/drm/i915/intel_hotplug.c | 108 +++
> 4 files changed, 115 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 03db011caa8e..3fd8c3fa6515 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2639,6 +2639,7 @@ enum hpd_pin intel_hpd_pin_default(struct
> drm_i915_private *dev_priv,
> enum port port);
> bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
> void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
> +void intel_hotplug_tc_wa_work(struct work_struct *work);
>
> /* i915_irq.c */
> static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index b0bb8dfc2ed5..2c149843cacf 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -4258,6 +4258,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> goto err;
>
> intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
> +
> + if (IS_ICELAKE(dev_priv) && intel_port_is_tc(dev_priv, port))
> + INIT_DELAYED_WORK(&intel_dig_port->tc_wa_work,
> + intel_hotplug_tc_wa_work);
> }
>
> /* In theory we don't need the encoder->type check, but leave it just in
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 33b733d37706..fbb6f78ce733 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1242,6 +1242,8 @@ struct intel_digital_port {
> enum intel_display_power_domain ddi_io_power_domain;
> bool tc_legacy_port:1;
> enum tc_port_type tc_type;
> + struct delayed_work tc_wa_work;
> + u8 tc_wa_count;
>
> void (*write_infoframe)(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
> b/drivers/gpu/drm/i915/intel_hotplug.c
> index e027d2b4abe5..9838b60e8f63 100644
> --- a/drivers/gpu/drm/i915/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> @@ -342,6 +342,74 @@ static void i915_digport_work_func(struct work_struct
> *work)
> }
> }
>
> +#define TC_WA_DELAY_MSEC 150
> +#define TC_WA_TRIES 5
> +
> +/*
> + * Test if type-c dongle is responsive return true if so otherwise schedule a
> + * work to try again and return false.
> + */
> +static bool intel_hotplug_tc_wa_test(struct intel_digital_port *dig_port)
> +{
> + struct intel_dp *intel_dp = &dig_port->dp;
> + u8 buffer;
> +
> + dig_port->tc_wa_count++;
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Set ->connectors_changed to force HDCP updates
== Series Details == Series: drm/i915: Set ->connectors_changed to force HDCP updates URL : https://patchwork.freedesktop.org/series/56089/ State : warning == Summary == $ dim checkpatch origin/drm-tip e2f23aecb4c1 drm/i915: Set ->connectors_changed to force HDCP updates -:29: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Set ->connectors_changed to force HDCP updates
On Fri, Feb 01, 2019 at 03:55:19PM +0100, Daniel Vetter wrote:
> ->mode_changed will be eaten by fastset, which is now enabled by
> default on at least some platforms. Once we have modeset-less hdcp, we
> need to go back to ->mode_changed (or maybe directly setting
> ->update_pipe) to avoid the modeset.
>
> Cc: Maarten Lankhorst
> Cc: Hans de Goede
> Cc: Ramalingam C
> Signed-off-by: Daniel Vetter
I think this was broken by the patch to enable fastset everywhere:
Fixes: d19f958db23c ("drm/i915: Enable fastset for non-boot modesets.")
But we also don't have any hdcp tests in CI, because the shard runs don't
have hdcp capable outputs :-/
-Daniel
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
> b/drivers/gpu/drm/i915/intel_hdcp.c
> index ce7ba3a9c000..7da25a7bfccb 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -864,7 +864,7 @@ void intel_hdcp_atomic_check(struct drm_connector
> *connector,
>
> crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
> new_state->crtc);
> - crtc_state->mode_changed = true;
> + crtc_state->connectors_changed = true;
> }
>
> /* Implements Part 3 of the HDCP authorization procedure */
> --
> 2.20.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] [PULL] drm-misc-next
Hi Dave, Daniel, Here is the drm-misc-next PR for this week. Thanks! Maxime drm-misc-next-2019-02-01: drm-misc-next for 5.1: UAPI Changes: Cross-subsystem Changes: Core Changes: - Split out some part of drm_crtc_helper.h into drm_probe_helper.h - DRIVER_* flags improvements - New tasks on the TODO-list - Improvements to the documentation Driver Changes: - Continual of drmP.h removal in multiple drivers - Removal of FBINFO_(FLAG_)DEFAULT in multiple drivers - sun4i: Addition of the A23 support, multiple fixes for the tiled formats - atmel-hlcdc: Fix of clipping and rotation properties - qxl: various BO-related improvements, prime and generic fbdev emulation support - dw-hdmi: Support for HDMI2.0 2160p modes and YUV420 output - New Sitronix ST7701 panel driver - New Kingdisplay KD097D04 panel driver - New LeMaker BL035-RGB-002 panel driver - New PDA 91-00156-A0 panel driver The following changes since commit 8ca4fd0406b41a872055048d694f3702d8eddb76: Merge tag 'drm-intel-next-2019-01-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2019-01-24 19:44:16 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-02-01 for you to fetch changes up to ba9877e2361c46cae3841181aea61e55fc2309b9: drm/bridge: dw-hdmi: add support for YUV420 output (2019-02-01 13:15:10 +0100) drm-misc-next for 5.1: UAPI Changes: Cross-subsystem Changes: Core Changes: - Split out some part of drm_crtc_helper.h into drm_probe_helper.h - DRIVER_* flags improvements - New tasks on the TODO-list - Improvements to the documentation Driver Changes: - Continual of drmP.h removal in multiple drivers - Removal of FBINFO_(FLAG_)DEFAULT in multiple drivers - sun4i: Addition of the A23 support, multiple fixes for the tiled formats - atmel-hlcdc: Fix of clipping and rotation properties - qxl: various BO-related improvements, prime and generic fbdev emulation support - dw-hdmi: Support for HDMI2.0 2160p modes and YUV420 output - New Sitronix ST7701 panel driver - New Kingdisplay KD097D04 panel driver - New LeMaker BL035-RGB-002 panel driver - New PDA 91-00156-A0 panel driver Chen-Yu Tsai (5): dt-bindings: display: sun4i-drm: Add compatible strings for A23 display drm/sun4i: backend: Remove BGRX from list of supported formats drm/sun4i: layer: Assign backend pointer before calling DRM helpers drm/sun4i: layer: support just backend formats when frontend is unavailable drm/sun4i: Add support for A23 display pipeline Cristian Birsan (1): dt-bindings: display: Add support for PDA 91-00156-A0 panel Damian Kos (1): drm/rockchip: fix for mailbox read validation. Daniel Vetter (10): drm: Split out drm_probe_helper.h drm/doc: Add a warning to drm_dev_is_unplugged drm/: Don't set FBINFO_(FLAG_)DEFAULT drm/irq: Don't check for DRIVER_HAVE_IRQ in drm_irq_(un)install drm: Switch DRIVER_ flags to an enum drm/irq: Ditch DRIVER_IRQ_SHARED drm/doc: fix VRR_ENABLED casing drm/doc: Task to rename CMA helpers drm/doc: Move hdmi infoframe docs drm/doc: Drop chapter "KMS Initialization and Cleanup" Eugen Hristev (2): dt-bindings: Add vendor prefix for PDA Precision Design Associates, Inc. drm/panel: simple: Add support for PDA 91-00156-A0 panel Frediano Ziglio (1): drm/qxl: change the way slot is detected Gerd Hoffmann (22): drm/qxl: drop ttm_mem_reg arg from qxl_hw_surface_alloc() drm/qxl: drop unused qxl_fb_virtual_address drm/qxl: simplify slot management drm/qxl: drop unused fields from struct qxl_device drm/qxl: use separate offset spaces for the two slots / ttm memory types. drm/qxl: allow both PRIV and VRAM placement for QXL_GEM_DOMAIN_SURFACE drm/qxl: use QXL_GEM_DOMAIN_SURFACE for shadow bo. drm/qxl: use QXL_GEM_DOMAIN_SURFACE for dumb gem objects drm/qxl: move qxl_primary_apply_cursor to correct place drm/qxl: drop unused offset parameter from qxl_io_create_primary() drm/qxl: track primary bo drm/qxl: use shadow bo directly drm/qxl: cover all crtcs in shadow bo. drm/qxl: use qxl_num_crtc directly drm/qxl: implement prime kmap/kunmap drm/qxl: use generic fbdev emulation drm/qxl: remove dead qxl fbdev emulation code drm/qxl: implement qxl_gem_prime_(un)pin drm/qxl: add mode/framebuffer check functions drm/qxl: add qxl_add_mode helper function drm/qxl: use kernel mode db drm/qxl: use ttm_tt Gustavo A. R. Silva (2): drm/via: mark expected switch fall-throughs drm/savage: mark expected switch fall-throughs Heiko Stuebner (1): drm/rockchip: check yuv2yuv existence before assigning window data Jagan
[Intel-gfx] [PATCH] drm/i915: Set ->connectors_changed to force HDCP updates
->mode_changed will be eaten by fastset, which is now enabled by default on at least some platforms. Once we have modeset-less hdcp, we need to go back to ->mode_changed (or maybe directly setting ->update_pipe) to avoid the modeset. Cc: Maarten Lankhorst Cc: Hans de Goede Cc: Ramalingam C Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hdcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c index ce7ba3a9c000..7da25a7bfccb 100644 --- a/drivers/gpu/drm/i915/intel_hdcp.c +++ b/drivers/gpu/drm/i915/intel_hdcp.c @@ -864,7 +864,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, crtc_state = drm_atomic_get_new_crtc_state(new_state->state, new_state->crtc); - crtc_state->mode_changed = true; + crtc_state->connectors_changed = true; } /* Implements Part 3 of the HDCP authorization procedure */ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_mocs_settings: Allow hangs around reset tests
To inject a GPU hang, we should ask the kernel first if it is legal to
do so.
Signed-off-by: Chris Wilson
---
tests/i915/gem_mocs_settings.c | 54 +-
1 file changed, 34 insertions(+), 20 deletions(-)
diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
index 967223f1b..5b3b6bc1e 100644
--- a/tests/i915/gem_mocs_settings.c
+++ b/tests/i915/gem_mocs_settings.c
@@ -453,26 +453,40 @@ igt_main
continue;
for (unsigned mode = NONE; mode < MAX_MOCS_TEST_MODES; mode++) {
- for (unsigned flags = 0; flags < ALL_MOCS_FLAGS + 1;
flags++) {
- /* Trying to test non-render engines for
dirtying MOCS
-* values from one context having effect on
different
-* context is bound to fail - only render
engine is
-* doing context save/restore of MOCS registers.
-* Let's also limit testing values on
non-default
-* contexts to render-only.
-*/
- if (flags && e->exec_id != I915_EXEC_RENDER)
- continue;
-
- igt_subtest_f("mocs-%s%s%s-%s",
- test_modes[mode],
- flags & MOCS_NON_DEFAULT_CTX ?
"-ctx": "",
- flags & MOCS_DIRTY_VALUES ?
"-dirty" : "",
- e->name) {
- if (flags & (MOCS_NON_DEFAULT_CTX |
MOCS_DIRTY_VALUES))
- gem_require_contexts(fd);
-
- run_test(fd, e->exec_id | e->flags,
flags, mode);
+ igt_subtest_group {
+ igt_hang_t hang = {};
+
+ igt_fixture {
+ if (mode == RESET)
+ hang = igt_allow_hang(fd, 0, 0);
+ }
+
+ for (unsigned flags = 0; flags < ALL_MOCS_FLAGS
+ 1; flags++) {
+ /* Trying to test non-render engines
for dirtying MOCS
+* values from one context having
effect on different
+* context is bound to fail - only
render engine is
+* doing context save/restore of MOCS
registers.
+* Let's also limit testing values on
non-default
+* contexts to render-only.
+*/
+ if (flags && e->exec_id !=
I915_EXEC_RENDER)
+ continue;
+
+ igt_subtest_f("mocs-%s%s%s-%s",
+ test_modes[mode],
+ flags &
MOCS_NON_DEFAULT_CTX ? "-ctx": "",
+ flags & MOCS_DIRTY_VALUES
? "-dirty" : "",
+ e->name) {
+ if (flags &
(MOCS_NON_DEFAULT_CTX | MOCS_DIRTY_VALUES))
+
gem_require_contexts(fd);
+
+ run_test(fd, e->exec_id |
e->flags, flags, mode);
+ }
+ }
+
+ igt_fixture {
+ if (mode == RESET)
+ igt_disallow_hang(fd, hang);
}
}
}
--
2.20.1
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[Intel-gfx] [PATCH i-g-t] i915/query: Update topology info to match reality
CI has a HSW GT1 with a single subslice. Accept this a possible truth
value.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106600
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
tests/i915/query.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/query.c b/tests/i915/query.c
index 764adc8fc..9ddd81f10 100644
--- a/tests/i915/query.c
+++ b/tests/i915/query.c
@@ -456,7 +456,7 @@ test_query_topology_known_pci_ids(int fd, int devid)
switch (dev_info->gt) {
case 1:
igt_assert_eq(n_slices, 1);
- igt_assert(n_subslices == 2 || n_subslices == 3);
+ igt_assert(n_subslices == 1 || n_subslices == 2 || n_subslices
== 3);
break;
case 2:
igt_assert_eq(n_slices, 1);
--
2.20.1
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[Intel-gfx] [PATCH i-g-t] i915/query: Update topology info to match reality
CI has a HSW GT1 with a single subslice. Accept this a possible truth
value.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106600
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
tests/i915/query.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/query.c b/tests/i915/query.c
index 764adc8fc..949858812 100644
--- a/tests/i915/query.c
+++ b/tests/i915/query.c
@@ -456,7 +456,7 @@ test_query_topology_known_pci_ids(int fd, int devid)
switch (dev_info->gt) {
case 1:
igt_assert_eq(n_slices, 1);
- igt_assert(n_subslices == 2 || n_subslices == 3);
+ igt_assert(n_sublices == 1 || n_subslices == 2 || n_subslices
== 3);
break;
case 2:
igt_assert_eq(n_slices, 1);
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915/cmdparser: whitelist needed predicate registers for Anv
Quoting Lionel Landwerlin (2019-01-11 19:53:36)
> There is no reason not to whitelist those registers. In particular
> MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
> other registers to predicate other commands.
Link to userspace changes?
Regards, Joonas
>
> Signed-off-by: Lionel Landwerlin
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +-
> drivers/gpu/drm/i915/i915_reg.h| 2 ++
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 95478db9998b..c5bf14c3f540 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -549,6 +549,8 @@ static const struct drm_i915_reg_descriptor
> gen7_render_regs[] = {
> REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
> REG64(MI_PREDICATE_SRC0),
> REG64(MI_PREDICATE_SRC1),
> + REG64(MI_PREDICATE_DATA),
> + REG32(MI_PREDICATE_RESULT),
> REG32(GEN7_3DPRIM_END_OFFSET),
> REG32(GEN7_3DPRIM_START_VERTEX),
> REG32(GEN7_3DPRIM_VERTEX_COUNT),
> @@ -1382,6 +1384,8 @@ int i915_cmd_parser_get_version(struct drm_i915_private
> *dev_priv)
> *the parser enabled.
> * 9. Don't whitelist or handle oacontrol specially, as ownership
> *for oacontrol state is moving to i915-perf.
> +* 10. Whitelist predicate data/result registers for conditional
> +* rendering in Anv.
> */
> - return 9;
> + return 10;
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ca8026ec0655..5c05d73eec8f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -461,6 +461,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
> #define MI_PREDICATE_SRC1 _MMIO(0x2408)
> #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
> +#define MI_PREDICATE_DATA _MMIO(0x2410)
> +#define MI_PREDICATE_RESULT_MMIO(0x2418)
>
> #define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
> #define LOWER_SLICE_ENABLED (1 << 0)
> --
> 2.20.1
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Avoid uninterruptible spinning in debugfs
== Series Details ==
Series: drm/i915: Avoid uninterruptible spinning in debugfs
URL : https://patchwork.freedesktop.org/series/56079/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5524 -> Patchwork_12117
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/56079/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12117 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965]
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: PASS -> FAIL [fdo#109485]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@basic-rte:
- fi-bsw-kefka: FAIL [fdo#108800] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (49 -> 45)
--
Additional (2): fi-hsw-4770r fi-ivb-3770
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-icl-y
Build changes
-
* Linux: CI_DRM_5524 -> Patchwork_12117
CI_DRM_5524: 94a739eee19da904a40e612464dfa9f1326accfb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12117: 4bf798b7ee1a9d54d571dc9c0470be480b209c9c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4bf798b7ee1a drm/i915: Avoid uninterruptible spinning in debugfs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12117/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Avoid uninterruptible spinning in debugfs (rev2)
== Series Details == Series: drm/i915: Avoid uninterruptible spinning in debugfs (rev2) URL : https://patchwork.freedesktop.org/series/56079/ State : failure == Summary == Applying: drm/i915: Avoid uninterruptible spinning in debugfs error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_debugfs.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Avoid uninterruptible spinning in debugfs When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Avoid uninterruptible spinning in debugfs
If we get caught in a kernel bug, we may never idle. Let the user regain
control of their system^Wterminal by responding to SIGINT!
v2: Push the signal checking into the loop around flush_work.
Reported-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c| 14 --
drivers/gpu/drm/i915/i915_gem.c| 10 +++---
drivers/gpu/drm/i915/i915_utils.h | 18 +++---
.../gpu/drm/i915/selftests/i915_gem_context.c | 5 -
4 files changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f3fa31d840f5..44fa34f4ebbc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3945,12 +3945,14 @@ i915_drop_caches_set(void *data, u64 val)
i915_gem_shrink_all(i915);
fs_reclaim_release(GFP_KERNEL);
- if (val & DROP_IDLE) {
- do {
- if (READ_ONCE(i915->gt.active_requests))
- flush_delayed_work(&i915->gt.retire_work);
- drain_delayed_work(&i915->gt.idle_work);
- } while (READ_ONCE(i915->gt.awake));
+ if (val & DROP_IDLE && READ_ONCE(i915->gt.awake)) {
+ if (drain_delayed_work_state(&i915->gt.retire_work,
+TASK_INTERRUPTIBLE) ||
+ drain_delayed_work_state(&i915->gt.idle_work,
+TASK_INTERRUPTIBLE)) {
+ ret = -EINTR;
+ goto out;
+ }
}
if (val & DROP_FREED)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4067eeaee78a..e47d53e9b634 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4499,13 +4499,17 @@ int i915_gem_suspend(struct drm_i915_private *i915)
mutex_unlock(&i915->drm.struct_mutex);
i915_reset_flush(i915);
- drain_delayed_work(&i915->gt.retire_work);
-
/*
* As the idle_work is rearming if it detects a race, play safe and
* repeat the flush until it is definitely idle.
*/
- drain_delayed_work(&i915->gt.idle_work);
+ if (drain_delayed_work_state(&i915->gt.retire_work,
+TASK_INTERRUPTIBLE) ||
+ drain_delayed_work_state(&i915->gt.idle_work,
+TASK_INTERRUPTIBLE)) {
+ ret = -EINTR;
+ goto err_unlock;
+ }
/*
* Assert that we successfully flushed all the work and
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index fcc751aa1ea8..6866b85e4239 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -25,6 +25,8 @@
#ifndef __I915_UTILS_H
#define __I915_UTILS_H
+#include
+
#undef WARN_ON
/* Many gcc seem to no see through this and fall over :( */
#if 0
@@ -148,12 +150,22 @@ static inline void __list_del_many(struct list_head *head,
* by requeueing itself. Note, that if the worker never cancels itself,
* we will spin forever.
*/
-static inline void drain_delayed_work(struct delayed_work *dw)
+
+static inline int drain_delayed_work_state(struct delayed_work *dw, int state)
{
do {
- while (flush_delayed_work(dw))
- ;
+ do {
+ if (signal_pending_state(state, current))
+ return -EINTR;
+ } while (flush_delayed_work(dw));
} while (delayed_work_pending(dw));
+
+ return 0;
+}
+
+static inline void drain_delayed_work(struct delayed_work *dw)
+{
+ drain_delayed_work_state(dw, 0);
}
static inline const char *yesno(bool v)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 2b423128002c..a87998b90bf6 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -1686,8 +1686,11 @@ static int __igt_switch_to_kernel_context(struct
drm_i915_private *i915,
/* XXX Bonus points for proving we are the kernel context! */
mutex_unlock(&i915->drm.struct_mutex);
- drain_delayed_work(&i915->gt.idle_work);
+ err = drain_delayed_work_state(&i915->gt.idle_work,
+ TASK_KILLABLE);
mutex_lock(&i915->drm.struct_mutex);
+ if (err)
+ return -EINTR;
}
if (igt_flush_test(i915, I915_WAIT_LOCKED))
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Avoid uninterruptible spinning in debugfs
Quoting Chris Wilson (2019-02-01 10:22:48)
> If we get caught in a kernel bug, we may never idle. Let the user regain
> control of their system^Wterminal by responding to SIGINT!
>
> Reported-by: Tvrtko Ursulin
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index f3fa31d840f5..baf8b548621c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3947,6 +3947,10 @@ i915_drop_caches_set(void *data, u64 val)
>
> if (val & DROP_IDLE) {
> do {
> + if (signal_pending(current)) {
> + ret = -EINTR;
> + goto out;
> + }
> if (READ_ONCE(i915->gt.active_requests))
> flush_delayed_work(&i915->gt.retire_work);
> drain_delayed_work(&i915->gt.idle_work);
Drain delayed work will want similar treatment.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Avoid uninterruptible spinning in debugfs
If we get caught in a kernel bug, we may never idle. Let the user regain
control of their system^Wterminal by responding to SIGINT!
Reported-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f3fa31d840f5..baf8b548621c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3947,6 +3947,10 @@ i915_drop_caches_set(void *data, u64 val)
if (val & DROP_IDLE) {
do {
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ goto out;
+ }
if (READ_ONCE(i915->gt.active_requests))
flush_delayed_work(&i915->gt.retire_work);
drain_delayed_work(&i915->gt.idle_work);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cfl: Adding another PCI Device ID.
== Series Details ==
Series: drm/i915/cfl: Adding another PCI Device ID.
URL : https://patchwork.freedesktop.org/series/56075/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5522_full -> Patchwork_12116_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12116_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@reset-stress:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: PASS -> FAIL [fdo#103166] +1
Possible fixes
* igt@gem_exec_blt@cold:
- shard-glk: DMESG-WARN [fdo#105763] / [fdo#106538] -> PASS
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_setmode@basic:
- shard-hsw: FAIL [fdo#99912] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (6 -> 4)
--
Missing(2): shard-skl shard-iclb
Build changes
-
* Linux: CI_DRM_5522 -> Patchwork_12116
CI_DRM_5522: 3f287cb6d4ae4689eb7c53e4c25f0fba3df16438 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12116: ab594f4fdd62f7e043b94092a218ba1b52af293d @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12116/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Enable fastboot by default on VLV and CHV
Hi, On 31-01-19 14:36, Maarten Lankhorst wrote: Op 29-01-2019 om 15:22 schreef Hans de Goede: We really want to have fastboot enabled by default to avoid an ugly modeset during boot. Currently we are enabling fastboot by default on gen9+ (Skylake and newer). The intention is to enable it on older generations after it has seen more testing on gen9+. VLV and CHV devices are still being sold in stores today, as such it is desirable to also enable fastboot by default on these now. I've extensively tested fastboot=1 support on over 50 different Bay- and Cherry-Trail devices. Testing DSI and eDP panels as well as HDMI output (and even DP over Type-C on one device). All 50 devices work fine with fastboot=1. On 2 devices their DSI panel turns black as soon as the i915 driver loads when fastboot=0, so having fastboot enabled is required for these 2 to work properly (for lack of a better fix). Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/intel_display.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d756d7358292..0ff42a38023c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11672,7 +11672,15 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv) return i915_modparams.fastboot; /* Enable fastboot by default on Skylake and newer */ - return INTEL_GEN(dev_priv) >= 9; + if (INTEL_GEN(dev_priv) >= 9) + return true; + + /* Enable fastboot by default on VLV and CHV */ + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + return true; + + /* Disabled by default on all others */ + return false; } static bool Reviewed-by: Maarten Lankhorst Thank you, pushed. Regards, Hans ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/11] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
Quoting Chris Wilson (2019-01-31 16:20:37) > Quoting Chris Wilson (2019-01-31 13:39:50) > > Quoting Tvrtko Ursulin (2019-01-31 13:19:31) > > > > > > On 30/01/2019 02:19, Chris Wilson wrote: > > > > Having introduced per-context seqno, we now have a means to identity > > > > progress across the system without feel of rollback as befell the > > > > global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in > > > > advance of submission safe in the knowledge that our target seqno and > > > > address is stable. > > > > > > > > However, since we are telling the GPU to busy-spin on the target address > > > > until it matches the signaling seqno, we only want to do so when we are > > > > sure that busy-spin will be completed quickly. To achieve this we only > > > > submit the request to HW once the signaler is itself executing (modulo > > > > preemption causing us to wait longer), and we only do so for default and > > > > above priority requests (so that idle priority tasks never themselves > > > > hog the GPU waiting for others). > > > > > > It could be milliseconds though. I think apart from media-bench saying > > > this is faster, we would need to look at performance per Watt as well. > > > > All throughput measurements are substantially faster, as you would > > expect, and inter-engine latency decreased. I would hope it would > > powergate/rc6 the EU while the CS was spinning, but I don't know :) > > Fwiw, it's about the power cost of simply spinning with the CS without > any additional cost of utilizing the engine. Another interesting data point is that the *total* energy consumed for a latency bound test that passes a piece of work from one engine to the next reduced by 30%, with a speed increase of nearly 100% (on glk). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for restore WaEnableFloatBlendOptimization
Quoting Patchwork (2019-02-01 05:05:57) > == Series Details == > > Series: restore WaEnableFloatBlendOptimization > URL : https://patchwork.freedesktop.org/series/56071/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_5521_full -> Patchwork_12113_full > > > Summary > --- > > **SUCCESS** > > No regressions found. Which means either it failed completely (and had no effect) or it worked and successfully hid itself from gem_workarounds. Thanks for the patch, pushed! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
