Re: [Intel-gfx] [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
On Fri, Mar 08, 2019 at 02:39:36PM -0800, Rodrigo Vivi wrote: Given that every platform so far has had different oa configurations, that looks to be a hasty assumption that future platforms will be fixed. I know... But my hope is that at some point it gets stabilized. Well, or at least start with this so any other gen11 could reuse and gen12 would start with that and change later for >= gen12 and on... If it's different, there's no harm in making this assumption now and then later change to cover the differences. Making it consistent everywhere allows to more easily add the next platform. Lucas De Marchi -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add new ICL PCI ID
== Series Details ==
Series: drm/i915: Add new ICL PCI ID
URL : https://patchwork.freedesktop.org/series/57769/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5728_full -> Patchwork_12427_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12427_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_fence@basic-wait-default:
- {shard-iclb}: WARN -> SKIP
* igt@kms_draw_crc@draw-method-rgb565-render-untiled:
- {shard-iclb}: PASS -> DMESG-WARN +1
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
- {shard-iclb}: NOTRUN -> SKIP +11
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc:
- {shard-iclb}: PASS -> FAIL +13
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-iclb}: NOTRUN -> FAIL +3
* igt@kms_plane@pixel-format-pipe-b-planes:
- {shard-iclb}: INCOMPLETE [fdo#107713] -> SKIP
* igt@kms_psr@psr2_sprite_plane_onoff:
- {shard-iclb}: SKIP [fdo#109441] -> FAIL
* igt@runner@aborted:
- {shard-iclb}: ( 7 FAIL ) [fdo#106612] -> ( 8 FAIL )
Known issues
Here are the changes found in Patchwork_12427_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_softpin@noreloc-s3:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@i915_pm_lpsp@screens-disabled:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +59
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: PASS -> SKIP [fdo#109271]
* igt@kms_atomic_transition@3x-modeset-transitions-nonblocking:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_busy@basic-flip-d:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#107725] / [fdo#108145]
* igt@kms_color@pipe-a-ctm-max:
- shard-glk: NOTRUN -> FAIL [fdo#108147]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-glk: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_crc@cursor-size-change:
- shard-skl: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: PASS -> FAIL [fdo#102670]
* igt@kms_cursor_legacy@pipe-c-single-bo:
- shard-kbl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +8
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-apl: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-kbl: PASS -> DMESG-WARN [fdo#103313] / [fdo#103558] /
[fdo#105602]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +20
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-skl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@prime_nv_api@i915_nv_import_vs_close:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +31
Possible fixes
* igt@gem_ctx_isolation@vcs0-none:
- {shard-iclb}: DMESG-FAIL -> PASS
* igt@gem_eio@wait-wedge-immediate:
- {shard-iclb}: WARN -> PASS
* igt@gem_tiled_pread_pwrite:
-
[Intel-gfx] ✓ Fi.CI.BAT: success for HDCP2.2 Phase II (rev3)
== Series Details ==
Series: HDCP2.2 Phase II (rev3)
URL : https://patchwork.freedesktop.org/series/57232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5729 -> Patchwork_12430
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57232/revisions/3/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12430:
### IGT changes ###
Possible regressions
* {igt@kms_content_protection@srm} (NEW):
- fi-icl-u3: NOTRUN -> DMESG-WARN
- fi-icl-u2: NOTRUN -> SKIP
New tests
-
New tests have been introduced between CI_DRM_5729 and Patchwork_12430:
### New IGT tests (1) ###
* igt@kms_content_protection@srm:
- Statuses : 1 dmesg-warn(s) 38 skip(s)
- Exec time: [0.0, 80.18] s
Known issues
Here are the changes found in Patchwork_12430 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +59
* igt@gem_exec_basic@gtt-bsd2:
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +60
* igt@gem_exec_basic@readonly-bsd1:
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +60
* igt@i915_module_load@reload-with-fault-injection:
- fi-skl-6770hq: PASS -> DMESG-WARN [fdo#108529] +2
* igt@i915_pm_rpm@basic-rte:
- fi-byt-n2820: NOTRUN -> FAIL [fdo#108800]
- fi-bsw-kefka: NOTRUN -> FAIL [fdo#108800]
* igt@kms_addfb_basic@addfb25-y-tiled-small:
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] +60
* igt@kms_busy@basic-flip-a:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@basic-flip-c:
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +65
* igt@kms_chamelium@hdmi-edid-read:
- fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +49
* igt@kms_content_protection@atomic:
- fi-skl-gvtdvm: NOTRUN -> FAIL [fdo#108597] / [fdo#108739] +1
- fi-ivb-3520m: NOTRUN -> SKIP [fdo#109271] +2
- fi-elk-e7500: NOTRUN -> SKIP [fdo#109271] +2
- fi-whl-u: NOTRUN -> SKIP [fdo#109271] +2
- fi-cfl-8700k: NOTRUN -> SKIP [fdo#109271] +2
- fi-skl-guc: NOTRUN -> SKIP [fdo#109271] +2
- fi-apl-guc: NOTRUN -> FAIL [fdo#108597] / [fdo#108739] +1
* igt@kms_content_protection@legacy:
- fi-cfl-guc: NOTRUN -> SKIP [fdo#109271] +2
- fi-snb-2600:NOTRUN -> SKIP [fdo#109271] +2
- fi-skl-6770hq: NOTRUN -> FAIL [fdo#108597] / [fdo#108739]
- fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +2
- fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +2
- fi-cfl-8109u: NOTRUN -> FAIL [fdo#108739] +1
- fi-kbl-guc: NOTRUN -> SKIP [fdo#109271] +2
- fi-bdw-gvtdvm: NOTRUN -> SKIP [fdo#109271] +2
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +2
- fi-bwr-2160:NOTRUN -> SKIP [fdo#109271] +2
- fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +2
- fi-ivb-3770:NOTRUN -> SKIP [fdo#109271] +2
- fi-kbl-8809g: NOTRUN -> SKIP [fdo#109271] +2
* {igt@kms_content_protection@srm} (NEW):
- fi-ilk-650: NOTRUN -> SKIP [fdo#109271] +2
- fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +2
- fi-cfl-8109u: NOTRUN -> SKIP [fdo#109271]
- fi-bdw-5557u: NOTRUN -> SKIP [fdo#109271] +2
- fi-kbl-7567u: NOTRUN -> SKIP [fdo#109271]
- fi-skl-6600u: NOTRUN -> SKIP [fdo#109271] +2
- fi-kbl-7560u: NOTRUN -> SKIP [fdo#109271] +2
- fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +2
- {fi-skl-lmem}: NOTRUN -> SKIP [fdo#109271]
- fi-apl-guc: NOTRUN -> SKIP [fdo#109271]
- fi-skl-6770hq: NOTRUN -> SKIP [fdo#109271] +1
- fi-skl-6700k2: NOTRUN -> SKIP [fdo#109271]
- fi-skl-6260u: NOTRUN -> SKIP [fdo#109271]
- fi-skl-gvtdvm: NOTRUN -> SKIP [fdo#109271]
- fi-kbl-x1275: NOTRUN -> SKIP [fdo#109271]
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: PASS -> SKIP [fdo#109271] +33
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: PASS -> FAIL [fdo#103167]
- fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814]
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@bad-source:
- fi-skl-6770hq: PASS -> DMESG-WARN [fdo#108833]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: NOTRUN -> FAIL
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: split pll functions (rev2)
== Series Details == Series: drm/i915/icl: split pll functions (rev2) URL : https://patchwork.freedesktop.org/series/57618/ State : success == Summary == CI Bug Log - changes from CI_DRM_5729 -> Patchwork_12429 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57618/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12429 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +55 * igt@gem_cpu_reloc@basic: - fi-kbl-7560u: PASS -> INCOMPLETE [fdo#103665] * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +57 * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@kms_addfb_basic@addfb25-y-tiled-small: - fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] +56 * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-b: - fi-gdg-551: PASS -> FAIL [fdo#103182] * igt@kms_busy@basic-flip-c: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62 * igt@kms_chamelium@hdmi-edid-read: - fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +46 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: PASS -> FAIL [fdo#103167] - fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814] * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: FAIL [fdo#103167] -> PASS [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (40 -> 40) -- Additional (6): fi-bsw-n3050 fi-hsw-peppy fi-snb-2520m fi-bsw-kefka fi-byt-n2820 fi-byt-clapper Missing(6): fi-hsw-4770r fi-ilk-m540 fi-bsw-cyan fi-pnv-d510 fi-bdw-samus fi-snb-2600 Build changes - * Linux: CI_DRM_5729 -> Patchwork_12429 CI_DRM_5729: b50390674ed3eff49d1926a86acfee68b5565093 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4878: 478615b1edba88559386ba80ccbf0f035f3360a9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12429: b9a4ea2378aebaf7cf8ddc2ba9240987b1b4141e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b9a4ea2378ae drm/i915/icl: remove intel_dpll_is_combophy() 40a0b15f85de drm/i915/icl: split combo and tbt pll funcs bf5537c76b30 drm/i915/icl: split combo and mg pll disable a0ff7e3c4302 drm/i915/icl: split pll enable in three steps d70c7ad97f50 drm/i915/icl: split combo and mg pll enable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12429/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP2.2 Phase II (rev3)
== Series Details == Series: HDCP2.2 Phase II (rev3) URL : https://patchwork.freedesktop.org/series/57232/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: debugfs: HDCP2.2 capability read Okay! Commit: drm: Add Content protection type property Okay! Commit: drm/i915: Attach content type property Okay! Commit: drm/i915: HDCP SRM parsing and revocation check -drivers/gpu/drm/i915/selftests/../i915_drv.h:3553:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3559:16: warning: expression using sizeof(void) Commit: drm/i915/sysfs: Node for hdcp srm Okay! Commit: drm: Add CP downstream_info property Okay! Commit: drm/i915: Populate downstream info for HDCP1.4 Okay! Commit: drm/i915: Populate downstream info for HDCP2.2 Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP2.2 Phase II (rev3)
== Series Details ==
Series: HDCP2.2 Phase II (rev3)
URL : https://patchwork.freedesktop.org/series/57232/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
60917522d34f drm/i915: debugfs: HDCP2.2 capability read
009fe1f15b74 drm: Add Content protection type property
-:58: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#58: FILE: drivers/gpu/drm/drm_connector.c:860:
+};
+DRM_ENUM_NAME_FN(drm_get_content_protection_type_name,
-:118: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#118: FILE: drivers/gpu/drm/drm_connector.c:1600:
+ ARRAY_SIZE(
-:176: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#176: FILE: include/drm/drm_connector.h:1325:
+int drm_connector_attach_content_protection_type_property(
total: 0 errors, 0 warnings, 3 checks, 146 lines checked
ba73cfe13f70 drm/i915: Attach content type property
-:88: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#88: FILE: drivers/gpu/drm/i915/intel_hdcp.c:1785:
+ ret = drm_connector_attach_content_protection_type_property(
total: 0 errors, 0 warnings, 1 checks, 117 lines checked
519754d1c377 drm/i915: HDCP SRM parsing and revocation check
d56237cd1cf3 drm/i915/sysfs: Node for hdcp srm
-:31: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IWUSR' are not preferred.
Consider using octal permissions '0200'.
#31: FILE: drivers/gpu/drm/i915/i915_sysfs.c:591:
+ .attr = {.name = "hdcp_srm", .mode = S_IWUSR},
total: 0 errors, 1 warnings, 0 checks, 50 lines checked
791f8c417ccc drm: Add CP downstream_info property
-:96: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#96: FILE: drivers/gpu/drm/drm_connector.c:1650:
+int drm_connector_attach_content_protection_downstream_property(
-:129: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#129: FILE: drivers/gpu/drm/drm_connector.c:1683:
+int drm_connector_update_content_protection_downstream_property(
-:140: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#140: FILE: drivers/gpu/drm/drm_connector.c:1694:
+ ret = drm_property_replace_global_blob(dev,
+ >content_protection_downstream_blob_ptr,
-:173: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#173: FILE: include/drm/drm_connector.h:1334:
+int drm_connector_attach_content_protection_downstream_property(
-:175: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#175: FILE: include/drm/drm_connector.h:1336:
+int drm_connector_update_content_protection_downstream_property(
total: 0 errors, 0 warnings, 5 checks, 174 lines checked
0e674e6c9f58 drm/i915: Populate downstream info for HDCP1.4
-:84: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#84: FILE: drivers/gpu/drm/i915/intel_hdcp.c:814:
+ if (drm_connector_update_content_protection_downstream_property(
-:96: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#96: FILE: drivers/gpu/drm/i915/intel_hdcp.c:852:
+ if
(drm_connector_update_content_protection_downstream_property(
-:107: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#107: FILE: drivers/gpu/drm/i915/intel_hdcp.c:1907:
+ ret = drm_connector_attach_content_protection_downstream_property(
total: 0 errors, 0 warnings, 3 checks, 107 lines checked
714ef374c15a drm/i915: Populate downstream info for HDCP2.2
-:53: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#53: FILE: drivers/gpu/drm/i915/intel_hdcp.c:1677:
+ drm_connector_update_content_protection_downstream_property(
-:64: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#64: FILE: drivers/gpu/drm/i915/intel_hdcp.c:1688:
+ drm_connector_update_content_protection_downstream_property(
-:87: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#87: FILE: drivers/gpu/drm/i915/intel_hdcp.c:1713:
+ drm_connector_update_content_protection_downstream_property(
total: 0 errors, 0 warnings, 3 checks, 76 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
== Series Details ==
Series: series starting with [1/3] drm/i915/gen11+: First assume next platforms
will inherit stuff
URL : https://patchwork.freedesktop.org/series/57768/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5728_full -> Patchwork_12426_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12426_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_coherency:
- {shard-iclb}: PASS -> DMESG-WARN +9
* igt@i915_selftest@live_contexts:
- {shard-iclb}: DMESG-FAIL [fdo#108569] -> DMESG-WARN
* igt@i915_selftest@live_gem:
- {shard-iclb}: PASS -> DMESG-FAIL +2
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- {shard-iclb}: NOTRUN -> SKIP +30
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- {shard-iclb}: NOTRUN -> FAIL +8
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- {shard-iclb}: PASS -> FAIL +16
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- {shard-iclb}: FAIL [fdo#108948] -> SKIP
* igt@perf_pmu@busy-start-vecs0:
- {shard-iclb}: PASS -> INCOMPLETE
* igt@runner@aborted:
- {shard-iclb}: ( 7 FAIL ) [fdo#106612] -> ( 4 FAIL )
Known issues
Here are the changes found in Patchwork_12426_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_userptr_blits@process-exit-gtt:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +41
* igt@i915_pm_lpsp@screens-disabled:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +54
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@gem-execbuf-stress-extra-wait:
- shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807] +1
* igt@i915_pm_rpm@modeset-lpsp:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
- shard-apl: PASS -> FAIL [fdo#109660]
* igt@kms_atomic_transition@3x-modeset-transitions-nonblocking:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_busy@basic-flip-d:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-a-ctm-max:
- shard-glk: NOTRUN -> FAIL [fdo#108147]
* igt@kms_cursor_crc@cursor-128x42-random:
- shard-glk: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: PASS -> FAIL [fdo#104894] +1
* igt@prime_nv_api@i915_nv_import_vs_close:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +31
Possible fixes
* igt@gem_ctx_isolation@vcs0-none:
- {shard-iclb}: DMESG-FAIL -> PASS
* igt@gem_eio@wait-wedge-immediate:
- {shard-iclb}: WARN -> PASS
* igt@gem_fence_thrash@bo-write-verify-y:
- {shard-iclb}:
[Intel-gfx] [PATCH v2 3/8] drm/i915: Attach content type property
Attaches the content type property for HDCP2.2 capable connectors.
Implements the update of content type from property and apply the
restriction on HDCP version selection.
v2:
s/cp_content_type/content_protection_type [daniel]
disable at hdcp_atomic_check to avoid check at atomic_set_property
[Maarten]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_ddi.c | 21 +++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_hdcp.c | 30 +-
3 files changed, 41 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7e3b4e8fdf3a..8702938ec376 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3499,7 +3499,8 @@ static void intel_enable_ddi(struct intel_encoder
*encoder,
/* Enable hdcp if it's desired */
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
+ intel_hdcp_enable(to_intel_connector(conn_state->connector),
+ (u8)conn_state->content_protection_type);
}
static void intel_disable_ddi_dp(struct intel_encoder *encoder,
@@ -3562,21 +3563,29 @@ static void intel_ddi_update_pipe_dp(struct
intel_encoder *encoder,
intel_panel_update_backlight(encoder, crtc_state, conn_state);
}
-static void intel_ddi_update_pipe(struct intel_encoder *encoder,
+static void intel_ddi_update_hdcp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
- intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
-
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
+ intel_hdcp_enable(to_intel_connector(conn_state->connector),
+ (u8)conn_state->content_protection_type);
else if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
intel_hdcp_disable(to_intel_connector(conn_state->connector));
}
+static void intel_ddi_update_pipe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
+
+ intel_ddi_update_hdcp(encoder, crtc_state, conn_state);
+}
+
static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
const struct intel_crtc_state
*pipe_config,
enum port port)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f143aaf57e55..186fa035f491 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2172,7 +2172,7 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
struct drm_connector_state *new_state);
int intel_hdcp_init(struct intel_connector *connector,
const struct intel_hdcp_shim *hdcp_shim);
-int intel_hdcp_enable(struct intel_connector *connector);
+int intel_hdcp_enable(struct intel_connector *connector, u8 content_type);
int intel_hdcp_disable(struct intel_connector *connector);
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
bool intel_hdcp_capable(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index ff9497e5c591..ff1bbbee2e52 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1782,6 +1782,13 @@ static void intel_hdcp2_init(struct intel_connector
*connector)
return;
}
+ ret = drm_connector_attach_content_protection_type_property(
+ >base);
+ if (ret) {
+ kfree(hdcp->port_data.streams);
+ return;
+ }
+
hdcp->hdcp2_supported = true;
}
@@ -1811,7 +1818,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return 0;
}
-int intel_hdcp_enable(struct intel_connector *connector)
+int intel_hdcp_enable(struct intel_connector *connector, u8 content_type)
{
struct intel_hdcp *hdcp = >hdcp;
unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS;
@@ -1822,6 +1829,7 @@ int intel_hdcp_enable(struct intel_connector *connector)
mutex_lock(>mutex);
WARN_ON(hdcp->value ==
[Intel-gfx] [PATCH v2 5/8] drm/i915/sysfs: Node for hdcp srm
Binary Sysfs entry is created to pass the HDCP SRM table into
kerel for the HDCP authentication purpose.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_sysfs.c | 32 +++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 41313005af42..4621e944a24e 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -576,6 +576,36 @@ static void i915_setup_error_capture(struct device *kdev)
{}
static void i915_teardown_error_capture(struct device *kdev) {}
#endif
+static ssize_t
+i915_srm_write(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *attr, char *buf,
+ loff_t offset, size_t count)
+{
+ struct device *kdev = kobj_to_dev(kobj);
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+
+ return intel_hdcp_srm_update(dev_priv, buf, count);
+}
+
+static const struct bin_attribute srm_attrs = {
+ .attr = {.name = "hdcp_srm", .mode = S_IWUSR},
+ .read = NULL,
+ .write = i915_srm_write,
+ .mmap = NULL,
+ .private = (void *)0
+};
+
+static void i915_setup_hdcp_srm(struct device *kdev)
+{
+ if (sysfs_create_bin_file(>kobj, _attrs))
+ DRM_ERROR("error_state sysfs setup failed\n");
+}
+
+static void i915_teardown_hdcp_srm(struct device *kdev)
+{
+ sysfs_remove_bin_file(>kobj, _attrs);
+}
+
void i915_setup_sysfs(struct drm_i915_private *dev_priv)
{
struct device *kdev = dev_priv->drm.primary->kdev;
@@ -623,12 +653,14 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
DRM_ERROR("RPS sysfs setup failed\n");
i915_setup_error_capture(kdev);
+ i915_setup_hdcp_srm(kdev);
}
void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
{
struct device *kdev = dev_priv->drm.primary->kdev;
+ i915_teardown_hdcp_srm(kdev);
i915_teardown_error_capture(kdev);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 6/8] drm: Add CP downstream_info property
This patch adds a optional CP downstream info blob property to the
connectors. This enables the Userspace to read the information of HDCP
authenticated downstream topology.
Driver will updated this blob with all downstream information at the
end of the authentication.
In case userspace configures this platform as repeater, then this
information is needed for the authentication with upstream HDCP
transmitter.
v2:
%s/cp_downstream/content_protection_downstream [daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++
drivers/gpu/drm/drm_connector.c | 89 +++
include/drm/drm_connector.h | 12 +
include/uapi/drm/drm_mode.h | 27 ++
4 files changed, 132 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index f383d4be5a92..51fa217f99f6 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -826,6 +826,10 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = state->content_protection;
} else if (property == connector->content_protection_type_property) {
*val = state->content_protection_type;
+ } else if (property ==
+ connector->content_protection_downstream_property) {
+ *val = connector->content_protection_downstream_blob_ptr ?
+ connector->content_protection_downstream_blob_ptr->base.id : 0;
} else if (property == config->writeback_fb_id_property) {
/* Writeback framebuffer is one-shot, write and forget */
*val = 0;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 4ce0830e9fb4..3a11624ca73c 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -245,6 +245,7 @@ int drm_connector_init(struct drm_device *dev,
INIT_LIST_HEAD(>modes);
mutex_init(>mutex);
connector->edid_blob_ptr = NULL;
+ connector->content_protection_downstream_blob_ptr = NULL;
connector->status = connector_status_unknown;
connector->display_info.panel_orientation =
DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
@@ -982,6 +983,25 @@ DRM_ENUM_NAME_FN(drm_get_content_protection_type_name,
* authentication process. If content type is changed when
* content_protection is not UNDESIRED, then kernel will disable the HDCP
* and re-enable with new type in the same atomic commit
+ * Content_protection_downstream_info:
+ * This blob property is used to pass the HDCP downstream topology details
+ * of a HDCP encrypted connector, from kernel to userspace.
+ * This provides all required information to userspace, so that userspace
+ * can implement the HDCP repeater using the kernel as downstream ports of
+ * the repeater. as illustrated below:
+ *
+ * HDCP Repeaters
+ * +--+
+ * | |
+ * | | |
+ * | Userspace HDCP Receiver +->KMD HDCP transmitters |
+ * | (Upstream Port) <--+ (Downstream Ports)|
+ * | | |
+ * | |
+ * +--+
+ *
+ * Kernel will populate this blob only when the HDCP authentication is
+ * successful.
*
* max bpc:
* This range property is used by userspace to limit the bit depth. When
@@ -1610,6 +1630,75 @@
drm_connector_attach_content_protection_type_property(struct drm_connector *
}
EXPORT_SYMBOL(drm_connector_attach_content_protection_type_property);
+/**
+ * drm_connector_attach_content_protection_downstream_property - attach content
+ * protection downstream property
+ *
+ * @connector: connector to attach content protection downstream property on.
+ *
+ * This is used to add support for content protection downstream info on
+ * select connectors. when Intel platform is configured as repeater,
+ * this downstream info is used by userspace, to complete the repeater
+ * authentication of HDCP specification with upstream HDCP transmitter.
+ *
+ * The content protection downstream will be set to
+ * _connector_state.content_protection_downstream
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_attach_content_protection_downstream_property(
+ struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_property *prop;
+
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB |
+ DRM_MODE_PROP_IMMUTABLE,
+ "CP_downstream_info", 0);
+ if (!prop)
+ return
[Intel-gfx] [PATCH v2 8/8] drm/i915: Populate downstream info for HDCP2.2
Populates the downstream info for HDCP2.2 encryption also. On success
of encryption Blob is updated.
Additional two variable are added to downstream info blob. Such as
ver_in_force and content type.
v2:
s/cp_downstream/content_protection_downstream [daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 30 +-
include/uapi/drm/drm_mode.h | 3 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 777f40202a15..3350b37375db 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1283,6 +1283,12 @@ static int hdcp2_authentication_key_exchange(struct
intel_connector *connector)
return -EPERM;
}
+ hdcp->downstream_info->ver_in_force = DRM_MODE_HDCP22_IN_FORCE;
+ hdcp->downstream_info->content_type = hdcp->content_type;
+ memcpy(hdcp->downstream_info->bksv, msgs.send_cert.cert_rx.receiver_id,
+ HDCP_2_2_RECEIVER_ID_LEN);
+ hdcp->downstream_info->is_repeater = hdcp->is_repeater;
+
/*
* Here msgs.no_stored_km will hold msgs corresponding to the km
* stored also.
@@ -1474,6 +1480,11 @@ int hdcp2_authenticate_repeater_topology(struct
intel_connector *connector)
return -EPERM;
}
+ hdcp->downstream_info->device_count = device_cnt;
+ hdcp->downstream_info->depth = HDCP_2_2_DEPTH(rx_info[0]);
+ memcpy(hdcp->downstream_info->ksv_list, msgs.recvid_list.receiver_ids,
+ device_cnt * HDCP_2_2_RECEIVER_ID_LEN);
+
ret = hdcp2_verify_rep_topology_prepare_ack(connector,
_list,
_ack);
@@ -1660,6 +1671,13 @@ static int _intel_hdcp2_enable(struct intel_connector
*connector)
if (ret) {
DRM_DEBUG_KMS("HDCP2 Type%d Enabling Failed. (%d)\n",
hdcp->content_type, ret);
+
+ memset(hdcp->downstream_info, 0,
+ sizeof(struct content_protection_downstream_info));
+ drm_connector_update_content_protection_downstream_property(
+ >base,
+ hdcp->downstream_info);
+
return ret;
}
@@ -1667,12 +1685,17 @@ static int _intel_hdcp2_enable(struct intel_connector
*connector)
connector->base.name, connector->base.base.id,
hdcp->content_type);
+ drm_connector_update_content_protection_downstream_property(
+ >base,
+ hdcp->downstream_info);
hdcp->hdcp2_encrypted = true;
+
return 0;
}
static int _intel_hdcp2_disable(struct intel_connector *connector)
{
+ struct intel_hdcp *hdcp = >hdcp;
int ret;
DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being Disabled\n",
@@ -1683,8 +1706,13 @@ static int _intel_hdcp2_disable(struct intel_connector
*connector)
if (hdcp2_deauthenticate_port(connector) < 0)
DRM_DEBUG_KMS("Port deauth failed.\n");
- connector->hdcp.hdcp2_encrypted = false;
+ hdcp->hdcp2_encrypted = false;
+ memset(hdcp->downstream_info, 0,
+ sizeof(struct content_protection_downstream_info));
+ drm_connector_update_content_protection_downstream_property(
+ >base,
+ hdcp->downstream_info);
return ret;
}
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 3973d35c3b57..dc81713d3a07 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -223,6 +223,9 @@ struct content_protection_downstream_info {
/* Version of HDCP authenticated (1.4/2.2) */
__u32 ver_in_force;
+ /* Applicable only for HDCP2.2 */
+ __u8 content_type;
+
/* KSV of immediate HDCP Sink. In Little-Endian Format. */
char bksv[DRM_MODE_HDCP_KSV_LEN];
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/8] drm: Add Content protection type property
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on any HDCP protected display wires.
But Type 1 content can be rendered only on HDCP2.2 protected paths.
So when a userspace sets this property to Type 1 and starts the HDCP
enable, kernel will honour it only if HDCP2.2 authentication is through
for type 1. Else HDCP enable will be failed.
v2:
cp_content_type is replaced with content_protection_type [daniel]
check at atomic_set_property is removed [Maarten]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++
drivers/gpu/drm/drm_connector.c | 63 +++
include/drm/drm_connector.h | 15
include/uapi/drm/drm_mode.h | 4 ++
4 files changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 4eb81f10bc54..f383d4be5a92 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -746,6 +746,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
return -EINVAL;
}
state->content_protection = val;
+ } else if (property == connector->content_protection_type_property) {
+ state->content_protection_type = val;
} else if (property == connector->colorspace_property) {
state->colorspace = val;
} else if (property == config->writeback_fb_id_property) {
@@ -822,6 +824,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = state->scaling_mode;
} else if (property == connector->content_protection_property) {
*val = state->content_protection;
+ } else if (property == connector->content_protection_type_property) {
+ *val = state->content_protection_type;
} else if (property == config->writeback_fb_id_property) {
/* Writeback framebuffer is one-shot, write and forget */
*val = 0;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 07d65a16c623..4ce0830e9fb4 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -853,6 +853,13 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
{ DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
};
+static struct drm_prop_enum_list drm_content_protection_type_enum_list[] = {
+ { DRM_MODE_CONTENT_PROTECTION_TYPE0, "Type 0" },
+ { DRM_MODE_CONTENT_PROTECTION_TYPE1, "Type 1" },
+};
+DRM_ENUM_NAME_FN(drm_get_content_protection_type_name,
+drm_content_protection_type_enum_list)
+
/**
* DOC: standard connector properties
*
@@ -958,6 +965,23 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
* the value transitions from ENABLED to DESIRED. This signifies the link
* is no longer protected and userspace should take appropriate action
* (whatever that might be).
+ * Content_protection_type:
+ * This property is used by the userspace to configure the kernel with
+ * upcoming stream's content type. Content Type of a stream is decided by
+ * the owner of the stream, as Type 0 or Type 1.
+ *
+ * The value of the property can be one the below:
+ * - DRM_MODE_CONTENT_PROTECTION_TYPE0 = 0
+ * Type 0 streams can be transmitted on a link which is encrypted
+ * with HDCP 1.4 or HDCP 2.2.
+ * - DRM_MODE_CONTENT_PROTECTION_TYPE1 = 1
+ * Type 1 streams can be transmitted on a link which is encrypted
+ * only with HDCP2.2.
+ *
+ * Please note this content type is introduced at HDCP2.2 and used in its
+ * authentication process. If content type is changed when
+ * content_protection is not UNDESIRED, then kernel will disable the HDCP
+ * and re-enable with new type in the same atomic commit
*
* max bpc:
* This range property is used by userspace to limit the bit depth. When
@@ -1547,6 +1571,45 @@ int drm_connector_attach_content_protection_property(
}
EXPORT_SYMBOL(drm_connector_attach_content_protection_property);
+/**
+ * drm_connector_attach_content_protection_type_property - attach content
+ * protection type property
+ *
+ * @connector: connector to attach content protection type property on.
+ *
+ * This is used to add support for sending the protected content's stream type
+ * from userspace to kernel on selected connectors. Protected content provider
+ * will decide their type of their content and declare the same to kernel.
+ *
+ * This information will be used during the HDCP2.2 authentication.
+ *
+ * Content type will be set to _connector_state.content_protection_type.
+ *
+ * Returns:
+ *
[Intel-gfx] [PATCH v2 4/8] drm/i915: HDCP SRM parsing and revocation check
Implements the SRM table parsing for HDCP 1.4 and 2.2.
And also revocation check is added at authentication of HDCP1.4
and 2.2
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_hdcp.c | 308 --
include/drm/drm_hdcp.h| 32
5 files changed, 334 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0d743907e7bc..6c396ec0f552 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -873,6 +873,7 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
mutex_init(_priv->wm.wm_mutex);
mutex_init(_priv->pps_mutex);
mutex_init(_priv->hdcp_comp_mutex);
+ mutex_init(_priv->srm_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4ffe19ec698..c6c7cb1ae1b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2054,6 +2054,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ unsigned int revocated_ksv_cnt;
+ u8 *revocated_ksv_list;
+
+ /* Mutex to protect the data about revocated ksvs */
+ struct mutex srm_mutex;
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 186fa035f491..7550f4ed5a98 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2181,6 +2181,8 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv);
void intel_hdcp_component_fini(struct drm_i915_private *dev_priv);
void intel_hdcp_cleanup(struct intel_connector *connector);
void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
+ssize_t intel_hdcp_srm_update(struct drm_i915_private *dev_priv, char *buf,
+ size_t count);
/* intel_psr.c */
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index ff1bbbee2e52..b1fa81666490 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -273,6 +273,62 @@ u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port
*intel_dig_port)
return -EINVAL;
}
+static inline void intel_hdcp_print_ksv(u8 *ksv)
+{
+ DRM_DEBUG_KMS("\t%#04x, %#04x, %#04x, %#04x, %#04x\n", *ksv,
+ *(ksv + 1), *(ksv + 2), *(ksv + 3), *(ksv + 4));
+}
+
+static inline
+struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp)
+{
+ return container_of(hdcp, struct intel_connector, hdcp);
+}
+
+/* Check if any of the KSV is revocated by DCP LLC through SRM table */
+static inline
+bool intel_hdcp_ksvs_revocated(struct intel_hdcp *hdcp, u8 *ksvs, u32
ksv_count)
+{
+ struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+ struct drm_i915_private *dev_priv =
+ intel_dig_port->base.base.dev->dev_private;
+ u32 rev_ksv_cnt, cnt, i, j;
+ u8 *rev_ksv_list;
+
+ mutex_lock(_priv->srm_mutex);
+ rev_ksv_cnt = dev_priv->revocated_ksv_cnt;
+ rev_ksv_list = dev_priv->revocated_ksv_list;
+
+ /* If the Revocated ksv list is empty */
+ if (!rev_ksv_cnt || !rev_ksv_list) {
+ mutex_unlock(_priv->srm_mutex);
+ return false;
+ }
+
+ for (cnt = 0; cnt < ksv_count; cnt++) {
+ rev_ksv_list = dev_priv->revocated_ksv_list;
+ for (i = 0; i < rev_ksv_cnt; i++) {
+ for (j = 0; j < DRM_HDCP_KSV_LEN; j++)
+ if (*(ksvs + j) != *(rev_ksv_list + j)) {
+ break;
+ } else if (j == (DRM_HDCP_KSV_LEN - 1)) {
+ DRM_DEBUG_KMS("Revocated KSV is ");
+ intel_hdcp_print_ksv(ksvs);
+ mutex_unlock(_priv->srm_mutex);
+ return true;
+ }
+ /* Move the offset to next KSV in the revocated list */
+ rev_ksv_list += DRM_HDCP_KSV_LEN;
+ }
+
+ /* Iterate to next ksv_offset */
+ ksvs += DRM_HDCP_KSV_LEN;
+ }
+ mutex_unlock(_priv->srm_mutex);
+ return false;
+}
+
static
int
[Intel-gfx] [PATCH v2 7/8] drm/i915: Populate downstream info for HDCP1.4
Implements drm blob property content_protection_downstream_info
property on HDCP capable connectors.
Downstream topology info is gathered across authentication stages
and stored in intel_hdcp. When HDCP authentication is complete,
new blob with latest downstream topology information is updated to
content_protection_downstream_info property.
v2:
%s/cp_downstream/content_protection_downstream [daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_hdcp.c | 35 ++-
include/drm/drm_hdcp.h| 1 +
include/uapi/drm/drm_mode.h | 5 +
4 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7550f4ed5a98..4e722702897a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -482,6 +482,8 @@ struct intel_hdcp {
wait_queue_head_t cp_irq_queue;
atomic_t cp_irq_count;
int cp_irq_count_cached;
+
+ struct content_protection_downstream_info *downstream_info;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index b1fa81666490..777f40202a15 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -580,6 +580,9 @@ int intel_hdcp_auth_downstream(struct intel_hdcp *hdcp,
if (num_downstream == 0)
return -EINVAL;
+ hdcp->downstream_info->device_count = num_downstream;
+ hdcp->downstream_info->depth = DRM_HDCP_DEPTH(bstatus[1]);
+
ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL);
if (!ksv_fifo)
return -ENOMEM;
@@ -593,6 +596,8 @@ int intel_hdcp_auth_downstream(struct intel_hdcp *hdcp,
return -EPERM;
}
+ memcpy(hdcp->downstream_info->ksv_list, ksv_fifo,
+ num_downstream * DRM_HDCP_KSV_LEN);
/*
* When V prime mismatches, DP Spec mandates re-read of
* V prime atleast twice.
@@ -694,15 +699,20 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
return -EPERM;
}
+ hdcp->downstream_info->ver_in_force = DRM_MODE_HDCP14_IN_FORCE;
+ memcpy(hdcp->downstream_info->bksv, bksv.shim, DRM_MODE_HDCP_KSV_LEN);
+
I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
ret = shim->repeater_present(intel_dig_port, _present);
if (ret)
return ret;
- if (repeater_present)
+ if (repeater_present) {
I915_WRITE(HDCP_REP_CTL,
intel_hdcp_get_repeater_ctl(intel_dig_port));
+ hdcp->downstream_info->is_repeater = true;
+ }
ret = shim->toggle_signalling(intel_dig_port, true);
if (ret)
@@ -798,6 +808,14 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
return ret;
}
+ memset(hdcp->downstream_info, 0,
+ sizeof(struct content_protection_downstream_info));
+
+ if (drm_connector_update_content_protection_downstream_property(
+ >base,
+ connector->hdcp.downstream_info))
+ DRM_ERROR("Downstream_info update failed.\n");
+
DRM_DEBUG_KMS("HDCP is disabled\n");
return 0;
}
@@ -831,6 +849,10 @@ static int _intel_hdcp_enable(struct intel_connector
*connector)
ret = intel_hdcp_auth(connector);
if (!ret) {
connector->hdcp.hdcp_encrypted = true;
+ if
(drm_connector_update_content_protection_downstream_property(
+ >base,
+ connector->hdcp.downstream_info))
+ DRM_ERROR("Downstream_info update failed.\n");
return 0;
}
@@ -1882,6 +1904,17 @@ int intel_hdcp_init(struct intel_connector *connector,
if (ret)
return ret;
+ ret = drm_connector_attach_content_protection_downstream_property(
+ >base);
+ if (ret)
+ return ret;
+
+ hdcp->downstream_info =
+ kzalloc(sizeof(struct content_protection_downstream_info),
+ GFP_KERNEL);
+ if (!hdcp->downstream_info)
+ return -ENOMEM;
+
hdcp->shim = shim;
mutex_init(>mutex);
INIT_DELAYED_WORK(>check_work, intel_hdcp_check_work);
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 652aaf5d658e..654a170f03eb 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -23,6 +23,7 @@
#define DRM_HDCP_V_PRIME_PART_LEN 4
#define DRM_HDCP_V_PRIME_NUM_PARTS 5
#define DRM_HDCP_NUM_DOWNSTREAM(x)
[Intel-gfx] [PATCH v2 0/8] HDCP2.2 Phase II
HDCP2.2 phase-II mojorly adds below features: Addition of three connector properties CP_Content_Type CP_Downstream_Info Addition of binary sysfs "hdcp_srm" parsing for HDCP1.4 and 2.2 SRM table Once HDCP1.4/2.2 authentication is completed gathering the all downstream topology for userspace Extending debugfs entry to provide the HDCP2.2 capability too. CP_Content_Type: This property is used to indicate the content type classification of a stream. Which indicate the HDCP version required for the rendering of that streams. This conten type is one of the parameter in the HDCP2.2 authentication flow, as even downstream repeaters will mandate the HDCP version requirement. Two values possible for content type of a stream: Type 0: Stream can be rendered only on HDCP encrypted link no restriction on HDCP versions. Type 1: Stream can be rendered only on HDCP2.2 encrypted link. There is a parallel effort in #wayland community to add the support for HDCP2.2 along with content type support. Patches are under review in #wayland community. CP_downstream_info: This blob property is used by the kernel to pass the downstream topology of the HDCP encrypted port to the userspace. This is used by the userspace to implement the HDCP repeater, which KMD implementing the HDCP transmitters(downstream ports) and userspace implementing the upstream port(HDCP receiver). Discussion is on going to add the downstream_info support in the weston HDCP stack. hdcp_srm: write only binary sysfs used by the userspace to pass the SRM table of HDCP1.4 and 2.2. These are nothing but revocated list of receiver IDs of the HDCP sinks. KMD will use this list to identify the revocated devices in the HDCP authentication and deny the hdcp encryption to it. v2: srm is passed through binary sysfs [Daniel] CP abbreviation is expanded except for downstream_info [Daniel] restrictions at atomic_set_property is removed [Maarten] upon content type change durin encryption, HDCP is restarted within kernel [Maarten] Resending it as previous submission was failed find the mentioned igt version. Series can be cloned from github https://github.com/ramalingampc2008/drm-tip.git hdcp2_2_p2_v2 Test-with: <20190308163049.9016-2-ramalinga...@intel.com> Ramalingam C (8): drm/i915: debugfs: HDCP2.2 capability read drm: Add Content protection type property drm/i915: Attach content type property drm/i915: HDCP SRM parsing and revocation check drm/i915/sysfs: Node for hdcp srm drm: Add CP downstream_info property drm/i915: Populate downstream info for HDCP1.4 drm/i915: Populate downstream info for HDCP2.2 drivers/gpu/drm/drm_atomic_uapi.c | 8 + drivers/gpu/drm/drm_connector.c | 152 +++ drivers/gpu/drm/i915/i915_debugfs.c | 13 +- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_sysfs.c | 32 +++ drivers/gpu/drm/i915/intel_ddi.c| 21 +- drivers/gpu/drm/i915/intel_drv.h| 7 +- drivers/gpu/drm/i915/intel_hdcp.c | 405 ++-- include/drm/drm_connector.h | 27 ++ include/drm/drm_hdcp.h | 33 +++ include/uapi/drm/drm_mode.h | 39 +++ 12 files changed, 712 insertions(+), 32 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/8] drm/i915: debugfs: HDCP2.2 capability read
Adding the HDCP2.2 capability of HDCP src and sink info into debugfs
entry "i915_hdcp_sink_capability"
This helps the userspace tests to skip the HDCP2.2 test on non HDCP2.2
sinks.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +++--
drivers/gpu/drm/i915/intel_drv.h| 1 +
drivers/gpu/drm/i915/intel_hdcp.c | 2 +-
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6a90558de213..8ef097c492d6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4755,6 +4755,7 @@ static int i915_hdcp_sink_capability_show(struct seq_file
*m, void *data)
{
struct drm_connector *connector = m->private;
struct intel_connector *intel_connector = to_intel_connector(connector);
+ bool hdcp_cap, hdcp2_cap;
if (connector->status != connector_status_connected)
return -ENODEV;
@@ -4765,8 +4766,16 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
seq_printf(m, "%s:%d HDCP version: ", connector->name,
connector->base.id);
- seq_printf(m, "%s ", !intel_hdcp_capable(intel_connector) ?
- "None" : "HDCP1.4");
+ hdcp_cap = intel_hdcp_capable(intel_connector);
+ hdcp2_cap = intel_hdcp2_capable(intel_connector);
+
+ if (hdcp_cap)
+ seq_puts(m, "HDCP1.4 ");
+ if (hdcp2_cap)
+ seq_puts(m, "HDCP2.2 ");
+
+ if (!hdcp_cap && !hdcp2_cap)
+ seq_puts(m, "None");
seq_puts(m, "\n");
return 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 58483f8245aa..f143aaf57e55 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2176,6 +2176,7 @@ int intel_hdcp_enable(struct intel_connector *connector);
int intel_hdcp_disable(struct intel_connector *connector);
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
bool intel_hdcp_capable(struct intel_connector *connector);
+bool intel_hdcp2_capable(struct intel_connector *connector);
void intel_hdcp_component_init(struct drm_i915_private *dev_priv);
void intel_hdcp_component_fini(struct drm_i915_private *dev_priv);
void intel_hdcp_cleanup(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 9ce09f67776d..ff9497e5c591 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -76,7 +76,7 @@ bool intel_hdcp_capable(struct intel_connector *connector)
}
/* Is HDCP2.2 capable on Platform and Sink */
-static bool intel_hdcp2_capable(struct intel_connector *connector)
+bool intel_hdcp2_capable(struct intel_connector *connector)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 4/5] drm/i915/icl: split combo and tbt pll funcs
Like was done for MG and combo, now finish the per-type split of the
vfunc by moving TBT out of the combo functions. Now we can completely
remove icl_pll_id_to_enable_reg() since each PLL type passes all the
information via arguments.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 74 +++
1 file changed, 54 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 7f50769699ab..10801be25c68 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2956,16 +2956,6 @@ icl_get_dpll(struct intel_crtc *crtc, struct
intel_crtc_state *crtc_state,
return pll;
}
-static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
-{
- if (intel_dpll_is_combophy(id))
- return CNL_DPLL_ENABLE(id);
- else if (id == DPLL_ID_ICL_TBTPLL)
- return TBT_PLL_ENABLE;
-
- return MG_PLL_ENABLE(icl_pll_id_to_tc_port(id));
-}
-
static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
@@ -3030,7 +3020,8 @@ static bool mg_pll_get_hw_state(struct drm_i915_private
*dev_priv,
static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
-struct intel_dpll_hw_state *hw_state)
+struct intel_dpll_hw_state *hw_state,
+i915_reg_t enable_reg)
{
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -3042,7 +3033,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
if (!wakeref)
return false;
- val = I915_READ(icl_pll_id_to_enable_reg(id));
+ val = I915_READ(enable_reg);
if (!(val & PLL_ENABLE))
goto out;
@@ -3055,6 +3046,21 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
return ret;
}
+static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll,
+ struct intel_dpll_hw_state *hw_state)
+{
+ return icl_pll_get_hw_state(dev_priv, pll, hw_state,
+ CNL_DPLL_ENABLE(pll->info->id));
+}
+
+static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll,
+struct intel_dpll_hw_state *hw_state)
+{
+ return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE);
+}
+
static void icl_dpll_write(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -3154,7 +3160,7 @@ static void icl_pll_enable(struct drm_i915_private
*dev_priv,
static void combo_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+ i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -3171,6 +3177,24 @@ static void combo_pll_enable(struct drm_i915_private
*dev_priv,
/* DVFS post sequence would be here. See the comment above. */
}
+static void tbt_pll_enable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE);
+
+ icl_dpll_write(dev_priv, pll);
+
+ /*
+* DVFS pre sequence would be here, but in our driver the cdclk code
+* paths should already be setting the appropriate voltage, hence we do
+* nothing here.
+*/
+
+ icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE);
+
+ /* DVFS post sequence would be here. See the comment above. */
+}
+
static void mg_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -3232,9 +3256,13 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+ icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
+}
- icl_pll_disable(dev_priv, pll, enable_reg);
+static void tbt_pll_disable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE);
}
static void mg_pll_disable(struct drm_i915_private *dev_priv,
@@ -3268,10 +3296,16 @@ static void icl_dump_hw_state(struct drm_i915_private
*dev_priv,
[Intel-gfx] [PATCH v2 1/5] drm/i915/icl: split combo and mg pll enable
Let's start using the vfuncs to differentiate MG and Combo PLLs. The end
goal is to decouple the type of the PLL from the IDs since the latter
are likely to change from one platform to another. This also makes the
code easier to read by not having lots of if/else chains on leaf
functions.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e4ec73d415d9..3b3de99756d6 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3117,10 +3117,10 @@ static void icl_mg_pll_write(struct drm_i915_private
*dev_priv,
}
static void icl_pll_enable(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ i915_reg_t enable_reg)
{
const enum intel_dpll_id id = pll->info->id;
- i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
u32 val;
val = I915_READ(enable_reg);
@@ -3157,6 +3157,23 @@ static void icl_pll_enable(struct drm_i915_private
*dev_priv,
/* DVFS post sequence would be here. See the comment above. */
}
+static void combo_pll_enable(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll)
+{
+ i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+
+ icl_pll_enable(dev_priv, pll, enable_reg);
+}
+
+static void mg_pll_enable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ i915_reg_t enable_reg =
+ MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+
+ icl_pll_enable(dev_priv, pll, enable_reg);
+}
+
static void icl_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -3218,13 +3235,13 @@ static void icl_dump_hw_state(struct drm_i915_private
*dev_priv,
}
static const struct intel_shared_dpll_funcs icl_pll_funcs = {
- .enable = icl_pll_enable,
+ .enable = combo_pll_enable,
.disable = icl_pll_disable,
.get_hw_state = icl_pll_get_hw_state,
};
static const struct intel_shared_dpll_funcs mg_pll_funcs = {
- .enable = icl_pll_enable,
+ .enable = mg_pll_enable,
.disable = icl_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
};
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/5] drm/i915/icl: split pll enable in three steps
Create separate functions to 1) enable power, 2) write pll config, and
3) enable pll. Doing this it makes it easier to share the functions for
the different PLL types by passing the right arguments.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 56 ++-
1 file changed, 37 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 3b3de99756d6..f7b618e08cab 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3116,11 +3116,10 @@ static void icl_mg_pll_write(struct drm_i915_private
*dev_priv,
POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
}
-static void icl_pll_enable(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll,
- i915_reg_t enable_reg)
+static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll,
+i915_reg_t enable_reg)
{
- const enum intel_dpll_id id = pll->info->id;
u32 val;
val = I915_READ(enable_reg);
@@ -3133,28 +3132,23 @@ static void icl_pll_enable(struct drm_i915_private
*dev_priv,
*/
if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE,
PLL_POWER_STATE, 1))
- DRM_ERROR("PLL %d Power not enabled\n", id);
-
- if (intel_dpll_is_combophy(id) || id == DPLL_ID_ICL_TBTPLL)
- icl_dpll_write(dev_priv, pll);
- else
- icl_mg_pll_write(dev_priv, pll);
+ DRM_ERROR("PLL %d Power not enabled\n", pll->info->id);
+}
- /*
-* DVFS pre sequence would be here, but in our driver the cdclk code
-* paths should already be setting the appropriate voltage, hence we do
-* nothign here.
-*/
+static void icl_pll_enable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll,
+ i915_reg_t enable_reg)
+{
+ u32 val;
val = I915_READ(enable_reg);
val |= PLL_ENABLE;
I915_WRITE(enable_reg, val);
+ /* Timeout is actually 600us. */
if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK,
- 1)) /* 600us actually. */
- DRM_ERROR("PLL %d not locked\n", id);
-
- /* DVFS post sequence would be here. See the comment above. */
+ 1))
+ DRM_ERROR("PLL %d not locked\n", pll->info->id);
}
static void combo_pll_enable(struct drm_i915_private *dev_priv,
@@ -3162,7 +3156,19 @@ static void combo_pll_enable(struct drm_i915_private
*dev_priv,
{
i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+ icl_pll_power_enable(dev_priv, pll, enable_reg);
+
+ icl_dpll_write(dev_priv, pll);
+
+ /*
+* DVFS pre sequence would be here, but in our driver the cdclk code
+* paths should already be setting the appropriate voltage, hence we do
+* nothing here.
+*/
+
icl_pll_enable(dev_priv, pll, enable_reg);
+
+ /* DVFS post sequence would be here. See the comment above. */
}
static void mg_pll_enable(struct drm_i915_private *dev_priv,
@@ -3171,7 +3177,19 @@ static void mg_pll_enable(struct drm_i915_private
*dev_priv,
i915_reg_t enable_reg =
MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+ icl_pll_power_enable(dev_priv, pll, enable_reg);
+
+ icl_mg_pll_write(dev_priv, pll);
+
+ /*
+* DVFS pre sequence would be here, but in our driver the cdclk code
+* paths should already be setting the appropriate voltage, hence we do
+* nothing here.
+*/
+
icl_pll_enable(dev_priv, pll, enable_reg);
+
+ /* DVFS post sequence would be here. See the comment above. */
}
static void icl_pll_disable(struct drm_i915_private *dev_priv,
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/5] drm/i915/icl: split combo and mg pll disable
Like was done in the enable case, split the implementation of the
disable for MG and Combo PLLs.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 30 ---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index f7b618e08cab..7f50769699ab 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3193,10 +3193,9 @@ static void mg_pll_enable(struct drm_i915_private
*dev_priv,
}
static void icl_pll_disable(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ i915_reg_t enable_reg)
{
- const enum intel_dpll_id id = pll->info->id;
- i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
u32 val;
/* The first steps are done by intel_ddi_post_disable(). */
@@ -3213,7 +3212,7 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
/* Timeout is actually 1us. */
if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, 0, 1))
- DRM_ERROR("PLL %d locked\n", id);
+ DRM_ERROR("PLL %d locked\n", pll->info->id);
/* DVFS post sequence would be here. See the comment above. */
@@ -3227,7 +3226,24 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
*/
if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE, 0,
1))
- DRM_ERROR("PLL %d Power not disabled\n", id);
+ DRM_ERROR("PLL %d Power not disabled\n", pll->info->id);
+}
+
+static void combo_pll_disable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+
+ icl_pll_disable(dev_priv, pll, enable_reg);
+}
+
+static void mg_pll_disable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ i915_reg_t enable_reg =
+ MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+
+ icl_pll_disable(dev_priv, pll, enable_reg);
}
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -3254,13 +3270,13 @@ static void icl_dump_hw_state(struct drm_i915_private
*dev_priv,
static const struct intel_shared_dpll_funcs icl_pll_funcs = {
.enable = combo_pll_enable,
- .disable = icl_pll_disable,
+ .disable = combo_pll_disable,
.get_hw_state = icl_pll_get_hw_state,
};
static const struct intel_shared_dpll_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
- .disable = icl_pll_disable,
+ .disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
};
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 5/5] drm/i915/icl: remove intel_dpll_is_combophy()
This is only used in intel_display() and shouldn't be needed there.
We don't want to keep converting from pll id to pll type so just remove
the function.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_display.c | 3 ---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 5 -
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 963b4bd69dbb..18b12136ead5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9610,9 +9610,6 @@ static void icelake_get_ddi_pll(struct drm_i915_private
*dev_priv,
temp = I915_READ(DPCLKA_CFGCR0_ICL) &
DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
-
- if (WARN_ON(!intel_dpll_is_combophy(id)))
- return;
} else if (intel_port_is_tc(dev_priv, port)) {
id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
} else {
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 10801be25c68..c76eb43cc0cc 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2649,11 +2649,6 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port
tc_port)
return tc_port + DPLL_ID_ICL_MGPLL1;
}
-bool intel_dpll_is_combophy(enum intel_dpll_id id)
-{
- return id == DPLL_ID_ICL_DPLL0 || id == DPLL_ID_ICL_DPLL1;
-}
-
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
u32 *target_dco_khz,
struct intel_dpll_hw_state *state)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/5] drm/i915/icl: split pll functions
v2 of https://patchwork.freedesktop.org/series/57618/ Only difference is that patch 2 got replaced with a different one. Instead of passing a function pointer to write the pll, split the function in three and pass the different arguments for each type of plls as suggested by Ville. I think this is neater and cleaner as well. Lucas De Marchi (5): drm/i915/icl: split combo and mg pll enable drm/i915/icl: split pll enable in three steps drm/i915/icl: split combo and mg pll disable drm/i915/icl: split combo and tbt pll funcs drm/i915/icl: remove intel_dpll_is_combophy() drivers/gpu/drm/i915/intel_display.c | 3 - drivers/gpu/drm/i915/intel_dpll_mgr.c | 174 +++--- 2 files changed, 127 insertions(+), 50 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Add broadcast RGB property for DP MST
== Series Details ==
Series: series starting with [1/5] drm/i915: Add broadcast RGB property for DP
MST
URL : https://patchwork.freedesktop.org/series/57766/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5728_full -> Patchwork_12424_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12424_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack:
- {shard-iclb}: NOTRUN -> SKIP +11
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- {shard-iclb}: PASS -> FAIL +24
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- {shard-iclb}: NOTRUN -> FAIL +1
* igt@perf_pmu@busy-accuracy-50-vecs0:
- {shard-iclb}: PASS -> TIMEOUT
* igt@perf_pmu@busy-start-vecs0:
- {shard-iclb}: PASS -> INCOMPLETE +1
* igt@runner@aborted:
- {shard-iclb}: ( 7 FAIL ) [fdo#106612] -> ( 5 FAIL )
Known issues
Here are the changes found in Patchwork_12424_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_cpu_reloc@full:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@gem_userptr_blits@process-exit-gtt:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +41
* igt@i915_pm_lpsp@screens-disabled:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +73
* igt@i915_pm_rpm@modeset-lpsp:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@kms_atomic_transition@3x-modeset-transitions-nonblocking:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_busy@basic-flip-d:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-a-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
- shard-glk: NOTRUN -> FAIL [fdo#108147]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_crc@cursor-128x42-random:
- shard-glk: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-size-change:
- shard-skl: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-skl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-glk: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@prime_nv_api@i915_nv_import_vs_close:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +31
Possible fixes
* igt@gem_ctx_isolation@vcs0-none:
- {shard-iclb}: DMESG-FAIL -> PASS
* igt@gem_eio@wait-wedge-immediate:
- {shard-iclb}: WARN -> PASS
* igt@i915_pm_rpm@basic-pci-d3-state:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS
* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_color@pipe-a-legacy-gamma:
- shard-skl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-128x42-random:
- shard-skl: FAIL [fdo#103232] ->
Re: [Intel-gfx] [PATCH] drm/i915: relax debug BUG_ON() for closed context in hw_id pin
On 2019.03.08 08:31:51 +, Chris Wilson wrote: > Quoting Zhenyu Wang (2019-03-08 07:52:37) > > Current GVT created context is marked closed as not to be used for > > host user. But its hw_id should still be used. So this is to relax > > debug BUG_ON() in __i915_gem_context_pin_hw_id() for GVT contexts > > which can use force single submission flag to identify. > > The alternative strategy would be to always pin the id for GVT. How many > gvt contexts? One per host or one per client? Or we don't mark them as > closed (not so keen on that as it does provide some protection). > Currently one per VM guest, always pin the id would also be good. > I think I'd rather delete the GEM_BUG_ON() if it's not invariant -- we > only escape it firing for kernel contexts because they pin their id. I think anyway we'd better pin id for gvt context, as it's good to keep it for one VM cycle. thanks -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/19] i915/gem_ppgtt: Estimate resource usage and bail if it means swapping!
== Series Details == Series: series starting with [01/19] i915/gem_ppgtt: Estimate resource usage and bail if it means swapping! URL : https://patchwork.freedesktop.org/series/57764/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5729 -> IGTPW_2581 Summary --- **FAILURE** Serious unknown changes coming with IGTPW_2581 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_2581, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/57764/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in IGTPW_2581: ### IGT changes ### Possible regressions * igt@i915_selftest@live_hangcheck: - fi-kbl-8809g: PASS -> DMESG-FAIL Known issues Here are the changes found in IGTPW_2581 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +56 * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +57 * igt@i915_pm_rpm@basic-rte: - fi-bsw-kefka: NOTRUN -> FAIL [fdo#108800] * igt@i915_selftest@live_evict: - fi-bsw-kefka: NOTRUN -> DMESG-WARN [fdo#107709] * igt@i915_selftest@live_hangcheck: - fi-ilk-650: PASS -> INCOMPLETE [fdo#109723] * igt@kms_addfb_basic@addfb25-y-tiled-small: - fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] +56 * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-b: - fi-gdg-551: PASS -> FAIL [fdo#103182] * igt@kms_busy@basic-flip-c: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62 * igt@kms_chamelium@hdmi-edid-read: - fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +46 * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814] - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> FAIL [fdo#107709] [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814 [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109723]: https://bugs.freedesktop.org/show_bug.cgi?id=109723 Participating hosts (40 -> 42) -- Additional (6): fi-bsw-n3050 fi-hsw-peppy fi-snb-2520m fi-bsw-kefka fi-byt-n2820 fi-byt-clapper Missing(4): fi-bsw-cyan fi-ilk-m540 fi-icl-u2 fi-bdw-samus Build changes - * IGT: IGT_4878 -> IGTPW_2581 CI_DRM_5729: b50390674ed3eff49d1926a86acfee68b5565093 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_2581: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2581/ IGT_4878: 478615b1edba88559386ba80ccbf0f035f3360a9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Testlist changes == +++ 207 lines --- 4 lines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2581/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register (rev2) URL : https://patchwork.freedesktop.org/series/57454/ State : success == Summary == CI Bug Log - changes from CI_DRM_5729 -> Patchwork_12428 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57454/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12428 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +56 * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57 * igt@i915_pm_rpm@basic-rte: - fi-bsw-kefka: NOTRUN -> FAIL [fdo#108800] * igt@kms_addfb_basic@addfb25-y-tiled-small: - fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] +56 * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: PASS -> FAIL [fdo#103167] - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#107362] Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@kms_busy@basic-flip-a: - fi-gdg-551: FAIL [fdo#103182] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (40 -> 38) -- Additional (4): fi-bsw-kefka fi-byt-n2820 fi-byt-clapper fi-bsw-n3050 Missing(6): fi-ilk-m540 fi-bdw-5557u fi-skl-6770hq fi-bsw-cyan fi-bwr-2160 fi-bdw-samus Build changes - * Linux: CI_DRM_5729 -> Patchwork_12428 CI_DRM_5729: b50390674ed3eff49d1926a86acfee68b5565093 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4878: 478615b1edba88559386ba80ccbf0f035f3360a9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12428: d7269a507b168f2d093476ccd9a14d24740024a4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d7269a507b16 drm/i915: remove ICP_PP_CONTROL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12428/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add new ICL PCI ID
== Series Details == Series: drm/i915: Add new ICL PCI ID URL : https://patchwork.freedesktop.org/series/57769/ State : success == Summary == CI Bug Log - changes from CI_DRM_5728 -> Patchwork_12427 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57769/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12427 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57 * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@kms_busy@basic-flip-c: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +52 * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@kms_busy@basic-flip-a: - fi-gdg-551: FAIL [fdo#103182] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (42 -> 42) -- Additional (3): fi-byt-j1900 fi-byt-clapper fi-pnv-d510 Missing(3): fi-ilk-m540 fi-bdw-samus fi-icl-u3 Build changes - * Linux: CI_DRM_5728 -> Patchwork_12427 CI_DRM_5728: 78b288a16a32e8828f93c5e2e9eb3c1b73bfdce7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4877: d15ad69be07a987d5c2ba408201b287adae8ca59 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12427: 60a43fb85c302abc653d3d793b611e50745c446d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 60a43fb85c30 drm/i915: Add new ICL PCI ID == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12427/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: remove ICP_PP_CONTROL
This register was placed in the middle of the PP_STATUS definition
instead of together with the PP_CONTROL where it should. Since it's not
used and there are no current plans to use it, just remove the
definition.
v2: remove the define rather than moving it.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 11 ---
1 file changed, 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0cd7a836799..4a855befa838 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4692,17 +4692,6 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
#define PP_ON(1 << 31)
-
-#define _PP_CONTROL_1 0xc7204
-#define _PP_CONTROL_2 0xc7304
-#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
- _PP_CONTROL_2)
-#define POWER_CYCLE_DELAY_MASK(0x1f << 4)
-#define POWER_CYCLE_DELAY_SHIFT 4
-#define VDD_OVERRIDE_FORCE(1 << 3)
-#define BACKLIGHT_ENABLE (1 << 2)
-#define PWR_DOWN_ON_RESET (1 << 1)
-#define PWR_STATE_TARGET (1 << 0)
/*
* Indicates that all dependencies of the panel are on:
*
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
== Series Details == Series: series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff URL : https://patchwork.freedesktop.org/series/57768/ State : success == Summary == CI Bug Log - changes from CI_DRM_5728 -> Patchwork_12426 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57768/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12426 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57 * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@kms_busy@basic-flip-c: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +52 * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#107362] * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@kms_busy@basic-flip-a: - fi-gdg-551: FAIL [fdo#103182] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: FAIL [fdo#103167] -> PASS Warnings * igt@i915_selftest@live_contexts: - fi-icl-u3: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108569] [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (42 -> 43) -- Additional (3): fi-byt-j1900 fi-byt-clapper fi-pnv-d510 Missing(2): fi-ilk-m540 fi-bdw-samus Build changes - * Linux: CI_DRM_5728 -> Patchwork_12426 CI_DRM_5728: 78b288a16a32e8828f93c5e2e9eb3c1b73bfdce7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4877: d15ad69be07a987d5c2ba408201b287adae8ca59 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12426: c660e5a5a1de9783f0e810d09fbdd1e76b314e86 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c660e5a5a1de drm/i915: Start using comparative INTEL_PCH_TYPE 75e7e41e7d7a drm/i915: Move PCH_NOP to -1 8279af225dca drm/i915/gen11+: First assume next platforms will inherit stuff == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12426/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
On Fri, Mar 08, 2019 at 10:23:20PM +, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2019-03-08 21:42:58)
> > This exactly same approach was already used from gen9
> > to gen10 and from gen10 to gen11. Let's also use it
> > for gen11+.
> >
> > Let's first assume that we inherit a similar platform
> > and than we apply the differences on top.
> >
> > Different from the previous attempts this will be
> > done this time with coccinelle. We obviously need to
> > exclude some case that is really exclusive for gen11
> > like PCH, Firmware, and few others. Luckly this was
> > easy to filter by selecting the files we are touching
> > with coccinelle as exposed below:
> >
> > spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
> >intel_bios.c intel_cdclk.c intel_ddi.c \
> >intel_device_info.c intel_display.c intel_dpll_mgr.c \
> >intel_dsi_vbt.c intel_hdmi.c intel_mocs.c intel_color.c
> >
> > @noticelake@ expression e; @@
> > -!IS_ICELAKE(e)
> > +INTEL_GEN(e) < 11
> > @notgen11@ expression e; @@
> > -!IS_GEN(e, 11)
> > +INTEL_GEN(e) < 11
> > @icelake@ expression e; @@
> > -IS_ICELAKE(e)
> > +INTEL_GEN(e) >= 11
> > @gen11@ expression e; @@
> > -IS_GEN(e, 11)
> > +INTEL_GEN(e) >= 11
> >
> > No functional change.
> >
> > v2: Remove intel_lrc.c per Tvrtko request since those were w/a
> > for ICL hw issuea and media related configuration.
> >
> > Cc: Tvrtko Ursulin
> > Cc: Lucas De Marchi
> > Signed-off-by: Rodrigo Vivi
> > Reviewed-by: Lucas De Marchi
> > ---
> > drivers/gpu/drm/i915/i915_perf.c | 2 +-
> > drivers/gpu/drm/i915/intel_bios.c| 4 ++--
> > drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
> > drivers/gpu/drm/i915/intel_color.c | 2 +-
> > drivers/gpu/drm/i915/intel_ddi.c | 18 +-
> > drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> > drivers/gpu/drm/i915/intel_display.c | 18 +-
> > drivers/gpu/drm/i915/intel_dpll_mgr.c| 2 +-
> > drivers/gpu/drm/i915/intel_dsi_vbt.c | 6 +++---
> > drivers/gpu/drm/i915/intel_hdmi.c| 4 ++--
> > drivers/gpu/drm/i915/intel_mocs.c| 2 +-
> > 11 files changed, 33 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c
> > b/drivers/gpu/drm/i915/i915_perf.c
> > index e19a89e4df64..9b0292a38865 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private
> > *dev_priv)
> >
> >
> > sysfs_attr_init(_priv->perf.oa.test_config.sysfs_metric_id.attr);
> >
> > - if (IS_ICELAKE(dev_priv)) {
> > + if (INTEL_GEN(dev_priv) >= 11) {
> > i915_perf_load_test_config_icl(dev_priv);
> > } else if (IS_CANNONLAKE(dev_priv)) {
> > i915_perf_load_test_config_cnl(dev_priv);
>
> Given that every platform so far has had different oa configurations,
> that looks to be a hasty assumption that future platforms will be fixed.
I know... But my hope is that at some point it gets stabilized.
Well, or at least start with this so any other gen11 could reuse and
gen12 would start with that and change later for >= gen12 and on...
> -Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
Quoting Rodrigo Vivi (2019-03-08 21:42:58)
> This exactly same approach was already used from gen9
> to gen10 and from gen10 to gen11. Let's also use it
> for gen11+.
>
> Let's first assume that we inherit a similar platform
> and than we apply the differences on top.
>
> Different from the previous attempts this will be
> done this time with coccinelle. We obviously need to
> exclude some case that is really exclusive for gen11
> like PCH, Firmware, and few others. Luckly this was
> easy to filter by selecting the files we are touching
> with coccinelle as exposed below:
>
> spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
>intel_bios.c intel_cdclk.c intel_ddi.c \
>intel_device_info.c intel_display.c intel_dpll_mgr.c \
>intel_dsi_vbt.c intel_hdmi.c intel_mocs.c intel_color.c
>
> @noticelake@ expression e; @@
> -!IS_ICELAKE(e)
> +INTEL_GEN(e) < 11
> @notgen11@ expression e; @@
> -!IS_GEN(e, 11)
> +INTEL_GEN(e) < 11
> @icelake@ expression e; @@
> -IS_ICELAKE(e)
> +INTEL_GEN(e) >= 11
> @gen11@ expression e; @@
> -IS_GEN(e, 11)
> +INTEL_GEN(e) >= 11
>
> No functional change.
>
> v2: Remove intel_lrc.c per Tvrtko request since those were w/a
> for ICL hw issuea and media related configuration.
>
> Cc: Tvrtko Ursulin
> Cc: Lucas De Marchi
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/intel_bios.c| 4 ++--
> drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
> drivers/gpu/drm/i915/intel_color.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 18 +-
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 18 +-
> drivers/gpu/drm/i915/intel_dpll_mgr.c| 2 +-
> drivers/gpu/drm/i915/intel_dsi_vbt.c | 6 +++---
> drivers/gpu/drm/i915/intel_hdmi.c| 4 ++--
> drivers/gpu/drm/i915/intel_mocs.c| 2 +-
> 11 files changed, 33 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index e19a89e4df64..9b0292a38865 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private
> *dev_priv)
>
> sysfs_attr_init(_priv->perf.oa.test_config.sysfs_metric_id.attr);
>
> - if (IS_ICELAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> i915_perf_load_test_config_icl(dev_priv);
> } else if (IS_CANNONLAKE(dev_priv)) {
> i915_perf_load_test_config_cnl(dev_priv);
Given that every platform so far has had different oa configurations,
that looks to be a hasty assumption that future platforms will be fixed.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
== Series Details == Series: series starting with [1/3] drm/i915/gen11+: First assume next platforms will inherit stuff URL : https://patchwork.freedesktop.org/series/57768/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/gen11+: First assume next platforms will inherit stuff Okay! Commit: drm/i915: Move PCH_NOP to -1 Okay! Commit: drm/i915: Start using comparative INTEL_PCH_TYPE -drivers/gpu/drm/i915/selftests/../i915_drv.h:3553:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3559:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Add new ICL PCI ID
A new PCI ID for ICL was added to BSpec, lets keep it in tight sync as ICL is not protected by the alpha support flag anymore. v2: Keeping BSpec order(Rodrigo) BSepc: 21141 Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- include/drm/i915_pciids.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index d2fad7b0fcf6..d20feeaa 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -469,6 +469,7 @@ INTEL_VGA_DEVICE(0x8A57, info), \ INTEL_VGA_DEVICE(0x8A56, info), \ INTEL_VGA_DEVICE(0x8A71, info), \ - INTEL_VGA_DEVICE(0x8A70, info) + INTEL_VGA_DEVICE(0x8A70, info), \ + INTEL_VGA_DEVICE(0x8A53, info) #endif /* _I915_PCIIDS_H */ -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915: Move PCH_NOP to -1
So we can later use PCH >= comparisons. The ultimate goal
is to make it easier for us to introduce a new platform
with south display engine on PCH just by reusing the previous
one.
Suggested-by: Lucas De Marchi
Cc: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4ffe19ec698..8a57cdde5385 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -524,6 +524,7 @@ struct i915_psr {
};
enum intel_pch {
+ PCH_NOP = -1, /* PCH without south display */
PCH_NONE = 0, /* No PCH present */
PCH_IBX,/* Ibexpeak PCH */
PCH_CPT,/* Cougarpoint/Pantherpoint PCH */
@@ -532,7 +533,6 @@ enum intel_pch {
PCH_KBP,/* Kaby Lake PCH */
PCH_CNP,/* Cannon Lake PCH */
PCH_ICP,/* Ice Lake PCH */
- PCH_NOP,/* PCH without south display */
};
enum intel_sbi_destination {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE
In order to make it easier to bring up new platforms
without having to take care about all corner cases
that was previously taken care for previous platforms
we already use comparative INTEL_GEN statements.
Let's start doing the same with PCH.
The only caveats are:
- less-than comparisons need to be avoided or done with
attention and check > PCH_NONE as well.
- It is not necessarily a chronological order, but a matter
of south display compatibility/inheritance.
v2: Rebased on top of Jani's clean-up which removed the
need for less-than comparison
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h| 6 ++
drivers/gpu/drm/i915/i915_irq.c| 7 ++-
drivers/gpu/drm/i915/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/intel_dp.c| 3 +--
drivers/gpu/drm/i915/intel_panel.c | 5 ++---
5 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8a57cdde5385..9a93accbb2e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -523,6 +523,12 @@ struct i915_psr {
u16 su_x_granularity;
};
+/*
+ * Sorted by south display engine compatibility.
+ * If the new PCH comes with a south display engine that is not
+ * inherited from the latest item, please do not add it to the
+ * end. Instead, add it right after its "parent" PCH.
+ */
enum intel_pch {
PCH_NOP = -1, /* PCH without south display */
PCH_NONE = 0, /* No PCH present */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1f4e984ce42f..c823d2e76852 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2831,9 +2831,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
u32 master_ctl)
if (HAS_PCH_ICP(dev_priv))
icp_irq_handler(dev_priv, iir);
- else if (HAS_PCH_SPT(dev_priv) ||
-HAS_PCH_KBP(dev_priv) ||
-HAS_PCH_CNP(dev_priv))
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
spt_irq_handler(dev_priv, iir);
else
cpt_irq_handler(dev_priv, iir);
@@ -4621,8 +4619,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->disable_vblank = gen8_disable_vblank;
if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
- else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
-HAS_PCH_CNP(dev_priv))
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
else
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 7e5132772477..9d236e4ed26a 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2723,7 +2723,7 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
*/
void intel_update_rawclk(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
dev_priv->rawclk_freq = pch_rawclk(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f40b3342d82a..47857f96c3b1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -951,8 +951,7 @@ static void intel_pps_get_registers(struct intel_dp
*intel_dp,
regs->pp_off = PP_OFF_DELAYS(pps_idx);
/* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
- HAS_PCH_ICP(dev_priv))
+ if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
regs->pp_div = INVALID_MMIO_REG;
else
regs->pp_div = PP_DIVISOR(pps_idx);
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index beca98d2b035..edd5540639b0 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1894,15 +1894,14 @@ intel_panel_init_backlight_funcs(struct intel_panel
*panel)
panel->backlight.set = bxt_set_backlight;
panel->backlight.get = bxt_get_backlight;
panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
- } else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) {
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) {
panel->backlight.setup = cnp_setup_backlight;
[Intel-gfx] [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
This exactly same approach was already used from gen9
to gen10 and from gen10 to gen11. Let's also use it
for gen11+.
Let's first assume that we inherit a similar platform
and than we apply the differences on top.
Different from the previous attempts this will be
done this time with coccinelle. We obviously need to
exclude some case that is really exclusive for gen11
like PCH, Firmware, and few others. Luckly this was
easy to filter by selecting the files we are touching
with coccinelle as exposed below:
spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
intel_bios.c intel_cdclk.c intel_ddi.c \
intel_device_info.c intel_display.c intel_dpll_mgr.c \
intel_dsi_vbt.c intel_hdmi.c intel_mocs.c intel_color.c
@noticelake@ expression e; @@
-!IS_ICELAKE(e)
+INTEL_GEN(e) < 11
@notgen11@ expression e; @@
-!IS_GEN(e, 11)
+INTEL_GEN(e) < 11
@icelake@ expression e; @@
-IS_ICELAKE(e)
+INTEL_GEN(e) >= 11
@gen11@ expression e; @@
-IS_GEN(e, 11)
+INTEL_GEN(e) >= 11
No functional change.
v2: Remove intel_lrc.c per Tvrtko request since those were w/a
for ICL hw issuea and media related configuration.
Cc: Tvrtko Ursulin
Cc: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/intel_bios.c| 4 ++--
drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
drivers/gpu/drm/i915/intel_color.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 18 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 18 +-
drivers/gpu/drm/i915/intel_dpll_mgr.c| 2 +-
drivers/gpu/drm/i915/intel_dsi_vbt.c | 6 +++---
drivers/gpu/drm/i915/intel_hdmi.c| 4 ++--
drivers/gpu/drm/i915/intel_mocs.c| 2 +-
11 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e19a89e4df64..9b0292a38865 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
sysfs_attr_init(_priv->perf.oa.test_config.sysfs_metric_id.attr);
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
i915_perf_load_test_config_icl(dev_priv);
} else if (IS_CANNONLAKE(dev_priv)) {
i915_perf_load_test_config_cnl(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index b508d8a735e0..48c62bea92cd 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -2093,8 +2093,8 @@ bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv,
dvo_port = child->dvo_port;
if (dvo_port == DVO_PORT_MIPIA ||
- (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
- (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
+ (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) ||
+ (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) {
if (port)
*port = dvo_port - DVO_PORT_MIPIA;
return true;
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 5d266538036d..7e5132772477 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2560,7 +2560,7 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
*/
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (dev_priv->cdclk.hw.ref == 24000)
dev_priv->max_cdclk_freq = 648000;
else
@@ -2744,7 +2744,7 @@ void intel_update_rawclk(struct drm_i915_private
*dev_priv)
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.set_cdclk = icl_set_cdclk;
dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2773,7 +2773,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
vlv_modeset_calc_cdclk;
}
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
dev_priv->display.get_cdclk = icl_get_cdclk;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.get_cdclk = cnl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index da7a07d5ccea..0173967ed593 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -841,7 +841,7 @@ void intel_color_init(struct intel_crtc *crtc)
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Sort ICL PCI IDs
On Fri, 2019-03-08 at 13:17 -0800, Rodrigo Vivi wrote: > On Thu, Mar 07, 2019 at 12:56:55PM -0800, José Roberto de Souza > wrote: > > Lets keep it sorted to make easy to spot missing PCI IDs. > > Hmm... In my opinion leaving it as the identical order > of the spec is the way to make it easier to spot if we missed > something... > > Otherwise when reviewing I have to stop and sort one or another. Oh it is following the order of the second table, okay makes sense keep this way. > > > Cc: Rodrigo Vivi > > Signed-off-by: José Roberto de Souza > > --- > > include/drm/i915_pciids.h | 16 > > 1 file changed, 8 insertions(+), 8 deletions(-) > > > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > > index d2fad7b0fcf6..be735811591d 100644 > > --- a/include/drm/i915_pciids.h > > +++ b/include/drm/i915_pciids.h > > @@ -459,16 +459,16 @@ > > #define INTEL_ICL_11_IDS(info) \ > > INTEL_VGA_DEVICE(0x8A50, info), \ > > INTEL_VGA_DEVICE(0x8A51, info), \ > > - INTEL_VGA_DEVICE(0x8A5C, info), \ > > - INTEL_VGA_DEVICE(0x8A5D, info), \ > > - INTEL_VGA_DEVICE(0x8A59, info), \ > > - INTEL_VGA_DEVICE(0x8A58, info), \ > > INTEL_VGA_DEVICE(0x8A52, info), \ > > + INTEL_VGA_DEVICE(0x8A56, info), \ > > + INTEL_VGA_DEVICE(0x8A57, info), \ > > + INTEL_VGA_DEVICE(0x8A58, info), \ > > + INTEL_VGA_DEVICE(0x8A59, info), \ > > INTEL_VGA_DEVICE(0x8A5A, info), \ > > INTEL_VGA_DEVICE(0x8A5B, info), \ > > - INTEL_VGA_DEVICE(0x8A57, info), \ > > - INTEL_VGA_DEVICE(0x8A56, info), \ > > - INTEL_VGA_DEVICE(0x8A71, info), \ > > - INTEL_VGA_DEVICE(0x8A70, info) > > + INTEL_VGA_DEVICE(0x8A5C, info), \ > > + INTEL_VGA_DEVICE(0x8A5D, info), \ > > + INTEL_VGA_DEVICE(0x8A70, info), \ > > + INTEL_VGA_DEVICE(0x8A71, info) > > > > #endif /* _I915_PCIIDS_H */ > > -- > > 2.21.0 > > signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add new ICL PCI ID
On Thu, Mar 07, 2019 at 12:56:56PM -0800, José Roberto de Souza wrote: > A new PCI ID for ICL was added to BSpec, lets keep it in tight sync > as ICL is not protected by the alpha support flag anymore. > > BSepc: 21141 > Cc: Rodrigo Vivi > Signed-off-by: José Roberto de Souza > --- > include/drm/i915_pciids.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index be735811591d..6a287f0b3c6d 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -460,6 +460,7 @@ > INTEL_VGA_DEVICE(0x8A50, info), \ > INTEL_VGA_DEVICE(0x8A51, info), \ > INTEL_VGA_DEVICE(0x8A52, info), \ > + INTEL_VGA_DEVICE(0x8A53, info), \ With this as the last item of the current list feel free to use: Reviewed-by: Rodrigo Vivi > INTEL_VGA_DEVICE(0x8A56, info), \ > INTEL_VGA_DEVICE(0x8A57, info), \ > INTEL_VGA_DEVICE(0x8A58, info), \ > -- > 2.21.0 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Sort ICL PCI IDs
On Thu, Mar 07, 2019 at 12:56:55PM -0800, José Roberto de Souza wrote: > Lets keep it sorted to make easy to spot missing PCI IDs. Hmm... In my opinion leaving it as the identical order of the spec is the way to make it easier to spot if we missed something... Otherwise when reviewing I have to stop and sort one or another. > > Cc: Rodrigo Vivi > Signed-off-by: José Roberto de Souza > --- > include/drm/i915_pciids.h | 16 > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index d2fad7b0fcf6..be735811591d 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -459,16 +459,16 @@ > #define INTEL_ICL_11_IDS(info) \ > INTEL_VGA_DEVICE(0x8A50, info), \ > INTEL_VGA_DEVICE(0x8A51, info), \ > - INTEL_VGA_DEVICE(0x8A5C, info), \ > - INTEL_VGA_DEVICE(0x8A5D, info), \ > - INTEL_VGA_DEVICE(0x8A59, info), \ > - INTEL_VGA_DEVICE(0x8A58, info), \ > INTEL_VGA_DEVICE(0x8A52, info), \ > + INTEL_VGA_DEVICE(0x8A56, info), \ > + INTEL_VGA_DEVICE(0x8A57, info), \ > + INTEL_VGA_DEVICE(0x8A58, info), \ > + INTEL_VGA_DEVICE(0x8A59, info), \ > INTEL_VGA_DEVICE(0x8A5A, info), \ > INTEL_VGA_DEVICE(0x8A5B, info), \ > - INTEL_VGA_DEVICE(0x8A57, info), \ > - INTEL_VGA_DEVICE(0x8A56, info), \ > - INTEL_VGA_DEVICE(0x8A71, info), \ > - INTEL_VGA_DEVICE(0x8A70, info) > + INTEL_VGA_DEVICE(0x8A5C, info), \ > + INTEL_VGA_DEVICE(0x8A5D, info), \ > + INTEL_VGA_DEVICE(0x8A70, info), \ > + INTEL_VGA_DEVICE(0x8A71, info) > > #endif /* _I915_PCIIDS_H */ > -- > 2.21.0 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Add broadcast RGB property for DP MST
== Series Details == Series: series starting with [1/5] drm/i915: Add broadcast RGB property for DP MST URL : https://patchwork.freedesktop.org/series/57766/ State : success == Summary == CI Bug Log - changes from CI_DRM_5728 -> Patchwork_12424 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57766/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12424 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57 * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@kms_busy@basic-flip-b: - fi-gdg-551: PASS -> FAIL [fdo#103182] * igt@kms_busy@basic-flip-c: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +52 * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#107362] Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (42 -> 43) -- Additional (3): fi-byt-j1900 fi-byt-clapper fi-pnv-d510 Missing(2): fi-ilk-m540 fi-bdw-samus Build changes - * Linux: CI_DRM_5728 -> Patchwork_12424 CI_DRM_5728: 78b288a16a32e8828f93c5e2e9eb3c1b73bfdce7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4877: d15ad69be07a987d5c2ba408201b287adae8ca59 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12424: ccb2723ec15a18ab1dcbfc69269004e4ce87dd79 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ccb2723ec15a drm/i915: Update TRANS_MSA_MISC for fastsets 0147c94c2c5b drm/i915: Add max_bpc property for DP MST 124b25ae1de0 drm/i915: Remove the 8bpc shackles from DP MST 8f0b667de193 drm/i915: Expose the force_audio property with DP MST 3a9a15b38816 drm/i915: Add broadcast RGB property for DP MST == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12424/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Zero initialize this_cpu in busywait_stop (rev2)
== Series Details == Series: drm/i915: Zero initialize this_cpu in busywait_stop (rev2) URL : https://patchwork.freedesktop.org/series/57718/ State : failure == Summary == Applying: drm/i915: Zero initialize this_cpu in busywait_stop error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_request.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Zero initialize this_cpu in busywait_stop When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915/icl: use a function pointer for pll_write when enabling
On Tue, Mar 05, 2019 at 05:26:33PM -0800, Lucas De Marchi wrote:
> This allows us to share the icl_pll_enable() between the different types
> of PLL while allowing the caller to differentiate how to write the
> registers.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 18 --
> 1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 3b3de99756d6..5511bc23ea3d 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -3118,9 +3118,10 @@ static void icl_mg_pll_write(struct drm_i915_private
> *dev_priv,
>
> static void icl_pll_enable(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll,
> -i915_reg_t enable_reg)
> +i915_reg_t enable_reg,
> +void (*pll_write)(struct drm_i915_private *dev_priv,
> + struct intel_shared_dpll *pll))
> {
> - const enum intel_dpll_id id = pll->info->id;
> u32 val;
>
> val = I915_READ(enable_reg);
> @@ -3133,12 +3134,9 @@ static void icl_pll_enable(struct drm_i915_private
> *dev_priv,
>*/
> if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE,
> PLL_POWER_STATE, 1))
> - DRM_ERROR("PLL %d Power not enabled\n", id);
> + DRM_ERROR("PLL %d Power not enabled\n", pll->info->id);
>
> - if (intel_dpll_is_combophy(id) || id == DPLL_ID_ICL_TBTPLL)
> - icl_dpll_write(dev_priv, pll);
> - else
> - icl_mg_pll_write(dev_priv, pll);
> + pll_write(dev_priv, pll);
Hmm. Would it be cleaner to just exract the pll power
enable/disable and pll enable/disable parts into small helpers?
It looks like like glk/cnl also follow this same pattern, so
there may be a chance to reuse the code on those platforms
as well.
>
> /*
>* DVFS pre sequence would be here, but in our driver the cdclk code
> @@ -3152,7 +3150,7 @@ static void icl_pll_enable(struct drm_i915_private
> *dev_priv,
>
> if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK,
> 1)) /* 600us actually. */
> - DRM_ERROR("PLL %d not locked\n", id);
> + DRM_ERROR("PLL %d not locked\n", pll->info->id);
>
> /* DVFS post sequence would be here. See the comment above. */
> }
> @@ -3162,7 +3160,7 @@ static void combo_pll_enable(struct drm_i915_private
> *dev_priv,
> {
> i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
>
> - icl_pll_enable(dev_priv, pll, enable_reg);
> + icl_pll_enable(dev_priv, pll, enable_reg, icl_dpll_write);
> }
>
> static void mg_pll_enable(struct drm_i915_private *dev_priv,
> @@ -3171,7 +3169,7 @@ static void mg_pll_enable(struct drm_i915_private
> *dev_priv,
> i915_reg_t enable_reg =
> MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
>
> - icl_pll_enable(dev_priv, pll, enable_reg);
> + icl_pll_enable(dev_priv, pll, enable_reg, icl_mg_pll_write);
> }
>
> static void icl_pll_disable(struct drm_i915_private *dev_priv,
> --
> 2.20.1
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Add broadcast RGB property for DP MST
== Series Details == Series: series starting with [1/5] drm/i915: Add broadcast RGB property for DP MST URL : https://patchwork.freedesktop.org/series/57766/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3a9a15b38816 drm/i915: Add broadcast RGB property for DP MST 8f0b667de193 drm/i915: Expose the force_audio property with DP MST 124b25ae1de0 drm/i915: Remove the 8bpc shackles from DP MST -:234: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #234: FILE: drivers/gpu/drm/i915/intel_drv.h:1912: +}; +void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, total: 0 errors, 0 warnings, 1 checks, 201 lines checked 0147c94c2c5b drm/i915: Add max_bpc property for DP MST ccb2723ec15a drm/i915: Update TRANS_MSA_MISC for fastsets ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Zero initialize this_cpu in busywait_stop
On Fri, Mar 8, 2019 at 12:27 AM Chris Wilson wrote:
>
> Quoting Nathan Chancellor (2019-03-08 01:20:24)
> > When building with -Wsometimes-uninitialized, Clang warns:
> >
> > drivers/gpu/drm/i915/i915_request.c:1032:6: warning: variable 'this_cpu'
> > is used uninitialized whenever '&&' condition is false
> > [-Wsometimes-uninitialized]
> >
> > time_after expands to use two typecheck with logical ANDs between them.
> > typecheck evaluates to 1 but Clang clearly gets confused with the logic
> > that as semantic analysis happens early in the pipeline. Fix this by
> > just zero initializing this_cpu as it will always be properly
> > initialized before the comparison below.
> >
> > Link: https://github.com/ClangBuiltLinux/linux/issues/415
> > Signed-off-by: Nathan Chancellor
> > ---
> >
> > Alternatively, this can be solved by having the return value of
> > local_clock_us(_cpu) be a local variable but this seems less
> > controversial.
>
> I'll just wait for clang to be fixed, as this severely undermines any
> respect I have for its semantic analysis.
> -Chris
I'm still playing around with this in Godbolt (my hunch is that GNU C
statement expressions are maybe inlined as part of GCC's early
inlining phase). For example:
https://godbolt.org/z/G54s5z
If you change `typecheck(unsigned long, a)` and `typecheck(unsigned
long, b)` in `time_after()` both to `1` (what `typecheck` would
evaluate to), then the warning goes away. But a further
simplification shows that GNU C statement expressions are not the
problem:
https://godbolt.org/z/KzCN8m
I need to keep investigating, but there may be more we can do on the
compiler side.
It seems that another workaround that avoid default initialization is
to just create another local for the temporary expression that
provably initialized this_cpu, ie.
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index c2a5c48c7541..5b90b5c35c8b 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1028,8 +1028,9 @@ static unsigned long local_clock_us(unsigned int *cpu)
static bool busywait_stop(unsigned long timeout, unsigned int cpu)
{
unsigned int this_cpu;
+ unsigned long local_clock = local_clock_us(_cpu);
- if (time_after(local_clock_us(_cpu), timeout))
+ if (time_after(local_clock, timeout))
return true;
return this_cpu != cpu;
--
Thanks,
~Nick Desaulniers
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: Remove the 8bpc shackles from DP MST
From: Ville Syrjälä
Allow DP MST to output any color depth. This means deep color as
well as falling back to 6bpc if we would otherwise require too
much bandwidth.
TODO: We should probably extend bw_contstrained scheme to force
all streams on the link to 6bpc if we can't fit the new stream(s)
otherwise.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 8 +-
drivers/gpu/drm/i915/intel_dp_mst.c | 120 +---
drivers/gpu/drm/i915/intel_drv.h| 8 ++
3 files changed, 83 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f40b3342d82a..e1ab50980b83 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1724,12 +1724,6 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp,
int port_clock,
}
}
-struct link_config_limits {
- int min_clock, max_clock;
- int min_lane_count, max_lane_count;
- int min_bpp, max_bpp;
-};
-
static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
const struct intel_crtc_state
*pipe_config)
{
@@ -1792,7 +1786,7 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
}
/* Adjust link config limits based on compliance test requests. */
-static void
+void
intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index f9ce9e87d35b..df8b396cbcdc 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -29,41 +29,81 @@
#include
#include
+static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state
*conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
+ struct intel_dp *intel_dp = _mst->primary->dp;
+ struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
+ const struct drm_display_mode *adjusted_mode =
+ _state->base.adjusted_mode;
+ void *port = connector->port;
+ bool constant_n = drm_dp_has_quirk(_dp->desc,
+ DP_DPCD_QUIRK_CONSTANT_N);
+ int slots;
+
+ for (;;) {
+ crtc_state->lane_count = limits->max_lane_count;
+ crtc_state->port_clock = limits->max_clock;
+ crtc_state->pipe_bpp = limits->max_bpp;
+
+ crtc_state->pbn =
drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
+ crtc_state->pipe_bpp);
+
+ slots = drm_dp_atomic_find_vcpi_slots(state, _dp->mst_mgr,
+ port, crtc_state->pbn);
+ if (slots == -EDEADLK)
+ return slots;
+ if (slots >= 0)
+ break;
+
+ if (limits->max_bpp > limits->min_bpp) {
+ limits->max_bpp -= 2 * 3;
+ continue;
+ }
+
+ DRM_DEBUG_KMS("failed finding vcpi slots:%d\n", slots);
+
+ return slots;
+ }
+
+ intel_link_compute_m_n(crtc_state->pipe_bpp,
+ crtc_state->lane_count,
+ adjusted_mode->crtc_clock,
+ crtc_state->port_clock,
+ _state->dp_m_n,
+ constant_n);
+ crtc_state->dp_m_n.tu = slots;
+
+ return 0;
+}
+
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
- struct intel_digital_port *intel_dig_port = intel_mst->primary;
- struct intel_dp *intel_dp = _dig_port->dp;
- struct drm_connector *connector = conn_state->connector;
+ struct intel_dp *intel_dp = _mst->primary->dp;
+ struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
- void *port = to_intel_connector(connector)->port;
- struct drm_atomic_state *state = pipe_config->base.state;
- struct drm_crtc
[Intel-gfx] [PATCH 1/5] drm/i915: Add broadcast RGB property for DP MST
From: Ville Syrjälä
Add the "Broadcast RGB" property to MST connectors, and implement
the same logic for it as we have in the SST code.
Cc: Ivan Vlk
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108821
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp_mst.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index fb67cd931117..2b791d67a43f 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -38,6 +38,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder
*encoder,
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = _dig_port->dp;
struct drm_connector *connector = conn_state->connector;
+ struct intel_digital_connector_state *intel_conn_state =
+ to_intel_digital_connector_state(conn_state);
void *port = to_intel_connector(connector)->port;
struct drm_atomic_state *state = pipe_config->base.state;
struct drm_crtc *crtc = pipe_config->base.crtc;
@@ -77,6 +79,21 @@ static int intel_dp_mst_compute_config(struct intel_encoder
*encoder,
if (drm_dp_mst_port_has_audio(_dp->mst_mgr, port))
pipe_config->has_audio = true;
+ if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
+ /*
+* See:
+* CEA-861-E - 5.1 Default Encoding Parameters
+* VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
+*/
+ pipe_config->limited_color_range =
+ pipe_config->pipe_bpp != 18 &&
+ drm_default_rgb_quant_range(adjusted_mode) ==
+ HDMI_QUANTIZATION_RANGE_LIMITED;
+ } else {
+ pipe_config->limited_color_range =
+ intel_conn_state->broadcast_rgb ==
INTEL_BROADCAST_RGB_LIMITED;
+ }
+
mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);
pipe_config->pbn = mst_pbn;
@@ -117,7 +134,11 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
struct drm_crtc *new_crtc = new_conn_state->crtc;
struct drm_crtc_state *crtc_state;
struct drm_dp_mst_topology_mgr *mgr;
- int ret = 0;
+ int ret;
+
+ ret = intel_digital_connector_atomic_check(connector, new_conn_state);
+ if (ret)
+ return ret;
if (!old_conn_state->crtc)
return 0;
@@ -354,11 +375,13 @@ intel_dp_mst_detect(struct drm_connector *connector, bool
force)
static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
.detect = intel_dp_mst_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
+ .atomic_get_property = intel_digital_connector_atomic_get_property,
+ .atomic_set_property = intel_digital_connector_atomic_set_property,
.late_register = intel_connector_register,
.early_unregister = intel_connector_unregister,
.destroy = intel_connector_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_duplicate_state = intel_digital_connector_duplicate_state,
};
static int intel_dp_mst_get_modes(struct drm_connector *connector)
@@ -487,6 +510,8 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
if (ret)
goto err;
+ intel_attach_broadcast_rgb_property(connector);
+
return connector;
err:
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915: Expose the force_audio property with DP MST
From: Ville Syrjälä
We already expose the force_audio property with SST. Do the same
with MST.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp_mst.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 2b791d67a43f..f9ce9e87d35b 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -64,6 +64,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder
*encoder,
DRM_DEBUG_KMS("Setting pipe bpp to %d\n",
bpp);
}
+
+ if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
+ pipe_config->has_audio =
+ drm_dp_mst_port_has_audio(_dp->mst_mgr, port);
+ else
+ pipe_config->has_audio =
+ intel_conn_state->force_audio == HDMI_AUDIO_ON;
+
/*
* for MST we always configure max link bw - the spec doesn't
* seem to suggest we should do otherwise.
@@ -76,9 +84,6 @@ static int intel_dp_mst_compute_config(struct intel_encoder
*encoder,
pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
- if (drm_dp_mst_port_has_audio(_dp->mst_mgr, port))
- pipe_config->has_audio = true;
-
if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
/*
* See:
@@ -510,6 +515,7 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
if (ret)
goto err;
+ intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
return connector;
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: Update TRANS_MSA_MISC for fastsets
From: Ville Syrjälä
Update the DP MSA MISC bits for fastsets. This is needed
when we change between limited and full range RGB output.
On HSW+ changing limited_range does not currently result in a
full modeset since we have don't have the readout code for it
(for DP we could, and probably should, readout from TRANS_MSA_MISC
itself, for HDMI we would have to rely on the infoframe). So
the PIPE_CONF_CHECK() is only performed for pre-HSW platforms.
That means any change in the value will result in a fastset
instead. Fortunately there is no prohibition to changing
TRANS_MSA_MISC dynamically, so it looks like we can legally do
fastsets for this.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7e3b4e8fdf3a..3d9ad4526cf9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3556,6 +3556,8 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
*encoder,
{
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ intel_ddi_set_pipe_settings(crtc_state);
+
intel_psr_update(intel_dp, crtc_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915: Add max_bpc property for DP MST
From: Ville Syrjälä Allow the user to limit the output bpc with DP MST. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp_mst.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index df8b396cbcdc..23ca2ab88fd1 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -545,6 +545,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo intel_attach_force_audio_property(connector); intel_attach_broadcast_rgb_property(connector); + drm_connector_attach_max_bpc_property(connector, 6, 12); return connector; -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Suppress the "Failed to idle" warning for gem_eio
== Series Details ==
Series: drm/i915: Suppress the "Failed to idle" warning for gem_eio
URL : https://patchwork.freedesktop.org/series/57740/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5722_full -> Patchwork_12418_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12418_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@in-flight-suspend:
- {shard-iclb}: DMESG-WARN -> SKIP
* igt@gem_ppgtt@blt-vs-render-ctxn:
- {shard-iclb}: DMESG-FAIL [fdo#109766] -> DMESG-WARN
* igt@i915_pm_rc6_residency@rc6-accuracy:
- {shard-iclb}: PASS -> SKIP
* igt@kms_flip@flip-vs-suspend-interruptible:
- {shard-iclb}: PASS -> DMESG-WARN
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- {shard-iclb}: PASS -> FAIL +9
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- {shard-iclb}: FAIL [fdo#108948] -> SKIP
* igt@perf_pmu@semaphore-wait-idle-vecs0:
- {shard-iclb}: PASS -> TIMEOUT
* igt@runner@aborted:
- {shard-iclb}: ( 7 FAIL ) -> ( 6 FAIL ) [fdo#106612] / [fdo#109263]
Known issues
Here are the changes found in Patchwork_12418_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_softpin@noreloc-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@i915_pm_rpm@basic-rte:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@gem-mmap-gtt:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@kms_busy@extended-modeset-hang-oldfb-render-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13
* igt@kms_busy@extended-pageflip-hang-newfb-render-a:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-a-degamma:
- shard-apl: NOTRUN -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-a-legacy-gamma:
- shard-skl: NOTRUN -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-apl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +31
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-xtiled:
- shard-skl: NOTRUN -> FAIL [fdo#107791]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-apl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +20
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-skl: NOTRUN -> FAIL [fdo#105682] +2
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +102
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103167] +1
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v6,1/9] drm/i915/psr: Remove PSR2 FIXME
And pushed to dinq On Fri, 2019-03-08 at 05:33 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v6,1/9] drm/i915/psr: Remove PSR2 FIXME > URL : https://patchwork.freedesktop.org/series/57716/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_5718_full -> Patchwork_12412_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > Known issues > > > Here are the changes found in Patchwork_12412_full that come from > known issues: > > ### IGT changes ### > > Issues hit > > * igt@i915_pm_rpm@gem-execbuf-stress: > - shard-skl: PASS -> INCOMPLETE [fdo#107803] / > [fdo#107807] > > * igt@kms_atomic_transition@3x-modeset-transitions-nonblocking: > - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] > +9 > > * igt@kms_busy@basic-modeset-e: > - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] > > * igt@kms_busy@extended-pageflip-hang-newfb-render-e: > - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] > > * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: > - shard-kbl: PASS -> DMESG-WARN [fdo#107956] > > * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: > - shard-glk: PASS -> FAIL [fdo#108145] > > * igt@kms_chv_cursor_fail@pipe-a-128x128-left-edge: > - shard-hsw: PASS -> INCOMPLETE [fdo#103540] > > * igt@kms_color@pipe-c-legacy-gamma: > - shard-glk: PASS -> FAIL [fdo#104782] > > * igt@kms_cursor_crc@cursor-256x85-random: > - shard-apl: PASS -> FAIL [fdo#103232] +1 > > * igt@kms_cursor_crc@cursor-size-change: > - shard-glk: PASS -> FAIL [fdo#103232] > > * igt@kms_flip@flip-vs-suspend-interruptible: > - shard-skl: PASS -> INCOMPLETE [fdo#109507] > > * igt@kms_flip@modeset-vs-vblank-race-interruptible: > - shard-glk: PASS -> FAIL [fdo#103060] > > * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt: > - shard-skl: NOTRUN -> SKIP [fdo#109271] +26 > > * igt@kms > _frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc: > - shard-glk: PASS -> FAIL [fdo#103167] +1 > > * igt@kms > _frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu: > - shard-snb: NOTRUN -> SKIP [fdo#109271] +68 > > * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt: > - shard-apl: NOTRUN -> SKIP [fdo#109271] +8 > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: > - shard-snb: PASS -> INCOMPLETE [fdo#105411] > > * igt@kms_plane@plane-position-covered-pipe-a-planes: > - shard-apl: PASS -> FAIL [fdo#103166] +1 > > * igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb: > - shard-skl: NOTRUN -> FAIL [fdo#108145] > > * igt@kms_plane_multiple@atomic-pipe-c-tiling-y: > - shard-glk: PASS -> FAIL [fdo#103166] +2 > > * igt@kms_psr@primary_blt: > - shard-kbl: NOTRUN -> SKIP [fdo#109271] +19 > > * igt@kms_rotation_crc@multiplane-rotation: > - shard-kbl: PASS -> INCOMPLETE [fdo#103665] > > * igt@kms_setmode@basic: > - shard-kbl: PASS -> FAIL [fdo#99912] > > * igt@perf_pmu@idle-vcs1: > - shard-glk: NOTRUN -> SKIP [fdo#109271] +13 > > > Possible fixes > > * igt@i915_pm_rpm@universal-planes: > - shard-skl: INCOMPLETE [fdo#107807] -> PASS > > * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: > - shard-apl: FAIL [fdo#106510] / [fdo#108145] -> PASS +1 > > * igt@kms_color@pipe-a-ctm-max: > - shard-apl: FAIL [fdo#108147] -> PASS > > * igt@kms_color@pipe-b-degamma: > - shard-apl: FAIL [fdo#104782] -> PASS > > * igt@kms_color@pipe-c-ctm-green-to-red: > - shard-skl: FAIL [fdo#107201] -> PASS > > * igt@kms_cursor_crc@cursor-256x256-random: > - shard-apl: FAIL [fdo#103232] -> PASS +1 > > * igt@kms_cursor_crc@cursor-64x21-offscreen: > - shard-skl: FAIL [fdo#103232] -> PASS > > * igt@kms_flip@flip-vs-expired-vblank-interruptible: > - shard-skl: FAIL [fdo#105363] -> PASS > > * igt@kms_flip@flip-vs-suspend-interruptible: > - shard-apl: DMESG-WARN [fdo#108566] -> PASS > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen > : > - shard-glk: FAIL [fdo#103167] -> PASS +4 > > * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: > - shard-apl: FAIL [fdo#108948] -> PASS > > * igt@kms_plane@plane-panning-bottom-right-pipe-b-planes: > - shard-skl: FAIL [fdo#103166] -> PASS > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: > - shard-glk: INCOMPLETE [fdo#103359] / [k.org#198133] -> > PASS > > *
Re: [Intel-gfx] [PATCH v6 8/9] drm/i915: Force PSR1 exit when getting pipe CRC
On Thu, 2019-03-07 at 16:00 -0800, José Roberto de Souza wrote:
> If PSR1 is active when pipe CRC is enabled the CRC calculations will
> be inhibit by the transition to low power states that PSR1 brings.
> So lets force a PSR1 exit and as soon as pipe CRC is enabled it will
> block PSR1 activation and avoid CRC timeouts when running IGT tests.
>
> There is a little window between the call to force exit PSR and the
> write to pipe CRC registers that needs to happen within the minimum
> of 6 idles frames otherwise PSR1 will be active again causing the CRC
> timeouts but anyways this will at least reduce the occurrence of CRC
> timeouts.
>
> This can possibily fix issues present right now but I did not found
> any open, I mostly got this issue from previous CI runs of this
> series, bellow some exambles:
>
> * igt@kms_color@pipe-b-ctm-0-75:
> - shard-apl: PASS -> FAIL +9
>
> * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
> - shard-apl: PASS -> DMESG-FAIL +17
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
> - shard-kbl: PASS -> DMESG-FAIL +12
>
> * igt@kms_pipe_crc_basic@read-crc-pipe-c:
> - shard-kbl: PASS -> FAIL +7
>
> v6: s/PSR/PSR1 (Dhinakaran)
I forgot to add DK's rv-b
https://patchwork.freedesktop.org/patch/290564/?series=57628=1#comment_547027
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 36
>
> 1 file changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 9847f6b0cd9a..053dbba6abde 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -452,6 +452,7 @@ static void hsw_activate_psr1(struct intel_dp
> *intel_dp)
>* frames, we'll go with 9 frames for now
>*/
> idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> + 1);
> +
> val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> @@ -853,6 +854,20 @@ void intel_psr_disable(struct intel_dp
> *intel_dp,
> cancel_work_sync(_priv->psr.work);
> }
>
> +static void psr_force_hw_tracking_exit(struct drm_i915_private
> *dev_priv)
> +{
> + /*
> + * Display WA #0884: all
> + * This documented WA for bxt can be safely applied
> + * broadly so we can force HW tracking to exit PSR
> + * instead of disabling and re-enabling.
> + * Workaround tells us to write 0 to CUR_SURFLIVE_A,
> + * but it makes more sense write to the current active
> + * pipe.
> + */
> + I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
> +}
> +
> /**
> * intel_psr_update - Update PSR state
> * @intel_dp: Intel DP
> @@ -877,8 +892,13 @@ void intel_psr_update(struct intel_dp *intel_dp,
> enable = crtc_state->has_psr && psr_global_enabled(psr->debug);
> psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
>
> - if (enable == psr->enabled && psr2_enable == psr->psr2_enabled)
> + if (enable == psr->enabled && psr2_enable == psr->psr2_enabled)
> {
> + /* Force a PSR exit when enabling CRC to avoid CRC
> timeouts */
> + if (crtc_state->crc_enabled && psr->enabled)
> + psr_force_hw_tracking_exit(dev_priv);
> +
> goto unlock;
> + }
>
> if (psr->enabled)
> intel_psr_disable_locked(intel_dp);
> @@ -1148,18 +1168,8 @@ void intel_psr_flush(struct drm_i915_private
> *dev_priv,
> dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
>
> /* By definition flush = invalidate + flush */
> - if (frontbuffer_bits) {
> - /*
> - * Display WA #0884: all
> - * This documented WA for bxt can be safely applied
> - * broadly so we can force HW tracking to exit PSR
> - * instead of disabling and re-enabling.
> - * Workaround tells us to write 0 to CUR_SURFLIVE_A,
> - * but it makes more sense write to the current active
> - * pipe.
> - */
> - I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
> - }
> + if (frontbuffer_bits)
> + psr_force_hw_tracking_exit(dev_priv);
>
> if (!dev_priv->psr.active && !dev_priv-
> >psr.busy_frontbuffer_bits)
> schedule_work(_priv->psr.work);
signature.asc
Description: This is a digitally signed message part
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 12/19] drm-uapi: Import i915_drm.h upto 364df3d04d51
commit 364df3d04d51f0aad13b898f3dffca8c2d03d2b3 (HEAD)
Author: Chris Wilson
Date: Fri Jun 30 13:40:53 2017 +0100
drm/i915: Allow specification of parallel execbuf
Signed-off-by: Chris Wilson
---
include/drm-uapi/i915_drm.h | 352
1 file changed, 279 insertions(+), 73 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 43fb8ede2..e606680a5 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,6 +62,26 @@ extern "C" {
#define I915_ERROR_UEVENT "ERROR"
#define I915_RESET_UEVENT "RESET"
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+ __u64 next_extension;
+ __u64 name;
+};
+
/*
* MOCS indexes used for GPU surfaces, defining the cacheability of the
* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@@ -99,9 +119,14 @@ enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_VIDEO = 2,
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
+ /* should be kept compact */
+
I915_ENGINE_CLASS_INVALID = -1
};
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+#define I915_ENGINE_CLASS_INVALID_VIRTUAL 0
+
/**
* DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
*
@@ -319,6 +344,9 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_PERF_ADD_CONFIG 0x37
#define DRM_I915_PERF_REMOVE_CONFIG0x38
#define DRM_I915_QUERY 0x39
+#define DRM_I915_GEM_VM_CREATE 0x3a
+#define DRM_I915_GEM_VM_DESTROY0x3b
+/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INITDRM_IOW( DRM_COMMAND_BASE +
DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE +
DRM_I915_FLUSH)
@@ -367,6 +395,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
#define DRM_IOCTL_I915_GEM_WAITDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
#define DRM_IOCTL_I915_REG_READDRM_IOWR
(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -377,6 +406,8 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE +
DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE +
DRM_I915_PERF_REMOVE_CONFIG, __u64)
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -476,6 +507,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
+#define I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
#define I915_PARAM_HUC_STATUS 42
@@ -559,6 +591,14 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_MMAP_GTT_COHERENT 52
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
+ * execution through use of explicit fence support.
+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
+ */
+#define
[Intel-gfx] [PATCH i-g-t 18/19] i915: Add gem_exec_balancer
Exercise the in-kernel load balancer checking that we can distribute
batches across the set of ctx->engines to avoid load.
Signed-off-by: Chris Wilson
---
tests/Makefile.am | 1 +
tests/Makefile.sources | 1 +
tests/i915/gem_exec_balancer.c | 627 +
tests/meson.build | 7 +
4 files changed, 636 insertions(+)
create mode 100644 tests/i915/gem_exec_balancer.c
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 289249b42..68a9c14bf 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -102,6 +102,7 @@ gem_close_race_LDADD = $(LDADD) -lpthread
gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_ctx_thrash_LDADD = $(LDADD) -lpthread
gem_ctx_sseu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
+i915_gem_exec_balancer_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
gem_exec_capture_LDADD = $(LDADD) -lz
gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_exec_parallel_LDADD = $(LDADD) -lpthread
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 41e756f15..f6c21a1aa 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -23,6 +23,7 @@ TESTS_progs = \
drm_read \
i915/gem_ctx_engines \
i915/gem_ctx_shared \
+ i915/gem_exec_balancer \
kms_3d \
kms_addfb_basic \
kms_atomic \
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
new file mode 100644
index 0..d9fdffe67
--- /dev/null
+++ b/tests/i915/gem_exec_balancer.c
@@ -0,0 +1,627 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include
+
+#include "igt.h"
+#include "igt_perf.h"
+#include "i915/gem_ring.h"
+#include "sw_sync.h"
+
+IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing");
+
+struct class_instance {
+ uint16_t class;
+ uint16_t instance;
+};
+#define INSTANCE_COUNT (1 << I915_PMU_SAMPLE_INSTANCE_BITS)
+
+static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
+{
+ int fd;
+
+ fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ if (fd != -1) {
+ close(fd);
+ return true;
+ }
+
+ return false;
+}
+
+static struct class_instance *
+list_engines(int i915, uint32_t class_mask, unsigned int *out)
+{
+ unsigned int count = 0, size = 64;
+ struct class_instance *engines;
+
+ engines = malloc(size * sizeof(*engines));
+ if (!engines) {
+ *out = 0;
+ return NULL;
+ }
+
+ for (enum drm_i915_gem_engine_class class = I915_ENGINE_CLASS_RENDER;
+class_mask;
+class++, class_mask >>= 1) {
+ if (!(class_mask & 1))
+ continue;
+
+ for (unsigned int instance = 0;
+instance < INSTANCE_COUNT;
+instance++) {
+if (!has_class_instance(i915, class, instance))
+continue;
+
+ if (count == size) {
+ struct class_instance *e;
+
+ size *= 2;
+ e = realloc(engines, size*sizeof(*engines));
+ if (!e) {
+ *out = count;
+ return engines;
+ }
+
+ engines = e;
+ }
+
+ engines[count++] = (struct class_instance){
+ .class = class,
+ .instance = instance,
+ };
+ }
+ }
+
+ if (!count) {
+ free(engines);
+ engines = NULL;
+ }
+
+ *out = count;
+ return engines;
+}
+
[Intel-gfx] [PATCH i-g-t 11/19] kms_fence_pin_leak: Ask for the GPU before use
Check that the GPU even exists before submitting a batch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109589 Signed-off-by: Chris Wilson --- tests/kms_fence_pin_leak.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/kms_fence_pin_leak.c b/tests/kms_fence_pin_leak.c index 62c52b627..e6c8b33c3 100644 --- a/tests/kms_fence_pin_leak.c +++ b/tests/kms_fence_pin_leak.c @@ -201,6 +201,7 @@ igt_simple_main igt_skip_on_simulation(); data.drm_fd = drm_open_driver_master(DRIVER_INTEL); + igt_require_gem(data.drm_fd); data.devid = intel_get_drm_devid(data.drm_fd); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 16/19] i915/gem_exec_whisper: debugfs/next_seqno is defunct
We removed next_seqno in 5.1, so time to wave goodbye.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_whisper.c | 12
1 file changed, 12 deletions(-)
diff --git a/tests/i915/gem_exec_whisper.c b/tests/i915/gem_exec_whisper.c
index d5afc8119..61b8d6dac 100644
--- a/tests/i915/gem_exec_whisper.c
+++ b/tests/i915/gem_exec_whisper.c
@@ -44,15 +44,6 @@
#define VERIFY 0
-static void write_seqno(int dir, unsigned offset)
-{
- uint32_t seqno = UINT32_MAX - offset;
-
- igt_sysfs_printf(dir, "i915_next_seqno", "0x%x", seqno);
-
- igt_debug("next seqno set to: 0x%x\n", seqno);
-}
-
static void check_bo(int fd, uint32_t handle, int pass)
{
uint32_t *map;
@@ -355,9 +346,6 @@ static void whisper(int fd, unsigned engine, unsigned flags)
igt_until_timeout(150) {
uint64_t offset;
- if (nchild == 1)
- write_seqno(debugfs, pass);
-
if (flags & HANG)
submit_hang(, engines, nengine,
flags);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 19/19] i915/gem_exec_balancer: Exercise bonded pairs
The submit-fence + load_balancing apis allow for us to execute a named
pair of engines in parallel; that this by submitting a request to one
engine, we can then use the generated submit-fence to submit a second
request to another engine and have it execute at the same time.
Furthermore, by specifying bonded pairs, we can direct the virtual
engine to use a particular engine in parallel to the first request.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_balancer.c | 174 +++--
1 file changed, 165 insertions(+), 9 deletions(-)
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index d9fdffe67..e727090e4 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -102,12 +102,44 @@ list_engines(int i915, uint32_t class_mask, unsigned int
*out)
return engines;
}
+static int __set_engines(int i915, uint32_t ctx,
+const struct class_instance *ci,
+unsigned int count)
+{
+ struct engines {
+ uint64_t extension;
+ uint64_t class_instance[count];
+ } engines;
+ struct drm_i915_gem_context_param p = {
+ .ctx_id = ctx,
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .size = sizeof(engines),
+ .value = to_user_pointer()
+ };
+
+ engines.extension = 0;
+ memcpy(engines.class_instance, ci, sizeof(engines.class_instance));
+
+ return __gem_context_set_param(i915, );
+}
+
+static void set_engines(int i915, uint32_t ctx,
+ const struct class_instance *ci,
+ unsigned int count)
+{
+ igt_assert_eq(__set_engines(i915, ctx, ci, count), 0);
+}
+
static int __set_load_balancer(int i915, uint32_t ctx,
const struct class_instance *ci,
- unsigned int count)
+ unsigned int count,
+ void *ext)
{
struct i915_context_engines_load_balance balancer = {
- { .name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE },
+ {
+ .next_extension = to_user_pointer(ext),
+ .name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE
+ },
.engines_mask = ~0ull,
};
I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, count + 1);
@@ -128,9 +160,10 @@ static int __set_load_balancer(int i915, uint32_t ctx,
static void set_load_balancer(int i915, uint32_t ctx,
const struct class_instance *ci,
- unsigned int count)
+ unsigned int count,
+ void *ext)
{
- igt_assert_eq(__set_load_balancer(i915, ctx, ci, count), 0);
+ igt_assert_eq(__set_load_balancer(i915, ctx, ci, count, ext), 0);
}
static uint32_t load_balancer_create(int i915,
@@ -140,7 +173,7 @@ static uint32_t load_balancer_create(int i915,
uint32_t ctx;
ctx = gem_context_create(i915);
- set_load_balancer(i915, ctx, ci, count);
+ set_load_balancer(i915, ctx, ci, count, NULL);
return ctx;
}
@@ -254,7 +287,7 @@ static void individual(int i915)
for (int pass = 0; pass < count; pass++) { /* approx. count! */
igt_permute_array(ci, count, igt_exchange_int64);
- set_load_balancer(i915, ctx, ci, count);
+ set_load_balancer(i915, ctx, ci, count, NULL);
for (unsigned int n = 0; n < count; n++)
check_individual_engine(i915, ctx, ci, n);
}
@@ -265,6 +298,123 @@ static void individual(int i915)
gem_context_destroy(i915, ctx);
}
+static void bonded(int i915, unsigned int flags)
+#define CORK 0x1
+{
+ struct class_instance *master_engines;
+ uint32_t master;
+ struct bond {
+ uint64_t next_extension;
+ uint64_t name;
+
+ uint16_t class;
+ uint16_t inst;
+ uint32_t flags;
+ uint64_t mask;
+ } bonds[16];
+
+ /*
+* I915_CONTEXT_PARAM_ENGINE provides an extension that allows us
+* to specify which engine(s) to pair with a parallel (EXEC_SUBMIT)
+* request submitted to another engine.
+*/
+
+ master = gem_queue_create(i915);
+
+ memset(bonds, 0, sizeof(bonds));
+ for (int n = 0; n < ARRAY_SIZE(bonds); n++) {
+ bonds[n].name = I915_CONTEXT_ENGINES_EXT_BOND;
+ bonds[n].next_extension =
+ n ? to_user_pointer([n - 1]) : 0;
+ bonds[n].mask = 1 << n;
+ }
+
+ for (int mask = 0; mask < 32; mask++) {
+ unsigned int count, limit;
+ struct class_instance *siblings;
+ uint32_t ctx;
+ int
[Intel-gfx] [PATCH i-g-t 03/19] lib: Add GPU power measurement
Read the RAPL power metrics courtesy of perf. Or your local HW
equivalent?
v2: uselocale()
Signed-off-by: Chris Wilson
---
lib/Makefile.sources | 2 +
lib/igt_gpu_power.c | 114 +++
lib/igt_gpu_power.h | 59 ++
lib/meson.build | 2 +
4 files changed, 177 insertions(+)
create mode 100644 lib/igt_gpu_power.c
create mode 100644 lib/igt_gpu_power.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf2720981..e00347f94 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -26,6 +26,8 @@ lib_source_list = \
igt_color_encoding.c\
igt_color_encoding.h\
igt_edid_template.h \
+ igt_gpu_power.c \
+ igt_gpu_power.h \
igt_gt.c\
igt_gt.h\
igt_gvt.c \
diff --git a/lib/igt_gpu_power.c b/lib/igt_gpu_power.c
new file mode 100644
index 0..a4e3c1420
--- /dev/null
+++ b/lib/igt_gpu_power.c
@@ -0,0 +1,114 @@
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "igt_gpu_power.h"
+#include "igt_perf.h"
+
+static int filename_to_buf(const char *filename, char *buf, unsigned int sz)
+{
+ int fd;
+ ssize_t ret;
+
+ fd = open(filename, O_RDONLY);
+ if (fd < 0)
+ return -1;
+
+ ret = read(fd, buf, sz - 1);
+ close(fd);
+ if (ret < 1)
+ return -1;
+
+ buf[ret] = '\0';
+
+ return 0;
+}
+
+static uint64_t filename_to_u64(const char *filename, int base)
+{
+ char buf[64], *b;
+
+ if (filename_to_buf(filename, buf, sizeof(buf)))
+ return 0;
+
+ /*
+* Handle both single integer and key=value formats by skipping
+* leading non-digits.
+*/
+ b = buf;
+ while (*b && !isdigit(*b))
+ b++;
+
+ return strtoull(b, NULL, base);
+}
+
+static double filename_to_double(const char *filename)
+{
+ locale_t locale, oldlocale;
+ char buf[80];
+ double v;
+
+ if (filename_to_buf(filename, buf, sizeof(buf)))
+ return 0;
+
+ /* Replace user environment with plain C to match kernel format */
+ locale = newlocale(LC_ALL, "C", 0);
+ oldlocale = uselocale(locale);
+
+ v = strtod(buf, NULL);
+
+ uselocale(oldlocale);
+ freelocale(locale);
+
+ return v;
+}
+
+static uint64_t rapl_type_id(void)
+{
+ return filename_to_u64("/sys/devices/power/type", 10);
+}
+
+static uint64_t rapl_gpu_power(void)
+{
+ return filename_to_u64("/sys/devices/power/events/energy-gpu", 0);
+}
+
+static double rapl_gpu_power_scale(void)
+{
+ return filename_to_double("/sys/devices/power/events/energy-gpu.scale");
+}
+
+int gpu_power_open(struct gpu_power *power)
+{
+ power->fd = igt_perf_open(rapl_type_id(), rapl_gpu_power());
+ if (power->fd < 0) {
+ power->fd = -errno;
+ goto err;
+ }
+
+ power->scale = rapl_gpu_power_scale();
+ if (isnan(power->scale) || !power->scale) {
+ close(power->fd);
+ goto err;
+ }
+ power->scale *= 1e9;
+
+ return 0;
+
+err:
+ errno = 0;
+ return power->fd;
+}
+
+bool gpu_power_read(struct gpu_power *power, struct gpu_power_sample *s)
+{
+ return read(power->fd, s, sizeof(*s)) == sizeof(*s);
+}
+
+void gpu_power_close(struct gpu_power *power)
+{
+ close(power->fd);
+}
diff --git a/lib/igt_gpu_power.h b/lib/igt_gpu_power.h
new file mode 100644
index 0..4e1b747c0
--- /dev/null
+++ b/lib/igt_gpu_power.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef IGT_GPU_POWER_H
+#define IGT_GPU_POWER_H
+
+#include
+#include
+
+struct gpu_power {
+ int fd;
+
[Intel-gfx] [PATCH i-g-t 04/19] i915/gem_exec_schedule: Measure semaphore power consumption
How much energy does spinning on a semaphore consume relative to plain
old spinning?
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_schedule.c | 72 +-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index a9383000a..4f0577b4e 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -29,9 +29,10 @@
#include
#include "igt.h"
-#include "igt_vgem.h"
+#include "igt_gpu_power.h"
#include "igt_rand.h"
#include "igt_sysfs.h"
+#include "igt_vgem.h"
#include "i915/gem_ring.h"
#define LO 0
@@ -1202,6 +1203,65 @@ static void test_pi_ringfull(int fd, unsigned int engine)
munmap(result, 4096);
}
+static void measure_semaphore_power(int i915)
+{
+ struct gpu_power power;
+ unsigned int engine, signaler;
+
+ igt_require(gpu_power_open() == 0);
+
+ for_each_physical_engine(i915, signaler) {
+ struct gpu_power_sample s_spin[2];
+ struct gpu_power_sample s_sema[2];
+ double baseline, total;
+ int64_t jiffie = 1;
+ igt_spin_t *spin;
+
+ spin = __igt_spin_batch_new(i915,
+ .engine = signaler,
+ .flags = IGT_SPIN_POLL_RUN);
+ gem_wait(i915, spin->handle, ); /* waitboost */
+ igt_assert(spin->running);
+ igt_spin_busywait_until_running(spin);
+
+ gpu_power_read(, _spin[0]);
+ usleep(100*1000);
+ gpu_power_read(, _spin[1]);
+
+ /* Add a waiter to each engine */
+ for_each_physical_engine(i915, engine) {
+ igt_spin_t *sema;
+
+ if (engine == signaler)
+ continue;
+
+ sema = __igt_spin_batch_new(i915,
+ .engine = engine,
+ .dependency = spin->handle);
+
+ igt_spin_batch_free(i915, sema);
+ }
+ usleep(10); /* just give the tasklets a chance to run */
+
+ gpu_power_read(, _sema[0]);
+ usleep(100*1000);
+ gpu_power_read(, _sema[1]);
+
+ igt_spin_batch_free(i915, spin);
+
+ baseline = gpu_power_W(, _spin[0], _spin[1]);
+ total = gpu_power_W(, _sema[0], _sema[1]);
+
+ igt_info("%s: %.1fmW + %.1fmW (total %1.fmW)\n",
+e__->name,
+1e3 * baseline,
+1e3 * (total - baseline),
+1e3 * total);
+ }
+
+ gpu_power_close();
+}
+
igt_main
{
const struct intel_execution_engine *e;
@@ -1362,6 +1422,16 @@ igt_main
}
}
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(gem_scheduler_enabled(fd));
+ igt_require(gem_scheduler_has_semaphores(fd));
+ }
+
+ igt_subtest("semaphore-power")
+ measure_semaphore_power(fd);
+ }
+
igt_fixture {
igt_stop_hang_detector();
close(fd);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 17/19] i915: Add gem_ctx_engines
To exercise the new I915_CONTEXT_PARAM_ENGINES and interactions with
gem_execbuf().
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Andi Shyti
---
tests/Makefile.sources | 1 +
tests/i915/gem_ctx_engines.c | 368 +++
tests/meson.build| 1 +
3 files changed, 370 insertions(+)
create mode 100644 tests/i915/gem_ctx_engines.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 9e0dab02e..41e756f15 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -21,6 +21,7 @@ TESTS_progs = \
drm_import_export \
drm_mm \
drm_read \
+ i915/gem_ctx_engines \
i915/gem_ctx_shared \
kms_3d \
kms_addfb_basic \
diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
new file mode 100644
index 0..acfdafa9c
--- /dev/null
+++ b/tests/i915/gem_ctx_engines.c
@@ -0,0 +1,368 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "i915/gem_context.h"
+
+#define engine_class(e, n) ((e)->class_instance[(n)].engine_class)
+#define engine_instance(e, n) ((e)->class_instance[(n)].engine_instance)
+
+static bool has_context_engines(int i915)
+{
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = 0,
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ };
+ return __gem_context_set_param(i915, ) == 0;
+}
+
+static void invalid_engines(int i915)
+{
+ struct i915_context_param_engines stack = {}, *engines;
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(),
+ };
+ uint32_t handle;
+ void *ptr;
+
+ param.size = 0;
+ igt_assert_eq(__gem_context_set_param(i915, ), 0);
+
+ param.size = 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EINVAL);
+
+ param.size = sizeof(stack) - 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EINVAL);
+
+ param.size = sizeof(stack) + 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EINVAL);
+
+ param.size = 0;
+ igt_assert_eq(__gem_context_set_param(i915, ), 0);
+
+ /* Create a single page surrounded by inaccessible nothingness */
+ ptr = mmap(NULL, 3 * 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
+ igt_assert(ptr != MAP_FAILED);
+
+ munmap(ptr, 4096);
+ engines = ptr + 4096;
+ munmap(ptr + 2 *4096, 4096);
+
+ param.size = sizeof(*engines) + sizeof(*engines->class_instance);
+ param.value = to_user_pointer(engines);
+
+ engines->class_instance[0].engine_class = -1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -ENOENT);
+
+ mprotect(engines, 4096, PROT_READ);
+ igt_assert_eq(__gem_context_set_param(i915, ), -ENOENT);
+
+ mprotect(engines, 4096, PROT_WRITE);
+ engines->class_instance[0].engine_class = 0;
+ if (__gem_context_set_param(i915, )) /* XXX needs RCS */
+ goto out;
+
+ engines->extensions = to_user_pointer(ptr);
+ igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+ engines->extensions = 0;
+ igt_assert_eq(__gem_context_set_param(i915, ), 0);
+
+ param.value = to_user_pointer(engines - 1);
+ igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+ param.value = to_user_pointer(engines) - 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+ param.value = to_user_pointer(engines) - param.size + 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+ param.value =
[Intel-gfx] [PATCH i-g-t 05/19] i915/gem_exec_whisper: Measure total power consumed
Show the total power consumed across all the whispers.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_whisper.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_whisper.c b/tests/i915/gem_exec_whisper.c
index 0b15fe431..6c3b53756 100644
--- a/tests/i915/gem_exec_whisper.c
+++ b/tests/i915/gem_exec_whisper.c
@@ -28,8 +28,9 @@
*/
#include "igt.h"
-#include "igt_gt.h"
#include "igt_debugfs.h"
+#include "igt_gpu_power.h"
+#include "igt_gt.h"
#include "igt_rand.h"
#include "igt_sysfs.h"
@@ -192,6 +193,8 @@ static void whisper(int fd, unsigned engine, unsigned flags)
unsigned int reloc_migrations = 0;
unsigned int reloc_interruptions = 0;
unsigned int eb_migrations = 0;
+ struct gpu_power_sample sample[2];
+ struct gpu_power power;
uint64_t old_offset;
int i, n, loc;
int debugfs;
@@ -202,6 +205,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
}
debugfs = igt_debugfs_dir(fd);
+ gpu_power_open();
nengine = 0;
if (engine == ALL_ENGINES) {
@@ -226,6 +230,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
init_hang();
intel_detect_and_clear_missed_interrupts(fd);
+ gpu_power_read(, [0]);
igt_fork(child, flags & FORKED ? sysconf(_SC_NPROCESSORS_ONLN) : 1) {
unsigned int pass;
@@ -495,6 +500,10 @@ static void whisper(int fd, unsigned engine, unsigned
flags)
fini_hang();
else
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+ if (gpu_power_read(, [1])) {
+ igt_info("Total energy used: %.1fmJ\n",
+gpu_power_J(, [0], [1]) * 1e3);
+ }
close(debugfs);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 07/19] i915/gem_exec_nop: poll-sequential requires ordering between rings
In order to correctly serialise the order of execution between rings, we
need to flag the scratch address as being written. Make it so.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_nop.c | 152 +-
1 file changed, 133 insertions(+), 19 deletions(-)
diff --git a/tests/i915/gem_exec_nop.c b/tests/i915/gem_exec_nop.c
index 59a08ad08..b91b4d0f6 100644
--- a/tests/i915/gem_exec_nop.c
+++ b/tests/i915/gem_exec_nop.c
@@ -104,7 +104,7 @@ static double nop_on_ring(int fd, uint32_t handle, unsigned
ring_id,
return elapsed(, );
}
-static void poll_ring(int fd, unsigned ring, const char *name, int timeout)
+static void poll_ring(int fd, unsigned engine, const char *name, int timeout)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
const uint32_t MI_ARB_CHK = 0x5 << 23;
@@ -112,29 +112,17 @@ static void poll_ring(int fd, unsigned ring, const char
*name, int timeout)
struct drm_i915_gem_exec_object2 obj;
struct drm_i915_gem_relocation_entry reloc[4], *r;
uint32_t *bbe[2], *state, *batch;
- unsigned engines[16], nengine, flags;
struct timespec tv = {};
unsigned long cycles;
+ unsigned flags;
uint64_t elapsed;
flags = I915_EXEC_NO_RELOC;
if (gen == 4 || gen == 5)
flags |= I915_EXEC_SECURE;
- nengine = 0;
- if (ring == ALL_ENGINES) {
- for_each_physical_engine(fd, ring) {
- if (!gem_can_store_dword(fd, ring))
- continue;
-
- engines[nengine++] = ring;
- }
- } else {
- gem_require_ring(fd, ring);
- igt_require(gem_can_store_dword(fd, ring));
- engines[nengine++] = ring;
- }
- igt_require(nengine);
+ gem_require_ring(fd, engine);
+ igt_require(gem_can_store_dword(fd, engine));
memset(, 0, sizeof(obj));
obj.handle = gem_create(fd, 4096);
@@ -198,7 +186,7 @@ static void poll_ring(int fd, unsigned ring, const char
*name, int timeout)
memset(, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer();
execbuf.buffer_count = 1;
- execbuf.flags = engines[0];
+ execbuf.flags = engine | flags;
cycles = 0;
do {
@@ -208,7 +196,6 @@ static void poll_ring(int fd, unsigned ring, const char
*name, int timeout)
execbuf.batch_start_offset =
(bbe[idx] - batch) * sizeof(*batch) - 64;
- execbuf.flags = engines[cycles % nengine] | flags;
gem_execbuf(fd, );
*bbe[!idx] = MI_BATCH_BUFFER_END;
@@ -227,6 +214,133 @@ static void poll_ring(int fd, unsigned ring, const char
*name, int timeout)
gem_close(fd, obj.handle);
}
+static void poll_sequential(int fd, const char *name, int timeout)
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ const uint32_t MI_ARB_CHK = 0x5 << 23;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_relocation_entry reloc[4], *r;
+ uint32_t *bbe[2], *state, *batch;
+ unsigned engines[16], nengine, engine, flags;
+ struct timespec tv = {};
+ unsigned long cycles;
+ uint64_t elapsed;
+ bool cached;
+
+ flags = I915_EXEC_NO_RELOC;
+ if (gen == 4 || gen == 5)
+ flags |= I915_EXEC_SECURE;
+
+ nengine = 0;
+ for_each_physical_engine(fd, engine) {
+ if (!gem_can_store_dword(fd, engine))
+ continue;
+
+ engines[nengine++] = engine;
+ }
+ igt_require(nengine);
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = gem_create(fd, 4096);
+ obj[0].flags = EXEC_OBJECT_WRITE;
+ cached = __gem_set_caching(fd, obj[0].handle, 1) == 0;
+ obj[1].handle = gem_create(fd, 4096);
+ obj[1].relocs_ptr = to_user_pointer(reloc);
+ obj[1].relocation_count = ARRAY_SIZE(reloc);
+
+ r = memset(reloc, 0, sizeof(reloc));
+ batch = gem_mmap__wc(fd, obj[1].handle, 0, 4096, PROT_WRITE);
+
+ for (unsigned int start_offset = 0;
+start_offset <= 128;
+start_offset += 128) {
+ uint32_t *b = batch + start_offset / sizeof(*batch);
+
+ r->target_handle = obj[0].handle;
+ r->offset = (b - batch + 1) * sizeof(uint32_t);
+ r->delta = 0;
+ r->read_domains = I915_GEM_DOMAIN_RENDER;
+ r->write_domain = I915_GEM_DOMAIN_RENDER;
+
+ *b = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ *++b = r->delta;
+ *++b = 0;
+ } else if (gen >= 4) {
+ r->offset += sizeof(uint32_t);
+ *++b = 0;
+ *++b
[Intel-gfx] [PATCH i-g-t 14/19] igt/gem_ctx_switch: Exercise queues
Queues are a form of contexts that share vm and enfore a single timeline
across all engines. Test switching between them, just like ordinary
contexts.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_switch.c | 75 +++--
1 file changed, 55 insertions(+), 20 deletions(-)
diff --git a/tests/i915/gem_ctx_switch.c b/tests/i915/gem_ctx_switch.c
index 87e13b915..647911d4c 100644
--- a/tests/i915/gem_ctx_switch.c
+++ b/tests/i915/gem_ctx_switch.c
@@ -44,7 +44,8 @@
#define LOCAL_I915_EXEC_NO_RELOC (1<<11)
#define LOCAL_I915_EXEC_HANDLE_LUT (1<<12)
-#define INTERRUPTIBLE 1
+#define INTERRUPTIBLE 0x1
+#define QUEUE 0x2
static double elapsed(const struct timespec *start, const struct timespec *end)
{
@@ -126,8 +127,12 @@ static void single(int fd, uint32_t handle,
gem_require_ring(fd, e->exec_id | e->flags);
- for (n = 0; n < 64; n++)
- contexts[n] = gem_context_create(fd);
+ for (n = 0; n < 64; n++) {
+ if (flags & QUEUE)
+ contexts[n] = gem_queue_create(fd);
+ else
+ contexts[n] = gem_context_create(fd);
+ }
memset(, 0, sizeof(obj));
obj.handle = handle;
@@ -232,8 +237,12 @@ static void all(int fd, uint32_t handle, unsigned flags,
int timeout)
}
igt_require(nengine);
- for (n = 0; n < ARRAY_SIZE(contexts); n++)
- contexts[n] = gem_context_create(fd);
+ for (n = 0; n < ARRAY_SIZE(contexts); n++) {
+ if (flags & QUEUE)
+ contexts[n] = gem_queue_create(fd);
+ else
+ contexts[n] = gem_context_create(fd);
+ }
memset(obj, 0, sizeof(obj));
obj[1].handle = handle;
@@ -298,6 +307,17 @@ igt_main
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
const struct intel_execution_engine *e;
+ static const struct {
+ const char *name;
+ unsigned int flags;
+ bool (*require)(int fd);
+ } phases[] = {
+ { "", 0, NULL },
+ { "-interruptible", INTERRUPTIBLE, NULL },
+ { "-queue", QUEUE, gem_has_queues },
+ { "-queue-interruptible", QUEUE | INTERRUPTIBLE, gem_has_queues
},
+ { }
+ };
uint32_t light = 0, heavy;
int fd = -1;
@@ -319,21 +339,26 @@ igt_main
}
for (e = intel_execution_engines; e->name; e++) {
- igt_subtest_f("%s%s", e->exec_id == 0 ? "basic-" : "", e->name)
- single(fd, light, e, 0, 1, 5);
-
- igt_skip_on_simulation();
-
- igt_subtest_f("%s%s-heavy", e->exec_id == 0 ? "basic-" : "",
e->name)
- single(fd, heavy, e, 0, 1, 5);
- igt_subtest_f("%s-interruptible", e->name)
- single(fd, light, e, INTERRUPTIBLE, 1, 150);
- igt_subtest_f("forked-%s", e->name)
- single(fd, light, e, 0, ncpus, 150);
- igt_subtest_f("forked-%s-heavy", e->name)
- single(fd, heavy, e, 0, ncpus, 150);
- igt_subtest_f("forked-%s-interruptible", e->name)
- single(fd, light, e, INTERRUPTIBLE, ncpus, 150);
+ for (typeof(*phases) *p = phases; p->name; p++) {
+ igt_subtest_group {
+ igt_fixture {
+ if (p->require)
+ igt_require(p->require(fd));
+ }
+
+ igt_subtest_f("%s%s%s", e->exec_id == 0 ?
"basic-" : "", e->name, p->name)
+ single(fd, light, e, p->flags, 1, 5);
+
+ igt_skip_on_simulation();
+
+ igt_subtest_f("%s%s-heavy%s", e->exec_id == 0 ?
"basic-" : "", e->name, p->name)
+ single(fd, heavy, e, p->flags, 1, 5);
+ igt_subtest_f("forked-%s%s", e->name, p->name)
+ single(fd, light, e, p->flags, ncpus,
150);
+ igt_subtest_f("forked-%s-heavy%s", e->name,
p->name)
+ single(fd, heavy, e, p->flags, ncpus,
150);
+ }
+ }
}
igt_subtest("basic-all-light")
@@ -341,6 +366,16 @@ igt_main
igt_subtest("basic-all-heavy")
all(fd, heavy, 0, 5);
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(gem_has_queues(fd));
+ }
+ igt_subtest("basic-queue-light")
+ all(fd, light, QUEUE, 5);
+ igt_subtest("basic-queue-heavy")
+ all(fd, heavy, QUEUE, 5);
+ }
+
[Intel-gfx] [PATCH i-g-t 01/19] i915/gem_ppgtt: Estimate resource usage and bail if it means swapping!
fi-kbl-guc's swap ran dry while running blt-vs-render-ctxN, which is
midly concerning but conceivable as we never checked there was enough
memory to run the test to begin with.
Each child needs to keep its own surface and possible a pair of logical
contexts (one for rcs and one for bcs) so check that there is enough
memory to allow all children to co-exist. During execution, we require
another surface and batch, but these are temporary and so should fit
fine with a small amount of thrashing on the boundary.
References: https://bugs.freedesktop.org/show_bug.cgi?id=109801
Signed-off-by: Chris Wilson
---
tests/i915/gem_ppgtt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
index 11ca31e74..9409bef14 100644
--- a/tests/i915/gem_ppgtt.c
+++ b/tests/i915/gem_ppgtt.c
@@ -91,8 +91,14 @@ static void fork_rcs_copy(int timeout, uint32_t final,
#define CREATE_CONTEXT 0x1
{
igt_render_copyfunc_t render_copy;
+ uint64_t mem_per_child;
int devid;
+ mem_per_child = SIZE;
+ if (flags & CREATE_CONTEXT)
+ mem_per_child += 2 * 128 * 1024; /* rough context sizes */
+ intel_require_memory(mem_per_child, count, CHECK_RAM);
+
for (int child = 0; child < count; child++) {
int fd = drm_open_driver(DRIVER_INTEL);
drm_intel_bufmgr *bufmgr;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 08/19] i915/gem_sync: Make switch-default asymmetric
To make the demonstration of the cheeky preemption more impactful, make
the second context a nop to contrast the first being 1024
MI_STORE_DWORD_IMM. Then if we execute and wait on the second context
before executing the first, the client latency is even more drastically
reduced.
To more clearly show any effect on wait reordering, measure the
alternative path and present both.
Signed-off-by: Chris Wilson
---
tests/i915/gem_sync.c | 40 +---
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/tests/i915/gem_sync.c b/tests/i915/gem_sync.c
index fb209977d..3e4feff32 100644
--- a/tests/i915/gem_sync.c
+++ b/tests/i915/gem_sync.c
@@ -651,7 +651,7 @@ switch_ring(int fd, unsigned ring, int num_children, int
timeout)
struct drm_i915_gem_relocation_entry reloc[1024];
struct drm_i915_gem_execbuffer2 execbuf;
} contexts[2];
- double start, elapsed;
+ double elapsed, baseline;
unsigned long cycles;
for (int i = 0; i < ARRAY_SIZE(contexts); i++) {
@@ -679,7 +679,7 @@ switch_ring(int fd, unsigned ring, int num_children, int
timeout)
c->object[1].handle = gem_create(fd, sz);
c->object[1].relocs_ptr = to_user_pointer(c->reloc);
- c->object[1].relocation_count = 1024;
+ c->object[1].relocation_count = 1024 * i;
batch = gem_mmap__cpu(fd, c->object[1].handle, 0, sz,
PROT_WRITE | PROT_READ);
@@ -688,7 +688,7 @@ switch_ring(int fd, unsigned ring, int num_children, int
timeout)
memset(c->reloc, 0, sizeof(c->reloc));
b = batch;
- for (int r = 0; r < 1024; r++) {
+ for (int r = 0; r < c->object[1].relocation_count; r++)
{
uint64_t offset;
c->reloc[r].presumed_offset =
c->object[0].offset;
@@ -722,26 +722,44 @@ switch_ring(int fd, unsigned ring, int num_children, int
timeout)
}
cycles = 0;
- elapsed = 0;
- start = gettime();
- do {
+ baseline = 0;
+ igt_until_timeout(timeout) {
do {
double this;
- gem_execbuf(fd, [0].execbuf);
gem_execbuf(fd, [1].execbuf);
+ gem_execbuf(fd, [0].execbuf);
this = gettime();
gem_sync(fd, contexts[1].object[1].handle);
- elapsed += gettime() - this;
+ gem_sync(fd, contexts[0].object[1].handle);
+ baseline += gettime() - this;
+ } while (++cycles & 1023);
+ }
+ baseline /= cycles;
+
+ cycles = 0;
+ elapsed = 0;
+ igt_until_timeout(timeout) {
+ do {
+ double this;
+ gem_execbuf(fd, [1].execbuf);
+ gem_execbuf(fd, [0].execbuf);
+
+ this = gettime();
gem_sync(fd, contexts[0].object[1].handle);
+ elapsed += gettime() - this;
+
+ gem_sync(fd, contexts[1].object[1].handle);
} while (++cycles & 1023);
- } while ((gettime() - start) < timeout);
- igt_info("%s%sompleted %ld cycles: %.3f us\n",
+ }
+ elapsed /= cycles;
+
+ igt_info("%s%sompleted %ld cycles: %.3f us, baseline %.3f us\n",
names[child % num_engines] ?: "",
names[child % num_engines] ? " c" : "C",
-cycles, elapsed*1e6/cycles);
+cycles, elapsed*1e6, baseline*1e6);
for (int i = 0; i < ARRAY_SIZE(contexts); i++) {
gem_close(fd, contexts[i].object[1].handle);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 06/19] i915/gem_exec_schedule: Verify that using HW semaphores doesn't block
We may use HW semaphores to schedule nearly-ready work such that they
are already spinning on the GPU waiting for the completion on another
engine. However, we don't want for that spinning task to actually block
any real work should it be scheduled.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_schedule.c | 87 ++
1 file changed, 87 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 4f0577b4e..ae850c4a3 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -48,6 +48,10 @@
#define MAX_CONTEXTS 1024
+#define LOCAL_I915_EXEC_BSD_SHIFT (13)
+#define LOCAL_I915_EXEC_BSD_MASK (3 << LOCAL_I915_EXEC_BSD_SHIFT)
+#define ENGINE_MASK (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
+
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
static inline
@@ -320,6 +324,86 @@ static void smoketest(int fd, unsigned ring, unsigned
timeout)
}
}
+static uint32_t __batch_create(int i915, uint32_t offset)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(i915, ALIGN(offset + 4, 4096));
+ gem_write(i915, handle, offset, , sizeof(bbe));
+
+ return handle;
+}
+
+static uint32_t batch_create(int i915)
+{
+ return __batch_create(i915, 0);
+}
+
+static void semaphore_userlock(int i915)
+{
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = batch_create(i915),
+ };
+ igt_spin_t *spin = NULL;
+ unsigned int engine;
+ uint32_t scratch;
+
+ igt_require(gem_scheduler_has_preemption(i915));
+
+ /*
+* Given the use of semaphores to govern parallel submission
+* of nearly-ready work to HW, we still want to run actually
+* ready work immediately. Without semaphores, the dependent
+* work wouldn't be submitted so our ready work will run.
+*/
+
+ scratch = gem_create(i915, 4096);
+ for_each_physical_engine(i915, engine) {
+ if (!spin) {
+ spin = igt_spin_batch_new(i915,
+ .dependency = scratch,
+ .engine = engine);
+ } else {
+ typeof(spin->execbuf.flags) saved = spin->execbuf.flags;
+
+ spin->execbuf.flags &= ~ENGINE_MASK;
+ spin->execbuf.flags |= engine;
+
+ gem_execbuf(i915, >execbuf);
+
+ spin->execbuf.flags = saved;
+ }
+ }
+ igt_require(spin);
+ gem_close(i915, scratch);
+
+ /*
+* On all dependent engines, the request may be executing (busywaiting
+* on a HW semaphore) but it should not prevent any real work from
+* taking precedence.
+*/
+ scratch = gem_context_create(i915);
+ for_each_physical_engine(i915, engine) {
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(),
+ .buffer_count = 1,
+ .flags = engine,
+ .rsvd1 = scratch,
+ };
+
+ if (engine == (spin->execbuf.flags & ENGINE_MASK))
+ continue;
+
+ gem_execbuf(i915, );
+ }
+ gem_context_destroy(i915, scratch);
+ gem_sync(i915, obj.handle); /* to hang unless we can preempt */
+ gem_close(i915, obj.handle);
+
+ igt_spin_batch_free(i915, spin);
+}
+
static void reorder(int fd, unsigned ring, unsigned flags)
#define EQUAL 1
{
@@ -1307,6 +1391,9 @@ igt_main
igt_require(gem_scheduler_has_ctx_priority(fd));
}
+ igt_subtest("semaphore-user")
+ semaphore_userlock(fd);
+
igt_subtest("smoketest-all")
smoketest(fd, ALL_ENGINES, 30);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 10/19] i915/gem_exec_big: Add a single shot test
CI complains that the exhaustive test of trying every size up to the
limit is too slow, so add a simple test that tries to submit one
extreme batch buffer and check all the relocations land.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=10
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_big.c| 70 ++--
tests/intel-ci/blacklist.txt | 1 +
2 files changed, 60 insertions(+), 11 deletions(-)
diff --git a/tests/i915/gem_exec_big.c b/tests/i915/gem_exec_big.c
index a15672f66..015f59e29 100644
--- a/tests/i915/gem_exec_big.c
+++ b/tests/i915/gem_exec_big.c
@@ -71,7 +71,7 @@ static void exec1(int fd, uint32_t handle, uint64_t
reloc_ofs, unsigned flags, c
gem_exec[0].relocs_ptr = to_user_pointer(gem_reloc);
gem_exec[0].alignment = 0;
gem_exec[0].offset = 0;
- gem_exec[0].flags = 0;
+ gem_exec[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
gem_exec[0].rsvd1 = 0;
gem_exec[0].rsvd2 = 0;
@@ -154,12 +154,11 @@ static void execN(int fd, uint32_t handle, uint64_t
batch_size, unsigned flags,
gem_exec[0].handle = handle;
gem_exec[0].relocation_count = nreloc;
gem_exec[0].relocs_ptr = to_user_pointer(gem_reloc);
+ gem_exec[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
memset(, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(gem_exec);
execbuf.buffer_count = 1;
- execbuf.batch_start_offset = 0;
- execbuf.batch_len = 8;
execbuf.flags = flags;
/* Avoid hitting slowpaths in the reloc processing which might yield a
@@ -197,16 +196,10 @@ static void execN(int fd, uint32_t handle, uint64_t
batch_size, unsigned flags,
#undef reloc_ofs
}
-igt_simple_main
+static void exhaustive(int fd)
{
uint32_t batch[2] = {MI_BATCH_BUFFER_END};
uint64_t batch_size, max, ggtt_max, reloc_ofs;
- int fd;
-
- fd = drm_open_driver(DRIVER_INTEL);
- igt_require_gem(fd);
-
- use_64bit_relocs = intel_gen(intel_get_drm_devid(fd)) >= 8;
max = 3 * gem_aperture_size(fd) / 4;
ggtt_max = 3 * gem_global_aperture_size(fd) / 4;
@@ -258,6 +251,61 @@ igt_simple_main
else
batch_size *= 2;
}
+}
+
+static void single(int i915)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint64_t batch_size, limit;
+ uint32_t handle;
+ void *ptr;
+
+ batch_size = (intel_get_avail_ram_mb() - 128) << 20; /* CI slack */
+ limit = gem_aperture_size(i915) - (256 << 10); /* low pages reserved */
+ if (!gem_uses_full_ppgtt(i915))
+ limit = 3 * limit / 4;
+
+ batch_size = min(batch_size, limit);
+ batch_size = ALIGN(batch_size, 4096);
+ igt_info("Submitting a %'"PRId64"MiB batch, %saperture size
%'"PRId64"MiB\n",
+batch_size >> 20,
+gem_uses_full_ppgtt(i915) ? "" : "shared ",
+gem_aperture_size(i915) >> 20);
+ intel_require_memory(1, batch_size, CHECK_RAM);
+
+ handle = gem_create(i915, batch_size);
+ gem_write(i915, handle, 0, , sizeof(bbe));
+
+ if (!FORCE_PREAD_PWRITE && gem_has_llc(i915))
+ ptr = __gem_mmap__cpu(i915, handle, 0, batch_size, PROT_READ);
+ else if (!FORCE_PREAD_PWRITE && gem_mmap__has_wc(i915))
+ ptr = __gem_mmap__wc(i915, handle, 0, batch_size, PROT_READ);
+ else
+ ptr = NULL;
+
+ execN(i915, handle, batch_size, 0, ptr);
+
+ if (ptr)
+ munmap(ptr, batch_size);
+}
+
+igt_main
+{
+ int i915 = -1;
+
+ igt_fixture {
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+
+ use_64bit_relocs = intel_gen(intel_get_drm_devid(i915)) >= 8;
+ }
+
+ igt_subtest("single")
+ single(i915);
+
+ igt_subtest("exhaustive")
+ exhaustive(i915);
- close(fd);
+ igt_fixture
+ close(i915);
}
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index a2101ae71..ae61efe3f 100644
--- a/tests/intel-ci/blacklist.txt
+++ b/tests/intel-ci/blacklist.txt
@@ -28,6 +28,7 @@ igt@gem_ctx_thrash(@.*)?
igt@gem_evict_alignment(@.*)?
igt@gem_evict_everything(@.*)?
igt@gem_exec_alignment@(?!.*single).*
+igt@gem_exec_big@(?!.*single).*
igt@gem_exec_capture@many-(?!4K-).*
igt@gem_exec_fence@(?!.*basic).*
igt@gem_exec_flush@(?!.*basic).*
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 09/19] i915/gem_ctx_param: Remove kneecapping
The invalid set/get tests do not serve the purpose of detecting whether
or not invalid parameters are indeed detect correctly -- simply because
the kernel is the arbiter of what is invalid and this test second
guesses that and is wrong.
The intent of this test was to ensure that we didn't include any holes
in the parameter space that may have been used for nefarious undisclosed
purposes, i.e. the maintainer's job backed up by reviewers.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
tests/i915/gem_ctx_param.c | 16
1 file changed, 16 deletions(-)
diff --git a/tests/i915/gem_ctx_param.c b/tests/i915/gem_ctx_param.c
index acc1e6297..b3f8637df 100644
--- a/tests/i915/gem_ctx_param.c
+++ b/tests/i915/gem_ctx_param.c
@@ -296,22 +296,6 @@ igt_main
/* I915_CONTEXT_PARAM_SSEU tests are located in gem_ctx_sseu.c */
- /* NOTE: This testcase intentionally tests for the next free parameter
-* to catch ABI extensions. Don't "fix" this testcase without adding all
-* the tests for the new param first.
-*/
- arg.param = I915_CONTEXT_PARAM_SSEU + 1;
-
- igt_subtest("invalid-param-get") {
- arg.ctx_id = ctx;
- igt_assert_eq(__gem_context_get_param(fd, ), -EINVAL);
- }
-
- igt_subtest("invalid-param-set") {
- arg.ctx_id = ctx;
- igt_assert_eq(__gem_context_set_param(fd, ), -EINVAL);
- }
-
igt_fixture
close(fd);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 15/19] igt/gem_exec_whisper: Fork all-engine tests one-per-engine
Add a new mode for some more stress, submit the all-engines tests
simultaneously, a stream per engine.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_whisper.c | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/tests/i915/gem_exec_whisper.c b/tests/i915/gem_exec_whisper.c
index d3e0b0ba2..d5afc8119 100644
--- a/tests/i915/gem_exec_whisper.c
+++ b/tests/i915/gem_exec_whisper.c
@@ -88,6 +88,7 @@ static void verify_reloc(int fd, uint32_t handle,
#define SYNC 0x40
#define PRIORITY 0x80
#define QUEUES 0x100
+#define ALL 0x200
struct hang {
struct drm_i915_gem_exec_object2 obj;
@@ -199,6 +200,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
uint64_t old_offset;
int i, n, loc;
int debugfs;
+ int nchild;
if (flags & PRIORITY) {
igt_require(gem_scheduler_enabled(fd));
@@ -215,6 +217,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
engines[nengine++] = engine;
}
} else {
+ igt_assert(!(flags & ALL));
igt_require(gem_has_ring(fd, engine));
igt_require(gem_can_store_dword(fd, engine));
engines[nengine++] = engine;
@@ -233,11 +236,22 @@ static void whisper(int fd, unsigned engine, unsigned
flags)
if (flags & HANG)
init_hang();
+ nchild = 1;
+ if (flags & FORKED)
+ nchild *= sysconf(_SC_NPROCESSORS_ONLN);
+ if (flags & ALL)
+ nchild *= nengine;
+
intel_detect_and_clear_missed_interrupts(fd);
gpu_power_read(, [0]);
- igt_fork(child, flags & FORKED ? sysconf(_SC_NPROCESSORS_ONLN) : 1) {
+ igt_fork(child, nchild) {
unsigned int pass;
+ if (flags & ALL) {
+ engines[0] = engines[child % nengine];
+ nengine = 1;
+ }
+
memset(, 0, sizeof(scratch));
scratch.handle = gem_create(fd, 4096);
scratch.flags = EXEC_OBJECT_WRITE;
@@ -341,7 +355,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
igt_until_timeout(150) {
uint64_t offset;
- if (!(flags & FORKED))
+ if (nchild == 1)
write_seqno(debugfs, pass);
if (flags & HANG)
@@ -382,8 +396,8 @@ static void whisper(int fd, unsigned engine, unsigned flags)
gem_write(fd, batches[1023].handle, loc, ,
sizeof(pass));
for (n = 1024; --n >= 1; ) {
+ uint32_t handle[2] = {};
int this_fd = fd;
- uint32_t handle[2];
execbuf.buffers_ptr =
to_user_pointer([n-1]);
reloc_migrations += batches[n-1].offset
!= inter[n].presumed_offset;
@@ -550,7 +564,7 @@ igt_main
{ "queues-sync", QUEUES | SYNC },
{ NULL }
};
- int fd;
+ int fd = -1;
igt_fixture {
fd = drm_open_driver_master(DRIVER_INTEL);
@@ -561,9 +575,12 @@ igt_main
igt_fork_hang_detector(fd);
}
- for (const struct mode *m = modes; m->name; m++)
+ for (const struct mode *m = modes; m->name; m++) {
igt_subtest_f("%s", m->name)
whisper(fd, ALL_ENGINES, m->flags);
+ igt_subtest_f("%s-all", m->name)
+ whisper(fd, ALL_ENGINES, m->flags | ALL);
+ }
for (const struct intel_execution_engine *e = intel_execution_engines;
e->name; e++) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 13/19] i915: Exercise creating context with shared GTT
v2: Test each shared context is its own timeline and allows request
reordering between shared contexts.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Michal Wajdeczko
---
lib/i915/gem_context.c| 68 +++
lib/i915/gem_context.h| 13 +
tests/Makefile.sources| 1 +
tests/i915/gem_ctx_shared.c | 894 ++
tests/i915/gem_exec_whisper.c | 32 +-
tests/meson.build | 1 +
6 files changed, 1000 insertions(+), 9 deletions(-)
create mode 100644 tests/i915/gem_ctx_shared.c
diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 16004685e..3212d529f 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -275,3 +275,71 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int
prio)
{
igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
}
+
+int
+__gem_context_clone(int i915,
+ uint32_t src, unsigned int share,
+ unsigned int flags,
+ uint32_t *out)
+{
+ struct drm_i915_gem_context_create_ext_clone clone = {
+ { .name = I915_CONTEXT_CREATE_EXT_CLONE },
+ .clone = src,
+ .flags = share,
+ };
+ struct drm_i915_gem_context_create_ext arg = {
+ .flags = flags | I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ .extensions = to_user_pointer(),
+ };
+ int err = 0;
+
+ if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, ))
+ err = -errno;
+
+ *out = arg.ctx_id;
+
+ errno = 0;
+ return err;
+}
+
+static bool __gem_context_has(int i915, uint32_t share, unsigned int flags)
+{
+ uint32_t ctx;
+
+ __gem_context_clone(i915, 0, share, flags, );
+ if (ctx)
+ gem_context_destroy(i915, ctx);
+
+ errno = 0;
+ return ctx;
+}
+
+bool gem_contexts_has_shared_gtt(int i915)
+{
+ return __gem_context_has(i915, I915_CONTEXT_CLONE_VM, 0);
+}
+
+bool gem_has_queues(int i915)
+{
+ return __gem_context_has(i915,
+I915_CONTEXT_CLONE_VM,
+I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE);
+}
+
+uint32_t gem_context_clone(int i915,
+ uint32_t src, unsigned int share,
+ unsigned int flags)
+{
+ uint32_t ctx;
+
+ igt_assert_eq(__gem_context_clone(i915, src, share, flags, ), 0);
+
+ return ctx;
+}
+
+uint32_t gem_queue_create(int i915)
+{
+ return gem_context_clone(i915, 0,
+I915_CONTEXT_CLONE_VM,
+I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE);
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index aef68dda6..ce2617980 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -29,6 +29,19 @@ int __gem_context_create(int fd, uint32_t *ctx_id);
void gem_context_destroy(int fd, uint32_t ctx_id);
int __gem_context_destroy(int fd, uint32_t ctx_id);
+int __gem_context_clone(int i915,
+ uint32_t src, unsigned int share,
+ unsigned int flags,
+ uint32_t *out);
+uint32_t gem_context_clone(int i915,
+ uint32_t src, unsigned int share,
+ unsigned int flags);
+
+uint32_t gem_queue_create(int i915);
+
+bool gem_contexts_has_shared_gtt(int i915);
+bool gem_has_queues(int i915);
+
bool gem_has_contexts(int fd);
void gem_require_contexts(int fd);
void gem_context_require_bannable(int fd);
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 71ccf00af..9e0dab02e 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -21,6 +21,7 @@ TESTS_progs = \
drm_import_export \
drm_mm \
drm_read \
+ i915/gem_ctx_shared \
kms_3d \
kms_addfb_basic \
kms_atomic \
diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
new file mode 100644
index 0..51e4b2dd6
--- /dev/null
+++ b/tests/i915/gem_ctx_shared.c
@@ -0,0 +1,894 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
[Intel-gfx] [PATCH i-g-t 02/19] lib/i915: Pretty print HW semaphores
Include whether the scheduler is using HW semaphore assistance in our
pretty debug strings, and make the caps known for requires.
Signed-off-by: Chris Wilson
---
lib/i915/gem_scheduler.c | 22 +++---
lib/i915/gem_scheduler.h | 2 ++
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/lib/i915/gem_scheduler.c b/lib/i915/gem_scheduler.c
index ad156306f..f9e052278 100644
--- a/lib/i915/gem_scheduler.c
+++ b/lib/i915/gem_scheduler.c
@@ -67,7 +67,7 @@ unsigned gem_scheduler_capability(int fd)
}
/**
- * gem_has_scheduler:
+ * gem_scheduler_enabled:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver has scheduling capability.
@@ -79,7 +79,7 @@ bool gem_scheduler_enabled(int fd)
}
/**
- * gem_has_ctx_priority:
+ * gem_scheduler_has_ctx_priority:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver supports assigning custom
@@ -92,7 +92,7 @@ bool gem_scheduler_has_ctx_priority(int fd)
}
/**
- * gem_has_preemption:
+ * gem_scheduler_has_preemption:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver supports preempting active
@@ -104,6 +104,20 @@ bool gem_scheduler_has_preemption(int fd)
LOCAL_I915_SCHEDULER_CAP_PREEMPTION;
}
+/**
+ * gem_scheduler_has_semaphores:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether the driver supports using HW semaphores
+ * to schedule dependencies in parallel (using the HW to delay execution until
+ * ready to reduce latency).
+ */
+bool gem_scheduler_has_semaphores(int fd)
+{
+ return gem_scheduler_capability(fd) &
+ LOCAL_I915_SCHEDULER_CAP_SEMAPHORES;
+}
+
/**
* gem_scheduler_print_capability:
* @fd: open i915 drm file descriptor
@@ -122,4 +136,6 @@ void gem_scheduler_print_capability(int fd)
igt_info(" - With priority sorting\n");
if (caps & LOCAL_I915_SCHEDULER_CAP_PREEMPTION)
igt_info(" - With preemption enabled\n");
+ if (caps & LOCAL_I915_SCHEDULER_CAP_SEMAPHORES)
+ igt_info(" - With HW semaphores enabled\n");
}
diff --git a/lib/i915/gem_scheduler.h b/lib/i915/gem_scheduler.h
index 9fcb02665..ead3eacb5 100644
--- a/lib/i915/gem_scheduler.h
+++ b/lib/i915/gem_scheduler.h
@@ -27,11 +27,13 @@
#define LOCAL_I915_SCHEDULER_CAP_ENABLED (1 << 0)
#define LOCAL_I915_SCHEDULER_CAP_PRIORITY (1 << 1)
#define LOCAL_I915_SCHEDULER_CAP_PREEMPTION(1 << 2)
+#define LOCAL_I915_SCHEDULER_CAP_SEMAPHORES(1 << 3)
unsigned gem_scheduler_capability(int fd);
bool gem_scheduler_enabled(int fd);
bool gem_scheduler_has_ctx_priority(int fd);
bool gem_scheduler_has_preemption(int fd);
+bool gem_scheduler_has_semaphores(int fd);
void gem_scheduler_print_capability(int fd);
#endif /* GEM_SCHEDULER_H */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/7] drm/i915: Track active engines within a context
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: Track active engines within a
context
URL : https://patchwork.freedesktop.org/series/57738/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5722_full -> Patchwork_12417_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12417_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12417_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12417_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@in-flight-suspend:
- shard-kbl: NOTRUN -> DMESG-WARN
- shard-skl: NOTRUN -> DMESG-WARN
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@i2c:
- {shard-iclb}: PASS -> DMESG-WARN
* igt@kms_chamelium@dp-frame-dump:
- {shard-iclb}: NOTRUN -> SKIP +17
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- {shard-iclb}: PASS -> FAIL +11
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- {shard-iclb}: NOTRUN -> FAIL +5
* igt@kms_plane@pixel-format-pipe-a-planes:
- {shard-iclb}: FAIL [fdo#103166] -> SKIP
* igt@perf_pmu@busy-start-vecs0:
- {shard-iclb}: PASS -> INCOMPLETE
* igt@perf_pmu@semaphore-wait-idle-vecs0:
- {shard-iclb}: PASS -> TIMEOUT
* igt@prime_busy@hang-default:
- {shard-iclb}: PASS -> DMESG-FAIL
* igt@runner@aborted:
- {shard-iclb}: ( 7 FAIL ) -> ( 3 FAIL )
Known issues
Here are the changes found in Patchwork_12417_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@kms_busy@extended-modeset-hang-oldfb-render-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +14
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-pageflip-hang-newfb-render-a:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#107725] / [fdo#108145]
* igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
- shard-skl: PASS -> FAIL [fdo#104671]
* igt@kms_color@pipe-a-legacy-gamma:
- shard-skl: NOTRUN -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-apl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +31
* igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
- shard-skl: PASS -> FAIL [fdo#105682] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-apl: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-glk: PASS -> FAIL [fdo#103167] +7
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +40
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-skl: NOTRUN -> FAIL [fdo#105682] +2
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +102
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103167] +1
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> FAIL [fdo#108145] +1
*
[Intel-gfx] [PATCH i-g-t] i915: Add gem_ctx_engines
To exercise the new I915_CONTEXT_PARAM_ENGINES and interactions with
gem_execbuf().
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Andi Shyti
---
tests/Makefile.sources | 1 +
tests/i915/gem_ctx_engines.c | 368 +++
tests/meson.build| 1 +
3 files changed, 370 insertions(+)
create mode 100644 tests/i915/gem_ctx_engines.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 9e0dab02e..41e756f15 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -21,6 +21,7 @@ TESTS_progs = \
drm_import_export \
drm_mm \
drm_read \
+ i915/gem_ctx_engines \
i915/gem_ctx_shared \
kms_3d \
kms_addfb_basic \
diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
new file mode 100644
index 0..acfdafa9c
--- /dev/null
+++ b/tests/i915/gem_ctx_engines.c
@@ -0,0 +1,368 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "i915/gem_context.h"
+
+#define engine_class(e, n) ((e)->class_instance[(n)].engine_class)
+#define engine_instance(e, n) ((e)->class_instance[(n)].engine_instance)
+
+static bool has_context_engines(int i915)
+{
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = 0,
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ };
+ return __gem_context_set_param(i915, ) == 0;
+}
+
+static void invalid_engines(int i915)
+{
+ struct i915_context_param_engines stack = {}, *engines;
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(),
+ };
+ uint32_t handle;
+ void *ptr;
+
+ param.size = 0;
+ igt_assert_eq(__gem_context_set_param(i915, ), 0);
+
+ param.size = 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EINVAL);
+
+ param.size = sizeof(stack) - 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EINVAL);
+
+ param.size = sizeof(stack) + 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EINVAL);
+
+ param.size = 0;
+ igt_assert_eq(__gem_context_set_param(i915, ), 0);
+
+ /* Create a single page surrounded by inaccessible nothingness */
+ ptr = mmap(NULL, 3 * 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
+ igt_assert(ptr != MAP_FAILED);
+
+ munmap(ptr, 4096);
+ engines = ptr + 4096;
+ munmap(ptr + 2 *4096, 4096);
+
+ param.size = sizeof(*engines) + sizeof(*engines->class_instance);
+ param.value = to_user_pointer(engines);
+
+ engines->class_instance[0].engine_class = -1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -ENOENT);
+
+ mprotect(engines, 4096, PROT_READ);
+ igt_assert_eq(__gem_context_set_param(i915, ), -ENOENT);
+
+ mprotect(engines, 4096, PROT_WRITE);
+ engines->class_instance[0].engine_class = 0;
+ if (__gem_context_set_param(i915, )) /* XXX needs RCS */
+ goto out;
+
+ engines->extensions = to_user_pointer(ptr);
+ igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+ engines->extensions = 0;
+ igt_assert_eq(__gem_context_set_param(i915, ), 0);
+
+ param.value = to_user_pointer(engines - 1);
+ igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+ param.value = to_user_pointer(engines) - 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+ param.value = to_user_pointer(engines) - param.size + 1;
+ igt_assert_eq(__gem_context_set_param(i915, ), -EFAULT);
+
+ param.value =
[Intel-gfx] ✗ Fi.CI.BAT: failure for HDCP2.2 Phase II (rev2)
== Series Details == Series: HDCP2.2 Phase II (rev2) URL : https://patchwork.freedesktop.org/series/57232/ State : failure == Summary == Series 57232 revision 2 Test-with: 20190308163049.9016-2-ramalinga...@intel.com not found ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/13] drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]
Quoting Tvrtko Ursulin (2019-03-08 16:31:51) > Looks okay. But one more thing is needed: > > https://cgit.freedesktop.org/~tursulin/drm-intel/commit/?h=media=38266bfe99469de9e13774a13fa641c377988c67 drm/i915: Allow SSEU configuration to be set on virtual engine /* Only render engine supports RPCS configuration. */ - if (engine->class != RENDER_CLASS) + if (engine->class != RENDER_CLASS && + !(engine->flags & I915_ENGINE_IS_VIRTUAL && + ctx->engines[1]->class == RENDER_CLASS)) return -ENODEV; A virtual engine composed of RCS engines would have engine->class == RENDER_CLASS. So it's just the engine->id BUG_ON that needs lifting? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 7/8] drm/i915: Populate downstream info for HDCP1.4
Implements drm blob property content_protection_downstream_info
property on HDCP capable connectors.
Downstream topology info is gathered across authentication stages
and stored in intel_hdcp. When HDCP authentication is complete,
new blob with latest downstream topology information is updated to
content_protection_downstream_info property.
v2:
%s/cp_downstream/content_protection_downstream [daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_hdcp.c | 35 ++-
include/drm/drm_hdcp.h| 1 +
include/uapi/drm/drm_mode.h | 5 +
4 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7550f4ed5a98..4e722702897a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -482,6 +482,8 @@ struct intel_hdcp {
wait_queue_head_t cp_irq_queue;
atomic_t cp_irq_count;
int cp_irq_count_cached;
+
+ struct content_protection_downstream_info *downstream_info;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index b1fa81666490..777f40202a15 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -580,6 +580,9 @@ int intel_hdcp_auth_downstream(struct intel_hdcp *hdcp,
if (num_downstream == 0)
return -EINVAL;
+ hdcp->downstream_info->device_count = num_downstream;
+ hdcp->downstream_info->depth = DRM_HDCP_DEPTH(bstatus[1]);
+
ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL);
if (!ksv_fifo)
return -ENOMEM;
@@ -593,6 +596,8 @@ int intel_hdcp_auth_downstream(struct intel_hdcp *hdcp,
return -EPERM;
}
+ memcpy(hdcp->downstream_info->ksv_list, ksv_fifo,
+ num_downstream * DRM_HDCP_KSV_LEN);
/*
* When V prime mismatches, DP Spec mandates re-read of
* V prime atleast twice.
@@ -694,15 +699,20 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
return -EPERM;
}
+ hdcp->downstream_info->ver_in_force = DRM_MODE_HDCP14_IN_FORCE;
+ memcpy(hdcp->downstream_info->bksv, bksv.shim, DRM_MODE_HDCP_KSV_LEN);
+
I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
ret = shim->repeater_present(intel_dig_port, _present);
if (ret)
return ret;
- if (repeater_present)
+ if (repeater_present) {
I915_WRITE(HDCP_REP_CTL,
intel_hdcp_get_repeater_ctl(intel_dig_port));
+ hdcp->downstream_info->is_repeater = true;
+ }
ret = shim->toggle_signalling(intel_dig_port, true);
if (ret)
@@ -798,6 +808,14 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
return ret;
}
+ memset(hdcp->downstream_info, 0,
+ sizeof(struct content_protection_downstream_info));
+
+ if (drm_connector_update_content_protection_downstream_property(
+ >base,
+ connector->hdcp.downstream_info))
+ DRM_ERROR("Downstream_info update failed.\n");
+
DRM_DEBUG_KMS("HDCP is disabled\n");
return 0;
}
@@ -831,6 +849,10 @@ static int _intel_hdcp_enable(struct intel_connector
*connector)
ret = intel_hdcp_auth(connector);
if (!ret) {
connector->hdcp.hdcp_encrypted = true;
+ if
(drm_connector_update_content_protection_downstream_property(
+ >base,
+ connector->hdcp.downstream_info))
+ DRM_ERROR("Downstream_info update failed.\n");
return 0;
}
@@ -1882,6 +1904,17 @@ int intel_hdcp_init(struct intel_connector *connector,
if (ret)
return ret;
+ ret = drm_connector_attach_content_protection_downstream_property(
+ >base);
+ if (ret)
+ return ret;
+
+ hdcp->downstream_info =
+ kzalloc(sizeof(struct content_protection_downstream_info),
+ GFP_KERNEL);
+ if (!hdcp->downstream_info)
+ return -ENOMEM;
+
hdcp->shim = shim;
mutex_init(>mutex);
INIT_DELAYED_WORK(>check_work, intel_hdcp_check_work);
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 652aaf5d658e..654a170f03eb 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -23,6 +23,7 @@
#define DRM_HDCP_V_PRIME_PART_LEN 4
#define DRM_HDCP_V_PRIME_NUM_PARTS 5
#define DRM_HDCP_NUM_DOWNSTREAM(x)
[Intel-gfx] [PATCH v2 5/8] drm/i915/sysfs: Node for hdcp srm
Binary Sysfs entry is created to pass the HDCP SRM table into
kerel for the HDCP authentication purpose.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_sysfs.c | 32 +++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 41313005af42..4621e944a24e 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -576,6 +576,36 @@ static void i915_setup_error_capture(struct device *kdev)
{}
static void i915_teardown_error_capture(struct device *kdev) {}
#endif
+static ssize_t
+i915_srm_write(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *attr, char *buf,
+ loff_t offset, size_t count)
+{
+ struct device *kdev = kobj_to_dev(kobj);
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+
+ return intel_hdcp_srm_update(dev_priv, buf, count);
+}
+
+static const struct bin_attribute srm_attrs = {
+ .attr = {.name = "hdcp_srm", .mode = S_IWUSR},
+ .read = NULL,
+ .write = i915_srm_write,
+ .mmap = NULL,
+ .private = (void *)0
+};
+
+static void i915_setup_hdcp_srm(struct device *kdev)
+{
+ if (sysfs_create_bin_file(>kobj, _attrs))
+ DRM_ERROR("error_state sysfs setup failed\n");
+}
+
+static void i915_teardown_hdcp_srm(struct device *kdev)
+{
+ sysfs_remove_bin_file(>kobj, _attrs);
+}
+
void i915_setup_sysfs(struct drm_i915_private *dev_priv)
{
struct device *kdev = dev_priv->drm.primary->kdev;
@@ -623,12 +653,14 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
DRM_ERROR("RPS sysfs setup failed\n");
i915_setup_error_capture(kdev);
+ i915_setup_hdcp_srm(kdev);
}
void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
{
struct device *kdev = dev_priv->drm.primary->kdev;
+ i915_teardown_hdcp_srm(kdev);
i915_teardown_error_capture(kdev);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/8] drm: Add Content protection type property
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on any HDCP protected display wires.
But Type 1 content can be rendered only on HDCP2.2 protected paths.
So when a userspace sets this property to Type 1 and starts the HDCP
enable, kernel will honour it only if HDCP2.2 authentication is through
for type 1. Else HDCP enable will be failed.
v2:
cp_content_type is replaced with content_protection_type [daniel]
check at atomic_set_property is removed [Maarten]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++
drivers/gpu/drm/drm_connector.c | 63 +++
include/drm/drm_connector.h | 15
include/uapi/drm/drm_mode.h | 4 ++
4 files changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 4eb81f10bc54..f383d4be5a92 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -746,6 +746,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
return -EINVAL;
}
state->content_protection = val;
+ } else if (property == connector->content_protection_type_property) {
+ state->content_protection_type = val;
} else if (property == connector->colorspace_property) {
state->colorspace = val;
} else if (property == config->writeback_fb_id_property) {
@@ -822,6 +824,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = state->scaling_mode;
} else if (property == connector->content_protection_property) {
*val = state->content_protection;
+ } else if (property == connector->content_protection_type_property) {
+ *val = state->content_protection_type;
} else if (property == config->writeback_fb_id_property) {
/* Writeback framebuffer is one-shot, write and forget */
*val = 0;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 07d65a16c623..4ce0830e9fb4 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -853,6 +853,13 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
{ DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
};
+static struct drm_prop_enum_list drm_content_protection_type_enum_list[] = {
+ { DRM_MODE_CONTENT_PROTECTION_TYPE0, "Type 0" },
+ { DRM_MODE_CONTENT_PROTECTION_TYPE1, "Type 1" },
+};
+DRM_ENUM_NAME_FN(drm_get_content_protection_type_name,
+drm_content_protection_type_enum_list)
+
/**
* DOC: standard connector properties
*
@@ -958,6 +965,23 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
* the value transitions from ENABLED to DESIRED. This signifies the link
* is no longer protected and userspace should take appropriate action
* (whatever that might be).
+ * Content_protection_type:
+ * This property is used by the userspace to configure the kernel with
+ * upcoming stream's content type. Content Type of a stream is decided by
+ * the owner of the stream, as Type 0 or Type 1.
+ *
+ * The value of the property can be one the below:
+ * - DRM_MODE_CONTENT_PROTECTION_TYPE0 = 0
+ * Type 0 streams can be transmitted on a link which is encrypted
+ * with HDCP 1.4 or HDCP 2.2.
+ * - DRM_MODE_CONTENT_PROTECTION_TYPE1 = 1
+ * Type 1 streams can be transmitted on a link which is encrypted
+ * only with HDCP2.2.
+ *
+ * Please note this content type is introduced at HDCP2.2 and used in its
+ * authentication process. If content type is changed when
+ * content_protection is not UNDESIRED, then kernel will disable the HDCP
+ * and re-enable with new type in the same atomic commit
*
* max bpc:
* This range property is used by userspace to limit the bit depth. When
@@ -1547,6 +1571,45 @@ int drm_connector_attach_content_protection_property(
}
EXPORT_SYMBOL(drm_connector_attach_content_protection_property);
+/**
+ * drm_connector_attach_content_protection_type_property - attach content
+ * protection type property
+ *
+ * @connector: connector to attach content protection type property on.
+ *
+ * This is used to add support for sending the protected content's stream type
+ * from userspace to kernel on selected connectors. Protected content provider
+ * will decide their type of their content and declare the same to kernel.
+ *
+ * This information will be used during the HDCP2.2 authentication.
+ *
+ * Content type will be set to _connector_state.content_protection_type.
+ *
+ * Returns:
+ *
[Intel-gfx] [PATCH v2 4/8] drm/i915: HDCP SRM parsing and revocation check
Implements the SRM table parsing for HDCP 1.4 and 2.2.
And also revocation check is added at authentication of HDCP1.4
and 2.2
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_hdcp.c | 308 --
include/drm/drm_hdcp.h| 32
5 files changed, 334 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0d743907e7bc..6c396ec0f552 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -873,6 +873,7 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
mutex_init(_priv->wm.wm_mutex);
mutex_init(_priv->pps_mutex);
mutex_init(_priv->hdcp_comp_mutex);
+ mutex_init(_priv->srm_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4ffe19ec698..c6c7cb1ae1b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2054,6 +2054,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ unsigned int revocated_ksv_cnt;
+ u8 *revocated_ksv_list;
+
+ /* Mutex to protect the data about revocated ksvs */
+ struct mutex srm_mutex;
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 186fa035f491..7550f4ed5a98 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2181,6 +2181,8 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv);
void intel_hdcp_component_fini(struct drm_i915_private *dev_priv);
void intel_hdcp_cleanup(struct intel_connector *connector);
void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
+ssize_t intel_hdcp_srm_update(struct drm_i915_private *dev_priv, char *buf,
+ size_t count);
/* intel_psr.c */
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index ff1bbbee2e52..b1fa81666490 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -273,6 +273,62 @@ u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port
*intel_dig_port)
return -EINVAL;
}
+static inline void intel_hdcp_print_ksv(u8 *ksv)
+{
+ DRM_DEBUG_KMS("\t%#04x, %#04x, %#04x, %#04x, %#04x\n", *ksv,
+ *(ksv + 1), *(ksv + 2), *(ksv + 3), *(ksv + 4));
+}
+
+static inline
+struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp)
+{
+ return container_of(hdcp, struct intel_connector, hdcp);
+}
+
+/* Check if any of the KSV is revocated by DCP LLC through SRM table */
+static inline
+bool intel_hdcp_ksvs_revocated(struct intel_hdcp *hdcp, u8 *ksvs, u32
ksv_count)
+{
+ struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+ struct drm_i915_private *dev_priv =
+ intel_dig_port->base.base.dev->dev_private;
+ u32 rev_ksv_cnt, cnt, i, j;
+ u8 *rev_ksv_list;
+
+ mutex_lock(_priv->srm_mutex);
+ rev_ksv_cnt = dev_priv->revocated_ksv_cnt;
+ rev_ksv_list = dev_priv->revocated_ksv_list;
+
+ /* If the Revocated ksv list is empty */
+ if (!rev_ksv_cnt || !rev_ksv_list) {
+ mutex_unlock(_priv->srm_mutex);
+ return false;
+ }
+
+ for (cnt = 0; cnt < ksv_count; cnt++) {
+ rev_ksv_list = dev_priv->revocated_ksv_list;
+ for (i = 0; i < rev_ksv_cnt; i++) {
+ for (j = 0; j < DRM_HDCP_KSV_LEN; j++)
+ if (*(ksvs + j) != *(rev_ksv_list + j)) {
+ break;
+ } else if (j == (DRM_HDCP_KSV_LEN - 1)) {
+ DRM_DEBUG_KMS("Revocated KSV is ");
+ intel_hdcp_print_ksv(ksvs);
+ mutex_unlock(_priv->srm_mutex);
+ return true;
+ }
+ /* Move the offset to next KSV in the revocated list */
+ rev_ksv_list += DRM_HDCP_KSV_LEN;
+ }
+
+ /* Iterate to next ksv_offset */
+ ksvs += DRM_HDCP_KSV_LEN;
+ }
+ mutex_unlock(_priv->srm_mutex);
+ return false;
+}
+
static
int
[Intel-gfx] [PATCH v2 6/8] drm: Add CP downstream_info property
This patch adds a optional CP downstream info blob property to the
connectors. This enables the Userspace to read the information of HDCP
authenticated downstream topology.
Driver will updated this blob with all downstream information at the
end of the authentication.
In case userspace configures this platform as repeater, then this
information is needed for the authentication with upstream HDCP
transmitter.
v2:
%s/cp_downstream/content_protection_downstream [daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++
drivers/gpu/drm/drm_connector.c | 89 +++
include/drm/drm_connector.h | 12 +
include/uapi/drm/drm_mode.h | 27 ++
4 files changed, 132 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index f383d4be5a92..51fa217f99f6 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -826,6 +826,10 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = state->content_protection;
} else if (property == connector->content_protection_type_property) {
*val = state->content_protection_type;
+ } else if (property ==
+ connector->content_protection_downstream_property) {
+ *val = connector->content_protection_downstream_blob_ptr ?
+ connector->content_protection_downstream_blob_ptr->base.id : 0;
} else if (property == config->writeback_fb_id_property) {
/* Writeback framebuffer is one-shot, write and forget */
*val = 0;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 4ce0830e9fb4..3a11624ca73c 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -245,6 +245,7 @@ int drm_connector_init(struct drm_device *dev,
INIT_LIST_HEAD(>modes);
mutex_init(>mutex);
connector->edid_blob_ptr = NULL;
+ connector->content_protection_downstream_blob_ptr = NULL;
connector->status = connector_status_unknown;
connector->display_info.panel_orientation =
DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
@@ -982,6 +983,25 @@ DRM_ENUM_NAME_FN(drm_get_content_protection_type_name,
* authentication process. If content type is changed when
* content_protection is not UNDESIRED, then kernel will disable the HDCP
* and re-enable with new type in the same atomic commit
+ * Content_protection_downstream_info:
+ * This blob property is used to pass the HDCP downstream topology details
+ * of a HDCP encrypted connector, from kernel to userspace.
+ * This provides all required information to userspace, so that userspace
+ * can implement the HDCP repeater using the kernel as downstream ports of
+ * the repeater. as illustrated below:
+ *
+ * HDCP Repeaters
+ * +--+
+ * | |
+ * | | |
+ * | Userspace HDCP Receiver +->KMD HDCP transmitters |
+ * | (Upstream Port) <--+ (Downstream Ports)|
+ * | | |
+ * | |
+ * +--+
+ *
+ * Kernel will populate this blob only when the HDCP authentication is
+ * successful.
*
* max bpc:
* This range property is used by userspace to limit the bit depth. When
@@ -1610,6 +1630,75 @@
drm_connector_attach_content_protection_type_property(struct drm_connector *
}
EXPORT_SYMBOL(drm_connector_attach_content_protection_type_property);
+/**
+ * drm_connector_attach_content_protection_downstream_property - attach content
+ * protection downstream property
+ *
+ * @connector: connector to attach content protection downstream property on.
+ *
+ * This is used to add support for content protection downstream info on
+ * select connectors. when Intel platform is configured as repeater,
+ * this downstream info is used by userspace, to complete the repeater
+ * authentication of HDCP specification with upstream HDCP transmitter.
+ *
+ * The content protection downstream will be set to
+ * _connector_state.content_protection_downstream
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_attach_content_protection_downstream_property(
+ struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_property *prop;
+
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB |
+ DRM_MODE_PROP_IMMUTABLE,
+ "CP_downstream_info", 0);
+ if (!prop)
+ return
[Intel-gfx] [PATCH v2 3/8] drm/i915: Attach content type property
Attaches the content type property for HDCP2.2 capable connectors.
Implements the update of content type from property and apply the
restriction on HDCP version selection.
v2:
s/cp_content_type/content_protection_type [daniel]
disable at hdcp_atomic_check to avoid check at atomic_set_property
[Maarten]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_ddi.c | 21 +++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_hdcp.c | 30 +-
3 files changed, 41 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7e3b4e8fdf3a..8702938ec376 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3499,7 +3499,8 @@ static void intel_enable_ddi(struct intel_encoder
*encoder,
/* Enable hdcp if it's desired */
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
+ intel_hdcp_enable(to_intel_connector(conn_state->connector),
+ (u8)conn_state->content_protection_type);
}
static void intel_disable_ddi_dp(struct intel_encoder *encoder,
@@ -3562,21 +3563,29 @@ static void intel_ddi_update_pipe_dp(struct
intel_encoder *encoder,
intel_panel_update_backlight(encoder, crtc_state, conn_state);
}
-static void intel_ddi_update_pipe(struct intel_encoder *encoder,
+static void intel_ddi_update_hdcp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
- intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
-
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
+ intel_hdcp_enable(to_intel_connector(conn_state->connector),
+ (u8)conn_state->content_protection_type);
else if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
intel_hdcp_disable(to_intel_connector(conn_state->connector));
}
+static void intel_ddi_update_pipe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
+
+ intel_ddi_update_hdcp(encoder, crtc_state, conn_state);
+}
+
static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
const struct intel_crtc_state
*pipe_config,
enum port port)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f143aaf57e55..186fa035f491 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2172,7 +2172,7 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
struct drm_connector_state *new_state);
int intel_hdcp_init(struct intel_connector *connector,
const struct intel_hdcp_shim *hdcp_shim);
-int intel_hdcp_enable(struct intel_connector *connector);
+int intel_hdcp_enable(struct intel_connector *connector, u8 content_type);
int intel_hdcp_disable(struct intel_connector *connector);
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
bool intel_hdcp_capable(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index ff9497e5c591..ff1bbbee2e52 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1782,6 +1782,13 @@ static void intel_hdcp2_init(struct intel_connector
*connector)
return;
}
+ ret = drm_connector_attach_content_protection_type_property(
+ >base);
+ if (ret) {
+ kfree(hdcp->port_data.streams);
+ return;
+ }
+
hdcp->hdcp2_supported = true;
}
@@ -1811,7 +1818,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return 0;
}
-int intel_hdcp_enable(struct intel_connector *connector)
+int intel_hdcp_enable(struct intel_connector *connector, u8 content_type)
{
struct intel_hdcp *hdcp = >hdcp;
unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS;
@@ -1822,6 +1829,7 @@ int intel_hdcp_enable(struct intel_connector *connector)
mutex_lock(>mutex);
WARN_ON(hdcp->value ==
[Intel-gfx] [PATCH v2 8/8] drm/i915: Populate downstream info for HDCP2.2
Populates the downstream info for HDCP2.2 encryption also. On success
of encryption Blob is updated.
Additional two variable are added to downstream info blob. Such as
ver_in_force and content type.
v2:
s/cp_downstream/content_protection_downstream [daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 30 +-
include/uapi/drm/drm_mode.h | 3 +++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 777f40202a15..3350b37375db 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1283,6 +1283,12 @@ static int hdcp2_authentication_key_exchange(struct
intel_connector *connector)
return -EPERM;
}
+ hdcp->downstream_info->ver_in_force = DRM_MODE_HDCP22_IN_FORCE;
+ hdcp->downstream_info->content_type = hdcp->content_type;
+ memcpy(hdcp->downstream_info->bksv, msgs.send_cert.cert_rx.receiver_id,
+ HDCP_2_2_RECEIVER_ID_LEN);
+ hdcp->downstream_info->is_repeater = hdcp->is_repeater;
+
/*
* Here msgs.no_stored_km will hold msgs corresponding to the km
* stored also.
@@ -1474,6 +1480,11 @@ int hdcp2_authenticate_repeater_topology(struct
intel_connector *connector)
return -EPERM;
}
+ hdcp->downstream_info->device_count = device_cnt;
+ hdcp->downstream_info->depth = HDCP_2_2_DEPTH(rx_info[0]);
+ memcpy(hdcp->downstream_info->ksv_list, msgs.recvid_list.receiver_ids,
+ device_cnt * HDCP_2_2_RECEIVER_ID_LEN);
+
ret = hdcp2_verify_rep_topology_prepare_ack(connector,
_list,
_ack);
@@ -1660,6 +1671,13 @@ static int _intel_hdcp2_enable(struct intel_connector
*connector)
if (ret) {
DRM_DEBUG_KMS("HDCP2 Type%d Enabling Failed. (%d)\n",
hdcp->content_type, ret);
+
+ memset(hdcp->downstream_info, 0,
+ sizeof(struct content_protection_downstream_info));
+ drm_connector_update_content_protection_downstream_property(
+ >base,
+ hdcp->downstream_info);
+
return ret;
}
@@ -1667,12 +1685,17 @@ static int _intel_hdcp2_enable(struct intel_connector
*connector)
connector->base.name, connector->base.base.id,
hdcp->content_type);
+ drm_connector_update_content_protection_downstream_property(
+ >base,
+ hdcp->downstream_info);
hdcp->hdcp2_encrypted = true;
+
return 0;
}
static int _intel_hdcp2_disable(struct intel_connector *connector)
{
+ struct intel_hdcp *hdcp = >hdcp;
int ret;
DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being Disabled\n",
@@ -1683,8 +1706,13 @@ static int _intel_hdcp2_disable(struct intel_connector
*connector)
if (hdcp2_deauthenticate_port(connector) < 0)
DRM_DEBUG_KMS("Port deauth failed.\n");
- connector->hdcp.hdcp2_encrypted = false;
+ hdcp->hdcp2_encrypted = false;
+ memset(hdcp->downstream_info, 0,
+ sizeof(struct content_protection_downstream_info));
+ drm_connector_update_content_protection_downstream_property(
+ >base,
+ hdcp->downstream_info);
return ret;
}
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 3973d35c3b57..dc81713d3a07 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -223,6 +223,9 @@ struct content_protection_downstream_info {
/* Version of HDCP authenticated (1.4/2.2) */
__u32 ver_in_force;
+ /* Applicable only for HDCP2.2 */
+ __u8 content_type;
+
/* KSV of immediate HDCP Sink. In Little-Endian Format. */
char bksv[DRM_MODE_HDCP_KSV_LEN];
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/8] drm/i915: debugfs: HDCP2.2 capability read
Adding the HDCP2.2 capability of HDCP src and sink info into debugfs
entry "i915_hdcp_sink_capability"
This helps the userspace tests to skip the HDCP2.2 test on non HDCP2.2
sinks.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +++--
drivers/gpu/drm/i915/intel_drv.h| 1 +
drivers/gpu/drm/i915/intel_hdcp.c | 2 +-
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6a90558de213..8ef097c492d6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4755,6 +4755,7 @@ static int i915_hdcp_sink_capability_show(struct seq_file
*m, void *data)
{
struct drm_connector *connector = m->private;
struct intel_connector *intel_connector = to_intel_connector(connector);
+ bool hdcp_cap, hdcp2_cap;
if (connector->status != connector_status_connected)
return -ENODEV;
@@ -4765,8 +4766,16 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
seq_printf(m, "%s:%d HDCP version: ", connector->name,
connector->base.id);
- seq_printf(m, "%s ", !intel_hdcp_capable(intel_connector) ?
- "None" : "HDCP1.4");
+ hdcp_cap = intel_hdcp_capable(intel_connector);
+ hdcp2_cap = intel_hdcp2_capable(intel_connector);
+
+ if (hdcp_cap)
+ seq_puts(m, "HDCP1.4 ");
+ if (hdcp2_cap)
+ seq_puts(m, "HDCP2.2 ");
+
+ if (!hdcp_cap && !hdcp2_cap)
+ seq_puts(m, "None");
seq_puts(m, "\n");
return 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 58483f8245aa..f143aaf57e55 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2176,6 +2176,7 @@ int intel_hdcp_enable(struct intel_connector *connector);
int intel_hdcp_disable(struct intel_connector *connector);
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
bool intel_hdcp_capable(struct intel_connector *connector);
+bool intel_hdcp2_capable(struct intel_connector *connector);
void intel_hdcp_component_init(struct drm_i915_private *dev_priv);
void intel_hdcp_component_fini(struct drm_i915_private *dev_priv);
void intel_hdcp_cleanup(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 9ce09f67776d..ff9497e5c591 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -76,7 +76,7 @@ bool intel_hdcp_capable(struct intel_connector *connector)
}
/* Is HDCP2.2 capable on Platform and Sink */
-static bool intel_hdcp2_capable(struct intel_connector *connector)
+bool intel_hdcp2_capable(struct intel_connector *connector)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/8] HDCP2.2 Phase II
HDCP2.2 phase-II mojorly adds below features: Addition of three connector properties CP_Content_Type CP_Downstream_Info Addition of binary sysfs "hdcp_srm" parsing for HDCP1.4 and 2.2 SRM table Once HDCP1.4/2.2 authentication is completed gathering the all downstream topology for userspace Extending debugfs entry to provide the HDCP2.2 capability too. CP_Content_Type: This property is used to indicate the content type classification of a stream. Which indicate the HDCP version required for the rendering of that streams. This conten type is one of the parameter in the HDCP2.2 authentication flow, as even downstream repeaters will mandate the HDCP version requirement. Two values possible for content type of a stream: Type 0: Stream can be rendered only on HDCP encrypted link no restriction on HDCP versions. Type 1: Stream can be rendered only on HDCP2.2 encrypted link. There is a parallel effort in #wayland community to add the support for HDCP2.2 along with content type support. Patches are under review in #wayland community. CP_downstream_info: This blob property is used by the kernel to pass the downstream topology of the HDCP encrypted port to the userspace. This is used by the userspace to implement the HDCP repeater, which KMD implementing the HDCP transmitters(downstream ports) and userspace implementing the upstream port(HDCP receiver). Discussion is on going to add the downstream_info support in the weston HDCP stack. hdcp_srm: write only binary sysfs used by the userspace to pass the SRM table of HDCP1.4 and 2.2. These are nothing but revocated list of receiver IDs of the HDCP sinks. KMD will use this list to identify the revocated devices in the HDCP authentication and deny the hdcp encryption to it. Test-with: 20190308163049.9016-2-ramalinga...@intel.com v2: srm is passed through binary sysfs [Daniel] CP abbreviation is expanded except for downstream_info [Daniel] restrictions at atomic_set_property is removed [Maarten] upon content type change durin encryption, HDCP is restarted within kernel [Maarten] Please note content_type support is submitted for review separately at https://patchwork.freedesktop.org/series/57757/ Still retained here for dependancy and testing all of them together. Ramalingam C (8): drm/i915: debugfs: HDCP2.2 capability read drm: Add Content protection type property drm/i915: Attach content type property drm/i915: HDCP SRM parsing and revocation check drm/i915/sysfs: Node for hdcp srm drm: Add CP downstream_info property drm/i915: Populate downstream info for HDCP1.4 drm/i915: Populate downstream info for HDCP2.2 drivers/gpu/drm/drm_atomic_uapi.c | 8 + drivers/gpu/drm/drm_connector.c | 152 +++ drivers/gpu/drm/i915/i915_debugfs.c | 13 +- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_sysfs.c | 32 +++ drivers/gpu/drm/i915/intel_ddi.c| 21 +- drivers/gpu/drm/i915/intel_drv.h| 7 +- drivers/gpu/drm/i915/intel_hdcp.c | 405 ++-- include/drm/drm_connector.h | 27 ++ include/drm/drm_hdcp.h | 33 +++ include/uapi/drm/drm_mode.h | 39 +++ 12 files changed, 712 insertions(+), 32 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/13] drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]
Quoting Tvrtko Ursulin (2019-03-08 16:31:51) > > On 08/03/2019 14:12, Chris Wilson wrote: > > Allow the user to specify a local engine index (as opposed to > > class:index) that they can use to refer to a preset engine inside the > > ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES. > > This will be useful for setting SSEU parameters on virtual engines that > > are local to the context and do not have a valid global class:instance > > lookup. > > > > Signed-off-by: Chris Wilson > > Cc: Tvrtko Ursulin > > --- > > drivers/gpu/drm/i915/i915_gem_context.c | 24 > > include/uapi/drm/i915_drm.h | 3 ++- > > 2 files changed, 22 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c > > b/drivers/gpu/drm/i915/i915_gem_context.c > > index 86d9bea6f275..a581c011 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_context.c > > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > > @@ -1313,6 +1313,7 @@ static int set_sseu(struct i915_gem_context *ctx, > > struct drm_i915_gem_context_param_sseu user_sseu; > > struct intel_engine_cs *engine; > > struct intel_sseu sseu; > > + unsigned long lookup; > > Poor 32-bit builds. ;) And in lookup_user_engine as well. It's an internal flags variable; not a direct part of the uABI. So it's only use is to control lookup_user_engine() so limiting it to 32b (natural register width) doesn't seem a like a concern for the forseeable future? How many different ABI interfacing methods of looking up an engine do you have planned? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for HDCP2.2 Content Type support
== Series Details == Series: HDCP2.2 Content Type support URL : https://patchwork.freedesktop.org/series/57757/ State : failure == Summary == Series 57757 revision 1 Test-with: 20190308163049.9016-2-ramalinga...@intel.com not found ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: Fix CRC mismatch error for DP link layer compliance (rev3)
== Series Details == Series: drm/i915/icl: Fix CRC mismatch error for DP link layer compliance (rev3) URL : https://patchwork.freedesktop.org/series/57619/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5724 -> Patchwork_12420 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12420 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12420, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/57619/revisions/3/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12420: ### IGT changes ### Possible regressions * igt@gem_cpu_reloc@basic: - fi-icl-u3: NOTRUN -> INCOMPLETE Known issues Here are the changes found in Patchwork_12420 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +57 - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_selftest@live_contexts: - fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@hdmi-edid-read: - fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +46 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814] - fi-icl-u2: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 Participating hosts (41 -> 38) -- Additional (5): fi-hsw-peppy fi-icl-u2 fi-snb-2520m fi-icl-u3 fi-byt-clapper Missing(8): fi-kbl-soraka fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-bwr-2160 fi-apl-guc fi-kbl-x1275 fi-gdg-551 Build changes - * Linux: CI_DRM_5724 -> Patchwork_12420 CI_DRM_5724: 3078a97d3931496cac45c0f4c94dc0f021fcb340 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4877: d15ad69be07a987d5c2ba408201b287adae8ca59 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12420: e6f80925d5d2d07b2a757502e666e3a6ecc04b87 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e6f80925d5d2 drm/i915/icl: Fix CRC mismatch error for DP link layer compliance == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12420/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/13] drm/i915: Allow a context to define its set of engines
Quoting Tvrtko Ursulin (2019-03-08 16:27:22)
>
> On 08/03/2019 14:12, Chris Wilson wrote:
> > Over the last few years, we have debated how to extend the user API to
> > support an increase in the number of engines, that may be sparse and
> > even be heterogeneous within a class (not all video decoders created
> > equal). We settled on using (class, instance) tuples to identify a
> > specific engine, with an API for the user to construct a map of engines
> > to capabilities. Into this picture, we then add a challenge of virtual
> > engines; one user engine that maps behind the scenes to any number of
> > physical engines. To keep it general, we want the user to have full
> > control over that mapping. To that end, we allow the user to constrain a
> > context to define the set of engines that it can access, order fully
> > controlled by the user via (class, instance). With such precise control
> > in context setup, we can continue to use the existing execbuf uABI of
> > specifying a single index; only now it doesn't automagically map onto
> > the engines, it uses the user defined engine map from the context.
> >
> > The I915_EXEC_DEFAULT slot is left empty, and invalid for use by
> > execbuf. It's use will be revealed in the next patch.
> >
> > v2: Fixup freeing of local on success of get_engines()
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/i915_gem_context.c | 204 +-
> > drivers/gpu/drm/i915/i915_gem_context_types.h | 4 +
> > drivers/gpu/drm/i915/i915_gem_execbuffer.c| 22 +-
> > include/uapi/drm/i915_drm.h | 42 +++-
> > 4 files changed, 259 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index 2cfc68b66944..86d9bea6f275 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -101,6 +101,21 @@ static struct i915_global_gem_context {
> > struct kmem_cache *slab_luts;
> > } global;
> >
> > +static struct intel_engine_cs *
> > +lookup_user_engine(struct i915_gem_context *ctx,
> > +unsigned long flags, u16 class, u16 instance)
> > +#define LOOKUP_USER_INDEX BIT(0)
> > +{
> > + if (flags & LOOKUP_USER_INDEX) {
> > + if (instance >= ctx->nengine)
> > + return NULL;
> > +
> > + return ctx->engines[instance];
> > + }
> > +
> > + return intel_engine_lookup_user(ctx->i915, class, instance);
> > +}
> > +
> > struct i915_lut_handle *i915_lut_handle_alloc(void)
> > {
> > return kmem_cache_alloc(global.slab_luts, GFP_KERNEL);
> > @@ -234,6 +249,8 @@ static void i915_gem_context_free(struct
> > i915_gem_context *ctx)
> > release_hw_id(ctx);
> > i915_ppgtt_put(ctx->ppgtt);
> >
> > + kfree(ctx->engines);
> > +
> > rbtree_postorder_for_each_entry_safe(it, n, >hw_contexts, node)
> > it->ops->destroy(it);
> >
> > @@ -1311,9 +1328,9 @@ static int set_sseu(struct i915_gem_context *ctx,
> > if (user_sseu.flags || user_sseu.rsvd)
> > return -EINVAL;
> >
> > - engine = intel_engine_lookup_user(i915,
> > - user_sseu.engine_class,
> > - user_sseu.engine_instance);
> > + engine = lookup_user_engine(ctx, 0,
> > + user_sseu.engine_class,
> > + user_sseu.engine_instance);
> > if (!engine)
> > return -EINVAL;
> >
> > @@ -1331,9 +1348,154 @@ static int set_sseu(struct i915_gem_context *ctx,
> >
> > args->size = sizeof(user_sseu);
> >
> > + return 0;
> > +};
> > +
> > +struct set_engines {
> > + struct i915_gem_context *ctx;
> > + struct intel_engine_cs **engines;
> > + unsigned int nengine;
> > +};
> > +
> > +static const i915_user_extension_fn set_engines__extensions[] = {
> > +};
> > +
> > +static int
> > +set_engines(struct i915_gem_context *ctx,
> > + const struct drm_i915_gem_context_param *args)
> > +{
> > + struct i915_context_param_engines __user *user;
> > + struct set_engines set = { .ctx = ctx };
> > + u64 size, extensions;
> > + unsigned int n;
> > + int err;
> > +
> > + user = u64_to_user_ptr(args->value);
> > + size = args->size;
> > + if (!size)
> > + goto out;
>
> This prevents a hypothetical extension with empty map data.
No... This is required for resetting and I think that's covered in what
little docs there are. It's the set.nengine==0 test later
that you mean to object to. But we can't do that as that's how we
differentiate between modes at the moment.
We could use ctx->nengine = 0 and ctx->engines = ZERO_PTR.
> > + BUILD_BUG_ON(!IS_ALIGNED(sizeof(*user),
> > sizeof(*user->class_instance)));
> > + if (size < sizeof(*user) || size %
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/13] drm/i915: Suppress the "Failed to idle" warning for gem_eio (rev2)
== Series Details == Series: series starting with [01/13] drm/i915: Suppress the "Failed to idle" warning for gem_eio (rev2) URL : https://patchwork.freedesktop.org/series/57742/ State : failure == Summary == Applying: drm/i915: Suppress the "Failed to idle" warning for gem_eio Applying: drm/i915: Introduce the i915_user_extension_method Applying: drm/i915: Introduce a context barrier callback Applying: drm/i915: Create/destroy VM (ppGTT) for use with contexts Applying: drm/i915: Extend CONTEXT_CREATE to set parameters upon construction Using index info to reconstruct a base tree... M include/uapi/drm/i915_drm.h Falling back to patching base and 3-way merge... Auto-merging include/uapi/drm/i915_drm.h CONFLICT (content): Merge conflict in include/uapi/drm/i915_drm.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0005 drm/i915: Extend CONTEXT_CREATE to set parameters upon construction When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/8] drm/i915: debugfs: HDCP2.2 capability read
Adding the HDCP2.2 capability of HDCP src and sink info into debugfs
entry "i915_hdcp_sink_capability"
This helps the userspace tests to skip the HDCP2.2 test on non HDCP2.2
sinks.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +++--
drivers/gpu/drm/i915/intel_drv.h| 1 +
drivers/gpu/drm/i915/intel_hdcp.c | 2 +-
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6a90558de213..8ef097c492d6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4755,6 +4755,7 @@ static int i915_hdcp_sink_capability_show(struct seq_file
*m, void *data)
{
struct drm_connector *connector = m->private;
struct intel_connector *intel_connector = to_intel_connector(connector);
+ bool hdcp_cap, hdcp2_cap;
if (connector->status != connector_status_connected)
return -ENODEV;
@@ -4765,8 +4766,16 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
seq_printf(m, "%s:%d HDCP version: ", connector->name,
connector->base.id);
- seq_printf(m, "%s ", !intel_hdcp_capable(intel_connector) ?
- "None" : "HDCP1.4");
+ hdcp_cap = intel_hdcp_capable(intel_connector);
+ hdcp2_cap = intel_hdcp2_capable(intel_connector);
+
+ if (hdcp_cap)
+ seq_puts(m, "HDCP1.4 ");
+ if (hdcp2_cap)
+ seq_puts(m, "HDCP2.2 ");
+
+ if (!hdcp_cap && !hdcp2_cap)
+ seq_puts(m, "None");
seq_puts(m, "\n");
return 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 58483f8245aa..f143aaf57e55 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2176,6 +2176,7 @@ int intel_hdcp_enable(struct intel_connector *connector);
int intel_hdcp_disable(struct intel_connector *connector);
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
bool intel_hdcp_capable(struct intel_connector *connector);
+bool intel_hdcp2_capable(struct intel_connector *connector);
void intel_hdcp_component_init(struct drm_i915_private *dev_priv);
void intel_hdcp_component_fini(struct drm_i915_private *dev_priv);
void intel_hdcp_cleanup(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 9ce09f67776d..ff9497e5c591 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -76,7 +76,7 @@ bool intel_hdcp_capable(struct intel_connector *connector)
}
/* Is HDCP2.2 capable on Platform and Sink */
-static bool intel_hdcp2_capable(struct intel_connector *connector)
+bool intel_hdcp2_capable(struct intel_connector *connector)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915: Attach content type property
Attaches the content type property for HDCP2.2 capable connectors.
Implements the update of content type from property and apply the
restriction on HDCP version selection.
v2:
s/cp_content_type/content_protection_type [daniel]
disable at hdcp_atomic_check to avoid check at atomic_set_property
[Maarten]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_ddi.c | 21 +++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_hdcp.c | 30 +-
3 files changed, 41 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7e3b4e8fdf3a..8702938ec376 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3499,7 +3499,8 @@ static void intel_enable_ddi(struct intel_encoder
*encoder,
/* Enable hdcp if it's desired */
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
+ intel_hdcp_enable(to_intel_connector(conn_state->connector),
+ (u8)conn_state->content_protection_type);
}
static void intel_disable_ddi_dp(struct intel_encoder *encoder,
@@ -3562,21 +3563,29 @@ static void intel_ddi_update_pipe_dp(struct
intel_encoder *encoder,
intel_panel_update_backlight(encoder, crtc_state, conn_state);
}
-static void intel_ddi_update_pipe(struct intel_encoder *encoder,
+static void intel_ddi_update_hdcp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
- intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
-
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
+ intel_hdcp_enable(to_intel_connector(conn_state->connector),
+ (u8)conn_state->content_protection_type);
else if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
intel_hdcp_disable(to_intel_connector(conn_state->connector));
}
+static void intel_ddi_update_pipe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
+
+ intel_ddi_update_hdcp(encoder, crtc_state, conn_state);
+}
+
static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
const struct intel_crtc_state
*pipe_config,
enum port port)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 58483f8245aa..07c049310f82 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2172,7 +2172,7 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
struct drm_connector_state *new_state);
int intel_hdcp_init(struct intel_connector *connector,
const struct intel_hdcp_shim *hdcp_shim);
-int intel_hdcp_enable(struct intel_connector *connector);
+int intel_hdcp_enable(struct intel_connector *connector, u8 content_type);
int intel_hdcp_disable(struct intel_connector *connector);
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
bool intel_hdcp_capable(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 9ce09f67776d..e51529983bd2 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1782,6 +1782,13 @@ static void intel_hdcp2_init(struct intel_connector
*connector)
return;
}
+ ret = drm_connector_attach_content_protection_type_property(
+ >base);
+ if (ret) {
+ kfree(hdcp->port_data.streams);
+ return;
+ }
+
hdcp->hdcp2_supported = true;
}
@@ -1811,7 +1818,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return 0;
}
-int intel_hdcp_enable(struct intel_connector *connector)
+int intel_hdcp_enable(struct intel_connector *connector, u8 content_type)
{
struct intel_hdcp *hdcp = >hdcp;
unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS;
@@ -1822,6 +1829,7 @@ int intel_hdcp_enable(struct intel_connector *connector)
mutex_lock(>mutex);
WARN_ON(hdcp->value ==
[Intel-gfx] [PATCH v2 1/2] drm: Add Content protection type property
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on any HDCP protected display wires.
But Type 1 content can be rendered only on HDCP2.2 protected paths.
So when a userspace sets this property to Type 1 and starts the HDCP
enable, kernel will honour it only if HDCP2.2 authentication is through
for type 1. Else HDCP enable will be failed.
v2:
cp_content_type is replaced with content_protection_type [daniel]
check at atomic_set_property is removed [Maarten]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++
drivers/gpu/drm/drm_connector.c | 63 +++
include/drm/drm_connector.h | 15
include/uapi/drm/drm_mode.h | 4 ++
4 files changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 4eb81f10bc54..f383d4be5a92 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -746,6 +746,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
return -EINVAL;
}
state->content_protection = val;
+ } else if (property == connector->content_protection_type_property) {
+ state->content_protection_type = val;
} else if (property == connector->colorspace_property) {
state->colorspace = val;
} else if (property == config->writeback_fb_id_property) {
@@ -822,6 +824,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = state->scaling_mode;
} else if (property == connector->content_protection_property) {
*val = state->content_protection;
+ } else if (property == connector->content_protection_type_property) {
+ *val = state->content_protection_type;
} else if (property == config->writeback_fb_id_property) {
/* Writeback framebuffer is one-shot, write and forget */
*val = 0;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 07d65a16c623..4ce0830e9fb4 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -853,6 +853,13 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
{ DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
};
+static struct drm_prop_enum_list drm_content_protection_type_enum_list[] = {
+ { DRM_MODE_CONTENT_PROTECTION_TYPE0, "Type 0" },
+ { DRM_MODE_CONTENT_PROTECTION_TYPE1, "Type 1" },
+};
+DRM_ENUM_NAME_FN(drm_get_content_protection_type_name,
+drm_content_protection_type_enum_list)
+
/**
* DOC: standard connector properties
*
@@ -958,6 +965,23 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
* the value transitions from ENABLED to DESIRED. This signifies the link
* is no longer protected and userspace should take appropriate action
* (whatever that might be).
+ * Content_protection_type:
+ * This property is used by the userspace to configure the kernel with
+ * upcoming stream's content type. Content Type of a stream is decided by
+ * the owner of the stream, as Type 0 or Type 1.
+ *
+ * The value of the property can be one the below:
+ * - DRM_MODE_CONTENT_PROTECTION_TYPE0 = 0
+ * Type 0 streams can be transmitted on a link which is encrypted
+ * with HDCP 1.4 or HDCP 2.2.
+ * - DRM_MODE_CONTENT_PROTECTION_TYPE1 = 1
+ * Type 1 streams can be transmitted on a link which is encrypted
+ * only with HDCP2.2.
+ *
+ * Please note this content type is introduced at HDCP2.2 and used in its
+ * authentication process. If content type is changed when
+ * content_protection is not UNDESIRED, then kernel will disable the HDCP
+ * and re-enable with new type in the same atomic commit
*
* max bpc:
* This range property is used by userspace to limit the bit depth. When
@@ -1547,6 +1571,45 @@ int drm_connector_attach_content_protection_property(
}
EXPORT_SYMBOL(drm_connector_attach_content_protection_property);
+/**
+ * drm_connector_attach_content_protection_type_property - attach content
+ * protection type property
+ *
+ * @connector: connector to attach content protection type property on.
+ *
+ * This is used to add support for sending the protected content's stream type
+ * from userspace to kernel on selected connectors. Protected content provider
+ * will decide their type of their content and declare the same to kernel.
+ *
+ * This information will be used during the HDCP2.2 authentication.
+ *
+ * Content type will be set to _connector_state.content_protection_type.
+ *
+ * Returns:
+ *
Re: [Intel-gfx] [PATCH 07/13] drm/i915: Allow userspace to clone contexts on creation
Quoting Tvrtko Ursulin (2019-03-08 16:13:56)
>
> On 08/03/2019 14:12, Chris Wilson wrote:
> > A usecase arose out of handling context recovery in mesa, whereby they
> > wish to recreate a context with fresh logical state but preserving all
> > other details of the original. Currently, they create a new context and
> > iterate over which bits they want to copy across, but it would much more
> > convenient if they were able to just pass in a target context to clone
> > during creation. This essentially extends the setparam during creation
> > to pull the details from a target context instead of the user supplied
> > parameters.
>
> This one is not used by media so it will likely have to find a separate
> route upstream.
Eh?
However, I do think there is one quite handy usecase:
i915_query -> engines[]
gem_context_set_param(0 /* default context */, ENGINES, engines[]);
Then whenever you want a context,
ctx = gem_context_clone(0, CLONE_ENGINES);
so that you don't have to store your query results, or build a param for
every create.
> > +static int create_clone(struct i915_user_extension __user *ext, void *data)
> > +{
> > + struct drm_i915_gem_context_create_ext_clone local;
> > + struct i915_gem_context *dst = data;
> > + struct i915_gem_context *src;
> > + int err;
> > +
> > + if (copy_from_user(, ext, sizeof(local)))
> > + return -EFAULT;
> > +
> > + if (local.flags & I915_CONTEXT_CLONE_UNKNOWN)
> > + return -EINVAL;
> > +
> > + if (local.rsvd)
> > + return -EINVAL;
> > +
> > + if (local.clone == dst->user_handle) /* good guess! denied. */
> > + return -ENOENT;
>
> :) Good one, but put a more obvious comment like "Cannot clone itself!".
>
> > +
> > + rcu_read_lock();
> > + src = __i915_gem_context_lookup_rcu(dst->file_priv, local.clone);
> > + rcu_read_unlock();
> > + if (!src)
> > + return -ENOENT;
> > +
> > + GEM_BUG_ON(src == dst);
> > +
> > + if (local.flags & I915_CONTEXT_CLONE_FLAGS)
> > + dst->user_flags = src->user_flags;
> > +
> > + if (local.flags & I915_CONTEXT_CLONE_SCHED)
> > + dst->sched = src->sched;
> > +
> > + if (local.flags & I915_CONTEXT_CLONE_SSEU) {
> > + err = clone_sseu(dst, src);
> > + if (err)
> > + return err;
> > + }
> > +
> > + if (local.flags & I915_CONTEXT_CLONE_TIMELINE && src->timeline) {
>
> Do we want to error out if no timeline and cloning was requested?
No. Because a clone of that situation is no common timeline. Basically
it allows one to ask "give me everything that can be cloned" without
having to worry about what you setup beforehand.
>
> > + if (dst->timeline)
> > + i915_timeline_put(dst->timeline);
> > + dst->timeline = i915_timeline_get(src->timeline);
>
> What prevents a different thread from changing either context in
> parallel and making reference counting go bad?
It should be that userspace isn't allowed to access dst before the
constructor returns. As hinted earlier, we insert ourselves into the idr
too early. So what should be impossible... isn't quite imposibble.
src->timeline is unchangeable so we don't have to worry about
serialisation there (yet, haven't found anyone to pitch first class
timelines to).
> > + }
> > +
> > + if (local.flags & I915_CONTEXT_CLONE_VM && src->ppgtt) {
>
> Also fail if impossible was requested?
Nope. Because !src->ppgtt implies that dst is already using the same
ppgtt (the aliasing ppgtt).
> > + GEM_BUG_ON(dst->ppgtt == src->ppgtt);
>
> Hm... what prevents this? Set_vm extension followed by clone could
> trigger it I think.
True.
> > +
> > + if (dst->ppgtt)
> > + i915_ppgtt_put(dst->ppgtt);
> > +
> > + dst->ppgtt = i915_ppgtt_get(src->ppgtt);
> > + i915_ppgtt_open(dst->ppgtt);
>
> Also some locking is needed I think to make the exchange atomic.
None required for dest, but we should serialise src (well and you'll
love this, since this is under RCU).
> Could use __assign_ppgtt?
Ah. I knew there should be something.
> > static const i915_user_extension_fn create_extensions[] = {
> > [I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam,
> > + [I915_CONTEXT_CREATE_EXT_CLONE] = create_clone,
> > };
> >
> > static bool client_is_banned(struct drm_i915_file_private *file_priv)
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 007d77ff7295..50d154954d5f 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -1579,6 +1579,20 @@ struct drm_i915_gem_context_create_ext_setparam {
> > struct drm_i915_gem_context_param setparam;
> > };
> >
> > +struct drm_i915_gem_context_create_ext_clone {
> > +#define I915_CONTEXT_CREATE_EXT_CLONE 1
> > + struct i915_user_extension base;
> > + __u32 clone;
>
[Intel-gfx] [PATCH v2 0/2] HDCP2.2 Content Type support
This series adds a property called Content_protection_type onto HDCP2.2 capable intel connectors. Using this property userspace app can set the Content Type of the stream as per HDCP2.2 specification. v2: Separated from the other patches for SRM and Downstream_info Restrictions at atomic_set_property is removed [Maarten] CP appreviation is expanded [Daniel] kernel does HDCP restart when type change is requested when CP is on. Needed to remove the restriction of at atomic_set_property. Test-with: 20190308163049.9016-2-ramalinga...@intel.com Ramalingam C (2): drm: Add Content protection type property drm/i915: Attach content type property drivers/gpu/drm/drm_atomic_uapi.c | 4 ++ drivers/gpu/drm/drm_connector.c | 63 +++ drivers/gpu/drm/i915/intel_ddi.c | 21 --- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_hdcp.c | 30 --- include/drm/drm_connector.h | 15 include/uapi/drm/drm_mode.h | 4 ++ 7 files changed, 127 insertions(+), 12 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/13] drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]
On 08/03/2019 14:12, Chris Wilson wrote:
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on virtual engines that
are local to the context and do not have a valid global class:instance
lookup.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 24
include/uapi/drm/i915_drm.h | 3 ++-
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 86d9bea6f275..a581c011 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1313,6 +1313,7 @@ static int set_sseu(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_engine_cs *engine;
struct intel_sseu sseu;
+ unsigned long lookup;
Poor 32-bit builds. ;) And in lookup_user_engine as well.
int ret;
if (args->size < sizeof(user_sseu))
@@ -1325,10 +1326,17 @@ static int set_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- engine = lookup_user_engine(ctx, 0,
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ engine = lookup_user_engine(ctx, lookup,
user_sseu.engine_class,
user_sseu.engine_instance);
if (!engine)
@@ -1807,6 +1815,7 @@ static int get_sseu(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_engine_cs *engine;
struct intel_context *ce;
+ unsigned long lookup;
if (args->size == 0)
goto out;
@@ -1817,10 +1826,17 @@ static int get_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- engine = lookup_user_engine(ctx, 0,
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ engine = lookup_user_engine(ctx, lookup,
user_sseu.engine_class,
user_sseu.engine_instance);
if (!engine)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 00147b990e63..a609619610f2 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1565,9 +1565,10 @@ struct drm_i915_gem_context_param_sseu {
__u16 engine_instance;
/*
-* Unused for now. Must be cleared to zero.
+* Unknown flags must be cleared to zero.
*/
__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
/*
* Mask of slices to enable for the context. Valid values are a subset
Looks okay. But one more thing is needed:
https://cgit.freedesktop.org/~tursulin/drm-intel/commit/?h=media=38266bfe99469de9e13774a13fa641c377988c67
If you don't disagree with this patch feel free to adopt it into your tree.
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/13] drm/i915: Allow a context to define its set of engines
On 08/03/2019 14:12, Chris Wilson wrote:
Over the last few years, we have debated how to extend the user API to
support an increase in the number of engines, that may be sparse and
even be heterogeneous within a class (not all video decoders created
equal). We settled on using (class, instance) tuples to identify a
specific engine, with an API for the user to construct a map of engines
to capabilities. Into this picture, we then add a challenge of virtual
engines; one user engine that maps behind the scenes to any number of
physical engines. To keep it general, we want the user to have full
control over that mapping. To that end, we allow the user to constrain a
context to define the set of engines that it can access, order fully
controlled by the user via (class, instance). With such precise control
in context setup, we can continue to use the existing execbuf uABI of
specifying a single index; only now it doesn't automagically map onto
the engines, it uses the user defined engine map from the context.
The I915_EXEC_DEFAULT slot is left empty, and invalid for use by
execbuf. It's use will be revealed in the next patch.
v2: Fixup freeing of local on success of get_engines()
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 204 +-
drivers/gpu/drm/i915/i915_gem_context_types.h | 4 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 22 +-
include/uapi/drm/i915_drm.h | 42 +++-
4 files changed, 259 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2cfc68b66944..86d9bea6f275 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -101,6 +101,21 @@ static struct i915_global_gem_context {
struct kmem_cache *slab_luts;
} global;
+static struct intel_engine_cs *
+lookup_user_engine(struct i915_gem_context *ctx,
+ unsigned long flags, u16 class, u16 instance)
+#define LOOKUP_USER_INDEX BIT(0)
+{
+ if (flags & LOOKUP_USER_INDEX) {
+ if (instance >= ctx->nengine)
+ return NULL;
+
+ return ctx->engines[instance];
+ }
+
+ return intel_engine_lookup_user(ctx->i915, class, instance);
+}
+
struct i915_lut_handle *i915_lut_handle_alloc(void)
{
return kmem_cache_alloc(global.slab_luts, GFP_KERNEL);
@@ -234,6 +249,8 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
release_hw_id(ctx);
i915_ppgtt_put(ctx->ppgtt);
+ kfree(ctx->engines);
+
rbtree_postorder_for_each_entry_safe(it, n, >hw_contexts, node)
it->ops->destroy(it);
@@ -1311,9 +1328,9 @@ static int set_sseu(struct i915_gem_context *ctx,
if (user_sseu.flags || user_sseu.rsvd)
return -EINVAL;
- engine = intel_engine_lookup_user(i915,
- user_sseu.engine_class,
- user_sseu.engine_instance);
+ engine = lookup_user_engine(ctx, 0,
+ user_sseu.engine_class,
+ user_sseu.engine_instance);
if (!engine)
return -EINVAL;
@@ -1331,9 +1348,154 @@ static int set_sseu(struct i915_gem_context *ctx,
args->size = sizeof(user_sseu);
+ return 0;
+};
+
+struct set_engines {
+ struct i915_gem_context *ctx;
+ struct intel_engine_cs **engines;
+ unsigned int nengine;
+};
+
+static const i915_user_extension_fn set_engines__extensions[] = {
+};
+
+static int
+set_engines(struct i915_gem_context *ctx,
+ const struct drm_i915_gem_context_param *args)
+{
+ struct i915_context_param_engines __user *user;
+ struct set_engines set = { .ctx = ctx };
+ u64 size, extensions;
+ unsigned int n;
+ int err;
+
+ user = u64_to_user_ptr(args->value);
+ size = args->size;
+ if (!size)
+ goto out;
This prevents a hypothetical extension with empty map data.
+
+ BUILD_BUG_ON(!IS_ALIGNED(sizeof(*user), sizeof(*user->class_instance)));
+ if (size < sizeof(*user) || size % sizeof(*user->class_instance))
IS_ALIGNED for the second condition for consistency with the BUILD_BUG_ON?
+ return -EINVAL;
+
+ set.nengine = (size - sizeof(*user)) / sizeof(*user->class_instance);
+ if (set.nengine == 0 || set.nengine > I915_EXEC_RING_MASK + 1)
I would prefer we drop the size restriction since it doesn't apply to
the engine map per se.
+ return -EINVAL;
+
+ set.engines = kmalloc_array(set.nengine,
+ sizeof(*set.engines),
+ GFP_KERNEL);
+ if (!set.engines)
+ return -ENOMEM;
+
+ for (n = 0; n < set.nengine; n++) {
+ u16 class, inst;
+
+ if
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix CRC mismatch error for DP link layer compliance (rev3)
== Series Details == Series: drm/i915/icl: Fix CRC mismatch error for DP link layer compliance (rev3) URL : https://patchwork.freedesktop.org/series/57619/ State : warning == Summary == $ dim checkpatch origin/drm-tip e6f80925d5d2 drm/i915/icl: Fix CRC mismatch error for DP link layer compliance -:41: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #41: FILE: drivers/gpu/drm/i915/i915_reg.h:7676: +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU ^I(1 << 15)$ total: 0 errors, 1 warnings, 0 checks, 33 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/13] drm/i915: Allow userspace to clone contexts on creation
On 08/03/2019 14:12, Chris Wilson wrote:
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy across, but it would much more
convenient if they were able to just pass in a target context to clone
during creation. This essentially extends the setparam during creation
to pull the details from a target context instead of the user supplied
parameters.
This one is not used by media so it will likely have to find a separate
route upstream.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 90 +
include/uapi/drm/i915_drm.h | 14
2 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 310892b42b68..2cfc68b66944 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1428,8 +1428,98 @@ static int create_setparam(struct i915_user_extension
__user *ext, void *data)
return ctx_setparam(data, );
}
+static int clone_sseu(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ const struct intel_sseu default_sseu =
+ intel_device_default_sseu(dst->i915);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dst->i915, id) {
+ struct intel_context *ce;
+ struct intel_sseu sseu;
+
+ ce = intel_context_lookup(src, engine);
+ if (!ce)
+ continue;
+
+ sseu = ce->sseu;
+ if (!memcmp(, _sseu, sizeof(sseu)))
+ continue;
+
+ ce = intel_context_pin_lock(dst, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ ce->sseu = sseu;
+ intel_context_pin_unlock(ce);
+ }
+
+ return 0;
+}
+
+static int create_clone(struct i915_user_extension __user *ext, void *data)
+{
+ struct drm_i915_gem_context_create_ext_clone local;
+ struct i915_gem_context *dst = data;
+ struct i915_gem_context *src;
+ int err;
+
+ if (copy_from_user(, ext, sizeof(local)))
+ return -EFAULT;
+
+ if (local.flags & I915_CONTEXT_CLONE_UNKNOWN)
+ return -EINVAL;
+
+ if (local.rsvd)
+ return -EINVAL;
+
+ if (local.clone == dst->user_handle) /* good guess! denied. */
+ return -ENOENT;
:) Good one, but put a more obvious comment like "Cannot clone itself!".
+
+ rcu_read_lock();
+ src = __i915_gem_context_lookup_rcu(dst->file_priv, local.clone);
+ rcu_read_unlock();
+ if (!src)
+ return -ENOENT;
+
+ GEM_BUG_ON(src == dst);
+
+ if (local.flags & I915_CONTEXT_CLONE_FLAGS)
+ dst->user_flags = src->user_flags;
+
+ if (local.flags & I915_CONTEXT_CLONE_SCHED)
+ dst->sched = src->sched;
+
+ if (local.flags & I915_CONTEXT_CLONE_SSEU) {
+ err = clone_sseu(dst, src);
+ if (err)
+ return err;
+ }
+
+ if (local.flags & I915_CONTEXT_CLONE_TIMELINE && src->timeline) {
Do we want to error out if no timeline and cloning was requested?
+ if (dst->timeline)
+ i915_timeline_put(dst->timeline);
+ dst->timeline = i915_timeline_get(src->timeline);
What prevents a different thread from changing either context in
parallel and making reference counting go bad?
+ }
+
+ if (local.flags & I915_CONTEXT_CLONE_VM && src->ppgtt) {
Also fail if impossible was requested?
+ GEM_BUG_ON(dst->ppgtt == src->ppgtt);
Hm... what prevents this? Set_vm extension followed by clone could
trigger it I think.
+
+ if (dst->ppgtt)
+ i915_ppgtt_put(dst->ppgtt);
+
+ dst->ppgtt = i915_ppgtt_get(src->ppgtt);
+ i915_ppgtt_open(dst->ppgtt);
Also some locking is needed I think to make the exchange atomic.
Could use __assign_ppgtt?
+ }
+
+ return 0;
+}
+
static const i915_user_extension_fn create_extensions[] = {
[I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam,
+ [I915_CONTEXT_CREATE_EXT_CLONE] = create_clone,
};
static bool client_is_banned(struct drm_i915_file_private *file_priv)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 007d77ff7295..50d154954d5f 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1579,6 +1579,20 @@ struct drm_i915_gem_context_create_ext_setparam {
struct drm_i915_gem_context_param setparam;
};
+struct drm_i915_gem_context_create_ext_clone {
Re: [Intel-gfx] [PATCH 06/13] drm/i915: Allow contexts to share a single timeline across all engines
On 08/03/2019 14:12, Chris Wilson wrote:
Previously, our view has been always to run the engines independently
within a context. (Multiple engines happened before we had contexts and
timelines, so they always operated independently and that behaviour
persisted into contexts.) However, at the user level the context often
represents a single timeline (e.g. GL contexts) and userspace must
ensure that the individual engines are serialised to present that
ordering to the client (or forgot about this detail entirely and hope no
one notices - a fair ploy if the client can only directly control one
engine themselves ;)
In the next patch, we will want to construct a set of engines that
operate as one, that have a single timeline interwoven between them, to
present a single virtual engine to the user. (They submit to the virtual
engine, then we decide which engine to execute on based.)
To that end, we want to be able to create contexts which have a single
timeline (fence context) shared between all engines, rather than multiple
timelines.
No change log.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 32 ++--
drivers/gpu/drm/i915/i915_gem_context_types.h | 2 +
drivers/gpu/drm/i915/i915_request.c | 80 +--
drivers/gpu/drm/i915/i915_request.h | 5 +-
drivers/gpu/drm/i915/i915_sw_fence.c | 39 +++--
drivers/gpu/drm/i915/i915_sw_fence.h | 13 ++-
drivers/gpu/drm/i915/intel_lrc.c | 5 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 18 +++--
drivers/gpu/drm/i915/selftests/mock_context.c | 2 +-
include/uapi/drm/i915_drm.h | 3 +-
10 files changed, 149 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b41b09f60edd..310892b42b68 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -237,6 +237,9 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
rbtree_postorder_for_each_entry_safe(it, n, >hw_contexts, node)
it->ops->destroy(it);
+ if (ctx->timeline)
+ i915_timeline_put(ctx->timeline);
+
kfree(ctx->name);
put_pid(ctx->pid);
@@ -448,12 +451,17 @@ static void __assign_ppgtt(struct i915_gem_context *ctx,
static struct i915_gem_context *
i915_gem_create_context(struct drm_i915_private *dev_priv,
- struct drm_i915_file_private *file_priv)
+ struct drm_i915_file_private *file_priv,
+ unsigned int flags)
{
struct i915_gem_context *ctx;
lockdep_assert_held(_priv->drm.struct_mutex);
+ if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE &&
+ !HAS_EXECLISTS(dev_priv))
+ return ERR_PTR(-EINVAL);
+
/* Reap the most stale context */
contexts_free_first(dev_priv);
@@ -476,6 +484,18 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
i915_ppgtt_put(ppgtt);
}
+ if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
+ struct i915_timeline *timeline;
+
+ timeline = i915_timeline_create(dev_priv, ctx->name, NULL);
+ if (IS_ERR(timeline)) {
+ __destroy_hw_context(ctx, file_priv);
+ return ERR_CAST(timeline);
+ }
+
+ ctx->timeline = timeline;
+ }
+
trace_i915_context_create(ctx);
return ctx;
@@ -504,7 +524,7 @@ i915_gem_context_create_gvt(struct drm_device *dev)
if (ret)
return ERR_PTR(ret);
- ctx = i915_gem_create_context(to_i915(dev), NULL);
+ ctx = i915_gem_create_context(to_i915(dev), NULL, 0);
if (IS_ERR(ctx))
goto out;
@@ -540,7 +560,7 @@ i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
struct i915_gem_context *ctx;
int err;
- ctx = i915_gem_create_context(i915, NULL);
+ ctx = i915_gem_create_context(i915, NULL, 0);
if (IS_ERR(ctx))
return ctx;
@@ -672,7 +692,7 @@ int i915_gem_context_open(struct drm_i915_private *i915,
idr_init_base(_priv->vm_idr, 1);
mutex_lock(>drm.struct_mutex);
- ctx = i915_gem_create_context(i915, file_priv);
+ ctx = i915_gem_create_context(i915, file_priv, 0);
mutex_unlock(>drm.struct_mutex);
if (IS_ERR(ctx)) {
idr_destroy(_priv->context_idr);
@@ -788,7 +808,7 @@ last_request_on_engine(struct i915_timeline *timeline,
rq = i915_active_request_raw(>last_request,
>i915->drm.struct_mutex);
- if (rq && rq->engine == engine) {
+ if (rq && rq->engine->mask & engine->mask) {
GEM_TRACE("last request for %s on engine %s: %llx:%llu\n",
timeline->name, engine->name,
[Intel-gfx] [PATCH v2] drm/i915: Create/destroy VM (ppGTT) for use with contexts
In preparation to making the ppGTT binding for a context explicit (to
facilitate reusing the same ppGTT between different contexts), allow the
user to create and destroy named ppGTT.
v2: Replace global barrier for swapping over the ppgtt and tlbs with a
local context barrier (Tvrtko)
v3: serialise with struct_mutex; it's lazy but required dammit
v4: Rewrite igt_ctx_shared_exec to be more different (aimed to be more
similarly, turned out different!)
v2: Fix up test unwind for aliasing-ppgtt (snb)
v3: Tighten language for uapi struct drm_i915_gem_vm_control.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_context.c | 254 +-
drivers/gpu/drm/i915/i915_gem_context.h | 5 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 16 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 1 -
.../gpu/drm/i915/selftests/i915_gem_context.c | 222 +++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 -
drivers/gpu/drm/i915/selftests/mock_context.c | 8 +-
include/uapi/drm/i915_drm.h | 43 +++
11 files changed, 508 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0d743907e7bc..5d53efc4c5d9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -3121,6 +3121,8 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG,
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
};
static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4ffe19ec698..8c4eb302cc0b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -218,6 +218,9 @@ struct drm_i915_file_private {
} mm;
struct idr context_idr;
+ struct mutex vm_lock;
+ struct idr vm_idr;
+
unsigned int bsd_engine;
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b6370225dcb5..fb2aba06f693 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -126,6 +126,8 @@ static void lut_close(struct i915_gem_context *ctx)
struct i915_vma *vma = rcu_dereference_raw(*slot);
radix_tree_iter_delete(>handles_vma, , slot);
+
+ vma->open_count--;
__i915_gem_object_release_unless_active(vma->obj);
}
rcu_read_unlock();
@@ -306,7 +308,7 @@ static void context_close(struct i915_gem_context *ctx)
*/
lut_close(ctx);
if (ctx->ppgtt)
- i915_ppgtt_close(>ppgtt->vm);
+ i915_ppgtt_close(ctx->ppgtt);
ctx->file_priv = ERR_PTR(-EBADF);
i915_gem_context_put(ctx);
@@ -417,6 +419,32 @@ static void __destroy_hw_context(struct i915_gem_context
*ctx,
context_close(ctx);
}
+static struct i915_hw_ppgtt *
+__set_ppgtt(struct i915_gem_context *ctx, struct i915_hw_ppgtt *ppgtt)
+{
+ struct i915_hw_ppgtt *old = ctx->ppgtt;
+
+ i915_ppgtt_open(ppgtt);
+ ctx->ppgtt = i915_ppgtt_get(ppgtt);
+
+ ctx->desc_template = default_desc_template(ctx->i915, ppgtt);
+
+ return old;
+}
+
+static void __assign_ppgtt(struct i915_gem_context *ctx,
+ struct i915_hw_ppgtt *ppgtt)
+{
+ if (ppgtt == ctx->ppgtt)
+ return;
+
+ ppgtt = __set_ppgtt(ctx, ppgtt);
+ if (ppgtt) {
+ i915_ppgtt_close(ppgtt);
+ i915_ppgtt_put(ppgtt);
+ }
+}
+
static struct i915_gem_context *
i915_gem_create_context(struct drm_i915_private *dev_priv,
struct drm_i915_file_private *file_priv)
@@ -443,8 +471,8 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
return ERR_CAST(ppgtt);
}
- ctx->ppgtt = ppgtt;
- ctx->desc_template = default_desc_template(dev_priv, ppgtt);
+ __assign_ppgtt(ctx, ppgtt);
+ i915_ppgtt_put(ppgtt);
}
trace_i915_context_create(ctx);
@@ -625,19 +653,29 @@ static int context_idr_cleanup(int id, void *p, void
*data)
return 0;
}
+static int vm_idr_cleanup(int id, void *p, void *data)
+{
+ i915_ppgtt_put(p);
+ return 0;
+}
+
int i915_gem_context_open(struct
