[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: move the edram detection out of uncore init
== Series Details ==
Series: drm/i915: move the edram detection out of uncore init
URL : https://patchwork.freedesktop.org/series/58684/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5831_full -> Patchwork_12621_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12621_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_lease@page_flip_implicit_plane}:
- shard-skl: NOTRUN -> FAIL +1
Known issues
Here are the changes found in Patchwork_12621_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_params@no-vebox:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +138
* igt@gem_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> SKIP [fdo#109289] +2
* igt@gem_pwrite@huge-gtt-backwards:
- shard-iclb: NOTRUN -> SKIP [fdo#109290]
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: PASS -> FAIL [fdo#108686]
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-iclb: NOTRUN -> SKIP [fdo#109308]
* igt@i915_suspend@sysfs-reader:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_atomic_transition@6x-modeset-transitions:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +5
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +1
* igt@kms_busy@extended-modeset-hang-oldfb-render-e:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +15
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@vga-edid-read:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +4
* igt@kms_color@pipe-b-ctm-max:
- shard-iclb: NOTRUN -> FAIL [fdo#108147]
* igt@kms_color@pipe-c-degamma:
- shard-iclb: NOTRUN -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_dp_dsc@basic-dsc-enable-dp:
- shard-iclb: NOTRUN -> SKIP [fdo#109349]
* igt@kms_flip@2x-flip-vs-modeset-vs-hang-interruptible:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +7
* igt@kms_force_connector_basic@force-edid:
- shard-iclb: NOTRUN -> SKIP [fdo#109285]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-skl: NOTRUN -> FAIL [fdo#105682]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-iclb: PASS -> FAIL [fdo#109247] +21
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render:
- shard-iclb: NOTRUN -> FAIL [fdo#109247] +8
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +15
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: PASS -> SKIP [fdo#109642]
* igt@kms_psr@basic:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +15
* igt@kms_psr@psr2_suspend:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_psr@sprite_blt:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +4
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-iclb: PASS -> FAIL [fdo#109016]
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +12
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-iclb: NOTRUN -> SKIP [fdo#109291] +2
* igt@prime_vgem@coherency-gtt:
- shard-iclb: NOTRUN -> SKIP [fdo#109292]
* igt@tools_test@sysfs_l3_parity:
- shard-iclb: NOTRUN -> SKIP [fdo#109307]
* igt@v3d_get_param@get-bad-param:
- shard-iclb: NOTRUN -> SKIP [fdo#109315]
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915 vgpu PV to improve vgpu performance
== Series Details ==
Series: i915 vgpu PV to improve vgpu performance
URL : https://patchwork.freedesktop.org/series/58707/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/i915_vgpu.o
drivers/gpu/drm/i915/i915_vgpu.c: In function ‘pv_submit’:
drivers/gpu/drm/i915/i915_vgpu.c:337:2: error: implicit declaration of function
‘__raw_i915_write32’; did you mean ‘__raw_uncore_write32’?
[-Werror=implicit-function-declaration]
__raw_i915_write32(uncore, vgtif_reg(g2v_notify),
^~
__raw_uncore_write32
drivers/gpu/drm/i915/i915_vgpu.c: In function ‘intel_vgpu_setup_shared_page’:
drivers/gpu/drm/i915/i915_vgpu.c:523:2: error: implicit declaration of function
‘__raw_i915_write64’; did you mean ‘__raw_uncore_write64’?
[-Werror=implicit-function-declaration]
__raw_i915_write64(uncore, vgtif_reg(shared_page_gpa), gpa);
^~
__raw_uncore_write64
drivers/gpu/drm/i915/i915_vgpu.c:524:13: error: implicit declaration of
function ‘__raw_i915_read64’; did you mean ‘__raw_uncore_read64’?
[-Werror=implicit-function-declaration]
if (gpa != __raw_i915_read64(uncore, vgtif_reg(shared_page_gpa))) {
^
__raw_uncore_read64
drivers/gpu/drm/i915/i915_vgpu.c: In function ‘intel_vgpu_check_pv_caps’:
drivers/gpu/drm/i915/i915_vgpu.c:582:15: error: implicit declaration of
function ‘__raw_i915_read32’; did you mean ‘__raw_uncore_read32’?
[-Werror=implicit-function-declaration]
gvt_pvcaps = __raw_i915_read32(uncore, vgtif_reg(pv_caps));
^
__raw_uncore_read32
cc1: all warnings being treated as errors
scripts/Makefile.build:278: recipe for target
'drivers/gpu/drm/i915/i915_vgpu.o' failed
make[5]: *** [drivers/gpu/drm/i915/i915_vgpu.o] Error 1
scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm/i915' failed
make[4]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm' failed
make[3]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:489: recipe for target 'drivers/gpu' failed
make[2]: *** [drivers/gpu] Error 2
/home/cidrm/kernel/Makefile:1046: recipe for target 'drivers' failed
make[1]: *** [drivers] Error 2
Makefile:170: recipe for target 'sub-make' failed
make: *** [sub-make] Error 2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Fix clockgating issue when using scalars (rev4)
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev4)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5831_full -> Patchwork_12620_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12620_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_lease@page_flip_implicit_plane}:
- shard-skl: NOTRUN -> FAIL +1
Known issues
Here are the changes found in Patchwork_12620_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_params@no-vebox:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +120
* igt@gem_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> SKIP [fdo#109289] +2
* igt@gem_pwrite@huge-gtt-backwards:
- shard-iclb: NOTRUN -> SKIP [fdo#109290]
* igt@gem_softpin@noreloc-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-iclb: NOTRUN -> SKIP [fdo#109308]
* igt@kms_atomic_transition@6x-modeset-transitions:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +5
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +1
* igt@kms_busy@extended-modeset-hang-oldfb-render-e:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@vga-edid-read:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +4
* igt@kms_color@pipe-b-ctm-max:
- shard-iclb: NOTRUN -> FAIL [fdo#108147]
* igt@kms_color@pipe-c-degamma:
- shard-iclb: NOTRUN -> FAIL [fdo#104782]
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-iclb: PASS -> FAIL [fdo#103355]
* igt@kms_dp_dsc@basic-dsc-enable-dp:
- shard-iclb: NOTRUN -> SKIP [fdo#109349]
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_flip@2x-flip-vs-modeset-vs-hang-interruptible:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +7
* igt@kms_force_connector_basic@force-edid:
- shard-iclb: NOTRUN -> SKIP [fdo#109285]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +15
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] +3
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
- shard-iclb: NOTRUN -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-iclb: PASS -> FAIL [fdo#109247] +26
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_psr@basic:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +15
* igt@kms_psr@cursor_render:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +4
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@perf@blocking:
- shard-iclb: PASS -> FAIL [fdo#108587]
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +11
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-iclb: NOTRUN -> SKIP [fdo#109291] +2
* igt@prime_vgem@coherency-gtt:
- shard-iclb: NOTRUN -> SKIP [fdo#109292]
* igt@tools_test@sysfs_l3_parity:
- shard-iclb: NOTRUN -> SKIP [fdo#109307]
* igt@v3d_get_param@get-bad-param:
- shard-iclb: NOTRUN -> SKIP [fdo#109315]
Possible fixes
* igt@gem_create@create-clear:
- shard-iclb: INCOMPLETE [fdo#109100] -> PASS
* igt@i915_pm_rpm@modeset-lpsp:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS +1
*
[Intel-gfx] [PATCH v4 5/8] drm/i915/gvt: GVTg handle pv_caps PVINFO register
implement pv_caps PVINFO register handler in GVTg to
control different level pv optimization within guest.
report VGT_CAPS_PV capability in pvinfo page for guest.
v0: RFC
v1: rebase
v2: rebase
v3: renamed enable_pvmmio to pvmmio_caps which is used for host
pv caps.
v4: renamed pvmmio_caps to pv_caps
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/gvt/handlers.c | 4
drivers/gpu/drm/i915/gvt/vgpu.c | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index 63418c8..0333652 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1167,6 +1167,7 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu,
unsigned int offset,
break;
case 0x78010: /* vgt_caps */
case 0x7881c:
+ case _vgtif_reg(pv_caps):
break;
default:
invalid_read = true;
@@ -1240,6 +1241,9 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu,
unsigned int offset,
case _vgtif_reg(g2v_notify):
ret = handle_g2v_notification(vgpu, data);
break;
+ case _vgtif_reg(pv_caps):
+ DRM_INFO("vgpu id=%d pv caps =0x%x\n", vgpu->id, data);
+ break;
/* add xhot and yhot to handled list to avoid error log */
case _vgtif_reg(cursor_x_hot):
case _vgtif_reg(cursor_y_hot):
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 314e401..9c9a192 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -47,6 +47,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
+ vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_PV;
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
vgpu_aperture_gmadr_base(vgpu);
@@ -531,6 +532,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu,
bool dmlr,
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_workload_scheduler *scheduler = >scheduler;
unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
+ int pv_caps = vgpu_vreg_t(vgpu, vgtif_reg(pv_caps));
gvt_dbg_core("--\n");
gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
@@ -562,6 +564,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu,
bool dmlr,
intel_vgpu_reset_mmio(vgpu, dmlr);
populate_pvinfo_page(vgpu);
+ vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = pv_caps;
intel_vgpu_reset_display(vgpu);
if (dmlr) {
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 7/8] drm/i915/gvt: GVTg support ppgtt pv optimization
This patch handles ppgtt update from g2v notification.
It read out ppgtt pte entries from guest pte tables page and
convert them to host pfns.
It creates local ppgtt tables and insert the content pages
into the local ppgtt tables directly, which does not track
the usage of guest page table and removes the cost of write
protection from the original shadow page mechansim.
v0: RFC
v1: rebase
v2: rebase
v3: report pv pggtt cap to guest
v4: renamed VGPU_PVMMIO with VGPU_PVCAP for name consistance, no PV
support if gfx vtd enabled.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/gvt/gtt.c | 317
drivers/gpu/drm/i915/gvt/gtt.h | 9 +
drivers/gpu/drm/i915/gvt/gvt.h | 4 +
drivers/gpu/drm/i915/gvt/handlers.c | 12 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 3 +
5 files changed, 344 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index f4c992d..f1c07f0 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1744,6 +1744,25 @@ static int ppgtt_handle_guest_write_page_table_bytes(
return 0;
}
+static void invalidate_mm_pv(struct intel_vgpu_mm *mm)
+{
+ struct intel_vgpu *vgpu = mm->vgpu;
+ struct intel_gvt *gvt = vgpu->gvt;
+ struct intel_gvt_gtt *gtt = >gtt;
+ struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+ struct intel_gvt_gtt_entry se;
+
+ i915_ppgtt_put(mm->ppgtt);
+
+ ppgtt_get_shadow_root_entry(mm, , 0);
+ if (!ops->test_present())
+ return;
+ se.val64 = 0;
+ ppgtt_set_shadow_root_entry(mm, , 0);
+
+ mm->ppgtt_mm.shadowed = false;
+}
+
static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
{
struct intel_vgpu *vgpu = mm->vgpu;
@@ -1756,6 +1775,11 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
if (!mm->ppgtt_mm.shadowed)
return;
+ if (VGPU_PVCAP(mm->vgpu, PV_PPGTT_UPDATE)) {
+ invalidate_mm_pv(mm);
+ return;
+ }
+
for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
ppgtt_get_shadow_root_entry(mm, , index);
@@ -1773,6 +1797,26 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
mm->ppgtt_mm.shadowed = false;
}
+static int shadow_mm_pv(struct intel_vgpu_mm *mm)
+{
+ struct intel_vgpu *vgpu = mm->vgpu;
+ struct intel_gvt *gvt = vgpu->gvt;
+ struct intel_gvt_gtt_entry se;
+
+ mm->ppgtt = i915_ppgtt_create(gvt->dev_priv);
+ if (IS_ERR(mm->ppgtt)) {
+ gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
+ px_dma(>ppgtt->pml4));
+ return PTR_ERR(mm->ppgtt);
+ }
+
+ se.type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
+ se.val64 = px_dma(>ppgtt->pml4);
+ ppgtt_set_shadow_root_entry(mm, , 0);
+ mm->ppgtt_mm.shadowed = true;
+
+ return 0;
+}
static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
{
@@ -1787,6 +1831,9 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
if (mm->ppgtt_mm.shadowed)
return 0;
+ if (VGPU_PVCAP(mm->vgpu, PV_PPGTT_UPDATE))
+ return shadow_mm_pv(mm);
+
mm->ppgtt_mm.shadowed = true;
for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
@@ -2787,3 +2834,273 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
intel_vgpu_destroy_all_ppgtt_mm(vgpu);
intel_vgpu_reset_ggtt(vgpu, true);
}
+
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
+{
+ struct intel_vgpu_mm *mm;
+ int ret = 0;
+ u32 offset;
+ struct pv_ppgtt_update pv_ppgtt;
+
+ offset = offsetof(struct gvt_shared_page, pv_ppgtt);
+ intel_gvt_read_shared_page(vgpu, offset, _ppgtt, sizeof(pv_ppgtt));
+
+ mm = intel_vgpu_find_ppgtt_mm(vgpu, _ppgtt.pdp);
+ if (!mm) {
+ gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
+ ret = -EINVAL;
+ } else {
+ ret = mm->ppgtt->vm.allocate_va_range(>ppgtt->vm,
+ pv_ppgtt.start, pv_ppgtt.length);
+ if (ret)
+ gvt_vgpu_err("failed to alloc %llx\n", pv_ppgtt.pdp);
+ }
+
+ return ret;
+}
+
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
+{
+ struct intel_vgpu_mm *mm;
+ int ret = 0;
+ u32 offset;
+ struct pv_ppgtt_update pv_ppgtt;
+
+ offset = offsetof(struct gvt_shared_page, pv_ppgtt);
+ intel_gvt_read_shared_page(vgpu, offset, _ppgtt, sizeof(pv_ppgtt));
+ mm = intel_vgpu_find_ppgtt_mm(vgpu, _ppgtt.pdp);
+ if (!mm) {
+ gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
+ ret = -EINVAL;
+ } else {
+ mm->ppgtt->vm.clear_range(>ppgtt->vm,
+
[Intel-gfx] [PATCH v4 8/8] drm/i915/gvt: GVTg support context submission pv optimization
implemented context submission pv optimizaiton within GVTg.
GVTg to read context submission data (elsp_data) from the shared_page
directly without trap cost and eliminate execlist HW behavior emulation
without injecting context switch interrupt to guest under PV
submisison mechanism.
v0: RFC
v1: rebase
v2: rebase
v3: report pv context submission cap and handle VGT_G2V_ELSP_SUBMIT
g2v pv notification.
v4: eliminate execlist HW emulation and don't inject context switch
interrupt to guest under PV submisison mechanism.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/gvt/execlist.c | 6 ++
drivers/gpu/drm/i915/gvt/handlers.c | 32
drivers/gpu/drm/i915/gvt/vgpu.c | 1 +
3 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c
b/drivers/gpu/drm/i915/gvt/execlist.c
index 1a93472..e68f1d4b 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -382,6 +382,9 @@ static int prepare_execlist_workload(struct
intel_vgpu_workload *workload)
int ring_id = workload->ring_id;
int ret;
+ if (VGPU_PVCAP(vgpu, PV_SUBMISSION))
+ return 0;
+
if (!workload->emulate_schedule_in)
return 0;
@@ -429,6 +432,9 @@ static int complete_execlist_workload(struct
intel_vgpu_workload *workload)
goto out;
}
+ if (VGPU_PVCAP(vgpu, PV_SUBMISSION))
+ goto out;
+
ret = emulate_execlist_ctx_schedule_out(execlist, >ctx_desc);
out:
intel_vgpu_unpin_mm(workload->shadow_mm);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index 2b4c686..cbba77c 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1182,6 +1182,35 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu,
unsigned int offset,
return 0;
}
+static int intel_vgpu_g2v_pv_elsp_submit(struct intel_vgpu *vgpu)
+{
+ struct intel_vgpu_execlist *execlist;
+ u32 ring_id_off;
+ int ring_id;
+ u32 descs_off;
+
+ int ret = -EINVAL;
+
+ if (!VGPU_PVCAP(vgpu, PV_SUBMISSION))
+ return ret;
+
+ ring_id_off = offsetof(struct gvt_shared_page, ring_id);
+ if (intel_gvt_read_shared_page(vgpu, ring_id_off, _id, 4))
+ return ret;
+
+ if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
+ return ret;
+
+ execlist = >submission.execlist[ring_id];
+
+ descs_off = offsetof(struct gvt_shared_page, descs);
+ if (intel_gvt_read_shared_page(vgpu, descs_off,
+ >elsp_dwords.data, 8 * EXECLIST_MAX_PORTS))
+ return ret;
+
+ return intel_vgpu_submit_execlist(vgpu, ring_id);
+}
+
static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
{
intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
@@ -1221,6 +1250,9 @@ static int handle_g2v_notification(struct intel_vgpu
*vgpu, int notification)
case VGT_G2V_PPGTT_L4_CLEAR:
ret = intel_vgpu_g2v_pv_ppgtt_clear_4lvl(vgpu, pdps);
break;
+ case VGT_G2V_PV_SUBMISSION:
+ ret = intel_vgpu_g2v_pv_elsp_submit(vgpu);
+ break;
case VGT_G2V_EXECLIST_CONTEXT_CREATE:
case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
case 1: /* Remove this in guest driver. */
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index bc7387e..c71aaf6 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -51,6 +51,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
if (!intel_vtd_active())
vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = PV_PPGTT_UPDATE;
+ vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) |= PV_SUBMISSION;
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
vgpu_aperture_gmadr_base(vgpu);
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 6/8] drm/i915/gvt: GVTg handle shared_page setup
GVTg implemented shared_page setup operation and read_shared_page
functionality based on hypervisor_read_gpa().
the shared_page_gpa was passed from guest driver through PVINFO
shared_page_gpa register.
v0: RFC
v1: rebase
v2: rebase
v3: added shared_page_gpa check and if read_gpa failure, return zero
memory and handle VGT_G2V_SHARED_PAGE_SETUP g2v notification
v4: rebase
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/gvt/gvt.h | 6 +-
drivers/gpu/drm/i915/gvt/handlers.c | 15 +++
drivers/gpu/drm/i915/gvt/vgpu.c | 24
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index a4fd979..b01a54f 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -49,6 +49,7 @@
#include "fb_decoder.h"
#include "dmabuf.h"
#include "page_track.h"
+#include "i915_vgpu.h"
#define GVT_MAX_VGPU 8
@@ -229,6 +230,8 @@ struct intel_vgpu {
struct completion vblank_done;
u32 scan_nonprivbb;
+ u64 shared_page_gpa;
+ bool shared_page_enabled;
};
/* validating GM healthy status*/
@@ -686,7 +689,8 @@ int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
int intel_gvt_debugfs_init(struct intel_gvt *gvt);
void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
-
+int intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len);
#include "trace.h"
#include "mpt.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index 0333652..28b390c 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1168,6 +1168,8 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu,
unsigned int offset,
case 0x78010: /* vgt_caps */
case 0x7881c:
case _vgtif_reg(pv_caps):
+ case _vgtif_reg(shared_page_gpa):
+ case _vgtif_reg(shared_page_gpa) + 4:
break;
default:
invalid_read = true;
@@ -1185,6 +1187,7 @@ static int handle_g2v_notification(struct intel_vgpu
*vgpu, int notification)
intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
struct intel_vgpu_mm *mm;
u64 *pdps;
+ unsigned long gpa, gfn;
pdps = (u64 *)_vreg64_t(vgpu, vgtif_reg(pdp[0]));
@@ -1198,6 +1201,16 @@ static int handle_g2v_notification(struct intel_vgpu
*vgpu, int notification)
case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
+ case VGT_G2V_SHARED_PAGE_SETUP:
+ gpa = vgpu_vreg64_t(vgpu, vgtif_reg(shared_page_gpa));
+ gfn = gpa >> PAGE_SHIFT;
+ if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
+ vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = 0;
+ return 0;
+ }
+ vgpu->shared_page_gpa = gpa;
+ vgpu->shared_page_enabled = true;
+ break;
case VGT_G2V_EXECLIST_CONTEXT_CREATE:
case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
case 1: /* Remove this in guest driver. */
@@ -1257,6 +1270,8 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu,
unsigned int offset,
case _vgtif_reg(pdp[3].hi):
case _vgtif_reg(execlist_context_descriptor_lo):
case _vgtif_reg(execlist_context_descriptor_hi):
+ case _vgtif_reg(shared_page_gpa):
+ case _vgtif_reg(shared_page_gpa) + 4:
break;
case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 9c9a192..4d241a7 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -63,6 +63,8 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
+ vgpu_vreg64_t(vgpu, vgtif_reg(shared_page_gpa)) = 0;
+
gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
@@ -593,3 +595,25 @@ void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
intel_gvt_reset_vgpu_locked(vgpu, true, 0);
mutex_unlock(>vgpu_lock);
}
+
+/**
+ * intel_gvt_read_shared_page - read content from shared page
+ */
+int intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len)
+{
+ int ret = -EINVAL;
+ unsigned long gpa;
+
+ if (offset >= sizeof(struct gvt_shared_page))
+ goto err;
+
+ gpa =
[Intel-gfx] [PATCH v4 4/8] drm/i915: vgpu context submission pv optimization
It is performance optimization to override the actual submisison backend
in order to eliminate execlists csb process and reduce mmio trap numbers
for workload submission without contextswith interrupt by talking with
GVT via PV submisison notification mechanism between guest and GVT.
Use PV_SUBMISSION to control this level of pv optimization.
v0: RFC
v1: rebase
v2: added pv ops for pv context submission. to maximize code resuse,
introduced 2 more ops (submit_ports & preempt_context) instead of 1 op
(set_default_submission) in engine structure. pv version of
submit_ports and preempt_context implemented.
v3:
1. to reduce more code duplication, code refactor and replaced 2 ops
"submit_ports & preempt_contex" from v2 by 1 ops "write_desc"
in engine structure. pv version of write_des implemented.
2. added VGT_G2V_ELSP_SUBMIT for g2v pv notification.
v4: implemented pv elsp submission tasklet as the backend workload
submisison by talking to GVT with PV notificaiton mechanism and renamed
VGT_G2V_ELSP_SUBMIT to VGT_G2V_PV_SUBMISIION.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_irq.c| 2 +
drivers/gpu/drm/i915/i915_pvinfo.h | 1 +
drivers/gpu/drm/i915/i915_vgpu.c | 158 -
drivers/gpu/drm/i915/i915_vgpu.h | 10 +++
drivers/gpu/drm/i915/intel_lrc.c | 3 +
5 files changed, 173 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2f78829..28e8ee0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -37,6 +37,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
+#include "i915_vgpu.h"
/**
* DOC: interrupt handling
@@ -1470,6 +1471,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir)
if (iir & GT_RENDER_USER_INTERRUPT) {
intel_engine_breadcrumbs_irq(engine);
tasklet |= USES_GUC_SUBMISSION(engine->i915);
+ tasklet |= USES_PV_SUBMISSION(engine->i915);
}
if (tasklet)
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 2408a9d..362d898 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -50,6 +50,7 @@ enum vgt_g2v_type {
VGT_G2V_PPGTT_L4_ALLOC,
VGT_G2V_PPGTT_L4_CLEAR,
VGT_G2V_PPGTT_L4_INSERT,
+ VGT_G2V_PV_SUBMISSION,
VGT_G2V_MAX,
};
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 87a0ca5..53d05b3 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -23,6 +23,7 @@
#include "intel_drv.h"
#include "i915_vgpu.h"
+#include "intel_lrc_reg.h"
/**
* DOC: Intel GVT-g guest support
@@ -81,7 +82,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
dev_priv->vgpu.active = true;
/* guest driver PV capability */
- dev_priv->vgpu.pv_caps = PV_PPGTT_UPDATE;
+ dev_priv->vgpu.pv_caps = PV_PPGTT_UPDATE | PV_SUBMISSION;
if (!intel_vgpu_check_pv_caps(dev_priv)) {
DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
@@ -292,6 +293,154 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
* i915 vgpu PV support for Linux
*/
+static u64 execlists_update_context(struct i915_request *rq)
+{
+ struct intel_context *ce = rq->hw_context;
+ u32 *reg_state = ce->lrc_reg_state;
+
+ reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
+
+ return ce->lrc_desc;
+}
+
+static inline struct i915_priolist *to_priolist(struct rb_node *rb)
+{
+ return rb_entry(rb, struct i915_priolist, node);
+}
+
+static void pv_submit(struct intel_engine_cs *engine)
+{
+ struct intel_uncore *uncore = >i915->uncore;
+ struct intel_engine_execlists * const execlists = >execlists;
+ struct execlist_port *port = execlists->port;
+ unsigned int n;
+ struct gvt_shared_page *shared_page = engine->i915->vgpu.shared_page;
+ u64 descs[2];
+
+ for (n = 0; n < execlists_num_ports(execlists); n++) {
+ struct i915_request *rq;
+ unsigned int count = 0;
+
+ descs[n] = 0;
+ rq = port_unpack([n], );
+ if (rq && count == 0) {
+ port_set([n], port_pack(rq, ++count));
+ descs[n] = execlists_update_context(rq);
+ }
+ }
+
+ spin_lock(>i915->vgpu.shared_page_lock);
+ shared_page->ring_id = engine->id;
+ for (n = 0; n < execlists_num_ports(execlists); n++)
+ shared_page->descs[n] = descs[n];
+
+ __raw_i915_write32(uncore, vgtif_reg(g2v_notify),
+ VGT_G2V_PV_SUBMISSION);
+ spin_unlock(>i915->vgpu.shared_page_lock);
+}
+
+static void pv_dequeue(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlists * const execlists = >execlists;
+ struct
[Intel-gfx] [PATCH v4 3/8] drm/i915: vgpu ppgtt update pv optimization
This patch extends vgpu ppgtt g2v notification to notify host
GVT-g of ppgtt update from guest including alloc_4lvl, clear_4lv4
and insert_4lvl.
These updates use the shared memory page to pass struct pv_ppgtt_update
from guest to GVT which is used for pv optimiation implemeation within
host GVT side.
This patch also add one new pv_caps level to control ppgtt update.
Use PV_PPGTT_UPDATE to control this level of pv optimization.
v0: RFC
v1: rebased
v2: added pv callbacks for vm.{allocate_va_range, insert_entries,
clear_range} within ppgtt.
v3: rebased, disable huge page ppgtt support when using PVMMIO ppgtt
update due to complex and performance impact.
v4: moved alloc/insert/clear_4lvl pv callbacks into i915_vgpu_pv.c and
added a single intel_vgpu_config_pv_caps() for vgpu pv callbacks setup.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_gem.c | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 8
drivers/gpu/drm/i915/i915_pvinfo.h | 3 ++
drivers/gpu/drm/i915/i915_vgpu.c| 84 +
drivers/gpu/drm/i915/i915_vgpu.h| 17
6 files changed, 120 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f6cdd5f..c96a6d0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4826,7 +4826,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
int ret;
/* We need to fallback to 4K pages if host doesn't support huge gtt. */
- if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
+ if ((intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
+ || intel_vgpu_enabled_pv_caps(dev_priv, PV_PPGTT_UPDATE))
mkwrite_device_info(dev_priv)->page_sizes =
I915_GTT_PAGE_SIZE_4K;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 736c845..8011527 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -923,7 +923,7 @@ static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
* This is the top-level structure in 4-level page tables used on gen8+.
* Empty entries are always scratch pml4e.
*/
-static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
u64 start, u64 length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
@@ -1162,7 +1162,7 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
} while (iter->sg);
}
-static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 flags)
@@ -1444,7 +1444,7 @@ static int gen8_ppgtt_alloc_3lvl(struct
i915_address_space *vm,
_vm_to_ppgtt(vm)->pdp, start, length);
}
-static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
u64 start, u64 length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
@@ -1571,6 +1571,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
+
+ if (intel_vgpu_active(i915))
+ intel_vgpu_config_pv_caps(i915, PV_PPGTT_UPDATE, ppgtt);
} else {
err = __pdp_init(>vm, >pdp);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 83ded9f..03cff75 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -625,6 +625,14 @@ int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base);
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
+ u64 start, u64 length);
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
+ struct i915_vma *vma,
+ enum i915_cache_level cache_level, u32 flags);
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
+ u64 start, u64 length);
+
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 4657bf7..2408a9d 100644
---
[Intel-gfx] [PATCH v4 0/8] i915 vgpu PV to improve vgpu performance
To improve vgpu performance, it could implement some PV optimization such as to reduce the mmio access trap numbers or eliminate certain piece of HW emulation within guest driver to reduce vm exit/vm enter cost. the solutions in this patch set are implemented two PV optimizations based on the shared memory region between guest and GVTg for data communication. The shared memory region is allocated by guest driver and this region's memory guest physical address will be passed to GVTg through PVINFO register and later GVTg can access this region directly without trap cost to achieve data exchange purpose between guest and GVTg. in this patch set, 2 kind of PV optimization implemented controlled by pv_caps PVINO register with different pv bit. 1. workload PV submission (context submission): reduce 4 traps to 1 trap and eliminated execlists HW behaviour emulation. 2. ppgtt PV update: eliminate the cost of ppgtt write protection. based on the experiment, for small workloads, specifally, glxgears with vblank_mode off, the average performance gain on single vgpu is 30~50%. for large workload such as media and 3D, the average performance gain is about 4%. based on the PV mechanism, it could achive more vgpu feature optimization such as globle GTT update, display plane and water mark update. v0: RFC patch set v1: addressed RFC review comments v2: addressed v1 review comments, added pv callbacks for pv operations v3: 1. addressed v2 review comments, removed pv callbacks code duplication in v2 and unified pv calls under g2v notification register. different g2v pv notifications defined. 2. dropped pv master irq feature due to hard conflict with recnet i915 change and take time to rework. v4: 1. addressed v3 review comments. 2. extended workload PV submission by skip execlists HW behaviour emulation and context switch interrupt injection. Xiaolin Zhang (8): drm/i915: introduced vgpu pv capability drm/i915: vgpu shared memory setup for pv optimization drm/i915: vgpu ppgtt update pv optimization drm/i915: vgpu context submission pv optimization drm/i915/gvt: GVTg handle pv_caps PVINFO register drm/i915/gvt: GVTg handle shared_page setup drm/i915/gvt: GVTg support ppgtt pv optimization drm/i915/gvt: GVTg support context submission pv optimization drivers/gpu/drm/i915/gvt/execlist.c | 6 + drivers/gpu/drm/i915/gvt/gtt.c | 317 +++ drivers/gpu/drm/i915/gvt/gtt.h | 9 + drivers/gpu/drm/i915/gvt/gvt.h | 10 +- drivers/gpu/drm/i915/gvt/handlers.c | 63 ++- drivers/gpu/drm/i915/gvt/vgpu.c | 31 drivers/gpu/drm/i915/i915_drv.h | 6 +- drivers/gpu/drm/i915/i915_gem.c | 3 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +- drivers/gpu/drm/i915/i915_gem_gtt.h | 8 + drivers/gpu/drm/i915/i915_irq.c | 2 + drivers/gpu/drm/i915/i915_pvinfo.h | 12 +- drivers/gpu/drm/i915/i915_vgpu.c| 323 +++- drivers/gpu/drm/i915/i915_vgpu.h| 52 ++ drivers/gpu/drm/i915/intel_lrc.c| 3 + 15 files changed, 845 insertions(+), 9 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/8] drm/i915: vgpu shared memory setup for pv optimization
To enable vgpu pv features, we need to setup a shared memory page
which will be used for data exchange directly accessed between both
guest and backend i915 driver to avoid emulation trap cost.
guest i915 will allocate this page memory and then pass it's physical
address to backend i915 driver through PVINFO register so that backend i915
driver can access this shared page meory without any trap cost with the
help form hyperviser's read guest gpa functionality.
guest i915 will send VGT_G2V_SHARED_PAGE_SETUP notification to host GVT
once shared memory setup finished.
the layout of the shared_page also defined as well in this patch which
is used for pv features implementation.
v0: RFC
v1: addressed RFC comment to move both shared_page_lock and shared_page
to i915_virtual_gpu structure
v2: packed i915_virtual_gpu structure
v3: added SHARED_PAGE_SETUP g2v notification for pv shared_page setup
v4: added intel_vgpu_setup_shared_page() in i915_vgpu_pv.c
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_drv.h| 4 +++-
drivers/gpu/drm/i915/i915_pvinfo.h | 5 -
drivers/gpu/drm/i915/i915_vgpu.c | 38 ++
drivers/gpu/drm/i915/i915_vgpu.h | 17 +
4 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b0c50bb..6abd112 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1248,7 +1248,9 @@ struct i915_virtual_gpu {
bool active;
u32 caps;
u32 pv_caps;
-};
+ spinlock_t shared_page_lock;
+ struct gvt_shared_page *shared_page;
+} __packed;
/* used in computing the new watermarks state */
struct intel_wm_config {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 619305a..4657bf7 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,7 @@ enum vgt_g2v_type {
VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
VGT_G2V_EXECLIST_CONTEXT_CREATE,
VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+ VGT_G2V_SHARED_PAGE_SETUP,
VGT_G2V_MAX,
};
@@ -110,7 +111,9 @@ struct vgt_if {
u32 pv_caps;
- u32 rsv7[0x200 - 25];/* pad to one page */
+ u64 shared_page_gpa;
+
+ u32 rsv7[0x200 - 27];/* pad to one page */
} __packed;
#define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index e9f6d96..1530552 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -135,6 +135,9 @@ void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
for (i = 0; i < 4; i++)
vgt_deballoon_space(_priv->ggtt, _info.space[i]);
+
+ if (dev_priv->vgpu.shared_page)
+ free_page((unsigned long)dev_priv->vgpu.shared_page);
}
static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -286,6 +289,36 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
* i915 vgpu PV support for Linux
*/
+/*
+ * shared_page setup for VGPU PV features
+ */
+static int intel_vgpu_setup_shared_page(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = _priv->uncore;
+ u64 gpa;
+
+ dev_priv->vgpu.shared_page = (struct gvt_shared_page *)
+ get_zeroed_page(GFP_KERNEL);
+ if (!dev_priv->vgpu.shared_page) {
+ DRM_ERROR("out of memory for shared page memory\n");
+ return -ENOMEM;
+ }
+
+ /* pass guest memory pa address to GVT and then read back to verify */
+ gpa = __pa(dev_priv->vgpu.shared_page);
+ __raw_i915_write64(uncore, vgtif_reg(shared_page_gpa), gpa);
+ if (gpa != __raw_i915_read64(uncore, vgtif_reg(shared_page_gpa))) {
+ DRM_ERROR("vgpu: passed shared_page_gpa failed\n");
+ free_page((unsigned long)dev_priv->vgpu.shared_page);
+ return -EIO;
+ }
+ __raw_i915_write32(uncore, vgtif_reg(g2v_notify),
+ VGT_G2V_SHARED_PAGE_SETUP);
+ spin_lock_init(_priv->vgpu.shared_page_lock);
+
+ return 0;
+}
+
/**
* intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities
* @dev_priv: i915 device private
@@ -313,6 +346,11 @@ bool intel_vgpu_check_pv_caps(struct drm_i915_private
*dev_priv)
if (!pvcaps)
return false;
+ if (intel_vgpu_setup_shared_page(dev_priv)) {
+ dev_priv->vgpu.pv_caps = 0;
+ return false;
+ }
+
__raw_i915_write32(uncore, vgtif_reg(pv_caps), pvcaps);
return true;
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 91010fc..68127d4 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -26,6 +26,23 @@
#include "i915_pvinfo.h"
+/*
+ * A shared page(4KB) between gvt and VM, could be allocated by guest driver
+ * or a
[Intel-gfx] [PATCH v4 1/8] drm/i915: introduced vgpu pv capability
pv capability for guest gpu was introduced by pv_caps in struct
i915_virtual_gpu and a new pv_caps register for host GVT
was defined in struct vgt_if for vgpu pv optimization.
both of them are used to control different feature pv optimization
supported and implemented by both guest and host.
These fields are default zero, no any pv feature enabled.
it also adds VGT_CAPS_PV capability BIT for guest to check GVTg
can support PV feature or not.
v0: RFC, introudced enable_pvmmio module parameter.
v1: addressed RFC comment to remove enable_pvmmio module parameter
by pv capability check.
v2: rebase
v3: distinct pv caps from guest and host. renamed enable_pvmmio to
pvmmio_caps which is used for host pv caps.
v4: consolidated all pv related functons into a single file i915_vgpu.c
and renamed pvmmio to pv_caps.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_drv.h| 2 ++
drivers/gpu/drm/i915/i915_pvinfo.h | 5 -
drivers/gpu/drm/i915/i915_vgpu.c | 45 +-
drivers/gpu/drm/i915/i915_vgpu.h | 8 +++
4 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eff0e9a..b0c50bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -86,6 +86,7 @@
#include "i915_vma.h"
#include "intel_gvt.h"
+#include "i915_pvinfo.h"
/* General customization:
*/
@@ -1246,6 +1247,7 @@ struct i915_frontbuffer_tracking {
struct i915_virtual_gpu {
bool active;
u32 caps;
+ u32 pv_caps;
};
/* used in computing the new watermarks state */
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 969e514..619305a 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -55,6 +55,7 @@ enum vgt_g2v_type {
#define VGT_CAPS_FULL_PPGTTBIT(2)
#define VGT_CAPS_HWSP_EMULATIONBIT(3)
#define VGT_CAPS_HUGE_GTT BIT(4)
+#define VGT_CAPS_PVBIT(5)
struct vgt_if {
u64 magic; /* VGT_MAGIC */
@@ -107,7 +108,9 @@ struct vgt_if {
u32 execlist_context_descriptor_lo;
u32 execlist_context_descriptor_hi;
- u32 rsv7[0x200 - 24];/* pad to one page */
+ u32 pv_caps;
+
+ u32 rsv7[0x200 - 25];/* pad to one page */
} __packed;
#define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 3d0b493..e9f6d96 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -79,7 +79,14 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
dev_priv->vgpu.active = true;
- DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+
+ if (!intel_vgpu_check_pv_caps(dev_priv)) {
+ DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+ return;
+ }
+
+ DRM_INFO("Virtual GPU for Intel GVT-g detected with pv_caps 0x%x.\n",
+ dev_priv->vgpu.pv_caps);
}
bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
@@ -274,3 +281,39 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
DRM_ERROR("VGT balloon fail\n");
return ret;
}
+
+/*
+ * i915 vgpu PV support for Linux
+ */
+
+/**
+ * intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities
+ * @dev_priv: i915 device private
+ *
+ * This function is called at the initialization stage, to detect VGPU
+ * PV capabilities
+ *
+ * If guest wants to enable pv_caps, it needs to config it explicitly
+ * through vgt_if interface from gvt layer.
+ */
+bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = _priv->uncore;
+ u32 gvt_pvcaps;
+ u32 pvcaps;
+
+ if (!intel_vgpu_has_pv_caps(dev_priv))
+ return false;
+
+ /* PV capability negotiation between PV guest and GVT */
+ gvt_pvcaps = __raw_i915_read32(uncore, vgtif_reg(pv_caps));
+ pvcaps = dev_priv->vgpu.pv_caps & gvt_pvcaps;
+ dev_priv->vgpu.pv_caps = pvcaps;
+
+ if (!pvcaps)
+ return false;
+
+ __raw_i915_write32(uncore, vgtif_reg(pv_caps), pvcaps);
+
+ return true;
+}
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index ebe1b7b..91010fc 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -42,7 +42,15 @@ intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
}
+static inline bool
+intel_vgpu_has_pv_caps(struct drm_i915_private *dev_priv)
+{
+ return dev_priv->vgpu.caps & VGT_CAPS_PV;
+}
+
int intel_vgt_balloon(struct drm_i915_private *dev_priv);
void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
+/* i915 vgpu pv related functions */
+bool
[Intel-gfx] i915: Questions for drm-panic development
Hello i915 developers, I'm currently working on a drm-based panic viewer. As can be seen from [1] and [2], the _initial_ design for drm-panic is now agreed upon, with ACKs from both DRM and active printk engineers. The main use-case is consumer-level x86 laptops, so i915 will be the natural first target. I've currently developed a prototype, based on code from Noralf Trønnes, that carefully picks the needed drm_framebuffer from within a panic context. The added drm_framebuffer_funcs hooks are: void *(*panic_prepare)(struct drm_framebuffer *fb); void (*panic_cleanup)(struct drm_framebuffer *fb, void *cookie); int (*panic_draw_xy)(struct drm_framebuffer *fb, void *cookie, int x, int y, bool foreground); Now it's time for the i915-specific bits, and I'm very new to the whole graphics / i915 world in general :) I'm currently learning all the basics (GTT, etc.) from: https://blog.ffwll.ch/2013/01/i915gem-crashcourse-overview.html https://bwidawsk.net/blog/index.php/2014/06/the-global-gtt-part-1 https://01.org/linuxgraphics/documentation/hardware-specification-prms Some questions: - Current development target is an Intel i5-8250U / Kaby Lake R / UHD 620 laptop. Does this make __any__ difference? - The i915 code covers a huge set of intel gfx HW families. Will this ever necessitate different drm-panic hooks implementation? - For the i915-specific hooks, do you have any further advice? e.g. points to be extra careful about, specific HW or SW refs I should further check, and so on? Thanks a lot! [1] https://lists.freedesktop.org/archives/dri-devel/2019-March/210973.html [2] https://lore.kernel.org/lkml/20190310013142.GA3376@darwi-home-pc -- darwi http://darwish.chasingpointers.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] PR - guC 32.0.3
Sending PR for guCv32.0.3- The following changes since commit 7bc246451318b3536d9bfd3c4e46d541a9831b33: Merge branch 'for-upstream' of git://git.chelsio.net/pub/git/linux-firmware (2019-03-14 08:22:39 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware guc_updates for you to fetch changes up to b84c6eaf14d2e9aa7ae2071e95ceb491485900f8: drm/i915/firmware: Add ICL HuC v08.4.3132 (2019-03-28 17:40:54 -0700) Anusha Srivatsa (7): drm/i915/firmware: Add BXT GuC v32.0.3 drm/i915/firmware: Add SKL GuC v32.0.3 drm/i915/firmware: Add KBL GuC v32.0.3 drm/i915/firmware: Add GLK GuC v32.0.3 drm/i915/firmware: Add GLK HuC v03.01.2893 drm/i915/firmware: Add ICL GuC v32.0.3 drm/i915/firmware: Add ICL HuC v08.4.3132 WHENCE | 21 + i915/bxt_guc_32.0.3.bin| Bin 0 -> 176256 bytes i915/glk_guc_32.0.3.bin| Bin 0 -> 176640 bytes i915/glk_huc_ver03_01_2893.bin | Bin 0 -> 222080 bytes i915/icl_guc_32.0.3.bin| Bin 0 -> 380096 bytes i915/icl_huc_ver8_4_3132.bin | Bin 0 -> 488512 bytes i915/kbl_guc_32.0.3.bin| Bin 0 -> 176448 bytes i915/skl_guc_32.0.3.bin| Bin 0 -> 175552 bytes 8 files changed, 21 insertions(+) create mode 100644 i915/bxt_guc_32.0.3.bin create mode 100644 i915/glk_guc_32.0.3.bin create mode 100644 i915/glk_huc_ver03_01_2893.bin create mode 100644 i915/icl_guc_32.0.3.bin create mode 100644 i915/icl_huc_ver8_4_3132.bin create mode 100644 i915/kbl_guc_32.0.3.bin create mode 100644 i915/skl_guc_32.0.3.bin Thanks, Anusha ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add 10bit LUT for ilk/snb
On Thu, Mar 28, 2019 at 11:05:03PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Plop in support for 10bit LUT on ilk/snb.
>
> There is no split gamma mode on these platforms, so we have
> to choose between degamma and gamma. That could be a runtime choice
> but for now let's just advertize the gamma as having 1024 entries.
> We'll also keep the ctm hidden for now.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
I also glanced through patches 5 and 6 and didn't notice anything
obviously wrong, but I'm not sure how to find bspec-level information
for those platforms.
Matt
> ---
> drivers/gpu/drm/i915/i915_pci.c| 4 +++
> drivers/gpu/drm/i915/i915_reg.h| 9 ++
> drivers/gpu/drm/i915/intel_color.c | 44 ++
> 3 files changed, 51 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 385056752939..0971eee4a4d1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -116,6 +116,8 @@
> [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> }
>
> +#define ILK_COLORS \
> + .color = { .gamma_lut_size = 1024 }
> #define IVB_COLORS \
> .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
> #define CHV_COLORS \
> @@ -325,6 +327,7 @@ static const struct intel_device_info intel_gm45_info = {
> .has_rc6 = 0, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> + ILK_COLORS, \
> GEN_DEFAULT_PAGE_SIZES
>
> static const struct intel_device_info intel_ironlake_d_info = {
> @@ -353,6 +356,7 @@ static const struct intel_device_info
> intel_ironlake_m_info = {
> .ppgtt_size = 31, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> + ILK_COLORS, \
> GEN_DEFAULT_PAGE_SIZES
>
> #define SNB_D_PLATFORM \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eb7e93354cfe..f6a5d8f11368 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7209,6 +7209,15 @@ enum {
> #define _LGC_PALETTE_B 0x4a800
> #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A,
> _LGC_PALETTE_B) + (i) * 4)
>
> +/* ilk/snb precision palette */
> +#define _PREC_PALETTE_A 0x4b000
> +#define _PREC_PALETTE_B 0x4c000
> +#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A,
> _PREC_PALETTE_B) + (i) * 4)
> +
> +#define _PREC_PIPEAGCMAX 0x4d000
> +#define _PREC_PIPEBGCMAX 0x4d010
> +#define PREC_PIPEGCMAX(pipe, i)_MMIO(_PIPE(pipe, _PIPEAGCMAX,
> _PIPEBGCMAX) + (i) * 4)
> +
> #define _GAMMA_MODE_A0x4a480
> #define _GAMMA_MODE_B0x4ac80
> #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 70a71c92e3e5..8e03f066adf7 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -468,6 +468,29 @@ static void skl_color_commit(const struct
> intel_crtc_state *crtc_state)
> ilk_load_csc_matrix(crtc_state);
> }
>
> +static void ilk_load_lut_10(struct intel_crtc *crtc,
> + const struct drm_property_blob *blob)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct drm_color_lut *lut = blob->data;
> + int i, lut_size = drm_color_lut_size(blob);
> + enum pipe pipe = crtc->pipe;
> +
> + for (i = 0; i < lut_size; i++)
> + I915_WRITE_FW(PREC_PALETTE(pipe, i), ilk_lut_10([i]));
> +}
> +
> +static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> +
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> + i9xx_load_luts(crtc_state);
> + else
> + ilk_load_lut_10(crtc, gamma_lut);
> +}
> +
> /*
> * IVB/HSW Bspec / PAL_PREC_INDEX:
> * "Restriction : Index auto increment mode is not
> @@ -961,6 +984,15 @@ static int chv_color_check(struct intel_crtc_state
> *crtc_state)
> return 0;
> }
>
> +static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
> +{
> + if (!crtc_state->gamma_enable ||
> + crtc_state_is_legacy_gamma(crtc_state))
> + return GAMMA_MODE_MODE_8BIT;
> + else
> + return GAMMA_MODE_MODE_10BIT;
> +}
> +
> static int ilk_color_check(struct intel_crtc_state *crtc_state)
> {
> int ret;
> @@ -980,8 +1012,7 @@ static int ilk_color_check(struct intel_crtc_state
> *crtc_state)
>*/
> crtc_state->csc_enable = false;
>
> - /* We don't expose fancy gamma modes on ilk/snb currently */
> - crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> + crtc_state->gamma_mode =
Re: [Intel-gfx] [PATCH 3/6] drm/i915: Implement split/10bit gamma for ivb/hsw
On Thu, Mar 28, 2019 at 11:05:02PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Reuse the bdw+ code to get split/10bit gamma for
> ivb/hsw. The hardware is nearly identical. The
> only slight snag is that on ivb/hsw the precision
> palette auto increment mode does not work. So we
> must increment the index manually. We'll probably
> want to stick to the auto increment mode on bdw+
> in the name of efficiency.
>
> Also we want to avoid using the CSC for limited range
> RGB output as PIPECONF will take care of that on IVB.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_pci.c| 6 +-
> drivers/gpu/drm/i915/intel_color.c | 113 +++--
> 2 files changed, 95 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index a7e1611af26d..385056752939 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -116,7 +116,7 @@
> [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> }
>
> -#define BDW_COLORS \
> +#define IVB_COLORS \
> .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
> #define CHV_COLORS \
> .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
> @@ -399,6 +399,7 @@ static const struct intel_device_info
> intel_sandybridge_m_gt2_info = {
> .ppgtt_size = 31, \
> IVB_PIPE_OFFSETS, \
> IVB_CURSOR_OFFSETS, \
> + IVB_COLORS, \
> GEN_DEFAULT_PAGE_SIZES
>
> #define IVB_D_PLATFORM \
> @@ -494,7 +495,6 @@ static const struct intel_device_info
> intel_haswell_gt3_info = {
> #define GEN8_FEATURES \
> G75_FEATURES, \
> GEN(8), \
> - BDW_COLORS, \
> .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> I915_GTT_PAGE_SIZE_2M, \
> .has_logical_ring_contexts = 1, \
> @@ -629,7 +629,7 @@ static const struct intel_device_info
> intel_skylake_gt4_info = {
> .display.has_ipc = 1, \
> HSW_PIPE_OFFSETS, \
> IVB_CURSOR_OFFSETS, \
> - BDW_COLORS, \
> + IVB_COLORS, \
> GEN9_DEFAULT_PAGE_SIZES
>
> static const struct intel_device_info intel_broxton_info = {
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index ed4bd9bd15f5..70a71c92e3e5 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -428,6 +428,8 @@ static void ilk_color_commit(const struct
> intel_crtc_state *crtc_state)
> val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
> val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> I915_WRITE(PIPECONF(pipe), val);
> +
> + ilk_load_csc_matrix(crtc_state);
> }
>
> static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> @@ -466,6 +468,48 @@ static void skl_color_commit(const struct
> intel_crtc_state *crtc_state)
> ilk_load_csc_matrix(crtc_state);
> }
>
> +/*
> + * IVB/HSW Bspec / PAL_PREC_INDEX:
> + * "Restriction : Index auto increment mode is not
> + * supported and must not be enabled."
> + */
> +static void ivb_load_lut_10(struct intel_crtc *crtc,
> + const struct drm_property_blob *blob,
> + u32 prec_index, bool duplicate)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct drm_color_lut *lut = blob->data;
> + int i, lut_size = drm_color_lut_size(blob);
> + enum pipe pipe = crtc->pipe;
> +
> + /*
> + * We advertize the split gamma sizes. When not using split
> + * gamma we just duplicate each entry.
> + *
> + * TODO: expose the full LUT to userspace
> + */
> + if (duplicate) {
> + for (i = 0; i < lut_size; i++) {
> + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
> + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
> + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
> + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
> + }
> + } else {
> + for (i = 0; i < lut_size; i++) {
> + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
> + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
> + }
> + }
> +
> + /*
> + * Reset the index, otherwise it prevents the legacy palette to be
> + * written properly.
> + */
> + I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> +}
> +
> +/* On BDW+ the index auto increment mode actually works */
> static void bdw_load_lut_10(struct intel_crtc *crtc,
> const struct drm_property_blob *blob,
> u32 prec_index, bool duplicate)
> @@ -501,7 +545,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> }
>
> -static void bdw_load_lut_10_max(struct intel_crtc *crtc,
> +static void ivb_load_lut_10_max(struct intel_crtc *crtc,
>
Re: [Intel-gfx] [PATCH 2/6] drm/i915: Don't use split gamma when we don't have to
On Thu, Mar 28, 2019 at 11:05:01PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Using the split gamma mode when we don't have to has the annoying
> requirement of loading a linear LUT to the unused half. Instead
> let's make life simpler by switching to the 10bit gamma mode
> and duplicating each entry.
>
> This also allows us to load the software gamma LUT into the
> hardware degamma LUT, thus removing some of the buggy
> configurations we currently allow (YCbCr/limited range RGB
> + gamma LUT). We do still have other configurations that are
> also buggy, but those will need more complicated fixes
> or they just need to be rejected. Sadly GLK doesn't have
> this flexibility anymore and the degamma and gamma LUTs
> are very different so no help there.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h| 1 +
> drivers/gpu/drm/i915/intel_color.c | 159 +++--
> 2 files changed, 86 insertions(+), 74 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c866379a521b..eb7e93354cfe 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10127,6 +10127,7 @@ enum skl_power_gate {
> #define PAL_PREC_SPLIT_MODE(1 << 31)
> #define PAL_PREC_AUTO_INCREMENT(1 << 15)
> #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
> +#define PAL_PREC_INDEX_VALUE(x)((x) << 0)
> #define _PAL_PREC_DATA_A 0x4A404
> #define _PAL_PREC_DATA_B 0x4AC04
> #define _PAL_PREC_DATA_C 0x4B404
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index d7c38a2bbd8f..ed4bd9bd15f5 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -466,72 +466,32 @@ static void skl_color_commit(const struct
> intel_crtc_state *crtc_state)
> ilk_load_csc_matrix(crtc_state);
> }
>
> -static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> +static void bdw_load_lut_10(struct intel_crtc *crtc,
> + const struct drm_property_blob *blob,
> + u32 prec_index, bool duplicate)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct drm_property_blob *degamma_lut =
> crtc_state->base.degamma_lut;
> - u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> + const struct drm_color_lut *lut = blob->data;
> + int i, lut_size = drm_color_lut_size(blob);
> enum pipe pipe = crtc->pipe;
>
> - I915_WRITE(PREC_PAL_INDEX(pipe),
> -PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
> -
> - if (degamma_lut) {
> - const struct drm_color_lut *lut = degamma_lut->data;
> + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
> +PAL_PREC_AUTO_INCREMENT);
>
> - for (i = 0; i < lut_size; i++)
> - I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
> - } else {
> + /*
> + * We advertize the split gamma sizes. When not using split
> + * gamma we just duplicate each entry.
> + *
> + * TODO: expose the full LUT to userspace
Any reason not to just do this immediately? Throwing away half the
table entries if we decide we need split mode doesn't seem any harder
than duplicating the entries when we decide we don't. The color
management kerneldoc already explicitly recommends this approach for
hardware that can support multiple gamma modes, so I don't think we need
any new ABI to handle it.
> + */
> + if (duplicate) {
> for (i = 0; i < lut_size; i++) {
> - u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
> -
> - I915_WRITE(PREC_PAL_DATA(pipe),
> -(v << 20) | (v << 10) | v);
> + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
> + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
> }
> - }
> -}
> -
> -static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state,
> u32 offset)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - u32 i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> - enum pipe pipe = crtc->pipe;
> -
> - WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
> -
> - I915_WRITE(PREC_PAL_INDEX(pipe),
> -(offset ? PAL_PREC_SPLIT_MODE : 0) |
> -PAL_PREC_AUTO_INCREMENT |
> -offset);
> -
> - if (gamma_lut) {
> - const struct drm_color_lut *lut = gamma_lut->data;
> -
> + } else {
> for (i = 0; i < lut_size; i++)
>
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Extract ilk_lut_10()
On Thu, Mar 28, 2019 at 11:05:00PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract a helper to calculate the ILK+ 10it gamma LUT entry.
Missing a 'b' in '10it' but otherwise:
Reviewed-by: Matt Roper
> It's already duplicated twice, and soon we'll have more.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_color.c | 27 +++
> 1 file changed, 11 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index ff910ed08468..d7c38a2bbd8f 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -359,6 +359,13 @@ static void cherryview_load_csc_matrix(const struct
> intel_crtc_state *crtc_state
> I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
> }
>
> +static u32 ilk_lut_10(const struct drm_color_lut *color)
> +{
> + return drm_color_lut_extract(color->red, 10) << 20 |
> + drm_color_lut_extract(color->green, 10) << 10 |
> + drm_color_lut_extract(color->blue, 10);
> +}
> +
> /* Loads the legacy palette/gamma unit for the CRTC. */
> static void i9xx_load_luts_internal(const struct intel_crtc_state
> *crtc_state,
> const struct drm_property_blob *blob)
> @@ -473,14 +480,8 @@ static void bdw_load_degamma_lut(const struct
> intel_crtc_state *crtc_state)
> if (degamma_lut) {
> const struct drm_color_lut *lut = degamma_lut->data;
>
> - for (i = 0; i < lut_size; i++) {
> - u32 word =
> - drm_color_lut_extract(lut[i].red, 10) << 20 |
> - drm_color_lut_extract(lut[i].green, 10) << 10 |
> - drm_color_lut_extract(lut[i].blue, 10);
> -
> - I915_WRITE(PREC_PAL_DATA(pipe), word);
> - }
> + for (i = 0; i < lut_size; i++)
> + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
> } else {
> for (i = 0; i < lut_size; i++) {
> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
> @@ -509,14 +510,8 @@ static void bdw_load_gamma_lut(const struct
> intel_crtc_state *crtc_state, u32 of
> if (gamma_lut) {
> const struct drm_color_lut *lut = gamma_lut->data;
>
> - for (i = 0; i < lut_size; i++) {
> - u32 word =
> - (drm_color_lut_extract(lut[i].red, 10) << 20) |
> - (drm_color_lut_extract(lut[i].green, 10) << 10) |
> - drm_color_lut_extract(lut[i].blue, 10);
> -
> - I915_WRITE(PREC_PAL_DATA(pipe), word);
> - }
> + for (i = 0; i < lut_size; i++)
> + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
>
> /* Program the max register to clamp values > 1.0. */
> i = lut_size - 1;
> --
> 2.19.2
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h (rev5)
== Series Details == Series: drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h (rev5) URL : https://patchwork.freedesktop.org/series/58052/ State : success == Summary == CI Bug Log - changes from CI_DRM_5832 -> Patchwork_12624 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58052/revisions/5/mbox/ Known issues Here are the changes found in Patchwork_12624 that come from known issues: ### IGT changes ### Issues hit * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] Possible fixes * igt@i915_selftest@live_uncore: - fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS * igt@kms_busy@basic-flip-b: - fi-gdg-551: FAIL [fdo#103182] -> PASS * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 Participating hosts (43 -> 38) -- Missing(5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-apl-guc Build changes - * Linux: CI_DRM_5832 -> Patchwork_12624 CI_DRM_5832: f1fc30ad3723a8b6265c2edf50a7f637ecd75a23 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4911: d9fe699ea45406e279b78d1afdb4d57a205a3c99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12624: bd4fcb4edac9380ff47cc2e9ce17687ec197b755 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bd4fcb4edac9 drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12624/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h (rev5)
== Series Details == Series: drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h (rev5) URL : https://patchwork.freedesktop.org/series/58052/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h -drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h (rev5)
== Series Details == Series: drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h (rev5) URL : https://patchwork.freedesktop.org/series/58052/ State : warning == Summary == $ dim checkpatch origin/drm-tip bd4fcb4edac9 drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h -:667: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #667: new file mode 100644 -:672: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #672: FILE: drivers/gpu/drm/i915/i915_scheduler_types.h:1: +/* -:673: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #673: FILE: drivers/gpu/drm/i915/i915_scheduler_types.h:2: + * SPDX-License-Identifier: MIT -:940: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #940: FILE: drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c:1: +/* -:941: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #941: FILE: drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c:2: + * SPDX-License-Identifier: MIT total: 0 errors, 5 warnings, 0 checks, 749 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Finish the GAMMA_LUT stuff
== Series Details == Series: drm/i915: Finish the GAMMA_LUT stuff URL : https://patchwork.freedesktop.org/series/58698/ State : success == Summary == CI Bug Log - changes from CI_DRM_5832 -> Patchwork_12623 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58698/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12623 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@i915_selftest@live_evict: - fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709] * igt@i915_selftest@live_requests: - fi-icl-u2: PASS -> INCOMPLETE [fdo#109644] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> FAIL [fdo#107709] Possible fixes * igt@i915_selftest@live_uncore: - fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: FAIL [fdo#103167] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (43 -> 37) -- Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-kbl-7500u fi-kbl-r Build changes - * Linux: CI_DRM_5832 -> Patchwork_12623 CI_DRM_5832: f1fc30ad3723a8b6265c2edf50a7f637ecd75a23 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4911: d9fe699ea45406e279b78d1afdb4d57a205a3c99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12623: 49c92870dd5d4ca83f2ceb7163ef5dc3d248712a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 49c92870dd5d drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props on gen2/3 72ab741ecfe0 drm/i915: Add "10.6" LUT mode for i965+ ccc74c4fbe18 drm/i915: Add 10bit LUT for ilk/snb 45f15d269be4 drm/i915: Implement split/10bit gamma for ivb/hsw e73e007ddfdf drm/i915: Don't use split gamma when we don't have to 75a71a08c077 drm/i915: Extract ilk_lut_10() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12623/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: adding state checker for gamma lut values
On Thu, Mar 28, 2019 at 01:56:18PM -0700, Matt Roper wrote:
> On Thu, Mar 28, 2019 at 12:03:48PM +0530, Swati Sharma wrote:
> > Added state checker to validate gamma_lut values. This
> > reads hardware state, and compares the originally requested
> > state to the state read from hardware.
> >
> > v1: -Implementation done for legacy platforms (removed all the
> > placeholders) (Jani)
> > -Added inverse function of drm_color_lut_extract to convert hardware
> > read values back to user values (code written by Jani)
> > -Renamed get_config() to color_config() (Jani)
> > -Placed all platform specific shifts and masks in i915_reg.h (Jani)
> > -Renamed i9xx_get_config to i9xx_color_config and all related
> > functions (Jani)
> > -Removed debug logs from compare function (Jani)
> > -Renamed intel_compare_blob to intel_compare_lut and added platform
> > specific
> > bit precision of the readout into the function (Jani)
> > -Renamed macro PIPE_CONF_CHECK_BLOB to PIPE_CONF_CHECK_COLOR_LUT (Jani)
> > -Added check if blobs can be NULL (Jani)
> > -Added function in intel_color.c that returns the bit precision (Jani),
> > didn't add in device info since its gonna die soon (Ville)
> >
> > TODO:
> > -Add a separate function to log errors at the higher level
> > -Haven't moved intel_compare_lut() from intel_display.c to intel_color.c
> > Since all the comparison functions are placed in intel_display, isn't
> > it the right place (or) we want to move to consolidate color related
> > functions
> > together? Opinion? Please correct me if I am wrong.
> > -Optimizations and refractoring
> >
> > Signed-off-by: Swati Sharma
>
> I agree with Jani's feedback and have a couple other comments inline below.
>
> Also, since I don't see it on the TODO list here, do you intend to also
> readout and compare degamma and CTM eventually?
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 12 +++
> > drivers/gpu/drm/i915/intel_color.c | 186
> > +--
> > drivers/gpu/drm/i915/intel_display.c | 48 +
> > drivers/gpu/drm/i915/intel_drv.h | 2 +
> > 5 files changed, 243 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index c4ffe19..b422ea6 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -334,6 +334,7 @@ struct drm_i915_display_funcs {
> > * involved with the same commit.
> > */
> > void (*load_luts)(const struct intel_crtc_state *crtc_state);
> > + void (*color_config)(struct intel_crtc_state *crtc_state);
> > };
> >
> > #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index c0cd7a8..2813033 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7156,6 +7156,10 @@ enum {
> > #define _LGC_PALETTE_B 0x4a800
> > #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A,
> > _LGC_PALETTE_B) + (i) * 4)
> >
> > +#define LGC_PALETTE_RED_MASK (0xFF << 16)
> > +#define LGC_PALETTE_GREEN_MASK (0xFF << 8)
> > +#define LGC_PALETTE_BLUE_MASK (0xFF << 0)
> > +
> > #define _GAMMA_MODE_A 0x4a480
> > #define _GAMMA_MODE_B 0x4ac80
> > #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> > @@ -10102,6 +10106,10 @@ enum skl_power_gate {
> > #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
> > _PRE_CSC_GAMC_INDEX_B)
> > #define PRE_CSC_GAMC_DATA(pipe)_MMIO_PIPE(pipe,
> > _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
> >
> > +#define PREC_PAL_DATA_RED_MASK (0x3FF << 20)
> > +#define PREC_PAL_DATA_GREEN_MASK (0x3FF << 10)
> > +#define PREC_PAL_DATA_BLUE_MASK(0x3FF << 0)
> > +
> > /* pipe CSC & degamma/gamma LUTs on CHV */
> > #define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
> > #define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
> > @@ -10133,6 +10141,10 @@ enum skl_power_gate {
> > #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA,
> > _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
> > #define CGM_PIPE_MODE(pipe)_MMIO_PIPE(pipe,
> > _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
> >
> > +#define CGM_PIPE_GAMMA_RED_MASK(0x3FF << 0)
> > +#define CGM_PIPE_GAMMA_GREEN_MASK (0x3FF << 16)
> > +#define CGM_PIPE_GAMMA_BLUE_MASK (0x3FF << 0)
> > +
> > /* MIPI DSI registers */
> >
> > #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c)/*
> > ports A and C only */
> > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > b/drivers/gpu/drm/i915/intel_color.c
> > index da7a07d..bd4f1b1 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++
[Intel-gfx] [PATCH] drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h
We want to use intel_engine_mask_t inside i915_request.h, which means
extracting it from the general header file mess and placing it inside a
types.h. A knock on effect is that the compiler wants to warn about
type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare
for the worst.
v2: Use intel_engine_mask_t consistently
v3: Move I915_NUM_ENGINES to its natural home at the end of the enum
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: John Harrison
---
Now without the stray selftests/igt_gem_utils.c
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gvt/execlist.c | 11 ++-
drivers/gpu/drm/i915/gvt/execlist.h | 2 +-
drivers/gpu/drm/i915/gvt/gvt.h| 8 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 8 +-
drivers/gpu/drm/i915/gvt/scheduler.h | 6 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem.h | 2 -
drivers/gpu/drm/i915/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/i915_gem_context.h | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 9 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
drivers/gpu/drm/i915/i915_reset.c | 43
drivers/gpu/drm/i915/i915_reset.h | 9 +-
drivers/gpu/drm/i915/i915_scheduler.h | 86 +---
drivers/gpu/drm/i915/i915_scheduler_types.h | 98 +++
drivers/gpu/drm/i915/i915_timeline.h | 1 +
drivers/gpu/drm/i915/i915_timeline_types.h| 3 +-
drivers/gpu/drm/i915/intel_device_info.h | 3 +-
drivers/gpu/drm/i915/intel_engine_types.h | 12 ++-
drivers/gpu/drm/i915/intel_guc_submission.h | 1 +
drivers/gpu/drm/i915/intel_hangcheck.c| 2 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 8 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 3 +-
.../test_i915_scheduler_types_standalone.c| 7 ++
29 files changed, 192 insertions(+), 152 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_scheduler_types.h
create mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 60de05f3fa60..1f3e8b145fc0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -61,6 +61,7 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
i915-$(CONFIG_DRM_I915_WERROR) += \
test_i915_active_types_standalone.o \
test_i915_gem_context_types_standalone.o \
+ test_i915_scheduler_types_standalone.o \
test_i915_timeline_types_standalone.o \
test_intel_context_types_standalone.o \
test_intel_engine_types_standalone.o \
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c
b/drivers/gpu/drm/i915/gvt/execlist.c
index 1a93472cb34e..f21b8fb5b37e 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -526,12 +526,13 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu,
int ring_id)
vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
}
-static void clean_execlist(struct intel_vgpu *vgpu, unsigned long engine_mask)
+static void clean_execlist(struct intel_vgpu *vgpu,
+ intel_engine_mask_t engine_mask)
{
- unsigned int tmp;
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_engine_cs *engine;
struct intel_vgpu_submission *s = >submission;
+ intel_engine_mask_t tmp;
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
kfree(s->ring_scan_buffer[engine->id]);
@@ -541,18 +542,18 @@ static void clean_execlist(struct intel_vgpu *vgpu,
unsigned long engine_mask)
}
static void reset_execlist(struct intel_vgpu *vgpu,
- unsigned long engine_mask)
+ intel_engine_mask_t engine_mask)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_engine_cs *engine;
- unsigned int tmp;
+ intel_engine_mask_t tmp;
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
init_vgpu_execlist(vgpu, engine->id);
}
static int init_execlist(struct intel_vgpu *vgpu,
-unsigned long engine_mask)
+intel_engine_mask_t engine_mask)
{
reset_execlist(vgpu, engine_mask);
return 0;
diff --git a/drivers/gpu/drm/i915/gvt/execlist.h
b/drivers/gpu/drm/i915/gvt/execlist.h
index 714d709829a2..5ccc2c695848 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.h
+++ b/drivers/gpu/drm/i915/gvt/execlist.h
@@ -180,6 +180,6 @@ int intel_vgpu_init_execlist(struct intel_vgpu *vgpu);
int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int
[Intel-gfx] [PATCH] drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h
We want to use intel_engine_mask_t inside i915_request.h, which means
extracting it from the general header file mess and placing it inside a
types.h. A knock on effect is that the compiler wants to warn about
type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare
for the worst.
v2: Use intel_engine_mask_t consistently
v3: Move I915_NUM_ENGINES to its natural home at the end of the enum
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: John Harrison
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gvt/execlist.c | 11 ++-
drivers/gpu/drm/i915/gvt/execlist.h | 2 +-
drivers/gpu/drm/i915/gvt/gvt.h| 8 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 8 +-
drivers/gpu/drm/i915/gvt/scheduler.h | 6 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem.h | 2 -
drivers/gpu/drm/i915/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/i915_gem_context.h | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 9 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
drivers/gpu/drm/i915/i915_reset.c | 43
drivers/gpu/drm/i915/i915_reset.h | 9 +-
drivers/gpu/drm/i915/i915_scheduler.h | 86 +---
drivers/gpu/drm/i915/i915_scheduler_types.h | 98 +++
drivers/gpu/drm/i915/i915_timeline.h | 1 +
drivers/gpu/drm/i915/i915_timeline_types.h| 3 +-
drivers/gpu/drm/i915/intel_device_info.h | 3 +-
drivers/gpu/drm/i915/intel_engine_types.h | 12 ++-
drivers/gpu/drm/i915/intel_guc_submission.h | 1 +
drivers/gpu/drm/i915/intel_hangcheck.c| 2 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 8 +-
.../gpu/drm/i915/selftests/igt_gem_utils.c| 40
.../gpu/drm/i915/selftests/intel_hangcheck.c | 3 +-
.../test_i915_scheduler_types_standalone.c| 7 ++
30 files changed, 232 insertions(+), 152 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_scheduler_types.h
create mode 100644 drivers/gpu/drm/i915/selftests/igt_gem_utils.c
create mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 60de05f3fa60..1f3e8b145fc0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -61,6 +61,7 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
i915-$(CONFIG_DRM_I915_WERROR) += \
test_i915_active_types_standalone.o \
test_i915_gem_context_types_standalone.o \
+ test_i915_scheduler_types_standalone.o \
test_i915_timeline_types_standalone.o \
test_intel_context_types_standalone.o \
test_intel_engine_types_standalone.o \
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c
b/drivers/gpu/drm/i915/gvt/execlist.c
index 1a93472cb34e..f21b8fb5b37e 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -526,12 +526,13 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu,
int ring_id)
vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
}
-static void clean_execlist(struct intel_vgpu *vgpu, unsigned long engine_mask)
+static void clean_execlist(struct intel_vgpu *vgpu,
+ intel_engine_mask_t engine_mask)
{
- unsigned int tmp;
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_engine_cs *engine;
struct intel_vgpu_submission *s = >submission;
+ intel_engine_mask_t tmp;
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
kfree(s->ring_scan_buffer[engine->id]);
@@ -541,18 +542,18 @@ static void clean_execlist(struct intel_vgpu *vgpu,
unsigned long engine_mask)
}
static void reset_execlist(struct intel_vgpu *vgpu,
- unsigned long engine_mask)
+ intel_engine_mask_t engine_mask)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_engine_cs *engine;
- unsigned int tmp;
+ intel_engine_mask_t tmp;
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
init_vgpu_execlist(vgpu, engine->id);
}
static int init_execlist(struct intel_vgpu *vgpu,
-unsigned long engine_mask)
+intel_engine_mask_t engine_mask)
{
reset_execlist(vgpu, engine_mask);
return 0;
diff --git a/drivers/gpu/drm/i915/gvt/execlist.h
b/drivers/gpu/drm/i915/gvt/execlist.h
index 714d709829a2..5ccc2c695848 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.h
+++ b/drivers/gpu/drm/i915/gvt/execlist.h
@@ -180,6 +180,6 @@ int intel_vgpu_init_execlist(struct
[Intel-gfx] [PATCH 4/6] drm/i915: Add 10bit LUT for ilk/snb
From: Ville Syrjälä
Plop in support for 10bit LUT on ilk/snb.
There is no split gamma mode on these platforms, so we have
to choose between degamma and gamma. That could be a runtime choice
but for now let's just advertize the gamma as having 1024 entries.
We'll also keep the ctm hidden for now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c| 4 +++
drivers/gpu/drm/i915/i915_reg.h| 9 ++
drivers/gpu/drm/i915/intel_color.c | 44 ++
3 files changed, 51 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 385056752939..0971eee4a4d1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -116,6 +116,8 @@
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
}
+#define ILK_COLORS \
+ .color = { .gamma_lut_size = 1024 }
#define IVB_COLORS \
.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
#define CHV_COLORS \
@@ -325,6 +327,7 @@ static const struct intel_device_info intel_gm45_info = {
.has_rc6 = 0, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
+ ILK_COLORS, \
GEN_DEFAULT_PAGE_SIZES
static const struct intel_device_info intel_ironlake_d_info = {
@@ -353,6 +356,7 @@ static const struct intel_device_info intel_ironlake_m_info
= {
.ppgtt_size = 31, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
+ ILK_COLORS, \
GEN_DEFAULT_PAGE_SIZES
#define SNB_D_PLATFORM \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eb7e93354cfe..f6a5d8f11368 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7209,6 +7209,15 @@ enum {
#define _LGC_PALETTE_B 0x4a800
#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
+ (i) * 4)
+/* ilk/snb precision palette */
+#define _PREC_PALETTE_A 0x4b000
+#define _PREC_PALETTE_B 0x4c000
+#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A,
_PREC_PALETTE_B) + (i) * 4)
+
+#define _PREC_PIPEAGCMAX 0x4d000
+#define _PREC_PIPEBGCMAX 0x4d010
+#define PREC_PIPEGCMAX(pipe, i)_MMIO(_PIPE(pipe, _PIPEAGCMAX,
_PIPEBGCMAX) + (i) * 4)
+
#define _GAMMA_MODE_A 0x4a480
#define _GAMMA_MODE_B 0x4ac80
#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 70a71c92e3e5..8e03f066adf7 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -468,6 +468,29 @@ static void skl_color_commit(const struct intel_crtc_state
*crtc_state)
ilk_load_csc_matrix(crtc_state);
}
+static void ilk_load_lut_10(struct intel_crtc *crtc,
+ const struct drm_property_blob *blob)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_color_lut *lut = blob->data;
+ int i, lut_size = drm_color_lut_size(blob);
+ enum pipe pipe = crtc->pipe;
+
+ for (i = 0; i < lut_size; i++)
+ I915_WRITE_FW(PREC_PALETTE(pipe, i), ilk_lut_10([i]));
+}
+
+static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ i9xx_load_luts(crtc_state);
+ else
+ ilk_load_lut_10(crtc, gamma_lut);
+}
+
/*
* IVB/HSW Bspec / PAL_PREC_INDEX:
* "Restriction : Index auto increment mode is not
@@ -961,6 +984,15 @@ static int chv_color_check(struct intel_crtc_state
*crtc_state)
return 0;
}
+static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->gamma_enable ||
+ crtc_state_is_legacy_gamma(crtc_state))
+ return GAMMA_MODE_MODE_8BIT;
+ else
+ return GAMMA_MODE_MODE_10BIT;
+}
+
static int ilk_color_check(struct intel_crtc_state *crtc_state)
{
int ret;
@@ -980,8 +1012,7 @@ static int ilk_color_check(struct intel_crtc_state
*crtc_state)
*/
crtc_state->csc_enable = false;
- /* We don't expose fancy gamma modes on ilk/snb currently */
- crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
+ crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
crtc_state->csc_mode = 0;
@@ -1178,14 +1209,15 @@ void intel_color_init(struct intel_crtc *crtc)
else if (INTEL_GEN(dev_priv) >= 7)
dev_priv->display.load_luts = ivb_load_luts;
else
- dev_priv->display.load_luts = i9xx_load_luts;
+ dev_priv->display.load_luts = ilk_load_luts;
}
- /* Enable color management
[Intel-gfx] [PATCH 5/6] drm/i915: Add "10.6" LUT mode for i965+
From: Ville Syrjälä
i965+ have an interpolate 10bit LUT mode. Let's expose that so
that we can actually enjoy real 10bpc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c| 6 +++
drivers/gpu/drm/i915/i915_reg.h| 4 ++
drivers/gpu/drm/i915/intel_color.c | 62 +-
3 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0971eee4a4d1..0c5258aa13bb 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -116,6 +116,10 @@
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
}
+#define I965_COLORS \
+ .color = { .gamma_lut_size = 129, \
+ .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+ }
#define ILK_COLORS \
.color = { .gamma_lut_size = 1024 }
#define IVB_COLORS \
@@ -278,6 +282,7 @@ static const struct intel_device_info intel_pineview_info =
{
.has_coherent_ggtt = true, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
+ I965_COLORS, \
GEN_DEFAULT_PAGE_SIZES
static const struct intel_device_info intel_i965g_info = {
@@ -462,6 +467,7 @@ static const struct intel_device_info intel_valleyview_info
= {
.display_mmio_offset = VLV_DISPLAY_BASE,
I9XX_PIPE_OFFSETS,
I9XX_CURSOR_OFFSETS,
+ I965_COLORS,
GEN_DEFAULT_PAGE_SIZES,
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6a5d8f11368..0437a3ab6cdc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5795,6 +5795,10 @@ enum {
#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
+#define _PIPEAGCMAX 0x70010
+#define _PIPEBGCMAX 0x71010
+#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
+
#define _PIPE_MISC_A 0x70030
#define _PIPE_MISC_B 0x71030
#define PIPEMISC_YUV420_ENABLE (1 << 27)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 8e03f066adf7..07d62c7cb386 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -359,6 +359,22 @@ static void cherryview_load_csc_matrix(const struct
intel_crtc_state *crtc_state
I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
}
+/* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
+static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
+{
+ return (color->red & 0xff) << 16 |
+ (color->green & 0xff) << 8 |
+ (color->blue & 0xff);
+}
+
+/* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */
+static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
+{
+ return (color->red >> 8) << 16 |
+ (color->green >> 8) << 8 |
+ (color->blue >> 8);
+}
+
static u32 ilk_lut_10(const struct drm_color_lut *color)
{
return drm_color_lut_extract(color->red, 10) << 20 |
@@ -468,6 +484,37 @@ static void skl_color_commit(const struct intel_crtc_state
*crtc_state)
ilk_load_csc_matrix(crtc_state);
}
+static void i965_load_lut_10p6(struct intel_crtc *crtc,
+ const struct drm_property_blob *blob)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_color_lut *lut = blob->data;
+ int i, lut_size = drm_color_lut_size(blob);
+ enum pipe pipe = crtc->pipe;
+
+ for (i = 0; i < lut_size - 1; i++) {
+ I915_WRITE_FW(PALETTE(pipe, 2 * i + 0),
+ i965_lut_10p6_ldw([i]));
+ I915_WRITE_FW(PALETTE(pipe, 2 * i + 1),
+ i965_lut_10p6_udw([i]));
+ }
+
+ I915_WRITE_FW(PIPEGCMAX(pipe, 0), lut[i].red);
+ I915_WRITE_FW(PIPEGCMAX(pipe, 1), lut[i].green);
+ I915_WRITE_FW(PIPEGCMAX(pipe, 2), lut[i].blue);
+}
+
+static void i965_load_luts(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ i9xx_load_luts(crtc_state);
+ else
+ i965_load_lut_10p6(crtc, gamma_lut);
+}
+
static void ilk_load_lut_10(struct intel_crtc *crtc,
const struct drm_property_blob *blob)
{
@@ -911,6 +958,15 @@ static int check_luts(const struct intel_crtc_state
*crtc_state)
return 0;
}
+static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->gamma_enable ||
+ crtc_state_is_legacy_gamma(crtc_state))
+ return GAMMA_MODE_MODE_8BIT;
+ else
+ return GAMMA_MODE_MODE_10BIT; /* i965+ only */
+}
+
static int
[Intel-gfx] [PATCH 6/6] drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props on gen2/3
From: Ville Syrjälä
Just so we don't leave gen2/3 out in the cold let's advertize the
legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props. Without the
GAMMA_LUT prop we can't actually load a LUT using the atomic ioctl
(in preparation for the day of 100% atomic driver).
Supposedly some gen2/3 platforms have an interpolated 10bit gamma mode
as well. It's slightly funkier than the i965+ mode since you have to
specify the slope for the interpolation by hand. But when I tried it
I couldn't get it to work, the hardware just insisted on using the
8bit more regardless of the state of the relevant PIPECONF bit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c| 5 +
drivers/gpu/drm/i915/intel_color.c | 13 +
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0c5258aa13bb..0e76df27f151 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -116,6 +116,8 @@
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
}
+#define I9XX_COLORS \
+ .color = { .gamma_lut_size = 256 }
#define I965_COLORS \
.color = { .gamma_lut_size = 129, \
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
@@ -156,6 +158,7 @@
.has_coherent_ggtt = false, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
+ I9XX_COLORS, \
GEN_DEFAULT_PAGE_SIZES
#define I845_FEATURES \
@@ -172,6 +175,7 @@
.has_coherent_ggtt = false, \
I845_PIPE_OFFSETS, \
I845_CURSOR_OFFSETS, \
+ I9XX_COLORS, \
GEN_DEFAULT_PAGE_SIZES
static const struct intel_device_info intel_i830_info = {
@@ -205,6 +209,7 @@ static const struct intel_device_info intel_i865g_info = {
.has_coherent_ggtt = true, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
+ I9XX_COLORS, \
GEN_DEFAULT_PAGE_SIZES
static const struct intel_device_info intel_i915g_info = {
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 07d62c7cb386..fd4a65af5cc4 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1272,12 +1272,9 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.load_luts = ilk_load_luts;
}
- /* Enable color management support when we have degamma and/or gamma
LUT. */
- if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 ||
- INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
- drm_crtc_enable_color_mgmt(>base,
-
INTEL_INFO(dev_priv)->color.degamma_lut_size,
-
INTEL_INFO(dev_priv)->color.degamma_lut_size &&
-
INTEL_INFO(dev_priv)->color.gamma_lut_size,
-
INTEL_INFO(dev_priv)->color.gamma_lut_size);
+ drm_crtc_enable_color_mgmt(>base,
+ INTEL_INFO(dev_priv)->color.degamma_lut_size,
+ INTEL_INFO(dev_priv)->color.degamma_lut_size
&&
+ INTEL_INFO(dev_priv)->color.gamma_lut_size,
+ INTEL_INFO(dev_priv)->color.gamma_lut_size);
}
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm/i915: Implement split/10bit gamma for ivb/hsw
From: Ville Syrjälä
Reuse the bdw+ code to get split/10bit gamma for
ivb/hsw. The hardware is nearly identical. The
only slight snag is that on ivb/hsw the precision
palette auto increment mode does not work. So we
must increment the index manually. We'll probably
want to stick to the auto increment mode on bdw+
in the name of efficiency.
Also we want to avoid using the CSC for limited range
RGB output as PIPECONF will take care of that on IVB.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c| 6 +-
drivers/gpu/drm/i915/intel_color.c | 113 +++--
2 files changed, 95 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a7e1611af26d..385056752939 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -116,7 +116,7 @@
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
}
-#define BDW_COLORS \
+#define IVB_COLORS \
.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
#define CHV_COLORS \
.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
@@ -399,6 +399,7 @@ static const struct intel_device_info
intel_sandybridge_m_gt2_info = {
.ppgtt_size = 31, \
IVB_PIPE_OFFSETS, \
IVB_CURSOR_OFFSETS, \
+ IVB_COLORS, \
GEN_DEFAULT_PAGE_SIZES
#define IVB_D_PLATFORM \
@@ -494,7 +495,6 @@ static const struct intel_device_info
intel_haswell_gt3_info = {
#define GEN8_FEATURES \
G75_FEATURES, \
GEN(8), \
- BDW_COLORS, \
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
@@ -629,7 +629,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
.display.has_ipc = 1, \
HSW_PIPE_OFFSETS, \
IVB_CURSOR_OFFSETS, \
- BDW_COLORS, \
+ IVB_COLORS, \
GEN9_DEFAULT_PAGE_SIZES
static const struct intel_device_info intel_broxton_info = {
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index ed4bd9bd15f5..70a71c92e3e5 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -428,6 +428,8 @@ static void ilk_color_commit(const struct intel_crtc_state
*crtc_state)
val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
I915_WRITE(PIPECONF(pipe), val);
+
+ ilk_load_csc_matrix(crtc_state);
}
static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
@@ -466,6 +468,48 @@ static void skl_color_commit(const struct intel_crtc_state
*crtc_state)
ilk_load_csc_matrix(crtc_state);
}
+/*
+ * IVB/HSW Bspec / PAL_PREC_INDEX:
+ * "Restriction : Index auto increment mode is not
+ * supported and must not be enabled."
+ */
+static void ivb_load_lut_10(struct intel_crtc *crtc,
+ const struct drm_property_blob *blob,
+ u32 prec_index, bool duplicate)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_color_lut *lut = blob->data;
+ int i, lut_size = drm_color_lut_size(blob);
+ enum pipe pipe = crtc->pipe;
+
+ /*
+* We advertize the split gamma sizes. When not using split
+* gamma we just duplicate each entry.
+*
+* TODO: expose the full LUT to userspace
+*/
+ if (duplicate) {
+ for (i = 0; i < lut_size; i++) {
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
+ }
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
+ }
+ }
+
+ /*
+* Reset the index, otherwise it prevents the legacy palette to be
+* written properly.
+*/
+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+}
+
+/* On BDW+ the index auto increment mode actually works */
static void bdw_load_lut_10(struct intel_crtc *crtc,
const struct drm_property_blob *blob,
u32 prec_index, bool duplicate)
@@ -501,7 +545,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}
-static void bdw_load_lut_10_max(struct intel_crtc *crtc,
+static void ivb_load_lut_10_max(struct intel_crtc *crtc,
const struct drm_property_blob *blob)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -518,6 +562,29 @@ static void bdw_load_lut_10_max(struct intel_crtc *crtc,
[Intel-gfx] [PATCH 0/6] drm/i915: Finish the GAMMA_LUT stuff
From: Ville Syrjälä This series exposes the GAMMA_LUT/GAMMA_LUT_SIZE props on all platforms, finally getting us back to some kind of uniformity. On i965+ we also gain the ability to gamma correct 10bpc data without crusing it to 8bpc with the legacy LUT. To go beyond this we'll need the new uapi to expose different gamma modes so that userspace can make the best use of the available hardware. We'll get to that later. One thing we still need to do is deal with the current bugs relating to the overloaded use of the pipe CSC for YCbCr and limited range RGB output. This series already removes some of those bugs on BDW+, and we can probably eliminate a bit more if we start to frob the gamma LUT to do the limited range compression. I've not decided what we're going to do with GLK however. It has sadly lost the flexibility we desperately need. Ville Syrjälä (6): drm/i915: Extract ilk_lut_10() drm/i915: Don't use split gamma when we don't have to drm/i915: Implement split/10bit gamma for ivb/hsw drm/i915: Add 10bit LUT for ilk/snb drm/i915: Add "10.6" LUT mode for i965+ drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props on gen2/3 drivers/gpu/drm/i915/i915_pci.c| 21 +- drivers/gpu/drm/i915/i915_reg.h| 14 ++ drivers/gpu/drm/i915/intel_color.c | 353 + 3 files changed, 292 insertions(+), 96 deletions(-) -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/6] drm/i915: Don't use split gamma when we don't have to
From: Ville Syrjälä
Using the split gamma mode when we don't have to has the annoying
requirement of loading a linear LUT to the unused half. Instead
let's make life simpler by switching to the 10bit gamma mode
and duplicating each entry.
This also allows us to load the software gamma LUT into the
hardware degamma LUT, thus removing some of the buggy
configurations we currently allow (YCbCr/limited range RGB
+ gamma LUT). We do still have other configurations that are
also buggy, but those will need more complicated fixes
or they just need to be rejected. Sadly GLK doesn't have
this flexibility anymore and the degamma and gamma LUTs
are very different so no help there.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 159 +++--
2 files changed, 86 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c866379a521b..eb7e93354cfe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10127,6 +10127,7 @@ enum skl_power_gate {
#define PAL_PREC_SPLIT_MODE (1 << 31)
#define PAL_PREC_AUTO_INCREMENT (1 << 15)
#define PAL_PREC_INDEX_VALUE_MASK(0x3ff << 0)
+#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
#define _PAL_PREC_DATA_A 0x4A404
#define _PAL_PREC_DATA_B 0x4AC04
#define _PAL_PREC_DATA_C 0x4B404
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index d7c38a2bbd8f..ed4bd9bd15f5 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -466,72 +466,32 @@ static void skl_color_commit(const struct
intel_crtc_state *crtc_state)
ilk_load_csc_matrix(crtc_state);
}
-static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
+static void bdw_load_lut_10(struct intel_crtc *crtc,
+ const struct drm_property_blob *blob,
+ u32 prec_index, bool duplicate)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_property_blob *degamma_lut =
crtc_state->base.degamma_lut;
- u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+ const struct drm_color_lut *lut = blob->data;
+ int i, lut_size = drm_color_lut_size(blob);
enum pipe pipe = crtc->pipe;
- I915_WRITE(PREC_PAL_INDEX(pipe),
- PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
-
- if (degamma_lut) {
- const struct drm_color_lut *lut = degamma_lut->data;
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
+ PAL_PREC_AUTO_INCREMENT);
- for (i = 0; i < lut_size; i++)
- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
- } else {
+ /*
+* We advertize the split gamma sizes. When not using split
+* gamma we just duplicate each entry.
+*
+* TODO: expose the full LUT to userspace
+*/
+ if (duplicate) {
for (i = 0; i < lut_size; i++) {
- u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
-
- I915_WRITE(PREC_PAL_DATA(pipe),
- (v << 20) | (v << 10) | v);
+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
}
- }
-}
-
-static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32
offset)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
- u32 i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
- enum pipe pipe = crtc->pipe;
-
- WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
-
- I915_WRITE(PREC_PAL_INDEX(pipe),
- (offset ? PAL_PREC_SPLIT_MODE : 0) |
- PAL_PREC_AUTO_INCREMENT |
- offset);
-
- if (gamma_lut) {
- const struct drm_color_lut *lut = gamma_lut->data;
-
+ } else {
for (i = 0; i < lut_size; i++)
I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
-
- /* Program the max register to clamp values > 1.0. */
- i = lut_size - 1;
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
- drm_color_lut_extract(lut[i].red, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
- drm_color_lut_extract(lut[i].green, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
- drm_color_lut_extract(lut[i].blue, 16));
- } else {
- for (i = 0; i
[Intel-gfx] [PATCH 1/6] drm/i915: Extract ilk_lut_10()
From: Ville Syrjälä
Extract a helper to calculate the ILK+ 10it gamma LUT entry.
It's already duplicated twice, and soon we'll have more.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 27 +++
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index ff910ed08468..d7c38a2bbd8f 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -359,6 +359,13 @@ static void cherryview_load_csc_matrix(const struct
intel_crtc_state *crtc_state
I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
}
+static u32 ilk_lut_10(const struct drm_color_lut *color)
+{
+ return drm_color_lut_extract(color->red, 10) << 20 |
+ drm_color_lut_extract(color->green, 10) << 10 |
+ drm_color_lut_extract(color->blue, 10);
+}
+
/* Loads the legacy palette/gamma unit for the CRTC. */
static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
const struct drm_property_blob *blob)
@@ -473,14 +480,8 @@ static void bdw_load_degamma_lut(const struct
intel_crtc_state *crtc_state)
if (degamma_lut) {
const struct drm_color_lut *lut = degamma_lut->data;
- for (i = 0; i < lut_size; i++) {
- u32 word =
- drm_color_lut_extract(lut[i].red, 10) << 20 |
- drm_color_lut_extract(lut[i].green, 10) << 10 |
- drm_color_lut_extract(lut[i].blue, 10);
-
- I915_WRITE(PREC_PAL_DATA(pipe), word);
- }
+ for (i = 0; i < lut_size; i++)
+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
} else {
for (i = 0; i < lut_size; i++) {
u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -509,14 +510,8 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
if (gamma_lut) {
const struct drm_color_lut *lut = gamma_lut->data;
- for (i = 0; i < lut_size; i++) {
- u32 word =
- (drm_color_lut_extract(lut[i].red, 10) << 20) |
- (drm_color_lut_extract(lut[i].green, 10) << 10) |
- drm_color_lut_extract(lut[i].blue, 10);
-
- I915_WRITE(PREC_PAL_DATA(pipe), word);
- }
+ for (i = 0; i < lut_size; i++)
+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10([i]));
/* Program the max register to clamp values > 1.0. */
i = lut_size - 1;
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RESEND PULL] drm-misc-next
On Thu, Mar 28, 2019 at 09:59:12PM +0100, Daniel Vetter wrote:
> On Thu, Mar 28, 2019 at 7:30 PM Sean Paul wrote:
> >
> >
> > Hi Da.*,
> > Here's the resend with the !CONFIG_FBDEV fix. I'll be sure to update my
> > build
> > scripts to get a bit more variety in them, hopefully catch something like
> > this
> > before it gets sent out.
>
> I really want to get this all sorted out with gitlab CI, but Daniel
> Stone still says he can't have big kernel repos because it'd take down
> fd.o. And the upstream rework doesn't look like it'll happen anytime
> soon :-/
I feel like !CONFIG_FBDEV is something that has bit us multiple times already,
so I'm kind of surprised I didn't have it covered.
It'd be soo nice to have a centralized builder doing the things that we all
think we're doing locally :)
Sean
> -Daniel
>
> >
> >
> > drm-misc-next-2019-03-28-1:
> > drm-misc-next for 5.2:
> >
> > UAPI Changes:
> > - None
> >
> > Cross-subsystem Changes:
> > - None
> >
> > Core Changes:
> > - Fix compilation when CONFIG_FBDEV not selected (Daniel)
> >
> > Driver Changes:
> > - virtio: package function args in virtio_gpu_object_params (Gerd)
> >
> > Cc: Daniel Vetter
> > Cc: Gerd Hoffmann
> >
> > drm-misc-next-2019-03-28:
> > drm-misc-next for 5.2:
> >
> > UAPI Changes:
> > - Remove unused DRM_DISPLAY_INFO_LEN (Ville)
> >
> > Cross-subsystem Changes:
> > - None
> >
> > Core Changes:
> > - fbdev: Make skip_vt_switch default (Daniel)
> > - Merge fb_helper_fill_fix, fb_helper_fill_var into fb_helper_fill_info
> > (Daniel)
> > - Remove unused fields in connector, display_info, and edid_quirks (Ville)
> >
> > Driver Changes:
> > - vkms: Fix potential NULL-dereference bug (Kangjie)
> >
> > Cc: Kangjie Lu
> > Cc: Daniel Vetter
> > Cc: Ville Syrjälä
> >
> > Cheers, Sean
> >
> >
> > The following changes since commit ff01e6971ecd9ba6a9c0538c46d713f38a751f11:
> >
> > drm/fourcc: Fix conflicting Y41x definitions (2019-03-21 09:49:04 +0100)
> >
> > are available in the Git repository at:
> >
> > git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-03-28-1
> >
> > for you to fetch changes up to 530b28426a94b822b3c03491cde5c9a961d80e7f:
> >
> > drm/virtio: rework resource creation workflow. (2019-03-28 12:11:56 +0100)
> >
> >
> > drm-misc-next for 5.2:
> >
> > UAPI Changes:
> > - None
> >
> > Cross-subsystem Changes:
> > - None
> >
> > Core Changes:
> > - Fix compilation when CONFIG_FBDEV not selected (Daniel)
> >
> > Driver Changes:
> > - virtio: package function args in virtio_gpu_object_params (Gerd)
> >
> > Cc: Daniel Vetter
> > Cc: Gerd Hoffmann
> >
> >
> > Daniel Vetter (25):
> > drm/hibmc: Drop best_encoder
> > drm/doc: Drop "content type" from the legacy kms property table
> > drm/fbdev: Make skip_vt_switch the default
> > drm/fb-helper: Add fill_info() functions
> > drm/fb-helper: set fbi->fix.id in fill_info()
> > drm/fb_helper: set info->par in fill_info()
> > drm/amdgpu: Use drm_fb_helper_fill_info
> > drm/armada: Use drm_fb_helper_fill_info
> > drm/ast: Use drm_fb_helper_fill_info
> > drm/cirrus: Use drm_fb_helper_fill_info
> > drm/exynos: Use drm_fb_helper_fill_info
> > drm/gma500: Use drm_fb_helper_fill_info
> > drm/hibmc: Use drm_fb_helper_fill_info
> > drm/i915: Use drm_fb_helper_fill_info
> > drm/mga200g: Use drm_fb_helper_fill_info
> > drm/msm: Use drm_fb_helper_fill_info
> > drm/nouveau: Use drm_fb_helper_fill_info
> > drm/omap: Use drm_fb_helper_fill_info
> > drm/radeon: Use drm_fb_helper_fill_info
> > drm/rockchip: Use drm_fb_helper_fill_info
> > drm/tegra: Use drm_fb_helper_fill_info
> > drm/vboxvideo: Use drm_fb_helper_fill_info
> > drm/udl: Use drm_fb_helper_fill_info
> > drm/fb-helper: Unexport fill_{var,info}
> > drm/fb-helper: Fixup fill_info cleanup
> >
> > Gerd Hoffmann (6):
> > drm/virtio: add virtio-gpu-features debugfs file.
> > drm/virtio: move virtio_gpu_object_{attach, detach} calls.
> > drm/virtio: use struct to pass params to virtio_gpu_object_create()
> > drm/virtio: params struct for virtio_gpu_cmd_create_resource()
> > drm/virtio: params struct for virtio_gpu_cmd_create_resource_3d()
> > drm/virtio: rework resource creation workflow.
> >
> > Kangjie Lu (1):
> > drm: vkms: check status of alloc_ordered_workqueue
> >
> > Luca Ceresoli (1):
> > drm/doc: fix missing verb
> >
> > Ville Syrjälä (5):
> > drm: Nuke unused drm_display_info.pixel_clock
> > drm: Fix tabs vs. spaces
> > drm: Kill drm_display_info.name
> > drm/uapi: Remove unused DRM_DISPLAY_INFO_LEN
> > drm/edid: Remove defunct EDID_QUIRK_FIRST_DETAILED_PREFERRED
> >
> > YueHaibing (1):
> > drm/virtio: remove set but not used variable 'vgdev'
> >
> >
Re: [Intel-gfx] [RESEND PULL] drm-misc-next
On Thu, Mar 28, 2019 at 7:30 PM Sean Paul wrote:
>
>
> Hi Da.*,
> Here's the resend with the !CONFIG_FBDEV fix. I'll be sure to update my build
> scripts to get a bit more variety in them, hopefully catch something like this
> before it gets sent out.
I really want to get this all sorted out with gitlab CI, but Daniel
Stone still says he can't have big kernel repos because it'd take down
fd.o. And the upstream rework doesn't look like it'll happen anytime
soon :-/
-Daniel
>
>
> drm-misc-next-2019-03-28-1:
> drm-misc-next for 5.2:
>
> UAPI Changes:
> - None
>
> Cross-subsystem Changes:
> - None
>
> Core Changes:
> - Fix compilation when CONFIG_FBDEV not selected (Daniel)
>
> Driver Changes:
> - virtio: package function args in virtio_gpu_object_params (Gerd)
>
> Cc: Daniel Vetter
> Cc: Gerd Hoffmann
>
> drm-misc-next-2019-03-28:
> drm-misc-next for 5.2:
>
> UAPI Changes:
> - Remove unused DRM_DISPLAY_INFO_LEN (Ville)
>
> Cross-subsystem Changes:
> - None
>
> Core Changes:
> - fbdev: Make skip_vt_switch default (Daniel)
> - Merge fb_helper_fill_fix, fb_helper_fill_var into fb_helper_fill_info
> (Daniel)
> - Remove unused fields in connector, display_info, and edid_quirks (Ville)
>
> Driver Changes:
> - vkms: Fix potential NULL-dereference bug (Kangjie)
>
> Cc: Kangjie Lu
> Cc: Daniel Vetter
> Cc: Ville Syrjälä
>
> Cheers, Sean
>
>
> The following changes since commit ff01e6971ecd9ba6a9c0538c46d713f38a751f11:
>
> drm/fourcc: Fix conflicting Y41x definitions (2019-03-21 09:49:04 +0100)
>
> are available in the Git repository at:
>
> git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-03-28-1
>
> for you to fetch changes up to 530b28426a94b822b3c03491cde5c9a961d80e7f:
>
> drm/virtio: rework resource creation workflow. (2019-03-28 12:11:56 +0100)
>
>
> drm-misc-next for 5.2:
>
> UAPI Changes:
> - None
>
> Cross-subsystem Changes:
> - None
>
> Core Changes:
> - Fix compilation when CONFIG_FBDEV not selected (Daniel)
>
> Driver Changes:
> - virtio: package function args in virtio_gpu_object_params (Gerd)
>
> Cc: Daniel Vetter
> Cc: Gerd Hoffmann
>
>
> Daniel Vetter (25):
> drm/hibmc: Drop best_encoder
> drm/doc: Drop "content type" from the legacy kms property table
> drm/fbdev: Make skip_vt_switch the default
> drm/fb-helper: Add fill_info() functions
> drm/fb-helper: set fbi->fix.id in fill_info()
> drm/fb_helper: set info->par in fill_info()
> drm/amdgpu: Use drm_fb_helper_fill_info
> drm/armada: Use drm_fb_helper_fill_info
> drm/ast: Use drm_fb_helper_fill_info
> drm/cirrus: Use drm_fb_helper_fill_info
> drm/exynos: Use drm_fb_helper_fill_info
> drm/gma500: Use drm_fb_helper_fill_info
> drm/hibmc: Use drm_fb_helper_fill_info
> drm/i915: Use drm_fb_helper_fill_info
> drm/mga200g: Use drm_fb_helper_fill_info
> drm/msm: Use drm_fb_helper_fill_info
> drm/nouveau: Use drm_fb_helper_fill_info
> drm/omap: Use drm_fb_helper_fill_info
> drm/radeon: Use drm_fb_helper_fill_info
> drm/rockchip: Use drm_fb_helper_fill_info
> drm/tegra: Use drm_fb_helper_fill_info
> drm/vboxvideo: Use drm_fb_helper_fill_info
> drm/udl: Use drm_fb_helper_fill_info
> drm/fb-helper: Unexport fill_{var,info}
> drm/fb-helper: Fixup fill_info cleanup
>
> Gerd Hoffmann (6):
> drm/virtio: add virtio-gpu-features debugfs file.
> drm/virtio: move virtio_gpu_object_{attach, detach} calls.
> drm/virtio: use struct to pass params to virtio_gpu_object_create()
> drm/virtio: params struct for virtio_gpu_cmd_create_resource()
> drm/virtio: params struct for virtio_gpu_cmd_create_resource_3d()
> drm/virtio: rework resource creation workflow.
>
> Kangjie Lu (1):
> drm: vkms: check status of alloc_ordered_workqueue
>
> Luca Ceresoli (1):
> drm/doc: fix missing verb
>
> Ville Syrjälä (5):
> drm: Nuke unused drm_display_info.pixel_clock
> drm: Fix tabs vs. spaces
> drm: Kill drm_display_info.name
> drm/uapi: Remove unused DRM_DISPLAY_INFO_LEN
> drm/edid: Remove defunct EDID_QUIRK_FIRST_DETAILED_PREFERRED
>
> YueHaibing (1):
> drm/virtio: remove set but not used variable 'vgdev'
>
> Documentation/gpu/kms-properties.csv | 1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 25 ++---
> drivers/gpu/drm/armada/armada_fbdev.c | 6 +-
> drivers/gpu/drm/ast/ast_drv.h | 2 +-
> drivers/gpu/drm/ast/ast_fb.c | 7 +-
> drivers/gpu/drm/cirrus/cirrus_drv.h| 2 +-
> drivers/gpu/drm/cirrus/cirrus_fbdev.c | 8 +-
> drivers/gpu/drm/drm_edid.c | 10 --
> drivers/gpu/drm/drm_fb_helper.c| 80 ---
>
Re: [Intel-gfx] [PATCH] drm/i915: adding state checker for gamma lut values
On Thu, Mar 28, 2019 at 12:03:48PM +0530, Swati Sharma wrote:
> Added state checker to validate gamma_lut values. This
> reads hardware state, and compares the originally requested
> state to the state read from hardware.
>
> v1: -Implementation done for legacy platforms (removed all the placeholders)
> (Jani)
> -Added inverse function of drm_color_lut_extract to convert hardware
> read values back to user values (code written by Jani)
> -Renamed get_config() to color_config() (Jani)
> -Placed all platform specific shifts and masks in i915_reg.h (Jani)
> -Renamed i9xx_get_config to i9xx_color_config and all related
> functions (Jani)
> -Removed debug logs from compare function (Jani)
> -Renamed intel_compare_blob to intel_compare_lut and added platform
> specific
> bit precision of the readout into the function (Jani)
> -Renamed macro PIPE_CONF_CHECK_BLOB to PIPE_CONF_CHECK_COLOR_LUT (Jani)
> -Added check if blobs can be NULL (Jani)
> -Added function in intel_color.c that returns the bit precision (Jani),
> didn't add in device info since its gonna die soon (Ville)
>
> TODO:
> -Add a separate function to log errors at the higher level
> -Haven't moved intel_compare_lut() from intel_display.c to intel_color.c
> Since all the comparison functions are placed in intel_display, isn't
> it the right place (or) we want to move to consolidate color related
> functions
> together? Opinion? Please correct me if I am wrong.
> -Optimizations and refractoring
>
> Signed-off-by: Swati Sharma
I agree with Jani's feedback and have a couple other comments inline below.
Also, since I don't see it on the TODO list here, do you intend to also
readout and compare degamma and CTM eventually?
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 12 +++
> drivers/gpu/drm/i915/intel_color.c | 186
> +--
> drivers/gpu/drm/i915/intel_display.c | 48 +
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 5 files changed, 243 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c4ffe19..b422ea6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -334,6 +334,7 @@ struct drm_i915_display_funcs {
>* involved with the same commit.
>*/
> void (*load_luts)(const struct intel_crtc_state *crtc_state);
> + void (*color_config)(struct intel_crtc_state *crtc_state);
> };
>
> #define CSR_VERSION(major, minor)((major) << 16 | (minor))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c0cd7a8..2813033 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7156,6 +7156,10 @@ enum {
> #define _LGC_PALETTE_B 0x4a800
> #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A,
> _LGC_PALETTE_B) + (i) * 4)
>
> +#define LGC_PALETTE_RED_MASK (0xFF << 16)
> +#define LGC_PALETTE_GREEN_MASK (0xFF << 8)
> +#define LGC_PALETTE_BLUE_MASK(0xFF << 0)
> +
> #define _GAMMA_MODE_A0x4a480
> #define _GAMMA_MODE_B0x4ac80
> #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> @@ -10102,6 +10106,10 @@ enum skl_power_gate {
> #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
> _PRE_CSC_GAMC_INDEX_B)
> #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe,
> _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
>
> +#define PREC_PAL_DATA_RED_MASK (0x3FF << 20)
> +#define PREC_PAL_DATA_GREEN_MASK (0x3FF << 10)
> +#define PREC_PAL_DATA_BLUE_MASK (0x3FF << 0)
> +
> /* pipe CSC & degamma/gamma LUTs on CHV */
> #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
> @@ -10133,6 +10141,10 @@ enum skl_power_gate {
> #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA,
> _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
> #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE,
> _CGM_PIPE_B_MODE)
>
> +#define CGM_PIPE_GAMMA_RED_MASK (0x3FF << 0)
> +#define CGM_PIPE_GAMMA_GREEN_MASK(0x3FF << 16)
> +#define CGM_PIPE_GAMMA_BLUE_MASK (0x3FF << 0)
> +
> /* MIPI DSI registers */
>
> #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c)/*
> ports A and C only */
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index da7a07d..bd4f1b1 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -679,6 +679,172 @@ void intel_color_load_luts(const struct
> intel_crtc_state *crtc_state)
> dev_priv->display.load_luts(crtc_state);
> }
>
> +u32 intel_color_bit_precision(struct drm_i915_private *dev_priv)
> +{
> +
Re: [Intel-gfx] [PATCH] drm/i915: move the edram detection out of uncore init
Quoting Daniele Ceraolo Spurio (2019-03-28 17:45:32) > edram is not part of uncore and there is no requirement for the > detection to be done before we initialize the uncore functions. The > first check on HAS_EDRAM is in the ggtt_init path, so move it to > i915_driver_init_hw, where other dram-related detection happens. > > While at it, save the size in MB instead of the capabilities because the > size is the only thing we look at outside of the init function. > > Signed-off-by: Daniele Ceraolo Spurio > Cc: Paulo Zanoni > Cc: Chris Wilson I'm devoid of good suggestions as to where better to place it. Certainly we don't want it in i915_drv.c, maybe intel_cache_topology.c. Anyway, that doesn't detract from the merits of this patch, Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Add Plane Color Properties (rev7)
== Series Details == Series: Add Plane Color Properties (rev7) URL : https://patchwork.freedesktop.org/series/30875/ State : failure == Summary == Applying: drm: Add Enhanced Gamma LUT precision structure Applying: drm: Add Plane Degamma properties Applying: drm: Add Plane CTM property Applying: drm: Add Plane Gamma properties Applying: drm: Define helper function for plane color enabling Applying: drm/i915: Enable plane color features Applying: drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms Applying: drm/i915: Load plane color luts from atomic flip Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_color.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_color.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_color.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0008 drm/i915: Load plane color luts from atomic flip When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 07/16] drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
v3: Rebase
v4: Used extended function for LUT extraction (pointed by
Alexandru).
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 5 +++-
drivers/gpu/drm/i915/i915_reg.h | 25
drivers/gpu/drm/i915/intel_color.c | 57
drivers/gpu/drm/i915/intel_display.c | 4 +++
drivers/gpu/drm/i915/intel_sprite.c | 4 +++
5 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a7e1611..e4d7e22 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -117,7 +117,10 @@
}
#define BDW_COLORS \
- .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+ .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }, \
+ .plane_color = { .plane_degamma_lut_size = 0, \
+.plane_gamma_lut_size = 16 }
+
#define CHV_COLORS \
.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c866379..e896798 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -257,6 +257,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
DISPLAY_MMIO_BASE(dev_priv))
+/* Plane Gamma Registers */
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+#define _MMIO_PLANE_GAMC16(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
if (__builtin_constant_p(mask))\
@@ -10156,6 +10160,27 @@ enum skl_power_gate {
#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
_PRE_CSC_GAMC_INDEX_B)
#define PRE_CSC_GAMC_DATA(pipe)_MMIO_PIPE(pipe,
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+/* Plane Gamma in Gen9+ */
+#define _PLANE_GAMC_1_A0x701d0
+#define _PLANE_GAMC_1_B0x711d0
+#define _PLANE_GAMC_2_A0x702d0
+#define _PLANE_GAMC_2_B0x712d0
+#define _PLANE_GAMC_1(pipe)_PIPE(pipe, _PLANE_GAMC_1_A, _PLANE_GAMC_1_B)
+#define _PLANE_GAMC_2(pipe)_PIPE(pipe, _PLANE_GAMC_2_A, _PLANE_GAMC_2_B)
+#define PLANE_GAMC(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), _PLANE_GAMC_2(pipe))
+
+#define _PLANE_GAMC16_1_A 0x70210
+#define _PLANE_GAMC16_1_B 0x71210
+#define _PLANE_GAMC16_2_A 0x70310
+#define _PLANE_GAMC16_2_B 0x71310
+#define _PLANE_GAMC16_1(pipe) _PIPE(pipe, _PLANE_GAMC16_1_A, \
+_PLANE_GAMC16_1_B)
+#define _PLANE_GAMC16_2(pipe) _PIPE(pipe, _PLANE_GAMC16_2_A, \
+_PLANE_GAMC16_2_B)
+#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \
+ _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe))
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 0f8cb18..c756cd9 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -562,6 +562,59 @@ static void broadwell_load_luts(const struct
intel_crtc_state *crtc_state)
}
}
+static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state,
+u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size =
+ INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size;
+
+ if (state->gamma_lut) {
+ struct drm_color_lut_ext *lut =
+ (struct drm_color_lut_ext *)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ u32 word =
+ drm_color_lut_extract_ext(lut[i].red, 10) << 20 |
+ drm_color_lut_extract_ext(lut[i].green, 10) << 10 |
+ drm_color_lut_extract_ext(lut[i].blue, 10);
+
+ I915_WRITE(PLANE_GAMC(pipe, plane, i), word);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ i = lut_size - 1;
+
[Intel-gfx] [v7 16/16] drm/i915: Enable Plane CSC
Implement plane CSC on ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 86
drivers/gpu/drm/i915/intel_display.c | 3 ++
3 files changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 657232bd..f82a5bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6750,6 +6750,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index aa73f88..ed21d98 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -606,6 +606,90 @@ static void bdw_load_plane_gamma_lut(const struct
drm_plane_state *state,
}
}
+static void icl_load_plane_csc_matrix(const struct drm_plane_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u16 coeffs[9] = {};
+ u16 postoff = 0;
+ int i;
+
+ if (state->ctm) {
+ struct drm_color_ctm *ctm = state->ctm->data;
+ const u64 *input;
+
+ input = ctm->matrix;
+
+ /*
+* Convert fixed point S31.32 input to format supported by the
+* hardware.
+*/
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+ u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
+
+ /*
+* Clamp input value to min/max supported by
+* hardware.
+*/
+ abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
+
+ /* sign bit */
+ if (CTM_COEFF_NEGATIVE(input[i]))
+ coeffs[i] |= 1 << 15;
+
+ if (abs_coeff < CTM_COEFF_0_125)
+ coeffs[i] |= (3 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 12);
+ else if (abs_coeff < CTM_COEFF_0_25)
+ coeffs[i] |= (2 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 11);
+ else if (abs_coeff < CTM_COEFF_0_5)
+ coeffs[i] |= (1 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 10);
+ else if (abs_coeff < CTM_COEFF_1_0)
+ coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
+ else if (abs_coeff < CTM_COEFF_2_0)
+ coeffs[i] |= (7 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 8);
+ else
+ coeffs[i] |= (6 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 7);
+ }
+ } else {
+ /*
+* Load an identity matrix if no coefficients are provided.
+*
+* TODO: Check what kind of values actually come out of the
+* pipe with these coeff/postoff values and adjust to get the
+* best accuracy. Perhaps we even need to take the bpc value
+* into consideration.
+*/
+ for (i = 0; i < 3; i++)
+ coeffs[i * 3 + i] = ILK_CSC_COEFF_1_0;
+ }
+
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 0),
+ coeffs[0] << 16 | coeffs[1]);
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 1), coeffs[2] << 16);
+
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 3),
+ coeffs[3] << 16 | coeffs[4]);
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 4), coeffs[5] << 16);
+
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 5),
+ coeffs[6] << 16 | coeffs[7]);
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 6), coeffs[8] << 16);
+
+ I915_WRITE(PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ I915_WRITE(PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ I915_WRITE(PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ I915_WRITE(PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ I915_WRITE(PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ I915_WRITE(PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
/* Loads the palette/gamma unit for
[Intel-gfx] [v7 12/16] drm/i915/icl: Add Plane Gamma Register Definitions
Add Plane Gamma Register definitions for ICL+
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 42 -
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed02963..5f5c18a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10222,7 +10222,47 @@ enum skl_power_gate {
#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)_MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_DATA_4(pipe),\
_PLANE_PRE_CSC_GAMC_DATA_5(pipe))
-
+/* Plane Gamma Registers */
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701D8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711D8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702D8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712D8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B)
+
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe),\
+
_PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_4_A 0x704D8
+#define _PLANE_POST_CSC_GAMC_INDEX_4_B 0x714D8
+#define _PLANE_POST_CSC_GAMC_INDEX_5_A 0x705D8
+#define _PLANE_POST_CSC_GAMC_INDEX_5_B 0x715D8
+#define _PLANE_POST_CSC_GAMC_INDEX_4(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_4_A, _PLANE_POST_CSC_GAMC_INDEX_4_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_5(pipe) _PIPE(pipe,
_PLANE_POSt_CSC_GAMC_INDEX_5_A, _PLANE_POST_CSC_GAMC_INDEX_5_B)
+
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_INDEX_4(pipe),\
+
_PLANE_POSt_CSC_GAMC_INDEX_5(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701DC
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711DC
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702DC
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712DC
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_ENH_1_A, _PLANE_POST_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_ENH_2_A, _PLANE_POST_CSC_GAMC_DATA_ENH_2_B)
+
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe),\
+
_PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_4_A 0x704DC
+#define _PLANE_POST_CSC_GAMC_DATA_4_B 0x714DC
+#define _PLANE_POST_CSC_GAMC_DATA_5_A 0x705DC
+#define _PLANE_POST_CSC_GAMC_DATA_5_B 0x715DC
+#define _PLANE_POST_CSC_GAMC_DATA_4(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_4_A, _PLANE_POST_CSC_GAMC_DATA_4_B)
+#define _PLANE_POST_CSC_GAMC_DATA_5(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_5_A, _PLANE_POST_CSC_GAMC_DATA_5_B)
+
+#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_DATA_4(pipe),\
+
_PLANE_POST_CSC_GAMC_DATA_5(pipe))
+/* Plane Gamma Registers */
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 13/16] drm/i915/icl: Implement Plane Gamma
Implement Plane Gamma on ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 504c046..22790b4 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -692,10 +692,85 @@ static void icl_load_plane_degamma_lut(const struct
drm_plane_state *state,
}
}
+static void icl_load_plane_gamma_lut(const struct drm_plane_state *state,
+u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size;
+
+ lut_size = 32;
+ if (icl_is_hdr_plane(dev_priv, plane)) {
+ if (state->degamma_lut) {
+ struct drm_color_lut_ext *lut =
+ (struct drm_color_lut_ext
*)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ u64 word =
drm_color_lut_extract_ext(lut[i].red, 24);
+ u32 lut_val = (word & 0x7) >> 8;
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i), lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ drm_color_lut_extract_ext(lut[i].red, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ drm_color_lut_extract_ext(lut[i].green, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ drm_color_lut_extract_ext(lut[i].blue, 24));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ (1 << 24) - 1);
+ }
+ } else {
+ if (state->degamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++)
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i),
+ lut[i].green);
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ }
+ }
+}
+
/* Loads the palette/gamma unit for the CRTC on Gen11+. */
static void icl_load_plane_luts(const struct drm_plane_state *state)
{
icl_load_plane_degamma_lut(state, 0);
+ icl_load_plane_gamma_lut(state, 0);
}
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 15/16] drm/i915: Define Plane CSC Registers
Define Register macros for plane CSC.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 44 +
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 40bde4b..657232bd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10263,6 +10263,50 @@ enum skl_power_gate {
#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_DATA_4(pipe),\
_PLANE_POST_CSC_GAMC_DATA_5(pipe))
+
+/* Plane CSC Registers */
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
+ _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A,
\
+ _PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \
+
_PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+
_PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
+#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
+
+#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
+#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
+
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
+ _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
+ _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane,
_PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4,
_PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
+
+#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
+#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
+
+#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
+#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
+
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
+ _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
+ _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane,
_PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4,
_PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
/* Plane Gamma Registers */
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 10/16] drm/i915/icl: Add ICL Plane Degamma Register definition
Add register definitions for ICL Plane Degamma.
v2: Fixed register definitions for Degamma Index, spotted
by Matt Roper.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 42 +
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e896798..ed02963 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10181,6 +10181,48 @@ enum skl_power_gate {
#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \
_PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe))
+/* Plane Color Register for Gen11+ */
+/* Plane Degamma Registers */
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x712D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
+
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe),\
+
_PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_4_A 0x704D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_4_B 0x714D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_5_A 0x705D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_5_B 0x715D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_4(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_4_A, _PLANE_PRE_CSC_GAMC_INDEX_4_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_5(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_5_A, _PLANE_PRE_CSC_GAMC_INDEX_5_B)
+
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_INDEX_4(pipe),\
+
_PLANE_PRE_CSC_GAMC_INDEX_5(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
+
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)_MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe),\
+
_PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_4_A 0x704D4
+#define _PLANE_PRE_CSC_GAMC_DATA_4_B 0x714D4
+#define _PLANE_PRE_CSC_GAMC_DATA_5_A 0x705D4
+#define _PLANE_PRE_CSC_GAMC_DATA_5_B 0x715D4
+#define _PLANE_PRE_CSC_GAMC_DATA_4(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_4_A, _PLANE_PRE_CSC_GAMC_DATA_4_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_5(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_5_A, _PLANE_PRE_CSC_GAMC_DATA_5_B)
+
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)_MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_DATA_4(pipe),\
+
_PLANE_PRE_CSC_GAMC_DATA_5(pipe))
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 09/16] drm/i915: Add plane color capabilities
Add Plane color capabilties, support for
degamma and gamma added.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 12 +---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_sprite.c | 11 +--
4 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index b56c3999..afb1d00 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -930,7 +930,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
-void intel_plane_color_init(struct drm_plane *plane)
+void intel_plane_color_init(struct drm_plane *plane, u32 degamma_lut_size,
+ u32 gamma_lut_size)
{
struct drm_i915_private *dev_priv = to_i915(plane->dev);
@@ -941,12 +942,9 @@ void intel_plane_color_init(struct drm_plane *plane)
drm_plane_color_create_prop(plane->dev, plane);
/* Enable color management support when we have degamma or gamma LUTs.
*/
- if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 ||
- INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0)
- drm_plane_enable_color_mgmt(plane,
-
INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size,
- true,
-
INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size);
+ if (degamma_lut_size != 0 || gamma_lut_size != 0)
+ drm_plane_enable_color_mgmt(plane, degamma_lut_size,
+ true, gamma_lut_size);
}
void intel_color_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2775c3f..fc43c37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14413,8 +14413,8 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private
*dev_priv,
supported_rotations);
/* Add Plane Color properties */
- if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
- intel_plane_color_init(>base);
+ if (IS_BROADWELL(dev_priv))
+ intel_plane_color_init(>base, 0, 16);
drm_plane_helper_add(>base, _plane_helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a17e6a4..3a68191 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2544,7 +2544,8 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
int intel_color_check(struct intel_crtc_state *crtc_state);
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
-void intel_plane_color_init(struct drm_plane *plane);
+void intel_plane_color_init(struct drm_plane *plane, u32 degamma_lut_size,
+ u32 gamma_lut_size);
void intel_color_load_plane_luts(const struct drm_plane_state *plane_state);
/* intel_lspcon.c */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 766e03e..41fdc12 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -2334,8 +2334,15 @@ struct intel_plane *
BIT(DRM_MODE_BLEND_COVERAGE));
/* Add Plane Color properties */
- if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
- intel_plane_color_init(>base);
+ if (INTEL_GEN(dev_priv) <= 10)
+ intel_plane_color_init(>base, 0, 16);
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ if (icl_is_hdr_plane(dev_priv, plane_id))
+ intel_plane_color_init(>base, 128, 33);
+ else
+ intel_plane_color_init(>base, 33, 33);
+ }
drm_plane_helper_add(>base, _plane_helper_funcs);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 14/16] drm/i915: Enable Plane Gamma/Degamma
Update the plane gamma and degamma feature in the
plane state and eventually program to PLANE_COLOR_CTL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 6 ++
drivers/gpu/drm/i915/intel_display.c | 6 +-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5f5c18a..40bde4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6757,6 +6757,7 @@ enum {
#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709(2 << 17)
#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
+#define PLANE_COLOR_PLANE_PRECSC_GAMMA_ENABLE(1 << 14)
#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
#define PLANE_COLOR_ALPHA_DISABLE(0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 22790b4..aa73f88 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -769,8 +769,14 @@ static void icl_load_plane_gamma_lut(const struct
drm_plane_state *state,
/* Loads the palette/gamma unit for the CRTC on Gen11+. */
static void icl_load_plane_luts(const struct drm_plane_state *state)
{
+ struct intel_plane_state *plane_state =
+ to_intel_plane_state(state);
+
icl_load_plane_degamma_lut(state, 0);
icl_load_plane_gamma_lut(state, 0);
+
+ plane_state->gamma_mode |= PLANE_COLOR_PLANE_PRECSC_GAMMA_ENABLE;
+ plane_state->gamma_mode |= ~PLANE_COLOR_PLANE_GAMMA_DISABLE;
}
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fc43c37..6b37052 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3815,7 +3815,11 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state,
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
u32 plane_color_ctl = 0;
- plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
+ if (INTEL_GEN(dev_priv) <= 11)
+ plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
+ else
+ plane_color_ctl |= plane_state->gamma_mode;
+
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 06/16] drm/i915: Enable plane color features
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_color.c | 15 +++
drivers/gpu/drm/i915/intel_device_info.h | 5 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 25c264e..51c1456 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -55,6 +55,7 @@
#include
#include
#include
+#include
#include
#include "i915_fixed.h"
@@ -339,6 +340,11 @@ struct drm_i915_display_funcs {
* involved with the same commit.
*/
void (*load_luts)(const struct intel_crtc_state *crtc_state);
+ /* Add Plane Color callbacks */
+ void (*load_plane_csc_matrix)(const struct drm_plane_state
+ *plane_state);
+ void (*load_plane_luts)(const struct drm_plane_state
+ *plane_state);
};
#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 467fd1a..0f8cb18 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -869,6 +869,21 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
+void intel_plane_color_init(struct drm_plane *plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->dev);
+
+ drm_plane_color_create_prop(plane->dev, plane);
+
+ /* Enable color management support when we have degamma or gamma LUTs.
*/
+ if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 ||
+ INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0)
+ drm_plane_enable_color_mgmt(plane,
+
INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size,
+ true,
+
INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 7e04b48..91c5925 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -194,6 +194,11 @@ struct intel_device_info {
u32 degamma_lut_tests;
u32 gamma_lut_tests;
} color;
+
+ struct plane_color_luts {
+ u16 plane_degamma_lut_size;
+ u16 plane_gamma_lut_size;
+ } plane_color;
};
struct intel_runtime_info {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f8c7b29..7c7dbb8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -658,6 +658,14 @@ struct intel_plane_state {
*/
u32 slave;
+ /*
+* Use reduced/limited/broadcast rbg range, compressing from the full
+* range fed into the crtcs.
+*/
+ bool limited_color_range;
+ /* Gamma mode programmed on the plane */
+ u32 gamma_mode;
+
struct drm_intel_sprite_colorkey ckey;
};
@@ -2536,6 +2544,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
int intel_color_check(struct intel_crtc_state *crtc_state);
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
+void intel_plane_color_init(struct drm_plane *plane);
/* intel_lspcon.c */
bool lspcon_init(struct intel_digital_port *intel_dig_port);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 11/16] drm/i915/icl: Enable Plane Degamma
Enable Plane Degamma for ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 86 ++
1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index afb1d00..504c046 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -615,6 +615,89 @@ static void broadwell_load_plane_luts(const struct
drm_plane_state *state)
INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size);
}
+static void icl_load_plane_degamma_lut(const struct drm_plane_state *state,
+ u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size;
+
+ if (icl_is_hdr_plane(dev_priv, plane)) {
+ lut_size = 128;
+ if (state->degamma_lut) {
+ struct drm_color_lut_ext *lut =
+ (struct drm_color_lut_ext
*)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ u64 word = drm_color_lut_extract_ext(lut[i].red,
+24);
+ u32 lut_val = (word & 0x7) >> 8;
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i),
+ lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ drm_color_lut_extract_ext(lut[i].red, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ drm_color_lut_extract_ext(lut[i].green, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ drm_color_lut_extract_ext(lut[i].blue, 24));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ (1 << 24) - 1);
+ }
+ } else {
+ lut_size = 32;
+ if (state->degamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++)
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i),
+ lut[i].green);
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ }
+ }
+}
+
+/* Loads the palette/gamma unit for the CRTC on Gen11+. */
+static void icl_load_plane_luts(const struct drm_plane_state *state)
+{
+ icl_load_plane_degamma_lut(state, 0);
+}
+
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -978,6 +1061,9 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_commit = ilk_color_commit;
}
+ if (INTEL_GEN(dev_priv) >= 11)
+
[Intel-gfx] [v7 08/16] drm/i915: Load plane color luts from atomic flip
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 3 +++
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 9d32a6f..32269bd 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -271,6 +271,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
+ if (new_plane_state->base.color_mgmt_changed)
+ intel_color_load_plane_luts(_plane_state->base);
+
if (new_plane_state->base.visible) {
intel_update_plane(plane, new_crtc_state,
new_plane_state);
} else if (new_plane_state->slave) {
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index c756cd9..b56c3999 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -841,6 +841,14 @@ static u32 chv_cgm_mode(const struct intel_crtc_state
*crtc_state)
return cgm_mode;
}
+void intel_color_load_plane_luts(const struct drm_plane_state *plane_state)
+{
+ struct drm_device *dev = plane_state->plane->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ dev_priv->display.load_plane_luts(plane_state);
+}
+
int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7c7dbb8..a17e6a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2545,6 +2545,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
void intel_plane_color_init(struct drm_plane *plane);
+void intel_color_load_plane_luts(const struct drm_plane_state *plane_state);
/* intel_lspcon.c */
bool lspcon_init(struct intel_digital_port *intel_dig_port);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 05/16] drm: Define helper function for plane color enabling
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
v4: Rebase
v5: Moved helper function to drm_color_mgmt.c file to have all
color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
drivers/gpu/drm/drm_color_mgmt.c | 42
include/drm/drm_color_mgmt.h | 5 +
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index f168609..9cedd27 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -484,6 +484,48 @@ int drm_plane_create_color_properties(struct drm_plane
*plane,
EXPORT_SYMBOL(drm_plane_create_color_properties);
/**
+ * drm_plane_enable_color_mgmt - enable color management properties
+ * @plane: DRM Plane
+ * @plane_degamma_lut_size: the size of the degamma lut (before CSC)
+ * @plane_has_ctm: whether to attach ctm_property for CSC matrix
+ * @plane_gamma_lut_size: the size of the gamma lut (after CSC)
+ *
+ * This function lets the driver enable the color correction
+ * properties on a plane. This includes 3 degamma, csc and gamma
+ * properties that userspace can set and 2 size properties to inform
+ * the userspace of the lut sizes. Each of the properties are
+ * optional. The gamma and degamma properties are only attached if
+ * their size is not 0 and ctm_property is only attached if has_ctm is
+ * true.
+ */
+void drm_plane_enable_color_mgmt(struct drm_plane *plane,
+u32 plane_degamma_lut_size,
+bool plane_has_ctm,
+u32 plane_gamma_lut_size)
+{
+ if (plane_degamma_lut_size) {
+ drm_object_attach_property(>base,
+ plane->degamma_lut_property, 0);
+ drm_object_attach_property(>base,
+ plane->degamma_lut_size_property,
+ plane_degamma_lut_size);
+ }
+
+ if (plane_has_ctm)
+ drm_object_attach_property(>base,
+ plane->ctm_property, 0);
+
+ if (plane_gamma_lut_size) {
+ drm_object_attach_property(>base,
+ plane->gamma_lut_property, 0);
+ drm_object_attach_property(>base,
+ plane->gamma_lut_size_property,
+ plane_gamma_lut_size);
+ }
+}
+EXPORT_SYMBOL(drm_plane_enable_color_mgmt);
+
+/**
* DOC: Plane Color Properties
*
* Plane Color management or color space adjustments is supported
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index c9d2746..8726cee 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -71,6 +71,11 @@ int drm_plane_create_color_properties(struct drm_plane
*plane,
enum drm_color_encoding default_encoding,
enum drm_color_range default_range);
+void drm_plane_enable_color_mgmt(struct drm_plane *plane,
+u32 plane_degamma_lut_size,
+bool plane_has_ctm,
+u32 plane_gamma_lut_size);
+
/**
* enum drm_color_lut_tests - hw-specific LUT tests to perform
*
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 03/16] drm: Add Plane CTM property
Add a blob property for plane CSC usage.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Moved property creation to drm_color_mgmt.c file to have all
color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
Documentation/gpu/drm-kms.rst | 3 +++
drivers/gpu/drm/drm_atomic_state_helper.c | 4
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 11 +++
include/drm/drm_plane.h | 15 +++
5 files changed, 43 insertions(+)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 9e64df5..14f79f1 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -569,6 +569,9 @@ Plane Color Management Properties
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
:doc: export
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: ctm_property
+
Tile Group Property
---
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index a8fb7f9..c5664aa 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -246,6 +246,9 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
if (state->degamma_lut)
drm_property_blob_get(state->degamma_lut);
+ if (state->ctm)
+ drm_property_blob_get(state->ctm);
+
state->color_mgmt_changed = false;
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state);
@@ -294,6 +297,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_property_blob_put(state->fb_damage_clips);
drm_property_blob_put(state->degamma_lut);
+ drm_property_blob_put(state->ctm);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index b21fba5..495152a 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -579,6 +579,14 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
);
state->color_mgmt_changed |= replaced;
return ret;
+ } else if (property == plane->ctm_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ >ctm,
+ val,
+ sizeof(struct drm_color_ctm), -1,
+ );
+ state->color_mgmt_changed |= replaced;
+ return ret;
} else if (property == config->prop_fb_damage_clips) {
ret = drm_atomic_replace_property_blob_from_id(dev,
>fb_damage_clips,
@@ -645,6 +653,8 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
} else if (property == plane->degamma_lut_property) {
*val = (state->degamma_lut) ?
state->degamma_lut->base.id : 0;
+ } else if (property == plane->ctm_property) {
+ *val = (state->ctm) ? state->ctm->base.id : 0;
} else if (property == config->prop_fb_damage_clips) {
*val = (state->fb_damage_clips) ?
state->fb_damage_clips->base.id : 0;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 8ccefd8..9747ac7 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -497,6 +497,11 @@ int drm_plane_create_color_properties(struct drm_plane
*plane,
*
* degamma_lut_size_property:
* Range Property to indicate size of the plane degamma LUT.
+ *
+ * ctm_property:
+ * Blob property which allows a userspace to provide CTM coefficients
+ * to do color space conversion or any other enhancement by doing a
+ * matrix multiplication using the h/w CTM processing engine
*/
int drm_plane_color_create_prop(struct drm_device *dev,
struct drm_plane *plane)
@@ -516,6 +521,12 @@ int drm_plane_color_create_prop(struct drm_device *dev,
return -ENOMEM;
plane->degamma_lut_size_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "PLANE_CTM", 0);
+ if (!prop)
+ return -ENOMEM;
+ plane->ctm_property = prop;
+
return 0;
}
EXPORT_SYMBOL(drm_plane_color_create_prop);
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 757f1e8..38b52a2 100644
---
[Intel-gfx] [v7 01/16] drm: Add Enhanced Gamma LUT precision structure
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values. Also added the code,
for extracting the same from values passed from userspace.
v4: Rebase
v5: Relocated the helper function to drm_color_mgmt.c. Declared
the same in a header file (Alexandru Gheorghe)
v6: Enhanced gamma lut structure to take U32.32 format as input.
This is needed for HDR usecase which require higher precision.
v7: Addressed Maarten's review comments and fixed the calculation.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
drivers/gpu/drm/drm_color_mgmt.c | 20
include/drm/drm_color_mgmt.h | 1 +
include/uapi/drm/drm_mode.h | 15 +++
3 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index d5d34d0..79ff874 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -128,6 +128,26 @@ uint32_t drm_color_lut_extract(uint32_t user_input,
uint32_t bit_precision)
}
EXPORT_SYMBOL(drm_color_lut_extract);
+/*
+ * Added to accommodate enhanced LUT precision.
+ * Max LUT precision is 32 bits.
+ */
+u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision)
+{
+ u64 val = user_input & 0x;
+ u32 max = 0x >> (32 - bit_precision);
+
+ /* Round only if we're not using full precision. */
+ if (bit_precision < 32) {
+ val += 1UL << (32 - bit_precision - 1);
+ val >>= 32 - bit_precision;
+ }
+
+ return ((user_input & 0x) |
+ clamp_val(val, 0, max));
+}
+EXPORT_SYMBOL(drm_color_lut_extract_ext);
+
/**
* drm_crtc_enable_color_mgmt - enable color management properties
* @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index d1c662d..c9d2746 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -30,6 +30,7 @@
struct drm_plane;
uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
+u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision);
void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
uint degamma_lut_size,
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 09d7296..ca81410 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -629,6 +629,21 @@ struct drm_color_lut {
__u16 reserved;
};
+/*
+ * Creating 64 bit palette entries for better data
+ * precision. This will be required for HDR and
+ * similar color processing usecases.
+ */
+struct drm_color_lut_ext {
+ /*
+* Data is U32.32 fixed point format.
+*/
+ __u64 red;
+ __u64 green;
+ __u64 blue;
+ __u64 reserved;
+};
+
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v7 04/16] drm: Add Plane Gamma properties
Add plane gamma as blob property and size as a
range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Moved property creation to drm_color_mgmt.c file to have all
color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
Documentation/gpu/drm-kms.rst | 6 ++
drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 9 +
drivers/gpu/drm/drm_color_mgmt.c | 22 ++
include/drm/drm_plane.h | 22 ++
5 files changed, 62 insertions(+)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 14f79f1..0877faf 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -572,6 +572,12 @@ Plane Color Management Properties
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
:doc: ctm_property
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: gamma_lut_property
+
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: gamma_lut_size_property
+
Tile Group Property
---
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index c5664aa..2739c27 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -248,6 +248,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
drm_property_blob_get(state->degamma_lut);
if (state->ctm)
drm_property_blob_get(state->ctm);
+ if (state->gamma_lut)
+ drm_property_blob_get(state->gamma_lut);
state->color_mgmt_changed = false;
}
@@ -298,6 +300,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_property_blob_put(state->fb_damage_clips);
drm_property_blob_put(state->degamma_lut);
drm_property_blob_put(state->ctm);
+ drm_property_blob_put(state->gamma_lut);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 495152a..3eb9423 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -587,6 +587,13 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
);
state->color_mgmt_changed |= replaced;
return ret;
+ } else if (property == plane->gamma_lut_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ >gamma_lut,
+ val, -1, sizeof(struct drm_color_lut),
+ );
+ state->color_mgmt_changed |= replaced;
+ return ret;
} else if (property == config->prop_fb_damage_clips) {
ret = drm_atomic_replace_property_blob_from_id(dev,
>fb_damage_clips,
@@ -655,6 +662,8 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
state->degamma_lut->base.id : 0;
} else if (property == plane->ctm_property) {
*val = (state->ctm) ? state->ctm->base.id : 0;
+ } else if (property == plane->gamma_lut_property) {
+ *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
} else if (property == config->prop_fb_damage_clips) {
*val = (state->fb_damage_clips) ?
state->fb_damage_clips->base.id : 0;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 9747ac7..f168609 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -502,6 +502,15 @@ int drm_plane_create_color_properties(struct drm_plane
*plane,
* Blob property which allows a userspace to provide CTM coefficients
* to do color space conversion or any other enhancement by doing a
* matrix multiplication using the h/w CTM processing engine
+ *
+ * gamma_lut_property:
+ * Blob property which allows a userspace to provide LUT values
+ * to apply gamma/tone-mapping curve using the h/w plane gamma
+ * processing engine, thereby making the content as non-linear
+ * or to perform any tone mapping operation for HDR usecases.
+ *
+ * gamma_lut_size_property:
+ * Range Property to indicate size of the plane gamma LUT.
*/
int drm_plane_color_create_prop(struct drm_device *dev,
struct drm_plane *plane)
@@ -527,6 +536,19 @@ int drm_plane_color_create_prop(struct drm_device *dev,
[Intel-gfx] [v7 02/16] drm: Add Plane Degamma properties
Add Plane Degamma as a blob property and plane degamma size as
a range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Added "Display Color Hardware Pipeline" flow to kernel
documentation as suggested by "Ville Syrjala" and "Brian Starkey".
Moved the property creation to drm_color_mgmt.c file to consolidate
all color operations at one place.
v6: Fixed checkpatch issues with --strict as parameter.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
Documentation/gpu/drm-kms.rst | 90 +++
drivers/gpu/drm/drm_atomic.c | 1 +
drivers/gpu/drm/drm_atomic_state_helper.c | 5 ++
drivers/gpu/drm/drm_atomic_uapi.c | 10
drivers/gpu/drm/drm_color_mgmt.c | 43 +--
include/drm/drm_plane.h | 24 +
6 files changed, 170 insertions(+), 3 deletions(-)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 23a3c98..9e64df5 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -473,12 +473,102 @@ FB_DAMAGE_CLIPS
Color Management Properties
---
+Below is how a typical hardware pipeline for color
+will look like:
+
+.. kernel-render:: DOT
+ :alt: Display Color Pipeline
+ :caption: Display Color Pipeline Overview
+
+ digraph "KMS" {
+ node [shape=box]
+
+ subgraph cluster_static {
+ style=dashed
+ label="Display Color Hardware Blocks"
+
+ node [bgcolor=grey style=filled]
+ "Plane Degamma A" -> "Plane CSC/CTM A"
+ "Plane CSC/CTM A" -> "Plane Gamma A"
+ "Pipe Blender" [color=lightblue,style=filled, width=5.25,
height=0.75];
+ "Plane Gamma A" -> "Pipe Blender"
+ "Pipe Blender" -> "Pipe DeGamma"
+ "Pipe DeGamma" -> "Pipe CSC/CTM"
+ "Pipe CSC/CTM" -> "Pipe Gamma"
+ "Pipe Gamma" -> "Pipe Output"
+ }
+
+ subgraph cluster_static {
+ style=dashed
+
+ node [shape=box]
+ "Plane Degamma B" -> "Plane CSC/CTM B"
+ "Plane CSC/CTM B" -> "Plane Gamma B"
+ "Plane Gamma B" -> "Pipe Blender"
+ }
+
+ subgraph cluster_static {
+ style=dashed
+
+ node [shape=box]
+ "Plane Degamma C" -> "Plane CSC/CTM C"
+ "Plane CSC/CTM C" -> "Plane Gamma C"
+ "Plane Gamma C" -> "Pipe Blender"
+ }
+
+ subgraph cluster_fb {
+ style=dashed
+ label="RAM"
+
+ node [shape=box width=1.7 height=0.2]
+
+ "FB 1" -> "Plane Degamma A"
+ "FB 2" -> "Plane Degamma B"
+ "FB 3" -> "Plane Degamma C"
+ }
+ }
+
+In real world usecases,
+
+1. Plane Degamma can be used to linearize a non linear gamma
+encoded framebuffer. This is needed to do any linear math like
+color space conversion. For ex, linearize frames encoded in SRGB
+or by HDR curve.
+
+2. Later Plane CTM block can convert the content to some different
+colorspace. For ex, SRGB to BT2020 etc.
+
+3. Plane Gamma block can be used later to re-apply the non-linear
+curve. This can also be used to apply Tone Mapping for HDR usecases.
+
+All the layers or framebuffers need to be converted to same color
+space and format before blending. The plane color hardware blocks
+can help with this. Once the Data is blended, similar color processing
+can be done on blended output using pipe color hardware blocks.
+
+DRM Properties have been created to define and expose all these
+hardware blocks to userspace. A userspace application (compositor
+or any color app) can use these interfaces and define policies to
+efficiently use the display hardware for such color operations.
+
+Pipe Color Management Properties
+-
+
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
:doc: overview
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
:export:
+Plane Color Management Properties
+-
+
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: Plane Color Properties
+
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: export
+
Tile Group Property
---
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 5eb4013..6336542 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -655,6 +655,7 @@ static void drm_atomic_plane_print_state(struct drm_printer
*p,
drm_get_color_encoding_name(state->color_encoding));
drm_printf(p, "\tcolor-range=%s\n",
drm_get_color_range_name(state->color_range));
+ drm_printf(p, "\tcolor_mgmt_changed=%d\n", state->color_mgmt_changed);
if
[Intel-gfx] [v7 00/16] Add Plane Color Properties
This is how a typical display color hardware pipeline looks like: +---+ |RAM| | +--++-++-+ | | | FB 1 || FB 2 || FB N| | | +--++-++-+ | +---+ | Plane Color Hardware Block | ++ | +---v-+ +---v---+ +---v--+ | | | Plane A | | Plane B | | Plane N | | | | DeGamma | | Degamma | | Degamma | | | +---+-+ +---+---+ +---+--+ | | | | || | +---v-+ +---v---+ +---v--+ | | |Plane A | | Plane B | | Plane N | | | |CSC/CTM | | CSC/CTM | | CSC/CTM | | | +---+-+ ++--+ ++-+ | | | | | | | +---v-+ +v--+ +v-+ | | | Plane A | | Plane B | | Plane N | | | | Gamma | | Gamma | | Gamma| | | +---+-+ ++--+ ++-+ | | | | | | ++ +--v--v---v---| || || || Pipe Blender|| +++ ||| |+---v--+ | || Pipe DeGamma| | || | | |+---+--+ | ||Pipe Color | |+---v--+ Hardware| || Pipe CSC/CTM| | || | | |+---+--+ | ||| |+---v--+ | || Pipe Gamma | | || | | |+---+--+ | ||| +-+ | v Pipe Output This patch series adds properties for plane color features. It adds properties for degamma used to linearize data, CSC used for gamut conversion, and gamma used to again non-linearize data as per panel supported color space. These can be utilize by user space to convert planes from one format to another, one color space to another etc. Usersapce can take smart blending decisions and utilize these hardware supported plane color features to get accurate color profile. The same can help in consistent color quality from source to panel taking advantage of advanced color features in hardware. These patches just add the property interfaces and enable helper functions. This series adds Intel Gen9 specific plane gamma feature. We can build up and add other platform/hardware specific implementation on top of this series Note: This is just to get a design feedback whether these interfaces look ok. Based on community feedback on interfaces, we will implement IGT tests to validate plane color features. This is un-tested currently. Userspace implementation using these properties have been done in drm hwcomposer by "Alexandru-Cosmin Gheorghe alexandru-cosmin.gheor...@arm.com" from ARM. A merge request has been opened by Alexandru for drm_hwcomposer, implementing the property changes for the same. Please review that as well: https://gitlab.freedesktop.org/drm-hwcomposer/drm-hwcomposer/merge_requests/25 v2: Dropped legacy gamma table for plane as suggested by Maarten. Added Gen9/BDW plane gamma feature and rebase on tot. v3: Added a new drm_color_lut_ext structure to accommodate 32 bit precision entries, pointed to by Brian, Starkey for HDR usecases. Addressed Sean,Paul comments and moved plane color properties to drm_plane instead of mode_config. Added property documentation as suggested by Daniel, Vetter. Fixed a rebase fumble which occurred in v2, pointed by Emil Velikov. v4: Rebase v5: Added "Display Color Hardware Pipeline" flow to kernel documentation as suggested by "Ville Syrjala" and "Brian Starkey". Moved the property creation to drm_color_mgmt.c file to consolidate all color operations at one place. Addressed Alexandru's review comments. v6: Rebase. Added support for ICL Color features. Enhanced Lut precision to accept input values in u32.32 format. This is needed for higher precision required in HDR data processing. v7: Fixed Lut roundup and extraction function in patch 1 and address definitions for Degamma index in patch 10. Rest of the patches are just rebased. Uma Shankar (16): drm: Add Enhanced Gamma LUT precision structure drm: Add Plane Degamma properties drm: Add Plane CTM property drm: Add Plane Gamma properties drm: Define helper function
Re: [Intel-gfx] [PATCH v2 00/10] drm/i915: Clean up intel_color_check()
On Wed, Mar 27, 2019 at 10:30:18AM -0700, Matt Roper wrote: > On Wed, Mar 27, 2019 at 05:50:35PM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Repost of the earlier series to clean up intel_color_check(). > > I tried to address all of Matt's review comments (thanks!). > > > > All reviewed except patch 8. > > Patch 8 (and the rest of the series): > > Reviewed-by: Matt Roper Awesome. Thanks for reviewing this. Series pushed to dinq. > > > Ville Syrjälä (10): > > drm/i915: Extract check_luts() > > drm/i915: Turn intel_color_check() into a vfunc > > drm/i915: Extract i9xx_color_check() > > drm/i915: Extract chv_color_check() > > drm/i915: Extract icl_color_check() > > drm/i915: Extract glk_color_check() > > drm/i915: Extract bdw_color_check() > > drm/i915: Extract ilk_color_check() > > drm/i915: Drop the pointless linear legacy LUT load on CHV > > drm/i915: Skip the linear degamma LUT load on ICL+ > > > > drivers/gpu/drm/i915/i915_drv.h| 1 + > > drivers/gpu/drm/i915/intel_color.c | 416 + > > 2 files changed, 311 insertions(+), 106 deletions(-) > > > > -- > > 2.19.2 > > > > -- > Matt Roper > Graphics Software Engineer > IoTG Platform Enabling & Development > Intel Corporation > (916) 356-2795 -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC v1 3/7] drm/i915: Add Support for Multi Segment Gamma Mode
On Thu, Mar 28, 2019 at 07:00:30PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Friday, March 22, 2019 7:23 PM
> >To: Shankar, Uma
> >Cc: Syrjala, Ville ; Lankhorst, Maarten
> >; intel-gfx@lists.freedesktop.org
> >Subject: Re: [Intel-gfx] [RFC v1 3/7] drm/i915: Add Support for Multi
> >Segment Gamma
> >Mode
> >
> >On Wed, Mar 20, 2019 at 05:03:16PM +, Shankar, Uma wrote:
> >>
> >>
> >> >-Original Message-
> >> >From: Syrjala, Ville
> >> >Sent: Tuesday, March 19, 2019 10:29 PM
> >> >To: Lankhorst, Maarten
> >> >Cc: Shankar, Uma ;
> >> >intel-gfx@lists.freedesktop.org; Sharma, Shashank
> >> >; Roper, Matthew D
> >> >
> >> >Subject: Re: [RFC v1 3/7] drm/i915: Add Support for Multi Segment
> >> >Gamma Mode
> >> >
> >> >On Tue, Mar 19, 2019 at 10:46:27AM +0200, Lankhorst, Maarten wrote:
> >> >> tis 2019-03-19 klockan 14:00 +0530 skrev Uma Shankar:
> >> >> > Multi Segment Gamma Mode is added in Gen11+ platforms.
> >> >> > Added a property interface to enable that.
> >> >> >
> >> >> > Signed-off-by: Uma Shankar
> >> >> > ---
> >> >> > drivers/gpu/drm/i915/i915_drv.h| 1 +
> >> >> > drivers/gpu/drm/i915/intel_color.c | 23 +++
> >> >> > include/uapi/drm/i915_drm.h| 14 ++
> >> >> > 3 files changed, 38 insertions(+)
> >> >> >
> >> >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> >> > b/drivers/gpu/drm/i915/i915_drv.h index 02231ae..f20d418 100644
> >> >> > --- a/drivers/gpu/drm/i915/i915_drv.h
> >> >> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> >> > @@ -1736,6 +1736,7 @@ struct drm_i915_private {
> >> >> > struct drm_property *force_audio_property;
> >> >> >
> >> >> > struct drm_property *gamma_mode_property;
> >> >> > + struct drm_property *multi_segment_gamma_mode_property;
> >> >>
> >> >> Seems to me both properties should be part of drm core?
> >>
> >> Sure Maarten, we can move gamma_mode property to drm.
> >>
> >> >>
> >> >> > /* hda/i915 audio component */
> >> >> > struct i915_audio_component *audio_component; diff --git
> >> >> > a/drivers/gpu/drm/i915/intel_color.c
> >> >> > b/drivers/gpu/drm/i915/intel_color.c
> >> >> > index 9d43d19..399d63d 100644
> >> >> > --- a/drivers/gpu/drm/i915/intel_color.c
> >> >> > +++ b/drivers/gpu/drm/i915/intel_color.c
> >> >> > @@ -149,6 +149,26 @@ static bool crtc_state_is_legacy_gamma(const
> >> >> > struct intel_crtc_state *crtc_state
> >> >> > drm_object_attach_property(>base.base, prop, 0); }
> >> >> >
> >> >> > +void
> >> >> > +intel_attach_multi_segment_gamma_mode_property(struct intel_crtc
> >> >> > *crtc)
> >> >> > +{
> >> >> > + struct drm_device *dev = crtc->base.dev;
> >> >> > + struct drm_i915_private *dev_priv = to_i915(dev);
> >> >> > + struct drm_property *prop;
> >> >> > +
> >> >> > + prop = dev_priv->multi_segment_gamma_mode_property;
> >> >> > + if (!prop) {
> >> >> > + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
> >> >> > +"Multi-segment Gamma",
> >> >> > 0);
> >> >> > + if (!prop)
> >> >> > + return;
> >> >> > +
> >> >> > + dev_priv->multi_segment_gamma_mode_property = prop;
> >> >> > + }
> >> >> > +
> >> >> > + drm_object_attach_property(>base.base, prop, 0); }
> >> >> > +
> >> >> > /*
> >> >> > * When using limited range, multiply the matrix given by
> >> >> > userspace by
> >> >> > * the matrix that we would use for the limited range.
> >> >> > @@ -953,4 +973,7 @@ void intel_color_init(struct intel_crtc *crtc)
> >> >> > INTEL_INFO(dev_priv)-
> >> >> > >color.gamma_lut_size);
> >> >> >
> >> >> > intel_attach_gamma_mode_property(crtc);
> >> >> > +
> >> >> > + if (INTEL_GEN(dev_priv) >= 11)
> >> >> > + intel_attach_multi_segment_gamma_mode_property(crtc)
> >> >> > ;
> >> >> > }
> >> >> > diff --git a/include/uapi/drm/i915_drm.h
> >> >> > b/include/uapi/drm/i915_drm.h index aa2d4c7..8f1974e 100644
> >> >> > --- a/include/uapi/drm/i915_drm.h
> >> >> > +++ b/include/uapi/drm/i915_drm.h
> >> >> > @@ -1842,6 +1842,20 @@ struct drm_i915_query_topology_info {
> >> >> > __u8 data[];
> >> >> > };
> >> >> >
> >> >> > +/*
> >> >> > + * Structure for muti segmented gamma lut */ struct
> >> >> > +multi_segment_gamma_lut {
> >> >> > + /* Number of Lut Segments */
> >> >> > + __u8 segment_cnt;
> >> >> > + /* Precison of LUT entries in bits */
> >> >> > + __u8 precision_bits;
> >> >> > + /* Pointer having number of LUT elements in each segment */
> >> >> > + __u32 *segment_lut_cnt_ptr;
> >> >> > + /* Pointer to store exact lut values for each segment */
> >> >> > + __u32 *segment_lut_ptr;
> >> >> > +};
> >> >> >
> >> >> And perhaps a variation of this as description for all gamma mode
> >> >> types.
> >> >
> >> >This is my old idea how to
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: move the edram detection out of uncore init
== Series Details == Series: drm/i915: move the edram detection out of uncore init URL : https://patchwork.freedesktop.org/series/58684/ State : success == Summary == CI Bug Log - changes from CI_DRM_5831 -> Patchwork_12621 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58684/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12621 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@i915_selftest@live_requests: - fi-icl-u2: PASS -> INCOMPLETE [fdo#109644] * igt@kms_busy@basic-flip-a: - fi-gdg-551: PASS -> FAIL [fdo#103182] * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-byt-clapper: PASS -> FAIL [fdo#107362] Possible fixes * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: FAIL [fdo#103167] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (43 -> 38) -- Missing(5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ivb-3770 Build changes - * Linux: CI_DRM_5831 -> Patchwork_12621 CI_DRM_5831: 8cac0cc264d2a6af0b33370b542b12d516e022c5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4911: d9fe699ea45406e279b78d1afdb4d57a205a3c99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12621: 35f535cdfdb31dd363cf328074e80219a2612822 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 35f535cdfdb3 drm/i915: move the edram detection out of uncore init == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12621/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: move the edram detection out of uncore init
== Series Details == Series: drm/i915: move the edram detection out of uncore init URL : https://patchwork.freedesktop.org/series/58684/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: move the edram detection out of uncore init -drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC v1 3/7] drm/i915: Add Support for Multi Segment Gamma Mode
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, March 22, 2019 7:23 PM
>To: Shankar, Uma
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [RFC v1 3/7] drm/i915: Add Support for Multi Segment
>Gamma
>Mode
>
>On Wed, Mar 20, 2019 at 05:03:16PM +, Shankar, Uma wrote:
>>
>>
>> >-Original Message-
>> >From: Syrjala, Ville
>> >Sent: Tuesday, March 19, 2019 10:29 PM
>> >To: Lankhorst, Maarten
>> >Cc: Shankar, Uma ;
>> >intel-gfx@lists.freedesktop.org; Sharma, Shashank
>> >; Roper, Matthew D
>> >
>> >Subject: Re: [RFC v1 3/7] drm/i915: Add Support for Multi Segment
>> >Gamma Mode
>> >
>> >On Tue, Mar 19, 2019 at 10:46:27AM +0200, Lankhorst, Maarten wrote:
>> >> tis 2019-03-19 klockan 14:00 +0530 skrev Uma Shankar:
>> >> > Multi Segment Gamma Mode is added in Gen11+ platforms.
>> >> > Added a property interface to enable that.
>> >> >
>> >> > Signed-off-by: Uma Shankar
>> >> > ---
>> >> > drivers/gpu/drm/i915/i915_drv.h| 1 +
>> >> > drivers/gpu/drm/i915/intel_color.c | 23 +++
>> >> > include/uapi/drm/i915_drm.h| 14 ++
>> >> > 3 files changed, 38 insertions(+)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> >> > b/drivers/gpu/drm/i915/i915_drv.h index 02231ae..f20d418 100644
>> >> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> >> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> >> > @@ -1736,6 +1736,7 @@ struct drm_i915_private {
>> >> > struct drm_property *force_audio_property;
>> >> >
>> >> > struct drm_property *gamma_mode_property;
>> >> > + struct drm_property *multi_segment_gamma_mode_property;
>> >>
>> >> Seems to me both properties should be part of drm core?
>>
>> Sure Maarten, we can move gamma_mode property to drm.
>>
>> >>
>> >> > /* hda/i915 audio component */
>> >> > struct i915_audio_component *audio_component; diff --git
>> >> > a/drivers/gpu/drm/i915/intel_color.c
>> >> > b/drivers/gpu/drm/i915/intel_color.c
>> >> > index 9d43d19..399d63d 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_color.c
>> >> > +++ b/drivers/gpu/drm/i915/intel_color.c
>> >> > @@ -149,6 +149,26 @@ static bool crtc_state_is_legacy_gamma(const
>> >> > struct intel_crtc_state *crtc_state
>> >> > drm_object_attach_property(>base.base, prop, 0); }
>> >> >
>> >> > +void
>> >> > +intel_attach_multi_segment_gamma_mode_property(struct intel_crtc
>> >> > *crtc)
>> >> > +{
>> >> > + struct drm_device *dev = crtc->base.dev;
>> >> > + struct drm_i915_private *dev_priv = to_i915(dev);
>> >> > + struct drm_property *prop;
>> >> > +
>> >> > + prop = dev_priv->multi_segment_gamma_mode_property;
>> >> > + if (!prop) {
>> >> > + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
>> >> > + "Multi-segment Gamma",
>> >> > 0);
>> >> > + if (!prop)
>> >> > + return;
>> >> > +
>> >> > + dev_priv->multi_segment_gamma_mode_property = prop;
>> >> > + }
>> >> > +
>> >> > + drm_object_attach_property(>base.base, prop, 0); }
>> >> > +
>> >> > /*
>> >> > * When using limited range, multiply the matrix given by
>> >> > userspace by
>> >> > * the matrix that we would use for the limited range.
>> >> > @@ -953,4 +973,7 @@ void intel_color_init(struct intel_crtc *crtc)
>> >> >INTEL_INFO(dev_priv)-
>> >> > >color.gamma_lut_size);
>> >> >
>> >> > intel_attach_gamma_mode_property(crtc);
>> >> > +
>> >> > + if (INTEL_GEN(dev_priv) >= 11)
>> >> > + intel_attach_multi_segment_gamma_mode_property(crtc)
>> >> > ;
>> >> > }
>> >> > diff --git a/include/uapi/drm/i915_drm.h
>> >> > b/include/uapi/drm/i915_drm.h index aa2d4c7..8f1974e 100644
>> >> > --- a/include/uapi/drm/i915_drm.h
>> >> > +++ b/include/uapi/drm/i915_drm.h
>> >> > @@ -1842,6 +1842,20 @@ struct drm_i915_query_topology_info {
>> >> > __u8 data[];
>> >> > };
>> >> >
>> >> > +/*
>> >> > + * Structure for muti segmented gamma lut */ struct
>> >> > +multi_segment_gamma_lut {
>> >> > + /* Number of Lut Segments */
>> >> > + __u8 segment_cnt;
>> >> > + /* Precison of LUT entries in bits */
>> >> > + __u8 precision_bits;
>> >> > + /* Pointer having number of LUT elements in each segment */
>> >> > + __u32 *segment_lut_cnt_ptr;
>> >> > + /* Pointer to store exact lut values for each segment */
>> >> > + __u32 *segment_lut_ptr;
>> >> > +};
>> >> >
>> >> And perhaps a variation of this as description for all gamma mode
>> >> types.
>> >
>> >This is my old idea how to represent fancier LUTs:
>> >https://github.com/vsyrjala/linux/commit/1aab7625dca77b831e05e32af179
>> >04c2130
>> >0ff95
>> >https://github.com/vsyrjala/linux/commit/74ffa5d441702c53830f6d71bb68
>> >7bb0ae5a
>> >a58f
>> >
>> >Each distinct segment of
Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Assign genlock CRTC pointer in all slave CRTC states for tiled displays
On Thu, Mar 28, 2019 at 11:32:18AM +0200, Jani Nikula wrote:
> On Thu, 21 Mar 2019, Manasi Navare wrote:
> > In case of tiled displays when the two tiles are sent across two CRTCs
> > over two separate DP SST connectors, we need a mechanism to synchronize
> > the two CRTCs and their corresponding transcoders.
> > So use the master-slave mode where there is one master corresponding
> > to last horizontal and vertical tile that needs to be genlocked with
> > all other slave tiles.
> > This patch identifies saves the master CRTC pointer in all the slave
> > CRTC states. This pointer is needed to select the master CRTC/transcoder
> > while configuring transcoder port sync for the corresponding slaves.
> >
> > Cc: Daniel Vetter
> > Cc: Ville Syrjälä
> > Cc: Maarten Lankhorst
> > Cc: Matt Roper
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 84
> > drivers/gpu/drm/i915/intel_drv.h | 3 +
> > 2 files changed, 87 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 8ff7aa8cb3cf..9980a4ed8c9c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -11281,6 +11281,86 @@ static int icl_check_nv12_planes(struct
> > intel_crtc_state *crtc_state)
> > return 0;
> > }
> >
> > +static int icl_add_genlock_crtcs(struct drm_device *dev,
> > +struct drm_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct drm_connector *genlock_connector, *connector;
> > + struct drm_connector_state *connector_state;
> > + struct drm_connector_list_iter conn_iter;
> > + struct drm_crtc *genlock_crtc = NULL;
> > + struct drm_crtc_state *genlock_crtc_state;
> > + struct intel_crtc_state *slave_crtc_state;
> > + int i, tile_group_id;
> > +
> > + if (INTEL_GEN(dev_priv) < 11)
> > + return 0;
> > +
> > + /*
> > +* In case of tiled displays there could be one or more slaves but
> > there is
> > +* only one master. Lets make the CRTC used by the connector
> > corresponding
> > +* to the last horizonal and last vertical tile a master/genlock CRTC.
> > +* All the other CRTCs corresponding to other tiles of the same Tile
> > group
> > +* are the slave CRTCs and hold a pointer to their genlock CRTC.
> > +*/
> > + for_each_new_connector_in_state(state, connector, connector_state, i) {
> > + if (!connector_state->crtc)
> > + continue;
> > + if (!connector->has_tile)
> > + continue;
> > + if (connector->tile_h_loc == connector->num_h_tile - 1 &&
> > + connector->tile_v_loc == connector->num_v_tile - 1)
> > + continue;
> > + slave_crtc_state = to_intel_crtc_state(
> > + drm_atomic_get_new_crtc_state(state,
> > + connector_state->crtc));
> > + slave_crtc_state->genlock_crtc = NULL;
> > + tile_group_id = connector->tile_group->id;
> > + drm_connector_list_iter_begin(dev, _iter);
> > + drm_for_each_connector_iter(genlock_connector, _iter) {
> > + struct drm_connector_state *genlock_conn_state = NULL;
> > +
> > + if (!genlock_connector->has_tile)
> > + continue;
> > + if (genlock_connector->tile_h_loc !=
> > genlock_connector->num_h_tile - 1 ||
> > + genlock_connector->tile_v_loc !=
> > genlock_connector->num_v_tile - 1)
> > + continue;
> > + if (genlock_connector->tile_group->id != tile_group_id)
> > + continue;
> > +
> > + genlock_conn_state =
> > drm_atomic_get_connector_state(state,
> > +
> > genlock_connector);
> > + if (IS_ERR(genlock_conn_state)) {
> > + drm_connector_list_iter_end(_iter);
> > + return PTR_ERR(genlock_conn_state);
> > + }
> > + if (genlock_conn_state->crtc) {
> > + genlock_crtc = genlock_conn_state->crtc;
> > + break;
> > + }
> > + }
> > + drm_connector_list_iter_end(_iter);
>
> The above loop would benefit from being abstracted to a separate
> function. "find genlock master based on tile info"
>
> I wonder if it would work to have each relevant encoder ->compute_config
> hook look for its genlock master instead of adding another top level
> loop.
So are you suggesting adding this directly inside say compute_config() hook
for DP encoder so inside intel_dp_compute_config(), or would it be better to add
just the inner find_genlock_master()
[Intel-gfx] [RESEND PULL] drm-misc-next
Hi Da.*,
Here's the resend with the !CONFIG_FBDEV fix. I'll be sure to update my build
scripts to get a bit more variety in them, hopefully catch something like this
before it gets sent out.
drm-misc-next-2019-03-28-1:
drm-misc-next for 5.2:
UAPI Changes:
- None
Cross-subsystem Changes:
- None
Core Changes:
- Fix compilation when CONFIG_FBDEV not selected (Daniel)
Driver Changes:
- virtio: package function args in virtio_gpu_object_params (Gerd)
Cc: Daniel Vetter
Cc: Gerd Hoffmann
drm-misc-next-2019-03-28:
drm-misc-next for 5.2:
UAPI Changes:
- Remove unused DRM_DISPLAY_INFO_LEN (Ville)
Cross-subsystem Changes:
- None
Core Changes:
- fbdev: Make skip_vt_switch default (Daniel)
- Merge fb_helper_fill_fix, fb_helper_fill_var into fb_helper_fill_info (Daniel)
- Remove unused fields in connector, display_info, and edid_quirks (Ville)
Driver Changes:
- vkms: Fix potential NULL-dereference bug (Kangjie)
Cc: Kangjie Lu
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cheers, Sean
The following changes since commit ff01e6971ecd9ba6a9c0538c46d713f38a751f11:
drm/fourcc: Fix conflicting Y41x definitions (2019-03-21 09:49:04 +0100)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-03-28-1
for you to fetch changes up to 530b28426a94b822b3c03491cde5c9a961d80e7f:
drm/virtio: rework resource creation workflow. (2019-03-28 12:11:56 +0100)
drm-misc-next for 5.2:
UAPI Changes:
- None
Cross-subsystem Changes:
- None
Core Changes:
- Fix compilation when CONFIG_FBDEV not selected (Daniel)
Driver Changes:
- virtio: package function args in virtio_gpu_object_params (Gerd)
Cc: Daniel Vetter
Cc: Gerd Hoffmann
Daniel Vetter (25):
drm/hibmc: Drop best_encoder
drm/doc: Drop "content type" from the legacy kms property table
drm/fbdev: Make skip_vt_switch the default
drm/fb-helper: Add fill_info() functions
drm/fb-helper: set fbi->fix.id in fill_info()
drm/fb_helper: set info->par in fill_info()
drm/amdgpu: Use drm_fb_helper_fill_info
drm/armada: Use drm_fb_helper_fill_info
drm/ast: Use drm_fb_helper_fill_info
drm/cirrus: Use drm_fb_helper_fill_info
drm/exynos: Use drm_fb_helper_fill_info
drm/gma500: Use drm_fb_helper_fill_info
drm/hibmc: Use drm_fb_helper_fill_info
drm/i915: Use drm_fb_helper_fill_info
drm/mga200g: Use drm_fb_helper_fill_info
drm/msm: Use drm_fb_helper_fill_info
drm/nouveau: Use drm_fb_helper_fill_info
drm/omap: Use drm_fb_helper_fill_info
drm/radeon: Use drm_fb_helper_fill_info
drm/rockchip: Use drm_fb_helper_fill_info
drm/tegra: Use drm_fb_helper_fill_info
drm/vboxvideo: Use drm_fb_helper_fill_info
drm/udl: Use drm_fb_helper_fill_info
drm/fb-helper: Unexport fill_{var,info}
drm/fb-helper: Fixup fill_info cleanup
Gerd Hoffmann (6):
drm/virtio: add virtio-gpu-features debugfs file.
drm/virtio: move virtio_gpu_object_{attach, detach} calls.
drm/virtio: use struct to pass params to virtio_gpu_object_create()
drm/virtio: params struct for virtio_gpu_cmd_create_resource()
drm/virtio: params struct for virtio_gpu_cmd_create_resource_3d()
drm/virtio: rework resource creation workflow.
Kangjie Lu (1):
drm: vkms: check status of alloc_ordered_workqueue
Luca Ceresoli (1):
drm/doc: fix missing verb
Ville Syrjälä (5):
drm: Nuke unused drm_display_info.pixel_clock
drm: Fix tabs vs. spaces
drm: Kill drm_display_info.name
drm/uapi: Remove unused DRM_DISPLAY_INFO_LEN
drm/edid: Remove defunct EDID_QUIRK_FIRST_DETAILED_PREFERRED
YueHaibing (1):
drm/virtio: remove set but not used variable 'vgdev'
Documentation/gpu/kms-properties.csv | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 25 ++---
drivers/gpu/drm/armada/armada_fbdev.c | 6 +-
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_fb.c | 7 +-
drivers/gpu/drm/cirrus/cirrus_drv.h| 2 +-
drivers/gpu/drm/cirrus/cirrus_fbdev.c | 8 +-
drivers/gpu/drm/drm_edid.c | 10 --
drivers/gpu/drm/drm_fb_helper.c| 80 ---
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 4 +-
drivers/gpu/drm/gma500/framebuffer.c | 7 +-
drivers/gpu/drm/gma500/framebuffer.h | 2 +-
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h| 2 +-
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c | 9 +-
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 7 --
drivers/gpu/drm/i915/i915_debugfs.c| 1 -
drivers/gpu/drm/i915/intel_fbdev.c | 10 +-
drivers/gpu/drm/mgag200/mgag200_drv.h | 2 +-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Fix clockgating issue when using scalars (rev4)
== Series Details == Series: drm/i915/icl: Fix clockgating issue when using scalars (rev4) URL : https://patchwork.freedesktop.org/series/58081/ State : success == Summary == CI Bug Log - changes from CI_DRM_5831 -> Patchwork_12620 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58081/revisions/4/mbox/ Known issues Here are the changes found in Patchwork_12620 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_uncore: - fi-ivb-3770:PASS -> DMESG-FAIL [fdo#110210] * igt@kms_busy@basic-flip-a: - fi-gdg-551: PASS -> FAIL [fdo#103182] +1 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 Participating hosts (43 -> 39) -- Missing(4): fi-kbl-soraka fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u Build changes - * Linux: CI_DRM_5831 -> Patchwork_12620 CI_DRM_5831: 8cac0cc264d2a6af0b33370b542b12d516e022c5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4911: d9fe699ea45406e279b78d1afdb4d57a205a3c99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12620: e5918f3b5230833b3c747e0501bc592aec8dc2b9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e5918f3b5230 drm/i915/icl: Fix clockgating issue when using scalers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12620/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] drm-intel-fixes
On Thu, 28 Mar 2019, Jani Nikula wrote: > Hi Dave and Daniel, a fairly normal fixes pull. > > drm-intel-fixes-2019-03-28: > drm/i915 fixes for v5.2-rc3: > - fix mmap range checks > - fix gvt ppgtt mm LRU list access races > - fix selftest error pointer check > - fix a macro definition (pre-emptive for potential further backports) > - fix one AML SKU ULX status Hum, the log dim opened in gitk failed to include some of the gvt changes listed in the changelog below. The gvt merge commit additionally lists: - Fix MI_FLUSH_DW cmd parser on index check (Zhenyu) - Fix Windows guest font render error (Colin) - Fix unexpected workload submission for inactive vGPU (Weinan) - Fix incorrect workload submission in error path (Zhenyu) - Fix warning for shadow ppgtt mm reclaim list walk with locking (Zhenyu) BR, Jani. > > BR, > Jani. > > The following changes since commit 000c4f90e3f0194eef218ff2c6a8fd8ca1de4313: > > drm/i915: Sanity check mmap length against object size (2019-03-18 13:59:42 > -0700) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-03-28 > > for you to fetch changes up to 26cdaac4793c49357d2c731f2190632cefb7efb1: > > drm/i915/icl: Fix VEBOX mismatch BUG_ON() (2019-03-28 15:36:40 +0200) > > > drm/i915 fixes for v5.2-rc3: > - fix mmap range checks > - fix gvt ppgtt mm LRU list access races > - fix selftest error pointer check > - fix a macro definition (pre-emptive for potential further backports) > - fix one AML SKU ULX status > > > Colin Xu (1): > drm/i915/gvt: Add in context mmio 0x20D8 to gen9 mmio list > > Dan Carpenter (1): > drm/i915/selftests: Fix an IS_ERR() vs NULL check > > José Roberto de Souza (1): > drm/i915/icl: Fix VEBOX mismatch BUG_ON() > > Manasi Navare (1): > drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro > > Rodrigo Vivi (1): > Merge tag 'gvt-fixes-2019-03-21' of https://github.com/intel/gvt-linux > into drm-intel-fixes > > Ville Syrjälä (1): > drm/i915: Mark AML 0x87CA as ULX > > Weinan Li (1): > drm/i915/gvt: stop scheduling workload when vgpu is inactive > > Zhenyu Wang (4): > drm/i915/gvt: Fix MI_FLUSH_DW parsing with correct index check > drm/i915/gvt: Don't submit request for error workload dispatch > drm/i915/gvt: Only assign ppgtt root at dispatch time > drm/i915/gvt: Add mutual lock for ppgtt mm LRU list > > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- > drivers/gpu/drm/i915/gvt/gtt.c | 14 - > drivers/gpu/drm/i915/gvt/gtt.h | 1 + > drivers/gpu/drm/i915/gvt/mmio_context.c | 1 + > drivers/gpu/drm/i915/gvt/scheduler.c| 28 > ++--- > drivers/gpu/drm/i915/i915_drv.h | 3 ++- > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +- > 8 files changed, 41 insertions(+), 14 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] gpu:drm: Remove duplicate headers
On Fri, 29 Mar 2019, Jagadeesh Pagadala wrote:
> On Thu, Mar 28, 2019 at 04:12:10PM +0200, Laurent Pinchart wrote:
>> Hi Jagadeesh,
>>
>> On Thu, Mar 28, 2019 at 09:32:06PM +0530, Jagadeesh Pagadala wrote:
>> > On Thu, Mar 28, 2019 at 08:51:24AM +0200, Laurent Pinchart wrote:
>> > > On Thu, Mar 28, 2019 at 02:41:56AM +0530, jagdsh.li...@gmail.com wrote:
>> > > > From: Jagadeesh Pagadala
>> > > >
>> > > > Remove duplicate headers which are included twice.
>> > >
>> > > Could you, while at it, also sort the existing #include statements
>> > > alphabetically ? This should help avoiding similar issues in the future.
>> > >
>> > > > Signed-off-by: Jagadeesh Pagadala
>> > > > ---
>> > > > drivers/gpu/drm/bridge/panel.c | 1 -
>> > > > drivers/gpu/drm/i915/intel_display.c | 7 ---
>> > > > 2 files changed, 8 deletions(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/bridge/panel.c
>> > > > b/drivers/gpu/drm/bridge/panel.c
>> > > > index 38eeaf8..eb9567d 100644
>> > > > --- a/drivers/gpu/drm/bridge/panel.c
>> > > > +++ b/drivers/gpu/drm/bridge/panel.c
>> > > > @@ -15,7 +15,6 @@
>> > > > #include
>> > > > #include
>> > > > #include
>> > > > -#include
>> > > >
>> > > > struct panel_bridge {
>> > > >struct drm_bridge bridge;
>> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
>> > > > b/drivers/gpu/drm/i915/intel_display.c
>> > > > index ccb6163..1166342 100644
>> > > > --- a/drivers/gpu/drm/i915/intel_display.c
>> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > > > @@ -51,14 +51,7 @@
>> > > > #include "intel_dsi.h"
>> > > > #include "intel_frontbuffer.h"
>> > > >
>> > > > -#include "intel_drv.h"
>> > > > -#include "intel_dsi.h"
>> > > > -#include "intel_frontbuffer.h"
>> > > > -
>> > > > -#include "i915_drv.h"
>> > > > -#include "i915_gem_clflush.h"
>> > > > #include "i915_reset.h"
>> > > > -#include "i915_trace.h"
>> > > >
>> > > > /* Primary plane formats for gen <= 3 */
>> > > > static const u32 i8xx_primary_formats[] = {
>>
>> > From c9a68b204fe4bb013c2b8481ca8239c957dd69cc Mon Sep 17 00:00:00 2001
>> > From: Jagadeesh Pagadala
>> > Date: Thu, 28 Mar 2019 21:20:12 +0530
>> > Subject: [PATCH] gpu:drm: sort the existing #includes alphabetically
>> >
>> > Hi Laurent,
>> >
>> > Hopefully this helps.
>>
>> It does, thanks. If you squash it with your original patch and send a
>> v2, you can add my
>>
>> Reviewed-by: Laurent Pinchart
>>
>> > Signed-off-by: Jagadeesh Pagadala
>> > ---
>> > drivers/gpu/drm/bridge/panel.c | 2 +-
>> > drivers/gpu/drm/i915/intel_display.c | 4 ++--
>> > 2 files changed, 3 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/bridge/panel.c
>> > b/drivers/gpu/drm/bridge/panel.c
>> > index eb9567d..000ba7c 100644
>> > --- a/drivers/gpu/drm/bridge/panel.c
>> > +++ b/drivers/gpu/drm/bridge/panel.c
>> > @@ -9,11 +9,11 @@
>> > */
>> >
>> > #include
>> > -#include
>> > #include
>> > #include
>> > #include
>> > #include
>> > +#include
>> > #include
>> >
>> > struct panel_bridge {
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c
>> > b/drivers/gpu/drm/i915/intel_display.c
>> > index 1166342..7956e89 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -46,13 +46,13 @@
>> >
>> > #include "i915_drv.h"
>> > #include "i915_gem_clflush.h"
>> > +#include "i915_reset.h"
>> > #include "i915_trace.h"
>> > +
>> > #include "intel_drv.h"
>> > #include "intel_dsi.h"
>> > #include "intel_frontbuffer.h"
>> >
>> > -#include "i915_reset.h"
>> > -
>> > /* Primary plane formats for gen <= 3 */
>> > static const u32 i8xx_primary_formats[] = {
>> >DRM_FORMAT_C8,
>>
>> --
>> Regards,
>>
>> Laurent Pinchart
> From 25776c74d289f8c2e6c89d8838f3110981ce2515 Mon Sep 17 00:00:00 2001
> From: Jagadeesh Pagadala
> Date: Fri, 29 Mar 2019 00:04:29 +0530
> Subject: [PATCH v2] gpu:drm: Remove duplicate headers
>
> 1. Remove duplicate headers which are included twice.
> 2. Sort the existing #includes alphabetically
>
> Signed-off-by: Jagadeesh Pagadala
>
> Reviewed-by: Laurent Pinchart
For further reference, please see how to use git send-email to reply to
previous versions instead of attaching. Also see 'git log --
drivers/gpu/drm' on the subject prefix; nobody uses "gpu:drm:".
Acked-by: Jani Nikula
for merging via drm-misc
> ---
> drivers/gpu/drm/bridge/panel.c | 3 +--
> drivers/gpu/drm/i915/intel_display.c | 9 +
> 2 files changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
> index 38eeaf8..000ba7c 100644
> --- a/drivers/gpu/drm/bridge/panel.c
> +++ b/drivers/gpu/drm/bridge/panel.c
> @@ -9,13 +9,12 @@
> */
>
> #include
> -#include
> #include
> #include
> #include
> #include
> -#include
> #include
> +#include
>
> struct panel_bridge {
> struct drm_bridge bridge;
> diff --git
[Intel-gfx] [PATCH] drm/i915: move the edram detection out of uncore init
edram is not part of uncore and there is no requirement for the
detection to be done before we initialize the uncore functions. The
first check on HAS_EDRAM is in the ggtt_init path, so move it to
i915_driver_init_hw, where other dram-related detection happens.
While at it, save the size in MB instead of the capabilities because the
size is the only thing we look at outside of the init function.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +--
drivers/gpu/drm/i915/i915_drv.c | 42 ++
drivers/gpu/drm/i915/i915_drv.h | 9 --
drivers/gpu/drm/i915/intel_uncore.c | 46 -
drivers/gpu/drm/i915/intel_uncore.h | 1 -
5 files changed, 50 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 652f65d2e131..f93a043f033a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2087,8 +2087,8 @@ static int i915_llc(struct seq_file *m, void *data)
const bool edram = INTEL_GEN(dev_priv) > 8;
seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
- seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
- intel_uncore_edram_size(dev_priv)/1024/1024);
+ seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
+ dev_priv->edram_size_mb);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bbe1a5d56480..4d5f3f2d94ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1441,6 +1441,45 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
dram_info->ranks, yesno(dram_info->is_16gb_dimm));
}
+static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
+{
+ const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
+ const unsigned int sets[4] = { 1, 1, 2, 2 };
+
+ return EDRAM_NUM_BANKS(cap) *
+ ways[EDRAM_WAYS_IDX(cap)] *
+ sets[EDRAM_SETS_IDX(cap)];
+}
+
+static void edram_detect(struct drm_i915_private *dev_priv)
+{
+ u32 edram_cap = 0;
+
+ if (!(IS_HASWELL(dev_priv) ||
+ IS_BROADWELL(dev_priv) ||
+ INTEL_GEN(dev_priv) >= 9))
+ return;
+
+ edram_cap = __raw_uncore_read32(_priv->uncore, HSW_EDRAM_CAP);
+
+ /* NB: We can't write IDICR yet because we don't have gt funcs set up */
+
+ if (!(edram_cap & EDRAM_ENABLED))
+ return;
+
+ /*
+* The needed capability bits for size calculation are not there with
+* pre gen9 so return 128MB always.
+*/
+ if (INTEL_GEN(dev_priv) < 9)
+ dev_priv->edram_size_mb = 128;
+ else
+ dev_priv->edram_size_mb =
+ gen9_edram_size_mb(dev_priv, edram_cap);
+
+ DRM_INFO("Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
+}
+
/**
* i915_driver_init_hw - setup state requiring device access
* @dev_priv: device private
@@ -1483,6 +1522,9 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
intel_sanitize_options(dev_priv);
+ /* needs to be done before ggtt probe */
+ edram_detect(dev_priv);
+
i915_perf_init(dev_priv);
ret = i915_ggtt_probe_hw(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b05687ed91ef..3c6b31f94278 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1706,8 +1706,11 @@ struct drm_i915_private {
struct intel_l3_parity l3_parity;
- /* Cannot be determined by PCIID. You must always read a register. */
- u32 edram_cap;
+ /*
+* edram size in MB.
+* Cannot be determined by PCIID. You must always read a register.
+*/
+ u32 edram_size_mb;
/*
* Protects RPS/RC6 register access and PCU communication.
@@ -2467,7 +2470,7 @@ static inline unsigned int i915_sg_segment_size(void)
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
#define HAS_SNOOP(dev_priv)(INTEL_INFO(dev_priv)->has_snoop)
-#define HAS_EDRAM(dev_priv)(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
+#define HAS_EDRAM(dev_priv)((dev_priv)->edram_size_mb > 0)
#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 5c80704bf283..106df24f20a5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -420,51 +420,6 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
return fw; /* track the lost user forcewake domains */
}
-static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
-{
- const
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, a fairly normal fixes pull. drm-intel-fixes-2019-03-28: drm/i915 fixes for v5.2-rc3: - fix mmap range checks - fix gvt ppgtt mm LRU list access races - fix selftest error pointer check - fix a macro definition (pre-emptive for potential further backports) - fix one AML SKU ULX status BR, Jani. The following changes since commit 000c4f90e3f0194eef218ff2c6a8fd8ca1de4313: drm/i915: Sanity check mmap length against object size (2019-03-18 13:59:42 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-03-28 for you to fetch changes up to 26cdaac4793c49357d2c731f2190632cefb7efb1: drm/i915/icl: Fix VEBOX mismatch BUG_ON() (2019-03-28 15:36:40 +0200) drm/i915 fixes for v5.2-rc3: - fix mmap range checks - fix gvt ppgtt mm LRU list access races - fix selftest error pointer check - fix a macro definition (pre-emptive for potential further backports) - fix one AML SKU ULX status Colin Xu (1): drm/i915/gvt: Add in context mmio 0x20D8 to gen9 mmio list Dan Carpenter (1): drm/i915/selftests: Fix an IS_ERR() vs NULL check José Roberto de Souza (1): drm/i915/icl: Fix VEBOX mismatch BUG_ON() Manasi Navare (1): drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro Rodrigo Vivi (1): Merge tag 'gvt-fixes-2019-03-21' of https://github.com/intel/gvt-linux into drm-intel-fixes Ville Syrjälä (1): drm/i915: Mark AML 0x87CA as ULX Weinan Li (1): drm/i915/gvt: stop scheduling workload when vgpu is inactive Zhenyu Wang (4): drm/i915/gvt: Fix MI_FLUSH_DW parsing with correct index check drm/i915/gvt: Don't submit request for error workload dispatch drm/i915/gvt: Only assign ppgtt root at dispatch time drm/i915/gvt: Add mutual lock for ppgtt mm LRU list drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- drivers/gpu/drm/i915/gvt/gtt.c | 14 - drivers/gpu/drm/i915/gvt/gtt.h | 1 + drivers/gpu/drm/i915/gvt/mmio_context.c | 1 + drivers/gpu/drm/i915/gvt/scheduler.c| 28 ++--- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +- 8 files changed, 41 insertions(+), 14 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Clean up intel_color_check() (rev2)
== Series Details == Series: drm/i915: Clean up intel_color_check() (rev2) URL : https://patchwork.freedesktop.org/series/58137/ State : success == Summary == CI Bug Log - changes from CI_DRM_5829_full -> Patchwork_12618_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12618_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@fifo-bsd2: - shard-snb: NOTRUN -> SKIP [fdo#109271] +68 * igt@gem_pwrite@stolen-normal: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +20 - shard-skl: NOTRUN -> SKIP [fdo#109271] +57 * igt@i915_pm_rpm@gem-mmap-gtt: - shard-skl: PASS -> INCOMPLETE [fdo#107807] +1 * igt@kms_available_modes_crc@available_mode_test_crc: - shard-iclb: PASS -> FAIL [fdo#106641] - shard-snb: PASS -> FAIL [fdo#106641] * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-f: - shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-pageflip-hang-newfb-render-a: - shard-glk: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-glk: PASS -> DMESG-WARN [fdo#110222] * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: PASS -> FAIL [fdo#105363] - shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-glk: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#109247] +21 * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt: - shard-glk: NOTRUN -> SKIP [fdo#109271] +17 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3 - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-glk: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_psr@cursor_mmap_gtt: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +4 * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: PASS -> SKIP [fdo#109441] +2 * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: PASS -> DMESG-FAIL [fdo#105763] * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0: - shard-iclb: PASS -> INCOMPLETE [fdo#110026] / [fdo#110040 ] * igt@kms_rotation_crc@sprite-rotation-270: - shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133] * igt@kms_universal_plane@universal-plane-gen9-features-pipe-e: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6 Possible fixes * igt@gem_softpin@noreloc-s3: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS * igt@gem_tiled_pread_pwrite: - shard-iclb: TIMEOUT [fdo#109673] -> PASS * igt@kms_color@pipe-a-degamma: - shard-glk: FAIL [fdo#104782] / [fdo#108145] -> PASS * igt@kms_color@pipe-c-degamma: - shard-glk: FAIL [fdo#104782] -> PASS +1 * igt@kms_cursor_crc@cursor-256x85-random: - shard-skl: FAIL [fdo#103232] -> PASS * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: INCOMPLETE [fdo#109507] -> PASS * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: FAIL [fdo#103167] -> PASS +3 * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt: - shard-skl: FAIL [fdo#103167] -> PASS +2 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt: - shard-iclb: FAIL [fdo#109247] -> PASS +7 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-skl: FAIL [fdo#103191] / [fdo#107362] -> PASS * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: FAIL [fdo#108145] -> PASS * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: FAIL [fdo#107815] -> PASS * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: - shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS * igt@kms_psr@primary_blt: - shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS +1 * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: - shard-kbl: DMESG-FAIL [fdo#105763] -> PASS * igt@kms_setmode@basic:
[Intel-gfx] [PATCH v4] drm/i915/icl: Fix clockgating issue when using scalers
Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)
V2: Fix typo in headline(Chris)
Handle the non double buffered nature of the register(Ville)
V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks unrelated.
V4: Split the icl and skl wa's(Ville)
Cc: Chris Wilson
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Aditya Swarup
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 48
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799f2..c3ca9cfd36fe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -466,6 +466,7 @@ static const struct intel_limit intel_limits_bxt = {
.p2 = { .p2_slow = 1, .p2_fast = 20 },
};
+/* WA Display #0827: Gen9:all */
static void
skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
{
@@ -478,6 +479,17 @@ skl_wa_clkgate(struct drm_i915_private *dev_priv, int
pipe, bool enable)
~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
}
+/* Wa_2006604312:icl */
+static void
+icl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
+{
+ if (enable)
+ I915_WRITE(CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS);
+ else
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
+}
+
static bool
needs_modeset(const struct drm_crtc_state *state)
{
@@ -5481,14 +5493,18 @@ static bool hsw_post_update_enable_ips(const struct
intel_crtc_state *old_crtc_s
return !old_crtc_state->ips_enabled;
}
-static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+static bool skl_needs_clk_wa(struct drm_i915_private *dev_priv,
+const struct intel_crtc_state *crtc_state)
{
- if (!crtc_state->nv12_planes)
- return false;
-
/* WA Display #0827: Gen9:all */
- if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
+ if (!!crtc_state->nv12_planes && IS_GEN(dev_priv, 9) &&
+ !IS_GEMINILAKE(dev_priv))
+ return true;
+
+ /*
+* Wa_2006604312:icl
+*/
+ if (IS_ICELAKE(dev_priv) && crtc_state->pch_pfit.enabled)
return true;
return false;
@@ -5527,10 +5543,12 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
intel_post_enable_primary(>base, pipe_config);
}
- /* Display WA 827 */
- if (needs_nv12_wa(dev_priv, old_crtc_state) &&
- !needs_nv12_wa(dev_priv, pipe_config)) {
- skl_wa_clkgate(dev_priv, crtc->pipe, false);
+ if (skl_needs_clk_wa(dev_priv, old_crtc_state) &&
+ !skl_needs_clk_wa(dev_priv, pipe_config)) {
+ if (IS_ICELAKE(dev_priv))
+ icl_wa_clkgate(dev_priv, crtc->pipe, false);
+ else
+ skl_wa_clkgate(dev_priv, crtc->pipe, false);
}
}
@@ -5566,10 +5584,12 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv,
crtc->pipe, false);
}
- /* Display WA 827 */
- if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
- needs_nv12_wa(dev_priv, pipe_config)) {
- skl_wa_clkgate(dev_priv, crtc->pipe, true);
+ if (!skl_needs_clk_wa(dev_priv, old_crtc_state) &&
+ skl_needs_clk_wa(dev_priv, pipe_config)) {
+ if (IS_ICELAKE(dev_priv))
+ icl_wa_clkgate(dev_priv, crtc->pipe, true);
+ else
+ skl_wa_clkgate(dev_priv, crtc->pipe, true);
}
/*
--
2.20.0.rc2.7.g965798d1f299
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] drm-misc-next
On Thu, Mar 28, 2019 at 4:33 PM Sean Paul wrote:
>
>
> Hi Da.*,
> This week's -next pull is here! A couple of things to monitor in this one, the
> skip_vt_switch default and the DRM_DISPLAY_INFO_LEN removal (which definitely
> shouldn't be used by anyone, but stranger things have happened).
>
> Please pull.
>
>
> drm-misc-next-2019-03-28:
> drm-misc-next for 5.2:
>
> UAPI Changes:
> - Remove unused DRM_DISPLAY_INFO_LEN (Ville)
>
> Cross-subsystem Changes:
> - None
>
> Core Changes:
> - fbdev: Make skip_vt_switch default (Daniel)
> - Merge fb_helper_fill_fix, fb_helper_fill_var into fb_helper_fill_info
> (Daniel)
> - Remove unused fields in connector, display_info, and edid_quirks (Ville)
>
> Driver Changes:
> - vkms: Fix potential NULL-dereference bug (Kangjie)
>
> Cc: Kangjie Lu
> Cc: Daniel Vetter
> Cc: Ville Syrjälä
Uh, can you pls respin with
commit ec8bf1942567bf0736314da9723e93bcc73c131f
Author: Daniel Vetter
Date: Wed Mar 27 13:58:19 2019 +0100
drm/fb-helper: Fixup fill_info cleanup
included? Doesn't compile too well for !CONFIG_FBDEV otherwise. Sorry
for the mess.
-Daniel
>
> Cheers, Sean
>
>
> The following changes since commit ff01e6971ecd9ba6a9c0538c46d713f38a751f11:
>
> drm/fourcc: Fix conflicting Y41x definitions (2019-03-21 09:49:04 +0100)
>
> are available in the Git repository at:
>
> git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-03-28
>
> for you to fetch changes up to 9d5549d8a865793a1faf6ac9a48df08a3e850af6:
>
> drm/edid: Remove defunct EDID_QUIRK_FIRST_DETAILED_PREFERRED (2019-03-27
> 13:55:13 +0200)
>
>
> drm-misc-next for 5.2:
>
> UAPI Changes:
> - Remove unused DRM_DISPLAY_INFO_LEN (Ville)
>
> Cross-subsystem Changes:
> - None
>
> Core Changes:
> - fbdev: Make skip_vt_switch default (Daniel)
> - Merge fb_helper_fill_fix, fb_helper_fill_var into fb_helper_fill_info
> (Daniel)
> - Remove unused fields in connector, display_info, and edid_quirks (Ville)
>
> Driver Changes:
> - vkms: Fix potential NULL-dereference bug (Kangjie)
>
> Cc: Kangjie Lu
> Cc: Daniel Vetter
> Cc: Ville Syrjälä
>
>
> Daniel Vetter (24):
> drm/hibmc: Drop best_encoder
> drm/doc: Drop "content type" from the legacy kms property table
> drm/fbdev: Make skip_vt_switch the default
> drm/fb-helper: Add fill_info() functions
> drm/fb-helper: set fbi->fix.id in fill_info()
> drm/fb_helper: set info->par in fill_info()
> drm/amdgpu: Use drm_fb_helper_fill_info
> drm/armada: Use drm_fb_helper_fill_info
> drm/ast: Use drm_fb_helper_fill_info
> drm/cirrus: Use drm_fb_helper_fill_info
> drm/exynos: Use drm_fb_helper_fill_info
> drm/gma500: Use drm_fb_helper_fill_info
> drm/hibmc: Use drm_fb_helper_fill_info
> drm/i915: Use drm_fb_helper_fill_info
> drm/mga200g: Use drm_fb_helper_fill_info
> drm/msm: Use drm_fb_helper_fill_info
> drm/nouveau: Use drm_fb_helper_fill_info
> drm/omap: Use drm_fb_helper_fill_info
> drm/radeon: Use drm_fb_helper_fill_info
> drm/rockchip: Use drm_fb_helper_fill_info
> drm/tegra: Use drm_fb_helper_fill_info
> drm/vboxvideo: Use drm_fb_helper_fill_info
> drm/udl: Use drm_fb_helper_fill_info
> drm/fb-helper: Unexport fill_{var,info}
>
> Kangjie Lu (1):
> drm: vkms: check status of alloc_ordered_workqueue
>
> Luca Ceresoli (1):
> drm/doc: fix missing verb
>
> Ville Syrjälä (5):
> drm: Nuke unused drm_display_info.pixel_clock
> drm: Fix tabs vs. spaces
> drm: Kill drm_display_info.name
> drm/uapi: Remove unused DRM_DISPLAY_INFO_LEN
> drm/edid: Remove defunct EDID_QUIRK_FIRST_DETAILED_PREFERRED
>
> Documentation/gpu/kms-properties.csv | 1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 25 +++-
> drivers/gpu/drm/armada/armada_fbdev.c | 6 +-
> drivers/gpu/drm/ast/ast_drv.h | 2 +-
> drivers/gpu/drm/ast/ast_fb.c | 7 +-
> drivers/gpu/drm/cirrus/cirrus_drv.h| 2 +-
> drivers/gpu/drm/cirrus/cirrus_fbdev.c | 8 +--
> drivers/gpu/drm/drm_edid.c | 10 ---
> drivers/gpu/drm/drm_fb_helper.c| 75
> +++---
> drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 4 +-
> drivers/gpu/drm/gma500/framebuffer.c | 7 +-
> drivers/gpu/drm/gma500/framebuffer.h | 2 +-
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h| 2 +-
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c | 9 +--
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 7 --
> drivers/gpu/drm/i915/i915_debugfs.c| 1 -
> drivers/gpu/drm/i915/intel_fbdev.c | 10 +--
> drivers/gpu/drm/mgag200/mgag200_drv.h | 2 +-
>
Re: [Intel-gfx] RMW considered harmful (was: Re: [PATCH 2/2] drm/i915/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports)
On Thu, Mar 28, 2019 at 11:18:56AM +0200, Jani Nikula wrote: > On Fri, 22 Mar 2019, Manasi Navare wrote: > > On Fri, Mar 22, 2019 at 09:28:01PM +0200, Jani Nikula wrote: > >> On Fri, 22 Mar 2019, Ville Syrjälä wrote: > >> > On Fri, Mar 22, 2019 at 11:44:21AM -0700, Manasi Navare wrote: > >> >> On Fri, Mar 22, 2019 at 08:09:50PM +0200, Ville Syrjälä wrote: > >> >> > In that case there is no point in doing a rmw. > >> >> > >> >> But isnt it always a good idea to do rmw? I mean what if the master > >> >> select was set to something else earlier? > >> > > >> > RMW is the root of many evils. It should be avoided unless there is a > >> > really compelling reason to use it. > >> > >> Hear, hear! > >> > >> We have the software state that we want to write to the hardware. If we > >> use RMW to do this, it might all work by coincidence due to the old > >> values in the registers, or it might just as well break by coincidence > >> due to some garbage in the registers. > >> > >> In most cases, there should only be one place that writes a particular > >> display register during modeset. Sometimes this isn't possible, and RMW > >> is required. > >> > >> Some registers also have reserved bits potentially used by the hardware > >> that must not be changed, and RMW is required. These are documented in > >> bspec. > >> > >> BR, > >> Jani. > >> > > > > Thanks for the explanation. It does make sense now that we are doing a > > full modeset, we should just be then writing the value directly? The > > only concern I have is that say DSI code sets this somewhere els ein > > the modeset path, then we would need to modify this to do RMW or > > always make sure DSI also uses the same function for writing to this > > reg. What do you suggest doing now? > > I think all encoders in a tile group are always of the same type. Yes all the encoders in tile group are always same type. > > If the tile grouping in your patch is based purely on EDID, we may need > to enforce this. Surely genlock only works on encoders of the same type? > So all the slaves and their master will always be of same type and yes it is based on the EDID tile block parsing. But just to double sure I think when i assign the master slave pointers, I should check that the connector type is the same. > In any case DSI (at least currently) does not use tile groups, and will > never be mixed up in non-DSI tile groups. The DSI transcoders are > separate from other transcoders, so we're not writing the same registers > here. > > --- > > Looking at the code, I am wondering if this should be pushed to encoder > hooks instead of adding into crtc enable. As per the Bspec sequence, this needs to happen before enabling the TRANS_DDI_FUNC_CTL and after the link training, so I put in the crtc_enable hook, which encoder hooks are you suggesting adding this? Regards Manasi > > BR, > Jani. > > > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-next
Hi Da.*,
This week's -next pull is here! A couple of things to monitor in this one, the
skip_vt_switch default and the DRM_DISPLAY_INFO_LEN removal (which definitely
shouldn't be used by anyone, but stranger things have happened).
Please pull.
drm-misc-next-2019-03-28:
drm-misc-next for 5.2:
UAPI Changes:
- Remove unused DRM_DISPLAY_INFO_LEN (Ville)
Cross-subsystem Changes:
- None
Core Changes:
- fbdev: Make skip_vt_switch default (Daniel)
- Merge fb_helper_fill_fix, fb_helper_fill_var into fb_helper_fill_info (Daniel)
- Remove unused fields in connector, display_info, and edid_quirks (Ville)
Driver Changes:
- vkms: Fix potential NULL-dereference bug (Kangjie)
Cc: Kangjie Lu
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cheers, Sean
The following changes since commit ff01e6971ecd9ba6a9c0538c46d713f38a751f11:
drm/fourcc: Fix conflicting Y41x definitions (2019-03-21 09:49:04 +0100)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-03-28
for you to fetch changes up to 9d5549d8a865793a1faf6ac9a48df08a3e850af6:
drm/edid: Remove defunct EDID_QUIRK_FIRST_DETAILED_PREFERRED (2019-03-27
13:55:13 +0200)
drm-misc-next for 5.2:
UAPI Changes:
- Remove unused DRM_DISPLAY_INFO_LEN (Ville)
Cross-subsystem Changes:
- None
Core Changes:
- fbdev: Make skip_vt_switch default (Daniel)
- Merge fb_helper_fill_fix, fb_helper_fill_var into fb_helper_fill_info (Daniel)
- Remove unused fields in connector, display_info, and edid_quirks (Ville)
Driver Changes:
- vkms: Fix potential NULL-dereference bug (Kangjie)
Cc: Kangjie Lu
Cc: Daniel Vetter
Cc: Ville Syrjälä
Daniel Vetter (24):
drm/hibmc: Drop best_encoder
drm/doc: Drop "content type" from the legacy kms property table
drm/fbdev: Make skip_vt_switch the default
drm/fb-helper: Add fill_info() functions
drm/fb-helper: set fbi->fix.id in fill_info()
drm/fb_helper: set info->par in fill_info()
drm/amdgpu: Use drm_fb_helper_fill_info
drm/armada: Use drm_fb_helper_fill_info
drm/ast: Use drm_fb_helper_fill_info
drm/cirrus: Use drm_fb_helper_fill_info
drm/exynos: Use drm_fb_helper_fill_info
drm/gma500: Use drm_fb_helper_fill_info
drm/hibmc: Use drm_fb_helper_fill_info
drm/i915: Use drm_fb_helper_fill_info
drm/mga200g: Use drm_fb_helper_fill_info
drm/msm: Use drm_fb_helper_fill_info
drm/nouveau: Use drm_fb_helper_fill_info
drm/omap: Use drm_fb_helper_fill_info
drm/radeon: Use drm_fb_helper_fill_info
drm/rockchip: Use drm_fb_helper_fill_info
drm/tegra: Use drm_fb_helper_fill_info
drm/vboxvideo: Use drm_fb_helper_fill_info
drm/udl: Use drm_fb_helper_fill_info
drm/fb-helper: Unexport fill_{var,info}
Kangjie Lu (1):
drm: vkms: check status of alloc_ordered_workqueue
Luca Ceresoli (1):
drm/doc: fix missing verb
Ville Syrjälä (5):
drm: Nuke unused drm_display_info.pixel_clock
drm: Fix tabs vs. spaces
drm: Kill drm_display_info.name
drm/uapi: Remove unused DRM_DISPLAY_INFO_LEN
drm/edid: Remove defunct EDID_QUIRK_FIRST_DETAILED_PREFERRED
Documentation/gpu/kms-properties.csv | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 25 +++-
drivers/gpu/drm/armada/armada_fbdev.c | 6 +-
drivers/gpu/drm/ast/ast_drv.h | 2 +-
drivers/gpu/drm/ast/ast_fb.c | 7 +-
drivers/gpu/drm/cirrus/cirrus_drv.h| 2 +-
drivers/gpu/drm/cirrus/cirrus_fbdev.c | 8 +--
drivers/gpu/drm/drm_edid.c | 10 ---
drivers/gpu/drm/drm_fb_helper.c| 75 +++---
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 4 +-
drivers/gpu/drm/gma500/framebuffer.c | 7 +-
drivers/gpu/drm/gma500/framebuffer.h | 2 +-
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h| 2 +-
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c | 9 +--
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 7 --
drivers/gpu/drm/i915/i915_debugfs.c| 1 -
drivers/gpu/drm/i915/intel_fbdev.c | 10 +--
drivers/gpu/drm/mgag200/mgag200_drv.h | 2 +-
drivers/gpu/drm/mgag200/mgag200_fb.c | 8 +--
drivers/gpu/drm/msm/msm_fbdev.c| 6 +-
drivers/gpu/drm/nouveau/nouveau_fbcon.c| 8 +--
drivers/gpu/drm/nouveau/nouveau_fbcon.h| 2 +-
drivers/gpu/drm/omapdrm/omap_fbdev.c | 6 +-
drivers/gpu/drm/panel/panel-arm-versatile.c| 2 -
drivers/gpu/drm/panel/panel-ilitek-ili9322.c | 2 -
drivers/gpu/drm/panel/panel-olimex-lcd-olinuxino.c | 1 -
drivers/gpu/drm/panel/panel-samsung-s6d16d0.c | 3 -
drivers/gpu/drm/panel/panel-tpo-tpg110.c
Re: [Intel-gfx] [PULL] drm-intel-next
Quoting Dave Airlie (2019-03-28 04:09:56) > On Mon, 25 Mar 2019 at 22:49, Joonas Lahtinen > wrote: > > > > Hi Dave & Daniel, > > > > First batch of features for 5.2, tagged last week. > > I asked on irc, but got no answer I saw, > /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/i915/i915_gem_context.c:698:12: > warning: ‘context_barrier_task’ defined but not used > [-Wunused-function] > static int context_barrier_task(struct i915_gem_context *ctx, > ^~~~ > > Is there a fix for this I can throw on top of the merge? > > I don't like warnings in my builds. As discussed in IRC, I sent a followup PR that has the patches that fix the build warning. Regards, Joonas > > Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-next
Hi Dave & Daniel,
Here's a pull request with a further drop of features. Sending this instead of
the build warning fix to avoid diverging the trees. To avoid such build warnings
in futore, I'll talk about doing a non-debug build of the PR tags. The build
warning only occurred when selftests were disabled, so I missed it.
This adds Elkhartlake support code and PCI IDs (still under alpha_support flag).
Adds DP MST properties and removes 8bpc restriction on DP MST. HDR format fixes
from Maarten. Fixes Bugzilla #109780 by using first EDID mode when preferred is
missing.
There is also slight uAPI optimization, to remove an implicit SET_DOMAIN on mmap
fault. No userspace known was depending on that one, and it gets us asynchronous
mmap, which is desireable in the ongoing war against too many synchronous locks.
Then there is a fix to add back missing writeback of BO size on creation that
has
been gone from 2011 after a mysterious DRM maintainer's patch. And we added an
IGT to avoid it from happening again :)
Best Regards, Joonas
drm-intel-next-2019-03-28:
UAPI Changes:
- Make mmap code more asynchronous. Avoid full SET_DOMAIN on GTT mmap pagefault,
and flushes pages on acquisition instead. Moves some of the work from mmap
fault
time to execbuf time to avoid lock contention during mmap access.
Has neutral to positive impact on perf as the flushing moves to execbuf time
in real world workloads on the current known userspaces due to recycling of
BOs.
If there exist an unknown non-recycling userspace, they should explicitly do
the
SET_DOMAIN and not rely on kernel doing implicit SET_DOMAIN because swapout/in
might have happenedt.
- Restore the accidentally removed behaviour of returning object size on
GEM_CREATE
From 2011: ff72145badb8 ("drm: dumb scanout create/mmap for intel/radeon
(v3)")
- Includes a some neutered patches to prepare to complete the earlier Mesa
recovery feature uAPI. Looking to enable this in the next PR.
Driver Changes:
- Add Elkhartlake (Gen11) support code and PCI IDs
- Add missing Amberlake PCI ID 0x87CA (Ville)
- Fix to Bugzilla #109780: Pick the first mode from EDID as the fixed mode when
there is no preferred mode (Ville)
- Fix GCC 4.8 build by using __is_constexpr() (Chris, Randy, Uma)
- Add "Broadcast RGB", "force_audio" and "max_bpc" properties to DP MST (Ville)
- Remove 8bpc limitation from DP MST (Ville)
- Fix changing between limited and full range RGB output in DP fastsets (Ville)
- Reject unsupported HDR formats (Maarten)
- Handle YUV subpixel support better (Maarten)
- Various plane watermarks fixes and cleaning of the code (Ville)
- Icelake port sync master select fix (Manasi)
- Icelake VEBOX disable bitmask fix (Jose)
- Close a race where userspace could see incompletely initialized GEM context
(Chris)
- Avoid C3 on i945gm to keep vblank interrupts steady (Ville)
- Avoid recalculating PLL HW readout each time (Lucas)
- A ton of patches to modularize uncore code (Daniel)
- Instead of storing media fuse value, immediately derive engine masks (Daniele)
- Reduce struct_mutex usage (Chris)
- Iterate over child devices to initialize ddi_port_info (Jani)
- Fixes to return correct error values when bailing out of functions (Dan)
- Use bitmap_zalloc() (Andy)
- Reorder and clarify Gen3/4 code (Ville)
- Refactor out common code in display mode handling (Ville)
- GuC code fixes (Sujaritha, Michal)
- Selftest improvements (Chris)
The following changes since commit 0bec6219e5a0cf2dd17716949a7592807e10f3d7:
Merge tag 'drm-misc-next-2019-03-21' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next (2019-03-25 11:05:12
+0100)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2019-03-28
for you to fetch changes up to a01b2c6f47d86c7d1a9fa822b3b91ec233b61784:
drm/i915: Update DRIVER_DATE to 20190328 (2019-03-28 14:41:55 +0200)
Abdiel Janulgue (1):
drm/i915/query: Split out query item checks
Aditya Swarup (3):
drm/i915: Make combo PHY DDI macro definitions consistent for ICL and CNL
drm/i915: Make MG PHY macros semantically consistent
drm/i915/icl: Fix CRC mismatch error for DP link layer compliance
Andy Shevchenko (1):
drm/i915: Switch to bitmap_zalloc()
Anusha Srivatsa (3):
drm/i915/cml: Add CML PCI IDS
drm/i915/cml: Introduce Comet Lake PCH
drm/i915/ehl: Add Support for DMC on EHL
Bob Paauwe (3):
drm/i915/ehl: Add ElkhartLake platform
drm/i915/ehl: EHL outputs are different from ICL
drm/i915/ehl: Set proper eu slice/subslice parameters for EHL
Chengguang Xu (1):
drm/i915: remove redundant likely/unlikely annotation
Chris Wilson (124):
drm/i915: Defer removing fence register tracking to rpm wakeup
drm/i915: Revoke mmaps and prevent access to fence registers across reset
drm/i915
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO enable (rev2)
== Series Details == Series: series starting with [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO enable (rev2) URL : https://patchwork.freedesktop.org/series/58527/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5828_full -> Patchwork_12617_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12617_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12617_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12617_full: ### IGT changes ### Possible regressions * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: PASS -> INCOMPLETE Known issues Here are the changes found in Patchwork_12617_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_parse@bitmasks: - shard-iclb: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_schedule@preempt-other-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +6 * igt@gem_exec_schedule@preempt-other-chain-blt: - shard-snb: NOTRUN -> SKIP [fdo#109271] +145 * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: NOTRUN -> FAIL [fdo#107847] * igt@i915_suspend@forcewake: - shard-snb: PASS -> FAIL [fdo#103375] * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-oldfb-render-e: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-snb: NOTRUN -> DMESG-WARN [fdo#110222] - shard-iclb: PASS -> DMESG-WARN [fdo#110222] * igt@kms_chamelium@dp-crc-single: - shard-iclb: NOTRUN -> SKIP [fdo#109284] * igt@kms_concurrent@pipe-d: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_cursor_crc@cursor-128x42-random: - shard-glk: PASS -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-256x85-random: - shard-skl: PASS -> FAIL [fdo#103232] * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +2 * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#103833] +1 * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: PASS -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#103167] +3 * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack: - shard-skl: NOTRUN -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-iclb: PASS -> FAIL [fdo#109247] +10 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> FAIL [fdo#105682] * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +4 * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move: - shard-apl: NOTRUN -> SKIP [fdo#109271] +16 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] +2 * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt: - shard-skl: PASS -> FAIL [fdo#103167] +2 * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +16 - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +20 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-skl: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: PASS -> DMESG-WARN [fdo#108566] * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +2 * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_psr2_su@frontbuffer: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@cursor_blt: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] * igt@kms_psr@psr2_cursor_render: - shard-iclb: PASS ->
Re: [Intel-gfx] [v6 01/16] drm: Add Enhanced Gamma LUT precision structure
>-Original Message-
>From: Lankhorst, Maarten
>Sent: Wednesday, March 27, 2019 5:43 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Sharma, Shashank ; Roper, Matthew D
>; Syrjala, Ville
>Subject: Re: [v6 01/16] drm: Add Enhanced Gamma LUT precision structure
>
>tis 2019-03-19 klockan 14:14 +0530 skrev Uma Shankar:
>> Existing LUT precision structure is having only 16 bit
>> precision. This is not enough for upcoming enhanced hardwares
>> and advance usecases like HDR processing. Hence added a new
>> structure with 32 bit precision values. Also added the code,
>> for extracting the same from values passed from userspace.
>>
>> v4: Rebase
>>
>> v5: Relocated the helper function to drm_color_mgmt.c. Declared
>> the same in a header file (Alexandru Gheorghe)
>>
>> v6: Enhanced gamma lut structure to take U32.32 format as input.
>> This is needed for HDR usecase which require higher precision.
>>
>> Signed-off-by: Uma Shankar
>> Reviewed-by: Alexandru Gheorghe
>> ---
>> drivers/gpu/drm/drm_color_mgmt.c | 19 +++
>> include/drm/drm_color_mgmt.h | 1 +
>> include/uapi/drm/drm_mode.h | 15 +++
>> 3 files changed, 35 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_color_mgmt.c
>> b/drivers/gpu/drm/drm_color_mgmt.c
>> index d5d34d0..9dbfe1d 100644
>> --- a/drivers/gpu/drm/drm_color_mgmt.c
>> +++ b/drivers/gpu/drm/drm_color_mgmt.c
>> @@ -128,6 +128,25 @@ uint32_t drm_color_lut_extract(uint32_t
>> user_input, uint32_t bit_precision)
>> }
>> EXPORT_SYMBOL(drm_color_lut_extract);
>>
>> +/*
>> + * Added to accommodate enhanced LUT precision.
>> + * Max LUT precision is 32 bits.
>> + */
>> +u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision)
>> +{
>> +u32 val = user_input & 0x;
>> +u32 max = 0x >> (32 - bit_precision);
>> +
>> +/* Round only if we're not using full precision. */
>> +if (bit_precision < 32) {
>> +val += 1UL << (32 - bit_precision - 1);
>> +val >>= 32 - bit_precision;
>> +}
>> +
>> +return ((user_input & 0x) | clamp_val(val, 0, max));
>I thought the userspace precision was U32.32, so the precision here is
>max 64-bits?
>
>Anyway the math looks wrong for a U32.32 value, it's probably:
>user_input >> (64ULL - precision)
Hi Maarten,
Since we have a limitation of 64bit container and overflow if we left shift. My
plan is
to preserve the fixed value of 32bit separately and just round up the floating
value ie
32bit after decimal which mostly represent values below 1.0. Kept bit
precision as 32 for that
purpose only.
But you are right, I need to have the val also as a long variable to make this
logic work.
Will update the val to long and this should work fine.
Thanks & Regards,
Uma Shankar
>
>> +}
>> +EXPORT_SYMBOL(drm_color_lut_extract_ext);
>> +
>> /**
>> * drm_crtc_enable_color_mgmt - enable color management properties
>> * @crtc: DRM CRTC
>> diff --git a/include/drm/drm_color_mgmt.h
>> b/include/drm/drm_color_mgmt.h
>> index d1c662d..c9d2746 100644
>> --- a/include/drm/drm_color_mgmt.h
>> +++ b/include/drm/drm_color_mgmt.h
>> @@ -30,6 +30,7 @@
>> struct drm_plane;
>>
>> uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t
>> bit_precision);
>> +u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision);
>>
>> void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
>> uint degamma_lut_size,
>> diff --git a/include/uapi/drm/drm_mode.h
>> b/include/uapi/drm/drm_mode.h
>> index a439c2e..a0fae71 100644
>> --- a/include/uapi/drm/drm_mode.h
>> +++ b/include/uapi/drm/drm_mode.h
>> @@ -630,6 +630,21 @@ struct drm_color_lut {
>> __u16 reserved;
>> };
>>
>> +/*
>> + * Creating 64 bit palette entries for better data
>> + * precision. This will be required for HDR and
>> + * similar color processing usecases.
>> + */
>> +struct drm_color_lut_ext {
>> +/*
>> + * Data is U32.32 fixed point format.
>> + */
>> +__u64 red;
>> +__u64 green;
>> +__u64 blue;
>> +__u64 reserved;
>> +};
>> +
>> #define DRM_MODE_PAGE_FLIP_EVENT 0x01
>> #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
>> #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev2)
On Thu, Mar 28, 2019 at 03:53:37AM +, Patchwork wrote: > == Series Details == > > Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on > glk/cnl when audio power is enabled (rev2) > URL : https://patchwork.freedesktop.org/series/58273/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_5825_full -> Patchwork_12613_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_12613_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_12613_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_12613_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_universal_plane@cursor-fb-leak-pipe-a: > - shard-iclb: PASS -> FAIL ICL shouldn't be affected by these changes since we'll always have cdclk.pipe == INVALID_PIPE there. The failure looks like https://bugs.freedesktop.org/show_bug.cgi?id=109814 not sure why it wasn't marked as a pre-existing issue. > > > Warnings > > * igt@kms_dp_dsc@basic-dsc-enable-edp: > - shard-iclb: SKIP [fdo#109349] -> FAIL As above it's unrelated, the test is broken, should do a full modeset to force DSC on, whereas it only does a fastset. > > > Known issues > > > Here are the changes found in Patchwork_12613_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_ppgtt@blt-vs-render-ctx0: > - shard-iclb: PASS -> INCOMPLETE [fdo#109801] > > * igt@gem_tiled_pread_pwrite: > - shard-iclb: PASS -> TIMEOUT [fdo#109673] > > * igt@gem_workarounds@suspend-resume: > - shard-apl: PASS -> DMESG-WARN [fdo#108566] > > * igt@i915_pm_rpm@sysfs-read: > - shard-skl: PASS -> INCOMPLETE [fdo#107807] +1 > > * igt@i915_selftest@live_requests: > - shard-iclb: PASS -> INCOMPLETE [fdo#109644] > > * igt@i915_selftest@mock_fence: > - shard-apl: PASS -> INCOMPLETE [fdo#103927] > > * igt@i915_suspend@debugfs-reader: > - shard-iclb: PASS -> DMESG-WARN [fdo#109638] / [fdo#109745] > > * igt@kms_cursor_legacy@cursor-vs-flip-toggle: > - shard-iclb: PASS -> FAIL [fdo#103355] > > * igt@kms_fbcon_fbt@fbc: > - shard-iclb: PASS -> DMESG-WARN [fdo#109593] > > * igt@kms_flip@flip-vs-expired-vblank-interruptible: > - shard-iclb: PASS -> FAIL [fdo#105363] > > * igt@kms_flip@flip-vs-suspend-interruptible: > - shard-skl: PASS -> INCOMPLETE [fdo#109507] > > * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move: > - shard-iclb: NOTRUN -> SKIP [fdo#109280] +1 > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: > - shard-iclb: PASS -> FAIL [fdo#103167] +9 > > * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt: > - shard-skl: NOTRUN -> SKIP [fdo#109271] +16 > > * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt: > - shard-snb: NOTRUN -> SKIP [fdo#109271] +28 > > * igt@kms_frontbuffer_tracking@fbcpsr-stridechange: > - shard-apl: NOTRUN -> SKIP [fdo#109271] > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt: > - shard-iclb: PASS -> FAIL [fdo#109247] +19 > > * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: > - shard-skl: NOTRUN -> FAIL [fdo#108145] > > * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: > - shard-skl: PASS -> FAIL [fdo#108145] > > * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: PASS -> FAIL [fdo#107815] > > * igt@kms_psr2_su@page_flip: > - shard-iclb: PASS -> SKIP [fdo#109642] > > * igt@kms_psr@primary_mmap_gtt: > - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] > > * igt@kms_psr@psr2_cursor_render: > - shard-iclb: PASS -> SKIP [fdo#109441] +2 > > * igt@kms_universal_plane@disable-primary-vs-flip-pipe-f: > - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 > > * igt@kms_universal_plane@universal-plane-gen9-features-pipe-e: > - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5 > > * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend: > - shard-apl: PASS -> FAIL [fdo#104894] +1 > > * igt@kms_vblank@pipe-c-ts-continuation-suspend: > - shard-iclb: PASS -> FAIL [fdo#104894] > > * igt@prime_nv_api@i915_nv_double_import: > - shard-iclb: NOTRUN -> SKIP [fdo#109291] > > *
[Intel-gfx] ✓ Fi.CI.IGT: success for Device id consolidation (rev2)
== Series Details == Series: Device id consolidation (rev2) URL : https://patchwork.freedesktop.org/series/58561/ State : success == Summary == CI Bug Log - changes from CI_DRM_5827_full -> Patchwork_12616_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12616_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-kbl: PASS -> INCOMPLETE [fdo#103665] * igt@gem_exec_parse@chained-batch: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +1 * igt@gem_exec_schedule@preempt-other-chain-blt: - shard-snb: NOTRUN -> SKIP [fdo#109271] +141 * igt@gem_pread@stolen-snoop: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@gem_tiled_fence_blits@normal: - shard-iclb: PASS -> TIMEOUT [fdo#109673] * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> FAIL [fdo#108686] * igt@i915_pm_rpm@basic-rte: - shard-skl: PASS -> INCOMPLETE [fdo#107807] +1 * igt@i915_pm_rpm@pc8-residency: - shard-iclb: NOTRUN -> SKIP [fdo#109293] * igt@i915_suspend@sysfs-reader: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_busy@extended-modeset-hang-newfb-render-b: - shard-snb: NOTRUN -> DMESG-WARN [fdo#110222] - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-kbl: PASS -> DMESG-WARN [fdo#110222] +1 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +14 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-kbl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_chamelium@hdmi-hpd-after-suspend: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +2 * igt@kms_color@pipe-c-degamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#103833] +1 * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +1 * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: PASS -> FAIL [fdo#105363] * igt@kms_flip@flip-vs-suspend: - shard-snb: PASS -> INCOMPLETE [fdo#105411] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +6 * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> SKIP [fdo#109271] +118 * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu: - shard-iclb: PASS -> FAIL [fdo#109247] * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-iclb: NOTRUN -> FAIL [fdo#109247] +3 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#103167] +9 * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +23 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] +1 * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +19 * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-kbl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: PASS -> SKIP [fdo#109441] +5 * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: - shard-kbl: PASS -> DMESG-FAIL [fdo#105763] * igt@kms_setmode@basic: - shard-apl: PASS -> FAIL [fdo#99912] - shard-iclb: NOTRUN
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Fix an IS_ERR() vs NULL check (rev3)
Patchwork writes: > == Series Details == > > Series: drm/i915/selftests: Fix an IS_ERR() vs NULL check (rev3) Ok, never ever send a patch with identical subject line. > URL : https://patchwork.freedesktop.org/series/58557/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_5824 -> Patchwork_12612 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_12612 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_12612, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://patchwork.freedesktop.org/api/1.0/series/58557/revisions/3/mbox/ > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_12612: > > ### IGT changes ### > > Possible regressions > > * igt@i915_selftest@live_uncore: > - fi-kbl-8809g: PASS -> DMESG-FAIL <3> [320.015575] bcs0:RING_MI_MODE=200, fw_domains 0x2 still up after 100ms! -Mika > > > Known issues > > > Here are the changes found in Patchwork_12612 that come from known issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_basic@readonly-bsd2: > - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 > > * igt@i915_selftest@live_contexts: > - fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] > > * igt@kms_busy@basic-flip-c: > - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] > > * igt@kms_frontbuffer_tracking@basic: > - fi-byt-clapper: PASS -> FAIL [fdo#103167] > > * igt@prime_vgem@basic-fence-flip: > - fi-gdg-551: PASS -> FAIL [fdo#103182] > > > Possible fixes > > * igt@kms_busy@basic-flip-a: > - fi-gdg-551: FAIL [fdo#103182] -> PASS > > > [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 > [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 > [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 > > > Participating hosts (42 -> 37) > -- > > Additional (1): fi-pnv-d510 > Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks > fi-bsw-cyan fi-bdw-samus > > > Build changes > - > > * Linux: CI_DRM_5824 -> Patchwork_12612 > > CI_DRM_5824: d6a239f8bd502261971e5a2fb0ec71ae0b30b298 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_4907: 7c8f2616fa0fd3ddb16e050c5b7ea9ce707abbe4 @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_12612: 545ca65d2548ce9a6d6c965abb1ce061d2c7eb18 @ > git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > 545ca65d2548 drm/i915/selftests: Fix an IS_ERR() vs NULL check > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12612/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_big: Only warn for the first sign of a pagefault
We only need the warning once, not for the several thousand relocations
we try. The current execbuf implementation will set all presumed_offset
to -1 so this loop should quit on the first entry if we hit the
pagefault, but for the sake of completeness check all.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110269
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_big.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_exec_big.c b/tests/i915/gem_exec_big.c
index 440136ee8..9da90ead6 100644
--- a/tests/i915/gem_exec_big.c
+++ b/tests/i915/gem_exec_big.c
@@ -169,8 +169,10 @@ static void execN(int fd, uint32_t handle, uint64_t
batch_size, unsigned flags,
igt_permute_array(gem_reloc, nreloc, xchg_reloc);
gem_execbuf(fd, );
- for (n = 0; n < nreloc; n++)
- igt_warn_on(gem_reloc[n].presumed_offset == -1);
+ for (n = 0; n < nreloc; n++) {
+ if (igt_warn_on(gem_reloc[n].presumed_offset == -1))
+ break;
+ }
if (use_64bit_relocs) {
for (n = 0; n < nreloc; n++) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2] scripts/trace.pl: Fix after intel_engine_notify removal
From: Tvrtko Ursulin
After the removal of engine global seqnos and the corresponding
intel_engine_notify tracepoints the script needs to be adjusted to cope
with the new state of things.
To keep working it switches over using the dma_fence:dma_fence_signaled:
tracepoint and keeps one extra internal map to connect the ctx-seqno pairs
with engines.
It also needs to key the completion events on the full engine/ctx/seqno
tokens, and adjust correspondingly the timeline sorting logic.
v2:
* Do not use late notifications (received after context complete) when
splitting up coalesced requests. They are now much more likely and can
not be used.
Signed-off-by: Tvrtko Ursulin
---
scripts/trace.pl | 82
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index 18f9f3b18396..95dc3a645e8e 100755
--- a/scripts/trace.pl
+++ b/scripts/trace.pl
@@ -27,7 +27,8 @@ use warnings;
use 5.010;
my $gid = 0;
-my (%db, %queue, %submit, %notify, %rings, %ctxdb, %ringmap, %reqwait,
%ctxtimelines);
+my (%db, %queue, %submit, %notify, %rings, %ctxdb, %ringmap, %reqwait,
+%ctxtimelines, %ctxengines);
my @freqs;
my $max_items = 3000;
@@ -66,7 +67,7 @@ Notes:
i915:i915_request_submit, \
i915:i915_request_in, \
i915:i915_request_out, \
- i915:intel_engine_notify, \
+ dma_fence:dma_fence_signaled, \
i915:i915_request_wait_begin, \
i915:i915_request_wait_end \
[command-to-be-profiled]
@@ -161,7 +162,7 @@ sub arg_trace
'i915:i915_request_submit',
'i915:i915_request_in',
'i915:i915_request_out',
- 'i915:intel_engine_notify',
+ 'dma_fence:dma_fence_signaled',
'i915:i915_request_wait_begin',
'i915:i915_request_wait_end' );
@@ -312,13 +313,6 @@ sub db_key
return $ring . '/' . $ctx . '/' . $seqno;
}
-sub global_key
-{
- my ($ring, $seqno) = @_;
-
- return $ring . '/' . $seqno;
-}
-
sub sanitize_ctx
{
my ($ctx, $ring) = @_;
@@ -419,6 +413,8 @@ while (<>) {
$req{'ring'} = $ring;
$req{'seqno'} = $seqno;
$req{'ctx'} = $ctx;
+ die if exists $ctxengines{$ctx} and $ctxengines{$ctx} ne $ring;
+ $ctxengines{$ctx} = $ring;
$ctxtimelines{$ctx . '/' . $ring} = 1;
$req{'name'} = $ctx . '/' . $seqno;
$req{'global'} = $tp{'global'};
@@ -429,16 +425,29 @@ while (<>) {
$ringmap{$rings{$ring}} = $ring;
$db{$key} = \%req;
} elsif ($tp_name eq 'i915:i915_request_out:') {
- my $gkey = global_key($ring, $tp{'global'});
+ my $gkey;
+
+ die unless exists $ctxengines{$ctx};
+
+ $gkey = db_key($ctxengines{$ctx}, $ctx, $seqno);
+
+ if ($tp{'completed?'}) {
+ die unless exists $db{$key};
+ die unless exists $db{$key}->{'start'};
+ die if exists $db{$key}->{'end'};
+
+ $db{$key}->{'end'} = $time;
+ $db{$key}->{'notify'} = $notify{$gkey}
+ if exists $notify{$gkey};
+ } else {
+ delete $db{$key};
+ }
+ } elsif ($tp_name eq 'dma_fence:dma_fence_signaled:') {
+ my $gkey;
- die unless exists $db{$key};
- die unless exists $db{$key}->{'start'};
- die if exists $db{$key}->{'end'};
+ die unless exists $ctxengines{$tp{'context'}};
- $db{$key}->{'end'} = $time;
- $db{$key}->{'notify'} = $notify{$gkey} if exists $notify{$gkey};
- } elsif ($tp_name eq 'i915:intel_engine_notify:') {
- my $gkey = global_key($ring, $seqno);
+ $gkey = db_key($ctxengines{$tp{'context'}}, $tp{'context'},
$tp{'seqno'});
$notify{$gkey} = $time unless exists $notify{$gkey};
} elsif ($tp_name eq 'i915:intel_gpu_freq_change:') {
@@ -452,7 +461,7 @@ while (<>) {
# find the largest seqno to be used for timeline sorting purposes.
my $max_seqno = 0;
foreach my $key (keys %db) {
- my $gkey = global_key($db{$key}->{'ring'}, $db{$key}->{'global'});
+ my $gkey = db_key($db{$key}->{'ring'}, $db{$key}->{'ctx'},
$db{$key}->{'seqno'});
die unless exists $db{$key}->{'start'};
@@ -478,14 +487,13 @@ my $key_count = scalar(keys %db);
my %engine_timelines;
-sub sortEngine {
- my $as = $db{$a}->{'global'};
- my $bs = $db{$b}->{'global'};
+sub
Re: [Intel-gfx] [PATCH] drm/i915: adding state checker for gamma lut values
On Thu, 28 Mar 2019, Swati Sharma wrote:
> Added state checker to validate gamma_lut values. This
> reads hardware state, and compares the originally requested
> state to the state read from hardware.
>
> v1: -Implementation done for legacy platforms (removed all the placeholders)
> (Jani)
> -Added inverse function of drm_color_lut_extract to convert hardware
> read values back to user values (code written by Jani)
> -Renamed get_config() to color_config() (Jani)
> -Placed all platform specific shifts and masks in i915_reg.h (Jani)
> -Renamed i9xx_get_config to i9xx_color_config and all related
> functions (Jani)
> -Removed debug logs from compare function (Jani)
> -Renamed intel_compare_blob to intel_compare_lut and added platform
> specific
> bit precision of the readout into the function (Jani)
> -Renamed macro PIPE_CONF_CHECK_BLOB to PIPE_CONF_CHECK_COLOR_LUT (Jani)
> -Added check if blobs can be NULL (Jani)
> -Added function in intel_color.c that returns the bit precision (Jani),
> didn't add in device info since its gonna die soon (Ville)
>
> TODO:
> -Add a separate function to log errors at the higher level
Should be a separate follow-up patch.
> -Haven't moved intel_compare_lut() from intel_display.c to intel_color.c
> Since all the comparison functions are placed in intel_display, isn't
> it the right place (or) we want to move to consolidate color related
> functions
> together? Opinion? Please correct me if I am wrong.
Consolidate color to intel_color.c, as all the info about the blob and
its use is there.
> -Optimizations and refractoring
>
> Signed-off-by: Swati Sharma
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 12 +++
> drivers/gpu/drm/i915/intel_color.c | 186
> +--
> drivers/gpu/drm/i915/intel_display.c | 48 +
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 5 files changed, 243 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c4ffe19..b422ea6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -334,6 +334,7 @@ struct drm_i915_display_funcs {
>* involved with the same commit.
>*/
> void (*load_luts)(const struct intel_crtc_state *crtc_state);
> + void (*color_config)(struct intel_crtc_state *crtc_state);
Please call this *get* config. Same for the platform specific
functions. It doesn't configure, it reads the configuration.
> };
>
> #define CSR_VERSION(major, minor)((major) << 16 | (minor))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c0cd7a8..2813033 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7156,6 +7156,10 @@ enum {
> #define _LGC_PALETTE_B 0x4a800
> #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A,
> _LGC_PALETTE_B) + (i) * 4)
>
No blank line here. Ditto for the other groups.
> +#define LGC_PALETTE_RED_MASK (0xFF << 16)
> +#define LGC_PALETTE_GREEN_MASK (0xFF << 8)
> +#define LGC_PALETTE_BLUE_MASK(0xFF << 0)
Please indent according to the comment at the top of the file. Please
define these using the new REG_GENMASK() and use the REG_FIELD_PREP()
and REG_FIELD_GET() macros in code. Ditto for the other groups.
> +
> #define _GAMMA_MODE_A0x4a480
> #define _GAMMA_MODE_B0x4ac80
> #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> @@ -10102,6 +10106,10 @@ enum skl_power_gate {
> #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
> _PRE_CSC_GAMC_INDEX_B)
> #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe,
> _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
>
> +#define PREC_PAL_DATA_RED_MASK (0x3FF << 20)
> +#define PREC_PAL_DATA_GREEN_MASK (0x3FF << 10)
> +#define PREC_PAL_DATA_BLUE_MASK (0x3FF << 0)
> +
> /* pipe CSC & degamma/gamma LUTs on CHV */
> #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
> @@ -10133,6 +10141,10 @@ enum skl_power_gate {
> #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA,
> _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
> #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE,
> _CGM_PIPE_B_MODE)
>
> +#define CGM_PIPE_GAMMA_RED_MASK (0x3FF << 0)
> +#define CGM_PIPE_GAMMA_GREEN_MASK(0x3FF << 16)
> +#define CGM_PIPE_GAMMA_BLUE_MASK (0x3FF << 0)
> +
> /* MIPI DSI registers */
>
> #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c)/*
> ports A and C only */
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index da7a07d..bd4f1b1 100644
> ---
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/fb-helper: Fixup fill_info cleanup
== Series Details == Series: drm/fb-helper: Fixup fill_info cleanup URL : https://patchwork.freedesktop.org/series/58640/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5827_full -> Patchwork_12615_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12615_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12615_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12615_full: ### IGT changes ### Possible regressions * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: PASS -> INCOMPLETE Known issues Here are the changes found in Patchwork_12615_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-kbl: PASS -> INCOMPLETE [fdo#103665] * igt@gem_eio@reset-stress: - shard-snb: NOTRUN -> FAIL [fdo#109661] - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@gem_exec_parse@chained-batch: - shard-iclb: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +3 * igt@gem_exec_schedule@preempt-other-chain-blt: - shard-snb: NOTRUN -> SKIP [fdo#109271] +141 * igt@gem_pread@stolen-snoop: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> FAIL [fdo#108686] * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: NOTRUN -> FAIL [fdo#107847] * igt@i915_pm_rpm@cursor-dpms: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@pc8-residency: - shard-iclb: NOTRUN -> SKIP [fdo#109293] * igt@kms_atomic_transition@5x-modeset-transitions: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +11 * igt@kms_busy@extended-modeset-hang-newfb-render-b: - shard-snb: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-kbl: PASS -> DMESG-WARN [fdo#110222] +1 - shard-iclb: NOTRUN -> DMESG-WARN [fdo#110222] +1 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +2 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-kbl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_chamelium@hdmi-hpd-after-suspend: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +2 * igt@kms_color@pipe-c-degamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_cursor_crc@cursor-128x42-random: - shard-glk: PASS -> FAIL [fdo#103232] * igt@kms_draw_crc@draw-method-xrgb-render-xtiled: - shard-skl: NOTRUN -> FAIL [fdo#107791] * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +1 * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: PASS -> FAIL [fdo#105363] * igt@kms_flip@flip-vs-suspend: - shard-kbl: PASS -> DMESG-WARN [fdo#108566] * igt@kms_flip_tiling@flip-to-y-tiled: - shard-iclb: PASS -> FAIL [fdo#107931] * igt@kms_frontbuffer_tracking@basic: - shard-skl: NOTRUN -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +9 * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> SKIP [fdo#109271] +104 * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +5 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#109247] +10 * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +23 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +19 *
Re: [Intel-gfx] [PATCH 0/4] Device id consolidation
Quoting Tvrtko Ursulin (2019-03-28 09:23:24) > > On 26/03/2019 07:40, Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin > > > > Series removes device id checks from i915_drv.h macros and consolidates > > them to > > i915_pciids.h as the main "database", while making intel_device_info.c > > reference > > the former, expanding the existing concept of a platform mask by a few low > > bits > > reserved for sub-platform mask. > > > > This has a two-fold positive effect of firstly consolidating the list of > > device > > ids to one location, and secondly removing the if-ladders from every > > IS__ call site. > > > > Maintenance burden is not completely removed but should be improved. One > > case in > > point is that I have found some disagreements between device id listed in > > i915_pciids.h and i915_drv.h. > > > > At the same time platform mask code is generalized to an array of u32 to > > accomodate the addition of EHL and avoid spilling into u64 which would > > cause a > > small code size increase. Downside is that any platforms on the u32 > > boundary, > > like currently ICL and EHL, lose the benefit of optimizing the "IS_ICELAKE > > || > > IS_ELKHARTLAKE" checks into a single conditional, although at the moment > > there > > aren't any such call-sites. > > > > Before vs after for the whole series: > > > > textdata bss dec hex filename > > 1891093 439037424 1942420 1da394 i915.ko.0 > > 1890434 439037424 1941761 1da101 i915.ko.1 > > > > add/remove: 12/3 grow/shrink: 92/121 up/down: 1974/-1769 (205) > > ... > > Total: Before=1286293, After=1286498, chg +0.02% > > After patch 4 v8: > > textdata bss dec hex filename > 1904423 438917424 1955738 1dd79a i915.ko.0 > 1903354 438917424 1954669 1dd36d i915.ko.1 > > add/remove: 8/3 grow/shrink: 94/124 up/down: 1623/-1889 (-266) > ... > Total: Before=1293823, After=1293557, chg -0.02% The series is an improvement, both for the reader and for the compiler, Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/16] drm/fb-helper: Move modesetting code to drm_client
On Tue, Mar 26, 2019 at 06:55:30PM +0100, Noralf Trønnes wrote:
> This moves the modesetting code from drm_fb_helper to drm_client so it
> can be shared by all internal clients.
>
> I have also added a client display abstraction and a bootsplash example
> client to show where this might be heading. Hopefully Max Staudt will be
> able to pick up his bootsplash work now.
First a fairly unrelated thing that I noticed while reading stuff:
In drm_fbdev_generic_setup() we register the drm_client to the world (with
drm_client_add) before it's fully set up. And the checks in the setup code
aren't safe against a concurrent hotplug call from another thread. Which
can happen, because usually by that point, and definitely by the time the
driver called drm_dev_register() the hotplug handler is running.
Maybe good idea to rename drm_client_add to drm_client_register (to stay
consistent with our naming scheme of _register() = others can start
calling us from any thread).
We need to do the basic setup code _before_ we call drm_client_register.
The kerneldoc for the various fbdev setup functions have explanations for
when exactly it's ok to handle hotplug events.
The other bit is kinda the high-level review on the drm_client modeset
api:
- Allowing multiple different modeset clients per drm_client feels like
overkill. I think we can just require a 1:1 mapping between drm_client
and modeset config. If a client wants to have multiple different modeset
configs per drm_device they can create more drm_clients.
- That also fixes your "do we need embedding" question, since drm_client
supports that already.
- That means we could clean up the api considerably by embedding all the
modeset stuff into drm_client, and e.g. allocating the modeset arrays at
drm_client_init() time.
- Except that wouldn't work with the current fbdev emulation code, because
that one isn't always using drm_client.
Hence my question/suggestion: Could we rework the fbdev emulation to
always allocate a drm_client, but only use drm_client for buffer
allocation for generic_setup(). That could also provide us with a smoother
upgrade path for other drivers to generic_setup, e.g. we could ditch all
the hotplug handling already.
I'm thinking of embedding a drm_client into drm_fb_helper, and calling
drm_client_init() on it at the right time. But only call drm_client_add()
for generic_setup(). At least as a first step.
Related question: What's the plan for drivers which don't support
generic_setup()? If we eventually have stuff like kmscon running on top of
drm_client, we'd have to somehow port them all ...
And finally the bikeshed: I thik drm_client_modeset would be a good prefix
for all this (maybe even in a separate file):
- we have a pretty clear split between basic drm stuff and kms
- modeset means kms, display usually only means the actual physical
display. drm_simple_display_pipe always gets me with using display
instead of modeset, but a bit too late to rename that one :-)
Thoughts on this?
Cheers, Daniel
>
> Noralf.
>
> Noralf Trønnes (16):
> drm/fb-helper: Remove unused gamma_size variable
> drm/fb-helper: dpms_legacy(): Only set on connectors in use
> drm/atomic: Move __drm_atomic_helper_disable_plane/set_config()
> drm/fb-helper: No need to cache rotation and sw_rotations
> drm/fb-helper: Remove drm_fb_helper_crtc->{x,y,desired_mode}
> drm/i915/fbdev: Move intel_fb_initial_config() to fbdev helper
> drm/fb-helper: Remove drm_fb_helper_crtc
> drm/fb-helper: Prepare to move out commit code
> drm/fb-helper: Move out commit code
> drm/fb-helper: Remove drm_fb_helper_connector
> drm/fb-helper: Prepare to move out modeset config code
> drm/fb-helper: Move out modeset config code
> drm/fb-helper: Avoid race with DRM userspace
> drm/client: Add display abstraction
> drm/client: Hack: Add bootsplash example
> drm/vc4: Call drm_dev_register() after all setup is done
>
> Documentation/gpu/todo.rst | 10 +
> drivers/gpu/drm/Kconfig |5 +
> drivers/gpu/drm/Makefile|1 +
> drivers/gpu/drm/drm_atomic.c| 168
> drivers/gpu/drm/drm_atomic_helper.c | 164 ---
> drivers/gpu/drm/drm_auth.c | 20 +
> drivers/gpu/drm/drm_bootsplash.c| 216
> drivers/gpu/drm/drm_client.c| 1449 +++
> drivers/gpu/drm/drm_crtc_internal.h |5 +
> drivers/gpu/drm/drm_drv.c |4 +
> drivers/gpu/drm/drm_fb_helper.c | 1151 ++---
> drivers/gpu/drm/drm_internal.h |2 +
> drivers/gpu/drm/i915/intel_fbdev.c | 218
> drivers/gpu/drm/vc4/vc4_drv.c |6 +-
> include/drm/drm_atomic_helper.h |4 -
> include/drm/drm_client.h| 117 +++
> include/drm/drm_fb_helper.h | 127 +--
> 17 files changed, 2128 insertions(+), 1539 deletions(-)
> create mode 100644 drivers/gpu/drm/drm_bootsplash.c
>
> --
> 2.20.1
>
>
Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Assign genlock CRTC pointer in all slave CRTC states for tiled displays
On Thu, 21 Mar 2019, Manasi Navare wrote:
> In case of tiled displays when the two tiles are sent across two CRTCs
> over two separate DP SST connectors, we need a mechanism to synchronize
> the two CRTCs and their corresponding transcoders.
> So use the master-slave mode where there is one master corresponding
> to last horizontal and vertical tile that needs to be genlocked with
> all other slave tiles.
> This patch identifies saves the master CRTC pointer in all the slave
> CRTC states. This pointer is needed to select the master CRTC/transcoder
> while configuring transcoder port sync for the corresponding slaves.
>
> Cc: Daniel Vetter
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Cc: Matt Roper
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_display.c | 84
> drivers/gpu/drm/i915/intel_drv.h | 3 +
> 2 files changed, 87 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8ff7aa8cb3cf..9980a4ed8c9c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11281,6 +11281,86 @@ static int icl_check_nv12_planes(struct
> intel_crtc_state *crtc_state)
> return 0;
> }
>
> +static int icl_add_genlock_crtcs(struct drm_device *dev,
> + struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_connector *genlock_connector, *connector;
> + struct drm_connector_state *connector_state;
> + struct drm_connector_list_iter conn_iter;
> + struct drm_crtc *genlock_crtc = NULL;
> + struct drm_crtc_state *genlock_crtc_state;
> + struct intel_crtc_state *slave_crtc_state;
> + int i, tile_group_id;
> +
> + if (INTEL_GEN(dev_priv) < 11)
> + return 0;
> +
> + /*
> + * In case of tiled displays there could be one or more slaves but
> there is
> + * only one master. Lets make the CRTC used by the connector
> corresponding
> + * to the last horizonal and last vertical tile a master/genlock CRTC.
> + * All the other CRTCs corresponding to other tiles of the same Tile
> group
> + * are the slave CRTCs and hold a pointer to their genlock CRTC.
> + */
> + for_each_new_connector_in_state(state, connector, connector_state, i) {
> + if (!connector_state->crtc)
> + continue;
> + if (!connector->has_tile)
> + continue;
> + if (connector->tile_h_loc == connector->num_h_tile - 1 &&
> + connector->tile_v_loc == connector->num_v_tile - 1)
> + continue;
> + slave_crtc_state = to_intel_crtc_state(
> + drm_atomic_get_new_crtc_state(state,
> + connector_state->crtc));
> + slave_crtc_state->genlock_crtc = NULL;
> + tile_group_id = connector->tile_group->id;
> + drm_connector_list_iter_begin(dev, _iter);
> + drm_for_each_connector_iter(genlock_connector, _iter) {
> + struct drm_connector_state *genlock_conn_state = NULL;
> +
> + if (!genlock_connector->has_tile)
> + continue;
> + if (genlock_connector->tile_h_loc !=
> genlock_connector->num_h_tile - 1 ||
> + genlock_connector->tile_v_loc !=
> genlock_connector->num_v_tile - 1)
> + continue;
> + if (genlock_connector->tile_group->id != tile_group_id)
> + continue;
> +
> + genlock_conn_state =
> drm_atomic_get_connector_state(state,
> +
> genlock_connector);
> + if (IS_ERR(genlock_conn_state)) {
> + drm_connector_list_iter_end(_iter);
> + return PTR_ERR(genlock_conn_state);
> + }
> + if (genlock_conn_state->crtc) {
> + genlock_crtc = genlock_conn_state->crtc;
> + break;
> + }
> + }
> + drm_connector_list_iter_end(_iter);
The above loop would benefit from being abstracted to a separate
function. "find genlock master based on tile info"
I wonder if it would work to have each relevant encoder ->compute_config
hook look for its genlock master instead of adding another top level
loop.
BR,
Jani.
> +
> + if (!genlock_crtc) {
> + DRM_DEBUG_KMS("Could not add Genlock CRTC for Slave
> CRTC %d\n",
> + connector_state->crtc->base.id);
> + return -EINVAL;
> + }
> +
> + genlock_crtc_state = drm_atomic_get_crtc_state(state,
> +
Re: [Intel-gfx] [PATCH 0/4] Device id consolidation
On 26/03/2019 07:40, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Series removes device id checks from i915_drv.h macros and consolidates them to i915_pciids.h as the main "database", while making intel_device_info.c reference the former, expanding the existing concept of a platform mask by a few low bits reserved for sub-platform mask. This has a two-fold positive effect of firstly consolidating the list of device ids to one location, and secondly removing the if-ladders from every IS__ call site. Maintenance burden is not completely removed but should be improved. One case in point is that I have found some disagreements between device id listed in i915_pciids.h and i915_drv.h. At the same time platform mask code is generalized to an array of u32 to accomodate the addition of EHL and avoid spilling into u64 which would cause a small code size increase. Downside is that any platforms on the u32 boundary, like currently ICL and EHL, lose the benefit of optimizing the "IS_ICELAKE || IS_ELKHARTLAKE" checks into a single conditional, although at the moment there aren't any such call-sites. Before vs after for the whole series: textdata bss dec hex filename 1891093 439037424 1942420 1da394 i915.ko.0 1890434 439037424 1941761 1da101 i915.ko.1 add/remove: 12/3 grow/shrink: 92/121 up/down: 1974/-1769 (205) ... Total: Before=1286293, After=1286498, chg +0.02% After patch 4 v8: textdata bss dec hex filename 1904423 438917424 1955738 1dd79a i915.ko.0 1903354 438917424 1954669 1dd36d i915.ko.1 add/remove: 8/3 grow/shrink: 94/124 up/down: 1623/-1889 (-266) ... Total: Before=1293823, After=1293557, chg -0.02% Regards, Tvrtko Tvrtko Ursulin (4): drm/i915: Split Pineview device info into desktop and mobile drm/i915: Remove redundant device id from IS_IRONLAKE_M macro drm/i915: Split some PCI ids into separate groups drm/i915: Introduce concept of a sub-platform arch/x86/kernel/early-quirks.c | 3 +- drivers/gpu/drm/i915/i915_drv.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 133 +++-- drivers/gpu/drm/i915/i915_gpu_error.c| 3 + drivers/gpu/drm/i915/i915_pci.c | 14 +- drivers/gpu/drm/i915/intel_device_info.c | 145 ++ drivers/gpu/drm/i915/intel_device_info.h | 27 +++- drivers/gpu/drm/i915/intel_pm.c | 4 +- include/drm/i915_pciids.h| 179 --- 9 files changed, 414 insertions(+), 102 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] RMW considered harmful (was: Re: [PATCH 2/2] drm/i915/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports)
On Fri, 22 Mar 2019, Manasi Navare wrote: > On Fri, Mar 22, 2019 at 09:28:01PM +0200, Jani Nikula wrote: >> On Fri, 22 Mar 2019, Ville Syrjälä wrote: >> > On Fri, Mar 22, 2019 at 11:44:21AM -0700, Manasi Navare wrote: >> >> On Fri, Mar 22, 2019 at 08:09:50PM +0200, Ville Syrjälä wrote: >> >> > In that case there is no point in doing a rmw. >> >> >> >> But isnt it always a good idea to do rmw? I mean what if the master >> >> select was set to something else earlier? >> > >> > RMW is the root of many evils. It should be avoided unless there is a >> > really compelling reason to use it. >> >> Hear, hear! >> >> We have the software state that we want to write to the hardware. If we >> use RMW to do this, it might all work by coincidence due to the old >> values in the registers, or it might just as well break by coincidence >> due to some garbage in the registers. >> >> In most cases, there should only be one place that writes a particular >> display register during modeset. Sometimes this isn't possible, and RMW >> is required. >> >> Some registers also have reserved bits potentially used by the hardware >> that must not be changed, and RMW is required. These are documented in >> bspec. >> >> BR, >> Jani. >> > > Thanks for the explanation. It does make sense now that we are doing a > full modeset, we should just be then writing the value directly? The > only concern I have is that say DSI code sets this somewhere els ein > the modeset path, then we would need to modify this to do RMW or > always make sure DSI also uses the same function for writing to this > reg. What do you suggest doing now? I think all encoders in a tile group are always of the same type. If the tile grouping in your patch is based purely on EDID, we may need to enforce this. Surely genlock only works on encoders of the same type? In any case DSI (at least currently) does not use tile groups, and will never be mixed up in non-DSI tile groups. The DSI transcoders are separate from other transcoders, so we're not writing the same registers here. --- Looking at the code, I am wondering if this should be pushed to encoder hooks instead of adding into crtc enable. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/16] drm/fb-helper: Remove drm_fb_helper_crtc->{x, y, desired_mode}
On Tue, Mar 26, 2019 at 06:55:35PM +0100, Noralf Trønnes wrote:
> The values are already present in the modeset.
>
> This is done in preparation for the removal of struct drm_fb_helper_crtc.
>
> Signed-off-by: Noralf Trønnes
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_fb_helper.c | 12
> include/drm/drm_fb_helper.h | 2 --
> 2 files changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index e1b147fdd3f9..36310901e935 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -2023,16 +2023,16 @@ static int drm_fb_helper_single_fb_probe(struct
> drm_fb_helper *fb_helper,
>*/
> bool lastv = true, lasth = true;
>
> - desired_mode = fb_helper->crtc_info[i].desired_mode;
> mode_set = _helper->crtc_info[i].mode_set;
> + desired_mode = mode_set->mode;
>
> if (!desired_mode)
> continue;
>
> crtc_count++;
>
> - x = fb_helper->crtc_info[i].x;
> - y = fb_helper->crtc_info[i].y;
> + x = mode_set->x;
> + y = mode_set->y;
>
> sizes.surface_width = max_t(u32, desired_mode->hdisplay + x,
> sizes.surface_width);
> sizes.surface_height = max_t(u32, desired_mode->vdisplay + y,
> sizes.surface_height);
> @@ -2617,11 +2617,7 @@ static void drm_setup_crtcs(struct drm_fb_helper
> *fb_helper,
> DRM_DEBUG_KMS("desired mode %s set on crtc %d
> (%d,%d)\n",
> mode->name,
> fb_crtc->mode_set.crtc->base.id, offset->x, offset->y);
>
> - fb_crtc->desired_mode = mode;
> - fb_crtc->x = offset->x;
> - fb_crtc->y = offset->y;
> - modeset->mode = drm_mode_duplicate(dev,
> -
> fb_crtc->desired_mode);
> + modeset->mode = drm_mode_duplicate(dev, mode);
> drm_connector_get(connector);
> modeset->connectors[modeset->num_connectors++] =
> connector;
> modeset->x = offset->x;
> diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
> index cff1aa222886..7a095964f6b2 100644
> --- a/include/drm/drm_fb_helper.h
> +++ b/include/drm/drm_fb_helper.h
> @@ -48,8 +48,6 @@ struct drm_fb_offset {
>
> struct drm_fb_helper_crtc {
> struct drm_mode_set mode_set;
> - struct drm_display_mode *desired_mode;
> - int x, y;
> };
>
> /**
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/16] drm/fb-helper: Avoid race with DRM userspace
On Tue, Mar 26, 2019 at 06:55:43PM +0100, Noralf Trønnes wrote:
> drm_fb_helper_is_bound() is used to check if DRM userspace is in control.
> This is done by looking at the fb on the primary plane. By the time
> fb-helper gets around to committing, it's possible that the facts have
> changed.
>
> Avoid this race by holding the drm_device->master_mutex lock while
> committing. When DRM userspace does its first open, it will now wait
> until fb-helper is done. The helper will stay away if there's a master.
>
> Locking rule: Always take the fb-helper lock first.
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Noralf Trønnes
I think it'd be good to reorder this earlier in the series. And I'm
wondering why you didn't replace all occurences of the _is_bound()
function. With the consistent master state check we're doing with this I
don't think any of the fbdev checking is still needed. Plus looking at
crtc->primary->fb without any locks is racy, so would be good to ditch
that hack.
-Daniel
> ---
> drivers/gpu/drm/drm_auth.c | 20 ++
> drivers/gpu/drm/drm_fb_helper.c | 49 -
> drivers/gpu/drm/drm_internal.h | 2 ++
> 3 files changed, 58 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
> index 1669c42c40ed..db199807b7dc 100644
> --- a/drivers/gpu/drm/drm_auth.c
> +++ b/drivers/gpu/drm/drm_auth.c
> @@ -368,3 +368,23 @@ void drm_master_put(struct drm_master **master)
> *master = NULL;
> }
> EXPORT_SYMBOL(drm_master_put);
> +
> +/* Used by drm_client and drm_fb_helper */
> +bool drm_master_internal_acquire(struct drm_device *dev)
> +{
> + mutex_lock(>master_mutex);
> + if (dev->master) {
> + mutex_unlock(>master_mutex);
> + return false;
> + }
> +
> + return true;
> +}
> +EXPORT_SYMBOL(drm_master_internal_acquire);
> +
> +/* Used by drm_client and drm_fb_helper */
> +void drm_master_internal_release(struct drm_device *dev)
> +{
> + mutex_unlock(>master_mutex);
> +}
> +EXPORT_SYMBOL(drm_master_internal_release);
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index 4a073cd4e423..9f253fcf3f79 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -41,6 +41,8 @@
> #include
> #include
>
> +#include "drm_internal.h"
> +
> static bool drm_fbdev_emulation = true;
> module_param_named(fbdev_emulation, drm_fbdev_emulation, bool, 0600);
> MODULE_PARM_DESC(fbdev_emulation,
> @@ -235,7 +237,12 @@ int drm_fb_helper_restore_fbdev_mode_unlocked(struct
> drm_fb_helper *fb_helper)
> return 0;
>
> mutex_lock(_helper->lock);
> - ret = drm_client_modesets_commit(fb_helper->dev, fb_helper->modesets);
> + if (drm_master_internal_acquire(fb_helper->dev)) {
> + ret = drm_client_modesets_commit(fb_helper->dev,
> fb_helper->modesets);
> + drm_master_internal_release(fb_helper->dev);
> + } else {
> + ret = -EBUSY;
> + }
>
> do_delayed = fb_helper->delayed_hotplug;
> if (do_delayed)
> @@ -332,13 +339,16 @@ static struct sysrq_key_op
> sysrq_drm_fb_helper_restore_op = { };
> static void drm_fb_helper_dpms(struct fb_info *info, int dpms_mode)
> {
> struct drm_fb_helper *fb_helper = info->par;
> + struct drm_device *dev = fb_helper->dev;
>
> /*
>* For each CRTC in this fb, turn the connectors on/off.
>*/
> mutex_lock(_helper->lock);
> - if (drm_fb_helper_is_bound(fb_helper))
> - drm_client_modesets_dpms(fb_helper->dev, fb_helper->modesets,
> dpms_mode);
> + if (drm_master_internal_acquire(dev)) {
> + drm_client_modesets_dpms(dev, fb_helper->modesets, dpms_mode);
> + drm_master_internal_release(dev);
> + }
> mutex_unlock(_helper->lock);
> }
>
> @@ -1097,6 +1107,7 @@ static int setcmap_atomic(struct fb_cmap *cmap, struct
> fb_info *info)
> int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info)
> {
> struct drm_fb_helper *fb_helper = info->par;
> + struct drm_device *dev = fb_helper->dev;
> int ret;
>
> if (oops_in_progress)
> @@ -1104,9 +1115,9 @@ int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct
> fb_info *info)
>
> mutex_lock(_helper->lock);
>
> - if (!drm_fb_helper_is_bound(fb_helper)) {
> + if (!drm_master_internal_acquire(dev)) {
> ret = -EBUSY;
> - goto out;
> + goto unlock;
> }
>
> if (info->fix.visual == FB_VISUAL_TRUECOLOR)
> @@ -1116,7 +1127,8 @@ int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct
> fb_info *info)
> else
> ret = setcmap_legacy(cmap, info);
>
> -out:
> + drm_master_internal_release(dev);
> +unlock:
> mutex_unlock(_helper->lock);
>
> return ret;
> @@ -1136,11 +1148,13 @@ int drm_fb_helper_ioctl(struct fb_info *info,
> unsigned int
Re: [Intel-gfx] [PATCH 04/16] drm/fb-helper: No need to cache rotation and sw_rotations
On Tue, Mar 26, 2019 at 06:55:34PM +0100, Noralf Trønnes wrote:
> Getting rotation info is cheap so we can do it on demand.
>
> This is done in preparation for the removal of struct drm_fb_helper_crtc.
>
> Cc: Hans de Goede
> Signed-off-by: Noralf Trønnes
> ---
>
> Hans,
>
> You had this comment inline in restore_fbdev_mode_atomic() the last time
> I sent this out:
>
> We want plane_state->rotation to be set to DRM_MODE_ROTATE_0 in the else
> case, AFAIK new_plane_state starts with the current state and rotation
> may have a different value there.
>
> Otherwise this looks good to me.
>
> Rotation is reset for each plane in the code section above the one I'm
> changing.
I think best to let Hans review/test this in detail. lgtm at a glance.
Acked-by: Daniel Vetter
>
> Noralf.
>
> drivers/gpu/drm/drm_fb_helper.c | 131
> include/drm/drm_fb_helper.h | 8 --
> 2 files changed, 65 insertions(+), 74 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index b91df658db59..e1b147fdd3f9 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -387,6 +387,49 @@ int drm_fb_helper_debug_leave(struct fb_info *info)
> }
> EXPORT_SYMBOL(drm_fb_helper_debug_leave);
>
> +/* Check if the plane can hw rotate to match panel orientation */
> +static bool drm_fb_helper_panel_rotation(struct drm_mode_set *modeset,
> + unsigned int *rotation)
> +{
> + struct drm_connector *connector = modeset->connectors[0];
> + struct drm_plane *plane = modeset->crtc->primary;
> + u64 valid_mask = 0;
> + unsigned int i;
> +
> + if (!modeset->num_connectors)
> + return false;
> +
> + switch (connector->display_info.panel_orientation) {
> + case DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP:
> + *rotation = DRM_MODE_ROTATE_180;
> + break;
> + case DRM_MODE_PANEL_ORIENTATION_LEFT_UP:
> + *rotation = DRM_MODE_ROTATE_90;
> + break;
> + case DRM_MODE_PANEL_ORIENTATION_RIGHT_UP:
> + *rotation = DRM_MODE_ROTATE_270;
> + break;
> + default:
> + *rotation = DRM_MODE_ROTATE_0;
> + }
> +
> + /*
> + * TODO: support 90 / 270 degree hardware rotation,
> + * depending on the hardware this may require the framebuffer
> + * to be in a specific tiling format.
> + */
> + if (*rotation != DRM_MODE_ROTATE_180 || !plane->rotation_property)
> + return false;
> +
> + for (i = 0; i < plane->rotation_property->num_values; i++)
> + valid_mask |= (1ULL << plane->rotation_property->values[i]);
> +
> + if (!(*rotation & valid_mask))
> + return false;
> +
> + return true;
> +}
> +
> static int restore_fbdev_mode_atomic(struct drm_fb_helper *fb_helper, bool
> active)
> {
> struct drm_device *dev = fb_helper->dev;
> @@ -427,10 +470,13 @@ static int restore_fbdev_mode_atomic(struct
> drm_fb_helper *fb_helper, bool activ
> for (i = 0; i < fb_helper->crtc_count; i++) {
> struct drm_mode_set *mode_set =
> _helper->crtc_info[i].mode_set;
> struct drm_plane *primary = mode_set->crtc->primary;
> + unsigned int rotation;
>
> - /* Cannot fail as we've already gotten the plane state above */
> - plane_state = drm_atomic_get_new_plane_state(state, primary);
> - plane_state->rotation = fb_helper->crtc_info[i].rotation;
> + if (drm_fb_helper_panel_rotation(mode_set, )) {
> + /* Cannot fail as we've already gotten the plane state
> above */
> + plane_state = drm_atomic_get_new_plane_state(state,
> primary);
> + plane_state->rotation = rotation;
> + }
>
> ret = __drm_atomic_helper_set_config(mode_set, state);
> if (ret != 0)
> @@ -881,7 +927,6 @@ int drm_fb_helper_init(struct drm_device *dev,
> if (!fb_helper->crtc_info[i].mode_set.connectors)
> goto out_free;
> fb_helper->crtc_info[i].mode_set.num_connectors = 0;
> - fb_helper->crtc_info[i].rotation = DRM_MODE_ROTATE_0;
> }
>
> i = 0;
> @@ -2500,62 +2545,6 @@ static int drm_pick_crtcs(struct drm_fb_helper
> *fb_helper,
> return best_score;
> }
>
> -/*
> - * This function checks if rotation is necessary because of panel orientation
> - * and if it is, if it is supported.
> - * If rotation is necessary and supported, it gets set in fb_crtc.rotation.
> - * If rotation is necessary but not supported, a DRM_MODE_ROTATE_* flag gets
> - * or-ed into fb_helper->sw_rotations. In drm_setup_crtcs_fb() we check if
> only
> - * one bit is set and then we set fb_info.fbcon_rotate_hint to make fbcon do
> - * the unsupported rotation.
> - */
> -static void
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: adding state checker for gamma lut values (rev2)
== Series Details == Series: drm/i915: adding state checker for gamma lut values (rev2) URL : https://patchwork.freedesktop.org/series/58039/ State : failure == Summary == Applying: drm/i915: adding state checker for gamma lut values Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_drv.h M drivers/gpu/drm/i915/i915_reg.h M drivers/gpu/drm/i915/intel_color.c M drivers/gpu/drm/i915/intel_display.c M drivers/gpu/drm/i915/intel_drv.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_drv.h Auto-merging drivers/gpu/drm/i915/intel_display.c Auto-merging drivers/gpu/drm/i915/intel_color.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_color.c Auto-merging drivers/gpu/drm/i915/i915_reg.h Auto-merging drivers/gpu/drm/i915/i915_drv.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: adding state checker for gamma lut values When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] gpu:drm: Remove duplicate headers
Hi Jagadeesh,
Thank you for the patch.
On Thu, Mar 28, 2019 at 02:41:56AM +0530, jagdsh.li...@gmail.com wrote:
> From: Jagadeesh Pagadala
>
> Remove duplicate headers which are included twice.
Could you, while at it, also sort the existing #include statements
alphabetically ? This should help avoiding similar issues in the future.
> Signed-off-by: Jagadeesh Pagadala
> ---
> drivers/gpu/drm/bridge/panel.c | 1 -
> drivers/gpu/drm/i915/intel_display.c | 7 ---
> 2 files changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
> index 38eeaf8..eb9567d 100644
> --- a/drivers/gpu/drm/bridge/panel.c
> +++ b/drivers/gpu/drm/bridge/panel.c
> @@ -15,7 +15,6 @@
> #include
> #include
> #include
> -#include
>
> struct panel_bridge {
> struct drm_bridge bridge;
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index ccb6163..1166342 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -51,14 +51,7 @@
> #include "intel_dsi.h"
> #include "intel_frontbuffer.h"
>
> -#include "intel_drv.h"
> -#include "intel_dsi.h"
> -#include "intel_frontbuffer.h"
> -
> -#include "i915_drv.h"
> -#include "i915_gem_clflush.h"
> #include "i915_reset.h"
> -#include "i915_trace.h"
>
> /* Primary plane formats for gen <= 3 */
> static const u32 i8xx_primary_formats[] = {
--
Regards,
Laurent Pinchart
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: adding state checker for gamma lut values
Added state checker to validate gamma_lut values. This
reads hardware state, and compares the originally requested
state to the state read from hardware.
v1: -Implementation done for legacy platforms (removed all the placeholders)
(Jani)
-Added inverse function of drm_color_lut_extract to convert hardware
read values back to user values (code written by Jani)
-Renamed get_config() to color_config() (Jani)
-Placed all platform specific shifts and masks in i915_reg.h (Jani)
-Renamed i9xx_get_config to i9xx_color_config and all related
functions (Jani)
-Removed debug logs from compare function (Jani)
-Renamed intel_compare_blob to intel_compare_lut and added platform specific
bit precision of the readout into the function (Jani)
-Renamed macro PIPE_CONF_CHECK_BLOB to PIPE_CONF_CHECK_COLOR_LUT (Jani)
-Added check if blobs can be NULL (Jani)
-Added function in intel_color.c that returns the bit precision (Jani),
didn't add in device info since its gonna die soon (Ville)
TODO:
-Add a separate function to log errors at the higher level
-Haven't moved intel_compare_lut() from intel_display.c to intel_color.c
Since all the comparison functions are placed in intel_display, isn't
it the right place (or) we want to move to consolidate color related functions
together? Opinion? Please correct me if I am wrong.
-Optimizations and refractoring
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 12 +++
drivers/gpu/drm/i915/intel_color.c | 186 +--
drivers/gpu/drm/i915/intel_display.c | 48 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
5 files changed, 243 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4ffe19..b422ea6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -334,6 +334,7 @@ struct drm_i915_display_funcs {
* involved with the same commit.
*/
void (*load_luts)(const struct intel_crtc_state *crtc_state);
+ void (*color_config)(struct intel_crtc_state *crtc_state);
};
#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0cd7a8..2813033 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7156,6 +7156,10 @@ enum {
#define _LGC_PALETTE_B 0x4a800
#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
+ (i) * 4)
+#define LGC_PALETTE_RED_MASK (0xFF << 16)
+#define LGC_PALETTE_GREEN_MASK (0xFF << 8)
+#define LGC_PALETTE_BLUE_MASK (0xFF << 0)
+
#define _GAMMA_MODE_A 0x4a480
#define _GAMMA_MODE_B 0x4ac80
#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
@@ -10102,6 +10106,10 @@ enum skl_power_gate {
#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
_PRE_CSC_GAMC_INDEX_B)
#define PRE_CSC_GAMC_DATA(pipe)_MMIO_PIPE(pipe,
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+#define PREC_PAL_DATA_RED_MASK (0x3FF << 20)
+#define PREC_PAL_DATA_GREEN_MASK (0x3FF << 10)
+#define PREC_PAL_DATA_BLUE_MASK(0x3FF << 0)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
@@ -10133,6 +10141,10 @@ enum skl_power_gate {
#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA,
_CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
#define CGM_PIPE_MODE(pipe)_MMIO_PIPE(pipe, _CGM_PIPE_A_MODE,
_CGM_PIPE_B_MODE)
+#define CGM_PIPE_GAMMA_RED_MASK(0x3FF << 0)
+#define CGM_PIPE_GAMMA_GREEN_MASK (0x3FF << 16)
+#define CGM_PIPE_GAMMA_BLUE_MASK (0x3FF << 0)
+
/* MIPI DSI registers */
#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c)/* ports A and
C only */
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index da7a07d..bd4f1b1 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -679,6 +679,172 @@ void intel_color_load_luts(const struct intel_crtc_state
*crtc_state)
dev_priv->display.load_luts(crtc_state);
}
+u32 intel_color_bit_precision(struct drm_i915_private *dev_priv)
+{
+ if (INTEL_GEN(dev_priv) >= 9)
+ return 10;
+ else
+ return 8;
+}
+
+/* convert hw value with given bit_precision to lut property val */
+static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
+{
+ u32 max = 0x >> (16 - bit_precision);
+
+ val = clamp_val(val, 0, max);
+
+ if (bit_precision < 16)
+ val <<= 16 - bit_precision;
+
+ return val;
+}
+
+static void
