[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Engine discovery query (rev9)
== Series Details == Series: drm/i915: Engine discovery query (rev9) URL : https://patchwork.freedesktop.org/series/39958/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h AR drivers/gpu/drm/i915/built-in.a CC [M] drivers/gpu/drm/i915/header_test_i915_active_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_drv.o CC [M] drivers/gpu/drm/i915/header_test_i915_gem_context_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_gem_pm.o CC [M] drivers/gpu/drm/i915/header_test_i915_irq.o CC [M] drivers/gpu/drm/i915/header_test_i915_params.o CC [M] drivers/gpu/drm/i915/header_test_i915_priolist_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_reg.o CC [M] drivers/gpu/drm/i915/header_test_i915_scheduler_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_timeline_types.o CC [M] drivers/gpu/drm/i915/header_test_intel_atomic.o CC [M] drivers/gpu/drm/i915/header_test_intel_atomic_plane.o CC [M] drivers/gpu/drm/i915/header_test_intel_audio.o CC [M] drivers/gpu/drm/i915/header_test_intel_bios.o CC [M] drivers/gpu/drm/i915/header_test_intel_cdclk.o CC [M] drivers/gpu/drm/i915/header_test_intel_color.o CC [M] drivers/gpu/drm/i915/header_test_intel_combo_phy.o CC [M] drivers/gpu/drm/i915/header_test_intel_connector.o CC [M] drivers/gpu/drm/i915/header_test_intel_crt.o CC [M] drivers/gpu/drm/i915/header_test_intel_csr.o CC [M] drivers/gpu/drm/i915/header_test_intel_ddi.o CC [M] drivers/gpu/drm/i915/header_test_intel_dp.o CC [M] drivers/gpu/drm/i915/header_test_intel_dp_aux_backlight.o CC [M] drivers/gpu/drm/i915/header_test_intel_dp_link_training.o CC [M] drivers/gpu/drm/i915/header_test_intel_dp_mst.o CC [M] drivers/gpu/drm/i915/header_test_intel_dpll_mgr.o CC [M] drivers/gpu/drm/i915/header_test_intel_drv.o CC [M] drivers/gpu/drm/i915/header_test_intel_dsi.o CC [M] drivers/gpu/drm/i915/header_test_intel_dsi_dcs_backlight.o CC [M] drivers/gpu/drm/i915/header_test_intel_dvo.o CC [M] drivers/gpu/drm/i915/header_test_intel_dvo_dev.o CC [M] drivers/gpu/drm/i915/header_test_intel_fbc.o CC [M] drivers/gpu/drm/i915/header_test_intel_fbdev.o CC [M] drivers/gpu/drm/i915/header_test_intel_fifo_underrun.o CC [M] drivers/gpu/drm/i915/header_test_intel_frontbuffer.o CC [M] drivers/gpu/drm/i915/header_test_intel_hdcp.o CC [M] drivers/gpu/drm/i915/header_test_intel_hdmi.o CC [M] drivers/gpu/drm/i915/header_test_intel_hotplug.o CC [M] drivers/gpu/drm/i915/header_test_intel_lspcon.o CC [M] drivers/gpu/drm/i915/header_test_intel_lvds.o CC [M] drivers/gpu/drm/i915/header_test_intel_overlay.o CC [M] drivers/gpu/drm/i915/header_test_intel_panel.o CC [M] drivers/gpu/drm/i915/header_test_intel_pipe_crc.o CC [M] drivers/gpu/drm/i915/header_test_intel_pm.o CC [M] drivers/gpu/drm/i915/header_test_intel_psr.o CC [M] drivers/gpu/drm/i915/header_test_intel_quirks.o CC [M] drivers/gpu/drm/i915/header_test_intel_sdvo.o CC [M] drivers/gpu/drm/i915/header_test_intel_sideband.o CC [M] drivers/gpu/drm/i915/header_test_intel_sprite.o CC [M] drivers/gpu/drm/i915/header_test_intel_tv.o CC [M] drivers/gpu/drm/i915/header_test_intel_uncore.o CC [M] drivers/gpu/drm/i915/header_test_intel_vdsc.o CC [M] drivers/gpu/drm/i915/header_test_intel_wakeref.o CC [M] drivers/gpu/drm/i915/gt/intel_engine_cs.o drivers/gpu/drm/i915/gt/intel_engine_cs.c: In function ‘intel_engines_init_mmio’: drivers/gpu/drm/i915/gt/intel_engine_cs.c:456:34: error: ‘dev_priv’ undeclared (first use in this function); did you mean ‘dev_crit’? intel_setup_engine_capabilities(dev_priv); ^~~~ dev_crit drivers/gpu/drm/i915/gt/intel_engine_cs.c:456:34: note: each undeclared identifier is reported only once for each function it appears in scripts/Makefile.build:275: recipe for target 'drivers/gpu/drm/i915/gt/intel_engine_cs.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/intel_engine_cs.o] Error 1 scripts/Makefile.build:486: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:486: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:486: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1051: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI v11] drm/i915: Engine discovery query
From: Tvrtko Ursulin
Engine discovery query allows userspace to enumerate engines, probe their
configuration features, all without needing to maintain the internal PCI
ID based database.
A new query for the generic i915 query ioctl is added named
DRM_I915_QUERY_ENGINE_INFO, together with accompanying structure
drm_i915_query_engine_info. The address of latter should be passed to the
kernel in the query.data_ptr field, and should be large enough for the
kernel to fill out all known engines as struct drm_i915_engine_info
elements trailing the query.
As with other queries, setting the item query length to zero allows
userspace to query minimum required buffer size.
Enumerated engines have common type mask which can be used to query all
hardware engines, versus engines userspace can submit to using the execbuf
uAPI.
Engines also have capabilities which are per engine class namespace of
bits describing features not present on all engine instances.
v2:
* Fixed HEVC assignment.
* Reorder some fields, rename type to flags, increase width. (Lionel)
* No need to allocate temporary storage if we do it engine by engine.
(Lionel)
v3:
* Describe engine flags and mark mbz fields. (Lionel)
* HEVC only applies to VCS.
v4:
* Squash SFC flag into main patch.
* Tidy some comments.
v5:
* Add uabi_ prefix to engine capabilities. (Chris Wilson)
* Report exact size of engine info array. (Chris Wilson)
* Drop the engine flags. (Joonas Lahtinen)
* Added some more reserved fields.
* Move flags after class/instance.
v6:
* Do not check engine info array was zeroed by userspace but zero the
unused fields for them instead.
v7:
* Simplify length calculation loop. (Lionel Landwerlin)
v8:
* Remove MBZ comments where not applicable.
* Rename ABI flags to match engine class define naming.
* Rename SFC ABI flag to reflect it applies to VCS and VECS.
* SFC is wired to even _logical_ engine instances.
* SFC applies to VCS and VECS.
* HEVC is present on all instances on Gen11. (Tony)
* Simplify length calculation even more. (Chris Wilson)
* Move info_ptr assigment closer to loop for clarity. (Chris Wilson)
* Use vdbox_sfc_access from runtime info.
* Rebase for RUNTIME_INFO.
* Refactor for lower indentation.
* Rename uAPI class/instance to engine_class/instance to avoid C++
keyword.
v9:
* Rebase for s/num_rings/num_engines/ in RUNTIME_INFO.
v10:
* Use new copy_query_item.
v11:
* Consolidate with struct i915_engine_class_instnace.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Jon Bloomfield
Cc: Dmitry Rogozhkin
Cc: Lionel Landwerlin
Cc: Joonas Lahtinen
Cc: Tony Ye
Reviewed-by: Lionel Landwerlin # v7
Reviewed-by: Chris Wilson
---
Test-with: 20190501114259.16158-3-tvrtko.ursu...@linux.intel.com
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 41
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +
drivers/gpu/drm/i915/i915_query.c| 49
include/uapi/drm/i915_drm.h | 42 +
4 files changed, 134 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f7308479d511..4e3e856f9065 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -343,6 +343,45 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
return 0;
}
+static void __setup_engine_capabilities(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *i915 = engine->i915;
+
+ if (engine->class == VIDEO_DECODE_CLASS) {
+ /*
+* HEVC support is present on first engine instance
+* before Gen11 and on all instances afterwards.
+*/
+ if (INTEL_GEN(i915) >= 11 ||
+ (INTEL_GEN(i915) >= 9 && engine->instance == 0))
+ engine->uabi_capabilities |=
+ I915_VIDEO_CLASS_CAPABILITY_HEVC;
+
+ /*
+* SFC block is present only on even logical engine
+* instances.
+*/
+ if ((INTEL_GEN(i915) >= 11 &&
+RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||
+ (INTEL_GEN(i915) >= 9 && engine->instance == 0))
+ engine->uabi_capabilities |=
+ I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
+ } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
+ if (INTEL_GEN(i915) >= 9)
+ engine->uabi_capabilities |=
+ I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
+ }
+}
+
+static void intel_setup_engine_capabilities(struct drm_i915_private *i915)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, i915, id)
+ __setup_engine_capabilities(engine);
+}
+
/**
* intel_engines_init_mmio() -
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Move the engine->destroy() vfunc onto the engine
== Series Details == Series: drm/i915: Move the engine->destroy() vfunc onto the engine URL : https://patchwork.freedesktop.org/series/60147/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6020_full -> Patchwork_12921_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12921_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12921_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12921_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@preempt-hang-vebox: - shard-skl: NOTRUN -> [INCOMPLETE][1] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-skl5/igt@gem_exec_sched...@preempt-hang-vebox.html * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-skl: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl8/igt@kms_b...@extended-modeset-hang-newfb-with-reset-render-a.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-skl10/igt@kms_b...@extended-modeset-hang-newfb-with-reset-render-a.html Warnings * igt@gem_tiled_fence_blits@normal: - shard-skl: [SKIP][4] ([fdo#109271]) -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl10/igt@gem_tiled_fence_bl...@normal.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-skl2/igt@gem_tiled_fence_bl...@normal.html Known issues Here are the changes found in Patchwork_12921_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_blt@dumb-buf-min: - shard-hsw: [PASS][6] -> [INCOMPLETE][7] ([fdo#103540]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-hsw4/igt@gem_exec_...@dumb-buf-min.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-hsw6/igt@gem_exec_...@dumb-buf-min.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-apl7/igt@gem_workarou...@suspend-resume.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-apl2/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_rpm@i2c: - shard-iclb: [PASS][10] -> [DMESG-WARN][11] ([fdo#109982]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-iclb5/igt@i915_pm_...@i2c.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-iclb2/igt@i915_pm_...@i2c.html * igt@i915_pm_rpm@legacy-planes-dpms: - shard-iclb: [PASS][12] -> [INCOMPLETE][13] ([fdo#107713] / [fdo#108840] / [fdo#109960]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-iclb2/igt@i915_pm_...@legacy-planes-dpms.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-iclb3/igt@i915_pm_...@legacy-planes-dpms.html * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-skl: [PASS][14] -> [INCOMPLETE][15] ([fdo#104108]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl7/igt@kms_cursor_...@cursor-256x256-suspend.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-skl5/igt@kms_cursor_...@cursor-256x256-suspend.html * igt@kms_cursor_crc@cursor-size-change: - shard-snb: [PASS][16] -> [SKIP][17] ([fdo#109271]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-snb4/igt@kms_cursor_...@cursor-size-change.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-snb6/igt@kms_cursor_...@cursor-size-change.html * igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled: - shard-skl: [PASS][18] -> [FAIL][19] ([fdo#103184] / [fdo#103232]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl1/igt@kms_draw_...@draw-method-xrgb2101010-render-xtiled.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-skl4/igt@kms_draw_...@draw-method-xrgb2101010-render-xtiled.html * igt@kms_flip@2x-flip-vs-dpms-interruptible: - shard-glk: [PASS][20] -> [INCOMPLETE][21] ([fdo#103359] / [k.org#198133]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-glk1/igt@kms_f...@2x-flip-vs-dpms-interruptible.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/shard-glk3/igt@kms_f...@2x-flip-vs-dpms-interruptible.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][22] ->
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/hangcheck: Track context changes
== Series Details == Series: drm/i915/hangcheck: Track context changes URL : https://patchwork.freedesktop.org/series/60143/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6020_full -> Patchwork_12920_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12920_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12920_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12920_full: ### IGT changes ### Possible regressions * igt@kms_cursor_crc@cursor-64x21-sliding: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl4/igt@kms_cursor_...@cursor-64x21-sliding.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-skl3/igt@kms_cursor_...@cursor-64x21-sliding.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render: - shard-skl: NOTRUN -> [INCOMPLETE][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-skl5/igt@kms_frontbuffer_track...@fbcpsr-2p-primscrn-cur-indfb-draw-render.html Known issues Here are the changes found in Patchwork_12920_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-rte: - shard-skl: [PASS][4] -> [INCOMPLETE][5] ([fdo#107807]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl7/igt@i915_pm_...@basic-rte.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-skl9/igt@i915_pm_...@basic-rte.html * igt@i915_pm_rpm@legacy-planes-dpms: - shard-iclb: [PASS][6] -> [INCOMPLETE][7] ([fdo#107713] / [fdo#108840] / [fdo#109960]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-iclb2/igt@i915_pm_...@legacy-planes-dpms.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-iclb3/igt@i915_pm_...@legacy-planes-dpms.html * igt@kms_flip@2x-flip-vs-dpms-interruptible: - shard-glk: [PASS][8] -> [INCOMPLETE][9] ([fdo#103359] / [k.org#198133]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-glk1/igt@kms_f...@2x-flip-vs-dpms-interruptible.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-glk4/igt@kms_f...@2x-flip-vs-dpms-interruptible.html * igt@kms_flip@flip-vs-suspend: - shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([fdo#108566]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-kbl1/igt@kms_f...@flip-vs-suspend.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-kbl1/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@basic: - shard-iclb: [PASS][12] -> [FAIL][13] ([fdo#103167]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-iclb7/igt@kms_frontbuffer_track...@basic.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-iclb2/igt@kms_frontbuffer_track...@basic.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([fdo#108566]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([fdo#104108]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-skl9/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][18] -> [FAIL][19] ([fdo#108145]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl3/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103166]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-y.html [21]:
Re: [Intel-gfx] [PATCH 6/6] drm/i915: Expand subslice mask
On 5/1/19 8:34 AM, Stuart Summers wrote:
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: fix spacing in set_sseu_info args
use set_sseu_info to initialize sseu data when building
device status in debugfs
rename variables in intel_engine_types.h to avoid checkpatch
warnings
v3: update headers in intel_sseu.h
v4: add const to some sseu_dev_info variables
use sseu->eu_stride for EU stride calculations
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Can you also get an ack from Lionel, to make sure this all fits with the
expected reporting?
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 49 +--
drivers/gpu/drm/i915/gt/intel_sseu.h | 16 ++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 44 +++---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c| 5 +-
drivers/gpu/drm/i915/i915_query.c| 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 142 +++
11 files changed, 198 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6e40f8ea9a6a..8f7967cc9a50 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -914,7 +914,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private
*dev_priv)
const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
u32 mcr_s_ss_select;
u32 slice = fls(sseu->slice_mask);
- u32 subslice = fls(sseu->subslice_mask[slice]);
+ u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
This (and the registers we use below) only works if ss_stride = 1. Can
we add a:
GEM_BUG_ON(sseu->ss_stride > 1);
to catch the fact that this function will need updating to handle that
case if/when we get it?
if (IS_GEN(dev_priv, 10))
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -990,6 +990,7 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *dev_priv = engine->i915;
+ const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -1007,7 +1008,8 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice,
+subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(dev_priv, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d64e33f8427..1710546a2446 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct
intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
-(slice__) < I915_MAX_SLICES; \
-(subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ?
(subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) &&
\
- (BIT(subslice__) &
instdone_subslice_mask(dev_priv__)))
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? \
+ 1 : (sseu___)->slice_mask) & \
I'd put the ternary op on the same line here for readability
+ BIT(slice___)) \
no need for "\" here (and below).
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__,
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Complete both freed-object passes before draining the workqueue
== Series Details == Series: drm/i915: Complete both freed-object passes before draining the workqueue URL : https://patchwork.freedesktop.org/series/60142/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6020_full -> Patchwork_12919_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12919_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12919_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12919_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@preempt-hang-vebox: - shard-skl: NOTRUN -> [INCOMPLETE][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-skl8/igt@gem_exec_sched...@preempt-hang-vebox.html * igt@gem_softpin@softpin: - shard-skl: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl2/igt@gem_soft...@softpin.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-skl6/igt@gem_soft...@softpin.html Warnings * igt@gem_tiled_blits@normal: - shard-skl: [SKIP][4] ([fdo#109271]) -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl10/igt@gem_tiled_bl...@normal.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-skl9/igt@gem_tiled_bl...@normal.html ### Piglit changes ### Possible regressions * spec@glsl-1.30@execution@tex-miplevel-selection texturelod 2darray (NEW): - pig-snb-2600: NOTRUN -> [FAIL][6] [6]: None New tests - New tests have been introduced between CI_DRM_6020_full and Patchwork_12919_full: ### New Piglit tests (1) ### * spec@glsl-1.30@execution@tex-miplevel-selection texturelod 2darray: - Statuses : 1 fail(s) - Exec time: [7.00] s Known issues Here are the changes found in Patchwork_12919_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-apl7/igt@gem_workarou...@suspend-resume.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-apl1/igt@gem_workarou...@suspend-resume.html * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-skl7/igt@kms_cursor_...@cursor-256x256-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-skl7/igt@kms_cursor_...@cursor-256x256-suspend.html * igt@kms_cursor_edge_walk@pipe-c-64x64-top-edge: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-iclb6/igt@kms_cursor_edge_w...@pipe-c-64x64-top-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-iclb8/igt@kms_cursor_edge_w...@pipe-c-64x64-top-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][13] -> [FAIL][14] ([fdo#105767]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_flip@flip-vs-expired-vblank: - shard-kbl: [PASS][15] -> [FAIL][16] ([fdo#102887] / [fdo#105363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-kbl7/igt@kms_f...@flip-vs-expired-vblank.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-kbl3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][17] -> [FAIL][18] ([fdo#105363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-glk1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-glk7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][19] -> [INCOMPLETE][20] ([fdo#103540]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/shard-hsw6/igt@kms_f...@flip-vs-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/shard-hsw1/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb:
Re: [Intel-gfx] [PATCH] drm/i915: Fix ICL output CSC programming
On 4/26/19 12:31 AM, Lucas De Marchi wrote:
On Thu, Apr 25, 2019 at 12:24 PM Ville Syrjala
wrote:
From: Ville Syrjälä
When I refactored the code into its own function I accidentally
misplaced the <<16 shifts for some of the registers causing us
to lose the blue channel entirely.
We should really find a way to test this...
Cc: Uma Shankar
Fixes: d2c19b06d6ea ("drm/i915: Clean up ilk/icl pipe/output CSC programming")
Signed-off-by: Ville Syrjälä
+Clint
Does this fix the problem you reported earlier this week?
Yes, Colors now appear correctly in many failing modes.
Clint
Lucas De Marchi
---
drivers/gpu/drm/i915/intel_color.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index ca341a9e47e6..9093daabc290 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -173,13 +173,13 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 |
coeff[1]);
- I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
+ I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2] << 16);
I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 |
coeff[4]);
- I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
+ I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5] << 16);
I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 |
coeff[7]);
- I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
+ I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8] << 16);
I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
--
2.21.0
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Re: [Intel-gfx] [PATCH 5/6] drm/i915: Remove inline from sseu helper functions
On Wed, 2019-05-01 at 14:19 -0700, Daniele Ceraolo Spurio wrote:
>
> On 5/1/19 2:04 PM, Summers, Stuart wrote:
> > On Wed, 2019-05-01 at 13:04 -0700, Daniele Ceraolo Spurio wrote:
> > > Can you elaborate a bit more on what's the rationale for this? do
> > > you
> > > just want to avoid having too many inlines since the paths
> > > they're
> > > used
> > > in are not critical, or do you have some more functional reason?
> > > This
> > > is
> > > not a critic to the patch, I just want to understand where you're
> > > coming
> > > from ;)
> >
> > This was a request from Jani Nikula in a previous series update. I
> > don't have a strong preference either way personally. If you don't
> > have
> > any major concerns, I'd prefer to keep the series as-is to prevent
> > too
> > much thrash here, but let me know.
> >
>
> No concerns, just please update the commit message to explain that
> we're
> moving them because there is no need for them to be inline since
> they're
> not on a critical path where we need preformance.
Sounds great.
>
> > >
> > > BTW, looking at this patch I realized there are a few more
> > > DIV_ROUND_UP(..., BITS_PER_BYTE) that could be converted to
> > > GEN_SSEU_STRIDE() in patch 2. I noticed you update them to a new
> > > variable in the next patch, but for consistency it might still be
> > > worth
> > > updating them all in patch 2 or at least mention in the commit
> > > message
> > > of patch 2 that the remaining cases are updated by a follow-up
> > > patch
> > > in
> > > the series. Patch 2 is quite small, so you could also just squash
> > > it
> > > into patch 6 to avoid the split.
> >
> > I'm happy to squash them. I did try to isolate this a bit, but
> > you're
> > right that I ended up pushing some of these DIV_ROUND_UP... stride
> > calculations to the last patch in the series. If you don't have any
> > objection, to keep the finaly patch a bit simpler, I'd rather pull
> > those changes into the earlier patch. I realize you already have a
> > RB
> > on that patch. Any issues doing this?
> >
>
> If you're changing all of them from DIV_ROUND_UP to GEN_SSEU_STRIDE
> in
> patch 2 I'm ok for you to keep the r-b. If you want to port the
> other
> logic for saving sseu->ss_stride to that patch then I'll have
> another
> quick look at it after you re-send as that is a more complex change.
I'll do the former, then convert those to the new structure layout in
the subsequent patches.
Thanks,
Stuart
>
> Daniele
>
> > Thanks,
> > Stuart
> >
> > >
> > > Daniele
> > >
> > > On 5/1/19 8:34 AM, Stuart Summers wrote:
> > > > Additionally, ensure these are all prefixed with intel_sseu_*
> > > > to match the convention of other functions in i915.
> > > >
> > > > Signed-off-by: Stuart Summers
> > > > ---
> > > >drivers/gpu/drm/i915/gt/intel_sseu.c | 54
> > > > +++
> > > >drivers/gpu/drm/i915/gt/intel_sseu.h | 57 +++---
> > > > ---
> > > > ---
> > > >drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
> > > >drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > > >drivers/gpu/drm/i915/intel_device_info.c | 69
> > > > ---
> > > > -
> > > >5 files changed, 102 insertions(+), 86 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > > b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > > index 7f448f3bea0b..4a0b82fc108c 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > > @@ -8,6 +8,60 @@
> > > >#include "intel_lrc_reg.h"
> > > >#include "intel_sseu.h"
> > > >
> > > > +unsigned int
> > > > +intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> > > > +{
> > > > + unsigned int i, total = 0;
> > > > +
> > > > + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > > > + total += hweight8(sseu->subslice_mask[i]);
> > > > +
> > > > + return total;
> > > > +}
> > > > +
> > > > +unsigned int
> > > > +intel_sseu_subslices_per_slice(const struct sseu_dev_info
> > > > *sseu,
> > > > u8 slice)
> > > > +{
> > > > + return hweight8(sseu->subslice_mask[slice]);
> > > > +}
> > > > +
> > > > +static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu,
> > > > int
> > > > slice,
> > > > +int subslice)
> > > > +{
> > > > + int subslice_stride = DIV_ROUND_UP(sseu-
> > > > >max_eus_per_subslice,
> > > > + BITS_PER_BYTE);
> > > > + int slice_stride = sseu->max_subslices *
> > > > subslice_stride;
> > > > +
> > > > + return slice * slice_stride + subslice *
> > > > subslice_stride;
> > > > +}
> > > > +
> > > > +u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int
> > > > slice,
> > > > + int subslice)
> > > > +{
> > > > + int i, offset = intel_sseu_eu_idx(sseu, slice,
> > > > subslice);
> > > > + u16 eu_mask = 0;
> > > > +
> > > > + for (i = 0;
> > >
Re: [Intel-gfx] [PATCH 5/6] drm/i915: Remove inline from sseu helper functions
On 5/1/19 2:04 PM, Summers, Stuart wrote:
On Wed, 2019-05-01 at 13:04 -0700, Daniele Ceraolo Spurio wrote:
Can you elaborate a bit more on what's the rationale for this? do
you
just want to avoid having too many inlines since the paths they're
used
in are not critical, or do you have some more functional reason? This
is
not a critic to the patch, I just want to understand where you're
coming
from ;)
This was a request from Jani Nikula in a previous series update. I
don't have a strong preference either way personally. If you don't have
any major concerns, I'd prefer to keep the series as-is to prevent too
much thrash here, but let me know.
No concerns, just please update the commit message to explain that we're
moving them because there is no need for them to be inline since they're
not on a critical path where we need preformance.
BTW, looking at this patch I realized there are a few more
DIV_ROUND_UP(..., BITS_PER_BYTE) that could be converted to
GEN_SSEU_STRIDE() in patch 2. I noticed you update them to a new
variable in the next patch, but for consistency it might still be
worth
updating them all in patch 2 or at least mention in the commit
message
of patch 2 that the remaining cases are updated by a follow-up patch
in
the series. Patch 2 is quite small, so you could also just squash it
into patch 6 to avoid the split.
I'm happy to squash them. I did try to isolate this a bit, but you're
right that I ended up pushing some of these DIV_ROUND_UP... stride
calculations to the last patch in the series. If you don't have any
objection, to keep the finaly patch a bit simpler, I'd rather pull
those changes into the earlier patch. I realize you already have a RB
on that patch. Any issues doing this?
If you're changing all of them from DIV_ROUND_UP to GEN_SSEU_STRIDE in
patch 2 I'm ok for you to keep the r-b. If you want to port the other
logic for saving sseu->ss_stride to that patch then I'll have another
quick look at it after you re-send as that is a more complex change.
Daniele
Thanks,
Stuart
Daniele
On 5/1/19 8:34 AM, Stuart Summers wrote:
Additionally, ensure these are all prefixed with intel_sseu_*
to match the convention of other functions in i915.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 54 +++
drivers/gpu/drm/i915/gt/intel_sseu.h | 57 +++--
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 69 ---
-
5 files changed, 102 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7f448f3bea0b..4a0b82fc108c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -8,6 +8,60 @@
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
+unsigned int
+intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
+{
+ unsigned int i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+ total += hweight8(sseu->subslice_mask[i]);
+
+ return total;
+}
+
+unsigned int
+intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu,
u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
+static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu, int
slice,
+int subslice)
+{
+ int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+ BITS_PER_BYTE);
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ return slice * slice_stride + subslice * subslice_stride;
+}
+
+u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int
slice,
+ int subslice)
+{
+ int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
BITS_PER_BYTE); i++) {
+ eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, int
subslice,
+ u16 eu_mask)
+{
+ int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
BITS_PER_BYTE); i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 029e71d8f140..56e3721ae83f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,58 +63,17 @@ intel_sseu_from_device_info(const struct
Re: [Intel-gfx] [PATCH 5/6] drm/i915: Remove inline from sseu helper functions
On Wed, 2019-05-01 at 13:04 -0700, Daniele Ceraolo Spurio wrote:
> Can you elaborate a bit more on what's the rationale for this? do
> you
> just want to avoid having too many inlines since the paths they're
> used
> in are not critical, or do you have some more functional reason? This
> is
> not a critic to the patch, I just want to understand where you're
> coming
> from ;)
This was a request from Jani Nikula in a previous series update. I
don't have a strong preference either way personally. If you don't have
any major concerns, I'd prefer to keep the series as-is to prevent too
much thrash here, but let me know.
>
> BTW, looking at this patch I realized there are a few more
> DIV_ROUND_UP(..., BITS_PER_BYTE) that could be converted to
> GEN_SSEU_STRIDE() in patch 2. I noticed you update them to a new
> variable in the next patch, but for consistency it might still be
> worth
> updating them all in patch 2 or at least mention in the commit
> message
> of patch 2 that the remaining cases are updated by a follow-up patch
> in
> the series. Patch 2 is quite small, so you could also just squash it
> into patch 6 to avoid the split.
I'm happy to squash them. I did try to isolate this a bit, but you're
right that I ended up pushing some of these DIV_ROUND_UP... stride
calculations to the last patch in the series. If you don't have any
objection, to keep the finaly patch a bit simpler, I'd rather pull
those changes into the earlier patch. I realize you already have a RB
on that patch. Any issues doing this?
Thanks,
Stuart
>
> Daniele
>
> On 5/1/19 8:34 AM, Stuart Summers wrote:
> > Additionally, ensure these are all prefixed with intel_sseu_*
> > to match the convention of other functions in i915.
> >
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.c | 54 +++
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 57 +++--
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
> > drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > drivers/gpu/drm/i915/intel_device_info.c | 69 ---
> > -
> > 5 files changed, 102 insertions(+), 86 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > index 7f448f3bea0b..4a0b82fc108c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > @@ -8,6 +8,60 @@
> > #include "intel_lrc_reg.h"
> > #include "intel_sseu.h"
> >
> > +unsigned int
> > +intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> > +{
> > + unsigned int i, total = 0;
> > +
> > + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > + total += hweight8(sseu->subslice_mask[i]);
> > +
> > + return total;
> > +}
> > +
> > +unsigned int
> > +intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu,
> > u8 slice)
> > +{
> > + return hweight8(sseu->subslice_mask[slice]);
> > +}
> > +
> > +static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu, int
> > slice,
> > +int subslice)
> > +{
> > + int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > + BITS_PER_BYTE);
> > + int slice_stride = sseu->max_subslices * subslice_stride;
> > +
> > + return slice * slice_stride + subslice * subslice_stride;
> > +}
> > +
> > +u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int
> > slice,
> > + int subslice)
> > +{
> > + int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
> > + u16 eu_mask = 0;
> > +
> > + for (i = 0;
> > +i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > + eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
> > + (i * BITS_PER_BYTE);
> > + }
> > +
> > + return eu_mask;
> > +}
> > +
> > +void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, int
> > subslice,
> > + u16 eu_mask)
> > +{
> > + int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
> > +
> > + for (i = 0;
> > +i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > + sseu->eu_mask[offset + i] =
> > + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> > + }
> > +}
> > +
> > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
> > const struct intel_sseu *req_sseu)
> > {
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index 029e71d8f140..56e3721ae83f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -63,58 +63,17 @@ intel_sseu_from_device_info(const struct
> > sseu_dev_info *sseu)
> > return value;
> > }
> >
> > -static inline unsigned int sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > -{
> > - unsigned int i, total = 0;
> > -
> > - for (i = 0; i <
Re: [Intel-gfx] [PATCH 5/6] drm/i915: Remove inline from sseu helper functions
Can you elaborate a bit more on what's the rationale for this? do you
just want to avoid having too many inlines since the paths they're used
in are not critical, or do you have some more functional reason? This is
not a critic to the patch, I just want to understand where you're coming
from ;)
BTW, looking at this patch I realized there are a few more
DIV_ROUND_UP(..., BITS_PER_BYTE) that could be converted to
GEN_SSEU_STRIDE() in patch 2. I noticed you update them to a new
variable in the next patch, but for consistency it might still be worth
updating them all in patch 2 or at least mention in the commit message
of patch 2 that the remaining cases are updated by a follow-up patch in
the series. Patch 2 is quite small, so you could also just squash it
into patch 6 to avoid the split.
Daniele
On 5/1/19 8:34 AM, Stuart Summers wrote:
Additionally, ensure these are all prefixed with intel_sseu_*
to match the convention of other functions in i915.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 54 +++
drivers/gpu/drm/i915/gt/intel_sseu.h | 57 +++-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 69
5 files changed, 102 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7f448f3bea0b..4a0b82fc108c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -8,6 +8,60 @@
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
+unsigned int
+intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
+{
+ unsigned int i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+ total += hweight8(sseu->subslice_mask[i]);
+
+ return total;
+}
+
+unsigned int
+intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
+static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
+int subslice)
+{
+ int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+ BITS_PER_BYTE);
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ return slice * slice_stride + subslice * subslice_stride;
+}
+
+u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
+ int subslice)
+{
+ int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
+ u16 eu_mask)
+{
+ int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 029e71d8f140..56e3721ae83f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,58 +63,17 @@ intel_sseu_from_device_info(const struct sseu_dev_info
*sseu)
return value;
}
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
-{
- unsigned int i, total = 0;
-
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
+unsigned int
+intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
- return total;
-}
+unsigned int
+intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
-static inline unsigned int
-sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
-{
- return hweight8(sseu->subslice_mask[slice]);
-}
-
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
- BITS_PER_BYTE);
- int slice_stride = sseu->max_subslices * subslice_stride;
-
- return slice * slice_stride + subslice * subslice_stride;
-}
+u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
+ int subslice);
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
- int slice,
Re: [Intel-gfx] [PATCH 6/6] drm/i915: Expand subslice mask
On Wed, 2019-05-01 at 19:29 +0100, Tvrtko Ursulin wrote:
> On 01/05/2019 19:22, Tvrtko Ursulin wrote:
>
> [snip]
>
> > > +#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2)
> > > +
> > > +static u8 *
> > > +subslice_per_slice_str(u8 *buf, const struct sseu_dev_info
> > > *sseu, u8
> > > slice)
> > > +{
> > > +int i;
> > > +u8 ss_offset = slice * sseu->ss_stride;
> > > +
> > > +GEM_BUG_ON(slice >= sseu->max_slices);
> > > +
> > > +memset(buf, 0, SS_STR_MAX_SIZE);
> >
> > I suggest a more hardened approach of caller passing in the buffer
> > size,
> > since it is their buffer.
Not a bad idea. I had the define to make this explicit and handle the
future cases, but probably right it's better to isolate this. I'll make
the change in the next series update.
>
> Having said this..
>
> > > +
> > > +/*
> > > + * Print subslice information in reverse order to match
> > > + * userspace expectations.
> > > + */
> > > +for (i = 0; i < sseu->ss_stride; i++)
> > > +sprintf([i * 2], "%02x",
> > > +sseu->subslice_mask[ss_offset + sseu->ss_stride -
> > > +(i + 1)]);
>
> ...sprintf also needs to check against overflowing the buffer.
> (Relationship between loop boundary (ss_stride) and buffer size is a
> bit
> decoupled.)
I'll add the check, makes sense.
>
> And buffer should probably be char *.
No problem. I'll make this change. Thanks for the feedback!
- Stuart
>
> Regards,
>
> Tvrtko
>
> > > +
> > > +return buf;
> > > +}
> > > +
> > > static void sseu_dump(const struct sseu_dev_info *sseu, struct
> > > drm_printer *p)
> > > {
> > > int s;
> > > +u8 buf[SS_STR_MAX_SIZE];
> > > drm_printf(p, "slice total: %u, mask=%04x\n",
> > > hweight8(sseu->slice_mask), sseu->slice_mask);
> > > drm_printf(p, "subslice total: %u\n",
> > > intel_sseu_subslice_total(sseu));
> > > for (s = 0; s < sseu->max_slices; s++) {
> > > -drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
> > > +drm_printf(p, "slice%d: %u subslices, mask=%s\n",
> > > s, intel_sseu_subslices_per_slice(sseu, s),
> > > - sseu->subslice_mask[s]);
> > > + subslice_per_slice_str(buf, sseu, s));
> > > }
> > > drm_printf(p, "EU total: %u\n", sseu->eu_total);
> > > drm_printf(p, "EU per subslice: %u\n", sseu-
> > > >eu_per_subslice);
> > > @@ -118,6 +143,7 @@ void intel_device_info_dump_topology(const
> > > struct
> > > sseu_dev_info *sseu,
> > >struct drm_printer *p)
> > > {
> > > int s, ss;
> > > +u8 buf[SS_STR_MAX_SIZE];
> > > if (sseu->max_slices == 0) {
> > > drm_printf(p, "Unavailable\n");
> > > @@ -125,9 +151,9 @@ void intel_device_info_dump_topology(const
> > > struct
> > > sseu_dev_info *sseu,
> > > }
> > > for (s = 0; s < sseu->max_slices; s++) {
> > > -drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
> > > +drm_printf(p, "slice%d: %u subslice(s) (0x%s):\n",
> > > s, intel_sseu_subslices_per_slice(sseu, s),
> > > - sseu->subslice_mask[s]);
> > > + subslice_per_slice_str(buf, sseu, s));
> > > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > > u16 enabled_eus = intel_sseu_get_eus(sseu, s, ss);
> > > @@ -156,15 +182,10 @@ static void gen11_sseu_info_init(struct
> > > drm_i915_private *dev_priv)
> > > u8 eu_en;
> > > int s;
> > > -if (IS_ELKHARTLAKE(dev_priv)) {
> > > -sseu->max_slices = 1;
> > > -sseu->max_subslices = 4;
> > > -sseu->max_eus_per_subslice = 8;
> > > -} else {
> > > -sseu->max_slices = 1;
> > > -sseu->max_subslices = 8;
> > > -sseu->max_eus_per_subslice = 8;
> > > -}
> > > +if (IS_ELKHARTLAKE(dev_priv))
> > > +intel_sseu_set_info(sseu, 1, 4, 8);
> > > +else
> > > +intel_sseu_set_info(sseu, 1, 8, 8);
> > > s_en = I915_READ(GEN11_GT_SLICE_ENABLE) &
> > > GEN11_GT_S_ENA_MASK;
> > > ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
> > > @@ -177,9 +198,11 @@ static void gen11_sseu_info_init(struct
> > > drm_i915_private *dev_priv)
> > > int ss;
> > > sseu->slice_mask |= BIT(s);
> > > -sseu->subslice_mask[s] = (ss_en >> ss_idx) &
> > > ss_en_mask;
> > > +sseu->subslice_mask[s * sseu->ss_stride] =
> > > +(ss_en >> ss_idx) & ss_en_mask;
> > > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > > -if (sseu->subslice_mask[s] & BIT(ss))
> > > +if (sseu->subslice_mask[s * sseu->ss_stride] &
> > > +BIT(ss))
> > > intel_sseu_set_eus(sseu, s, ss, eu_en);
> > > }
> > > }
> > > @@ -201,23 +224,10 @@ static void gen10_sseu_info_init(struct
> > > drm_i915_private *dev_priv)
> > > const int eu_mask =
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
On Wed, 2019-05-01 at 10:54 -0700, Daniele Ceraolo Spurio wrote:
>
> On 5/1/19 8:34 AM, Stuart Summers wrote:
> > In the GETPARAM ioctl handler, use a local variable to consolidate
> > usage of SSEU runtime info.
> >
> > v2: add const to sseu_dev_info variable
> >
> > Cc: Daniele Ceraolo Spurio
> > Signed-off-by: Stuart Summers
>
Thanks for the review!
-Stuart
> Reviewed-by: Daniele Ceraolo Spurio
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 11 ++-
> > 1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 21dac5a09fbe..c376244c19c4 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -324,6 +324,7 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> > {
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct pci_dev *pdev = dev_priv->drm.pdev;
> > + const struct sseu_dev_info *sseu = _INFO(dev_priv)-
> > >sseu;
> > drm_i915_getparam_t *param = data;
> > int value;
> >
> > @@ -377,12 +378,12 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> > value = i915_cmd_parser_get_version(dev_priv);
> > break;
> > case I915_PARAM_SUBSLICE_TOTAL:
> > - value = sseu_subslice_total(_INFO(dev_priv)-
> > >sseu);
> > + value = sseu_subslice_total(sseu);
> > if (!value)
> > return -ENODEV;
> > break;
> > case I915_PARAM_EU_TOTAL:
> > - value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
> > + value = sseu->eu_total;
> > if (!value)
> > return -ENODEV;
> > break;
> > @@ -399,7 +400,7 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> > value = HAS_POOLED_EU(dev_priv);
> > break;
> > case I915_PARAM_MIN_EU_IN_POOL:
> > - value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
> > + value = sseu->min_eu_in_pool;
> > break;
> > case I915_PARAM_HUC_STATUS:
> > value = intel_huc_check_status(_priv->huc);
> > @@ -449,12 +450,12 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> > value = intel_engines_has_context_isolation(dev_priv);
> > break;
> > case I915_PARAM_SLICE_MASK:
> > - value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
> > + value = sseu->slice_mask;
> > if (!value)
> > return -ENODEV;
> > break;
> > case I915_PARAM_SUBSLICE_MASK:
> > - value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
> > + value = sseu->subslice_mask[0];
> > if (!value)
> > return -ENODEV;
> > break;
> >
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Add macro for SSEU stride calculation
On Wed, 2019-05-01 at 11:11 -0700, Daniele Ceraolo Spurio wrote:
>
> On 5/1/19 8:34 AM, Stuart Summers wrote:
> > Subslice stride and EU stride are calculated multiple times in
> > i915_query. Move this calculation to a macro to reduce code
> > duplication.
> >
> > v2: update headers in intel_sseu.h
> >
> > Cc: Daniele Ceraolo Spurio
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
> > drivers/gpu/drm/i915/i915_query.c| 17 -
> > 2 files changed, 10 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index 73bc824094e8..c0b16b248d4c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -8,11 +8,13 @@
> > #define __INTEL_SSEU_H__
> >
> > #include
> > +#include
> >
> > struct drm_i915_private;
> >
> > #define GEN_MAX_SLICES(6) /* CNL upper bound */
> > #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
> > +#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
>
> What we pass to this macro isn't really a bits count but the maximum
> amount of s/ss/eus. s/bits/max_entry/, or something like that? with
> that:
Makes sense, I'll make the change in the next series post. Thanks for
the review!
-Stuart
>
> Reviewed-by: Daniele Ceraolo Spurio
>
> Daniele
>
> >
> > struct sseu_dev_info {
> > u8 slice_mask;
> > diff --git a/drivers/gpu/drm/i915/i915_query.c
> > b/drivers/gpu/drm/i915/i915_query.c
> > index 782183b78f49..7c1708c22811 100644
> > --- a/drivers/gpu/drm/i915/i915_query.c
> > +++ b/drivers/gpu/drm/i915/i915_query.c
> > @@ -37,6 +37,8 @@ static int query_topology_info(struct
> > drm_i915_private *dev_priv,
> > const struct sseu_dev_info *sseu = _INFO(dev_priv)-
> > >sseu;
> > struct drm_i915_query_topology_info topo;
> > u32 slice_length, subslice_length, eu_length, total_length;
> > + u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> > + u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> > int ret;
> >
> > if (query_item->flags != 0)
> > @@ -48,12 +50,10 @@ static int query_topology_info(struct
> > drm_i915_private *dev_priv,
> > BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> >
> > slice_length = sizeof(sseu->slice_mask);
> > - subslice_length = sseu->max_slices *
> > - DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
> > - eu_length = sseu->max_slices * sseu->max_subslices *
> > - DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE);
> > -
> > - total_length = sizeof(topo) + slice_length + subslice_length +
> > eu_length;
> > + subslice_length = sseu->max_slices * subslice_stride;
> > + eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
> > + total_length = sizeof(topo) + slice_length + subslice_length +
> > + eu_length;
> >
> > ret = copy_query_item(, sizeof(topo), total_length,
> > query_item);
> > @@ -69,10 +69,9 @@ static int query_topology_info(struct
> > drm_i915_private *dev_priv,
> > topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
> >
> > topo.subslice_offset = slice_length;
> > - topo.subslice_stride = DIV_ROUND_UP(sseu->max_subslices,
> > BITS_PER_BYTE);
> > + topo.subslice_stride = subslice_stride;
> > topo.eu_offset = slice_length + subslice_length;
> > - topo.eu_stride =
> > - DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE);
> > + topo.eu_stride = eu_stride;
> >
> > if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> >, sizeof(topo)))
> >
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Re: [Intel-gfx] [PATCH 3/6] drm/i915: Move calculation of subslices per slice to new function
On Wed, 2019-05-01 at 11:14 -0700, Daniele Ceraolo Spurio wrote:
>
> On 5/1/19 8:34 AM, Stuart Summers wrote:
> > Add a new function to return the number of subslices per slice to
> > consolidate code usage.
> >
> > v2: rebase on changes to move sseu struct to intel_sseu.h
> >
> > Cc: Daniele Ceraolo Spurio
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
> > 3 files changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index c0b16b248d4c..f5ff6b7a756a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -63,6 +63,12 @@ intel_sseu_from_device_info(const struct
> > sseu_dev_info *sseu)
> > return value;
> > }
> >
> > +static inline unsigned int
> > +sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8
> > slice)
>
> This is exposed, so needs an intel_* prefix. with that:
Will change in the next series update. Thanks for the review!
-Stuart
>
> Reviewed-by: Daniele Ceraolo Spurio
>
> Daniele
>
> > +{
> > + return hweight8(sseu->subslice_mask[slice]);
> > +}
> > +
> > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
> > const struct intel_sseu *req_sseu);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 0e4dffcd4da4..fe854c629a32 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4185,7 +4185,7 @@ static void i915_print_sseu_info(struct
> > seq_file *m, bool is_available_info,
> >sseu_subslice_total(sseu));
> > for (s = 0; s < fls(sseu->slice_mask); s++) {
> > seq_printf(m, " %s Slice%i subslices: %u\n", type,
> > - s, hweight8(sseu->subslice_mask[s]));
> > + s, sseu_subslices_per_slice(sseu, s));
> > }
> > seq_printf(m, " %s EU Total: %u\n", type,
> >sseu->eu_total);
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 6af480b95bc6..559cf0d0628e 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info
> > *sseu, struct drm_printer *p)
> > drm_printf(p, "subslice total: %u\n",
> > sseu_subslice_total(sseu));
> > for (s = 0; s < sseu->max_slices; s++) {
> > drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
> > - s, hweight8(sseu->subslice_mask[s]),
> > + s, sseu_subslices_per_slice(sseu, s),
> >sseu->subslice_mask[s]);
> > }
> > drm_printf(p, "EU total: %u\n", sseu->eu_total);
> > @@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const
> > struct sseu_dev_info *sseu,
> >
> > for (s = 0; s < sseu->max_slices; s++) {
> > drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
> > - s, hweight8(sseu->subslice_mask[s]),
> > + s, sseu_subslices_per_slice(sseu, s),
> >sseu->subslice_mask[s]);
> >
> > for (ss = 0; ss < sseu->max_subslices; ss++) {
> >
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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Move sseu helper functions to intel_sseu.h
On Wed, 2019-05-01 at 11:48 -0700, Daniele Ceraolo Spurio wrote:
>
> On 5/1/19 8:34 AM, Stuart Summers wrote:
> > v2: fix spacing from checkpatch warning
> >
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 47
> >
> > drivers/gpu/drm/i915/intel_device_info.h | 47 -
> > ---
> > 2 files changed, 47 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index f5ff6b7a756a..029e71d8f140 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -63,12 +63,59 @@ intel_sseu_from_device_info(const struct
> > sseu_dev_info *sseu)
> > return value;
> > }
> >
> > +static inline unsigned int sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > +{
> > + unsigned int i, total = 0;
> > +
> > + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > + total += hweight8(sseu->subslice_mask[i]);
> > +
> > + return total;
> > +}
> > +
> > static inline unsigned int
> > sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8
> > slice)
> > {
> > return hweight8(sseu->subslice_mask[slice]);
> > }
> >
> > +static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> > + int slice, int subslice)
> > +{
> > + int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > + BITS_PER_BYTE);
> > + int slice_stride = sseu->max_subslices * subslice_stride;
> > +
> > + return slice * slice_stride + subslice * subslice_stride;
> > +}
> > +
> > +static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> > + int slice, int subslice)
> > +{
> > + int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > + u16 eu_mask = 0;
> > +
> > + for (i = 0;
> > +i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > + eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
> > + (i * BITS_PER_BYTE);
> > + }
> > +
> > + return eu_mask;
> > +}
> > +
> > +static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> > + int slice, int subslice, u16 eu_mask)
> > +{
> > + int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > +
> > + for (i = 0;
> > +i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > + sseu->eu_mask[offset + i] =
> > + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> > + }
> > +}
> > +
>
> AFAICS sseu_get_eus() and sseu_set_eus() are only used by sseu-
> related
> functions in device_info.c and sseu_eu_idx() is only used by those 2,
> so
> we can make all 3 of them static in that file. We should also
> migrate
> all of the sseu code from device_info.c to intel_sseu.c for
> consistency;
> I'm ok with that being done as a follow up if you prefer to avoid it
> in
> this series.
>
> I was also about to mention adding the intel_* prefix to the
> remaining
> functions but then I realized you add it in the next patch. My
> personal
> preference would be to do that in this patch, but I'm not going to
> block
> on it.
Not sure why I missed this one, but good catch! I'll post a fix in the
next series update.
-Stuart
>
> Daniele
>
> > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
> > const struct intel_sseu *req_sseu);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index 5a2e17d6146b..6412a9c72898 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -218,53 +218,6 @@ struct intel_driver_caps {
> > bool has_logical_contexts:1;
> > };
> >
> > -static inline unsigned int sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > -{
> > - unsigned int i, total = 0;
> > -
> > - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > - total += hweight8(sseu->subslice_mask[i]);
> > -
> > - return total;
> > -}
> > -
> > -static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> > - int slice, int subslice)
> > -{
> > - int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > - BITS_PER_BYTE);
> > - int slice_stride = sseu->max_subslices * subslice_stride;
> > -
> > - return slice * slice_stride + subslice * subslice_stride;
> > -}
> > -
> > -static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> > - int slice, int subslice)
> > -{
> > - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > - u16 eu_mask = 0;
> > -
> > - for (i = 0;
> > -i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > - eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
> > -
[Intel-gfx] [PULL] drm-misc-next-fixes
Hi Da.*, Quiet week since the last PR, I'd say we're ready for the merge window! drm-misc-next-fixes-2019-05-01: core: restore drm mmap_range size back to 1TB (Philip) sphinx: squash warning (Sean) Cc: Philip Yang Cc: Sean Paul Cheers, Sean The following changes since commit 1de7259275ca4ebc66459de6620558d3e38d4142: drm/fb-helper: Fix drm_fb_helper_firmware_config() NULL pointer deref (2019-04-24 15:57:43 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2019-05-01 for you to fetch changes up to 761e473f6b23f206862d904a1a5fcbc012656b47: drm/gem: Fix sphinx warnings (2019-04-25 10:02:10 -0400) core: restore drm mmap_range size back to 1TB (Philip) sphinx: squash warning (Sean) Cc: Philip Yang Cc: Sean Paul Philip Yang (1): drm: increase drm mmap_range size to 1TB Sean Paul (1): drm/gem: Fix sphinx warnings drivers/gpu/drm/drm_gem.c | 10 +- include/drm/drm_vma_manager.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Move sseu helper functions to intel_sseu.h
On 5/1/19 8:34 AM, Stuart Summers wrote:
v2: fix spacing from checkpatch warning
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 47
drivers/gpu/drm/i915/intel_device_info.h | 47
2 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index f5ff6b7a756a..029e71d8f140 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,12 +63,59 @@ intel_sseu_from_device_info(const struct sseu_dev_info
*sseu)
return value;
}
+static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
+{
+ unsigned int i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+ total += hweight8(sseu->subslice_mask[i]);
+
+ return total;
+}
+
static inline unsigned int
sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
return hweight8(sseu->subslice_mask[slice]);
}
+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+ BITS_PER_BYTE);
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ return slice * slice_stride + subslice * subslice_stride;
+}
+
+static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+static inline void sseu_set_eus(struct sseu_dev_info *sseu,
+ int slice, int subslice, u16 eu_mask)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
AFAICS sseu_get_eus() and sseu_set_eus() are only used by sseu-related
functions in device_info.c and sseu_eu_idx() is only used by those 2, so
we can make all 3 of them static in that file. We should also migrate
all of the sseu code from device_info.c to intel_sseu.c for consistency;
I'm ok with that being done as a follow up if you prefer to avoid it in
this series.
I was also about to mention adding the intel_* prefix to the remaining
functions but then I realized you add it in the next patch. My personal
preference would be to do that in this patch, but I'm not going to block
on it.
Daniele
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 5a2e17d6146b..6412a9c72898 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -218,53 +218,6 @@ struct intel_driver_caps {
bool has_logical_contexts:1;
};
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
-{
- unsigned int i, total = 0;
-
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
-
- return total;
-}
-
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
- BITS_PER_BYTE);
- int slice_stride = sseu->max_subslices * subslice_stride;
-
- return slice * slice_stride + subslice * subslice_stride;
-}
-
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
- (i * BITS_PER_BYTE);
- }
-
- return eu_mask;
-}
-
-static inline void sseu_set_eus(struct sseu_dev_info *sseu,
- int slice, int subslice, u16 eu_mask)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
- }
-}
-
const char
Re: [Intel-gfx] [PATCH 6/6] drm/i915: Expand subslice mask
On 01/05/2019 19:22, Tvrtko Ursulin wrote:
[snip]
+#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2)
+
+static u8 *
+subslice_per_slice_str(u8 *buf, const struct sseu_dev_info *sseu, u8
slice)
+{
+ int i;
+ u8 ss_offset = slice * sseu->ss_stride;
+
+ GEM_BUG_ON(slice >= sseu->max_slices);
+
+ memset(buf, 0, SS_STR_MAX_SIZE);
I suggest a more hardened approach of caller passing in the buffer size,
since it is their buffer.
Having said this..
+
+ /*
+ * Print subslice information in reverse order to match
+ * userspace expectations.
+ */
+ for (i = 0; i < sseu->ss_stride; i++)
+ sprintf([i * 2], "%02x",
+ sseu->subslice_mask[ss_offset + sseu->ss_stride -
+ (i + 1)]);
...sprintf also needs to check against overflowing the buffer.
(Relationship between loop boundary (ss_stride) and buffer size is a bit
decoupled.)
And buffer should probably be char *.
Regards,
Tvrtko
+
+ return buf;
+}
+
static void sseu_dump(const struct sseu_dev_info *sseu, struct
drm_printer *p)
{
int s;
+ u8 buf[SS_STR_MAX_SIZE];
drm_printf(p, "slice total: %u, mask=%04x\n",
hweight8(sseu->slice_mask), sseu->slice_mask);
drm_printf(p, "subslice total: %u\n",
intel_sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
+ drm_printf(p, "slice%d: %u subslices, mask=%s\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ subslice_per_slice_str(buf, sseu, s));
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
@@ -118,6 +143,7 @@ void intel_device_info_dump_topology(const struct
sseu_dev_info *sseu,
struct drm_printer *p)
{
int s, ss;
+ u8 buf[SS_STR_MAX_SIZE];
if (sseu->max_slices == 0) {
drm_printf(p, "Unavailable\n");
@@ -125,9 +151,9 @@ void intel_device_info_dump_topology(const struct
sseu_dev_info *sseu,
}
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+ drm_printf(p, "slice%d: %u subslice(s) (0x%s):\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ subslice_per_slice_str(buf, sseu, s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = intel_sseu_get_eus(sseu, s, ss);
@@ -156,15 +182,10 @@ static void gen11_sseu_info_init(struct
drm_i915_private *dev_priv)
u8 eu_en;
int s;
- if (IS_ELKHARTLAKE(dev_priv)) {
- sseu->max_slices = 1;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
- } else {
- sseu->max_slices = 1;
- sseu->max_subslices = 8;
- sseu->max_eus_per_subslice = 8;
- }
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_sseu_set_info(sseu, 1, 4, 8);
+ else
+ intel_sseu_set_info(sseu, 1, 8, 8);
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
@@ -177,9 +198,11 @@ static void gen11_sseu_info_init(struct
drm_i915_private *dev_priv)
int ss;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+ sseu->subslice_mask[s * sseu->ss_stride] =
+ (ss_en >> ss_idx) & ss_en_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
- if (sseu->subslice_mask[s] & BIT(ss))
+ if (sseu->subslice_mask[s * sseu->ss_stride] &
+ BIT(ss))
intel_sseu_set_eus(sseu, s, ss, eu_en);
}
}
@@ -201,23 +224,10 @@ static void gen10_sseu_info_init(struct
drm_i915_private *dev_priv)
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
+ intel_sseu_set_info(sseu, 6, 4, 8);
+
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- sseu->max_slices = 6;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
-
- subslice_mask = (1 << 4) - 1;
- subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
- GEN10_F2_SS_DIS_SHIFT);
-
- /*
- * Slice0 can have up to 3 subslices, but there are only 2 in
- * slice1/2.
- */
- sseu->subslice_mask[0] = subslice_mask;
- for (s = 1; s < sseu->max_slices; s++)
- sseu->subslice_mask[s] = subslice_mask & 0x3;
/* Slice0 */
eu_en = ~I915_READ(GEN8_EU_DISABLE0);
@@ -242,14 +252,22 @@ static void gen10_sseu_info_init(struct
drm_i915_private *dev_priv)
eu_en = ~I915_READ(GEN10_EU_DISABLE3);
intel_sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
- /* Do a second pass where we mark the subslices disabled if all
their
- * eus are off.
Re: [Intel-gfx] [PATCH 6/6] drm/i915: Expand subslice mask
Just one drive by below...
On 01/05/2019 16:34, Stuart Summers wrote:
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: fix spacing in set_sseu_info args
use set_sseu_info to initialize sseu data when building
device status in debugfs
rename variables in intel_engine_types.h to avoid checkpatch
warnings
v3: update headers in intel_sseu.h
v4: add const to some sseu_dev_info variables
use sseu->eu_stride for EU stride calculations
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 49 +--
drivers/gpu/drm/i915/gt/intel_sseu.h | 16 ++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 44 +++---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c| 5 +-
drivers/gpu/drm/i915/i915_query.c| 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 142 +++
11 files changed, 198 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6e40f8ea9a6a..8f7967cc9a50 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -914,7 +914,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private
*dev_priv)
const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
u32 mcr_s_ss_select;
u32 slice = fls(sseu->slice_mask);
- u32 subslice = fls(sseu->subslice_mask[slice]);
+ u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
if (IS_GEN(dev_priv, 10))
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -990,6 +990,7 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *dev_priv = engine->i915;
+ const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -1007,7 +1008,8 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice,
+subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(dev_priv, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d64e33f8427..1710546a2446 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct
intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
-(slice__) < I915_MAX_SLICES; \
-(subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ?
(subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) &&
\
- (BIT(subslice__) &
instdone_subslice_mask(dev_priv__)))
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? \
+ 1 : (sseu___)->slice_mask) & \
+ BIT(slice___)) \
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+BIT(subslice__ % BITS_PER_BYTE)) \
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+
Re: [Intel-gfx] [PATCH 3/6] drm/i915: Move calculation of subslices per slice to new function
On 5/1/19 8:34 AM, Stuart Summers wrote:
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index c0b16b248d4c..f5ff6b7a756a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
This is exposed, so needs an intel_* prefix. with that:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0e4dffcd4da4..fe854c629a32 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4185,7 +4185,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool
is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu,
struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct
sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
___
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Add macro for SSEU stride calculation
On 5/1/19 8:34 AM, Stuart Summers wrote:
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
v2: update headers in intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
drivers/gpu/drm/i915/i915_query.c| 17 -
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 73bc824094e8..c0b16b248d4c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -8,11 +8,13 @@
#define __INTEL_SSEU_H__
#include
+#include
struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
+#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
What we pass to this macro isn't really a bits count but the maximum
amount of s/ss/eus. s/bits/max_entry/, or something like that? with that:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
struct sseu_dev_info {
u8 slice_mask;
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index 782183b78f49..7c1708c22811 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,6 +37,8 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -48,12 +50,10 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices *
- DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
- eu_length = sseu->max_slices * sseu->max_subslices *
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
-
- total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
+ subslice_length = sseu->max_slices * subslice_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ total_length = sizeof(topo) + slice_length + subslice_length +
+ eu_length;
ret = copy_query_item(, sizeof(topo), total_length,
query_item);
@@ -69,10 +69,9 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
+ topo.subslice_stride = subslice_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride =
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+ topo.eu_stride = eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
, sizeof(topo)))
___
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Re: [Intel-gfx] [PATCH 1/6] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
On 5/1/19 8:34 AM, Stuart Summers wrote:
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
v2: add const to sseu_dev_info variable
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 21dac5a09fbe..c376244c19c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -324,6 +324,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
+ const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
drm_i915_getparam_t *param = data;
int value;
@@ -377,12 +378,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(sseu);
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
+ value = sseu->eu_total;
if (!value)
return -ENODEV;
break;
@@ -399,7 +400,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = sseu->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
value = intel_huc_check_status(_priv->huc);
@@ -449,12 +450,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
+ value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
+ value = sseu->subslice_mask[0];
if (!value)
return -ENODEV;
break;
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Refactor oa object to better manage resources
== Series Details == Series: drm/i915/perf: Refactor oa object to better manage resources URL : https://patchwork.freedesktop.org/series/60176/ State : success == Summary == CI Bug Log - changes from CI_DRM_6021 -> Patchwork_12929 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60176/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12929 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12929/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@gem_render_tiled_blits@basic: - fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-icl-y/igt@gem_render_tiled_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12929/fi-icl-y/igt@gem_render_tiled_bl...@basic.html Possible fixes * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [DMESG-WARN][5] ([fdo#103841]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12929/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][7] ([fdo#109271]) -> [INCOMPLETE][8] ([fdo#107807]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12929/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (52 -> 46) -- Additional (1): fi-pnv-d510 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6021 -> Patchwork_12929 CI_DRM_6021: 850aa4220e8bf7609b03bf89bce146305704bec6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12929: aec4c50375a0a7a76b36c067372e0ed0a6326e0e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == aec4c50375a0 drm/i915/perf: Refactor oa object to better manage resources == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12929/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/14] drm/i915/hangcheck: Track context changes (rev4)
== Series Details == Series: series starting with [01/14] drm/i915/hangcheck: Track context changes (rev4) URL : https://patchwork.freedesktop.org/series/60153/ State : success == Summary == CI Bug Log - changes from CI_DRM_6021 -> Patchwork_12928 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60153/revisions/4/mbox/ Known issues Here are the changes found in Patchwork_12928 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [PASS][1] -> [INCOMPLETE][2] ([fdo#108602] / [fdo#108744]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12928/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html Possible fixes * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12928/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][5] ([fdo#109271]) -> [INCOMPLETE][6] ([fdo#107807]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12928/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (52 -> 46) -- Additional (1): fi-pnv-d510 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6021 -> Patchwork_12928 CI_DRM_6021: 850aa4220e8bf7609b03bf89bce146305704bec6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12928: 01f589b56645790b5775e319e3f4ff827e46 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 01f589b56645 drm/i915: Convert inconsistent static engine tables into an init error f2d6eddeb32d drm/i915: Bump signaler priority on adding a waiter 5218802aa1f6 drm/i915: Pass i915_sched_node around internally 026843605d46 drm/i915: Rearrange i915_scheduler.c cf13ef929e7c drm/i915/execlists: Don't apply priority boost for resets 5b463d70273d drm/i915: Delay semaphore submission until the start of the signaler 2f91bc3c1649 drm/i915: Only reschedule the submission tasklet if preemption is possible 5bd685806aa5 drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches) 639f5996c165 drm/i915: Cancel retire_worker on parking 79fa465f1d46 drm/i915: Remove delay for idle_work fcabf363d051 drm/i915: Leave engine parking to the engines 3067553e8d99 drm/i915/execlists: Flush the tasklet on parking 784762bc47d9 drm/i915: Include fence signaled bit in print_request() d288339c7974 drm/i915/hangcheck: Track context changes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12928/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/perf: Refactor oa object to better manage resources
== Series Details == Series: drm/i915/perf: Refactor oa object to better manage resources URL : https://patchwork.freedesktop.org/series/60176/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/perf: Refactor oa object to better manage resources -O:drivers/gpu/drm/i915/i915_perf.c:1430:15: warning: memset with byte count of 16777216 -O:drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1495:15: warning: memset with byte count of 16777216 -drivers/gpu/drm/i915/selftests/../i915_drv.h:3448:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3443:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Complete both freed-object passes before draining the workqueue
On Wed, 1 May 2019 at 14:58, Chris Wilson wrote: > > The workqueue code complains viciously if we try to queue more work onto > the queue while attampting to drain it. As we asynchronously free > objects and defer their enqueuing with RCU, it is quite tricky to > quiesce the system before attempting to drain the workqueue. Yet drain > we must to ensure that the worker is idle before unloading the module. > > Give the freed object drain 3 whole passes with multiple rcu_barrier() > to give the defer freeing of several levels each protected by RCU and > needing a grace period before its parent can be freed, ultimately > resulting in a GEM object being freed after another RCU period. > > A consequence is that it will make module unload even slower. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110550 > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: Refactor oa object to better manage resources
== Series Details ==
Series: drm/i915/perf: Refactor oa object to better manage resources
URL : https://patchwork.freedesktop.org/series/60176/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aec4c50375a0 drm/i915/perf: Refactor oa object to better manage resources
-:1161: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around
'stream->oa_buffer.last_ctx_id ==
stream->specific_ctx_id'
#1161: FILE: drivers/gpu/drm/i915/i915_perf.c:791:
+ if (!dev_priv->perf.exclusive_stream->ctx ||
+ stream->specific_ctx_id == ctx_id ||
+ (stream->oa_buffer.last_ctx_id ==
+stream->specific_ctx_id) ||
reason & OAREPORT_REASON_CTX_SWITCH) {
-:1520: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#1520: FILE: drivers/gpu/drm/i915/i915_perf.c:1367:
+ BUG_ON(stream != dev_priv->perf.exclusive_stream);
-:1792: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#1792: FILE: drivers/gpu/drm/i915/i915_perf.c:1838:
+ _MASKED_BIT_ENABLE(
-:2271: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#2271: FILE: drivers/gpu/drm/i915/i915_perf.c:3479:
+ dev_priv->perf.gen8_valid_ctx_bit = (1<<25);
^
-:2279: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#2279: FILE: drivers/gpu/drm/i915/i915_perf.c:3484:
+ dev_priv->perf.gen8_valid_ctx_bit = (1<<16);
^
-:2305: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#2305: FILE: drivers/gpu/drm/i915/i915_perf.c:3502:
+ dev_priv->perf.gen8_valid_ctx_bit = (1<<16);
^
total: 0 errors, 1 warnings, 5 checks, 2163 lines checked
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/14] drm/i915/hangcheck: Track context changes (rev4)
== Series Details == Series: series starting with [01/14] drm/i915/hangcheck: Track context changes (rev4) URL : https://patchwork.freedesktop.org/series/60153/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/hangcheck: Track context changes Okay! Commit: drm/i915: Include fence signaled bit in print_request() Okay! Commit: drm/i915/execlists: Flush the tasklet on parking Okay! Commit: drm/i915: Leave engine parking to the engines Okay! Commit: drm/i915: Remove delay for idle_work Okay! Commit: drm/i915: Cancel retire_worker on parking Okay! Commit: drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches) Okay! Commit: drm/i915: Only reschedule the submission tasklet if preemption is possible -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) Commit: drm/i915: Delay semaphore submission until the start of the signaler Okay! Commit: drm/i915/execlists: Don't apply priority boost for resets Okay! Commit: drm/i915: Rearrange i915_scheduler.c Okay! Commit: drm/i915: Pass i915_sched_node around internally Okay! Commit: drm/i915: Bump signaler priority on adding a waiter Okay! Commit: drm/i915: Convert inconsistent static engine tables into an init error Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/14] drm/i915/hangcheck: Track context changes (rev3)
== Series Details == Series: series starting with [01/14] drm/i915/hangcheck: Track context changes (rev3) URL : https://patchwork.freedesktop.org/series/60153/ State : success == Summary == CI Bug Log - changes from CI_DRM_6021 -> Patchwork_12927 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60153/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_12927 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [PASS][1] -> [DMESG-WARN][2] ([fdo#105541]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12927/fi-skl-6770hq/igt@i915_pm_...@module-reload.html Possible fixes * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12927/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][5] ([fdo#109271]) -> [INCOMPLETE][6] ([fdo#107807]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12927/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (52 -> 46) -- Additional (1): fi-pnv-d510 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6021 -> Patchwork_12927 CI_DRM_6021: 850aa4220e8bf7609b03bf89bce146305704bec6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12927: aa242739648eef99230bfe29776b2b5a8dfb0953 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == aa242739648e drm/i915: Convert inconsistent static engine tables into an init error acea16a2683b drm/i915: Bump signaler priority on adding a waiter 4d93039126e6 drm/i915: Pass i915_sched_node around internally 237dea2e6369 drm/i915: Rearrange i915_scheduler.c 9fb71130c987 drm/i915/execlists: Don't apply priority boost for resets 89b9e63d0de9 drm/i915: Delay semaphore submission until the start of the signaler aab09ac1c0d0 drm/i915: Only reschedule the submission tasklet if preemption is possible c04e7edf12e3 drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches) 0c4ed77e0ff2 drm/i915: Cancel retire_worker on parking 1373aa28b84f drm/i915: Remove delay for idle_work 9a055938ab47 drm/i915: Leave engine parking to the engines bfb97e815599 drm/i915/execlists: Flush the tasklet on parking abdf4d8765ad drm/i915: Include fence signaled bit in print_request() cecc697e31f0 drm/i915/hangcheck: Track context changes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12927/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/perf: Refactor oa object to better manage resources
The oa object manages the oa buffer and must be allocated when the user
intends to read performance counter snapshots. This can be achieved by
making the oa object part of the stream object which is allocated when a
stream is opened by the user.
Attributes in the oa object that are gen-specific are moved to the perf
object so that they can be initialized on driver load.
The split provides a better separation of the objects used in perf
implementation of i915 driver so that resources are allocated and
initialized only when needed.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 219 +-
drivers/gpu/drm/i915/i915_oa_bdw.c| 30 +-
drivers/gpu/drm/i915/i915_oa_bxt.c| 30 +-
drivers/gpu/drm/i915/i915_oa_cflgt2.c | 30 +-
drivers/gpu/drm/i915/i915_oa_cflgt3.c | 30 +-
drivers/gpu/drm/i915/i915_oa_chv.c| 30 +-
drivers/gpu/drm/i915/i915_oa_cnl.c| 30 +-
drivers/gpu/drm/i915/i915_oa_glk.c| 30 +-
drivers/gpu/drm/i915/i915_oa_hsw.c| 30 +-
drivers/gpu/drm/i915/i915_oa_icl.c| 30 +-
drivers/gpu/drm/i915/i915_oa_kblgt2.c | 30 +-
drivers/gpu/drm/i915/i915_oa_kblgt3.c | 30 +-
drivers/gpu/drm/i915/i915_oa_sklgt2.c | 30 +-
drivers/gpu/drm/i915/i915_oa_sklgt3.c | 30 +-
drivers/gpu/drm/i915/i915_oa_sklgt4.c | 30 +-
drivers/gpu/drm/i915/i915_perf.c | 580 ++
18 files changed, 627 insertions(+), 598 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7f448f3bea0b..fa78df39521a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -32,7 +32,7 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
* cases which disable slices for functional, apart for performance
* reasons. So in this case we select a known stable subset.
*/
- if (!i915->perf.oa.exclusive_stream) {
+ if (!i915->perf.exclusive_stream) {
ctx_sseu = *req_sseu;
} else {
ctx_sseu = intel_sseu_from_device_info(sseu);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 7ae42f2ebfe8..878e71a927de 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -81,8 +81,8 @@ static void sr_oa_regs(struct intel_vgpu_workload *workload,
u32 *reg_state, bool save)
{
struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
- u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
- u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
+ u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset;
+ u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset;
int i = 0;
u32 flex_mmio[] = {
i915_mmio_reg_offset(EU_PERF_CNTL0),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1cea98f8b85c..9536550f11cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1399,6 +1399,86 @@ struct i915_perf_stream {
* @oa_config: The OA configuration used by the stream.
*/
struct i915_oa_config *oa_config;
+
+ /**
+* The OA context specific information.
+*/
+ struct intel_context *pinned_ctx;
+ u32 specific_ctx_id;
+ u32 specific_ctx_id_mask;
+
+ struct hrtimer poll_check_timer;
+ wait_queue_head_t poll_wq;
+ bool pollin;
+
+ bool periodic;
+ int period_exponent;
+
+ /**
+* State of the OA buffer.
+*/
+ struct {
+ struct i915_vma *vma;
+ u8 *vaddr;
+ u32 last_ctx_id;
+ int format;
+ int format_size;
+ int size_exponent;
+
+ /**
+* Locks reads and writes to all head/tail state
+*
+* Consider: the head and tail pointer state needs to be read
+* consistently from a hrtimer callback (atomic context) and
+* read() fop (user context) with tail pointer updates happening
+* in atomic context and head updates in user context and the
+* (unlikely) possibility of read() errors needing to reset all
+* head/tail state.
+*
+* Note: Contention/performance aren't currently a significant
+* concern here considering the relatively low frequency of
+* hrtimer callbacks (5ms period) and that reads typically only
+* happen in response to a hrtimer event and likely complete
+* before the next callback.
+*
+* Note: This lock is not held *while* reading and copying data
+* to userspace so the value of head
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/14] drm/i915/hangcheck: Track context changes (rev3)
== Series Details == Series: series starting with [01/14] drm/i915/hangcheck: Track context changes (rev3) URL : https://patchwork.freedesktop.org/series/60153/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/hangcheck: Track context changes Okay! Commit: drm/i915: Include fence signaled bit in print_request() Okay! Commit: drm/i915/execlists: Flush the tasklet on parking Okay! Commit: drm/i915: Leave engine parking to the engines Okay! Commit: drm/i915: Remove delay for idle_work Okay! Commit: drm/i915: Cancel retire_worker on parking Okay! Commit: drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches) Okay! Commit: drm/i915: Only reschedule the submission tasklet if preemption is possible -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) Commit: drm/i915: Delay semaphore submission until the start of the signaler Okay! Commit: drm/i915/execlists: Don't apply priority boost for resets Okay! Commit: drm/i915: Rearrange i915_scheduler.c Okay! Commit: drm/i915: Pass i915_sched_node around internally Okay! Commit: drm/i915: Bump signaler priority on adding a waiter Okay! Commit: drm/i915: Convert inconsistent static engine tables into an init error Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Bump signaler priority on adding a waiter
The handling of the no-preemption priority level imposes the restriction
that we need to maintain the implied ordering even though preemption is
disabled. Otherwise we may end up with an AB-BA deadlock across multiple
engine due to a real preemption event reordering the no-preemption
WAITs. To resolve this issue we currently promote all requests to WAIT
on unsubmission, however this interferes with the timeslicing
requirement that we do not apply any implicit promotion that will defeat
the round-robin timeslice list. (If we automatically promote the active
request it will go back to the head of the queue and not the tail!)
So we need implicit promotion to prevent reordering around semaphores
where we are not allowed to preempt, and we must avoid implicit
promotion on unsubmission. So instead of at unsubmit, if we apply that
implicit promotion on adding the dependency, we avoid the semaphore
deadlock and we also reduce the gains made by the promotion for user
space waiting. Furthermore, by keeping the earlier dependencies at a
higher level, we reduce the search space for timeslicing without
altering runtime scheduling too badly (no dependencies at all will be
assigned a higher priority for rrul).
v2: Limit the bump to external edges (as originally intended) i.e.
between contexts and out to the user.
Testcase: igt/gem_concurrent_blit
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 12
drivers/gpu/drm/i915/i915_request.c | 9 -
drivers/gpu/drm/i915/i915_scheduler.c | 11 +++
drivers/gpu/drm/i915/i915_scheduler_types.h | 3 ++-
4 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 4b042893dc0e..5b3d8e33f1cf 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -98,12 +98,14 @@ static int live_busywait_preempt(void *arg)
ctx_hi = kernel_context(i915);
if (!ctx_hi)
goto err_unlock;
- ctx_hi->sched.priority = INT_MAX;
+ ctx_hi->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
ctx_lo = kernel_context(i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority = INT_MIN;
+ ctx_lo->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj)) {
@@ -958,12 +960,14 @@ static int live_preempt_hang(void *arg)
ctx_hi = kernel_context(i915);
if (!ctx_hi)
goto err_spin_lo;
- ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
+ ctx_hi->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
ctx_lo = kernel_context(i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
+ ctx_lo->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
for_each_engine(engine, i915, id) {
struct i915_request *rq;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 8cb3ed5531e3..065da1bcbb4c 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -468,15 +468,6 @@ void __i915_request_unsubmit(struct i915_request *request)
/* We may be recursing from the signal callback of another i915 fence */
spin_lock_nested(>lock, SINGLE_DEPTH_NESTING);
- /*
-* As we do not allow WAIT to preempt inflight requests,
-* once we have executed a request, along with triggering
-* any execution callbacks, we must preserve its ordering
-* within the non-preemptible FIFO.
-*/
- BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */
- request->sched.attr.priority |= __NO_PREEMPTION;
-
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
i915_request_cancel_breadcrumb(request);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 05eb50558aba..ea0ab0c8f571 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -388,6 +388,16 @@ bool __i915_sched_node_add_dependency(struct
i915_sched_node *node,
!node_started(signal))
node->flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
+ /*
+* As we do not allow WAIT to preempt inflight requests,
+* once we have executed a request, along with triggering
+* any execution callbacks, we must preserve its ordering
+* within the non-preemptible FIFO.
+*/
+ BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK);
+ if
[Intel-gfx] [PATCH v2] drm/i915: Bump signaler priority on adding a waiter
The handling of the no-preemption priority level imposes the restriction
that we need to maintain the implied ordering even though preemption is
disabled. Otherwise we may end up with an AB-BA deadlock across multiple
engine due to a real preemption event reordering the no-preemption
WAITs. To resolve this issue we currently promote all requests to WAIT
on unsubmission, however this interferes with the timeslicing
requirement that we do not apply any implicit promotion that will defeat
the round-robin timeslice list. (If we automatically promote the active
request it will go back to the head of the queue and not the tail!)
So we need implicit promotion to prevent reordering around semaphores
where we are not allowed to preempt, and we must avoid implicit
promotion on unsubmission. So instead of at unsubmit, if we apply that
implicit promotion on adding the dependency, we avoid the semaphore
deadlock and we also reduce the gains made by the promotion for user
space waiting. Furthermore, by keeping the earlier dependencies at a
higher level, we reduce the search space for timeslicing without
altering runtime scheduling too badly (no dependencies at all will be
assigned a higher priority for rrul).
v2: Limit the bump to external edges (as originally intended) i.e.
between contexts and out to the user.
Testcase: igt/gem_concurrent_blit
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 12
drivers/gpu/drm/i915/i915_request.c | 13 +++--
drivers/gpu/drm/i915/i915_scheduler.c | 15 +--
drivers/gpu/drm/i915/i915_scheduler.h | 3 ++-
drivers/gpu/drm/i915/i915_scheduler_types.h | 3 ++-
5 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 4b042893dc0e..5b3d8e33f1cf 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -98,12 +98,14 @@ static int live_busywait_preempt(void *arg)
ctx_hi = kernel_context(i915);
if (!ctx_hi)
goto err_unlock;
- ctx_hi->sched.priority = INT_MAX;
+ ctx_hi->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
ctx_lo = kernel_context(i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority = INT_MIN;
+ ctx_lo->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj)) {
@@ -958,12 +960,14 @@ static int live_preempt_hang(void *arg)
ctx_hi = kernel_context(i915);
if (!ctx_hi)
goto err_spin_lo;
- ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
+ ctx_hi->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
ctx_lo = kernel_context(i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
+ ctx_lo->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
for_each_engine(engine, i915, id) {
struct i915_request *rq;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 8cb3ed5531e3..1a04894a904b 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -468,15 +468,6 @@ void __i915_request_unsubmit(struct i915_request *request)
/* We may be recursing from the signal callback of another i915 fence */
spin_lock_nested(>lock, SINGLE_DEPTH_NESTING);
- /*
-* As we do not allow WAIT to preempt inflight requests,
-* once we have executed a request, along with triggering
-* any execution callbacks, we must preserve its ordering
-* within the non-preemptible FIFO.
-*/
- BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */
- request->sched.attr.priority |= __NO_PREEMPTION;
-
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
i915_request_cancel_breadcrumb(request);
@@ -861,7 +852,9 @@ i915_request_await_request(struct i915_request *to, struct
i915_request *from)
return 0;
if (to->engine->schedule) {
- ret = i915_sched_node_add_dependency(>sched, >sched);
+ ret = i915_sched_node_add_dependency(>sched,
+>sched,
+I915_DEPENDENCY_EXTERNAL);
if (ret < 0)
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 05eb50558aba..319eb8703451 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -388,6 +388,16 @@ bool
[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev7)
== Series Details == Series: Refactor to expand subslice mask (rev7) URL : https://patchwork.freedesktop.org/series/59742/ State : success == Summary == CI Bug Log - changes from CI_DRM_6021 -> Patchwork_12926 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59742/revisions/7/mbox/ Known issues Here are the changes found in Patchwork_12926 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-icl-y: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-icl-y/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12926/fi-icl-y/igt@gem_ctx_cre...@basic-files.html * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: [PASS][3] -> [DMESG-FAIL][4] ([fdo#110235]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12926/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-glk-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#103359] / [k.org#198133]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-glk-dsi/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12926/fi-glk-dsi/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html Possible fixes * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12926/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][9] ([fdo#109271]) -> [INCOMPLETE][10] ([fdo#107807]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12926/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (52 -> 44) -- Additional (1): fi-pnv-d510 Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-cfl-8109u fi-icl-u3 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6021 -> Patchwork_12926 CI_DRM_6021: 850aa4220e8bf7609b03bf89bce146305704bec6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12926: 3416f0a72f5df37142ab06ae57f55bff003ecf5d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3416f0a72f5d drm/i915: Expand subslice mask bf909e717bcf drm/i915: Remove inline from sseu helper functions 0dbec2982376 drm/i915: Move sseu helper functions to intel_sseu.h be21e44a771d drm/i915: Move calculation of subslices per slice to new function b0f425609a7b drm/i915: Add macro for SSEU stride calculation 47812364a20c drm/i915: Use local variable for SSEU info in GETPARAM ioctl == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12926/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor to expand subslice mask (rev7)
== Series Details == Series: Refactor to expand subslice mask (rev7) URL : https://patchwork.freedesktop.org/series/59742/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Use local variable for SSEU info in GETPARAM ioctl Okay! Commit: drm/i915: Add macro for SSEU stride calculation Okay! Commit: drm/i915: Move calculation of subslices per slice to new function Okay! Commit: drm/i915: Move sseu helper functions to intel_sseu.h Okay! Commit: drm/i915: Remove inline from sseu helper functions Okay! Commit: drm/i915: Expand subslice mask +drivers/gpu/drm/i915/i915_drv.c:460:24: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v11] drm/i915: Engine discovery query
Quoting Tvrtko Ursulin (2019-05-01 16:51:28) > > On 01/05/2019 12:55, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2019-05-01 12:45:36) > >> Hmm.. probably manual check for no holes _and_ alignment is good enough > >> for uAPI since once it's in it's in. Will triple-check. > > > > Yeah, we actually need something more like > > offsetofend(previous_field) == offsetof(next_field) > > > > BUILD_BUG_ON(check_user_struct(info, previous_field, next_field)) ? > > How would you logistically do it? List all struct members for each uapi > struct you want to check? > > Maybe a variadic macro like: > > CHECK_USER_STRUCT_FUNCTION(type, member0, ... memberN); > > Which expands to a dedicated function to check this type, using > va_start/va_end to iterate all members checking for holes. So somewhere > in code we would also need: > > CHECK_USER_STRUCT(type); > > Which would call the function. But thats not build time.. Could be under > debug and selftests I guess. Could even be IGT in this case. > > But I am not to keen in listing each struct member with a > prev/next_field BUILD_BUG_ON. > > Perhaps IGT is indeed a better place to start testing for this. Since we > anyway require each new uAPI to have good IGT coverage. Definitely don't like the idea of doing it manually, I could have just about accepted it if we could have rolled it into a get_user wrapper. We should just go annoy Jani to whip up some Makefile magic to call pahole and check the structs defined in uapi.h -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev7)
== Series Details == Series: Refactor to expand subslice mask (rev7) URL : https://patchwork.freedesktop.org/series/59742/ State : warning == Summary == $ dim checkpatch origin/drm-tip 47812364a20c drm/i915: Use local variable for SSEU info in GETPARAM ioctl b0f425609a7b drm/i915: Add macro for SSEU stride calculation be21e44a771d drm/i915: Move calculation of subslices per slice to new function 0dbec2982376 drm/i915: Move sseu helper functions to intel_sseu.h bf909e717bcf drm/i915: Remove inline from sseu helper functions 3416f0a72f5d drm/i915: Expand subslice mask -:84: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu__' - possible side-effects? #84: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542: +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ + ((IS_GEN(dev_priv__, 7) ? \ + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \ + subslice__ / BITS_PER_BYTE]) & \ +BIT(subslice__ % BITS_PER_BYTE)) \ + -:84: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'slice__' may be better as '(slice__)' to avoid precedence issues #84: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542: +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ + ((IS_GEN(dev_priv__, 7) ? \ + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \ + subslice__ / BITS_PER_BYTE]) & \ +BIT(subslice__ % BITS_PER_BYTE)) \ + -:84: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice__' - possible side-effects? #84: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542: +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ + ((IS_GEN(dev_priv__, 7) ? \ + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \ + subslice__ / BITS_PER_BYTE]) & \ +BIT(subslice__ % BITS_PER_BYTE)) \ + -:84: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'subslice__' may be better as '(subslice__)' to avoid precedence issues #84: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542: +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ + ((IS_GEN(dev_priv__, 7) ? \ + 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \ + subslice__ / BITS_PER_BYTE]) & \ +BIT(subslice__ % BITS_PER_BYTE)) \ + -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ +(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \ + instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \ -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ +(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \ + instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \ -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ +(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \ + instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \ -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ +(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \ + instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \ total: 0 errors, 0 warnings, 8 checks, 692 lines checked ___
Re: [Intel-gfx] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests
On 01/05/2019 12:52, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-01 12:42:59)
+ switch (engine->engine.engine_class) {
+ case I915_ENGINE_CLASS_RENDER:
+ /* Will be tested later. */
+ break;
+ case I915_ENGINE_CLASS_COPY:
+ igt_assert(gem_has_blt(fd));
+ break;
+ case I915_ENGINE_CLASS_VIDEO:
+ switch (engine->engine.engine_instance) {
+ case 0:
+ igt_assert(gem_has_bsd(fd));
+ break;
+ case 1:
+ igt_assert(gem_has_bsd2(fd));
+ break;
Is that relationship a given?
One could argue that gem_has_blt() means that I915_EXEC_BLT works, but
without !gem_has_blt() we could still access CLASS_COPY:0 via
ctx->engines[].
"without !gem_has_blt()".. hmmm what do you mean? If you mean
gem_has_blt() is false but bcs:0 is still accessible via ctx->engines[]
then how?
+ }
+ break;
+ case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ igt_assert(gem_has_vebox(fd));
+ break;
+ default:
+ igt_assert(0);
+ }
+ }
+
+ /* Reverse check to the above - all GET_PARAM engines are present. */
+ igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0));
+ if (gem_has_blt(fd))
+ igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0));
+ if (gem_has_bsd(fd))
+ igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0));
+ if (gem_has_bsd2(fd))
+ igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1));
+ if (gem_has_vebox(fd))
+ igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE,
+ 0));
Whereas this should always make sense, given the legacy interface and
the modern interface, the modern interface should be a superset of the
legacy.
Just thinking aloud.
Sure, no harm in looking at it again. The test was written long time ago.
Regards,
Tvrtko
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2)
== Series Details == Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks (rev2) URL : https://patchwork.freedesktop.org/series/59956/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6018_full -> Patchwork_12916_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12916_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12916_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12916_full: ### IGT changes ### Possible regressions * igt@kms_draw_crc@draw-method-xrgb2101010-blt-xtiled: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-skl3/igt@kms_draw_...@draw-method-xrgb2101010-blt-xtiled.html * igt@kms_flip@bo-too-big: - shard-skl: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl9/igt@kms_f...@bo-too-big.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-skl8/igt@kms_f...@bo-too-big.html Known issues Here are the changes found in Patchwork_12916_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-iclb: [PASS][4] -> [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-iclb2/igt@gem_fence_thr...@bo-write-verify-threaded-y.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-iclb7/igt@gem_fence_thr...@bo-write-verify-threaded-y.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([fdo#104108] / [fdo#107773]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl3/igt@gem_soft...@noreloc-s3.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-skl9/igt@gem_soft...@noreloc-s3.html * igt@i915_pm_rpm@i2c: - shard-skl: [PASS][8] -> [INCOMPLETE][9] ([fdo#107807]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl6/igt@i915_pm_...@i2c.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-skl2/igt@i915_pm_...@i2c.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([fdo#108566]) +6 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-apl4/igt@i915_susp...@debugfs-reader.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-apl5/igt@i915_susp...@debugfs-reader.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][12] -> [FAIL][13] ([fdo#105767]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_flip@dpms-vs-vblank-race-interruptible: - shard-glk: [PASS][14] -> [FAIL][15] ([fdo#103060]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-glk4/igt@kms_f...@dpms-vs-vblank-race-interruptible.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-glk1/igt@kms_f...@dpms-vs-vblank-race-interruptible.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: [PASS][16] -> [FAIL][17] ([fdo#100368]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl6/igt@kms_f...@plain-flip-ts-check-interruptible.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-skl2/igt@kms_f...@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-iclb: [PASS][18] -> [FAIL][19] ([fdo#103167]) +4 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-skl: [PASS][20] -> [INCOMPLETE][21] ([fdo#106978]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl9/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12916/shard-skl9/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
Re: [Intel-gfx] [PATCH v11] drm/i915: Engine discovery query
On 01/05/2019 12:55, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-01 12:45:36)
On 01/05/2019 12:10, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-01 11:52:28)
From: Tvrtko Ursulin
Engine discovery query allows userspace to enumerate engines, probe their
configuration features, all without needing to maintain the internal PCI
ID based database.
A new query for the generic i915 query ioctl is added named
DRM_I915_QUERY_ENGINE_INFO, together with accompanying structure
drm_i915_query_engine_info. The address of latter should be passed to the
kernel in the query.data_ptr field, and should be large enough for the
kernel to fill out all known engines as struct drm_i915_engine_info
elements trailing the query.
As with other queries, setting the item query length to zero allows
userspace to query minimum required buffer size.
Enumerated engines have common type mask which can be used to query all
hardware engines, versus engines userspace can submit to using the execbuf
uAPI.
Engines also have capabilities which are per engine class namespace of
bits describing features not present on all engine instances.
v2:
* Fixed HEVC assignment.
* Reorder some fields, rename type to flags, increase width. (Lionel)
* No need to allocate temporary storage if we do it engine by engine.
(Lionel)
v3:
* Describe engine flags and mark mbz fields. (Lionel)
* HEVC only applies to VCS.
v4:
* Squash SFC flag into main patch.
* Tidy some comments.
v5:
* Add uabi_ prefix to engine capabilities. (Chris Wilson)
* Report exact size of engine info array. (Chris Wilson)
* Drop the engine flags. (Joonas Lahtinen)
* Added some more reserved fields.
* Move flags after class/instance.
v6:
* Do not check engine info array was zeroed by userspace but zero the
unused fields for them instead.
v7:
* Simplify length calculation loop. (Lionel Landwerlin)
v8:
* Remove MBZ comments where not applicable.
* Rename ABI flags to match engine class define naming.
* Rename SFC ABI flag to reflect it applies to VCS and VECS.
* SFC is wired to even _logical_ engine instances.
* SFC applies to VCS and VECS.
* HEVC is present on all instances on Gen11. (Tony)
* Simplify length calculation even more. (Chris Wilson)
* Move info_ptr assigment closer to loop for clarity. (Chris Wilson)
* Use vdbox_sfc_access from runtime info.
* Rebase for RUNTIME_INFO.
* Refactor for lower indentation.
* Rename uAPI class/instance to engine_class/instance to avoid C++
keyword.
v9:
* Rebase for s/num_rings/num_engines/ in RUNTIME_INFO.
v10:
* Use new copy_query_item.
v11:
* Consolidate with struct i915_engine_class_instnace.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Jon Bloomfield
Cc: Dmitry Rogozhkin
Cc: Lionel Landwerlin
Cc: Joonas Lahtinen
Cc: Tony Ye
Reviewed-by: Lionel Landwerlin # v7
Reviewed-by: Chris Wilson # v7
---
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+ /** Engine class and instance. */
+ struct i915_engine_class_instance engine;
+
+ /** Reserved field. */
+ __u32 rsvd0;
+
+ /** Engine flags. */
+ __u64 flags;
Do you think we could do something like
BUILD_BUG_ON(!IS_ALIGNED(offsetof(*info, flags), sizeof(info->flags));
Will that work, and worthwhile? Maybe work into a
BUILD_BUG_ON(check_user_alignment(info, flags));
Hmm.. probably manual check for no holes _and_ alignment is good enough
for uAPI since once it's in it's in. Will triple-check.
Yeah, we actually need something more like
offsetofend(previous_field) == offsetof(next_field)
BUILD_BUG_ON(check_user_struct(info, previous_field, next_field)) ?
How would you logistically do it? List all struct members for each uapi
struct you want to check?
Maybe a variadic macro like:
CHECK_USER_STRUCT_FUNCTION(type, member0, ... memberN);
Which expands to a dedicated function to check this type, using
va_start/va_end to iterate all members checking for holes. So somewhere
in code we would also need:
CHECK_USER_STRUCT(type);
Which would call the function. But thats not build time.. Could be under
debug and selftests I guess. Could even be IGT in this case.
But I am not to keen in listing each struct member with a
prev/next_field BUILD_BUG_ON.
Perhaps IGT is indeed a better place to start testing for this. Since we
anyway require each new uAPI to have good IGT coverage.
Regards,
Tvrtko
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor to expand subslice mask (rev6)
On Wed, 2019-05-01 at 00:58 +, Patchwork wrote: > == Series Details == > > Series: Refactor to expand subslice mask (rev6) > URL : https://patchwork.freedesktop.org/series/59742/ > State : failure I'm not sure what happened here, but my assumption is that CI didn't like the fact that I sent a single update to the series without the entire series. I sent a fully rebased series (as of this morning) to trybot and had no issues. So I went ahead and sent an updated series to this list to trigger CI and push for review. Sorry for the spam! -Stuart > > == Summary == > > Applying: drm/i915: Use local variable for SSEU info in GETPARAM > ioctl > Applying: drm/i915: Add macro for SSEU stride calculation > Applying: drm/i915: Move calculation of subslices per slice to new > function > Applying: drm/i915: Move sseu helper functions to intel_sseu.h > Applying: drm/i915: Remove inline from sseu helper functions > Applying: drm/i915: Expand subslice mask > error: sha1 information is lacking or useless > (drivers/gpu/drm/i915/i915_debugfs.c). > error: could not build fake ancestor > hint: Use 'git am --show-current-patch' to see the failed patch > Patch failed at 0006 drm/i915: Expand subslice mask > When you have resolved this problem, run "git am --continue". > If you prefer to skip this patch, run "git am --skip" instead. > To restore the original branch and stop patching, run "git am -- > abort". > smime.p7s Description: S/MIME cryptographic signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/14] drm/i915/hangcheck: Track context changes (rev2)
== Series Details == Series: series starting with [01/14] drm/i915/hangcheck: Track context changes (rev2) URL : https://patchwork.freedesktop.org/series/60153/ State : success == Summary == CI Bug Log - changes from CI_DRM_6021 -> Patchwork_12925 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60153/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12925 that come from known issues: ### IGT changes ### Possible fixes * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: [INCOMPLETE][1] ([fdo#107718]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12925/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][3] ([fdo#109271]) -> [INCOMPLETE][4] ([fdo#107807]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12925/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (52 -> 46) -- Additional (1): fi-pnv-d510 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6021 -> Patchwork_12925 CI_DRM_6021: 850aa4220e8bf7609b03bf89bce146305704bec6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12925: 44d3f4a1fc72b988930cbbc495db611d0ff07d2e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 44d3f4a1fc72 drm/i915: Convert inconsistent static engine tables into an init error 72d20cf4bf9d drm/i915: Bump signaler priority on adding a waiter eb5a92c844ee drm/i915: Pass i915_sched_node around internally e66579587990 drm/i915: Rearrange i915_scheduler.c 4e8130e19b73 drm/i915/execlists: Don't apply priority boost for resets 294ff64dcdc3 drm/i915: Delay semaphore submission until the start of the signaler ee299f13ddc6 drm/i915: Only reschedule the submission tasklet if preemption is possible 10ed7d87fab6 drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches) 07be304f9b61 drm/i915: Cancel retire_worker on parking 6215a5f82de4 drm/i915: Remove delay for idle_work e6839ab1c412 drm/i915: Leave engine parking to the engines 0643d22dc542 drm/i915/execlists: Flush the tasklet on parking 8d54e3388676 drm/i915: Include fence signaled bit in print_request() f55b819edc02 drm/i915/hangcheck: Track context changes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12925/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm/i915: Move calculation of subslices per slice to new function
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index c0b16b248d4c..f5ff6b7a756a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0e4dffcd4da4..fe854c629a32 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4185,7 +4185,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool
is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu,
struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct
sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.21.0.5.gaeb582a983
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[Intel-gfx] [PATCH 6/6] drm/i915: Expand subslice mask
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: fix spacing in set_sseu_info args
use set_sseu_info to initialize sseu data when building
device status in debugfs
rename variables in intel_engine_types.h to avoid checkpatch
warnings
v3: update headers in intel_sseu.h
v4: add const to some sseu_dev_info variables
use sseu->eu_stride for EU stride calculations
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 49 +--
drivers/gpu/drm/i915/gt/intel_sseu.h | 16 ++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 44 +++---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c| 5 +-
drivers/gpu/drm/i915/i915_query.c| 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 142 +++
11 files changed, 198 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6e40f8ea9a6a..8f7967cc9a50 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -914,7 +914,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private
*dev_priv)
const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
u32 mcr_s_ss_select;
u32 slice = fls(sseu->slice_mask);
- u32 subslice = fls(sseu->subslice_mask[slice]);
+ u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
if (IS_GEN(dev_priv, 10))
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -990,6 +990,7 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *dev_priv = engine->i915;
+ const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -1007,7 +1008,8 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice,
+subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(dev_priv, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d64e33f8427..1710546a2446 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct
intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
-(slice__) < I915_MAX_SLICES; \
-(subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ?
(subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) &&
\
- (BIT(subslice__) &
instdone_subslice_mask(dev_priv__)))
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? \
+ 1 : (sseu___)->slice_mask) & \
+ BIT(slice___)) \
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+BIT(subslice__ % BITS_PER_BYTE)) \
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_)
+ 1 : 0,
[Intel-gfx] [PATCH 4/6] drm/i915: Move sseu helper functions to intel_sseu.h
v2: fix spacing from checkpatch warning
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 47
drivers/gpu/drm/i915/intel_device_info.h | 47
2 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index f5ff6b7a756a..029e71d8f140 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,12 +63,59 @@ intel_sseu_from_device_info(const struct sseu_dev_info
*sseu)
return value;
}
+static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
+{
+ unsigned int i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+ total += hweight8(sseu->subslice_mask[i]);
+
+ return total;
+}
+
static inline unsigned int
sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
return hweight8(sseu->subslice_mask[slice]);
}
+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+ BITS_PER_BYTE);
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ return slice * slice_stride + subslice * subslice_stride;
+}
+
+static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+static inline void sseu_set_eus(struct sseu_dev_info *sseu,
+ int slice, int subslice, u16 eu_mask)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 5a2e17d6146b..6412a9c72898 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -218,53 +218,6 @@ struct intel_driver_caps {
bool has_logical_contexts:1;
};
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
-{
- unsigned int i, total = 0;
-
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
-
- return total;
-}
-
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
- BITS_PER_BYTE);
- int slice_stride = sseu->max_subslices * subslice_stride;
-
- return slice * slice_stride + subslice * subslice_stride;
-}
-
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
- (i * BITS_PER_BYTE);
- }
-
- return eu_mask;
-}
-
-static inline void sseu_set_eus(struct sseu_dev_info *sseu,
- int slice, int subslice, u16 eu_mask)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
- }
-}
-
const char *intel_platform_name(enum intel_platform platform);
void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
--
2.21.0.5.gaeb582a983
___
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[Intel-gfx] [PATCH 0/6] Refactor to expand subslice mask
This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 v2: fix i915_pm_sseu test failure v3: no changes to patches in the series, just resending to pick up in CI correctly v4: rebase v5: fix header test v6: address review comments from Jari address minor checkpatch warning in existing code use eu_stride for EU div-by-8 v7: another rebase Stuart Summers (6): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Move sseu helper functions to intel_sseu.h drm/i915: Remove inline from sseu helper functions drm/i915: Expand subslice mask drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +-- drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 85 drivers/gpu/drm/i915/gt/intel_sseu.h | 30 ++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 50 +++-- drivers/gpu/drm/i915/i915_drv.c | 15 +- drivers/gpu/drm/i915/i915_gpu_error.c| 5 +- drivers/gpu/drm/i915/i915_query.c| 15 +- drivers/gpu/drm/i915/intel_device_info.c | 209 +++ drivers/gpu/drm/i915/intel_device_info.h | 47 - 12 files changed, 302 insertions(+), 197 deletions(-) -- 2.21.0.5.gaeb582a983 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6] drm/i915: Remove inline from sseu helper functions
Additionally, ensure these are all prefixed with intel_sseu_*
to match the convention of other functions in i915.
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 54 +++
drivers/gpu/drm/i915/gt/intel_sseu.h | 57 +++-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 69
5 files changed, 102 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7f448f3bea0b..4a0b82fc108c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -8,6 +8,60 @@
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
+unsigned int
+intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
+{
+ unsigned int i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+ total += hweight8(sseu->subslice_mask[i]);
+
+ return total;
+}
+
+unsigned int
+intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
+static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
+int subslice)
+{
+ int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+ BITS_PER_BYTE);
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ return slice * slice_stride + subslice * subslice_stride;
+}
+
+u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
+ int subslice)
+{
+ int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
+ u16 eu_mask)
+{
+ int i, offset = intel_sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 029e71d8f140..56e3721ae83f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,58 +63,17 @@ intel_sseu_from_device_info(const struct sseu_dev_info
*sseu)
return value;
}
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
-{
- unsigned int i, total = 0;
-
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
+unsigned int
+intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
- return total;
-}
+unsigned int
+intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
-static inline unsigned int
-sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
-{
- return hweight8(sseu->subslice_mask[slice]);
-}
-
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
- BITS_PER_BYTE);
- int slice_stride = sseu->max_subslices * subslice_stride;
-
- return slice * slice_stride + subslice * subslice_stride;
-}
+u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
+ int subslice);
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
- (i * BITS_PER_BYTE);
- }
-
- return eu_mask;
-}
-
-static inline void sseu_set_eus(struct sseu_dev_info *sseu,
- int slice, int subslice, u16 eu_mask)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
- }
-}
+void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
+
[Intel-gfx] [PATCH 2/6] drm/i915: Add macro for SSEU stride calculation
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
v2: update headers in intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
drivers/gpu/drm/i915/i915_query.c| 17 -
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 73bc824094e8..c0b16b248d4c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -8,11 +8,13 @@
#define __INTEL_SSEU_H__
#include
+#include
struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
+#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
struct sseu_dev_info {
u8 slice_mask;
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index 782183b78f49..7c1708c22811 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,6 +37,8 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -48,12 +50,10 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices *
- DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
- eu_length = sseu->max_slices * sseu->max_subslices *
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
-
- total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
+ subslice_length = sseu->max_slices * subslice_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ total_length = sizeof(topo) + slice_length + subslice_length +
+ eu_length;
ret = copy_query_item(, sizeof(topo), total_length,
query_item);
@@ -69,10 +69,9 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
+ topo.subslice_stride = subslice_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride =
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+ topo.eu_stride = eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
, sizeof(topo)))
--
2.21.0.5.gaeb582a983
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[Intel-gfx] [PATCH 1/6] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
v2: add const to sseu_dev_info variable
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 21dac5a09fbe..c376244c19c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -324,6 +324,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
+ const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
drm_i915_getparam_t *param = data;
int value;
@@ -377,12 +378,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(sseu);
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
+ value = sseu->eu_total;
if (!value)
return -ENODEV;
break;
@@ -399,7 +400,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = sseu->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
value = intel_huc_check_status(_priv->huc);
@@ -449,12 +450,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
+ value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
+ value = sseu->subslice_mask[0];
if (!value)
return -ENODEV;
break;
--
2.21.0.5.gaeb582a983
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/14] drm/i915/hangcheck: Track context changes (rev2)
== Series Details == Series: series starting with [01/14] drm/i915/hangcheck: Track context changes (rev2) URL : https://patchwork.freedesktop.org/series/60153/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/hangcheck: Track context changes Okay! Commit: drm/i915: Include fence signaled bit in print_request() Okay! Commit: drm/i915/execlists: Flush the tasklet on parking Okay! Commit: drm/i915: Leave engine parking to the engines Okay! Commit: drm/i915: Remove delay for idle_work Okay! Commit: drm/i915: Cancel retire_worker on parking Okay! Commit: drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches) Okay! Commit: drm/i915: Only reschedule the submission tasklet if preemption is possible -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) Commit: drm/i915: Delay semaphore submission until the start of the signaler Okay! Commit: drm/i915/execlists: Don't apply priority boost for resets Okay! Commit: drm/i915: Rearrange i915_scheduler.c Okay! Commit: drm/i915: Pass i915_sched_node around internally Okay! Commit: drm/i915: Bump signaler priority on adding a waiter Okay! Commit: drm/i915: Convert inconsistent static engine tables into an init error Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Bump signaler priority on adding a waiter
The handling of the no-preemption priority level imposes the restriction
that we need to maintain the implied ordering even though preemption is
disabled. Otherwise we may end up with an AB-BA deadlock across multiple
engine due to a real preemption event reordering the no-preemption
WAITs. To resolve this issue we currently promote all requests to WAIT
on unsubmission, however this interferes with the timeslicing
requirement that we do not apply any implicit promotion that will defeat
the round-robin timeslice list. (If we automatically promote the active
request it will go back to the head of the queue and not the tail!)
So we need implicit promotion to prevent reordering around semaphores
where we are not allowed to preempt, and we must avoid implicit
promotion on unsubmission. So instead of at unsubmit, if we apply that
implicit promotion on adding the dependency, we avoid the semaphore
deadlock and we also reduce the gains made by the promotion for user
space waiting. Furthermore, by keeping the earlier dependencies at a
higher level, we reduce the search space for timeslicing without
altering runtime scheduling too badly (no dependencies at all will be
assigned a higher priority for rrul).
Testcase: igt/gem_concurrent_blit
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 12
drivers/gpu/drm/i915/i915_request.c| 9 -
drivers/gpu/drm/i915/i915_scheduler.c | 9 +
3 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 4b042893dc0e..5b3d8e33f1cf 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -98,12 +98,14 @@ static int live_busywait_preempt(void *arg)
ctx_hi = kernel_context(i915);
if (!ctx_hi)
goto err_unlock;
- ctx_hi->sched.priority = INT_MAX;
+ ctx_hi->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
ctx_lo = kernel_context(i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority = INT_MIN;
+ ctx_lo->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj)) {
@@ -958,12 +960,14 @@ static int live_preempt_hang(void *arg)
ctx_hi = kernel_context(i915);
if (!ctx_hi)
goto err_spin_lo;
- ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY;
+ ctx_hi->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY);
ctx_lo = kernel_context(i915);
if (!ctx_lo)
goto err_ctx_hi;
- ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY;
+ ctx_lo->sched.priority =
+ I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
for_each_engine(engine, i915, id) {
struct i915_request *rq;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 8cb3ed5531e3..065da1bcbb4c 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -468,15 +468,6 @@ void __i915_request_unsubmit(struct i915_request *request)
/* We may be recursing from the signal callback of another i915 fence */
spin_lock_nested(>lock, SINGLE_DEPTH_NESTING);
- /*
-* As we do not allow WAIT to preempt inflight requests,
-* once we have executed a request, along with triggering
-* any execution callbacks, we must preserve its ordering
-* within the non-preemptible FIFO.
-*/
- BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */
- request->sched.attr.priority |= __NO_PREEMPTION;
-
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
i915_request_cancel_breadcrumb(request);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 05eb50558aba..ecc3e83ef28d 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -388,6 +388,15 @@ bool __i915_sched_node_add_dependency(struct
i915_sched_node *node,
!node_started(signal))
node->flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
+ /*
+* As we do not allow WAIT to preempt inflight requests,
+* once we have executed a request, along with triggering
+* any execution callbacks, we must preserve its ordering
+* within the non-preemptible FIFO.
+*/
+ BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK);
+ __bump_priority(signal, __NO_PREEMPTION);
+
ret = true;
}
--
2.20.1
___
Intel-gfx mailing list
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Complete both freed-object passes before draining the workqueue
== Series Details == Series: series starting with [1/3] drm/i915: Complete both freed-object passes before draining the workqueue URL : https://patchwork.freedesktop.org/series/60162/ State : success == Summary == CI Bug Log - changes from CI_DRM_6021 -> Patchwork_12924 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60162/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12924 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#110235]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12924/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html Possible fixes * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12924/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][5] ([fdo#109271]) -> [INCOMPLETE][6] ([fdo#107807]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12924/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (52 -> 45) -- Additional (1): fi-pnv-d510 Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus fi-snb-2600 Build changes - * Linux: CI_DRM_6021 -> Patchwork_12924 CI_DRM_6021: 850aa4220e8bf7609b03bf89bce146305704bec6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12924: 49c0aaf0abe27ac4c752ce429222a07f576ff6f3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 49c0aaf0abe2 drm/i915: Assert the local engine->wakeref is active bccc4746b810 drm/i915: Prefer checking the wakeref itself rather than the counter 06ed3eefb441 drm/i915: Complete both freed-object passes before draining the workqueue == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12924/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 5/5] drm/i915: Use memory cgroup for enforcing device memory limit
i915 driver now includes DRIVER_CGROUPS in feature bits.
To charge device memory allocations, we need to (1) identify appropriate
cgroup to charge (currently decided at object creation time), and (2)
make the charging call at the time that memory pages are being allocated.
For (1), see prior DRM patch which associates current task's cgroup with
GEM objects as they are created. That cgroup will be charged/uncharged
for all paging activity against the GEM object.
For (2), we call mem_cgroup_try_charge_direct() in .get_pages callback
for the GEM object type. Uncharging is done in .put_pages when the
memory is marked such that it can be evicted. The try_charge() call will
fail with -ENOMEM if the current memory allocation will exceed the cgroup
device memory maximum, and allow for driver to perform memory reclaim.
Cc: cgro...@vger.kernel.org
Cc: linux...@kvack.org
Cc: dri-de...@lists.freedesktop.org
Cc: Matt Roper
Signed-off-by: Brian Welty
---
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/intel_memory_region.c | 24 ++
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5a0a59922cb4..4d496c3c3681 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -3469,7 +3469,7 @@ static struct drm_driver driver = {
* deal with them for Intel hardware.
*/
.driver_features =
- DRIVER_GEM | DRIVER_PRIME |
+ DRIVER_GEM | DRIVER_PRIME | DRIVER_CGROUPS |
DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
.release = i915_driver_release,
.open = i915_driver_open,
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index 813ff83c132b..e4ac5e4d4857 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -53,6 +53,8 @@ i915_memory_region_put_pages_buddy(struct drm_i915_gem_object
*obj,
mutex_unlock(>memory_region->mm_lock);
obj->mm.dirty = false;
+ mem_cgroup_uncharge_direct(obj->base.memcg,
+ obj->base.size >> PAGE_SHIFT);
}
int
@@ -65,19 +67,29 @@ i915_memory_region_get_pages_buddy(struct
drm_i915_gem_object *obj)
struct scatterlist *sg;
unsigned int sg_page_sizes;
unsigned long n_pages;
+ int err;
GEM_BUG_ON(!IS_ALIGNED(size, mem->mm.min_size));
GEM_BUG_ON(!list_empty(>blocks));
+ err = mem_cgroup_try_charge_direct(obj->base.memcg, size >> PAGE_SHIFT);
+ if (err) {
+ DRM_DEBUG("MEMCG: try_charge failed for %lld\n", size);
+ return err;
+ }
+
st = kmalloc(sizeof(*st), GFP_KERNEL);
- if (!st)
- return -ENOMEM;
+ if (!st) {
+ err = -ENOMEM;
+ goto err_uncharge;
+ }
n_pages = div64_u64(size, mem->mm.min_size);
if (sg_alloc_table(st, n_pages, GFP_KERNEL)) {
kfree(st);
- return -ENOMEM;
+ err = -ENOMEM;
+ goto err_uncharge;
}
sg = st->sgl;
@@ -161,7 +173,11 @@ i915_memory_region_get_pages_buddy(struct
drm_i915_gem_object *obj)
err_free_blocks:
memory_region_free_pages(obj, st);
mutex_unlock(>mm_lock);
- return -ENXIO;
+ err = -ENXIO;
+err_uncharge:
+ mem_cgroup_uncharge_direct(obj->base.memcg,
+ obj->base.size >> PAGE_SHIFT);
+ return err;
}
int i915_memory_region_init_buddy(struct intel_memory_region *mem)
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 2/5] cgroup: Change kernfs_node for directories to store cgroup_subsys_state
Change the kernfs_node.priv to store the cgroup_subsys_state (CSS) pointer
for directories, instead of storing cgroup pointer. This is done in order
to support files within the cgroup associated with devices. We require
of_css() to return the device-specific CSS pointer for these files.
Cc: cgro...@vger.kernel.org
Signed-off-by: Brian Welty
---
kernel/cgroup/cgroup-v1.c | 10
kernel/cgroup/cgroup.c| 48 +--
2 files changed, 27 insertions(+), 31 deletions(-)
diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c
index c126b34fd4ff..4fa56cc2b99c 100644
--- a/kernel/cgroup/cgroup-v1.c
+++ b/kernel/cgroup/cgroup-v1.c
@@ -723,6 +723,7 @@ int proc_cgroupstats_show(struct seq_file *m, void *v)
int cgroupstats_build(struct cgroupstats *stats, struct dentry *dentry)
{
struct kernfs_node *kn = kernfs_node_from_dentry(dentry);
+ struct cgroup_subsys_state *css;
struct cgroup *cgrp;
struct css_task_iter it;
struct task_struct *tsk;
@@ -740,12 +741,13 @@ int cgroupstats_build(struct cgroupstats *stats, struct
dentry *dentry)
* @kn->priv is RCU safe. Let's do the RCU dancing.
*/
rcu_read_lock();
- cgrp = rcu_dereference(*(void __rcu __force **)>priv);
- if (!cgrp || cgroup_is_dead(cgrp)) {
+ css = rcu_dereference(*(void __rcu __force **)>priv);
+ if (!css || cgroup_is_dead(css->cgroup)) {
rcu_read_unlock();
mutex_unlock(_mutex);
return -ENOENT;
}
+ cgrp = css->cgroup;
rcu_read_unlock();
css_task_iter_start(>self, 0, );
@@ -851,7 +853,7 @@ void cgroup1_release_agent(struct work_struct *work)
static int cgroup1_rename(struct kernfs_node *kn, struct kernfs_node
*new_parent,
const char *new_name_str)
{
- struct cgroup *cgrp = kn->priv;
+ struct cgroup_subsys_state *css = kn->priv;
int ret;
if (kernfs_type(kn) != KERNFS_DIR)
@@ -871,7 +873,7 @@ static int cgroup1_rename(struct kernfs_node *kn, struct
kernfs_node *new_parent
ret = kernfs_rename(kn, new_parent, new_name_str);
if (!ret)
- TRACE_CGROUP_PATH(rename, cgrp);
+ TRACE_CGROUP_PATH(rename, css->cgroup);
mutex_unlock(_mutex);
diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c
index 9b035e728941..1fe4fee502ea 100644
--- a/kernel/cgroup/cgroup.c
+++ b/kernel/cgroup/cgroup.c
@@ -595,12 +595,13 @@ static void cgroup_get_live(struct cgroup *cgrp)
struct cgroup_subsys_state *of_css(struct kernfs_open_file *of)
{
- struct cgroup *cgrp = of->kn->parent->priv;
+ struct cgroup_subsys_state *css = of->kn->parent->priv;
struct cftype *cft = of_cft(of);
- /* FIXME this needs updating to lookup device-specific CSS */
-
/*
+* If the cft specifies a subsys and this is not a device file,
+* then lookup the css, otherwise it is already correct.
+*
* This is open and unprotected implementation of cgroup_css().
* seq_css() is only called from a kernfs file operation which has
* an active reference on the file. Because all the subsystem
@@ -608,10 +609,9 @@ struct cgroup_subsys_state *of_css(struct kernfs_open_file
*of)
* the matching css from the cgroup's subsys table is guaranteed to
* be and stay valid until the enclosing operation is complete.
*/
- if (cft->ss)
- return rcu_dereference_raw(cgrp->subsys[cft->ss->id]);
- else
- return >self;
+ if (cft->ss && !css->device)
+ css = rcu_dereference_raw(css->cgroup->subsys[cft->ss->id]);
+ return css;
}
EXPORT_SYMBOL_GPL(of_css);
@@ -1524,12 +1524,14 @@ static u16 cgroup_calc_subtree_ss_mask(u16
subtree_control, u16 this_ss_mask)
*/
void cgroup_kn_unlock(struct kernfs_node *kn)
{
+ struct cgroup_subsys_state *css;
struct cgroup *cgrp;
if (kernfs_type(kn) == KERNFS_DIR)
- cgrp = kn->priv;
+ css = kn->priv;
else
- cgrp = kn->parent->priv;
+ css = kn->parent->priv;
+ cgrp = css->cgroup;
mutex_unlock(_mutex);
@@ -1556,12 +1558,14 @@ void cgroup_kn_unlock(struct kernfs_node *kn)
*/
struct cgroup *cgroup_kn_lock_live(struct kernfs_node *kn, bool drain_offline)
{
+ struct cgroup_subsys_state *css;
struct cgroup *cgrp;
if (kernfs_type(kn) == KERNFS_DIR)
- cgrp = kn->priv;
+ css = kn->priv;
else
- cgrp = kn->parent->priv;
+ css = kn->parent->priv;
+ cgrp = css->cgroup;
/*
* We're gonna grab cgroup_mutex which nests outside kernfs
@@ -1652,7 +1656,7 @@ static int cgroup_device_mkdir(struct cgroup_subsys_state
*css)
if (WARN_ON_ONCE(ret >= CGROUP_FILE_NAME_MAX))
[Intel-gfx] [RFC PATCH 4/5] drm: Add memory cgroup registration and DRIVER_CGROUPS feature bit
With new cgroups per-device framework, registration with memory cgroup
subsystem can allow us to enforce limit for allocation of device memory
against process cgroups.
This patch adds new driver feature bit, DRIVER_CGROUPS, such that DRM
will register the device with cgroups. Doing so allows device drivers to
charge memory allocations to device-specific state within the cgroup.
Note, this is only for GEM objects allocated from device memory.
Memory charging for GEM objects using system memory is already handled
by the mm subsystem charing the normal (non-device) memory cgroup.
To charge device memory allocations, we need to (1) identify appropriate
cgroup to charge (currently decided at object creation time), and (2)
make the charging call at the time that memory pages are being allocated.
Above is one policy, and this is open for debate if this is the right
choice.
For (1), we associate the current task's cgroup with GEM objects as they
are created. That cgroup will be charged/uncharged for all paging
activity against the GEM object. Note, if the process is not part of a
memory cgroup, then this returns NULL and no charging will occur.
For shared objects, this may make the charge against a cgroup that is
potentially not the same cgroup as the process using the memory. Based
on the memory cgroup's discussion of "memory ownership", this seems
acceptable [1]. For (2), this is for device drivers to implement within
appropriate page allocation logic.
[1] https://www.kernel.org/doc/Documentation/cgroup-v2.txt, "Memory Ownership"
Cc: cgro...@vger.kernel.org
Cc: linux...@kvack.org
Cc: dri-de...@lists.freedesktop.org
Cc: Matt Roper
Signed-off-by: Brian Welty
---
drivers/gpu/drm/drm_drv.c | 12
drivers/gpu/drm/drm_gem.c | 7 +++
include/drm/drm_device.h | 3 +++
include/drm/drm_drv.h | 8
include/drm/drm_gem.h | 11 +++
5 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 862621494a93..890bd3c0e63e 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -28,6 +28,7 @@
#include
#include
+#include
#include
#include
#include
@@ -987,6 +988,12 @@ int drm_dev_register(struct drm_device *dev, unsigned long
flags)
if (ret)
goto err_minors;
+ if (dev->dev && drm_core_check_feature(dev, DRIVER_CGROUPS)) {
+ ret = mem_cgroup_device_register(dev->dev, >memcg_id);
+ if (ret)
+ goto err_minors;
+ }
+
dev->registered = true;
if (dev->driver->load) {
@@ -1009,6 +1016,8 @@ int drm_dev_register(struct drm_device *dev, unsigned
long flags)
goto out_unlock;
err_minors:
+ if (dev->memcg_id)
+ mem_cgroup_device_unregister(dev->memcg_id);
remove_compat_control_link(dev);
drm_minor_unregister(dev, DRM_MINOR_PRIMARY);
drm_minor_unregister(dev, DRM_MINOR_RENDER);
@@ -1052,6 +1061,9 @@ void drm_dev_unregister(struct drm_device *dev)
drm_legacy_rmmaps(dev);
+ if (dev->memcg_id)
+ mem_cgroup_device_unregister(dev->memcg_id);
+
remove_compat_control_link(dev);
drm_minor_unregister(dev, DRM_MINOR_PRIMARY);
drm_minor_unregister(dev, DRM_MINOR_RENDER);
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 50de138c89e0..966fbd701deb 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -281,6 +282,9 @@ drm_gem_handle_delete(struct drm_file *filp, u32 handle)
if (IS_ERR_OR_NULL(obj))
return -EINVAL;
+ /* Release reference on cgroup used with GEM object charging */
+ mem_cgroup_put(obj->memcg);
+
/* Release driver's reference and decrement refcount. */
drm_gem_object_release_handle(handle, obj, filp);
@@ -410,6 +414,9 @@ drm_gem_handle_create_tail(struct drm_file *file_priv,
goto err_revoke;
}
+ /* Acquire reference on cgroup for charging GEM memory allocations */
+ obj->memcg = mem_cgroup_device_from_task(dev->memcg_id, current);
+
*handlep = handle;
return 0;
diff --git a/include/drm/drm_device.h b/include/drm/drm_device.h
index 7f9ef709b2b6..9859f2289066 100644
--- a/include/drm/drm_device.h
+++ b/include/drm/drm_device.h
@@ -190,6 +190,9 @@ struct drm_device {
*/
int irq;
+ /* @memcg_id: cgroup subsys (memcg) index for our device state */
+ unsigned long memcg_id;
+
/**
* @vblank_disable_immediate:
*
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index 5cc7f728ec73..13b0e0b9527f 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -92,6 +92,14 @@ enum drm_driver_feature {
*/
DRIVER_SYNCOBJ = BIT(5),
+ /**
+*
[Intel-gfx] [RFC PATCH 3/5] memcg: Add per-device support to memory cgroup subsystem
Here we update memory cgroup to enable the newly introduced per-device
framework. As mentioned in the prior patch, the intent here is to allow
drivers to have their own private cgroup controls (such as memory limit)
to be applied to device resources instead of host system resources.
In summary, to enable device registration for memory cgroup subsystem:
* set .allow_devices to true
* add new exported device register and device unregister functions
to register a device with the cgroup subsystem
* implement the .device_css_alloc callback to create device
specific cgroups_subsys_state within a cgroup
As cgroup is created and for current registered devices, one will see in
the cgroup filesystem these additional files:
mount//memory.devices//
Registration of a new device is performed in device drivers using new
mem_cgroup_device_register(). This will create above files in existing
cgroups.
And for runtime charging to the cgroup, we add the following:
* add new routine to lookup the device-specific cgroup_subsys_state
which is within the task's cgroup (mem_cgroup_device_from_task)
* add new functions for device specific 'direct' charging
The last point above involves adding new mem_cgroup_try_charge_direct
and mem_cgroup_uncharge_direct functions. The 'direct' name is to say
that we are charging the specified cgroup state directly and not using
any associated page or mm_struct. We are called within device specific
memory management routines, where the device driver will track which
cgroup to charge within its own private data structures.
With this initial submission, support for memory accounting and charging
is functional. Nested cgroups will correctly maintain the parent for
device-specific state as well, such that hierarchial charging to device
files is supported.
Cc: cgro...@vger.kernel.org
Cc: linux...@kvack.org
Cc: dri-de...@lists.freedesktop.org
Cc: Matt Roper
Signed-off-by: Brian Welty
---
include/linux/memcontrol.h | 10 ++
mm/memcontrol.c| 183 ++---
2 files changed, 178 insertions(+), 15 deletions(-)
diff --git a/include/linux/memcontrol.h b/include/linux/memcontrol.h
index dbb6118370c1..711669b613dc 100644
--- a/include/linux/memcontrol.h
+++ b/include/linux/memcontrol.h
@@ -348,6 +348,11 @@ void mem_cgroup_cancel_charge(struct page *page, struct
mem_cgroup *memcg,
bool compound);
void mem_cgroup_uncharge(struct page *page);
void mem_cgroup_uncharge_list(struct list_head *page_list);
+/* direct charging to mem_cgroup is primarily for device driver usage */
+int mem_cgroup_try_charge_direct(struct mem_cgroup *memcg,
+unsigned long nr_pages);
+void mem_cgroup_uncharge_direct(struct mem_cgroup *memcg,
+ unsigned long nr_pages);
void mem_cgroup_migrate(struct page *oldpage, struct page *newpage);
@@ -395,6 +400,11 @@ struct lruvec *mem_cgroup_page_lruvec(struct page *,
struct pglist_data *);
bool task_in_mem_cgroup(struct task_struct *task, struct mem_cgroup *memcg);
struct mem_cgroup *mem_cgroup_from_task(struct task_struct *p);
+struct mem_cgroup *mem_cgroup_device_from_task(unsigned long id,
+ struct task_struct *p);
+int mem_cgroup_device_register(struct device *dev, unsigned long *dev_id);
+void mem_cgroup_device_unregister(unsigned long dev_id);
+
struct mem_cgroup *get_mem_cgroup_from_mm(struct mm_struct *mm);
struct mem_cgroup *get_mem_cgroup_from_page(struct page *page);
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index 81a0d3914ec9..2c8407aed0f5 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -823,6 +823,47 @@ struct mem_cgroup *mem_cgroup_from_task(struct task_struct
*p)
}
EXPORT_SYMBOL(mem_cgroup_from_task);
+int mem_cgroup_device_register(struct device *dev, unsigned long *dev_id)
+{
+ return cgroup_device_register(_cgrp_subsys, dev, dev_id);
+}
+EXPORT_SYMBOL(mem_cgroup_device_register);
+
+void mem_cgroup_device_unregister(unsigned long dev_id)
+{
+ cgroup_device_unregister(_cgrp_subsys, dev_id);
+}
+EXPORT_SYMBOL(mem_cgroup_device_unregister);
+
+/**
+ * mem_cgroup_device_from_task: Lookup device-specific memcg
+ * @id: device-specific id returned from mem_cgroup_device_register
+ * @p: task to lookup the memcg
+ *
+ * First use mem_cgroup_from_task to lookup and obtain a reference on
+ * the memcg associated with this task @p. Within this memcg, find the
+ * device-specific one associated with @id.
+ * However if mem_cgroup is disabled, NULL is returned.
+ */
+struct mem_cgroup *mem_cgroup_device_from_task(unsigned long id,
+ struct task_struct *p)
+{
+ struct mem_cgroup *memcg;
+ struct mem_cgroup *dev_memcg = NULL;
+
+ if (mem_cgroup_disabled())
+ return NULL;
+
+ rcu_read_lock();
+ memcg = mem_cgroup_from_task(p);
+ if (memcg)
+
[Intel-gfx] [RFC PATCH 0/5] cgroup support for GPU devices
In containerized or virtualized environments, there is desire to have controls in place for resources that can be consumed by users of a GPU device. This RFC patch series proposes a framework for integrating use of existing cgroup controllers into device drivers. The i915 driver is updated in this series as our primary use case to leverage this framework and to serve as an example for discussion. The patch series enables device drivers to use cgroups to control the following resources within a GPU (or other accelerator device): * control allocation of device memory (reuse of memcg) and with future work, we could extend to: * track and control share of GPU time (reuse of cpu/cpuacct) * apply mask of allowed execution engines (reuse of cpusets) Instead of introducing a new cgroup subsystem for GPU devices, a new framework is proposed to allow devices to register with existing cgroup controllers, which creates per-device cgroup_subsys_state within the cgroup. This gives device drivers their own private cgroup controls (such as memory limits or other parameters) to be applied to device resources instead of host system resources. Device drivers (GPU or other) are then able to reuse the existing cgroup controls, instead of inventing similar ones. Per-device controls would be exposed in cgroup filesystem as: mount//.devices// such as (for example): mount//memory.devices//memory.max mount//memory.devices//memory.current mount//cpu.devices//cpu.stat mount//cpu.devices//cpu.weight The drm/i915 patch in this series is based on top of other RFC work [1] for i915 device memory support. AMD [2] and Intel [3] have proposed related work in this area within the last few years, listed below as reference. This new RFC reuses existing cgroup controllers and takes a different approach than prior work. Finally, some potential discussion points for this series: * merge proposed .devices into a single devices directory? * allow devices to have multiple registrations for subsets of resources? * document a 'common charging policy' for device drivers to follow? [1] https://patchwork.freedesktop.org/series/56683/ [2] https://lists.freedesktop.org/archives/dri-devel/2018-November/197106.html [3] https://lists.freedesktop.org/archives/intel-gfx/2018-January/153156.html Brian Welty (5): cgroup: Add cgroup_subsys per-device registration framework cgroup: Change kernfs_node for directories to store cgroup_subsys_state memcg: Add per-device support to memory cgroup subsystem drm: Add memory cgroup registration and DRIVER_CGROUPS feature bit drm/i915: Use memory cgroup for enforcing device memory limit drivers/gpu/drm/drm_drv.c | 12 + drivers/gpu/drm/drm_gem.c | 7 + drivers/gpu/drm/i915/i915_drv.c| 2 +- drivers/gpu/drm/i915/intel_memory_region.c | 24 +- include/drm/drm_device.h | 3 + include/drm/drm_drv.h | 8 + include/drm/drm_gem.h | 11 + include/linux/cgroup-defs.h| 28 ++ include/linux/cgroup.h | 3 + include/linux/memcontrol.h | 10 + kernel/cgroup/cgroup-v1.c | 10 +- kernel/cgroup/cgroup.c | 310 ++--- mm/memcontrol.c| 183 +++- 13 files changed, 552 insertions(+), 59 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 1/5] cgroup: Add cgroup_subsys per-device registration framework
In containerized or virtualized environments, there is desire to have
controls in place for resources that can be consumed by users of a GPU
device. For this purpose, we extend control groups with a mechanism
for device drivers to register with cgroup subsystems.
Device drivers (GPU or other) are then able to reuse the existing cgroup
controls, instead of inventing similar ones.
A new framework is proposed to allow devices to register with existing
cgroup controllers, which creates per-device cgroup_subsys_state within
the cgroup. This gives device drivers their own private cgroup controls
(such as memory limits or other parameters) to be applied to device
resources instead of host system resources.
It is exposed in cgroup filesystem as:
mount//.devices//
such as (for example):
mount//memory.devices//memory.max
mount//memory.devices//memory.current
mount//cpu.devices//cpu.stat
The creation of above files is implemented in css_populate_dir() for
cgroup subsystems that have enabled per-device support.
Above files are created either at time of cgroup creation (for known
registered devices) or at the time of device driver registration of the
device, during cgroup_register_device. cgroup_device_unregister will
remove files from all current cgroups.
Cc: cgro...@vger.kernel.org
Cc: linux...@kvack.org
Cc: dri-de...@lists.freedesktop.org
Cc: Matt Roper
Signed-off-by: Brian Welty
---
include/linux/cgroup-defs.h | 28
include/linux/cgroup.h | 3 +
kernel/cgroup/cgroup.c | 270 ++--
3 files changed, 289 insertions(+), 12 deletions(-)
diff --git a/include/linux/cgroup-defs.h b/include/linux/cgroup-defs.h
index 1c70803e9f77..aeaab420e349 100644
--- a/include/linux/cgroup-defs.h
+++ b/include/linux/cgroup-defs.h
@@ -162,6 +162,17 @@ struct cgroup_subsys_state {
struct work_struct destroy_work;
struct rcu_work destroy_rwork;
+ /*
+* Per-device state for devices registered with our subsys.
+* @device_css_idr stores pointer to per-device cgroup_subsys_state,
+* created when devices are associated with this css.
+* @device_kn is for creating .devices sub-directory within this cgroup
+* or for the per-device sub-directory (subsys.devices/).
+*/
+ struct device *device;
+ struct idr device_css_idr;
+ struct kernfs_node *device_kn;
+
/*
* PI: the parent css. Placed here for cache proximity to following
* fields of the containing structure.
@@ -589,6 +600,9 @@ struct cftype {
*/
struct cgroup_subsys {
struct cgroup_subsys_state *(*css_alloc)(struct cgroup_subsys_state
*parent_css);
+ struct cgroup_subsys_state *(*device_css_alloc)(struct device *device,
+ struct
cgroup_subsys_state *cgroup_css,
+ struct
cgroup_subsys_state *parent_device_css);
int (*css_online)(struct cgroup_subsys_state *css);
void (*css_offline)(struct cgroup_subsys_state *css);
void (*css_released)(struct cgroup_subsys_state *css);
@@ -636,6 +650,13 @@ struct cgroup_subsys {
*/
bool threaded:1;
+ /*
+* If %true, the controller supports device drivers to register
+* with this controller for cloning the cgroup functionality
+* into per-device cgroup state under .dev//.
+*/
+ bool allow_devices:1;
+
/*
* If %false, this subsystem is properly hierarchical -
* configuration, resource accounting and restriction on a parent
@@ -664,6 +685,13 @@ struct cgroup_subsys {
/* idr for css->id */
struct idr css_idr;
+ /*
+* IDR of registered devices, allows subsys_state to have state
+* for each device. Exposed as per-device entries in filesystem,
+* under .device//.
+*/
+ struct idr device_idr;
+
/*
* List of cftypes. Each entry is the first entry of an array
* terminated by zero length name.
diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h
index 81f58b4a5418..3531bf948703 100644
--- a/include/linux/cgroup.h
+++ b/include/linux/cgroup.h
@@ -116,6 +116,9 @@ int cgroupstats_build(struct cgroupstats *stats, struct
dentry *dentry);
int proc_cgroup_show(struct seq_file *m, struct pid_namespace *ns,
struct pid *pid, struct task_struct *tsk);
+int cgroup_device_register(struct cgroup_subsys *ss, struct device *dev,
+ unsigned long *dev_id);
+void cgroup_device_unregister(struct cgroup_subsys *ss, unsigned long dev_id);
void cgroup_fork(struct task_struct *p);
extern int cgroup_can_fork(struct task_struct *p);
extern void cgroup_cancel_fork(struct task_struct *p);
diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c
index 3f2b4bde0f9c..9b035e728941 100644
--- a/kernel/cgroup/cgroup.c
+++
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Prefer checking the wakeref itself rather than the counter
Quoting Chris Wilson (2019-05-01 14:57:52) > The counter goes to zero at the start of the parking cycle, but the > wakeref itself is held until the end. Likewise, the counter becomes one > at the end of the unparking, but the wakeref is taken first. If we check > the wakeref instead of the counter, we include the unpark/unparking time > as intel_wakeref_is_active(), and do not spuriously declare inactive if > we fail to park (i.e. the parking and wakeref drop is postponed). > > The premature inactive deactivation may result us in randomly stopping > the retire worker too early with a potential for a livelock if that was > the only means by which we were retiring at the time (e.g. in handling > i915_drop_caches). Forget this paragraph, this was not the solution. I need the longer active boundary for the next patch. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Assert the local engine->wakeref is active
Due to the asynchronous tasklet and recursive GT wakeref, it may happen
that we submit to the engine (underneath it's own wakeref) prior to the
central wakeref being marked as taken. Switch to checking the local wakeref
for greater consistency.
Fixes: 79ffac8599c4 ("drm/i915: Invert the GEM wakeref hierarchy")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6e40f8ea9a6a..a62753a429a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1090,6 +1090,9 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
if (i915_reset_failed(engine->i915))
return true;
+ if (!intel_wakeref_active(>wakeref))
+ return true;
+
/* Waiting to drain ELSP? */
if (READ_ONCE(engine->execlists.active)) {
struct tasklet_struct *t = >execlists.tasklet;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 851e62ddcb87..8c2eeff79f03 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -534,7 +534,7 @@ static void execlists_submit_ports(struct intel_engine_cs
*engine)
* that all ELSP are drained i.e. we have processed the CSB,
* before allowing ourselves to idle and calling intel_runtime_pm_put().
*/
- GEM_BUG_ON(!engine->i915->gt.awake);
+ GEM_BUG_ON(!intel_wakeref_active(>wakeref));
/*
* ELSQ note: the submit queue is not cleared after being submitted
@@ -1084,7 +1084,7 @@ static void execlists_submission_tasklet(unsigned long
data)
GEM_TRACE("%s awake?=%d, active=%x\n",
engine->name,
- !!engine->i915->gt.awake,
+ !!intel_wakeref_active(>wakeref),
engine->execlists.active);
spin_lock_irqsave(>timeline.lock, flags);
--
2.20.1
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[Intel-gfx] [PATCH 2/3] drm/i915: Prefer checking the wakeref itself rather than the counter
The counter goes to zero at the start of the parking cycle, but the
wakeref itself is held until the end. Likewise, the counter becomes one
at the end of the unparking, but the wakeref is taken first. If we check
the wakeref instead of the counter, we include the unpark/unparking time
as intel_wakeref_is_active(), and do not spuriously declare inactive if
we fail to park (i.e. the parking and wakeref drop is postponed).
The premature inactive deactivation may result us in randomly stopping
the retire worker too early with a potential for a livelock if that was
the only means by which we were retiring at the time (e.g. in handling
i915_drop_caches).
Testcase: igt/gem_concurrent_blit
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_wakeref.c | 20 +---
drivers/gpu/drm/i915/intel_wakeref.h | 2 +-
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
b/drivers/gpu/drm/i915/intel_wakeref.c
index 1f94bc4ff9e4..91196d9612bb 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -7,6 +7,19 @@
#include "intel_drv.h"
#include "intel_wakeref.h"
+static void rpm_get(struct drm_i915_private *i915, struct intel_wakeref *wf)
+{
+ wf->wakeref = intel_runtime_pm_get(i915);
+}
+
+static void rpm_put(struct drm_i915_private *i915, struct intel_wakeref *wf)
+{
+ intel_wakeref_t wakeref = fetch_and_zero(>wakeref);
+
+ intel_runtime_pm_put(i915, wakeref);
+ GEM_BUG_ON(!wakeref);
+}
+
int __intel_wakeref_get_first(struct drm_i915_private *i915,
struct intel_wakeref *wf,
int (*fn)(struct intel_wakeref *wf))
@@ -21,11 +34,11 @@ int __intel_wakeref_get_first(struct drm_i915_private *i915,
if (!atomic_read(>count)) {
int err;
- wf->wakeref = intel_runtime_pm_get(i915);
+ rpm_get(i915, wf);
err = fn(wf);
if (unlikely(err)) {
- intel_runtime_pm_put(i915, wf->wakeref);
+ rpm_put(i915, wf);
mutex_unlock(>mutex);
return err;
}
@@ -46,7 +59,7 @@ int __intel_wakeref_put_last(struct drm_i915_private *i915,
err = fn(wf);
if (likely(!err))
- intel_runtime_pm_put(i915, wf->wakeref);
+ rpm_put(i915, wf);
else
atomic_inc(>count);
mutex_unlock(>mutex);
@@ -58,4 +71,5 @@ void __intel_wakeref_init(struct intel_wakeref *wf, struct
lock_class_key *key)
{
__mutex_init(>mutex, "wakeref", key);
atomic_set(>count, 0);
+ wf->wakeref = 0;
}
diff --git a/drivers/gpu/drm/i915/intel_wakeref.h
b/drivers/gpu/drm/i915/intel_wakeref.h
index a979d638344b..db742291211c 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.h
+++ b/drivers/gpu/drm/i915/intel_wakeref.h
@@ -127,7 +127,7 @@ intel_wakeref_unlock(struct intel_wakeref *wf)
static inline bool
intel_wakeref_active(struct intel_wakeref *wf)
{
- return atomic_read(>count);
+ return READ_ONCE(wf->wakeref);
}
#endif /* INTEL_WAKEREF_H */
--
2.20.1
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[Intel-gfx] [PATCH 1/3] drm/i915: Complete both freed-object passes before draining the workqueue
The workqueue code complains viciously if we try to queue more work onto
the queue while attampting to drain it. As we asynchronously free
objects and defer their enqueuing with RCU, it is quite tricky to
quiesce the system before attempting to drain the workqueue. Yet drain
we must to ensure that the worker is idle before unloading the module.
Give the freed object drain 3 whole passes with multiple rcu_barrier()
to give the defer freeing of several levels each protected by RCU and
needing a grace period before its parent can be freed, ultimately
resulting in a GEM object being freed after another RCU period.
A consequence is that it will make module unload even slower.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110550
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 13270e19eb87..9a634ba57ff9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2824,15 +2824,15 @@ static inline void i915_gem_drain_workqueue(struct
drm_i915_private *i915)
* grace period so that we catch work queued via RCU from the first
* pass. As neither drain_workqueue() nor flush_workqueue() report
* a result, we make an assumption that we only don't require more
-* than 2 passes to catch all recursive RCU delayed work.
+* than 3 passes to catch all _recursive_ RCU delayed work.
*
*/
- int pass = 2;
+ int pass = 3;
do {
rcu_barrier();
i915_gem_drain_freed_objects(i915);
- drain_workqueue(i915->wq);
} while (--pass);
+ drain_workqueue(i915->wq);
}
struct i915_vma * __must_check
--
2.20.1
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/14] drm/i915/hangcheck: Track context changes
== Series Details == Series: series starting with [01/14] drm/i915/hangcheck: Track context changes URL : https://patchwork.freedesktop.org/series/60153/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6021 -> Patchwork_12923 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12923 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12923, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/60153/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12923: ### IGT changes ### Possible regressions * igt@i915_selftest@live_execlists: - fi-cfl-8700k: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-cfl-8700k/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-cfl-8700k/igt@i915_selftest@live_execlists.html - fi-kbl-7567u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-7567u/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-kbl-7567u/igt@i915_selftest@live_execlists.html - fi-whl-u: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-whl-u/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-whl-u/igt@i915_selftest@live_execlists.html - fi-kbl-7500u: NOTRUN -> [INCOMPLETE][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-kbl-7500u/igt@i915_selftest@live_execlists.html - fi-kbl-8809g: [PASS][8] -> [INCOMPLETE][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-8809g/igt@i915_selftest@live_execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-kbl-8809g/igt@i915_selftest@live_execlists.html - fi-kbl-x1275: [PASS][10] -> [INCOMPLETE][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-x1275/igt@i915_selftest@live_execlists.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-kbl-x1275/igt@i915_selftest@live_execlists.html - fi-skl-6600u: [PASS][12] -> [INCOMPLETE][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-skl-6600u/igt@i915_selftest@live_execlists.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-skl-6600u/igt@i915_selftest@live_execlists.html - fi-bsw-n3050: [PASS][14] -> [INCOMPLETE][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-bsw-n3050/igt@i915_selftest@live_execlists.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-bsw-n3050/igt@i915_selftest@live_execlists.html - fi-bsw-kefka: [PASS][16] -> [INCOMPLETE][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-bsw-kefka/igt@i915_selftest@live_execlists.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-bsw-kefka/igt@i915_selftest@live_execlists.html - fi-skl-6700k2: [PASS][18] -> [INCOMPLETE][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-skl-6700k2/igt@i915_selftest@live_execlists.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-skl-6700k2/igt@i915_selftest@live_execlists.html - fi-skl-6260u: [PASS][20] -> [INCOMPLETE][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-skl-6260u/igt@i915_selftest@live_execlists.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-skl-6260u/igt@i915_selftest@live_execlists.html - fi-skl-6770hq: [PASS][22] -> [INCOMPLETE][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-skl-6770hq/igt@i915_selftest@live_execlists.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-skl-6770hq/igt@i915_selftest@live_execlists.html - fi-bdw-5557u: [PASS][24] -> [INCOMPLETE][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-bdw-5557u/igt@i915_selftest@live_execlists.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-bdw-5557u/igt@i915_selftest@live_execlists.html - fi-kbl-r: [PASS][26] -> [INCOMPLETE][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6021/fi-kbl-r/igt@i915_selftest@live_execlists.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12923/fi-kbl-r/igt@i915_selftest@live_execlists.html - fi-skl-lmem:[PASS][28] -> [INCOMPLETE][29] [28]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable Multi-segmented-gamma for ICL
== Series Details == Series: Enable Multi-segmented-gamma for ICL URL : https://patchwork.freedesktop.org/series/60126/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6018_full -> Patchwork_12915_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12915_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12915_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12915_full: ### IGT changes ### Possible regressions * igt@gem_mocs_settings@mocs-rc6-render: - shard-skl: NOTRUN -> [INCOMPLETE][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-skl4/igt@gem_mocs_setti...@mocs-rc6-render.html * igt@gem_pwrite@small-cpu-random: - shard-skl: [PASS][2] -> [INCOMPLETE][3] +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl9/igt@gem_pwr...@small-cpu-random.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-skl9/igt@gem_pwr...@small-cpu-random.html * igt@kms_color@pipe-b-ctm-0-25: - shard-iclb: [PASS][4] -> [FAIL][5] +5 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-iclb6/igt@kms_co...@pipe-b-ctm-0-25.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-iclb5/igt@kms_co...@pipe-b-ctm-0-25.html Warnings * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-pwrite: - shard-skl: [SKIP][6] ([fdo#109271]) -> [INCOMPLETE][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl10/igt@kms_frontbuffer_track...@psr-2p-primscrn-pri-shrfb-draw-pwrite.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-skl10/igt@kms_frontbuffer_track...@psr-2p-primscrn-pri-shrfb-draw-pwrite.html Known issues Here are the changes found in Patchwork_12915_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - shard-skl: [PASS][8] -> [INCOMPLETE][9] ([fdo#104108] / [fdo#107773]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl7/igt@gem_exec_susp...@basic-s3.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-skl4/igt@gem_exec_susp...@basic-s3.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([fdo#108566]) +4 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-apl4/igt@gem_workarou...@suspend-resume.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-apl3/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_rpm@basic-rte: - shard-skl: [PASS][12] -> [INCOMPLETE][13] ([fdo#107807]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl8/igt@i915_pm_...@basic-rte.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-skl1/igt@i915_pm_...@basic-rte.html * igt@i915_pm_rpm@gem-execbuf: - shard-hsw: [PASS][14] -> [INCOMPLETE][15] ([fdo#103540] / [fdo#107803] / [fdo#107807]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-hsw6/igt@i915_pm_...@gem-execbuf.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-hsw1/igt@i915_pm_...@gem-execbuf.html * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-glk: [PASS][16] -> [INCOMPLETE][17] ([fdo#103359] / [k.org#198133]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-glk3/igt@kms_b...@extended-modeset-hang-newfb-with-reset-render-a.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-glk1/igt@kms_b...@extended-modeset-hang-newfb-with-reset-render-a.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: [PASS][18] -> [FAIL][19] ([fdo#100368]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl6/igt@kms_f...@plain-flip-ts-check-interruptible.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12915/shard-skl6/igt@kms_f...@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: - shard-skl: [PASS][20] -> [FAIL][21] ([fdo#103167]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl10/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html [21]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/14] drm/i915/hangcheck: Track context changes
== Series Details == Series: series starting with [01/14] drm/i915/hangcheck: Track context changes URL : https://patchwork.freedesktop.org/series/60153/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/hangcheck: Track context changes Okay! Commit: drm/i915: Include fence signaled bit in print_request() Okay! Commit: drm/i915/execlists: Flush the tasklet on parking Okay! Commit: drm/i915: Leave engine parking to the engines Okay! Commit: drm/i915: Remove delay for idle_work Okay! Commit: drm/i915: Cancel retire_worker on parking Okay! Commit: drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches) Okay! Commit: drm/i915: Only reschedule the submission tasklet if preemption is possible -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/gt/intel_engine.h:124:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) Commit: drm/i915: Delay semaphore submission until the start of the signaler Okay! Commit: drm/i915/execlists: Don't apply priority boost for resets Okay! Commit: drm/i915: Rearrange i915_scheduler.c Okay! Commit: drm/i915: Pass i915_sched_node around internally Okay! Commit: drm/i915: Bump signaler priority on adding a waiter Okay! Commit: drm/i915: Convert inconsistent static engine tables into an init error Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v11] drm/i915: Engine discovery query
Quoting Tvrtko Ursulin (2019-05-01 12:45:36)
>
> On 01/05/2019 12:10, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-05-01 11:52:28)
> >> From: Tvrtko Ursulin
> >>
> >> Engine discovery query allows userspace to enumerate engines, probe their
> >> configuration features, all without needing to maintain the internal PCI
> >> ID based database.
> >>
> >> A new query for the generic i915 query ioctl is added named
> >> DRM_I915_QUERY_ENGINE_INFO, together with accompanying structure
> >> drm_i915_query_engine_info. The address of latter should be passed to the
> >> kernel in the query.data_ptr field, and should be large enough for the
> >> kernel to fill out all known engines as struct drm_i915_engine_info
> >> elements trailing the query.
> >>
> >> As with other queries, setting the item query length to zero allows
> >> userspace to query minimum required buffer size.
> >>
> >> Enumerated engines have common type mask which can be used to query all
> >> hardware engines, versus engines userspace can submit to using the execbuf
> >> uAPI.
> >>
> >> Engines also have capabilities which are per engine class namespace of
> >> bits describing features not present on all engine instances.
> >>
> >> v2:
> >> * Fixed HEVC assignment.
> >> * Reorder some fields, rename type to flags, increase width. (Lionel)
> >> * No need to allocate temporary storage if we do it engine by engine.
> >> (Lionel)
> >>
> >> v3:
> >> * Describe engine flags and mark mbz fields. (Lionel)
> >> * HEVC only applies to VCS.
> >>
> >> v4:
> >> * Squash SFC flag into main patch.
> >> * Tidy some comments.
> >>
> >> v5:
> >> * Add uabi_ prefix to engine capabilities. (Chris Wilson)
> >> * Report exact size of engine info array. (Chris Wilson)
> >> * Drop the engine flags. (Joonas Lahtinen)
> >> * Added some more reserved fields.
> >> * Move flags after class/instance.
> >>
> >> v6:
> >> * Do not check engine info array was zeroed by userspace but zero the
> >> unused fields for them instead.
> >>
> >> v7:
> >> * Simplify length calculation loop. (Lionel Landwerlin)
> >>
> >> v8:
> >> * Remove MBZ comments where not applicable.
> >> * Rename ABI flags to match engine class define naming.
> >> * Rename SFC ABI flag to reflect it applies to VCS and VECS.
> >> * SFC is wired to even _logical_ engine instances.
> >> * SFC applies to VCS and VECS.
> >> * HEVC is present on all instances on Gen11. (Tony)
> >> * Simplify length calculation even more. (Chris Wilson)
> >> * Move info_ptr assigment closer to loop for clarity. (Chris Wilson)
> >> * Use vdbox_sfc_access from runtime info.
> >> * Rebase for RUNTIME_INFO.
> >> * Refactor for lower indentation.
> >> * Rename uAPI class/instance to engine_class/instance to avoid C++
> >> keyword.
> >>
> >> v9:
> >> * Rebase for s/num_rings/num_engines/ in RUNTIME_INFO.
> >>
> >> v10:
> >> * Use new copy_query_item.
> >>
> >> v11:
> >> * Consolidate with struct i915_engine_class_instnace.
> >>
> >> Signed-off-by: Tvrtko Ursulin
> >> Cc: Chris Wilson
> >> Cc: Jon Bloomfield
> >> Cc: Dmitry Rogozhkin
> >> Cc: Lionel Landwerlin
> >> Cc: Joonas Lahtinen
> >> Cc: Tony Ye
> >> Reviewed-by: Lionel Landwerlin # v7
> >> Reviewed-by: Chris Wilson # v7
> >> ---
> >> +/**
> >> + * struct drm_i915_engine_info
> >> + *
> >> + * Describes one engine and it's capabilities as known to the driver.
> >> + */
> >> +struct drm_i915_engine_info {
> >> + /** Engine class and instance. */
> >> + struct i915_engine_class_instance engine;
> >> +
> >> + /** Reserved field. */
> >> + __u32 rsvd0;
> >> +
> >> + /** Engine flags. */
> >> + __u64 flags;
> >
> > Do you think we could do something like
> > BUILD_BUG_ON(!IS_ALIGNED(offsetof(*info, flags), sizeof(info->flags));
> >
> > Will that work, and worthwhile? Maybe work into a
> >
> > BUILD_BUG_ON(check_user_alignment(info, flags));
>
> Hmm.. probably manual check for no holes _and_ alignment is good enough
> for uAPI since once it's in it's in. Will triple-check.
Yeah, we actually need something more like
offsetofend(previous_field) == offsetof(next_field)
BUILD_BUG_ON(check_user_struct(info, previous_field, next_field)) ?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/14] drm/i915: Rearrange i915_scheduler.c
To avoid pulling in a forward declaration in the next patch, move the
i915_sched_node handling to after the main dfs of the scheduler.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_scheduler.c | 210 +-
1 file changed, 105 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 88d18600f5db..834b10ad4ce1 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -35,109 +35,6 @@ static inline bool node_signaled(const struct
i915_sched_node *node)
return i915_request_completed(node_to_request(node));
}
-void i915_sched_node_init(struct i915_sched_node *node)
-{
- INIT_LIST_HEAD(>signalers_list);
- INIT_LIST_HEAD(>waiters_list);
- INIT_LIST_HEAD(>link);
- node->attr.priority = I915_PRIORITY_INVALID;
- node->semaphores = 0;
- node->flags = 0;
-}
-
-static struct i915_dependency *
-i915_dependency_alloc(void)
-{
- return kmem_cache_alloc(global.slab_dependencies, GFP_KERNEL);
-}
-
-static void
-i915_dependency_free(struct i915_dependency *dep)
-{
- kmem_cache_free(global.slab_dependencies, dep);
-}
-
-bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
- struct i915_sched_node *signal,
- struct i915_dependency *dep,
- unsigned long flags)
-{
- bool ret = false;
-
- spin_lock_irq(_lock);
-
- if (!node_signaled(signal)) {
- INIT_LIST_HEAD(>dfs_link);
- list_add(>wait_link, >waiters_list);
- list_add(>signal_link, >signalers_list);
- dep->signaler = signal;
- dep->flags = flags;
-
- /* Keep track of whether anyone on this chain has a semaphore */
- if (signal->flags & I915_SCHED_HAS_SEMAPHORE_CHAIN &&
- !node_started(signal))
- node->flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
-
- ret = true;
- }
-
- spin_unlock_irq(_lock);
-
- return ret;
-}
-
-int i915_sched_node_add_dependency(struct i915_sched_node *node,
- struct i915_sched_node *signal)
-{
- struct i915_dependency *dep;
-
- dep = i915_dependency_alloc();
- if (!dep)
- return -ENOMEM;
-
- if (!__i915_sched_node_add_dependency(node, signal, dep,
- I915_DEPENDENCY_ALLOC))
- i915_dependency_free(dep);
-
- return 0;
-}
-
-void i915_sched_node_fini(struct i915_sched_node *node)
-{
- struct i915_dependency *dep, *tmp;
-
- GEM_BUG_ON(!list_empty(>link));
-
- spin_lock_irq(_lock);
-
- /*
-* Everyone we depended upon (the fences we wait to be signaled)
-* should retire before us and remove themselves from our list.
-* However, retirement is run independently on each timeline and
-* so we may be called out-of-order.
-*/
- list_for_each_entry_safe(dep, tmp, >signalers_list, signal_link) {
- GEM_BUG_ON(!node_signaled(dep->signaler));
- GEM_BUG_ON(!list_empty(>dfs_link));
-
- list_del(>wait_link);
- if (dep->flags & I915_DEPENDENCY_ALLOC)
- i915_dependency_free(dep);
- }
-
- /* Remove ourselves from everyone who depends upon us */
- list_for_each_entry_safe(dep, tmp, >waiters_list, wait_link) {
- GEM_BUG_ON(dep->signaler != node);
- GEM_BUG_ON(!list_empty(>dfs_link));
-
- list_del(>signal_link);
- if (dep->flags & I915_DEPENDENCY_ALLOC)
- i915_dependency_free(dep);
- }
-
- spin_unlock_irq(_lock);
-}
-
static inline struct i915_priolist *to_priolist(struct rb_node *rb)
{
return rb_entry(rb, struct i915_priolist, node);
@@ -239,6 +136,11 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine,
int prio)
return >requests[idx];
}
+void __i915_priolist_free(struct i915_priolist *p)
+{
+ kmem_cache_free(global.slab_priorities, p);
+}
+
struct sched_cache {
struct list_head *priolist;
};
@@ -440,9 +342,107 @@ void i915_schedule_bump_priority(struct i915_request *rq,
unsigned int bump)
spin_unlock_irqrestore(_lock, flags);
}
-void __i915_priolist_free(struct i915_priolist *p)
+void i915_sched_node_init(struct i915_sched_node *node)
{
- kmem_cache_free(global.slab_priorities, p);
+ INIT_LIST_HEAD(>signalers_list);
+ INIT_LIST_HEAD(>waiters_list);
+ INIT_LIST_HEAD(>link);
+ node->attr.priority = I915_PRIORITY_INVALID;
+ node->semaphores = 0;
+ node->flags = 0;
+}
+
+static struct i915_dependency *
+i915_dependency_alloc(void)
+{
+ return kmem_cache_alloc(global.slab_dependencies,
[Intel-gfx] [PATCH 07/14] drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches)
If the user is racing a call to debugfs/i915_drop_caches with ongoing
submission from another thread/process, we may never end up idling the
GPU and be uninterruptibly spinning in debugfs/i915_drop_caches trying
to catch an idle moment.
Just flush the work once, that should be enough to park the system under
correct conditions. Outside of those we either have a driver bug or the
user is racing themselves. Sadly, because the user may be provoking the
unwanted situation we can't put a warn here to attract attention to a
probable bug.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7e8898d0b78b..2ecefacb1e66 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3933,9 +3933,7 @@ i915_drop_caches_set(void *data, u64 val)
fs_reclaim_release(GFP_KERNEL);
if (val & DROP_IDLE) {
- do {
- flush_delayed_work(>gem.retire_work);
- } while (READ_ONCE(i915->gt.awake));
+ flush_delayed_work(>gem.retire_work);
flush_work(>gem.idle_work);
}
--
2.20.1
___
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Re: [Intel-gfx] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests
Quoting Tvrtko Ursulin (2019-05-01 12:42:59)
> + switch (engine->engine.engine_class) {
> + case I915_ENGINE_CLASS_RENDER:
> + /* Will be tested later. */
> + break;
> + case I915_ENGINE_CLASS_COPY:
> + igt_assert(gem_has_blt(fd));
> + break;
> + case I915_ENGINE_CLASS_VIDEO:
> + switch (engine->engine.engine_instance) {
> + case 0:
> + igt_assert(gem_has_bsd(fd));
> + break;
> + case 1:
> + igt_assert(gem_has_bsd2(fd));
> + break;
Is that relationship a given?
One could argue that gem_has_blt() means that I915_EXEC_BLT works, but
without !gem_has_blt() we could still access CLASS_COPY:0 via
ctx->engines[].
> + }
> + break;
> + case I915_ENGINE_CLASS_VIDEO_ENHANCE:
> + igt_assert(gem_has_vebox(fd));
> + break;
> + default:
> + igt_assert(0);
> + }
> + }
> +
> + /* Reverse check to the above - all GET_PARAM engines are present. */
> + igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0));
> + if (gem_has_blt(fd))
> + igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0));
> + if (gem_has_bsd(fd))
> + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0));
> + if (gem_has_bsd2(fd))
> + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1));
> + if (gem_has_vebox(fd))
> + igt_assert(has_engine(engines,
> I915_ENGINE_CLASS_VIDEO_ENHANCE,
> + 0));
Whereas this should always make sense, given the legacy interface and
the modern interface, the modern interface should be a superset of the
legacy.
Just thinking aloud.
-Chris
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[Intel-gfx] [PATCH 14/14] drm/i915: Convert inconsistent static engine tables into an init error
Remove the modification of the "constant" device info by promoting the
inconsistent intel_engine static table into an initialisation error.
Now, if we add a new engine into the device_info, we must first add that
engine information into the intel_engines.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 ---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f178f1268f4e..0b3da6d2ef59 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -372,15 +372,14 @@ void intel_engines_cleanup(struct drm_i915_private *i915)
*/
int intel_engines_init_mmio(struct drm_i915_private *i915)
{
- struct intel_device_info *device_info = mkwrite_device_info(i915);
- const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
- unsigned int mask = 0;
unsigned int i;
int err;
- WARN_ON(engine_mask == 0);
- WARN_ON(engine_mask &
- GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
+ /* We always presume we have at least RCS available for later probing */
+ if (GEM_WARN_ON(!HAS_ENGINE(i915, RCS0))) {
+ err = -ENODEV;
+ goto cleanup;
+ }
if (i915_inject_load_failure())
return -ENODEV;
@@ -392,25 +391,16 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
err = intel_engine_setup(i915, i);
if (err)
goto cleanup;
-
- mask |= BIT(i);
}
- /*
-* Catch failures to update intel_engines table when the new engines
-* are added to the driver by a warning and disabling the forgotten
-* engines.
-*/
- if (WARN_ON(mask != engine_mask))
- device_info->engine_mask = mask;
-
- /* We always presume we have at least RCS available for later probing */
- if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
+ /* Catch failures to update intel_engines table for new engines. */
+ if (GEM_WARN_ON(INTEL_INFO(i915)->engine_mask >> i)) {
err = -ENODEV;
goto cleanup;
}
- RUNTIME_INFO(i915)->num_engines = hweight32(mask);
+ RUNTIME_INFO(i915)->num_engines =
+ hweight32(INTEL_INFO(i915)->engine_mask);
i915_check_and_clear_faults(i915);
--
2.20.1
___
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[Intel-gfx] [PATCH 05/14] drm/i915: Remove delay for idle_work
The original intent for the delay before running the idle_work was to
provide a hysteresis to avoid ping-ponging the device runtime-pm. Since
then we have also pulled in some memory management and general device
management for parking. But with the inversion of the wakeref handling,
GEM is no longer responsible for the wakeref and by the time we call the
idle_work, the device is asleep. It seems appropriate now to drop the
delay and just run the worker immediately to flush the cached GEM state
before sleeping.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_pm.c| 21 +++
.../gpu/drm/i915/selftests/i915_gem_object.c | 2 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 4 ++--
5 files changed, 12 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0e4dffcd4da4..7e8898d0b78b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3935,8 +3935,8 @@ i915_drop_caches_set(void *data, u64 val)
if (val & DROP_IDLE) {
do {
flush_delayed_work(>gem.retire_work);
- drain_delayed_work(>gem.idle_work);
} while (READ_ONCE(i915->gt.awake));
+ flush_work(>gem.idle_work);
}
if (val & DROP_FREED)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 13270e19eb87..cbf4a7d8bdae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2035,7 +2035,7 @@ struct drm_i915_private {
* arrive within a small period of time, we fire
* off the idle_work.
*/
- struct delayed_work idle_work;
+ struct work_struct idle_work;
} gem;
/* For i945gm vblank irq vs. C3 workaround */
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index 49b0ce594f20..ae91ad7cb31e 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -29,12 +29,12 @@ static void i915_gem_park(struct drm_i915_private *i915)
static void idle_work_handler(struct work_struct *work)
{
struct drm_i915_private *i915 =
- container_of(work, typeof(*i915), gem.idle_work.work);
+ container_of(work, typeof(*i915), gem.idle_work);
mutex_lock(>drm.struct_mutex);
intel_wakeref_lock(>gt.wakeref);
- if (!intel_wakeref_active(>gt.wakeref))
+ if (!intel_wakeref_active(>gt.wakeref) && !work_pending(work))
i915_gem_park(i915);
intel_wakeref_unlock(>gt.wakeref);
@@ -74,9 +74,7 @@ static int pm_notifier(struct notifier_block *nb,
break;
case INTEL_GT_PARK:
- mod_delayed_work(i915->wq,
->gem.idle_work,
-msecs_to_jiffies(100));
+ queue_work(i915->wq, >gem.idle_work);
break;
}
@@ -142,16 +140,11 @@ void i915_gem_suspend(struct drm_i915_private *i915)
* Assert that we successfully flushed all the work and
* reset the GPU back to its idle, low power state.
*/
- GEM_BUG_ON(i915->gt.awake);
- cancel_delayed_work_sync(>gpu_error.hangcheck_work);
-
drain_delayed_work(>gem.retire_work);
+ GEM_BUG_ON(i915->gt.awake);
+ flush_work(>gem.idle_work);
- /*
-* As the idle_work is rearming if it detects a race, play safe and
-* repeat the flush until it is definitely idle.
-*/
- drain_delayed_work(>gem.idle_work);
+ cancel_delayed_work_sync(>gpu_error.hangcheck_work);
i915_gem_drain_freed_objects(i915);
@@ -242,7 +235,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
void i915_gem_init__pm(struct drm_i915_private *i915)
{
- INIT_DELAYED_WORK(>gem.idle_work, idle_work_handler);
+ INIT_WORK(>gem.idle_work, idle_work_handler);
INIT_DELAYED_WORK(>gem.retire_work, retire_work_handler);
i915->gem.pm_notifier.notifier_call = pm_notifier;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
index 088b2aa05dcd..b926d1cd165d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -509,7 +509,7 @@ static void disable_retire_worker(struct drm_i915_private
*i915)
intel_gt_pm_get(i915);
cancel_delayed_work_sync(>gem.retire_work);
- cancel_delayed_work_sync(>gem.idle_work);
+ flush_work(>gem.idle_work);
}
static void restore_retire_worker(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
[Intel-gfx] [PATCH 12/14] drm/i915: Pass i915_sched_node around internally
To simplify the next patch, update bump_priority and schedule to accept
the internal i915_sched_ndoe directly and not expect a request pointer.
add/remove: 0/0 grow/shrink: 2/1 up/down: 8/-15 (-7)
Function old new delta
i915_schedule_bump_priority 109 113 +4
i915_schedule 50 54 +4
__i915_schedule 922 907 -15
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_scheduler.c | 33 +++
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 834b10ad4ce1..05eb50558aba 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -179,7 +179,7 @@ static bool kick_tasklet(const struct intel_engine_cs
*engine, int prio)
return i915_scheduler_need_preempt(prio, rq_prio(inflight));
}
-static void __i915_schedule(struct i915_request *rq,
+static void __i915_schedule(struct i915_sched_node *rq,
const struct i915_sched_attr *attr)
{
struct intel_engine_cs *engine;
@@ -193,13 +193,13 @@ static void __i915_schedule(struct i915_request *rq,
lockdep_assert_held(_lock);
GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
- if (i915_request_completed(rq))
+ if (prio <= READ_ONCE(rq->attr.priority))
return;
- if (prio <= READ_ONCE(rq->sched.attr.priority))
+ if (node_signaled(rq))
return;
- stack.signaler = >sched;
+ stack.signaler = rq;
list_add(_link, );
/*
@@ -250,9 +250,9 @@ static void __i915_schedule(struct i915_request *rq,
* execlists_submit_request()), we can set our own priority and skip
* acquiring the engine locks.
*/
- if (rq->sched.attr.priority == I915_PRIORITY_INVALID) {
- GEM_BUG_ON(!list_empty(>sched.link));
- rq->sched.attr = *attr;
+ if (rq->attr.priority == I915_PRIORITY_INVALID) {
+ GEM_BUG_ON(!list_empty(>link));
+ rq->attr = *attr;
if (stack.dfs_link.next == stack.dfs_link.prev)
return;
@@ -261,7 +261,7 @@ static void __i915_schedule(struct i915_request *rq,
}
memset(, 0, sizeof(cache));
- engine = rq->engine;
+ engine = node_to_request(rq)->engine;
spin_lock(>timeline.lock);
/* Fifo and depth-first replacement ensure our deps execute before us */
@@ -319,13 +319,20 @@ static void __i915_schedule(struct i915_request *rq,
void i915_schedule(struct i915_request *rq, const struct i915_sched_attr *attr)
{
spin_lock_irq(_lock);
- __i915_schedule(rq, attr);
+ __i915_schedule(>sched, attr);
spin_unlock_irq(_lock);
}
+static void __bump_priority(struct i915_sched_node *node, unsigned int bump)
+{
+ struct i915_sched_attr attr = node->attr;
+
+ attr.priority |= bump;
+ __i915_schedule(node, );
+}
+
void i915_schedule_bump_priority(struct i915_request *rq, unsigned int bump)
{
- struct i915_sched_attr attr;
unsigned long flags;
GEM_BUG_ON(bump & ~I915_PRIORITY_MASK);
@@ -334,11 +341,7 @@ void i915_schedule_bump_priority(struct i915_request *rq,
unsigned int bump)
return;
spin_lock_irqsave(_lock, flags);
-
- attr = rq->sched.attr;
- attr.priority |= bump;
- __i915_schedule(rq, );
-
+ __bump_priority(>sched, bump);
spin_unlock_irqrestore(_lock, flags);
}
--
2.20.1
___
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[Intel-gfx] [PATCH 10/14] drm/i915/execlists: Don't apply priority boost for resets
Do not treat reset as a normal preemption event and avoid giving the
guilty request a priority boost for simply being active at the time of
reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 35aae7b5c6b9..aa03dd0760e9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -370,11 +370,11 @@ static void unwind_wa_tail(struct i915_request *rq)
}
static struct i915_request *
-__unwind_incomplete_requests(struct intel_engine_cs *engine)
+__unwind_incomplete_requests(struct intel_engine_cs *engine, int boost)
{
struct i915_request *rq, *rn, *active = NULL;
struct list_head *uninitialized_var(pl);
- int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
+ int prio = I915_PRIORITY_INVALID | boost;
lockdep_assert_held(>timeline.lock);
@@ -418,8 +418,9 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine)
* in the priority queue, but they will not gain immediate access to
* the GPU.
*/
- if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) {
- prio |= ACTIVE_PRIORITY;
+ if (~prio & boost && __i915_request_has_started(active)) {
+ prio |= boost;
+ GEM_BUG_ON(active->sched.attr.priority >= prio);
active->sched.attr.priority = prio;
list_move_tail(>sched.link,
i915_sched_lookup_priolist(engine, prio));
@@ -434,7 +435,7 @@ execlists_unwind_incomplete_requests(struct
intel_engine_execlists *execlists)
struct intel_engine_cs *engine =
container_of(execlists, typeof(*engine), execlists);
- return __unwind_incomplete_requests(engine);
+ return __unwind_incomplete_requests(engine, 0);
}
static inline void
@@ -655,7 +656,8 @@ static void complete_preempt_context(struct
intel_engine_execlists *execlists)
execlists_cancel_port_requests(execlists);
__unwind_incomplete_requests(container_of(execlists,
struct intel_engine_cs,
- execlists));
+ execlists),
+ACTIVE_PRIORITY);
}
static void execlists_dequeue(struct intel_engine_cs *engine)
@@ -1908,7 +1910,7 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
execlists_cancel_port_requests(execlists);
/* Push back any incomplete requests for replay after the reset. */
- rq = __unwind_incomplete_requests(engine);
+ rq = __unwind_incomplete_requests(engine, 0);
if (!rq)
goto out_replay;
--
2.20.1
___
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[Intel-gfx] [PATCH 04/14] drm/i915: Leave engine parking to the engines
Drop the check in GEM parking that the engines were already parked. The
intention here was that before we dropped the GT wakeref, we were sure
that no more interrupts could be raised -- however, we have already
dropped the wakeref by this point and the warning is no longer valid.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_pm.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index 3b6e8d5be8e1..49b0ce594f20 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -17,24 +17,8 @@ static void i915_gem_park(struct drm_i915_private *i915)
lockdep_assert_held(>drm.struct_mutex);
- for_each_engine(engine, i915, id) {
- /*
-* We are committed now to parking the engines, make sure there
-* will be no more interrupts arriving later and the engines
-* are truly idle.
-*/
- if (wait_for(intel_engine_is_idle(engine), 10)) {
- struct drm_printer p = drm_debug_printer(__func__);
-
- dev_err(i915->drm.dev,
- "%s is not idle before parking\n",
- engine->name);
- intel_engine_dump(engine, , NULL);
- }
- tasklet_kill(>execlists.tasklet);
-
+ for_each_engine(engine, i915, id)
i915_gem_batch_pool_fini(>batch_pool);
- }
i915_timelines_park(i915);
i915_vma_parked(i915);
--
2.20.1
___
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[Intel-gfx] [PATCH 08/14] drm/i915: Only reschedule the submission tasklet if preemption is possible
If we couple the scheduler more tightly with the execlists policy, we
can apply the preemption policy to the question of whether we need to
kick the tasklet at all for this priority bump.
v2: Rephrase it as a core i915 policy and not an execlists foible.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 18 --
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 7 ++-
drivers/gpu/drm/i915/i915_request.c | 2 --
drivers/gpu/drm/i915/i915_scheduler.c | 18 +++---
drivers/gpu/drm/i915/i915_scheduler.h | 18 ++
drivers/gpu/drm/i915/intel_guc_submission.c | 3 ++-
7 files changed, 39 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index f5b0f27cecb6..06d785533502 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -106,24 +106,6 @@ hangcheck_action_to_str(const enum
intel_engine_hangcheck_action a)
void intel_engines_set_scheduler_caps(struct drm_i915_private *i915);
-static inline bool __execlists_need_preempt(int prio, int last)
-{
- /*
-* Allow preemption of low -> normal -> high, but we do
-* not allow low priority tasks to preempt other low priority
-* tasks under the impression that latency for low priority
-* tasks does not matter (as much as background throughput),
-* so kiss.
-*
-* More naturally we would write
-* prio >= max(0, last);
-* except that we wish to prevent triggering preemption at the same
-* priority level: the task that is running should remain running
-* to preserve FIFO ordering of dependencies.
-*/
- return prio > max(I915_PRIORITY_NORMAL - 1, last);
-}
-
static inline void
execlists_set_active(struct intel_engine_execlists *execlists,
unsigned int bit)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7be54b868d8e..35aae7b5c6b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -251,8 +251,8 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
* ourselves, ignore the request.
*/
last_prio = effective_prio(rq);
- if (!__execlists_need_preempt(engine->execlists.queue_priority_hint,
- last_prio))
+ if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint,
+last_prio))
return false;
/*
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 84538f69185b..4b042893dc0e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -638,14 +638,19 @@ static struct i915_request *dummy_request(struct
intel_engine_cs *engine)
GEM_BUG_ON(i915_request_completed(rq));
i915_sw_fence_init(>submit, dummy_notify);
- i915_sw_fence_commit(>submit);
+ set_bit(I915_FENCE_FLAG_ACTIVE, >fence.flags);
return rq;
}
static void dummy_request_free(struct i915_request *dummy)
{
+ /* We have to fake the CS interrupt to kick the next request */
+ i915_sw_fence_commit(>submit);
+
i915_request_mark_complete(dummy);
+ dma_fence_signal(>fence);
+
i915_sched_node_fini(>sched);
i915_sw_fence_fini(>submit);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index af8c9fa5e066..2e22da66a56c 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1358,9 +1358,7 @@ long i915_request_wait(struct i915_request *rq,
if (flags & I915_WAIT_PRIORITY) {
if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
gen6_rps_boost(rq);
- local_bh_disable(); /* suspend tasklets for reprioritisation */
i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
- local_bh_enable(); /* kick tasklets en masse */
}
wait.tsk = current;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 39bc4f54e272..88d18600f5db 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -261,16 +261,20 @@ sched_lock_engine(const struct i915_sched_node *node,
return engine;
}
-static bool inflight(const struct i915_request *rq,
-const struct intel_engine_cs *engine)
+static inline int rq_prio(const struct i915_request *rq)
{
- const struct i915_request *active;
+ return rq->sched.attr.priority | __NO_PREEMPTION;
+}
+
+static bool kick_tasklet(const struct intel_engine_cs *engine, int prio)
+{
+
[Intel-gfx] [PATCH 09/14] drm/i915: Delay semaphore submission until the start of the signaler
Currently we submit the semaphore busywait as soon as the signaler is
submitted to HW. However, we may submit the signaler as the tail of a
batch of requests, and even not as the first context in the HW list,
i.e. the busywait may start spinning far in advance of the signaler even
starting.
If we wait until the request before the signaler is completed before
submitting the busywait, we prevent the busywait from starting too
early, if the signaler is not first in submission port.
To handle the case where the signaler is at the start of the second (or
later) submission port, we will need to delay the execution callback
until we know the context is promoted to port0. A challenge for later.
Fixes: e88619646971 ("drm/i915: Use HW semaphores for inter-engine synchroni
sation on gen8+")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 2e22da66a56c..8cb3ed5531e3 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -770,6 +770,21 @@ i915_request_create(struct intel_context *ce)
return rq;
}
+static int
+i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
+{
+ if (list_is_first(>ring_link, >ring->request_list))
+ return 0;
+
+ signal = list_prev_entry(signal, ring_link);
+ if (i915_timeline_sync_is_later(rq->timeline, >fence))
+ return 0;
+
+ return i915_sw_fence_await_dma_fence(>submit,
+>fence, 0,
+I915_FENCE_GFP);
+}
+
static int
emit_semaphore_wait(struct i915_request *to,
struct i915_request *from,
@@ -788,6 +803,10 @@ emit_semaphore_wait(struct i915_request *to,
>fence, 0,
I915_FENCE_GFP);
+ err = i915_request_await_start(to, from);
+ if (err < 0)
+ return err;
+
err = i915_sw_fence_await_dma_fence(>semaphore,
>fence, 0,
I915_FENCE_GFP);
--
2.20.1
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[Intel-gfx] [PATCH 01/14] drm/i915/hangcheck: Track context changes
Given sufficient preemption, we may see a busy system that doesn't
advance seqno while performing work across multiple contexts, and given
sufficient pathology not even notice a change in ACTHD. What does change
between the preempting contexts is their RING, so take note of that and
treat a change in the ring address as being an indication of forward
progress.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 12 +---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9d64e33f8427..c0ab11b12e14 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -53,6 +53,7 @@ struct intel_instdone {
struct intel_engine_hangcheck {
u64 acthd;
+ u32 last_ring;
u32 last_seqno;
u32 next_seqno;
unsigned long action_timestamp;
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index e5eaa06fe74d..721ab74a382f 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -27,6 +27,7 @@
struct hangcheck {
u64 acthd;
+ u32 ring;
u32 seqno;
enum intel_engine_hangcheck_action action;
unsigned long action_timestamp;
@@ -134,6 +135,7 @@ static void hangcheck_load_sample(struct intel_engine_cs
*engine,
{
hc->acthd = intel_engine_get_active_head(engine);
hc->seqno = intel_engine_get_hangcheck_seqno(engine);
+ hc->ring = ENGINE_READ(engine, RING_START);
}
static void hangcheck_store_sample(struct intel_engine_cs *engine,
@@ -141,18 +143,22 @@ static void hangcheck_store_sample(struct intel_engine_cs
*engine,
{
engine->hangcheck.acthd = hc->acthd;
engine->hangcheck.last_seqno = hc->seqno;
+ engine->hangcheck.last_ring = hc->ring;
}
static enum intel_engine_hangcheck_action
hangcheck_get_action(struct intel_engine_cs *engine,
const struct hangcheck *hc)
{
- if (engine->hangcheck.last_seqno != hc->seqno)
- return ENGINE_ACTIVE_SEQNO;
-
if (intel_engine_is_idle(engine))
return ENGINE_IDLE;
+ if (engine->hangcheck.last_ring != hc->ring)
+ return ENGINE_ACTIVE_SEQNO;
+
+ if (engine->hangcheck.last_seqno != hc->seqno)
+ return ENGINE_ACTIVE_SEQNO;
+
return engine_stuck(engine, hc->acthd);
}
--
2.20.1
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[Intel-gfx] [PATCH 03/14] drm/i915/execlists: Flush the tasklet on parking
Tidy up the cleanup sequence by always ensure that the tasklet is
flushed on parking (before we cleanup). The parking provides a
convenient point to ensure that the backend is truly idle.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 ++-
drivers/gpu/drm/i915/intel_guc_submission.c | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 851e62ddcb87..7be54b868d8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2331,6 +2331,11 @@ static int gen8_init_rcs_context(struct i915_request *rq)
return i915_gem_render_state_emit(rq);
}
+static void execlists_park(struct intel_engine_cs *engine)
+{
+ tasklet_kill(>execlists.tasklet);
+}
+
void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = execlists_submit_request;
@@ -2342,7 +2347,7 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->reset.reset = execlists_reset;
engine->reset.finish = execlists_reset_finish;
- engine->park = NULL;
+ engine->park = execlists_park;
engine->unpark = NULL;
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 4c814344809c..ed94001028f2 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1363,6 +1363,7 @@ static void guc_interrupts_release(struct
drm_i915_private *dev_priv)
static void guc_submission_park(struct intel_engine_cs *engine)
{
+ tasklet_kill(>execlists.tasklet);
intel_engine_unpin_breadcrumbs_irq(engine);
engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
--
2.20.1
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[Intel-gfx] [PATCH 13/14] drm/i915: Bump signaler priority on adding a waiter
The handling of the no-preemption priority level imposes the restriction that we need to maintain the implied ordering even though preemption is disabled. Otherwise we may end up with an AB-BA deadlock across multiple engine due to a real preemption event reordering the no-preemption WAITs. To resolve this issue we currently promote all requests to WAIT on unsubmission, however this interferes with the timeslicing requirement that we do not apply any implicit promotion that will defeat the round-robin timeslice list. (If we automatically promote the active request it will go back to the head of the queue and not the tail!) So we need implicit promotion to prevent reordering around semaphores where we are not allowed to preempt, and we must avoid implicit promotion on unsubmission. So instead of at unsubmit, if we apply that implicit promotion on adding the dependency, we avoid the semaphore deadlock and we also reduce the gains made by the promotion for user space waiting. Furthermore, by keeping the earlier dependencies at a higher level, we reduce the search space for timeslicing without altering runtime scheduling too badly (no dependencies at all will be assigned a higher priority for rrul). Testcase: igt/gem_concurrent_blit Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_request.c | 9 - drivers/gpu/drm/i915/i915_scheduler.c | 9 + 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 8cb3ed5531e3..065da1bcbb4c 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -468,15 +468,6 @@ void __i915_request_unsubmit(struct i915_request *request) /* We may be recursing from the signal callback of another i915 fence */ spin_lock_nested(>lock, SINGLE_DEPTH_NESTING); - /* -* As we do not allow WAIT to preempt inflight requests, -* once we have executed a request, along with triggering -* any execution callbacks, we must preserve its ordering -* within the non-preemptible FIFO. -*/ - BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */ - request->sched.attr.priority |= __NO_PREEMPTION; - if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags)) i915_request_cancel_breadcrumb(request); diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 05eb50558aba..ecc3e83ef28d 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -388,6 +388,15 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node, !node_started(signal)) node->flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN; + /* +* As we do not allow WAIT to preempt inflight requests, +* once we have executed a request, along with triggering +* any execution callbacks, we must preserve its ordering +* within the non-preemptible FIFO. +*/ + BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); + __bump_priority(signal, __NO_PREEMPTION); + ret = true; } -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/14] drm/i915: Include fence signaled bit in print_request()
Show the fence flags view of request completion in addition to the normal hwsp check and whether signaling is enabled. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 6e40f8ea9a6a..f178f1268f4e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1229,8 +1229,11 @@ static void print_request(struct drm_printer *m, i915_request_completed(rq) ? "!" : i915_request_started(rq) ? "*" : "", + test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, + >fence.flags) ? "+" : test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - >fence.flags) ? "+" : "", + >fence.flags) ? "-" : + "", buf, jiffies_to_msecs(jiffies - rq->emitted_jiffies), name); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v11] drm/i915: Engine discovery query
On 01/05/2019 12:10, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-05-01 11:52:28)
From: Tvrtko Ursulin
Engine discovery query allows userspace to enumerate engines, probe their
configuration features, all without needing to maintain the internal PCI
ID based database.
A new query for the generic i915 query ioctl is added named
DRM_I915_QUERY_ENGINE_INFO, together with accompanying structure
drm_i915_query_engine_info. The address of latter should be passed to the
kernel in the query.data_ptr field, and should be large enough for the
kernel to fill out all known engines as struct drm_i915_engine_info
elements trailing the query.
As with other queries, setting the item query length to zero allows
userspace to query minimum required buffer size.
Enumerated engines have common type mask which can be used to query all
hardware engines, versus engines userspace can submit to using the execbuf
uAPI.
Engines also have capabilities which are per engine class namespace of
bits describing features not present on all engine instances.
v2:
* Fixed HEVC assignment.
* Reorder some fields, rename type to flags, increase width. (Lionel)
* No need to allocate temporary storage if we do it engine by engine.
(Lionel)
v3:
* Describe engine flags and mark mbz fields. (Lionel)
* HEVC only applies to VCS.
v4:
* Squash SFC flag into main patch.
* Tidy some comments.
v5:
* Add uabi_ prefix to engine capabilities. (Chris Wilson)
* Report exact size of engine info array. (Chris Wilson)
* Drop the engine flags. (Joonas Lahtinen)
* Added some more reserved fields.
* Move flags after class/instance.
v6:
* Do not check engine info array was zeroed by userspace but zero the
unused fields for them instead.
v7:
* Simplify length calculation loop. (Lionel Landwerlin)
v8:
* Remove MBZ comments where not applicable.
* Rename ABI flags to match engine class define naming.
* Rename SFC ABI flag to reflect it applies to VCS and VECS.
* SFC is wired to even _logical_ engine instances.
* SFC applies to VCS and VECS.
* HEVC is present on all instances on Gen11. (Tony)
* Simplify length calculation even more. (Chris Wilson)
* Move info_ptr assigment closer to loop for clarity. (Chris Wilson)
* Use vdbox_sfc_access from runtime info.
* Rebase for RUNTIME_INFO.
* Refactor for lower indentation.
* Rename uAPI class/instance to engine_class/instance to avoid C++
keyword.
v9:
* Rebase for s/num_rings/num_engines/ in RUNTIME_INFO.
v10:
* Use new copy_query_item.
v11:
* Consolidate with struct i915_engine_class_instnace.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Jon Bloomfield
Cc: Dmitry Rogozhkin
Cc: Lionel Landwerlin
Cc: Joonas Lahtinen
Cc: Tony Ye
Reviewed-by: Lionel Landwerlin # v7
Reviewed-by: Chris Wilson # v7
---
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+ /** Engine class and instance. */
+ struct i915_engine_class_instance engine;
+
+ /** Reserved field. */
+ __u32 rsvd0;
+
+ /** Engine flags. */
+ __u64 flags;
Do you think we could do something like
BUILD_BUG_ON(!IS_ALIGNED(offsetof(*info, flags), sizeof(info->flags));
Will that work, and worthwhile? Maybe work into a
BUILD_BUG_ON(check_user_alignment(info, flags));
Hmm.. probably manual check for no holes _and_ alignment is good enough
for uAPI since once it's in it's in. Will triple-check.
Reviewed-by: Chris Wilson
Thanks! I apparently messed up the actual branch and will resend once
IGT series finished so I can play with Test-with:
Regards,
Tvrtko
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[Intel-gfx] [PATCH 06/14] drm/i915: Cancel retire_worker on parking
Replace the racy continuation check within retire_work with a definite
kill-switch on idling. The race was being exposed by gem_concurrent_blit
where the retire_worker would be terminated too early leaving us
spinning in debugfs/i915_drop_caches with nothing flushing the
retirement queue.
Although that the igt is trying to idle from one child while submitting
from another may be a contributing factor as to why it runs so slowly...
Testcase: igt/gem_concurrent_blit
Fixes: 79ffac8599c4 ("drm/i915: Invert the GEM wakeref hierarchy")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_pm.c | 18 --
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 -
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_pm.c
b/drivers/gpu/drm/i915/i915_gem_pm.c
index ae91ad7cb31e..b239b55f84cd 100644
--- a/drivers/gpu/drm/i915/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/i915_gem_pm.c
@@ -30,15 +30,23 @@ static void idle_work_handler(struct work_struct *work)
{
struct drm_i915_private *i915 =
container_of(work, typeof(*i915), gem.idle_work);
+ bool restart = true;
+ cancel_delayed_work_sync(>gem.retire_work);
mutex_lock(>drm.struct_mutex);
intel_wakeref_lock(>gt.wakeref);
- if (!intel_wakeref_active(>gt.wakeref) && !work_pending(work))
+ if (!intel_wakeref_active(>gt.wakeref) && !work_pending(work)) {
i915_gem_park(i915);
+ restart = false;
+ }
intel_wakeref_unlock(>gt.wakeref);
mutex_unlock(>drm.struct_mutex);
+ if (restart)
+ queue_delayed_work(i915->wq,
+ >gem.retire_work,
+ round_jiffies_up_relative(HZ));
}
static void retire_work_handler(struct work_struct *work)
@@ -52,10 +60,9 @@ static void retire_work_handler(struct work_struct *work)
mutex_unlock(>drm.struct_mutex);
}
- if (intel_wakeref_active(>gt.wakeref))
- queue_delayed_work(i915->wq,
- >gem.retire_work,
- round_jiffies_up_relative(HZ));
+ queue_delayed_work(i915->wq,
+ >gem.retire_work,
+ round_jiffies_up_relative(HZ));
}
static int pm_notifier(struct notifier_block *nb,
@@ -140,7 +147,6 @@ void i915_gem_suspend(struct drm_i915_private *i915)
* Assert that we successfully flushed all the work and
* reset the GPU back to its idle, low power state.
*/
- drain_delayed_work(>gem.retire_work);
GEM_BUG_ON(i915->gt.awake);
flush_work(>gem.idle_work);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index d919f512042c..9fd02025d382 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -58,7 +58,6 @@ static void mock_device_release(struct drm_device *dev)
i915_gem_contexts_lost(i915);
mutex_unlock(>drm.struct_mutex);
- drain_delayed_work(>gem.retire_work);
flush_work(>gem.idle_work);
i915_gem_drain_workqueue(i915);
--
2.20.1
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[Intel-gfx] [PATCH i-g-t 2/2] tests/i915_query: Engine discovery tests
From: Tvrtko Ursulin
Test the new engine discovery query.
Signed-off-by: Tvrtko Ursulin
---
tests/i915/i915_query.c | 247
1 file changed, 247 insertions(+)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 7d0c0e3a061c..ecbec3ae141d 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -483,6 +483,241 @@ test_query_topology_known_pci_ids(int fd, int devid)
free(topo_info);
}
+static bool query_engine_info_supported(int fd)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_ENGINE_INFO,
+ };
+
+ return __i915_query_items(fd, , 1) == 0 && item.length > 0;
+}
+
+static void engines_invalid(int fd)
+{
+ struct drm_i915_query_engine_info *engines;
+ struct drm_i915_query_item item;
+ unsigned int len;
+
+ /* Flags is MBZ. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.flags = 1;
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ /* Length not zero and not greater or equal required size. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = 1;
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ /* Query correct length. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ i915_query_items(fd, , 1);
+ igt_assert(item.length >= 0);
+ len = item.length;
+
+ engines = malloc(len);
+ igt_assert(engines);
+
+ /* Ivalid pointer. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EFAULT);
+
+ /* All fields in engines query are MBZ and only filled by the kernel. */
+
+ memset(engines, 0, len);
+ engines->num_engines = 1;
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ memset(engines, 0, len);
+ engines->rsvd[0] = 1;
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ memset(engines, 0, len);
+ engines->rsvd[1] = 1;
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ memset(engines, 0, len);
+ engines->rsvd[2] = 1;
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ free(engines);
+
+ igt_assert(len <= 4096);
+ engines = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON,
+ -1, 0);
+ igt_assert(engines != MAP_FAILED);
+
+ /* PROT_NONE is similar to unmapped area. */
+ memset(engines, 0, len);
+ igt_assert_eq(mprotect(engines, len, PROT_NONE), 0);
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EFAULT);
+ igt_assert_eq(mprotect(engines, len, PROT_WRITE), 0);
+
+ /* Read-only so kernel cannot fill the data back. */
+ memset(engines, 0, len);
+ igt_assert_eq(mprotect(engines, len, PROT_READ), 0);
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.length = len;
+ item.data_ptr = to_user_pointer(engines);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EFAULT);
+
+ munmap(engines, 4096);
+}
+
+static bool
+has_engine(struct drm_i915_query_engine_info *engines,
+ unsigned class, unsigned instance)
+{
+ unsigned int i;
+
+ for (i = 0; i < engines->num_engines; i++) {
+ struct drm_i915_engine_info *engine =
+ (struct drm_i915_engine_info *)>engines[i];
+
+ if (engine->engine.engine_class == class &&
+ engine->engine.engine_instance == instance)
+ return true;
+ }
+
+ return false;
+}
+
+static void engines(int fd)
+{
+ struct drm_i915_query_engine_info *engines;
+ struct drm_i915_query_item item;
+ unsigned int len, i;
+
+ engines =
[Intel-gfx] [PATCH i-g-t 1/2] headers: bump
From: Tvrtko Ursulin
Catch up to drm-tip headers.
Signed-off-by: Tvrtko Ursulin
---
include/drm-uapi/amdgpu_drm.h | 52 +-
include/drm-uapi/drm.h | 36 +++
include/drm-uapi/drm_mode.h | 4 +-
include/drm-uapi/i915_drm.h | 42
include/drm-uapi/lima_drm.h | 169
include/drm-uapi/msm_drm.h | 14 +++
include/drm-uapi/nouveau_drm.h | 51 ++
include/drm-uapi/panfrost_drm.h | 142 +++
include/drm-uapi/v3d_drm.h | 28 ++
9 files changed, 535 insertions(+), 3 deletions(-)
create mode 100644 include/drm-uapi/lima_drm.h
create mode 100644 include/drm-uapi/panfrost_drm.h
diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index be84e43c1e19..4788730dbe78 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -210,6 +210,9 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
/* indicate some job from this context once cause gpu hang */
#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
+/* indicate some errors are detected by RAS */
+#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
+#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
/* Context priority level */
#define AMDGPU_CTX_PRIORITY_UNSET -2048
@@ -272,13 +275,14 @@ union drm_amdgpu_vm {
/* sched ioctl */
#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
+#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
struct drm_amdgpu_sched_in {
/* AMDGPU_SCHED_OP_* */
__u32 op;
__u32 fd;
__s32 priority;
- __u32 flags;
+ __u32 ctx_id;
};
union drm_amdgpu_sched {
@@ -523,6 +527,9 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
+#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT0x08
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
@@ -565,6 +572,11 @@ union drm_amdgpu_cs {
* caches (L2/vL1/sL1/I$). */
#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
+/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
+ * This will reset wave ID counters for the IB.
+ */
+#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
+
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
@@ -598,6 +610,12 @@ struct drm_amdgpu_cs_chunk_sem {
__u32 handle;
};
+struct drm_amdgpu_cs_chunk_syncobj {
+ __u32 handle;
+ __u32 flags;
+ __u64 point;
+};
+
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD2
@@ -673,6 +691,7 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
/* Subquery id: Query DMCU firmware version */
#define AMDGPU_INFO_FW_DMCU 0x12
+ #define AMDGPU_INFO_FW_TA 0x13
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED0x0f
/* the used VRAM size */
@@ -726,6 +745,37 @@ struct drm_amdgpu_cs_chunk_data {
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
+/* query ras mask of enabled features*/
+#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
+
+/* RAS MASK: UMC (VRAM) */
+#define AMDGPU_INFO_RAS_ENABLED_UMC(1 << 0)
+/* RAS MASK: SDMA */
+#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
+/* RAS MASK: GFX */
+#define AMDGPU_INFO_RAS_ENABLED_GFX(1 << 2)
+/* RAS MASK: MMHUB */
+#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
+/* RAS MASK: ATHUB */
+#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
+/* RAS MASK: PCIE */
+#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
+/* RAS MASK: HDP */
+#define AMDGPU_INFO_RAS_ENABLED_HDP(1 << 6)
+/* RAS MASK: XGMI */
+#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
+/* RAS MASK: DF */
+#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
+/* RAS MASK: SMN */
+#define AMDGPU_INFO_RAS_ENABLED_SMN(1 << 9)
+/* RAS MASK: SEM */
+#define AMDGPU_INFO_RAS_ENABLED_SEM(1 << 10)
+/* RAS MASK: MP0 */
+#define AMDGPU_INFO_RAS_ENABLED_MP0(1 << 11)
+/* RAS MASK: MP1 */
+#define AMDGPU_INFO_RAS_ENABLED_MP1(1 << 12)
+/* RAS MASK: FUSE */
+#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h
index 85c685a2075e..c893f3b4a895
[Intel-gfx] [PATCH i-g-t 0/2] Engine discovery tests
From: Tvrtko Ursulin As usual, second patch is the only one to be looked at. Tvrtko Ursulin (2): headers: bump tests/i915_query: Engine discovery tests include/drm-uapi/amdgpu_drm.h | 52 ++- include/drm-uapi/drm.h | 36 + include/drm-uapi/drm_mode.h | 4 +- include/drm-uapi/i915_drm.h | 42 ++ include/drm-uapi/lima_drm.h | 169 ++ include/drm-uapi/msm_drm.h | 14 ++ include/drm-uapi/nouveau_drm.h | 51 +++ include/drm-uapi/panfrost_drm.h | 142 ++ include/drm-uapi/v3d_drm.h | 28 tests/i915/i915_query.c | 247 10 files changed, 782 insertions(+), 3 deletions(-) create mode 100644 include/drm-uapi/lima_drm.h create mode 100644 include/drm-uapi/panfrost_drm.h -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915/execlists: Flush the tasklet on parking
== Series Details == Series: series starting with [1/5] drm/i915/execlists: Flush the tasklet on parking URL : https://patchwork.freedesktop.org/series/60125/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6018_full -> Patchwork_12914_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12914_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12914_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12914_full: ### IGT changes ### Possible regressions * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-skl: NOTRUN -> [INCOMPLETE][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-skl7/igt@gem_fence_thr...@bo-write-verify-threaded-y.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-hsw: [PASS][2] -> [FAIL][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-hsw5/igt@gem_pp...@flink-and-close-vma-leak.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-hsw1/igt@gem_pp...@flink-and-close-vma-leak.html - shard-iclb: [PASS][4] -> [FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-iclb6/igt@gem_pp...@flink-and-close-vma-leak.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-iclb7/igt@gem_pp...@flink-and-close-vma-leak.html - shard-skl: [PASS][6] -> [FAIL][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl7/igt@gem_pp...@flink-and-close-vma-leak.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-skl5/igt@gem_pp...@flink-and-close-vma-leak.html * igt@i915_pm_rpm@cursor: - shard-iclb: [PASS][8] -> [DMESG-WARN][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-iclb7/igt@i915_pm_...@cursor.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-iclb8/igt@i915_pm_...@cursor.html * igt@kms_psr@primary_render: - shard-skl: [PASS][10] -> [INCOMPLETE][11] +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl10/igt@kms_psr@primary_render.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-skl7/igt@kms_psr@primary_render.html Known issues Here are the changes found in Patchwork_12914_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-iclb: [PASS][12] -> [INCOMPLETE][13] ([fdo#107713] / [fdo#109100]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-iclb2/igt@gem_fence_thr...@bo-write-verify-threaded-y.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-iclb4/igt@gem_fence_thr...@bo-write-verify-threaded-y.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([fdo#108566]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-apl4/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@drm-resources-equal: - shard-skl: [PASS][16] -> [SKIP][17] ([fdo#109271]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl2/igt@i915_pm_...@drm-resources-equal.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-skl6/igt@i915_pm_...@drm-resources-equal.html * igt@kms_cursor_crc@cursor-128x42-offscreen: - shard-iclb: [PASS][18] -> [INCOMPLETE][19] ([fdo#107713]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-iclb5/igt@kms_cursor_...@cursor-128x42-offscreen.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-iclb3/igt@kms_cursor_...@cursor-128x42-offscreen.html * igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled: - shard-skl: [PASS][20] -> [FAIL][21] ([fdo#103184] / [fdo#103232]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl10/igt@kms_draw_...@draw-method-xrgb2101010-render-xtiled.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12914/shard-skl4/igt@kms_draw_...@draw-method-xrgb2101010-render-xtiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: [PASS][22] -> [FAIL][23] ([fdo#103167]) +4 similar issues [22]:
Re: [Intel-gfx] [PATCH v11] drm/i915: Engine discovery query
Quoting Tvrtko Ursulin (2019-05-01 11:52:28)
> From: Tvrtko Ursulin
>
> Engine discovery query allows userspace to enumerate engines, probe their
> configuration features, all without needing to maintain the internal PCI
> ID based database.
>
> A new query for the generic i915 query ioctl is added named
> DRM_I915_QUERY_ENGINE_INFO, together with accompanying structure
> drm_i915_query_engine_info. The address of latter should be passed to the
> kernel in the query.data_ptr field, and should be large enough for the
> kernel to fill out all known engines as struct drm_i915_engine_info
> elements trailing the query.
>
> As with other queries, setting the item query length to zero allows
> userspace to query minimum required buffer size.
>
> Enumerated engines have common type mask which can be used to query all
> hardware engines, versus engines userspace can submit to using the execbuf
> uAPI.
>
> Engines also have capabilities which are per engine class namespace of
> bits describing features not present on all engine instances.
>
> v2:
> * Fixed HEVC assignment.
> * Reorder some fields, rename type to flags, increase width. (Lionel)
> * No need to allocate temporary storage if we do it engine by engine.
>(Lionel)
>
> v3:
> * Describe engine flags and mark mbz fields. (Lionel)
> * HEVC only applies to VCS.
>
> v4:
> * Squash SFC flag into main patch.
> * Tidy some comments.
>
> v5:
> * Add uabi_ prefix to engine capabilities. (Chris Wilson)
> * Report exact size of engine info array. (Chris Wilson)
> * Drop the engine flags. (Joonas Lahtinen)
> * Added some more reserved fields.
> * Move flags after class/instance.
>
> v6:
> * Do not check engine info array was zeroed by userspace but zero the
>unused fields for them instead.
>
> v7:
> * Simplify length calculation loop. (Lionel Landwerlin)
>
> v8:
> * Remove MBZ comments where not applicable.
> * Rename ABI flags to match engine class define naming.
> * Rename SFC ABI flag to reflect it applies to VCS and VECS.
> * SFC is wired to even _logical_ engine instances.
> * SFC applies to VCS and VECS.
> * HEVC is present on all instances on Gen11. (Tony)
> * Simplify length calculation even more. (Chris Wilson)
> * Move info_ptr assigment closer to loop for clarity. (Chris Wilson)
> * Use vdbox_sfc_access from runtime info.
> * Rebase for RUNTIME_INFO.
> * Refactor for lower indentation.
> * Rename uAPI class/instance to engine_class/instance to avoid C++
>keyword.
>
> v9:
> * Rebase for s/num_rings/num_engines/ in RUNTIME_INFO.
>
> v10:
> * Use new copy_query_item.
>
> v11:
> * Consolidate with struct i915_engine_class_instnace.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> Cc: Jon Bloomfield
> Cc: Dmitry Rogozhkin
> Cc: Lionel Landwerlin
> Cc: Joonas Lahtinen
> Cc: Tony Ye
> Reviewed-by: Lionel Landwerlin # v7
> Reviewed-by: Chris Wilson # v7
> ---
> +/**
> + * struct drm_i915_engine_info
> + *
> + * Describes one engine and it's capabilities as known to the driver.
> + */
> +struct drm_i915_engine_info {
> + /** Engine class and instance. */
> + struct i915_engine_class_instance engine;
> +
> + /** Reserved field. */
> + __u32 rsvd0;
> +
> + /** Engine flags. */
> + __u64 flags;
Do you think we could do something like
BUILD_BUG_ON(!IS_ALIGNED(offsetof(*info, flags), sizeof(info->flags));
Will that work, and worthwhile? Maybe work into a
BUILD_BUG_ON(check_user_alignment(info, flags));
Reviewed-by: Chris Wilson
-Chris
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move the engine->destroy() vfunc onto the engine
== Series Details == Series: drm/i915: Move the engine->destroy() vfunc onto the engine URL : https://patchwork.freedesktop.org/series/60147/ State : success == Summary == CI Bug Log - changes from CI_DRM_6020 -> Patchwork_12921 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60147/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12921 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [PASS][3] -> [INCOMPLETE][4] ([fdo#108602] / [fdo#108744]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html Possible fixes * igt@i915_selftest@live_hangcheck: - fi-bsw-kefka: [INCOMPLETE][5] -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 Participating hosts (53 -> 46) -- Additional (1): fi-pnv-d510 Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6020 -> Patchwork_12921 CI_DRM_6020: 087f11254b9a7a79156a88509afc4c1e2d640a7f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12921: c973cdaea5390bfb7afde3ce1df66accb9bf118f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c973cdaea539 drm/i915: Move the engine->destroy() vfunc onto the engine == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12921/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Engine discovery query (rev8)
== Series Details == Series: drm/i915: Engine discovery query (rev8) URL : https://patchwork.freedesktop.org/series/39958/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h AR drivers/gpu/drm/i915/built-in.a CC [M] drivers/gpu/drm/i915/header_test_i915_active_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_drv.o CC [M] drivers/gpu/drm/i915/header_test_i915_gem_context_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_gem_pm.o CC [M] drivers/gpu/drm/i915/header_test_i915_irq.o CC [M] drivers/gpu/drm/i915/header_test_i915_params.o CC [M] drivers/gpu/drm/i915/header_test_i915_priolist_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_reg.o CC [M] drivers/gpu/drm/i915/header_test_i915_scheduler_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_timeline_types.o CC [M] drivers/gpu/drm/i915/header_test_intel_atomic.o CC [M] drivers/gpu/drm/i915/header_test_intel_atomic_plane.o CC [M] drivers/gpu/drm/i915/header_test_intel_audio.o CC [M] drivers/gpu/drm/i915/header_test_intel_bios.o CC [M] drivers/gpu/drm/i915/header_test_intel_cdclk.o CC [M] drivers/gpu/drm/i915/header_test_intel_color.o CC [M] drivers/gpu/drm/i915/header_test_intel_combo_phy.o CC [M] drivers/gpu/drm/i915/header_test_intel_connector.o CC [M] drivers/gpu/drm/i915/header_test_intel_crt.o CC [M] drivers/gpu/drm/i915/header_test_intel_csr.o CC [M] drivers/gpu/drm/i915/header_test_intel_ddi.o CC [M] drivers/gpu/drm/i915/header_test_intel_dp.o CC [M] drivers/gpu/drm/i915/header_test_intel_dp_aux_backlight.o CC [M] drivers/gpu/drm/i915/header_test_intel_dp_link_training.o CC [M] drivers/gpu/drm/i915/header_test_intel_dp_mst.o CC [M] drivers/gpu/drm/i915/header_test_intel_dpll_mgr.o CC [M] drivers/gpu/drm/i915/header_test_intel_drv.o CC [M] drivers/gpu/drm/i915/header_test_intel_dsi.o CC [M] drivers/gpu/drm/i915/header_test_intel_dsi_dcs_backlight.o CC [M] drivers/gpu/drm/i915/header_test_intel_dvo.o CC [M] drivers/gpu/drm/i915/header_test_intel_dvo_dev.o CC [M] drivers/gpu/drm/i915/header_test_intel_fbc.o CC [M] drivers/gpu/drm/i915/header_test_intel_fbdev.o CC [M] drivers/gpu/drm/i915/header_test_intel_fifo_underrun.o CC [M] drivers/gpu/drm/i915/header_test_intel_frontbuffer.o CC [M] drivers/gpu/drm/i915/header_test_intel_hdcp.o CC [M] drivers/gpu/drm/i915/header_test_intel_hdmi.o CC [M] drivers/gpu/drm/i915/header_test_intel_hotplug.o CC [M] drivers/gpu/drm/i915/header_test_intel_lspcon.o CC [M] drivers/gpu/drm/i915/header_test_intel_lvds.o CC [M] drivers/gpu/drm/i915/header_test_intel_overlay.o CC [M] drivers/gpu/drm/i915/header_test_intel_panel.o CC [M] drivers/gpu/drm/i915/header_test_intel_pipe_crc.o CC [M] drivers/gpu/drm/i915/header_test_intel_pm.o CC [M] drivers/gpu/drm/i915/header_test_intel_psr.o CC [M] drivers/gpu/drm/i915/header_test_intel_quirks.o CC [M] drivers/gpu/drm/i915/header_test_intel_sdvo.o CC [M] drivers/gpu/drm/i915/header_test_intel_sideband.o CC [M] drivers/gpu/drm/i915/header_test_intel_sprite.o CC [M] drivers/gpu/drm/i915/header_test_intel_tv.o CC [M] drivers/gpu/drm/i915/header_test_intel_uncore.o CC [M] drivers/gpu/drm/i915/header_test_intel_vdsc.o CC [M] drivers/gpu/drm/i915/header_test_intel_wakeref.o CC [M] drivers/gpu/drm/i915/gt/intel_engine_cs.o drivers/gpu/drm/i915/gt/intel_engine_cs.c: In function ‘intel_engines_init_mmio’: drivers/gpu/drm/i915/gt/intel_engine_cs.c:437:34: error: ‘i915’ undeclared (first use in this function) intel_setup_engine_capabilities(i915); ^~~~ drivers/gpu/drm/i915/gt/intel_engine_cs.c:437:34: note: each undeclared identifier is reported only once for each function it appears in scripts/Makefile.build:275: recipe for target 'drivers/gpu/drm/i915/gt/intel_engine_cs.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/intel_engine_cs.o] Error 1 scripts/Makefile.build:486: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:486: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:486: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1051: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v11] drm/i915: Engine discovery query
From: Tvrtko Ursulin
Engine discovery query allows userspace to enumerate engines, probe their
configuration features, all without needing to maintain the internal PCI
ID based database.
A new query for the generic i915 query ioctl is added named
DRM_I915_QUERY_ENGINE_INFO, together with accompanying structure
drm_i915_query_engine_info. The address of latter should be passed to the
kernel in the query.data_ptr field, and should be large enough for the
kernel to fill out all known engines as struct drm_i915_engine_info
elements trailing the query.
As with other queries, setting the item query length to zero allows
userspace to query minimum required buffer size.
Enumerated engines have common type mask which can be used to query all
hardware engines, versus engines userspace can submit to using the execbuf
uAPI.
Engines also have capabilities which are per engine class namespace of
bits describing features not present on all engine instances.
v2:
* Fixed HEVC assignment.
* Reorder some fields, rename type to flags, increase width. (Lionel)
* No need to allocate temporary storage if we do it engine by engine.
(Lionel)
v3:
* Describe engine flags and mark mbz fields. (Lionel)
* HEVC only applies to VCS.
v4:
* Squash SFC flag into main patch.
* Tidy some comments.
v5:
* Add uabi_ prefix to engine capabilities. (Chris Wilson)
* Report exact size of engine info array. (Chris Wilson)
* Drop the engine flags. (Joonas Lahtinen)
* Added some more reserved fields.
* Move flags after class/instance.
v6:
* Do not check engine info array was zeroed by userspace but zero the
unused fields for them instead.
v7:
* Simplify length calculation loop. (Lionel Landwerlin)
v8:
* Remove MBZ comments where not applicable.
* Rename ABI flags to match engine class define naming.
* Rename SFC ABI flag to reflect it applies to VCS and VECS.
* SFC is wired to even _logical_ engine instances.
* SFC applies to VCS and VECS.
* HEVC is present on all instances on Gen11. (Tony)
* Simplify length calculation even more. (Chris Wilson)
* Move info_ptr assigment closer to loop for clarity. (Chris Wilson)
* Use vdbox_sfc_access from runtime info.
* Rebase for RUNTIME_INFO.
* Refactor for lower indentation.
* Rename uAPI class/instance to engine_class/instance to avoid C++
keyword.
v9:
* Rebase for s/num_rings/num_engines/ in RUNTIME_INFO.
v10:
* Use new copy_query_item.
v11:
* Consolidate with struct i915_engine_class_instnace.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Jon Bloomfield
Cc: Dmitry Rogozhkin
Cc: Lionel Landwerlin
Cc: Joonas Lahtinen
Cc: Tony Ye
Reviewed-by: Lionel Landwerlin # v7
Reviewed-by: Chris Wilson # v7
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 41
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +
drivers/gpu/drm/i915/i915_query.c| 49
include/uapi/drm/i915_drm.h | 42 +
4 files changed, 134 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f7308479d511..dc1df1e0a9c7 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -343,6 +343,45 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
return 0;
}
+static void __setup_engine_capabilities(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *i915 = engine->i915;
+
+ if (engine->class == VIDEO_DECODE_CLASS) {
+ /*
+* HEVC support is present on first engine instance
+* before Gen11 and on all instances afterwards.
+*/
+ if (INTEL_GEN(i915) >= 11 ||
+ (INTEL_GEN(i915) >= 9 && engine->instance == 0))
+ engine->uabi_capabilities |=
+ I915_VIDEO_CLASS_CAPABILITY_HEVC;
+
+ /*
+* SFC block is present only on even logical engine
+* instances.
+*/
+ if ((INTEL_GEN(i915) >= 11 &&
+RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||
+ (INTEL_GEN(i915) >= 9 && engine->instance == 0))
+ engine->uabi_capabilities |=
+ I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
+ } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
+ if (INTEL_GEN(i915) >= 9)
+ engine->uabi_capabilities |=
+ I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
+ }
+}
+
+static void intel_setup_engine_capabilities(struct drm_i915_private *i915)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, i915, id)
+ __setup_engine_capabilities(engine);
+}
+
/**
* intel_engines_init_mmio() - allocate and prepare the Engine Command
Streamers
* @dev_priv:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move the engine->destroy() vfunc onto the engine
== Series Details == Series: drm/i915: Move the engine->destroy() vfunc onto the engine URL : https://patchwork.freedesktop.org/series/60147/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Move the engine->destroy() vfunc onto the engine -drivers/gpu/drm/i915/selftests/../i915_drv.h:3454:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3448:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 38/45] drm/i915: Drop the deferred active reference
On Thu, 25 Apr 2019 at 10:20, Chris Wilson wrote: > > An old optimisation to reduce the number of atomics per batch sadly > relies on struct_mutex for coordination. In order to remove struct_mutex > from serialising object/context closing, always taking and releasing an > active reference on first use / last use greatly simplifies the locking. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915: Move the engine->destroy() vfunc onto the engine
Make the engine responsible for cleaning itself up!
This removes the i915->gt.cleanup vfunc that has been annoying the
casual reader and myself for the last several years, and helps keep a
future patch to add more cleanup tidy.
v2: Assert that engine->destroy is set after the backend starts
allocating its own state.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 4 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 68 +++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 51 +--
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 35 +-
drivers/gpu/drm/i915/i915_drv.h | 6 --
drivers/gpu/drm/i915/i915_gem.c | 19 +-
7 files changed, 77 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 3e53f53bc52b..f5b0f27cecb6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -362,7 +362,11 @@ __intel_ring_space(unsigned int head, unsigned int tail,
unsigned int size)
return (head - tail - CACHELINE_BYTES) & (size - 1);
}
+int intel_engines_init_mmio(struct drm_i915_private *i915);
int intel_engines_setup(struct drm_i915_private *i915);
+int intel_engines_init(struct drm_i915_private *i915);
+void intel_engines_cleanup(struct drm_i915_private *i915);
+
int intel_engine_init_common(struct intel_engine_cs *engine);
void intel_engine_cleanup_common(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f7308479d511..6e40f8ea9a6a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -319,6 +319,12 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
engine->class = info->class;
engine->instance = info->instance;
+ /*
+* To be overridden by the backend on setup. However to facilitate
+* cleanup on error during setup, we always provide the destroy vfunc.
+*/
+ engine->destroy = (typeof(engine->destroy))kfree;
+
engine->uabi_class = intel_engine_classes[info->class].uabi_class;
engine->context_size = __intel_engine_context_size(dev_priv,
@@ -343,18 +349,31 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
return 0;
}
+/**
+ * intel_engines_cleanup() - free the resources allocated for Command Streamers
+ * @i915: the i915 devic
+ */
+void intel_engines_cleanup(struct drm_i915_private *i915)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, i915, id) {
+ engine->destroy(engine);
+ i915->engine[id] = NULL;
+ }
+}
+
/**
* intel_engines_init_mmio() - allocate and prepare the Engine Command
Streamers
- * @dev_priv: i915 device private
+ * @i915: the i915 device
*
* Return: non-zero if the initialization failed.
*/
-int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
+int intel_engines_init_mmio(struct drm_i915_private *i915)
{
- struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
- const unsigned int engine_mask = INTEL_INFO(dev_priv)->engine_mask;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
+ struct intel_device_info *device_info = mkwrite_device_info(i915);
+ const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
unsigned int mask = 0;
unsigned int i;
int err;
@@ -367,10 +386,10 @@ int intel_engines_init_mmio(struct drm_i915_private
*dev_priv)
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
- if (!HAS_ENGINE(dev_priv, i))
+ if (!HAS_ENGINE(i915, i))
continue;
- err = intel_engine_setup(dev_priv, i);
+ err = intel_engine_setup(i915, i);
if (err)
goto cleanup;
@@ -386,20 +405,19 @@ int intel_engines_init_mmio(struct drm_i915_private
*dev_priv)
device_info->engine_mask = mask;
/* We always presume we have at least RCS available for later probing */
- if (WARN_ON(!HAS_ENGINE(dev_priv, RCS0))) {
+ if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
err = -ENODEV;
goto cleanup;
}
- RUNTIME_INFO(dev_priv)->num_engines = hweight32(mask);
+ RUNTIME_INFO(i915)->num_engines = hweight32(mask);
- i915_check_and_clear_faults(dev_priv);
+ i915_check_and_clear_faults(i915);
return 0;
cleanup:
- for_each_engine(engine, dev_priv, id)
- kfree(engine);
+ intel_engines_cleanup(i915);
return err;
}
@@ -413,7 +431,7 @@ int intel_engines_init(struct
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Drop the _INCOMPLETE for has_infoframe
== Series Details == Series: drm/i915: Drop the _INCOMPLETE for has_infoframe URL : https://patchwork.freedesktop.org/series/60120/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6018_full -> Patchwork_12913_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12913_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12913_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12913_full: ### IGT changes ### Possible regressions * igt@gem_fence_thrash@bo-write-verify-threaded-y: - shard-skl: NOTRUN -> [INCOMPLETE][1] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-skl2/igt@gem_fence_thr...@bo-write-verify-threaded-y.html * igt@kms_vblank@pipe-a-wait-busy: - shard-skl: [PASS][2] -> [INCOMPLETE][3] +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl4/igt@kms_vbl...@pipe-a-wait-busy.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-skl3/igt@kms_vbl...@pipe-a-wait-busy.html Known issues Here are the changes found in Patchwork_12913_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][4] -> [DMESG-WARN][5] ([fdo#108566]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-apl7/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@gem-evict-pwrite: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([fdo#107807]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl9/igt@i915_pm_...@gem-evict-pwrite.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-skl2/igt@i915_pm_...@gem-evict-pwrite.html * igt@i915_pm_rpm@gem-execbuf: - shard-hsw: [PASS][8] -> [INCOMPLETE][9] ([fdo#103540] / [fdo#107803] / [fdo#107807]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-hsw6/igt@i915_pm_...@gem-execbuf.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-hsw5/igt@i915_pm_...@gem-execbuf.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-skl: [PASS][10] -> [INCOMPLETE][11] ([fdo#104108] / [fdo#107773]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl1/igt@i915_susp...@fence-restore-tiled2untiled.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-skl5/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_color@pipe-b-ctm-negative: - shard-iclb: [PASS][12] -> [INCOMPLETE][13] ([fdo#107713]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-iclb8/igt@kms_co...@pipe-b-ctm-negative.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-iclb6/igt@kms_co...@pipe-b-ctm-negative.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#103167]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([fdo#106978]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-skl3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-msflip-blt.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-skl9/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-msflip-blt.html * igt@kms_plane@pixel-format-pipe-a-planes: - shard-glk: [PASS][18] -> [SKIP][19] ([fdo#109271]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-glk9/igt@kms_pl...@pixel-format-pipe-a-planes.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12913/shard-glk7/igt@kms_pl...@pixel-format-pipe-a-planes.html * igt@kms_plane_scaling@pipe-b-scaler-with-rotation: - shard-glk: [PASS][20] -> [SKIP][21] ([fdo#109271] / [fdo#109278]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6018/shard-glk9/igt@kms_plane_scal...@pipe-b-scaler-with-rotation.html [21]:
Re: [Intel-gfx] [PATCH] drm/i915: Introduce struct class_instance for engines across the uAPI
Quoting Rodrigo Vivi (2019-04-29 18:08:24)
> On Fri, Apr 12, 2019 at 07:51:47AM +0100, Chris Wilson wrote:
> > SSEU reprogramming of the context introduced the notion of engine class
> > and instance for a forwards compatible method of describing any engine
> > beyond the old execbuf interface. We wish to adopt this class:instance
> > description for more interfaces, so pull it out into a separate type for
> > userspace convenience.
> >
> > References: e46c2e99f600 ("drm/i915: Expose RPCS (SSEU) configuration to
> > userspace (Gen11 only)")
>
> I'm a bit confused here how/why this References become a Fixes.
It's required to make sure that the kernel was not released with
incompatible ABI.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hangcheck: Track context changes
== Series Details == Series: drm/i915/hangcheck: Track context changes URL : https://patchwork.freedesktop.org/series/60143/ State : success == Summary == CI Bug Log - changes from CI_DRM_6020 -> Patchwork_12920 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60143/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12920 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [PASS][1] -> [INCOMPLETE][2] ([fdo#108602] / [fdo#108744]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html - fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-icl-y/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/fi-icl-y/igt@i915_selftest@live_hangcheck.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-glk-dsi: [PASS][5] -> [FAIL][6] ([fdo#103191]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-glk-dsi/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/fi-glk-dsi/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html Possible fixes * igt@i915_selftest@live_hangcheck: - fi-bsw-kefka: [INCOMPLETE][7] -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 Participating hosts (53 -> 46) -- Additional (1): fi-pnv-d510 Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6020 -> Patchwork_12920 CI_DRM_6020: 087f11254b9a7a79156a88509afc4c1e2d640a7f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12920: 0dc7a3940822a55060bd58878bdd5644e854c2a1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0dc7a3940822 drm/i915/hangcheck: Track context changes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12920/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Complete both freed-object passes before draining the workqueue
== Series Details ==
Series: drm/i915: Complete both freed-object passes before draining the
workqueue
URL : https://patchwork.freedesktop.org/series/60142/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6020 -> Patchwork_12919
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/60142/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12919:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_basic@gtt-render:
- {fi-cml-u2}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-cml-u2/igt@gem_exec_ba...@gtt-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/fi-cml-u2/igt@gem_exec_ba...@gtt-render.html
Known issues
Here are the changes found in Patchwork_12919 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-icl-y/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/fi-icl-y/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@i915_selftest@live_hangcheck:
- fi-bsw-kefka: [INCOMPLETE][5] -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6020/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
Participating hosts (53 -> 46)
--
Additional (1): fi-pnv-d510
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6020 -> Patchwork_12919
CI_DRM_6020: 087f11254b9a7a79156a88509afc4c1e2d640a7f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4971: fc5e0467eb6913d21ad932aa8a31c77fdb5a9c77 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12919: c1388d9bba25cb0ed241fceda3a627cd4a8eccd3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c1388d9bba25 drm/i915: Complete both freed-object passes before draining the
workqueue
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12919/
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[Intel-gfx] [PATCH] drm/i915/hangcheck: Track context changes
Given sufficient preemption, we may see a busy system that doesn't
advance seqno while performing work across multiple contexts, and given
sufficient pathology not even notice a change in ACTHD. What does change
between the preempting contexts is their RING, so take note of that and
treat a change in the ring address as being an indication of forward
progress.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 12 +---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index d972c339309c..3b8d2f692bd5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -53,6 +53,7 @@ struct intel_instdone {
struct intel_engine_hangcheck {
u64 acthd;
+ u32 last_ring;
u32 last_seqno;
u32 next_seqno;
unsigned long action_timestamp;
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index e5eaa06fe74d..721ab74a382f 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -27,6 +27,7 @@
struct hangcheck {
u64 acthd;
+ u32 ring;
u32 seqno;
enum intel_engine_hangcheck_action action;
unsigned long action_timestamp;
@@ -134,6 +135,7 @@ static void hangcheck_load_sample(struct intel_engine_cs
*engine,
{
hc->acthd = intel_engine_get_active_head(engine);
hc->seqno = intel_engine_get_hangcheck_seqno(engine);
+ hc->ring = ENGINE_READ(engine, RING_START);
}
static void hangcheck_store_sample(struct intel_engine_cs *engine,
@@ -141,18 +143,22 @@ static void hangcheck_store_sample(struct intel_engine_cs
*engine,
{
engine->hangcheck.acthd = hc->acthd;
engine->hangcheck.last_seqno = hc->seqno;
+ engine->hangcheck.last_ring = hc->ring;
}
static enum intel_engine_hangcheck_action
hangcheck_get_action(struct intel_engine_cs *engine,
const struct hangcheck *hc)
{
- if (engine->hangcheck.last_seqno != hc->seqno)
- return ENGINE_ACTIVE_SEQNO;
-
if (intel_engine_is_idle(engine))
return ENGINE_IDLE;
+ if (engine->hangcheck.last_ring != hc->ring)
+ return ENGINE_ACTIVE_SEQNO;
+
+ if (engine->hangcheck.last_seqno != hc->seqno)
+ return ENGINE_ACTIVE_SEQNO;
+
return engine_stuck(engine, hc->acthd);
}
--
2.20.1
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[Intel-gfx] [PATCH] drm/i915: Complete both freed-object passes before draining the workqueue
The workqueue code complains viciously if we try to queue more work onto
the queue while attampting to drain it. As we asynchronously free
objects and defer their enqueuing with RCU, it is quite tricky to
quiesce the system before attempting to drain the workqueue. Yet drain
we must to ensure that the worker is idle before unloading the module.
Give the freed object drain 3 whole passes with multiple rcu_barrier()
to give the defer freeing of several levels each protected by RCU and
needing a grace period before its parent can be freed, ultimately
resulting in a GEM object being freed after another RCU period.
A consequence is that it will make module unload even slower.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110550
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 886a30243fe3..54258cb8ccee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2829,15 +2829,15 @@ static inline void i915_gem_drain_workqueue(struct
drm_i915_private *i915)
* grace period so that we catch work queued via RCU from the first
* pass. As neither drain_workqueue() nor flush_workqueue() report
* a result, we make an assumption that we only don't require more
-* than 2 passes to catch all recursive RCU delayed work.
+* than 3 passes to catch all _recursive_ RCU delayed work.
*
*/
- int pass = 2;
+ int pass = 3;
do {
rcu_barrier();
i915_gem_drain_freed_objects(i915);
- drain_workqueue(i915->wq);
} while (--pass);
+ drain_workqueue(i915->wq);
}
struct i915_vma * __must_check
--
2.20.1
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