[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/wopcm: update default size for gen11+
== Series Details ==
Series: drm/i915/wopcm: update default size for gen11+
URL : https://patchwork.freedesktop.org/series/61617/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6189_full -> Patchwork_13176_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_13176_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-suspend:
- shard-glk: [PASS][1] -> [FAIL][2] ([fdo#110667])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-glk3/igt@gem_...@in-flight-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-glk3/igt@gem_...@in-flight-suspend.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-skl8/igt@gem_soft...@noreloc-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-skl2/igt@gem_soft...@noreloc-s3.html
* igt@kms_flip@2x-plain-flip:
- shard-hsw: [PASS][5] -> [SKIP][6] ([fdo#109271]) +32 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-hsw2/igt@kms_f...@2x-plain-flip.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-hsw1/igt@kms_f...@2x-plain-flip.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-kbl: [PASS][7] -> [FAIL][8] ([fdo#102887] / [fdo#105363])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-kbl3/igt@kms_f...@flip-vs-expired-vblank.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-kbl3/igt@kms_f...@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-apl1/igt@kms_f...@flip-vs-suspend-interruptible.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-apl6/igt@kms_f...@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +2 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] /
[fdo#110403]) +1 similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
Possible fixes
* {igt@gem_ctx_param@vm}:
- shard-hsw: [DMESG-WARN][17] ([fdo#110836]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-hsw8/igt@gem_ctx_pa...@vm.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-hsw8/igt@gem_ctx_pa...@vm.html
* igt@gem_exec_schedule@in-order-vebox:
- shard-apl: [INCOMPLETE][19] ([fdo#103927]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-apl3/igt@gem_exec_sched...@in-order-vebox.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-apl6/igt@gem_exec_sched...@in-order-vebox.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] +2
similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-apl5/igt@i915_susp...@fence-restore-tiled2untiled.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-iclb: [FAIL][23] ([fdo#103833]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6189/shard-iclb2/igt@kms_fbcon_...@psr-suspend.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13176/shard-iclb6/igt@kms_fbcon_...@psr-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
- shard-hsw: [SKIP][25] ([fdo#109271]) -> [PASS][26] +39 similar
Re: [Intel-gfx] [PATCH] drm/i915: rename header test build commands to avoid conflicts
Hi, > -Original Message- > From: Jani Nikula [mailto:jani.nik...@intel.com] > Sent: Wednesday, June 05, 2019 10:22 PM > To: intel-gfx@lists.freedesktop.org > Cc: jani.nik...@intel.com; kbuild test robot ; Chris Wilson > ; Yamada, Masahiro/山田 真弘 > ; Sam Ravnborg > Subject: [PATCH] drm/i915: rename header test build commands to avoid > conflicts > > We have a local hack to test if headers are self-contained, while > upstreaming a proper generic solution in kbuild [1]. Now that both have > found themselves in linux-next, the identical cmd_header_test build > commands conflict, leading to errors such as: > > >> drivers/gpu/drm/i915/header_test_intel_audio.c:1:10: fatal error: > >> drivers/gpu/drm/i915/intel_audio.h: No such file or directory > #include "drivers/gpu/drm/i915/intel_audio.h" >^~~~ > > Rename the i915 local build command until the proper kbuild solution > finds its way to Linus' master and gets backported to our tree, and we > can finally switch over. > > Note that since the kbuild header test requires CONFIG_HEADER_TEST=y, > and our hack requires our debug option CONFIG_DRM_I915_WERROR=y, this is > likely hit only by build test bots. > > [1] http://marc.info/?i=20190604124248.5564-1-jani.nik...@intel.com > > Reported-by: kbuild test robot > Cc: Chris Wilson > Cc: Masahiro Yamada > Cc: Sam Ravnborg > Signed-off-by: Jani Nikula > --- This is not really queued up yet. So, we can squash fix-up to avoid 0day bot report. I attached two patches. 1-FIXUP1.patch is a one-liner fixup. If you want to clean up your Makefile by yourself later, I will squash it. If you want to switch to the generic notation now, I will squash 0001-FIXUP2.patch. Either is OK for me. Thanks. Masahiro Yamada 0001-FIXUP1.patch Description: 0001-FIXUP1.patch 0001-FIXUP2.patch Description: 0001-FIXUP2.patch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Kill INTEL_SUBPLATFORM_AML
This is the same as WHL, we added the AML separated just in case it
needed some different workaround or code path but looks like it don't
need at all.
Any objection with this change Rodrigo?
On Wed, 2019-06-05 at 19:29 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> All AML parts are either KBL ULX or CFL ULX so there is no point
> in keeping INTEL_SUBPLATFORM_AML around. As these are the only
> CFL ULX parts (normal CFL didn't have Y SKUs) so we'll just
> replace IS_AML_ULX with IS_CFL_ULX (it was already paired with
> IS_KBL_ULX which accounts for the other half of the AML parts).
>
> Cc: Tvrtko Ursulin
> Cc: José Roberto de Souza
> Cc: Rodrigo Vivi
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 ++---
> drivers/gpu/drm/i915/intel_ddi.c | 8 +---
> drivers/gpu/drm/i915/intel_device_info.c | 6 --
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> 4 files changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 89bf1e34feaa..16ea0e6077cf 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2213,9 +2213,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
> #define IS_KBL_ULX(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
> -#define IS_AML_ULX(dev_priv) \
> - (IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE,
> INTEL_SUBPLATFORM_AML) || \
> - IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE,
> INTEL_SUBPLATFORM_AML))
> #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
>INTEL_INFO(dev_priv)->gt == 2)
> #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
> @@ -2228,6 +2225,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
>INTEL_INFO(dev_priv)->gt == 3)
> #define IS_CFL_ULT(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE,
> INTEL_SUBPLATFORM_ULT)
> +#define IS_CFL_ULX(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE,
> INTEL_SUBPLATFORM_ULX)
> #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
>INTEL_INFO(dev_priv)->gt == 2)
> #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 350eaf54f01f..65c02b260c98 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -615,7 +615,7 @@ skl_get_buf_trans_dp(struct drm_i915_private
> *dev_priv, int *n_entries)
> static const struct ddi_buf_trans *
> kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int
> *n_entries)
> {
> - if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
> + if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
> *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
> return kbl_y_ddi_translations_dp;
> } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
> @@ -631,7 +631,8 @@ static const struct ddi_buf_trans *
> skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int
> *n_entries)
> {
> if (dev_priv->vbt.edp.low_vswing) {
> - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
> IS_AML_ULX(dev_priv)) {
> + if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
> + IS_CFL_ULX(dev_priv)) {
> *n_entries =
> ARRAY_SIZE(skl_y_ddi_translations_edp);
> return skl_y_ddi_translations_edp;
> } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)
> ||
> @@ -653,7 +654,8 @@ skl_get_buf_trans_edp(struct drm_i915_private
> *dev_priv, int *n_entries)
> static const struct ddi_buf_trans *
> skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int
> *n_entries)
> {
> - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
> IS_AML_ULX(dev_priv)) {
> + if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
> + IS_CFL_ULX(dev_priv)) {
> *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
> return skl_y_ddi_translations_hdmi;
> } else {
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 19437e8ec6fa..7135d8dc32a7 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -787,9 +787,6 @@ static const u16 subplatform_ulx_ids[] = {
> INTEL_SKL_ULX_GT2_IDS(0),
> INTEL_KBL_ULX_GT1_IDS(0),
> INTEL_KBL_ULX_GT2_IDS(0),
> -};
> -
> -static const u16 subplatform_aml_ids[] = {
> INTEL_AML_KBL_GT2_IDS(0),
> INTEL_AML_CFL_GT2_IDS(0),
> };
> @@ -832,9 +829,6 @@ void intel_device_info_subplatform_init(struct
> drm_i915_private *i915)
> /* ULX machines are also considered ULT. */
> mask |= BIT(INTEL_SUBPLATFO
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: protect against reading random memory
== Series Details ==
Series: drm/i915/dmc: protect against reading random memory
URL : https://patchwork.freedesktop.org/series/61695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6199 -> Patchwork_13187
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13187/
Known issues
Here are the changes found in Patchwork_13187 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13187/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108840])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13187/fi-icl-dsi/igt@i915_pm_...@module-reload.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-ilk-650: [DMESG-WARN][5] ([fdo#106387]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-ilk-650/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13187/fi-ilk-650/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_basic@basic-all:
- fi-icl-y: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-icl-y/igt@gem_exec_ba...@basic-all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13187/fi-icl-y/igt@gem_exec_ba...@basic-all.html
* igt@gem_exec_reloc@basic-gtt-read-noreloc:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read-noreloc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13187/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read-noreloc.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-snb-2600:[SKIP][11] ([fdo#109271]) -> [INCOMPLETE][12]
([fdo#105411])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-snb-2600/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13187/fi-snb-2600/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (51 -> 45)
--
Additional (2): fi-kbl-7500u fi-cml-u
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-kbl-7560u fi-byt-clapper fi-bdw-samus fi-kbl-r
Build changes
-
* Linux: CI_DRM_6199 -> Patchwork_13187
CI_DRM_6199: 3c7e356549a2286539d91f191196acd734b40729 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5041: 4f2b9f5930fa33d091cf89637dc6e7f76f632a88 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13187: 8417b00f5296d653ef19eebd87960b269ee801b8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8417b00f5296 drm/i915/dmc: protect against reading random memory
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13187/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/ehl: Add support for DPLL4 (v6)
== Series Details == Series: drm/i915/ehl: Add support for DPLL4 (v6) URL : https://patchwork.freedesktop.org/series/61696/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/header_test_intel_dpll_mgr.o In file included from drivers/gpu/drm/i915/header_test_intel_dpll_mgr.c:1:0: drivers/gpu/drm/i915/intel_dpll_mgr.h:319:2: error: unknown type name ‘intel_wakeref_t’ intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; ^~~ drivers/gpu/drm/i915/intel_dpll_mgr.h:319:27: error: ‘POWER_DOMAIN_NUM’ undeclared here (not in a function) intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; ^~~~ scripts/Makefile.build:278: recipe for target 'drivers/gpu/drm/i915/header_test_intel_dpll_mgr.o' failed make[4]: *** [drivers/gpu/drm/i915/header_test_intel_dpll_mgr.o] Error 1 scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:489: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1071: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v6)
This patch adds support for DPLL4 on EHL that include the
following restrictions:
- DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
DPLL4 can be used with other DDIs, including DDID
(combo port A external usage).
- DPLL4 cannot be enabled when DC5 or DC6 are enabled.
- The DPLL4 enable, lock, power enabled, and power state are connected
to the MGPLL1_ENABLE register.
v2: (suggestions from Bob Paauwe)
- Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
iterate twice: once for Combo plls and once for MG plls.
- Use MG pll funcs for DPLL4 instead of creating new ones and modify
mg_pll_enable to include the restrictions for EHL.
v3: Fix compilation error
v4: (suggestions from Lucas and Ville)
- Treat DPLL4 as a combo phy PLL and not as MG PLL
- Disable DC states when this DPLL is being enabled
- Reuse icl_get_dpll instead of creating a separate one for EHL
v5: (suggestion from Ville)
- Refcount the DC OFF power domains during the enabling and disabling
of this DPLL.
v6: rebase
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/i915/intel_display_power.c | 20 +++
drivers/gpu/drm/i915/intel_display_power.h | 6
drivers/gpu/drm/i915/intel_dpll_mgr.c | 40 +++---
drivers/gpu/drm/i915/intel_dpll_mgr.h | 5 +++
4 files changed, 67 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display_power.c
b/drivers/gpu/drm/i915/intel_display_power.c
index 278a7edc94f5..fd6d0d6a285a 100644
--- a/drivers/gpu/drm/i915/intel_display_power.c
+++ b/drivers/gpu/drm/i915/intel_display_power.c
@@ -4524,6 +4524,26 @@ void intel_power_domains_resume(struct drm_i915_private
*i915)
intel_power_domains_verify_state(i915);
}
+void icl_disable_dc_states(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ enum intel_display_power_domain domain;
+
+ for_each_power_domain(domain, ICL_DISPLAY_DC_OFF_POWER_DOMAINS)
+ pll->wakerefs[domain] = intel_display_power_get(dev_priv,
+ domain);
+}
+
+void icl_enable_dc_states(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ enum intel_display_power_domain domain;
+
+ for_each_power_domain(domain, ICL_DISPLAY_DC_OFF_POWER_DOMAINS)
+ intel_display_power_put(dev_priv, domain,
+ pll->wakerefs[domain]);
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
static void intel_power_domains_dump_info(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/intel_display_power.h
b/drivers/gpu/drm/i915/intel_display_power.h
index ff57b0a7fe59..2abaa3806ec6 100644
--- a/drivers/gpu/drm/i915/intel_display_power.h
+++ b/drivers/gpu/drm/i915/intel_display_power.h
@@ -12,6 +12,7 @@
struct drm_i915_private;
struct intel_encoder;
+struct intel_shared_dpll;
enum intel_display_power_domain {
POWER_DOMAIN_DISPLAY_CORE,
@@ -285,4 +286,9 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override);
+void icl_disable_dc_states(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll);
+void icl_enable_dc_states(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll);
+
#endif /* __INTEL_DISPLAY_POWER_H__ */
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 69787f259677..2829b37e2909 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -22,8 +22,8 @@
*/
#include "intel_dpio_phy.h"
-#include "intel_dpll_mgr.h"
#include "intel_drv.h"
+#include "intel_dpll_mgr.h"
/**
* DOC: Display PLLs
@@ -2806,6 +2806,12 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
if (intel_port_is_combophy(dev_priv, port)) {
min = DPLL_ID_ICL_DPLL0;
max = DPLL_ID_ICL_DPLL1;
+
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ max = DPLL_ID_EHL_DPLL4;
+ }
+
ret = icl_calc_dpll_state(crtc_state, encoder);
} else if (intel_port_is_tc(dev_priv, port)) {
if (encoder->type == INTEL_OUTPUT_DP_MST) {
@@ -2945,8 +2951,14 @@ static bool combo_pll_get_hw_state(struct
drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- return icl_pll_get_hw_state(dev_priv, pll, hw_state,
- CNL_DPLL_ENABLE(pll->info->id));
+ i915_reg_t
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: protect against reading random memory
== Series Details == Series: drm/i915/dmc: protect against reading random memory URL : https://patchwork.freedesktop.org/series/61695/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8417b00f5296 drm/i915/dmc: protect against reading random memory -:23: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #23: i915 :00:02.0: Failed to load DMC firmware i915/icl_dmc_ver1_07.bin. Disabling runtime power management. total: 0 errors, 1 warnings, 0 checks, 46 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Do not touch the PCH SSC reference if a PLL is using it
== Series Details == Series: series starting with [1/5] drm/i915: Do not touch the PCH SSC reference if a PLL is using it URL : https://patchwork.freedesktop.org/series/61608/ State : success == Summary == CI Bug Log - changes from CI_DRM_6188_full -> Patchwork_13174_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13174_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][1] -> [FAIL][2] ([fdo#102887] / [fdo#105363]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-glk6/igt@kms_f...@flip-vs-expired-vblank.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-glk1/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip_tiling@flip-y-tiled: - shard-iclb: [PASS][3] -> [FAIL][4] ([fdo#108303]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-iclb2/igt@kms_flip_til...@flip-y-tiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-iclb6/igt@kms_flip_til...@flip-y-tiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#103167]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-render.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move: - shard-hsw: [PASS][7] -> [SKIP][8] ([fdo#109271]) +10 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-hsw2/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-move.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-move.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-skl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-skl5/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-iclb7/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-iclb3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109642]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-iclb2/igt@kms_psr2_su@page_flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-iclb5/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-iclb2/igt@kms_psr@psr2_cursor_render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-iclb6/igt@kms_psr@psr2_cursor_render.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-apl5/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-apl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible fixes * igt@kms_atomic_interruptible@universal-setplane-primary: - shard-iclb: [INCOMPLETE][21] ([fdo#107713]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-iclb7/igt@kms_atomic_interrupti...@universal-setplane-primary.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13174/shard-iclb3/igt@kms_atomic_interrupti...@universal-setplane-primary.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [INCOMPLETE][23] ([fdo#110741]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6188/shard-skl3/igt@kms_cursor_...@pipe-b-c
[Intel-gfx] [PATCH] drm/i915/dmc: protect against reading random memory
While loading the DMC firmware we were double checking the headers made
sense, but in no place we checked that we were actually reading memory
we were supposed to. This could be wrong in case the firmware file is
truncated or malformed.
Before this patch:
# ls -l /lib/firmware/i915/icl_dmc_ver1_07.bin
-rw-r--r-- 1 root root 25716 Feb 1 12:26 icl_dmc_ver1_07.bin
# truncate -s 25700 /lib/firmware/i915/icl_dmc_ver1_07.bin
# modprobe i915
# dmesg| grep -i dmc
[drm:intel_csr_ucode_init [i915]] Loading i915/icl_dmc_ver1_07.bin
[drm] Finished loading DMC firmware i915/icl_dmc_ver1_07.bin (v1.7)
i.e. it loads random data. Now it fails like below:
[drm:intel_csr_ucode_init [i915]] Loading i915/icl_dmc_ver1_07.bin
[drm:csr_load_work_fn [i915]] *ERROR* Truncated DMC firmware, rejecting.
i915 :00:02.0: Failed to load DMC firmware
i915/icl_dmc_ver1_07.bin. Disabling runtime power management.
i915 :00:02.0: DMC firmware homepage:
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915
Before reading any part of the firmware file, validate the input first.
Fixes: eb805623d8b1 ("drm/i915/skl: Add support to load SKL CSR firmware.")
Cc: sta...@vger.kernel.org
Signed-off-by: Lucas De Marchi
---
This has been extracted from the bigger series
https://patchwork.freedesktop.org/series/61016/ in a way that can be
propagated to stable.
drivers/gpu/drm/i915/intel_csr.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 4527b9662330..bf0eebd385b9 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -303,10 +303,17 @@ static u32 *parse_csr_fw(struct drm_i915_private
*dev_priv,
u32 dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
u32 i;
u32 *dmc_payload;
+ size_t fsize;
if (!fw)
return NULL;
+ fsize = sizeof(struct intel_css_header) +
+ sizeof(struct intel_package_header) +
+ sizeof(struct intel_dmc_header);
+ if (fsize > fw->size)
+ goto error_truncated;
+
/* Extract CSS Header information*/
css_header = (struct intel_css_header *)fw->data;
if (sizeof(struct intel_css_header) !=
@@ -366,6 +373,9 @@ static u32 *parse_csr_fw(struct drm_i915_private *dev_priv,
/* Convert dmc_offset into number of bytes. By default it is in dwords*/
dmc_offset *= 4;
readcount += dmc_offset;
+ fsize += dmc_offset;
+ if (fsize > fw->size)
+ goto error_truncated;
/* Extract dmc_header information. */
dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
@@ -397,6 +407,10 @@ static u32 *parse_csr_fw(struct drm_i915_private *dev_priv,
/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
nbytes = dmc_header->fw_size * 4;
+ fsize += nbytes;
+ if (fsize > fw->size)
+ goto error_truncated;
+
if (nbytes > csr->max_fw_size) {
DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
return NULL;
@@ -410,6 +424,10 @@ static u32 *parse_csr_fw(struct drm_i915_private *dev_priv,
}
return memcpy(dmc_payload, &fw->data[readcount], nbytes);
+
+error_truncated:
+ DRM_ERROR("Truncated DMC firmware, rejecting.\n");
+ return NULL;
}
static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
--
2.21.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Enable SSC for ICL using panel_use_ssc
== Series Details ==
Series: drm/i915/icl: Enable SSC for ICL using panel_use_ssc
URL : https://patchwork.freedesktop.org/series/61692/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6199 -> Patchwork_13186
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13186/
Known issues
Here are the changes found in Patchwork_13186 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries:
- fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#110566])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-cml-u2/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13186/fi-cml-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_mmap_gtt@basic-wc:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-icl-u3/igt@gem_mmap_...@basic-wc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13186/fi-icl-u3/igt@gem_mmap_...@basic-wc.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] /
[fdo#108569])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13186/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-ilk-650: [DMESG-WARN][7] ([fdo#106387]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-ilk-650/igt@debugfs_test@read_all_entries.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13186/fi-ilk-650/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_basic@basic-all:
- fi-icl-y: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-icl-y/igt@gem_exec_ba...@basic-all.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13186/fi-icl-y/igt@gem_exec_ba...@basic-all.html
* igt@gem_exec_reloc@basic-gtt-read-noreloc:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read-noreloc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13186/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read-noreloc.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-dsi: [INCOMPLETE][13] ([fdo#107713] / [fdo#108569]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6199/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13186/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
Participating hosts (51 -> 45)
--
Additional (2): fi-kbl-7500u fi-cml-u
Missing(8): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6199 -> Patchwork_13186
CI_DRM_6199: 3c7e356549a2286539d91f191196acd734b40729 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5041: 4f2b9f5930fa33d091cf89637dc6e7f76f632a88 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13186: 2bbb59c67ab3183759aed3728064cd45fc2caaeb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2bbb59c67ab3 drm/i915/icl: Enable SSC for ICL using panel_use_ssc
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13186/
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Enable SSC for ICL using panel_use_ssc
== Series Details ==
Series: drm/i915/icl: Enable SSC for ICL using panel_use_ssc
URL : https://patchwork.freedesktop.org/series/61692/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2bbb59c67ab3 drm/i915/icl: Enable SSC for ICL using panel_use_ssc
-:44: WARNING:BRACES: braces {} are not necessary for single statement blocks
#44: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2530:
+ if (intel_panel_use_ssc(dev_priv)) {
+ cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
+ }
-:59: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#59: FILE: drivers/gpu/drm/i915/intel_drv.h:1505:
}
+static inline bool
-:65: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the
previous line
#65: FILE: drivers/gpu/drm/i915/intel_drv.h:1511:
+ return dev_priv->vbt.lvds_use_ssc
+ && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
total: 0 errors, 1 warnings, 2 checks, 38 lines checked
___
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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Support HBR3 on EHL combo PHY
On Wed, Jun 05, 2019 at 02:51:08PM -0700, Manasi Navare wrote: > On Wed, Jun 05, 2019 at 02:18:32PM -0700, Matt Roper wrote: > > Unlike ICL, EHL's combo PHYs can support HBR3 data rates. Note that > > this just extends the upper limit; we will continue to honor the max > > data rate specified in the VBT in cases where it is lower than HBR3. > > > > Signed-off-by: Matt Roper > > Yes looks good to me. > > Reviewed-by: Manasi Navare > > Manasi Thanks for the quick review. CI looks happy too, so pushed to dinq. Matt > > > --- > > drivers/gpu/drm/i915/intel_dp.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > b/drivers/gpu/drm/i915/intel_dp.c > > index 24b56b2a76c8..b099a9dc28fd 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -332,6 +332,7 @@ static int icl_max_source_rate(struct intel_dp > > *intel_dp) > > enum port port = dig_port->base.port; > > > > if (intel_port_is_combophy(dev_priv, port) && > > + !IS_ELKHARTLAKE(dev_priv) && > > !intel_dp_is_edp(intel_dp)) > > return 54; > > > > -- > > 2.14.5 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Support HBR3 on EHL combo PHY
== Series Details ==
Series: drm/i915/ehl: Support HBR3 on EHL combo PHY
URL : https://patchwork.freedesktop.org/series/61690/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6198 -> Patchwork_13185
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13185/
Known issues
Here are the changes found in Patchwork_13185 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6198/fi-icl-u3/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13185/fi-icl-u3/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6198/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13185/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][5] -> [FAIL][6] ([fdo#110627])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6198/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13185/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@core_auth@basic-auth:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +2
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6198/fi-icl-u3/igt@core_a...@basic-auth.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13185/fi-icl-u3/igt@core_a...@basic-auth.html
* igt@gem_ctx_switch@basic-default:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6198/fi-icl-guc/igt@gem_ctx_swi...@basic-default.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13185/fi-icl-guc/igt@gem_ctx_swi...@basic-default.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][11] ([fdo#103167]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6198/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13185/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
Participating hosts (52 -> 46)
--
Additional (1): fi-icl-dsi
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6198 -> Patchwork_13185
CI_DRM_6198: 5550e8de34053c54224724c876cda34db56fc15c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5041: 4f2b9f5930fa33d091cf89637dc6e7f76f632a88 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13185: 3288b87377675b05d743dee4cf458ba48e6f3e54 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3288b8737767 drm/i915/ehl: Support HBR3 on EHL combo PHY
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13185/
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/icl: Enable SSC for ICL using panel_use_ssc
To enable SSC for DPLL, we need to set the bit DPLL_CFGCR0_SSC_ENABLE_ICL
while configuring cfgcr0 register. This bit should be set only when we
are enabling SSC using kernel mod parameter panel_use_ssc.
Also, moving intel_panel_use_ssc() declaration to intel_drv.h.
Signed-off-by: Aditya Swarup
Cc: Lucas De Marchi
Cc: Clinton Taylor
Cc: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 8
drivers/gpu/drm/i915/intel_dpll_mgr.c | 4
drivers/gpu/drm/i915/intel_drv.h | 8
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 012ad08f38c3..34c82a17ab1b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7377,14 +7377,6 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
constant_n);
}
-static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
-{
- if (i915_modparams.panel_use_ssc >= 0)
- return i915_modparams.panel_use_ssc != 0;
- return dev_priv->vbt.lvds_use_ssc
- && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
-}
-
static u32 pnv_dpll_compute_fp(struct dpll *dpll)
{
return (1 << dpll->n) << 16 | dpll->m2;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 897d93537414..6c460fb81d6a 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2527,6 +2527,10 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
*crtc_state,
cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
pll_params.dco_integer;
+ if (intel_panel_use_ssc(dev_priv)) {
+ cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
+ }
+
cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
DPLL_CFGCR1_KDIV(pll_params.kdiv) |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 270f5bb43d9b..e9af27e841b3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1497,6 +1497,14 @@ intel_wait_for_vblank(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
drm_wait_one_vblank(&dev_priv->drm, pipe);
}
+static inline bool
+intel_panel_use_ssc(struct drm_i915_private *dev_priv)
+{
+ if (i915_modparams.panel_use_ssc >= 0)
+ return i915_modparams.panel_use_ssc != 0;
+ return dev_priv->vbt.lvds_use_ssc
+ && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
+}
static inline void
intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
{
--
2.17.1
___
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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Support HBR3 on EHL combo PHY
On Wed, Jun 05, 2019 at 02:18:32PM -0700, Matt Roper wrote: > Unlike ICL, EHL's combo PHYs can support HBR3 data rates. Note that > this just extends the upper limit; we will continue to honor the max > data rate specified in the VBT in cases where it is lower than HBR3. > > Signed-off-by: Matt Roper Yes looks good to me. Reviewed-by: Manasi Navare Manasi > --- > drivers/gpu/drm/i915/intel_dp.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 24b56b2a76c8..b099a9dc28fd 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -332,6 +332,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp) > enum port port = dig_port->base.port; > > if (intel_port_is_combophy(dev_priv, port) && > + !IS_ELKHARTLAKE(dev_priv) && > !intel_dp_is_edp(intel_dp)) > return 54; > > -- > 2.14.5 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/ehl: Support HBR3 on EHL combo PHY
Unlike ICL, EHL's combo PHYs can support HBR3 data rates. Note that this just extends the upper limit; we will continue to honor the max data rate specified in the VBT in cases where it is lower than HBR3. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_dp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 24b56b2a76c8..b099a9dc28fd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -332,6 +332,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp) enum port port = dig_port->base.port; if (intel_port_is_combophy(dev_priv, port) && + !IS_ELKHARTLAKE(dev_priv) && !intel_dp_is_edp(intel_dp)) return 54; -- 2.14.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-fixes
Hi Da.*, Our slow release cycle continues, only 2 contributors since last time! The set from Helen avoids blocking in async commits and Lucas ensures the sg list is unmapped with the udmabuf. drm-misc-fixes-2019-06-05: - Allow fb changes in async commits (fixes igt failures) (Helen) - Actually unmap the scatterlist when unmapping udmabuf (Lucas) Cc: Lucas Stach Cc: Helen Koike Cheers, Sean The following changes since commit 2a3e0b716296a504d9e65fea7acb379c86fe4283: Merge tag 'imx-drm-fixes-2019-05-29' of git://git.pengutronix.de/git/pza/linux into drm-fixes (2019-05-31 09:15:25 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2019-06-05 for you to fetch changes up to 283f1e383e91d96fe652fad549537ae15cf31d60: udmabuf: actually unmap the scatterlist (2019-06-05 10:41:17 +0200) - Allow fb changes in async commits (fixes igt failures) (Helen) - Actually unmap the scatterlist when unmapping udmabuf (Lucas) Cc: Lucas Stach Cc: Helen Koike Helen Koike (5): drm/rockchip: fix fb references in async update drm/amd: fix fb references in async update drm/msm: fix fb references in async update drm/vc4: fix fb references in async update drm: don't block fb changes for async plane updates Lucas Stach (1): udmabuf: actually unmap the scatterlist drivers/dma-buf/udmabuf.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +- drivers/gpu/drm/drm_atomic_helper.c | 22 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c| 4 ++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 51 --- drivers/gpu/drm/vc4/vc4_plane.c | 2 +- include/drm/drm_modeset_helper_vtables.h | 8 7 files changed, 53 insertions(+), 38 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_create: Do not build create-clear for MIPS
On 03/04/2019 08:25, Guillaume Tucker wrote:
> On 02/04/2019 09:35, Petri Latvala wrote:
>> On Mon, Apr 01, 2019 at 04:39:24PM +0200, Guillaume Tucker wrote:
>>> The MIPS architecture doesn't provide the hardware atomics that are
>>> required for the "create-clear" sub-test such as
>>> __sync_add_and_fetch(). As a simple and pragmatic solution, disable
>>> this sub-test when building for MIPS. A better approach would be to
>>> add a fallback implementation for these operations.
>>>
>>> Fixes: 6727e17c00b2 ("i915/gem_create: Verify that all new objects are
>>> clear")
>>> Signed-off-by: Guillaume Tucker
>>> ---
>>> tests/i915/gem_create.c | 4
>>> 1 file changed, 4 insertions(+)
>>>
>>> diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
>>> index 2a861ca8a7ec..8a48496e6c19 100644
>>> --- a/tests/i915/gem_create.c
>>> +++ b/tests/i915/gem_create.c
>>> @@ -142,6 +142,7 @@ static void invalid_nonaligned_size(int fd)
>>> gem_close(fd, handle);
>>> }
>>>
>>> +#if !defined(__mips__) /* MIPS doesn't provide the required hardware
>>> atomics */
>>> static uint64_t get_npages(uint64_t *global, uint64_t npages)
>>> {
>>> uint64_t try, old, max;
>>> @@ -208,6 +209,7 @@ static void always_clear(int i915, int timeout)
>>> for (int i = 0; i < ncpus; i++)
>>> pthread_join(thread[i], NULL);
>>> }
>>> +#endif /* !defined(__mips__) */
>>>
>>> igt_main
>>> {
>>> @@ -231,6 +233,8 @@ igt_main
>>> igt_subtest("create-invalid-nonaligned")
>>> invalid_nonaligned_size(fd);
>>>
>>> +#if !defined(__mips__)
>>> igt_subtest("create-clear")
>>> always_clear(fd, 30);
>>> +#endif
>>> }
>>
>>
>> It's a bit ugly. I wonder how much work a fallback mechanism would be?
>
> Sorry I should have sent this as RFC.
>
>> The test is i915 specific and using those on non-x86 architectures
>> sounds silly. We could limit building tests/i915/* only if
>> host_machine.cpu_family() is x86 or x86_64. But that requires
>> revisiting this issue if ever the day comes when i915 can be used on
>> other architectures *cough*.
>
> Right, I thought it might not be worth implementing fallback
> functions if there is no MIPS hardware on which this test can be
> run. Still it would be a shame to leave i-g-t failing to build
> on MIPS.
>
>> Apropos, compile-testing on MIPS in gitlab-CI?
>
> This issue was actually hit while building the KernelCI root file
> system with i-g-t tests. We're starting to add some MIPS
> platforms, so running the generic DRM/KMS tests on them might
> start to make sense at some point (cc khilman).
>
> And yes I guess it seems worth considering adding MIPS to
> Gitlab-CI as it only appears to be covering x86, armhf and
> arm64 (although I did fix an armhf build issue a few weeks ago).
>
>> A compile-tested-only fallback mechanism suggestion, and a bad spot
>> for placing the fallback functions:
>
> Thanks, I agree that does look like a sustainable way forward.
> We don't quite have a MIPS platform to test that yet in KernelCI,
> so hopefully QEMU can be used to test a fallback implementation.
>
> I guess adding placeholder functions as in your example with
> igt_assert_f() statements would just add some technical debt with
> little added benefit, so I'll work on a v2 with something that
> works. Meanwhile we'll just skip i-g-t KernelCI builds on MIPS.
>
>> diff --git a/meson.build b/meson.build
>> index 557400a5..0552e858 100644
>> --- a/meson.build
>> +++ b/meson.build
>> @@ -246,6 +246,9 @@ endif
>> have = cc.has_function('memfd_create', prefix : '''#include
>> ''', args : '-D_GNU_SOURCE')
>> config.set10('HAVE_MEMFD_CREATE', have)
>>
>> +have_atomics = cc.compiles('void f() { int x, y; __sync_add_and_fetch(&x,
>> y); }')
>> +config.set10('HAVE_BUILTIN_ATOMICS', have_atomics)
>> +
>> add_project_arguments('-D_GNU_SOURCE', language : 'c')
>> add_project_arguments('-include', 'config.h', language : 'c')
>>
>> diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
>> index 2a861ca8..615bb475 100644
>> --- a/tests/i915/gem_create.c
>> +++ b/tests/i915/gem_create.c
>> @@ -62,6 +62,18 @@ IGT_TEST_DESCRIPTION("This is a test for the extended &
>> old gem_create ioctl,"
>> " that includes allocation of object from stolen memory"
>> " and shmem.");
>>
>> +#if !HAVE_BUILTIN_ATOMICS
>> +int __sync_add_and_fetch(void *ptr, uint64_t val)
>> +{
>> + igt_assert_f(false, "Don't have builtin atomics\n");
>> +}
>> +
>> +int __sync_val_compare_and_swap(void *ptr, uint64_t old, uint64_t new)
>> +{
>> + igt_assert_f(false, "Don't have builtin atomics\n");
>> +}
>> +#endif
>> +
>> #define CLEAR(s) memset(&s, 0, sizeof(s))
>> #define PAGE_SIZE 4096
Just to close this thread, I sent some patches earlier this week
to fix the build on MIPS using the more recent __atomic_*
functions from libatomic as they do have the 64-bit
implementations for MIPS that were missing for the __sync_*
functions (tested w
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/crc-debugfs: User irqsafe spinlock in drm_crtc_add_crc_entry
== Series Details ==
Series: drm/crc-debugfs: User irqsafe spinlock in drm_crtc_add_crc_entry
URL : https://patchwork.freedesktop.org/series/61687/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6197 -> Patchwork_13184
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13184/
Known issues
Here are the changes found in Patchwork_13184 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6197/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13184/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
Possible fixes
* igt@gem_basic@bad-close:
- {fi-icl-guc}: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6197/fi-icl-guc/igt@gem_ba...@bad-close.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13184/fi-icl-guc/igt@gem_ba...@bad-close.html
* igt@gem_ctx_create@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6197/fi-icl-u3/igt@gem_ctx_cre...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13184/fi-icl-u3/igt@gem_ctx_cre...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
Participating hosts (53 -> 46)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6197 -> Patchwork_13184
CI_DRM_6197: 68289d6c8db69b6b6571f191b85b7658bf69c3ee @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5041: 4f2b9f5930fa33d091cf89637dc6e7f76f632a88 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13184: 91ba38231fc18cbb9afdf22a9ba105a44ed8448b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
91ba38231fc1 drm/crc-debugfs: User irqsafe spinlock in drm_crtc_add_crc_entry
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13184/
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] gitlab-ci: add build for MIPS
Add Docker image and Gitlab CI steps to run builds for the MIPS architecture using Debian Buster. Signed-off-by: Guillaume Tucker --- .gitlab-ci.yml | 28 Dockerfile.debian-mips | 38 ++ meson-cross-mips.txt | 12 3 files changed, 78 insertions(+) create mode 100644 Dockerfile.debian-mips create mode 100644 meson-cross-mips.txt diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 771143a9ea95..e390f8f472d5 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -90,6 +90,17 @@ build:tests-debian-meson-arm64: paths: - build +build:tests-debian-meson-mips: + image: $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-mips:latest + stage: build + script: +- export PKG_CONFIG_PATH=/usr/lib/mips-linux-gnu/pkgconfig/ +- meson --cross-file meson-cross-mips.txt build +- ninja -C build + artifacts: +paths: + - build + build:tests-debian-autotools: image: $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian:latest stage: build @@ -221,6 +232,23 @@ containers:igt-debian-arm64: - docker build -t $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-arm64 -f Dockerfile.debian-arm64 . - docker push $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-arm64 +containers:igt-debian-mips: + stage: containers + image: docker:stable + only: +changes: + - Dockerfile.debian-mips + - .gitlab-ci.yml + services: +- docker:dind + variables: +DOCKER_HOST: tcp://docker:2375 +DOCKER_DRIVER: overlay2 + script: +- docker login -u gitlab-ci-token -p $CI_JOB_TOKEN $CI_REGISTRY +- docker build -t $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-mips -f Dockerfile.debian-mips . +- docker push $CI_REGISTRY/$CI_PROJECT_PATH/igt-debian-mips + containers:igt-fedora: stage: containers image: docker:stable diff --git a/Dockerfile.debian-mips b/Dockerfile.debian-mips new file mode 100644 index ..2612b7b148e3 --- /dev/null +++ b/Dockerfile.debian-mips @@ -0,0 +1,38 @@ +FROM debian:buster + +RUN apt-get update +RUN apt-get install -y \ + flex \ + bison \ + pkg-config \ + x11proto-dri2-dev \ + python-docutils \ + valgrind \ + peg + +RUN dpkg --add-architecture mips +RUN apt-get update +RUN apt-get install -y \ + gcc-mips-linux-gnu \ + libpciaccess-dev:mips \ + libkmod-dev:mips \ + libprocps-dev:mips \ + libunwind-dev:mips \ + libdw-dev:mips \ + zlib1g-dev:mips \ + liblzma-dev:mips \ + libcairo-dev:mips \ + libpixman-1-dev:mips \ + libudev-dev:mips \ + libgsl-dev:mips \ + libasound2-dev:mips \ + libjson-c-dev:mips \ + libcurl4-openssl-dev:mips \ + libxrandr-dev:mips \ + libxv-dev:mips + +RUN apt-get install -y \ + meson \ + libdrm-dev:mips \ + qemu-user \ + qemu-user-static diff --git a/meson-cross-mips.txt b/meson-cross-mips.txt new file mode 100644 index ..6350d677e0bc --- /dev/null +++ b/meson-cross-mips.txt @@ -0,0 +1,12 @@ +[binaries] +c = '/usr/bin/mips-linux-gnu-gcc' +ar = '/usr/bin/mips-linux-gnu-gcc-ar' +strip = '/usr/bin/mips-linux-gnu-strip' +pkgconfig = 'pkg-config' +exe_wrapper = 'qemu-mips' + +[host_machine] +system = 'linux' +cpu_family = 'mips' +cpu = 'mips' +endian = 'big' -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/crc-debugfs: User irqsafe spinlock in drm_crtc_add_crc_entry
== Series Details == Series: drm/crc-debugfs: User irqsafe spinlock in drm_crtc_add_crc_entry URL : https://patchwork.freedesktop.org/series/61687/ State : warning == Summary == $ dim checkpatch origin/drm-tip 91ba38231fc1 drm/crc-debugfs: User irqsafe spinlock in drm_crtc_add_crc_entry -:41: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 18 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Don't check uv_wm in skl_plane_wm_equals() (rev2)
== Series Details ==
Series: drm/i915: Don't check uv_wm in skl_plane_wm_equals() (rev2)
URL : https://patchwork.freedesktop.org/series/58281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6187_full -> Patchwork_13173_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_13173_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_engines@independent}:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-glk3/igt@gem_ctx_engi...@independent.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-glk8/igt@gem_ctx_engi...@independent.html
Known issues
Here are the changes found in Patchwork_13173_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-apl7/igt@gem_ctx_isolat...@bcs0-s3.html
* igt@gem_mmap_gtt@forked-medium-copy-odd:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb4/igt@gem_mmap_...@forked-medium-copy-odd.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-iclb5/igt@gem_mmap_...@forked-medium-copy-odd.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][7] -> [FAIL][8] ([fdo#105767])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: [PASS][9] -> [FAIL][10] ([fdo#106509] / [fdo#107409])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-glk7/igt@kms_cursor_leg...@2x-nonblocking-modeset-vs-cursor-atomic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-glk3/igt@kms_cursor_leg...@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109349])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-iclb3/igt@kms_dp_...@basic-dsc-enable-edp.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
- shard-hsw: [PASS][13] -> [SKIP][14] ([fdo#109271]) +32 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw5/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-hsw1/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-skl6/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][21] -> [FAIL][22] ([fdo#99912])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-kbl1/igt@kms_setm...@basic.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13173/shard-kbl7/igt@kms_setm...@basic.html
Possible fixes
* {igt@gem_ctx_param@vm}:
- shard-hsw: [DMESG-WARN][23] ([fdo#110836]) ->
[Intel-gfx] [PATCH] drm/crc-debugfs: User irqsafe spinlock in drm_crtc_add_crc_entry
We can be called from any context, we need to be prepared.
Noticed this while hacking on vkms, which calls this function from a
normal worker. Which really upsets lockdep.
Cc: Rodrigo Siqueira
Cc: Tomeu Vizoso
Cc: Emil Velikov
Cc: Benjamin Gaignard
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_debugfs_crc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_debugfs_crc.c
b/drivers/gpu/drm/drm_debugfs_crc.c
index 585169f0dcc5..7f35b5ba1924 100644
--- a/drivers/gpu/drm/drm_debugfs_crc.c
+++ b/drivers/gpu/drm/drm_debugfs_crc.c
@@ -396,8 +396,9 @@ int drm_crtc_add_crc_entry(struct drm_crtc *crtc, bool
has_frame,
struct drm_crtc_crc *crc = &crtc->crc;
struct drm_crtc_crc_entry *entry;
int head, tail;
+ unsigned long flags;
- spin_lock(&crc->lock);
+ spin_lock_irqsave(&crc->lock, flags);
/* Caller may not have noticed yet that userspace has stopped reading */
if (!crc->entries) {
@@ -428,7 +429,7 @@ int drm_crtc_add_crc_entry(struct drm_crtc *crtc, bool
has_frame,
head = (head + 1) & (DRM_CRC_ENTRIES_NR - 1);
crc->head = head;
- spin_unlock(&crc->lock);
+ spin_unlock_irqrestore(&crc->lock, flags);
wake_up_interruptible(&crc->wq);
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/ehl: Add support for DPLL4 (v5)
== Series Details == Series: drm/i915/ehl: Add support for DPLL4 (v5) URL : https://patchwork.freedesktop.org/series/61684/ State : failure == Summary == Applying: drm/i915/ehl: Add support for DPLL4 (v5) .git/rebase-apply/patch:146: new blank line at EOF. + warning: 1 line adds whitespace errors. Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_dpll_mgr.c M drivers/gpu/drm/i915/intel_dpll_mgr.h M drivers/gpu/drm/i915/intel_runtime_pm.c M drivers/gpu/drm/i915/intel_runtime_pm.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_runtime_pm.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_runtime_pm.h Auto-merging drivers/gpu/drm/i915/intel_runtime_pm.c Auto-merging drivers/gpu/drm/i915/intel_dpll_mgr.h Auto-merging drivers/gpu/drm/i915/intel_dpll_mgr.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/ehl: Add support for DPLL4 (v5) When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
== Series Details == Series: series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function URL : https://patchwork.freedesktop.org/series/61679/ State : success == Summary == CI Bug Log - changes from CI_DRM_6196 -> Patchwork_13182 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/ Known issues Here are the changes found in Patchwork_13182 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_evict: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([fdo#107709]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-bsw-kefka/igt@i915_selftest@live_evict.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-bsw-kefka/igt@i915_selftest@live_evict.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-dsi: [PASS][3] -> [FAIL][4] ([fdo#103167]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-flip: - fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-icl-u3/igt@prime_v...@basic-fence-flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-icl-u3/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [FAIL][7] ([fdo#108511]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@kms_addfb_basic@basic: - fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-icl-u3/igt@kms_addfb_ba...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-icl-u3/igt@kms_addfb_ba...@basic.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [DMESG-WARN][11] ([fdo#102614]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 Participating hosts (52 -> 46) -- Additional (1): fi-cfl-guc Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6196 -> Patchwork_13182 CI_DRM_6196: 7a984cf09665b9ef4c63e82a8551bdde5da229ae @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5040: f190ab5dcd3fa52f4b47bc28c01bcfbbdc26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13182: 9787f959f37c9f3324dfae43e4c2f0080a553f73 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9787f959f37c drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3) c48843171c41 drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2) e5829ea35195 drm/i915/dsi: Move logging of DSI VBT parameters to a helper function == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13182/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Replace struct_mutex serialisation for allocation (rev2)
== Series Details == Series: drm/i915/gtt: Replace struct_mutex serialisation for allocation (rev2) URL : https://patchwork.freedesktop.org/series/61533/ State : success == Summary == CI Bug Log - changes from CI_DRM_6187_full -> Patchwork_13172_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13172_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109349]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-iclb5/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite: - shard-hsw: [PASS][3] -> [SKIP][4] ([fdo#109271]) +25 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw4/igt@kms_frontbuffer_track...@fbc-2p-primscrn-cur-indfb-draw-pwrite.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-primscrn-cur-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#103167]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-shrfb-fliptrack.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-shrfb-fliptrack.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108145] / [fdo#110403]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109441]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_setmode@basic: - shard-apl: [PASS][11] -> [FAIL][12] ([fdo#99912]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-apl3/igt@kms_setm...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-apl2/igt@kms_setm...@basic.html - shard-kbl: [PASS][13] -> [FAIL][14] ([fdo#99912]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-kbl1/igt@kms_setm...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-kbl7/igt@kms_setm...@basic.html * igt@kms_sysfs_edid_timing: - shard-hsw: [PASS][15] -> [FAIL][16] ([fdo#100047]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw4/igt@kms_sysfs_edid_timing.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-hsw1/igt@kms_sysfs_edid_timing.html Possible fixes * igt@gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][17] ([fdo#104108]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-skl5/igt@gem_soft...@noreloc-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-skl8/igt@gem_soft...@noreloc-s3.html * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-hsw: [INCOMPLETE][19] ([fdo#103540]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw4/igt@kms_b...@extended-modeset-hang-newfb-render-a.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-hsw2/igt@kms_b...@extended-modeset-hang-newfb-render-a.html * igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-snb: [SKIP][21] ([fdo#109271]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-snb7/igt@kms_draw_...@draw-method-xrgb2101010-blt-untiled.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-snb6/igt@kms_draw_...@draw-method-xrgb2101010-blt-untiled.html * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible: - shard-hsw: [SKIP][23] ([fdo#109271]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw1/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13172/shard-hsw6/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: [FAIL][25] ([fdo#1
[Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v5)
This patch adds support for DPLL4 on EHL that include the
following restrictions:
- DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
DPLL4 can be used with other DDIs, including DDID
(combo port A external usage).
- DPLL4 cannot be enabled when DC5 or DC6 are enabled.
- The DPLL4 enable, lock, power enabled, and power state are connected
to the MGPLL1_ENABLE register.
v2: (suggestions from Bob Paauwe)
- Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
iterate twice: once for Combo plls and once for MG plls.
- Use MG pll funcs for DPLL4 instead of creating new ones and modify
mg_pll_enable to include the restrictions for EHL.
v3: Fix compilation error
v4: (suggestions from Lucas and Ville)
- Treat DPLL4 as a combo phy PLL and not as MG PLL
- Disable DC states when this DPLL is being enabled
- Reuse icl_get_dpll instead of creating a separate one for EHL
v5: (suggestion from Ville)
- Refcount the DC OFF power domains during the enabling and disabling
of this DPLL.
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 40 ++---
drivers/gpu/drm/i915/intel_dpll_mgr.h | 5
drivers/gpu/drm/i915/intel_runtime_pm.c | 21 +
drivers/gpu/drm/i915/intel_runtime_pm.h | 5
4 files changed, 67 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 897d93537414..6d89d231b33d 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -22,8 +22,8 @@
*/
#include "intel_dpio_phy.h"
-#include "intel_dpll_mgr.h"
#include "intel_drv.h"
+#include "intel_dpll_mgr.h"
/**
* DOC: Display PLLs
@@ -2806,6 +2806,12 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
if (intel_port_is_combophy(dev_priv, port)) {
min = DPLL_ID_ICL_DPLL0;
max = DPLL_ID_ICL_DPLL1;
+
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ max = DPLL_ID_EHL_DPLL4;
+ }
+
ret = icl_calc_dpll_state(crtc_state, encoder);
} else if (intel_port_is_tc(dev_priv, port)) {
if (encoder->type == INTEL_OUTPUT_DP_MST) {
@@ -2945,8 +2951,14 @@ static bool combo_pll_get_hw_state(struct
drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- return icl_pll_get_hw_state(dev_priv, pll, hw_state,
- CNL_DPLL_ENABLE(pll->info->id));
+ i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+
+ if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ enable_reg = MG_PLL_ENABLE(0);
+ }
+
+ return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
}
static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -3057,6 +3069,14 @@ static void combo_pll_enable(struct drm_i915_private
*dev_priv,
{
i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ enable_reg = MG_PLL_ENABLE(0);
+
+ /* Need to disable DC states when this DPLL is enabled. */
+ icl_disable_dc_states(dev_priv, pll);
+ }
+
icl_pll_power_enable(dev_priv, pll, enable_reg);
icl_dpll_write(dev_priv, pll);
@@ -3152,7 +3172,18 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
+ i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+
+ if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ enable_reg = MG_PLL_ENABLE(0);
+ icl_pll_disable(dev_priv, pll, enable_reg);
+
+ icl_enable_dc_states(dev_priv, pll);
+ return;
+ }
+
+ icl_pll_disable(dev_priv, pll, enable_reg);
}
static void tbt_pll_disable(struct drm_i915_private *dev_priv,
@@ -3230,6 +3261,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
static const struct dpll_info ehl_plls[] = {
{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
{ },
};
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 8835dd20f1d2..5a70134f539f 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -117,6 +117,10 @@ enum
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2)
On Wed, Jun 05, 2019 at 08:17:34PM +0200, Hans de Goede wrote:
> The vlv/icl_dphy_param_init calls do various calculations to set dphy
> parameters based on the pclk.
>
> Move the calling of vlv/icl_dphy_param_init to vlv_dsi_init to give
> vlv_dsi_init a chance to tweak the pclk before these calculations are done.
>
> Changes in v2:
> -Also moves the icl and vlv specific dphy_param_init functions from the
> generic intel_dsi_vbt.c file into the icl_ and vlv_dsi.c specific files.
>
> Note icl_dphy_param_init() and vlv_dphy_param_init() are only moved,
> otherwise they are completely unchanged.
>
> Signed-off-by: Hans de Goede
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 108 ++
> drivers/gpu/drm/i915/intel_dsi.h | 1 +
> drivers/gpu/drm/i915/intel_dsi_vbt.c | 282 +--
> drivers/gpu/drm/i915/vlv_dsi.c | 170
> 4 files changed, 280 insertions(+), 281 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 9d962ea1e635..511c76e788ef 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1363,6 +1363,113 @@ static const struct mipi_dsi_host_ops
> gen11_dsi_host_ops = {
> .transfer = gen11_dsi_host_transfer,
> };
>
> +#define ICL_PREPARE_CNT_MAX 0x7
> +#define ICL_CLK_ZERO_CNT_MAX 0xf
> +#define ICL_TRAIL_CNT_MAX0x7
> +#define ICL_TCLK_PRE_CNT_MAX 0x3
> +#define ICL_TCLK_POST_CNT_MAX0x7
> +#define ICL_HS_ZERO_CNT_MAX 0xf
> +#define ICL_EXIT_ZERO_CNT_MAX0x7
> +
> +static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> +{
> + struct drm_device *dev = intel_dsi->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> + u32 tlpx_ns;
> + u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> + u32 ths_prepare_ns, tclk_trail_ns;
> + u32 hs_zero_cnt;
> + u32 tclk_pre_cnt, tclk_post_cnt;
> +
> + tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
> +
> + tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> + ths_prepare_ns = max(mipi_config->ths_prepare,
> + mipi_config->tclk_prepare);
> +
> + /*
> + * prepare cnt in escape clocks
> + * this field represents a hexadecimal value with a precision
> + * of 1.2 – i.e. the most significant bit is the integer
> + * and the least significant 2 bits are fraction bits.
> + * so, the field can represent a range of 0.25 to 1.75
> + */
> + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
> + if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
> + DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
> + prepare_cnt = ICL_PREPARE_CNT_MAX;
> + }
> +
> + /* clk zero count in escape clocks */
> + clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
> + ths_prepare_ns, tlpx_ns);
> + if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
> + DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
> + clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
> + }
> +
> + /* trail cnt in escape clocks*/
> + trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
> + if (trail_cnt > ICL_TRAIL_CNT_MAX) {
> + DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
> + trail_cnt = ICL_TRAIL_CNT_MAX;
> + }
> +
> + /* tclk pre count in escape clocks */
> + tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
> + if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
> + DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
> + tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
> + }
> +
> + /* tclk post count in escape clocks */
> + tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
> + if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
> + DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n",
> tclk_post_cnt);
> + tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
> + }
> +
> + /* hs zero cnt in escape clocks */
> + hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
> +ths_prepare_ns, tlpx_ns);
> + if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
> + DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
> + hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
> + }
> +
> + /* hs exit zero cnt in escape clocks */
> + exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
> + if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
> + DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n",
> exit_zero_cnt);
> + exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
> + }
> +
> + /* clock lane dphy timings */
> + intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
> +CLK_PREPARE(
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
== Series Details == Series: series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function URL : https://patchwork.freedesktop.org/series/61679/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/dsi: Move logging of DSI VBT parameters to a helper function Okay! Commit: drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2) +drivers/gpu/drm/i915/icl_dsi.c:1404:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/icl_dsi.c:1404:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/icl_dsi.c:1405:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/icl_dsi.c:1405:26: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:599:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:599:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:600:26: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:600:26: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:737:26: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:737:26: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:779:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:779:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:811:37: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:811:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/vlv_dsi.c:1731:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/vlv_dsi.c:1731:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/vlv_dsi.c:1773:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/vlv_dsi.c:1773:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/vlv_dsi.c:1805:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/vlv_dsi.c:1805:37: warning: expression using sizeof(void) Commit: drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3) Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
== Series Details ==
Series: series starting with [1/3] drm/i915/dsi: Move logging of DSI VBT
parameters to a helper function
URL : https://patchwork.freedesktop.org/series/61679/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e5829ea35195 drm/i915/dsi: Move logging of DSI VBT parameters to a helper
function
-:59: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#59: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:575:
+ DRM_DEBUG_KMS("BTA %s\n",
+ enableddisabled(!(intel_dsi->video_frmt_cfg_bits &
DISABLE_VIDEO_BTA)));
total: 0 errors, 0 warnings, 1 checks, 101 lines checked
c48843171c41 drm/i915/dsi: Move vlv/icl_dphy_param_init call out of
intel_dsi_vbt_init (v2)
-:552: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#552: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1743:
+ exit_zero_cnt = DIV_ROUND_UP(
-:572: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#572: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1763:
+ clk_zero_cnt = DIV_ROUND_UP(
-:608: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#608: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1799:
+* The comment above does not match with the code */
-:627: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#627: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1818:
+ DIV_ROUND_UP(
-:643: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#643: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1834:
+ DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
+ 8);
total: 0 errors, 1 warnings, 4 checks, 614 lines checked
9787f959f37c drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3)
___
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Re: [Intel-gfx] [PATCH] drm/i915/wopcm: update default size for gen11+
On Wed, 05 Jun 2019 20:21:54 +0200, Daniele Ceraolo Spurio
wrote:
On 6/5/19 7:51 AM, Michal Wajdeczko wrote:
On Wed, 05 Jun 2019 01:15:29 +0200, Daniele Ceraolo Spurio
wrote:
The size has been increased to 2MB starting from gen11. GuC and HuC FWs
nit: s/gen11/Gen11
fit in 1MB so we were fine even with the legacy define, but let's still
move to the correct one before the blobs grow to avoid being caught off
guard in the future.
Bspec: 44982
I think for ICL this should be 12690
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_wopcm.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f82a415ea2ba..6cb993eea206 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -41,8 +41,9 @@
* context).
*/
-/* Default WOPCM size 1MB. */
-#define GEN9_WOPCM_SIZE(1024 * 1024)
+/* Default WOPCM size is 2MB from gen11, 1MB on previous platforms */
nit: s/gen11/Gen11
+#define GEN11_WOPCM_SIZE(SZ_2M)
+#define GEN9_WOPCM_SIZE(SZ_1M)
/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
#define WOPCM_RESERVED_SIZE(16 * 1024)
@@ -71,7 +72,10 @@
*/
void intel_wopcm_init_early(struct intel_wopcm *wopcm)
{
-wopcm->size = GEN9_WOPCM_SIZE;
+if (INTEL_GEN(wopcm_to_i915(wopcm)) >= 11)
+wopcm->size = GEN11_WOPCM_SIZE;
+else
+wopcm->size = GEN9_WOPCM_SIZE;
While here, maybe we should not try to setup WOPCM size on pre-Gen9
platforms ? Then we can drop below log if WOPCM is zero/not available.
Are you ok if I just return early if !HAS_GUC(), to make it not
gen-specific?
That's even better (and aligned with other intel_wopcm_init functions)
Thanks,
Michal
Daniele
DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
}
With above,
Reviewed-by: Michal Wajdeczko
___
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Re: [Intel-gfx] [PATCH] drm/i915/wopcm: update default size for gen11+
On 6/5/19 7:51 AM, Michal Wajdeczko wrote:
On Wed, 05 Jun 2019 01:15:29 +0200, Daniele Ceraolo Spurio
wrote:
The size has been increased to 2MB starting from gen11. GuC and HuC FWs
nit: s/gen11/Gen11
fit in 1MB so we were fine even with the legacy define, but let's still
move to the correct one before the blobs grow to avoid being caught off
guard in the future.
Bspec: 44982
I think for ICL this should be 12690
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_wopcm.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f82a415ea2ba..6cb993eea206 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -41,8 +41,9 @@
* context).
*/
-/* Default WOPCM size 1MB. */
-#define GEN9_WOPCM_SIZE (1024 * 1024)
+/* Default WOPCM size is 2MB from gen11, 1MB on previous platforms */
nit: s/gen11/Gen11
+#define GEN11_WOPCM_SIZE (SZ_2M)
+#define GEN9_WOPCM_SIZE (SZ_1M)
/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
#define WOPCM_RESERVED_SIZE (16 * 1024)
@@ -71,7 +72,10 @@
*/
void intel_wopcm_init_early(struct intel_wopcm *wopcm)
{
- wopcm->size = GEN9_WOPCM_SIZE;
+ if (INTEL_GEN(wopcm_to_i915(wopcm)) >= 11)
+ wopcm->size = GEN11_WOPCM_SIZE;
+ else
+ wopcm->size = GEN9_WOPCM_SIZE;
While here, maybe we should not try to setup WOPCM size on pre-Gen9
platforms ? Then we can drop below log if WOPCM is zero/not available.
Are you ok if I just return early if !HAS_GUC(), to make it not
gen-specific?
Daniele
DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
}
With above,
Reviewed-by: Michal Wajdeczko
___
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[Intel-gfx] [PATCH 2/3] drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2)
The vlv/icl_dphy_param_init calls do various calculations to set dphy
parameters based on the pclk.
Move the calling of vlv/icl_dphy_param_init to vlv_dsi_init to give
vlv_dsi_init a chance to tweak the pclk before these calculations are done.
Changes in v2:
-Also moves the icl and vlv specific dphy_param_init functions from the
generic intel_dsi_vbt.c file into the icl_ and vlv_dsi.c specific files.
Note icl_dphy_param_init() and vlv_dphy_param_init() are only moved,
otherwise they are completely unchanged.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/icl_dsi.c | 108 ++
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 282 +--
drivers/gpu/drm/i915/vlv_dsi.c | 170
4 files changed, 280 insertions(+), 281 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9d962ea1e635..511c76e788ef 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1363,6 +1363,113 @@ static const struct mipi_dsi_host_ops
gen11_dsi_host_ops = {
.transfer = gen11_dsi_host_transfer,
};
+#define ICL_PREPARE_CNT_MAX0x7
+#define ICL_CLK_ZERO_CNT_MAX 0xf
+#define ICL_TRAIL_CNT_MAX 0x7
+#define ICL_TCLK_PRE_CNT_MAX 0x3
+#define ICL_TCLK_POST_CNT_MAX 0x7
+#define ICL_HS_ZERO_CNT_MAX0xf
+#define ICL_EXIT_ZERO_CNT_MAX 0x7
+
+static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
+{
+ struct drm_device *dev = intel_dsi->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+ u32 tlpx_ns;
+ u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
+ u32 ths_prepare_ns, tclk_trail_ns;
+ u32 hs_zero_cnt;
+ u32 tclk_pre_cnt, tclk_post_cnt;
+
+ tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
+
+ tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
+ ths_prepare_ns = max(mipi_config->ths_prepare,
+mipi_config->tclk_prepare);
+
+ /*
+* prepare cnt in escape clocks
+* this field represents a hexadecimal value with a precision
+* of 1.2 – i.e. the most significant bit is the integer
+* and the least significant 2 bits are fraction bits.
+* so, the field can represent a range of 0.25 to 1.75
+*/
+ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
+ if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
+ DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt);
+ prepare_cnt = ICL_PREPARE_CNT_MAX;
+ }
+
+ /* clk zero count in escape clocks */
+ clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
+ ths_prepare_ns, tlpx_ns);
+ if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
+ DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
+ clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
+ }
+
+ /* trail cnt in escape clocks*/
+ trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
+ if (trail_cnt > ICL_TRAIL_CNT_MAX) {
+ DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt);
+ trail_cnt = ICL_TRAIL_CNT_MAX;
+ }
+
+ /* tclk pre count in escape clocks */
+ tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
+ if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
+ DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
+ tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
+ }
+
+ /* tclk post count in escape clocks */
+ tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
+ if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
+ DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n",
tclk_post_cnt);
+ tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
+ }
+
+ /* hs zero cnt in escape clocks */
+ hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
+ ths_prepare_ns, tlpx_ns);
+ if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
+ DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt);
+ hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
+ }
+
+ /* hs exit zero cnt in escape clocks */
+ exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
+ if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
+ DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n",
exit_zero_cnt);
+ exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
+ }
+
+ /* clock lane dphy timings */
+ intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
+ CLK_PREPARE(prepare_cnt) |
+ CLK_ZERO_OVERRIDE |
+ CLK_ZERO(clk_zero_cnt) |
+ CLK_PRE_OVERRIDE |
+
[Intel-gfx] [PATCH 3/3] drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3)
The GOP sometimes initializes the pclk at a (slightly) different frequency
then the pclk which we've calculated.
This commit makes the DSI code read-back the pclk set by the GOP and
if that is within a reasonable margin of the calculated pclk, uses
that instead.
This fixes the first modeset being a full modeset instead of a
fast modeset on systems where the GOP pclk is different.
Changes in v2:
-Use intel_encoder_current_mode() to get the pclk setup by the GOP
Changes in v3:
-Back to the readback approach, skipping the dsi_pll.ctrl / .dev checks
in intel_pipe_config_compare() when adjust is set leads to:
[drm:pipe_config_err [i915]] *ERROR* mismatch in dsi_pll.ctrl (...)
[drm:pipe_config_err [i915]] *ERROR* mismatch in dsi_pll.div (...)
-Do the readback and pclk overriding from vlv_dsi_init(), rather then from
intel_dsi_vbt_init() as the vbt code should not be touching the hw
Reviewed-by: Ville Syrjälä
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/vlv_dsi.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index 59500c838b9d..6d96891984a5 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -1865,7 +1865,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
struct drm_encoder *encoder;
struct intel_connector *intel_connector;
struct drm_connector *connector;
- struct drm_display_mode *fixed_mode;
+ struct drm_display_mode *current_mode, *fixed_mode;
enum port port;
DRM_DEBUG_KMS("\n");
@@ -1909,6 +1909,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_encoder->port = port;
+ intel_encoder->type = INTEL_OUTPUT_DSI;
+ intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
+ intel_encoder->cloneable = 0;
/*
* On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
@@ -1946,6 +1949,20 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
goto err;
}
+ /* Use clock read-back from current hw-state for fastboot */
+ current_mode = intel_encoder_current_mode(intel_encoder);
+ if (current_mode) {
+ DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n",
+ intel_dsi->pclk, current_mode->clock);
+ if (intel_fuzzy_clock_check(intel_dsi->pclk,
+ current_mode->clock)) {
+ DRM_DEBUG_KMS("Using GOP pclk\n");
+ intel_dsi->pclk = current_mode->clock;
+ }
+
+ kfree(current_mode);
+ }
+
vlv_dphy_param_init(intel_dsi);
/*
@@ -1963,9 +1980,6 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
}
}
- intel_encoder->type = INTEL_OUTPUT_DSI;
- intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
- intel_encoder->cloneable = 0;
drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
DRM_MODE_CONNECTOR_DSI);
--
2.21.0
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[Intel-gfx] [PATCH 1/3] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
This is a preparation patch for moving the calling of *_dphy_param_init()
out of intel_dsi_vbt_init.
Reviewed-by: Ville Syrjälä
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 77 +++-
1 file changed, 42 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 4b8e48db1843..3a187ffabfbd 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -532,6 +532,44 @@ void intel_dsi_msleep(struct intel_dsi *intel_dsi, int
msec)
msleep(msec);
}
+static void intel_dsi_log_params(struct intel_dsi *intel_dsi)
+{
+ DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
+ DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
+ DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count);
+ DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
+ DRM_DEBUG_KMS("Video mode format %s\n",
+ intel_dsi->video_mode_format ==
VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
+ "non-burst with sync pulse" :
+ intel_dsi->video_mode_format ==
VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
+ "non-burst with sync events" :
+ intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
+ "burst" : "");
+ DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
+ DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val);
+ DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
+ DRM_DEBUG_KMS("Clockstop %s\n",
enableddisabled(!intel_dsi->clock_stop));
+ DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" :
"video");
+ if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+ DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
+ else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
+ DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
+ else
+ DRM_DEBUG_KMS("Dual link: NONE\n");
+ DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
+ DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
+ DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
+ DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
+ DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
+ DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
+ DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
+ DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
+ DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n",
intel_dsi->clk_lp_to_hs_count);
+ DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n",
intel_dsi->clk_hs_to_lp_count);
+ DRM_DEBUG_KMS("BTA %s\n",
+ enableddisabled(!(intel_dsi->video_frmt_cfg_bits &
DISABLE_VIDEO_BTA)));
+}
+
#define ICL_PREPARE_CNT_MAX0x7
#define ICL_CLK_ZERO_CNT_MAX 0xf
#define ICL_TRAIL_CNT_MAX 0x7
@@ -635,6 +673,8 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
HS_TRAIL(trail_cnt) |
HS_EXIT_OVERRIDE |
HS_EXIT(exit_zero_cnt));
+
+ intel_dsi_log_params(intel_dsi);
}
static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
@@ -794,6 +834,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
8);
intel_dsi->clk_hs_to_lp_count += extra_byte_count;
+
+ intel_dsi_log_params(intel_dsi);
}
bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
@@ -888,41 +930,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
else
vlv_dphy_param_init(intel_dsi);
- DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
- DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
- DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count);
- DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
- DRM_DEBUG_KMS("Video mode format %s\n",
- intel_dsi->video_mode_format ==
VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
- "non-burst with sync pulse" :
- intel_dsi->video_mode_format ==
VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
- "non-burst with sync events" :
- intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
- "burst" : "");
- DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
- DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val);
- DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
- DRM_DEBUG_KMS("Clockstop %s\n",
enableddisabled(!intel_dsi->clock_stop));
- DRM_DEBUG
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init
Hi,
On 04-06-19 19:35, Ville Syrjälä wrote:
On Fri, May 24, 2019 at 06:30:19PM +0200, Hans de Goede wrote:
The vlv/icl_dphy_param_init calls do various calculations to set dphy
parameters based on the pclk.
Move the calling of vlv/icl_dphy_param_init to vlv_dsi_init to give
vlv_dsi_init a chance to tweak the pclk before these calculations are done.
This also removes the single "if (IS_ICELAKE(dev_priv))" check from
intel_dsi_vbt_init making it fully platform agnostic.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/icl_dsi.c | 1 +
drivers/gpu/drm/i915/intel_dsi.h | 2 ++
drivers/gpu/drm/i915/intel_dsi_vbt.c | 9 ++---
drivers/gpu/drm/i915/vlv_dsi.c | 2 ++
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9d962ea1e635..0f43ef07efec 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1455,6 +1455,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
goto err;
}
+ icl_dphy_param_init(intel_dsi);
I think we should move the entire function into this file.
I was thinking the same thing when I was writing the patch, but I was
not 100% sure. I'm glad that you think the same, I will post a
new version with this fixed (both of them).
Regards,
Hans
return;
err:
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 705a609050c0..a58d3d988d9f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -192,5 +192,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id);
void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
enum mipi_seq seq_id);
void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
+void icl_dphy_param_init(struct intel_dsi *intel_dsi);
+void vlv_dphy_param_init(struct intel_dsi *intel_dsi);
#endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 3448e8d51057..022bf59418df 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -578,7 +578,7 @@ static void intel_dsi_log_params(struct intel_dsi
*intel_dsi)
#define ICL_HS_ZERO_CNT_MAX 0xf
#define ICL_EXIT_ZERO_CNT_MAX 0x7
-static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
+void icl_dphy_param_init(struct intel_dsi *intel_dsi)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -677,7 +677,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
intel_dsi_log_params(intel_dsi);
}
-static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
+void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -914,11 +914,6 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
intel_dsi->burst_mode_ratio = burst_mode_ratio;
- if (INTEL_GEN(dev_priv) >= 11)
- icl_dphy_param_init(intel_dsi);
- else
- vlv_dphy_param_init(intel_dsi);
-
/* delays in VBT are in unit of 100us, so need to convert
* here in ms
* Delay (100us) * 100 /1000 = Delay / 10 (ms) */
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index fce8b58f7f93..3329ccf3b346 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -1782,6 +1782,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
goto err;
}
+ vlv_dphy_param_init(intel_dsi);
ditto
+
/*
* In case of BYT with CRC PMIC, we need to use GPIO for
* Panel control.
--
2.21.0
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: always use Command Transport Buffers
On 6/5/19 8:20 AM, Michal Wajdeczko wrote: On Tue, 04 Jun 2019 22:29:20 +0200, Daniele Ceraolo Spurio wrote: Now that we've moved the gen9 guc blobs to version 32 we have CTB support on all gens, so no need to restrict the usage to gen11+. Note that mmio communication is still required for CTB initialization. s/gen9/Gen9 s/guc/GuC s/gen11/Gen11 s/mmio/MMIO Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko --- For simple enable_guc=2 mode (HuC auth only) use of CTB might be viewed as small overkill, but I assume fw prefers that way. Spoiler alert: I've heard that since huc auth is currently a multi-step process within guc/HW, to make debugging HuC loading issues easier the guc devs plan to add an extra G2H after the completion of the first step, which will only be supported via CTB. This was not the reason why I sent this patch (I'm not even sure if the plan is confirmed), but I guess it helps reinforcing the argument for using CTB with enable_guc=2. Daniele With above commit message nits, Reviewed-by: Michal Wajdeczko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Add missing commas to the end of the subplatform ID arrays
== Series Details ==
Series: series starting with [1/2] drm/i915: Add missing commas to the end of
the subplatform ID arrays
URL : https://patchwork.freedesktop.org/series/61673/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6196 -> Patchwork_13181
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13181/
Known issues
Here are the changes found in Patchwork_13181 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-icl-u3/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13181/fi-icl-u3/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-snb-2520m: [PASS][3] -> [FAIL][4] ([fdo#100368])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-snb-2520m/igt@kms_flip@basic-flip-vs-wf_vblank.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13181/fi-snb-2520m/igt@kms_flip@basic-flip-vs-wf_vblank.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][5] ([fdo#108511]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13181/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@kms_addfb_basic@basic:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-icl-u3/igt@kms_addfb_ba...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13181/fi-icl-u3/igt@kms_addfb_ba...@basic.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][9] ([fdo#102614]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6196/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13181/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
Participating hosts (52 -> 45)
--
Additional (1): fi-cfl-guc
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-skl-6260u fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6196 -> Patchwork_13181
CI_DRM_6196: 7a984cf09665b9ef4c63e82a8551bdde5da229ae @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5040: f190ab5dcd3fa52f4b47bc28c01bcfbbdc26 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13181: 24eb1a1ddcd73485f29a4dd7f2d1530f86aea3c5 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
24eb1a1ddcd7 drm/i915: Kill INTEL_SUBPLATFORM_AML
aa238fb22ef4 drm/i915: Add missing commas to the end of the subplatform ID
arrays
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13181/
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Skip context_barrier emission for unused contexts
== Series Details ==
Series: drm/i915: Skip context_barrier emission for unused contexts
URL : https://patchwork.freedesktop.org/series/61595/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6187_full -> Patchwork_13171_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_13171_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-apl2/igt@kms_cursor_...@pipe-b-cursor-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-apl6/igt@kms_cursor_...@pipe-b-cursor-suspend.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109349])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-iclb3/igt@kms_dp_...@basic-dsc-enable-edp.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move:
- shard-hsw: [PASS][5] -> [SKIP][6] ([fdo#109271]) +28 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw2/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-move.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +4 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb7/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-iclb1/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108] /
[fdo#106978])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-skl3/igt@kms_frontbuffer_track...@psr-suspend.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-skl9/igt@kms_frontbuffer_track...@psr-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] /
[fdo#110042])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-iclb3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-skl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-skl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][19] -> [FAIL][20] ([fdo#99912])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-kbl1/igt@kms_setm...@basic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-kbl7/igt@kms_setm...@basic.html
Possible fixes
* {igt@gem_ctx_param@vm}:
- shard-hsw: [DMESG-WARN][21] ([fdo#110836]) -> [PASS][22] +1
similar issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw2/igt@gem_ctx_pa...@vm.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13171/shard-hsw6/igt@gem_ctx_pa...@vm.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][23] ([fdo#104108]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-skl5/igt@gem_soft...@noreloc-s3.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix TypeC port mode switching
== Series Details == Series: drm/i915: Fix TypeC port mode switching URL : https://patchwork.freedesktop.org/series/61590/ State : success == Summary == CI Bug Log - changes from CI_DRM_6187_full -> Patchwork_13170_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13170_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@reset-stress: - shard-snb: [PASS][1] -> ([FAIL][2], [PASS][3]) ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-snb6/igt@gem_...@reset-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-snb7/igt@gem_...@reset-stress.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-snb4/igt@gem_...@reset-stress.html * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][4] -> [FAIL][5] ([fdo#109661]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-snb2/igt@gem_...@unwedge-stress.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-snb2/igt@gem_...@unwedge-stress.html * igt@i915_pm_rpm@gem-execbuf: - shard-iclb: [PASS][6] -> [INCOMPLETE][7] ([fdo#107713] / [fdo#108840]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb4/igt@i915_pm_...@gem-execbuf.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-iclb7/igt@i915_pm_...@gem-execbuf.html * igt@i915_suspend@debugfs-reader: - shard-skl: [PASS][8] -> ([PASS][9], [INCOMPLETE][10]) ([fdo#104108]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-skl8/igt@i915_susp...@debugfs-reader.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-skl4/igt@i915_susp...@debugfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-skl3/igt@i915_susp...@debugfs-reader.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][11] -> ([PASS][12], [DMESG-WARN][13]) ([fdo#108566]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-apl2/igt@kms_cursor_...@pipe-b-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-apl8/igt@kms_cursor_...@pipe-b-cursor-suspend.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-apl7/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109349]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-iclb8/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [PASS][16] -> ([FAIL][17], [PASS][18]) ([fdo#105363]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-glk9/igt@kms_f...@2x-flip-vs-expired-vblank.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-glk4/igt@kms_f...@2x-flip-vs-expired-vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank.html * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][19] -> ([FAIL][20], [PASS][21]) ([fdo#103060]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-glk3/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-glk8/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-glk6/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: - shard-glk: [PASS][22] -> [FAIL][23] ([fdo#100368]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-glk2/igt@kms_f...@2x-plain-flip-fb-recreate-interruptible.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-glk1/igt@kms_f...@2x-plain-flip-fb-recreate-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][24] -> ([FAIL][25], [PASS][26]) ([fdo#102887] / [fdo#105363]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-glk4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-glk2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13170/shard-glk5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip_tiling@flip-to-x-tiled: - shard-iclb: [PASS][27] -> [FAIL][28] ([fdo#108134]) [27]: h
[Intel-gfx] [PATCH 2/2] drm/i915: Kill INTEL_SUBPLATFORM_AML
From: Ville Syrjälä
All AML parts are either KBL ULX or CFL ULX so there is no point
in keeping INTEL_SUBPLATFORM_AML around. As these are the only
CFL ULX parts (normal CFL didn't have Y SKUs) so we'll just
replace IS_AML_ULX with IS_CFL_ULX (it was already paired with
IS_KBL_ULX which accounts for the other half of the AML parts).
Cc: Tvrtko Ursulin
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++---
drivers/gpu/drm/i915/intel_ddi.c | 8 +---
drivers/gpu/drm/i915/intel_device_info.c | 6 --
drivers/gpu/drm/i915/intel_device_info.h | 1 -
4 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89bf1e34feaa..16ea0e6077cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2213,9 +2213,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_KBL_ULX(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_AML_ULX(dev_priv) \
- (IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
-IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 2)
#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
@@ -2228,6 +2225,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
INTEL_INFO(dev_priv)->gt == 3)
#define IS_CFL_ULT(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_CFL_ULX(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 2)
#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 350eaf54f01f..65c02b260c98 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -615,7 +615,7 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int
*n_entries)
static const struct ddi_buf_trans *
kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
{
- if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
+ if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
*n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
return kbl_y_ddi_translations_dp;
} else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
@@ -631,7 +631,8 @@ static const struct ddi_buf_trans *
skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{
if (dev_priv->vbt.edp.low_vswing) {
- if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
IS_AML_ULX(dev_priv)) {
+ if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
+ IS_CFL_ULX(dev_priv)) {
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
return skl_y_ddi_translations_edp;
} else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
@@ -653,7 +654,8 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
int *n_entries)
static const struct ddi_buf_trans *
skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
{
- if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
IS_AML_ULX(dev_priv)) {
+ if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
+ IS_CFL_ULX(dev_priv)) {
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
return skl_y_ddi_translations_hdmi;
} else {
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 19437e8ec6fa..7135d8dc32a7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -787,9 +787,6 @@ static const u16 subplatform_ulx_ids[] = {
INTEL_SKL_ULX_GT2_IDS(0),
INTEL_KBL_ULX_GT1_IDS(0),
INTEL_KBL_ULX_GT2_IDS(0),
-};
-
-static const u16 subplatform_aml_ids[] = {
INTEL_AML_KBL_GT2_IDS(0),
INTEL_AML_CFL_GT2_IDS(0),
};
@@ -832,9 +829,6 @@ void intel_device_info_subplatform_init(struct
drm_i915_private *i915)
/* ULX machines are also considered ULT. */
mask |= BIT(INTEL_SUBPLATFORM_ULT);
}
- } else if (find_devid(devid, subplatform_aml_ids,
- ARRAY_SIZE(subplatform_aml_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_AML);
} else if (find_devid(devid, subplatform_portf_ids,
ARRAY_SIZE(subplatform_portf_ids))) {
mask = BIT(INTEL_SUBPLATFORM_PORTF);
diff -
[Intel-gfx] [PATCH 1/2] drm/i915: Add missing commas to the end of the subplatform ID arrays
From: Ville Syrjälä
Add a comma after the final entry to make diffs less obnoxious if
we have to add further entries past the last one.
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_device_info.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 97f742530fa1..19437e8ec6fa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -773,7 +773,7 @@ static const u16 subplatform_ult_ids[] = {
INTEL_CFL_U_GT3_IDS(0),
INTEL_WHL_U_GT1_IDS(0),
INTEL_WHL_U_GT2_IDS(0),
- INTEL_WHL_U_GT3_IDS(0)
+ INTEL_WHL_U_GT3_IDS(0),
};
static const u16 subplatform_ulx_ids[] = {
@@ -786,17 +786,17 @@ static const u16 subplatform_ulx_ids[] = {
INTEL_SKL_ULX_GT1_IDS(0),
INTEL_SKL_ULX_GT2_IDS(0),
INTEL_KBL_ULX_GT1_IDS(0),
- INTEL_KBL_ULX_GT2_IDS(0)
+ INTEL_KBL_ULX_GT2_IDS(0),
};
static const u16 subplatform_aml_ids[] = {
INTEL_AML_KBL_GT2_IDS(0),
- INTEL_AML_CFL_GT2_IDS(0)
+ INTEL_AML_CFL_GT2_IDS(0),
};
static const u16 subplatform_portf_ids[] = {
INTEL_CNL_PORT_F_IDS(0),
- INTEL_ICL_PORT_F_IDS(0)
+ INTEL_ICL_PORT_F_IDS(0),
};
static bool find_devid(u16 id, const u16 *p, unsigned int num)
--
2.21.0
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/dsi: Use a fuzzy check for burst mode clock check
Hi,
Thank you for the reviews.
On 04-06-19 19:29, Ville Syrjälä wrote:
On Fri, May 24, 2019 at 07:40:28PM +0200, Hans de Goede wrote:
Prior to this commit we fail to init the DSI panel on the GPD MicroPC:
https://www.indiegogo.com/projects/gpd-micropc-6-inch-handheld-industry-laptop#/
The problem is intel_dsi_vbt_init() failing with the following error:
*ERROR* Burst mode freq is less than computed
The pclk in the VBT panel modeline is 7, together with 24 bpp and
4 lines this results in a bitrate value of 7 * 24 / 4 = 42.
But the target_burst_mode_freq in the VBT is 418000.
This commit works around this problem by adding an intel_fuzzy_clock_check
when target_burst_mode_freq < bitrate and setting target_burst_mode_freq to
bitrate when that checks succeeds, fixing the panel not working.
Cc: sta...@vger.kernel.org
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 022bf59418df..a2a9b9d0eeaa 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -895,6 +895,17 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
if (mipi_config->target_burst_mode_freq) {
u32 bitrate = intel_dsi_bitrate(intel_dsi);
+ /*
+* Sometimes the VBT contains a slightly lower clock,
+* then the bitrate we have calculated, in this case
+* just replace it with the calculated bitrate.
+*/
+ if (mipi_config->target_burst_mode_freq < bitrate &&
+ intel_fuzzy_clock_check(
+ mipi_config->target_burst_mode_freq,
+ bitrate))
+ mipi_config->target_burst_mode_freq = bitrate;
Maybe should squash these patches together to make the stable
backport less painful?
Good idea, done.
Anyways, seems OK to me.
Reviewed-by: Ville Syrjälä
And pushed with your Reviewed-by.
Regards,
Hans
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: Rename HSW/BDW PLL bits
On Wed, Jun 05, 2019 at 04:24:25PM +0200, Maarten Lankhorst wrote:
> Op 04-06-2019 om 22:09 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > Give the PLL control register bits better names on HSW/BDW.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 37 ++-
> > drivers/gpu/drm/i915/intel_ddi.c | 16 ++--
> > drivers/gpu/drm/i915/intel_display.c | 8 +++---
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +--
> > 4 files changed, 39 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index d5fee72fc079..b7dd42bfffaa 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9465,24 +9465,33 @@ enum skl_power_gate {
> > /* SPLL */
> > #define SPLL_CTL _MMIO(0x46020)
> > #define SPLL_PLL_ENABLE (1 << 31)
> > -#define SPLL_PLL_SSC (1 << 28)
> > -#define SPLL_PLL_NON_SSC (2 << 28)
> > -#define SPLL_PLL_LCPLL(3 << 28)
> > -#define SPLL_PLL_REF_MASK (3 << 28)
> > -#define SPLL_PLL_FREQ_810MHz (0 << 26)
> > -#define SPLL_PLL_FREQ_1350MHz (1 << 26)
> > -#define SPLL_PLL_FREQ_2700MHz (2 << 26)
> > -#define SPLL_PLL_FREQ_MASK(3 << 26)
> > +#define SPLL_REF_BCLK (0 << 28)
> > +#define SPLL_REF_MUXED_SSC(1 << 28) /* CPU SSC if fused
> > enabled, PCH SSC otherwise */
> > +#define SPLL_REF_NON_SSC_HSW (2 << 28)
> > +#define SPLL_REF_PCH_SSC_BDW (2 << 28)
> > +#define SPLL_REF_LCPLL(3 << 28)
> > +#define SPLL_REF_MASK (3 << 28)
> > +#define SPLL_REF_BCLK (0 << 28)
> > +#define SPLL_REF_SSC (1 << 28)
> > +#define SPLL_REF_NON_SSC (2 << 28)
> > +#define SPLL_REF_LCPLL(3 << 28)
>
> ? Bit unclear or double definitions, at least of SPLL_REF_MASK.
Oh, that one is a copy paste fail. The others are due to HSW
and BDW having slightly different meanings for the bits.
>
>
> > +#define SPLL_REF_MASK (3 << 28)
> > +#define SPLL_FREQ_810MHz (0 << 26)
> > +#define SPLL_FREQ_1350MHz (1 << 26)
> > +#define SPLL_FREQ_2700MHz (2 << 26)
> > +#define SPLL_FREQ_MASK(3 << 26)
> >
> > /* WRPLL */
> > #define _WRPLL_CTL10x46040
> > #define _WRPLL_CTL20x46060
> > #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1,
> > _WRPLL_CTL2)
> > #define WRPLL_PLL_ENABLE (1 << 31)
> > -#define WRPLL_PLL_SSC (1 << 28)
> > -#define WRPLL_PLL_NON_SSC (2 << 28)
> > -#define WRPLL_PLL_LCPLL (3 << 28)
> > -#define WRPLL_PLL_REF_MASK(3 << 28)
> > +#define WRPLL_REF_BCLK(0 << 28)
> > +#define WRPLL_REF_PCH_SSC (1 << 28)
> > +#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled,
> > PCH SSC otherwise */
> > +#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT),
> > non-SSC (non-ULT) */
> > +#define WRPLL_REF_LCPLL (3 << 28)
> > +#define WRPLL_REF_MASK(3 << 28)
> > /* WRPLL divider programming */
> > #define WRPLL_DIVIDER_REFERENCE(x)((x) << 0)
> > #define WRPLL_DIVIDER_REF_MASK(0xff)
> > @@ -9548,6 +9557,10 @@ enum skl_power_gate {
> > #define LCPLL_CTL _MMIO(0x130040)
> > #define LCPLL_PLL_DISABLE (1 << 31)
> > #define LCPLL_PLL_LOCK(1 << 30)
> > +#define LCPLL_REF_NON_SSC (0 << 28)
> > +#define LCPLL_REF_BCLK(2 << 28)
> > +#define LCPLL_REF_PCH_SSC (3 << 28)
> > +#define LCPLL_REF_MASK(3 << 28)
> > #define LCPLL_CLK_FREQ_MASK (3 << 26)
> > #define LCPLL_CLK_FREQ_450(0 << 26)
> > #define LCPLL_CLK_FREQ_54O_BDW(1 << 26)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 350eaf54f01f..183f91abda19 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1231,9 +1231,9 @@ static int hsw_ddi_calc_wrpll_link(struct
> > drm_i915_private *dev_priv,
> > u32 wrpll;
> >
> > wrpll = I915_READ(reg);
> > - switch (wrpll & WRPLL_PLL_REF_MASK) {
> > - case WRPLL_PLL_SSC:
> > - case WRPLL_PLL_NON_SSC:
> > + switch (wrpll & WRPLL_REF_MASK) {
> > + case WRPLL_REF_SPECIAL_HSW:
> > + case WRPLL_REF_PCH_SSC:
> > /*
> > * We could calculate spread here, but our checking
> > * code only cares about 5% accuracy, and spread is a max of
> > @@ -1241,7 +1241,7 @@ static int hsw_ddi_calc_wrpll_link(struct
> > drm_i915_pri
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915: Add windowing for primary planes on gen2/3 and chv
On Wed, Jun 05, 2019 at 04:01:05PM +0200, Maarten Lankhorst wrote: > Op 31-05-2019 om 15:05 schreef Ville Syrjälä: > > On Thu, May 30, 2019 at 05:43:00AM -, Patchwork wrote: > >> == Series Details == > >> > >> Series: series starting with [01/10] drm/i915: Add windowing for primary > >> planes on gen2/3 and chv > >> URL : https://patchwork.freedesktop.org/series/61345/ > >> State : failure > >> > >> == Summary == > >> > >> CI Bug Log - changes from CI_DRM_6165_full -> Patchwork_13133_full > >> > >> > >> Summary > >> --- > >> > >> **FAILURE** > >> > >> Serious unknown changes coming with Patchwork_13133_full absolutely need > >> to be > >> verified manually. > >> > >> If you think the reported changes have nothing to do with the changes > >> introduced in Patchwork_13133_full, please notify your bug team to allow > >> them > >> to document this new failure mode, which will reduce false positives in > >> CI. > >> > >> > >> > >> Possible new issues > >> --- > >> > >> Here are the unknown changes that may have been introduced in > >> Patchwork_13133_full: > >> > >> ### IGT changes ### > >> > >> Possible regressions > >> > >> * igt@kms_plane@pixel-format-pipe-a-planes: > >> - shard-glk: [PASS][1] -> [FAIL][2] > >>[1]: > >> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-glk3/igt@kms_pl...@pixel-format-pipe-a-planes.html > >>[2]: > >> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-glk8/igt@kms_pl...@pixel-format-pipe-a-planes.html > > <7> [125.370679] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": > > 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 > > ... > > <7> [125.542650] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to > > 79200 kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage > > level 4 > > ... > > <7> [133.682144] [drm:skl_check_pipe_max_pixel_rate [i915]] Max supported > > pixel clock with scaling exceeded > > > > Max pixel rate for 64bpp is 79.2*2 * 8/9 = 140.8 Mhz, which we are > > exceeding. We'd need some way to bump the cdclk for this case, but > > the kernel will only do that for modesets, and it won't account for > > that 8/9 factor. Not sure there is a great way to handle these sorts > > of cases. > > > >> * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: > >> - shard-apl: [PASS][3] -> [FAIL][4] +4 similar issues > >>[3]: > >> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-apl5/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html > >>[4]: > >> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-apl7/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html > > <7> [1749.831610] [drm:drm_atomic_helper_check_plane_state] Invalid scaling > > of plane > > <7> [1749.831620] [drm:drm_rect_debug_print] src: > > 8.00x8.00+0.00+0.00 > > <7> [1749.831625] [drm:drm_rect_debug_print] dst: 1920x1080+0+0 > > > > Not quite sure what's going on here. Unfortunately the debugs don't have > > enough information to see what's going on. > > For first 6 patches > > Reviewed-by: Maarten Lankhorst Thanks. > > What happens on < gen9 btw with half float support? > > Enabling patches look sane, but worried about hw coverage. > > So if you are sure it works on add my r-b on those too. But I would like to have no regressions so have to > get gen9 fixed first before pushing. :) We do have some missing checks for the cdclk vs. fp16 case on pre-gen9, as well as missing similar cdclk vs. scaling checks. I think I have some kind of plan to remedy that. And I can probably tweak that into bumping the cdclk for fp16 as well (assuming a modeset is allowed for the commit in question of course). -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915: Add windowing for primary planes on gen2/3 and chv
On Fri, May 31, 2019 at 04:05:51PM +0300, Ville Syrjälä wrote: > On Thu, May 30, 2019 at 05:43:00AM -, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [01/10] drm/i915: Add windowing for primary > > planes on gen2/3 and chv > > URL : https://patchwork.freedesktop.org/series/61345/ > > State : failure > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_6165_full -> Patchwork_13133_full > > > > > > Summary > > --- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_13133_full absolutely need > > to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_13133_full, please notify your bug team to allow > > them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > > > > > Possible new issues > > --- > > > > Here are the unknown changes that may have been introduced in > > Patchwork_13133_full: > > > > ### IGT changes ### > > > > Possible regressions > > > > * igt@kms_plane@pixel-format-pipe-a-planes: > > - shard-glk: [PASS][1] -> [FAIL][2] > >[1]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-glk3/igt@kms_pl...@pixel-format-pipe-a-planes.html > >[2]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-glk8/igt@kms_pl...@pixel-format-pipe-a-planes.html > > <7> [125.370679] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 > 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 > ... > <7> [125.542650] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 > kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage > level 4 > ... > <7> [133.682144] [drm:skl_check_pipe_max_pixel_rate [i915]] Max supported > pixel clock with scaling exceeded > > Max pixel rate for 64bpp is 79.2*2 * 8/9 = 140.8 Mhz, which we are > exceeding. We'd need some way to bump the cdclk for this case, but > the kernel will only do that for modesets, and it won't account for > that 8/9 factor. Not sure there is a great way to handle these sorts > of cases. > > > > > * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: > > - shard-apl: [PASS][3] -> [FAIL][4] +4 similar issues > >[3]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-apl5/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html > >[4]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-apl7/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html > > <7> [1749.831610] [drm:drm_atomic_helper_check_plane_state] Invalid scaling > of plane > <7> [1749.831620] [drm:drm_rect_debug_print] src: > 8.00x8.00+0.00+0.00 > <7> [1749.831625] [drm:drm_rect_debug_print] dst: 1920x1080+0+0 > > Not quite sure what's going on here. Unfortunately the debugs don't have > enough information to see what's going on. Doh. That's obviously the "no scaling with fp16" hardware limitation kicking in. I'll need to adjust the test somehow to make it skip fp16 on these platforms. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Vulkan performance query support (rev4)
== Series Details == Series: drm/i915: Vulkan performance query support (rev4) URL : https://patchwork.freedesktop.org/series/60916/ State : success == Summary == CI Bug Log - changes from CI_DRM_6195 -> Patchwork_13180 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/ Known issues Here are the changes found in Patchwork_13180 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fence@basic-await-default: - fi-icl-y: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#110246]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-icl-y/igt@gem_exec_fe...@basic-await-default.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/fi-icl-y/igt@gem_exec_fe...@basic-await-default.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [DMESG-WARN][3] ([fdo#102614]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-flip: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-icl-u3/igt@prime_v...@basic-fence-flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/fi-icl-u3/igt@prime_v...@basic-fence-flip.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#110246]: https://bugs.freedesktop.org/show_bug.cgi?id=110246 Participating hosts (52 -> 45) -- Additional (1): fi-apl-guc Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-icl-guc fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6195 -> Patchwork_13180 CI_DRM_6195: 06b71939f2477c76f9eecb1dd5e99dcb25cb8371 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5039: 2d4f470bba1cb51ed116fb80b170f717c6294714 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13180: ce2af5b1a9ca2cbbdb66304b5ad559290fb8dbd3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ce2af5b1a9ca drm/i915: add support for perf configuration queries ccd1cbb63c8e drm/i915/perf: allow holding preemption on filtered ctx 151ed539e4ba drm/i915: add a new perf configuration execbuf parameter bfa3bc40 drm/i915: add syncobj timeline support 3aef0b772b8a drm/i915: introduce a mechanism to extend execbuf2 32203e3c3c4c drm/i915/perf: allow for CS OA configs to be created lazily abfe9e305ec9 drm/i915/perf: introduce a versioning of the i915-perf uapi == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13180/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Move intel_dp->prepare_link_train assignment into ddi code
== Series Details ==
Series: series starting with [1/2] drm/i915: Move intel_dp->prepare_link_train
assignment into ddi code
URL : https://patchwork.freedesktop.org/series/61586/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6187_full -> Patchwork_13169_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_13169_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb5/igt@gem_ctx_isolat...@rcs0-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-iclb3/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][3] -> [FAIL][4] ([fdo#109661])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-snb2/igt@gem_...@unwedge-stress.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-snb1/igt@gem_...@unwedge-stress.html
* igt@gem_mmap_gtt@forked-medium-copy-odd:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb4/igt@gem_mmap_...@forked-medium-copy-odd.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-iclb1/igt@gem_mmap_...@forked-medium-copy-odd.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109349])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-iclb8/igt@kms_dp_...@basic-dsc-enable-edp.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) +16 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw8/igt@kms_frontbuffer_track...@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-apl4/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-apl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar
issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#99912])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-kbl1/igt@kms_setm...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-kbl3/igt@kms_setm...@basic.html
* igt@tools_test@tools_test:
- shard-snb: [PASS][19] -> [SKIP][20] ([fdo#109271])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-snb4/igt@tools_test@tools_test.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-snb4/igt@tools_test@tools_test.html
Possible fixes
* {igt@gem_ctx_param@vm}:
- shard-hsw: [DMESG-WARN][21] ([fdo#110836]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-hsw2/igt@gem_ctx_pa...@vm.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-hsw6/igt@gem_ctx_pa...@vm.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][23] ([fdo#104108]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/shard-skl5/igt@gem_soft...@noreloc-s3.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13169/shard-skl6/igt@gem_soft...@noreloc-s3.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][25] ([fdo#105767]) -> [PASS][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Vulkan performance query support (rev4)
== Series Details == Series: drm/i915: Vulkan performance query support (rev4) URL : https://patchwork.freedesktop.org/series/60916/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/perf: introduce a versioning of the i915-perf uapi Okay! Commit: drm/i915/perf: allow for CS OA configs to be created lazily +drivers/gpu/drm/i915/i915_perf.c:394:37: warning: expression using sizeof(void) Commit: drm/i915: introduce a mechanism to extend execbuf2 Okay! Commit: drm/i915: add syncobj timeline support +./include/linux/mm.h:652:13: error: not a function Commit: drm/i915: add a new perf configuration execbuf parameter + ^~ +^~ +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2114:40: error: ‘struct i915_perf_stream’ has no member named ‘hold_preemption’ +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2114:47: error: no member 'hold_preemption' in struct i915_perf_stream +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2115:14: error: ‘struct i915_request’ has no member named ‘has_perf’ +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2115:28: error: no member 'has_perf' in struct i915_request +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c: In function ‘eb_oa_config’: -drivers/gpu/drm/i915/gvt/mmio.c:281:23: warning: memcpy with byte count of 279040 -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gpu_error.c:1006:21: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gpu_error.c:1006:21: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gpu_error.c:906:23: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gpu_error.c:906:23: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_perf.c:1528:15: warning: memset with byte count of 16777216 -drivers/gpu/drm/i915/i915_perf.c:1586:15: warning: memset with byte count of 16777216 -drivers/gpu/drm/i915/i915_perf.c:395:37: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_utils.h:220:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_utils.h:220:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_utils.h:220:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_utils.h:220:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_utils.h:220:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_utils.h:220:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_utils.h:220:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:565:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:565:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:566:21: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:566:21: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:568:24: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:568:24: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:569:29: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:569:29: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:582:23: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:582:23: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:584:23: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:655:37: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_vma.c:655:37: warning: expression using sizeof(void) -drivers/gpu/drm/i915/icl_dsi.c:135:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_audio.c:306:15: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel
Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: always use Command Transport Buffers
On Tue, 04 Jun 2019 22:29:20 +0200, Daniele Ceraolo Spurio wrote: Now that we've moved the gen9 guc blobs to version 32 we have CTB support on all gens, so no need to restrict the usage to gen11+. Note that mmio communication is still required for CTB initialization. s/gen9/Gen9 s/guc/GuC s/gen11/Gen11 s/mmio/MMIO Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko --- For simple enable_guc=2 mode (HuC auth only) use of CTB might be viewed as small overkill, but I assume fw prefers that way. With above commit message nits, Reviewed-by: Michal Wajdeczko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Vulkan performance query support (rev4)
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev4)
URL : https://patchwork.freedesktop.org/series/60916/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
abfe9e305ec9 drm/i915/perf: introduce a versioning of the i915-perf uapi
32203e3c3c4c drm/i915/perf: allow for CS OA configs to be created lazily
-:124: CHECK:SPACING: No space is necessary after a cast
#124: FILE: drivers/gpu/drm/i915/i915_perf.c:395:
+ (u32) MI_LOAD_REGISTER_IMM_MAX_REGS);
total: 0 errors, 0 warnings, 1 checks, 311 lines checked
3aef0b772b8a drm/i915: introduce a mechanism to extend execbuf2
-:126: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#126: FILE: include/uapi/drm/i915_drm.h:1170:
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_EXT<<1))
^
total: 0 errors, 0 warnings, 1 checks, 103 lines checked
bfa3bc40 drm/i915: add syncobj timeline support
-:341: WARNING:TYPO_SPELLING: 'transfered' may be misspelled - perhaps
'transferred'?
#341: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2488:
+* The chain's ownership is transfered to the
-:365: ERROR:CODE_INDENT: code indent should use tabs where possible
#365: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2512:
+[DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,$
-:365: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#365: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2512:
+[DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,$
total: 1 errors, 2 warnings, 0 checks, 511 lines checked
151ed539e4ba drm/i915: add a new perf configuration execbuf parameter
-:44: CHECK:LINE_SPACING: Please don't use multiple blank lines
#44: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1206:
+
-:170: ERROR:CODE_INDENT: code indent should use tabs where possible
#170: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2620:
+[DRM_I915_GEM_EXECBUFFER_EXT_PERF] = parse_perf_config,$
-:170: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#170: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2620:
+[DRM_I915_GEM_EXECBUFFER_EXT_PERF] = parse_perf_config,$
total: 1 errors, 1 warnings, 1 checks, 416 lines checked
ccd1cbb63c8e drm/i915/perf: allow holding preemption on filtered ctx
-:140: WARNING:BRACES: braces {} are not necessary for single statement blocks
#140: FILE: drivers/gpu/drm/i915/i915_perf.c:2727:
+ if (IS_HASWELL(dev_priv) && specific_ctx && !props->hold_preemption) {
privileged_op = false;
+ }
total: 0 errors, 1 warnings, 0 checks, 165 lines checked
ce2af5b1a9ca drm/i915: add support for perf configuration queries
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Re: [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_latency: Measure the latency of context switching
Chris Wilson writes:
> Measure the baseline latency between contexts in order to directly
> compare that with the additional cost of preemption.
>
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_exec_latency.c | 230 ++
> 1 file changed, 230 insertions(+)
>
> diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
> index e56d62780..e88fbbc6a 100644
> --- a/tests/i915/gem_exec_latency.c
> +++ b/tests/i915/gem_exec_latency.c
> @@ -410,6 +410,86 @@ static void latency_from_ring(int fd,
> }
> }
>
> +static void execution_latency(int i915, unsigned int ring, const char *name)
> +{
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = gem_create(i915, 4095),
> + };
> + struct drm_i915_gem_execbuffer2 execbuf = {
> + .buffers_ptr = to_user_pointer(&obj),
> + .buffer_count = 1,
> + .flags = ring | LOCAL_I915_EXEC_NO_RELOC |
> LOCAL_I915_EXEC_HANDLE_LUT,
> + };
> + const unsigned int mmio_base = 0x2000;
> + const unsigned int cs_timestamp = mmio_base + 0x358;
> + volatile uint32_t *timestamp;
> + uint32_t *cs, *result;
> +
> + timestamp =
> + (volatile uint32_t *)((volatile char *)igt_global_mmio +
> cs_timestamp);
> +
> + obj.handle = gem_create(i915, 4096);
> + obj.flags = EXEC_OBJECT_PINNED;
> + result = gem_mmap__wc(i915, obj.handle, 0, 4096, PROT_WRITE);
> +
> + for (int i = 0; i < 16; i++) {
> + cs = result + 16 * i;
> + *cs++ = 0x24 << 23 | 2; /* SRM */
> + *cs++ = cs_timestamp;
> + *cs++ = 4096 - 16 * 4 + i * 4;
> + *cs++ = 0;
> + *cs++ = 0xa << 23;
Why not MI_BATCH_BUFFER_END? To emphasize that we have
multiple batches inside a bo?
> + }
> +
> + cs = result + 1024 - 16;
> +
> + for (int length = 2; length <= 16; length <<= 1) {
> + struct igt_mean submit, batch, total;
> + int last = length - 1;
> +
> + igt_mean_init(&submit);
> + igt_mean_init(&batch);
> + igt_mean_init(&total);
> +
> + igt_until_timeout(2) {
> + uint32_t now, end;
> +
> + cs[last] = 0;
> +
> + now = *timestamp;
> + for (int i = 0; i < length; i++) {
> + execbuf.batch_start_offset = 64 * i;
> + gem_execbuf(i915, &execbuf);
> + }
> + while (!((volatile uint32_t *)cs)[last])
> + ;
> + end = *timestamp;
> +
> + igt_mean_add(&submit, (cs[0] - now) * rcs_clock);
> + igt_mean_add(&batch, (cs[last] - cs[0]) * rcs_clock /
> last);
Just curious of what do you use of inter batch latency?
Oh and do we need to to take the rcs_clock resolution into account
on result calculation. Prolly not as it seems to be ticking fast enough
for 0.1us accuracy.
> + igt_mean_add(&total, (end - now) * rcs_clock);
> + }
> +
> + igt_info("%sx%d Submission latency: %.2f±%.2fus\n",
> + name, length,
> + 1e-3 * igt_mean_get(&submit),
> + 1e-3 * sqrt(igt_mean_get_variance(&submit)));
> +
> + igt_info("%sx%d Inter-batch latency: %.2f±%.2fus\n",
> + name, length,
> + 1e-3 * igt_mean_get(&batch),
> + 1e-3 * sqrt(igt_mean_get_variance(&batch)));
> +
> + igt_info("%sx%d End-to-end latency: %.2f±%.2fus\n",
> + name, length,
> + 1e-3 * igt_mean_get(&total),
> + 1e-3 * sqrt(igt_mean_get_variance(&total)));
> + }
> +
> + munmap(result, 4096);
> + gem_close(i915, obj.handle);
> +}
> +
> static void
> __submit_spin(int fd, igt_spin_t *spin, unsigned int flags)
> {
> @@ -616,6 +696,142 @@ rthog_latency_on_ring(int fd, unsigned int engine,
> const char *name, unsigned in
> munmap(results, MMAP_SZ);
> }
>
> +static void context_switch(int i915,
> +unsigned int engine, const char *name,
> +unsigned int flags)
> +{
> + struct drm_i915_gem_exec_object2 obj[2];
> + struct drm_i915_gem_relocation_entry reloc[5];
> + struct drm_i915_gem_execbuffer2 eb;
> + uint32_t *cs, *bbe, *results, v;
> + unsigned int mmio_base;
> + struct igt_mean mean;
> + uint32_t ctx[2];
> +
> + /* XXX i915_query()! */
> + switch (engine) {
> + case I915_EXEC_DEFAULT:
> + case I915_EXEC_RENDER:
> + mmio_base = 0x2000;
> + break;
> +#if 0
> + case I915_EXEC_BSD:
> + mmio_base = 0x12000;
> + break;
> +#endif
It seems to be there according to bspec. Timestamps don't
work with it?
> + case I915_E
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: rename header test build commands to avoid conflicts
== Series Details == Series: drm/i915: rename header test build commands to avoid conflicts URL : https://patchwork.freedesktop.org/series/61655/ State : success == Summary == CI Bug Log - changes from CI_DRM_6195 -> Patchwork_13179 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/ Known issues Here are the changes found in Patchwork_13179 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_exec@basic: - fi-cml-u: [PASS][1] -> [INCOMPLETE][2] ([fdo#110566]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-cml-u/igt@gem_ctx_e...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/fi-cml-u/igt@gem_ctx_e...@basic.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [DMESG-WARN][3] ([fdo#102614]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-flip: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-icl-u3/igt@prime_v...@basic-fence-flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/fi-icl-u3/igt@prime_v...@basic-fence-flip.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566 Participating hosts (52 -> 44) -- Additional (1): fi-apl-guc Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6195 -> Patchwork_13179 CI_DRM_6195: 06b71939f2477c76f9eecb1dd5e99dcb25cb8371 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5039: 2d4f470bba1cb51ed116fb80b170f717c6294714 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13179: 372ace4ba9e48be405ce0624313d1fba5e7b76da @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 372ace4ba9e4 drm/i915: rename header test build commands to avoid conflicts == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13179/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/wopcm: update default size for gen11+
On Wed, 05 Jun 2019 01:15:29 +0200, Daniele Ceraolo Spurio
wrote:
The size has been increased to 2MB starting from gen11. GuC and HuC FWs
nit: s/gen11/Gen11
fit in 1MB so we were fine even with the legacy define, but let's still
move to the correct one before the blobs grow to avoid being caught off
guard in the future.
Bspec: 44982
I think for ICL this should be 12690
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_wopcm.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f82a415ea2ba..6cb993eea206 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -41,8 +41,9 @@
* context).
*/
-/* Default WOPCM size 1MB. */
-#define GEN9_WOPCM_SIZE(1024 * 1024)
+/* Default WOPCM size is 2MB from gen11, 1MB on previous platforms */
nit: s/gen11/Gen11
+#define GEN11_WOPCM_SIZE (SZ_2M)
+#define GEN9_WOPCM_SIZE(SZ_1M)
/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
#define WOPCM_RESERVED_SIZE(16 * 1024)
@@ -71,7 +72,10 @@
*/
void intel_wopcm_init_early(struct intel_wopcm *wopcm)
{
- wopcm->size = GEN9_WOPCM_SIZE;
+ if (INTEL_GEN(wopcm_to_i915(wopcm)) >= 11)
+ wopcm->size = GEN11_WOPCM_SIZE;
+ else
+ wopcm->size = GEN9_WOPCM_SIZE;
While here, maybe we should not try to setup WOPCM size on pre-Gen9
platforms ? Then we can drop below log if WOPCM is zero/not available.
DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
}
With above,
Reviewed-by: Michal Wajdeczko
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl (rev2)
== Series Details == Series: drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl (rev2) URL : https://patchwork.freedesktop.org/series/61299/ State : success == Summary == CI Bug Log - changes from CI_DRM_6195 -> Patchwork_13178 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/ Known issues Here are the changes found in Patchwork_13178 that come from known issues: ### IGT changes ### Issues hit * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-icl-u3/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/fi-icl-u3/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html Possible fixes * igt@prime_vgem@basic-fence-flip: - fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-icl-u3/igt@prime_v...@basic-fence-flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/fi-icl-u3/igt@prime_v...@basic-fence-flip.html Warnings * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: [FAIL][5] ([fdo#103167]) -> [DMESG-FAIL][6] ([fdo#103167] / [fdo#107724]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6195/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 Participating hosts (52 -> 43) -- Missing(9): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-icl-y fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6195 -> Patchwork_13178 CI_DRM_6195: 06b71939f2477c76f9eecb1dd5e99dcb25cb8371 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5039: 2d4f470bba1cb51ed116fb80b170f717c6294714 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13178: b69c7ced50903ace5eabde3d4a13c30ffb2400d7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b69c7ced5090 drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13178/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Fix 90/270 degree rotated RGB565 src coord checks
Op 30-04-2019 om 19:33 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Supposedly both src coordinates have to even when doing 90/270
> degree rotation with RGB565. This is definitely true for the
> X coordinate (we just get a black screen when it is odd). My
> experiments didn't show any misbehaviour with an odd
> Y coordinate, but let's trust the spec and reject that one
> as well.
>
> v2: Ignore ccs hsub/vsub
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 28 +---
> 1 file changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 2913e89280d7..b133f254e26d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -294,26 +294,32 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
> src->y1 = src_y << 16;
> src->y2 = (src_y + src_h) << 16;
>
> - if (!fb->format->is_yuv)
> - return 0;
> -
> - /* YUV specific checks */
> - if (!rotated) {
> + if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
> + hsub = 2;
> + vsub = 2;
> + } else if (is_ccs_modifier(fb->modifier)) {
> + hsub = 1;
> + vsub = 1;
Just return 0 here, with a comment how ccs sets vsub/hsub. Less confusing.
Other than that.
Reviewed-by: Maarten Lankhorst
> + } else {
> hsub = fb->format->hsub;
> vsub = fb->format->vsub;
> - } else {
> - hsub = vsub = max(fb->format->hsub, fb->format->vsub);
> }
>
> + if (rotated)
> + hsub = vsub = max(hsub, vsub);
> +
> + if (hsub == 1 && vsub == 1)
> + return 0;
> +
> if (src_x % hsub || src_w % hsub) {
> - DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u for
> %sYUV planes\n",
> - src_x, src_w, hsub, rotated ? "rotated " : "");
> + DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u
> (rotated: %s)\n",
> + src_x, src_w, hsub, yesno(rotated));
> return -EINVAL;
> }
>
> if (src_y % vsub || src_h % vsub) {
> - DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u for
> %sYUV planes\n",
> - src_y, src_h, vsub, rotated ? "rotated " : "");
> + DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u
> (rotated: %s)\n",
> + src_y, src_h, vsub, yesno(rotated));
> return -EINVAL;
> }
>
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: Improve WRPLL reference clock readout on HSW/BDW
Op 04-06-2019 om 22:09 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> On non-ULT HSW the "special" WRPLL reference clock select
> actually means non-SSC. Take that into account when reading
> out the WRPLL state.
>
> Also the non-SSC reference may be either 24MHz or 135MHz,
> which we can read out from FUSE_STRAP3. The BDW docs actually
> say: "also indicates whether the CPU and PCH are in a single
> package or separate packages", so it may be that this is not
> actually required and we could just assume 135 MHz (just like
> the code already did). But it doesn't really hurt to read this
> out as the HSW docs aren't quite so clear.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_ddi.c | 15 ++-
> 2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b7dd42bfffaa..533b1d8d23cb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7513,6 +7513,9 @@ enum {
> #define ILK_DESKTOP (1 << 23)
> #define HSW_CPU_SSC_ENABLE (1 << 21)
>
> +#define FUSE_STRAP3 _MMIO(0x42020)
> +#define HSW_REF_CLK_SELECT (1 << 1)
> +
> #define ILK_DSPCLK_GATE_D_MMIO(0x42020)
> #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
> #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE(1 << 9)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index fc9bcbd75c3a..49dab3e72019 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1231,6 +1231,19 @@ static int hsw_ddi_calc_wrpll_link(struct
> drm_i915_private *dev_priv,
> wrpll = I915_READ(reg);
> switch (wrpll & WRPLL_REF_MASK) {
> case WRPLL_REF_SPECIAL_HSW:
> + /*
> + * muxed-SSC for BDW.
> + * non-SSC for non-ULT HSW. Check FUSE_STRAP3
> + * for the non-SSC reference frequency.
> + */
> + if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
> + if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> + refclk = 24;
> + else
> + refclk = 135;
> + break;
> + }
> + /* fall through */
> case WRPLL_REF_PCH_SSC:
> /*
>* We could calculate spread here, but our checking
> @@ -1243,7 +1256,7 @@ static int hsw_ddi_calc_wrpll_link(struct
> drm_i915_private *dev_priv,
> refclk = 2700;
> break;
> default:
> - WARN(1, "bad wrpll refclk\n");
> + MISSING_CASE(wrpll);
> return 0;
> }
>
Other patches look sane.
Reviewed-by: Maarten Lankhorst
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: Rename HSW/BDW PLL bits
Op 04-06-2019 om 22:09 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Give the PLL control register bits better names on HSW/BDW.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 37 ++-
> drivers/gpu/drm/i915/intel_ddi.c | 16 ++--
> drivers/gpu/drm/i915/intel_display.c | 8 +++---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +--
> 4 files changed, 39 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d5fee72fc079..b7dd42bfffaa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9465,24 +9465,33 @@ enum skl_power_gate {
> /* SPLL */
> #define SPLL_CTL _MMIO(0x46020)
> #define SPLL_PLL_ENABLE (1 << 31)
> -#define SPLL_PLL_SSC(1 << 28)
> -#define SPLL_PLL_NON_SSC(2 << 28)
> -#define SPLL_PLL_LCPLL (3 << 28)
> -#define SPLL_PLL_REF_MASK (3 << 28)
> -#define SPLL_PLL_FREQ_810MHz(0 << 26)
> -#define SPLL_PLL_FREQ_1350MHz (1 << 26)
> -#define SPLL_PLL_FREQ_2700MHz (2 << 26)
> -#define SPLL_PLL_FREQ_MASK (3 << 26)
> +#define SPLL_REF_BCLK (0 << 28)
> +#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled,
> PCH SSC otherwise */
> +#define SPLL_REF_NON_SSC_HSW(2 << 28)
> +#define SPLL_REF_PCH_SSC_BDW(2 << 28)
> +#define SPLL_REF_LCPLL (3 << 28)
> +#define SPLL_REF_MASK (3 << 28)
> +#define SPLL_REF_BCLK (0 << 28)
> +#define SPLL_REF_SSC(1 << 28)
> +#define SPLL_REF_NON_SSC(2 << 28)
> +#define SPLL_REF_LCPLL (3 << 28)
? Bit unclear or double definitions, at least of SPLL_REF_MASK.
> +#define SPLL_REF_MASK (3 << 28)
> +#define SPLL_FREQ_810MHz(0 << 26)
> +#define SPLL_FREQ_1350MHz (1 << 26)
> +#define SPLL_FREQ_2700MHz (2 << 26)
> +#define SPLL_FREQ_MASK (3 << 26)
>
> /* WRPLL */
> #define _WRPLL_CTL1 0x46040
> #define _WRPLL_CTL2 0x46060
> #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1,
> _WRPLL_CTL2)
> #define WRPLL_PLL_ENABLE(1 << 31)
> -#define WRPLL_PLL_SSC (1 << 28)
> -#define WRPLL_PLL_NON_SSC (2 << 28)
> -#define WRPLL_PLL_LCPLL (3 << 28)
> -#define WRPLL_PLL_REF_MASK (3 << 28)
> +#define WRPLL_REF_BCLK (0 << 28)
> +#define WRPLL_REF_PCH_SSC (1 << 28)
> +#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled,
> PCH SSC otherwise */
> +#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT),
> non-SSC (non-ULT) */
> +#define WRPLL_REF_LCPLL (3 << 28)
> +#define WRPLL_REF_MASK (3 << 28)
> /* WRPLL divider programming */
> #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
> #define WRPLL_DIVIDER_REF_MASK (0xff)
> @@ -9548,6 +9557,10 @@ enum skl_power_gate {
> #define LCPLL_CTL_MMIO(0x130040)
> #define LCPLL_PLL_DISABLE (1 << 31)
> #define LCPLL_PLL_LOCK (1 << 30)
> +#define LCPLL_REF_NON_SSC (0 << 28)
> +#define LCPLL_REF_BCLK (2 << 28)
> +#define LCPLL_REF_PCH_SSC (3 << 28)
> +#define LCPLL_REF_MASK (3 << 28)
> #define LCPLL_CLK_FREQ_MASK (3 << 26)
> #define LCPLL_CLK_FREQ_450 (0 << 26)
> #define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 350eaf54f01f..183f91abda19 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1231,9 +1231,9 @@ static int hsw_ddi_calc_wrpll_link(struct
> drm_i915_private *dev_priv,
> u32 wrpll;
>
> wrpll = I915_READ(reg);
> - switch (wrpll & WRPLL_PLL_REF_MASK) {
> - case WRPLL_PLL_SSC:
> - case WRPLL_PLL_NON_SSC:
> + switch (wrpll & WRPLL_REF_MASK) {
> + case WRPLL_REF_SPECIAL_HSW:
> + case WRPLL_REF_PCH_SSC:
> /*
>* We could calculate spread here, but our checking
>* code only cares about 5% accuracy, and spread is a max of
> @@ -1241,7 +1241,7 @@ static int hsw_ddi_calc_wrpll_link(struct
> drm_i915_private *dev_priv,
>*/
> refclk = 135;
> break;
> - case WRPLL_PLL_LCPLL:
> + case WRPLL_REF_LCPLL:
> refclk = LC_FREQ;
> break;
> default:
> @@ -1613,12 +1613,12 @@ static void hsw_ddi_clock_get(struct intel_encoder
> *encoder,
> link_cloc
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl (rev2)
== Series Details ==
Series: drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl (rev2)
URL : https://patchwork.freedesktop.org/series/61299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b69c7ced5090 drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit ea487835e887 ("drm: Enforce
unlocked ioctl operation for kms driver ioctls")'
#14:
commit ea487835e8876abf7ad909636e308c801a2bcda6
-:24: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit ed8b67040965 ("drm: convert
drm_ioctl to unlocked_ioctl")'
#24:
commit ed8b67040965e4fe695db333d5914e18ea5f146f
-:42: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 8f4ff2b06afc ("drm: do not sleep
on vblank while holding a mutex")'
#42:
commit 8f4ff2b06afcd6f151868474a432c603057eaf56
-:52: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit fdd5b877e9eb ("drm: Enforce
BKL-less ioctls for modern drivers")'
#52:
commit fdd5b877e9ebc2029e1373b4a3cd057329a9ab7a
-:231: WARNING:LONG_LINE: line over 100 characters
#231: FILE: drivers/gpu/drm/drm_ioctl.c:650:
+ DRM_IOCTL_DEF(DRM_IOCTL_PRIME_HANDLE_TO_FD,
drm_prime_handle_to_fd_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
-:231: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#231: FILE: drivers/gpu/drm/drm_ioctl.c:650:
+ DRM_IOCTL_DEF(DRM_IOCTL_PRIME_HANDLE_TO_FD,
drm_prime_handle_to_fd_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
^
-:232: WARNING:LONG_LINE: line over 100 characters
#232: FILE: drivers/gpu/drm/drm_ioctl.c:651:
+ DRM_IOCTL_DEF(DRM_IOCTL_PRIME_FD_TO_HANDLE,
drm_prime_fd_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
-:232: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#232: FILE: drivers/gpu/drm/drm_ioctl.c:651:
+ DRM_IOCTL_DEF(DRM_IOCTL_PRIME_FD_TO_HANDLE,
drm_prime_fd_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
^
-:335: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 4 errors, 3 warnings, 2 checks, 240 lines checked
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: Allow page pinning to be in the background
On Mon, 3 Jun 2019 at 18:49, Chris Wilson wrote:
>
> Assume that pages may be pinned in a background task and use a
> completion event to synchronise with callers that must access the pages
> immediately.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object.c| 1 +
> drivers/gpu/drm/i915/gem/i915_gem_object.h| 7 +--
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 3 ++
> drivers/gpu/drm/i915/gem/i915_gem_pages.c | 53 +++
> 4 files changed, 52 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 2702e060102e..2c5a02274170 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -79,6 +79,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
> obj->mm.madv = I915_MADV_WILLNEED;
> INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
> mutex_init(&obj->mm.get_page.lock);
> + init_completion(&obj->mm.completion);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index 7cb1871d7128..194e4fb6a259 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> @@ -240,7 +240,7 @@ int i915_gem_object_get_pages(struct
> drm_i915_gem_object *obj);
> int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
>
> static inline int __must_check
> -i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
> +i915_gem_object_pin_pages_async(struct drm_i915_gem_object *obj)
> {
> might_lock(&obj->mm.lock);
>
> @@ -250,6 +250,9 @@ i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
> return __i915_gem_object_get_pages(obj);
> }
>
> +int __must_check
> +i915_gem_object_pin_pages(struct drm_i915_gem_object *obj);
> +
> static inline bool
> i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
> {
> @@ -273,9 +276,7 @@ i915_gem_object_has_pinned_pages(struct
> drm_i915_gem_object *obj)
> static inline void
> __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
> {
> - GEM_BUG_ON(!i915_gem_object_has_pages(obj));
> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
> -
> atomic_dec(&obj->mm.pages_pin_count);
> }
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 41d2e7c8e332..615a59b927d6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -7,6 +7,7 @@
> #ifndef __I915_GEM_OBJECT_TYPES_H__
> #define __I915_GEM_OBJECT_TYPES_H__
>
> +#include
> #include
>
> #include
> @@ -211,6 +212,8 @@ struct drm_i915_gem_object {
> */
> struct list_head link;
>
> + struct completion completion;
> +
> /**
> * Advice: are the backing pages purgeable?
> */
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> index 7868dd48d931..68262231f56f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -72,21 +72,18 @@ void __i915_gem_object_set_pages(struct
> drm_i915_gem_object *obj,
>
> spin_unlock(&i915->mm.obj_lock);
> }
> +
> + complete_all(&obj->mm.completion);
> }
Worth having __i915_gem_object_set_pages_error(struct
drm_i915_gem_object, int err) at some point?
Reviewed-by: Matthew Auld
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915: Add windowing for primary planes on gen2/3 and chv
Op 31-05-2019 om 15:05 schreef Ville Syrjälä:
> On Thu, May 30, 2019 at 05:43:00AM -, Patchwork wrote:
>> == Series Details ==
>>
>> Series: series starting with [01/10] drm/i915: Add windowing for primary
>> planes on gen2/3 and chv
>> URL : https://patchwork.freedesktop.org/series/61345/
>> State : failure
>>
>> == Summary ==
>>
>> CI Bug Log - changes from CI_DRM_6165_full -> Patchwork_13133_full
>>
>>
>> Summary
>> ---
>>
>> **FAILURE**
>>
>> Serious unknown changes coming with Patchwork_13133_full absolutely need
>> to be
>> verified manually.
>>
>> If you think the reported changes have nothing to do with the changes
>> introduced in Patchwork_13133_full, please notify your bug team to allow
>> them
>> to document this new failure mode, which will reduce false positives in CI.
>>
>>
>>
>> Possible new issues
>> ---
>>
>> Here are the unknown changes that may have been introduced in
>> Patchwork_13133_full:
>>
>> ### IGT changes ###
>>
>> Possible regressions
>>
>> * igt@kms_plane@pixel-format-pipe-a-planes:
>> - shard-glk: [PASS][1] -> [FAIL][2]
>>[1]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-glk3/igt@kms_pl...@pixel-format-pipe-a-planes.html
>>[2]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-glk8/igt@kms_pl...@pixel-format-pipe-a-planes.html
> <7> [125.370679] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60
> 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
> ...
> <7> [125.542650] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200
> kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage
> level 4
> ...
> <7> [133.682144] [drm:skl_check_pipe_max_pixel_rate [i915]] Max supported
> pixel clock with scaling exceeded
>
> Max pixel rate for 64bpp is 79.2*2 * 8/9 = 140.8 Mhz, which we are
> exceeding. We'd need some way to bump the cdclk for this case, but
> the kernel will only do that for modesets, and it won't account for
> that 8/9 factor. Not sure there is a great way to handle these sorts
> of cases.
>
>> * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
>> - shard-apl: [PASS][3] -> [FAIL][4] +4 similar issues
>>[3]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-apl5/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html
>>[4]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-apl7/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html
> <7> [1749.831610] [drm:drm_atomic_helper_check_plane_state] Invalid scaling
> of plane
> <7> [1749.831620] [drm:drm_rect_debug_print] src:
> 8.00x8.00+0.00+0.00
> <7> [1749.831625] [drm:drm_rect_debug_print] dst: 1920x1080+0+0
>
> Not quite sure what's going on here. Unfortunately the debugs don't have
> enough information to see what's going on.
For first 6 patches
Reviewed-by: Maarten Lankhorst
What happens on < gen9 btw with half float support?
Enabling patches look sane, but worried about hw coverage.
So if you are sure it works on >
>> Suppressed
>>
>> The following results come from untrusted machines, tests, or statuses.
>> They do not affect the overall result.
>>
>> * igt@gem_workarounds@suspend-resume-context:
>> - {shard-iclb}: [PASS][5] -> [FAIL][6] +1 similar issue
>>[5]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-iclb3/igt@gem_workarou...@suspend-resume-context.html
>>[6]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-iclb2/igt@gem_workarou...@suspend-resume-context.html
>>
>>
>> Known issues
>>
>>
>> Here are the changes found in Patchwork_13133_full that come from known
>> issues:
>>
>> ### IGT changes ###
>>
>> Issues hit
>>
>> * igt@gem_ctx_switch@basic-all-heavy:
>> - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([fdo#103540])
>>[7]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-hsw5/igt@gem_ctx_swi...@basic-all-heavy.html
>>[8]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-hsw1/igt@gem_ctx_swi...@basic-all-heavy.html
>>
>> * igt@i915_pm_rc6_residency@rc6-accuracy:
>> - shard-kbl: [PASS][9] -> [SKIP][10] ([fdo#109271])
>>[9]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-kbl3/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>>[10]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-kbl2/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>> - shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271])
>>[11]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-snb7/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>>[12]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-snb6/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>>
>> * igt@i915_suspend@fence-restore-untiled:
>> - shard-apl: [PASS
[Intel-gfx] [PATCH v4 6/7] drm/i915/perf: allow holding preemption on filtered ctx
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of command buffer concept meant that
queries' duration could span multiple command buffers.
With that restriction gone in Vulkan, we would like to simplify
measuring performance just by measuring the deltas between the counter
snapshots written by 2 MI_RECORD_PERF_COUNT commands, rather than the
more complex scheme we currently have in the GL driver, using 2
MI_RECORD_PERF_COUNT commands and doing some post processing on the
stream of OA reports, coming from the global OA buffer, to remove any
unrelated deltas in between the 2 MI_RECORD_PERF_COUNT.
Disabling preemption only apply to a single context with which want to
query performance counters for and is considered a privileged
operation, by default protected by CAP_SYS_ADMIN. It is possible to
enable it for a normal user by disabling the paranoid stream setting.
v2: Store preemption setting in intel_context (Chris)
v3: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 13
drivers/gpu/drm/i915/i915_perf.c| 22 +++--
drivers/gpu/drm/i915/i915_priolist_types.h | 7 +++
drivers/gpu/drm/i915/i915_request.c | 1 +
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/intel_guc_submission.c | 10 +-
include/uapi/drm/i915_drm.h | 11 +++
9 files changed, 69 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index ed19f4e53d31..b32b04b268eb 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -233,7 +233,12 @@ static inline int rq_prio(const struct i915_request *rq)
static int effective_prio(const struct i915_request *rq)
{
- int prio = rq_prio(rq);
+ int prio;
+
+ if (rq->has_perf)
+ prio = I915_USER_PRIORITY(I915_PRIORITY_PERF);
+ else
+ prio = rq_prio(rq);
/*
* On unwinding the active request, we give it a priority bump
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 75029d1a3802..984b76a09cfa 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -476,7 +476,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
break;
case I915_PARAM_PERF_REVISION:
- value = 1;
+ value = 2;
break;
case I915_PARAM_HAS_EXEC_PERF_CONFIG:
/* Obviously requires perf support. */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7b82bb85e45d..1cb41f398c05 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1292,6 +1292,19 @@ struct i915_perf_stream {
*/
bool enabled;
+ /**
+* @hold_preemption: Whether preemption is put on hold for command
+* submissions done on the @ctx. This is useful for some drivers that
+* cannot easily post process the OA buffer context to subtract delta
+* of performance counters not associated with @ctx.
+*/
+ bool hold_preemption;
+
+ /**
+* @last_config_request
+*/
+ struct i915_request *last_config_request;
+
/**
* @ops: The callbacks providing the implementation of this specific
* type of configured stream.
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 4e69266bba61..0755746d416e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -343,6 +343,8 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* struct perf_open_properties - for validated properties given to open a
stream
* @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
* @single_context: Whether a single or all gpu contexts should be monitored
+ * @hold_preemption: Whether the preemption is disabled for the filtered
+ * context
* @ctx_handle: A gem ctx handle for use with @single_context
* @metrics_set: An ID for an OA unit metric set advertised via sysfs
* @oa_format: An OA unit HW report format
@@ -357,6 +359,7 @@ struct perf_open_properties {
u32 sample_flags;
u64 single_context:1;
+ u64 hold_preemption:1;
u64 ctx_handle;
[Intel-gfx] [PATCH v4 1/7] drm/i915/perf: introduce a versioning of the i915-perf uapi
Reporting this version will help application figure out what level of
the support the running kernel provides.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
include/uapi/drm/i915_drm.h | 21 +
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1af6751e1b36..9ed4d0016ee1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -474,6 +474,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
case I915_PARAM_MMAP_GTT_COHERENT:
value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
break;
+ case I915_PARAM_PERF_REVISION:
+ value = 1;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 328d05e77d9f..e27a8eda9121 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -610,6 +610,13 @@ typedef struct drm_i915_irq_wait {
* See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
*/
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
+
+/*
+ * Revision of the i915-perf uAPI. The value returned helps determine what
+ * i915-perf features are available. See drm_i915_perf_property_id.
+ */
+#define I915_PARAM_PERF_REVISION 54
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1843,23 +1850,31 @@ enum drm_i915_perf_property_id {
* Open the stream for a specific context handle (as used with
* execbuffer2). A stream opened for a specific context this way
* won't typically require root privileges.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_CTX_HANDLE = 1,
/**
* A value of 1 requests the inclusion of raw OA unit reports as
* part of stream samples.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
* The value specifies which set of OA unit metrics should be
* be configured, defining the contents of any OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_METRICS_SET,
/**
* The value specifies the size and layout of OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_FORMAT,
@@ -1869,6 +1884,8 @@ enum drm_i915_perf_property_id {
* from this exponent as follows:
*
* 80ns * 2^(period_exponent + 1)
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
@@ -1900,6 +1917,8 @@ struct drm_i915_perf_open_param {
* to close and re-open a stream with the same configuration.
*
* It's undefined whether any pending data for the stream will be lost.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
@@ -1907,6 +1926,8 @@ struct drm_i915_perf_open_param {
* Disable data capture for a stream.
*
* It is an error to try and read a stream that is disabled.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_DISABLE_IO('i', 0x1)
--
2.21.0.392.gf8f6787159e
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 3/7] drm/i915: introduce a mechanism to extend execbuf2
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 30 ++-
include/uapi/drm/i915_drm.h | 25 ++--
2 files changed, 51 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ed522fdfbe7f..a961fab70fb2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -20,6 +20,7 @@
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_trace.h"
+#include "i915_user_extensions.h"
#include "intel_drv.h"
#include "intel_frontbuffer.h"
@@ -269,6 +270,10 @@ struct i915_execbuffer {
*/
int lut_size;
struct hlist_head *buckets; /** ht for relocation handles */
+
+ struct {
+ u64 flags; /** Available extensions parameters */
+ } extensions;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -1958,7 +1963,7 @@ static bool i915_gem_check_execbuffer(struct
drm_i915_gem_execbuffer2 *exec)
return false;
/* Kernel clipping was a DRI1 misfeature */
- if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
+ if (!(exec->flags & (I915_EXEC_FENCE_ARRAY | I915_EXEC_EXT))) {
if (exec->num_cliprects || exec->cliprects_ptr)
return false;
}
@@ -2336,6 +2341,22 @@ signal_fence_array(struct i915_execbuffer *eb,
}
}
+static const i915_user_extension_fn execbuf_extensions[] = {
+};
+
+static int
+parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
+ struct i915_execbuffer *eb)
+{
+ if (args->num_cliprects != 0)
+ return -EINVAL;
+
+ return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
+ execbuf_extensions,
+ ARRAY_SIZE(execbuf_extensions),
+ eb);
+}
+
static int
i915_gem_do_execbuffer(struct drm_device *dev,
struct drm_file *file,
@@ -2382,6 +2403,13 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (args->flags & I915_EXEC_IS_PINNED)
eb.batch_flags |= I915_DISPATCH_PINNED;
+ eb.extensions.flags = 0;
+ if (args->flags & I915_EXEC_EXT) {
+ err = parse_execbuf2_extensions(args, &eb);
+ if (err)
+ return err;
+ }
+
if (args->flags & I915_EXEC_FENCE_IN) {
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
if (!in_fence)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e27a8eda9121..efa195d6994e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1013,6 +1013,10 @@ struct drm_i915_gem_exec_fence {
__u32 flags;
};
+enum drm_i915_gem_execbuffer_ext {
+ DRM_I915_GEM_EXECBUFFER_EXT_MAX /* non-ABI */
+};
+
struct drm_i915_gem_execbuffer2 {
/**
* List of gem_exec_object2 structs
@@ -1029,8 +1033,14 @@ struct drm_i915_gem_execbuffer2 {
__u32 num_cliprects;
/**
* This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
-* is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
-* struct drm_i915_gem_exec_fence *fences.
+* & I915_EXEC_EXT are not set.
+*
+* If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
+* of struct drm_i915_gem_exec_fence and num_cliprects is the length
+* of the array.
+*
+* If I915_EXEC_EXT is set, then this is a pointer to a single struct
+* drm_i915_gem_base_execbuffer_ext and num_cliprects is 0.
*/
__u64 cliprects_ptr;
#define I915_EXEC_RING_MASK (0x3f)
@@ -1148,7 +1158,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_SUBMIT (1 << 20)
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
+/*
+ * Setting I915_EXEC_EXT implies that drm_i915_gem_execbuffer2.cliprects_ptr
+ * is treated as a pointer to an linked list of i915_user_extension. Each
+ * i915_user_extension node is the base of a larger structure. The list of
+ * supported structures are listed in the drm_i915_gem_execbuffer_ext
+ * enum.
+ */
+#define I915_EXEC_EXT (1 << 21)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_EXT<<1))
#define I915_EXEC_CONTEXT_ID_MASK (0x)
#define i915_execbuffer2_set_context_id(eb2, context) \
--
2.21.0.392.gf8f6787159e
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 7/7] drm/i915: add support for perf configuration queries
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_perf.c | 4 +
drivers/gpu/drm/i915/i915_query.c | 279 ++
include/uapi/drm/i915_drm.h | 62 ++-
4 files changed, 350 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1cb41f398c05..eb34d7cb857e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1793,6 +1793,12 @@ struct drm_i915_private {
*/
struct list_head metrics_buffers;
+ /*
+* Number of dynamic configurations, you need to hold
+* dev_priv->perf.metrics_lock to access it.
+*/
+ u32 n_metrics;
+
/*
* Lock associated with anything below within this structure
* except exclusive_stream.
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0755746d416e..4a767087de27 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3417,6 +3417,8 @@ int i915_perf_add_config_ioctl(struct drm_device *dev,
void *data,
goto sysfs_err;
}
+ dev_priv->perf.n_metrics++;
+
mutex_unlock(&dev_priv->perf.metrics_lock);
DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id);
@@ -3478,6 +3480,8 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev,
void *data,
idr_remove(&dev_priv->perf.metrics_idr, *arg);
+ dev_priv->perf.n_metrics--;
+
DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
i915_oa_config_put(oa_config);
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index 7b7016171057..c1e203c7b2c2 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -143,10 +143,289 @@ query_engine_info(struct drm_i915_private *i915,
return len;
}
+static int can_copy_perf_config_registers_or_number(u32 user_n_regs,
+ u64 user_regs_ptr,
+ u32 kernel_n_regs)
+{
+ /*
+* We'll just put the number of registers, and won't copy the
+* register.
+*/
+ if (user_n_regs == 0)
+ return 0;
+
+ if (user_n_regs < kernel_n_regs)
+ return -EINVAL;
+
+ if (!access_ok(u64_to_user_ptr(user_regs_ptr),
+ 2 * sizeof(u32) * kernel_n_regs))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int copy_perf_config_registers_or_number(const struct i915_oa_reg
*kernel_regs,
+ u32 kernel_n_regs,
+ u64 user_regs_ptr,
+ u32 *user_n_regs)
+{
+ u32 r;
+
+ if (*user_n_regs == 0) {
+ *user_n_regs = kernel_n_regs;
+ return 0;
+ }
+
+ *user_n_regs = kernel_n_regs;
+
+ for (r = 0; r < kernel_n_regs; r++) {
+ u32 __user *user_reg_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2);
+ u32 __user *user_val_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2 +
+ sizeof(u32));
+ int ret;
+
+ ret = __put_user(i915_mmio_reg_offset(kernel_regs[r].addr),
+user_reg_ptr);
+ if (ret)
+ return -EFAULT;
+
+ ret = __put_user(kernel_regs[r].value, user_val_ptr);
+ if (ret)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
+{
+ struct drm_i915_query_perf_config __user *user_query_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_perf_oa_config __user *user_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr +
+ sizeof(struct drm_i915_query_perf_config));
+ struct drm_i915_perf_o
[Intel-gfx] [PATCH v4 4/7] drm/i915: add syncobj timeline support
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 279 ++
drivers/gpu/drm/i915/i915_drv.c | 4 +-
include/uapi/drm/i915_drm.h | 37 +++
3 files changed, 263 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index a961fab70fb2..86864ec76a8b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -211,6 +211,13 @@ enum {
* the batchbuffer in trusted mode, otherwise the ioctl is rejected.
*/
+struct i915_drm_dma_fences {
+ struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
+ struct dma_fence *dma_fence;
+ u64 value;
+ struct dma_fence_chain *chain_fence;
+};
+
struct i915_execbuffer {
struct drm_i915_private *i915; /** i915 backpointer */
struct drm_file *file; /** per-file lookup tables and limits */
@@ -273,6 +280,7 @@ struct i915_execbuffer {
struct {
u64 flags; /** Available extensions parameters */
+ struct drm_i915_gem_execbuffer_ext_timeline_fences
timeline_fences;
} extensions;
};
@@ -2213,67 +2221,193 @@ eb_select_engine(struct i915_execbuffer *eb,
}
static void
-__free_fence_array(struct drm_syncobj **fences, unsigned int n)
+__free_fence_array(struct i915_drm_dma_fences *fences, unsigned int n)
{
- while (n--)
- drm_syncobj_put(ptr_mask_bits(fences[n], 2));
+ while (n--) {
+ drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
+ dma_fence_put(fences[n].dma_fence);
+ kfree(fences[n].chain_fence);
+ }
kvfree(fences);
}
-static struct drm_syncobj **
-get_fence_array(struct drm_i915_gem_execbuffer2 *args,
- struct drm_file *file)
+static struct i915_drm_dma_fences *
+get_timeline_fence_array(struct i915_execbuffer *eb, int *out_n_fences)
+{
+ struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences =
+ &eb->extensions.timeline_fences;
+ struct drm_i915_gem_exec_fence __user *user_fences;
+ struct i915_drm_dma_fences *fences;
+ u64 __user *user_values;
+ unsigned long n;
+ int err;
+
+ *out_n_fences = timeline_fences->handle_count;
+
+ /* Check multiplication overflow for access_ok() and kvmalloc_array() */
+ BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
+ if (*out_n_fences > min_t(unsigned long,
+ ULONG_MAX / sizeof(*user_fences),
+ SIZE_MAX / sizeof(*fences)))
+ return ERR_PTR(-EINVAL);
+
+ user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
+ if (!access_ok(user_fences, *out_n_fences * sizeof(*user_fences)))
+ return ERR_PTR(-EFAULT);
+
+ user_values = u64_to_user_ptr(timeline_fences->values_ptr);
+ if (!access_ok(user_values, *out_n_fences * sizeof(*user_values)))
+ return ERR_PTR(-EFAULT);
+
+ fences = kvmalloc_array(*out_n_fences, sizeof(*fences),
+ __GFP_NOWARN | GFP_KERNEL);
+ if (!fences)
+ return ERR_PTR(-ENOMEM);
+
+ BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
+~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
+
+ for (n = 0; n < *out_n_fences; n++) {
+ struct drm_i915_gem_exec_fence user_fence;
+ struct drm_syncobj *syncobj;
+ struct dma_fence *fence = NULL;
+ u64 point;
+
+ if (__copy_from_user(&user_fence, user_fences++,
sizeof(user_fence))) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
+ err = -EINVAL;
+ goto err;
+ }
+
+ if (__get_user(point, user_values++)) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ syncobj = drm_syncobj_find(eb->file, user_fence.handle);
+ if (!syncobj) {
+ DRM_DEBUG("Invalid syncobj handle provided\n");
+ err = -EINVAL;
+ goto err;
+ }
+
+ if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
+ fence = drm_syncobj_fence_get(syncobj);
+ if (!fence) {
+ DRM_DEBUG("Syncobj handle has no fence\n");
+ drm_syncobj_put(syncobj);
+ err = -EINVAL;
+ goto err;
+ }
+
+
[Intel-gfx] [PATCH v4 5/7] drm/i915: add a new perf configuration execbuf parameter
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process making the execbuf with this flag to
also own the perf fd at the time of execbuf.
v2: Add a emit_oa_config() vfunc in the intel_engine_cs (Chris)
Move oa_config vma to active (Chris)
v3: Don't drop the lock for engine lookup (Chris)
Move OA config vma to active before writing the ringbuffer (Chris)
v4: Reuse i915_user_extension_fn
Serialize requests with OA config updates
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 130 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 4 +-
drivers/gpu/drm/i915/i915_drv.c | 4 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_perf.c | 26 ++--
include/uapi/drm/i915_drm.h | 37 +
9 files changed, 208 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 86864ec76a8b..dc7e765edf4b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -281,7 +281,11 @@ struct i915_execbuffer {
struct {
u64 flags; /** Available extensions parameters */
struct drm_i915_gem_execbuffer_ext_timeline_fences
timeline_fences;
+ struct drm_i915_gem_execbuffer_ext_perf perf_config;
} extensions;
+
+ struct i915_oa_config *oa_config; /** HW configuration for OA, NULL is
not needed. */
+ struct drm_i915_gem_object *oa_bo;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -1199,6 +1203,34 @@ static int reloc_move_to_gpu(struct i915_request *rq,
struct i915_vma *vma)
return err;
}
+
+static int
+get_execbuf_oa_config(struct drm_i915_private *dev_priv,
+ s32 perf_fd, u64 oa_config_id,
+ struct i915_oa_config **out_oa_config,
+ struct drm_i915_gem_object **out_oa_obj)
+{
+ struct file *perf_file;
+ int ret;
+
+ if (!dev_priv->perf.oa.exclusive_stream)
+ return -EINVAL;
+
+ perf_file = fget(perf_fd);
+ if (!perf_file)
+ return -EINVAL;
+
+ if (perf_file->private_data != dev_priv->perf.oa.exclusive_stream)
+ return -EINVAL;
+
+ fput(perf_file);
+
+ ret = i915_perf_get_oa_config(dev_priv, oa_config_id,
+ out_oa_config, out_oa_obj);
+
+ return ret;
+}
+
static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
struct i915_vma *vma,
unsigned int len)
@@ -2061,6 +2093,64 @@ add_to_client(struct i915_request *rq, struct drm_file
*file)
list_add_tail(&rq->client_link, &rq->file_priv->mm.request_list);
}
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ struct i915_vma *oa_vma;
+ int err;
+
+ if (!eb->oa_config)
+ return 0;
+
+ err = i915_active_request_set(&eb->engine->last_oa_config,
+ eb->request);
+ if (err)
+ return err;
+
+ /*
+* If the perf stream was opened with hold preemption, flag the
+* request properly so that the priority of the request is bumped once
+* it reaches the execlist ports.
+*/
+ if (eb->i915->perf.oa.exclusive_stream->hold_preemption)
+ eb->request->has_perf = true;
+
+ /*
+* If the config hasn't changed, skip reconfiguring the HW (this is
+* subject to a delay we want to avoid has much as possible).
+*/
+ if (eb->oa_config == eb->i915->perf.oa.exclusive_stream->oa_config)
+ return 0;
+
+ oa_vma = i915_vma_instance(eb->oa_bo,
+ &eb->engine->i915->ggtt.vm, NULL);
+ if (unlikely(IS_ERR(oa_vma)))
+ return PTR_ERR(oa_vma);
+
+ err = i915_vma_pin(oa_vma, 0, 0, PIN_GLOBAL);
+ if (err)
+ return err;
+
+ err = i915_vma_move_to_active(oa_vma, eb->request, 0);
+ if (err) {
+ i915_vma_unpin(oa_vma);
+ return err;
+ }
+
+ err = eb->engine->emit_bb_start(eb->request,
+ oa_vma->node.start,
+ 0, I915_DISPATCH_SECURE);
+ if (err) {
+ i915_vma_unpin(oa_vma);
+ return err;
+ }
+
+ i915_vma_unpin(oa_vm
[Intel-gfx] [PATCH v4 0/7] drm/i915: Vulkan performance query support
Hi all, Here is a list of changes in this iteration : - Reuse i915_user_extension_fn - Serialize OA configuration updates - Report the perf priority through the effective_prio() helper rather than updating the value Cheers, Lionel Landwerlin (7): drm/i915/perf: introduce a versioning of the i915-perf uapi drm/i915/perf: allow for CS OA configs to be created lazily drm/i915: introduce a mechanism to extend execbuf2 drm/i915: add syncobj timeline support drm/i915: add a new perf configuration execbuf parameter drm/i915/perf: allow holding preemption on filtered ctx drm/i915: add support for perf configuration queries .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 439 +++--- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 8 +- drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 4 +- drivers/gpu/drm/i915/i915_drv.c | 11 +- drivers/gpu/drm/i915/i915_drv.h | 51 +- drivers/gpu/drm/i915/i915_perf.c | 203 ++-- drivers/gpu/drm/i915/i915_priolist_types.h| 7 + drivers/gpu/drm/i915/i915_query.c | 279 +++ drivers/gpu/drm/i915/i915_request.c | 1 + drivers/gpu/drm/i915/i915_request.h | 1 + drivers/gpu/drm/i915/intel_guc_submission.c | 10 +- include/uapi/drm/i915_drm.h | 193 +++- 15 files changed, 1116 insertions(+), 103 deletions(-) -- 2.21.0.392.gf8f6787159e ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/7] drm/i915/perf: allow for CS OA configs to be created lazily
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particular user batchbuffer be
executed with a given OA configuration.
This mechanism essentially allows the userspace driver to go through
several OA configuration without having to open/close the i915/perf
stream.
v2: No need for locking on object OA config object creation (Chris)
Flush cpu mapping of OA config (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 22 ++-
drivers/gpu/drm/i915/i915_perf.c | 171 +++
3 files changed, 162 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index eec31e36aca7..e7eff9db343e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -126,6 +126,7 @@
*/
#define MI_LOAD_REGISTER_IMM(x)MI_INSTR(0x22, 2*(x)-1)
#define MI_LRI_FORCE_POSTED (1<<12)
+#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT(1<<22)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89bf1e34feaa..83a32e9d86b5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1170,6 +1170,10 @@ struct i915_oa_config {
struct attribute *attrs[2];
struct device_attribute sysfs_metric_id;
+ struct drm_i915_gem_object *obj;
+
+ struct list_head vma_link;
+
atomic_t ref_count;
};
@@ -1759,11 +1763,21 @@ struct drm_i915_private {
struct mutex metrics_lock;
/*
-* List of dynamic configurations, you need to hold
-* dev_priv->perf.metrics_lock to access it.
+* List of dynamic configurations (struct i915_oa_config), you
+* need to hold dev_priv->perf.metrics_lock to access it.
*/
struct idr metrics_idr;
+ /*
+* List of dynamic configurations (struct i915_oa_config)
+* which have an allocated buffer in GGTT for reconfiguration,
+* you need to hold dev_priv->perf.metrics_lock to access it.
+* Elements are added to the list lazilly on execbuf (when a
+* particular configuration is requested). The list is freed
+* upon closing the perf stream.
+*/
+ struct list_head metrics_buffers;
+
/*
* Lock associated with anything below within this structure
* except exclusive_stream.
@@ -2709,6 +2723,10 @@ int i915_perf_remove_config_ioctl(struct drm_device
*dev, void *data,
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
struct intel_context *ce,
u32 *reg_state);
+int i915_perf_get_oa_config(struct drm_i915_private *i915,
+ int metrics_set,
+ struct i915_oa_config **out_config,
+ struct drm_i915_gem_object **out_obj);
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2e33a9b4eae7..e0071e44de3d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -366,9 +366,16 @@ struct perf_open_properties {
int oa_period_exponent;
};
-static void free_oa_config(struct drm_i915_private *dev_priv,
- struct i915_oa_config *oa_config)
+static void put_oa_config(struct i915_oa_config *oa_config)
{
+ if (!atomic_dec_and_test(&oa_config->ref_count))
+ return;
+
+ if (oa_config->obj) {
+ list_del(&oa_config->vma_link);
+ i915_gem_object_put(oa_config->obj);
+ }
+
if (!PTR_ERR(oa_config->flex_regs))
kfree(oa_config->flex_regs);
if (!PTR_ERR(oa_config->b_counter_regs))
@@ -378,38 +385,126 @@ static void free_oa_config(struct drm_i915_private
*dev_priv,
kfree(oa_config);
}
-static void put_oa_config(struct drm_i915_private *dev_priv,
- struct i915_oa_config *oa_config)
+static u32 *write_cs_mi_lri(u32 *cs, const struct i915_oa_reg *reg_data, u32
n_regs)
{
- if (!atomic_dec_and_test(&oa_config->ref_count))
- return;
+ u32 i;
- free_oa_config(dev_priv, oa_config);
+ for (i = 0; i < n_regs; i++)
Re: [Intel-gfx] [PATCH] drm/i915: rename header test build commands to avoid conflicts
Hi Jani. On Wed, Jun 05, 2019 at 04:21:37PM +0300, Jani Nikula wrote: > We have a local hack to test if headers are self-contained, while > upstreaming a proper generic solution in kbuild [1]. Now that both have > found themselves in linux-next, the identical cmd_header_test build > commands conflict, leading to errors such as: > > >> drivers/gpu/drm/i915/header_test_intel_audio.c:1:10: fatal error: > >> drivers/gpu/drm/i915/intel_audio.h: No such file or directory > #include "drivers/gpu/drm/i915/intel_audio.h" >^~~~ > > Rename the i915 local build command until the proper kbuild solution > finds its way to Linus' master and gets backported to our tree, and we > can finally switch over. You could also ihave switched over now, and accpet that this only would be used in -next for a few months. Then at least you did not have to rememebr to change it again. Any way works for me, just a suggestion. Sam ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: rename header test build commands to avoid conflicts
We have a local hack to test if headers are self-contained, while upstreaming a proper generic solution in kbuild [1]. Now that both have found themselves in linux-next, the identical cmd_header_test build commands conflict, leading to errors such as: >> drivers/gpu/drm/i915/header_test_intel_audio.c:1:10: fatal error: >> drivers/gpu/drm/i915/intel_audio.h: No such file or directory #include "drivers/gpu/drm/i915/intel_audio.h" ^~~~ Rename the i915 local build command until the proper kbuild solution finds its way to Linus' master and gets backported to our tree, and we can finally switch over. Note that since the kbuild header test requires CONFIG_HEADER_TEST=y, and our hack requires our debug option CONFIG_DRM_I915_WERROR=y, this is likely hit only by build test bots. [1] http://marc.info/?i=20190604124248.5564-1-jani.nik...@intel.com Reported-by: kbuild test robot Cc: Chris Wilson Cc: Masahiro Yamada Cc: Sam Ravnborg Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/Makefile.header-test | 6 +++--- drivers/gpu/drm/i915/gem/Makefile.header-test | 6 +++--- drivers/gpu/drm/i915/gt/Makefile.header-test | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/Makefile.header-test b/drivers/gpu/drm/i915/Makefile.header-test index 6ef3b647ac65..1b4537405b4b 100644 --- a/drivers/gpu/drm/i915/Makefile.header-test +++ b/drivers/gpu/drm/i915/Makefile.header-test @@ -63,11 +63,11 @@ header_test := \ intel_vdsc.h \ intel_wakeref.h -quiet_cmd_header_test = HDRTEST $@ - cmd_header_test = echo "\#include \"$( $@ +quiet_cmd_i915_header_test = HDRTEST $@ + cmd_i915_header_test = echo "\#include \"$( $@ header_test_%.c: %.h - $(call cmd,header_test) + $(call cmd,i915_header_test) i915-$(CONFIG_DRM_I915_WERROR) += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h))) diff --git a/drivers/gpu/drm/i915/gem/Makefile.header-test b/drivers/gpu/drm/i915/gem/Makefile.header-test index 61e06cbb4b32..50a3aa983659 100644 --- a/drivers/gpu/drm/i915/gem/Makefile.header-test +++ b/drivers/gpu/drm/i915/gem/Makefile.header-test @@ -4,11 +4,11 @@ # Test the headers are compilable as standalone units header_test := $(notdir $(wildcard $(src)/*.h)) -quiet_cmd_header_test = HDRTEST $@ - cmd_header_test = echo "\#include \"$( $@ +quiet_cmd_i915_header_test = HDRTEST $@ + cmd_i915_header_test = echo "\#include \"$( $@ header_test_%.c: %.h - $(call cmd,header_test) + $(call cmd,i915_header_test) extra-$(CONFIG_DRM_I915_WERROR) += \ $(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h))) diff --git a/drivers/gpu/drm/i915/gt/Makefile.header-test b/drivers/gpu/drm/i915/gt/Makefile.header-test index 61e06cbb4b32..50a3aa983659 100644 --- a/drivers/gpu/drm/i915/gt/Makefile.header-test +++ b/drivers/gpu/drm/i915/gt/Makefile.header-test @@ -4,11 +4,11 @@ # Test the headers are compilable as standalone units header_test := $(notdir $(wildcard $(src)/*.h)) -quiet_cmd_header_test = HDRTEST $@ - cmd_header_test = echo "\#include \"$( $@ +quiet_cmd_i915_header_test = HDRTEST $@ + cmd_i915_header_test = echo "\#include \"$( $@ header_test_%.c: %.h - $(call cmd,header_test) + $(call cmd,i915_header_test) extra-$(CONFIG_DRM_I915_WERROR) += \ $(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h))) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: fix documentation build warnings
Jani Nikula writes: > Just a straightforward bag of fixes for a clean htmldocs build. > > Signed-off-by: Jani Nikula Reviewed-by: Mika Kuoppala
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] Documentation/i915: Fix kernel-doc references to moved gem files
== Series Details ==
Series: series starting with [1/2] Documentation/i915: Fix kernel-doc
references to moved gem files
URL : https://patchwork.freedesktop.org/series/61645/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6194 -> Patchwork_13177
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/
Known issues
Here are the changes found in Patchwork_13177 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_basic@basic-all:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/fi-icl-u2/igt@gem_exec_ba...@basic-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/fi-icl-u2/igt@gem_exec_ba...@basic-all.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/fi-blb-e6850/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/fi-blb-e6850/igt@i915_module_l...@reload.html
Possible fixes
* igt@gem_ctx_switch@basic-default:
- {fi-icl-guc}: [INCOMPLETE][5] ([fdo#107713] / [fdo#108569]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/fi-icl-guc/igt@gem_ctx_swi...@basic-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/fi-icl-guc/igt@gem_ctx_swi...@basic-default.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#109485]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6194/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (49 -> 46)
--
Additional (5): fi-kbl-7567u fi-skl-gvtdvm fi-byt-j1900 fi-icl-u3
fi-skl-6600u
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6194 -> Patchwork_13177
CI_DRM_6194: 10a75edfc43885387e1e9e2bc50f9678e9bf59d6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5038: a34cbc9834aed017d1a452ba42d3e53f9258f8d2 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13177: 8d6b14e486a1afd738663c23ea4f2bc00dfbaf4f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8d6b14e486a1 drm/i915: fix documentation build warnings
8e81a681b8ce Documentation/i915: Fix kernel-doc references to moved gem files
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13177/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/13] drm/i915/bios: make child device order the priority order
On Fri, 31 May 2019, Ville Syrjälä wrote:
> On Fri, May 31, 2019 at 04:14:51PM +0300, Jani Nikula wrote:
>> Make the child device order the priority order in sanitizing DDC pin and
>> AUX CH. First come, first served.
>>
>> Cc: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_bios.c | 32 +++
>> 1 file changed, 15 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index a0b708f7f384..0a1b9a4a1b71 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -1242,8 +1242,7 @@ static u8 translate_iboost(u8 val)
>> static void sanitize_ddc_pin(struct drm_i915_private *dev_priv,
>> enum port port)
>> {
>> -const struct ddi_vbt_port_info *info =
>> -&dev_priv->vbt.ddi_port_info[port];
>> +struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
>> enum port p;
>>
>> if (!info->alternate_ddc_pin)
>> @@ -1258,8 +1257,8 @@ static void sanitize_ddc_pin(struct drm_i915_private
>> *dev_priv,
>>
>> DRM_DEBUG_KMS("port %c trying to use the same DDC pin (0x%x) as
>> port %c, "
>>"disabling port %c DVI/HDMI support\n",
>> - port_name(p), i->alternate_ddc_pin,
>> - port_name(port), port_name(p));
>> + port_name(port), info->alternate_ddc_pin,
>> + port_name(p), port_name(port));
>>
>> /*
>> * If we have multiple ports supposedly sharing the
>> @@ -1267,20 +1266,19 @@ static void sanitize_ddc_pin(struct drm_i915_private
>> *dev_priv,
>> * port. Otherwise they share the same ddc bin and
>> * system couldn't communicate with them separately.
>> *
>> - * Due to parsing the ports in child device order,
>> - * a later device will always clobber an earlier one.
>> + * Give child device order the priority, first come first
>> + * served.
>> */
>> -i->supports_dvi = false;
>> -i->supports_hdmi = false;
>> -i->alternate_ddc_pin = 0;
>> +info->supports_dvi = false;
>> +info->supports_hdmi = false;
>> +info->alternate_ddc_pin = 0;
>
> 'i' can now be const I think.
I ignored that because 'i' gets removed a couple of patches later
anyway.
>
> Series is
> Reviewed-by: Ville Syrjälä
>
> Though I only glanced at the header reorganization things instead
> of reading through it all in detail.
Thanks, pushed the lot.
BR,
Jani.
>
>> }
>> }
>>
>> static void sanitize_aux_ch(struct drm_i915_private *dev_priv,
>> enum port port)
>> {
>> -const struct ddi_vbt_port_info *info =
>> -&dev_priv->vbt.ddi_port_info[port];
>> +struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
>> enum port p;
>>
>> if (!info->alternate_aux_channel)
>> @@ -1295,8 +1293,8 @@ static void sanitize_aux_ch(struct drm_i915_private
>> *dev_priv,
>>
>> DRM_DEBUG_KMS("port %c trying to use the same AUX CH (0x%x) as
>> port %c, "
>>"disabling port %c DP support\n",
>> - port_name(p), i->alternate_aux_channel,
>> - port_name(port), port_name(p));
>> + port_name(port), info->alternate_aux_channel,
>> + port_name(p), port_name(port));
>>
>> /*
>> * If we have multiple ports supposedlt sharing the
>> @@ -1304,11 +1302,11 @@ static void sanitize_aux_ch(struct drm_i915_private
>> *dev_priv,
>> * port. Otherwise they share the same aux channel
>> * and system couldn't communicate with them separately.
>> *
>> - * Due to parsing the ports in child device order,
>> - * a later device will always clobber an earlier one.
>> + * Give child device order the priority, first come first
>> + * served.
>> */
>> -i->supports_dp = false;
>> -i->alternate_aux_channel = 0;
>> +info->supports_dp = false;
>> +info->alternate_aux_channel = 0;
>> }
>> }
>>
>> --
>> 2.20.1
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Vulkan performance query support (rev3)
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev3)
URL : https://patchwork.freedesktop.org/series/60916/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6186_full -> Patchwork_13168_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_13168_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_shared@exec-shared-gtt-render}:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-glk9/igt@gem_ctx_sha...@exec-shared-gtt-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-glk2/igt@gem_ctx_sha...@exec-shared-gtt-render.html
Known issues
Here are the changes found in Patchwork_13168_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-kbl3/igt@gem_soft...@noreloc-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-kbl3/igt@gem_soft...@noreloc-s3.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#110741])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-suspend.html
* igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-xtiled:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb5/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-xtiled.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-iclb7/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-xtiled.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-apl4/igt@kms_f...@flip-vs-suspend-interruptible.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-apl6/igt@kms_f...@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move:
- shard-hsw: [PASS][11] -> [SKIP][12] ([fdo#109271]) +36 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-hsw5/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-move.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +4 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#106978] /
[fdo#107713])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-rgb101010-draw-mmap-wc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-iclb4/igt@kms_psr@psr2_cursor_plane_onoff.html
Possible fixes
* {igt@gem_ctx_param@vm}:
- shard-hsw: [DMESG-WARN][21] ([fdo#110836]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-hsw6/igt@gem_ctx_pa...@vm.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13168/shard-hsw8/igt@gem_ctx_pa...@vm.html
* igt@gem_m
[Intel-gfx] [PATCH] drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl
This completes Emil's series of removing DRM_UNLOCKED from modern drivers. It's entirely cargo-culted since we ignore it on non-DRIVER_LEGACY drivers since: commit ea487835e8876abf7ad909636e308c801a2bcda6 Author: Daniel Vetter Date: Mon Sep 28 21:42:40 2015 +0200 drm: Enforce unlocked ioctl operation for kms driver ioctls Now justifying why we can do this for legacy drives too (and hence close the source of all the bogus copypasting) is a bit more involved. DRM_UNLOCKED was introduced in: commit ed8b67040965e4fe695db333d5914e18ea5f146f Author: Arnd Bergmann Date: Wed Dec 16 22:17:09 2009 + drm: convert drm_ioctl to unlocked_ioctl As a immediate hack to keep i810 happy, which would have deadlocked without this trickery. The old BKL is automatically dropped in schedule(), and hence the i810 vs. mmap_sem deadlock didn't actually cause a real deadlock. But with a mutex it would. The solution was to annotate these as DRM_UNLOCKED and mark i810 unsafe on SMP machines. This conversion caused a regression, because unlike the BKL a mutex isn't dropped over schedule (that thing again), which caused a vblank wait in one thread to block the entire desktop and all its apps. Back then we did vblank scheduling by blocking in the client, awesome isn't it. This was fixed quickly in (ok not so quickly, took 2 years): commit 8f4ff2b06afcd6f151868474a432c603057eaf56 Author: Ilija Hadzic Date: Mon Oct 31 17:46:18 2011 -0400 drm: do not sleep on vblank while holding a mutex All the other DRM_UNLOCKED annotations for all the core ioctls was work to reach finer-grained locking for modern drivers. This took years, and culminated in: commit fdd5b877e9ebc2029e1373b4a3cd057329a9ab7a Author: Daniel Vetter Date: Sat Dec 10 22:52:54 2016 +0100 drm: Enforce BKL-less ioctls for modern drivers DRM_UNLOCKED was never required by any legacy drivers, except for the vblank_wait IOCTL. Therefore we will not regress these old drivers by going back to where we've been in 2011. For all modern drivers nothing will change. To make this perfectly clear, also add a comment to DRM_UNLOCKED. v2: Don't forget about drm_ioc32.c (Michel). Not a source of copypasta mistakes when creating driver ioctl tables, but better to be consistent. Cc: Michel Dänzer Cc: Emil Velikov Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_ioc32.c | 13 ++-- drivers/gpu/drm/drm_ioctl.c | 139 ++-- include/drm/drm_ioctl.h | 3 + 3 files changed, 78 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/drm_ioc32.c b/drivers/gpu/drm/drm_ioc32.c index 586aa28024c5..e1371f30f065 100644 --- a/drivers/gpu/drm/drm_ioc32.c +++ b/drivers/gpu/drm/drm_ioc32.c @@ -108,7 +108,7 @@ static int compat_drm_version(struct file *file, unsigned int cmd, .desc = compat_ptr(v32.desc), }; err = drm_ioctl_kernel(file, drm_version, &v, - DRM_UNLOCKED|DRM_RENDER_ALLOW); + DRM_RENDER_ALLOW); if (err) return err; @@ -142,7 +142,7 @@ static int compat_drm_getunique(struct file *file, unsigned int cmd, .unique = compat_ptr(uq32.unique), }; - err = drm_ioctl_kernel(file, drm_getunique, &uq, DRM_UNLOCKED); + err = drm_ioctl_kernel(file, drm_getunique, &uq, 0); if (err) return err; @@ -181,7 +181,7 @@ static int compat_drm_getmap(struct file *file, unsigned int cmd, return -EFAULT; map.offset = m32.offset; - err = drm_ioctl_kernel(file, drm_legacy_getmap_ioctl, &map, DRM_UNLOCKED); + err = drm_ioctl_kernel(file, drm_legacy_getmap_ioctl, &map, 0); if (err) return err; @@ -267,7 +267,7 @@ static int compat_drm_getclient(struct file *file, unsigned int cmd, client.idx = c32.idx; - err = drm_ioctl_kernel(file, drm_getclient, &client, DRM_UNLOCKED); + err = drm_ioctl_kernel(file, drm_getclient, &client, 0); if (err) return err; @@ -297,7 +297,7 @@ static int compat_drm_getstats(struct file *file, unsigned int cmd, drm_stats32_t __user *argp = (void __user *)arg; int err; - err = drm_ioctl_kernel(file, drm_noop, NULL, DRM_UNLOCKED); + err = drm_ioctl_kernel(file, drm_noop, NULL, 0); if (err) return err; @@ -892,8 +892,7 @@ static int compat_drm_mode_addfb2(struct file *file, unsigned int cmd, sizeof(req64.modifier))) return -EFAULT; - err = drm_ioctl_kernel(file, drm_mode_addfb2, &req64, - DRM_UNLOCKED); + err = drm_ioctl_kernel(file, drm_mode_addfb2, &req64, 0); if (err) return err; diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index a1eb422a5711..365d7a5629f6 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl
Re: [Intel-gfx] [PATCH 07/15] drm/i915: Move object close under its own lock
On Mon, 3 Jun 2019 at 15:00, Chris Wilson wrote:
>
> Use i915_gem_object_lock() to guard the LUT and active reference to
> allow us to break free of struct_mutex for handling GEM_CLOSE.
>
> Testcase: igt/gem_close_race
> Testcase: igt/gem_exec_parallel
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 75 ++-
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 12 +--
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 25 +--
> drivers/gpu/drm/i915/gem/i915_gem_object.c| 38 ++
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 -
> .../gpu/drm/i915/gem/selftests/mock_context.c | 1 -
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_gem.c | 1 +
> drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
> drivers/gpu/drm/i915/i915_timeline.c | 13 ++--
> drivers/gpu/drm/i915/i915_vma.c | 42 +++
> drivers/gpu/drm/i915/i915_vma.h | 17 ++---
> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
> 13 files changed, 131 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 08721ef62e4e..fb03a19932cf 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -95,24 +95,40 @@ void i915_lut_handle_free(struct i915_lut_handle *lut)
>
> static void lut_close(struct i915_gem_context *ctx)
> {
> - struct i915_lut_handle *lut, *ln;
> struct radix_tree_iter iter;
> void __rcu **slot;
>
> - list_for_each_entry_safe(lut, ln, &ctx->handles_list, ctx_link) {
> - list_del(&lut->obj_link);
> - i915_lut_handle_free(lut);
> - }
> - INIT_LIST_HEAD(&ctx->handles_list);
> + lockdep_assert_held(&ctx->mutex);
>
> rcu_read_lock();
> radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
> struct i915_vma *vma = rcu_dereference_raw(*slot);
> + struct drm_i915_gem_object *obj = vma->obj;
> + struct i915_lut_handle *lut;
> +
> + rcu_read_unlock();
> + i915_gem_object_lock(obj);
> + list_for_each_entry(lut, &obj->lut_list, obj_link) {
> + if (lut->ctx != ctx)
> + continue;
>
> - radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
> + if (lut->handle != iter.index)
> + continue;
>
> - vma->open_count--;
> - i915_vma_put(vma);
> + list_del(&lut->obj_link);
> + break;
> + }
> + i915_gem_object_unlock(obj);
> + rcu_read_lock();
> +
> + if (&lut->obj_link != &obj->lut_list) {
So mean.
Fwiw,
Reviewed-by: Matthew Auld
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Re: [Intel-gfx] [PATCH] drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl
On Wed, Jun 5, 2019 at 12:50 PM Michel Dänzer wrote: > > On 2019-05-29 11:30 a.m., Daniel Vetter wrote: > > This completes Emil's series of removing DRM_UNLOCKED from modern > > drivers. It's entirely cargo-culted since we ignore it on > > non-DRIVER_LEGACY drivers since: > > > > commit ea487835e8876abf7ad909636e308c801a2bcda6 > > Author: Daniel Vetter > > Date: Mon Sep 28 21:42:40 2015 +0200 > > > > drm: Enforce unlocked ioctl operation for kms driver ioctls > > > > Now justifying why we can do this for legacy drives too (and hence > > close the source of all the bogus copypasting) is a bit more involved. > > DRM_UNLOCKED was introduced in: > > > > commit ed8b67040965e4fe695db333d5914e18ea5f146f > > Author: Arnd Bergmann > > Date: Wed Dec 16 22:17:09 2009 + > > > > drm: convert drm_ioctl to unlocked_ioctl > > > > As a immediate hack to keep i810 happy, which would have deadlocked > > without this trickery. The old BKL is automatically dropped in > > schedule(), and hence the i810 vs. mmap_sem deadlock didn't actually > > cause a real deadlock. But with a mutex it would. The solution was to > > annotate these as DRM_UNLOCKED and mark i810 unsafe on SMP machines. > > > > This conversion caused a regression, because unlike the BKL a mutex > > isn't dropped over schedule (that thing again), which caused a vblank > > wait in one thread to block the entire desktop and all its apps. Back > > then we did vblank scheduling by blocking in the client, awesome isn't > > it. This was fixed quickly in (ok not so quickly, took 2 years): > > > > commit 8f4ff2b06afcd6f151868474a432c603057eaf56 > > Author: Ilija Hadzic > > Date: Mon Oct 31 17:46:18 2011 -0400 > > > > drm: do not sleep on vblank while holding a mutex > > > > All the other DRM_UNLOCKED annotations for all the core ioctls was > > work to reach finer-grained locking for modern drivers. This took > > years, and culminated in: > > > > commit fdd5b877e9ebc2029e1373b4a3cd057329a9ab7a > > Author: Daniel Vetter > > Date: Sat Dec 10 22:52:54 2016 +0100 > > > > drm: Enforce BKL-less ioctls for modern drivers > > > > DRM_UNLOCKED was never required by any legacy drivers, except for the > > vblank_wait IOCTL. Therefore we will not regress these old drivers by > > going back to where we've been in 2011. For all modern drivers nothing > > will change. > > > > To make this perfectly clear, also add a comment to DRM_UNLOCKED. > > > > Cc: Emil Velikov > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/drm_ioctl.c | 139 ++-- > > include/drm/drm_ioctl.h | 3 + > > 2 files changed, 72 insertions(+), 70 deletions(-) > > Did you miss drivers/gpu/drm/drm_ioc32.c ? Hm indeed. Not a worry from a copypasta-spreading pov, since hopefully no one copypastes ioc32 compat code. But from a consistency side should definitely make sure ioctls work the same whether userspace is 32bit or 64bit. I'll respin, thanks for spotting this. -Daniel > > > -- > Earthling Michel Dänzer | https://www.amd.com > Libre software enthusiast | Mesa and X developer -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for dma-buf: Discard old fence_excl on retrying get_fences_rcu for realloc (rev3)
== Series Details == Series: dma-buf: Discard old fence_excl on retrying get_fences_rcu for realloc (rev3) URL : https://patchwork.freedesktop.org/series/61581/ State : success == Summary == CI Bug Log - changes from CI_DRM_6186_full -> Patchwork_13167_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13167_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-apl4/igt@gem_soft...@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-apl8/igt@gem_soft...@noreloc-s3.html - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#103313]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-kbl3/igt@gem_soft...@noreloc-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-kbl6/igt@gem_soft...@noreloc-s3.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#103167]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite: - shard-hsw: [PASS][7] -> [SKIP][8] ([fdo#109271]) +19 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-hsw2/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [fdo#110403]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_sequence@get-forked: - shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-snb1/igt@kms_seque...@get-forked.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-snb7/igt@kms_seque...@get-forked.html * igt@prime_self_import@export-vs-gem_close-race: - shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-hsw7/igt@prime_self_import@export-vs-gem_close-race.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-hsw5/igt@prime_self_import@export-vs-gem_close-race.html Possible fixes * igt@gem_mmap_gtt@forked-medium-copy-odd: - shard-iclb: [INCOMPLETE][15] ([fdo#107713]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb8/igt@gem_mmap_...@forked-medium-copy-odd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-iclb2/igt@gem_mmap_...@forked-medium-copy-odd.html * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible: - shard-glk: [FAIL][17] ([fdo#103060]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-glk3/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-glk6/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [FAIL][19] ([fdo#105363]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-skl5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-skl1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [FAIL][21] ([fdo#103167]) -> [PASS][22] +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13167/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][23] ([fdo#108145] / [fdo#110403]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/sh
Re: [Intel-gfx] [PATCH] drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl
On 2019-05-29 11:30 a.m., Daniel Vetter wrote: > This completes Emil's series of removing DRM_UNLOCKED from modern > drivers. It's entirely cargo-culted since we ignore it on > non-DRIVER_LEGACY drivers since: > > commit ea487835e8876abf7ad909636e308c801a2bcda6 > Author: Daniel Vetter > Date: Mon Sep 28 21:42:40 2015 +0200 > > drm: Enforce unlocked ioctl operation for kms driver ioctls > > Now justifying why we can do this for legacy drives too (and hence > close the source of all the bogus copypasting) is a bit more involved. > DRM_UNLOCKED was introduced in: > > commit ed8b67040965e4fe695db333d5914e18ea5f146f > Author: Arnd Bergmann > Date: Wed Dec 16 22:17:09 2009 + > > drm: convert drm_ioctl to unlocked_ioctl > > As a immediate hack to keep i810 happy, which would have deadlocked > without this trickery. The old BKL is automatically dropped in > schedule(), and hence the i810 vs. mmap_sem deadlock didn't actually > cause a real deadlock. But with a mutex it would. The solution was to > annotate these as DRM_UNLOCKED and mark i810 unsafe on SMP machines. > > This conversion caused a regression, because unlike the BKL a mutex > isn't dropped over schedule (that thing again), which caused a vblank > wait in one thread to block the entire desktop and all its apps. Back > then we did vblank scheduling by blocking in the client, awesome isn't > it. This was fixed quickly in (ok not so quickly, took 2 years): > > commit 8f4ff2b06afcd6f151868474a432c603057eaf56 > Author: Ilija Hadzic > Date: Mon Oct 31 17:46:18 2011 -0400 > > drm: do not sleep on vblank while holding a mutex > > All the other DRM_UNLOCKED annotations for all the core ioctls was > work to reach finer-grained locking for modern drivers. This took > years, and culminated in: > > commit fdd5b877e9ebc2029e1373b4a3cd057329a9ab7a > Author: Daniel Vetter > Date: Sat Dec 10 22:52:54 2016 +0100 > > drm: Enforce BKL-less ioctls for modern drivers > > DRM_UNLOCKED was never required by any legacy drivers, except for the > vblank_wait IOCTL. Therefore we will not regress these old drivers by > going back to where we've been in 2011. For all modern drivers nothing > will change. > > To make this perfectly clear, also add a comment to DRM_UNLOCKED. > > Cc: Emil Velikov > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/drm_ioctl.c | 139 ++-- > include/drm/drm_ioctl.h | 3 + > 2 files changed, 72 insertions(+), 70 deletions(-) Did you miss drivers/gpu/drm/drm_ioc32.c ? -- Earthling Michel Dänzer | https://www.amd.com Libre software enthusiast | Mesa and X developer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Skip context_barrier emission for unused contexts
On 04/06/2019 16:24, Chris Wilson wrote:
The intent was to skip unused HW contexts by checking ce->state.
However, this only works for execlists where the ppGTT pointers is
stored inside the HW context. For gen7, the ppGTT is alongside the
logical state and must be updated on all active engines but, crucially,
only on active engines. As we need different checks, and to keep
context_barrier_task() agnostic, pass in the predicate.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110836
Fixes: 62c8e423450d ("drm/i915: Skip unused contexts for
context_barrier_task()")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++-
.../drm/i915/gem/selftests/i915_gem_context.c | 19 +++
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 08721ef62e4e..6819b598d226 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -902,6 +902,7 @@ static void cb_retire(struct i915_active *base)
I915_SELFTEST_DECLARE(static intel_engine_mask_t
context_barrier_inject_fault);
static int context_barrier_task(struct i915_gem_context *ctx,
intel_engine_mask_t engines,
+ bool (*skip)(struct intel_context *ce, void
*data),
int (*emit)(struct i915_request *rq, void
*data),
void (*task)(void *data),
void *data)
@@ -931,7 +932,10 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
break;
}
- if (!(ce->engine->mask & engines) || !ce->state)
+ if (!(ce->engine->mask & engines))
+ continue;
+
+ if (skip && skip(ce, data))
continue;
rq = intel_context_create_request(ce);
@@ -1058,6 +1062,14 @@ static int emit_ppgtt_update(struct i915_request *rq,
void *data)
return 0;
}
+static bool skip_ppgtt_update(struct intel_context *ce, void *data)
+{
+ if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
+ return !ce->state;
+ else
+ return !atomic_read(&ce->pin_count);
Would "return !atomic_read(&ce->pin_count) || !ce->state;" work and
avoid the somewhat irky HAS_LOGICAL_RING_CONTEXTS check?
Regards,
Tvrtko
+}
+
static int set_ppgtt(struct drm_i915_file_private *file_priv,
struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -1103,6 +1115,7 @@ static int set_ppgtt(struct drm_i915_file_private
*file_priv,
* only indirectly through the context.
*/
err = context_barrier_task(ctx, ALL_ENGINES,
+ skip_ppgtt_update,
emit_ppgtt_update,
set_ppgtt_barrier,
old);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 1bc3b8026400..41105f6ed206 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1619,6 +1619,11 @@ __engine_name(struct drm_i915_private *i915,
intel_engine_mask_t engines)
return "none";
}
+static bool skip_unused_engines(struct intel_context *ce, void *data)
+{
+ return !ce->state;
+}
+
static void mock_barrier_task(void *data)
{
unsigned int *counter = data;
@@ -1651,7 +1656,7 @@ static int mock_context_barrier(void *arg)
counter = 0;
err = context_barrier_task(ctx, 0,
- NULL, mock_barrier_task, &counter);
+ NULL, NULL, mock_barrier_task, &counter);
if (err) {
pr_err("Failed at line %d, err=%d\n", __LINE__, err);
goto out;
@@ -1664,7 +1669,10 @@ static int mock_context_barrier(void *arg)
counter = 0;
err = context_barrier_task(ctx, ALL_ENGINES,
- NULL, mock_barrier_task, &counter);
+ skip_unused_engines,
+ NULL,
+ mock_barrier_task,
+ &counter);
if (err) {
pr_err("Failed at line %d, err=%d\n", __LINE__, err);
goto out;
@@ -1685,7 +1693,7 @@ static int mock_context_barrier(void *arg)
counter = 0;
context_barrier_inject_fault = BIT(RCS0);
err = context_barrier_task(ctx, ALL_ENGINES,
- NULL, mock_barrier_task, &counter);
+ NULL, NULL, mock_barrier_task, &counter);
context_barrier_inject_fault = 0;
Re: [Intel-gfx] [PATCH 1/2] Documentation/i915: Fix kernel-doc references to moved gem files
Jani Nikula writes:
> The error messages could be more descriptive, but fix these caused by
> file moves:
>
> WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal
> ./drivers/gpu/drm/i915/i915_gem_shrinker.c' failed with return code 2
> WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function
> User command execution ./drivers/gpu/drm/i915/i915_gem_execbuffer.c'
> failed with return code 1
> WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal
> ./drivers/gpu/drm/i915/i915_gem_tiling.c' failed with return code 2
> WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function
> buffer object tiling ./drivers/gpu/drm/i915/i915_gem_tiling.c'
> failed with return code 1
>
> Fixes: 10be98a77c55 ("drm/i915: Move more GEM objects under gem/")
> Cc: Chris Wilson
> Cc: Mika Kuoppala
> Signed-off-by: Jani Nikula
/o\
Reviewed-by: Mika Kuoppala
> ---
> Documentation/gpu/i915.rst | 11 ---
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 6c75380b2928..f98ee95da90f 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -349,7 +349,7 @@ of buffer object caches. Shrinking is used to make main
> memory
> available. Note that this is mostly orthogonal to evicting buffer
> objects, which has the goal to make space in gpu virtual address spaces.
>
> -.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> :internal:
>
> Batchbuffer Parsing
> @@ -373,7 +373,7 @@ Batchbuffer Pools
> User Batchbuffer Execution
> --
>
> -.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> :doc: User command execution
>
> Logical Rings, Logical Ring Contexts and Execlists
> @@ -382,9 +382,6 @@ Logical Rings, Logical Ring Contexts and Execlists
> .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
> :doc: Logical Rings, Logical Ring Contexts and Execlists
>
> -.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
> - :internal:
> -
> Global GTT views
>
>
> @@ -415,10 +412,10 @@ Hardware Tiling and Swizzling Details
> Object Tiling IOCTLs
>
>
> -.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> :internal:
>
> -.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
> +.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> :doc: buffer object tiling
>
> WOPCM
> --
> 2.20.1
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Re: [Intel-gfx] [v7][PATCH 02/12] drm/i915: Enable intel_color_get_config()
On Wed, 29 May 2019, Swati Sharma wrote:
> In this patch, intel_color_get_config() is enabled and support
> for read_luts() will be added platform by platform incrementally
> in the follow-up patches.
>
> v4: -Renamed intel_get_color_config to intel_color_get_config [Jani]
> -Added the user early on such that support for get_color_config()
> can be added platform by platform incrementally [Jani]
> v5: -Incorrect place for calling intel_color_get_config() in
> haswell_get_pipe_config() [Ville]
> v6: -Renamed intel_color_read_luts() to intel_color_get_config()
> [Jani and Ville]
>
> Signed-off-by: Swati Sharma
I pushed patches 1 and 2, thanks for the patches.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_display.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 05177f3..3e01028 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8351,6 +8351,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc
> *crtc,
> pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
>
> i9xx_get_pipe_color_config(pipe_config);
> + intel_color_get_config(pipe_config);
>
> if (INTEL_GEN(dev_priv) < 4)
> pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
> @@ -9426,6 +9427,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc
> *crtc,
> pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
>
> i9xx_get_pipe_color_config(pipe_config);
> + intel_color_get_config(pipe_config);
>
> if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> struct intel_shared_dpll *pll;
> @@ -9874,6 +9876,8 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
> i9xx_get_pipe_color_config(pipe_config);
> }
>
> + intel_color_get_config(pipe_config);
> +
> power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
> WARN_ON(power_domain_mask & BIT_ULL(power_domain));
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [v7][PATCH 03/12] drm/i915: Add func to compare hw/sw gamma lut
On Wed, 29 May 2019, Swati Sharma wrote:
> v3: -Rebase
> v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal() [Jani]
> -Added the default label above the correct label [Jani]
> -Corrected smatch warn "variable dereferenced before check"
> [Dan Carpenter]
> v5: -Added condition (!blob1 && !blob2) return true [Jani]
> -Called PIPE_CONF_CHECK_COLOR_LUT inside if (!adjust) [Jani]
> -Added #undef PIPE_CONF_CHECK_COLOR_LUT [Jani]
> v6: -Added func intel_color_get_bit_precision() to get bit precision for
> gamma and degamma lut readout depending upon platform and
> corresponding to load_luts() [Ankit]
> -Added debug log for color para in intel_dump_pipe_config [Jani]
> -Made patch11 as patch3 [Jani]
> v7: -Renamed func intel_color_get_bit_precision() to
> intel_color_get_gamma_bit_precision()
> -Added separate function/platform for gamma bit precision [Ville]
> -Corrected checkpatch warnings
The patch revisions are great, but you do need to add an actual commit
message first as well.
In general, please don't reference "this patch" because on the one hand
it's kind of obvious and on the other hand it ceases to be a patch when
it gets applied and becomes a commit.
Please also use the imperative style in the commit message like you have
in the title/subject line.
So instead of "In this patch, foo is added." use "Add foo."
BR,
Jani.
>
> Signed-off-by: Swati Sharma
> ---
> drivers/gpu/drm/i915/intel_color.c | 166
> +++
> drivers/gpu/drm/i915/intel_color.h | 7 ++
> drivers/gpu/drm/i915/intel_display.c | 24 +
> 3 files changed, 197 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 50b98ee..b20a2c6 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -1251,6 +1251,172 @@ static int icl_color_check(struct intel_crtc_state
> *crtc_state)
> return 0;
> }
>
> +static int i9xx_gamma_precision(struct intel_crtc_state *crtc_state)
> +{
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> + switch (crtc_state->gamma_mode) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 16;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +}
> +
> +static int chv_gamma_precision(struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> + return 10;
> + else
> + return i9xx_gamma_precision(crtc_state);
> +}
> +
> +static int ilk_gamma_precision(struct intel_crtc_state *crtc_state)
> +{
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> + if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +}
> +
> +static int ivb_gamma_precision(struct intel_crtc_state *crtc_state)
> +{
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> + if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_SPLIT:
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +}
> +
> +static int glk_gamma_precision(struct intel_crtc_state *crtc_state)
> +{
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> + if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +}
> +
> +static int icl_gamma_precision(struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & PRE_CSC_GAMMA_ENABLE) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +}
> +
> +int intel_color_get_gamma_bit_precision(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
>
[PATCH 2/2] drm/i915: fix documentation build warnings
Just a straightforward bag of fixes for a clean htmldocs build.
Signed-off-by: Jani Nikula
---
Documentation/gpu/i915.rst | 6 --
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/i915_vma.h | 2 ++
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 --
5 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index f98ee95da90f..300220c4b498 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -475,12 +475,6 @@ i915_context_create and i915_context_free
.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
:doc: i915_context_create and i915_context_free tracepoints
-switch_mm
--
-
-.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
- :doc: switch_mm tracepoint
-
Perf
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07e3f861a92e..b7c13d5deb15 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -153,7 +153,7 @@
* REG_FIELD_PREP() - Prepare a u32 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to put in the field
-
+ *
* Local copy of FIELD_PREP() to generate an integer constant expression, force
* u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
*
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 2657c99fe187..bc15083bd479 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -40,6 +40,8 @@
enum i915_cache_level;
/**
+ * DOC: Virtual Memory Address
+ *
* A VMA represents a GEM BO that is bound into an address space. Therefore, a
* VMA's presence cannot be guaranteed before binding, or after unbinding the
* object into/from the address space.
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 3d1de288d96c..f55f3bc8524d 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -500,6 +500,8 @@ enum guc_log_buffer_type {
};
/**
+ * struct guc_log_buffer_state - GuC log buffer state
+ *
* Below state structure is used for coordination of retrieval of GuC firmware
* logs. Separate state is maintained for each log buffer type.
* read_ptr points to the location where i915 read last in log buffer and
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3bdeea596ad5..af3c1ada1b2e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -391,8 +391,6 @@ static intel_wakeref_t __intel_runtime_pm_get(struct
drm_i915_private *i915,
* asynchronous PM management from display code) and ensures that it is powered
* up. Raw references are not considered during wakelock assert checks.
*
- * Returns:
- * True when the power domain is enabled, false otherwise.
* Any runtime pm reference obtained by this function must have a symmetric
* call to intel_runtime_pm_put_raw() to release the reference again.
*
--
2.20.1
[PATCH 1/2] Documentation/i915: Fix kernel-doc references to moved gem files
The error messages could be more descriptive, but fix these caused by
file moves:
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal
./drivers/gpu/drm/i915/i915_gem_shrinker.c' failed with return code 2
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function
User command execution ./drivers/gpu/drm/i915/i915_gem_execbuffer.c'
failed with return code 1
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal
./drivers/gpu/drm/i915/i915_gem_tiling.c' failed with return code 2
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function
buffer object tiling ./drivers/gpu/drm/i915/i915_gem_tiling.c'
failed with return code 1
Fixes: 10be98a77c55 ("drm/i915: Move more GEM objects under gem/")
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Jani Nikula
---
Documentation/gpu/i915.rst | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 6c75380b2928..f98ee95da90f 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -349,7 +349,7 @@ of buffer object caches. Shrinking is used to make main
memory
available. Note that this is mostly orthogonal to evicting buffer
objects, which has the goal to make space in gpu virtual address spaces.
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c
+.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
:internal:
Batchbuffer Parsing
@@ -373,7 +373,7 @@ Batchbuffer Pools
User Batchbuffer Execution
--
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_execbuffer.c
+.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
:doc: User command execution
Logical Rings, Logical Ring Contexts and Execlists
@@ -382,9 +382,6 @@ Logical Rings, Logical Ring Contexts and Execlists
.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
:doc: Logical Rings, Logical Ring Contexts and Execlists
-.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
- :internal:
-
Global GTT views
@@ -415,10 +412,10 @@ Hardware Tiling and Swizzling Details
Object Tiling IOCTLs
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
+.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
:internal:
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
+.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
:doc: buffer object tiling
WOPCM
--
2.20.1
Re: [Intel-gfx] [PATCH v2 08/22] gpu: i915.rst: Fix references to renamed files
On Tue, 04 Jun 2019, Mauro Carvalho Chehab wrote:
> WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function
> Hardware workarounds ./drivers/gpu/drm/i915/intel_workarounds.c' failed with
> return code 1
> WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function
> Logical Rings, Logical Ring Contexts and Execlists
> ./drivers/gpu/drm/i915/intel_lrc.c' failed with return code 1
> WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal
> ./drivers/gpu/drm/i915/intel_lrc.c' failed with return code 2
>
> Fixes: 112ed2d31a46 ("drm/i915: Move GraphicsTechnology files under gt/")
> Signed-off-by: Mauro Carvalho Chehab
Thanks for the patch, I picked this via drm-intel because the commit
being fixed is not in Linus' tree yet.
BR,
Jani.
> ---
> Documentation/gpu/i915.rst | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 055df45596c1..6c75380b2928 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -61,7 +61,7 @@ Intel GVT-g Host Support(vGPU device model)
> Workarounds
> ---
>
> -.. kernel-doc:: drivers/gpu/drm/i915/intel_workarounds.c
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c
> :doc: Hardware workarounds
>
> Display Hardware Handling
> @@ -379,10 +379,10 @@ User Batchbuffer Execution
> Logical Rings, Logical Ring Contexts and Execlists
> --
>
> -.. kernel-doc:: drivers/gpu/drm/i915/intel_lrc.c
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
> :doc: Logical Rings, Logical Ring Contexts and Execlists
>
> -.. kernel-doc:: drivers/gpu/drm/i915/intel_lrc.c
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
> :internal:
>
> Global GTT views
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-next
drm-misc-next-2019-06-05:
drm-misc-next for v5.3:
UAPI Changes:
Cross-subsystem Changes:
- Add devicetree bindings for new panels.
- Convert allwinner's DT bindings to a schema.
- Drop video/hdmi static functions from kernel docs.
- Discard old fence when reserving space in reservation_object_get_fences_rcu.
Core Changes:
- Add missing -ENOMEM handling in edid loading.
- Fix null pointer deref in scheduler.
- Header cleanups, making them self-contained.
- Remove drmP.h inclusion from core.
- Fix make htmldocs warning in scheduler and HDR metadata.
- Fix a few warnings in the uapi header and add a doc section for it.
- Small MST sideband error handling fix.
- Clarify userspace review requirements.
- Clarify implicit/explicit fencing in docs.
- Flush output polling on shutdown.
Driver Changes:
- Small cleanups to stm.
- Add new driver for ST-Ericsson MCDE
- Kconfig fix for meson HDMI.
- Add support for Armadeus ST0700 Adapt panel.
- Add KOE tx14d24vm1bpa panel.
- Update timings for st7701.
- Fix compile error in mcde.
- Big series of tc358767 fixes, and enabling support for IRQ and HPD handling.
- Assorted fixes to sii902x, and implementing HDMI audio support.
- Enable HDR metadata support on amdgpu.
- Assorted fixes to atmel-hlcdc, and add sam9x60 LCD controller support.
The following changes since commit 14ee642c2ab0a3d8a1ded11fade692d8b77172b9:
Merge tag 'drm-intel-next-2019-05-24' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next (2019-05-28 09:26:52
+1000)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-06-05
for you to fetch changes up to f5b07b04e5f090a85d1e96938520f2b2b58e4a8e:
dma-buf: Discard old fence_excl on retrying get_fences_rcu for realloc
(2019-06-05 07:38:37 +0100)
drm-misc-next for v5.3:
UAPI Changes:
Cross-subsystem Changes:
- Add devicetree bindings for new panels.
- Convert allwinner's DT bindings to a schema.
- Drop video/hdmi static functions from kernel docs.
- Discard old fence when reserving space in reservation_object_get_fences_rcu.
Core Changes:
- Add missing -ENOMEM handling in edid loading.
- Fix null pointer deref in scheduler.
- Header cleanups, making them self-contained.
- Remove drmP.h inclusion from core.
- Fix make htmldocs warning in scheduler and HDR metadata.
- Fix a few warnings in the uapi header and add a doc section for it.
- Small MST sideband error handling fix.
- Clarify userspace review requirements.
- Clarify implicit/explicit fencing in docs.
- Flush output polling on shutdown.
Driver Changes:
- Small cleanups to stm.
- Add new driver for ST-Ericsson MCDE
- Kconfig fix for meson HDMI.
- Add support for Armadeus ST0700 Adapt panel.
- Add KOE tx14d24vm1bpa panel.
- Update timings for st7701.
- Fix compile error in mcde.
- Big series of tc358767 fixes, and enabling support for IRQ and HPD handling.
- Assorted fixes to sii902x, and implementing HDMI audio support.
- Enable HDR metadata support on amdgpu.
- Assorted fixes to atmel-hlcdc, and add sam9x60 LCD controller support.
Andrey Grodzovsky (2):
drm/sched: Fix static checker warning for potential NULL ptr
drm/sched: Fix make htmldocs warnings.
Benjamin Gaignard (1):
drm/stm: ltdc: restore calls to clk_{enable/disable}
Chris Wilson (2):
drm: Flush output polling on shutdown
dma-buf: Discard old fence_excl on retrying get_fences_rcu for realloc
Claudiu Beznea (3):
drm: atmel-hlcdc: add config option for clock selection
drm: atmel-hlcdc: avoid initializing cfg with zero
drm/atmel-hlcdc: revert shift by 8
Daniel Vetter (2):
drm/doc: More fine-tuning on userspace review requirements
drm/docs: More links for implicit/explicit fencing.
Fabio Estevam (1):
drm/damage-helper: Use NULL instead of 0
Gen Zhang (1):
drm/edid: Fix a missing-check bug in drm_load_edid_firmware()
Imre Deak (1):
drm/mst: Fix MST sideband up-reply failure handling
Jagan Teki (1):
drm/panel: st7701: Swap vertical front and back porch timings
Jerome Brunet (1):
drm/meson: imply dw-hdmi i2s audio for meson hdmi
Jyri Sarha (5):
drm/bridge: sii902x: Set output mode to HDMI or DVI according to EDID
drm/bridge: sii902x: pixel clock unit is 10kHz instead of 1kHz
dt-bindings: display: sii902x: Remove trailing white space
dt-bindings: display: sii902x: Add HDMI audio bindings
drm/bridge: sii902x: Implement HDMI audio support
Linus Walleij (1):
drm/mcde: Add new driver for ST-Ericsson MCDE
Lukasz Majewski (2):
dt-bindings: display/panel: Add KOE tx14d24vm1bpa display description
drm/panel: simple: Add KOE tx14d24vm1bpa display support (320x240)
Maarten Lankhorst (1):
Merge remote-tracking branch 'drm/drm-next' into drm-misc-next
Maxime Ripard (1):
dt-bindings: display: Co
Re: [Intel-gfx] [PATCH i-g-t 1/5] lib/tests: fix conflicting args test
On 6/5/19 12:38 AM, Lucas De Marchi wrote: On Fri, May 31, 2019 at 07:55:45AM -0700, Lucas De Marchi wrote: On Fri, May 31, 2019 at 12:59:35PM +0300, Petri Latvala wrote: On Wed, May 29, 2019 at 04:27:33PM -0700, Lucas De Marchi wrote: We want to check if the long option conflicts with one from the core. The check for conflicting short option already exists just above. No, this one is checking that the val (the 0) doesn't conflict. My point is that this check is already done above. We don't need to do it again. There's two val conflict tests. One checks for conflicts against core short options, the latter (modified here) checks for conflicts against core long option values. If you insist, then we will need to raise it to magic number 500, because 0 won't be a conflict after this series. Yeah that would be the correct change. Petri ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915/selftests: Flush partial-tiling object once
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/selftests: Flush partial-tiling
object once
URL : https://patchwork.freedesktop.org/series/61578/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6186_full -> Patchwork_13166_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_13166_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
- shard-hsw: [PASS][1] -> [SKIP][2] ([fdo#109271]) +28 similar
issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-hsw6/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-hsw1/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][3] -> [FAIL][4] ([fdo#102887] / [fdo#105363])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-glk4/igt@kms_f...@flip-vs-expired-vblank.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-glk4/igt@kms_f...@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#109507])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-skl6/igt@kms_f...@flip-vs-suspend-interruptible.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-skl3/igt@kms_f...@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +4 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +4
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-apl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-iclb6/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] /
[fdo#110026] / [fdo#110040 ])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb2/igt@kms_rotation_...@primary-rotation-270.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-iclb5/igt@kms_rotation_...@primary-rotation-270.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][17] -> [FAIL][18] ([fdo#99912])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-apl8/igt@kms_setm...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-apl8/igt@kms_setm...@basic.html
* igt@perf@blocking:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728]) +1 similar
issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-skl8/igt@p...@blocking.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-skl6/igt@p...@blocking.html
* igt@perf@polling:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#110728])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb1/igt@p...@polling.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-iclb7/igt@p...@polling.html
Possible fixes
* {igt@gem_ctx_param@vm}:
- shard-hsw: [DMESG-WARN][23] ([fdo#110836]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-hsw6/igt@gem_ctx_pa...@vm.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13166/shard-hsw2/igt@gem_ctx_pa...@vm.html
* igt@gem_mmap_gtt@forked-medium-copy-odd:
- shard-iclb: [INCOMPLETE][25] ([fdo#107713])
[Intel-gfx] [PULL] gvt-fixes
Hi, More gvt fixes for 5.2-rc. This fixed one regression when enabling debug build of i915 guest, guest ring state fix after execution for hang check, and with two misc fixes from klocwork check. Thanks -- The following changes since commit 3035e8cd6c316cb633b45bc9b38052ba2dfd299b: drm/i915/gvt: Fix cmd length of VEB_DI_IECP (2019-05-30 11:31:43 +0800) are available in the Git repository at: https://github.com/intel/gvt-linux tags/gvt-fixes-2019-06-05 for you to fetch changes up to 15e7f52a4596b496ce3da2fa4c1f94c6fb0023f2: drm/i915/gvt: save RING_HEAD into vreg when vgpu switched out (2019-06-03 13:18:36 +0800) gvt-fixes-2019-06-05 - Fix i915 guest debug build for register command access (Weinan) - Fix guest ring state after execution for hangcheck (Xiaolin) - klocwork static check fixes (Alek) Aleksei Gimbitskii (2): drm/i915/gvt: Check if cur_pt_type is valid drm/i915/gvt: Assign NULL to the pointer after memory free. Weinan Li (1): drm/i915/gvt: add F_CMD_ACCESS flag for wa regs Xiaolin Zhang (1): drm/i915/gvt: save RING_HEAD into vreg when vgpu switched out drivers/gpu/drm/i915/gvt/gtt.c | 12 +++- drivers/gpu/drm/i915/gvt/handlers.c | 13 +++-- drivers/gpu/drm/i915/gvt/reg.h | 2 ++ drivers/gpu/drm/i915/gvt/scheduler.c | 25 + drivers/gpu/drm/i915/gvt/scheduler.h | 1 + 5 files changed, 46 insertions(+), 7 deletions(-) -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
