[Intel-gfx] [CI 03/33] drm/i915: Move intel_gt initialization to a separate file
From: Tvrtko Ursulin
As it will grow in a following patch make a new home for it.
v2:
* Convert mock_gem_device as well. (Chris)
v3:
* Rename to intel_gt_init_early and move call site to i915_drv.c. (Chris)
v4:
* Adjust SPDX tags.
* No need to gt/ path when including intel_gt_types.h. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 14 ++
drivers/gpu/drm/i915/gt/intel_gt.h | 13 +
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_gem.c | 4
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 6 ++
6 files changed, 33 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 91355c2ea8a5..19f8b6745772 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -74,6 +74,7 @@ gt-y += \
gt/intel_context.o \
gt/intel_engine_cs.o \
gt/intel_engine_pm.o \
+ gt/intel_gt.o \
gt/intel_gt_pm.o \
gt/intel_hangcheck.o \
gt/intel_lrc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
new file mode 100644
index ..10adee1120e6
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_gt.h"
+
+void intel_gt_init_early(struct intel_gt *gt)
+{
+ INIT_LIST_HEAD(>->active_rings);
+ INIT_LIST_HEAD(>->closed_vma);
+
+ spin_lock_init(>->closed_lock);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
new file mode 100644
index ..63284ca81d69
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_GT__
+#define __INTEL_GT__
+
+#include "intel_gt_types.h"
+
+void intel_gt_init_early(struct intel_gt *gt);
+
+#endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8f84ed26e972..961f76d3efa4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -61,6 +61,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_ioctls.h"
+#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_reset.h"
#include "gt/intel_workarounds.h"
@@ -922,6 +923,8 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
if (ret < 0)
goto err_engines;
+ intel_gt_init_early(&dev_priv->gt);
+
ret = i915_gem_init_early(dev_priv);
if (ret < 0)
goto err_workqueues;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 190ad54fb072..fc8fd41dd32e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1748,10 +1748,6 @@ int i915_gem_init_early(struct drm_i915_private
*dev_priv)
intel_gt_pm_init(dev_priv);
- INIT_LIST_HEAD(&dev_priv->gt.active_rings);
- INIT_LIST_HEAD(&dev_priv->gt.closed_vma);
- spin_lock_init(&dev_priv->gt.closed_lock);
-
i915_gem_init__mm(dev_priv);
i915_gem_init__pm(dev_priv);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 64bc51400ae7..8dc9296892e6 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -25,6 +25,7 @@
#include
#include
+#include "gt/intel_gt.h"
#include "gt/mock_engine.h"
#include "mock_request.h"
@@ -179,6 +180,7 @@ struct drm_i915_private *mock_gem_device(void)
mock_uncore_init(&i915->uncore);
i915_gem_init__mm(i915);
+ intel_gt_init_early(&i915->gt);
intel_gt_pm_init(i915);
atomic_inc(&i915->gt.wakeref.count); /* disable; no hw support */
@@ -200,10 +202,6 @@ struct drm_i915_private *mock_gem_device(void)
i915_timelines_init(i915);
- INIT_LIST_HEAD(&i915->gt.active_rings);
- INIT_LIST_HEAD(&i915->gt.closed_vma);
- spin_lock_init(&i915->gt.closed_lock);
-
mutex_lock(&i915->drm.struct_mutex);
mock_init_ggtt(i915, &i915->ggtt);
--
2.20.1
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[Intel-gfx] [CI 09/33] drm/i915: Convert init_unused_rings to intel_gt
From: Tvrtko Ursulin
More removal of implicit dev_priv from using old mmio accessors.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 42 ++---
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 30da603ee7fd..6f96d360e8d5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1202,28 +1202,32 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
}
-static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
+static void init_unused_ring(struct intel_gt *gt, u32 base)
{
- I915_WRITE(RING_CTL(base), 0);
- I915_WRITE(RING_HEAD(base), 0);
- I915_WRITE(RING_TAIL(base), 0);
- I915_WRITE(RING_START(base), 0);
+ struct intel_uncore *uncore = gt->uncore;
+
+ intel_uncore_write(uncore, RING_CTL(base), 0);
+ intel_uncore_write(uncore, RING_HEAD(base), 0);
+ intel_uncore_write(uncore, RING_TAIL(base), 0);
+ intel_uncore_write(uncore, RING_START(base), 0);
}
-static void init_unused_rings(struct drm_i915_private *dev_priv)
+static void init_unused_rings(struct intel_gt *gt)
{
- if (IS_I830(dev_priv)) {
- init_unused_ring(dev_priv, PRB1_BASE);
- init_unused_ring(dev_priv, SRB0_BASE);
- init_unused_ring(dev_priv, SRB1_BASE);
- init_unused_ring(dev_priv, SRB2_BASE);
- init_unused_ring(dev_priv, SRB3_BASE);
- } else if (IS_GEN(dev_priv, 2)) {
- init_unused_ring(dev_priv, SRB0_BASE);
- init_unused_ring(dev_priv, SRB1_BASE);
- } else if (IS_GEN(dev_priv, 3)) {
- init_unused_ring(dev_priv, PRB1_BASE);
- init_unused_ring(dev_priv, PRB2_BASE);
+ struct drm_i915_private *i915 = gt->i915;
+
+ if (IS_I830(i915)) {
+ init_unused_ring(gt, PRB1_BASE);
+ init_unused_ring(gt, SRB0_BASE);
+ init_unused_ring(gt, SRB1_BASE);
+ init_unused_ring(gt, SRB2_BASE);
+ init_unused_ring(gt, SRB3_BASE);
+ } else if (IS_GEN(i915, 2)) {
+ init_unused_ring(gt, SRB0_BASE);
+ init_unused_ring(gt, SRB1_BASE);
+ } else if (IS_GEN(i915, 3)) {
+ init_unused_ring(gt, PRB1_BASE);
+ init_unused_ring(gt, PRB2_BASE);
}
}
@@ -1256,7 +1260,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
* will prevent c3 entry. Makes sure all unused rings
* are totally idle.
*/
- init_unused_rings(dev_priv);
+ init_unused_rings(&dev_priv->gt);
BUG_ON(!dev_priv->kernel_context);
ret = i915_terminally_wedged(dev_priv);
--
2.20.1
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[Intel-gfx] [CI 02/33] drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt
From: Tvrtko Ursulin
We have long been slighlty annoyed by the anonymous i915->gt.
Promote it to a separate structure and give it its own header.
This is a first step towards cleaning up the separation between
i915 and gt.
v2:
* Adjust SPDX header.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 52
drivers/gpu/drm/i915/i915_drv.h | 34 +---
2 files changed, 54 insertions(+), 32 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_types.h
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
new file mode 100644
index ..72e94aba8b2a
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_GT_TYPES__
+#define __INTEL_GT_TYPES__
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "i915_vma.h"
+#include "intel_wakeref.h"
+
+struct intel_gt {
+ struct i915_gt_timelines {
+ struct mutex mutex; /* protects list, tainted by GPU */
+ struct list_head active_list;
+
+ /* Pack multiple timelines' seqnos into the same page */
+ spinlock_t hwsp_lock;
+ struct list_head hwsp_free_list;
+ } timelines;
+
+ struct list_head active_rings;
+
+ struct intel_wakeref wakeref;
+
+ struct list_head closed_vma;
+ spinlock_t closed_lock; /* guards the list of closed_vma */
+
+ /**
+* Is the GPU currently considered idle, or busy executing
+* userspace requests? Whilst idle, we allow runtime power
+* management to power down the hardware and display clocks.
+* In order to reduce the effect on performance, there
+* is a slight delay before we do so.
+*/
+ intel_wakeref_t awake;
+
+ struct blocking_notifier_head pm_notifications;
+
+ ktime_t last_init_time;
+
+ struct i915_vma *scratch;
+};
+
+#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2734f62ab19a..3509eb88b452 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -72,6 +72,7 @@
#include "gt/intel_lrc.h"
#include "gt/intel_engine.h"
+#include "gt/intel_gt_types.h"
#include "gt/intel_workarounds.h"
#include "intel_device_info.h"
@@ -1824,38 +1825,7 @@ struct drm_i915_private {
} perf;
/* Abstract the submission mechanism (legacy ringbuffer or execlists)
away */
- struct {
- struct i915_gt_timelines {
- struct mutex mutex; /* protects list, tainted by GPU */
- struct list_head active_list;
-
- /* Pack multiple timelines' seqnos into the same page */
- spinlock_t hwsp_lock;
- struct list_head hwsp_free_list;
- } timelines;
-
- struct list_head active_rings;
-
- struct intel_wakeref wakeref;
-
- struct list_head closed_vma;
- spinlock_t closed_lock; /* guards the list of closed_vma */
-
- /**
-* Is the GPU currently considered idle, or busy executing
-* userspace requests? Whilst idle, we allow runtime power
-* management to power down the hardware and display clocks.
-* In order to reduce the effect on performance, there
-* is a slight delay before we do so.
-*/
- intel_wakeref_t awake;
-
- struct blocking_notifier_head pm_notifications;
-
- ktime_t last_init_time;
-
- struct i915_vma *scratch;
- } gt;
+ struct intel_gt gt;
struct {
struct notifier_block pm_notifier;
--
2.20.1
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[Intel-gfx] [CI 06/33] drm/i915: Make i915_check_and_clear_faults take intel_gt
From: Tvrtko Ursulin
Continuing the conversion and elimination of implicit dev_priv.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Rodrigo Vivi
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 130 ++
drivers/gpu/drm/i915/gt/intel_gt.h| 5 +
drivers/gpu/drm/i915/gt/intel_reset.c | 126 +
drivers/gpu/drm/i915/gt/intel_reset.h | 2 -
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +-
7 files changed, 144 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d45328e254dc..5e4bf738ee59 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -28,6 +28,8 @@
#include "i915_drv.h"
+#include "gt/intel_gt.h"
+
#include "intel_engine.h"
#include "intel_engine_pm.h"
#include "intel_context.h"
@@ -453,7 +455,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->num_engines = hweight32(mask);
- i915_check_and_clear_faults(i915);
+ intel_gt_check_and_clear_faults(&i915->gt);
intel_setup_engine_capabilities(i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f760c2e0253e..5c9be38713db 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -7,6 +7,7 @@
#include "intel_gt.h"
#include "intel_gt_pm.h"
+#include "intel_uncore.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -20,3 +21,132 @@ void intel_gt_init_early(struct intel_gt *gt, struct
drm_i915_private *i915)
intel_gt_pm_init_early(gt);
}
+
+static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
+{
+ intel_uncore_rmw(uncore, reg, 0, set);
+}
+
+static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
+{
+ intel_uncore_rmw(uncore, reg, clr, 0);
+}
+
+static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
+{
+ intel_uncore_rmw(uncore, reg, 0, 0);
+}
+
+static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
+{
+ GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
+ GEN6_RING_FAULT_REG_POSTING_READ(engine);
+}
+
+void
+intel_gt_clear_error_registers(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 eir;
+
+ if (!IS_GEN(i915, 2))
+ clear_register(uncore, PGTBL_ER);
+
+ if (INTEL_GEN(i915) < 4)
+ clear_register(uncore, IPEIR(RENDER_RING_BASE));
+ else
+ clear_register(uncore, IPEIR_I965);
+
+ clear_register(uncore, EIR);
+ eir = intel_uncore_read(uncore, EIR);
+ if (eir) {
+ /*
+* some errors might have become stuck,
+* mask them.
+*/
+ DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
+ rmw_set(uncore, EMR, eir);
+ intel_uncore_write(uncore, GEN2_IIR,
+ I915_MASTER_ERROR_INTERRUPT);
+ }
+
+ if (INTEL_GEN(i915) >= 8) {
+ rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
+ intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
+ } else if (INTEL_GEN(i915) >= 6) {
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine_masked(engine, i915, engine_mask, id)
+ gen8_clear_engine_error_register(engine);
+ }
+}
+
+static void gen6_check_faults(struct intel_gt *gt)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ u32 fault;
+
+ for_each_engine(engine, gt->i915, id) {
+ fault = GEN6_RING_FAULT_REG_READ(engine);
+ if (fault & RING_FAULT_VALID) {
+ DRM_DEBUG_DRIVER("Unexpected fault\n"
+"\tAddr: 0x%08lx\n"
+"\tAddress space: %s\n"
+"\tSource ID: %d\n"
+"\tType: %d\n",
+fault & PAGE_MASK,
+fault & RING_FAULT_GTTSEL_MASK ?
+"GGTT" : "PPGTT",
+RING_FAULT_SRCID(fault),
+RING_FAULT_FAULT_TYPE(fault));
+ }
+ }
+}
+
+static void gen8_check_faults(struct intel_gt *gt)
+{
+ struct intel_uncore *uncore = gt->uncore;
+ u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_R
[Intel-gfx] [CI 15/33] drm/i915: Convert i915_gem_init_hw to intel_gt
From: Tvrtko Ursulin
More removal of implicit dev_priv from using old mmio accessors.
Actually the top level function remains but is split into a part which
writes to i915 and part which operates on intel_gt in order to initialize
the hardware.
GuC and engines are the only odd ones out remaining.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem.c | 66 -
1 file changed, 40 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 769cfb15e6ca..989d987c42d4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1231,28 +1231,32 @@ static void init_unused_rings(struct intel_gt *gt)
}
}
-int i915_gem_init_hw(struct drm_i915_private *dev_priv)
+static int init_hw(struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
int ret;
- dev_priv->gt.last_init_time = ktime_get();
+ gt->last_init_time = ktime_get();
/* Double layer security blanket, see i915_gem_init() */
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
- if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
- I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
+ if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
+ intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
- if (IS_HASWELL(dev_priv))
- I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
- LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
+ if (IS_HASWELL(i915))
+ intel_uncore_write(uncore,
+ MI_PREDICATE_RESULT_2,
+ IS_HSW_GT3(i915) ?
+ LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
/* Apply the GT workarounds... */
- intel_gt_apply_workarounds(&dev_priv->gt);
+ intel_gt_apply_workarounds(gt);
/* ...and determine whether they are sticking. */
- intel_gt_verify_workarounds(&dev_priv->gt, "init");
+ intel_gt_verify_workarounds(gt, "init");
- intel_gt_init_swizzling(&dev_priv->gt);
+ intel_gt_init_swizzling(gt);
/*
* At least 830 can leave some of the unused rings
@@ -1260,48 +1264,58 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
* will prevent c3 entry. Makes sure all unused rings
* are totally idle.
*/
- init_unused_rings(&dev_priv->gt);
-
- BUG_ON(!dev_priv->kernel_context);
- ret = i915_terminally_wedged(dev_priv);
- if (ret)
- goto out;
+ init_unused_rings(gt);
- ret = i915_ppgtt_init_hw(&dev_priv->gt);
+ ret = i915_ppgtt_init_hw(gt);
if (ret) {
DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
goto out;
}
- ret = intel_wopcm_init_hw(&dev_priv->wopcm);
+ ret = intel_wopcm_init_hw(&i915->wopcm);
if (ret) {
DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
goto out;
}
/* We can't enable contexts until all firmware is loaded */
- ret = intel_uc_init_hw(dev_priv);
+ ret = intel_uc_init_hw(i915);
if (ret) {
DRM_ERROR("Enabling uc failed (%d)\n", ret);
goto out;
}
- intel_mocs_init_l3cc_table(&dev_priv->gt);
+ intel_mocs_init_l3cc_table(gt);
/* Only when the HW is re-initialised, can we replay the requests */
- ret = intel_engines_resume(dev_priv);
+ ret = intel_engines_resume(i915);
if (ret)
goto cleanup_uc;
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
- intel_engines_set_scheduler_caps(dev_priv);
return 0;
cleanup_uc:
- intel_uc_fini_hw(dev_priv);
+ intel_uc_fini_hw(i915);
out:
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
+
+ return ret;
+}
+
+int i915_gem_init_hw(struct drm_i915_private *i915)
+{
+ int ret;
+
+ BUG_ON(!i915->kernel_context);
+ ret = i915_terminally_wedged(i915);
+ if (ret)
+ return ret;
+
+ ret = init_hw(&i915->gt);
+
+ intel_engines_set_scheduler_caps(i915);
return ret;
}
--
2.20.1
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[Intel-gfx] [CI 01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore
From: Tvrtko Ursulin
More removal of implicit dev_priv from using old mmio accessors.
Furthermore these calls really operate on ggtt so it logically makes sense
if they take it as parameter.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_vgpu.c| 24 ++--
drivers/gpu/drm/i915/i915_vgpu.h| 4 ++--
3 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5b858f675f29..685505f45991 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2811,7 +2811,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
intel_wopcm_guc_size(&dev_priv->wopcm));
- ret = intel_vgt_balloon(dev_priv);
+ ret = intel_vgt_balloon(ggtt);
if (ret)
return ret;
@@ -2882,7 +2882,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv)
ggtt_release_guc_top(ggtt);
if (drm_mm_initialized(&ggtt->vm.mm)) {
- intel_vgt_deballoon(dev_priv);
+ intel_vgt_deballoon(ggtt);
i915_address_space_fini(&ggtt->vm);
}
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 1a8f7c731126..9916bc6159b6 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -136,17 +136,17 @@ static void vgt_deballoon_space(struct i915_ggtt *ggtt,
* This function is called to deallocate the ballooned-out graphic memory, when
* driver is unloaded or when ballooning fails.
*/
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
+void intel_vgt_deballoon(struct i915_ggtt *ggtt)
{
int i;
- if (!intel_vgpu_active(dev_priv))
+ if (!intel_vgpu_active(ggtt->vm.i915))
return;
DRM_DEBUG("VGT deballoon.\n");
for (i = 0; i < 4; i++)
- vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
+ vgt_deballoon_space(ggtt, &bl_info.space[i]);
}
static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -214,22 +214,26 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt,
* Returns:
* zero on success, non-zero if configuration invalid or ballooning failed
*/
-int intel_vgt_balloon(struct drm_i915_private *dev_priv)
+int intel_vgt_balloon(struct i915_ggtt *ggtt)
{
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
unsigned long ggtt_end = ggtt->vm.total;
unsigned long mappable_base, mappable_size, mappable_end;
unsigned long unmappable_base, unmappable_size, unmappable_end;
int ret;
- if (!intel_vgpu_active(dev_priv))
+ if (!intel_vgpu_active(ggtt->vm.i915))
return 0;
- mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
- mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
- unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
- unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
+ mappable_base =
+ intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
+ mappable_size =
+ intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
+ unmappable_base =
+ intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
+ unmappable_size =
+ intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));
mappable_end = mappable_base + mappable_size;
unmappable_end = unmappable_base + unmappable_size;
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index a919735fb6ce..8dd7497eda15 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -42,7 +42,7 @@ intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
}
-int intel_vgt_balloon(struct drm_i915_private *dev_priv);
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
+int intel_vgt_balloon(struct i915_ggtt *ggtt);
+void intel_vgt_deballoon(struct i915_ggtt *ggtt);
#endif /* _I915_VGPU_H_ */
--
2.20.1
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[Intel-gfx] [CI 08/33] drm/i915: Use intel_uncore_rmw in intel_gt_init_swizzling
From: Tvrtko Ursulin Two easy opportunities to compact the code by using the existing helper. Signed-off-by: Tvrtko Ursulin Suggested-by: Rodrigo Vivi Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index dd09790c420d..bcac359ec661 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -844,17 +844,12 @@ void intel_gt_init_swizzling(struct intel_gt *gt) i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) return; - intel_uncore_write(uncore, - DISP_ARB_CTL, - intel_uncore_read(uncore, DISP_ARB_CTL) | - DISP_TILE_SURFACE_SWIZZLING); + intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING); if (IS_GEN(i915, 5)) return; - intel_uncore_write(uncore, - TILECTL, - intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL); + intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL); if (IS_GEN(i915, 6)) intel_uncore_write(uncore, -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 19/33] drm/i915: Compartmentalize i915_ggtt_init_hw
From: Tvrtko Ursulin
Having made start to better code compartmentalization by introducing
struct intel_gt, continue the theme elsewhere in code by making functions
take parameters take what logically makes most sense for them instead of
the global struct drm_i915_private.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 64 +++--
1 file changed, 42 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 629683c52e50..6f86c8e051fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3516,45 +3516,65 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
return 0;
}
-/**
- * i915_ggtt_init_hw - Initialize GGTT hardware
- * @dev_priv: i915 device
- */
-int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
+static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
{
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
- int ret;
+ ggtt->vm.cleanup(&ggtt->vm);
+}
- stash_init(&dev_priv->mm.wc_stash);
+static int ggtt_init_hw(struct i915_ggtt *ggtt)
+{
+ struct drm_i915_private *i915 = ggtt->vm.i915;
+ int ret = 0;
+
+ mutex_lock(&i915->drm.struct_mutex);
- /* Note that we use page colouring to enforce a guard page at the
-* end of the address space. This is required as the CS may prefetch
-* beyond the end of the batch buffer, across the page boundary,
-* and beyond the end of the GTT if we do not provide a guard.
-*/
- mutex_lock(&dev_priv->drm.struct_mutex);
i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
ggtt->vm.is_ggtt = true;
/* Only VLV supports read-only GGTT mappings */
- ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
+ ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
- if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
+ if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
- mutex_unlock(&dev_priv->drm.struct_mutex);
- if (!io_mapping_init_wc(&dev_priv->ggtt.iomap,
- dev_priv->ggtt.gmadr.start,
- dev_priv->ggtt.mappable_end)) {
+ if (!io_mapping_init_wc(&ggtt->iomap,
+ ggtt->gmadr.start,
+ ggtt->mappable_end)) {
+ ggtt_cleanup_hw(ggtt);
ret = -EIO;
- goto out_gtt_cleanup;
+ goto out;
}
ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
i915_ggtt_init_fences(ggtt);
+out:
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ return ret;
+}
+
+/**
+ * i915_ggtt_init_hw - Initialize GGTT hardware
+ * @dev_priv: i915 device
+ */
+int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
+{
+ int ret;
+
+ stash_init(&dev_priv->mm.wc_stash);
+
+ /* Note that we use page colouring to enforce a guard page at the
+* end of the address space. This is required as the CS may prefetch
+* beyond the end of the batch buffer, across the page boundary,
+* and beyond the end of the GTT if we do not provide a guard.
+*/
+ ret = ggtt_init_hw(&dev_priv->ggtt);
+ if (ret)
+ return ret;
+
/*
* Initialise stolen early so that we may reserve preallocated
* objects for the BIOS to KMS transition.
@@ -3566,7 +3586,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
return 0;
out_gtt_cleanup:
- ggtt->vm.cleanup(&ggtt->vm);
+ ggtt_cleanup_hw(&dev_priv->ggtt);
return ret;
}
--
2.20.1
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[Intel-gfx] [CI 12/33] drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt
From: Tvrtko Ursulin
More removal of implicit dev_priv from using old mmio accessors.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 52 +---
drivers/gpu/drm/i915/gt/intel_mocs.h | 3 +-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
3 files changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 1f9db50b1869..d08b8f47269b 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -23,6 +23,7 @@
#include "i915_drv.h"
#include "intel_engine.h"
+#include "intel_gt.h"
#include "intel_mocs.h"
#include "intel_lrc.h"
@@ -247,7 +248,7 @@ static const struct drm_i915_mocs_entry
icelake_mocs_table[] = {
/**
* get_mocs_settings()
- * @dev_priv: i915 device.
+ * @gt:gt device
* @table: Output table that will be made to point at appropriate
* MOCS values for the device.
*
@@ -257,33 +258,34 @@ static const struct drm_i915_mocs_entry
icelake_mocs_table[] = {
*
* Return: true if there are applicable MOCS settings for the device.
*/
-static bool get_mocs_settings(struct drm_i915_private *dev_priv,
+static bool get_mocs_settings(struct intel_gt *gt,
struct drm_i915_mocs_table *table)
{
+ struct drm_i915_private *i915 = gt->i915;
bool result = false;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(i915) >= 11) {
table->size = ARRAY_SIZE(icelake_mocs_table);
table->table = icelake_mocs_table;
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
result = true;
- } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
table->size = ARRAY_SIZE(skylake_mocs_table);
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
table->table = skylake_mocs_table;
result = true;
- } else if (IS_GEN9_LP(dev_priv)) {
+ } else if (IS_GEN9_LP(i915)) {
table->size = ARRAY_SIZE(broxton_mocs_table);
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
table->table = broxton_mocs_table;
result = true;
} else {
- WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
+ WARN_ONCE(INTEL_GEN(i915) >= 9,
"Platform that should have a MOCS table does not.\n");
}
/* WaDisableSkipCaching:skl,bxt,kbl,glk */
- if (IS_GEN(dev_priv, 9)) {
+ if (IS_GEN(i915, 9)) {
int i;
for (i = 0; i < table->size; i++)
@@ -338,12 +340,13 @@ static u32 get_entry_control(const struct
drm_i915_mocs_table *table,
*/
void intel_mocs_init_engine(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
+ struct intel_gt *gt = engine->gt;
+ struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
unsigned int index;
u32 unused_value;
- if (!get_mocs_settings(dev_priv, &table))
+ if (!get_mocs_settings(gt, &table))
return;
/* Set unused values to PTE */
@@ -352,12 +355,16 @@ void intel_mocs_init_engine(struct intel_engine_cs
*engine)
for (index = 0; index < table.size; index++) {
u32 value = get_entry_control(&table, index);
- I915_WRITE(mocs_register(engine->id, index), value);
+ intel_uncore_write(uncore,
+ mocs_register(engine->id, index),
+ value);
}
/* All remaining entries are also unused */
for (; index < table.n_entries; index++)
- I915_WRITE(mocs_register(engine->id, index), unused_value);
+ intel_uncore_write(uncore,
+ mocs_register(engine->id, index),
+ unused_value);
}
/**
@@ -502,13 +509,14 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
*
* Return: Nothing.
*/
-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
+void intel_mocs_init_l3cc_table(struct intel_gt *gt)
{
+ struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
unsigned int i;
u16 unused_value;
- if (!get_mocs_settings(dev_priv, &table))
+ if (!get_mocs_settings(gt, &table))
return;
/* Set unused values to PTE */
@@ -518,23 +526,27 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private
*dev_priv)
u16 low = get_entry_l3cc(&table, 2 * i);
u16 high = get_entry_l3cc(&table, 2 * i + 1);
- I915_WRITE(GEN9_LNCFCMOCS(i),
- l3cc_combine(&table, low, high));
+ intel_u
[Intel-gfx] [CI 10/33] drm/i915: Convert gt workarounds to intel_gt
From: Tvrtko Ursulin
More conversion of i915_gem_init_hw to uncore.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +-
drivers/gpu/drm/i915/gt/intel_workarounds.h | 6 +++---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f6663cec387a..140cf3f24141 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_context.h"
+#include "intel_gt.h"
#include "intel_workarounds.h"
/**
@@ -984,9 +985,9 @@ wa_list_apply(struct intel_uncore *uncore, const struct
i915_wa_list *wal)
spin_unlock_irqrestore(&uncore->lock, flags);
}
-void intel_gt_apply_workarounds(struct drm_i915_private *i915)
+void intel_gt_apply_workarounds(struct intel_gt *gt)
{
- wa_list_apply(&i915->uncore, &i915->gt_wa_list);
+ wa_list_apply(gt->uncore, >->i915->gt_wa_list);
}
static bool wa_list_verify(struct intel_uncore *uncore,
@@ -1005,10 +1006,9 @@ static bool wa_list_verify(struct intel_uncore *uncore,
return ok;
}
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
-const char *from)
+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
{
- return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
+ return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from);
}
static void
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.h
b/drivers/gpu/drm/i915/gt/intel_workarounds.h
index 3761a6ee58bb..8c9c769c2204 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.h
@@ -14,6 +14,7 @@
struct drm_i915_private;
struct i915_request;
struct intel_engine_cs;
+struct intel_gt;
static inline void intel_wa_list_free(struct i915_wa_list *wal)
{
@@ -25,9 +26,8 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine);
int intel_engine_emit_ctx_wa(struct i915_request *rq);
void intel_gt_init_workarounds(struct drm_i915_private *i915);
-void intel_gt_apply_workarounds(struct drm_i915_private *i915);
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
-const char *from);
+void intel_gt_apply_workarounds(struct intel_gt *gt);
+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from);
void intel_engine_init_whitelist(struct intel_engine_cs *engine);
void intel_engine_apply_whitelist(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6f96d360e8d5..0a313289f984 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1248,9 +1248,9 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
/* Apply the GT workarounds... */
- intel_gt_apply_workarounds(dev_priv);
+ intel_gt_apply_workarounds(&dev_priv->gt);
/* ...and determine whether they are sticking. */
- intel_gt_verify_workarounds(dev_priv, "init");
+ intel_gt_verify_workarounds(&dev_priv->gt, "init");
intel_gt_init_swizzling(&dev_priv->gt);
--
2.20.1
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[Intel-gfx] [CI 04/33] drm/i915: Store some backpointers in struct intel_gt
From: Tvrtko Ursulin
We need an easy way to get back to i915 and uncore.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt.c | 7 ++-
drivers/gpu/drm/i915/gt/intel_gt.h | 4 +++-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 6 ++
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
5 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 10adee1120e6..eccb52cf37b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -3,10 +3,15 @@
* Copyright © 2019 Intel Corporation
*/
+#include "i915_drv.h"
+
#include "intel_gt.h"
-void intel_gt_init_early(struct intel_gt *gt)
+void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
+ gt->i915 = i915;
+ gt->uncore = &i915->uncore;
+
INIT_LIST_HEAD(>->active_rings);
INIT_LIST_HEAD(>->closed_vma);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 63284ca81d69..0dd218e53368 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -8,6 +8,8 @@
#include "intel_gt_types.h"
-void intel_gt_init_early(struct intel_gt *gt);
+struct drm_i915_private;
+
+void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
#endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 72e94aba8b2a..86a4985f8e84 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -16,7 +16,13 @@
#include "i915_vma.h"
#include "intel_wakeref.h"
+struct drm_i915_private;
+struct intel_uncore;
+
struct intel_gt {
+ struct drm_i915_private *i915;
+ struct intel_uncore *uncore;
+
struct i915_gt_timelines {
struct mutex mutex; /* protects list, tainted by GPU */
struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 961f76d3efa4..df11a0d6d52d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -923,7 +923,7 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
if (ret < 0)
goto err_engines;
- intel_gt_init_early(&dev_priv->gt);
+ intel_gt_init_early(&dev_priv->gt, dev_priv);
ret = i915_gem_init_early(dev_priv);
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 8dc9296892e6..2b87200477f6 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -180,7 +180,7 @@ struct drm_i915_private *mock_gem_device(void)
mock_uncore_init(&i915->uncore);
i915_gem_init__mm(i915);
- intel_gt_init_early(&i915->gt);
+ intel_gt_init_early(&i915->gt, i915);
intel_gt_pm_init(i915);
atomic_inc(&i915->gt.wakeref.count); /* disable; no hw support */
--
2.20.1
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[Intel-gfx] [CI 23/33] drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt
From: Tvrtko Ursulin
Having introduced struct intel_gt (named the anonymous structure in i915)
we can start using it to compartmentalize our code better. It makes more
sense logically to have the code internally like this and it will also
help with future split between gt and display in i915.
v2:
* Keep ggtt flush before fb obj flush. (Chris)
v3:
* Fix refactoring fail.
* Always flush ggtt writes. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 7 ++--
.../drm/i915/gem/selftests/i915_gem_mman.c| 3 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 41 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 2 +
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_gem.c | 40 --
drivers/gpu/drm/i915/i915_vma.c | 3 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
8 files changed, 52 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index be6caccce0c5..87275f9883ac 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -23,7 +23,7 @@
*/
#include "display/intel_frontbuffer.h"
-
+#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
@@ -319,7 +319,6 @@ void
i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
unsigned int flush_domains)
{
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct i915_vma *vma;
assert_object_held(obj);
@@ -329,7 +328,8 @@ i915_gem_object_flush_write_domain(struct
drm_i915_gem_object *obj,
switch (obj->write_domain) {
case I915_GEM_DOMAIN_GTT:
- i915_gem_flush_ggtt_writes(dev_priv);
+ for_each_ggtt_vma(vma, obj)
+ intel_gt_flush_ggtt_writes(vma->vm->gt);
intel_fb_obj_flush(obj,
fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
@@ -340,6 +340,7 @@ i915_gem_object_flush_write_domain(struct
drm_i915_gem_object *obj,
i915_vma_unset_ggtt_write(vma);
}
+
break;
case I915_GEM_DOMAIN_WC:
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 5c81f4b4813a..2812f7fa27fe 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -6,6 +6,7 @@
#include
+#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "huge_gem_object.h"
#include "i915_selftest.h"
@@ -143,7 +144,7 @@ static int check_partial_mapping(struct drm_i915_gem_object
*obj,
if (offset >= obj->base.size)
continue;
- i915_gem_flush_ggtt_writes(to_i915(obj->base.dev));
+ intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
cpu = kmap(p) + offset_in_page(offset);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5c9be38713db..4fd9977fe284 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -150,3 +150,44 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
intel_gt_clear_error_registers(gt, ALL_ENGINES);
}
+
+void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ intel_wakeref_t wakeref;
+
+ /*
+* No actual flushing is required for the GTT write domain for reads
+* from the GTT domain. Writes to it "immediately" go to main memory
+* as far as we know, so there's no chipset flush. It also doesn't
+* land in the GPU render cache.
+*
+* However, we do have to enforce the order so that all writes through
+* the GTT land before any writes to the device, such as updates to
+* the GATT itself.
+*
+* We also have to wait a bit for the writes to land from the GTT.
+* An uncached read (i.e. mmio) seems to be ideal for the round-trip
+* timing. This issue has only been observed when switching quickly
+* between GTT writes and CPU reads from inside the kernel on recent hw,
+* and it appears to only affect discrete GTT blocks (i.e. on LLC
+* system agents we cannot reproduce this behaviour, until Cannonlake
+* that was!).
+*/
+
+ wmb();
+
+ if (INTEL_INFO(i915)->has_coherent_ggtt)
+ return;
+
+ i915_gem_chipset_flush(i915);
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ struct intel_uncore *uncore = gt->uncore;
+
+ spin_lock_
[Intel-gfx] [CI 05/33] drm/i915: Move intel_gt_pm_init under intel_gt_init_early
From: Tvrtko Ursulin
And also rename to intel_gt_pm_init_early and make it operate on gt.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 6 +++---
drivers/gpu/drm/i915/gt/intel_gt_pm.h| 3 ++-
drivers/gpu/drm/i915/i915_gem.c | 2 --
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 1 -
5 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index eccb52cf37b6..f760c2e0253e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_gt.h"
+#include "intel_gt_pm.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -16,4 +17,6 @@ void intel_gt_init_early(struct intel_gt *gt, struct
drm_i915_private *i915)
INIT_LIST_HEAD(>->closed_vma);
spin_lock_init(>->closed_lock);
+
+ intel_gt_pm_init_early(gt);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 7b5967751762..6062840b5b46 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -80,10 +80,10 @@ void intel_gt_pm_put(struct drm_i915_private *i915)
intel_wakeref_put(&i915->runtime_pm, &i915->gt.wakeref, intel_gt_park);
}
-void intel_gt_pm_init(struct drm_i915_private *i915)
+void intel_gt_pm_init_early(struct intel_gt *gt)
{
- intel_wakeref_init(&i915->gt.wakeref);
- BLOCKING_INIT_NOTIFIER_HEAD(&i915->gt.pm_notifications);
+ intel_wakeref_init(>->wakeref);
+ BLOCKING_INIT_NOTIFIER_HEAD(>->pm_notifications);
}
static bool reset_engines(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 7dd1130a19a4..b6049a907890 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -10,6 +10,7 @@
#include
struct drm_i915_private;
+struct intel_gt;
enum {
INTEL_GT_UNPARK,
@@ -19,7 +20,7 @@ enum {
void intel_gt_pm_get(struct drm_i915_private *i915);
void intel_gt_pm_put(struct drm_i915_private *i915);
-void intel_gt_pm_init(struct drm_i915_private *i915);
+void intel_gt_pm_init_early(struct intel_gt *gt);
void intel_gt_sanitize(struct drm_i915_private *i915, bool force);
void intel_gt_resume(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fc8fd41dd32e..9de1b1e88949 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1746,8 +1746,6 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
{
int err;
- intel_gt_pm_init(dev_priv);
-
i915_gem_init__mm(dev_priv);
i915_gem_init__pm(dev_priv);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 2b87200477f6..021ba42a3a00 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,7 +181,6 @@ struct drm_i915_private *mock_gem_device(void)
mock_uncore_init(&i915->uncore);
i915_gem_init__mm(i915);
intel_gt_init_early(&i915->gt, i915);
- intel_gt_pm_init(i915);
atomic_inc(&i915->gt.wakeref.count); /* disable; no hw support */
init_waitqueue_head(&i915->gpu_error.wait_queue);
--
2.20.1
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[Intel-gfx] [CI 13/33] drm/i915: Convert i915_ppgtt_init_hw to intel_gt
From: Tvrtko Ursulin
More removal of implicit dev_priv from using old mmio accessors.
v2:
* Rebase for uncore_to_i915 removal.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 101 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +-
3 files changed, 67 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 26caa0b5b5d7..769cfb15e6ca 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1267,7 +1267,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
if (ret)
goto out;
- ret = i915_ppgtt_init_hw(dev_priv);
+ ret = i915_ppgtt_init_hw(&dev_priv->gt);
if (ret) {
DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
goto out;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 697e8511ab24..9eba5460ad14 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1720,25 +1720,29 @@ static inline void gen6_write_pde(const struct
gen6_ppgtt *ppgtt,
ppgtt->pd_addr + pde);
}
-static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
+static void gen7_ppgtt_enable(struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
u32 ecochk, ecobits;
enum intel_engine_id id;
- ecobits = I915_READ(GAC_ECO_BITS);
- I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
+ ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
+ intel_uncore_write(uncore,
+ GAC_ECO_BITS,
+ ecobits | ECOBITS_PPGTT_CACHE64B);
- ecochk = I915_READ(GAM_ECOCHK);
- if (IS_HASWELL(dev_priv)) {
+ ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
+ if (IS_HASWELL(i915)) {
ecochk |= ECOCHK_PPGTT_WB_HSW;
} else {
ecochk |= ECOCHK_PPGTT_LLC_IVB;
ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
}
- I915_WRITE(GAM_ECOCHK, ecochk);
+ intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
- for_each_engine(engine, dev_priv, id) {
+ for_each_engine(engine, i915, id) {
/* GFX_MODE is per-ring on gen7+ */
ENGINE_WRITE(engine,
RING_MODE_GEN7,
@@ -1746,22 +1750,30 @@ static void gen7_ppgtt_enable(struct drm_i915_private
*dev_priv)
}
}
-static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
+static void gen6_ppgtt_enable(struct intel_gt *gt)
{
+ struct intel_uncore *uncore = gt->uncore;
u32 ecochk, gab_ctl, ecobits;
- ecobits = I915_READ(GAC_ECO_BITS);
- I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
- ECOBITS_PPGTT_CACHE64B);
+ ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
+ intel_uncore_write(uncore,
+ GAC_ECO_BITS,
+ ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
- gab_ctl = I915_READ(GAB_CTL);
- I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
+ gab_ctl = intel_uncore_read(uncore, GAB_CTL);
+ intel_uncore_write(uncore,
+ GAB_CTL,
+ gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
- ecochk = I915_READ(GAM_ECOCHK);
- I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
+ ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
+ intel_uncore_write(uncore,
+ GAM_ECOCHK,
+ ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
- if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
- I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+ if (HAS_PPGTT(uncore->i915)) /* may be disabled for VT-d */
+ intel_uncore_write(uncore,
+ GFX_MODE,
+ _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
}
/* PPGTT support for Sandybdrige/Gen6 and later */
@@ -2174,21 +2186,32 @@ static struct i915_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
return ERR_PTR(err);
}
-static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
+static void gtt_write_workarounds(struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+
/* This function is for gtt related workarounds. This function is
* called on driver load and after a GPU reset, so you can place
* workarounds here even if they get overwritten by GPU reset.
*/
/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
- if
[Intel-gfx] [CI 11/33] drm/i915: Store backpointer to intel_gt in the engine
From: Tvrtko Ursulin
It will come useful in the next patch.
v2:
* Do mock_engine as well.
v3:
* And the virtual engine...
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 1 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/mock_engine.c| 1 +
4 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5e4bf738ee59..dd23fcaced52 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -316,6 +316,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
engine->id = id;
engine->mask = BIT(id);
engine->i915 = dev_priv;
+ engine->gt = &dev_priv->gt;
engine->uncore = &dev_priv->uncore;
__sprint_engine_name(engine->name, info);
engine->hw_id = engine->guc_id = info->hw_id;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9940bad37812..fb65e96fa36b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -36,6 +36,7 @@ struct drm_i915_reg_table;
struct i915_gem_context;
struct i915_request;
struct i915_sched_attr;
+struct intel_gt;
struct intel_uncore;
typedef u8 intel_engine_mask_t;
@@ -257,6 +258,7 @@ struct intel_engine_execlists {
struct intel_engine_cs {
struct drm_i915_private *i915;
+ struct intel_gt *gt;
struct intel_uncore *uncore;
char name[INTEL_ENGINE_CS_MAX_NAME];
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f8ad49006917..afb351ed4089 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3363,6 +3363,7 @@ intel_execlists_create_virtual(struct i915_gem_context
*ctx,
return ERR_PTR(-ENOMEM);
ve->base.i915 = ctx->i915;
+ ve->base.gt = siblings[0]->gt;
ve->base.id = -1;
ve->base.class = OTHER_CLASS;
ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index 486c6953dcb1..b022af3385f3 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -257,6 +257,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private
*i915,
/* minimal engine setup for requests */
engine->base.i915 = i915;
+ engine->base.gt = &i915->gt;
snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
engine->base.id = id;
engine->base.mask = BIT(id);
--
2.20.1
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[Intel-gfx] [CI 14/33] drm/i915: Consolidate some open coded mmio rmw
From: Tvrtko Ursulin
Replace some gen6/7 open coded rmw with intel_uncore_rmw.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 41 +
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9eba5460ad14..7c543e067623 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1725,13 +1725,10 @@ static void gen7_ppgtt_enable(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
- u32 ecochk, ecobits;
enum intel_engine_id id;
+ u32 ecochk;
- ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
- intel_uncore_write(uncore,
- GAC_ECO_BITS,
- ecobits | ECOBITS_PPGTT_CACHE64B);
+ intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
if (IS_HASWELL(i915)) {
@@ -1753,22 +1750,21 @@ static void gen7_ppgtt_enable(struct intel_gt *gt)
static void gen6_ppgtt_enable(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
- u32 ecochk, gab_ctl, ecobits;
- ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
- intel_uncore_write(uncore,
- GAC_ECO_BITS,
- ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
+ intel_uncore_rmw(uncore,
+GAC_ECO_BITS,
+0,
+ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
- gab_ctl = intel_uncore_read(uncore, GAB_CTL);
- intel_uncore_write(uncore,
- GAB_CTL,
- gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
+ intel_uncore_rmw(uncore,
+GAB_CTL,
+0,
+GAB_CTL_CONT_AFTER_PAGEFAULT);
- ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
- intel_uncore_write(uncore,
- GAM_ECOCHK,
- ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
+ intel_uncore_rmw(uncore,
+GAM_ECOCHK,
+0,
+ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
if (HAS_PPGTT(uncore->i915)) /* may be disabled for VT-d */
intel_uncore_write(uncore,
@@ -2226,11 +,10 @@ static void gtt_write_workarounds(struct intel_gt *gt)
*/
if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
INTEL_GEN(i915) <= 10)
- intel_uncore_write(uncore,
- GEN8_GAMW_ECO_DEV_RW_IA,
- intel_uncore_read(uncore,
-GEN8_GAMW_ECO_DEV_RW_IA) |
- GAMW_ECO_ENABLE_64K_IPS_FIELD);
+ intel_uncore_rmw(uncore,
+GEN8_GAMW_ECO_DEV_RW_IA,
+0,
+GAMW_ECO_ENABLE_64K_IPS_FIELD);
}
int i915_ppgtt_init_hw(struct intel_gt *gt)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 30/33] drm/i915: Save trip via top-level i915 in a few more places
From: Tvrtko Ursulin
For gt related operations it makes more logical sense to stay in the realm
of gt instead of dereferencing via driver i915.
This patch handles a few of the easy ones with work requiring more
refactoring still outstanding.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 3 +--
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 3 +--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8
drivers/gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
11 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index dcf60a8c229e..2154cdee4ab3 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1039,8 +1039,7 @@ static int __igt_write_huge(struct i915_gem_context *ctx,
u64 size, u64 offset,
u32 dword, u32 val)
{
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
+ struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
unsigned int flags = PIN_USER | PIN_OFFSET_FIXED;
struct i915_vma *vma;
int err;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index f2d4e773404a..167c4a57c4cd 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -234,8 +234,7 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
struct intel_engine_cs *engine,
unsigned int dw)
{
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
+ struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
struct i915_request *rq;
struct i915_vma *vma;
struct i915_vma *batch;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dd23fcaced52..5fee1e184b6b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -584,7 +584,7 @@ static int init_status_page(struct intel_engine_cs *engine)
i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
- vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto err;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index afb351ed4089..dd266a7aa499 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1954,7 +1954,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs
*engine)
if (IS_ERR(obj))
return PTR_ERR(obj);
- vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto err;
@@ -3038,7 +3038,7 @@ static int execlists_context_deferred_alloc(struct
intel_context *ce,
if (IS_ERR(ctx_obj))
return PTR_ERR(ctx_obj);
- vma = i915_vma_instance(ctx_obj, &engine->i915->ggtt.vm, NULL);
+ vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto error_deref_obj;
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index c946c42d4834..e8e00df056e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -1414,7 +1414,7 @@ alloc_context_vma(struct intel_engine_cs *engine)
i915_gem_object_unpin_map(obj);
}
- vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto err_obj;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 140cf3f24141..c70445adfb02 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1
[Intel-gfx] [CI 07/33] drm/i915: Convert i915_gem_init_swizzling to intel_gt
From: Tvrtko Ursulin
Start using the newly introduced struct intel_gt to fuse together correct
logical init flow with uncore for more removal of implicit dev_priv in
mmio access.
v2:
* Move code to i915_gem_fence_reg. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem.c | 25 +--
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 37 +++
drivers/gpu/drm/i915/i915_gem_fence_reg.h | 3 ++
5 files changed, 43 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ef4100ed49fd..c02fdefcb356 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2957,7 +2957,7 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uc_resume(dev_priv);
- i915_gem_init_swizzling(dev_priv);
+ intel_gt_init_swizzling(&dev_priv->gt);
i915_gem_restore_fences(dev_priv);
enable_rpm_wakeref_asserts(rpm);
@@ -3059,7 +3059,7 @@ static int intel_runtime_resume(struct device *kdev)
* No point of rolling back things in case of an error, as the best
* we can do is to hope that things will still work (and disable RPM).
*/
- i915_gem_init_swizzling(dev_priv);
+ intel_gt_init_swizzling(&dev_priv->gt);
i915_gem_restore_fences(dev_priv);
/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3509eb88b452..44196bed4d81 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2537,7 +2537,6 @@ bool i915_gem_unset_wedged(struct drm_i915_private
*dev_priv);
void i915_gem_init_mmio(struct drm_i915_private *i915);
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
void i915_gem_fini(struct drm_i915_private *dev_priv);
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9de1b1e88949..30da603ee7fd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1202,29 +1202,6 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
}
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
-{
- if (INTEL_GEN(dev_priv) < 5 ||
- dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
- return;
-
- I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-DISP_TILE_SURFACE_SWIZZLING);
-
- if (IS_GEN(dev_priv, 5))
- return;
-
- I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
- if (IS_GEN(dev_priv, 6))
- I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
- else if (IS_GEN(dev_priv, 7))
- I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
- else if (IS_GEN(dev_priv, 8))
- I915_WRITE(GAMTARBMODE,
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
- else
- BUG();
-}
-
static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
{
I915_WRITE(RING_CTL(base), 0);
@@ -1271,7 +1248,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
/* ...and determine whether they are sticking. */
intel_gt_verify_workarounds(dev_priv, "init");
- i915_gem_init_swizzling(dev_priv);
+ intel_gt_init_swizzling(&dev_priv->gt);
/*
* At least 830 can leave some of the unused rings
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 0bf53ac1c835..dd09790c420d 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -834,3 +834,40 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
i915_gem_restore_fences(i915);
}
+
+void intel_gt_init_swizzling(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+
+ if (INTEL_GEN(i915) < 5 ||
+ i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+ return;
+
+ intel_uncore_write(uncore,
+ DISP_ARB_CTL,
+ intel_uncore_read(uncore, DISP_ARB_CTL) |
+ DISP_TILE_SURFACE_SWIZZLING);
+
+ if (IS_GEN(i915, 5))
+ return;
+
+ intel_uncore_write(uncore,
+ TILECTL,
+ intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);
+
+ if (IS_GEN(i915,
[Intel-gfx] [CI 31/33] drm/i915: Make timelines gt centric
From: Tvrtko Ursulin
Our timelines are stored inside intel_gt so we can convert the interface
to take exactly that and not i915.
At the same time re-order the params to our more typical layout and
replace the backpointer to the new containing structure.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +--
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 2 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 2 +-
drivers/gpu/drm/i915/i915_timeline.c | 43 +--
drivers/gpu/drm/i915/i915_timeline.h | 7 ++-
drivers/gpu/drm/i915/i915_timeline_types.h| 2 +-
.../gpu/drm/i915/selftests/i915_timeline.c| 8 ++--
.../gpu/drm/i915/selftests/mock_timeline.c| 2 +-
10 files changed, 38 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 35871c8a42a6..fb691535fbf2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -530,7 +530,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
unsigned int flags)
if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
struct i915_timeline *timeline;
- timeline = i915_timeline_create(dev_priv, NULL);
+ timeline = i915_timeline_create(&dev_priv->gt, NULL);
if (IS_ERR(timeline)) {
context_close(ctx);
return ERR_CAST(timeline);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5fee1e184b6b..89edf97d8ad7 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -740,8 +740,8 @@ static int measure_breadcrumb_dw(struct intel_engine_cs
*engine)
if (!frame)
return -ENOMEM;
- if (i915_timeline_init(engine->i915,
- &frame->timeline,
+ if (i915_timeline_init(&frame->timeline,
+ engine->gt,
engine->status_page.vma))
goto out_frame;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index dd266a7aa499..fa86dd519b01 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3005,12 +3005,13 @@ populate_lr_context(struct intel_context *ce,
return ret;
}
-static struct i915_timeline *get_timeline(struct i915_gem_context *ctx)
+static struct i915_timeline *
+get_timeline(struct i915_gem_context *ctx, struct intel_gt *gt)
{
if (ctx->timeline)
return i915_timeline_get(ctx->timeline);
else
- return i915_timeline_create(ctx->i915, NULL);
+ return i915_timeline_create(gt, NULL);
}
static int execlists_context_deferred_alloc(struct intel_context *ce,
@@ -3044,7 +3045,7 @@ static int execlists_context_deferred_alloc(struct
intel_context *ce,
goto error_deref_obj;
}
- timeline = get_timeline(ce->gem_context);
+ timeline = get_timeline(ce->gem_context, engine->gt);
if (IS_ERR(timeline)) {
ret = PTR_ERR(timeline);
goto error_deref_obj;
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index e8e00df056e1..9a748be0ce0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -2273,7 +2273,7 @@ int intel_ring_submission_init(struct intel_engine_cs
*engine)
struct intel_ring *ring;
int err;
- timeline = i915_timeline_create(engine->i915, engine->status_page.vma);
+ timeline = i915_timeline_create(engine->gt, engine->status_page.vma);
if (IS_ERR(timeline)) {
err = PTR_ERR(timeline);
goto err;
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index b022af3385f3..423027aa71cd 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -56,7 +56,7 @@ static struct intel_ring *mock_ring(struct intel_engine_cs
*engine)
if (!ring)
return NULL;
- if (i915_timeline_init(engine->i915, &ring->timeline, NULL)) {
+ if (i915_timeline_init(&ring->timeline, engine->gt, NULL)) {
kfree(ring);
return NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index dc885a13b16d..3e2c3169dc69 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -4,6 +4,8 @@
* Copyright © 2016-2018 Intel Corporation
*/
+#include "gt/intel_gt_types.h"
+
#include "i915_drv.
[Intel-gfx] [CI 28/33] drm/i915: Store ggtt pointer in intel_gt
From: Tvrtko Ursulin
This will become useful in the following patch.
v2:
* Assign the pointer through a helper on the top level to work around
the layering violation. (Chris)
v3:
* Handle selftests.
v4:
* Move call to intel_gt_init_hw into mock_init_ggtt. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt.c| 5 +
drivers/gpu/drm/i915/gt/intel_gt.h| 1 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 ++
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 ++
5 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f632b7b5b490..e22ee3e823fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -22,6 +22,11 @@ void intel_gt_init_early(struct intel_gt *gt, struct
drm_i915_private *i915)
intel_gt_pm_init_early(gt);
}
+void intel_gt_init_hw(struct drm_i915_private *i915)
+{
+ i915->gt.ggtt = &i915->ggtt;
+}
+
static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
{
intel_uncore_rmw(uncore, reg, 0, set);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index fb064758b591..29cd15be6a01 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -12,6 +12,7 @@
struct drm_i915_private;
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
+void intel_gt_init_hw(struct drm_i915_private *i915);
void intel_gt_check_and_clear_faults(struct intel_gt *gt);
void intel_gt_clear_error_registers(struct intel_gt *gt,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 86a4985f8e84..be891492505d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -17,11 +17,13 @@
#include "intel_wakeref.h"
struct drm_i915_private;
+struct i915_ggtt;
struct intel_uncore;
struct intel_gt {
struct drm_i915_private *i915;
struct intel_uncore *uncore;
+ struct i915_ggtt *ggtt;
struct i915_gt_timelines {
struct mutex mutex; /* protects list, tainted by GPU */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c02fdefcb356..4a211d5e2701 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1593,6 +1593,8 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
if (ret)
goto err_ggtt;
+ intel_gt_init_hw(dev_priv);
+
ret = i915_ggtt_enable_hw(dev_priv);
if (ret) {
DRM_ERROR("failed to enable GGTT\n");
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c
b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index 215372f75eec..e62a67e0f79c 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -117,6 +117,8 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct
i915_ggtt *ggtt)
ggtt->vm.vma_ops.clear_pages = clear_pages;
i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
+
+ intel_gt_init_hw(i915);
}
void mock_fini_ggtt(struct i915_ggtt *ggtt)
--
2.20.1
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[Intel-gfx] [CI 17/33] drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw
From: Tvrtko Ursulin
More legacy mmio accessor removal. We pass in intel_gt explicitly allowing
code to use new intel_uncore_read/write helpers.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem.c| 2 +-
drivers/gpu/drm/i915/intel_wopcm.c | 31 --
drivers/gpu/drm/i915/intel_wopcm.h | 4 +++-
3 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1760a0761130..8966f32fe2a2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1272,7 +1272,7 @@ static int init_hw(struct intel_gt *gt)
goto out;
}
- ret = intel_wopcm_init_hw(&i915->wopcm);
+ ret = intel_wopcm_init_hw(&i915->wopcm, gt);
if (ret) {
DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
goto out;
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 7b4ba84b9fb8..931987e37241 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -225,17 +225,18 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
return 0;
}
-static inline int write_and_verify(struct drm_i915_private *dev_priv,
- i915_reg_t reg, u32 val, u32 mask,
- u32 locked_bit)
+static int
+write_and_verify(struct intel_gt *gt,
+i915_reg_t reg, u32 val, u32 mask, u32 locked_bit)
{
+ struct intel_uncore *uncore = gt->uncore;
u32 reg_val;
GEM_BUG_ON(val & ~mask);
- I915_WRITE(reg, val);
+ intel_uncore_write(uncore, reg, val);
- reg_val = I915_READ(reg);
+ reg_val = intel_uncore_read(uncore, reg);
return (reg_val & mask) != (val | locked_bit) ? -EIO : 0;
}
@@ -250,29 +251,30 @@ static inline int write_and_verify(struct
drm_i915_private *dev_priv,
*
* Return: 0 on success. -EIO if registers were locked with incorrect values.
*/
-int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
+int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt)
{
- struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
+ struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
+ struct intel_uncore *uncore = gt->uncore;
u32 huc_agent;
u32 mask;
int err;
- if (!USES_GUC(dev_priv))
+ if (!USES_GUC(i915))
return 0;
- GEM_BUG_ON(!HAS_GUC(dev_priv));
+ GEM_BUG_ON(!HAS_GUC(i915));
GEM_BUG_ON(!wopcm->guc.size);
GEM_BUG_ON(!wopcm->guc.base);
- err = write_and_verify(dev_priv, GUC_WOPCM_SIZE, wopcm->guc.size,
+ err = write_and_verify(gt, GUC_WOPCM_SIZE, wopcm->guc.size,
GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED,
GUC_WOPCM_SIZE_LOCKED);
if (err)
goto err_out;
- huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
+ huc_agent = USES_HUC(i915) ? HUC_LOADING_AGENT_GUC : 0;
mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
- err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
+ err = write_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
wopcm->guc.base | huc_agent, mask,
GUC_WOPCM_OFFSET_VALID);
if (err)
@@ -283,8 +285,9 @@ int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
err_out:
DRM_ERROR("Failed to init WOPCM registers:\n");
DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
- I915_READ(DMA_GUC_WOPCM_OFFSET));
- DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));
+ intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
+ DRM_ERROR("GUC_WOPCM_SIZE=%#x\n",
+ intel_uncore_read(uncore, GUC_WOPCM_SIZE));
return err;
}
diff --git a/drivers/gpu/drm/i915/intel_wopcm.h
b/drivers/gpu/drm/i915/intel_wopcm.h
index 114401971520..56aaed4d64ff 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_wopcm.h
@@ -9,6 +9,8 @@
#include
+struct intel_gt;
+
/**
* struct intel_wopcm - Overall WOPCM info and WOPCM regions.
* @size: Size of overall WOPCM.
@@ -41,6 +43,6 @@ static inline u32 intel_wopcm_guc_size(struct intel_wopcm
*wopcm)
void intel_wopcm_init_early(struct intel_wopcm *wopcm);
int intel_wopcm_init(struct intel_wopcm *wopcm);
-int intel_wopcm_init_hw(struct intel_wopcm *wopcm);
+int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt);
#endif
--
2.20.1
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[Intel-gfx] [CI 27/33] drm/i915: Compartmentalize i915_gem_init_ggtt
From: Tvrtko Ursulin
Continuing on the theme of better logical organization of our code, make
the first step towards making the ggtt code better isolated from wider
struct drm_i915_private.
v2:
* Bring the ickle onion unwind back. (Chris)
* Rename to i915_init_ggtt. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
3 files changed, 29 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ae36955d819a..50d7e1e8d8ad 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1510,7 +1510,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
mutex_lock(&dev_priv->drm.struct_mutex);
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
- ret = i915_gem_init_ggtt(dev_priv);
+ ret = i915_init_ggtt(dev_priv);
if (ret) {
GEM_BUG_ON(ret == -EIO);
goto err_unlock;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d10590f868b7..44a32ccbd922 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2816,7 +2816,13 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
drm_mm_remove_node(&ggtt->uc_fw);
}
-int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
+static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
+{
+ ggtt_release_guc_top(ggtt);
+ drm_mm_remove_node(&ggtt->error_capture);
+}
+
+static int init_ggtt(struct i915_ggtt *ggtt)
{
/* Let GEM Manage all of the aperture.
*
@@ -2827,7 +2833,6 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
* aperture. One page should be enough to keep any prefetching inside
* of the aperture.
*/
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
unsigned long hole_start, hole_end;
struct drm_mm_node *entry;
int ret;
@@ -2839,7 +2844,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
* why.
*/
ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
- intel_wopcm_guc_size(&dev_priv->wopcm));
+ intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
ret = intel_vgt_balloon(ggtt);
if (ret)
@@ -2860,7 +2865,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
*/
ret = ggtt_reserve_guc_top(ggtt);
if (ret)
- goto err_reserve;
+ goto err;
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
@@ -2873,19 +2878,28 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
/* And finally clear the reserved guard page */
ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
- if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
- ret = init_aliasing_ppgtt(dev_priv);
+ return 0;
+
+err:
+ cleanup_init_ggtt(ggtt);
+ return ret;
+}
+
+int i915_init_ggtt(struct drm_i915_private *i915)
+{
+ int ret;
+
+ ret = init_ggtt(&i915->ggtt);
+ if (ret)
+ return ret;
+
+ if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
+ ret = init_aliasing_ppgtt(i915);
if (ret)
- goto err_appgtt;
+ cleanup_init_ggtt(&i915->ggtt);
}
return 0;
-
-err_appgtt:
- ggtt_release_guc_top(ggtt);
-err_reserve:
- drm_mm_remove_node(&ggtt->error_capture);
- return ret;
}
static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 6d1aad555ffa..e8b9ebe50c4e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -655,7 +655,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
void i915_ggtt_enable_guc(struct drm_i915_private *i915);
void i915_ggtt_disable_guc(struct drm_i915_private *i915);
-int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
+int i915_init_ggtt(struct drm_i915_private *dev_priv);
void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
int i915_ppgtt_init_hw(struct intel_gt *gt);
--
2.20.1
___
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[Intel-gfx] [CI 16/33] drm/i915: Move intel_engines_resume into common init
From: Tvrtko Ursulin
Since this part still operates on i915 and not intel_gt, move it to the
common (top-level) function.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 29 ++---
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 989d987c42d4..1760a0761130 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1287,17 +1287,10 @@ static int init_hw(struct intel_gt *gt)
intel_mocs_init_l3cc_table(gt);
- /* Only when the HW is re-initialised, can we replay the requests */
- ret = intel_engines_resume(i915);
- if (ret)
- goto cleanup_uc;
-
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
return 0;
-cleanup_uc:
- intel_uc_fini_hw(i915);
out:
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
@@ -1306,6 +1299,7 @@ static int init_hw(struct intel_gt *gt)
int i915_gem_init_hw(struct drm_i915_private *i915)
{
+ struct intel_uncore *uncore = &i915->uncore;
int ret;
BUG_ON(!i915->kernel_context);
@@ -1313,7 +1307,28 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
if (ret)
return ret;
+ /* Double layer security blanket, see i915_gem_init() */
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
+
ret = init_hw(&i915->gt);
+ if (ret)
+ goto err_init;
+
+ /* Only when the HW is re-initialised, can we replay the requests */
+ ret = intel_engines_resume(i915);
+ if (ret)
+ goto err_engines;
+
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
+
+ intel_engines_set_scheduler_caps(i915);
+
+ return 0;
+
+err_engines:
+ intel_uc_fini_hw(i915);
+err_init:
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
intel_engines_set_scheduler_caps(i915);
--
2.20.1
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[Intel-gfx] [CI 21/33] drm/i915: Store intel_gt backpointer in vm
From: Tvrtko Ursulin
This will come useful in the following patch.
v2:
* Handle mock ggtt.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 16 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/selftests/mock_gtt.c | 1 +
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 17f690f9d95d..1467b65c9a10 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1603,9 +1603,11 @@ static int gen8_preallocate_top_level_pdp(struct
i915_ppgtt *ppgtt)
return -ENOMEM;
}
-static void ppgtt_init(struct drm_i915_private *i915,
- struct i915_ppgtt *ppgtt)
+static void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
+
+ ppgtt->vm.gt = gt;
ppgtt->vm.i915 = i915;
ppgtt->vm.dma = &i915->drm.pdev->dev;
ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
@@ -1634,7 +1636,7 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- ppgtt_init(i915, ppgtt);
+ ppgtt_init(ppgtt, &i915->gt);
/*
* From bdw, there is hw support for read-only pages in the PPGTT.
@@ -2141,7 +2143,7 @@ static struct i915_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- ppgtt_init(i915, &ppgtt->base);
+ ppgtt_init(&ppgtt->base, &i915->gt);
ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
@@ -3452,10 +3454,12 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
return 0;
}
-static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct drm_i915_private *i915)
+static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
int ret;
+ ggtt->vm.gt = gt;
ggtt->vm.i915 = i915;
ggtt->vm.dma = &i915->drm.pdev->dev;
@@ -3501,7 +3505,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
int ret;
- ret = ggtt_probe_hw(&i915->ggtt, i915);
+ ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index ca8ba458a310..6d1aad555ffa 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -288,6 +288,7 @@ struct i915_address_space {
struct rcu_work rcu;
struct drm_mm mm;
+ struct intel_gt *gt;
struct drm_i915_private *i915;
struct device *dma;
/* Every address space belongs to a struct file - except for the global
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c
b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index f625c307a406..215372f75eec 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -98,6 +98,7 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct
i915_ggtt *ggtt)
{
memset(ggtt, 0, sizeof(*ggtt));
+ ggtt->vm.gt = &i915->gt;
ggtt->vm.i915 = i915;
ggtt->vm.is_ggtt = true;
--
2.20.1
___
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[Intel-gfx] [CI 32/33] drm/i915: Rename i915_timeline to intel_timeline and move under gt
From: Tvrtko Ursulin
Move all timeline code under gt and rename to intel_gt prefix.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/Makefile.header-test | 1 -
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +-
.../gpu/drm/i915/gem/i915_gem_context_types.h | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 2 +-
drivers/gpu/drm/i915/gt/intel_engine.h| 4 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 14 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 10 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 18 +--
.../{i915_timeline.c => gt/intel_timeline.c} | 108
drivers/gpu/drm/i915/gt/intel_timeline.h | 93 +
.../intel_timeline_types.h} | 6 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 10 +-
.../selftest_timeline.c} | 122 +-
.../i915/{ => gt}/selftests/mock_timeline.c | 6 +-
.../i915/{ => gt}/selftests/mock_timeline.h | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 8 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_request.c | 14 +-
drivers/gpu/drm/i915/i915_request.h | 8 +-
drivers/gpu/drm/i915/i915_timeline.h | 93 -
.../drm/i915/selftests/i915_live_selftests.h | 2 +-
.../drm/i915/selftests/i915_mock_selftests.h | 2 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
27 files changed, 279 insertions(+), 280 deletions(-)
rename drivers/gpu/drm/i915/{i915_timeline.c => gt/intel_timeline.c} (82%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_timeline.h
rename drivers/gpu/drm/i915/{i915_timeline_types.h =>
gt/intel_timeline_types.h} (93%)
rename drivers/gpu/drm/i915/{selftests/i915_timeline.c =>
gt/selftest_timeline.c} (87%)
rename drivers/gpu/drm/i915/{ => gt}/selftests/mock_timeline.c (72%)
rename drivers/gpu/drm/i915/{ => gt}/selftests/mock_timeline.h (53%)
delete mode 100644 drivers/gpu/drm/i915/i915_timeline.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 19f8b6745772..84ac0fd1b8d0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -82,6 +82,7 @@ gt-y += \
gt/intel_ringbuffer.o \
gt/intel_mocs.o \
gt/intel_sseu.o \
+ gt/intel_timeline.o \
gt/intel_workarounds.o
gt-$(CONFIG_DRM_I915_SELFTEST) += \
gt/mock_engine.o
@@ -127,7 +128,6 @@ i915-y += \
i915_query.o \
i915_request.o \
i915_scheduler.o \
- i915_timeline.o \
i915_trace_points.o \
i915_vma.o \
intel_wopcm.o
diff --git a/drivers/gpu/drm/i915/Makefile.header-test
b/drivers/gpu/drm/i915/Makefile.header-test
index cb74242f9c3b..b1c3e642f621 100644
--- a/drivers/gpu/drm/i915/Makefile.header-test
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -12,7 +12,6 @@ header_test := \
i915_priolist_types.h \
i915_reg.h \
i915_scheduler_types.h \
- i915_timeline_types.h \
i915_utils.h \
intel_csr.h \
intel_drv.h \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index fb691535fbf2..628673d1d7f8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -316,7 +316,7 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
mutex_destroy(&ctx->engines_mutex);
if (ctx->timeline)
- i915_timeline_put(ctx->timeline);
+ intel_timeline_put(ctx->timeline);
kfree(ctx->name);
put_pid(ctx->pid);
@@ -528,9 +528,9 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
unsigned int flags)
}
if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
- struct i915_timeline *timeline;
+ struct intel_timeline *timeline;
- timeline = i915_timeline_create(&dev_priv->gt, NULL);
+ timeline = intel_timeline_create(&dev_priv->gt, NULL);
if (IS_ERR(timeline)) {
context_close(ctx);
return ERR_CAST(timeline);
@@ -2015,8 +2015,8 @@ static int clone_timeline(struct i915_gem_context *dst,
GEM_BUG_ON(src->timeline == dst->timeline);
if (dst->timeline)
- i915_timeline_put(dst->timeline);
- dst->timeline = i915_timeline_get(src->timeline);
+ intel_timeline_put(dst->timeline);
+ dst->timeline = intel_timeline_get(src->timeline);
}
return 0;
diff --git a/drivers/gpu/d
[Intel-gfx] [CI 29/33] drm/i915: Compartmentalize ring buffer creation
From: Tvrtko Ursulin
Continuing on the theme of compartmentalizing the code better to make
future split between gt and display in global i915 clearer.
v2:
* Pass in ggtt instead of gt. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 8b1da57c3764..c946c42d4834 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -1234,16 +1234,16 @@ void intel_ring_unpin(struct intel_ring *ring)
i915_timeline_unpin(ring->timeline);
}
-static struct i915_vma *
-intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
+static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
{
- struct i915_address_space *vm = &dev_priv->ggtt.vm;
+ struct i915_address_space *vm = &ggtt->vm;
+ struct drm_i915_private *i915 = vm->i915;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- obj = i915_gem_object_create_stolen(dev_priv, size);
+ obj = i915_gem_object_create_stolen(i915, size);
if (!obj)
- obj = i915_gem_object_create_internal(dev_priv, size);
+ obj = i915_gem_object_create_internal(i915, size);
if (IS_ERR(obj))
return ERR_CAST(obj);
@@ -1270,6 +1270,7 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
struct i915_timeline *timeline,
int size)
{
+ struct drm_i915_private *i915 = engine->i915;
struct intel_ring *ring;
struct i915_vma *vma;
@@ -1290,12 +1291,12 @@ intel_engine_create_ring(struct intel_engine_cs *engine,
* of the buffer.
*/
ring->effective_size = size;
- if (IS_I830(engine->i915) || IS_I845G(engine->i915))
+ if (IS_I830(i915) || IS_I845G(i915))
ring->effective_size -= 2 * CACHELINE_BYTES;
intel_ring_update_space(ring);
- vma = intel_ring_create_vma(engine->i915, size);
+ vma = create_ring_vma(engine->gt->ggtt, size);
if (IS_ERR(vma)) {
kfree(ring);
return ERR_CAST(vma);
--
2.20.1
___
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[Intel-gfx] [CI 25/33] drm/i915: Compartmentalize timeline_init/park/fini
From: Tvrtko Ursulin
Continuing on the theme of better logical organization of our code, make
the first step towards making the timeline code better isolated from wider
struct drm_i915_private.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_timeline.c | 67 +---
1 file changed, 41 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index c311ce9c6f9d..dc885a13b16d 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -261,18 +261,23 @@ int i915_timeline_init(struct drm_i915_private *i915,
return 0;
}
-void i915_timelines_init(struct drm_i915_private *i915)
+static void timelines_init(struct intel_gt *gt)
{
- struct i915_gt_timelines *gt = &i915->gt.timelines;
+ struct i915_gt_timelines *timelines = >->timelines;
- mutex_init(>->mutex);
- INIT_LIST_HEAD(>->active_list);
+ mutex_init(&timelines->mutex);
+ INIT_LIST_HEAD(&timelines->active_list);
- spin_lock_init(>->hwsp_lock);
- INIT_LIST_HEAD(>->hwsp_free_list);
+ spin_lock_init(&timelines->hwsp_lock);
+ INIT_LIST_HEAD(&timelines->hwsp_free_list);
/* via i915_gem_wait_for_idle() */
- i915_gem_shrinker_taints_mutex(i915, >->mutex);
+ i915_gem_shrinker_taints_mutex(gt->i915, &timelines->mutex);
+}
+
+void i915_timelines_init(struct drm_i915_private *i915)
+{
+ timelines_init(&i915->gt);
}
static void timeline_add_to_active(struct i915_timeline *tl)
@@ -293,6 +298,24 @@ static void timeline_remove_from_active(struct
i915_timeline *tl)
mutex_unlock(>->mutex);
}
+static void timelines_park(struct intel_gt *gt)
+{
+ struct i915_gt_timelines *timelines = >->timelines;
+ struct i915_timeline *timeline;
+
+ mutex_lock(&timelines->mutex);
+ list_for_each_entry(timeline, &timelines->active_list, link) {
+ /*
+* All known fences are completed so we can scrap
+* the current sync point tracking and start afresh,
+* any attempt to wait upon a previous sync point
+* will be skipped as the fence was signaled.
+*/
+ i915_syncmap_free(&timeline->sync);
+ }
+ mutex_unlock(&timelines->mutex);
+}
+
/**
* i915_timelines_park - called when the driver idles
* @i915: the drm_i915_private device
@@ -305,20 +328,7 @@ static void timeline_remove_from_active(struct
i915_timeline *tl)
*/
void i915_timelines_park(struct drm_i915_private *i915)
{
- struct i915_gt_timelines *gt = &i915->gt.timelines;
- struct i915_timeline *timeline;
-
- mutex_lock(>->mutex);
- list_for_each_entry(timeline, >->active_list, link) {
- /*
-* All known fences are completed so we can scrap
-* the current sync point tracking and start afresh,
-* any attempt to wait upon a previous sync point
-* will be skipped as the fence was signaled.
-*/
- i915_syncmap_free(&timeline->sync);
- }
- mutex_unlock(>->mutex);
+ timelines_park(&i915->gt);
}
void i915_timeline_fini(struct i915_timeline *timeline)
@@ -563,14 +573,19 @@ void __i915_timeline_free(struct kref *kref)
kfree(timeline);
}
-void i915_timelines_fini(struct drm_i915_private *i915)
+static void timelines_fini(struct intel_gt *gt)
{
- struct i915_gt_timelines *gt = &i915->gt.timelines;
+ struct i915_gt_timelines *timelines = >->timelines;
- GEM_BUG_ON(!list_empty(>->active_list));
- GEM_BUG_ON(!list_empty(>->hwsp_free_list));
+ GEM_BUG_ON(!list_empty(&timelines->active_list));
+ GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
- mutex_destroy(>->mutex);
+ mutex_destroy(&timelines->mutex);
+}
+
+void i915_timelines_fini(struct drm_i915_private *i915)
+{
+ timelines_fini(&i915->gt);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
--
2.20.1
___
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[Intel-gfx] [CI 20/33] drm/i915: Make ggtt invalidation work on ggtt
From: Tvrtko Ursulin
It is more logical for ggtt invalidation to take ggtt as input parameter.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 51 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
2 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6f86c8e051fe..17f690f9d95d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -110,9 +110,9 @@
static int
i915_get_ggtt_vma_pages(struct i915_vma *vma);
-static void gen6_ggtt_invalidate(struct drm_i915_private *i915)
+static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
{
- struct intel_uncore *uncore = &i915->uncore;
+ struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
/*
* Note that as an uncached mmio write, this will flush the
@@ -121,24 +121,19 @@ static void gen6_ggtt_invalidate(struct drm_i915_private
*i915)
intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
}
-static void guc_ggtt_invalidate(struct drm_i915_private *i915)
+static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
{
- struct intel_uncore *uncore = &i915->uncore;
+ struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
- gen6_ggtt_invalidate(i915);
+ gen6_ggtt_invalidate(ggtt);
intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
}
-static void gmch_ggtt_invalidate(struct drm_i915_private *i915)
+static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
{
intel_gtt_chipset_flush();
}
-static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
-{
- i915->ggtt.invalidate(i915);
-}
-
static int ppgtt_bind_vma(struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 unused)
@@ -1904,7 +1899,7 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
if (flush) {
mark_tlbs_dirty(&ppgtt->base);
- gen6_ggtt_invalidate(vm->i915);
+ gen6_ggtt_invalidate(&vm->i915->ggtt);
}
goto out;
@@ -2010,7 +2005,7 @@ static int pd_vma_bind(struct i915_vma *vma,
gen6_write_pde(ppgtt, pde, pt);
mark_tlbs_dirty(&ppgtt->base);
- gen6_ggtt_invalidate(ppgtt->base.vm.i915);
+ gen6_ggtt_invalidate(ggtt);
return 0;
}
@@ -2290,7 +2285,7 @@ void i915_gem_suspend_gtt_mappings(struct
drm_i915_private *dev_priv)
ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
- i915_ggtt_invalidate(dev_priv);
+ ggtt->invalidate(ggtt);
}
int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
@@ -2336,7 +2331,7 @@ static void gen8_ggtt_insert_page(struct
i915_address_space *vm,
gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
- ggtt->invalidate(vm->i915);
+ ggtt->invalidate(ggtt);
}
static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
@@ -2364,7 +2359,7 @@ static void gen8_ggtt_insert_entries(struct
i915_address_space *vm,
* We want to flush the TLBs only after we're certain all the PTE
* updates have finished.
*/
- ggtt->invalidate(vm->i915);
+ ggtt->invalidate(ggtt);
}
static void gen6_ggtt_insert_page(struct i915_address_space *vm,
@@ -2379,7 +2374,7 @@ static void gen6_ggtt_insert_page(struct
i915_address_space *vm,
iowrite32(vm->pte_encode(addr, level, flags), pte);
- ggtt->invalidate(vm->i915);
+ ggtt->invalidate(ggtt);
}
/*
@@ -2405,7 +2400,7 @@ static void gen6_ggtt_insert_entries(struct
i915_address_space *vm,
* We want to flush the TLBs only after we're certain all the PTE
* updates have finished.
*/
- ggtt->invalidate(vm->i915);
+ ggtt->invalidate(ggtt);
}
static void nop_clear_range(struct i915_address_space *vm,
@@ -3600,25 +3595,29 @@ int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv)
void i915_ggtt_enable_guc(struct drm_i915_private *i915)
{
- GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
+ struct i915_ggtt *ggtt = &i915->ggtt;
- i915->ggtt.invalidate = guc_ggtt_invalidate;
+ GEM_BUG_ON(ggtt->invalidate != gen6_ggtt_invalidate);
- i915_ggtt_invalidate(i915);
+ ggtt->invalidate = guc_ggtt_invalidate;
+
+ ggtt->invalidate(ggtt);
}
void i915_ggtt_disable_guc(struct drm_i915_private *i915)
{
+ struct i915_ggtt *ggtt = &i915->ggtt;
+
/* XXX Temporary pardon for error unload */
- if (i915->ggtt.invalidate == gen6_ggtt_invalidate)
+ if (ggtt->invalidate == gen6_ggtt_invalidate)
return;
/* We should only be called after i915_ggtt_enable_guc() */
- GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
+ GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalida
[Intel-gfx] [CI 18/33] drm/i915: Compartmentalize i915_ggtt_probe_hw
From: Tvrtko Ursulin
Having made start to better code compartmentalization by introducing
struct intel_gt, continue the theme elsewhere in code by making functions
take parameters take what logically makes most sense for them instead of
the global struct drm_i915_private.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 31 +++--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7c543e067623..629683c52e50 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3457,21 +3457,16 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
return 0;
}
-/**
- * i915_ggtt_probe_hw - Probe GGTT hardware location
- * @dev_priv: i915 device
- */
-int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
+static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct drm_i915_private *i915)
{
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
int ret;
- ggtt->vm.i915 = dev_priv;
- ggtt->vm.dma = &dev_priv->drm.pdev->dev;
+ ggtt->vm.i915 = i915;
+ ggtt->vm.dma = &i915->drm.pdev->dev;
- if (INTEL_GEN(dev_priv) <= 5)
+ if (INTEL_GEN(i915) <= 5)
ret = i915_gmch_probe(ggtt);
- else if (INTEL_GEN(dev_priv) < 8)
+ else if (INTEL_GEN(i915) < 8)
ret = gen6_gmch_probe(ggtt);
else
ret = gen8_gmch_probe(ggtt);
@@ -3499,6 +3494,22 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);
DRM_DEBUG_DRIVER("DSM size = %lluM\n",
(u64)resource_size(&intel_graphics_stolen_res) >> 20);
+
+ return 0;
+}
+
+/**
+ * i915_ggtt_probe_hw - Probe GGTT hardware location
+ * @dev_priv: i915 device
+ */
+int i915_ggtt_probe_hw(struct drm_i915_private *i915)
+{
+ int ret;
+
+ ret = ggtt_probe_hw(&i915->ggtt, i915);
+ if (ret)
+ return ret;
+
if (intel_vtd_active())
DRM_INFO("VT-d active for gfx access\n");
--
2.20.1
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[Intel-gfx] [CI 24/33] drm/i915: Move i915_gem_chipset_flush to intel_gt
From: Tvrtko Ursulin
This aligns better with the rest of restructuring.
v2:
* Move call out of line. (Chris)
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 5 +++--
drivers/gpu/drm/i915/gem/i915_gem_phys.c| 3 ++-
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 4 +++-
drivers/gpu/drm/i915/gt/intel_gt.c | 9 -
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm/i915/gt/selftest_hangcheck.c| 14 ++
drivers/gpu/drm/i915/gt/selftest_workarounds.c | 5 +++--
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/selftests/i915_request.c | 10 ++
drivers/gpu/drm/i915/selftests/igt_spinner.c| 7 +--
drivers/gpu/drm/i915/selftests/igt_spinner.h| 3 +++
12 files changed, 46 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 5fae0e50aad0..cf8edb6822ee 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -16,6 +16,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gt/intel_context.h"
+#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "i915_gem_ioctls.h"
@@ -994,7 +995,7 @@ static void reloc_gpu_flush(struct reloc_cache *cache)
__i915_gem_object_flush_map(cache->rq->batch->obj, 0, cache->rq_size);
i915_gem_object_unpin_map(cache->rq->batch->obj);
- i915_gem_chipset_flush(cache->rq->i915);
+ intel_gt_chipset_flush(cache->rq->engine->gt);
i915_request_add(cache->rq);
cache->rq = NULL;
@@ -1954,7 +1955,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
eb->exec = NULL;
/* Unconditionally flush any chipset caches (for streaming writes). */
- i915_gem_chipset_flush(eb->i915);
+ intel_gt_chipset_flush(eb->engine->gt);
return 0;
err_skip:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 2deac933cf59..7b900ee4ed8d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -13,6 +13,7 @@
#include /* for drm_pci.h! */
#include
+#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
@@ -60,7 +61,7 @@ static int i915_gem_object_get_pages_phys(struct
drm_i915_gem_object *obj)
vaddr += PAGE_SIZE;
}
- i915_gem_chipset_flush(to_i915(obj->base.dev));
+ intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st) {
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index b74729b6f353..dcf60a8c229e 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -10,6 +10,8 @@
#include "gem/i915_gem_pm.h"
+#include "gt/intel_gt.h"
+
#include "igt_gem_utils.h"
#include "mock_context.h"
@@ -926,7 +928,7 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
}
*cmd = MI_BATCH_BUFFER_END;
- i915_gem_chipset_flush(i915);
+ intel_gt_chipset_flush(vma->vm->gt);
i915_gem_object_unpin_map(obj);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 4fd9977fe284..f632b7b5b490 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -180,7 +180,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
if (INTEL_INFO(i915)->has_coherent_ggtt)
return;
- i915_gem_chipset_flush(i915);
+ intel_gt_chipset_flush(gt);
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
struct intel_uncore *uncore = gt->uncore;
@@ -191,3 +191,10 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
spin_unlock_irq(&uncore->lock);
}
}
+
+void intel_gt_chipset_flush(struct intel_gt *gt)
+{
+ wmb();
+ if (INTEL_GEN(gt->i915) < 6)
+ intel_gtt_chipset_flush();
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 6073f3617caa..fb064758b591 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -18,5 +18,6 @@ void intel_gt_clear_error_registers(struct intel_gt *gt,
intel_engine_mask_t engine_mask);
void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
+void intel_gt_chipset_flush(struct intel_gt *gt);
#endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 1ee4c923044f..2d773f11e203 100644
--- a/drivers/gpu/drm/i915/gt/selftest_
[Intel-gfx] [CI 26/33] drm/i915: Compartmentalize i915_ggtt_cleanup_hw
From: Tvrtko Ursulin
Continuing on the theme of better logical organization of our code, make
the first step towards making the ggtt code better isolated from wider
struct drm_i915_private.
v2:
* Cleanup of mm.wc_stash does not need struct_mutex. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 55 -
1 file changed, 31 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b38af1df1fe9..d10590f868b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2775,14 +2775,19 @@ static void fini_aliasing_ppgtt(struct drm_i915_private
*i915)
struct i915_ggtt *ggtt = &i915->ggtt;
struct i915_ppgtt *ppgtt;
+ mutex_lock(&i915->drm.struct_mutex);
+
ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
if (!ppgtt)
- return;
+ goto out;
i915_vm_put(&ppgtt->vm);
ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
+
+out:
+ mutex_unlock(&i915->drm.struct_mutex);
}
static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
@@ -2883,20 +2888,14 @@ int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv)
return ret;
}
-/**
- * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
- * @dev_priv: i915 device
- */
-void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
+static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
{
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct drm_i915_private *i915 = ggtt->vm.i915;
struct i915_vma *vma, *vn;
- struct pagevec *pvec;
ggtt->vm.closed = true;
- mutex_lock(&dev_priv->drm.struct_mutex);
- fini_aliasing_ppgtt(dev_priv);
+ mutex_lock(&i915->drm.struct_mutex);
list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
WARN_ON(i915_vma_unbind(vma));
@@ -2913,18 +2912,31 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv)
ggtt->vm.cleanup(&ggtt->vm);
- pvec = &dev_priv->mm.wc_stash.pvec;
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ arch_phys_wc_del(ggtt->mtrr);
+ io_mapping_fini(&ggtt->iomap);
+}
+
+/**
+ * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
+ * @dev_priv: i915 device
+ */
+void i915_ggtt_cleanup_hw(struct drm_i915_private *i915)
+{
+ struct pagevec *pvec;
+
+ fini_aliasing_ppgtt(i915);
+
+ ggtt_cleanup_hw(&i915->ggtt);
+
+ pvec = &i915->mm.wc_stash.pvec;
if (pvec->nr) {
set_pages_array_wb(pvec->pages, pvec->nr);
__pagevec_release(pvec);
}
- mutex_unlock(&dev_priv->drm.struct_mutex);
-
- arch_phys_wc_del(ggtt->mtrr);
- io_mapping_fini(&ggtt->iomap);
-
- i915_gem_cleanup_stolen(dev_priv);
+ i915_gem_cleanup_stolen(i915);
}
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3520,11 +3532,6 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
return 0;
}
-static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
-{
- ggtt->vm.cleanup(&ggtt->vm);
-}
-
static int ggtt_init_hw(struct i915_ggtt *ggtt)
{
struct drm_i915_private *i915 = ggtt->vm.i915;
@@ -3545,7 +3552,7 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
if (!io_mapping_init_wc(&ggtt->iomap,
ggtt->gmadr.start,
ggtt->mappable_end)) {
- ggtt_cleanup_hw(ggtt);
+ ggtt->vm.cleanup(&ggtt->vm);
ret = -EIO;
goto out;
}
@@ -3590,7 +3597,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
return 0;
out_gtt_cleanup:
- ggtt_cleanup_hw(&dev_priv->ggtt);
+ dev_priv->ggtt.vm.cleanup(&dev_priv->ggtt.vm);
return ret;
}
--
2.20.1
___
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[Intel-gfx] [CI 22/33] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings
From: Tvrtko Ursulin
Having made start to better code compartmentalization by introducing
struct intel_gt, continue the theme elsewhere in code by making functions
take parameters take what logically makes most sense for them instead of
the global struct drm_i915_private.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1467b65c9a10..b38af1df1fe9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2273,23 +2273,28 @@ static bool needs_idle_maps(struct drm_i915_private
*dev_priv)
return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
}
-void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
+static void ggtt_suspend_mappings(struct i915_ggtt *ggtt)
{
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct drm_i915_private *i915 = ggtt->vm.i915;
/* Don't bother messing with faults pre GEN6 as we have little
* documentation supporting that it's a good idea.
*/
- if (INTEL_GEN(dev_priv) < 6)
+ if (INTEL_GEN(i915) < 6)
return;
- intel_gt_check_and_clear_faults(&dev_priv->gt);
+ intel_gt_check_and_clear_faults(ggtt->vm.gt);
ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
ggtt->invalidate(ggtt);
}
+void i915_gem_suspend_gtt_mappings(struct drm_i915_private *i915)
+{
+ ggtt_suspend_mappings(&i915->ggtt);
+}
+
int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
@@ -3624,12 +3629,11 @@ void i915_ggtt_disable_guc(struct drm_i915_private
*i915)
ggtt->invalidate(ggtt);
}
-void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
+static void ggtt_restore_mappings(struct i915_ggtt *ggtt)
{
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
struct i915_vma *vma, *vn;
- intel_gt_check_and_clear_faults(&dev_priv->gt);
+ intel_gt_check_and_clear_faults(ggtt->vm.gt);
mutex_lock(&ggtt->vm.mutex);
@@ -3666,12 +3670,17 @@ void i915_gem_restore_gtt_mappings(struct
drm_i915_private *dev_priv)
ggtt->invalidate(ggtt);
mutex_unlock(&ggtt->vm.mutex);
+}
+
+void i915_gem_restore_gtt_mappings(struct drm_i915_private *i915)
+{
+ ggtt_restore_mappings(&i915->ggtt);
- if (INTEL_GEN(dev_priv) >= 8) {
- struct intel_ppat *ppat = &dev_priv->ppat;
+ if (INTEL_GEN(i915) >= 8) {
+ struct intel_ppat *ppat = &i915->ppat;
bitmap_set(ppat->dirty, 0, ppat->max_entries);
- dev_priv->ppat.update_hw(dev_priv);
+ i915->ppat.update_hw(i915);
return;
}
}
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 33/33] drm/i915: Eliminate dual personality of i915_scratch_offset
From: Tvrtko Ursulin
Scratch vma lives under gt but the API used to work on i915. Make this
consistent by renaming the function to intel_gt_scratch_offset and make
it take struct intel_gt.
v2:
* Move to intel_gt. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 38 ++
drivers/gpu/drm/i915/gt/intel_gt.h | 8 +
drivers/gpu/drm/i915/gt/intel_lrc.c| 9 ++---
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 30 ++---
drivers/gpu/drm/i915/i915_drv.h| 5 ---
drivers/gpu/drm/i915/i915_gem.c| 31 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +--
8 files changed, 75 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index e30212e219ec..4961f74fd902 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -734,7 +734,7 @@ static int measure_breadcrumb_dw(struct intel_engine_cs
*engine)
struct measure_breadcrumb *frame;
int dw = -ENOMEM;
- GEM_BUG_ON(!engine->i915->gt.scratch);
+ GEM_BUG_ON(!engine->gt->scratch);
frame = kzalloc(sizeof(*frame), GFP_KERNEL);
if (!frame)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index e22ee3e823fa..8cca6b22b386 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -203,3 +203,41 @@ void intel_gt_chipset_flush(struct intel_gt *gt)
if (INTEL_GEN(gt->i915) < 6)
intel_gtt_chipset_flush();
}
+
+int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int ret;
+
+ obj = i915_gem_object_create_stolen(i915, size);
+ if (!obj)
+ obj = i915_gem_object_create_internal(i915, size);
+ if (IS_ERR(obj)) {
+ DRM_ERROR("Failed to allocate scratch page\n");
+ return PTR_ERR(obj);
+ }
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto err_unref;
+ }
+
+ ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ if (ret)
+ goto err_unref;
+
+ gt->scratch = vma;
+ return 0;
+
+err_unref:
+ i915_gem_object_put(obj);
+ return ret;
+}
+
+void intel_gt_fini_scratch(struct intel_gt *gt)
+{
+ i915_vma_unpin_and_release(>->scratch, 0);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 29cd15be6a01..cf3c6cecc8ee 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -21,4 +21,12 @@ void intel_gt_clear_error_registers(struct intel_gt *gt,
void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
void intel_gt_chipset_flush(struct intel_gt *gt);
+int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size);
+void intel_gt_fini_scratch(struct intel_gt *gt);
+
+static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt)
+{
+ return i915_ggtt_offset(gt->scratch);
+}
+
#endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4fce6895e9ab..e7c8ea4e1cce 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -135,6 +135,7 @@
#include "gem/i915_gem_context.h"
+#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_render_state.h"
#include "i915_vgpu.h"
@@ -1756,7 +1757,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine, u32 *batch)
/* NB no one else is allowed to scribble over scratch + 256! */
*batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
- *batch++ = i915_scratch_offset(engine->i915) + 256;
+ *batch++ = intel_gt_scratch_offset(engine->gt) + 256;
*batch++ = 0;
*batch++ = MI_LOAD_REGISTER_IMM(1);
@@ -1770,7 +1771,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine, u32 *batch)
*batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
- *batch++ = i915_scratch_offset(engine->i915) + 256;
+ *batch++ = intel_gt_scratch_offset(engine->gt) + 256;
*batch++ = 0;
return batch;
@@ -1807,7 +1808,7 @@ static u32 *gen8_init_indirectctx_bb(struct
intel_engine_cs *engine, u32 *batch)
PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_QW_WRITE,
- i915_scr
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/3] drm/i915/icl: Add new supported CD clocks
== Series Details == Series: series starting with [v2,1/3] drm/i915/icl: Add new supported CD clocks URL : https://patchwork.freedesktop.org/series/62490/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6318_full -> Patchwork_13378_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13378_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13378_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13378_full: ### IGT changes ### Possible regressions * igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-kbl4/igt@kms_cursor_...@pipe-b-cursor-64x64-offscreen.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-kbl2/igt@kms_cursor_...@pipe-b-cursor-64x64-offscreen.html Known issues Here are the changes found in Patchwork_13378_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-snb: [PASS][3] -> [DMESG-WARN][4] ([fdo#110789] / [fdo#110913 ]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-snb7/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-snb5/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#110913 ]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-apl4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-apl1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#110913 ]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-kbl3/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-kbl6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-apl4/igt@gem_workarou...@suspend-resume-context.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-apl2/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@gem-mmap-gtt: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#108840]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-iclb2/igt@i915_pm_...@gem-mmap-gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-iclb2/igt@i915_pm_...@gem-mmap-gtt.html * igt@kms_atomic_transition@2x-modeset-transitions-fencing: - shard-hsw: [PASS][13] -> [SKIP][14] ([fdo#109271]) +12 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-hsw7/igt@kms_atomic_transit...@2x-modeset-transitions-fencing.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-hsw1/igt@kms_atomic_transit...@2x-modeset-transitions-fencing.html * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy: - shard-glk: [PASS][15] -> [INCOMPLETE][16] ([fdo#103359] / [k.org#198133]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-glk7/igt@kms_cursor_leg...@2x-cursor-vs-flip-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-glk7/igt@kms_cursor_leg...@2x-cursor-vs-flip-legacy.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#109507]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-skl4/igt@kms_f...@flip-vs-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-skl10/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip_tiling@flip-x-tiled: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([fdo#103313]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6318/shard-kbl4/igt@kms_flip_til...@flip-x-tiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13378/shard-kbl2/igt@kms_flip_til...@flip-x-tiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +8 similar issues [2
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore
== Series Details == Series: series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore URL : https://patchwork.freedesktop.org/series/62496/ State : warning == Summary == $ dim checkpatch origin/drm-tip b8c60e2d0b66 drm/i915: Convert intel_vgt_(de)balloon to uncore 4a3508a80c72 drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt -:21: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #21: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 98 lines checked acd94baa8745 drm/i915: Move intel_gt initialization to a separate file -:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #35: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 83 lines checked dd8d717c7ec3 drm/i915: Store some backpointers in struct intel_gt 0fbc641c8480 drm/i915: Move intel_gt_pm_init under intel_gt_init_early 83c819ce1ec3 drm/i915: Make i915_check_and_clear_faults take intel_gt 373e5dbe52ba drm/i915: Convert i915_gem_init_swizzling to intel_gt 5f83e2b7dac0 drm/i915: Use intel_uncore_rmw in intel_gt_init_swizzling 03dd1a1caeb8 drm/i915: Convert init_unused_rings to intel_gt 85345da4c6c3 drm/i915: Convert gt workarounds to intel_gt 35ce8ec21338 drm/i915: Store backpointer to intel_gt in the engine e66e0bd16555 drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt cc14354560a8 drm/i915: Convert i915_ppgtt_init_hw to intel_gt f7489fb04cf9 drm/i915: Consolidate some open coded mmio rmw 9766e15093ba drm/i915: Convert i915_gem_init_hw to intel_gt -:128: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() #128: FILE: drivers/gpu/drm/i915/i915_gem.c:1311: + BUG_ON(!i915->kernel_context); total: 0 errors, 1 warnings, 0 checks, 116 lines checked acc6bf8adf46 drm/i915: Move intel_engines_resume into common init 6b7188c27677 drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw 4797e618e7db drm/i915: Compartmentalize i915_ggtt_probe_hw fae79514053f drm/i915: Compartmentalize i915_ggtt_init_hw 88d56344f4da drm/i915: Make ggtt invalidation work on ggtt 024c9b1906cf drm/i915: Store intel_gt backpointer in vm 3e1ecd9c50d1 drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings a5fd627fcf20 drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt -:114: WARNING:MEMORY_BARRIER: memory barrier without comment #114: FILE: drivers/gpu/drm/i915/gt/intel_gt.c:178: + wmb(); total: 0 errors, 1 warnings, 0 checks, 173 lines checked 5f5a8726e216 drm/i915: Move i915_gem_chipset_flush to intel_gt -:108: WARNING:MEMORY_BARRIER: memory barrier without comment #108: FILE: drivers/gpu/drm/i915/gt/intel_gt.c:197: + wmb(); total: 0 errors, 1 warnings, 0 checks, 268 lines checked 4bdbb1ce1bda drm/i915: Compartmentalize timeline_init/park/fini 434b5ed7ccc4 drm/i915: Compartmentalize i915_ggtt_cleanup_hw fea91a3802fb drm/i915: Compartmentalize i915_gem_init_ggtt e5143444dec7 drm/i915: Store ggtt pointer in intel_gt b2ea54bc79c9 drm/i915: Compartmentalize ring buffer creation 9d315c0ab0fe drm/i915: Save trip via top-level i915 in a few more places 1e06a432b0b6 drm/i915: Make timelines gt centric 18d2396124ea drm/i915: Rename i915_timeline to intel_timeline and move under gt -:342: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #342: rename from drivers/gpu/drm/i915/i915_timeline.c -:682: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #682: FILE: drivers/gpu/drm/i915/gt/intel_timeline.h:1: +/* total: 0 errors, 2 warnings, 0 checks, 1326 lines checked 5eefeb04c29c drm/i915: Eliminate dual personality of i915_scratch_offset ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/execlists: Keep context alive until after we kick
The call to kick_siblings() dereferences the rq->context, so we should
not drop our local reference until afterwards!
Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6522801af2d6..a9493f2cb38f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -544,9 +544,6 @@ execlists_schedule_out(struct i915_request *rq)
intel_engine_context_out(ce->inflight);
execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
- ce->inflight = NULL;
- intel_context_put(ce);
-
/*
* If this is part of a virtual engine, its next request may
* have been blocked waiting for access to the active context.
@@ -558,6 +555,9 @@ execlists_schedule_out(struct i915_request *rq)
*/
if (rq->engine != ce->engine)
kick_siblings(rq, ce);
+
+ ce->inflight = NULL;
+ intel_context_put(ce);
}
i915_request_put(rq);
--
2.20.1
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore
== Series Details == Series: series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore URL : https://patchwork.freedesktop.org/series/62496/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Convert intel_vgt_(de)balloon to uncore -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2811:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:2811:26: warning: expression using sizeof(void) Commit: drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915: Move intel_gt initialization to a separate file +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915: Store some backpointers in struct intel_gt Okay! Commit: drm/i915: Move intel_gt_pm_init under intel_gt_init_early Okay! Commit: drm/i915: Make i915_check_and_clear_faults take intel_gt Okay! Commit: drm/i915: Convert i915_gem_init_swizzling to intel_gt Okay! Commit: drm/i915: Use intel_uncore_rmw in intel_gt_init_swizzling Okay! Commit: drm/i915: Convert init_unused_rings to intel_gt Okay! Commit: drm/i915: Convert gt workarounds to intel_gt Okay! Commit: drm/i915: Store backpointer to intel_gt in the engine Okay! Commit: drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt Okay! Commit: drm/i915: Convert i915_ppgtt_init_hw to intel_gt Okay! Commit: drm/i915: Consolidate some open coded mmio rmw Okay! Commit: drm/i915: Convert i915_gem_init_hw to intel_gt Okay! Commit: drm/i915: Move intel_engines_resume into common init Okay! Commit: drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw Okay! Commit: drm/i915: Compartmentalize i915_ggtt_probe_hw Okay! Commit: drm/i915: Compartmentalize i915_ggtt_init_hw Okay! Commit: drm/i915: Make ggtt invalidation work on ggtt Okay! Commit: drm/i915: Store intel_gt backpointer in vm Okay! Commit: drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings Okay! Commit: drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt Okay! Commit: drm/i915: Move i915_gem_chipset_flush to intel_gt Okay! Commit: drm/i915: Compartmentalize timeline_init/park/fini Okay! Commit: drm/i915: Compartmentalize i915_ggtt_cleanup_hw -drivers/gpu/drm/i915/i915_gem_gtt.c:3498:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gem_gtt.c:3498:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:3498:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:3498:25: warning: expression using sizeof(void) Commit: drm/i915: Compartmentalize i915_gem_init_ggtt -O:drivers/gpu/drm/i915/i915_gem_gtt.c:2841:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:2846:26: warning: expression using sizeof(void) Commit: drm/i915: Store ggtt pointer in intel_gt Okay! Commit: drm/i915: Compartmentalize ring buffer creation Okay! Commit: drm/i915: Save trip via top-level i915 in a few more places Okay! Commit: drm/i915: Make timelines gt centric Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore
== Series Details == Series: series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore URL : https://patchwork.freedesktop.org/series/62496/ State : success == Summary == CI Bug Log - changes from CI_DRM_6320 -> Patchwork_13381 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/ Known issues Here are the changes found in Patchwork_13381 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_contexts: - fi-kbl-x1275: [PASS][1] -> [DMESG-FAIL][2] ([fdo#110235]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-kbl-x1275/igt@i915_selftest@live_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-kbl-x1275/igt@i915_selftest@live_contexts.html * igt@vgem_basic@sysfs: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-icl-u3/igt@vgem_ba...@sysfs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-icl-u3/igt@vgem_ba...@sysfs.html Possible fixes * igt@i915_module_load@reload: - fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-blb-e6850/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [INCOMPLETE][7] ([fdo#108602]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-skl-iommu/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-skl-iommu/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][11] ([fdo#103167]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (51 -> 44) -- Additional (1): fi-cml-u2 Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus Build changes - * Linux: CI_DRM_6320 -> Patchwork_13381 CI_DRM_6320: 6c42b26a62077226edcc8014ee5bca0366ae133b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13381: 5eefeb04c29c48d77ba63263b61a4ca56a3fd514 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5eefeb04c29c drm/i915: Eliminate dual personality of i915_scratch_offset 18d2396124ea drm/i915: Rename i915_timeline to intel_timeline and move under gt 1e06a432b0b6 drm/i915: Make timelines gt centric 9d315c0ab0fe drm/i915: Save trip via top-level i915 in a few more places b2ea54bc79c9 drm/i915: Compartmentalize ring buffer creation e5143444dec7 drm/i915: Store ggtt pointer in intel_gt fea91a3802fb drm/i915: Compartmentalize i915_gem_init_ggtt 434b5ed7ccc4 drm/i915: Compartmentalize i915_ggtt_cleanup_hw 4bdbb1ce1bda drm/i915: Compartmentalize timeline_init/park/fini 5f5a8726e216 drm/i915: Move i915_gem_chipset_flush to intel_gt a5fd627fcf20 drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt 3e1ecd9c50d1 drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings 024c9b1906cf drm/i915: Store intel_gt backpointer in vm 88d56344f4da drm/i915: Make ggtt invalidation work on ggtt fae79514053f drm/i915: Compartmentalize i915_ggtt_init_hw 4797e618e7db drm/i915: Compartmentalize i915_ggtt_probe_hw 6b7188c27677 drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw acc6bf8adf46 drm/i915: Move intel_engines_resume into common init 9766e15093ba drm/i915: Convert i915_gem_init_hw to intel_gt f7489fb04cf9 drm/i915: Consolidate some open coded mmio rmw cc14354560a8 drm/i915: Convert i915_ppgtt_init_hw to intel_gt e66e0bd16555 drm/i915: Convert int
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Keep context alive until after we kick
On 21/06/2019 08:33, Chris Wilson wrote:
The call to kick_siblings() dereferences the rq->context, so we should
not drop our local reference until afterwards!
Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6522801af2d6..a9493f2cb38f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -544,9 +544,6 @@ execlists_schedule_out(struct i915_request *rq)
intel_engine_context_out(ce->inflight);
execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
- ce->inflight = NULL;
- intel_context_put(ce);
-
/*
* If this is part of a virtual engine, its next request may
* have been blocked waiting for access to the active context.
@@ -558,6 +555,9 @@ execlists_schedule_out(struct i915_request *rq)
*/
if (rq->engine != ce->engine)
kick_siblings(rq, ce);
+
+ ce->inflight = NULL;
+ intel_context_put(ce);
}
i915_request_put(rq);
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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[Intel-gfx] [PATCH v2] drm/i915/execlists: Keep virtual context alive until after we kick
The call to kick_siblings() dereferences the rq->context, so we should
not drop our local reference until afterwards!
v2: Stick to setting ce.inflight=NULL before kicking as this is what the
other threads will check to see if the context is ready for takeover.
Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f8ad49006917..faa9a2e4e40b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -557,9 +557,6 @@ execlists_schedule_out(struct i915_request *rq)
intel_engine_context_out(ce->inflight);
execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
- ce->inflight = NULL;
- intel_context_put(ce);
-
/*
* If this is part of a virtual engine, its next request may
* have been blocked waiting for access to the active context.
@@ -569,8 +566,11 @@ execlists_schedule_out(struct i915_request *rq)
* request before the tasklet runs and do not need to rebuild
* each virtual tree and kick everyone again.
*/
+ ce->inflight = NULL;
if (rq->engine != ce->engine)
kick_siblings(rq, ce);
+
+ intel_context_put(ce);
}
i915_request_put(rq);
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Keep context alive until after we kick
== Series Details == Series: drm/i915/execlists: Keep context alive until after we kick URL : https://patchwork.freedesktop.org/series/62503/ State : success == Summary == CI Bug Log - changes from CI_DRM_6320 -> Patchwork_13382 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13382/ Known issues Here are the changes found in Patchwork_13382 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [PASS][1] -> [FAIL][2] ([fdo#108511]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13382/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@kms_busy@basic-flip-a: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-icl-u3/igt@kms_b...@basic-flip-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13382/fi-icl-u3/igt@kms_b...@basic-flip-a.html Possible fixes * igt@i915_module_load@reload: - fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-blb-e6850/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13382/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [INCOMPLETE][7] ([fdo#108602]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-skl-iommu/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13382/fi-skl-iommu/igt@i915_selftest@live_blt.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 Participating hosts (51 -> 44) -- Additional (1): fi-cml-u2 Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6320 -> Patchwork_13382 CI_DRM_6320: 6c42b26a62077226edcc8014ee5bca0366ae133b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13382: f937e1d2cc361a96b82ef08d31d23baa19b2ea04 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f937e1d2cc36 drm/i915/execlists: Keep context alive until after we kick == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13382/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Keep context alive until after we kick (rev2)
== Series Details == Series: drm/i915/execlists: Keep context alive until after we kick (rev2) URL : https://patchwork.freedesktop.org/series/62503/ State : success == Summary == CI Bug Log - changes from CI_DRM_6320 -> Patchwork_13383 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/ Known issues Here are the changes found in Patchwork_13383 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-icl-u2/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/fi-icl-u2/igt@debugfs_test@read_all_entries.html * igt@gem_ctx_param@basic: - fi-icl-dsi: [PASS][3] -> [DMESG-WARN][4] ([fdo#106107]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-icl-dsi/igt@gem_ctx_pa...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/fi-icl-dsi/igt@gem_ctx_pa...@basic.html * igt@i915_selftest@live_contexts: - fi-kbl-x1275: [PASS][5] -> [DMESG-FAIL][6] ([fdo#110235]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-kbl-x1275/igt@i915_selftest@live_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/fi-kbl-x1275/igt@i915_selftest@live_contexts.html Possible fixes * igt@i915_module_load@reload: - fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-blb-e6850/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [INCOMPLETE][9] ([fdo#108602]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-skl-iommu/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/fi-skl-iommu/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][11] ([fdo#109485]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (51 -> 44) -- Additional (1): fi-cml-u2 Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus fi-snb-2600 Build changes - * Linux: CI_DRM_6320 -> Patchwork_13383 CI_DRM_6320: 6c42b26a62077226edcc8014ee5bca0366ae133b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13383: 5acef2b8a2db661d4092962e69a17e9d02cfefc8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5acef2b8a2db drm/i915/execlists: Keep virtual context alive until after we kick == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for EHL port programming
== Series Details == Series: EHL port programming URL : https://patchwork.freedesktop.org/series/62492/ State : success == Summary == CI Bug Log - changes from CI_DRM_6319_full -> Patchwork_13379_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13379_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@execbuf: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#110913 ]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-apl3/igt@gem_...@execbuf.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-apl5/igt@gem_...@execbuf.html * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][3] -> [FAIL][4] ([fdo#109661]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-snb4/igt@gem_...@unwedge-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-snb1/igt@gem_...@unwedge-stress.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-snb: [PASS][5] -> [DMESG-WARN][6] ([fdo#110789] / [fdo#110913 ]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-snb7/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-snb2/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_persistent_relocs@forked-thrashing: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#110913 ]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-kbl7/igt@gem_persistent_rel...@forked-thrashing.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-kbl2/igt@gem_persistent_rel...@forked-thrashing.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-apl2/igt@gem_soft...@noreloc-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-apl7/igt@gem_soft...@noreloc-s3.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-skl3/igt@kms_fbcon_...@psr-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-skl2/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-snb: [PASS][13] -> [INCOMPLETE][14] ([fdo#105411]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-snb6/igt@kms_f...@flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-snb1/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#100368]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-glk6/igt@kms_f...@plain-flip-ts-check-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-glk8/igt@kms_f...@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite: - shard-hsw: [PASS][17] -> [SKIP][18] ([fdo#109271]) +19 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-hsw8/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108] / [fdo#106978]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-skl10/igt@kms_frontbuffer_track...@psr-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-skl3/igt@kms_frontbuffer_track...@psr-suspend.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103166]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-y.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_sprite_pl
Re: [Intel-gfx] [PATCH 3/5] drm/panel: Add attach/detach callbacks
On Tue, Jun 11, 2019 at 05:25:47PM -0700, dbasehore . wrote:
> On Tue, Jun 11, 2019 at 1:57 AM Daniel Vetter wrote:
> >
> > On Mon, Jun 10, 2019 at 09:03:48PM -0700, Derek Basehore wrote:
> > > This adds the attach/detach callbacks. These are for setting up
> > > internal state for the connector/panel pair that can't be done at
> > > probe (since the connector doesn't exist) and which don't need to be
> > > repeatedly done for every get/modes, prepare, or enable callback.
> > > Values such as the panel orientation, and display size can be filled
> > > in for the connector.
> > >
> > > Signed-off-by: Derek Basehore
> > > ---
> > > drivers/gpu/drm/drm_panel.c | 14 ++
> > > include/drm/drm_panel.h | 4
> > > 2 files changed, 18 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
> > > index 3b689ce4a51a..72f67678d9d5 100644
> > > --- a/drivers/gpu/drm/drm_panel.c
> > > +++ b/drivers/gpu/drm/drm_panel.c
> > > @@ -104,12 +104,23 @@ EXPORT_SYMBOL(drm_panel_remove);
> > > */
> > > int drm_panel_attach(struct drm_panel *panel, struct drm_connector
> > > *connector)
> > > {
> > > + int ret;
> > > +
> > > if (panel->connector)
> > > return -EBUSY;
> > >
> > > panel->connector = connector;
> > > panel->drm = connector->dev;
> > >
> > > + if (panel->funcs->attach) {
> > > + ret = panel->funcs->attach(panel);
> > > + if (ret < 0) {
> > > + panel->connector = NULL;
> > > + panel->drm = NULL;
> > > + return ret;
> > > + }
> > > + }
> >
> > Why can't we just implement this in the drm helpers for everyone, by e.g.
> > storing a dt node in drm_panel? Feels a bit overkill to have these new
> > hooks here.
> >
> > Also, my understanding is that this dt stuff is supposed to be
> > standardized, so this should work.
>
> So do you want all of this information added to the drm_panel struct?
> If we do that, we don't necessarily even need the drm helper function.
> We could just copy the values over here in the drm_panel_attach
> function (and clear them in drm_panel_detach).
Yeah, I think we should have all this extra information in the struct
drm_panel. However, I think we need to more carefully split things such
that the DT parsing happens at panel probe time. That way we can catch
errors in DT, or missing entries/resources when we can still do
something about it.
If we start parsing DT and encounter failures, it's going to be very
confusing if that's at panel attach time where code will usually just
assume that everything is already validated and can't fail anymore.
Thierry
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Re: [Intel-gfx] [PATCH 1/6] dma-buf: add dynamic DMA-buf handling v10
On Tue, Jun 18, 2019 at 01:54:50PM +0200, Christian König wrote:
> On the exporter side we add optional explicit pinning callbacks. If those
> callbacks are implemented the framework no longer caches sg tables and the
> map/unmap callbacks are always called with the lock of the reservation object
> held.
>
> On the importer side we add an optional invalidate callback. This callback is
> used by the exporter to inform the importers that their mappings should be
> destroyed as soon as possible.
>
> This allows the exporter to provide the mappings without the need to pin
> the backing store.
>
> v2: don't try to invalidate mappings when the callback is NULL,
> lock the reservation obj while using the attachments,
> add helper to set the callback
> v3: move flag for invalidation support into the DMA-buf,
> use new attach_info structure to set the callback
> v4: use importer_priv field instead of mangling exporter priv.
> v5: drop invalidation_supported flag
> v6: squash together with pin/unpin changes
> v7: pin/unpin takes an attachment now
> v8: nuke dma_buf_attachment_(map|unmap)_locked,
> everything is now handled backward compatible
> v9: always cache when export/importer don't agree on dynamic handling
> v10: minimal style cleanup
>
> Signed-off-by: Christian König
> ---
> drivers/dma-buf/dma-buf.c | 188 --
> include/linux/dma-buf.h | 109 --
> 2 files changed, 283 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
> index 6c15deb5d4ad..9c9c95a88655 100644
> --- a/drivers/dma-buf/dma-buf.c
> +++ b/drivers/dma-buf/dma-buf.c
> @@ -531,6 +531,9 @@ struct dma_buf *dma_buf_export(const struct
> dma_buf_export_info *exp_info)
> return ERR_PTR(-EINVAL);
> }
>
> + if (WARN_ON(exp_info->ops->cache_sgt_mapping && exp_info->ops->pin))
> + return ERR_PTR(-EINVAL);
> +
> if (!try_module_get(exp_info->owner))
> return ERR_PTR(-ENOENT);
>
> @@ -651,10 +654,12 @@ void dma_buf_put(struct dma_buf *dmabuf)
> EXPORT_SYMBOL_GPL(dma_buf_put);
>
> /**
> - * dma_buf_attach - Add the device to dma_buf's attachments list; optionally,
> + * dma_buf_dynamic_attach - Add the device to dma_buf's attachments list;
> optionally,
> * calls attach() of dma_buf_ops to allow device-specific attach
> functionality
> - * @dmabuf: [in]buffer to attach device to.
> - * @dev: [in]device to be attached.
> + * @dmabuf: [in]buffer to attach device to.
> + * @dev: [in]device to be attached.
> + * @importer_ops [in]importer operations for the attachment
> + * @importer_priv[in]importer private pointer for the attachment
> *
> * Returns struct dma_buf_attachment pointer for this attachment. Attachments
> * must be cleaned up by calling dma_buf_detach().
> @@ -668,8 +673,10 @@ EXPORT_SYMBOL_GPL(dma_buf_put);
> * accessible to @dev, and cannot be moved to a more suitable place. This is
> * indicated with the error code -EBUSY.
> */
> -struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
> - struct device *dev)
> +struct dma_buf_attachment *
> +dma_buf_dynamic_attach(struct dma_buf *dmabuf, struct device *dev,
> +const struct dma_buf_attach_ops *importer_ops,
> +void *importer_priv)
> {
> struct dma_buf_attachment *attach;
> int ret;
> @@ -683,6 +690,8 @@ struct dma_buf_attachment *dma_buf_attach(struct dma_buf
> *dmabuf,
>
> attach->dev = dev;
> attach->dmabuf = dmabuf;
> + attach->importer_ops = importer_ops;
> + attach->importer_priv = importer_priv;
>
> mutex_lock(&dmabuf->lock);
>
> @@ -691,16 +700,72 @@ struct dma_buf_attachment *dma_buf_attach(struct
> dma_buf *dmabuf,
> if (ret)
> goto err_attach;
> }
> + reservation_object_lock(dmabuf->resv, NULL);
> list_add(&attach->node, &dmabuf->attachments);
> + reservation_object_unlock(dmabuf->resv);
>
> mutex_unlock(&dmabuf->lock);
>
> + /* When either the importer or the exporter can't handle dynamic
> + * mappings we cache the mapping here to avoid issues with the
> + * reservation object lock.
> + */
> + if (dma_buf_attachment_is_dynamic(attach) !=
> + dma_buf_is_dynamic(dmabuf)) {
> + struct sg_table *sgt;
> +
> + if (dma_buf_is_dynamic(attach->dmabuf)) {
> + reservation_object_lock(attach->dmabuf->resv, NULL);
> + ret = dma_buf_pin(attach);
> + if (ret)
> + goto err_unlock;
> + }
> +
> + sgt = dmabuf->ops->map_dma_buf(attach, DMA_BIDIRECTIONAL);
> + if (!sgt)
> + sgt = ERR_PTR(-ENOMEM);
> + if (IS_ERR(sgt)) {
> +
Re: [Intel-gfx] [PATCH 1/6] dma-buf: add dynamic DMA-buf handling v10
Am 21.06.19 um 11:20 schrieb Daniel Vetter:
On Tue, Jun 18, 2019 at 01:54:50PM +0200, Christian König wrote:
On the exporter side we add optional explicit pinning callbacks. If those
callbacks are implemented the framework no longer caches sg tables and the
map/unmap callbacks are always called with the lock of the reservation object
held.
On the importer side we add an optional invalidate callback. This callback is
used by the exporter to inform the importers that their mappings should be
destroyed as soon as possible.
This allows the exporter to provide the mappings without the need to pin
the backing store.
v2: don't try to invalidate mappings when the callback is NULL,
lock the reservation obj while using the attachments,
add helper to set the callback
v3: move flag for invalidation support into the DMA-buf,
use new attach_info structure to set the callback
v4: use importer_priv field instead of mangling exporter priv.
v5: drop invalidation_supported flag
v6: squash together with pin/unpin changes
v7: pin/unpin takes an attachment now
v8: nuke dma_buf_attachment_(map|unmap)_locked,
everything is now handled backward compatible
v9: always cache when export/importer don't agree on dynamic handling
v10: minimal style cleanup
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 188 --
include/linux/dma-buf.h | 109 --
2 files changed, 283 insertions(+), 14 deletions(-)
[SNIP]
+ if (dma_buf_attachment_is_dynamic(attach)) {
+ reservation_object_assert_held(attach->dmabuf->resv);
+
+ /*
+* Mapping a DMA-buf can trigger its invalidation, prevent
+* sending this event to the caller by temporary removing
+* this attachment from the list.
+*/
+ list_del(&attach->node);
I'm still hung up about this, that still feels like leaking random ttm
implementation details into the dma-buf interfaces. And it's asymmetric:
- When acquiring a buffer mapping (whether p2p or system memory sg or
whatever) we always have to wait for pending fences before we can access
the buffer. At least for full dynamic dma-buf access.
- Same is true when dropping a mapping: We could drop the mapping
immediately, but only actually release it when that fence has signalled.
Then this hack here wouldn't be necessary.
It feels a bit like this is just an artifact of how ttm currently does bo
moves with the shadow bo. There's other ways to fix that, you could just
have a memory manager reservation of a given range or whatever and a
release fence from when it's actually good to use.
No, that is for handling a completely different case :)
Imo the below semantics would be much cleaner:
- invalidate may add new fences
- invalidate _must_ unmap its mappings
- an unmap must wait for current fences before the mapping can be
released.
Imo there's no reason why unmap is special, and the only thing where we
don't use fences to gate access to resources/memory when it's in the
process of getting moved around.
Well in general I want to avoid waiting for fences as much as possible.
But the key point here is that this actually won't help with the problem
I'm trying to solve.
btw this is like the 2nd or 3rd time I'm typing this, haven't seen your
thoughts on this yet.
Yeah, and I'm responding for the 3rd time now that you are
misunderstanding why we need this here :)
Maybe I can make that clear with an example:
1. You got a sharing between device A (exporter) and B (importer) which
uses P2P.
2. Now device C (importer) comes along and wants to use the DMA-buf
object as well.
3. The handling now figures out that we can't do P2P between device A
and device C (for whatever reason).
4. The map_attachment implementation in device driver A doesn't want to
fail with -EBUSY and migrates the DMA-buf somewhere where both device A
and device C can access it.
5. This migration will result in sending an invalidation event around.
And here it doesn't make sense to send this invalidation event to device
C, because we know that device C is actually causing this event and
doesn't have a valid mapping.
One alternative would be to completely disallow buffer migration which
can cause invalidation in the drivers map_attachment call. But with
dynamic handling you definitely need to be able to migrate in the
map_attachment call for swapping evicted things back into a place where
they are accessible. So that would make it harder for drivers to get it
right.
Another alternative (and that's what I implemented initially) is to make
sure the driver calling map_attachment can handle invalidation events
re-entering itself while doing so. But then you add another tricky thing
for drivers to handle which could be done in the general code.
The reason I don't have that on unmap is that I think migrating things
on unmap
Re: [Intel-gfx] [PATCH 1/6] dma-buf: add dynamic DMA-buf handling v10
On Fri, Jun 21, 2019 at 11:55 AM Christian König
wrote:
>
> Am 21.06.19 um 11:20 schrieb Daniel Vetter:
> > On Tue, Jun 18, 2019 at 01:54:50PM +0200, Christian König wrote:
> >> On the exporter side we add optional explicit pinning callbacks. If those
> >> callbacks are implemented the framework no longer caches sg tables and the
> >> map/unmap callbacks are always called with the lock of the reservation
> >> object
> >> held.
> >>
> >> On the importer side we add an optional invalidate callback. This callback
> >> is
> >> used by the exporter to inform the importers that their mappings should be
> >> destroyed as soon as possible.
> >>
> >> This allows the exporter to provide the mappings without the need to pin
> >> the backing store.
> >>
> >> v2: don't try to invalidate mappings when the callback is NULL,
> >> lock the reservation obj while using the attachments,
> >> add helper to set the callback
> >> v3: move flag for invalidation support into the DMA-buf,
> >> use new attach_info structure to set the callback
> >> v4: use importer_priv field instead of mangling exporter priv.
> >> v5: drop invalidation_supported flag
> >> v6: squash together with pin/unpin changes
> >> v7: pin/unpin takes an attachment now
> >> v8: nuke dma_buf_attachment_(map|unmap)_locked,
> >> everything is now handled backward compatible
> >> v9: always cache when export/importer don't agree on dynamic handling
> >> v10: minimal style cleanup
> >>
> >> Signed-off-by: Christian König
> >> ---
> >> drivers/dma-buf/dma-buf.c | 188 --
> >> include/linux/dma-buf.h | 109 --
> >> 2 files changed, 283 insertions(+), 14 deletions(-)
> >>
> >> [SNIP]
> >> +if (dma_buf_attachment_is_dynamic(attach)) {
> >> +reservation_object_assert_held(attach->dmabuf->resv);
> >> +
> >> +/*
> >> + * Mapping a DMA-buf can trigger its invalidation, prevent
> >> + * sending this event to the caller by temporary removing
> >> + * this attachment from the list.
> >> + */
> >> +list_del(&attach->node);
> > I'm still hung up about this, that still feels like leaking random ttm
> > implementation details into the dma-buf interfaces. And it's asymmetric:
> >
> > - When acquiring a buffer mapping (whether p2p or system memory sg or
> >whatever) we always have to wait for pending fences before we can access
> >the buffer. At least for full dynamic dma-buf access.
> >
> > - Same is true when dropping a mapping: We could drop the mapping
> >immediately, but only actually release it when that fence has signalled.
> >Then this hack here wouldn't be necessary.
> >
> > It feels a bit like this is just an artifact of how ttm currently does bo
> > moves with the shadow bo. There's other ways to fix that, you could just
> > have a memory manager reservation of a given range or whatever and a
> > release fence from when it's actually good to use.
>
> No, that is for handling a completely different case :)
>
> >
> > Imo the below semantics would be much cleaner:
> >
> > - invalidate may add new fences
> > - invalidate _must_ unmap its mappings
> > - an unmap must wait for current fences before the mapping can be
> >released.
> >
> > Imo there's no reason why unmap is special, and the only thing where we
> > don't use fences to gate access to resources/memory when it's in the
> > process of getting moved around.
>
> Well in general I want to avoid waiting for fences as much as possible.
> But the key point here is that this actually won't help with the problem
> I'm trying to solve.
The point of using fences is not to wait on them. I mean if you have
the shadow ttm bo on the lru you also don't wait for that fence to
retire before you insert the shadow bo onto the lru. You don't even
wait when you try to use that memory again, you just pipeline more
stuff on top.
In the end it will be the exact same amount of fences and waiting in
both solutions. One just leaks less implementationt details (at least
in my opinion) across the dma-buf border.
> > btw this is like the 2nd or 3rd time I'm typing this, haven't seen your
> > thoughts on this yet.
>
> Yeah, and I'm responding for the 3rd time now that you are
> misunderstanding why we need this here :)
>
> Maybe I can make that clear with an example:
>
> 1. You got a sharing between device A (exporter) and B (importer) which
> uses P2P.
>
> 2. Now device C (importer) comes along and wants to use the DMA-buf
> object as well.
>
> 3. The handling now figures out that we can't do P2P between device A
> and device C (for whatever reason).
>
> 4. The map_attachment implementation in device driver A doesn't want to
> fail with -EBUSY and migrates the DMA-buf somewhere where both device A
> and device C can access it.
>
> 5. This migration will result in sending an invalidation event around.
> And here it doesn't make sense to send this invalida
Re: [Intel-gfx] [PATCH 09/59] drm/prime: Align gem_prime_export with obj_funcs.export
On Fri, Jun 14, 2019 at 10:35:25PM +0200, Daniel Vetter wrote:
> The idea is that gem_prime_export is deprecated in favor of
> obj_funcs.export. That's much easier to do if both have matching
> function signatures.
>
> Signed-off-by: Daniel Vetter
> Cc: Russell King
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Sean Paul
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Zhenyu Wang
> Cc: Zhi Wang
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Tomi Valkeinen
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "David (ChunMing) Zhou"
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: Dave Airlie
> Cc: Eric Anholt
> Cc: "Michel Dänzer"
> Cc: Chris Wilson
> Cc: Huang Rui
> Cc: Felix Kuehling
> Cc: Hawking Zhang
> Cc: Feifei Xu
> Cc: Jim Qu
> Cc: Evan Quan
> Cc: Matthew Auld
> Cc: Mika Kuoppala
> Cc: Thomas Zimmermann
> Cc: Kate Stewart
> Cc: Sumit Semwal
> Cc: Jilayne Lovejoy
> Cc: Thomas Gleixner
> Cc: Mikulas Patocka
> Cc: Greg Kroah-Hartman
> Cc: Junwei Zhang
> Cc: intel-gvt-...@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org
> Cc: amd-...@lists.freedesktop.org
> Cc: linux-te...@vger.kernel.org
Merged up to this one to drm-misc-next (for 5.4), thanks everyone for the
review and comments thus far.
-Daniel
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 7 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 3 +--
> drivers/gpu/drm/armada/armada_gem.c | 5 ++---
> drivers/gpu/drm/armada/armada_gem.h | 3 +--
> drivers/gpu/drm/drm_prime.c | 9 -
> drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 5 ++---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 8
> drivers/gpu/drm/i915/gvt/dmabuf.c| 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +--
> drivers/gpu/drm/omapdrm/omap_gem.h | 3 +--
> drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c| 5 ++---
> drivers/gpu/drm/radeon/radeon_drv.c | 3 +--
> drivers/gpu/drm/radeon/radeon_prime.c| 5 ++---
> drivers/gpu/drm/tegra/gem.c | 7 +++
> drivers/gpu/drm/tegra/gem.h | 3 +--
> drivers/gpu/drm/udl/udl_dmabuf.c | 5 ++---
> drivers/gpu/drm/udl/udl_drv.h| 3 +--
> drivers/gpu/drm/vc4/vc4_bo.c | 5 ++---
> drivers/gpu/drm/vc4/vc4_drv.h| 3 +--
> drivers/gpu/drm/vgem/vgem_fence.c| 2 +-
> include/drm/drm_drv.h| 4 ++--
> include/drm/drm_prime.h | 3 +--
> 22 files changed, 39 insertions(+), 57 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> index 489041df1f45..4809d4a5d72a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> @@ -345,8 +345,7 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = {
> * Returns:
> * Shared DMA buffer representing the GEM BO from the given device.
> */
> -struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
> - struct drm_gem_object *gobj,
> +struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
> int flags)
> {
> struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
> @@ -356,9 +355,9 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device
> *dev,
> bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
> return ERR_PTR(-EPERM);
>
> - buf = drm_gem_prime_export(dev, gobj, flags);
> + buf = drm_gem_prime_export(gobj, flags);
> if (!IS_ERR(buf)) {
> - buf->file->f_mapping = dev->anon_inode->i_mapping;
> + buf->file->f_mapping = gobj->dev->anon_inode->i_mapping;
> buf->ops = &amdgpu_dmabuf_ops;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
> index c7056cbe8685..7f73a4f94204 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
> @@ -30,8 +30,7 @@ struct drm_gem_object *
> amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
>struct dma_buf_attachment *attach,
>struct sg_table *sg);
> -struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
> - struct drm_gem_object *gobj,
> +struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
> int flags);
> struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
> struct dma_buf *dma_buf);
> diff --git a/drivers/gpu/drm/armada/armada_gem.c
> b/drivers/g
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Refine eDP aux backlight enable/disable sequence
== Series Details == Series: drm/i915: Refine eDP aux backlight enable/disable sequence URL : https://patchwork.freedesktop.org/series/62494/ State : success == Summary == CI Bug Log - changes from CI_DRM_6319_full -> Patchwork_13380_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13380_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@banned: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#110913 ]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-apl2/igt@gem_...@banned.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-apl3/igt@gem_...@banned.html * igt@gem_mmap_gtt@hang: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([fdo#105411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-snb1/igt@gem_mmap_...@hang.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-snb4/igt@gem_mmap_...@hang.html * igt@gem_persistent_relocs@forked-thrashing: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#110913 ]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-kbl7/igt@gem_persistent_rel...@forked-thrashing.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-kbl4/igt@gem_persistent_rel...@forked-thrashing.html * igt@gem_workarounds@suspend-resume-context: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-skl9/igt@gem_workarou...@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-skl3/igt@gem_workarou...@suspend-resume-context.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109349]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-iclb1/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_flip@flip-vs-suspend: - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([fdo#103359] / [k.org#198133]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-glk6/igt@kms_f...@flip-vs-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-glk4/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#109507]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-skl3/igt@kms_f...@flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-skl5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite: - shard-hsw: [PASS][17] -> [SKIP][18] ([fdo#109271]) +27 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-hsw8/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103166]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-y.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109642]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb2/igt@kms_psr2...@frontbuffer.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13380/shard-iclb1/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_sp
Re: [Intel-gfx] [PATCH 1/6] dma-buf: add dynamic DMA-buf handling v10
Am 21.06.19 um 12:32 schrieb Daniel Vetter: On Fri, Jun 21, 2019 at 11:55 AM Christian König wrote: Am 21.06.19 um 11:20 schrieb Daniel Vetter: On Tue, Jun 18, 2019 at 01:54:50PM +0200, Christian König wrote: [SNIP] Imo the below semantics would be much cleaner: - invalidate may add new fences - invalidate _must_ unmap its mappings - an unmap must wait for current fences before the mapping can be released. Imo there's no reason why unmap is special, and the only thing where we don't use fences to gate access to resources/memory when it's in the process of getting moved around. Well in general I want to avoid waiting for fences as much as possible. But the key point here is that this actually won't help with the problem I'm trying to solve. The point of using fences is not to wait on them. I mean if you have the shadow ttm bo on the lru you also don't wait for that fence to retire before you insert the shadow bo onto the lru. You don't even wait when you try to use that memory again, you just pipeline more stuff on top. Correct. Ok, if I understand it correctly your suggestion is to move the responsibility to delay destruction of mappings until they are no longer used from the importer to the exporter based on the fences of the reservation object. I seriously don't think that this is a good idea because you need to move the tracking who is using which mapping from the importer to the exporter as well. So duplicating quite a bunch of housekeeping. On the other hand that we have this house keeping in the importer because we get it for free from TTM. But I can't think of a way other memory management backends would do this without keeping the sg table around either. In the end it will be the exact same amount of fences and waiting in both solutions. One just leaks less implementationt details (at least in my opinion) across the dma-buf border. I agree that leaking implementation details over the DMA-buf border is a bad idea. But I can assure you that this has absolutely nothing todo with the ghost object handling of TTM. ghost objects doesn't even receive an invalidation, they are just a possible implementation of the delayed destruction of sg tables. btw this is like the 2nd or 3rd time I'm typing this, haven't seen your thoughts on this yet. Yeah, and I'm responding for the 3rd time now that you are misunderstanding why we need this here :) Maybe I can make that clear with an example: 1. You got a sharing between device A (exporter) and B (importer) which uses P2P. 2. Now device C (importer) comes along and wants to use the DMA-buf object as well. 3. The handling now figures out that we can't do P2P between device A and device C (for whatever reason). 4. The map_attachment implementation in device driver A doesn't want to fail with -EBUSY and migrates the DMA-buf somewhere where both device A and device C can access it. 5. This migration will result in sending an invalidation event around. And here it doesn't make sense to send this invalidation event to device C, because we know that device C is actually causing this event and doesn't have a valid mapping. Hm I thought the last time around there was a different scenario, with just one importer: - importer has a mapping, gets an ->invalidate call. - importer arranges for the mappings/usage to get torn down, maybe updating fences, all from ->invalidate. But the mapping itself wont disappear. - exporter moves buffer to new places (for whatever reasons it felt that was the thing to do). - importer does another execbuf, the exporter needs to move the buffer back. Again it calls ->invalidate, but on a mapping it already has called ->invalidate on, and to prevent that silliness we take the importer temporary off the list. Mhm, strange I don't remember giving this explanation. It also doesn't make to much sense, but see below. Your scenario here is new, and iirc my suggestion back then was to count the number of pending mappings so you don't go around calling ->invalidate on mappings that don't exist. Well the key point is we don't call invalidate on mappings, but we call invalidate on attachments. When the invalidate on an attachment is received all the importer should at least start to tear down all mappings. But even if you fix your scenario here there's still the issue that we can receive invalidates on a mapping we've already torn down and which is on the process of disappearing. That's kinda the part I don't think is great semantics. Yeah, that is a rather valid point. Currently it is perfectly valid to receive an invalidation when you don't even have any mappings at all. But this is intentional, because otherwise I would need to move the housekeeping which mappings are currently made from the importer to the exporter. And as explained above that would essentially mean double housekeeping. [SNIP] The reason I don't have that on unmap is that I think migrating things on unmap doesn'
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore
== Series Details == Series: series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore URL : https://patchwork.freedesktop.org/series/62496/ State : success == Summary == CI Bug Log - changes from CI_DRM_6320_full -> Patchwork_13381_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13381_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-iclb1/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-iclb7/igt@gem_exec_balan...@smoke.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-snb: [PASS][3] -> [DMESG-WARN][4] ([fdo#110789] / [fdo#110913 ]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-snb4/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-snb2/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#110913 ]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-apl8/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-apl1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html - shard-snb: [PASS][7] -> [DMESG-WARN][8] ([fdo#110913 ]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-snb7/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@kms_flip@2x-flip-vs-suspend-interruptible: - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([fdo#103540]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-hsw8/igt@kms_f...@2x-flip-vs-suspend-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-hsw2/igt@kms_f...@2x-flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt: - shard-hsw: [PASS][13] -> [SKIP][14] ([fdo#109271]) +22 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-hsw6/igt@kms_frontbuffer_track...@fbc-2p-primscrn-indfb-plflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-hsw1/igt@kms_frontbuffer_track...@fbc-2p-primscrn-indfb-plflip-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_setmode@basic: - shard-hsw: [PASS][19] -> [FAIL][20] ([fdo#99912]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-hsw1/igt@kms_setm...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-hsw8/igt@kms_setm...@basic.html * igt@perf_pmu@rc6: - shard-kbl: [PASS][21] -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-kbl4/igt@perf_...@rc6.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/shard-kbl1/igt@perf_...@rc6.html Possible fixes * igt@gem_ctx_isolation@vecs0-s3: - shard-skl: [INCOMPLETE][23] ([fdo#104108]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-skl5/igt@gem_ctx_isolat...@vecs0-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/sha
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore
On 21/06/2019 08:49, Patchwork wrote: == Series Details == Series: series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore URL : https://patchwork.freedesktop.org/series/62496/ State : success == Summary == CI Bug Log - changes from CI_DRM_6320 -> Patchwork_13381 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/ Known issues Here are the changes found in Patchwork_13381 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_contexts: - fi-kbl-x1275: [PASS][1] -> [DMESG-FAIL][2] ([fdo#110235]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-kbl-x1275/igt@i915_selftest@live_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-kbl-x1275/igt@i915_selftest@live_contexts.html * igt@vgem_basic@sysfs: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-icl-u3/igt@vgem_ba...@sysfs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-icl-u3/igt@vgem_ba...@sysfs.html Possible fixes * igt@i915_module_load@reload: - fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-blb-e6850/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [INCOMPLETE][7] ([fdo#108602]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-skl-iommu/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-skl-iommu/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][11] ([fdo#103167]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13381/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (51 -> 44) -- Additional (1): fi-cml-u2 Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus Build changes - * Linux: CI_DRM_6320 -> Patchwork_13381 CI_DRM_6320: 6c42b26a62077226edcc8014ee5bca0366ae133b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13381: 5eefeb04c29c48d77ba63263b61a4ca56a3fd514 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5eefeb04c29c drm/i915: Eliminate dual personality of i915_scratch_offset 18d2396124ea drm/i915: Rename i915_timeline to intel_timeline and move under gt 1e06a432b0b6 drm/i915: Make timelines gt centric 9d315c0ab0fe drm/i915: Save trip via top-level i915 in a few more places b2ea54bc79c9 drm/i915: Compartmentalize ring buffer creation e5143444dec7 drm/i915: Store ggtt pointer in intel_gt fea91a3802fb drm/i915: Compartmentalize i915_gem_init_ggtt 434b5ed7ccc4 drm/i915: Compartmentalize i915_ggtt_cleanup_hw 4bdbb1ce1bda drm/i915: Compartmentalize timeline_init/park/fini 5f5a8726e216 drm/i915: Move i915_gem_chipset_flush to intel_gt a5fd627fcf20 drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt 3e1ecd9c50d1 drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings 024c9b1906cf drm/i915: Store intel_gt backpointer in vm 88d56344f4da drm/i915: Make ggtt invalidation work on ggtt fae79514053f drm/i915: Compartmentalize i915_ggtt_init_hw 4797e618e7db drm/i915: Compartmentalize i915_ggtt_probe_hw 6b7188c27677 drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw acc6bf8adf46 drm/i915: Move intel_engines_resume into common init 9766e15093ba drm/i915: Convert i915_gem_init_hw to intel_gt f7489fb04cf9 drm/i915: Consolidate some open coded mmio rmw cc14354560a8
[Intel-gfx] [PATCH 1/5] drm/i915: Remove waiting & retiring from shrinker paths
i915_gem_wait_for_idle() and i915_retire_requests() introduce a
dependency on the timeline->mutex. This is problematic as we want to
later perform allocations underneath i915_active.mutex, forming a link
between the shrinker, the timeline and active mutexes. Nip this cycle in
the bud by removing the acquisition of the timeline mutex (i.e.
retiring) from inside the shrinker.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 10 --
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 3 ---
4 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 3a926a8755c6..1bbc690494c7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -169,7 +169,6 @@ i915_gem_shrink(struct drm_i915_private *i915,
*/
trace_i915_gem_shrink(i915, target, shrink);
- i915_retire_requests(i915);
/*
* Unbinding of objects will require HW access; Let us not wake the
@@ -269,8 +268,6 @@ i915_gem_shrink(struct drm_i915_private *i915,
if (shrink & I915_SHRINK_BOUND)
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
- i915_retire_requests(i915);
-
shrinker_unlock(i915, unlock);
if (nr_scanned)
@@ -427,12 +424,6 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned
long event, void *ptr
if (!shrinker_lock(i915, 0, &unlock))
return NOTIFY_DONE;
- /* Force everything onto the inactive lists */
- if (i915_gem_wait_for_idle(i915,
- I915_WAIT_LOCKED,
- MAX_SCHEDULE_TIMEOUT))
- goto out;
-
with_intel_runtime_pm(&i915->runtime_pm, wakeref)
freed_pages += i915_gem_shrink(i915, -1UL, NULL,
I915_SHRINK_BOUND |
@@ -455,7 +446,6 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned
long event, void *ptr
}
mutex_unlock(&i915->ggtt.vm.mutex);
-out:
shrinker_unlock(i915, unlock);
*(unsigned long *)ptr += freed_pages;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 167c4a57c4cd..53c81b5dfd69 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -427,6 +427,9 @@ create_test_object(struct i915_gem_context *ctx,
u64 size;
int err;
+ /* Keep in GEM's good graces */
+ i915_retire_requests(ctx->i915);
+
size = min(vm->total / 2, 1024ull * DW_PER_PAGE * PAGE_SIZE);
size = round_down(size, DW_PER_PAGE * PAGE_SIZE);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index be891492505d..18964aaac643 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -26,7 +26,7 @@ struct intel_gt {
struct i915_ggtt *ggtt;
struct i915_gt_timelines {
- struct mutex mutex; /* protects list, tainted by GPU */
+ struct mutex mutex; /* protects list */
struct list_head active_list;
/* Pack multiple timelines' seqnos into the same page */
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 1a3f04458730..a1038291c5e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -268,9 +268,6 @@ static void timelines_init(struct intel_gt *gt)
spin_lock_init(&timelines->hwsp_lock);
INIT_LIST_HEAD(&timelines->hwsp_free_list);
-
- /* via i915_gem_wait_for_idle() */
- i915_gem_shrinker_taints_mutex(gt->i915, &timelines->mutex);
}
void intel_timelines_init(struct drm_i915_private *i915)
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915: Track i915_active using debugobjects
Provide runtime asserts and tracking of i915_active via debugobjects.
For example, this should allow us to check that the i915_active is only
active when we expect it to be and is never freed too early.
One consequence is that, for simplicity, we no longer allow i915_active
to be on-stack which only affected the selftests.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 66 -
drivers/gpu/drm/i915/selftests/i915_active.c | 78 +++-
2 files changed, 123 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 293e5bcc4b6c..eb91a625c71f 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -4,6 +4,8 @@
* Copyright © 2019 Intel Corporation
*/
+#include
+
#include "gt/intel_engine_pm.h"
#include "i915_drv.h"
@@ -31,6 +33,55 @@ struct active_node {
u64 timeline;
};
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && IS_ENABLED(CONFIG_DEBUG_OBJECTS)
+
+static void *active_debug_hint(void *addr)
+{
+ struct i915_active *ref = addr;
+
+ return (void *)ref->retire ?: (void *)ref;
+}
+
+static struct debug_obj_descr active_debug_desc = {
+ .name = "i915_active",
+ .debug_hint = active_debug_hint,
+};
+
+static void debug_active_init(struct i915_active *ref)
+{
+ debug_object_init(ref, &active_debug_desc);
+}
+
+static void debug_active_activate(struct i915_active *ref)
+{
+ debug_object_activate(ref, &active_debug_desc);
+}
+
+static void debug_active_deactivate(struct i915_active *ref)
+{
+ debug_object_deactivate(ref, &active_debug_desc);
+}
+
+static void debug_active_fini(struct i915_active *ref)
+{
+ debug_object_free(ref, &active_debug_desc);
+}
+
+static void debug_active_assert(struct i915_active *ref)
+{
+ debug_object_assert_init(ref, &active_debug_desc);
+}
+
+#else
+
+static inline void debug_active_init(struct i915_active *ref) { }
+static inline void debug_active_activate(struct i915_active *ref) { }
+static inline void debug_active_deactivate(struct i915_active *ref) { }
+static inline void debug_active_fini(struct i915_active *ref) { }
+static inline void debug_active_assert(struct i915_active *ref) { }
+
+#endif
+
static void
__active_park(struct i915_active *ref)
{
@@ -50,6 +101,8 @@ __active_retire(struct i915_active *ref)
if (--ref->count)
return;
+ debug_active_deactivate(ref);
+
/* return the unused nodes to our slabcache */
__active_park(ref);
@@ -155,6 +208,8 @@ void i915_active_init(struct drm_i915_private *i915,
struct i915_active *ref,
void (*retire)(struct i915_active *ref))
{
+ debug_active_init(ref);
+
ref->i915 = i915;
ref->retire = retire;
ref->tree = RB_ROOT;
@@ -191,13 +246,21 @@ int i915_active_ref(struct i915_active *ref,
bool i915_active_acquire(struct i915_active *ref)
{
+ debug_active_assert(ref);
lockdep_assert_held(BKL(ref));
- return !ref->count++;
+
+ if (ref->count++)
+ return false;
+
+ debug_active_activate(ref);
+ return true;
}
void i915_active_release(struct i915_active *ref)
{
+ debug_active_assert(ref);
lockdep_assert_held(BKL(ref));
+
__active_retire(ref);
}
@@ -260,6 +323,7 @@ int i915_request_await_active(struct i915_request *rq,
struct i915_active *ref)
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
void i915_active_fini(struct i915_active *ref)
{
+ debug_active_fini(ref);
GEM_BUG_ON(i915_active_request_isset(&ref->last));
GEM_BUG_ON(!RB_EMPTY_ROOT(&ref->tree));
GEM_BUG_ON(ref->count);
diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c
b/drivers/gpu/drm/i915/selftests/i915_active.c
index c0b3537a5fa6..98493bcc91f2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_active.c
+++ b/drivers/gpu/drm/i915/selftests/i915_active.c
@@ -16,28 +16,51 @@ struct live_active {
bool retired;
};
-static void __live_active_retire(struct i915_active *base)
+static void __live_free(struct live_active *active)
+{
+ i915_active_fini(&active->base);
+ kfree(active);
+}
+
+static void __live_retire(struct i915_active *base)
{
struct live_active *active = container_of(base, typeof(*active), base);
active->retired = true;
}
-static int __live_active_setup(struct drm_i915_private *i915,
- struct live_active *active)
+static struct live_active *__live_alloc(struct drm_i915_private *i915)
+{
+ struct live_active *active;
+
+ active = kzalloc(sizeof(*active), GFP_KERNEL);
+ if (!active)
+ return NULL;
+
+ i915_active_init(i915, &active->base, __live_retire);
+
+ return active;
+}
+
+static struct live_active *
+__live_active_setup(struct drm_i915_private *i915)
{
struct intel_engine_cs
[Intel-gfx] [PATCH 3/5] drm/i915: Throw away the active object retirement complexity
Remove the accumulated optimisations that we have for i915_vma_retire
and reduce it to the bare essential of tracking the active object
reference. This allows us to only use atomic operations, and so will be
able to avoid the struct_mutex requirement.
The principal loss here is the shrinker MRU bumping, so now if we have
to shrink, we will do so in much more random order and more likely to
try and shrink recently used objects. That is a nuisance, but shrinking
active objects is a second step we try to avoid and will always be a
system-wide performance issue.
The other loss is here is in the automatic pruning of the
reservation_object when idling. This is not as large an issue as upon
reservation_object introduction as now adding new fences into the object
replaces already signaled fences, keeping the array compact. But we do
lose the auto-expiration of stale fences and unused arrays. That may be
a noticeable problem for which we need to re-implement autopruning.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 1 -
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 ---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 -
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 5 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 9
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 1 -
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 34 +---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +--
drivers/gpu/drm/i915/i915_gem_batch_pool.c| 42 ++-
drivers/gpu/drm/i915/i915_vma.c | 54 ---
11 files changed, 47 insertions(+), 118 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 87275f9883ac..43194fbcbc2e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -160,7 +160,6 @@ static void __i915_gem_free_objects(struct drm_i915_private
*i915,
mutex_lock(&i915->drm.struct_mutex);
- GEM_BUG_ON(i915_gem_object_is_active(obj));
list_for_each_entry_safe(vma, vn, &obj->vma.list, obj_link) {
GEM_BUG_ON(i915_vma_is_active(vma));
vma->flags &= ~I915_VMA_PIN_MASK;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index dfebd5706f16..20754c15412a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -158,12 +158,6 @@ i915_gem_object_needs_async_cancel(const struct
drm_i915_gem_object *obj)
return obj->ops->flags & I915_GEM_OBJECT_ASYNC_CANCEL;
}
-static inline bool
-i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
-{
- return READ_ONCE(obj->active_count);
-}
-
static inline bool
i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 18bf4f8d6d80..34b51fad02de 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -154,7 +154,6 @@ struct drm_i915_gem_object {
/** Count of VMA actually bound by this object */
atomic_t bind_count;
- unsigned int active_count;
/** Count of how many global VMA are currently pinned for use by HW */
unsigned int pin_global;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 1bbc690494c7..d99f1a600b96 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -229,8 +229,9 @@ i915_gem_shrink(struct drm_i915_private *i915,
continue;
if (!(shrink & I915_SHRINK_ACTIVE) &&
- (i915_gem_object_is_active(obj) ||
-i915_gem_object_is_framebuffer(obj)))
+ (i915_gem_object_is_framebuffer(obj) ||
+
!reservation_object_test_signaled_rcu(obj->base.resv,
+ true)))
continue;
if (!(shrink & I915_SHRINK_BOUND) &&
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 2812f7fa27fe..24a3c677ccd5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -475,15 +475,6 @@ static int igt_mmap_offset_exhaustion(void *arg)
pr_err("[loop %d] Failed to busy the object\n", loop);
goto err_obj;
}
-
- /* NB we rely on the _active_ reference to access
[Intel-gfx] [PATCH 5/5] drm/i915: Local debug BUG_ON for intel_wakeref
Avoid pulling in i915_gem.h just so that we can use a conditional BUG_ON
for debugging.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_wakeref.c | 9 +
drivers/gpu/drm/i915/intel_wakeref.h | 7 +++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
b/drivers/gpu/drm/i915/intel_wakeref.c
index 3db6fa682823..06bd8b215cc2 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -5,7 +5,7 @@
*/
#include "intel_runtime_pm.h"
-#include "i915_gem.h"
+#include "intel_wakeref.h"
static void rpm_get(struct intel_runtime_pm *rpm, struct intel_wakeref *wf)
{
@@ -17,7 +17,7 @@ static void rpm_put(struct intel_runtime_pm *rpm, struct
intel_wakeref *wf)
intel_wakeref_t wakeref = fetch_and_zero(&wf->wakeref);
intel_runtime_pm_put(rpm, wakeref);
- GEM_BUG_ON(!wakeref);
+ INTEL_WAKEREF_BUG_ON(!wakeref);
}
int __intel_wakeref_get_first(struct intel_runtime_pm *rpm,
@@ -48,6 +48,7 @@ int __intel_wakeref_get_first(struct intel_runtime_pm *rpm,
atomic_inc(&wf->count);
mutex_unlock(&wf->mutex);
+ INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);
return 0;
}
@@ -115,7 +116,7 @@ void intel_wakeref_auto(struct intel_wakeref_auto *wf,
unsigned long timeout)
if (!refcount_inc_not_zero(&wf->count)) {
spin_lock_irqsave(&wf->lock, flags);
if (!refcount_inc_not_zero(&wf->count)) {
- GEM_BUG_ON(wf->wakeref);
+ INTEL_WAKEREF_BUG_ON(wf->wakeref);
wf->wakeref = intel_runtime_pm_get_if_in_use(wf->rpm);
refcount_set(&wf->count, 1);
}
@@ -134,5 +135,5 @@ void intel_wakeref_auto(struct intel_wakeref_auto *wf,
unsigned long timeout)
void intel_wakeref_auto_fini(struct intel_wakeref_auto *wf)
{
intel_wakeref_auto(wf, 0);
- GEM_BUG_ON(wf->wakeref);
+ INTEL_WAKEREF_BUG_ON(wf->wakeref);
}
diff --git a/drivers/gpu/drm/i915/intel_wakeref.h
b/drivers/gpu/drm/i915/intel_wakeref.h
index 9cbb2ebf575b..d45e78639dc4 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.h
+++ b/drivers/gpu/drm/i915/intel_wakeref.h
@@ -13,6 +13,12 @@
#include
#include
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
+#define INTEL_WAKEREF_BUG_ON(expr) BUG_ON(expr)
+#else
+#define INTEL_WAKEREF_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
+#endif
+
struct intel_runtime_pm;
typedef depot_stack_handle_t intel_wakeref_t;
@@ -86,6 +92,7 @@ intel_wakeref_put(struct intel_runtime_pm *rpm,
struct intel_wakeref *wf,
int (*fn)(struct intel_wakeref *wf))
{
+ INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);
if (atomic_dec_and_mutex_lock(&wf->count, &wf->mutex))
return __intel_wakeref_put_last(rpm, wf, fn);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915: Provide an i915_active.acquire callback
If we introduce a callback for i915_active that is only called the first
time we use the i915_active and is symmetrically paired with the
i915_active.retire callback, we can replace the open-coded and
non-atomic implementations -- which will be very fragile (i.e. broken)
upon removing the struct_mutex serialisation.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 8 +-
drivers/gpu/drm/i915/gt/intel_context.c | 65 +++---
drivers/gpu/drm/i915/gt/intel_context.h | 14 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +-
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 16 +-
drivers/gpu/drm/i915/gt/mock_engine.c| 2 +-
drivers/gpu/drm/i915/i915_active.c | 225 ++-
drivers/gpu/drm/i915/i915_active.h | 25 ++-
drivers/gpu/drm/i915/i915_active_types.h | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 22 +-
drivers/gpu/drm/i915/selftests/i915_active.c | 53 -
13 files changed, 258 insertions(+), 192 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 628673d1d7f8..8a9787cf0cd0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -923,8 +923,12 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
if (!cb)
return -ENOMEM;
- i915_active_init(i915, &cb->base, cb_retire);
- i915_active_acquire(&cb->base);
+ i915_active_init(i915, &cb->base, NULL, cb_retire);
+ err = i915_active_acquire(&cb->base);
+ if (err) {
+ kfree(cb);
+ return err;
+ }
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
struct i915_request *rq;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 23120901c55f..938dd032b820 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -95,11 +95,15 @@ void intel_context_unpin(struct intel_context *ce)
intel_context_put(ce);
}
-static int __context_pin_state(struct i915_vma *vma, unsigned long flags)
+static int __context_pin_state(struct i915_vma *vma)
{
+ u64 flags;
int err;
- err = i915_vma_pin(vma, 0, 0, flags | PIN_GLOBAL);
+ flags = i915_ggtt_pin_bias(vma) | PIN_OFFSET_BIAS;
+ flags |= PIN_HIGH | PIN_GLOBAL;
+
+ err = i915_vma_pin(vma, 0, 0, flags);
if (err)
return err;
@@ -119,7 +123,7 @@ static void __context_unpin_state(struct i915_vma *vma)
__i915_vma_unpin(vma);
}
-static void intel_context_retire(struct i915_active *active)
+static void __intel_context_retire(struct i915_active *active)
{
struct intel_context *ce = container_of(active, typeof(*ce), active);
@@ -130,35 +134,11 @@ static void intel_context_retire(struct i915_active
*active)
intel_context_put(ce);
}
-void
-intel_context_init(struct intel_context *ce,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
- GEM_BUG_ON(!engine->cops);
-
- kref_init(&ce->ref);
-
- ce->gem_context = ctx;
- ce->engine = engine;
- ce->ops = engine->cops;
- ce->sseu = engine->sseu;
-
- INIT_LIST_HEAD(&ce->signal_link);
- INIT_LIST_HEAD(&ce->signals);
-
- mutex_init(&ce->pin_mutex);
-
- i915_active_init(ctx->i915, &ce->active, intel_context_retire);
-}
-
-int intel_context_active_acquire(struct intel_context *ce, unsigned long flags)
+static int __intel_context_active(struct i915_active *active)
{
+ struct intel_context *ce = container_of(active, typeof(*ce), active);
int err;
- if (!i915_active_acquire(&ce->active))
- return 0;
-
intel_context_get(ce);
err = intel_ring_pin(ce->ring);
@@ -168,7 +148,7 @@ int intel_context_active_acquire(struct intel_context *ce,
unsigned long flags)
if (!ce->state)
return 0;
- err = __context_pin_state(ce->state, flags);
+ err = __context_pin_state(ce->state);
if (err)
goto err_ring;
@@ -188,15 +168,30 @@ int intel_context_active_acquire(struct intel_context
*ce, unsigned long flags)
intel_ring_unpin(ce->ring);
err_put:
intel_context_put(ce);
- i915_active_cancel(&ce->active);
return err;
}
-void intel_context_active_release(struct intel_context *ce)
+void
+intel_context_init(struct intel_context *ce,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine)
{
- /* Nodes preallocated in intel_context_active() */
- i915_active_acquire_barrier(&ce->active);
- i915_active_release(&ce->
[Intel-gfx] [PATCH 1/2] drm/i915/gt: Rename i915_gt_timelines
Since the anonymous i915_gt became struct intel_gt and encloses
struct i915_gt_timelines, rename i915_gt_timelines to intel_gt_timelines
to match its parentage.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 16
drivers/gpu/drm/i915/i915_gem.c | 2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index be891492505d..722506b7cec0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -25,7 +25,7 @@ struct intel_gt {
struct intel_uncore *uncore;
struct i915_ggtt *ggtt;
- struct i915_gt_timelines {
+ struct intel_gt_timelines {
struct mutex mutex; /* protects list, tainted by GPU */
struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 1a3f04458730..d6accef50f8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -17,7 +17,7 @@
struct intel_timeline_hwsp {
struct intel_gt *gt;
- struct i915_gt_timelines *gt_timelines;
+ struct intel_gt_timelines *gt_timelines;
struct list_head free_link;
struct i915_vma *vma;
u64 free_bitmap;
@@ -53,7 +53,7 @@ static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
static struct i915_vma *
hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline)
{
- struct i915_gt_timelines *gt = &timeline->gt->timelines;
+ struct intel_gt_timelines *gt = &timeline->gt->timelines;
struct intel_timeline_hwsp *hwsp;
BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
@@ -102,7 +102,7 @@ hwsp_alloc(struct intel_timeline *timeline, unsigned int
*cacheline)
static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline)
{
- struct i915_gt_timelines *gt = hwsp->gt_timelines;
+ struct intel_gt_timelines *gt = hwsp->gt_timelines;
unsigned long flags;
spin_lock_irqsave(>->hwsp_lock, flags);
@@ -261,7 +261,7 @@ int intel_timeline_init(struct intel_timeline *timeline,
static void timelines_init(struct intel_gt *gt)
{
- struct i915_gt_timelines *timelines = >->timelines;
+ struct intel_gt_timelines *timelines = >->timelines;
mutex_init(&timelines->mutex);
INIT_LIST_HEAD(&timelines->active_list);
@@ -280,7 +280,7 @@ void intel_timelines_init(struct drm_i915_private *i915)
static void timeline_add_to_active(struct intel_timeline *tl)
{
- struct i915_gt_timelines *gt = &tl->gt->timelines;
+ struct intel_gt_timelines *gt = &tl->gt->timelines;
mutex_lock(>->mutex);
list_add(&tl->link, >->active_list);
@@ -289,7 +289,7 @@ static void timeline_add_to_active(struct intel_timeline
*tl)
static void timeline_remove_from_active(struct intel_timeline *tl)
{
- struct i915_gt_timelines *gt = &tl->gt->timelines;
+ struct intel_gt_timelines *gt = &tl->gt->timelines;
mutex_lock(>->mutex);
list_del(&tl->link);
@@ -298,7 +298,7 @@ static void timeline_remove_from_active(struct
intel_timeline *tl)
static void timelines_park(struct intel_gt *gt)
{
- struct i915_gt_timelines *timelines = >->timelines;
+ struct intel_gt_timelines *timelines = >->timelines;
struct intel_timeline *timeline;
mutex_lock(&timelines->mutex);
@@ -572,7 +572,7 @@ void __intel_timeline_free(struct kref *kref)
static void timelines_fini(struct intel_gt *gt)
{
- struct i915_gt_timelines *timelines = >->timelines;
+ struct intel_gt_timelines *timelines = >->timelines;
GEM_BUG_ON(!list_empty(&timelines->active_list));
GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8dff3b8f12c3..e59be5c05e1b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -908,7 +908,7 @@ static long
wait_for_timelines(struct drm_i915_private *i915,
unsigned int flags, long timeout)
{
- struct i915_gt_timelines *gt = &i915->gt.timelines;
+ struct intel_gt_timelines *gt = &i915->gt.timelines;
struct intel_timeline *tl;
mutex_lock(>->mutex);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/gt: Fixup kerneldoc parameters
drivers/gpu/drm/i915/gt/intel_mocs.c:513: warning: Function parameter or
member 'gt' not described in 'intel_mocs_init_l3cc_table'
drivers/gpu/drm/i915/gt/intel_mocs.c:513: warning: Excess function parameter
'dev_priv' description in 'intel_mocs_init_l3cc_table'
intel_vgt_balloon/deballoon, i915_ggtt_probe_hw intel_wopcm_init_hw need
similar treatment
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_vgpu.c | 4 ++--
drivers/gpu/drm/i915/intel_wopcm.c | 1 +
4 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index d08b8f47269b..ae6cbf0d517c 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -497,7 +497,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
/**
* intel_mocs_init_l3cc_table() - program the mocs control table
- * @dev_priv: i915 device private
+ * @gt: the intel_gt container
*
* This function simply programs the mocs registers for the given table
* starting at the given address. This register set is programmed in pairs.
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4dbfbccfa618..90f367397656 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2934,7 +2934,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
/**
* i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
- * @dev_priv: i915 device
+ * @i915: i915 device
*/
void i915_ggtt_cleanup_hw(struct drm_i915_private *i915)
{
@@ -3530,7 +3530,7 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct
intel_gt *gt)
/**
* i915_ggtt_probe_hw - Probe GGTT hardware location
- * @dev_priv: i915 device
+ * @i915: i915 device
*/
int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 9916bc6159b6..dbd1fa3c7d90 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -131,7 +131,7 @@ static void vgt_deballoon_space(struct i915_ggtt *ggtt,
/**
* intel_vgt_deballoon - deballoon reserved graphics address trunks
- * @dev_priv: i915 device private data
+ * @ggtt: the global GGTT from which we reserved earlier
*
* This function is called to deallocate the ballooned-out graphic memory, when
* driver is unloaded or when ballooning fails.
@@ -172,7 +172,7 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt,
/**
* intel_vgt_balloon - balloon out reserved graphics address trunks
- * @dev_priv: i915 device private data
+ * @ggtt: the global GGTT from which to reserve
*
* This function is called at the initialization stage, to balloon out the
* graphic address space allocated to other vGPUs, by marking these spaces as
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 931987e37241..8c850785e4b4 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -244,6 +244,7 @@ write_and_verify(struct intel_gt *gt,
/**
* intel_wopcm_init_hw() - Setup GuC WOPCM registers.
* @wopcm: pointer to intel_wopcm.
+ * @gt: pointer to the containing GT
*
* Setup the GuC WOPCM size and offset registers with the calculated values. It
* will verify the register values to make sure the registers are locked with
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Keep context alive until after we kick (rev2)
== Series Details == Series: drm/i915/execlists: Keep context alive until after we kick (rev2) URL : https://patchwork.freedesktop.org/series/62503/ State : success == Summary == CI Bug Log - changes from CI_DRM_6320_full -> Patchwork_13383_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13383_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-iclb1/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#110913 ]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-apl2/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-apl4/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#110913 ]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-kbl1/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-kbl3/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html * igt@gem_workarounds@suspend-resume-context: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-skl5/igt@gem_workarou...@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-skl9/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#103313]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-kbl2/igt@i915_pm_...@system-suspend-execbuf.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-kbl1/igt@i915_pm_...@system-suspend-execbuf.html * igt@i915_pm_rpm@universal-planes: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#108840]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-iclb6/igt@i915_pm_...@universal-planes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-iclb2/igt@i915_pm_...@universal-planes.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#110741]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108] / [fdo#107773]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-skl2/igt@kms_fbcon_...@psr-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-skl9/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#109507]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-skl9/igt@kms_f...@flip-vs-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-skl7/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +9 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-pwrite.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167] / [fdo#110378]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-rte.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-rte.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite: - shard-hsw: [PASS][23] -> [SKIP][24] ([fdo#109271]) +17 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6320/shard-hsw7/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13383/shard-hsw1/igt@kms_frontbuf
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Remove waiting & retiring from shrinker paths
== Series Details == Series: series starting with [1/5] drm/i915: Remove waiting & retiring from shrinker paths URL : https://patchwork.freedesktop.org/series/62526/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2576c15160f4 drm/i915: Remove waiting & retiring from shrinker paths ad6dedb32df1 drm/i915: Track i915_active using debugobjects c0edae8f7dcb drm/i915: Throw away the active object retirement complexity 7f6dd3b151fc drm/i915: Provide an i915_active.acquire callback -:735: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #735: FILE: drivers/gpu/drm/i915/i915_active_types.h:36: + struct mutex mutex; total: 0 errors, 0 warnings, 1 checks, 827 lines checked d08a6f278313 drm/i915: Local debug BUG_ON for intel_wakeref -:66: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() #66: FILE: drivers/gpu/drm/i915/intel_wakeref.h:17: +#define INTEL_WAKEREF_BUG_ON(expr) BUG_ON(expr) total: 0 errors, 1 warnings, 0 checks, 56 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Remove waiting & retiring from shrinker paths
== Series Details == Series: series starting with [1/5] drm/i915: Remove waiting & retiring from shrinker paths URL : https://patchwork.freedesktop.org/series/62526/ State : success == Summary == CI Bug Log - changes from CI_DRM_6323 -> Patchwork_13384 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/ Known issues Here are the changes found in Patchwork_13384 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#103167]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 Participating hosts (50 -> 45) -- Additional (3): fi-icl-guc fi-icl-dsi fi-apl-guc Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6323 -> Patchwork_13384 CI_DRM_6323: b440a8f975a5d9ea7807517e4228077bc795e91e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13384: d08a6f278313e17c838df9e60eb9ad758fb9fa60 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d08a6f278313 drm/i915: Local debug BUG_ON for intel_wakeref 7f6dd3b151fc drm/i915: Provide an i915_active.acquire callback c0edae8f7dcb drm/i915: Throw away the active object retirement complexity ad6dedb32df1 drm/i915: Track i915_active using debugobjects 2576c15160f4 drm/i915: Remove waiting & retiring from shrinker paths == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Prevent dereference of engine before NULL check in error capture
drivers/gpu/drm/i915//i915_gpu_error.c:1418 gem_record_rings() warn: variable
dereferenced before check 'engine' (see line 1413)
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 59f5b0265ee3..5489cd879315 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1410,7 +1410,6 @@ static void gem_record_rings(struct i915_gpu_state *error)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct intel_engine_cs *engine = i915->engine[i];
struct drm_i915_error_engine *ee = &error->engine[i];
- struct i915_ggtt *ggtt = engine->gt->ggtt;
struct i915_request *request;
ee->engine_id = -1;
@@ -1428,7 +1427,7 @@ static void gem_record_rings(struct i915_gpu_state *error)
struct i915_gem_context *ctx = request->gem_context;
struct intel_ring *ring;
- ee->vm = ctx->vm ?: &ggtt->vm;
+ ee->vm = ctx->vm ?: &engine->gt->ggtt->vm;
record_context(&ee->context, ctx);
--
2.20.1
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[Intel-gfx] XDC 2019: Less than three weeks to go to submit your talks, workshops or demos!
Hello! Less than three weeks to go to submit your talks, workshops or demos for this year's X.Org Developer Conference, which will be taking place in Montréal, Canada on October 2-4, 2019! The 2019 X.Org Developers Conference is the annual technical meeting for X Window System and Free Desktop developers. Attendees will gather to discuss outstanding technical issues related to the Open Source Graphics stack (Linux kernel, Mesa, DRM, Wayland, X11, etc.) and its software ecosystem. While any serious proposal will be gratefully considered, topics of interest to X.Org and freedesktop.org developers are encouraged. The program focus is on new development, ongoing challenges and anything else that will spark discussions among attendees in the hallway track. We are open to talks across all layers of the graphics stack, from the kernel to desktop environments / graphical applications and about how to make things better for the developers who build them. Head to the XDC website to learn more: https://xdc2019.x.org/ The deadline for submissions Sunday, 7 July 2019. Best, Mark ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
Because of this, both the bspec documentation and our i915 code has used
the term "port" when talking about either DDI's or PHY's; it was always
easy to tell what terms like "Port A" were referring to from the
context.
Unfortunately this is starting to break down now that EHL allows PHY-A
to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
PHY-A considered "Port A" or "Port D?" The answer depends on which
register we're working with, and even the bspec doesn't do a great job
of clarifying this.
Let's try to be more explicit about whether we're talking about the DDI
or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
new 'enum phy' namespace to refer to the PHY in use.
A few general notes:
- ICL_PORT_COMP_* and ICL_PORT_CL_* belong to the actual combo PHY so
they should always be programmed according to the PHY in use,
regardless of which DDI is driving it.
- The pipe part of the hardware expects "port" to refer to the
DDI, so registers like TRANS_CLK_SEL and TRANS_DDI_FUNC_CTL should
set bits according to the desired DDI (e.g., DDI-D) rather than the
PHY (PHY-A).
- Non-pipe registers refer to the PHY. Notably, DPCLKA_CFGCR0_ICL
needs to set bits according to the PHY.
Most of the changes here are on the combo PHY side. I didn't touch most
of the TC port code yet, so it still refers to everything as ports.
That's okay for now since there's no TC on EHL, but we'll probably want
to separate out the DDI vs PHY terminology for TC in the future as well
to avoid confusion.
v2:
- Convert a few more 'port' uses to 'phy.' (Sparse)
Suggested-by: Ville Syrjala
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/icl_dsi.c| 24 ++-
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
.../gpu/drm/i915/display/intel_combo_phy.c| 143 +-
.../gpu/drm/i915/display/intel_combo_phy.h| 3 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 106 +++--
drivers/gpu/drm/i915/display/intel_display.c | 36 +++--
drivers/gpu/drm/i915/display/intel_display.h | 16 ++
drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 +-
drivers/gpu/drm/i915/i915_reg.h | 18 +--
drivers/gpu/drm/i915/intel_drv.h | 4 +-
11 files changed, 215 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index b8673debf932..b338746003ea 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -365,10 +365,13 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder
*encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
+ enum phy phy;
- for_each_dsi_port(port, intel_dsi->ports)
- intel_combo_phy_power_up_lanes(dev_priv, port, true,
+ for_each_dsi_port(port, intel_dsi->ports) {
+ phy = intel_port_to_phy(dev_priv, port);
+ intel_combo_phy_power_up_lanes(dev_priv, phy, true,
intel_dsi->lane_count, false);
+ }
}
static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
@@ -560,11 +563,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder
*encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
enum port port;
+ enum phy phy;
mutex_lock(&dev_priv->dpll_lock);
tmp = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_dsi_port(port, intel_dsi->ports) {
- tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -577,11 +582,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder
*encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
enum port port;
+ enum phy phy;
mutex_lock(&dev_priv->dpll_lock);
tmp = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_dsi_port(port, intel_dsi->ports) {
- tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -595,19 +602,22 @@ static void gen11_dsi_map_pll(struct intel_encoder
*encoder,
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum port port;
+ enum phy phy;
u32 val;
mutex_lock(&dev_priv->dpll_lock);
val =
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Rename i915_gt_timelines
== Series Details == Series: series starting with [1/2] drm/i915/gt: Rename i915_gt_timelines URL : https://patchwork.freedesktop.org/series/62527/ State : success == Summary == CI Bug Log - changes from CI_DRM_6323 -> Patchwork_13385 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13385/ Known issues Here are the changes found in Patchwork_13385 that come from known issues: ### IGT changes ### Issues hit * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][1] -> [DMESG-WARN][2] ([fdo#102614]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13385/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#103167]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13385/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_flink_basic@flink-lifetime: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13385/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 Participating hosts (50 -> 43) -- Additional (2): fi-icl-guc fi-icl-dsi Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus fi-cml-u Build changes - * Linux: CI_DRM_6323 -> Patchwork_13385 CI_DRM_6323: b440a8f975a5d9ea7807517e4228077bc795e91e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13385: 933c4286d361fa0ca9843a7b5642138f4415b0ed @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 933c4286d361 drm/i915/gt: Fixup kerneldoc parameters 2cfeec383213 drm/i915/gt: Rename i915_gt_timelines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13385/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Prevent dereference of engine before NULL check in error capture
== Series Details == Series: drm/i915: Prevent dereference of engine before NULL check in error capture URL : https://patchwork.freedesktop.org/series/62528/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7cc507b17f06 drm/i915: Prevent dereference of engine before NULL check in error capture -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: drivers/gpu/drm/i915//i915_gpu_error.c:1418 gem_record_rings() warn: variable dereferenced before check 'engine' (see line 1413) total: 0 errors, 1 warnings, 0 checks, 15 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Prevent dereference of engine before NULL check in error capture
On 21/06/2019 14:52, Chris Wilson wrote:
drivers/gpu/drm/i915//i915_gpu_error.c:1418 gem_record_rings() warn: variable
dereferenced before check 'engine' (see line 1413)
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 59f5b0265ee3..5489cd879315 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1410,7 +1410,6 @@ static void gem_record_rings(struct i915_gpu_state *error)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct intel_engine_cs *engine = i915->engine[i];
struct drm_i915_error_engine *ee = &error->engine[i];
- struct i915_ggtt *ggtt = engine->gt->ggtt;
struct i915_request *request;
ee->engine_id = -1;
@@ -1428,7 +1427,7 @@ static void gem_record_rings(struct i915_gpu_state *error)
struct i915_gem_context *ctx = request->gem_context;
struct intel_ring *ring;
- ee->vm = ctx->vm ?: &ggtt->vm;
+ ee->vm = ctx->vm ?: &engine->gt->ggtt->vm;
record_context(&ee->context, ctx);
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev2)
== Series Details ==
Series: EHL port programming (rev2)
URL : https://patchwork.freedesktop.org/series/62492/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5685d98b6706 drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes
per BSPEC")
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 9659c1af451a ("drm/i915/icl:
combo port vswing programming changes per BSPEC")'
#10:
References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes
per BSPEC")
total: 1 errors, 1 warnings, 0 checks, 36 lines checked
a396b4e39927 drm/i915/ehl: Add third combo PHY offset
83b87151a761 drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
be24fefad142 drm/i915/gen11: Start distinguishing 'phy' from 'port'
-:167: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible
side-effects?
#167: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:9:
+#define for_each_combo_phy(__dev_priv, __phy) \
+ for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
+ for_each_if(intel_phy_is_combo(__dev_priv, __phy))
-:174: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible
side-effects?
#174: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:13:
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+ for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+ for_each_if(intel_phy_is_combo(__dev_priv, __phy))
-:1048: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible
side-effects?
#1048: FILE: drivers/gpu/drm/i915/i915_reg.h:9684:
+#define DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << ((phy) == PHY_F ?
23 : \
+ (phy) + 10))
-:1057: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible
side-effects?
#1057: FILE: drivers/gpu/drm/i915/i915_reg.h:9689:
+#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) == PHY_F ? 21 : \
+ (phy) * 2)
total: 0 errors, 0 warnings, 4 checks, 926 lines checked
4b99477f1916 drm/i915/ehl: Enable DDI-D
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prevent dereference of engine before NULL check in error capture
== Series Details == Series: drm/i915: Prevent dereference of engine before NULL check in error capture URL : https://patchwork.freedesktop.org/series/62528/ State : success == Summary == CI Bug Log - changes from CI_DRM_6323 -> Patchwork_13386 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13386/ Known issues Here are the changes found in Patchwork_13386 that come from known issues: ### IGT changes ### Issues hit * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][1] -> [FAIL][2] ([fdo#103167]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13386/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_flink_basic@flink-lifetime: - fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13386/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 Participating hosts (50 -> 45) -- Additional (3): fi-icl-guc fi-icl-dsi fi-apl-guc Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6323 -> Patchwork_13386 CI_DRM_6323: b440a8f975a5d9ea7807517e4228077bc795e91e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13386: 7cc507b17f0643067ef723506deee0cb57b0fcaf @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7cc507b17f06 drm/i915: Prevent dereference of engine before NULL check in error capture == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13386/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for EHL port programming (rev2)
== Series Details == Series: EHL port programming (rev2) URL : https://patchwork.freedesktop.org/series/62492/ State : success == Summary == CI Bug Log - changes from CI_DRM_6323 -> Patchwork_13387 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/ Known issues Here are the changes found in Patchwork_13387 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-rte: - fi-skl-6600u: [PASS][1] -> [FAIL][2] ([fdo#108800]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-skl-6600u/igt@i915_pm_...@basic-rte.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/fi-skl-6600u/igt@i915_pm_...@basic-rte.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#103167]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800 Participating hosts (50 -> 43) -- Additional (3): fi-icl-guc fi-icl-dsi fi-apl-guc Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ivb-3770 fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6323 -> Patchwork_13387 CI_DRM_6323: b440a8f975a5d9ea7807517e4228077bc795e91e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13387: 4b99477f19165b4d454bf8fc2aeb112447dceb95 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4b99477f1916 drm/i915/ehl: Enable DDI-D be24fefad142 drm/i915/gen11: Start distinguishing 'phy' from 'port' 83b87151a761 drm/i915/ehl: Don't program PHY_MISC on EHL PHY C a396b4e39927 drm/i915/ehl: Add third combo PHY offset 5685d98b6706 drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Rename i915_gt_timelines
On 21/06/2019 14:16, Chris Wilson wrote:
Since the anonymous i915_gt became struct intel_gt and encloses
struct i915_gt_timelines, rename i915_gt_timelines to intel_gt_timelines
to match its parentage.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 16
drivers/gpu/drm/i915/i915_gem.c | 2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index be891492505d..722506b7cec0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -25,7 +25,7 @@ struct intel_gt {
struct intel_uncore *uncore;
struct i915_ggtt *ggtt;
- struct i915_gt_timelines {
+ struct intel_gt_timelines {
struct mutex mutex; /* protects list, tainted by GPU */
struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 1a3f04458730..d6accef50f8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -17,7 +17,7 @@
struct intel_timeline_hwsp {
struct intel_gt *gt;
- struct i915_gt_timelines *gt_timelines;
+ struct intel_gt_timelines *gt_timelines;
struct list_head free_link;
struct i915_vma *vma;
u64 free_bitmap;
@@ -53,7 +53,7 @@ static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
static struct i915_vma *
hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline)
{
- struct i915_gt_timelines *gt = &timeline->gt->timelines;
+ struct intel_gt_timelines *gt = &timeline->gt->timelines;
struct intel_timeline_hwsp *hwsp;
BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
@@ -102,7 +102,7 @@ hwsp_alloc(struct intel_timeline *timeline, unsigned int
*cacheline)
static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline)
{
- struct i915_gt_timelines *gt = hwsp->gt_timelines;
+ struct intel_gt_timelines *gt = hwsp->gt_timelines;
unsigned long flags;
spin_lock_irqsave(>->hwsp_lock, flags);
@@ -261,7 +261,7 @@ int intel_timeline_init(struct intel_timeline *timeline,
static void timelines_init(struct intel_gt *gt)
{
- struct i915_gt_timelines *timelines = >->timelines;
+ struct intel_gt_timelines *timelines = >->timelines;
mutex_init(&timelines->mutex);
INIT_LIST_HEAD(&timelines->active_list);
@@ -280,7 +280,7 @@ void intel_timelines_init(struct drm_i915_private *i915)
static void timeline_add_to_active(struct intel_timeline *tl)
{
- struct i915_gt_timelines *gt = &tl->gt->timelines;
+ struct intel_gt_timelines *gt = &tl->gt->timelines;
mutex_lock(>->mutex);
list_add(&tl->link, >->active_list);
@@ -289,7 +289,7 @@ static void timeline_add_to_active(struct intel_timeline
*tl)
static void timeline_remove_from_active(struct intel_timeline *tl)
{
- struct i915_gt_timelines *gt = &tl->gt->timelines;
+ struct intel_gt_timelines *gt = &tl->gt->timelines;
mutex_lock(>->mutex);
list_del(&tl->link);
@@ -298,7 +298,7 @@ static void timeline_remove_from_active(struct
intel_timeline *tl)
static void timelines_park(struct intel_gt *gt)
{
- struct i915_gt_timelines *timelines = >->timelines;
+ struct intel_gt_timelines *timelines = >->timelines;
struct intel_timeline *timeline;
mutex_lock(&timelines->mutex);
@@ -572,7 +572,7 @@ void __intel_timeline_free(struct kref *kref)
static void timelines_fini(struct intel_gt *gt)
{
- struct i915_gt_timelines *timelines = >->timelines;
+ struct intel_gt_timelines *timelines = >->timelines;
GEM_BUG_ON(!list_empty(&timelines->active_list));
GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8dff3b8f12c3..e59be5c05e1b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -908,7 +908,7 @@ static long
wait_for_timelines(struct drm_i915_private *i915,
unsigned int flags, long timeout)
{
- struct i915_gt_timelines *gt = &i915->gt.timelines;
+ struct intel_gt_timelines *gt = &i915->gt.timelines;
struct intel_timeline *tl;
mutex_lock(>->mutex);
Reviewed-by: Tvrtko Ursulin
Next up renaming the confusing gt locals.
Regards,
Tvrtko
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[Intel-gfx] [PATCH] drm/i915/execlists: Disable preemption under GVT
Preempt-to-busy uses a GPU semaphore to enforce an idle-barrier across
preemption, but mediated gvt does not fully support semaphores.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b3e0e25c5d80..f8ac9a856bf4 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2676,10 +2676,11 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->unpark = NULL;
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
- if (!intel_vgpu_active(engine->i915))
+ if (!intel_vgpu_active(engine->i915)) {
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
- engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+ if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
+ engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+ }
}
static void execlists_destroy(struct intel_engine_cs *engine)
--
2.20.1
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Fixup kerneldoc parameters
On 21/06/2019 14:16, Chris Wilson wrote:
drivers/gpu/drm/i915/gt/intel_mocs.c:513: warning: Function parameter or
member 'gt' not described in 'intel_mocs_init_l3cc_table'
drivers/gpu/drm/i915/gt/intel_mocs.c:513: warning: Excess function parameter
'dev_priv' description in 'intel_mocs_init_l3cc_table'
intel_vgt_balloon/deballoon, i915_ggtt_probe_hw intel_wopcm_init_hw need
similar treatment
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_vgpu.c | 4 ++--
drivers/gpu/drm/i915/intel_wopcm.c | 1 +
4 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index d08b8f47269b..ae6cbf0d517c 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -497,7 +497,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
/**
* intel_mocs_init_l3cc_table() - program the mocs control table
- * @dev_priv: i915 device private
+ * @gt: the intel_gt container
*
* This function simply programs the mocs registers for the given table
* starting at the given address. This register set is programmed in pairs.
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4dbfbccfa618..90f367397656 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2934,7 +2934,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
/**
* i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
- * @dev_priv: i915 device
+ * @i915: i915 device
*/
void i915_ggtt_cleanup_hw(struct drm_i915_private *i915)
{
@@ -3530,7 +3530,7 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct
intel_gt *gt)
/**
* i915_ggtt_probe_hw - Probe GGTT hardware location
- * @dev_priv: i915 device
+ * @i915: i915 device
*/
int i915_ggtt_probe_hw(struct drm_i915_private *i915)
{
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 9916bc6159b6..dbd1fa3c7d90 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -131,7 +131,7 @@ static void vgt_deballoon_space(struct i915_ggtt *ggtt,
/**
* intel_vgt_deballoon - deballoon reserved graphics address trunks
- * @dev_priv: i915 device private data
+ * @ggtt: the global GGTT from which we reserved earlier
*
* This function is called to deallocate the ballooned-out graphic memory,
when
* driver is unloaded or when ballooning fails.
@@ -172,7 +172,7 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt,
/**
* intel_vgt_balloon - balloon out reserved graphics address trunks
- * @dev_priv: i915 device private data
+ * @ggtt: the global GGTT from which to reserve
*
* This function is called at the initialization stage, to balloon out the
* graphic address space allocated to other vGPUs, by marking these spaces as
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 931987e37241..8c850785e4b4 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -244,6 +244,7 @@ write_and_verify(struct intel_gt *gt,
/**
* intel_wopcm_init_hw() - Setup GuC WOPCM registers.
* @wopcm: pointer to intel_wopcm.
+ * @gt: pointer to the containing GT
*
* Setup the GuC WOPCM size and offset registers with the calculated values.
It
* will verify the register values to make sure the registers are locked with
Order is reversed in last hunk.
Thanks for fixing this up!
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Remove waiting & retiring from shrinker paths
On 21/06/2019 14:05, Chris Wilson wrote: i915_gem_wait_for_idle() and i915_retire_requests() introduce a dependency on the timeline->mutex. This is problematic as we want to later perform allocations underneath i915_active.mutex, forming a link between the shrinker, the timeline and active mutexes. Nip this cycle in the bud by removing the acquisition of the timeline mutex (i.e. retiring) from inside the shrinker. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Rename i915_gt_timelines
Quoting Tvrtko Ursulin (2019-06-21 16:00:15)
>
> On 21/06/2019 14:16, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 8dff3b8f12c3..e59be5c05e1b 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -908,7 +908,7 @@ static long
> > wait_for_timelines(struct drm_i915_private *i915,
> > unsigned int flags, long timeout)
> > {
> > - struct i915_gt_timelines *gt = &i915->gt.timelines;
> > + struct intel_gt_timelines *gt = &i915->gt.timelines;
> > struct intel_timeline *tl;
> >
> > mutex_lock(>->mutex);
> >
>
> Reviewed-by: Tvrtko Ursulin
>
> Next up renaming the confusing gt locals.
Did I manage to sneak some by? *plays innocent*
-Chris
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[Intel-gfx] [PATCH] drm/i915/ehl: Add one additional PCH ID to MCC
There's one additional ID that we should treat as Mule Creek Canyon.
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8f84ed26e972..2e6389168854 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -219,6 +219,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
WARN_ON(!IS_ICELAKE(dev_priv));
return PCH_ICP;
case INTEL_PCH_MCC_DEVICE_ID_TYPE:
+ case INTEL_PCH_MCC2_DEVICE_ID_TYPE:
DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
WARN_ON(!IS_ELKHARTLAKE(dev_priv));
return PCH_MCC;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2734f62ab19a..a0469bbe6c8e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2353,6 +2353,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
+#define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
--
2.17.2
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: Track i915_active using debugobjects
On 21/06/2019 14:05, Chris Wilson wrote:
Provide runtime asserts and tracking of i915_active via debugobjects.
For example, this should allow us to check that the i915_active is only
active when we expect it to be and is never freed too early.
One consequence is that, for simplicity, we no longer allow i915_active
to be on-stack which only affected the selftests.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 66 -
drivers/gpu/drm/i915/selftests/i915_active.c | 78 +++-
2 files changed, 123 insertions(+), 21 deletions(-)
[snip]
+
+static struct live_active *
+__live_active_setup(struct drm_i915_private *i915)
{
struct intel_engine_cs *engine;
struct i915_sw_fence *submit;
+ struct live_active *active;
enum intel_engine_id id;
unsigned int count = 0;
int err = 0;
- submit = heap_fence_create(GFP_KERNEL);
- if (!submit)
- return -ENOMEM;
+ active = __live_alloc(i915);
+ if (!active)
+ return ERR_PTR(-ENOMEM);
- i915_active_init(i915, &active->base, __live_active_retire);
- active->retired = false;
+ submit = heap_fence_create(GFP_KERNEL);
+ if (!submit) {
+ kfree(active);
+ return ERR_PTR(-ENOMEM);
+ }
if (!i915_active_acquire(&active->base)) {
pr_err("First i915_active_acquire should report being idle\n");
@@ -84,64 +107,79 @@ static int __live_active_setup(struct drm_i915_private
*i915,
i915_sw_fence_commit(submit);
heap_fence_put(submit);
- return err;
+ /* XXX leaks live_active on error */
+ return err ? ERR_PTR(err) : active
Too much of a pain?
Not a blocker,
Reviewed-by: Matthew Auld
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: Track i915_active using debugobjects
Quoting Matthew Auld (2019-06-21 16:25:05)
> On 21/06/2019 14:05, Chris Wilson wrote:
> > Provide runtime asserts and tracking of i915_active via debugobjects.
> > For example, this should allow us to check that the i915_active is only
> > active when we expect it to be and is never freed too early.
> >
> > One consequence is that, for simplicity, we no longer allow i915_active
> > to be on-stack which only affected the selftests.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/i915_active.c | 66 -
> > drivers/gpu/drm/i915/selftests/i915_active.c | 78 +++-
> > 2 files changed, 123 insertions(+), 21 deletions(-)
> >
>
> [snip]
>
> > +
> > +static struct live_active *
> > +__live_active_setup(struct drm_i915_private *i915)
> > {
> > struct intel_engine_cs *engine;
> > struct i915_sw_fence *submit;
> > + struct live_active *active;
> > enum intel_engine_id id;
> > unsigned int count = 0;
> > int err = 0;
> >
> > - submit = heap_fence_create(GFP_KERNEL);
> > - if (!submit)
> > - return -ENOMEM;
> > + active = __live_alloc(i915);
> > + if (!active)
> > + return ERR_PTR(-ENOMEM);
> >
> > - i915_active_init(i915, &active->base, __live_active_retire);
> > - active->retired = false;
> > + submit = heap_fence_create(GFP_KERNEL);
> > + if (!submit) {
> > + kfree(active);
> > + return ERR_PTR(-ENOMEM);
> > + }
> >
> > if (!i915_active_acquire(&active->base)) {
> > pr_err("First i915_active_acquire should report being
> > idle\n");
> > @@ -84,64 +107,79 @@ static int __live_active_setup(struct drm_i915_private
> > *i915,
> > i915_sw_fence_commit(submit);
> > heap_fence_put(submit);
> >
> > - return err;
> > + /* XXX leaks live_active on error */
> > + return err ? ERR_PTR(err) : active
>
> Too much of a pain?
In the next patch (with an active callback), it grew a ref count and
gets cleaned up automatically. Could have pulled it into this patch, but
too much effort for a hopefully never seen result.
-Chris
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: Local debug BUG_ON for intel_wakeref
On 21/06/2019 14:05, Chris Wilson wrote: Avoid pulling in i915_gem.h just so that we can use a conditional BUG_ON for debugging. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/icl: Add new supported CD clocks
On Thu, Jun 20, 2019 at 05:45:54PM -0700, José Roberto de Souza wrote:
> Now 180, 172.8 and 192 MHz are supported.
>
> 180 and 172.8 MHz CD clocks will only be used when audio is not
> enabled as state by BSpec and implemented in
> intel_crtc_compute_min_cdclk(), CD clock must be at least twice of
> Azalia BCLK and BCLK by default is 96 MHz, it could be set to 48 MHz
> but we are not reading it.
>
> BSpec: 20598
> BSpec: 15729
> Cc: Clint Taylor
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
I think Ville wanted a 'static' on the range arrays. But aside from
that, the changes here match the bspec, so
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++---
> 1 file changed, 21 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8993ab283562..8eef177b2bbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1756,9 +1756,10 @@ static void cnl_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
>
> static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> {
> - int ranges_24[] = { 312000, 552000, 648000 };
> - int ranges_19_38[] = { 307200, 556800, 652800 };
> - int *ranges;
> + const int ranges_24[] = { 18, 192000, 312000, 552000, 648000 };
> + const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 };
> + const int *ranges;
> + int len, i;
>
> switch (ref) {
> default:
> @@ -1766,19 +1767,22 @@ static int icl_calc_cdclk(int min_cdclk, unsigned int
> ref)
> /* fall through */
> case 24000:
> ranges = ranges_24;
> + len = ARRAY_SIZE(ranges_24);
> break;
> case 19200:
> case 38400:
> ranges = ranges_19_38;
> + len = ARRAY_SIZE(ranges_19_38);
> break;
> }
>
> - if (min_cdclk > ranges[1])
> - return ranges[2];
> - else if (min_cdclk > ranges[0])
> - return ranges[1];
> - else
> - return ranges[0];
> + for (i = 0; i < len; i++) {
> + if (min_cdclk <= ranges[i])
> + return ranges[i];
> + }
> +
> + WARN_ON(min_cdclk > ranges[len - 1]);
> + return ranges[len - 1];
> }
>
> static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int
> cdclk)
> @@ -1792,16 +1796,24 @@ static int icl_calc_cdclk_pll_vco(struct
> drm_i915_private *dev_priv, int cdclk)
> default:
> MISSING_CASE(cdclk);
> /* fall through */
> + case 172800:
> case 307200:
> case 556800:
> case 652800:
> WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> dev_priv->cdclk.hw.ref != 38400);
> break;
> + case 18:
> case 312000:
> case 552000:
> case 648000:
> WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> + break;
> + case 192000:
> + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> + dev_priv->cdclk.hw.ref != 38400 &&
> + dev_priv->cdclk.hw.ref != 24000);
> + break;
> }
>
> ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> --
> 2.22.0
>
> ___
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Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/ehl: Remove unsupported cd clocks
On Thu, Jun 20, 2019 at 05:45:55PM -0700, José Roberto de Souza wrote:
> EHL do not support 648 and 652.8 MHz.
>
> v2:
> - Limiting maximum CD clock by max_cdclk_freq instead of remove it
> from icl_calc_cdclk()(Ville and Jani)
>
> BSpec: 20598
> Cc: Clint Taylor
> Cc: Matt Roper
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Matches bspec.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8eef177b2bbd..daab4e9a6359 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2606,7 +2606,12 @@ static int intel_compute_max_dotclk(struct
> drm_i915_private *dev_priv)
> */
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> {
> - if (INTEL_GEN(dev_priv) >= 11) {
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + if (dev_priv->cdclk.hw.ref == 24000)
> + dev_priv->max_cdclk_freq = 552000;
> + else
> + dev_priv->max_cdclk_freq = 556800;
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> if (dev_priv->cdclk.hw.ref == 24000)
> dev_priv->max_cdclk_freq = 648000;
> else
> --
> 2.22.0
>
--
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Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/ehl: Add voltage level requirement table
On Thu, Jun 20, 2019 at 05:45:56PM -0700, José Roberto de Souza wrote:
> EHL has it own voltage level requirement depending on cd clock.
>
> BSpec: 21809
> Cc: Clint Taylor
> Cc: Matt Roper
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
Matches bspec.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 35 ++
> 1 file changed, 23 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index daab4e9a6359..7d26841d1700 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1866,14 +1866,23 @@ static void icl_set_cdclk(struct drm_i915_private
> *dev_priv,
> dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
> }
>
> -static u8 icl_calc_voltage_level(int cdclk)
> +static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int
> cdclk)
> {
> - if (cdclk > 556800)
> - return 2;
> - else if (cdclk > 312000)
> - return 1;
> - else
> - return 0;
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + if (cdclk > 312000)
> + return 2;
> + else if (cdclk > 18)
> + return 1;
> + else
> + return 0;
> + } else {
> + if (cdclk > 556800)
> + return 2;
> + else if (cdclk > 312000)
> + return 1;
> + else
> + return 0;
> + }
> }
>
> static void icl_get_cdclk(struct drm_i915_private *dev_priv,
> @@ -1924,7 +1933,7 @@ static void icl_get_cdclk(struct drm_i915_private
> *dev_priv,
>* at least what the CDCLK frequency requires.
>*/
> cdclk_state->voltage_level =
> - icl_calc_voltage_level(cdclk_state->cdclk);
> + icl_calc_voltage_level(dev_priv, cdclk_state->cdclk);
> }
>
> static void icl_init_cdclk(struct drm_i915_private *dev_priv)
> @@ -1959,7 +1968,8 @@ static void icl_init_cdclk(struct drm_i915_private
> *dev_priv)
> sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
>sanitized_state.cdclk);
> sanitized_state.voltage_level =
> - icl_calc_voltage_level(sanitized_state.cdclk);
> + icl_calc_voltage_level(dev_priv,
> +sanitized_state.cdclk);
>
> icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
> }
> @@ -1970,7 +1980,8 @@ static void icl_uninit_cdclk(struct drm_i915_private
> *dev_priv)
>
> cdclk_state.cdclk = cdclk_state.bypass;
> cdclk_state.vco = 0;
> - cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
> + cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv,
> +cdclk_state.cdclk);
>
> icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> }
> @@ -2561,7 +2572,7 @@ static int icl_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> state->cdclk.logical.vco = vco;
> state->cdclk.logical.cdclk = cdclk;
> state->cdclk.logical.voltage_level =
> - max(icl_calc_voltage_level(cdclk),
> + max(icl_calc_voltage_level(dev_priv, cdclk),
> cnl_compute_min_voltage_level(state));
>
> if (!state->active_crtcs) {
> @@ -2571,7 +2582,7 @@ static int icl_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> state->cdclk.actual.vco = vco;
> state->cdclk.actual.cdclk = cdclk;
> state->cdclk.actual.voltage_level =
> - icl_calc_voltage_level(cdclk);
> + icl_calc_voltage_level(dev_priv, cdclk);
> } else {
> state->cdclk.actual = state->cdclk.logical;
> }
> --
> 2.22.0
>
--
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[Intel-gfx] [PATCH] drm/i915/execlists: Always clear ring_pause if we do not submit
In the unlikely case (thank you CI!), we may find ourselves wanting to
issue a preemption but having no runnable requests left. In this case,
we set the semaphore before computing the preemption and so must unset
it before forgetting (or else we leave the machine busywaiting until the
next request comes along and so likely hang).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b3e0e25c5d80..eb813249a8fb 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -233,13 +233,18 @@ static inline u32 intel_hws_preempt_address(struct
intel_engine_cs *engine)
static inline void
ring_set_paused(const struct intel_engine_cs *engine, int state)
{
+ u32 *sema = &engine->status_page.addr[I915_GEM_HWS_PREEMPT];
+
+ if (*sema == state)
+ return;
+
/*
* We inspect HWS_PREEMPT with a semaphore inside
* engine->emit_fini_breadcrumb. If the dword is true,
* the ring is paused as the semaphore will busywait
* until the dword is false.
*/
- engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;
+ *sema = state;
wmb();
}
@@ -1243,6 +1248,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
*port = execlists_schedule_in(last, port - execlists->pending);
memset(port + 1, 0, (last_port - port) * sizeof(*port));
execlists_submit_ports(engine);
+ } else {
+ ring_set_paused(engine, 0);
}
}
--
2.20.1
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Re: [Intel-gfx] [PATCH 1/6] dma-buf: add dynamic DMA-buf handling v10
On Fri, Jun 21, 2019 at 02:06:54PM +0200, Christian König wrote: > Am 21.06.19 um 12:32 schrieb Daniel Vetter: > > On Fri, Jun 21, 2019 at 11:55 AM Christian König > > wrote: > > > Am 21.06.19 um 11:20 schrieb Daniel Vetter: > > > > On Tue, Jun 18, 2019 at 01:54:50PM +0200, Christian König wrote: > > > > [SNIP] > > > > Imo the below semantics would be much cleaner: > > > > > > > > - invalidate may add new fences > > > > - invalidate _must_ unmap its mappings > > > > - an unmap must wait for current fences before the mapping can be > > > > released. > > > > > > > > Imo there's no reason why unmap is special, and the only thing where we > > > > don't use fences to gate access to resources/memory when it's in the > > > > process of getting moved around. > > > Well in general I want to avoid waiting for fences as much as possible. > > > But the key point here is that this actually won't help with the problem > > > I'm trying to solve. > > The point of using fences is not to wait on them. I mean if you have > > the shadow ttm bo on the lru you also don't wait for that fence to > > retire before you insert the shadow bo onto the lru. You don't even > > wait when you try to use that memory again, you just pipeline more > > stuff on top. > > Correct. > > Ok, if I understand it correctly your suggestion is to move the > responsibility to delay destruction of mappings until they are no longer > used from the importer to the exporter based on the fences of the > reservation object. > > I seriously don't think that this is a good idea because you need to move > the tracking who is using which mapping from the importer to the exporter as > well. So duplicating quite a bunch of housekeeping. > > On the other hand that we have this house keeping in the importer because we > get it for free from TTM. But I can't think of a way other memory management > backends would do this without keeping the sg table around either. > > > In the end it will be the exact same amount of fences and waiting in > > both solutions. One just leaks less implementationt details (at least > > in my opinion) across the dma-buf border. > > I agree that leaking implementation details over the DMA-buf border is a bad > idea. > > But I can assure you that this has absolutely nothing todo with the ghost > object handling of TTM. ghost objects doesn't even receive an invalidation, > they are just a possible implementation of the delayed destruction of sg > tables. > > > > > btw this is like the 2nd or 3rd time I'm typing this, haven't seen your > > > > thoughts on this yet. > > > Yeah, and I'm responding for the 3rd time now that you are > > > misunderstanding why we need this here :) > > > > > > Maybe I can make that clear with an example: > > > > > > 1. You got a sharing between device A (exporter) and B (importer) which > > > uses P2P. > > > > > > 2. Now device C (importer) comes along and wants to use the DMA-buf > > > object as well. > > > > > > 3. The handling now figures out that we can't do P2P between device A > > > and device C (for whatever reason). > > > > > > 4. The map_attachment implementation in device driver A doesn't want to > > > fail with -EBUSY and migrates the DMA-buf somewhere where both device A > > > and device C can access it. > > > > > > 5. This migration will result in sending an invalidation event around. > > > And here it doesn't make sense to send this invalidation event to device > > > C, because we know that device C is actually causing this event and > > > doesn't have a valid mapping. > > Hm I thought the last time around there was a different scenario, with > > just one importer: > > > > - importer has a mapping, gets an ->invalidate call. > > - importer arranges for the mappings/usage to get torn down, maybe > > updating fences, all from ->invalidate. But the mapping itself wont > > disappear. > > - exporter moves buffer to new places (for whatever reasons it felt > > that was the thing to do). > > - importer does another execbuf, the exporter needs to move the buffer > > back. Again it calls ->invalidate, but on a mapping it already has > > called ->invalidate on, and to prevent that silliness we take the > > importer temporary off the list. > > Mhm, strange I don't remember giving this explanation. It also doesn't make > to much sense, but see below. Yeah maybe I mixed things up somewhere. I guess you started with the first scenario, I replied with "why don't we track this in the exporter or dma-buf.c then?" and then the thread died out or something. > > > Your scenario here is new, and iirc my suggestion back then was to > > count the number of pending mappings so you don't go around calling > > ->invalidate on mappings that don't exist. > > Well the key point is we don't call invalidate on mappings, but we call > invalidate on attachments. > > When the invalidate on an attachment is received all the importer should at > least start to tear down all mappings. Hm, so either we invalidate
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Disable preemption under GVT
== Series Details == Series: drm/i915/execlists: Disable preemption under GVT URL : https://patchwork.freedesktop.org/series/62533/ State : success == Summary == CI Bug Log - changes from CI_DRM_6324 -> Patchwork_13388 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13388/ Known issues Here are the changes found in Patchwork_13388 that come from known issues: ### IGT changes ### Issues hit * igt@gem_flink_basic@bad-open: - fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-icl-dsi/igt@gem_flink_ba...@bad-open.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13388/fi-icl-dsi/igt@gem_flink_ba...@bad-open.html Possible fixes * igt@gem_exec_create@basic: - fi-icl-guc: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-icl-guc/igt@gem_exec_cre...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13388/fi-icl-guc/igt@gem_exec_cre...@basic.html * igt@i915_module_load@reload-with-fault-injection: - fi-bsw-kefka: [DMESG-WARN][5] ([fdo#110900]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13388/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#110900]: https://bugs.freedesktop.org/show_bug.cgi?id=110900 Participating hosts (52 -> 45) -- Additional (1): fi-icl-u3 Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6324 -> Patchwork_13388 CI_DRM_6324: f80b457bfb36a287607444876ceffd92492b2039 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13388: dcfe467fbaf0859deae88e80f960573888afdf50 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == dcfe467fbaf0 drm/i915/execlists: Disable preemption under GVT == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13388/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Disable preemption under GVT
Quoting Patchwork (2019-06-21 17:42:58) > == Series Details == > > Series: drm/i915/execlists: Disable preemption under GVT > URL : https://patchwork.freedesktop.org/series/62533/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6324 -> Patchwork_13388 > > > Summary > --- > > **SUCCESS** > > No regressions found. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13388/ > > Known issues > > > Here are the changes found in Patchwork_13388 that come from known issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_flink_basic@bad-open: > - fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-icl-dsi/igt@gem_flink_ba...@bad-open.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13388/fi-icl-dsi/igt@gem_flink_ba...@bad-open.html > > > Possible fixes > > * igt@gem_exec_create@basic: > - fi-icl-guc: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-icl-guc/igt@gem_exec_cre...@basic.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13388/fi-icl-guc/igt@gem_exec_cre...@basic.html > > * igt@i915_module_load@reload-with-fault-injection: > - fi-bsw-kefka: [DMESG-WARN][5] ([fdo#110900]) -> [PASS][6] >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13388/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html Well scratch that theory. This didn't fix fi-bdw-gvtdm. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Add one additional PCH ID to MCC
== Series Details == Series: drm/i915/ehl: Add one additional PCH ID to MCC URL : https://patchwork.freedesktop.org/series/62534/ State : success == Summary == CI Bug Log - changes from CI_DRM_6324 -> Patchwork_13389 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13389/ Known issues Here are the changes found in Patchwork_13389 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13389/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html * igt@i915_selftest@live_hangcheck: - fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-icl-u2/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13389/fi-icl-u2/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13389/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_module_load@reload-with-fault-injection: - fi-bsw-kefka: [DMESG-WARN][7] ([fdo#110900]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13389/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html * igt@kms_busy@basic-flip-b: - fi-icl-dsi: [DMESG-WARN][9] ([fdo#106107]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-icl-dsi/igt@kms_b...@basic-flip-b.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13389/fi-icl-dsi/igt@kms_b...@basic-flip-b.html [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#110900]: https://bugs.freedesktop.org/show_bug.cgi?id=110900 Participating hosts (52 -> 44) -- Additional (1): fi-icl-u3 Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6324 -> Patchwork_13389 CI_DRM_6324: f80b457bfb36a287607444876ceffd92492b2039 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13389: eb8167b7b4104bb37de1ab67823ca04f435caaef @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == eb8167b7b410 drm/i915/ehl: Add one additional PCH ID to MCC == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13389/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/ioctl: Ditch DRM_UNLOCKED except for the legacy vblank ioctl
On Fri, Jun 07, 2019 at 11:24:01AM +0100, Emil Velikov wrote: > On Wed, 5 Jun 2019 at 13:08, Daniel Vetter wrote: > > > > This completes Emil's series of removing DRM_UNLOCKED from modern > > drivers. It's entirely cargo-culted since we ignore it on > > non-DRIVER_LEGACY drivers since: > > > > commit ea487835e8876abf7ad909636e308c801a2bcda6 > > Author: Daniel Vetter > > Date: Mon Sep 28 21:42:40 2015 +0200 > > > > drm: Enforce unlocked ioctl operation for kms driver ioctls > > > > Now justifying why we can do this for legacy drives too (and hence > > close the source of all the bogus copypasting) is a bit more involved. > > DRM_UNLOCKED was introduced in: > > > > commit ed8b67040965e4fe695db333d5914e18ea5f146f > > Author: Arnd Bergmann > > Date: Wed Dec 16 22:17:09 2009 + > > > > drm: convert drm_ioctl to unlocked_ioctl > > > > As a immediate hack to keep i810 happy, which would have deadlocked > > without this trickery. The old BKL is automatically dropped in > > schedule(), and hence the i810 vs. mmap_sem deadlock didn't actually > > cause a real deadlock. But with a mutex it would. The solution was to > > annotate these as DRM_UNLOCKED and mark i810 unsafe on SMP machines. > > > > This conversion caused a regression, because unlike the BKL a mutex > > isn't dropped over schedule (that thing again), which caused a vblank > > wait in one thread to block the entire desktop and all its apps. Back > > then we did vblank scheduling by blocking in the client, awesome isn't > > it. This was fixed quickly in (ok not so quickly, took 2 years): > > > > commit 8f4ff2b06afcd6f151868474a432c603057eaf56 > > Author: Ilija Hadzic > > Date: Mon Oct 31 17:46:18 2011 -0400 > > > > drm: do not sleep on vblank while holding a mutex > > > > All the other DRM_UNLOCKED annotations for all the core ioctls was > > work to reach finer-grained locking for modern drivers. This took > > years, and culminated in: > > > > commit fdd5b877e9ebc2029e1373b4a3cd057329a9ab7a > > Author: Daniel Vetter > > Date: Sat Dec 10 22:52:54 2016 +0100 > > > > drm: Enforce BKL-less ioctls for modern drivers > > > > DRM_UNLOCKED was never required by any legacy drivers, except for the > > vblank_wait IOCTL. Therefore we will not regress these old drivers by > > going back to where we've been in 2011. For all modern drivers nothing > > will change. > > > > To make this perfectly clear, also add a comment to DRM_UNLOCKED. > > > > v2: Don't forget about drm_ioc32.c (Michel). Not a source of copypasta > > mistakes when creating driver ioctl tables, but better to be > > consistent. > > > Personally I would omit the "Not a source of copupasta..." note. Done. > > Cc: Michel Dänzer > > Cc: Emil Velikov > > Signed-off-by: Daniel Vetter > > Double-checked that only the VBLACK ioctl retained its annotation and > all other core ioctls are DRM_UNLOCKED free. > Technically with this change UMS drivers will start using a lock on > the listed ioctls. I do not expect this to be a problem and admittedly > I did not audit existing userspace. > > That said, the patch looks reasonable: > Acked-by: Emil Velikov Applied also with Michel's irc ack. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Always clear ring_pause if we do not submit
== Series Details == Series: drm/i915/execlists: Always clear ring_pause if we do not submit URL : https://patchwork.freedesktop.org/series/62540/ State : success == Summary == CI Bug Log - changes from CI_DRM_6324 -> Patchwork_13390 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13390/ Known issues Here are the changes found in Patchwork_13390 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@basic-all: - fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-icl-guc/igt@gem_exec_ba...@basic-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13390/fi-icl-guc/igt@gem_exec_ba...@basic-all.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-6600u: [PASS][3] -> [FAIL][4] ([fdo#107707]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13390/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [PASS][5] -> [INCOMPLETE][6] ([fdo#108602]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-skl-iommu/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13390/fi-skl-iommu/igt@i915_selftest@live_blt.html Possible fixes * igt@i915_module_load@reload-with-fault-injection: - fi-bsw-kefka: [DMESG-WARN][7] ([fdo#110900]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6324/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13390/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html [fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#110900]: https://bugs.freedesktop.org/show_bug.cgi?id=110900 Participating hosts (52 -> 44) -- Additional (1): fi-icl-u3 Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus Build changes - * Linux: CI_DRM_6324 -> Patchwork_13390 CI_DRM_6324: f80b457bfb36a287607444876ceffd92492b2039 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13390: f1850065c1cd9ab2a4597f8512ba5da5bee3ae67 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f1850065c1cd drm/i915/execlists: Always clear ring_pause if we do not submit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13390/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] drm/i915/guc: reorder enable/disable communication steps
Make sure we always have CT buffers enabled when the interrupts are
enabled, so we can always handle interrupts from GuC. Also move the
setting of the guc->send and guc->handler functions to the GuC
communication control functions for consistency.
The reorder also fixes the onion unwinding of intel_uc_init_hw, because
guc_enable_communication would've left interrupts enabled when failing
to enable CTB.
v2: always retunr the result of ctch_enable() in
intel_guc_ct_enable() (Michal)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110943
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Reviewed-by: Matthew Brost
Reviewed-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_guc_ct.c | 22 --
drivers/gpu/drm/i915/intel_guc_ct.h | 4
drivers/gpu/drm/i915/intel_uc.c | 19 ---
3 files changed, 24 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c
b/drivers/gpu/drm/i915/intel_guc_ct.c
index 3921809f812b..9e383a47609f 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -529,8 +529,8 @@ static int ctch_send(struct intel_guc_ct *ct,
/*
* Command Transport (CT) buffer based GuC send function.
*/
-static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
-u32 *response_buf, u32 response_buf_size)
+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
+ u32 *response_buf, u32 response_buf_size)
{
struct intel_guc_ct *ct = &guc->ct;
struct intel_guc_ct_channel *ctch = &ct->host_channel;
@@ -834,7 +834,7 @@ static void ct_process_host_channel(struct intel_guc_ct *ct)
* When we're communicating with the GuC over CT, GuC uses events
* to notify us about new messages being posted on the RECV buffer.
*/
-static void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
{
struct intel_guc_ct *ct = &guc->ct;
@@ -892,20 +892,11 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
struct intel_guc_ct_channel *ctch = &ct->host_channel;
- int err;
if (ctch->enabled)
return 0;
- err = ctch_enable(guc, ctch);
- if (unlikely(err))
- return err;
-
- /* Switch into cmd transport buffer based send() */
- guc->send = intel_guc_send_ct;
- guc->handler = intel_guc_to_host_event_handler_ct;
- DRM_INFO("CT: %s\n", enableddisabled(true));
- return 0;
+ return ctch_enable(guc, ctch);
}
/**
@@ -921,9 +912,4 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
return;
ctch_disable(guc, ctch);
-
- /* Disable send */
- guc->send = intel_guc_send_nop;
- guc->handler = intel_guc_to_host_event_handler_nop;
- DRM_INFO("CT: %s\n", enableddisabled(false));
}
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.h
b/drivers/gpu/drm/i915/intel_guc_ct.h
index 41ba593a4df7..0ec17493d83b 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/intel_guc_ct.h
@@ -101,4 +101,8 @@ static inline void intel_guc_ct_stop(struct intel_guc_ct
*ct)
ct->host_channel.enabled = false;
}
+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
+ u32 *response_buf, u32 response_buf_size);
+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
+
#endif /* _INTEL_GUC_CT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ae45651ac73c..c7f82c944dd6 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -235,9 +235,20 @@ static void guc_disable_interrupts(struct intel_guc *guc)
static int guc_enable_communication(struct intel_guc *guc)
{
+ int ret;
+
+ ret = intel_guc_ct_enable(&guc->ct);
+ if (ret)
+ return ret;
+
+ guc->send = intel_guc_send_ct;
+ guc->handler = intel_guc_to_host_event_handler_ct;
+
guc_enable_interrupts(guc);
- return intel_guc_ct_enable(&guc->ct);
+ DRM_INFO("GuC communication enabled\n");
+
+ return 0;
}
static void guc_stop_communication(struct intel_guc *guc)
@@ -250,12 +261,14 @@ static void guc_stop_communication(struct intel_guc *guc)
static void guc_disable_communication(struct intel_guc *guc)
{
- intel_guc_ct_disable(&guc->ct);
-
guc_disable_interrupts(guc);
guc->send = intel_guc_send_nop;
guc->handler = intel_guc_to_host_event_handler_nop;
+
+ intel_guc_ct_disable(&guc->ct);
+
+ DRM_INFO("GuC communication disabled\n");
}
int intel_uc_init_misc(struct drm_i915_private *i915)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mai
[Intel-gfx] [PATCH v2 2/2] drm/i915/guc: handle GuC messages received with CTB disabled
There is a very small chance of triggering a log flush event when
enabling or disabling CT buffers. Events triggered while CT buffers
are disabled are logged in the SCRATCH_15 register using the same bits
used in the CT message payload. Since our communication channel with
GuC is turned off, we can save the message and handle it after we turn
it back on.
GuC should be idle and not generate more events in the meantime because
we're not talking to it.
v2: clear the mmio register on stop_communication as well (Chris)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc.h | 5 +++
drivers/gpu/drm/i915/intel_uc.c | 74
2 files changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 08c906abdfa2..d6a75bc3d7f4 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -88,6 +88,9 @@ struct intel_guc {
enum forcewake_domains fw_domains;
} send_regs;
+ /* Store msg (e.g. log flush) that we see while CTBs are disabled */
+ u32 mmio_msg;
+
/* To serialize the intel_guc_send actions */
struct mutex send_mutex;
@@ -181,6 +184,8 @@ static inline bool intel_guc_is_loaded(struct intel_guc
*guc)
static inline int intel_guc_sanitize(struct intel_guc *guc)
{
intel_uc_fw_sanitize(&guc->fw);
+ guc->mmio_msg = 0;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index c7f82c944dd6..fdf00f1ebb57 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -218,6 +218,53 @@ static void guc_free_load_err_log(struct intel_guc *guc)
i915_gem_object_put(guc->load_err_log);
}
+/*
+ * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
+ * register using the same bits used in the CT message payload. Since our
+ * communication channel with guc is turned off at this point, we can save the
+ * message and handle it after we turn it back on.
+ */
+static void guc_clear_mmio_msg(struct intel_guc *guc)
+{
+ intel_uncore_write(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15), 0);
+}
+
+static void guc_get_mmio_msg(struct intel_guc *guc)
+{
+ u32 val;
+
+ spin_lock_irq(&guc->irq_lock);
+
+ val = intel_uncore_read(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15));
+ guc->mmio_msg |= val & guc->msg_enabled_mask;
+
+ /*
+* clear all events, including the ones we're not currently servicing,
+* to make sure we don't try to process a stale message if we enable
+* handling of more events later.
+*/
+ guc_clear_mmio_msg(guc);
+
+ spin_unlock_irq(&guc->irq_lock);
+}
+
+static void guc_handle_mmio_msg(struct intel_guc *guc)
+{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+
+ /* we need communication to be enabled to reply to GuC */
+ GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop);
+
+ if (!guc->mmio_msg)
+ return;
+
+ spin_lock_irq(&i915->irq_lock);
+ intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
+ spin_unlock_irq(&i915->irq_lock);
+
+ guc->mmio_msg = 0;
+}
+
static void guc_reset_interrupts(struct intel_guc *guc)
{
guc->interrupts.reset(guc_to_i915(guc));
@@ -235,6 +282,7 @@ static void guc_disable_interrupts(struct intel_guc *guc)
static int guc_enable_communication(struct intel_guc *guc)
{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
int ret;
ret = intel_guc_ct_enable(&guc->ct);
@@ -244,8 +292,17 @@ static int guc_enable_communication(struct intel_guc *guc)
guc->send = intel_guc_send_ct;
guc->handler = intel_guc_to_host_event_handler_ct;
+ /* check for mmio messages received before/during the CT enable */
+ guc_get_mmio_msg(guc);
+ guc_handle_mmio_msg(guc);
+
guc_enable_interrupts(guc);
+ /* check for CT messages received before we enabled interrupts */
+ spin_lock_irq(&i915->irq_lock);
+ intel_guc_to_host_event_handler_ct(guc);
+ spin_unlock_irq(&i915->irq_lock);
+
DRM_INFO("GuC communication enabled\n");
return 0;
@@ -257,10 +314,19 @@ static void guc_stop_communication(struct intel_guc *guc)
guc->send = intel_guc_send_nop;
guc->handler = intel_guc_to_host_event_handler_nop;
+
+ guc_clear_mmio_msg(guc);
}
static void guc_disable_communication(struct intel_guc *guc)
{
+ /*
+* Events generated during or after CT disable are logged by guc in
+* via mmio. Make sure the register is clear before disabling CT since
+* all events we cared about have already been processed via CT.
+*/
+ guc_clear_mmio_msg(guc);
+
guc_disable_interrupts(guc);
guc->send = intel_guc_send_nop;
@@ -268,6 +334,14 @@ st
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/guc: handle GuC messages received with CTB disabled
Quoting Daniele Ceraolo Spurio (2019-06-21 19:21:23) > There is a very small chance of triggering a log flush event when > enabling or disabling CT buffers. Events triggered while CT buffers > are disabled are logged in the SCRATCH_15 register using the same bits > used in the CT message payload. Since our communication channel with > GuC is turned off, we can save the message and handle it after we turn > it back on. > GuC should be idle and not generate more events in the meantime because > we're not talking to it. > > v2: clear the mmio register on stop_communication as well (Chris) > > Signed-off-by: Daniele Ceraolo Spurio > Cc: Michal Wajdeczko > Cc: Chris Wilson I'll take your word that the guc leaves useful tidbits of info there. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/5] drm/i915: Remove waiting & retiring from shrinker paths
i915_gem_wait_for_idle() and i915_retire_requests() introduce a
dependency on the timeline->mutex. This is problematic as we want to
later perform allocations underneath i915_active.mutex, forming a link
between the shrinker, the timeline and active mutexes. Nip this cycle in
the bud by removing the acquisition of the timeline mutex (i.e.
retiring) from inside the shrinker.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 10 --
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 3 ---
4 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 3a926a8755c6..1bbc690494c7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -169,7 +169,6 @@ i915_gem_shrink(struct drm_i915_private *i915,
*/
trace_i915_gem_shrink(i915, target, shrink);
- i915_retire_requests(i915);
/*
* Unbinding of objects will require HW access; Let us not wake the
@@ -269,8 +268,6 @@ i915_gem_shrink(struct drm_i915_private *i915,
if (shrink & I915_SHRINK_BOUND)
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
- i915_retire_requests(i915);
-
shrinker_unlock(i915, unlock);
if (nr_scanned)
@@ -427,12 +424,6 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned
long event, void *ptr
if (!shrinker_lock(i915, 0, &unlock))
return NOTIFY_DONE;
- /* Force everything onto the inactive lists */
- if (i915_gem_wait_for_idle(i915,
- I915_WAIT_LOCKED,
- MAX_SCHEDULE_TIMEOUT))
- goto out;
-
with_intel_runtime_pm(&i915->runtime_pm, wakeref)
freed_pages += i915_gem_shrink(i915, -1UL, NULL,
I915_SHRINK_BOUND |
@@ -455,7 +446,6 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned
long event, void *ptr
}
mutex_unlock(&i915->ggtt.vm.mutex);
-out:
shrinker_unlock(i915, unlock);
*(unsigned long *)ptr += freed_pages;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 167c4a57c4cd..53c81b5dfd69 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -427,6 +427,9 @@ create_test_object(struct i915_gem_context *ctx,
u64 size;
int err;
+ /* Keep in GEM's good graces */
+ i915_retire_requests(ctx->i915);
+
size = min(vm->total / 2, 1024ull * DW_PER_PAGE * PAGE_SIZE);
size = round_down(size, DW_PER_PAGE * PAGE_SIZE);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 722506b7cec0..c03e56628ee2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -26,7 +26,7 @@ struct intel_gt {
struct i915_ggtt *ggtt;
struct intel_gt_timelines {
- struct mutex mutex; /* protects list, tainted by GPU */
+ struct mutex mutex; /* protects list */
struct list_head active_list;
/* Pack multiple timelines' seqnos into the same page */
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index d6accef50f8e..44273b7c96f8 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -268,9 +268,6 @@ static void timelines_init(struct intel_gt *gt)
spin_lock_init(&timelines->hwsp_lock);
INIT_LIST_HEAD(&timelines->hwsp_free_list);
-
- /* via i915_gem_wait_for_idle() */
- i915_gem_shrinker_taints_mutex(gt->i915, &timelines->mutex);
}
void intel_timelines_init(struct drm_i915_private *i915)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/5] drm/i915: Track i915_active using debugobjects
Provide runtime asserts and tracking of i915_active via debugobjects.
For example, this should allow us to check that the i915_active is only
active when we expect it to be and is never freed too early.
One consequence is that, for simplicity, we no longer allow i915_active
to be on-stack which only affected the selftests.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_active.c | 66 -
drivers/gpu/drm/i915/selftests/i915_active.c | 78 +++-
2 files changed, 123 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 293e5bcc4b6c..eb91a625c71f 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -4,6 +4,8 @@
* Copyright © 2019 Intel Corporation
*/
+#include
+
#include "gt/intel_engine_pm.h"
#include "i915_drv.h"
@@ -31,6 +33,55 @@ struct active_node {
u64 timeline;
};
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && IS_ENABLED(CONFIG_DEBUG_OBJECTS)
+
+static void *active_debug_hint(void *addr)
+{
+ struct i915_active *ref = addr;
+
+ return (void *)ref->retire ?: (void *)ref;
+}
+
+static struct debug_obj_descr active_debug_desc = {
+ .name = "i915_active",
+ .debug_hint = active_debug_hint,
+};
+
+static void debug_active_init(struct i915_active *ref)
+{
+ debug_object_init(ref, &active_debug_desc);
+}
+
+static void debug_active_activate(struct i915_active *ref)
+{
+ debug_object_activate(ref, &active_debug_desc);
+}
+
+static void debug_active_deactivate(struct i915_active *ref)
+{
+ debug_object_deactivate(ref, &active_debug_desc);
+}
+
+static void debug_active_fini(struct i915_active *ref)
+{
+ debug_object_free(ref, &active_debug_desc);
+}
+
+static void debug_active_assert(struct i915_active *ref)
+{
+ debug_object_assert_init(ref, &active_debug_desc);
+}
+
+#else
+
+static inline void debug_active_init(struct i915_active *ref) { }
+static inline void debug_active_activate(struct i915_active *ref) { }
+static inline void debug_active_deactivate(struct i915_active *ref) { }
+static inline void debug_active_fini(struct i915_active *ref) { }
+static inline void debug_active_assert(struct i915_active *ref) { }
+
+#endif
+
static void
__active_park(struct i915_active *ref)
{
@@ -50,6 +101,8 @@ __active_retire(struct i915_active *ref)
if (--ref->count)
return;
+ debug_active_deactivate(ref);
+
/* return the unused nodes to our slabcache */
__active_park(ref);
@@ -155,6 +208,8 @@ void i915_active_init(struct drm_i915_private *i915,
struct i915_active *ref,
void (*retire)(struct i915_active *ref))
{
+ debug_active_init(ref);
+
ref->i915 = i915;
ref->retire = retire;
ref->tree = RB_ROOT;
@@ -191,13 +246,21 @@ int i915_active_ref(struct i915_active *ref,
bool i915_active_acquire(struct i915_active *ref)
{
+ debug_active_assert(ref);
lockdep_assert_held(BKL(ref));
- return !ref->count++;
+
+ if (ref->count++)
+ return false;
+
+ debug_active_activate(ref);
+ return true;
}
void i915_active_release(struct i915_active *ref)
{
+ debug_active_assert(ref);
lockdep_assert_held(BKL(ref));
+
__active_retire(ref);
}
@@ -260,6 +323,7 @@ int i915_request_await_active(struct i915_request *rq,
struct i915_active *ref)
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
void i915_active_fini(struct i915_active *ref)
{
+ debug_active_fini(ref);
GEM_BUG_ON(i915_active_request_isset(&ref->last));
GEM_BUG_ON(!RB_EMPTY_ROOT(&ref->tree));
GEM_BUG_ON(ref->count);
diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c
b/drivers/gpu/drm/i915/selftests/i915_active.c
index c0b3537a5fa6..98493bcc91f2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_active.c
+++ b/drivers/gpu/drm/i915/selftests/i915_active.c
@@ -16,28 +16,51 @@ struct live_active {
bool retired;
};
-static void __live_active_retire(struct i915_active *base)
+static void __live_free(struct live_active *active)
+{
+ i915_active_fini(&active->base);
+ kfree(active);
+}
+
+static void __live_retire(struct i915_active *base)
{
struct live_active *active = container_of(base, typeof(*active), base);
active->retired = true;
}
-static int __live_active_setup(struct drm_i915_private *i915,
- struct live_active *active)
+static struct live_active *__live_alloc(struct drm_i915_private *i915)
+{
+ struct live_active *active;
+
+ active = kzalloc(sizeof(*active), GFP_KERNEL);
+ if (!active)
+ return NULL;
+
+ i915_active_init(i915, &active->base, __live_retire);
+
+ return active;
+}
+
+static struct live_active *
+__live_active_setup(struct drm_i915_private *i915)
{
[Intel-gfx] [CI 3/5] drm/i915: Throw away the active object retirement complexity
Remove the accumulated optimisations that we have for i915_vma_retire
and reduce it to the bare essential of tracking the active object
reference. This allows us to only use atomic operations, and so will be
able to avoid the struct_mutex requirement.
The principal loss here is the shrinker MRU bumping, so now if we have
to shrink, we will do so in much more random order and more likely to
try and shrink recently used objects. That is a nuisance, but shrinking
active objects is a second step we try to avoid and will always be a
system-wide performance issue.
The other loss is here is in the automatic pruning of the
reservation_object when idling. This is not as large an issue as upon
reservation_object introduction as now adding new fences into the object
replaces already signaled fences, keeping the array compact. But we do
lose the auto-expiration of stale fences and unused arrays. That may be
a noticeable problem for which we need to re-implement autopruning.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 1 -
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 ---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 -
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 5 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 9
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 1 -
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 34 +---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +--
drivers/gpu/drm/i915/i915_gem_batch_pool.c| 42 ++-
drivers/gpu/drm/i915/i915_vma.c | 54 ---
11 files changed, 47 insertions(+), 118 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 87275f9883ac..43194fbcbc2e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -160,7 +160,6 @@ static void __i915_gem_free_objects(struct drm_i915_private
*i915,
mutex_lock(&i915->drm.struct_mutex);
- GEM_BUG_ON(i915_gem_object_is_active(obj));
list_for_each_entry_safe(vma, vn, &obj->vma.list, obj_link) {
GEM_BUG_ON(i915_vma_is_active(vma));
vma->flags &= ~I915_VMA_PIN_MASK;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index dfebd5706f16..20754c15412a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -158,12 +158,6 @@ i915_gem_object_needs_async_cancel(const struct
drm_i915_gem_object *obj)
return obj->ops->flags & I915_GEM_OBJECT_ASYNC_CANCEL;
}
-static inline bool
-i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
-{
- return READ_ONCE(obj->active_count);
-}
-
static inline bool
i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 18bf4f8d6d80..34b51fad02de 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -154,7 +154,6 @@ struct drm_i915_gem_object {
/** Count of VMA actually bound by this object */
atomic_t bind_count;
- unsigned int active_count;
/** Count of how many global VMA are currently pinned for use by HW */
unsigned int pin_global;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 1bbc690494c7..d99f1a600b96 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -229,8 +229,9 @@ i915_gem_shrink(struct drm_i915_private *i915,
continue;
if (!(shrink & I915_SHRINK_ACTIVE) &&
- (i915_gem_object_is_active(obj) ||
-i915_gem_object_is_framebuffer(obj)))
+ (i915_gem_object_is_framebuffer(obj) ||
+
!reservation_object_test_signaled_rcu(obj->base.resv,
+ true)))
continue;
if (!(shrink & I915_SHRINK_BOUND) &&
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 2812f7fa27fe..24a3c677ccd5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -475,15 +475,6 @@ static int igt_mmap_offset_exhaustion(void *arg)
pr_err("[loop %d] Failed to busy the object\n", loop);
goto err_obj;
}
-
- /* NB we rely on the _active_ reference to access
[Intel-gfx] [CI 5/5] drm/i915: Local debug BUG_ON for intel_wakeref
Avoid pulling in i915_gem.h just so that we can use a conditional BUG_ON
for debugging.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_wakeref.c | 9 +
drivers/gpu/drm/i915/intel_wakeref.h | 7 +++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
b/drivers/gpu/drm/i915/intel_wakeref.c
index 3db6fa682823..06bd8b215cc2 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -5,7 +5,7 @@
*/
#include "intel_runtime_pm.h"
-#include "i915_gem.h"
+#include "intel_wakeref.h"
static void rpm_get(struct intel_runtime_pm *rpm, struct intel_wakeref *wf)
{
@@ -17,7 +17,7 @@ static void rpm_put(struct intel_runtime_pm *rpm, struct
intel_wakeref *wf)
intel_wakeref_t wakeref = fetch_and_zero(&wf->wakeref);
intel_runtime_pm_put(rpm, wakeref);
- GEM_BUG_ON(!wakeref);
+ INTEL_WAKEREF_BUG_ON(!wakeref);
}
int __intel_wakeref_get_first(struct intel_runtime_pm *rpm,
@@ -48,6 +48,7 @@ int __intel_wakeref_get_first(struct intel_runtime_pm *rpm,
atomic_inc(&wf->count);
mutex_unlock(&wf->mutex);
+ INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);
return 0;
}
@@ -115,7 +116,7 @@ void intel_wakeref_auto(struct intel_wakeref_auto *wf,
unsigned long timeout)
if (!refcount_inc_not_zero(&wf->count)) {
spin_lock_irqsave(&wf->lock, flags);
if (!refcount_inc_not_zero(&wf->count)) {
- GEM_BUG_ON(wf->wakeref);
+ INTEL_WAKEREF_BUG_ON(wf->wakeref);
wf->wakeref = intel_runtime_pm_get_if_in_use(wf->rpm);
refcount_set(&wf->count, 1);
}
@@ -134,5 +135,5 @@ void intel_wakeref_auto(struct intel_wakeref_auto *wf,
unsigned long timeout)
void intel_wakeref_auto_fini(struct intel_wakeref_auto *wf)
{
intel_wakeref_auto(wf, 0);
- GEM_BUG_ON(wf->wakeref);
+ INTEL_WAKEREF_BUG_ON(wf->wakeref);
}
diff --git a/drivers/gpu/drm/i915/intel_wakeref.h
b/drivers/gpu/drm/i915/intel_wakeref.h
index 9cbb2ebf575b..d45e78639dc4 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.h
+++ b/drivers/gpu/drm/i915/intel_wakeref.h
@@ -13,6 +13,12 @@
#include
#include
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
+#define INTEL_WAKEREF_BUG_ON(expr) BUG_ON(expr)
+#else
+#define INTEL_WAKEREF_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
+#endif
+
struct intel_runtime_pm;
typedef depot_stack_handle_t intel_wakeref_t;
@@ -86,6 +92,7 @@ intel_wakeref_put(struct intel_runtime_pm *rpm,
struct intel_wakeref *wf,
int (*fn)(struct intel_wakeref *wf))
{
+ INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);
if (atomic_dec_and_mutex_lock(&wf->count, &wf->mutex))
return __intel_wakeref_put_last(rpm, wf, fn);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/5] drm/i915: Provide an i915_active.acquire callback
If we introduce a callback for i915_active that is only called the first
time we use the i915_active and is symmetrically paired with the
i915_active.retire callback, we can replace the open-coded and
non-atomic implementations -- which will be very fragile (i.e. broken)
upon removing the struct_mutex serialisation.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 8 +-
drivers/gpu/drm/i915/gt/intel_context.c | 65 +++---
drivers/gpu/drm/i915/gt/intel_context.h | 14 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +-
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 16 +-
drivers/gpu/drm/i915/gt/mock_engine.c| 2 +-
drivers/gpu/drm/i915/i915_active.c | 225 ++-
drivers/gpu/drm/i915/i915_active.h | 25 ++-
drivers/gpu/drm/i915/i915_active_types.h | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 22 +-
drivers/gpu/drm/i915/selftests/i915_active.c | 53 -
13 files changed, 258 insertions(+), 192 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 628673d1d7f8..8a9787cf0cd0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -923,8 +923,12 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
if (!cb)
return -ENOMEM;
- i915_active_init(i915, &cb->base, cb_retire);
- i915_active_acquire(&cb->base);
+ i915_active_init(i915, &cb->base, NULL, cb_retire);
+ err = i915_active_acquire(&cb->base);
+ if (err) {
+ kfree(cb);
+ return err;
+ }
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
struct i915_request *rq;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 23120901c55f..938dd032b820 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -95,11 +95,15 @@ void intel_context_unpin(struct intel_context *ce)
intel_context_put(ce);
}
-static int __context_pin_state(struct i915_vma *vma, unsigned long flags)
+static int __context_pin_state(struct i915_vma *vma)
{
+ u64 flags;
int err;
- err = i915_vma_pin(vma, 0, 0, flags | PIN_GLOBAL);
+ flags = i915_ggtt_pin_bias(vma) | PIN_OFFSET_BIAS;
+ flags |= PIN_HIGH | PIN_GLOBAL;
+
+ err = i915_vma_pin(vma, 0, 0, flags);
if (err)
return err;
@@ -119,7 +123,7 @@ static void __context_unpin_state(struct i915_vma *vma)
__i915_vma_unpin(vma);
}
-static void intel_context_retire(struct i915_active *active)
+static void __intel_context_retire(struct i915_active *active)
{
struct intel_context *ce = container_of(active, typeof(*ce), active);
@@ -130,35 +134,11 @@ static void intel_context_retire(struct i915_active
*active)
intel_context_put(ce);
}
-void
-intel_context_init(struct intel_context *ce,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
- GEM_BUG_ON(!engine->cops);
-
- kref_init(&ce->ref);
-
- ce->gem_context = ctx;
- ce->engine = engine;
- ce->ops = engine->cops;
- ce->sseu = engine->sseu;
-
- INIT_LIST_HEAD(&ce->signal_link);
- INIT_LIST_HEAD(&ce->signals);
-
- mutex_init(&ce->pin_mutex);
-
- i915_active_init(ctx->i915, &ce->active, intel_context_retire);
-}
-
-int intel_context_active_acquire(struct intel_context *ce, unsigned long flags)
+static int __intel_context_active(struct i915_active *active)
{
+ struct intel_context *ce = container_of(active, typeof(*ce), active);
int err;
- if (!i915_active_acquire(&ce->active))
- return 0;
-
intel_context_get(ce);
err = intel_ring_pin(ce->ring);
@@ -168,7 +148,7 @@ int intel_context_active_acquire(struct intel_context *ce,
unsigned long flags)
if (!ce->state)
return 0;
- err = __context_pin_state(ce->state, flags);
+ err = __context_pin_state(ce->state);
if (err)
goto err_ring;
@@ -188,15 +168,30 @@ int intel_context_active_acquire(struct intel_context
*ce, unsigned long flags)
intel_ring_unpin(ce->ring);
err_put:
intel_context_put(ce);
- i915_active_cancel(&ce->active);
return err;
}
-void intel_context_active_release(struct intel_context *ce)
+void
+intel_context_init(struct intel_context *ce,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine)
{
- /* Nodes preallocated in intel_context_active() */
- i915_active_acquire_barrier(&ce->active);
- i915_active_release(&ce->
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/icl: Assign Master slave crtc links for Transcoder Port Sync
As per the feedback, I tested the code with saving master_transcoder instead of
master_crtc
and in the HW state readout I loop through all transcoders to fill the
trans_port_sync_slaves bitmask.
This is working great and i dont see any pipe state mismatches now.
Thanks for all the feedback and I will be sending the new patch revision out
later today.
Regards
Manasi
On Thu, Jun 13, 2019 at 01:13:28PM -0700, Manasi Navare wrote:
> On Thu, Jun 13, 2019 at 08:12:37PM +0300, Ville Syrjälä wrote:
> > On Thu, Jun 13, 2019 at 09:41:42AM -0700, Manasi Navare wrote:
> > > On Thu, Jun 13, 2019 at 12:10:57PM +0300, Ville Syrjälä wrote:
> > > > On Wed, Jun 12, 2019 at 01:59:52PM -0700, Manasi Navare wrote:
> > > > > On Wed, Jun 12, 2019 at 10:30:55PM +0300, Ville Syrjälä wrote:
> > > > > > On Wed, Jun 12, 2019 at 12:11:02PM -0700, Manasi Navare wrote:
> > > > > > > On Wed, Jun 12, 2019 at 10:04:26PM +0300, Ville Syrjälä wrote:
> > > > > > > > On Wed, Jun 12, 2019 at 11:39:03AM +0200, Maarten Lankhorst
> > > > > > > > wrote:
> > > > > > > > > Op 23-04-2019 om 17:48 schreef Manasi Navare:
> > > > > > > > > > In case of tiled displays when the two tiles are sent
> > > > > > > > > > across two CRTCs
> > > > > > > > > > over two separate DP SST connectors, we need a mechanism to
> > > > > > > > > > synchronize
> > > > > > > > > > the two CRTCs and their corresponding transcoders.
> > > > > > > > > > So use the master-slave mode where there is one master
> > > > > > > > > > corresponding
> > > > > > > > > > to last horizontal and vertical tile that needs to be
> > > > > > > > > > genlocked with
> > > > > > > > > > all other slave tiles.
> > > > > > > > > > This patch identifies saves the master CRTC pointer in all
> > > > > > > > > > the slave
> > > > > > > > > > CRTC states. This pointer is needed to select the master
> > > > > > > > > > CRTC/transcoder
> > > > > > > > > > while configuring transcoder port sync for the
> > > > > > > > > > corresponding slaves.
> > > > > > > > > >
> > > > > > > > > > v2:
> > > > > > > > > > * Move this to intel_mode_set_pipe_config(Jani N, Ville)
> > > > > > > > > > * Use slave_bitmask to save associated slaves in master
> > > > > > > > > > crtc state (Ville)
> > > > > > > > > >
> > > > > > > > > > Cc: Daniel Vetter
> > > > > > > > > > Cc: Ville Syrjälä
> > > > > > > > > > Cc: Maarten Lankhorst
> > > > > > > > > > Cc: Matt Roper
> > > > > > > > > > Signed-off-by: Manasi Navare
> > > > > > > > > > ---
> > > > > > > > > > drivers/gpu/drm/i915/intel_display.c | 89
> > > > > > > > > >
> > > > > > > > > > drivers/gpu/drm/i915/intel_drv.h | 6 ++
> > > > > > > > > > 2 files changed, 95 insertions(+)
> > > > > > > > > >
> > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > > > > > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > > > > > > > index b276345779e6..92dea2231499 100644
> > > > > > > > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > > > > > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > > > > > > > @@ -11316,6 +11316,86 @@ static int
> > > > > > > > > > icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
> > > > > > > > > > return 0;
> > > > > > > > > > }
> > > > > > > > > >
> > > > > > > > > > +static int icl_add_genlock_crtcs(struct drm_crtc *crtc,
> > > > > > > > > > +struct intel_crtc_state
> > > > > > > > > > *crtc_state,
> > > > > > > > > > +struct drm_atomic_state *state)
> > > > > > > > > > +{
> > > > > > > > > > + struct drm_i915_private *dev_priv =
> > > > > > > > > > to_i915(crtc_state->base.crtc->dev);
> > > > > > > > > > + struct drm_connector *master_connector, *connector;
> > > > > > > > > > + struct drm_connector_state *connector_state;
> > > > > > > > > > + struct drm_connector_list_iter conn_iter;
> > > > > > > > > > + struct drm_crtc *master_crtc = NULL;
> > > > > > > > > > + struct drm_crtc_state *master_crtc_state;
> > > > > > > > > > + int i, tile_group_id;
> > > > > > > > > > +
> > > > > > > > > > + if (INTEL_GEN(dev_priv) < 11)
> > > > > > > > > > + return 0;
> > > > > > > > > > +
> > > > > > > > > > + /*
> > > > > > > > > > +* In case of tiled displays there could be one or more
> > > > > > > > > > slaves but there is
> > > > > > > > > > +* only one master. Lets make the CRTC used by the
> > > > > > > > > > connector corresponding
> > > > > > > > > > +* to the last horizonal and last vertical tile a
> > > > > > > > > > master/genlock CRTC.
> > > > > > > > > > +* All the other CRTCs corresponding to other tiles of
> > > > > > > > > > the same Tile group
> > > > > > > > > > +* are the slave CRTCs and hold a pointer to their
> > > > > > > > > > genlock CRTC.
> > > > > > > > > > +*/
> > > > > > > > > > + for_each_new_connector_in_state(state, connector,
> > > > > > > > > > connector_state, i) {
> > > > > > > > > > + if (connector_
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Remove waiting & retiring from shrinker paths
== Series Details == Series: series starting with [1/5] drm/i915: Remove waiting & retiring from shrinker paths URL : https://patchwork.freedesktop.org/series/62526/ State : success == Summary == CI Bug Log - changes from CI_DRM_6323_full -> Patchwork_13384_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13384_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-glk: [PASS][1] -> [FAIL][2] ([fdo#110667]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-glk9/igt@gem_...@in-flight-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-glk4/igt@gem_...@in-flight-suspend.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-iclb2/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_partial_pwrite_pread@reads-snoop: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#110913 ]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-kbl3/igt@gem_partial_pwrite_pr...@reads-snoop.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-kbl4/igt@gem_partial_pwrite_pr...@reads-snoop.html * igt@gem_persistent_relocs@forked-thrashing: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#110913 ]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-apl8/igt@gem_persistent_rel...@forked-thrashing.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-apl2/igt@gem_persistent_rel...@forked-thrashing.html * igt@gem_tiled_fence_blits@normal: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#110789] / [fdo#110913 ]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-snb2/igt@gem_tiled_fence_bl...@normal.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-snb6/igt@gem_tiled_fence_bl...@normal.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-apl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-b-64x64-bottom-edge: - shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-iclb8/igt@kms_cursor_edge_w...@pipe-b-64x64-bottom-edge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-iclb7/igt@kms_cursor_edge_w...@pipe-b-64x64-bottom-edge.html * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy: - shard-glk: [PASS][15] -> [INCOMPLETE][16] ([fdo#103359] / [k.org#198133]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-glk5/igt@kms_cursor_leg...@2x-cursor-vs-flip-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-glk3/igt@kms_cursor_leg...@2x-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][17] -> [FAIL][18] ([fdo#105767]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-hsw2/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#102670]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-skl9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-skl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset: - shard-hsw: [PASS][21] -> [SKIP][22] ([fdo#109271]) +13 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-hsw8/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-hsw1/igt@kms_f...@2x-flip-vs-dpms-off-vs-modeset.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-snb: [PASS][23] -> [INCOMPLETE][24] ([fdo#105411]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-snb1/igt@kms_f...@flip-vs-suspend-interruptible.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13384/shard-snb1/igt@kms_f...@flip-vs-suspend-interrup
