[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Report if i915_active is still busy upon waiting
== Series Details == Series: drm/i915: Report if i915_active is still busy upon waiting URL : https://patchwork.freedesktop.org/series/63062/ State : success == Summary == CI Bug Log - changes from CI_DRM_6394_full -> Patchwork_13487_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13487_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: [PASS][1] -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-kbl7/igt@i915_pm_rc6_reside...@rc6-accuracy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-kbl7/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-a: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb6/igt@kms_b...@extended-modeset-hang-oldfb-with-reset-render-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-iclb7/igt@kms_b...@extended-modeset-hang-oldfb-with-reset-render-a.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#103167]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [fdo#110403]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-skl4/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_psr@psr2_dpms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-iclb6/igt@kms_psr@psr2_dpms.html * igt@kms_vblank@pipe-c-wait-idle-hang: - shard-glk: [PASS][13] -> [INCOMPLETE][14] ([fdo#103359] / [k.org#198133]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk9/igt@kms_vbl...@pipe-c-wait-idle-hang.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-glk4/igt@kms_vbl...@pipe-c-wait-idle-hang.html Possible fixes * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][15] ([fdo#108686]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-glk2/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_selftest@mock_requests: - shard-glk: [INCOMPLETE][17] ([fdo#103359] / [k.org#198133]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk2/igt@i915_selftest@mock_requests.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-glk5/igt@i915_selftest@mock_requests.html * igt@kms_color@pipe-b-ctm-negative: - shard-skl: [FAIL][19] ([fdo#107361]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl3/igt@kms_co...@pipe-b-ctm-negative.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-skl3/igt@kms_co...@pipe-b-ctm-negative.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/shard-apl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-hsw: [FAIL][23] ([fdo#103355]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions.html [24]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Improve whitelist selftest for read-only registers
== Series Details ==
Series: Improve whitelist selftest for read-only registers
URL : https://patchwork.freedesktop.org/series/63102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6398 -> Patchwork_13499
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13499:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_chamelium@common-hpd-after-suspend:
- {fi-icl-u4}:[DMESG-WARN][1] ([fdo#102505]) -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u4/igt@kms_chamel...@common-hpd-after-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/fi-icl-u4/igt@kms_chamel...@common-hpd-after-suspend.html
Known issues
Here are the changes found in Patchwork_13499 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@vgem_basic@debugfs:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u3/igt@vgem_ba...@debugfs.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/fi-icl-u3/igt@vgem_ba...@debugfs.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-r: [DMESG-WARN][11] ([fdo#111012]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-kbl-r/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/fi-kbl-r/igt@i915_pm_...@module-reload.html
- fi-hsw-peppy: [DMESG-WARN][13] ([fdo#111012]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-hsw-peppy/igt@i915_pm_...@module-reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/fi-hsw-peppy/igt@i915_pm_...@module-reload.html
* igt@prime_vgem@basic-read:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u3/igt@prime_v...@basic-read.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/fi-icl-u3/igt@prime_v...@basic-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012
Participating hosts (55 -> 47)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6398 -> Patchwork_13499
CI_DRM_6398: 9b9df28dc0ec04a7fb1a020d869ef0ea14be4d14 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13499: 82ce470c711a50b727ab8c902ea66505f7dbdd41 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13499/build_32bit.log
CALLscripts/checksyscalls.sh
CALL
Re: [Intel-gfx] [PATCH] drm/i915: Implement read-only support in whitelist selftest
Patches sent.
I haven't made any changes to dmesg output as I'm not sure what you mean.
Ah, do you mean the debug print in wa_init_finish()? Sure, I can add the
engine name to that.
John.
On 6/25/2019 01:33, Tvrtko Ursulin wrote:
Ping.
We agreed to follow up with a test ASAP after merging.
Here's another feature request for you: Add engine->name logging to
wa_init_start in intel_engine_init_whitelist. Because with the change
to add whitelist on other engines there are now multiple identical
lines in dmesg.
To sum up that's three todo items:
1. Resend the selftest for CI.
2. Add GEM_BUG_ON for reg->flags checking invalid flag usage.
3. Improve dmesg so we know which engine got how many whitelist entries.
Thanks,
Tvrtko
On 20/06/2019 16:43, Tvrtko Ursulin wrote:
Hi,
You will need to send this not as reply to this thread so it is
picked up by CI and then can be merged.
But please also add a patch which adds that GEM_BUG_ON reg->flags
check we talked about.
Regards,
Tvrtko
On 18/06/2019 20:54, john.c.harri...@intel.com wrote:
From: John Harrison
Newer hardware supports extra feature in the whitelist registers. This
patch updates the selftest to test that entries marked as read only
are actually read only.
Also updated the read/write access definitions to make it clearer that
they are an enum field not a set of single bit flags.
Signed-off-by: John Harrison
CC: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +--
.../gpu/drm/i915/gt/selftest_workarounds.c | 53
+--
drivers/gpu/drm/i915/i915_reg.h | 9 ++--
3 files changed, 48 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 93caa7b6d7a9..4429ee08b20e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1028,7 +1028,7 @@ whitelist_reg_ext(struct i915_wa_list *wal,
i915_reg_t reg, u32 flags)
static void
whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
- whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);
+ whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
}
static void gen9_whitelist_build(struct i915_wa_list *w)
@@ -1134,13 +1134,13 @@ printk(KERN_INFO "%-32s:%4d> Boo! [engine =
%s, instance = %d, base = 0x%X, reg
/* hucStatusRegOffset */
whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
- RING_FORCE_TO_NONPRIV_RD);
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
/* hucUKernelHdrInfoRegOffset */
whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
- RING_FORCE_TO_NONPRIV_RD);
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
/* hucStatus2RegOffset */
whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
- RING_FORCE_TO_NONPRIV_RD);
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
break;
default:
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index eb6d3aa2c8cc..a0a88ec66861 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -399,6 +399,10 @@ static bool wo_register(struct intel_engine_cs
*engine, u32 reg)
enum intel_platform platform =
INTEL_INFO(engine->i915)->platform;
int i;
+ if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
+ RING_FORCE_TO_NONPRIV_ACCESS_WR)
+ return true;
+
for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
if (wo_registers[i].platform == platform &&
wo_registers[i].reg == reg)
@@ -410,7 +414,8 @@ static bool wo_register(struct intel_engine_cs
*engine, u32 reg)
static bool ro_register(u32 reg)
{
- if (reg & RING_FORCE_TO_NONPRIV_RD)
+ if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
+ RING_FORCE_TO_NONPRIV_ACCESS_RD)
return true;
return false;
@@ -482,12 +487,12 @@ static int check_dirty_whitelist(struct
i915_gem_context *ctx,
u32 srm, lrm, rsvd;
u32 expect;
int idx;
+ bool ro_reg;
if (wo_register(engine, reg))
continue;
- if (ro_register(reg))
- continue;
+ ro_reg = ro_register(reg);
srm = MI_STORE_REGISTER_MEM;
lrm = MI_LOAD_REGISTER_MEM;
@@ -588,24 +593,36 @@ static int check_dirty_whitelist(struct
i915_gem_context *ctx,
}
GEM_BUG_ON(values[ARRAY_SIZE(values) - 1] != 0x);
- rsvd = results[ARRAY_SIZE(values)]; /* detect write masking */
- if (!rsvd) {
- pr_err("%s: Unable to write to whitelisted register %x\n",
- engine->name, reg);
- err = -EINVAL;
- goto out_unpin;
+ if (ro_reg) {
+ rsvd = 0x;
+ } else {
+ rsvd =
[Intel-gfx] [PATCH 0/2] Improve whitelist selftest for read-only registers
From: John Harrison Follow up patch to earlier whitelist updates. This series adds some extra sanity checking to the driver and improves the self-test. John Harrison (2): drm/i915: Add test for invalid flag bits in whitelist entries drm/i915: Implement read-only support in whitelist selftest drivers/gpu/drm/i915/gt/intel_workarounds.c | 29 -- .../gpu/drm/i915/gt/selftest_workarounds.c| 57 +-- drivers/gpu/drm/i915/i915_reg.h | 12 +++- 3 files changed, 73 insertions(+), 25 deletions(-) -- 2.21.0.5.gaeb582a983 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Add test for invalid flag bits in whitelist entries
From: John Harrison
As per review feedback by Tvrtko, added a check that no invalid bits
are being set in the whitelist flags fields.
Also updated the read/write access definitions to make it clearer that
they are an enum field not a set of single bit flags.
Signed-off-by: John Harrison
CC: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 29 +++
.../gpu/drm/i915/gt/selftest_workarounds.c| 14 ++---
drivers/gpu/drm/i915/i915_reg.h | 12 ++--
3 files changed, 42 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a908d829d6bd..9b401833aceb 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1011,6 +1011,20 @@ bool intel_gt_verify_workarounds(struct intel_gt *gt,
const char *from)
return wa_list_verify(gt->uncore, >i915->gt_wa_list, from);
}
+static inline bool is_nonpriv_flags_valid(u32 flags)
+{
+ /* Check only valid flag bits are set */
+ if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
+ return false;
+
+ /* NB: Only 3 out of 4 enum values are valid for access field */
+ if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
+ RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
+ return false;
+
+ return true;
+}
+
static void
whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
{
@@ -1021,6 +1035,9 @@ whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t
reg, u32 flags)
if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
return;
+ if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
+ return;
+
wa.reg.reg |= flags;
_wa_add(wal, );
}
@@ -1028,7 +1045,7 @@ whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t
reg, u32 flags)
static void
whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
- whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);
+ whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
}
static void gen9_whitelist_build(struct i915_wa_list *w)
@@ -1109,7 +1126,7 @@ static void cfl_whitelist_build(struct intel_engine_cs
*engine)
* - PS_DEPTH_COUNT_UDW
*/
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
- RING_FORCE_TO_NONPRIV_RD |
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
RING_FORCE_TO_NONPRIV_RANGE_4);
}
@@ -1149,20 +1166,20 @@ static void icl_whitelist_build(struct intel_engine_cs
*engine)
* - PS_DEPTH_COUNT_UDW
*/
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
- RING_FORCE_TO_NONPRIV_RD |
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
RING_FORCE_TO_NONPRIV_RANGE_4);
break;
case VIDEO_DECODE_CLASS:
/* hucStatusRegOffset */
whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
- RING_FORCE_TO_NONPRIV_RD);
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
/* hucUKernelHdrInfoRegOffset */
whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
- RING_FORCE_TO_NONPRIV_RD);
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
/* hucStatus2RegOffset */
whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
- RING_FORCE_TO_NONPRIV_RD);
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
break;
default:
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index b933d831eeb1..f8151d5946c8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -394,6 +394,10 @@ static bool wo_register(struct intel_engine_cs *engine,
u32 reg)
enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
int i;
+ if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
+RING_FORCE_TO_NONPRIV_ACCESS_WR)
+ return true;
+
for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
if (wo_registers[i].platform == platform &&
wo_registers[i].reg == reg)
@@ -405,7 +409,8 @@ static bool wo_register(struct intel_engine_cs *engine, u32
reg)
static bool ro_register(u32 reg)
{
- if (reg & RING_FORCE_TO_NONPRIV_RD)
+ if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
+RING_FORCE_TO_NONPRIV_ACCESS_RD)
return true;
return false;
@@ -757,8 +762,8 @@ static int read_whitelisted_registers(struct
i915_gem_context *ctx,
u64 offset = results->node.start +
[Intel-gfx] [PATCH 2/2] drm/i915: Implement read-only support in whitelist selftest
From: John Harrison
Newer hardware supports extra feature in the whitelist registers. This
patch updates the selftest to test that entries marked as read only
are actually read only.
Signed-off-by: John Harrison
CC: Tvrtko Ursulin
---
.../gpu/drm/i915/gt/selftest_workarounds.c| 43 +--
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index f8151d5946c8..5cd2b17105ba 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -482,12 +482,12 @@ static int check_dirty_whitelist(struct i915_gem_context
*ctx,
u32 srm, lrm, rsvd;
u32 expect;
int idx;
+ bool ro_reg;
if (wo_register(engine, reg))
continue;
- if (ro_register(reg))
- continue;
+ ro_reg = ro_register(reg);
srm = MI_STORE_REGISTER_MEM;
lrm = MI_LOAD_REGISTER_MEM;
@@ -588,24 +588,37 @@ static int check_dirty_whitelist(struct i915_gem_context
*ctx,
}
GEM_BUG_ON(values[ARRAY_SIZE(values) - 1] != 0x);
- rsvd = results[ARRAY_SIZE(values)]; /* detect write masking */
- if (!rsvd) {
- pr_err("%s: Unable to write to whitelisted register
%x\n",
- engine->name, reg);
- err = -EINVAL;
- goto out_unpin;
+ if (ro_reg) {
+ rsvd = 0x;
+ } else {
+ /* detect write masking */
+ rsvd = results[ARRAY_SIZE(values)];
+ if (!rsvd) {
+ pr_err("%s: Unable to write to whitelisted
register %x\n",
+ engine->name, reg);
+ err = -EINVAL;
+ goto out_unpin;
+ }
}
expect = results[0];
idx = 1;
for (v = 0; v < ARRAY_SIZE(values); v++) {
- expect = reg_write(expect, values[v], rsvd);
+ if (ro_reg)
+ expect = results[0];
+ else
+ expect = reg_write(expect, values[v], rsvd);
+
if (results[idx] != expect)
err++;
idx++;
}
for (v = 0; v < ARRAY_SIZE(values); v++) {
- expect = reg_write(expect, ~values[v], rsvd);
+ if (ro_reg)
+ expect = results[0];
+ else
+ expect = reg_write(expect, ~values[v], rsvd);
+
if (results[idx] != expect)
err++;
idx++;
@@ -622,7 +635,10 @@ static int check_dirty_whitelist(struct i915_gem_context
*ctx,
for (v = 0; v < ARRAY_SIZE(values); v++) {
u32 w = values[v];
- expect = reg_write(expect, w, rsvd);
+ if (ro_reg)
+ expect = results[0];
+ else
+ expect = reg_write(expect, w, rsvd);
pr_info("Wrote %08x, read %08x, expect %08x\n",
w, results[idx], expect);
idx++;
@@ -630,7 +646,10 @@ static int check_dirty_whitelist(struct i915_gem_context
*ctx,
for (v = 0; v < ARRAY_SIZE(values); v++) {
u32 w = ~values[v];
- expect = reg_write(expect, w, rsvd);
+ if (ro_reg)
+ expect = results[0];
+ else
+ expect = reg_write(expect, w, rsvd);
pr_info("Wrote %08x, read %08x, expect %08x\n",
w, results[idx], expect);
idx++;
--
2.21.0.5.gaeb582a983
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for Support mipi dsi video mode on TGL
== Series Details == Series: Support mipi dsi video mode on TGL URL : https://patchwork.freedesktop.org/series/63058/ State : success == Summary == CI Bug Log - changes from CI_DRM_6394_full -> Patchwork_13486_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13486_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_swapping@non-threaded: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-kbl1/igt@gem_tiled_swapp...@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-kbl2/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl2/igt@i915_susp...@fence-restore-tiled2untiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@i915_suspend@forcewake: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#103313]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-kbl4/igt@i915_susp...@forcewake.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-kbl3/igt@i915_susp...@forcewake.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_f...@flip-vs-expired-vblank.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl9/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_frontbuffer_track...@fbc-tilingchange.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb1/igt@kms_frontbuffer_track...@fbc-tilingchange.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_psr@psr2_dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb5/igt@kms_psr@psr2_dpms.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#104108]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl5/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl1/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html * igt@perf@blocking: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl2/igt@p...@blocking.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl7/igt@p...@blocking.html Possible fixes * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][21] ([fdo#110854]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb5/igt@gem_exec_balan...@smoke.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb2/igt@gem_exec_balan...@smoke.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][23] ([fdo#108686]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-glk7/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_selftest@mock_requests: - shard-glk: [INCOMPLETE][25] ([fdo#103359] / [k.org#198133]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk2/igt@i915_selftest@mock_requests.html [26]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Remove preemption support for current fw (rev2)
== Series Details == Series: drm/i915/guc: Remove preemption support for current fw (rev2) URL : https://patchwork.freedesktop.org/series/56767/ State : success == Summary == CI Bug Log - changes from CI_DRM_6394_full -> Patchwork_13485_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13485_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#110741]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-skl9/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@cursor-vs-flip-legacy: - shard-hsw: [PASS][3] -> [FAIL][4] ([fdo#103355]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-hsw7/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][5] -> [FAIL][6] ([fdo#105363]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk7/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-glk4/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-iclb6/igt@kms_psr@psr2_primary_mmap_gtt.html Possible fixes * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][17] ([fdo#108686]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-glk3/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_selftest@mock_requests: - shard-glk: [INCOMPLETE][19] ([fdo#103359] / [k.org#198133]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk2/igt@i915_selftest@mock_requests.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-glk2/igt@i915_selftest@mock_requests.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13485/shard-apl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-hsw: [FAIL][23] ([fdo#103355]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions.html
Re: [Intel-gfx] [RFC 6/7] drm/i915: Try to make bigjoiner work in atomic check.
On Tue, Jul 02, 2019 at 09:42:04PM +0200, Maarten Lankhorst wrote:
> When the clock is higher than the dotclock, try with 2 pipes enabled.
> If we can enable 2, then we will go into big joiner mode, and steal
> the adjacent crtc.
>
> This only links the planes in software, no hardware programming is
> done yet.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 145 ++-
> drivers/gpu/drm/i915/display/intel_dp.c | 22 ++-
> drivers/gpu/drm/i915/intel_drv.h | 6 +
> 3 files changed, 168 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d8e63f133a62..ca72058202f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12203,6 +12203,47 @@ static void copy_hw_to_uapi_state(struct
> intel_crtc_state *crtc_state)
> crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
> }
>
> +static int
> +copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
> + const struct intel_crtc_state *from_crtc_state)
> +{
> + struct intel_crtc_state *saved_state;
> +
> + saved_state = kmemdup(from_crtc_state, sizeof(*saved_state),
> GFP_KERNEL);
> + if (!saved_state)
> + return -ENOMEM;
> +
> + saved_state->uapi = crtc_state->uapi;
> + saved_state->scaler_state = crtc_state->scaler_state;
> + saved_state->shared_dpll = crtc_state->shared_dpll;
> + saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> + saved_state->crc_enabled = crtc_state->crc_enabled;
> +
> + intel_crtc_free_hw_state(crtc_state);
> + memcpy(crtc_state, saved_state, sizeof(*crtc_state));
> + kfree(saved_state);
> +
> + /* Re-init hw state */
> + memset(_state->hw, 0, sizeof(saved_state->hw));
> + crtc_state->hw.enable = from_crtc_state->hw.enable;
> + crtc_state->hw.active = from_crtc_state->hw.active;
> + crtc_state->hw.mode = from_crtc_state->hw.mode;
> + crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
> +
> + /* Some fixups */
> + crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
> + crtc_state->uapi.connectors_changed =
> from_crtc_state->uapi.connectors_changed;
> + crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
> + crtc_state->nv12_planes = crtc_state->c8_planes =
> crtc_state->update_planes = 0;
> +
> + crtc_state->bigjoiner_master_crtc =
> to_intel_crtc(from_crtc_state->uapi.crtc);
> +
> + /* XXX/TODO: Do we need the master's cpu_transcoder here, or reset to
> default? */
> + crtc_state->cpu_transcoder = (enum
> transcoder)to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +
> + return 0;
> +}
> +
> static int
> clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
> {
> @@ -13577,6 +13618,96 @@ static void intel_crtc_check_fastset(const struct
> intel_crtc_state *old_crtc_sta
> new_crtc_state->has_drrs = old_crtc_state->has_drrs;
> }
>
> +static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *old_crtc_state, *new_crtc_state,
> *slave_crtc_state, *master_crtc_state;
> + struct intel_crtc *crtc, *slave, *master;
> + int i, ret = 0;
> +
> + if (INTEL_GEN(dev_priv) < 11)
> + return 0;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + if (!old_crtc_state->bigjoiner_master_crtc)
> + continue;
> +
> + if (crtc->pipe == PIPE_A) {
> + DRM_ERROR("Bigjoiner slave on pipe A?\n");
> + return -EINVAL;
> + }
> +
> + /* crtc staying in slave mode? */
> + if (!new_crtc_state->uapi.enable)
> + continue;
> +
> + if (needs_modeset(new_crtc_state) ||
> new_crtc_state->update_pipe) {
> + master = intel_get_crtc_for_pipe(dev_priv, crtc->pipe -
> 1);
> + master_crtc_state =
> intel_atomic_get_crtc_state(>base, master);
> + if (IS_ERR(master_crtc_state))
> + return PTR_ERR(master_crtc_state);
> +
> + /*
> + * Force modeset on master, to recalculate bigjoiner
> + * state.
> + *
> + * If master_crtc_state was not part of the atomic
> commit,
> + * we will fail because the master was not deconfigured,
> + * but at least fail below to unify the checks.
> + */
> + master_crtc_state->uapi.mode_changed = true;
> +
> +
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Free pages before rcu-freeing the object (rev2)
== Series Details == Series: drm/i915/gem: Free pages before rcu-freeing the object (rev2) URL : https://patchwork.freedesktop.org/series/63042/ State : success == Summary == CI Bug Log - changes from CI_DRM_6394_full -> Patchwork_13484_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13484_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl3/igt@gem_tiled_swapp...@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-apl6/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl2/igt@i915_susp...@fence-restore-tiled2untiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][5] -> [FAIL][6] ([fdo#104873]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk5/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-glk9/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-glk9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-iclb5/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_psr@psr2_dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-iclb8/igt@kms_psr@psr2_dpms.html * igt@perf@oa-formats: - shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([fdo#103540] / [fdo#108767]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-hsw4/igt@p...@oa-formats.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-hsw2/igt@p...@oa-formats.html Possible fixes * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][19] ([fdo#108686]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-glk1/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_selftest@mock_requests: - shard-glk: [INCOMPLETE][21] ([fdo#103359] / [k.org#198133]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk2/igt@i915_selftest@mock_requests.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-glk1/igt@i915_selftest@mock_requests.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13484/shard-apl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html *
Re: [Intel-gfx] [RFC 4/7] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid()
On Tue, Jul 02, 2019 at 09:42:02PM +0200, Maarten Lankhorst wrote: > Signed-off-by: Maarten Lankhorst > --- > drivers/gpu/drm/i915/display/intel_dp.c | 10 -- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index d5c56ea079a4..b41ff88d3258 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -506,6 +506,7 @@ intel_dp_mode_valid(struct drm_connector *connector, > int max_dotclk; > u16 dsc_max_output_bpp = 0; > u8 dsc_slice_count = 0; > + bool dsc; > > if (mode->flags & DRM_MODE_FLAG_DBLSCAN) > return MODE_NO_DBLESCAN; > @@ -553,8 +554,13 @@ intel_dp_mode_valid(struct drm_connector *connector, > } > } > > - if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) > || > - target_clock > max_dotclk) > + dsc = dsc_max_output_bpp && dsc_slice_count; > + > + /* Gen11 has big joiner for handling this */ > + if (dsc && dsc_slice_count >= 2 && INTEL_GEN(dev_priv) >= 11) > + max_dotclk *= 2; This should be dsc_slice_Count >=4 since big joiner cannot be enabled if small joiner is not enabled and small joiner cannot be enabled for slice count < 2 Manasi > + > + if ((mode_rate > max_rate && !dsc) || target_clock > max_dotclk) > return MODE_CLOCK_HIGH; > > if (mode->clock < 1) > -- > 2.20.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 1/4] drm/panel: Add helper for reading DT rotation
This adds a helper function for reading the rotation (panel
orientation) from the device tree.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/drm_panel.c | 43 +
include/drm/drm_panel.h | 7 ++
2 files changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index dbd5b873e8f2..169bab54d52d 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -172,6 +172,49 @@ struct drm_panel *of_drm_find_panel(const struct
device_node *np)
return ERR_PTR(-EPROBE_DEFER);
}
EXPORT_SYMBOL(of_drm_find_panel);
+
+/**
+ * of_drm_get_panel_orientation - look up the orientation of the panel through
+ * the "rotation" binding from a device tree node
+ * @np: device tree node of the panel
+ * @orientation: orientation enum to be filled in
+ *
+ * Looks up the rotation of a panel in the device tree. The orientation of the
+ * panel is expressed as a property name "rotation" in the device tree. The
+ * rotation in the device tree is counter clockwise.
+ *
+ * Return: 0 when a valid rotation value (0, 90, 180, or 270) is read or the
+ * rotation property doesn't exist. -EERROR otherwise.
+ */
+int of_drm_get_panel_orientation(const struct device_node *np,
+enum drm_panel_orientation *orientation)
+{
+ int rotation, ret;
+
+ ret = of_property_read_u32(np, "rotation", );
+ if (ret == -EINVAL) {
+ /* Don't return an error if there's no rotation property. */
+ *orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+ return 0;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ if (rotation == 0)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
+ else if (rotation == 90)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
+ else if (rotation == 180)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
+ else if (rotation == 270)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
+ else
+ return -EINVAL;
+
+ return 0;
+}
+EXPORT_SYMBOL(of_drm_get_panel_orientation);
#endif
MODULE_AUTHOR("Thierry Reding ");
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 8c738c0e6e9f..3564952f1a4f 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -197,11 +197,18 @@ int drm_panel_detach(struct drm_panel *panel);
#if defined(CONFIG_OF) && defined(CONFIG_DRM_PANEL)
struct drm_panel *of_drm_find_panel(const struct device_node *np);
+int of_drm_get_panel_orientation(const struct device_node *np,
+enum drm_panel_orientation *orientation);
#else
static inline struct drm_panel *of_drm_find_panel(const struct device_node *np)
{
return ERR_PTR(-ENODEV);
}
+int of_drm_get_panel_orientation(const struct device_node *np,
+enum drm_panel_orientation *orientation)
+{
+ return -ENODEV;
+}
#endif
#endif
--
2.22.0.410.gd8fdbe21b5-goog
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[Intel-gfx] [PATCH v4 4/4] drm/mtk: add panel orientation property
This inits the panel orientation property for the mediatek dsi driver
if the panel orientation (connector.display_info.panel_orientation) is
not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 4a0b9150a7bb..08ffdc7526dd 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -782,10 +782,18 @@ static int mtk_dsi_create_connector(struct drm_device
*drm, struct mtk_dsi *dsi)
DRM_ERROR("Failed to attach panel to drm\n");
goto err_connector_cleanup;
}
+
+ ret = drm_connector_init_panel_orientation_property(>conn);
+ if (ret) {
+ DRM_ERROR("Failed to init panel orientation\n");
+ goto err_panel_detach;
+ }
}
return 0;
+err_panel_detach:
+ drm_panel_detach(dsi->panel);
err_connector_cleanup:
drm_connector_cleanup(>conn);
return ret;
--
2.22.0.410.gd8fdbe21b5-goog
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[Intel-gfx] [PATCH v4 0/4] Panel rotation patches
This adds the plumbing for reading panel rotation from the devicetree and sets up adding a panel property for the panel orientation on Mediatek SoCs when a rotation is present. v4 changes: -fixed some changes made to the i915 driver -clarified comments on of orientation helper v3 changes: -changed from attach/detach callbacks to directly setting fixed panel values in drm_panel_attach -removed update to Documentation -added separate function for quirked panel orientation property init v2 changes: fixed build errors in i915 Derek Basehore (4): drm/panel: Add helper for reading DT rotation drm/panel: set display info in panel attach drm/connector: Split out orientation quirk detection drm/mtk: add panel orientation property drivers/gpu/drm/drm_connector.c| 45 ++- drivers/gpu/drm/drm_panel.c| 70 ++ drivers/gpu/drm/i915/intel_dp.c| 4 +- drivers/gpu/drm/i915/vlv_dsi.c | 5 +-- drivers/gpu/drm/mediatek/mtk_dsi.c | 8 include/drm/drm_connector.h| 2 + include/drm/drm_panel.h| 21 + 7 files changed, 138 insertions(+), 17 deletions(-) -- 2.22.0.410.gd8fdbe21b5-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 3/4] drm/connector: Split out orientation quirk detection
Not every platform needs quirk detection for panel orientation, so
split the drm_connector_init_panel_orientation_property into two
functions. One for platforms without the need for quirks, and the
other for platforms that need quirks.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/drm_connector.c | 45 -
drivers/gpu/drm/i915/intel_dp.c | 4 +--
drivers/gpu/drm/i915/vlv_dsi.c | 2 +-
include/drm/drm_connector.h | 2 ++
4 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index e17586aaa80f..c4b01adf927a 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1894,31 +1894,23 @@ EXPORT_SYMBOL(drm_connector_set_vrr_capable_property);
* drm_connector_init_panel_orientation_property -
* initialize the connecters panel_orientation property
* @connector: connector for which to init the panel-orientation property.
- * @width: width in pixels of the panel, used for panel quirk detection
- * @height: height in pixels of the panel, used for panel quirk detection
*
* This function should only be called for built-in panels, after setting
* connector->display_info.panel_orientation first (if known).
*
- * This function will check for platform specific (e.g. DMI based) quirks
- * overriding display_info.panel_orientation first, then if panel_orientation
- * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the
- * "panel orientation" property to the connector.
+ * This function will check if the panel_orientation is not
+ * DRM_MODE_PANEL_ORIENTATION_UNKNOWN. If not, it will attach the "panel
+ * orientation" property to the connector.
*
* Returns:
* Zero on success, negative errno on failure.
*/
int drm_connector_init_panel_orientation_property(
- struct drm_connector *connector, int width, int height)
+ struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
struct drm_display_info *info = >display_info;
struct drm_property *prop;
- int orientation_quirk;
-
- orientation_quirk = drm_get_panel_orientation_quirk(width, height);
- if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
- info->panel_orientation = orientation_quirk;
if (info->panel_orientation == DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
return 0;
@@ -1941,6 +1933,35 @@ int drm_connector_init_panel_orientation_property(
}
EXPORT_SYMBOL(drm_connector_init_panel_orientation_property);
+/**
+ * drm_connector_init_panel_orientation_property_quirk -
+ * initialize the connecters panel_orientation property with a quirk
+ * override
+ * @connector: connector for which to init the panel-orientation property.
+ * @width: width in pixels of the panel, used for panel quirk detection
+ * @height: height in pixels of the panel, used for panel quirk detection
+ *
+ * This function will check for platform specific (e.g. DMI based) quirks
+ * overriding display_info.panel_orientation first, then if panel_orientation
+ * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the
+ * "panel orientation" property to the connector.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_init_panel_orientation_property_quirk(
+ struct drm_connector *connector, int width, int height)
+{
+ int orientation_quirk;
+
+ orientation_quirk = drm_get_panel_orientation_quirk(width, height);
+ if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
+ connector->display_info.panel_orientation = orientation_quirk;
+
+ return drm_connector_init_panel_orientation_property(connector);
+}
+EXPORT_SYMBOL(drm_connector_init_panel_orientation_property_quirk);
+
int drm_connector_set_obj_prop(struct drm_mode_object *obj,
struct drm_property *property,
uint64_t value)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b099a9dc28fd..7d4e61cf5463 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -7282,8 +7282,8 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
intel_panel_setup_backlight(connector, pipe);
if (fixed_mode)
- drm_connector_init_panel_orientation_property(
- connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
+ drm_connector_init_panel_orientation_property_quirk(connector,
+ fixed_mode->hdisplay, fixed_mode->vdisplay);
return true;
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index bfe2891eac37..aca99ece045e 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -1662,7 +1662,7 @@ static void intel_dsi_add_properties(struct
intel_connector *connector)
[Intel-gfx] [PATCH v4 2/4] drm/panel: set display info in panel attach
Devicetree systems can set panel orientation via a panel binding, but
there's no way, as is, to propagate this setting to the connector,
where the property need to be added.
To address this, this patch sets orientation, as well as other fixed
values for the panel, in the drm_panel_attach function. These values
are stored from probe in the drm_panel struct.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/drm_panel.c | 28
include/drm/drm_panel.h | 14 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index 169bab54d52d..ca01095470a9 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -104,11 +104,23 @@ EXPORT_SYMBOL(drm_panel_remove);
*/
int drm_panel_attach(struct drm_panel *panel, struct drm_connector *connector)
{
+ struct drm_display_info *info;
+
if (panel->connector)
return -EBUSY;
panel->connector = connector;
panel->drm = connector->dev;
+ info = >display_info;
+ info->width_mm = panel->width_mm;
+ info->height_mm = panel->height_mm;
+ info->bpc = panel->bpc;
+ info->panel_orientation = panel->orientation;
+ info->bus_flags = panel->bus_flags;
+ if (panel->bus_formats)
+ drm_display_info_set_bus_formats(>display_info,
+panel->bus_formats,
+panel->num_bus_formats);
return 0;
}
@@ -128,6 +140,22 @@ EXPORT_SYMBOL(drm_panel_attach);
*/
int drm_panel_detach(struct drm_panel *panel)
{
+ struct drm_display_info *info;
+
+ if (!panel->connector)
+ goto out;
+
+ info = >connector->display_info;
+ info->width_mm = 0;
+ info->height_mm = 0;
+ info->bpc = 0;
+ info->panel_orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+ info->bus_flags = 0;
+ kfree(info->bus_formats);
+ info->bus_formats = NULL;
+ info->num_bus_formats = 0;
+
+out:
panel->connector = NULL;
panel->drm = NULL;
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 3564952f1a4f..760ca5865962 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -37,6 +37,8 @@ struct display_timing;
* struct drm_panel_funcs - perform operations on a given panel
* @disable: disable panel (turn off back light, etc.)
* @unprepare: turn off panel
+ * @detach: detach panel->connector (clear internal state, etc.)
+ * @attach: attach panel->connector (update internal state, etc.)
* @prepare: turn on panel and perform set up
* @enable: enable panel (turn on back light, etc.)
* @get_modes: add modes to the connector that the panel is attached to and
@@ -93,6 +95,18 @@ struct drm_panel {
const struct drm_panel_funcs *funcs;
+ /*
+* panel information to be set in the connector when the panel is
+* attached.
+*/
+ unsigned int width_mm;
+ unsigned int height_mm;
+ unsigned int bpc;
+ int orientation;
+ const u32 *bus_formats;
+ unsigned int num_bus_formats;
+ u32 bus_flags;
+
struct list_head list;
};
--
2.22.0.410.gd8fdbe21b5-goog
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Common live setup/teardown
== Series Details == Series: drm/i915/selftests: Common live setup/teardown URL : https://patchwork.freedesktop.org/series/63099/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6398 -> Patchwork_13498 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13498 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13498, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13498: ### IGT changes ### Possible regressions * igt@i915_selftest@live_contexts: - fi-skl-iommu: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-skl-iommu/igt@i915_selftest@live_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-skl-iommu/igt@i915_selftest@live_contexts.html * igt@runner@aborted: - fi-bdw-gvtdvm: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-bdw-gvtdvm/igt@run...@aborted.html - fi-cml-u: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-cml-u/igt@run...@aborted.html Warnings * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: [INCOMPLETE][5] ([fdo#110976]) -> [TIMEOUT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html Known issues Here are the changes found in Patchwork_13498 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-blb-e6850: [PASS][7] -> [INCOMPLETE][8] ([fdo#107718]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-blb-e6850/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@module-reload: - fi-cml-u: [PASS][9] -> [DMESG-WARN][10] ([fdo#111012]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-cml-u/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-cml-u/igt@i915_pm_...@module-reload.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][11] -> [DMESG-WARN][12] ([fdo#102614]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html - fi-icl-u2: [PASS][13] -> [FAIL][14] ([fdo#103167]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html * igt@vgem_basic@unload: - fi-icl-u3: [PASS][15] -> [DMESG-WARN][16] ([fdo#107724]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u3/igt@vgem_ba...@unload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-icl-u3/igt@vgem_ba...@unload.html Possible fixes * igt@gem_ctx_create@basic-files: - fi-icl-dsi: [INCOMPLETE][17] ([fdo#107713] / [fdo#109100]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html * igt@i915_pm_rpm@module-reload: - fi-kbl-r: [DMESG-WARN][19] ([fdo#111012]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-kbl-r/igt@i915_pm_...@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-kbl-r/igt@i915_pm_...@module-reload.html - fi-hsw-peppy: [DMESG-WARN][21] ([fdo#111012]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-hsw-peppy/igt@i915_pm_...@module-reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-hsw-peppy/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: [INCOMPLETE][23] ([fdo#110976]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13498/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/guc: Remove preemption support for current fw
== Series Details == Series: series starting with [1/3] drm/i915/guc: Remove preemption support for current fw URL : https://patchwork.freedesktop.org/series/63095/ State : success == Summary == CI Bug Log - changes from CI_DRM_6398 -> Patchwork_13497 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/ Known issues Here are the changes found in Patchwork_13497 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_evict: - fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([fdo#105411]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-snb-2600/igt@i915_selftest@live_evict.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/fi-snb-2600/igt@i915_selftest@live_evict.html * igt@i915_selftest@live_hangcheck: - fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u2/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/fi-icl-u2/igt@i915_selftest@live_hangcheck.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_ctx_create@basic-files: - fi-icl-dsi: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html * igt@i915_pm_rpm@module-reload: - fi-kbl-r: [DMESG-WARN][9] ([fdo#111012]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-kbl-r/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/fi-kbl-r/igt@i915_pm_...@module-reload.html - fi-hsw-peppy: [DMESG-WARN][11] ([fdo#111012]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-hsw-peppy/igt@i915_pm_...@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/fi-hsw-peppy/igt@i915_pm_...@module-reload.html * igt@prime_vgem@basic-read: - fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u3/igt@prime_v...@basic-read.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/fi-icl-u3/igt@prime_v...@basic-read.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 Participating hosts (55 -> 46) -- Missing(9): fi-kbl-soraka fi-ilk-m540 fi-skl-gvtdvm fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6398 -> Patchwork_13497 CI_DRM_6398: 9b9df28dc0ec04a7fb1a020d869ef0ea14be4d14 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13497: 547860d7ee4f3d1bc1460defcc932cf08755fee6 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 547860d7ee4f drm/i915/uc: replace uc init/fini misc 877471f86b10 drm/i915/guc: simplify guc client 627e2de437dc drm/i915/guc: Remove preemption support for current fw == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13497/ ___ Intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Common live setup/teardown
== Series Details ==
Series: drm/i915/selftests: Common live setup/teardown
URL : https://patchwork.freedesktop.org/series/63099/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5f846dba1d19 drm/i915/selftests: Common live setup/teardown
-:239: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'T' - possible side-effects?
#239: FILE: drivers/gpu/drm/i915/i915_selftest.h:85:
+#define i915_live_subtests(T, data) ({ \
+ typecheck(struct drm_i915_private *, data); \
+ __i915_subtests(__func__, \
+ __i915_live_setup, __i915_live_teardown, \
+ T, ARRAY_SIZE(T), data); \
+})
total: 0 errors, 0 warnings, 1 checks, 273 lines checked
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()
== Series Details == Series: drm/i915: Use the "display core" power domain in vlv/chv set_cdclk() URL : https://patchwork.freedesktop.org/series/63045/ State : success == Summary == CI Bug Log - changes from CI_DRM_6394_full -> Patchwork_13483_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13483_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-pci-d3-state: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#103558] / [fdo#105602]) +8 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-kbl4/igt@i915_pm_...@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-kbl2/igt@i915_pm_...@basic-pci-d3-state.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-apl5/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_flip@flip-vs-dpms-off-vs-modeset: - shard-kbl: [PASS][5] -> [DMESG-FAIL][6] ([fdo#103558] / [fdo#105602]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-kbl4/igt@kms_f...@flip-vs-dpms-off-vs-modeset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-kbl2/igt@kms_f...@flip-vs-dpms-off-vs-modeset.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_f...@flip-vs-expired-vblank.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip_tiling@flip-to-x-tiled: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#108134]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb8/igt@kms_flip_til...@flip-to-x-tiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-iclb4/igt@kms_flip_til...@flip-to-x-tiled.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-spr-indfb-draw-render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-spr-indfb-draw-render.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-x.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_psr@psr2_dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-iclb3/igt@kms_psr@psr2_dpms.html * igt@perf@oa-exponents: - shard-glk: [PASS][17] -> [FAIL][18] ([fdo#105483]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk3/igt@p...@oa-exponents.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-glk8/igt@p...@oa-exponents.html Possible fixes * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][19] ([fdo#108686]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-glk3/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_selftest@mock_requests: - shard-glk: [INCOMPLETE][21] ([fdo#103359] / [k.org#198133]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk2/igt@i915_selftest@mock_requests.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-glk6/igt@i915_selftest@mock_requests.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-hsw: [FAIL][23] ([fdo#103355]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13483/shard-hsw8/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/guc: Remove preemption support for current fw
== Series Details == Series: series starting with [1/3] drm/i915/guc: Remove preemption support for current fw URL : https://patchwork.freedesktop.org/series/63095/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/guc: Remove preemption support for current fw -./drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) Commit: drm/i915/guc: simplify guc client Okay! Commit: drm/i915/uc: replace uc init/fini misc Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Bigjoiner atomic preparations.
== Series Details ==
Series: Bigjoiner atomic preparations.
URL : https://patchwork.freedesktop.org/series/63094/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6398 -> Patchwork_13496
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13496/
Known issues
Here are the changes found in Patchwork_13496 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13496/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-write-gtt:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13496/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13496/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13496/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-r: [DMESG-WARN][9] ([fdo#111012]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-kbl-r/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13496/fi-kbl-r/igt@i915_pm_...@module-reload.html
- fi-hsw-peppy: [DMESG-WARN][11] ([fdo#111012]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-hsw-peppy/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13496/fi-hsw-peppy/igt@i915_pm_...@module-reload.html
* igt@prime_vgem@basic-read:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u3/igt@prime_v...@basic-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13496/fi-icl-u3/igt@prime_v...@basic-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012
Participating hosts (55 -> 46)
--
Missing(9): fi-kbl-soraka fi-icl-u4 fi-ilk-m540 fi-hsw-4200u
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6398 -> Patchwork_13496
CI_DRM_6398: 9b9df28dc0ec04a7fb1a020d869ef0ea14be4d14 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13496: f41590956879419271312edbffbbceb613d49e7d @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13496/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
f41590956879 drm/i915: Allow vdsc functions to be called without encoder.
deb270f134b8 drm/i915: Try to make bigjoiner work in atomic check.
1909a2665a65 drm/i915/dp: Validate modes that can only be handled in a
bigjoiner configuration
9516b4dffdfa drm/i915/dp: Allow big joiner modes
[Intel-gfx] [PATCH] drm/i915/selftests: Common live setup/teardown
We frequently, and not frequently enough, remember to flush residual
openations and objects at the end of a live subtest. The purpose is to
cleanup after every subtest, leaving a clean slate for the next subtest,
and perform early detection of leaky state.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
.../i915/gem/selftests/i915_gem_client_blt.c | 11 ++---
.../drm/i915/gem/selftests/i915_gem_context.c | 2 +-
.../i915/gem/selftests/i915_gem_object_blt.c | 11 ++---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 16 +--
drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 +-
drivers/gpu/drm/i915/i915_selftest.h | 18 +++-
drivers/gpu/drm/i915/selftests/i915_gem.c | 6 +--
.../gpu/drm/i915/selftests/i915_selftest.c| 44 ++-
9 files changed, 71 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 855481252bda..fa79233093eb 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -11,8 +11,8 @@
static int igt_client_fill(void *arg)
{
- struct intel_context *ce = arg;
- struct drm_i915_private *i915 = ce->gem_context->i915;
+ struct drm_i915_private *i915 = arg;
+ struct intel_context *ce = i915->engine[BCS0]->kernel_context;
struct drm_i915_gem_object *obj;
struct rnd_state prng;
IGT_TIMEOUT(end);
@@ -89,11 +89,6 @@ static int igt_client_fill(void *arg)
err_put:
i915_gem_object_put(obj);
err_flush:
- mutex_lock(>drm.struct_mutex);
- if (igt_flush_test(i915, I915_WAIT_LOCKED))
- err = -EIO;
- mutex_unlock(>drm.struct_mutex);
-
if (err == -ENOMEM)
err = 0;
@@ -112,5 +107,5 @@ int i915_gem_client_blt_live_selftests(struct
drm_i915_private *i915)
if (!HAS_ENGINE(i915, BCS0))
return 0;
- return i915_subtests(tests, i915->engine[BCS0]->kernel_context);
+ return i915_live_subtests(tests, i915);
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 53c81b5dfd69..a23c6df9b9f4 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1731,5 +1731,5 @@ int i915_gem_context_live_selftests(struct
drm_i915_private *dev_priv)
if (i915_terminally_wedged(dev_priv))
return 0;
- return i915_subtests(tests, dev_priv);
+ return i915_live_subtests(tests, dev_priv);
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index e23d8c9e9298..11d37238c62c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -11,8 +11,8 @@
static int igt_fill_blt(void *arg)
{
- struct intel_context *ce = arg;
- struct drm_i915_private *i915 = ce->gem_context->i915;
+ struct drm_i915_private *i915 = arg;
+ struct intel_context *ce = i915->engine[BCS0]->kernel_context;
struct drm_i915_gem_object *obj;
struct rnd_state prng;
IGT_TIMEOUT(end);
@@ -83,11 +83,6 @@ static int igt_fill_blt(void *arg)
err_put:
i915_gem_object_put(obj);
err_flush:
- mutex_lock(>drm.struct_mutex);
- if (igt_flush_test(i915, I915_WAIT_LOCKED))
- err = -EIO;
- mutex_unlock(>drm.struct_mutex);
-
if (err == -ENOMEM)
err = 0;
@@ -106,5 +101,5 @@ int i915_gem_object_blt_live_selftests(struct
drm_i915_private *i915)
if (!HAS_ENGINE(i915, BCS0))
return 0;
- return i915_subtests(tests, i915->engine[BCS0]->kernel_context);
+ return i915_live_subtests(tests, i915);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index cf592a049a71..2d9cc3cd1f27 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1744,7 +1744,7 @@ int intel_hangcheck_live_selftests(struct
drm_i915_private *i915)
saved_hangcheck = fetch_and_zero(_modparams.enable_hangcheck);
drain_delayed_work(>gpu_error.hangcheck_work); /* flush param */
- err = i915_subtests(tests, i915);
+ err = i915_live_subtests(tests, i915);
mutex_lock(>drm.struct_mutex);
igt_flush_test(i915, I915_WAIT_LOCKED);
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 0c97f953e908..11f490502ca6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -73,7 +73,6 @@ static int live_sanitycheck(void *arg)
err_spin:
igt_spinner_fini();
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: Check crtc_state->wm.need_postvbl_update before grabbing wm.mutex
== Series Details == Series: series starting with [1/6] drm/i915: Check crtc_state->wm.need_postvbl_update before grabbing wm.mutex URL : https://patchwork.freedesktop.org/series/63044/ State : success == Summary == CI Bug Log - changes from CI_DRM_6394_full -> Patchwork_13482_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13482_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-pci-d3-state: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#103558] / [fdo#105602]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-kbl4/igt@i915_pm_...@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-kbl2/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@mock_requests: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#110550]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl5/igt@i915_selftest@mock_requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-skl7/igt@i915_selftest@mock_requests.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][5] -> [FAIL][6] ([fdo#104873]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk5/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-glk2/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_flip@absolute-wf_vblank-interruptible: - shard-apl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl2/igt@kms_flip@absolute-wf_vblank-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-apl5/igt@kms_flip@absolute-wf_vblank-interruptible.html * igt@kms_flip@flip-vs-dpms-off-vs-modeset: - shard-kbl: [PASS][9] -> [DMESG-FAIL][10] ([fdo#103558] / [fdo#105602]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-kbl4/igt@kms_f...@flip-vs-dpms-off-vs-modeset.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-kbl2/igt@kms_f...@flip-vs-dpms-off-vs-modeset.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_f...@flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-apl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-apl2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#108341]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb3/igt@kms_psr@no_drrs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_psr@psr2_dpms.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13482/shard-iclb3/igt@kms_psr@psr2_dpms.html Possible fixes * igt@gem_tiled_swapping@non-threaded:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Bigjoiner atomic preparations.
== Series Details == Series: Bigjoiner atomic preparations. URL : https://patchwork.freedesktop.org/series/63094/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Prepare to split crtc state in uapi and hw state -O:drivers/gpu/drm/i915/intel_pm.c:2548:16: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_pm.c:2548:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:2548:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:2548:16: warning: expression using sizeof(void) Commit: drm/i915: Handle a few more cases for hw/sw split Okay! Commit: drm/i915: Complete sw/hw split Okay! Commit: drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid() Okay! Commit: drm/i915/dp: Validate modes that can only be handled in a bigjoiner configuration -O:drivers/gpu/drm/i915/display/intel_dp.c:4352:26: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/display/intel_dp.c:4352:26: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/display/intel_dp.c:4395:27: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/display/intel_dp.c:4395:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:527:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:527:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:570:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:570:27: warning: expression using sizeof(void) Commit: drm/i915: Try to make bigjoiner work in atomic check. -O:drivers/gpu/drm/i915/display/intel_dp.c:2051:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/display/intel_dp.c:2051:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:2060:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:2060:25: warning: expression using sizeof(void) Commit: drm/i915: Allow vdsc functions to be called without encoder. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Bigjoiner atomic preparations.
== Series Details == Series: Bigjoiner atomic preparations. URL : https://patchwork.freedesktop.org/series/63094/ State : warning == Summary == $ dim checkpatch origin/drm-tip b9e17bf6bac7 drm/i915: Prepare to split crtc state in uapi and hw state -:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #11: - crtc, *_changed flags, event, commit, state, mode_blob, (plane/connector/encoder)_mask. -:1968: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #1968: FILE: drivers/gpu/drm/i915/display/intel_display.c:11139: + crtc_state->uapi.active = crtc_state->uapi.enable = true; -:2625: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #2625: FILE: drivers/gpu/drm/i915/display/intel_display.c:16640: + crtc_state->hw.active = crtc_state->hw.enable = -:3731: ERROR:CODE_INDENT: code indent should use tabs where possible #3731: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:223: +^I^I^I^I new_crtc_state->uapi.event);$ -:3731: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #3731: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:223: + drm_crtc_arm_vblank_event(>base, + new_crtc_state->uapi.event); total: 1 errors, 1 warnings, 3 checks, 4166 lines checked fe8910ead298 drm/i915: Handle a few more cases for hw/sw split -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 118 lines checked d31a4fc4501d drm/i915: Complete sw/hw split -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 201 lines checked 9516b4dffdfa drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid() -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 22 lines checked 1909a2665a65 drm/i915/dp: Validate modes that can only be handled in a bigjoiner configuration -:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 307 lines checked deb270f134b8 drm/i915: Try to make bigjoiner work in atomic check. -:54: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #54: FILE: drivers/gpu/drm/i915/display/intel_display.c:12237: + crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0; -:74: WARNING:LONG_LINE: line over 100 characters #74: FILE: drivers/gpu/drm/i915/display/intel_display.c:13624: + struct intel_crtc_state *old_crtc_state, *new_crtc_state, *slave_crtc_state, *master_crtc_state; total: 0 errors, 1 warnings, 1 checks, 230 lines checked f41590956879 drm/i915: Allow vdsc functions to be called without encoder. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: synchronize_irq() against the actual irq (rev2)
== Series Details == Series: drm/i915: synchronize_irq() against the actual irq (rev2) URL : https://patchwork.freedesktop.org/series/63081/ State : success == Summary == CI Bug Log - changes from CI_DRM_6398 -> Patchwork_13494 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/ Known issues Here are the changes found in Patchwork_13494 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-6600u: [PASS][1] -> [FAIL][2] ([fdo#107707]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [PASS][3] -> [INCOMPLETE][4] ([fdo#108602]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-skl-iommu/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/fi-skl-iommu/igt@i915_selftest@live_blt.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_ctx_create@basic-files: - fi-icl-dsi: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html * igt@i915_pm_rpm@module-reload: - fi-kbl-r: [DMESG-WARN][9] ([fdo#111012]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-kbl-r/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/fi-kbl-r/igt@i915_pm_...@module-reload.html - fi-hsw-peppy: [DMESG-WARN][11] ([fdo#111012]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-hsw-peppy/igt@i915_pm_...@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/fi-hsw-peppy/igt@i915_pm_...@module-reload.html * igt@prime_vgem@basic-read: - fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6398/fi-icl-u3/igt@prime_v...@basic-read.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/fi-icl-u3/igt@prime_v...@basic-read.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 Participating hosts (55 -> 47) -- Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6398 -> Patchwork_13494 CI_DRM_6398: 9b9df28dc0ec04a7fb1a020d869ef0ea14be4d14 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13494: 3da1b4f318793bd203a06588a7480108cde80849 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 3da1b4f31879 drm/i915: synchronize_irq() against the actual irq == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13494/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dmc: protect against reading random memory (rev2)
== Series Details == Series: drm/i915/dmc: protect against reading random memory (rev2) URL : https://patchwork.freedesktop.org/series/61695/ State : failure == Summary == Applying: drm/i915/dmc: protect against reading random memory Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_csr.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_csr.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_csr.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/dmc: protect against reading random memory When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915/uc: replace uc init/fini misc
On 7/2/19 1:52 PM, Michal Wajdeczko wrote:
On Tue, 02 Jul 2019 22:09:47 +0200, Daniele Ceraolo Spurio
wrote:
The "misc" terminology doesn't clearly explain what we intend to cover
in this phase. The only thing we do in there apart from FW fetch is
initializing the log workqueue. We can move the latter to the
init_early phase and rename the function to clarify that they only
fetch/release the blobs.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++-
drivers/gpu/drm/i915/i915_gem.c | 12 +++---
drivers/gpu/drm/i915/intel_guc.c | 57
drivers/gpu/drm/i915/intel_guc.h | 5 +--
drivers/gpu/drm/i915/intel_guc_log.c | 32 +++-
drivers/gpu/drm/i915/intel_guc_log.h | 3 +-
drivers/gpu/drm/i915/intel_huc.c | 8
drivers/gpu/drm/i915/intel_huc.h | 6 ---
drivers/gpu/drm/i915/intel_uc.c | 50 ++--
drivers/gpu/drm/i915/intel_uc.h | 6 +--
10 files changed, 75 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index 794c6814a6d0..20ca0208dd98 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -934,7 +934,11 @@ static int i915_driver_init_early(struct
drm_i915_private *dev_priv)
intel_detect_pch(dev_priv);
intel_wopcm_init_early(_priv->wopcm);
- intel_uc_init_early(dev_priv);
+
+ ret = intel_uc_init_early(dev_priv);
+ if (ret)
+ goto err_gem;
+
intel_pm_setup(dev_priv);
intel_init_dpio(dev_priv);
ret = intel_power_domains_init(dev_priv);
@@ -953,6 +957,7 @@ static int i915_driver_init_early(struct
drm_i915_private *dev_priv)
err_uc:
intel_uc_cleanup_early(dev_priv);
+err_gem:
i915_gem_cleanup_early(dev_priv);
err_workqueues:
i915_workqueues_cleanup(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index b7f290b77f8f..46a75844f303 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1429,13 +1429,11 @@ int i915_gem_init(struct drm_i915_private
*dev_priv)
if (ret)
return ret;
- ret = intel_uc_init_misc(dev_priv);
- if (ret)
- return ret;
+ intel_uc_fetch_firmwares(dev_priv);
ret = intel_wopcm_init(_priv->wopcm);
if (ret)
- goto err_uc_misc;
+ goto err_uc_fw;
/* This is just a security blanket to placate dragons.
* On some systems, we very sporadically observe that the first TLBs
@@ -1561,8 +1559,8 @@ int i915_gem_init(struct drm_i915_private
*dev_priv)
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
-err_uc_misc:
- intel_uc_fini_misc(dev_priv);
+err_uc_fw:
+ intel_uc_cleanup_firmwares(dev_priv);
if (ret != -EIO) {
i915_gem_cleanup_userptr(dev_priv);
@@ -1628,7 +1626,7 @@ void i915_gem_fini(struct drm_i915_private
*dev_priv)
intel_cleanup_gt_powersave(dev_priv);
- intel_uc_fini_misc(dev_priv);
+ intel_uc_cleanup_firmwares(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
intel_timelines_fini(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc.c
b/drivers/gpu/drm/i915/intel_guc.c
index 501b74f44374..03fad4fe3d9b 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -74,13 +74,16 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
guc->send_regs.fw_domains = fw_domains;
}
-void intel_guc_init_early(struct intel_guc *guc)
+int intel_guc_init_early(struct intel_guc *guc)
{
struct drm_i915_private *i915 = guc_to_i915(guc);
+ int ret;
intel_guc_fw_init_early(guc);
intel_guc_ct_init_early(>ct);
- intel_guc_log_init_early(>log);
+ ret = intel_guc_log_init_early(>log);
+ if (ret)
+ return ret;
mutex_init(>send_mutex);
spin_lock_init(>irq_lock);
@@ -97,59 +100,13 @@ void intel_guc_init_early(struct intel_guc *guc)
guc->interrupts.enable = gen9_enable_guc_interrupts;
guc->interrupts.disable = gen9_disable_guc_interrupts;
}
-}
-
-static int guc_init_wq(struct intel_guc *guc)
-{
- /*
- * GuC log buffer flush work item has to do register access to
- * send the ack to GuC and this work item, if not synced before
- * suspend, can potentially get executed after the GFX device is
- * suspended.
- * By marking the WQ as freezable, we don't have to bother about
- * flushing of this work item from the suspend hooks, the pending
- * work item if any will be either executed before the suspend
- * or scheduled later on resume. This way the handling of work
- * item can be kept same between system suspend & rpm suspend.
- */
- guc->log.relay.flush_wq =
- alloc_ordered_workqueue("i915-guc_log",
- WQ_HIGHPRI | WQ_FREEZABLE);
- if (!guc->log.relay.flush_wq) {
- DRM_ERROR("Couldn't allocate
Re: [Intel-gfx] [PATCH V2] include: linux: Regularise the use of FIELD_SIZEOF macro
On Sat, Jun 29, 2019 at 09:45:10AM -0700, Joe Perches wrote: > On Sat, 2019-06-29 at 17:25 +0300, Alexey Dobriyan wrote: > > On Tue, Jun 11, 2019 at 03:00:10PM -0600, Andreas Dilger wrote: > > > On Jun 11, 2019, at 2:48 PM, Andrew Morton > > > wrote: > > > > On Wed, 12 Jun 2019 01:08:36 +0530 Shyam Saini > > > > wrote: > > > I did a check, and FIELD_SIZEOF() is used about 350x, while sizeof_field() > > > is about 30x, and SIZEOF_FIELD() is only about 5x. > > > > > > That said, I'm much more in favour of "sizeof_field()" or > > > "sizeof_member()" > > > than FIELD_SIZEOF(). Not only does that better match "offsetof()", with > > > which it is closely related, but is also closer to the original > > > "sizeof()". > > > > > > Since this is a rather trivial change, it can be split into a number of > > > patches to get approval/landing via subsystem maintainers, and there is no > > > huge urgency to remove the original macros until the users are gone. It > > > would make sense to remove SIZEOF_FIELD() and sizeof_field() quickly so > > > they don't gain more users, and the remaining FIELD_SIZEOF() users can be > > > whittled away as the patches come through the maintainer trees. > > > > The signature should be > > > > sizeof_member(T, m) > > > > it is proper English, > > it is lowercase, so is easier to type, > > it uses standard term (member, not field), > > it blends in with standard "sizeof" operator, > > yes please. > > Also, a simple script conversion applied > immediately after an rc1 might be easiest > rather than individual patches. This seems reasonable to me. I think the patch steps would be: 1) implement sizeof_member(T, m) as a stand-alone macro 2) do a scripted replacement of all identical macros. 3) remove all the identical macros. Step 2 can be a patch that includes the script used to do the replacement. That way Linus can choose to just run the script instead of taking the patch. -- Kees Cook ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915/uc: replace uc init/fini misc
On Tue, 02 Jul 2019 22:09:47 +0200, Daniele Ceraolo Spurio
wrote:
The "misc" terminology doesn't clearly explain what we intend to cover
in this phase. The only thing we do in there apart from FW fetch is
initializing the log workqueue. We can move the latter to the
init_early phase and rename the function to clarify that they only
fetch/release the blobs.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++-
drivers/gpu/drm/i915/i915_gem.c | 12 +++---
drivers/gpu/drm/i915/intel_guc.c | 57
drivers/gpu/drm/i915/intel_guc.h | 5 +--
drivers/gpu/drm/i915/intel_guc_log.c | 32 +++-
drivers/gpu/drm/i915/intel_guc_log.h | 3 +-
drivers/gpu/drm/i915/intel_huc.c | 8
drivers/gpu/drm/i915/intel_huc.h | 6 ---
drivers/gpu/drm/i915/intel_uc.c | 50 ++--
drivers/gpu/drm/i915/intel_uc.h | 6 +--
10 files changed, 75 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index 794c6814a6d0..20ca0208dd98 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -934,7 +934,11 @@ static int i915_driver_init_early(struct
drm_i915_private *dev_priv)
intel_detect_pch(dev_priv);
intel_wopcm_init_early(_priv->wopcm);
- intel_uc_init_early(dev_priv);
+
+ ret = intel_uc_init_early(dev_priv);
+ if (ret)
+ goto err_gem;
+
intel_pm_setup(dev_priv);
intel_init_dpio(dev_priv);
ret = intel_power_domains_init(dev_priv);
@@ -953,6 +957,7 @@ static int i915_driver_init_early(struct
drm_i915_private *dev_priv)
err_uc:
intel_uc_cleanup_early(dev_priv);
+err_gem:
i915_gem_cleanup_early(dev_priv);
err_workqueues:
i915_workqueues_cleanup(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index b7f290b77f8f..46a75844f303 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1429,13 +1429,11 @@ int i915_gem_init(struct drm_i915_private
*dev_priv)
if (ret)
return ret;
- ret = intel_uc_init_misc(dev_priv);
- if (ret)
- return ret;
+ intel_uc_fetch_firmwares(dev_priv);
ret = intel_wopcm_init(_priv->wopcm);
if (ret)
- goto err_uc_misc;
+ goto err_uc_fw;
/* This is just a security blanket to placate dragons.
* On some systems, we very sporadically observe that the first TLBs
@@ -1561,8 +1559,8 @@ int i915_gem_init(struct drm_i915_private
*dev_priv)
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
-err_uc_misc:
- intel_uc_fini_misc(dev_priv);
+err_uc_fw:
+ intel_uc_cleanup_firmwares(dev_priv);
if (ret != -EIO) {
i915_gem_cleanup_userptr(dev_priv);
@@ -1628,7 +1626,7 @@ void i915_gem_fini(struct drm_i915_private
*dev_priv)
intel_cleanup_gt_powersave(dev_priv);
- intel_uc_fini_misc(dev_priv);
+ intel_uc_cleanup_firmwares(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
intel_timelines_fini(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc.c
b/drivers/gpu/drm/i915/intel_guc.c
index 501b74f44374..03fad4fe3d9b 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -74,13 +74,16 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
guc->send_regs.fw_domains = fw_domains;
}
-void intel_guc_init_early(struct intel_guc *guc)
+int intel_guc_init_early(struct intel_guc *guc)
{
struct drm_i915_private *i915 = guc_to_i915(guc);
+ int ret;
intel_guc_fw_init_early(guc);
intel_guc_ct_init_early(>ct);
- intel_guc_log_init_early(>log);
+ ret = intel_guc_log_init_early(>log);
+ if (ret)
+ return ret;
mutex_init(>send_mutex);
spin_lock_init(>irq_lock);
@@ -97,59 +100,13 @@ void intel_guc_init_early(struct intel_guc *guc)
guc->interrupts.enable = gen9_enable_guc_interrupts;
guc->interrupts.disable = gen9_disable_guc_interrupts;
}
-}
-
-static int guc_init_wq(struct intel_guc *guc)
-{
- /*
-* GuC log buffer flush work item has to do register access to
-* send the ack to GuC and this work item, if not synced before
-* suspend, can potentially get executed after the GFX device is
-* suspended.
-* By marking the WQ as freezable, we don't have to bother about
-* flushing of this work item from the suspend hooks, the pending
-* work item if any will be either executed before the suspend
-* or scheduled later on resume. This way the handling of work
-* item can be kept same between system suspend & rpm suspend.
-*/
-
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Enable hotplug retry
On Tue, 2019-07-02 at 23:29 +0300, Timo Aaltonen wrote: > On 2.7.2019 22.54, Souza, Jose wrote: > > Here a dmesg output of this patch working in a unpowered type-c > > dongle: > > https://gist.github.com/zehortigoza/93c54b03fb65237cc1a2e193acef61a8 > > > > With the latest type-c patches from Imre it is becoming really hard > > to > > reproduce this but is still possible, also looks like due some > > internal > > error on the dongle it being re-discovered by USB sub-system. > > > > I added this to the patches bellow have more log information: > > https://gist.github.com/zehortigoza/baecabeb7097b9322723b6caf5a9ced5 > > Let me know if you think this or something similar should be > > squashed > > to this patch, I think it is not necessary. > > FWIW, we've tested these on a WHL which is suffering from HDMI unplug > still showing the display connected, and it's working fine now. > > Thanks, I will add your: Tested-by: Timo Aaltonen ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Enable hotplug retry
On 2.7.2019 22.54, Souza, Jose wrote: > Here a dmesg output of this patch working in a unpowered type-c dongle: > https://gist.github.com/zehortigoza/93c54b03fb65237cc1a2e193acef61a8 > > With the latest type-c patches from Imre it is becoming really hard to > reproduce this but is still possible, also looks like due some internal > error on the dongle it being re-discovered by USB sub-system. > > I added this to the patches bellow have more log information: > https://gist.github.com/zehortigoza/baecabeb7097b9322723b6caf5a9ced5 > Let me know if you think this or something similar should be squashed > to this patch, I think it is not necessary. FWIW, we've tested these on a WHL which is suffering from HDMI unplug still showing the display connected, and it's working fine now. -- t ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Use caller provided forcewake for intel_mocs_init_engine
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Use caller provided forcewake
for intel_mocs_init_engine
URL : https://patchwork.freedesktop.org/series/63082/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6397 -> Patchwork_13493
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13493/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13493:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-icl-u4}:[FAIL][1] ([fdo#109485]) -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6397/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13493/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
Known issues
Here are the changes found in Patchwork_13493 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#109100])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6397/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13493/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_render_tiled_blits@basic:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6397/fi-icl-u3/igt@gem_render_tiled_bl...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13493/fi-icl-u3/igt@gem_render_tiled_bl...@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][7] -> [FAIL][8] ([fdo#108511])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6397/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13493/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
Possible fixes
* igt@core_auth@basic-auth:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6397/fi-icl-u3/igt@core_a...@basic-auth.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13493/fi-icl-u3/igt@core_a...@basic-auth.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6397/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13493/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6397/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13493/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (53 -> 46)
--
Additional (2): fi-bdw-gvtdvm fi-bwr-2160
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6397 -> Patchwork_13493
CI_DRM_6397: fe2b6d5aa044f4e57c6c0bf0ac4fa162792e5fa1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13493: df165e394f84ede00f54c5f7b87e65796cedf00d @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13493/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
[Intel-gfx] [PATCH 1/3] drm/i915/guc: Remove preemption support for current fw
From: Chris Wilson
Preemption via GuC submission is not being supported with its current
legacy incarnation. The current FW does support a similar pre-emption
flow via H2G, but it is class-based instead of being instance-based,
which doesn't fit well with the i915 tracking. To fix this, the
firmware is being updated to better support our needs with a new flow,
so we can safely remove the old code.
v2 (Daniele): resurrect & rebase, reword commit message, remove
preempt_context as well
Signed-off-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 --
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 13 --
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 5 -
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/intel_guc.c | 31 ---
drivers/gpu/drm/i915/intel_guc.h | 9 -
drivers/gpu/drm/i915/intel_guc_submission.c | 220 +--
drivers/gpu/drm/i915/selftests/intel_guc.c | 31 +--
10 files changed, 14 insertions(+), 319 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 8a9787cf0cd0..9c695910bc43 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -644,18 +644,12 @@ static void init_contexts(struct drm_i915_private *i915)
init_llist_head(>contexts.free_list);
}
-static bool needs_preempt_context(struct drm_i915_private *i915)
-{
- return USES_GUC_SUBMISSION(i915);
-}
-
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
- GEM_BUG_ON(dev_priv->preempt_context);
intel_engine_init_ctx_wa(dev_priv->engine[RCS0]);
init_contexts(dev_priv);
@@ -677,15 +671,6 @@ int i915_gem_contexts_init(struct drm_i915_private
*dev_priv)
GEM_BUG_ON(!atomic_read(>hw_id_pin_count));
dev_priv->kernel_context = ctx;
- /* highest priority; preempting task */
- if (needs_preempt_context(dev_priv)) {
- ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
- if (!IS_ERR(ctx))
- dev_priv->preempt_context = ctx;
- else
- DRM_ERROR("Failed to create preempt context; disabling
preemption\n");
- }
-
DRM_DEBUG_DRIVER("%s context support initialized\n",
DRIVER_CAPS(dev_priv)->has_logical_contexts ?
"logical" : "fake");
@@ -696,8 +681,6 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
{
lockdep_assert_held(>drm.struct_mutex);
- if (i915->preempt_context)
- destroy_kernel_context(>preempt_context);
destroy_kernel_context(>kernel_context);
/* Must free all deferred contexts (via flush_workqueue) first */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d1508f0b4c84..55b11409c1f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -842,15 +842,6 @@ int intel_engine_init_common(struct intel_engine_cs
*engine)
if (ret)
return ret;
- /*
-* Similarly the preempt context must always be available so that
-* we can interrupt the engine at any time. However, as preemption
-* is optional, we allow it to fail.
-*/
- if (i915->preempt_context)
- pin_context(i915->preempt_context, engine,
- >preempt_context);
-
ret = measure_breadcrumb_dw(engine);
if (ret < 0)
goto err_unpin;
@@ -862,8 +853,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
return 0;
err_unpin:
- if (engine->preempt_context)
- intel_context_unpin(engine->preempt_context);
intel_context_unpin(engine->kernel_context);
return ret;
}
@@ -888,8 +877,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
if (engine->default_state)
i915_gem_object_put(engine->default_state);
- if (engine->preempt_context)
- intel_context_unpin(engine->preempt_context);
intel_context_unpin(engine->kernel_context);
GEM_BUG_ON(!llist_empty(>barrier_tasks));
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 7e056114344e..8be63019d707 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -288,7 +288,6 @@ struct intel_engine_cs {
[Intel-gfx] [PATCH 3/3] drm/i915/uc: replace uc init/fini misc
The "misc" terminology doesn't clearly explain what we intend to cover
in this phase. The only thing we do in there apart from FW fetch is
initializing the log workqueue. We can move the latter to the
init_early phase and rename the function to clarify that they only
fetch/release the blobs.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++-
drivers/gpu/drm/i915/i915_gem.c | 12 +++---
drivers/gpu/drm/i915/intel_guc.c | 57
drivers/gpu/drm/i915/intel_guc.h | 5 +--
drivers/gpu/drm/i915/intel_guc_log.c | 32 +++-
drivers/gpu/drm/i915/intel_guc_log.h | 3 +-
drivers/gpu/drm/i915/intel_huc.c | 8
drivers/gpu/drm/i915/intel_huc.h | 6 ---
drivers/gpu/drm/i915/intel_uc.c | 50 ++--
drivers/gpu/drm/i915/intel_uc.h | 6 +--
10 files changed, 75 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 794c6814a6d0..20ca0208dd98 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -934,7 +934,11 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
intel_detect_pch(dev_priv);
intel_wopcm_init_early(_priv->wopcm);
- intel_uc_init_early(dev_priv);
+
+ ret = intel_uc_init_early(dev_priv);
+ if (ret)
+ goto err_gem;
+
intel_pm_setup(dev_priv);
intel_init_dpio(dev_priv);
ret = intel_power_domains_init(dev_priv);
@@ -953,6 +957,7 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
err_uc:
intel_uc_cleanup_early(dev_priv);
+err_gem:
i915_gem_cleanup_early(dev_priv);
err_workqueues:
i915_workqueues_cleanup(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b7f290b77f8f..46a75844f303 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1429,13 +1429,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- ret = intel_uc_init_misc(dev_priv);
- if (ret)
- return ret;
+ intel_uc_fetch_firmwares(dev_priv);
ret = intel_wopcm_init(_priv->wopcm);
if (ret)
- goto err_uc_misc;
+ goto err_uc_fw;
/* This is just a security blanket to placate dragons.
* On some systems, we very sporadically observe that the first TLBs
@@ -1561,8 +1559,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
-err_uc_misc:
- intel_uc_fini_misc(dev_priv);
+err_uc_fw:
+ intel_uc_cleanup_firmwares(dev_priv);
if (ret != -EIO) {
i915_gem_cleanup_userptr(dev_priv);
@@ -1628,7 +1626,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
intel_cleanup_gt_powersave(dev_priv);
- intel_uc_fini_misc(dev_priv);
+ intel_uc_cleanup_firmwares(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
intel_timelines_fini(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 501b74f44374..03fad4fe3d9b 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -74,13 +74,16 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
guc->send_regs.fw_domains = fw_domains;
}
-void intel_guc_init_early(struct intel_guc *guc)
+int intel_guc_init_early(struct intel_guc *guc)
{
struct drm_i915_private *i915 = guc_to_i915(guc);
+ int ret;
intel_guc_fw_init_early(guc);
intel_guc_ct_init_early(>ct);
- intel_guc_log_init_early(>log);
+ ret = intel_guc_log_init_early(>log);
+ if (ret)
+ return ret;
mutex_init(>send_mutex);
spin_lock_init(>irq_lock);
@@ -97,59 +100,13 @@ void intel_guc_init_early(struct intel_guc *guc)
guc->interrupts.enable = gen9_enable_guc_interrupts;
guc->interrupts.disable = gen9_disable_guc_interrupts;
}
-}
-
-static int guc_init_wq(struct intel_guc *guc)
-{
- /*
-* GuC log buffer flush work item has to do register access to
-* send the ack to GuC and this work item, if not synced before
-* suspend, can potentially get executed after the GFX device is
-* suspended.
-* By marking the WQ as freezable, we don't have to bother about
-* flushing of this work item from the suspend hooks, the pending
-* work item if any will be either executed before the suspend
-* or scheduled later on resume. This way the handling of work
-* item can be kept same between system suspend & rpm suspend.
-*/
- guc->log.relay.flush_wq =
- alloc_ordered_workqueue("i915-guc_log",
-
[Intel-gfx] [PATCH 2/3] drm/i915/guc: simplify guc client
We originally added support, in some cases partial, for different modes
of operations via guc clients:
- proxy vs direct submission;
- variable engine mask per-client.
We only ever used one flow (all submissions via a single proxy), so the
other code paths haven't been exercised and are most likely
non-functional. The guc firmware interface is also in the process of
being updated to better fit the i915 flow and our client abstraction
will need to change accordingly (or possibly go away entirely), so these
old unused paths can be considered dead and removed.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 73 ++---
drivers/gpu/drm/i915/intel_guc_submission.h | 2 -
drivers/gpu/drm/i915/selftests/intel_guc.c | 12 +---
4 files changed, 8 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 02eaa15d47c0..65ddb24a0f4b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2028,7 +2028,6 @@ static int i915_guc_stage_pool(struct seq_file *m, void
*data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const struct intel_guc *guc = _priv->guc;
struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
- struct intel_guc_client *client = guc->execbuf_client;
intel_engine_mask_t tmp;
int index;
@@ -2058,7 +2057,7 @@ static int i915_guc_stage_pool(struct seq_file *m, void
*data)
desc->wq_addr, desc->wq_size);
seq_putc(m, '\n');
- for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
+ for_each_engine(engine, dev_priv, tmp) {
u32 guc_engine_id = engine->guc_id;
struct guc_execlist_context *lrc =
>lrc[guc_engine_id];
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 8520bb224175..30692f8289bd 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -363,10 +363,7 @@ static void guc_stage_desc_pool_destroy(struct intel_guc
*guc)
static void guc_stage_desc_init(struct intel_guc_client *client)
{
struct intel_guc *guc = client->guc;
- struct i915_gem_context *ctx = client->owner;
- struct i915_gem_engines_iter it;
struct guc_stage_desc *desc;
- struct intel_context *ce;
u32 gfx_addr;
desc = __get_stage_desc(client);
@@ -380,55 +377,6 @@ static void guc_stage_desc_init(struct intel_guc_client
*client)
desc->priority = client->priority;
desc->db_id = client->doorbell_id;
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- struct guc_execlist_context *lrc;
-
- if (!(ce->engine->mask & client->engines))
- continue;
-
- /* TODO: We have a design issue to be solved here. Only when we
-* receive the first batch, we know which engine is used by the
-* user. But here GuC expects the lrc and ring to be pinned. It
-* is not an issue for default context, which is the only one
-* for now who owns a GuC client. But for future owner of GuC
-* client, need to make sure lrc is pinned prior to enter here.
-*/
- if (!ce->state)
- break; /* XXX: continue? */
-
- /*
-* XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
-* submission or, in other words, not using a direct submission
-* model) the KMD's LRCA is not used for any work submission.
-* Instead, the GuC uses the LRCA of the user mode context (see
-* guc_add_request below).
-*/
- lrc = >lrc[ce->engine->guc_id];
- lrc->context_desc = lower_32_bits(ce->lrc_desc);
-
- /* The state page is after PPHWSP */
- lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
-LRC_STATE_PN * PAGE_SIZE;
-
- /* XXX: In direct submission, the GuC wants the HW context id
-* here. In proxy submission, it wants the stage id
-*/
- lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
- (ce->engine->guc_id << GUC_ELC_ENGINE_OFFSET);
-
- lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
- lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
- lrc->ring_next_free_location = lrc->ring_begin;
-
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Enable hotplug retry
Here a dmesg output of this patch working in a unpowered type-c dongle:
https://gist.github.com/zehortigoza/93c54b03fb65237cc1a2e193acef61a8
With the latest type-c patches from Imre it is becoming really hard to
reproduce this but is still possible, also looks like due some internal
error on the dongle it being re-discovered by USB sub-system.
I added this to the patches bellow have more log information:
https://gist.github.com/zehortigoza/baecabeb7097b9322723b6caf5a9ced5
Let me know if you think this or something similar should be squashed
to this patch, I think it is not necessary.
On Fri, 2019-06-28 at 14:39 -0700, José Roberto de Souza wrote:
> Right now we are aware of two cases that needs another hotplug retry:
> - Unpowered type-c dongles
> - HDMI slow unplug
>
> Both have a complete explanation in the code to schedule another run
> of the hotplug handler.
>
> It could have more checks to just trigger the retry in those two
> specific cases but why would sink signal a long pulse if there is
> no change? Also the drawback of running the hotplug handler again
> is really low and that could fix another cases that we are not
> aware.
>
> Also retrying for old DP ports(non-DDI) to make it consistent and not
> cause CI failures if those systems are connected to chamelium boards
> that will be used to simulate the issues reported in here.
>
> v2: Also retrying for old DP ports(non-DDI)(Imre)
>
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 21 +
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
> drivers/gpu/drm/i915/display/intel_hdmi.c | 28
> ++-
> 3 files changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 53009984e046..d7df1940b826 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4086,6 +4086,7 @@ intel_ddi_hotplug(struct intel_encoder
> *encoder,
> struct intel_connector *connector,
> bool irq_received)
> {
> + struct intel_digital_port *dig_port = enc_to_dig_port(
> >base);
> struct drm_modeset_acquire_ctx ctx;
> enum intel_hotplug_state state;
> int ret;
> @@ -4112,6 +4113,26 @@ intel_ddi_hotplug(struct intel_encoder
> *encoder,
> drm_modeset_acquire_fini();
> WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
>
> + /*
> + * Unpowered type-c dongles can take some time to boot and be
> + * responsible, so here giving some time to those dongles to
> power up
> + * and then retrying the probe.
> + *
> + * On many platforms the HDMI live state signal is known to be
> + * unreliable, so we can't use it to detect if a sink is
> connected or
> + * not. Instead we detect if it's connected based on whether we
> can
> + * read the EDID or not. That in turn has a problem during
> disconnect,
> + * since the HPD interrupt may be raised before the DDC lines
> get
> + * disconnected (due to how the required length of DDC vs. HPD
> + * connector pins are specified) and so we'll still be able to
> get a
> + * valid EDID. To solve this schedule another detection cycle
> if this
> + * time around we didn't detect any change in the sink's
> connection
> + * status.
> + */
> + if (state == INTEL_HOTPLUG_NOCHANGE && irq_received &&
> + !dig_port->dp.is_mst)
> + state = INTEL_HOTPLUG_RETRY;
> +
> return state;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 95d0da9d1bac..8eb479daa8a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4906,6 +4906,9 @@ intel_dp_hotplug(struct intel_encoder *encoder,
> drm_modeset_acquire_fini();
> WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
>
> + if (state == INTEL_HOTPLUG_NOCHANGE && irq_received)
> + state = INTEL_HOTPLUG_RETRY;
> +
> return state;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0ebec69bbbfc..5ed91caf3b4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3143,6 +3143,32 @@ void intel_hdmi_init_connector(struct
> intel_digital_port *intel_dig_port,
> DRM_DEBUG_KMS("CEC notifier get failed\n");
> }
>
> +static enum intel_hotplug_state
> +intel_hdmi_hotplug(struct intel_encoder *encoder,
> +struct intel_connector *connector, bool
> irq_received)
> +{
> + enum intel_hotplug_state state;
> +
> + state = intel_encoder_hotplug(encoder, connector,
> irq_received);
> +
> + /*
> + * On many platforms the HDMI live state signal is
[Intel-gfx] [RFC 4/7] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid()
Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/display/intel_dp.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d5c56ea079a4..b41ff88d3258 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -506,6 +506,7 @@ intel_dp_mode_valid(struct drm_connector *connector, int max_dotclk; u16 dsc_max_output_bpp = 0; u8 dsc_slice_count = 0; + bool dsc; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) return MODE_NO_DBLESCAN; @@ -553,8 +554,13 @@ intel_dp_mode_valid(struct drm_connector *connector, } } - if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || - target_clock > max_dotclk) + dsc = dsc_max_output_bpp && dsc_slice_count; + + /* Gen11 has big joiner for handling this */ + if (dsc && dsc_slice_count >= 2 && INTEL_GEN(dev_priv) >= 11) + max_dotclk *= 2; + + if ((mode_rate > max_rate && !dsc) || target_clock > max_dotclk) return MODE_CLOCK_HIGH; if (mode->clock < 1) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 2/7] drm/i915: Handle a few more cases for hw/sw split
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 38 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 +--
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 73060623b83f..2bbcff9a4c54 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11722,10 +11722,10 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
bool mode_changed = needs_modeset(pipe_config);
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
- mode_changed && !crtc_state->active)
+ mode_changed && !pipe_config->hw.active)
pipe_config->update_wm_post = true;
- if (mode_changed && crtc_state->enable &&
+ if (mode_changed && pipe_config->hw.enable &&
dev_priv->display.crtc_compute_clock &&
!WARN_ON(pipe_config->shared_dpll)) {
ret = dev_priv->display.crtc_compute_clock(intel_crtc,
@@ -11739,10 +11739,10 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
* when C8 planes are getting enabled/disabled.
*/
if (c8_planes_changed(pipe_config))
- crtc_state->color_mgmt_changed = true;
+ pipe_config->uapi.color_mgmt_changed = true;
if (mode_changed || pipe_config->update_pipe ||
- crtc_state->color_mgmt_changed) {
+ pipe_config->uapi.color_mgmt_changed) {
ret = intel_color_check(pipe_config);
if (ret)
return ret;
@@ -13374,30 +13374,30 @@ static int intel_lock_all_pipes(struct
drm_atomic_state *state)
static int intel_modeset_all_pipes(struct drm_atomic_state *state)
{
- struct drm_crtc *crtc;
+ struct intel_crtc *crtc;
/*
* Add all pipes to the state, and force
* a modeset on all the active ones.
*/
- for_each_crtc(state->dev, crtc) {
- struct drm_crtc_state *crtc_state;
+ for_each_intel_crtc(state->dev, crtc) {
+ struct intel_crtc_state *crtc_state;
int ret;
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ crtc_state = intel_atomic_get_crtc_state(state, crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
- if (!crtc_state->active ||
needs_modeset(to_intel_crtc_state(crtc_state)))
+ if (!crtc_state->hw.active || needs_modeset(crtc_state))
continue;
- crtc_state->mode_changed = true;
+ crtc_state->uapi.mode_changed = true;
- ret = drm_atomic_add_affected_connectors(state, crtc);
+ ret = drm_atomic_add_affected_connectors(state, >base);
if (ret)
return ret;
- ret = drm_atomic_add_affected_planes(state, crtc);
+ ret = drm_atomic_add_affected_planes(state, >base);
if (ret)
return ret;
}
@@ -16030,8 +16030,8 @@ static int intel_initial_commit(struct drm_device *dev)
{
struct drm_atomic_state *state = NULL;
struct drm_modeset_acquire_ctx ctx;
- struct drm_crtc *crtc;
- struct drm_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
int ret = 0;
state = drm_atomic_state_alloc(dev);
@@ -16043,15 +16043,15 @@ static int intel_initial_commit(struct drm_device
*dev)
retry:
state->acquire_ctx =
- drm_for_each_crtc(crtc, dev) {
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ for_each_intel_crtc(dev, crtc) {
+ crtc_state = intel_atomic_get_crtc_state(state, crtc);
if (IS_ERR(crtc_state)) {
ret = PTR_ERR(crtc_state);
goto out;
}
- if (crtc_state->active) {
- ret = drm_atomic_add_affected_planes(state, crtc);
+ if (crtc_state->hw.active) {
+ ret = drm_atomic_add_affected_planes(state,
>base);
if (ret)
goto out;
@@ -16061,7 +16061,7 @@ static int intel_initial_commit(struct drm_device *dev)
* having a proper LUT loaded. Remove once we
* have readout for pipe gamma enable.
*/
- crtc_state->color_mgmt_changed = true;
+ crtc_state->uapi.color_mgmt_changed = true;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 236bf06148ab..5739a9536928
[Intel-gfx] [RFC 3/7] drm/i915: Complete sw/hw split
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 44
drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 39 ++---
drivers/gpu/drm/i915/intel_drv.h | 8 ++--
4 files changed, 85 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index b95015cfa5dc..2cc3d87bdafc 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
__drm_atomic_helper_crtc_duplicate_state(crtc, _state->uapi);
+ /* copy color blobs */
+ if (crtc_state->hw.degamma_lut)
+ drm_property_blob_get(crtc_state->hw.degamma_lut);
+ if (crtc_state->hw.ctm)
+ drm_property_blob_get(crtc_state->hw.ctm);
+ if (crtc_state->hw.gamma_lut)
+ drm_property_blob_get(crtc_state->hw.gamma_lut);
+
crtc_state->update_pipe = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
@@ -209,6 +217,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
return _state->uapi;
}
+static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ drm_property_blob_put(crtc_state->hw.degamma_lut);
+ drm_property_blob_put(crtc_state->hw.gamma_lut);
+ drm_property_blob_put(crtc_state->hw.ctm);
+}
+
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+}
+
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+
+ if (crtc_state->uapi.degamma_lut)
+ crtc_state->hw.degamma_lut =
+ drm_property_blob_get(crtc_state->uapi.degamma_lut);
+ else
+ crtc_state->hw.degamma_lut = NULL;
+
+ if (crtc_state->uapi.gamma_lut)
+ crtc_state->hw.gamma_lut =
+ drm_property_blob_get(crtc_state->uapi.gamma_lut);
+ else
+ crtc_state->hw.gamma_lut = NULL;
+
+ if (crtc_state->uapi.ctm)
+ crtc_state->hw.ctm =
+ drm_property_blob_get(crtc_state->uapi.ctm);
+ else
+ crtc_state->hw.ctm = NULL;
+}
+
/**
* intel_crtc_destroy_state - destroy crtc state
* @crtc: drm crtc
@@ -224,6 +267,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
__drm_atomic_helper_crtc_destroy_state(_state->uapi);
+ intel_crtc_free_hw_state(crtc_state);
kfree(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 58065d3161a3..42be91e0772a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -35,6 +35,8 @@ intel_digital_connector_duplicate_state(struct drm_connector
*connector);
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2bbcff9a4c54..d8e63f133a62 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -114,6 +114,7 @@ static const u64 cursor_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state);
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
@@ -7039,6 +7040,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc,
crtc->enabled = false;
crtc->state->connector_mask = 0;
crtc->state->encoder_mask = 0;
+ copy_uapi_to_hw_state(to_intel_crtc_state(crtc->state));
for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
encoder->base.crtc = NULL;
@@ -11743,6 +11745,9 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
if (mode_changed || pipe_config->update_pipe ||
pipe_config->uapi.color_mgmt_changed) {
+ /* Copy color blobs to hw state */
+ intel_crtc_copy_color_blobs(pipe_config);
+
ret = intel_color_check(pipe_config);
if (ret)
[Intel-gfx] [RFC 0/7] Bigjoiner atomic preparations.
This is just a proof of concept for the software state, not sure I handled every case correctly, and completely untested on real hardware. Maarten Lankhorst (7): drm/i915: Prepare to split crtc state in uapi and hw state drm/i915: Handle a few more cases for hw/sw split drm/i915: Complete sw/hw split drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid() drm/i915/dp: Validate modes that can only be handled in a bigjoiner configuration drm/i915: Try to make bigjoiner work in atomic check. drm/i915: Allow vdsc functions to be called without encoder. drivers/gpu/drm/i915/display/icl_dsi.c| 18 +- drivers/gpu/drm/i915/display/intel_atomic.c | 60 +- drivers/gpu/drm/i915/display/intel_atomic.h | 2 + .../gpu/drm/i915/display/intel_atomic_plane.c | 6 +- drivers/gpu/drm/i915/display/intel_audio.c| 14 +- drivers/gpu/drm/i915/display/intel_bw.c | 4 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 8 +- drivers/gpu/drm/i915/display/intel_color.c| 150 ++-- drivers/gpu/drm/i915/display/intel_crt.c | 24 +- drivers/gpu/drm/i915/display/intel_ddi.c | 30 +- drivers/gpu/drm/i915/display/intel_display.c | 735 +++--- drivers/gpu/drm/i915/display/intel_dp.c | 292 --- drivers/gpu/drm/i915/display/intel_dp.h | 4 - drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 +- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 14 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +- drivers/gpu/drm/i915/display/intel_dvo.c | 14 +- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 62 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 4 +- drivers/gpu/drm/i915/display/intel_lvds.c | 12 +- drivers/gpu/drm/i915/display/intel_panel.c| 14 +- drivers/gpu/drm/i915/display/intel_pipe_crc.c | 6 +- drivers/gpu/drm/i915/display/intel_psr.c | 14 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 22 +- drivers/gpu/drm/i915/display/intel_sprite.c | 25 +- drivers/gpu/drm/i915/display/intel_tv.c | 8 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 18 +- drivers/gpu/drm/i915/display/vlv_dsi.c| 20 +- drivers/gpu/drm/i915/i915_debugfs.c | 14 +- drivers/gpu/drm/i915/intel_drv.h | 36 +- drivers/gpu/drm/i915/intel_pm.c | 180 +++-- 32 files changed, 1073 insertions(+), 767 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 5/7] drm/i915/dp: Validate modes that can only be handled in a bigjoiner configuration
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_dp.c | 234 +---
drivers/gpu/drm/i915/display/intel_dp.h | 4 -
2 files changed, 130 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index b41ff88d3258..bf28970c01aa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -248,7 +248,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
}
static int
-intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
+intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp, bool
allow_bigjoiner)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = _dig_port->base;
@@ -258,6 +258,9 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+ if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11)
+ max_dotclk *= 2;
+
if (type != DP_DS_PORT_TYPE_VGA)
return max_dotclk;
@@ -493,6 +496,103 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
return 0;
}
+static u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
+{
+ u16 bits_per_pixel, max_bpp_small_joiner_ram;
+ int i;
+
+ /*
+* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
+* (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
+* FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
+* for MST -> TimeSlotsPerMTP has to be calculated
+*/
+ bits_per_pixel = (link_clock * lane_count * 8 *
+ DP_DSC_FEC_OVERHEAD_FACTOR) /
+ mode_clock;
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
+ mode_hdisplay;
+
+ if (bigjoiner)
+ max_bpp_small_joiner_ram *= 2;
+
+ /*
+* Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
+* check, output bpp from small joiner RAM check)
+*/
+ bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+
+ /* Error out if the max bpp is less than smallest allowed valid bpp */
+ if (bits_per_pixel < valid_dsc_bpp[0]) {
+ DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
+ return 0;
+ }
+
+ /* Find the nearest match in the array of known BPPs from VESA */
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
+ break;
+ }
+ bits_per_pixel = valid_dsc_bpp[i];
+
+ /*
+* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
+* fractional part is 0
+*/
+ return bits_per_pixel << 4;
+}
+
+static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
+{
+ u8 min_slice_count, i;
+ int max_slice_width;
+
+ if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_0);
+ else
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_1);
+
+ max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
+ if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
+ DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink
device\n",
+ max_slice_width);
+ return 0;
+ }
+ /* Also take into account max slice width */
+ min_slice_count = min_t(u8, min_slice_count,
+ DIV_ROUND_UP(mode_hdisplay,
+max_slice_width));
+
+ /* Find the closest match to the valid slice count values */
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
+ u8 test_slice_count = bigjoiner ?
+ 2 * valid_dsc_slicecount[i] :
+ valid_dsc_slicecount[i];
+
+ if (test_slice_count >
+ drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
+ break;
+
+ /* big joiner needs small joiner to be enabled */
+ if (bigjoiner && test_slice_count < 4)
+ continue;
+
+ if (min_slice_count <= test_slice_count)
+ return test_slice_count;
+ }
[Intel-gfx] [RFC 6/7] drm/i915: Try to make bigjoiner work in atomic check.
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the planes in software, no hardware programming is
done yet.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 145 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++-
drivers/gpu/drm/i915/intel_drv.h | 6 +
3 files changed, 168 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d8e63f133a62..ca72058202f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12203,6 +12203,47 @@ static void copy_hw_to_uapi_state(struct
intel_crtc_state *crtc_state)
crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
}
+static int
+copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
+ const struct intel_crtc_state *from_crtc_state)
+{
+ struct intel_crtc_state *saved_state;
+
+ saved_state = kmemdup(from_crtc_state, sizeof(*saved_state),
GFP_KERNEL);
+ if (!saved_state)
+ return -ENOMEM;
+
+ saved_state->uapi = crtc_state->uapi;
+ saved_state->scaler_state = crtc_state->scaler_state;
+ saved_state->shared_dpll = crtc_state->shared_dpll;
+ saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
+ saved_state->crc_enabled = crtc_state->crc_enabled;
+
+ intel_crtc_free_hw_state(crtc_state);
+ memcpy(crtc_state, saved_state, sizeof(*crtc_state));
+ kfree(saved_state);
+
+ /* Re-init hw state */
+ memset(_state->hw, 0, sizeof(saved_state->hw));
+ crtc_state->hw.enable = from_crtc_state->hw.enable;
+ crtc_state->hw.active = from_crtc_state->hw.active;
+ crtc_state->hw.mode = from_crtc_state->hw.mode;
+ crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
+
+ /* Some fixups */
+ crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
+ crtc_state->uapi.connectors_changed =
from_crtc_state->uapi.connectors_changed;
+ crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
+ crtc_state->nv12_planes = crtc_state->c8_planes =
crtc_state->update_planes = 0;
+
+ crtc_state->bigjoiner_master_crtc =
to_intel_crtc(from_crtc_state->uapi.crtc);
+
+ /* XXX/TODO: Do we need the master's cpu_transcoder here, or reset to
default? */
+ crtc_state->cpu_transcoder = (enum
transcoder)to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+
+ return 0;
+}
+
static int
clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
{
@@ -13577,6 +13618,96 @@ static void intel_crtc_check_fastset(const struct
intel_crtc_state *old_crtc_sta
new_crtc_state->has_drrs = old_crtc_state->has_drrs;
}
+static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state,
*slave_crtc_state, *master_crtc_state;
+ struct intel_crtc *crtc, *slave, *master;
+ int i, ret = 0;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return 0;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (!old_crtc_state->bigjoiner_master_crtc)
+ continue;
+
+ if (crtc->pipe == PIPE_A) {
+ DRM_ERROR("Bigjoiner slave on pipe A?\n");
+ return -EINVAL;
+ }
+
+ /* crtc staying in slave mode? */
+ if (!new_crtc_state->uapi.enable)
+ continue;
+
+ if (needs_modeset(new_crtc_state) ||
new_crtc_state->update_pipe) {
+ master = intel_get_crtc_for_pipe(dev_priv, crtc->pipe -
1);
+ master_crtc_state =
intel_atomic_get_crtc_state(>base, master);
+ if (IS_ERR(master_crtc_state))
+ return PTR_ERR(master_crtc_state);
+
+ /*
+* Force modeset on master, to recalculate bigjoiner
+* state.
+*
+* If master_crtc_state was not part of the atomic
commit,
+* we will fail because the master was not deconfigured,
+* but at least fail below to unify the checks.
+*/
+ master_crtc_state->uapi.mode_changed = true;
+
+ ret = drm_atomic_add_affected_planes(>base,
>base);
+ if (ret)
+ return ret;
+
+ ret =
[Intel-gfx] [RFC 7/7] drm/i915: Allow vdsc functions to be called without encoder.
This can be useful when calling the vdsc enable functions
directly without encoder.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 419a77723894..f009524ab735 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -897,7 +897,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
u32 dss_ctl1_val = 0;
@@ -910,9 +910,11 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_display_power_get(dev_priv,
intel_dsc_power_domain(crtc_state));
- intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ if (encoder) {
+ intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
- intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+ intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+ }
if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
dss_ctl1_reg = DSS_CTL1;
--
2.20.1
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Use caller provided forcewake for intel_mocs_init_engine
== Series Details == Series: series starting with [1/3] drm/i915/gt: Use caller provided forcewake for intel_mocs_init_engine URL : https://patchwork.freedesktop.org/series/63082/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1d27975cb696 drm/i915/gt: Use caller provided forcewake for intel_mocs_init_engine 1809163e1416 drm/i915/gt: Assume we hold forcewake for execlists resume -:35: ERROR:SPACING: spaces required around that '=' (ctx:WxV) #35: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:2088: + mode =_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE); ^ total: 1 errors, 0 warnings, 0 checks, 41 lines checked df165e394f84 drm/i915/gt: Ignore forcewake acquisition for posting_reads ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH stable-4.9+] drm/i915/dmc: protect against reading random memory
commit bc7b488b1d1c71dc4c5182206911127bc6c410d6 upstream.
While loading the DMC firmware we were double checking the headers made
sense, but in no place we checked that we were actually reading memory
we were supposed to. This could be wrong in case the firmware file is
truncated or malformed.
Before this patch:
# ls -l /lib/firmware/i915/icl_dmc_ver1_07.bin
-rw-r--r-- 1 root root 25716 Feb 1 12:26 icl_dmc_ver1_07.bin
# truncate -s 25700 /lib/firmware/i915/icl_dmc_ver1_07.bin
# modprobe i915
# dmesg| grep -i dmc
[drm:intel_csr_ucode_init [i915]] Loading i915/icl_dmc_ver1_07.bin
[drm] Finished loading DMC firmware i915/icl_dmc_ver1_07.bin (v1.7)
i.e. it loads random data. Now it fails like below:
[drm:intel_csr_ucode_init [i915]] Loading i915/icl_dmc_ver1_07.bin
[drm:csr_load_work_fn [i915]] *ERROR* Truncated DMC firmware, rejecting.
i915 :00:02.0: Failed to load DMC firmware
i915/icl_dmc_ver1_07.bin. Disabling runtime power management.
i915 :00:02.0: DMC firmware homepage:
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915
Before reading any part of the firmware file, validate the input first.
Fixes: eb805623d8b1 ("drm/i915/skl: Add support to load SKL CSR firmware.")
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190605235535.17791-1-lucas.demar...@intel.com
(cherry picked from commit bc7b488b1d1c71dc4c5182206911127bc6c410d6)
Signed-off-by: Jani Nikula
[ Lucas: backported to 4.9+ adjusting the context ]
Cc: sta...@vger.kernel.org # v4.9+
---
drivers/gpu/drm/i915/intel_csr.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1ea0e1f43397..54d878cb458f 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -280,10 +280,17 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
uint32_t i;
uint32_t *dmc_payload;
uint32_t required_version;
+ size_t fsize;
if (!fw)
return NULL;
+ fsize = sizeof(struct intel_css_header) +
+ sizeof(struct intel_package_header) +
+ sizeof(struct intel_dmc_header);
+ if (fsize > fw->size)
+ goto error_truncated;
+
/* Extract CSS Header information*/
css_header = (struct intel_css_header *)fw->data;
if (sizeof(struct intel_css_header) !=
@@ -349,6 +356,9 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
return NULL;
}
readcount += dmc_offset;
+ fsize += dmc_offset;
+ if (fsize > fw->size)
+ goto error_truncated;
/* Extract dmc_header information. */
dmc_header = (struct intel_dmc_header *)>data[readcount];
@@ -379,6 +389,10 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
nbytes = dmc_header->fw_size * 4;
+ fsize += nbytes;
+ if (fsize > fw->size)
+ goto error_truncated;
+
if (nbytes > CSR_MAX_FW_SIZE) {
DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
return NULL;
@@ -392,6 +406,10 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
}
return memcpy(dmc_payload, >data[readcount], nbytes);
+
+error_truncated:
+ DRM_ERROR("Truncated DMC firmware, rejecting.\n");
+ return NULL;
}
static void csr_load_work_fn(struct work_struct *work)
--
2.21.0
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[Intel-gfx] ✓ Fi.CI.IGT: success for Extend BT2020 support in iCSC and fixes (rev5)
== Series Details == Series: Extend BT2020 support in iCSC and fixes (rev5) URL : https://patchwork.freedesktop.org/series/60480/ State : success == Summary == CI Bug Log - changes from CI_DRM_6379_full -> Patchwork_13466_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13466_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-apl2/igt@gem_soft...@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-apl3/igt@gem_soft...@noreloc-s3.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103665] / [fdo#108767]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-kbl2/igt@i915_susp...@sysfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-kbl1/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([fdo#103540]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-hsw7/igt@kms_cursor_...@pipe-b-cursor-256x256-onscreen.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-hsw6/igt@kms_cursor_...@pipe-b-cursor-256x256-onscreen.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-skl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-skl10/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-skl6/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: - shard-glk: [PASS][17] -> [DMESG-FAIL][18] ([fdo#105763] / [fdo#106538]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-glk7/igt@kms_rotation_...@multiplane-rotation-cropping-bottom.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-glk1/igt@kms_rotation_...@multiplane-rotation-cropping-bottom.html Possible fixes * igt@i915_selftest@mock_requests: - shard-skl: [INCOMPLETE][19] ([fdo#110550]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-skl9/igt@i915_selftest@mock_requests.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-skl4/igt@i915_selftest@mock_requests.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-kbl3/igt@i915_susp...@debugfs-reader.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/shard-kbl3/igt@i915_susp...@debugfs-reader.html * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-b: - shard-snb: [SKIP][23] ([fdo#109271] / [fdo#109278]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/shard-snb5/igt@kms_b...@extended-modeset-hang-oldfb-with-reset-render-b.html [24]:
[Intel-gfx] [PATCH i-g-t] i915/gem_create: Show number of pages cleared
Just a little bit of feedback at the end of an otherwise quiet 20s.
Signed-off-by: Chris Wilson
---
tests/i915/gem_create.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index 9008cd8a2..aed7d1cec 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -187,6 +187,7 @@ struct thread_clear {
static void *thread_clear(void *data)
{
struct thread_clear *arg = data;
+ unsigned long checked = 0;
int i915 = arg->i915;
igt_until_timeout(arg->timeout) {
@@ -209,11 +210,12 @@ static void *thread_clear(void *data)
igt_assert_eq_u64(x, 0);
}
gem_close(i915, create.handle);
+ checked += npages;
atomic_fetch_add(>max, npages);
}
- return NULL;
+ return (void *)(uintptr_t)checked;
}
static void always_clear(int i915, int timeout)
@@ -224,12 +226,19 @@ static void always_clear(int i915, int timeout)
.max = intel_get_avail_ram_mb() << (20 - 12), /* in pages */
};
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
+ unsigned long checked;
pthread_t thread[ncpus];
+ void *result;
for (int i = 0; i < ncpus; i++)
pthread_create([i], NULL, thread_clear, );
- for (int i = 0; i < ncpus; i++)
- pthread_join(thread[i], NULL);
+
+ checked = 0;
+ for (int i = 0; i < ncpus; i++) {
+ pthread_join(thread[i], );
+ checked += (uintptr_t)result;
+ }
+ igt_info("Checked %'lu page allocations\n", checked);
}
static void size_update(int fd)
--
2.20.1
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Exploratory patch for fi-icl-dsi (rev2)
== Series Details == Series: drm/i915/display: Exploratory patch for fi-icl-dsi (rev2) URL : https://patchwork.freedesktop.org/series/63069/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6396 -> Patchwork_13492 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13492 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13492, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13492: ### IGT changes ### Possible regressions * igt@runner@aborted: - fi-cml-u: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/fi-cml-u/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_13492 that come from known issues: ### IGT changes ### Issues hit * igt@core_auth@basic-auth: - fi-icl-u3: [PASS][2] -> [DMESG-WARN][3] ([fdo#107724]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-u3/igt@core_a...@basic-auth.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/fi-icl-u3/igt@core_a...@basic-auth.html * igt@gem_ctx_create@basic-files: - fi-icl-guc: [PASS][4] -> [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: [PASS][6] -> [INCOMPLETE][7] ([fdo#107718]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-cml-u: [PASS][8] -> [DMESG-WARN][9] ([fdo#111012]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-cml-u/igt@i915_pm_...@basic-pci-d3-state.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/fi-cml-u/igt@i915_pm_...@basic-pci-d3-state.html Possible fixes * igt@gem_basic@create-close: - fi-icl-u3: [DMESG-WARN][10] ([fdo#107724]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-u3/igt@gem_ba...@create-close.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/fi-icl-u3/igt@gem_ba...@create-close.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [INCOMPLETE][12] ([fdo#108602]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-skl-iommu/igt@i915_selftest@live_blt.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/fi-skl-iommu/igt@i915_selftest@live_blt.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][14] ([fdo#103167]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 Participating hosts (56 -> 46) -- Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus Build changes - * Linux: CI_DRM_6396 -> Patchwork_13492 CI_DRM_6396: f6747e7cc19107131922db8fdeabc6c09d812300 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13492: 9744eaa0a76fa7ad1ef9abd1d854505e9bb31281 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13492/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules,
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Vulkan performance query support (rev6)
== Series Details == Series: drm/i915: Vulkan performance query support (rev6) URL : https://patchwork.freedesktop.org/series/60916/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6390_full -> Patchwork_13480_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13480_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13480_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13480_full: ### IGT changes ### Possible regressions * igt@perf@blocking: - shard-hsw: [PASS][1] -> [DMESG-WARN][2] +12 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-hsw8/igt@p...@blocking.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-hsw7/igt@p...@blocking.html * igt@perf@create-destroy-userspace-config: - shard-glk: [PASS][3] -> [DMESG-WARN][4] +12 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-glk9/igt@p...@create-destroy-userspace-config.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-glk7/igt@p...@create-destroy-userspace-config.html * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-skl: [PASS][5] -> [DMESG-WARN][6] +10 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-skl9/igt@p...@gen8-unprivileged-single-ctx-counters.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-skl5/igt@p...@gen8-unprivileged-single-ctx-counters.html * igt@perf@invalid-oa-exponent: - shard-iclb: [PASS][7] -> [DMESG-WARN][8] +12 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-iclb2/igt@p...@invalid-oa-exponent.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-iclb8/igt@p...@invalid-oa-exponent.html * igt@perf@invalid-oa-format-id: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] +12 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-kbl3/igt@p...@invalid-oa-format-id.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-kbl1/igt@p...@invalid-oa-format-id.html - shard-hsw: NOTRUN -> [DMESG-WARN][11] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-hsw1/igt@p...@invalid-oa-format-id.html * igt@perf@invalid-oa-metric-set-id: - shard-skl: [PASS][12] -> [INCOMPLETE][13] +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-skl1/igt@p...@invalid-oa-metric-set-id.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-skl7/igt@p...@invalid-oa-metric-set-id.html * igt@perf@low-oa-exponent-permissions: - shard-apl: [PASS][14] -> [DMESG-WARN][15] +11 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-apl8/igt@p...@low-oa-exponent-permissions.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-apl6/igt@p...@low-oa-exponent-permissions.html * igt@runner@aborted: - shard-hsw: NOTRUN -> [FAIL][16] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-hsw4/igt@run...@aborted.html - shard-kbl: NOTRUN -> [FAIL][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-kbl1/igt@run...@aborted.html - shard-iclb: NOTRUN -> [FAIL][18] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-iclb1/igt@run...@aborted.html - shard-apl: NOTRUN -> [FAIL][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-apl1/igt@run...@aborted.html Warnings * igt@perf@blocking: - shard-skl: [FAIL][20] ([fdo#110728]) -> [DMESG-WARN][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-skl10/igt@p...@blocking.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-skl3/igt@p...@blocking.html Known issues Here are the changes found in Patchwork_13480_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_await@wide-contexts: - shard-iclb: [PASS][22] -> [FAIL][23] ([fdo#110769] / [fdo#110946]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-iclb1/igt@gem_exec_aw...@wide-contexts.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13480/shard-iclb2/igt@gem_exec_aw...@wide-contexts.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: [PASS][24] -> [DMESG-WARN][25] ([fdo#108566]) +1 similar issue [24]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with drm/i915/gem: Free pages before rcu-freeing the object (rev2)
== Series Details ==
Series: series starting with drm/i915/gem: Free pages before rcu-freeing the
object (rev2)
URL : https://patchwork.freedesktop.org/series/63076/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6396 -> Patchwork_13491
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_13491 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13491, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13491/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13491:
### IGT changes ###
Warnings
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [INCOMPLETE][1] ([fdo#110976]) -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13491/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
Known issues
Here are the changes found in Patchwork_13491 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_basic@create-close:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-u3/igt@gem_ba...@create-close.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13491/fi-icl-u3/igt@gem_ba...@create-close.html
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13491/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_blt:
- fi-skl-iommu: [INCOMPLETE][7] ([fdo#108602]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-skl-iommu/igt@i915_selftest@live_blt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13491/fi-skl-iommu/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13491/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Warnings
* igt@i915_selftest@live_contexts:
- fi-skl-gvtdvm: [INCOMPLETE][11] ([fdo#110976]) -> [DMESG-FAIL][12]
([fdo#110458])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13491/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110458]: https://bugs.freedesktop.org/show_bug.cgi?id=110458
[fdo#110976]: https://bugs.freedesktop.org/show_bug.cgi?id=110976
Participating hosts (56 -> 47)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6396 -> Patchwork_13491
CI_DRM_6396: f6747e7cc19107131922db8fdeabc6c09d812300 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13491: a57f30504214c460a45fb68bd9ce0daf06df6a69 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13491/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Rework some interrupt handling functions to take intel_gt
On 7/2/19 4:45 AM, Tvrtko Ursulin wrote:
On 02/07/2019 11:34, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-07-02 11:23:11)
From: Tvrtko Ursulin
Some interrupt handling functions already have gt in their names
suggesting them as obvious candidates to make them take struct intel_gt
instead of i915.
Signed-off-by: Paulo Zanoni
Co-authored-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
static void
-gen11_other_irq_handler(struct drm_i915_private * const i915,
- const u8 instance, const u16 iir)
+gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
+ const u16 iir)
{
+ struct drm_i915_private *i915 = gt->i915;
+
if (instance == OTHER_GUC_INSTANCE)
return gen11_guc_irq_handler(i915, iir);
That looks like a candidate for gt as well. Even for the guc, the
interrupt vector is GT centric. I was hoping we could place guc/ parallel
to gt/, but it looks like it will indeed be a child of intel_gt.
Yeah. Daniele will deal with the GuC code paths.
Reviewed-by: Chris Wilson
Thanks. I'll also let Daniele comment on whether this refactoring fits
with his work before merging it.
Yup, works for me. On the whole series:
Acked-by: Daniele Ceraolo Spurio
Daniele
Regards,
Tvrtko
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
== Series Details == Series: drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+ URL : https://patchwork.freedesktop.org/series/63074/ State : success == Summary == CI Bug Log - changes from CI_DRM_6396 -> Patchwork_13490 Summary --- **WARNING** Minor unknown changes coming with Patchwork_13490 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13490, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13490: ### IGT changes ### Warnings * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: [INCOMPLETE][1] ([fdo#110976]) -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html Known issues Here are the changes found in Patchwork_13490 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-blb-e6850/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@kms_addfb_basic@tile-pitch-mismatch: - fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-u3/igt@kms_addfb_ba...@tile-pitch-mismatch.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-icl-u3/igt@kms_addfb_ba...@tile-pitch-mismatch.html Possible fixes * igt@gem_basic@create-close: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-u3/igt@gem_ba...@create-close.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-icl-u3/igt@gem_ba...@create-close.html * igt@gem_ctx_create@basic-files: - fi-icl-dsi: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [INCOMPLETE][11] ([fdo#108602]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-skl-iommu/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/fi-skl-iommu/igt@i915_selftest@live_blt.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#110976]: https://bugs.freedesktop.org/show_bug.cgi?id=110976 Participating hosts (56 -> 46) -- Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6396 -> Patchwork_13490 CI_DRM_6396: f6747e7cc19107131922db8fdeabc6c09d812300 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13490: 4f21a937a4bd44dd48b1e2271e1a1d0552de3a4e @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 4f21a937a4bd drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13490/ ___ Intel-gfx mailing list
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] Revert "drm/i915: Introduce private PAT management"
== Series Details == Series: series starting with [1/2] Revert "drm/i915: Introduce private PAT management" URL : https://patchwork.freedesktop.org/series/63065/ State : success == Summary == CI Bug Log - changes from CI_DRM_6396 -> Patchwork_13489 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13489/ Known issues Here are the changes found in Patchwork_13489 that come from known issues: ### IGT changes ### Issues hit * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][1] -> [DMESG-WARN][2] ([fdo#102614]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13489/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_basic@create-close: - fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-icl-u3/igt@gem_ba...@create-close.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13489/fi-icl-u3/igt@gem_ba...@create-close.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [INCOMPLETE][5] ([fdo#108602]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-skl-iommu/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13489/fi-skl-iommu/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][7] ([fdo#109485]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6396/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13489/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 Participating hosts (56 -> 45) -- Missing(11): fi-kbl-soraka fi-ilk-m540 fi-skl-gvtdvm fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus Build changes - * Linux: CI_DRM_6396 -> Patchwork_13489 CI_DRM_6396: f6747e7cc19107131922db8fdeabc6c09d812300 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5079: 873df2fa9e8f5fd02d4532b30ef2579f4fe4f27f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13489: 5773f32698c7086d39d55abcd281723a7c396a45 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13489/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 5773f32698c7 drm/i915/gtt: Don't check PPGTT presence on PPGTT-only platforms 73077b75c985 Revert "drm/i915: Introduce private PAT management" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13489/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] Revert "drm/i915: Introduce private PAT management"
== Series Details == Series: series starting with [1/2] Revert "drm/i915: Introduce private PAT management" URL : https://patchwork.freedesktop.org/series/63065/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: Revert "drm/i915: Introduce private PAT management" -drivers/gpu/drm/i915/i915_gem_gtt.c:349:14: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gem_gtt.c:349:14: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:349:14: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:349:14: warning: expression using sizeof(void) Commit: drm/i915/gtt: Don't check PPGTT presence on PPGTT-only platforms Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] Revert "drm/i915: Introduce private PAT management"
== Series Details ==
Series: series starting with [1/2] Revert "drm/i915: Introduce private PAT
management"
URL : https://patchwork.freedesktop.org/series/63065/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
73077b75c985 Revert "drm/i915: Introduce private PAT management"
-:267: WARNING:LONG_LINE_COMMENT: line over 100 characters
#267: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:3066:
+ pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for
normal objects, no eLLC */
-:268: WARNING:LONG_LINE_COMMENT: line over 100 characters
#268: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:3067:
+ GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for
something pointing to ptes? */
-:270: WARNING:LONG_LINE_COMMENT: line over 100 characters
#270: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:3069:
+ GEN8_PPAT(3, GEN8_PPAT_UC) | /*
Uncached objects, mostly for scanout */
total: 0 errors, 3 warnings, 0 checks, 381 lines checked
5773f32698c7 drm/i915/gtt: Don't check PPGTT presence on PPGTT-only platforms
-:15: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 4bdafb9ddfa4 ("drm/i915: Remove
i915.enable_ppgtt override")'
#15:
References: 4bdafb9ddfa4 ("drm/i915: Remove i915.enable_ppgtt override")
-:54: WARNING:LONG_LINE_COMMENT: line over 100 characters
#54: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:3051:
+ GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for
something pointing to ptes? */
-:56: WARNING:LONG_LINE_COMMENT: line over 100 characters
#56: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:3053:
+ GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached
objects, mostly for scanout */
total: 1 errors, 2 warnings, 0 checks, 47 lines checked
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[Intel-gfx] [PATCH v2] drm/i915: synchronize_irq() against the actual irq
From: Ville Syrjälä
When eliminating our use of drm_irq_install() I failed to convert
all our synchronize_irq() calls to consult pdev->irq instead of
dev_priv->drm.irq. As we no longer populate dev_priv->drm.irq
we're no longer synchronizing against anything.
v2: Add intel_syncrhonize_irq() (Chris)
Cc: Chris Wilson
Reported-by: Imre Deak
Fixes: b318b82455bd ("drm/i915: Nuke drm_driver irq vfuncs")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111012
Reviewed-by: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
drivers/gpu/drm/i915/i915_irq.c| 10 +-
drivers/gpu/drm/i915/i915_irq.h| 5 +
drivers/gpu/drm/i915/intel_guc_log.c | 2 +-
7 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 86a38116dc3a..c19b958461ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1158,7 +1158,7 @@ static void vlv_display_power_well_deinit(struct
drm_i915_private *dev_priv)
spin_unlock_irq(_priv->irq_lock);
/* make sure we're done processing display irqs */
- synchronize_irq(dev_priv->drm.irq);
+ intel_synchronize_irq(dev_priv);
intel_power_sequencer_reset(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 1e2c4307d05a..9a48f7a01e7e 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -667,5 +667,5 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc
*intel_crtc)
I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
POSTING_READ(PIPE_CRC_CTL(crtc->index));
- synchronize_irq(dev_priv->drm.irq);
+ intel_synchronize_irq(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d1508f0b4c84..c1fb5fa3952e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1162,7 +1162,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
if (execlists_active(>execlists)) {
struct tasklet_struct *t = >execlists.tasklet;
- synchronize_hardirq(engine->i915->drm.irq);
+ synchronize_hardirq(engine->i915->drm.pdev->irq);
local_bh_disable();
if (tasklet_trylock(t)) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index eeecdad0e3ca..6340cec733d2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4081,7 +4081,7 @@ static int i915_hpd_storm_ctl_show(struct seq_file *m,
void *data)
/* Synchronize with everything first in case there's been an HPD
* storm, but we haven't finished handling it in the kernel yet
*/
- synchronize_irq(dev_priv->drm.irq);
+ intel_synchronize_irq(dev_priv);
flush_work(_priv->hotplug.dig_port_work);
flush_work(_priv->hotplug.hotplug_work);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 73f0338faf9f..b5724ad38bf5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -580,7 +580,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
spin_unlock_irq(_priv->irq_lock);
- synchronize_irq(dev_priv->drm.irq);
+ intel_synchronize_irq(dev_priv);
/* Now that we will not be generating any more work, flush any
* outstanding tasks. As we are called on the RPS idle path,
@@ -627,7 +627,7 @@ void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv)
gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
spin_unlock_irq(_priv->irq_lock);
- synchronize_irq(dev_priv->drm.irq);
+ intel_synchronize_irq(dev_priv);
gen9_reset_guc_interrupts(dev_priv);
}
@@ -663,7 +663,7 @@ void gen11_disable_guc_interrupts(struct drm_i915_private
*dev_priv)
I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
spin_unlock_irq(_priv->irq_lock);
- synchronize_irq(dev_priv->drm.irq);
+ intel_synchronize_irq(dev_priv);
gen11_reset_guc_interrupts(dev_priv);
}
@@ -3680,7 +3680,7 @@ void gen8_irq_power_well_pre_disable(struct
drm_i915_private *dev_priv,
spin_unlock_irq(_priv->irq_lock);
/* make sure we're done processing display irqs */
- synchronize_irq(dev_priv->drm.irq);
+ intel_synchronize_irq(dev_priv);
}
static void
Re: [Intel-gfx] [PATCH] drm/i915: synchronize_irq() against the actual irq
On Tue, Jul 02, 2019 at 03:58:46PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-07-02 15:49:47)
> > From: Ville Syrjälä
> >
> > When eliminating our use of drm_irq_install() I failed to convert
> > all our synchronize_irq() calls to consult pdev->irq instead of
> > dev_priv->drm.irq. As we no longer populate dev_priv->drm.irq
> > we're no longer synchronizing against anything.
> >
> > Cc: Chris Wilson
> > Reported-by: Imre Deak
> > Fixes: b318b82455bd ("drm/i915: Nuke drm_driver irq vfuncs")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111012
> > Signed-off-by: Ville Syrjälä
>
> Oops.
>
> Lots of duplication there, I don't think an
>
> static inline void intel_synchronize_irq(struct drm_i915_private *i915)
> {
> synchronize_irq(i915->drm.pdev->irq);
> }
>
> (intel_ or i915_ depending on taste)
>
> would go amiss. Sadly kernel/irq/irqdesc.c doesn't report a bogus irq
> number or else we could have marked the drm.irq as bad.
>
> Kudos to Imre for figuring out the link as that bug report had been
> worrying me, and never once did I suspect it was the irq serialisation.
The wakeref count tracking gave the clue and then what the common thing
on the path could be for HSW..ICL (probably not irq_reset()!) :)
>
> All callsites converted,
> Reviewed-by: Chris Wilson
> -Chris
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Re: [Intel-gfx] [CI] drm/i915: Fix memleak in runtime wakeref tracking
Quoting Mika Kuoppala (2019-07-01 11:44:42)
> If we untrack wakerefs, the actual count may reach zero.
> However the krealloced owners array is still there and
> needs to be taken care of. Free the owners unconditionally
> to fix the leak.
>
> Fixes: bd780f37a361 ("drm/i915: Track all held rpm wakerefs")
> Reported-by: Juha-Pekka Heikkila
> Cc: Juha-Pekka Heikkila
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
> Reviewed-by: Chris Wilson
And pushed so that we can rule out any undue influence elsewhere in CI.
Thanks for catching my mistake,
-Chris
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[Intel-gfx] [PATCH 3/3] drm/i915/gt: Ignore forcewake acquisition for posting_reads
We don't care about the result of the read, so it may be garbage, we only care that the mmio is flushed. As such, we can forgo using an individual forcewake and lock around any posting-read for an engine. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 557b08b13feb..0331e9ac2485 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -51,7 +51,7 @@ struct drm_printer; #define ENGINE_READ16(...) __ENGINE_READ_OP(read16, __VA_ARGS__) #define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__) #define ENGINE_READ_FW(...)__ENGINE_READ_OP(read_fw, __VA_ARGS__) -#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read, __VA_ARGS__) +#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__) #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__) #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/gt: Assume we hold forcewake for execlists resume
We can assume the caller is holding a blanket forcewake for the
register writes during resume, and so we can skip taking individual
locks around each write inside execlists resume.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 953b3938a85f..94caf0f58fef 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2076,22 +2076,23 @@ static int intel_init_workaround_bb(struct
intel_engine_cs *engine)
static void enable_execlists(struct intel_engine_cs *engine)
{
+ u32 mode;
+
+ assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
+
intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
if (INTEL_GEN(engine->i915) >= 11)
- ENGINE_WRITE(engine,
-RING_MODE_GEN7,
-_MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+ mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
else
- ENGINE_WRITE(engine,
-RING_MODE_GEN7,
-_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+ mode =_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
+ ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode);
- ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
+ ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
- ENGINE_WRITE(engine,
-RING_HWS_PGA,
-i915_ggtt_offset(engine->status_page.vma));
+ ENGINE_WRITE_FW(engine,
+ RING_HWS_PGA,
+ i915_ggtt_offset(engine->status_page.vma));
ENGINE_POSTING_READ(engine, RING_HWS_PGA);
}
@@ -2099,7 +2100,7 @@ static bool unexpected_starting_state(struct
intel_engine_cs *engine)
{
bool unexpected = false;
- if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
+ if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
unexpected = true;
}
--
2.20.1
___
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[Intel-gfx] [PATCH 1/3] drm/i915/gt: Use caller provided forcewake for intel_mocs_init_engine
During post-reset resume, we call intel_mocs_init_engine to reinitialise
the MOCS registers. Suprisingly, especially when enhanced by lockdep,
the acquisition of the forcewake lock around each register write takes a
substantial portion of the reset time. We don't need to use the
individual forcewake here as we can assume that the caller is holding a
blanket forcewake for the reset and the resume is serialised.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index ae6cbf0d517c..290a5e9b90b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -346,6 +346,9 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unsigned int index;
u32 unused_value;
+ /* Called under a blanket forcewake */
+ assert_forcewakes_active(uncore, FORCEWAKE_ALL);
+
if (!get_mocs_settings(gt, ))
return;
@@ -355,16 +358,16 @@ void intel_mocs_init_engine(struct intel_engine_cs
*engine)
for (index = 0; index < table.size; index++) {
u32 value = get_entry_control(, index);
- intel_uncore_write(uncore,
- mocs_register(engine->id, index),
- value);
+ intel_uncore_write_fw(uncore,
+ mocs_register(engine->id, index),
+ value);
}
/* All remaining entries are also unused */
for (; index < table.n_entries; index++)
- intel_uncore_write(uncore,
- mocs_register(engine->id, index),
- unused_value);
+ intel_uncore_write_fw(uncore,
+ mocs_register(engine->id, index),
+ unused_value);
}
/**
--
2.20.1
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[Intel-gfx] [PATCH] drm/i915: synchronize_irq() against the actual irq
From: Ville Syrjälä
When eliminating our use of drm_irq_install() I failed to convert
all our synchronize_irq() calls to consult pdev->irq instead of
dev_priv->drm.irq. As we no longer populate dev_priv->drm.irq
we're no longer synchronizing against anything.
Cc: Chris Wilson
Reported-by: Imre Deak
Fixes: b318b82455bd ("drm/i915: Nuke drm_driver irq vfuncs")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111012
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
drivers/gpu/drm/i915/i915_irq.c| 10 +-
drivers/gpu/drm/i915/intel_guc_log.c | 2 +-
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 86a38116dc3a..118b0808f77a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1158,7 +1158,7 @@ static void vlv_display_power_well_deinit(struct
drm_i915_private *dev_priv)
spin_unlock_irq(_priv->irq_lock);
/* make sure we're done processing display irqs */
- synchronize_irq(dev_priv->drm.irq);
+ synchronize_irq(dev_priv->drm.pdev->irq);
intel_power_sequencer_reset(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 1e2c4307d05a..aa975834f4dc 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -667,5 +667,5 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc
*intel_crtc)
I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
POSTING_READ(PIPE_CRC_CTL(crtc->index));
- synchronize_irq(dev_priv->drm.irq);
+ synchronize_irq(dev_priv->drm.pdev->irq);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d1508f0b4c84..c1fb5fa3952e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1162,7 +1162,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
if (execlists_active(>execlists)) {
struct tasklet_struct *t = >execlists.tasklet;
- synchronize_hardirq(engine->i915->drm.irq);
+ synchronize_hardirq(engine->i915->drm.pdev->irq);
local_bh_disable();
if (tasklet_trylock(t)) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index eeecdad0e3ca..781d7dcaa1bf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4081,7 +4081,7 @@ static int i915_hpd_storm_ctl_show(struct seq_file *m,
void *data)
/* Synchronize with everything first in case there's been an HPD
* storm, but we haven't finished handling it in the kernel yet
*/
- synchronize_irq(dev_priv->drm.irq);
+ synchronize_irq(dev_priv->drm.pdev->irq);
flush_work(_priv->hotplug.dig_port_work);
flush_work(_priv->hotplug.hotplug_work);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 73f0338faf9f..0230ef43fb12 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -580,7 +580,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
spin_unlock_irq(_priv->irq_lock);
- synchronize_irq(dev_priv->drm.irq);
+ synchronize_irq(dev_priv->drm.pdev->irq);
/* Now that we will not be generating any more work, flush any
* outstanding tasks. As we are called on the RPS idle path,
@@ -627,7 +627,7 @@ void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv)
gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
spin_unlock_irq(_priv->irq_lock);
- synchronize_irq(dev_priv->drm.irq);
+ synchronize_irq(dev_priv->drm.pdev->irq);
gen9_reset_guc_interrupts(dev_priv);
}
@@ -663,7 +663,7 @@ void gen11_disable_guc_interrupts(struct drm_i915_private
*dev_priv)
I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
spin_unlock_irq(_priv->irq_lock);
- synchronize_irq(dev_priv->drm.irq);
+ synchronize_irq(dev_priv->drm.pdev->irq);
gen11_reset_guc_interrupts(dev_priv);
}
@@ -3680,7 +3680,7 @@ void gen8_irq_power_well_pre_disable(struct
drm_i915_private *dev_priv,
spin_unlock_irq(_priv->irq_lock);
/* make sure we're done processing display irqs */
- synchronize_irq(dev_priv->drm.irq);
+ synchronize_irq(dev_priv->drm.pdev->irq);
}
static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
@@ -4970,7
Re: [Intel-gfx] [PATCH] drm/i915: synchronize_irq() against the actual irq
Quoting Ville Syrjala (2019-07-02 15:49:47)
> From: Ville Syrjälä
>
> When eliminating our use of drm_irq_install() I failed to convert
> all our synchronize_irq() calls to consult pdev->irq instead of
> dev_priv->drm.irq. As we no longer populate dev_priv->drm.irq
> we're no longer synchronizing against anything.
>
> Cc: Chris Wilson
> Reported-by: Imre Deak
> Fixes: b318b82455bd ("drm/i915: Nuke drm_driver irq vfuncs")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111012
> Signed-off-by: Ville Syrjälä
Oops.
Lots of duplication there, I don't think an
static inline void intel_synchronize_irq(struct drm_i915_private *i915)
{
synchronize_irq(i915->drm.pdev->irq);
}
(intel_ or i915_ depending on taste)
would go amiss. Sadly kernel/irq/irqdesc.c doesn't report a bogus irq
number or else we could have marked the drm.irq as bad.
Kudos to Imre for figuring out the link as that bug report had been
worrying me, and never once did I suspect it was the irq serialisation.
All callsites converted,
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix memleak in runtime wakeref tracking
== Series Details == Series: drm/i915: Fix memleak in runtime wakeref tracking URL : https://patchwork.freedesktop.org/series/63031/ State : success == Summary == CI Bug Log - changes from CI_DRM_6390_full -> Patchwork_13479_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13479_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-apl7/igt@gem_workarou...@suspend-resume-context.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-apl4/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@i2c: - shard-hsw: [PASS][3] -> [FAIL][4] ([fdo#104097]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-hsw8/igt@i915_pm_...@i2c.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-hsw1/igt@i915_pm_...@i2c.html * igt@i915_suspend@sysfs-reader: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-skl3/igt@i915_susp...@sysfs-reader.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-skl8/igt@i915_susp...@sysfs-reader.html * igt@kms_color@pipe-b-legacy-gamma-reset: - shard-snb: [PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-snb5/igt@kms_co...@pipe-b-legacy-gamma-reset.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-snb1/igt@kms_co...@pipe-b-legacy-gamma-reset.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-random: - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([fdo#103540]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-hsw4/igt@kms_cursor_...@pipe-a-cursor-64x64-random.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-hsw2/igt@kms_cursor_...@pipe-a-cursor-64x64-random.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#110741]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge: - shard-snb: [PASS][13] -> [SKIP][14] ([fdo#109271] / [fdo#109278]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-snb5/igt@kms_cursor_edge_w...@pipe-a-64x64-bottom-edge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-snb1/igt@kms_cursor_edge_w...@pipe-a-64x64-bottom-edge.html * igt@kms_flip@basic-flip-vs-modeset: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#103313] / [fdo#105345]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-kbl3/igt@kms_f...@basic-flip-vs-modeset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-kbl2/igt@kms_f...@basic-flip-vs-modeset.html * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible: - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-iclb4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-iclb7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-iclb6/igt@kms_frontbuffer_track...@fbc-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-iclb7/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109642]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-iclb2/igt@kms_psr2_su@page_flip.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13479/shard-iclb6/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) [25]:
[Intel-gfx] [PATCH i-g-t] i915/gem_eio: Assert the hanging request is correctly identified
When forcing a reset, it is crucial that the kernel correctly identifies
the injected hang. Verify this is the case for reset-stress.
Signed-off-by: Chris Wilson
---
Keep the igt_spin_free at the end to avoid issues where we fail to
bypass the guilty batch.
---
tests/i915/gem_eio.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index 5396a04e2..dc7afb0fd 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -175,7 +175,7 @@ static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
unsigned long flags)
struct igt_spin_factory opts = {
.ctx = ctx,
.engine = flags,
- .flags = IGT_SPIN_FAST,
+ .flags = IGT_SPIN_FAST | IGT_SPIN_FENCE_OUT,
};
if (gem_can_store_dword(fd, opts.engine))
@@ -270,12 +270,12 @@ static void check_wait(int fd, uint32_t bo, unsigned int
wait, igt_stats_t *st)
igt_stats_push(st, igt_nsec_elapsed());
}
-static void check_wait_elapsed(int fd, igt_stats_t *st)
+static void check_wait_elapsed(const char *prefix, int fd, igt_stats_t *st)
{
double med, max, limit;
- igt_info("Completed %d resets, wakeups took %.3f+-%.3fms (min:%.3fms,
median:%.3fms, max:%.3fms)\n",
-st->n_values,
+ igt_info("%s: completed %d resets, wakeups took %.3f+-%.3fms
(min:%.3fms, median:%.3fms, max:%.3fms)\n",
+prefix, st->n_values,
igt_stats_get_mean(st)*1e-6,
igt_stats_get_std_deviation(st)*1e-6,
igt_stats_get_min(st)*1e-6,
@@ -715,8 +715,8 @@ static void test_inflight_internal(int fd, unsigned int
wait)
close(fd);
}
-static void reset_stress(int fd,
-uint32_t ctx0, unsigned int engine,
+static void reset_stress(int fd, uint32_t ctx0,
+const char *name, unsigned int engine,
unsigned int flags)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -759,6 +759,7 @@ static void reset_stress(int fd,
/* Wedge after a small delay. */
check_wait(fd, obj.handle, 100e3, );
+ igt_assert_eq(sync_fence_status(hang->out_fence), -EIO);
/* Unwedge by forcing a reset. */
igt_assert(i915_reset_control(true));
@@ -782,7 +783,7 @@ static void reset_stress(int fd,
igt_spin_free(fd, hang);
gem_context_destroy(fd, ctx);
}
- check_wait_elapsed(fd, );
+ check_wait_elapsed(name, fd, );
igt_stats_fini();
gem_close(fd, obj.handle);
@@ -797,7 +798,7 @@ static void test_reset_stress(int fd, unsigned int flags)
unsigned int engine;
for_each_engine(fd, engine)
- reset_stress(fd, ctx0, engine, flags);
+ reset_stress(fd, ctx0, e__->name, engine, flags);
gem_context_destroy(fd, ctx0);
}
--
2.20.1
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[Intel-gfx] [PATCH] drm/i915/display: Handle lost primary_port across suspend
icl-dsi is dying on suspend/resume at
RIP: 0010:icl_update_active_dpll+0x2c/0xa0 [i915]
which appears due to the loss of the time primary_port across suspend.
Protect against the potential NULL dereference by assuming
ICL_PORT_DPLL_DEFAULT unless the port is actively specified otherwise.
Fixes: 24a7bfe0c2d7 ("drm/i915: Keep the TypeC port mode fixed when the port is
active")
Signed-off-by: Chris Wilson
Reviewed-by: Imre Deak
---
With a chance that this might be a good enough fix, tidy up the
changelog in preparation!
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 76a2c879efc2..f953971e7c3b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2883,21 +2883,16 @@ static void icl_update_active_dpll(struct
intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_digital_port *primary_port;
- enum icl_port_dpll_id port_dpll_id;
+ enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
enc_to_mst(>base)->primary :
enc_to_dig_port(>base);
- switch (primary_port->tc_mode) {
- case TC_PORT_TBT_ALT:
- port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- break;
- case TC_PORT_DP_ALT:
- case TC_PORT_LEGACY:
+ if (primary_port &&
+ (primary_port->tc_mode == TC_PORT_DP_ALT ||
+primary_port->tc_mode == TC_PORT_LEGACY))
port_dpll_id = ICL_PORT_DPLL_MG_PHY;
- break;
- }
icl_set_active_port_dpll(crtc_state, port_dpll_id);
}
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/12] drm/i915/guc: Avoid reclaim locks during reset
== Series Details == Series: series starting with [01/12] drm/i915/guc: Avoid reclaim locks during reset URL : https://patchwork.freedesktop.org/series/63029/ State : success == Summary == CI Bug Log - changes from CI_DRM_6390_full -> Patchwork_13478_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13478_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-snb: [PASS][1] -> [DMESG-WARN][2] ([fdo#102365]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-snb7/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-snb1/igt@gem_ctx_isolat...@rcs0-s3.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-apl8/igt@i915_susp...@sysfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-apl2/igt@i915_susp...@sysfs-reader.html * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][5] -> [FAIL][6] ([fdo#103060]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-glk5/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-glk7/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff: - shard-hsw: [PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-hsw7/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-onoff.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-hsw2/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-cur-indfb-onoff.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-skl10/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-skl8/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping: - shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-apl5/igt@kms_pl...@pixel-format-pipe-c-planes-source-clamping.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-apl2/igt@kms_pl...@pixel-format-pipe-c-planes-source-clamping.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-iclb2/igt@kms_psr2_su@page_flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-iclb6/igt@kms_psr2_su@page_flip.html * igt@kms_setmode@basic: - shard-apl: [PASS][19] -> [FAIL][20] ([fdo#99912]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-apl4/igt@kms_setm...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-apl8/igt@kms_setm...@basic.html * igt@kms_sysfs_edid_timing: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#100047]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-iclb5/igt@kms_sysfs_edid_timing.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-iclb3/igt@kms_sysfs_edid_timing.html Possible fixes * igt@gem_exec_schedule@preemptive-hang-vebox: - shard-iclb: [INCOMPLETE][23] ([fdo#107713]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6390/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-vebox.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13478/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-vebox.html *
Re: [Intel-gfx] [PATCH] drm/i915/display: Exploratory patch for fi-icl-dsi
On Tue, Jul 02, 2019 at 01:33:26PM +0100, Chris Wilson wrote:
> icl-dsi is dying on suspend/resume at
>
> RIP: 0010:icl_update_active_dpll+0x2c/0xa0 [i915]
>
> so take a guess that it is the primary_port is NULL.
Yes, DSI ports are not intel_digital_ports but use the shared DPLL code.
Not sure why this wasn't caught already earlier.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 -
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 76a2c879efc2..f953971e7c3b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2883,21 +2883,16 @@ static void icl_update_active_dpll(struct
> intel_atomic_state *state,
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_digital_port *primary_port;
> - enum icl_port_dpll_id port_dpll_id;
> + enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
>
> primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
> enc_to_mst(>base)->primary :
> enc_to_dig_port(>base);
>
> - switch (primary_port->tc_mode) {
> - case TC_PORT_TBT_ALT:
> - port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> - break;
> - case TC_PORT_DP_ALT:
> - case TC_PORT_LEGACY:
> + if (primary_port &&
> + (primary_port->tc_mode == TC_PORT_DP_ALT ||
> + primary_port->tc_mode == TC_PORT_LEGACY))
> port_dpll_id = ICL_PORT_DPLL_MG_PHY;
> - break;
> - }
>
> icl_set_active_port_dpll(crtc_state, port_dpll_id);
> }
> --
> 2.20.1
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 1/2] drm: report dp downstream port type as a subconnector property
Hi Oleg, On Mon, 1 Jul 2019 at 09:00, Oleg Vasilev wrote: > > Currently, downstream port type is only reported in debugfs. This > information should be considered important since it reflects the actual > physical connector type. Some userspace (e.g. window compositors) > may want to show this info to a user. > > The 'subconnector' property is already utilized for DVI-I and TV-out for > reporting connector subtype. > > The initial motivation for this feature came from i2c test [1]. > It is supposed to be skipped on VGA connectors, but it cannot > detect VGA over DP and fails instead. > > [1]: https://bugs.freedesktop.org/show_bug.cgi?id=104097 > Signed-off-by: Oleg Vasilev > --- > drivers/gpu/drm/drm_connector.c | 38 +++-- > drivers/gpu/drm/drm_dp_helper.c | 36 +++ > include/drm/drm_connector.h | 2 ++ > include/drm/drm_dp_helper.h | 3 +++ > include/drm/drm_mode_config.h | 6 ++ > include/uapi/drm/drm_mode.h | 22 --- > 6 files changed, 97 insertions(+), 10 deletions(-) > Can you please update other drivers to make use of this - quick grep shows 5-10 in total. if only i915 does this, then the point of making this uAPI is very meh. Think user-space having per-vendor quirks for KMS. While KMS should be vendor agnostic. -Emil ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gem: Free pages before rcu-freeing the object
As we have dropped the final reference to the object, we do not need to
wait until after the rcu grace period to drop its pages. We still require
struct_mutex to completely unbind the object to release the pages, so we
still need a free-worker to manage that from process context. By
scheduling the release of pages before waiting for the rcu should mean
that we are not trapping those pages from beyond the reach of the
shrinker.
v2: Pass along the request to skip if the vma is busy to the underlying
unbind routine, to avoid checking the reservation underneath the
i915->mm.obj_lock which may be used from inside irq context.
v3: Flip the bit for unbinding while active, for later convenience.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111035
Fixes: a93615f900bd ("drm/i915: Throw away the active object retirement
complexity")
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 82 +---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 18 +++--
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 15 ++--
drivers/gpu/drm/i915/i915_gem.c | 8 +-
6 files changed, 67 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 43194fbcbc2e..d3e96f09c6b7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -146,6 +146,18 @@ void i915_gem_close_object(struct drm_gem_object *gem,
struct drm_file *file)
}
}
+static void __i915_gem_free_object_rcu(struct rcu_head *head)
+{
+ struct drm_i915_gem_object *obj =
+ container_of(head, typeof(*obj), rcu);
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+
+ i915_gem_object_free(obj);
+
+ GEM_BUG_ON(!atomic_read(>mm.free_count));
+ atomic_dec(>mm.free_count);
+}
+
static void __i915_gem_free_objects(struct drm_i915_private *i915,
struct llist_node *freed)
{
@@ -168,22 +180,6 @@ static void __i915_gem_free_objects(struct
drm_i915_private *i915,
GEM_BUG_ON(!list_empty(>vma.list));
GEM_BUG_ON(!RB_EMPTY_ROOT(>vma.tree));
- /*
-* This serializes freeing with the shrinker. Since the free
-* is delayed, first by RCU then by the workqueue, we want the
-* shrinker to be able to free pages of unreferenced objects,
-* or else we may oom whilst there are plenty of deferred
-* freed objects.
-*/
- if (i915_gem_object_has_pages(obj) &&
- i915_gem_object_is_shrinkable(obj)) {
- unsigned long flags;
-
- spin_lock_irqsave(>mm.obj_lock, flags);
- list_del_init(>mm.link);
- spin_unlock_irqrestore(>mm.obj_lock, flags);
- }
-
mutex_unlock(>drm.struct_mutex);
GEM_BUG_ON(atomic_read(>bind_count));
@@ -197,19 +193,15 @@ static void __i915_gem_free_objects(struct
drm_i915_private *i915,
atomic_set(>mm.pages_pin_count, 0);
__i915_gem_object_put_pages(obj, I915_MM_NORMAL);
GEM_BUG_ON(i915_gem_object_has_pages(obj));
+ bitmap_free(obj->bit_17);
if (obj->base.import_attach)
drm_prime_gem_destroy(>base, NULL);
drm_gem_object_release(>base);
- bitmap_free(obj->bit_17);
- i915_gem_object_free(obj);
-
- GEM_BUG_ON(!atomic_read(>mm.free_count));
- atomic_dec(>mm.free_count);
-
- cond_resched();
+ /* But keep the pointer alive for RCU-protected lookups */
+ call_rcu(>rcu, __i915_gem_free_object_rcu);
}
intel_runtime_pm_put(>runtime_pm, wakeref);
}
@@ -260,18 +252,34 @@ static void __i915_gem_free_work(struct work_struct *work)
spin_unlock(>mm.free_lock);
}
-static void __i915_gem_free_object_rcu(struct rcu_head *head)
+void i915_gem_free_object(struct drm_gem_object *gem_obj)
{
- struct drm_i915_gem_object *obj =
- container_of(head, typeof(*obj), rcu);
+ struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
struct drm_i915_private *i915 = to_i915(obj->base.dev);
/*
-* We reuse obj->rcu for the freed list, so we had better not treat
-* it like a rcu_head from this point forwards. And we expect all
-* objects to be freed via this path.
+* Before we free the object, make sure any pure RCU-only
+* read-side critical sections are complete, e.g.
+* i915_gem_busy_ioctl(). For the corresponding synchronized
+* lookup see
[Intel-gfx] [PATCH 4/4] drm/i915/selftests: Lock the drm_mm while modifying
Remember to lock the drm_mm as we modify it, lest it be modified in the
background by retire/free workers!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index a1f0b235f56b..9b05bef15023 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -414,7 +414,9 @@ static int igt_mmap_offset_exhaustion(void *arg)
drm_mm_for_each_hole(hole, mm, hole_start, hole_end) {
resv.start = hole_start;
resv.size = hole_end - hole_start - 1; /* PAGE_SIZE units */
+ mutex_lock(>drm.struct_mutex);
err = drm_mm_reserve_node(mm, );
+ mutex_unlock(>drm.struct_mutex);
if (err) {
pr_err("Failed to trim VMA manager, err=%d\n", err);
goto out_park;
@@ -478,7 +480,9 @@ static int igt_mmap_offset_exhaustion(void *arg)
}
out:
+ mutex_lock(>drm.struct_mutex);
drm_mm_remove_node();
+ mutex_unlock(>drm.struct_mutex);
out_park:
restore_retire_worker(i915);
return err;
--
2.20.1
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[Intel-gfx] [PATCH 2/4] drm/i915: Markup potential lock for i915_active
Make the lockchains more deterministic via i915_active by flagging the potential lock. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_active.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c index 584b247df9bc..13f304a29fc8 100644 --- a/drivers/gpu/drm/i915/i915_active.c +++ b/drivers/gpu/drm/i915/i915_active.c @@ -268,6 +268,8 @@ int i915_active_wait(struct i915_active *ref) int err; might_sleep(); + might_lock(>mutex); + if (RB_EMPTY_ROOT(>tree)) return 0; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm/i915/gem: Free pages before rcu-freeing the object
As we have dropped the final reference to the object, we do not need to
wait until after the rcu grace period to drop its pages. We still require
struct_mutex to completely unbind the object to release the pages, so we
still need a free-worker to manage that from process context. By
scheduling the release of pages before waiting for the rcu should mean
that we are not trapping those pages from beyond the reach of the
shrinker.
v2: Pass along the request to skip if the vma is busy to the underlying
unbind routine, to avoid checking the reservation underneath the
i915->mm.obj_lock which may be used from inside irq context.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111035
Fixes: a93615f900bd ("drm/i915: Throw away the active object retirement
complexity")
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 82 +---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 18 +++--
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 15 ++--
drivers/gpu/drm/i915/i915_gem.c | 9 ++-
6 files changed, 67 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 43194fbcbc2e..d3e96f09c6b7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -146,6 +146,18 @@ void i915_gem_close_object(struct drm_gem_object *gem,
struct drm_file *file)
}
}
+static void __i915_gem_free_object_rcu(struct rcu_head *head)
+{
+ struct drm_i915_gem_object *obj =
+ container_of(head, typeof(*obj), rcu);
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+
+ i915_gem_object_free(obj);
+
+ GEM_BUG_ON(!atomic_read(>mm.free_count));
+ atomic_dec(>mm.free_count);
+}
+
static void __i915_gem_free_objects(struct drm_i915_private *i915,
struct llist_node *freed)
{
@@ -168,22 +180,6 @@ static void __i915_gem_free_objects(struct
drm_i915_private *i915,
GEM_BUG_ON(!list_empty(>vma.list));
GEM_BUG_ON(!RB_EMPTY_ROOT(>vma.tree));
- /*
-* This serializes freeing with the shrinker. Since the free
-* is delayed, first by RCU then by the workqueue, we want the
-* shrinker to be able to free pages of unreferenced objects,
-* or else we may oom whilst there are plenty of deferred
-* freed objects.
-*/
- if (i915_gem_object_has_pages(obj) &&
- i915_gem_object_is_shrinkable(obj)) {
- unsigned long flags;
-
- spin_lock_irqsave(>mm.obj_lock, flags);
- list_del_init(>mm.link);
- spin_unlock_irqrestore(>mm.obj_lock, flags);
- }
-
mutex_unlock(>drm.struct_mutex);
GEM_BUG_ON(atomic_read(>bind_count));
@@ -197,19 +193,15 @@ static void __i915_gem_free_objects(struct
drm_i915_private *i915,
atomic_set(>mm.pages_pin_count, 0);
__i915_gem_object_put_pages(obj, I915_MM_NORMAL);
GEM_BUG_ON(i915_gem_object_has_pages(obj));
+ bitmap_free(obj->bit_17);
if (obj->base.import_attach)
drm_prime_gem_destroy(>base, NULL);
drm_gem_object_release(>base);
- bitmap_free(obj->bit_17);
- i915_gem_object_free(obj);
-
- GEM_BUG_ON(!atomic_read(>mm.free_count));
- atomic_dec(>mm.free_count);
-
- cond_resched();
+ /* But keep the pointer alive for RCU-protected lookups */
+ call_rcu(>rcu, __i915_gem_free_object_rcu);
}
intel_runtime_pm_put(>runtime_pm, wakeref);
}
@@ -260,18 +252,34 @@ static void __i915_gem_free_work(struct work_struct *work)
spin_unlock(>mm.free_lock);
}
-static void __i915_gem_free_object_rcu(struct rcu_head *head)
+void i915_gem_free_object(struct drm_gem_object *gem_obj)
{
- struct drm_i915_gem_object *obj =
- container_of(head, typeof(*obj), rcu);
+ struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
struct drm_i915_private *i915 = to_i915(obj->base.dev);
/*
-* We reuse obj->rcu for the freed list, so we had better not treat
-* it like a rcu_head from this point forwards. And we expect all
-* objects to be freed via this path.
+* Before we free the object, make sure any pure RCU-only
+* read-side critical sections are complete, e.g.
+* i915_gem_busy_ioctl(). For the corresponding synchronized
+* lookup see i915_gem_object_lookup_rcu().
*/
- destroy_rcu_head(>rcu);
+
[Intel-gfx] [PATCH 3/4] drm/i915: Mark up vma->active as safe for use inside shrinkers
Since a shrinker may be forced to wait on GPU activity,
i915_active_wait(>active) must be safe for use inside a shrinker,
and so let's mark up the lock as being acquired by the shrinker to avoid
any nasty surprises creeping in.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_vma.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index c20a3022cd80..ee73baf29415 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -22,6 +22,7 @@
*
*/
+#include
#include
#include "display/intel_frontbuffer.h"
@@ -120,6 +121,13 @@ vma_create(struct drm_i915_gem_object *obj,
__i915_vma_active, __i915_vma_retire);
INIT_ACTIVE_REQUEST(>last_fence);
+ /* Declare ourselves safe for use inside shrinkers */
+ if (IS_ENABLED(CONFIG_LOCKDEP)) {
+ fs_reclaim_acquire(GFP_KERNEL);
+ might_lock(>active.mutex);
+ fs_reclaim_release(GFP_KERNEL);
+ }
+
INIT_LIST_HEAD(>closed_link);
if (view && view->type != I915_GGTT_VIEW_NORMAL) {
--
2.20.1
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Extend BT2020 support in iCSC and fixes (rev5)
>-Original Message- >From: Peres, Martin >Sent: Monday, July 1, 2019 7:05 PM >To: Shankar, Uma ; intel-gfx@lists.freedesktop.org >Subject: Re: ✗ Fi.CI.BAT: failure for Extend BT2020 support in iCSC and fixes >(rev5) > >On 28/06/2019 18:06, Shankar, Uma wrote: >> >> >>> -Original Message- >>> From: Patchwork [mailto:patchw...@emeril.freedesktop.org] >>> Sent: Friday, June 28, 2019 8:34 PM >>> To: Shankar, Uma >>> Cc: intel-gfx@lists.freedesktop.org >>> Subject: ✗ Fi.CI.BAT: failure for Extend BT2020 support in iCSC and >>> fixes (rev5) >>> >>> == Series Details == >>> >>> Series: Extend BT2020 support in iCSC and fixes (rev5) >>> URL : https://patchwork.freedesktop.org/series/60480/ >>> State : failure >>> >>> == Summary == >>> >>> CI Bug Log - changes from CI_DRM_6379 -> Patchwork_13466 >>> >>> >>> Summary >>> --- >>> >>> **FAILURE** >>> >>> Serious unknown changes coming with Patchwork_13466 absolutely need >>> to be verified manually. >>> >>> If you think the reported changes have nothing to do with the >>> changes introduced in Patchwork_13466, please notify your bug team >>> to allow them to document this new failure mode, which will reduce false >positives in CI. >>> >>> External URL: >>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/ >>> >>> Possible new issues >>> --- >>> >>> Here are the unknown changes that may have been introduced in >Patchwork_13466: >>> >>> ### IGT changes ### >>> >>> Possible regressions >>> >>> * igt@i915_selftest@live_mman: >>>- fi-bsw-n3050: [PASS][1] -> [DMESG-WARN][2] >>> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/fi-bsw- >>> n3050/igt@i915_selftest@live_mman.html >>> [2]: >>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/fi-bsw- >>> n3050/igt@i915_selftest@live_mman.html >>> >> >> Hi Martin, >> This doesn't seem to be related to this change. >> >> Please check once and update this. > >New bug filed: https://bugs.freedesktop.org/show_bug.cgi?id=111037 > >I've queued re-reporting which should start the shards result. > >Thanks! Thanks Martin. CI.BAT now shows a Green, but CI.IGT result is still not generated. Should we wait or it needs to be triggered separately. We have CI.IGT a green on trybot though. Regards, Uma Shankar >Martin > >> >> Thanks & Regards, >> Uma Shankar >> >>> Known issues >>> >>> >>> Here are the changes found in Patchwork_13466 that come from known issues: >>> >>> ### IGT changes ### >>> >>> Issues hit >>> >>> * igt@i915_pm_rpm@module-reload: >>>- fi-kbl-r: [PASS][3] -> [DMESG-WARN][4] ([fdo#111012]) >>> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/fi-kbl- >>> r/igt@i915_pm_...@module-reload.html >>> [4]: >>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/fi-kbl- >>> r/igt@i915_pm_...@module-reload.html >>> >>> >>> Possible fixes >>> >>> * igt@gem_mmap_gtt@basic-write-gtt-no-prefault: >>>- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 >>> similar issue >>> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/fi-icl- >>> u3/igt@gem_mmap_...@basic-write-gtt-no-prefault.html >>> [6]: >>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/fi-icl- >>> u3/igt@gem_mmap_...@basic-write-gtt-no-prefault.html >>> >>> * igt@kms_frontbuffer_tracking@basic: >>>- fi-hsw-peppy: [DMESG-WARN][7] ([fdo#102614]) -> [PASS][8] >>> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6379/fi-hsw- >>> peppy/igt@kms_frontbuffer_track...@basic.html >>> [8]: >>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/fi-hsw- >>> peppy/igt@kms_frontbuffer_track...@basic.html >>> >>> >>> [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 >>> [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 >>> [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 >>> >>> >>> Participating hosts (51 -> 45) >>> -- >>> >>> Additional (2): fi-icl-dsi fi-skl-gvtdvm >>> Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks >>> fi-bsw-cyan fi- >icl- >>> y fi-byt-clapper fi-bdw-samus >>> >>> >>> Build changes >>> - >>> >>> * Linux: CI_DRM_6379 -> Patchwork_13466 >>> >>> CI_DRM_6379: 12f8aba06508afb9b668a2496b2fb296ed21e377 @ >>> git://anongit.freedesktop.org/gfx-ci/linux >>> IGT_5072: 5f6cf7070b249975bac4d747a9c44d81c94c4381 @ >>> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools >>> Patchwork_13466: a1cff9784bf59b14027b36876e4aaff7ab8b9599 @ >>> git://anongit.freedesktop.org/gfx-ci/linux >>> >>> >>> == Kernel 32bit build == >>> >>> Warning: Kernel 32bit buildtest failed: >>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13466/build_32bit. >>> log >>> >>> CALLscripts/checksyscalls.sh >>> CALLscripts/atomic/check-atomics.sh >>> CHK include/generated/compile.h >>> Kernel:
[Intel-gfx] [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
v2:
_MMIO_TRANS is used [Lucas and Daniel]
platform check is moved into the caller [Lucas]
v3:
platform check is moved into a macro [Shashank]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 155 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +-
drivers/gpu/drm/i915/i915_reg.h | 120 +++--
drivers/gpu/drm/i915/intel_drv.h | 8 ++
4 files changed, 221 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index bc3a94d491c4..14ba723a3561 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -17,6 +17,7 @@
#include "intel_drv.h"
#include "intel_hdcp.h"
#include "intel_sideband.h"
+#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
@@ -104,23 +105,21 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
return capable;
}
-static inline bool intel_hdcp_in_use(struct intel_connector *connector)
+static inline bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
+enum pipe pipe, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
u32 reg;
- reg = I915_READ(PORT_HDCP_STATUS(port));
+ reg = I915_READ(HDCP_STATUS(dev_priv, pipe, port));
return reg & HDCP_STATUS_ENC;
}
-static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
+static inline bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
u32 reg;
- reg = I915_READ(HDCP2_STATUS_DDI(port));
+ reg = I915_READ(HDCP2_STATUS(dev_priv, pipe, port));
return reg & LINK_ENCRYPTION_STATUS;
}
@@ -253,37 +252,59 @@ static int intel_write_sha_text(struct drm_i915_private
*dev_priv, u32 sha_text)
}
static
-u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
+u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum port port)
{
- enum port port = intel_dig_port->base.port;
- switch (port) {
- case PORT_A:
- return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
- case PORT_B:
- return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
- case PORT_C:
- return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
- case PORT_D:
- return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
- case PORT_E:
- return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
- default:
- break;
- }
- DRM_ERROR("Unknown port %d\n", port);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ switch (pipe) {
+ case PIPE_A:
+ return HDCP_TRANSA_REP_PRESENT |
+ HDCP_TRANSA_SHA1_M0;
+ case PIPE_B:
+ return HDCP_TRANSB_REP_PRESENT |
+ HDCP_TRANSB_SHA1_M0;
+ case PIPE_C:
+ return HDCP_TRANSC_REP_PRESENT |
+ HDCP_TRANSC_SHA1_M0;
+ /* FIXME: Add a case for PIPE_D */
+ default:
+ DRM_ERROR("Unknown pipe %d\n", pipe);
+ break;
+ }
+ } else {
+ switch (port) {
+ case PORT_A:
+ return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
+ case PORT_B:
+ return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
+ case PORT_C:
+ return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
+ case PORT_D:
+ return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
+ case PORT_E:
+ return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
+ default:
+ DRM_ERROR("Unknown port %d\n", port);
+ break;
+ }
+ }
return -EINVAL;
}
static
-int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
+int intel_hdcp_validate_v_prime(struct intel_connector *connector,
const struct intel_hdcp_shim *shim,
u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
{
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
struct
Re: [Intel-gfx] [PATCH 1/2] drm: report dp downstream port type as a subconnector property
On Mon, Jul 01, 2019 at 11:00:21AM +0300, Oleg Vasilev wrote:
> Currently, downstream port type is only reported in debugfs. This
> information should be considered important since it reflects the actual
> physical connector type. Some userspace (e.g. window compositors)
> may want to show this info to a user.
>
> The 'subconnector' property is already utilized for DVI-I and TV-out for
> reporting connector subtype.
>
> The initial motivation for this feature came from i2c test [1].
> It is supposed to be skipped on VGA connectors, but it cannot
> detect VGA over DP and fails instead.
>
> [1]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
> Signed-off-by: Oleg Vasilev
> ---
> drivers/gpu/drm/drm_connector.c | 38 +++--
> drivers/gpu/drm/drm_dp_helper.c | 36 +++
> include/drm/drm_connector.h | 2 ++
> include/drm/drm_dp_helper.h | 3 +++
> include/drm/drm_mode_config.h | 6 ++
> include/uapi/drm/drm_mode.h | 22 ---
> 6 files changed, 97 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 068d4b05f1be..95cd51254be6 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -793,7 +793,7 @@ static const struct drm_prop_enum_list
> drm_dvi_i_select_enum_list[] = {
> DRM_ENUM_NAME_FN(drm_get_dvi_i_select_name, drm_dvi_i_select_enum_list)
>
> static const struct drm_prop_enum_list drm_dvi_i_subconnector_enum_list[] = {
> - { DRM_MODE_SUBCONNECTOR_Unknown, "Unknown" }, /* DVI-I and TV-out */
> + { DRM_MODE_SUBCONNECTOR_Unknown, "Unknown" }, /* DVI-I, TV-out and
> DP */
> { DRM_MODE_SUBCONNECTOR_DVID, "DVI-D" }, /* DVI-I */
> { DRM_MODE_SUBCONNECTOR_DVIA, "DVI-A" }, /* DVI-I */
> };
> @@ -810,7 +810,7 @@ static const struct drm_prop_enum_list
> drm_tv_select_enum_list[] = {
> DRM_ENUM_NAME_FN(drm_get_tv_select_name, drm_tv_select_enum_list)
>
> static const struct drm_prop_enum_list drm_tv_subconnector_enum_list[] = {
> - { DRM_MODE_SUBCONNECTOR_Unknown, "Unknown" }, /* DVI-I and TV-out */
> + { DRM_MODE_SUBCONNECTOR_Unknown, "Unknown" }, /* DVI-I, TV-out and
> DP */
> { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */
> { DRM_MODE_SUBCONNECTOR_SVIDEO,"SVIDEO"}, /* TV-out */
> { DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */
> @@ -819,6 +819,19 @@ static const struct drm_prop_enum_list
> drm_tv_subconnector_enum_list[] = {
> DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
>drm_tv_subconnector_enum_list)
>
> +static const struct drm_prop_enum_list drm_dp_subconnector_enum_list[] = {
> + { DRM_MODE_SUBCONNECTOR_Unknown, "Unknown" }, /* DVI-I, TV-out and
> DP */
> + { DRM_MODE_SUBCONNECTOR_VGA, "VGA" }, /* DP */
> + { DRM_MODE_SUBCONNECTOR_DVI, "DVI" }, /* DP */
> + { DRM_MODE_SUBCONNECTOR_HDMI, "HDMI" }, /* DP */
> + { DRM_MODE_SUBCONNECTOR_DP,"DP"}, /* DP */
> + { DRM_MODE_SUBCONNECTOR_Wireless, "Wireless" }, /* DP */
> + { DRM_MODE_SUBCONNECTOR_Native,"Native"}, /* DP */
> +};
> +
> +DRM_ENUM_NAME_FN(drm_get_dp_subconnector_name,
> + drm_dp_subconnector_enum_list)
> +
> static const struct drm_prop_enum_list hdmi_colorspaces[] = {
> /* For Default case, driver will set the colorspace */
> { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
> @@ -1128,6 +1141,27 @@ int drm_mode_create_dvi_i_properties(struct drm_device
> *dev)
> }
> EXPORT_SYMBOL(drm_mode_create_dvi_i_properties);
>
> +/**
> + * drm_mode_create_dp_properties - create DP specific connector properties
> + * @dev: DRM device
> + *
> + * Called by a driver the first time a DP connector is made.
> + */
> +void drm_mode_create_dp_properties(struct drm_device *dev)
> +{
> + struct drm_property *dp_subconnector;
> +
> + if (dev->mode_config.dp_subconnector_property)
> + return;
> +
> + dp_subconnector = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE,
> +"subconnector",
> +
> drm_dp_subconnector_enum_list,
> +
> ARRAY_SIZE(drm_dp_subconnector_enum_list));
> + dev->mode_config.dp_subconnector_property = dp_subconnector;
> +}
> +EXPORT_SYMBOL(drm_mode_create_dp_properties);
> +
> /**
> * DOC: HDMI connector properties
> *
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 0b994d083a89..63d8f0b8492c 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -662,6 +662,42 @@ void drm_dp_downstream_debug(struct seq_file *m,
> }
> EXPORT_SYMBOL(drm_dp_downstream_debug);
>
> +/**
> + * drm_dp_downstream_subconnector_type() - get DP branch
[Intel-gfx] [PATCH] drm/i915/display: Exploratory patch for fi-icl-dsi
icl-dsi is dying on suspend/resume at
RIP: 0010:icl_update_active_dpll+0x2c/0xa0 [i915]
so take a guess that it is the primary_port is NULL.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 76a2c879efc2..f953971e7c3b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2883,21 +2883,16 @@ static void icl_update_active_dpll(struct
intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_digital_port *primary_port;
- enum icl_port_dpll_id port_dpll_id;
+ enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
enc_to_mst(>base)->primary :
enc_to_dig_port(>base);
- switch (primary_port->tc_mode) {
- case TC_PORT_TBT_ALT:
- port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- break;
- case TC_PORT_DP_ALT:
- case TC_PORT_LEGACY:
+ if (primary_port &&
+ (primary_port->tc_mode == TC_PORT_DP_ALT ||
+primary_port->tc_mode == TC_PORT_LEGACY))
port_dpll_id = ICL_PORT_DPLL_MG_PHY;
- break;
- }
icl_set_active_port_dpll(crtc_state, port_dpll_id);
}
--
2.20.1
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Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
On 02/07/2019 15:30, Mika Kuoppala wrote: Lionel Landwerlin writes: The same tests failing on CFL+ platforms are also failing on ICL. Documentation doesn't list the WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but applying it fixes the same tests as CFL. Didn't find more documentation either but I have asked for the wa author for update. I've filed an issue on the register definition (maybe a week ago), so far no response. Hopefully you get luckier ;) -Lionel v2: Use only one whitelist entry (Lionel) Signed-off-by: Lionel Landwerlin Tested-by: Anuj Phogat Cc: sta...@vger.kernel.org The register offsets are the same so we can't really do harm with this so we go with the evidence, Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index b117583e38bb..a908d829d6bd 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1138,6 +1138,19 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) /* WaEnableStateCacheRedirectToCS:icl */ whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + + /* +* WaAllowPMDepthAndInvocationCountAccessFromUMD:icl +* +* This covers 4 register which are next to one another : +* - PS_INVOCATION_COUNT +* - PS_INVOCATION_COUNT_UDW +* - PS_DEPTH_COUNT +* - PS_DEPTH_COUNT_UDW +*/ + whitelist_reg_ext(w, PS_INVOCATION_COUNT, + RING_FORCE_TO_NONPRIV_RD | + RING_FORCE_TO_NONPRIV_RANGE_4); break; case VIDEO_DECODE_CLASS: -- 2.21.0.392.gf8f6787159e ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
Lionel Landwerlin writes: > The same tests failing on CFL+ platforms are also failing on ICL. > Documentation doesn't list the > WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but > applying it fixes the same tests as CFL. Didn't find more documentation either but I have asked for the wa author for update. > > v2: Use only one whitelist entry (Lionel) > > Signed-off-by: Lionel Landwerlin > Tested-by: Anuj Phogat > Cc: sta...@vger.kernel.org The register offsets are the same so we can't really do harm with this so we go with the evidence, Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index b117583e38bb..a908d829d6bd 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1138,6 +1138,19 @@ static void icl_whitelist_build(struct intel_engine_cs > *engine) > > /* WaEnableStateCacheRedirectToCS:icl */ > whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); > + > + /* > + * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl > + * > + * This covers 4 register which are next to one another : > + * - PS_INVOCATION_COUNT > + * - PS_INVOCATION_COUNT_UDW > + * - PS_DEPTH_COUNT > + * - PS_DEPTH_COUNT_UDW > + */ > + whitelist_reg_ext(w, PS_INVOCATION_COUNT, > + RING_FORCE_TO_NONPRIV_RD | > + RING_FORCE_TO_NONPRIV_RANGE_4); > break; > > case VIDEO_DECODE_CLASS: > -- > 2.21.0.392.gf8f6787159e > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
Chris Wilson writes: > Quoting Lionel Landwerlin (2019-06-28 13:07:19) >> CFL:C0+ changed the status of those registers which are now >> blacklisted by default. >> >> This is breaking a number of CTS tests on GL & Vulkan : >> >> >> KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations >> (GL) >> >> dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan) >> >> v2: Only use one whitelist entry (Lionel) > > Bspec: 14091 Sometimes we have optionally used References: BSID#0934 to mark the workaround. But it feels a tad redudant now. >> Signed-off-by: Lionel Landwerlin >> Cc: sta...@vger.kernel.org > Acked-by: Chris Wilson Reviewed-by: Mika Kuoppala ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] Revert "drm/i915: Introduce private PAT management"
Quoting Michał Winiarski (2019-07-02 12:31:48) > This reverts commit 4395890a48551982549d222d1923e2833dac47cf. > > It's been over a year since this was merged, and the actual users of > intel_ppat_get / intel_ppat_put never materialized. > > Time to remove it! > > v2: Unbreak suspend (Chris) > v3: Rebase, drop fixes tag to avoid confusion > > Signed-off-by: Michał Winiarski > Cc: Chris Wilson > Cc: Joonas Lahtinen > Cc: Rodrigo Vivi > Cc: Zhi Wang Reviewed-by: Chris Wilson While I would appreciate an ack from Zhi (being the original author), since we've already sent this a few times, there's no reason to delay waiting for a response. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Don't check PPGTT presence on PPGTT-only platforms
Quoting Michał Winiarski (2019-07-02 12:31:49)
> We missed one place where we check PPGTT-only platform for PPGTT
> presence. Let's remove it.
> While I'm here let's assert that this particular code is never called on
> pre-gen8 platforms.
>
> References: 4bdafb9ddfa4 ("drm/i915: Remove i915.enable_ppgtt override")
> Signed-off-by: Michał Winiarski
> Cc: Chris Wilson
Reviewed-by: Chris Wilson
Hazy memory says that disabling pat (making everything uncached) was
desired for some early sanity checks. Hmm, there might be scope in here
for some selftests (to which I mean there is definitely room for more!)
-Chris
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Rework some interrupt handling functions to take intel_gt
On 02/07/2019 11:34, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-07-02 11:23:11)
From: Tvrtko Ursulin
Some interrupt handling functions already have gt in their names
suggesting them as obvious candidates to make them take struct intel_gt
instead of i915.
Signed-off-by: Paulo Zanoni
Co-authored-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
static void
-gen11_other_irq_handler(struct drm_i915_private * const i915,
- const u8 instance, const u16 iir)
+gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
+ const u16 iir)
{
+ struct drm_i915_private *i915 = gt->i915;
+
if (instance == OTHER_GUC_INSTANCE)
return gen11_guc_irq_handler(i915, iir);
That looks like a candidate for gt as well. Even for the guc, the
interrupt vector is GT centric. I was hoping we could place guc/ parallel
to gt/, but it looks like it will indeed be a child of intel_gt.
Yeah. Daniele will deal with the GuC code paths.
Reviewed-by: Chris Wilson
Thanks. I'll also let Daniele comment on whether this refactoring fits
with his work before merging it.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH i-g-t] i915: Fix gem_context_has_engine_map() for older kernels
On 02/07/2019 11:50, Chris Wilson wrote: CI is currently breaking on linus/drm-intel-fixes due to the assert that the kernel supports context engine maps. Report the lack of maps on older kernels gracefully! Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- lib/i915/gem_engine_topology.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c index cae5a0292..cc2b3ff6e 100644 --- a/lib/i915/gem_engine_topology.c +++ b/lib/i915/gem_engine_topology.c @@ -321,10 +321,13 @@ bool gem_context_has_engine_map(int fd, uint32_t ctx) .param = I915_CONTEXT_PARAM_ENGINES, .ctx_id = ctx }; - int ret; - ret = __gem_context_get_param(fd, ); - igt_assert_eq(ret, 0); + /* +* If the kernel is too old to support PARAM_ENGINES, +* then naturally is has no engine map. +*/ + if (__gem_context_get_param(fd, )) + return false; return param.size; } Bleurgh, sorry. I even have some memories of checking ret, otherwise I wouldn't have had the local. Don't know what happened there.. Reviewed-by: Tvrtko Ursulin Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_eio: Assert the hanging request is correctly identified
When forcing a reset, it is crucial that the kernel correctly identifies
the injected hang. Verify this is the case for reset-stress.
Signed-off-by: Chris Wilson
---
tests/i915/gem_eio.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index 5396a04e2..1d75f357f 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -175,7 +175,7 @@ static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
unsigned long flags)
struct igt_spin_factory opts = {
.ctx = ctx,
.engine = flags,
- .flags = IGT_SPIN_FAST,
+ .flags = IGT_SPIN_FAST | IGT_SPIN_FENCE_OUT,
};
if (gem_can_store_dword(fd, opts.engine))
@@ -270,12 +270,12 @@ static void check_wait(int fd, uint32_t bo, unsigned int
wait, igt_stats_t *st)
igt_stats_push(st, igt_nsec_elapsed());
}
-static void check_wait_elapsed(int fd, igt_stats_t *st)
+static void check_wait_elapsed(const char *prefix, int fd, igt_stats_t *st)
{
double med, max, limit;
- igt_info("Completed %d resets, wakeups took %.3f+-%.3fms (min:%.3fms,
median:%.3fms, max:%.3fms)\n",
-st->n_values,
+ igt_info("%s: completed %d resets, wakeups took %.3f+-%.3fms
(min:%.3fms, median:%.3fms, max:%.3fms)\n",
+prefix, st->n_values,
igt_stats_get_mean(st)*1e-6,
igt_stats_get_std_deviation(st)*1e-6,
igt_stats_get_min(st)*1e-6,
@@ -715,8 +715,8 @@ static void test_inflight_internal(int fd, unsigned int
wait)
close(fd);
}
-static void reset_stress(int fd,
-uint32_t ctx0, unsigned int engine,
+static void reset_stress(int fd, uint32_t ctx0,
+const char *name, unsigned int engine,
unsigned int flags)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -759,6 +759,8 @@ static void reset_stress(int fd,
/* Wedge after a small delay. */
check_wait(fd, obj.handle, 100e3, );
+ igt_assert_eq(sync_fence_status(hang->out_fence), -EIO);
+ igt_spin_free(fd, hang);
/* Unwedge by forcing a reset. */
igt_assert(i915_reset_control(true));
@@ -779,10 +781,9 @@ static void reset_stress(int fd,
gem_execbuf(fd, );
gem_sync(fd, obj.handle);
- igt_spin_free(fd, hang);
gem_context_destroy(fd, ctx);
}
- check_wait_elapsed(fd, );
+ check_wait_elapsed(name, fd, );
igt_stats_fini();
gem_close(fd, obj.handle);
@@ -797,7 +798,7 @@ static void test_reset_stress(int fd, unsigned int flags)
unsigned int engine;
for_each_engine(fd, engine)
- reset_stress(fd, ctx0, engine, flags);
+ reset_stress(fd, ctx0, e__->name, engine, flags);
gem_context_destroy(fd, ctx0);
}
--
2.20.1
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[Intel-gfx] [PATCH 1/2] Revert "drm/i915: Introduce private PAT management"
This reverts commit 4395890a48551982549d222d1923e2833dac47cf.
It's been over a year since this was merged, and the actual users of
intel_ppat_get / intel_ppat_put never materialized.
Time to remove it!
v2: Unbreak suspend (Chris)
v3: Rebase, drop fixes tag to avoid confusion
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Zhi Wang
---
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_gem_gtt.c | 279 +---
drivers/gpu/drm/i915/i915_gem_gtt.h | 36
3 files changed, 42 insertions(+), 275 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 02dd9f9f3a89..09e09d26e67d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1489,8 +1489,6 @@ struct drm_i915_private {
DECLARE_HASHTABLE(mm_structs, 7);
struct mutex mm_lock;
- struct intel_ppat ppat;
-
/* Kernel Modesetting */
struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ff1d5008a256..30e14eac47ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3028,203 +3028,26 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt,
u64 size)
return 0;
}
-static struct intel_ppat_entry *
-__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
+static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
{
- struct intel_ppat_entry *entry = >entries[index];
-
- GEM_BUG_ON(index >= ppat->max_entries);
- GEM_BUG_ON(test_bit(index, ppat->used));
-
- entry->ppat = ppat;
- entry->value = value;
- kref_init(>ref);
- set_bit(index, ppat->used);
- set_bit(index, ppat->dirty);
-
- return entry;
-}
-
-static void __free_ppat_entry(struct intel_ppat_entry *entry)
-{
- struct intel_ppat *ppat = entry->ppat;
- unsigned int index = entry - ppat->entries;
-
- GEM_BUG_ON(index >= ppat->max_entries);
- GEM_BUG_ON(!test_bit(index, ppat->used));
-
- entry->value = ppat->clear_value;
- clear_bit(index, ppat->used);
- set_bit(index, ppat->dirty);
-}
-
-/**
- * intel_ppat_get - get a usable PPAT entry
- * @i915: i915 device instance
- * @value: the PPAT value required by the caller
- *
- * The function tries to search if there is an existing PPAT entry which
- * matches with the required value. If perfectly matched, the existing PPAT
- * entry will be used. If only partially matched, it will try to check if
- * there is any available PPAT index. If yes, it will allocate a new PPAT
- * index for the required entry and update the HW. If not, the partially
- * matched entry will be used.
- */
-const struct intel_ppat_entry *
-intel_ppat_get(struct drm_i915_private *i915, u8 value)
-{
- struct intel_ppat *ppat = >ppat;
- struct intel_ppat_entry *entry = NULL;
- unsigned int scanned, best_score;
- int i;
-
- GEM_BUG_ON(!ppat->max_entries);
-
- scanned = best_score = 0;
- for_each_set_bit(i, ppat->used, ppat->max_entries) {
- unsigned int score;
-
- score = ppat->match(ppat->entries[i].value, value);
- if (score > best_score) {
- entry = >entries[i];
- if (score == INTEL_PPAT_PERFECT_MATCH) {
- kref_get(>ref);
- return entry;
- }
- best_score = score;
- }
- scanned++;
- }
-
- if (scanned == ppat->max_entries) {
- if (!entry)
- return ERR_PTR(-ENOSPC);
-
- kref_get(>ref);
- return entry;
- }
-
- i = find_first_zero_bit(ppat->used, ppat->max_entries);
- entry = __alloc_ppat_entry(ppat, i, value);
- ppat->update_hw(i915);
- return entry;
-}
-
-static void release_ppat(struct kref *kref)
-{
- struct intel_ppat_entry *entry =
- container_of(kref, struct intel_ppat_entry, ref);
- struct drm_i915_private *i915 = entry->ppat->i915;
-
- __free_ppat_entry(entry);
- entry->ppat->update_hw(i915);
-}
-
-/**
- * intel_ppat_put - put back the PPAT entry got from intel_ppat_get()
- * @entry: an intel PPAT entry
- *
- * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the
- * entry is dynamically allocated, its reference count will be decreased. Once
- * the reference count becomes into zero, the PPAT index becomes free again.
- */
-void intel_ppat_put(const struct intel_ppat_entry *entry)
-{
- struct intel_ppat *ppat = entry->ppat;
- unsigned int index = entry - ppat->entries;
-
- GEM_BUG_ON(!ppat->max_entries);
-
- kref_put(>entries[index].ref, release_ppat);
-}
-
-static void
Re: [Intel-gfx] [PATCH v6 06/11] drm/i915: introduce a mechanism to extend execbuf2
On 01/07/2019 18:17, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:32)
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin
Looks ok, are you convinced by I915_EXEC_EXT? It doesn't roll off the
tongue too well for me, but I guess EXT is a bit more ingrained in
your cerebral cortex.
I'm open to any suggestion for the name :)
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 32 ++-
include/uapi/drm/i915_drm.h | 25 +--
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 1c5dfbfad71b..9887fa9e3ac8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -23,6 +23,7 @@
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_trace.h"
+#include "i915_user_extensions.h"
#include "intel_drv.h"
enum {
@@ -271,6 +272,10 @@ struct i915_execbuffer {
*/
int lut_size;
struct hlist_head *buckets; /** ht for relocation handles */
+
+ struct {
+ u64 flags; /** Available extensions parameters */
+ } extensions;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -1969,7 +1974,7 @@ static bool i915_gem_check_execbuffer(struct
drm_i915_gem_execbuffer2 *exec)
return false;
/* Kernel clipping was a DRI1 misfeature */
- if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
+ if (!(exec->flags & (I915_EXEC_FENCE_ARRAY | I915_EXEC_EXT))) {
if (exec->num_cliprects || exec->cliprects_ptr)
return false;
}
@@ -2347,6 +2352,27 @@ signal_fence_array(struct i915_execbuffer *eb,
}
}
+static const i915_user_extension_fn execbuf_extensions[] = {
+};
+
+static int
+parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
+ struct i915_execbuffer *eb)
+{
+ eb->extensions.flags = 0;
+
+ if (!(args->flags & I915_EXEC_EXT))
+ return 0;
+
+ if (args->num_cliprects != 0)
+ return -EINVAL;
+
+ return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
+ execbuf_extensions,
+ ARRAY_SIZE(execbuf_extensions),
+ eb);
+}
+
static int
i915_gem_do_execbuffer(struct drm_device *dev,
struct drm_file *file,
@@ -2393,6 +2419,10 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (args->flags & I915_EXEC_IS_PINNED)
eb.batch_flags |= I915_DISPATCH_PINNED;
+ err = parse_execbuf2_extensions(args, );
+ if (err)
+ return err;
+
if (args->flags & I915_EXEC_FENCE_IN) {
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
if (!in_fence)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e27a8eda9121..efa195d6994e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1013,6 +1013,10 @@ struct drm_i915_gem_exec_fence {
__u32 flags;
};
+enum drm_i915_gem_execbuffer_ext {
+ DRM_I915_GEM_EXECBUFFER_EXT_MAX /* non-ABI */
We have a weird mix of trying to avoid drm_i915_gem and yet it's
plastered all over the structs. Sigh.
Yeah, I couldn't figure out what is desired.
Happy to change it if you have a naming scheme.
+};
enums next to uABI make me nervous :)
Reviewed-by: Chris Wilson
-Chris
Thanks a lot,
-Lionel
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[Intel-gfx] [PATCH 2/2] drm/i915/gtt: Don't check PPGTT presence on PPGTT-only platforms
We missed one place where we check PPGTT-only platform for PPGTT
presence. Let's remove it.
While I'm here let's assert that this particular code is never called on
pre-gen8 platforms.
References: 4bdafb9ddfa4 ("drm/i915: Remove i915.enable_ppgtt override")
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +
1 file changed, 10 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 30e14eac47ac..9e76347e039e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3047,31 +3047,14 @@ static void bdw_setup_private_ppat(struct
drm_i915_private *dev_priv)
{
u64 pat;
- if (!HAS_PPGTT(dev_priv)) {
- /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
-* so RTL will always use the value corresponding to
-* pat_sel = 000".
-* So let's disable cache for GGTT to avoid screen corruptions.
-* MOCS still can be used though.
-* - System agent ggtt writes (i.e. cpu gtt mmaps) already work
-* before this patch, i.e. the same uncached + snooping access
-* like on gen6/7 seems to be in effect.
-* - So this just fixes blitter/render access. Again it looks
-* like it's not just uncached access, but uncached + snooping.
-* So we can still hold onto all our assumptions wrt cpu
-* clflushing on LLC machines.
-*/
- pat = GEN8_PPAT(0, GEN8_PPAT_UC);
- } else {
- pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for
normal objects, no eLLC */
- GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for
something pointing to ptes? */
- GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for
scanout with eLLC */
- GEN8_PPAT(3, GEN8_PPAT_UC) | /*
Uncached objects, mostly for scanout */
- GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(0)) |
- GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(1)) |
- GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(2)) |
- GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
GEN8_PPAT_AGE(3));
- }
+ pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal
objects, no eLLC */
+ GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for
something pointing to ptes? */
+ GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout
with eLLC */
+ GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached
objects, mostly for scanout */
+ GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0))
|
+ GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1))
|
+ GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2))
|
+ GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
@@ -3123,6 +3106,8 @@ static void gen6_gmch_remove(struct i915_address_space
*vm)
static void setup_private_pat(struct drm_i915_private *dev_priv)
{
+ GEM_BUG_ON(INTEL_GEN(dev_priv) < 8);
+
if (INTEL_GEN(dev_priv) >= 10)
cnl_setup_private_ppat(dev_priv);
else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
--
2.21.0
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: CTS fixes (rev7)
Quoting Lionel Landwerlin (2019-06-29 14:00:40) > Okay to land? Pushed with my ack. Thanks for the patches and sorry that simple changes with such clear causality take so long to get reviewed. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm: report dp downstream port type as a subconnector property
== Series Details == Series: series starting with [1/2] drm: report dp downstream port type as a subconnector property URL : https://patchwork.freedesktop.org/series/63026/ State : success == Summary == CI Bug Log - changes from CI_DRM_6389_full -> Patchwork_13477_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13477_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@universal-planes: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-apl5/igt@i915_pm_...@universal-planes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-apl5/igt@i915_pm_...@universal-planes.html - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108840]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-iclb5/igt@i915_pm_...@universal-planes.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-iclb2/igt@i915_pm_...@universal-planes.html * igt@i915_selftest@mock_requests: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#110550]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-skl1/igt@i915_selftest@mock_requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-skl7/igt@i915_selftest@mock_requests.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-glk2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-glk5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html * igt@kms_lease@atomic_implicit_crtc: - shard-snb: [PASS][15] -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-snb6/igt@kms_lease@atomic_implicit_crtc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-snb5/igt@kms_lease@atomic_implicit_crtc.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-iclb2/igt@kms_psr@psr2_no_drrs.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-iclb5/igt@kms_psr@psr2_no_drrs.html * igt@kms_setmode@basic: - shard-apl: [PASS][21] -> [FAIL][22] ([fdo#99912]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-apl1/igt@kms_setm...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-apl3/igt@kms_setm...@basic.html Possible fixes * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][23] ([fdo#108686]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6389/shard-glk8/igt@gem_tiled_swapp...@non-threaded.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13477/shard-glk3/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_pm_rpm@i2c: - shard-hsw: [FAIL][25] ([fdo#104097]) -> [PASS][26] [25]:
Re: [Intel-gfx] [PATCH] drm/i915: fix whitelist selftests with readonly registers
Quoting Chris Wilson (2019-06-29 14:13:50)
> From: Lionel Landwerlin
>
> When a register is readonly there is not much we can tell about its
> value (apart from its default value?). This can be covered by tests
> exercising the value of the register from userspace.
>
> For PS_INVOCATION_COUNT we've got the following piglit tests :
>
>
> KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
>
> Vulkan CTS tests :
>
>dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*
>
> v2: Use a local to shrink under 80cols.
>
> Signed-off-by: Lionel Landwerlin
> Fixes: 86554f48e511 ("drm/i915/selftests: Verify whitelist of context
> registers")
> Tested-by: Anuj Phogat
Reviewed-by: Chris Wilson
> Signed-off-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
Quoting Lionel Landwerlin (2019-06-28 13:07:20) > The same tests failing on CFL+ platforms are also failing on ICL. > Documentation doesn't list the > WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but > applying it fixes the same tests as CFL. > > v2: Use only one whitelist entry (Lionel) > > Signed-off-by: Lionel Landwerlin > Tested-by: Anuj Phogat > Cc: sta...@vger.kernel.org Acked-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
Quoting Lionel Landwerlin (2019-06-28 13:07:19) > CFL:C0+ changed the status of those registers which are now > blacklisted by default. > > This is breaking a number of CTS tests on GL & Vulkan : > > > KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations > (GL) > > dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan) > > v2: Only use one whitelist entry (Lionel) Bspec: 14091 > Signed-off-by: Lionel Landwerlin > Cc: sta...@vger.kernel.org Acked-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for More mmio and intel_gt cleanups and refactorings
== Series Details == Series: More mmio and intel_gt cleanups and refactorings URL : https://patchwork.freedesktop.org/series/63063/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6394 -> Patchwork_13488 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13488 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13488, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13488: ### IGT changes ### Possible regressions * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html Known issues Here are the changes found in Patchwork_13488 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-skl-iommu: [PASS][2] -> [INCOMPLETE][3] ([fdo#108602]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-skl-iommu/igt@i915_selftest@live_blt.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-skl-iommu/igt@i915_selftest@live_blt.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][4] -> [DMESG-WARN][5] ([fdo#102614]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-flip: - fi-icl-u3: [PASS][6] -> [DMESG-WARN][7] ([fdo#107724]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-icl-u3/igt@prime_v...@basic-fence-flip.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-icl-u3/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@gem_mmap_gtt@basic-small-bo-tiledy: - fi-icl-u3: [DMESG-WARN][8] ([fdo#107724]) -> [PASS][9] +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-6600u: [DMESG-WARN][10] ([fdo#111012]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live_blt: - fi-cfl-guc: [DMESG-WARN][12] ([fdo#110943]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-cfl-guc/igt@i915_selftest@live_blt.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-cfl-guc/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hugepages: - fi-skl-gvtdvm: [DMESG-WARN][14] ([fdo#110976]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-skl-gvtdvm/igt@i915_selftest@live_hugepages.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-skl-gvtdvm/igt@i915_selftest@live_hugepages.html * igt@prime_vgem@basic-fence-flip: - fi-ilk-650: [DMESG-WARN][16] ([fdo#106387]) -> [PASS][17] +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-ilk-650/igt@prime_v...@basic-fence-flip.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-ilk-650/igt@prime_v...@basic-fence-flip.html Warnings * igt@i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][18] ([fdo#111041]) -> [DMESG-WARN][19] ([fdo#110595]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-icl-u2/igt@i915_module_l...@reload.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13488/fi-icl-u2/igt@i915_module_l...@reload.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595 [fdo#110943]: https://bugs.freedesktop.org/show_bug.cgi?id=110943 [fdo#110976]: https://bugs.freedesktop.org/show_bug.cgi?id=110976 [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 [fdo#111041]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Report if i915_active is still busy upon waiting
== Series Details == Series: drm/i915: Report if i915_active is still busy upon waiting URL : https://patchwork.freedesktop.org/series/63062/ State : success == Summary == CI Bug Log - changes from CI_DRM_6394 -> Patchwork_13487 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/ Known issues Here are the changes found in Patchwork_13487 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-r: [PASS][1] -> [DMESG-WARN][2] ([fdo#111012]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-kbl-r/igt@i915_pm_...@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/fi-kbl-r/igt@i915_pm_...@basic-pci-d3-state.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@gem_mmap_gtt@basic-small-bo-tiledy: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-6600u: [DMESG-WARN][7] ([fdo#111012]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live_blt: - fi-cfl-guc: [DMESG-WARN][9] ([fdo#110943]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-cfl-guc/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/fi-cfl-guc/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hugepages: - fi-skl-gvtdvm: [DMESG-WARN][11] ([fdo#110976]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-skl-gvtdvm/igt@i915_selftest@live_hugepages.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/fi-skl-gvtdvm/igt@i915_selftest@live_hugepages.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][13] ([fdo#109485]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-fence-flip: - fi-ilk-650: [DMESG-WARN][15] ([fdo#106387]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-ilk-650/igt@prime_v...@basic-fence-flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/fi-ilk-650/igt@prime_v...@basic-fence-flip.html Warnings * igt@i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][17] ([fdo#111041]) -> [DMESG-WARN][18] ([fdo#110595]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-icl-u2/igt@i915_module_l...@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13487/fi-icl-u2/igt@i915_module_l...@reload.html [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595 [fdo#110943]: https://bugs.freedesktop.org/show_bug.cgi?id=110943 [fdo#110976]: https://bugs.freedesktop.org/show_bug.cgi?id=110976 [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 [fdo#111041]: https://bugs.freedesktop.org/show_bug.cgi?id=111041 Participating hosts (50 -> 45) -- Additional (2): fi-icl-guc fi-cml-u Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper Build changes - * Linux: CI_DRM_6394 -> Patchwork_13487 CI_DRM_6394: ad42b755acd3c10f7a8e23309189f0a850ec92c5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5075: 03779dd3de8a57544f124d9952a6d2b3e34e34ca @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13487: 218527cc609479b1186233db3b830e41dfbc310e @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More mmio and intel_gt cleanups and refactorings
Quoting Patchwork (2019-07-02 11:46:48) > == Series Details == > > Series: More mmio and intel_gt cleanups and refactorings > URL : https://patchwork.freedesktop.org/series/63063/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > a59370ad3ca8 drm/i915: Rework some interrupt handling functions to take > intel_gt > -:12: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-authored-by: > #12: > Co-authored-by: Paulo Zanoni Approved tag is "Co-developed-by" -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915: Fix gem_context_has_engine_map() for older kernels
CI is currently breaking on linus/drm-intel-fixes due to the assert that the kernel supports context engine maps. Report the lack of maps on older kernels gracefully! Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- lib/i915/gem_engine_topology.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c index cae5a0292..cc2b3ff6e 100644 --- a/lib/i915/gem_engine_topology.c +++ b/lib/i915/gem_engine_topology.c @@ -321,10 +321,13 @@ bool gem_context_has_engine_map(int fd, uint32_t ctx) .param = I915_CONTEXT_PARAM_ENGINES, .ctx_id = ctx }; - int ret; - ret = __gem_context_get_param(fd, ); - igt_assert_eq(ret, 0); + /* +* If the kernel is too old to support PARAM_ENGINES, +* then naturally is has no engine map. +*/ + if (__gem_context_get_param(fd, )) + return false; return param.size; } -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
