[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Drain the freedlists between exec passes
== Series Details ==
Series: drm/i915/selftests: Drain the freedlists between exec passes
URL : https://patchwork.freedesktop.org/series/63233/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6417_full -> Patchwork_13532_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_13532_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-apl4/igt@gem_ctx_isolat...@rcs0-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-apl6/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_fence_thrash@bo-write-verify-threaded-x:
- shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-apl8/igt@gem_fence_thr...@bo-write-verify-threaded-x.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-apl5/igt@gem_fence_thr...@bo-write-verify-threaded-x.html
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([fdo#103540])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-hsw2/igt@kms_b...@extended-pageflip-hang-newfb-render-b.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-hsw2/igt@kms_b...@extended-pageflip-hang-newfb-render-b.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-rapid-movement:
- shard-snb: [PASS][7] -> [SKIP][8] ([fdo#109271]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-snb2/igt@kms_cursor_...@pipe-a-cursor-64x64-rapid-movement.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-snb2/igt@kms_cursor_...@pipe-a-cursor-64x64-rapid-movement.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge:
- shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271] / [fdo#109278])
+1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-snb2/igt@kms_cursor_edge_w...@pipe-b-64x64-left-edge.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-snb1/igt@kms_cursor_edge_w...@pipe-b-64x64-left-edge.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-skl3/igt@kms_fbcon_...@fbc-suspend.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-skl2/igt@kms_fbcon_...@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-skl10/igt@kms_f...@flip-vs-expired-vblank.html
- shard-glk: [PASS][15] -> [FAIL][16] ([fdo#105363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-glk4/igt@kms_f...@flip-vs-expired-vblank.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-glk9/igt@kms_f...@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +4 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +3 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@perf_pmu@rc6-runtime-pm:
- shard-apl: [PASS][21] -> [FAIL][22] ([fdo#105010])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-apl7/igt@perf_...@rc6-runtime-pm.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-apl2/igt@perf_...@rc6-runtime-pm.html
Possible fixes
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +4
similar issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-apl5/igt@gem_ctx_isolat...@bcs0-s3.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13532/shard-apl5/igt@gem_ctx_isolat...@bcs0-s3.html
* {igt@gem_ctx_switch@queue-heavy}:
- shard-apl:
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gtt: pde entry encoding is identical
== Series Details == Series: series starting with [1/3] drm/i915/gtt: pde entry encoding is identical URL : https://patchwork.freedesktop.org/series/63229/ State : success == Summary == CI Bug Log - changes from CI_DRM_6417_full -> Patchwork_13531_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13531_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@reset-stress: - shard-snb: [PASS][1] -> [FAIL][2] ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-snb7/igt@gem_...@reset-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-snb4/igt@gem_...@reset-stress.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-snb: [PASS][3] -> [SKIP][4] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-snb6/igt@i915_pm_rc6_reside...@rc6-accuracy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-snb7/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-apl3/igt@i915_susp...@sysfs-reader.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-apl8/igt@i915_susp...@sysfs-reader.html * igt@kms_atomic_interruptible@universal-setplane-primary: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#103558] / [fdo#105602]) +37 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-kbl6/igt@kms_atomic_interrupti...@universal-setplane-primary.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-kbl4/igt@kms_atomic_interrupti...@universal-setplane-primary.html * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#103558] / [fdo#105602] / [fdo#110222]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-kbl6/igt@kms_b...@extended-pageflip-modeset-hang-oldfb-render-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-kbl4/igt@kms_b...@extended-pageflip-modeset-hang-oldfb-render-a.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-skl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-skl5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-render.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-render.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-y.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-iclb5/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642] / [fdo#111068]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-iclb2/igt@kms_psr2_su@page_flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-iclb1/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-iclb2/igt@kms_psr@psr2_cursor_render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-iclb7/igt@kms_psr@psr2_cursor_render.html * igt@perf@blocking: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#110728]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-skl2/igt@p...@blocking.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-skl8/igt@p...@blocking.html * igt@perf_pmu@rc6-runtime-pm: - shard-apl: [PASS][23] -> [FAIL][24] ([fdo#105010]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6417/shard-apl7/igt@perf_...@rc6-runtime-pm.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13531/shard-apl3/igt@perf_...@rc6-runtime-pm.html Possible fixes * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [DMESG-WARN][25] ([fdo#108566])
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/gtt: pde entry encoding is identical
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/gtt: pde entry encoding is
identical
URL : https://patchwork.freedesktop.org/series/63296/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6425 -> Patchwork_13551
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13551/
Known issues
Here are the changes found in Patchwork_13551 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_busy@busy-all:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_b...@busy-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13551/fi-icl-u3/igt@gem_b...@busy-all.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][3] -> [INCOMPLETE][4] ([fdo#107807])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-skl-6600u/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13551/fi-skl-6600u/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13551/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-u2: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13551/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13551/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13551/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][13] ([fdo#109485]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13551/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (55 -> 45)
--
Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6425 -> Patchwork_13551
CI_DRM_6425: 62149faa04e66d4d16166c89ba441977a0656119 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5087: f0e39642f6f8da5406627bfa79c6600df949e203 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13551: febcf6082014322aa6bc4a636ab69f88ebd01968 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13551/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
febcf6082014 drm/i915/gtt: Introduce release_pd_entry
5f8db3589c0e drm/i915/gtt: Setup phys pages for 3lvl pdps
35efc82bc1b3 drm/i915/gtt: Tear down setup and cleanup macros for page dma
cac55008fa27 drm/i915/gtt: pde entry encoding is identical
==
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915/gtt: pde entry encoding is identical
== Series Details == Series: series starting with [CI,1/4] drm/i915/gtt: pde entry encoding is identical URL : https://patchwork.freedesktop.org/series/63296/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/gtt: pde entry encoding is identical -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1610:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1610:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1584:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1584:9: warning: expression using sizeof(void) Commit: drm/i915/gtt: Tear down setup and cleanup macros for page dma Okay! Commit: drm/i915/gtt: Setup phys pages for 3lvl pdps Okay! Commit: drm/i915/gtt: Introduce release_pd_entry -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1574:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1574:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:852:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:852:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:883:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:883:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:924:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:924:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:871:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:871:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:892:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:892:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:923:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:923:9: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915/gtt: pde entry encoding is identical
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/gtt: pde entry encoding is
identical
URL : https://patchwork.freedesktop.org/series/63296/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cac55008fa27 drm/i915/gtt: pde entry encoding is identical
-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pd' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:777:
+#define init_pd(vm, pd, to) { \
+ GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));\
+ fill_px((vm), (pd), gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \
+ memset_p((pd)->entry, (to), 512); \
+}
-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'to' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:777:
+#define init_pd(vm, pd, to) { \
+ GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));\
+ fill_px((vm), (pd), gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \
+ memset_p((pd)->entry, (to), 512); \
+}
total: 0 errors, 0 warnings, 2 checks, 285 lines checked
35efc82bc1b3 drm/i915/gtt: Tear down setup and cleanup macros for page dma
5f8db3589c0e drm/i915/gtt: Setup phys pages for 3lvl pdps
febcf6082014 drm/i915/gtt: Introduce release_pd_entry
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/4] drm/i915/gtt: Setup phys pages for 3lvl pdps
From: Mika Kuoppala
If we setup backing phys page for 3lvl pdps, as they
are not used, we will lose 5 pages per ppgtt.
Trading this memory on bsw, we gain more common code paths for all
gen8+ directory manipulation. And those paths are now void of checks
for page directory type, making the hot paths faster.
v2: don't shortcut vm (Chris)
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 77 +++--
1 file changed, 50 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f011ce1ae03a..0a55b0932c86 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -758,22 +758,14 @@ static struct i915_page_directory *alloc_pd(struct
i915_address_space *vm)
return pd;
}
-static inline bool pd_has_phys_page(const struct i915_page_directory * const
pd)
-{
- return pd->base.page;
-}
-
static void free_pd(struct i915_address_space *vm,
struct i915_page_directory *pd)
{
- if (likely(pd_has_phys_page(pd)))
- cleanup_page_dma(vm, &pd->base);
-
+ cleanup_page_dma(vm, &pd->base);
kfree(pd);
}
#define init_pd(vm, pd, to) { \
- GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));\
fill_px((vm), (pd), gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \
memset_p((pd)->entry, (to), 512); \
}
@@ -1604,6 +1596,50 @@ static void ppgtt_init(struct i915_ppgtt *ppgtt, struct
intel_gt *gt)
ppgtt->vm.vma_ops.clear_pages = clear_pages;
}
+static void init_pd_n(struct i915_address_space *vm,
+ struct i915_page_directory *pd,
+ struct i915_page_directory *to,
+ const unsigned int entries)
+{
+ const u64 daddr = gen8_pde_encode(px_dma(to), I915_CACHE_LLC);
+ u64 * const vaddr = kmap_atomic(pd->base.page);
+
+ memset64(vaddr, daddr, entries);
+ kunmap_atomic(vaddr);
+
+ memset_p(pd->entry, to, entries);
+}
+
+static struct i915_page_directory *
+gen8_alloc_top_pd(struct i915_address_space *vm)
+{
+ struct i915_page_directory *pd;
+
+ if (i915_vm_is_4lvl(vm)) {
+ pd = alloc_pd(vm);
+ if (!IS_ERR(pd))
+ init_pd(vm, pd, vm->scratch_pdp);
+
+ return pd;
+ }
+
+ /* 3lvl */
+ pd = __alloc_pd();
+ if (!pd)
+ return ERR_PTR(-ENOMEM);
+
+ pd->entry[GEN8_3LVL_PDPES] = NULL;
+
+ if (unlikely(setup_page_dma(vm, &pd->base))) {
+ kfree(pd);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init_pd_n(vm, pd, vm->scratch_pd, GEN8_3LVL_PDPES);
+
+ return pd;
+}
+
/*
* GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
* with a net effect resembling a 2-level page table in normal x86 terms. Each
@@ -1640,34 +1676,21 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
if (err)
goto err_free;
- ppgtt->pd = __alloc_pd();
- if (!ppgtt->pd) {
- err = -ENOMEM;
+ ppgtt->pd = gen8_alloc_top_pd(&ppgtt->vm);
+ if (IS_ERR(ppgtt->pd)) {
+ err = PTR_ERR(ppgtt->pd);
goto err_free_scratch;
}
if (i915_vm_is_4lvl(&ppgtt->vm)) {
- err = setup_page_dma(&ppgtt->vm, &ppgtt->pd->base);
- if (err)
- goto err_free_pdp;
-
- init_pd(&ppgtt->vm, ppgtt->pd, ppgtt->vm.scratch_pdp);
-
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
} else {
- /*
-* We don't need to setup dma for top level pdp, only
-* for entries. So point entries to scratch.
-*/
- memset_p(ppgtt->pd->entry, ppgtt->vm.scratch_pd,
-GEN8_3LVL_PDPES);
-
if (intel_vgpu_active(i915)) {
err = gen8_preallocate_top_level_pdp(ppgtt);
if (err)
- goto err_free_pdp;
+ goto err_free_pd;
}
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
@@ -1682,7 +1705,7 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
return ppgtt;
-err_free_pdp:
+err_free_pd:
free_pd(&ppgtt->vm, ppgtt->pd);
err_free_scratch:
gen8_free_scratch(&ppgtt->vm);
--
2.20.1
___
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[Intel-gfx] [CI 2/4] drm/i915/gtt: Tear down setup and cleanup macros for page dma
From: Mika Kuoppala
We don't use common codepaths to setup and cleanup page
directories vs page tables. So their setup and cleanup macros
are of no use and can be removed.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index adf6eadd5009..f011ce1ae03a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -594,8 +594,6 @@ static void cleanup_page_dma(struct i915_address_space *vm,
#define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
-#define setup_px(vm, px) setup_page_dma((vm), px_base(px))
-#define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
#define fill_px(vm, px, v) fill_page_dma((vm), px_base(px), (v))
#define fill32_px(vm, px, v) fill_page_dma_32((vm), px_base(px), (v))
@@ -697,7 +695,7 @@ static struct i915_page_table *alloc_pt(struct
i915_address_space *vm)
if (unlikely(!pt))
return ERR_PTR(-ENOMEM);
- if (unlikely(setup_px(vm, pt))) {
+ if (unlikely(setup_page_dma(vm, &pt->base))) {
kfree(pt);
return ERR_PTR(-ENOMEM);
}
@@ -709,7 +707,7 @@ static struct i915_page_table *alloc_pt(struct
i915_address_space *vm)
static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt)
{
- cleanup_px(vm, pt);
+ cleanup_page_dma(vm, &pt->base);
kfree(pt);
}
@@ -752,7 +750,7 @@ static struct i915_page_directory *alloc_pd(struct
i915_address_space *vm)
if (unlikely(!pd))
return ERR_PTR(-ENOMEM);
- if (unlikely(setup_px(vm, pd))) {
+ if (unlikely(setup_page_dma(vm, &pd->base))) {
kfree(pd);
return ERR_PTR(-ENOMEM);
}
@@ -769,7 +767,7 @@ static void free_pd(struct i915_address_space *vm,
struct i915_page_directory *pd)
{
if (likely(pd_has_phys_page(pd)))
- cleanup_px(vm, pd);
+ cleanup_page_dma(vm, &pd->base);
kfree(pd);
}
@@ -1649,7 +1647,7 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
}
if (i915_vm_is_4lvl(&ppgtt->vm)) {
- err = setup_px(&ppgtt->vm, ppgtt->pd);
+ err = setup_page_dma(&ppgtt->vm, &ppgtt->pd->base);
if (err)
goto err_free_pdp;
--
2.20.1
___
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[Intel-gfx] [CI 4/4] drm/i915/gtt: Introduce release_pd_entry
From: Mika Kuoppala
By encapsulating the locking upper level and used check for entry
into a helper function, we can use it in all callsites.
v2: get rid of atomic_reads on lower level clears (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 114 ++--
1 file changed, 42 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0a55b0932c86..236c964dd761 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -811,7 +811,25 @@ __clear_pd_entry(struct i915_page_directory * const pd,
__set_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
#define clear_pd_entry(pd, pde, to) \
- __clear_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
+ __clear_pd_entry((pd), (pde), (to), gen8_pde_encode)
+
+static bool
+release_pd_entry(struct i915_page_directory * const pd,
+const unsigned short pde,
+atomic_t *counter,
+struct i915_page_dma * const scratch)
+{
+ bool free = false;
+
+ spin_lock(&pd->lock);
+ if (atomic_dec_and_test(counter)) {
+ clear_pd_entry(pd, pde, scratch);
+ free = true;
+ }
+ spin_unlock(&pd->lock);
+
+ return free;
+}
/*
* PDE TLBs are a pain to invalidate on GEN8+. When we modify
@@ -827,11 +845,11 @@ static void mark_tlbs_dirty(struct i915_ppgtt *ppgtt)
/* Removes entries from a single page table, releasing it if it's empty.
* Caller can use the return value to update higher-level entries.
*/
-static bool gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
struct i915_page_table *pt,
u64 start, u64 length)
{
- unsigned int num_entries = gen8_pte_count(start, length);
+ const unsigned int num_entries = gen8_pte_count(start, length);
gen8_pte_t *vaddr;
vaddr = kmap_atomic_px(pt);
@@ -839,10 +857,11 @@ static bool gen8_ppgtt_clear_pt(const struct
i915_address_space *vm,
kunmap_atomic(vaddr);
GEM_BUG_ON(num_entries > atomic_read(&pt->used));
- return !atomic_sub_return(num_entries, &pt->used);
+
+ atomic_sub(num_entries, &pt->used);
}
-static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_directory *pd,
u64 start, u64 length)
{
@@ -850,30 +869,20 @@ static bool gen8_ppgtt_clear_pd(struct i915_address_space
*vm,
u32 pde;
gen8_for_each_pde(pt, pd, start, length, pde) {
- bool free = false;
-
GEM_BUG_ON(pt == vm->scratch_pt);
- if (!gen8_ppgtt_clear_pt(vm, pt, start, length))
- continue;
-
- spin_lock(&pd->lock);
- if (!atomic_read(&pt->used)) {
- clear_pd_entry(pd, pde, vm->scratch_pt);
- free = true;
- }
- spin_unlock(&pd->lock);
- if (free)
+ atomic_inc(&pt->used);
+ gen8_ppgtt_clear_pt(vm, pt, start, length);
+ if (release_pd_entry(pd, pde, &pt->used,
+px_base(vm->scratch_pt)))
free_pt(vm, pt);
}
-
- return !atomic_read(&pd->used);
}
/* Removes entries from a single page dir pointer, releasing it if it's empty.
* Caller can use the return value to update higher-level entries
*/
-static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
struct i915_page_directory * const pdp,
u64 start, u64 length)
{
@@ -881,24 +890,14 @@ static bool gen8_ppgtt_clear_pdp(struct
i915_address_space *vm,
unsigned int pdpe;
gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
- bool free = false;
-
GEM_BUG_ON(pd == vm->scratch_pd);
- if (!gen8_ppgtt_clear_pd(vm, pd, start, length))
- continue;
-
- spin_lock(&pdp->lock);
- if (!atomic_read(&pd->used)) {
- clear_pd_entry(pdp, pdpe, vm->scratch_pd);
- free = true;
- }
- spin_unlock(&pdp->lock);
- if (free)
+ atomic_inc(&pd->used);
+ gen8_ppgtt_clear_pd(vm, pd, start, length);
+ if (release_pd_entry(pdp, pdpe, &pd->used,
+px_base(vm->scratch_pd)))
free_pd(vm, pd);
}
-
- return !atomic_read(&pdp->used);
}
[Intel-gfx] [CI 1/4] drm/i915/gtt: pde entry encoding is identical
From: Mika Kuoppala
For all page directory entries, the pde encoding is
identical. Don't complicate call sites with different
versions of doing the same thing, so we always check the
existence of physical page before writing the entry into
it. This further generalizes the pd so that manipulation in
callsites will be identical, removing the need to handle
pdps differently for gen8.
v2: squash
v3: inc/dec with set/clear (Chris)
v4: inlines, warn, stray set_pd (Chris)
Cc: Chris Wilson
Cc: Matthew Auld
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 152
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 -
2 files changed, 63 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 57db2d7270c5..adf6eadd5009 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -211,10 +211,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
return pte;
}
-static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
- const enum i915_cache_level level)
+static u64 gen8_pde_encode(const dma_addr_t addr,
+ const enum i915_cache_level level)
{
- gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
+ u64 pde = _PAGE_PRESENT | _PAGE_RW;
pde |= addr;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE;
@@ -223,9 +223,6 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
return pde;
}
-#define gen8_pdpe_encode gen8_pde_encode
-#define gen8_pml4e_encode gen8_pde_encode
-
static u64 snb_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
@@ -777,24 +774,55 @@ static void free_pd(struct i915_address_space *vm,
kfree(pd);
}
-static void init_pd_with_page(struct i915_address_space *vm,
- struct i915_page_directory * const pd,
- struct i915_page_table *pt)
+#define init_pd(vm, pd, to) { \
+ GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));\
+ fill_px((vm), (pd), gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \
+ memset_p((pd)->entry, (to), 512); \
+}
+
+static inline void
+write_dma_entry(struct i915_page_dma * const pdma,
+ const unsigned short pde,
+ const u64 encoded_entry)
+{
+ u64 * const vaddr = kmap_atomic(pdma->page);
+
+ vaddr[pde] = encoded_entry;
+ kunmap_atomic(vaddr);
+}
+
+static inline void
+__set_pd_entry(struct i915_page_directory * const pd,
+ const unsigned short pde,
+ struct i915_page_dma * const to,
+ u64 (*encode)(const dma_addr_t, const enum i915_cache_level))
{
- fill_px(vm, pd, gen8_pde_encode(px_dma(pt), I915_CACHE_LLC));
- memset_p(pd->entry, pt, 512);
+ GEM_BUG_ON(atomic_read(&pd->used) > 512);
+
+ atomic_inc(&pd->used);
+ pd->entry[pde] = to;
+ write_dma_entry(px_base(pd), pde, encode(to->daddr, I915_CACHE_LLC));
}
-static void init_pd(struct i915_address_space *vm,
- struct i915_page_directory * const pd,
- struct i915_page_directory * const to)
+static inline void
+__clear_pd_entry(struct i915_page_directory * const pd,
+const unsigned short pde,
+struct i915_page_dma * const to,
+u64 (*encode)(const dma_addr_t, const enum i915_cache_level))
{
- GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));
+ GEM_BUG_ON(atomic_read(&pd->used) == 0);
- fill_px(vm, pd, gen8_pdpe_encode(px_dma(to), I915_CACHE_LLC));
- memset_p(pd->entry, to, 512);
+ write_dma_entry(px_base(pd), pde, encode(to->daddr, I915_CACHE_LLC));
+ pd->entry[pde] = to;
+ atomic_dec(&pd->used);
}
+#define set_pd_entry(pd, pde, to) \
+ __set_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
+
+#define clear_pd_entry(pd, pde, to) \
+ __clear_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
+
/*
* PDE TLBs are a pain to invalidate on GEN8+. When we modify
* the page table structures, we mark them dirty so that
@@ -824,18 +852,6 @@ static bool gen8_ppgtt_clear_pt(const struct
i915_address_space *vm,
return !atomic_sub_return(num_entries, &pt->used);
}
-static void gen8_ppgtt_set_pde(struct i915_address_space *vm,
- struct i915_page_directory *pd,
- struct i915_page_table *pt,
- unsigned int pde)
-{
- gen8_pde_t *vaddr;
-
- vaddr = kmap_atomic_px(pd);
- vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC);
- kunmap_atomic(vaddr);
-}
-
static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_direc
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915: Rework some interrupt handling functions to take intel_gt
== Series Details == Series: series starting with [CI,1/3] drm/i915: Rework some interrupt handling functions to take intel_gt URL : https://patchwork.freedesktop.org/series/63225/ State : success == Summary == CI Bug Log - changes from CI_DRM_6413_full -> Patchwork_13530_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13530_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#103313] / [fdo#105345]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-kbl6/igt@i915_pm_...@modeset-non-lpsp-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-kbl2/igt@i915_pm_...@modeset-non-lpsp-stress.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-apl8/igt@i915_susp...@sysfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-apl7/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#110741]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-skl10/igt@kms_f...@flip-vs-expired-vblank.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-skl3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@plain-flip-fb-recreate: - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([fdo#103540]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-hsw1/igt@kms_f...@plain-flip-fb-recreate.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-hsw2/igt@kms_f...@plain-flip-fb-recreate.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#103167]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-skl4/igt@kms_frontbuffer_track...@psr-1p-primscrn-shrfb-msflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-skl6/igt@kms_frontbuffer_track...@psr-1p-primscrn-shrfb-msflip-blt.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-skl4/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-skl6/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-kbl6/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-kbl2/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-iclb5/igt@kms_plane_low...@pipe-a-tiling-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-iclb5/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#108341]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-iclb8/igt@kms_psr@no_drrs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6413/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13530/shard-iclb7/igt@kms_psr@psr2_cursor_plane_onoff.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Handle double alloc failures
== Series Details == Series: drm/i915/gtt: Handle double alloc failures URL : https://patchwork.freedesktop.org/series/63223/ State : success == Summary == CI Bug Log - changes from CI_DRM_6410_full -> Patchwork_13529_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13529_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@close-race: - shard-snb: [PASS][1] -> [DMESG-FAIL][2] ([fdo#111063]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-snb4/igt@gem_b...@close-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-snb4/igt@gem_b...@close-race.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#103313]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-kbl6/igt@gem_soft...@noreloc-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-kbl4/igt@gem_soft...@noreloc-s3.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][5] -> [FAIL][6] ([fdo#105363]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-glk1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-glk1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#109507]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl3/igt@kms_f...@flip-vs-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-skl2/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-apl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_setmode@basic: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#99912]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl3/igt@kms_setm...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-skl10/igt@kms_setm...@basic.html - shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-kbl3/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-kbl1/igt@kms_setm...@basic.html Possible fixes * igt@i915_selftest@mock_requests: - shard-skl: [DMESG-WARN][19] -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl9/igt@i915_selftest@mock_requests.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-skl9/igt@i915_selftest@mock_requests.html * igt@i915_suspend@sysfs-reader: - shard-hsw: [INCOMPLETE][21] ([fdo#103540]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-hsw5/igt@i915_susp...@sysfs-reader.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-hsw2/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen: - shard-iclb: [INCOMPLETE][23] ([fdo#107713]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-iclb7/igt@kms_cursor_...@pipe-a-cursor-64x21-onscreen.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13529/shard-iclb5/igt@kms_cursor_...@pipe-a-cursor-64x21-onscreen.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +5 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-apl4/igt@kms_f...@flip-vs-sus
Re: [Intel-gfx] [PATCH] drm/i915/gtt: Introduce release_pd_entry
Quoting Chris Wilson (2019-07-05 16:07:13) > From: Mika Kuoppala > > By encapsulating the locking upper level and used check for entry > into a helper function, we can use it in all callsites. > > v2: get rid of atomic_reads on lower level clears (Chris) > > Cc: Chris Wilson > Signed-off-by: Mika Kuoppala A nice bit of needless duplicity eliminated. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915/gtt: pde entry encoding is identical
Quoting Mika Kuoppala (2019-07-05 15:29:05) > For all page directory entries, the pde encoding is > identical. Don't compilicate call sites with different > versions of doing the same thing. We check the existence of > physical page before writing the entry into it. This further > generalizes the pd so that manipulation in callsites will be > identical, removing the need to handle pdps differently for gen8. > > v2: squash > v3: inc/dec with set/clear (Chris) > v4: inlines, warn, stray set_pd (Chris) > > Cc: Chris Wilson > Cc: Matthew Auld > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/gtt: pde entry encoding is identical (rev3)
== Series Details ==
Series: series starting with [1/4] drm/i915/gtt: pde entry encoding is
identical (rev3)
URL : https://patchwork.freedesktop.org/series/63284/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6425 -> Patchwork_13550
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/
Known issues
Here are the changes found in Patchwork_13550 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_render_linear_blits@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([fdo#108511])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-u2: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][13] ([fdo#111050]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][15] ([fdo#109485]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (55 -> 46)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6425 -> Patchwork_13550
CI_DRM_6425: 62149faa04e66d4d16166c89ba441977a0656119 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5087: f0e39642f6f8da5406627bfa79c6600df949e203 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13550: 3327784fcffbbd12b93280d4b64417c959eedbc6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13550/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK in
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/gtt: pde entry encoding is identical (rev3)
== Series Details == Series: series starting with [1/4] drm/i915/gtt: pde entry encoding is identical (rev3) URL : https://patchwork.freedesktop.org/series/63284/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/gtt: pde entry encoding is identical -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1610:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1610:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1584:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1584:9: warning: expression using sizeof(void) Commit: drm/i915/gtt: Tear down setup and cleanup macros for page dma Okay! Commit: drm/i915/gtt: Setup phys pages for 3lvl pdps Okay! Commit: drm/i915/gtt: Introduce release_pd_entry -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1574:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1574:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:852:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:852:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:883:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:883:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:924:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:924:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:868:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:868:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:891:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:891:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:924:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:924:9: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/gtt: pde entry encoding is identical (rev3)
== Series Details ==
Series: series starting with [1/4] drm/i915/gtt: pde entry encoding is
identical (rev3)
URL : https://patchwork.freedesktop.org/series/63284/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
44d181c48441 drm/i915/gtt: pde entry encoding is identical
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pd' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:777:
+#define init_pd(vm, pd, to) { \
+ GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));\
+ fill_px((vm), (pd), gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \
+ memset_p((pd)->entry, (to), 512); \
+}
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'to' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:777:
+#define init_pd(vm, pd, to) { \
+ GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));\
+ fill_px((vm), (pd), gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \
+ memset_p((pd)->entry, (to), 512); \
+}
total: 0 errors, 0 warnings, 2 checks, 285 lines checked
6dabe15619bc drm/i915/gtt: Tear down setup and cleanup macros for page dma
60f62dee7e02 drm/i915/gtt: Setup phys pages for 3lvl pdps
3327784fcffb drm/i915/gtt: Introduce release_pd_entry
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Clear the shared PLL from the put_dplls() hook
== Series Details ==
Series: series starting with [1/2] drm/i915: Clear the shared PLL from the
put_dplls() hook
URL : https://patchwork.freedesktop.org/series/63283/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6425 -> Patchwork_13549
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13549/
Known issues
Here are the changes found in Patchwork_13549 that come from known issues:
### IGT changes ###
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-u2: [INCOMPLETE][1] ([fdo#107713]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13549/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13549/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13549/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][7] ([fdo#109485]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13549/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (55 -> 46)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6425 -> Patchwork_13549
CI_DRM_6425: 62149faa04e66d4d16166c89ba441977a0656119 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5087: f0e39642f6f8da5406627bfa79c6600df949e203 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13549: b41cad89bcdf424e332d79366e6d428aa4fd6821 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13549/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
b41cad89bcdf drm/i915/icl: Clear the shared port PLLs from the new crtc state
d7ddd9523793 drm/i915: Clear the shared PLL from the put_dplls() hook
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13549/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix possible memory leak in intel_hdcp_auth_downstream()
== Series Details ==
Series: drm/i915: fix possible memory leak in intel_hdcp_auth_downstream()
URL : https://patchwork.freedesktop.org/series/63282/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6425 -> Patchwork_13548
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/
Known issues
Here are the changes found in Patchwork_13548 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108840])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/fi-icl-dsi/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109483] / [fdo#109635 ])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#109485])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-u2: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][15] ([fdo#111050]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][17] ([fdo#109485]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13548/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (55 -> 47)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6425 -> Patchwork_13548
CI_DRM_6425: 62149faa04e66d4d16166c89ba441977a0656119 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5087: f0e39642f6f8da5406627bfa79c6600df949e203 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13548: 0882479eccc7a632350578e47302e315285b5885 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel
[Intel-gfx] [PATCH] drm/i915/gtt: Introduce release_pd_entry
From: Mika Kuoppala
By encapsulating the locking upper level and used check for entry
into a helper function, we can use it in all callsites.
v2: get rid of atomic_reads on lower level clears (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 121 +++-
1 file changed, 47 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0a55b0932c86..dd581e038fce 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -795,10 +795,10 @@ __set_pd_entry(struct i915_page_directory * const pd,
}
static inline void
-__clear_pd_entry(struct i915_page_directory * const pd,
-const unsigned short pde,
-struct i915_page_dma * const to,
-u64 (*encode)(const dma_addr_t, const enum i915_cache_level))
+clear_pd_entry(struct i915_page_directory * const pd,
+ const unsigned short pde,
+ struct i915_page_dma * const to,
+ u64 (*encode)(const dma_addr_t, const enum i915_cache_level))
{
GEM_BUG_ON(atomic_read(&pd->used) == 0);
@@ -810,8 +810,23 @@ __clear_pd_entry(struct i915_page_directory * const pd,
#define set_pd_entry(pd, pde, to) \
__set_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
-#define clear_pd_entry(pd, pde, to) \
- __clear_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
+static bool
+release_pd_entry(struct i915_page_directory * const pd,
+const unsigned short pde,
+atomic_t *counter,
+struct i915_page_dma * const scratch)
+{
+ bool free = false;
+
+ spin_lock(&pd->lock);
+ if (atomic_dec_and_test(counter)) {
+ clear_pd_entry(pd, pde, scratch, gen8_pde_encode);
+ free = true;
+ }
+ spin_unlock(&pd->lock);
+
+ return free;
+}
/*
* PDE TLBs are a pain to invalidate on GEN8+. When we modify
@@ -827,11 +842,11 @@ static void mark_tlbs_dirty(struct i915_ppgtt *ppgtt)
/* Removes entries from a single page table, releasing it if it's empty.
* Caller can use the return value to update higher-level entries.
*/
-static bool gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
struct i915_page_table *pt,
u64 start, u64 length)
{
- unsigned int num_entries = gen8_pte_count(start, length);
+ const unsigned int num_entries = gen8_pte_count(start, length);
gen8_pte_t *vaddr;
vaddr = kmap_atomic_px(pt);
@@ -839,10 +854,11 @@ static bool gen8_ppgtt_clear_pt(const struct
i915_address_space *vm,
kunmap_atomic(vaddr);
GEM_BUG_ON(num_entries > atomic_read(&pt->used));
- return !atomic_sub_return(num_entries, &pt->used);
+
+ atomic_sub(num_entries, &pt->used);
}
-static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_directory *pd,
u64 start, u64 length)
{
@@ -850,30 +866,22 @@ static bool gen8_ppgtt_clear_pd(struct i915_address_space
*vm,
u32 pde;
gen8_for_each_pde(pt, pd, start, length, pde) {
- bool free = false;
-
GEM_BUG_ON(pt == vm->scratch_pt);
- if (!gen8_ppgtt_clear_pt(vm, pt, start, length))
- continue;
+ atomic_inc(&pt->used);
- spin_lock(&pd->lock);
- if (!atomic_read(&pt->used)) {
- clear_pd_entry(pd, pde, vm->scratch_pt);
- free = true;
- }
- spin_unlock(&pd->lock);
- if (free)
+ gen8_ppgtt_clear_pt(vm, pt, start, length);
+
+ if (release_pd_entry(pd, pde, &pt->used,
+px_base(vm->scratch_pt)))
free_pt(vm, pt);
}
-
- return !atomic_read(&pd->used);
}
/* Removes entries from a single page dir pointer, releasing it if it's empty.
* Caller can use the return value to update higher-level entries
*/
-static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
struct i915_page_directory * const pdp,
u64 start, u64 length)
{
@@ -881,24 +889,16 @@ static bool gen8_ppgtt_clear_pdp(struct
i915_address_space *vm,
unsigned int pdpe;
gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
- bool free = false;
-
GEM_BUG_ON(pd == vm->scratch_pd);
- if (!gen8_ppgtt_clear_pd(vm, pd, start, length))
- continue;
+ atomic_inc
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4] drm/i915: Check caller held wakerefs in assert_forcewakes_active (rev4)
== Series Details == Series: series starting with [v4] drm/i915: Check caller held wakerefs in assert_forcewakes_active (rev4) URL : https://patchwork.freedesktop.org/series/63151/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6410_full -> Patchwork_13528_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13528_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13528_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13528_full: ### IGT changes ### Possible regressions * igt@i915_selftest@mock_requests: - shard-glk: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-glk2/igt@i915_selftest@mock_requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-glk5/igt@i915_selftest@mock_requests.html Known issues Here are the changes found in Patchwork_13528_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@close-race: - shard-kbl: [PASS][3] -> [DMESG-FAIL][4] ([fdo#111063]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-kbl7/igt@gem_b...@close-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-kbl3/igt@gem_b...@close-race.html * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-apl5/igt@gem_ctx_isolat...@bcs0-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-apl1/igt@gem_ctx_isolat...@bcs0-s3.html * igt@i915_pm_rpm@gem-execbuf-stress: - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([fdo#103540] / [fdo#107803] / [fdo#107807]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-hsw5/igt@i915_pm_...@gem-execbuf-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-hsw1/igt@i915_pm_...@gem-execbuf-stress.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#104873]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-glk5/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-glk9/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-skl9/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_setmode@basic: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl3/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-skl4/igt@kms_setm...@basic.html Possible fixes * igt@gem_busy@close-race: - shard-skl: [DMESG-FAIL][19] ([fdo#111063]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl1/igt@gem_b...@close-race.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-skl6/igt@gem_b...@close-race.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][21] ([fdo#110854]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-iclb8/igt@gem_exec_balan...@smoke.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13528/shard-iclb1/igt@gem_exec_balan...@smoke.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS
[Intel-gfx] [PATCH] drm/i915/gtt: Introduce release_pd_entry
From: Mika Kuoppala
By encapsulating the locking upper level and used check for entry
into a helper function, we can use it in all callsites.
v2: get rid of atomic_reads on lower level clears (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 109 +++-
1 file changed, 41 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0a55b0932c86..d369394c0ae8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -813,6 +813,24 @@ __clear_pd_entry(struct i915_page_directory * const pd,
#define clear_pd_entry(pd, pde, to) \
__clear_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
+static bool
+release_pd_entry(struct i915_page_directory * const pd,
+const unsigned short pde,
+atomic_t *counter,
+void * const scratch)
+{
+ bool free = false;
+
+ spin_lock(&pd->lock);
+ if (atomic_dec_and_test(counter)) {
+ clear_pd_entry(pd, pde, scratch);
+ free = true;
+ }
+ spin_unlock(&pd->lock);
+
+ return free;
+}
+
/*
* PDE TLBs are a pain to invalidate on GEN8+. When we modify
* the page table structures, we mark them dirty so that
@@ -827,11 +845,11 @@ static void mark_tlbs_dirty(struct i915_ppgtt *ppgtt)
/* Removes entries from a single page table, releasing it if it's empty.
* Caller can use the return value to update higher-level entries.
*/
-static bool gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
struct i915_page_table *pt,
u64 start, u64 length)
{
- unsigned int num_entries = gen8_pte_count(start, length);
+ const unsigned int num_entries = gen8_pte_count(start, length);
gen8_pte_t *vaddr;
vaddr = kmap_atomic_px(pt);
@@ -839,10 +857,11 @@ static bool gen8_ppgtt_clear_pt(const struct
i915_address_space *vm,
kunmap_atomic(vaddr);
GEM_BUG_ON(num_entries > atomic_read(&pt->used));
- return !atomic_sub_return(num_entries, &pt->used);
+
+ atomic_sub(num_entries, &pt->used);
}
-static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_directory *pd,
u64 start, u64 length)
{
@@ -850,30 +869,21 @@ static bool gen8_ppgtt_clear_pd(struct i915_address_space
*vm,
u32 pde;
gen8_for_each_pde(pt, pd, start, length, pde) {
- bool free = false;
-
GEM_BUG_ON(pt == vm->scratch_pt);
- if (!gen8_ppgtt_clear_pt(vm, pt, start, length))
- continue;
+ atomic_inc(&pt->used);
- spin_lock(&pd->lock);
- if (!atomic_read(&pt->used)) {
- clear_pd_entry(pd, pde, vm->scratch_pt);
- free = true;
- }
- spin_unlock(&pd->lock);
- if (free)
+ gen8_ppgtt_clear_pt(vm, pt, start, length);
+
+ if (release_pd_entry(pd, pde, &pt->used, vm->scratch_pt))
free_pt(vm, pt);
}
-
- return !atomic_read(&pd->used);
}
/* Removes entries from a single page dir pointer, releasing it if it's empty.
* Caller can use the return value to update higher-level entries
*/
-static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
struct i915_page_directory * const pdp,
u64 start, u64 length)
{
@@ -881,24 +891,15 @@ static bool gen8_ppgtt_clear_pdp(struct
i915_address_space *vm,
unsigned int pdpe;
gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
- bool free = false;
-
GEM_BUG_ON(pd == vm->scratch_pd);
- if (!gen8_ppgtt_clear_pd(vm, pd, start, length))
- continue;
+ atomic_inc(&pd->used);
- spin_lock(&pdp->lock);
- if (!atomic_read(&pd->used)) {
- clear_pd_entry(pdp, pdpe, vm->scratch_pd);
- free = true;
- }
- spin_unlock(&pdp->lock);
- if (free)
+ gen8_ppgtt_clear_pd(vm, pd, start, length);
+
+ if (release_pd_entry(pdp, pdpe, &pd->used, vm->scratch_pd))
free_pd(vm, pd);
}
-
- return !atomic_read(&pdp->used);
}
static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm,
@@ -922,19 +923,13 @@ static void gen8_ppgtt_clear_4lvl(struct
i915_address_space *vm,
GEM_BUG_ON(!i915_vm_is_4lvl(vm));
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/oa: Reconfigure contexts on the fly (rev2)
== Series Details ==
Series: drm/i915/oa: Reconfigure contexts on the fly (rev2)
URL : https://patchwork.freedesktop.org/series/63276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6425 -> Patchwork_13547
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13547/
Known issues
Here are the changes found in Patchwork_13547 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([fdo#111074])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13547/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-u2: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13547/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13547/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13547/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][9] ([fdo#109485]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13547/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111074]: https://bugs.freedesktop.org/show_bug.cgi?id=111074
Participating hosts (55 -> 46)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6425 -> Patchwork_13547
CI_DRM_6425: 62149faa04e66d4d16166c89ba441977a0656119 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5087: f0e39642f6f8da5406627bfa79c6600df949e203 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13547: 8d1210faf04e2d9313b99adf17828a71bfcb5624 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13547/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
8d1210faf04e drm/i915/oa: Reconfigure contexts on the fly
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13547/
___
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[Intel-gfx] [PATCH 1/4] drm/i915/gtt: pde entry encoding is identical
For all page directory entries, the pde encoding is
identical. Don't compilicate call sites with different
versions of doing the same thing. We check the existence of
physical page before writing the entry into it. This further
generalizes the pd so that manipulation in callsites will be
identical, removing the need to handle pdps differently for gen8.
v2: squash
v3: inc/dec with set/clear (Chris)
v4: inlines, warn, stray set_pd (Chris)
Cc: Chris Wilson
Cc: Matthew Auld
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 152
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 -
2 files changed, 63 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 57db2d7270c5..adf6eadd5009 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -211,10 +211,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
return pte;
}
-static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
- const enum i915_cache_level level)
+static u64 gen8_pde_encode(const dma_addr_t addr,
+ const enum i915_cache_level level)
{
- gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
+ u64 pde = _PAGE_PRESENT | _PAGE_RW;
pde |= addr;
if (level != I915_CACHE_NONE)
pde |= PPAT_CACHED_PDE;
@@ -223,9 +223,6 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
return pde;
}
-#define gen8_pdpe_encode gen8_pde_encode
-#define gen8_pml4e_encode gen8_pde_encode
-
static u64 snb_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
@@ -777,24 +774,55 @@ static void free_pd(struct i915_address_space *vm,
kfree(pd);
}
-static void init_pd_with_page(struct i915_address_space *vm,
- struct i915_page_directory * const pd,
- struct i915_page_table *pt)
+#define init_pd(vm, pd, to) { \
+ GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));\
+ fill_px((vm), (pd), gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \
+ memset_p((pd)->entry, (to), 512); \
+}
+
+static inline void
+write_dma_entry(struct i915_page_dma * const pdma,
+ const unsigned short pde,
+ const u64 encoded_entry)
+{
+ u64 * const vaddr = kmap_atomic(pdma->page);
+
+ vaddr[pde] = encoded_entry;
+ kunmap_atomic(vaddr);
+}
+
+static inline void
+__set_pd_entry(struct i915_page_directory * const pd,
+ const unsigned short pde,
+ struct i915_page_dma * const to,
+ u64 (*encode)(const dma_addr_t, const enum i915_cache_level))
{
- fill_px(vm, pd, gen8_pde_encode(px_dma(pt), I915_CACHE_LLC));
- memset_p(pd->entry, pt, 512);
+ GEM_BUG_ON(atomic_read(&pd->used) > 512);
+
+ atomic_inc(&pd->used);
+ pd->entry[pde] = to;
+ write_dma_entry(px_base(pd), pde, encode(to->daddr, I915_CACHE_LLC));
}
-static void init_pd(struct i915_address_space *vm,
- struct i915_page_directory * const pd,
- struct i915_page_directory * const to)
+static inline void
+__clear_pd_entry(struct i915_page_directory * const pd,
+const unsigned short pde,
+struct i915_page_dma * const to,
+u64 (*encode)(const dma_addr_t, const enum i915_cache_level))
{
- GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));
+ GEM_BUG_ON(atomic_read(&pd->used) == 0);
- fill_px(vm, pd, gen8_pdpe_encode(px_dma(to), I915_CACHE_LLC));
- memset_p(pd->entry, to, 512);
+ write_dma_entry(px_base(pd), pde, encode(to->daddr, I915_CACHE_LLC));
+ pd->entry[pde] = to;
+ atomic_dec(&pd->used);
}
+#define set_pd_entry(pd, pde, to) \
+ __set_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
+
+#define clear_pd_entry(pd, pde, to) \
+ __clear_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
+
/*
* PDE TLBs are a pain to invalidate on GEN8+. When we modify
* the page table structures, we mark them dirty so that
@@ -824,18 +852,6 @@ static bool gen8_ppgtt_clear_pt(const struct
i915_address_space *vm,
return !atomic_sub_return(num_entries, &pt->used);
}
-static void gen8_ppgtt_set_pde(struct i915_address_space *vm,
- struct i915_page_directory *pd,
- struct i915_page_table *pt,
- unsigned int pde)
-{
- gen8_pde_t *vaddr;
-
- vaddr = kmap_atomic_px(pd);
- vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC);
- kunmap_atomic(vaddr);
-}
-
static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_directory *pd,
u64 start, u64 l
[Intel-gfx] [PATCH 4/4] drm/i915/gtt: Introduce release_pd_entry
By encapsulating the locking upper level and used check for entry
into a helper function, we can use it in all callsites.
v2: get rid of atomic_reads on lower level clears (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 125 +---
1 file changed, 60 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0a55b0932c86..3d9612c776dc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -813,6 +813,42 @@ __clear_pd_entry(struct i915_page_directory * const pd,
#define clear_pd_entry(pd, pde, to) \
__clear_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
+static bool
+release_pt_entry(struct i915_page_directory * const pd,
+const unsigned short pde,
+struct i915_page_table * const pt,
+struct i915_page_table * const scratch)
+{
+ bool free = false;
+
+ spin_lock(&pd->lock);
+ if (atomic_dec_and_test(&pt->used)) {
+ clear_pd_entry(pd, pde, scratch);
+ free = true;
+ }
+ spin_unlock(&pd->lock);
+
+ return free;
+}
+
+static bool
+release_pd_entry(struct i915_page_directory * const pd,
+const unsigned short pde,
+struct i915_page_directory * const entry,
+struct i915_page_directory * const scratch)
+{
+ bool free = false;
+
+ spin_lock(&pd->lock);
+ if (atomic_dec_and_test(&entry->used)) {
+ clear_pd_entry(pd, pde, scratch);
+ free = true;
+ }
+ spin_unlock(&pd->lock);
+
+ return free;
+}
+
/*
* PDE TLBs are a pain to invalidate on GEN8+. When we modify
* the page table structures, we mark them dirty so that
@@ -827,11 +863,11 @@ static void mark_tlbs_dirty(struct i915_ppgtt *ppgtt)
/* Removes entries from a single page table, releasing it if it's empty.
* Caller can use the return value to update higher-level entries.
*/
-static bool gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
struct i915_page_table *pt,
u64 start, u64 length)
{
- unsigned int num_entries = gen8_pte_count(start, length);
+ const unsigned int num_entries = gen8_pte_count(start, length);
gen8_pte_t *vaddr;
vaddr = kmap_atomic_px(pt);
@@ -839,10 +875,11 @@ static bool gen8_ppgtt_clear_pt(const struct
i915_address_space *vm,
kunmap_atomic(vaddr);
GEM_BUG_ON(num_entries > atomic_read(&pt->used));
- return !atomic_sub_return(num_entries, &pt->used);
+
+ atomic_sub(num_entries, &pt->used);
}
-static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_directory *pd,
u64 start, u64 length)
{
@@ -850,30 +887,21 @@ static bool gen8_ppgtt_clear_pd(struct i915_address_space
*vm,
u32 pde;
gen8_for_each_pde(pt, pd, start, length, pde) {
- bool free = false;
-
GEM_BUG_ON(pt == vm->scratch_pt);
- if (!gen8_ppgtt_clear_pt(vm, pt, start, length))
- continue;
+ atomic_inc(&pt->used);
- spin_lock(&pd->lock);
- if (!atomic_read(&pt->used)) {
- clear_pd_entry(pd, pde, vm->scratch_pt);
- free = true;
- }
- spin_unlock(&pd->lock);
- if (free)
+ gen8_ppgtt_clear_pt(vm, pt, start, length);
+
+ if (release_pt_entry(pd, pde, pt, vm->scratch_pt))
free_pt(vm, pt);
}
-
- return !atomic_read(&pd->used);
}
/* Removes entries from a single page dir pointer, releasing it if it's empty.
* Caller can use the return value to update higher-level entries
*/
-static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
struct i915_page_directory * const pdp,
u64 start, u64 length)
{
@@ -881,24 +909,15 @@ static bool gen8_ppgtt_clear_pdp(struct
i915_address_space *vm,
unsigned int pdpe;
gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
- bool free = false;
-
GEM_BUG_ON(pd == vm->scratch_pd);
- if (!gen8_ppgtt_clear_pd(vm, pd, start, length))
- continue;
+ atomic_inc(&pd->used);
- spin_lock(&pdp->lock);
- if (!atomic_read(&pd->used)) {
- clear_pd_entry(pdp, pdpe, vm->scratch_pd);
- free = true;
- }
-
[Intel-gfx] [PATCH 2/4] drm/i915/gtt: Tear down setup and cleanup macros for page dma
We don't use common codepaths to setup and cleanup page
directories vs page tables. So their setup and cleanup macros
are of no use.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index adf6eadd5009..f011ce1ae03a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -594,8 +594,6 @@ static void cleanup_page_dma(struct i915_address_space *vm,
#define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
-#define setup_px(vm, px) setup_page_dma((vm), px_base(px))
-#define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
#define fill_px(vm, px, v) fill_page_dma((vm), px_base(px), (v))
#define fill32_px(vm, px, v) fill_page_dma_32((vm), px_base(px), (v))
@@ -697,7 +695,7 @@ static struct i915_page_table *alloc_pt(struct
i915_address_space *vm)
if (unlikely(!pt))
return ERR_PTR(-ENOMEM);
- if (unlikely(setup_px(vm, pt))) {
+ if (unlikely(setup_page_dma(vm, &pt->base))) {
kfree(pt);
return ERR_PTR(-ENOMEM);
}
@@ -709,7 +707,7 @@ static struct i915_page_table *alloc_pt(struct
i915_address_space *vm)
static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt)
{
- cleanup_px(vm, pt);
+ cleanup_page_dma(vm, &pt->base);
kfree(pt);
}
@@ -752,7 +750,7 @@ static struct i915_page_directory *alloc_pd(struct
i915_address_space *vm)
if (unlikely(!pd))
return ERR_PTR(-ENOMEM);
- if (unlikely(setup_px(vm, pd))) {
+ if (unlikely(setup_page_dma(vm, &pd->base))) {
kfree(pd);
return ERR_PTR(-ENOMEM);
}
@@ -769,7 +767,7 @@ static void free_pd(struct i915_address_space *vm,
struct i915_page_directory *pd)
{
if (likely(pd_has_phys_page(pd)))
- cleanup_px(vm, pd);
+ cleanup_page_dma(vm, &pd->base);
kfree(pd);
}
@@ -1649,7 +1647,7 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
}
if (i915_vm_is_4lvl(&ppgtt->vm)) {
- err = setup_px(&ppgtt->vm, ppgtt->pd);
+ err = setup_page_dma(&ppgtt->vm, &ppgtt->pd->base);
if (err)
goto err_free_pdp;
--
2.17.1
___
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[Intel-gfx] [PATCH 3/4] drm/i915/gtt: Setup phys pages for 3lvl pdps
If we setup backing phys page for 3lvl pdps, even they
are not used, we lose 5 pages per ppgtt.
Trading this memory on bsw, we gain more common code paths for all
gen8+ directory manipulation. And those paths are now void of checks
for page directory type, making the hot paths faster.
v2: don't shortcut vm (Chris)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 77 +++--
1 file changed, 50 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f011ce1ae03a..0a55b0932c86 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -758,22 +758,14 @@ static struct i915_page_directory *alloc_pd(struct
i915_address_space *vm)
return pd;
}
-static inline bool pd_has_phys_page(const struct i915_page_directory * const
pd)
-{
- return pd->base.page;
-}
-
static void free_pd(struct i915_address_space *vm,
struct i915_page_directory *pd)
{
- if (likely(pd_has_phys_page(pd)))
- cleanup_page_dma(vm, &pd->base);
-
+ cleanup_page_dma(vm, &pd->base);
kfree(pd);
}
#define init_pd(vm, pd, to) { \
- GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));\
fill_px((vm), (pd), gen8_pde_encode(px_dma(to), I915_CACHE_LLC)); \
memset_p((pd)->entry, (to), 512); \
}
@@ -1604,6 +1596,50 @@ static void ppgtt_init(struct i915_ppgtt *ppgtt, struct
intel_gt *gt)
ppgtt->vm.vma_ops.clear_pages = clear_pages;
}
+static void init_pd_n(struct i915_address_space *vm,
+ struct i915_page_directory *pd,
+ struct i915_page_directory *to,
+ const unsigned int entries)
+{
+ const u64 daddr = gen8_pde_encode(px_dma(to), I915_CACHE_LLC);
+ u64 * const vaddr = kmap_atomic(pd->base.page);
+
+ memset64(vaddr, daddr, entries);
+ kunmap_atomic(vaddr);
+
+ memset_p(pd->entry, to, entries);
+}
+
+static struct i915_page_directory *
+gen8_alloc_top_pd(struct i915_address_space *vm)
+{
+ struct i915_page_directory *pd;
+
+ if (i915_vm_is_4lvl(vm)) {
+ pd = alloc_pd(vm);
+ if (!IS_ERR(pd))
+ init_pd(vm, pd, vm->scratch_pdp);
+
+ return pd;
+ }
+
+ /* 3lvl */
+ pd = __alloc_pd();
+ if (!pd)
+ return ERR_PTR(-ENOMEM);
+
+ pd->entry[GEN8_3LVL_PDPES] = NULL;
+
+ if (unlikely(setup_page_dma(vm, &pd->base))) {
+ kfree(pd);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init_pd_n(vm, pd, vm->scratch_pd, GEN8_3LVL_PDPES);
+
+ return pd;
+}
+
/*
* GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
* with a net effect resembling a 2-level page table in normal x86 terms. Each
@@ -1640,34 +1676,21 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
if (err)
goto err_free;
- ppgtt->pd = __alloc_pd();
- if (!ppgtt->pd) {
- err = -ENOMEM;
+ ppgtt->pd = gen8_alloc_top_pd(&ppgtt->vm);
+ if (IS_ERR(ppgtt->pd)) {
+ err = PTR_ERR(ppgtt->pd);
goto err_free_scratch;
}
if (i915_vm_is_4lvl(&ppgtt->vm)) {
- err = setup_page_dma(&ppgtt->vm, &ppgtt->pd->base);
- if (err)
- goto err_free_pdp;
-
- init_pd(&ppgtt->vm, ppgtt->pd, ppgtt->vm.scratch_pdp);
-
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
} else {
- /*
-* We don't need to setup dma for top level pdp, only
-* for entries. So point entries to scratch.
-*/
- memset_p(ppgtt->pd->entry, ppgtt->vm.scratch_pd,
-GEN8_3LVL_PDPES);
-
if (intel_vgpu_active(i915)) {
err = gen8_preallocate_top_level_pdp(ppgtt);
if (err)
- goto err_free_pdp;
+ goto err_free_pd;
}
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
@@ -1682,7 +1705,7 @@ static struct i915_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
return ppgtt;
-err_free_pdp:
+err_free_pd:
free_pd(&ppgtt->vm, ppgtt->pd);
err_free_scratch:
gen8_free_scratch(&ppgtt->vm);
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Apply RCS workarounds to the render class
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Apply RCS workarounds to the
render class
URL : https://patchwork.freedesktop.org/series/63277/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6425 -> Patchwork_13546
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/
Known issues
Here are the changes found in Patchwork_13546 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_mmap_...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/fi-icl-u3/igt@gem_mmap_...@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108840])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/fi-icl-dsi/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-u2: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][13] ([fdo#109485]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6425/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (55 -> 47)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6425 -> Patchwork_13546
CI_DRM_6425: 62149faa04e66d4d16166c89ba441977a0656119 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5087: f0e39642f6f8da5406627bfa79c6600df949e203 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13546: 8de975ed269b36487e6c97f9c07d856a979c4a01 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
8de975ed269b drm/i915/gt: Remove presumption of RCS0
69cbbeeded20 drm/i915/gt: Apply RCS workarounds to the render class
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13546/
___
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hdcp: debugs logs for sink related failures
== Series Details == Series: drm/i915/hdcp: debugs logs for sink related failures URL : https://patchwork.freedesktop.org/series/63217/ State : success == Summary == CI Bug Log - changes from CI_DRM_6410_full -> Patchwork_13527_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13527_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-apl5/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-apl7/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl8/igt@gem_soft...@noreloc-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-skl3/igt@gem_soft...@noreloc-s3.html * igt@kms_busy@extended-modeset-hang-oldfb-render-a: - shard-hsw: [PASS][5] -> [DMESG-WARN][6] ([fdo#102614]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-hsw8/igt@kms_b...@extended-modeset-hang-oldfb-render-a.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-hsw5/igt@kms_b...@extended-modeset-hang-oldfb-render-a.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-skl4/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#109507]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl3/igt@kms_f...@flip-vs-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-skl6/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108] / [fdo#106978]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl6/igt@kms_frontbuffer_track...@psr-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-skl2/igt@kms_frontbuffer_track...@psr-suspend.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_setmode@basic: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl3/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-skl1/igt@kms_setm...@basic.html - shard-kbl: [PASS][19] -> [FAIL][20] ([fdo#99912]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-kbl3/igt@kms_setm...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-kbl7/igt@kms_setm...@basic.html * igt@perf@blocking: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#110728]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl10/igt@p...@blocking.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-skl8/igt@p...@blocking.html Possible fixes * igt@gem_busy@close-race: - shard-skl: [DMESG-FAIL][23] ([fdo#111063]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-skl1/igt@gem_b...@close-race.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-skl8/igt@gem_b...@close-race.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][25] ([fdo#110854]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6410/shard-iclb8/igt@gem_exec_balan...@smoke.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13527/shard-iclb1/igt@gem_exec_balan...@smoke.html * igt@gem_workarounds@suspend-resume-context: - shard-
Re: [Intel-gfx] [PATCH v7 07/11] drm: Add Content protection type property
On Fri, 5 Jul 2019 12:03:18 +0530
Ramalingam C wrote:
> On 2019-07-05 at 16:00:37 +0300, Pekka Paalanen wrote:
> > On Thu, 4 Jul 2019 16:06:05 +0530
> > Ramalingam C wrote:
> >
> > > On 2019-07-04 at 14:11:59 +0300, Pekka Paalanen wrote:
> > > > On Tue, 7 May 2019 21:57:41 +0530
> > > > Ramalingam C wrote:
> > > >
> > > > > This patch adds a DRM ENUM property to the selected connectors.
> > > > > This property is used for mentioning the protected content's type
> > > > > from userspace to kernel HDCP authentication.
> > > > >
> > > > > Type of the stream is decided by the protected content providers.
> > > > > Type 0 content can be rendered on any HDCP protected display wires.
> > > > > But Type 1 content can be rendered only on HDCP2.2 protected paths.
> > > > >
> > > > > So when a userspace sets this property to Type 1 and starts the HDCP
> > > > > enable, kernel will honour it only if HDCP2.2 authentication is
> > > > > through
> > > > > for type 1. Else HDCP enable will be failed.
> > > > >
> > > > > Need ACK for this new conenctor property from userspace consumer.
> > > > >
> > > > > v2:
> > > > > cp_content_type is replaced with content_protection_type [daniel]
> > > > > check at atomic_set_property is removed [Maarten]
> > > > > v3:
> > > > > %s/content_protection_type/hdcp_content_type [Pekka]
> > > > > v4:
> > > > > property is created for the first requested connector and then
> > > > > reused.
> > > > > [Danvet]
> > > > > v5:
> > > > > kernel doc nits addressed [Daniel]
> > > > > Rebased as part of patch reordering.
> > > > >
> > > > > Signed-off-by: Ramalingam C
> > > > > Reviewed-by: Daniel Vetter
> > > > > ---
> > > > > drivers/gpu/drm/drm_atomic_uapi.c | 4
> > > > > drivers/gpu/drm/drm_connector.c | 18
> > > > > drivers/gpu/drm/drm_hdcp.c| 36
> > > > > ++-
> > > > > drivers/gpu/drm/i915/intel_hdcp.c | 4 +++-
> > > > > include/drm/drm_connector.h | 7 ++
> > > > > include/drm/drm_hdcp.h| 2 +-
> > > > > include/drm/drm_mode_config.h | 6 ++
> > > > > include/uapi/drm/drm_mode.h | 4
> > > > > 8 files changed, 78 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > > b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > > index 4131e669785a..a85f3ccfe699 100644
> > > > > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > > @@ -738,6 +738,8 @@ static int
> > > > > drm_atomic_connector_set_property(struct drm_connector *connector,
> > > > > return -EINVAL;
> > > > > }
> > > > > state->content_protection = val;
> > > > > + } else if (property == config->hdcp_content_type_property) {
> > > > > + state->hdcp_content_type = val;
> > > > > } else if (property == connector->colorspace_property) {
> > > > > state->colorspace = val;
> > > > > } else if (property == config->writeback_fb_id_property) {
> > > > > @@ -816,6 +818,8 @@ drm_atomic_connector_get_property(struct
> > > > > drm_connector *connector,
> > > > > *val = state->scaling_mode;
> > > > > } else if (property == config->content_protection_property) {
> > > > > *val = state->content_protection;
> > > > > + } else if (property == config->hdcp_content_type_property) {
> > > > > + *val = state->hdcp_content_type;
> > > > > } else if (property == config->writeback_fb_id_property) {
> > > > > /* Writeback framebuffer is one-shot, write and forget
> > > > > */
> > > > > *val = 0;
> > > > > diff --git a/drivers/gpu/drm/drm_connector.c
> > > > > b/drivers/gpu/drm/drm_connector.c
> > > > > index 764c7903edf6..de9e06583e8c 100644
> > > > > --- a/drivers/gpu/drm/drm_connector.c
> > > > > +++ b/drivers/gpu/drm/drm_connector.c
> > > >
> > > > Hi,
> > > >
> > > > below I have some comments and questions before I can say whether
> > > > https://gitlab.freedesktop.org/wayland/weston/merge_requests/48
> > > > adheres to this specification.
> > > >
> > > > > @@ -955,6 +955,24 @@ static const struct drm_prop_enum_list
> > > > > hdmi_colorspaces[] = {
> > > > > * the value transitions from ENABLED to DESIRED. This signifies
> > > > > the link
> > > > > * is no longer protected and userspace should take appropriate
> > > > > action
> > > > > * (whatever that might be).
> > > > > + * HDCP Content Type:
> > > > > + * This property is used by the userspace to configure the kernel
> > > > > with
> > > > > + * to be displayed stream's content type. Content Type of a stream
> > > > > is
> > > > > + * decided by the owner of the stream, as HDCP Type0 or HDCP Type1.
> > > > > + *
> > > > > + * The value of the property can be one the below:
> > > > > + * - DRM_MODE_HDCP_CONTENT_TYPE0 = 0
> > > >
> > >
[Intel-gfx] [PATCH 1/2] drm/i915: Clear the shared PLL from the put_dplls() hook
For symmetry with the get_dplls() hook which sets the shared_dpll
pointer clear the same pointer from the put_dplls() hook.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 2 --
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 +-
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 919f5ac844c8..280e0f1b7005 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13285,8 +13285,6 @@ static void intel_modeset_clear_plls(struct
intel_atomic_state *state)
if (!needs_modeset(new_crtc_state))
continue;
- new_crtc_state->shared_dpll = NULL;
-
intel_release_shared_dplls(state, crtc);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f953971e7c3b..722b1deca999 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -323,13 +323,17 @@ static void intel_unreference_shared_dpll(struct
intel_atomic_state *state,
static void intel_put_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct intel_crtc_state *crtc_state =
+ struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ new_crtc_state->shared_dpll = NULL;
- if (!crtc_state->shared_dpll)
+ if (!old_crtc_state->shared_dpll)
return;
- intel_unreference_shared_dpll(state, crtc, crtc_state->shared_dpll);
+ intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
}
/**
@@ -3008,13 +3012,17 @@ static bool icl_get_dplls(struct intel_atomic_state
*state,
static void icl_put_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct intel_crtc_state *crtc_state =
+ struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
enum icl_port_dpll_id id;
+ new_crtc_state->shared_dpll = NULL;
+
for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
struct icl_port_dpll *port_dpll =
- &crtc_state->icl_port_dplls[id];
+ &old_crtc_state->icl_port_dplls[id];
if (!port_dpll->pll)
continue;
--
2.17.1
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[Intel-gfx] [PATCH 2/2] drm/i915/icl: Clear the shared port PLLs from the new crtc state
For consistency clear the icl_port_dplls from the new crtc state, when
releasing the DPLLs from the old crtc state. Leaving them set could
result in releasing the same PLLs multiple times from the same CRTC
state incorrectly (if the same CRTC was first used for a TypeC port then
for a combo PHY port).
Leaving the stale pointers behind happens not to cause a problem atm
(since the incorrect releasing will be a NOP), but we need to fix that
for consistency.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 722b1deca999..f4db2410ca93 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3021,15 +3021,17 @@ static void icl_put_dplls(struct intel_atomic_state
*state,
new_crtc_state->shared_dpll = NULL;
for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
- struct icl_port_dpll *port_dpll =
+ struct icl_port_dpll *old_port_dpll =
&old_crtc_state->icl_port_dplls[id];
+ struct icl_port_dpll *new_port_dpll =
+ &new_crtc_state->icl_port_dplls[id];
- if (!port_dpll->pll)
- continue;
+ new_port_dpll->pll = NULL;
- intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
+ if (!old_port_dpll->pll)
+ continue;
- /* FIXME: Clear the icl_port_dplls from the new crtc state */
+ intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
}
}
--
2.17.1
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Re: [Intel-gfx] [PATCH v7 10/11] drm/hdcp: update content protection property with uevent
On Thu, 4 Jul 2019 16:41:15 +0530
Ramalingam C wrote:
> On 2019-07-04 at 14:14:19 +0300, Pekka Paalanen wrote:
> > On Tue, 7 May 2019 21:57:44 +0530
> > Ramalingam C wrote:
> >
> > > drm function is defined and exported to update a connector's
> > > content protection property state and to generate a uevent along
> > > with it.
> > >
> > > Need ACK for the uevent from userspace consumer.
> > >
> > > v2:
> > > Update only when state is different from old one.
> > > v3:
> > > KDoc is added [Daniel]
> > >
> > > Signed-off-by: Ramalingam C
> > > Reviewed-by: Daniel Vetter
> > > ---
> > > drivers/gpu/drm/drm_hdcp.c | 32
> > > include/drm/drm_hdcp.h | 2 ++
> > > 2 files changed, 34 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
> > > index 75402463466b..f29b7abda51f 100644
> > > --- a/drivers/gpu/drm/drm_hdcp.c
> > > +++ b/drivers/gpu/drm/drm_hdcp.c
> > > @@ -372,6 +372,10 @@ DRM_ENUM_NAME_FN(drm_get_hdcp_content_type_name,
> > > *
> > > * The content protection will be set to
> > > &drm_connector_state.content_protection
> > > *
> > > + * When kernel triggered content protection state change like
> > > DESIRED->ENABLED
> > > + * and ENABLED->DESIRED, will use drm_hdcp_update_content_protection()
> > > to update
> > > + * the content protection state of a connector.
> Here we indicated that drm_hdcp_update_content_protection() used for
> kernel triggered content protection state change.
Hi,
sure. I don't know how a userspace programmer could guess it is in any
way relevant to when the events are sent and when not. They wouldn't
even read the doc of this function to begin with.
> > > + *
> > > * Returns:
> > > * Zero on success, negative errno on failure.
> > > */
> > > @@ -412,3 +416,31 @@ int drm_connector_attach_content_protection_property(
> > > return 0;
> > > }
> > > EXPORT_SYMBOL(drm_connector_attach_content_protection_property);
> > > +
> > > +/**
> > > + * drm_hdcp_update_content_protection - Updates the content protection
> > > state
> > > + * of a connector
> > > + *
> > > + * @connector: drm_connector on which content protection state needs an
> > > update
> > > + * @val: New state of the content protection property
> > > + *
> > > + * This function can be used by display drivers, to update the kernel
> > > triggered
> > > + * content protection state change of a drm_connector.This function
> > > update the
> These lines also indicate that this function is used for kernel
> triggered content protection state change of a drm_connector.
How could any userspace programmer know to decipher what this means
for event sending?
The event semantics must be documented somewhere where userspace people
actually read. In this case it would be with the definition of the
connector property for which the event was added, lacking a proper
place for UAPI docs.
>
> -Ram
> > > + * new state of the property into the connector's state and generate an
> > > uevent
> > > + * to notify the userspace.
> > > + */
> > > +void drm_hdcp_update_content_protection(struct drm_connector *connector,
> > > + u64 val)
> > > +{
> >
> > Hi,
> >
> > don't you need to ensure that 'val' cannot be UNDESIRED?
> @ https://patchwork.freedesktop.org/patch/303909/?series=57232&rev=9
> caller(I915) of this function is ensuring that.
Yes, the caller does that right now. Don't you want to catch other
callers written by someone else who don't know or forget to do the same
check as i915 does?
Isn't that what all the WARN_ON etc. macros are mostly about, to catch
badly written kernel code?
I mean, it is at least a semantic kernel bug if anyone attempts to
call this function with UNDESIRED, right? Because when they do, this
function may send the uevent.
> > > + struct drm_device *dev = connector->dev;
> > > + struct drm_connector_state *state = connector->state;
> > > +
> > > + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> > > + if (state->content_protection == val)
> when val==UNDESIRED even the state->content_protection also UNDESIRED.
> Hence explicit check is not needed here.
So it accidentally won't cause any visible harm? Until something subtly
changes elsewhere and it does.
Thanks,
pq
>
> -Ram
> >
> > > + struct drm_device *dev = connector->dev;
> > > + struct drm_connector_state *state = connector->state;
> > > +
> > > + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> > > + if (state->content_protection == val)
> > > + return;
> > > +
> > > + state->content_protection = val;
> > > + drm_sysfs_connector_status_event(connector,
> > > + dev->mode_config.content_protection_property);
> > > +}
> > > +EXPORT_SYMBOL(drm_hdcp_update_content_protection);
> > > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> > > index 2970abdfaf12..dd864ac9ce85 100644
> > > --- a/include/dr
[Intel-gfx] [PATCH -next] drm/i915: fix possible memory leak in intel_hdcp_auth_downstream()
'ksv_fifo' is malloced in intel_hdcp_auth_downstream() and should be
freed before leaving from the error handling cases, otherwise it will
cause memory leak.
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index bc3a94d491c4..27bd7276a82d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -536,7 +536,8 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
if (drm_hdcp_check_ksvs_revoked(dev, ksv_fifo, num_downstream)) {
DRM_ERROR("Revoked Ksv(s) in ksv_fifo\n");
- return -EPERM;
+ ret = -EPERM;
+ goto err;
}
/*
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Re: [Intel-gfx] [PATCH v7 09/11] drm: uevent for connector status change
On Thu, 4 Jul 2019 16:12:10 +0530
Ramalingam C wrote:
> On 2019-07-04 at 14:12:27 +0300, Pekka Paalanen wrote:
> > On Tue, 7 May 2019 21:57:43 +0530
> > Ramalingam C wrote:
> >
> > > DRM API for generating uevent for a status changes of connector's
> > > property.
> > >
> > > This uevent will have following details related to the status change:
> > >
> > > HOTPLUG=1, CONNECTOR= and PROPERTY=
> > >
> > > Need ACK from this uevent from userspace consumer.
> > >
> > > v2:
> > > Minor fixes at KDoc comments [Daniel]
> > > v3:
> > > Check the property is really attached with connector [Daniel]
> > >
> > > Signed-off-by: Ramalingam C
> > > Reviewed-by: Daniel Vetter
> > > ---
> > > drivers/gpu/drm/drm_sysfs.c | 35 +++
> > > include/drm/drm_sysfs.h | 5 -
> > > 2 files changed, 39 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
> > > index 18b1ac442997..63fa951a20db 100644
> > > --- a/drivers/gpu/drm/drm_sysfs.c
> > > +++ b/drivers/gpu/drm/drm_sysfs.c
> > > @@ -21,6 +21,7 @@
> > > #include
> > > #include
> > > #include "drm_internal.h"
> > > +#include "drm_crtc_internal.h"
> > >
> > > #define to_drm_minor(d) dev_get_drvdata(d)
> > > #define to_drm_connector(d) dev_get_drvdata(d)
> > > @@ -320,6 +321,9 @@ void drm_sysfs_lease_event(struct drm_device *dev)
> > > * Send a uevent for the DRM device specified by @dev. Currently we only
> > > * set HOTPLUG=1 in the uevent environment, but this could be expanded to
> > > * deal with other types of events.
> > > + *
> > > + * Any new uapi should be using the drm_sysfs_connector_status_event()
> > > + * for uevents on connector status change.
> > > */
> > > void drm_sysfs_hotplug_event(struct drm_device *dev)
> > > {
> > > @@ -332,6 +336,37 @@ void drm_sysfs_hotplug_event(struct drm_device *dev)
> > > }
> > > EXPORT_SYMBOL(drm_sysfs_hotplug_event);
> > >
> > > +/**
> > > + * drm_sysfs_connector_status_event - generate a DRM uevent for connector
> > > + * property status change
> > > + * @connector: connector on which property status changed
> > > + * @property: connector property whoes status changed.
> > > + *
> > > + * Send a uevent for the DRM device specified by @dev. Currently we
> > > + * set HOTPLUG=1 and connector id along with the attached property id
> > > + * related to the status change.
> > > + */
> This is the kernel doc added for drm_sysfs_connector_status_event()
> similar to drm_sysfs_hotplug_event()
Hi,
yes, it is the kernel internal doc. An UAPI doc would spell out the
attributes "CONNECTOR" and "PROPERTY" and describe their values
explaining what they are, instead of decsribing a kernel-internal
function arguments.
However, as discussed, we cannot have UAPI docs at this time, so I
guess this is the best we can have.
Thanks,
pq
> > > +void drm_sysfs_connector_status_event(struct drm_connector *connector,
> > > + struct drm_property *property)
> > > +{
> > > + struct drm_device *dev = connector->dev;
> > > + char hotplug_str[] = "HOTPLUG=1", conn_id[30], prop_id[30];
> > > + char *envp[4] = { hotplug_str, conn_id, prop_id, NULL };
> > > +
> > > + WARN_ON(!drm_mode_obj_find_prop_id(&connector->base,
> > > +property->base.id));
> > > +
> > > + snprintf(conn_id, ARRAY_SIZE(conn_id),
> > > + "CONNECTOR=%u", connector->base.id);
> > > + snprintf(prop_id, ARRAY_SIZE(prop_id),
> > > + "PROPERTY=%u", property->base.id);
> > > +
> > > + DRM_DEBUG("generating connector status event\n");
> > > +
> > > + kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp);
> > > +}
> > > +EXPORT_SYMBOL(drm_sysfs_connector_status_event);
> > > +
> > > static void drm_sysfs_release(struct device *dev)
> > > {
> > > kfree(dev);
> > > diff --git a/include/drm/drm_sysfs.h b/include/drm/drm_sysfs.h
> > > index 4f311e836cdc..d454ef617b2c 100644
> > > --- a/include/drm/drm_sysfs.h
> > > +++ b/include/drm/drm_sysfs.h
> > > @@ -4,10 +4,13 @@
> > >
> > > struct drm_device;
> > > struct device;
> > > +struct drm_connector;
> > > +struct drm_property;
> > >
> > > int drm_class_device_register(struct device *dev);
> > > void drm_class_device_unregister(struct device *dev);
> > >
> > > void drm_sysfs_hotplug_event(struct drm_device *dev);
> > > -
> > > +void drm_sysfs_connector_status_event(struct drm_connector *connector,
> > > + struct drm_property *property);
> > > #endif
> >
> > Hi,
> >
> > this patch is completely missing the UAPI documentation.
> >
> > Weston in
> > https://gitlab.freedesktop.org/wayland/weston/merge_requests/48
> > does have good looking code to parse this event.
> >
> >
> > Thanks,
> > pq
>
>
pgpirxKH5sXpJ.pgp
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Re: [Intel-gfx] [PATCH v7 07/11] drm: Add Content protection type property
On 2019-07-05 at 16:00:37 +0300, Pekka Paalanen wrote:
> On Thu, 4 Jul 2019 16:06:05 +0530
> Ramalingam C wrote:
>
> > On 2019-07-04 at 14:11:59 +0300, Pekka Paalanen wrote:
> > > On Tue, 7 May 2019 21:57:41 +0530
> > > Ramalingam C wrote:
> > >
> > > > This patch adds a DRM ENUM property to the selected connectors.
> > > > This property is used for mentioning the protected content's type
> > > > from userspace to kernel HDCP authentication.
> > > >
> > > > Type of the stream is decided by the protected content providers.
> > > > Type 0 content can be rendered on any HDCP protected display wires.
> > > > But Type 1 content can be rendered only on HDCP2.2 protected paths.
> > > >
> > > > So when a userspace sets this property to Type 1 and starts the HDCP
> > > > enable, kernel will honour it only if HDCP2.2 authentication is through
> > > > for type 1. Else HDCP enable will be failed.
> > > >
> > > > Need ACK for this new conenctor property from userspace consumer.
> > > >
> > > > v2:
> > > > cp_content_type is replaced with content_protection_type [daniel]
> > > > check at atomic_set_property is removed [Maarten]
> > > > v3:
> > > > %s/content_protection_type/hdcp_content_type [Pekka]
> > > > v4:
> > > > property is created for the first requested connector and then reused.
> > > > [Danvet]
> > > > v5:
> > > > kernel doc nits addressed [Daniel]
> > > > Rebased as part of patch reordering.
> > > >
> > > > Signed-off-by: Ramalingam C
> > > > Reviewed-by: Daniel Vetter
> > > > ---
> > > > drivers/gpu/drm/drm_atomic_uapi.c | 4
> > > > drivers/gpu/drm/drm_connector.c | 18
> > > > drivers/gpu/drm/drm_hdcp.c| 36 ++-
> > > > drivers/gpu/drm/i915/intel_hdcp.c | 4 +++-
> > > > include/drm/drm_connector.h | 7 ++
> > > > include/drm/drm_hdcp.h| 2 +-
> > > > include/drm/drm_mode_config.h | 6 ++
> > > > include/uapi/drm/drm_mode.h | 4
> > > > 8 files changed, 78 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > index 4131e669785a..a85f3ccfe699 100644
> > > > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > @@ -738,6 +738,8 @@ static int drm_atomic_connector_set_property(struct
> > > > drm_connector *connector,
> > > > return -EINVAL;
> > > > }
> > > > state->content_protection = val;
> > > > + } else if (property == config->hdcp_content_type_property) {
> > > > + state->hdcp_content_type = val;
> > > > } else if (property == connector->colorspace_property) {
> > > > state->colorspace = val;
> > > > } else if (property == config->writeback_fb_id_property) {
> > > > @@ -816,6 +818,8 @@ drm_atomic_connector_get_property(struct
> > > > drm_connector *connector,
> > > > *val = state->scaling_mode;
> > > > } else if (property == config->content_protection_property) {
> > > > *val = state->content_protection;
> > > > + } else if (property == config->hdcp_content_type_property) {
> > > > + *val = state->hdcp_content_type;
> > > > } else if (property == config->writeback_fb_id_property) {
> > > > /* Writeback framebuffer is one-shot, write and forget
> > > > */
> > > > *val = 0;
> > > > diff --git a/drivers/gpu/drm/drm_connector.c
> > > > b/drivers/gpu/drm/drm_connector.c
> > > > index 764c7903edf6..de9e06583e8c 100644
> > > > --- a/drivers/gpu/drm/drm_connector.c
> > > > +++ b/drivers/gpu/drm/drm_connector.c
> > >
> > > Hi,
> > >
> > > below I have some comments and questions before I can say whether
> > > https://gitlab.freedesktop.org/wayland/weston/merge_requests/48
> > > adheres to this specification.
> > >
> > > > @@ -955,6 +955,24 @@ static const struct drm_prop_enum_list
> > > > hdmi_colorspaces[] = {
> > > > * the value transitions from ENABLED to DESIRED. This signifies
> > > > the link
> > > > * is no longer protected and userspace should take appropriate
> > > > action
> > > > * (whatever that might be).
> > > > + * HDCP Content Type:
> > > > + * This property is used by the userspace to configure the kernel
> > > > with
> > > > + * to be displayed stream's content type. Content Type of a stream
> > > > is
> > > > + * decided by the owner of the stream, as HDCP Type0 or HDCP Type1.
> > > > + *
> > > > + * The value of the property can be one the below:
> > > > + * - DRM_MODE_HDCP_CONTENT_TYPE0 = 0
> > >
> > > If this doc is meant as the UAPI doc, it needs to use the string names
> > > for enum property values, not the C language definitions (integers).
>
> > kernel documentation for all other properties followed this way. We
> > could add string associated
Re: [Intel-gfx] [PATCH v2] drm/i915/oa: Reconfigure contexts on the fly
Looks good, probably best to have someone more familiar with the i915
codebase look at it too.
Thanks a bunch!
Reviewed-by: Lionel Landwerlin
On 05/07/2019 16:16, Chris Wilson wrote:
Avoid a global idle barrier by reconfiguring each context by rewriting
them with MI_STORE_DWORD from the kernel context.
v2: We only need to determine the desired register values once, they are
the same for all contexts.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +-
drivers/gpu/drm/i915/i915_perf.c| 244 +++-
3 files changed, 190 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e367dce2a696..1f0d10bb88c1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -624,7 +624,9 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
ctx->sched.priority = I915_USER_PRIORITY(prio);
ctx->ring_size = PAGE_SIZE;
+ /* Isolate the kernel context from prying eyes and sticky fingers */
GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+ list_del_init(&ctx->link);
return ctx;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e1ae1399c72b..9cc5374401e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1552,9 +1552,12 @@ __execlists_update_reg_state(struct intel_context *ce,
regs[CTX_RING_TAIL + 1] = ring->tail;
/* RPCS */
- if (engine->class == RENDER_CLASS)
+ if (engine->class == RENDER_CLASS) {
regs[CTX_R_PWR_CLK_STATE + 1] =
intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+
+ i915_oa_init_reg_state(engine, ce, regs);
+ }
}
static int
@@ -2966,8 +2969,6 @@ static void execlists_init_reg_state(u32 *regs,
if (rcs) {
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
-
- i915_oa_init_reg_state(engine, ce, regs);
}
regs[CTX_END] = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 357e63beb373..8353589ee31b 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1630,6 +1630,27 @@ static void hsw_disable_metric_set(struct
drm_i915_private *dev_priv)
~GT_NOA_ENABLE));
}
+static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
+ i915_reg_t reg)
+{
+ u32 mmio = i915_mmio_reg_offset(reg);
+ int i;
+
+ /*
+* This arbitrary default will select the 'EU FPU0 Pipeline
+* Active' event. In the future it's anticipated that there
+* will be an explicit 'No Event' we can select, but not yet...
+*/
+ if (!oa_config)
+ return 0;
+
+ for (i = 0; i < oa_config->flex_regs_len; i++) {
+ if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
+ return oa_config->flex_regs[i].value;
+ }
+
+ return 0;
+}
/*
* NB: It must always remain pointer safe to run this even if the OA unit
* has been disabled.
@@ -1663,28 +1684,8 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,
GEN8_OA_COUNTER_RESUME);
for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
- u32 state_offset = ctx_flexeu0 + i * 2;
- u32 mmio = i915_mmio_reg_offset(flex_regs[i]);
-
- /*
-* This arbitrary default will select the 'EU FPU0 Pipeline
-* Active' event. In the future it's anticipated that there
-* will be an explicit 'No Event' we can select, but not yet...
-*/
- u32 value = 0;
-
- if (oa_config) {
- u32 j;
-
- for (j = 0; j < oa_config->flex_regs_len; j++) {
- if
(i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {
- value = oa_config->flex_regs[j].value;
- break;
- }
- }
- }
-
- CTX_REG(reg_state, state_offset, flex_regs[i], value);
+ CTX_REG(reg_state, ctx_flexeu0 + i * 2, flex_regs[i],
+ oa_config_flex_reg(oa_config, flex_regs[i]));
}
CTX_REG(reg_state,
@@ -1692,6 +1693,107 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,
intel_sseu_make_rpcs(i915, &ce->sseu));
}
+struct flex {
+ i915_reg_t reg;
+ u32 offset;
+
[Intel-gfx] [PATCH v2] drm/i915/oa: Reconfigure contexts on the fly
Avoid a global idle barrier by reconfiguring each context by rewriting
them with MI_STORE_DWORD from the kernel context.
v2: We only need to determine the desired register values once, they are
the same for all contexts.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +-
drivers/gpu/drm/i915/i915_perf.c| 244 +++-
3 files changed, 190 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e367dce2a696..1f0d10bb88c1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -624,7 +624,9 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
ctx->sched.priority = I915_USER_PRIORITY(prio);
ctx->ring_size = PAGE_SIZE;
+ /* Isolate the kernel context from prying eyes and sticky fingers */
GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+ list_del_init(&ctx->link);
return ctx;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e1ae1399c72b..9cc5374401e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1552,9 +1552,12 @@ __execlists_update_reg_state(struct intel_context *ce,
regs[CTX_RING_TAIL + 1] = ring->tail;
/* RPCS */
- if (engine->class == RENDER_CLASS)
+ if (engine->class == RENDER_CLASS) {
regs[CTX_R_PWR_CLK_STATE + 1] =
intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+
+ i915_oa_init_reg_state(engine, ce, regs);
+ }
}
static int
@@ -2966,8 +2969,6 @@ static void execlists_init_reg_state(u32 *regs,
if (rcs) {
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
-
- i915_oa_init_reg_state(engine, ce, regs);
}
regs[CTX_END] = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 357e63beb373..8353589ee31b 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1630,6 +1630,27 @@ static void hsw_disable_metric_set(struct
drm_i915_private *dev_priv)
~GT_NOA_ENABLE));
}
+static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
+ i915_reg_t reg)
+{
+ u32 mmio = i915_mmio_reg_offset(reg);
+ int i;
+
+ /*
+* This arbitrary default will select the 'EU FPU0 Pipeline
+* Active' event. In the future it's anticipated that there
+* will be an explicit 'No Event' we can select, but not yet...
+*/
+ if (!oa_config)
+ return 0;
+
+ for (i = 0; i < oa_config->flex_regs_len; i++) {
+ if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
+ return oa_config->flex_regs[i].value;
+ }
+
+ return 0;
+}
/*
* NB: It must always remain pointer safe to run this even if the OA unit
* has been disabled.
@@ -1663,28 +1684,8 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,
GEN8_OA_COUNTER_RESUME);
for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
- u32 state_offset = ctx_flexeu0 + i * 2;
- u32 mmio = i915_mmio_reg_offset(flex_regs[i]);
-
- /*
-* This arbitrary default will select the 'EU FPU0 Pipeline
-* Active' event. In the future it's anticipated that there
-* will be an explicit 'No Event' we can select, but not yet...
-*/
- u32 value = 0;
-
- if (oa_config) {
- u32 j;
-
- for (j = 0; j < oa_config->flex_regs_len; j++) {
- if
(i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {
- value = oa_config->flex_regs[j].value;
- break;
- }
- }
- }
-
- CTX_REG(reg_state, state_offset, flex_regs[i], value);
+ CTX_REG(reg_state, ctx_flexeu0 + i * 2, flex_regs[i],
+ oa_config_flex_reg(oa_config, flex_regs[i]));
}
CTX_REG(reg_state,
@@ -1692,6 +1693,107 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,
intel_sseu_make_rpcs(i915, &ce->sseu));
}
+struct flex {
+ i915_reg_t reg;
+ u32 offset;
+ u32 value;
+};
+
+static int
+gen8_store_flex(struct i915_request *rq,
+ struct intel_context *ce,
+ const struct flex *flex, unsigned int count)
+{
+ u
Re: [Intel-gfx] [PATCH] drm/i915/oa: Reconfigure contexts on the fly
Quoting Lionel Landwerlin (2019-07-05 14:06:25)
> On 05/07/2019 15:54, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2019-07-05 13:42:51)
> >> Wow nice. I didn't have the courage to actually write it, knowing how
> >> easy it could be to screw an offset and write at random in GGTT...
> >>
> >> I only have one concern below.
> >>
> >> Thanks a lot,
> >>
> >> -Lionel
> >>
> >> On 05/07/2019 15:30, Chris Wilson wrote:
> >>>CTX_REG(reg_state,
> >>> @@ -1692,6 +1693,150 @@ gen8_update_reg_state_unlocked(struct
> >>> intel_context *ce,
> >>>intel_sseu_make_rpcs(i915, &ce->sseu));
> >>>}
> >>>
> >>> +struct flex {
> >>> + i915_reg_t reg;
> >>> + u32 offset;
> >>> + u32 value;
> >>> +};
> >>> +
> >>> +static int
> >>> +gen8_store_flex(struct i915_request *rq,
> >>> + struct intel_context *ce,
> >>> + const struct flex *flex, unsigned int count)
> >>> +{
> >>> + u32 offset;
> >>> + u32 *cs;
> >>> +
> >>> + cs = intel_ring_begin(rq, 4 * count);
> >>> + if (IS_ERR(cs))
> >>> + return PTR_ERR(cs);
> >>
> >> Is the right of the kernel context large enough to hold the MI_SDIs for
> >> all the contexts?
> > At the moment we are using 9 registers, add in say 128 bytes tops for
> > the request overhead, that's <300 bytes. The kernel context uses 4k
> > rings, so enough for a few updates before we have to flush. We may have
> > to wait for external rings to idle and be interrupt -- but that's the
> > same as before, including the chance that we may be interrupted in the
> > middle of conversion.
> >
> > The worst case is that we overrun the ring and we should get a juicy
> > warning (GEM_BUG_ON or -ENOSPC) in that case. We can increase the
> > kernel_context ring if that's an issue or just fallback to suballocating
> > a batchbuffer for the updates.
>
>
> Ah, thanks. I didn't notice it was one request per context to reconfigure.
>
> Still I wouldn't want to have this fail somewhat randomly because
> something else stayed on the HW just a bit too long.
Same problem we have now, since the wait-for-idle may randomly be
interrupted (as may the mapping of the context images).
> Maybe checking the available space in the ring in
> gen8_configure_all_contexts() and wait on last_request if there isn't
> enough?
The wait is automatic by virtue of intel_ring_begin. The error I was
alluding to before is that if we try and create a packet
(intel_ring_begin) too large, it will fail an assert. The number of
registers we need to write should have an upper bound, we should be able
to spot a problem before it happens.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/oa: Reconfigure contexts on the fly
On 05/07/2019 15:54, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-05 13:42:51)
Wow nice. I didn't have the courage to actually write it, knowing how
easy it could be to screw an offset and write at random in GGTT...
I only have one concern below.
Thanks a lot,
-Lionel
On 05/07/2019 15:30, Chris Wilson wrote:
CTX_REG(reg_state,
@@ -1692,6 +1693,150 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,
intel_sseu_make_rpcs(i915, &ce->sseu));
}
+struct flex {
+ i915_reg_t reg;
+ u32 offset;
+ u32 value;
+};
+
+static int
+gen8_store_flex(struct i915_request *rq,
+ struct intel_context *ce,
+ const struct flex *flex, unsigned int count)
+{
+ u32 offset;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4 * count);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
Is the right of the kernel context large enough to hold the MI_SDIs for
all the contexts?
At the moment we are using 9 registers, add in say 128 bytes tops for
the request overhead, that's <300 bytes. The kernel context uses 4k
rings, so enough for a few updates before we have to flush. We may have
to wait for external rings to idle and be interrupt -- but that's the
same as before, including the chance that we may be interrupted in the
middle of conversion.
The worst case is that we overrun the ring and we should get a juicy
warning (GEM_BUG_ON or -ENOSPC) in that case. We can increase the
kernel_context ring if that's an issue or just fallback to suballocating
a batchbuffer for the updates.
Ah, thanks. I didn't notice it was one request per context to reconfigure.
Still I wouldn't want to have this fail somewhat randomly because
something else stayed on the HW just a bit too long.
Maybe checking the available space in the ring in
gen8_configure_all_contexts() and wait on last_request if there isn't
enough?
-Lionel
+static int
+gen8_emit_oa_config(struct i915_request *rq,
+ struct intel_context *ce,
+ const struct i915_oa_config *oa_config,
+ bool self)
+{
+ struct drm_i915_private *i915 = rq->i915;
+ /* The MMIO offsets for Flex EU registers aren't contiguous */
+ const u32 ctx_flexeu0 = i915->perf.oa.ctx_flexeu0_offset;
+#define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N))
+ struct flex regs[] = {
+ {
+ GEN8_R_PWR_CLK_STATE,
+ CTX_R_PWR_CLK_STATE,
+ intel_sseu_make_rpcs(i915, &ce->sseu)
+ },
+ {
+ GEN8_OACTXCONTROL,
+ i915->perf.oa.ctx_oactxctrl_offset,
+ ((i915->perf.oa.period_exponent <<
GEN8_OA_TIMER_PERIOD_SHIFT) |
+ (i915->perf.oa.periodic ? GEN8_OA_TIMER_ENABLE : 0) |
+ GEN8_OA_COUNTER_RESUME)
+ },
+ { EU_PERF_CNTL0, ctx_flexeuN(0) },
+ { EU_PERF_CNTL1, ctx_flexeuN(1) },
+ { EU_PERF_CNTL2, ctx_flexeuN(2) },
+ { EU_PERF_CNTL3, ctx_flexeuN(3) },
+ { EU_PERF_CNTL4, ctx_flexeuN(4) },
+ { EU_PERF_CNTL5, ctx_flexeuN(5) },
+ { EU_PERF_CNTL6, ctx_flexeuN(6) },
+ };
+#undef ctx_flexeuN
+ int i;
+
+ for (i = 2; i < ARRAY_SIZE(regs); i++)
+ regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
I guess this mapping could be done only once in
gen8_configure_all_contexts().
Ah, it's just ce->sseu giving the appearance of it being context
specific :)
-Chris
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Re: [Intel-gfx] [PATCH v7 07/11] drm: Add Content protection type property
On Thu, 4 Jul 2019 16:06:05 +0530
Ramalingam C wrote:
> On 2019-07-04 at 14:11:59 +0300, Pekka Paalanen wrote:
> > On Tue, 7 May 2019 21:57:41 +0530
> > Ramalingam C wrote:
> >
> > > This patch adds a DRM ENUM property to the selected connectors.
> > > This property is used for mentioning the protected content's type
> > > from userspace to kernel HDCP authentication.
> > >
> > > Type of the stream is decided by the protected content providers.
> > > Type 0 content can be rendered on any HDCP protected display wires.
> > > But Type 1 content can be rendered only on HDCP2.2 protected paths.
> > >
> > > So when a userspace sets this property to Type 1 and starts the HDCP
> > > enable, kernel will honour it only if HDCP2.2 authentication is through
> > > for type 1. Else HDCP enable will be failed.
> > >
> > > Need ACK for this new conenctor property from userspace consumer.
> > >
> > > v2:
> > > cp_content_type is replaced with content_protection_type [daniel]
> > > check at atomic_set_property is removed [Maarten]
> > > v3:
> > > %s/content_protection_type/hdcp_content_type [Pekka]
> > > v4:
> > > property is created for the first requested connector and then reused.
> > > [Danvet]
> > > v5:
> > > kernel doc nits addressed [Daniel]
> > > Rebased as part of patch reordering.
> > >
> > > Signed-off-by: Ramalingam C
> > > Reviewed-by: Daniel Vetter
> > > ---
> > > drivers/gpu/drm/drm_atomic_uapi.c | 4
> > > drivers/gpu/drm/drm_connector.c | 18
> > > drivers/gpu/drm/drm_hdcp.c| 36 ++-
> > > drivers/gpu/drm/i915/intel_hdcp.c | 4 +++-
> > > include/drm/drm_connector.h | 7 ++
> > > include/drm/drm_hdcp.h| 2 +-
> > > include/drm/drm_mode_config.h | 6 ++
> > > include/uapi/drm/drm_mode.h | 4
> > > 8 files changed, 78 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > > b/drivers/gpu/drm/drm_atomic_uapi.c
> > > index 4131e669785a..a85f3ccfe699 100644
> > > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > > @@ -738,6 +738,8 @@ static int drm_atomic_connector_set_property(struct
> > > drm_connector *connector,
> > > return -EINVAL;
> > > }
> > > state->content_protection = val;
> > > + } else if (property == config->hdcp_content_type_property) {
> > > + state->hdcp_content_type = val;
> > > } else if (property == connector->colorspace_property) {
> > > state->colorspace = val;
> > > } else if (property == config->writeback_fb_id_property) {
> > > @@ -816,6 +818,8 @@ drm_atomic_connector_get_property(struct
> > > drm_connector *connector,
> > > *val = state->scaling_mode;
> > > } else if (property == config->content_protection_property) {
> > > *val = state->content_protection;
> > > + } else if (property == config->hdcp_content_type_property) {
> > > + *val = state->hdcp_content_type;
> > > } else if (property == config->writeback_fb_id_property) {
> > > /* Writeback framebuffer is one-shot, write and forget */
> > > *val = 0;
> > > diff --git a/drivers/gpu/drm/drm_connector.c
> > > b/drivers/gpu/drm/drm_connector.c
> > > index 764c7903edf6..de9e06583e8c 100644
> > > --- a/drivers/gpu/drm/drm_connector.c
> > > +++ b/drivers/gpu/drm/drm_connector.c
> >
> > Hi,
> >
> > below I have some comments and questions before I can say whether
> > https://gitlab.freedesktop.org/wayland/weston/merge_requests/48
> > adheres to this specification.
> >
> > > @@ -955,6 +955,24 @@ static const struct drm_prop_enum_list
> > > hdmi_colorspaces[] = {
> > > * the value transitions from ENABLED to DESIRED. This signifies
> > > the link
> > > * is no longer protected and userspace should take appropriate
> > > action
> > > * (whatever that might be).
> > > + * HDCP Content Type:
> > > + * This property is used by the userspace to configure the kernel
> > > with
> > > + * to be displayed stream's content type. Content Type of a stream
> > > is
> > > + * decided by the owner of the stream, as HDCP Type0 or HDCP Type1.
> > > + *
> > > + * The value of the property can be one the below:
> > > + * - DRM_MODE_HDCP_CONTENT_TYPE0 = 0
> >
> > If this doc is meant as the UAPI doc, it needs to use the string names
> > for enum property values, not the C language definitions (integers).
> kernel documentation for all other properties followed this way. We
> could add string associated to the enum state too for this property.
Hi,
I don't really care what kernel internal APIs use, this may well be
correct for them, but the UAPI uses strings.
Because the kernel internal and UAPI docs are mixed up, it will be hard
to write proper docs. I guess can't help it this time.
It would be really good if the enum value strings were explicitly
prese
Re: [Intel-gfx] [PATCH] drm/i915/oa: Reconfigure contexts on the fly
Quoting Lionel Landwerlin (2019-07-05 13:42:51)
> Wow nice. I didn't have the courage to actually write it, knowing how
> easy it could be to screw an offset and write at random in GGTT...
>
> I only have one concern below.
>
> Thanks a lot,
>
> -Lionel
>
> On 05/07/2019 15:30, Chris Wilson wrote:
> > CTX_REG(reg_state,
> > @@ -1692,6 +1693,150 @@ gen8_update_reg_state_unlocked(struct intel_context
> > *ce,
> > intel_sseu_make_rpcs(i915, &ce->sseu));
> > }
> >
> > +struct flex {
> > + i915_reg_t reg;
> > + u32 offset;
> > + u32 value;
> > +};
> > +
> > +static int
> > +gen8_store_flex(struct i915_request *rq,
> > + struct intel_context *ce,
> > + const struct flex *flex, unsigned int count)
> > +{
> > + u32 offset;
> > + u32 *cs;
> > +
> > + cs = intel_ring_begin(rq, 4 * count);
> > + if (IS_ERR(cs))
> > + return PTR_ERR(cs);
>
>
> Is the right of the kernel context large enough to hold the MI_SDIs for
> all the contexts?
At the moment we are using 9 registers, add in say 128 bytes tops for
the request overhead, that's <300 bytes. The kernel context uses 4k
rings, so enough for a few updates before we have to flush. We may have
to wait for external rings to idle and be interrupt -- but that's the
same as before, including the chance that we may be interrupted in the
middle of conversion.
The worst case is that we overrun the ring and we should get a juicy
warning (GEM_BUG_ON or -ENOSPC) in that case. We can increase the
kernel_context ring if that's an issue or just fallback to suballocating
a batchbuffer for the updates.
> > +static int
> > +gen8_emit_oa_config(struct i915_request *rq,
> > + struct intel_context *ce,
> > + const struct i915_oa_config *oa_config,
> > + bool self)
> > +{
> > + struct drm_i915_private *i915 = rq->i915;
> > + /* The MMIO offsets for Flex EU registers aren't contiguous */
> > + const u32 ctx_flexeu0 = i915->perf.oa.ctx_flexeu0_offset;
> > +#define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N))
> > + struct flex regs[] = {
> > + {
> > + GEN8_R_PWR_CLK_STATE,
> > + CTX_R_PWR_CLK_STATE,
> > + intel_sseu_make_rpcs(i915, &ce->sseu)
> > + },
> > + {
> > + GEN8_OACTXCONTROL,
> > + i915->perf.oa.ctx_oactxctrl_offset,
> > + ((i915->perf.oa.period_exponent <<
> > GEN8_OA_TIMER_PERIOD_SHIFT) |
> > + (i915->perf.oa.periodic ? GEN8_OA_TIMER_ENABLE : 0) |
> > + GEN8_OA_COUNTER_RESUME)
> > + },
> > + { EU_PERF_CNTL0, ctx_flexeuN(0) },
> > + { EU_PERF_CNTL1, ctx_flexeuN(1) },
> > + { EU_PERF_CNTL2, ctx_flexeuN(2) },
> > + { EU_PERF_CNTL3, ctx_flexeuN(3) },
> > + { EU_PERF_CNTL4, ctx_flexeuN(4) },
> > + { EU_PERF_CNTL5, ctx_flexeuN(5) },
> > + { EU_PERF_CNTL6, ctx_flexeuN(6) },
> > + };
> > +#undef ctx_flexeuN
> > + int i;
> > +
> > + for (i = 2; i < ARRAY_SIZE(regs); i++)
> > + regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
>
>
> I guess this mapping could be done only once in
> gen8_configure_all_contexts().
Ah, it's just ce->sseu giving the appearance of it being context
specific :)
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Pull assert_forcewake_active() underneath the lock
== Series Details == Series: drm/i915: Pull assert_forcewake_active() underneath the lock URL : https://patchwork.freedesktop.org/series/63273/ State : success == Summary == CI Bug Log - changes from CI_DRM_6424 -> Patchwork_13545 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13545/ Known issues Here are the changes found in Patchwork_13545 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-process: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-icl-u3/igt@gem_close_r...@basic-process.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13545/fi-icl-u3/igt@gem_close_r...@basic-process.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [FAIL][3] ([fdo#108511]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13545/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7567u: [FAIL][5] ([fdo#109485]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13545/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-dsi: [FAIL][7] ([fdo#103167]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13545/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 Participating hosts (53 -> 47) -- Additional (1): fi-skl-guc Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6424 -> Patchwork_13545 CI_DRM_6424: 53cb3b4e44e36a3a25f8885a3578f8a24f8b35e2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5086: f2985a03e223679c24ae085f247a430e55229e64 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13545: 0c683210f8afde8873fcf3958fdd0af6a5b9feb8 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13545/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 0c683210f8af drm/i915: Pull assert_forcewake_active() underneath the lock == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13545/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/oa: Reconfigure contexts on the fly
On 05/07/2019 15:42, Lionel Landwerlin wrote:
+
+static int
+gen8_store_flex(struct i915_request *rq,
+ struct intel_context *ce,
+ const struct flex *flex, unsigned int count)
+{
+ u32 offset;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4 * count);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
Is the right of the kernel context large enough to hold the MI_SDIs
for all the contexts?
s/right/ring/
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[Intel-gfx] [PATCH 2/2] drm/i915/gt: Remove presumption of RCS0
We now track features correctly instead of probing i915->engine[RCS0]
which is much more flexible and avoids any nasty surprises.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index df5932f5f578..bdf279fa3b2e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -448,12 +448,6 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
if (WARN_ON(mask != engine_mask))
device_info->engine_mask = mask;
- /* We always presume we have at least RCS available for later probing */
- if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
- err = -ENODEV;
- goto cleanup;
- }
-
RUNTIME_INFO(i915)->num_engines = hweight32(mask);
intel_gt_check_and_clear_faults(&i915->gt);
--
2.20.1
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[Intel-gfx] [PATCH 1/2] drm/i915/gt: Apply RCS workarounds to the render class
Treat all render engines to the RCS workarounds, simply to avoid using engine->id when we are trying to think in terms of classes. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d7da094170be..9e069286d3ce 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1354,7 +1354,7 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8)) return; - if (engine->id == RCS0) + if (engine->class == RENDER_CLASS) rcs_engine_wa_init(engine, wal); else xcs_engine_wa_init(engine, wal); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove set but not used variable 'intel_dig_port'
== Series Details == Series: drm/i915: Remove set but not used variable 'intel_dig_port' URL : https://patchwork.freedesktop.org/series/63270/ State : success == Summary == CI Bug Log - changes from CI_DRM_6424 -> Patchwork_13544 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13544/ Known issues Here are the changes found in Patchwork_13544 that come from known issues: ### IGT changes ### Issues hit * igt@gem_basic@create-close: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-icl-u3/igt@gem_ba...@create-close.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13544/fi-icl-u3/igt@gem_ba...@create-close.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13544/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [FAIL][5] ([fdo#108511]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13544/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_hangcheck: - fi-kbl-8809g: [DMESG-WARN][7] ([fdo#111074]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13544/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7567u: [FAIL][9] ([fdo#109485]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13544/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-dsi: [FAIL][11] ([fdo#103167]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13544/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#111074]: https://bugs.freedesktop.org/show_bug.cgi?id=111074 Participating hosts (53 -> 47) -- Additional (1): fi-skl-guc Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6424 -> Patchwork_13544 CI_DRM_6424: 53cb3b4e44e36a3a25f8885a3578f8a24f8b35e2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5086: f2985a03e223679c24ae085f247a430e55229e64 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13544: cae32b0d9a77eccb1b890b9c1c4313dcc6ff6b8d @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13544/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == cae32b0d9a77 drm/i915: Remove set but not used variable 'intel_dig_port' == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13544/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/oa: Reconfigure contexts on the fly
Wow nice. I didn't have the courage to actually write it, knowing how
easy it could be to screw an offset and write at random in GGTT...
I only have one concern below.
Thanks a lot,
-Lionel
On 05/07/2019 15:30, Chris Wilson wrote:
Avoid a global idle barrier by reconfiguring each context by rewriting
them with MI_STORE_DWORD from the kernel context.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +-
drivers/gpu/drm/i915/i915_perf.c| 255 +++-
3 files changed, 200 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e367dce2a696..1f0d10bb88c1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -624,7 +624,9 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
ctx->sched.priority = I915_USER_PRIORITY(prio);
ctx->ring_size = PAGE_SIZE;
+ /* Isolate the kernel context from prying eyes and sticky fingers */
GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+ list_del_init(&ctx->link);
return ctx;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e1ae1399c72b..9cc5374401e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1552,9 +1552,12 @@ __execlists_update_reg_state(struct intel_context *ce,
regs[CTX_RING_TAIL + 1] = ring->tail;
/* RPCS */
- if (engine->class == RENDER_CLASS)
+ if (engine->class == RENDER_CLASS) {
regs[CTX_R_PWR_CLK_STATE + 1] =
intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+
+ i915_oa_init_reg_state(engine, ce, regs);
+ }
}
static int
@@ -2966,8 +2969,6 @@ static void execlists_init_reg_state(u32 *regs,
if (rcs) {
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
-
- i915_oa_init_reg_state(engine, ce, regs);
}
regs[CTX_END] = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 357e63beb373..a2a0752ffa57 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1630,6 +1630,27 @@ static void hsw_disable_metric_set(struct
drm_i915_private *dev_priv)
~GT_NOA_ENABLE));
}
+static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
+ i915_reg_t reg)
+{
+ u32 mmio = i915_mmio_reg_offset(reg);
+ int i;
+
+ /*
+* This arbitrary default will select the 'EU FPU0 Pipeline
+* Active' event. In the future it's anticipated that there
+* will be an explicit 'No Event' we can select, but not yet...
+*/
+ if (!oa_config)
+ return 0;
+
+ for (i = 0; i < oa_config->flex_regs_len; i++) {
+ if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
+ return oa_config->flex_regs[i].value;
+ }
+
+ return 0;
+}
/*
* NB: It must always remain pointer safe to run this even if the OA unit
* has been disabled.
@@ -1663,28 +1684,8 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,
GEN8_OA_COUNTER_RESUME);
for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
- u32 state_offset = ctx_flexeu0 + i * 2;
- u32 mmio = i915_mmio_reg_offset(flex_regs[i]);
-
- /*
-* This arbitrary default will select the 'EU FPU0 Pipeline
-* Active' event. In the future it's anticipated that there
-* will be an explicit 'No Event' we can select, but not yet...
-*/
- u32 value = 0;
-
- if (oa_config) {
- u32 j;
-
- for (j = 0; j < oa_config->flex_regs_len; j++) {
- if
(i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {
- value = oa_config->flex_regs[j].value;
- break;
- }
- }
- }
-
- CTX_REG(reg_state, state_offset, flex_regs[i], value);
+ CTX_REG(reg_state, ctx_flexeu0 + i * 2, flex_regs[i],
+ oa_config_flex_reg(oa_config, flex_regs[i]));
}
CTX_REG(reg_state,
@@ -1692,6 +1693,150 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,
intel_sseu_make_rpcs(i915, &ce->sseu));
}
+struct flex {
+ i915_reg_t reg;
+ u32 offset;
+ u32 value;
+};
+
+static int
+gen8_store_flex(stru
Re: [Intel-gfx] [PATCH -next] drm/i915: Remove set but not used variable 'encoder'
On Fri, Jul 05, 2019 at 11:31:12AM +, YueHaibing wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/i915/display/intel_dp.c: In function
> 'intel_dp_set_drrs_state':
> drivers/gpu/drm/i915/display/intel_dp.c:6623:24: warning:
> variable 'encoder' set but not used [-Wunused-but-set-variable]
>
> It's never used, so can be removed.Also remove related
> variable 'dig_port'
>
> Signed-off-by: YueHaibing
Applied to drm-intel-next-queued. Thanks for the patch.
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8f7188d71d08..0bdb7ecc5a81 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6620,8 +6620,6 @@ static void intel_dp_set_drrs_state(struct
> drm_i915_private *dev_priv,
> const struct intel_crtc_state *crtc_state,
> int refresh_rate)
> {
> - struct intel_encoder *encoder;
> - struct intel_digital_port *dig_port = NULL;
> struct intel_dp *intel_dp = dev_priv->drrs.dp;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
> @@ -6636,9 +6634,6 @@ static void intel_dp_set_drrs_state(struct
> drm_i915_private *dev_priv,
> return;
> }
>
> - dig_port = dp_to_dig_port(intel_dp);
> - encoder = &dig_port->base;
> -
> if (!intel_crtc) {
> DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
> return;
>
>
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH -next] drm/i915: Remove set but not used variable 'intel_dig_port'
On Fri, Jul 05, 2019 at 11:31:38AM +, YueHaibing wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/i915/display/intel_ddi.c: In function 'intel_ddi_get_config':
> drivers/gpu/drm/i915/display/intel_ddi.c:3774:29: warning:
> variable 'intel_dig_port' set but not used [-Wunused-but-set-variable]
> struct intel_digital_port *intel_dig_port;
>
> It is never used, so can be removed.
>
> Signed-off-by: YueHaibing
Applied to drm-intel-next-queued. Thanks for the patch.
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a4172595c8d8..30e48609db1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3771,7 +3771,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> - struct intel_digital_port *intel_dig_port;
> u32 temp, flags = 0;
>
> /* XXX: DSI transcoder paranoia */
> @@ -3810,7 +3809,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
> case TRANS_DDI_MODE_SELECT_HDMI:
> pipe_config->has_hdmi_sink = true;
> - intel_dig_port = enc_to_dig_port(&encoder->base);
>
> pipe_config->infoframes.enable |=
> intel_hdmi_infoframes_enabled(encoder, pipe_config);
>
>
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove set but not used variable 'encoder'
== Series Details == Series: drm/i915: Remove set but not used variable 'encoder' URL : https://patchwork.freedesktop.org/series/63269/ State : success == Summary == CI Bug Log - changes from CI_DRM_6424 -> Patchwork_13543 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/ Known issues Here are the changes found in Patchwork_13543 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html * igt@i915_selftest@live_hangcheck: - fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([fdo#111074]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html * igt@vgem_basic@mmap: - fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-icl-u3/igt@vgem_ba...@mmap.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/fi-icl-u3/igt@vgem_ba...@mmap.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [FAIL][9] ([fdo#108511]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_contexts: - fi-skl-iommu: [INCOMPLETE][11] ([fdo#111050]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-skl-iommu/igt@i915_selftest@live_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/fi-skl-iommu/igt@i915_selftest@live_contexts.html * igt@i915_selftest@live_hangcheck: - fi-kbl-8809g: [DMESG-WARN][13] ([fdo#111074]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7567u: [FAIL][15] ([fdo#109485]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-dsi: [FAIL][17] ([fdo#103167]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6424/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050 [fdo#111074]: https://bugs.freedesktop.org/show_bug.cgi?id=111074 Participating hosts (53 -> 45) -- Additional (1): fi-skl-guc Missing(9): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6424 -> Patchwork_13543 CI_DRM_6424: 53cb3b4e44e36a3a25f8885a3578f8a24f8b35e2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5086: f2985a03e223679c24ae085f247a430e55229e64 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13543: 544dd644bbc091fab218edefdfea369485376a32 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13543/build_32bit.log CALLscripts/checksyscalls.sh
[Intel-gfx] [PATCH] drm/i915/oa: Reconfigure contexts on the fly
Avoid a global idle barrier by reconfiguring each context by rewriting
them with MI_STORE_DWORD from the kernel context.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +-
drivers/gpu/drm/i915/i915_perf.c| 255 +++-
3 files changed, 200 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e367dce2a696..1f0d10bb88c1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -624,7 +624,9 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
ctx->sched.priority = I915_USER_PRIORITY(prio);
ctx->ring_size = PAGE_SIZE;
+ /* Isolate the kernel context from prying eyes and sticky fingers */
GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+ list_del_init(&ctx->link);
return ctx;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e1ae1399c72b..9cc5374401e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1552,9 +1552,12 @@ __execlists_update_reg_state(struct intel_context *ce,
regs[CTX_RING_TAIL + 1] = ring->tail;
/* RPCS */
- if (engine->class == RENDER_CLASS)
+ if (engine->class == RENDER_CLASS) {
regs[CTX_R_PWR_CLK_STATE + 1] =
intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+
+ i915_oa_init_reg_state(engine, ce, regs);
+ }
}
static int
@@ -2966,8 +2969,6 @@ static void execlists_init_reg_state(u32 *regs,
if (rcs) {
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
-
- i915_oa_init_reg_state(engine, ce, regs);
}
regs[CTX_END] = MI_BATCH_BUFFER_END;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 357e63beb373..a2a0752ffa57 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1630,6 +1630,27 @@ static void hsw_disable_metric_set(struct
drm_i915_private *dev_priv)
~GT_NOA_ENABLE));
}
+static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
+ i915_reg_t reg)
+{
+ u32 mmio = i915_mmio_reg_offset(reg);
+ int i;
+
+ /*
+* This arbitrary default will select the 'EU FPU0 Pipeline
+* Active' event. In the future it's anticipated that there
+* will be an explicit 'No Event' we can select, but not yet...
+*/
+ if (!oa_config)
+ return 0;
+
+ for (i = 0; i < oa_config->flex_regs_len; i++) {
+ if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
+ return oa_config->flex_regs[i].value;
+ }
+
+ return 0;
+}
/*
* NB: It must always remain pointer safe to run this even if the OA unit
* has been disabled.
@@ -1663,28 +1684,8 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,
GEN8_OA_COUNTER_RESUME);
for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
- u32 state_offset = ctx_flexeu0 + i * 2;
- u32 mmio = i915_mmio_reg_offset(flex_regs[i]);
-
- /*
-* This arbitrary default will select the 'EU FPU0 Pipeline
-* Active' event. In the future it's anticipated that there
-* will be an explicit 'No Event' we can select, but not yet...
-*/
- u32 value = 0;
-
- if (oa_config) {
- u32 j;
-
- for (j = 0; j < oa_config->flex_regs_len; j++) {
- if
(i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {
- value = oa_config->flex_regs[j].value;
- break;
- }
- }
- }
-
- CTX_REG(reg_state, state_offset, flex_regs[i], value);
+ CTX_REG(reg_state, ctx_flexeu0 + i * 2, flex_regs[i],
+ oa_config_flex_reg(oa_config, flex_regs[i]));
}
CTX_REG(reg_state,
@@ -1692,6 +1693,150 @@ gen8_update_reg_state_unlocked(struct intel_context *ce,
intel_sseu_make_rpcs(i915, &ce->sseu));
}
+struct flex {
+ i915_reg_t reg;
+ u32 offset;
+ u32 value;
+};
+
+static int
+gen8_store_flex(struct i915_request *rq,
+ struct intel_context *ce,
+ const struct flex *flex, unsigned int count)
+{
+ u32 offset;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4 * count);
+ if (IS_ERR(cs))
+
[Intel-gfx] [PATCH] drm/i915: Pull assert_forcewake_active() underneath the lock
Make no assumption that something in the background is not acquiring the fw_domain -- but we still do not track owner so assume that any active domain is intended by the caller. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_uncore.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index bb9e0da30e94..5f0367fd3200 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -747,6 +747,8 @@ void assert_forcewakes_active(struct intel_uncore *uncore, if (!uncore->funcs.force_wake_get) return; + spin_lock_irq(&uncore->lock); + assert_rpm_wakelock_held(uncore->rpm); fw_domains &= uncore->fw_domains; @@ -770,6 +772,8 @@ void assert_forcewakes_active(struct intel_uncore *uncore, domain->id, actual)) break; } + + spin_unlock_irq(&uncore->lock); } /* We give fast paths for the really cool registers */ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH -next] drm/i915: Remove set but not used variable 'intel_dig_port'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/i915/display/intel_ddi.c: In function 'intel_ddi_get_config':
drivers/gpu/drm/i915/display/intel_ddi.c:3774:29: warning:
variable 'intel_dig_port' set but not used [-Wunused-but-set-variable]
struct intel_digital_port *intel_dig_port;
It is never used, so can be removed.
Signed-off-by: YueHaibing
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4172595c8d8..30e48609db1d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3771,7 +3771,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
- struct intel_digital_port *intel_dig_port;
u32 temp, flags = 0;
/* XXX: DSI transcoder paranoia */
@@ -3810,7 +3809,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
case TRANS_DDI_MODE_SELECT_HDMI:
pipe_config->has_hdmi_sink = true;
- intel_dig_port = enc_to_dig_port(&encoder->base);
pipe_config->infoframes.enable |=
intel_hdmi_infoframes_enabled(encoder, pipe_config);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH -next] drm/i915: Remove set but not used variable 'encoder'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/i915/display/intel_dp.c: In function 'intel_dp_set_drrs_state':
drivers/gpu/drm/i915/display/intel_dp.c:6623:24: warning:
variable 'encoder' set but not used [-Wunused-but-set-variable]
It's never used, so can be removed.Also remove related
variable 'dig_port'
Signed-off-by: YueHaibing
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8f7188d71d08..0bdb7ecc5a81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6620,8 +6620,6 @@ static void intel_dp_set_drrs_state(struct
drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
int refresh_rate)
{
- struct intel_encoder *encoder;
- struct intel_digital_port *dig_port = NULL;
struct intel_dp *intel_dp = dev_priv->drrs.dp;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
@@ -6636,9 +6634,6 @@ static void intel_dp_set_drrs_state(struct
drm_i915_private *dev_priv,
return;
}
- dig_port = dp_to_dig_port(intel_dp);
- encoder = &dig_port->base;
-
if (!intel_crtc) {
DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
return;
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move the renderstate setup under gt/
== Series Details == Series: drm/i915: Move the renderstate setup under gt/ URL : https://patchwork.freedesktop.org/series/63214/ State : success == Summary == CI Bug Log - changes from CI_DRM_6408_full -> Patchwork_13525_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13525_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@close-race: - shard-hsw: [PASS][1] -> [DMESG-FAIL][2] ([fdo#111063]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-hsw8/igt@gem_b...@close-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-hsw5/igt@gem_b...@close-race.html - shard-kbl: [PASS][3] -> [DMESG-FAIL][4] ([fdo#111063]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-kbl3/igt@gem_b...@close-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-kbl2/igt@gem_b...@close-race.html * igt@gem_cpu_reloc@forked: - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-apl5/igt@gem_cpu_re...@forked.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-apl3/igt@gem_cpu_re...@forked.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-iclb1/igt@gem_exec_balan...@smoke.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@kms_busy@basic-modeset-a: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271] / [fdo#109278]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-snb6/igt@kms_b...@basic-modeset-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-snb2/igt@kms_b...@basic-modeset-a.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-apl8/igt@kms_cursor_...@pipe-b-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-apl7/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-glk7/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-glk3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-iclb5/igt@kms_f...@plain-flip-ts-check-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-iclb7/igt@kms_f...@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +5 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#103167]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-skl1/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-skl1/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_plane@plane-panning-top-left-pipe-b-planes: - shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-snb6/igt@kms_pl...@plane-panning-top-left-pipe-b-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-snb2/igt@kms_pl...@plane-panning-top-left-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-skl1/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13525/shard-skl1/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [fdo#110403]) +1 similar issue [25]:
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_eio: Assert the hanging request is correctly identified
Chris Wilson writes:
> Quoting Chris Wilson (2019-07-02 15:23:39)
>> When forcing a reset, it is crucial that the kernel correctly identifies
>> the injected hang. Verify this is the case for reset-stress.
>>
>> Signed-off-by: Chris Wilson
>> ---
>> Keep the igt_spin_free at the end to avoid issues where we fail to
>> bypass the guilty batch.
>
> Ping?
Sorry for the latency.
Patch does does it what it says in the tin.
Reviewed-by: Mika Kuoppala
>
>> ---
>> tests/i915/gem_eio.c | 17 +
>> 1 file changed, 9 insertions(+), 8 deletions(-)
>>
>> diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
>> index 5396a04e2..dc7afb0fd 100644
>> --- a/tests/i915/gem_eio.c
>> +++ b/tests/i915/gem_eio.c
>> @@ -175,7 +175,7 @@ static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
>> unsigned long flags)
>> struct igt_spin_factory opts = {
>> .ctx = ctx,
>> .engine = flags,
>> - .flags = IGT_SPIN_FAST,
>> + .flags = IGT_SPIN_FAST | IGT_SPIN_FENCE_OUT,
>> };
>>
>> if (gem_can_store_dword(fd, opts.engine))
>> @@ -270,12 +270,12 @@ static void check_wait(int fd, uint32_t bo, unsigned
>> int wait, igt_stats_t *st)
>> igt_stats_push(st, igt_nsec_elapsed(&ts));
>> }
>>
>> -static void check_wait_elapsed(int fd, igt_stats_t *st)
>> +static void check_wait_elapsed(const char *prefix, int fd, igt_stats_t *st)
>> {
>> double med, max, limit;
>>
>> - igt_info("Completed %d resets, wakeups took %.3f+-%.3fms
>> (min:%.3fms, median:%.3fms, max:%.3fms)\n",
>> -st->n_values,
>> + igt_info("%s: completed %d resets, wakeups took %.3f+-%.3fms
>> (min:%.3fms, median:%.3fms, max:%.3fms)\n",
>> +prefix, st->n_values,
>> igt_stats_get_mean(st)*1e-6,
>> igt_stats_get_std_deviation(st)*1e-6,
>> igt_stats_get_min(st)*1e-6,
>> @@ -715,8 +715,8 @@ static void test_inflight_internal(int fd, unsigned int
>> wait)
>> close(fd);
>> }
>>
>> -static void reset_stress(int fd,
>> -uint32_t ctx0, unsigned int engine,
>> +static void reset_stress(int fd, uint32_t ctx0,
>> +const char *name, unsigned int engine,
>> unsigned int flags)
>> {
>> const uint32_t bbe = MI_BATCH_BUFFER_END;
>> @@ -759,6 +759,7 @@ static void reset_stress(int fd,
>>
>> /* Wedge after a small delay. */
>> check_wait(fd, obj.handle, 100e3, &stats);
>> + igt_assert_eq(sync_fence_status(hang->out_fence), -EIO);
>>
>> /* Unwedge by forcing a reset. */
>> igt_assert(i915_reset_control(true));
>> @@ -782,7 +783,7 @@ static void reset_stress(int fd,
>> igt_spin_free(fd, hang);
>> gem_context_destroy(fd, ctx);
>> }
>> - check_wait_elapsed(fd, &stats);
>> + check_wait_elapsed(name, fd, &stats);
>> igt_stats_fini(&stats);
>>
>> gem_close(fd, obj.handle);
>> @@ -797,7 +798,7 @@ static void test_reset_stress(int fd, unsigned int flags)
>> unsigned int engine;
>>
>> for_each_engine(fd, engine)
>> - reset_stress(fd, ctx0, engine, flags);
>> + reset_stress(fd, ctx0, e__->name, engine, flags);
>>
>> gem_context_destroy(fd, ctx0);
>> }
>> --
>> 2.20.1
>>
> ___
> igt-dev mailing list
> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/8] drm/i915: Order assert forcewake test
Quoting Chris Wilson (2019-07-05 08:45:57) > Read the current value before computing the expected to ensure that if > the timer does complete early (against our will), it should not cause a > false positive. > > v2: The local irq disable did not prevent the timer from running. > > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin irc r-b, Reviewed-by: Tvrtko Ursulin -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
On Thu, Jul 04, 2019 at 08:55:51AM -0700, Lucas De Marchi wrote:
> On Thu, Jul 04, 2019 at 06:09:04PM +0300, Ville Syrjälä wrote:
> >On Thu, Jul 04, 2019 at 07:54:26AM -0700, Lucas De Marchi wrote:
> >> On Thu, Jul 04, 2019 at 12:18:11PM +0300, Ville Syrjälä wrote:
> >> >On Wed, Jul 03, 2019 at 04:37:32PM -0700, Matt Roper wrote:
> >> >> Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
> >> >> Because of this, both the bspec documentation and our i915 code has used
> >> >> the term "port" when talking about either DDI's or PHY's; it was always
> >> >> easy to tell what terms like "Port A" were referring to from the
> >> >> context.
> >> >>
> >> >> Unfortunately this is starting to break down now that EHL allows PHY-A
> >> >> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
> >> >> PHY-A considered "Port A" or "Port D?" The answer depends on which
> >> >> register we're working with, and even the bspec doesn't do a great job
> >> >> of clarifying this.
> >> >>
> >> >> Let's try to be more explicit about whether we're talking about the DDI
> >> >> or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
> >> >> new 'enum phy' namespace to refer to the PHY in use.
> >> >>
> >> >> This patch just adds the new PHY namespace, new phy-based versions of
> >> >> intel_port_is_*(), and a helper to convert a port to a PHY.
> >> >> Transitioning various areas of the code over to using the PHY namespace
> >> >> will be done in subsequent patches to make review easier. We'll remove
> >> >> the intel_port_is_*() functions at the end of the series when we
> >> >> transition all callers over to using the PHY-based versions.
> >> >>
> >> >> v2:
> >> >> - Convert a few more 'port' uses to 'phy.' (Sparse)
> >> >>
> >> >> v3:
> >> >> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> >> >> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
> >> >>for its bit definitions, even though the register description is
> >> >>given in terms of DDI.
> >> >> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
> >> >>port and create separate ICL+ definitions that work in terms of PHY.
> >> >>
> >> >> v4:
> >> >> - Rebase and resolve conflicts with Imre's TC series.
> >> >> - This patch now just adds the namespace and a few convenience
> >> >>functions; the important changes are now split out into separate
> >> >>patches to make review easier.
> >> >>
> >> >> Suggested-by: Ville Syrjala
> >> >> Cc: José Roberto de Souza
> >> >> Cc: Lucas De Marchi
> >> >> Cc: Ville Syrjälä
> >> >> Cc: Imre Deak
> >> >> Cc: Jani Nikula
> >> >> Signed-off-by: Matt Roper
> >> >> ---
> >> >> drivers/gpu/drm/i915/display/intel_display.c | 32 +++-
> >> >> drivers/gpu/drm/i915/display/intel_display.h | 16 ++
> >> >> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> >> >> 3 files changed, 49 insertions(+), 1 deletion(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >> >> b/drivers/gpu/drm/i915/display/intel_display.c
> >> >> index 919f5ac844c8..4a85abef93e7 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> >> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct
> >> >> drm_i915_private *dev_priv, enum port port)
> >> >> return false;
> >> >> }
> >> >>
> >> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> >> >> phy)
> >> >> +{
> >> >> + if (phy == PHY_NONE)
> >> >> + return false;
> >> >> +
> >> >> + if (IS_ELKHARTLAKE(dev_priv))
> >> >> + return phy <= PHY_C;
> >> >> +
> >> >> + if (INTEL_GEN(dev_priv) >= 11)
> >> >> + return phy <= PHY_B;
> >> >> +
> >> >> + return false;
> >> >> +}
> >> >> +
> >> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> >> >> port)
> >> >> {
> >> >> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> >> >> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private
> >> >> *dev_priv, enum port port)
> >> >> return false;
> >> >> }
> >> >>
> >> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> >> >> +{
> >> >> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> >> >> + return phy >= PHY_C && phy <= PHY_F;
> >> >> +
> >> >> + return false;
> >> >> +}
> >> >> +
> >> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port
> >> >> port)
> >> >> +{
> >> >> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> >> >> + return PHY_A;
> >> >> +
> >> >> + return (enum phy)port;
> >> >> +}
> >> >> +
> >> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum
> >> >> port port)
> >> >> {
> >> >> - if (!intel_port_is_tc(dev_priv, port))
> >> >> + if (!intel_phy_is_tc(dev_priv, intel_po
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v10)
On Wed, Jul 03, 2019 at 04:03:53PM -0700, Vivek Kasireddy wrote: > This patch adds support for DPLL4 on EHL that include the > following restrictions: > > - DPLL4 cannot be used with DDIA (combo port A internal eDP usage). > DPLL4 can be used with other DDIs, including DDID > (combo port A external usage). > > - DPLL4 cannot be enabled when DC5 or DC6 are enabled. > > - The DPLL4 enable, lock, power enabled, and power state are connected > to the MGPLL1_ENABLE register. > > v2: (suggestions from Bob Paauwe) > - Rework ehl_get_dpll() function to call intel_find_shared_dpll() and > iterate twice: once for Combo plls and once for MG plls. > > - Use MG pll funcs for DPLL4 instead of creating new ones and modify > mg_pll_enable to include the restrictions for EHL. > > v3: Fix compilation error > > v4: (suggestions from Lucas and Ville) > - Treat DPLL4 as a combo phy PLL and not as MG PLL > - Disable DC states when this DPLL is being enabled > - Reuse icl_get_dpll instead of creating a separate one for EHL > > v5: (suggestion from Ville) > - Refcount the DC OFF power domains during the enabling and disabling > of this DPLL. > > v6: rebase > > v7: (suggestion from Imre) > - Add a new power domain instead of iterating over the domains > assoicated with DC OFF power well. > > v8: (Ville and Imre) > - Rename POWER_DOMAIN_DPLL4 TO POWER_DOMAIN_DPLL_DC_OFF > - Grab a reference in intel_modeset_setup_hw_state() if this > DPLL was already enabled perhaps by BIOS. > - Check for the port type instead of the encoder > > v9: (Ville) > - Move the block of code that grabs a reference to the power domain > POWER_DOMAIN_DPLL_DC_OFF to intel_modeset_readout_hw_state() to ensure > that there is a reference present before this DPLL might get disabled. > > v10: rebase > > Cc: José Roberto de Souza > Cc: Ville Syrjälä > Cc: Matt Roper > Cc: Imre Deak > Signed-off-by: Vivek Kasireddy lgtm. Picked up José's r-b from an earlier posting (in the future plese collect those yourself so they don't get lost), and pushed to dinq. Thanks for the patch. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ehl: Add support for DPLL4 (v10)
On Fri, Jul 05, 2019 at 03:11:05AM -, Patchwork wrote: > == Series Details == > > Series: drm/i915/ehl: Add support for DPLL4 (v10) > URL : https://patchwork.freedesktop.org/series/63171/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_6405_full -> Patchwork_13517_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_13517_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_13517_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_13517_full: > > ### IGT changes ### > > Possible regressions > > * igt@gem_busy@close-race: > - shard-snb: [PASS][1] -> [DMESG-FAIL][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-snb4/igt@gem_b...@close-race.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-snb6/igt@gem_b...@close-race.html Some kind of gem fail. Nothing to do with this patch. <4> [602.084517] general protection fault: [#1] PREEMPT SMP PTI <4> [602.084530] CPU: 1 PID: 2824 Comm: gem_busy Tainted: G U 5.2.0-rc7-CI-Patchwork_13517+ #1 <4> [602.084542] Hardware name: Dell Inc. XPS 8300 /0Y2MRG, BIOS A06 10/17/2011 <4> [602.084611] RIP: 0010:i915_gem_busy_ioctl+0x136/0x5d0 [i915] -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915: Order assert forcewake test
== Series Details ==
Series: series starting with [1/8] drm/i915: Order assert forcewake test
URL : https://patchwork.freedesktop.org/series/63256/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6423 -> Patchwork_13542
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/
Known issues
Here are the changes found in Patchwork_13542 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- fi-ilk-650: [PASS][3] -> [DMESG-WARN][4] ([fdo#106387])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-ilk-650/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-ilk-650/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][7] -> [INCOMPLETE][8] ([fdo#107807])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-skl-6600u/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-skl-6600u/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#109485])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][11] -> [FAIL][12] ([fdo#103167])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* {igt@gem_ctx_switch@rcs0}:
- fi-icl-guc: [INCOMPLETE][13] ([fdo#107713]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][15] ([fdo#107718]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][17] ([fdo#111050]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-kbl-7500u: [DMESG-WARN][19] ([fdo#111074]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html
* igt@kms_busy@basic-flip-c:
- fi-skl-6770hq: [SKIP][21] ([fdo#109271] / [fdo#109278]) ->
[PASS][22] +2 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-skl-6770hq/igt@kms_b...@basic-flip-c.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-skl-6770hq/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][23] ([fdo#109485]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: [SKIP][25] ([fdo#109271]) -> [PASS][26] +23 similar
issues
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6423/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13542/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html
{name}: This
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/vkms: prime import support
== Series Details == Series: drm/vkms: prime import support URL : https://patchwork.freedesktop.org/series/63213/ State : success == Summary == CI Bug Log - changes from CI_DRM_6408_full -> Patchwork_13524_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13524_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@close-race: - shard-kbl: [PASS][1] -> [DMESG-FAIL][2] ([fdo#111063]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-kbl3/igt@gem_b...@close-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-kbl6/igt@gem_b...@close-race.html * igt@gem_wait@write-wait-bcs0: - shard-hsw: [PASS][3] -> [INCOMPLETE][4] ([fdo#103540]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-hsw1/igt@gem_w...@write-wait-bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-hsw4/igt@gem_w...@write-wait-bcs0.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-apl5/igt@gem_workarou...@suspend-resume-context.html * igt@kms_addfb_basic@no-handle: - shard-hsw: [PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-hsw1/igt@kms_addfb_ba...@no-handle.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-hsw4/igt@kms_addfb_ba...@no-handle.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@plain-flip-ts-check: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#100368]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-glk7/igt@kms_f...@plain-flip-ts-check.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-glk3/igt@kms_f...@plain-flip-ts-check.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-iclb2/igt@kms_frontbuffer_track...@fbc-stridechange.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-iclb8/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108040]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-skl1/igt@kms_frontbuffer_track...@fbc-tilingchange.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-skl3/igt@kms_frontbuffer_track...@fbc-tilingchange.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#103167]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-skl1/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-skl3/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-skl1/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-skl3/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109642] / [fdo#111068]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-iclb2/igt@kms_psr2...@frontbuffer.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13524/shard-iclb3/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#108341]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6408/shard-iclb7/igt@kms_psr@no_drrs.html [26]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/8] drm/i915: Order assert forcewake test
== Series Details == Series: series starting with [1/8] drm/i915: Order assert forcewake test URL : https://patchwork.freedesktop.org/series/63256/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Order assert forcewake test Okay! Commit: drm/i915: Teach execbuffer to take the engine wakeref not GT Okay! Commit: drm/i915/gt: Track timeline activeness in enter/exit Okay! Commit: drm/i915/gt: Convert timeline tracking to spinlock Okay! Commit: drm/i915/gt: Guard timeline pinning with its own mutex Okay! Commit: drm/i915: Protect request retirement with timeline->mutex Okay! Commit: drm/i915: Replace struct_mutex for batch pool serialisation +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/gt: Use intel_gt as the primary object for handling resets -O:drivers/gpu/drm/i915/gt/intel_reset.c:1292:5: warning: context imbalance in 'i915_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_reset.c:1276:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block -./drivers/gpu/drm/i915/gt/selftest_timeline.c:91:38: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/gt/selftest_timeline.c:91:38: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/gt/selftest_timeline.c:94:44: warning: expression using sizeof(void) -./drivers/gpu/drm/i915/gt/selftest_timeline.c:94:44: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/gt/selftest_timeline.c:92:38: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/gt/selftest_timeline.c:92:38: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/gt/selftest_timeline.c:95:44: warning: expression using sizeof(void) +./drivers/gpu/drm/i915/gt/selftest_timeline.c:95:44: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/i915: Order assert forcewake test
== Series Details == Series: series starting with [1/8] drm/i915: Order assert forcewake test URL : https://patchwork.freedesktop.org/series/63256/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1601f21b3929 drm/i915: Order assert forcewake test 477c5b107129 drm/i915: Teach execbuffer to take the engine wakeref not GT 6a8be28690b9 drm/i915/gt: Track timeline activeness in enter/exit 396a6d039cdc drm/i915/gt: Convert timeline tracking to spinlock 68c0019139cc drm/i915/gt: Guard timeline pinning with its own mutex 1c1420202474 drm/i915: Protect request retirement with timeline->mutex 9b040a14b98f drm/i915: Replace struct_mutex for batch pool serialisation -:305: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #305: new file mode 100644 -:310: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #310: FILE: drivers/gpu/drm/i915/gt/intel_engine_pool.c:1: +/* -:311: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #311: FILE: drivers/gpu/drm/i915/gt/intel_engine_pool.c:2: + * SPDX-License-Identifier: MIT -:482: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #482: FILE: drivers/gpu/drm/i915/gt/intel_engine_pool.h:1: +/* -:483: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #483: FILE: drivers/gpu/drm/i915/gt/intel_engine_pool.h:2: + * SPDX-License-Identifier: MIT -:522: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #522: FILE: drivers/gpu/drm/i915/gt/intel_engine_pool_types.h:1: +/* -:523: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #523: FILE: drivers/gpu/drm/i915/gt/intel_engine_pool_types.h:2: + * SPDX-License-Identifier: MIT -:539: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #539: FILE: drivers/gpu/drm/i915/gt/intel_engine_pool_types.h:18: + spinlock_t lock; total: 0 errors, 7 warnings, 1 checks, 595 lines checked 92549228548f drm/i915/gt: Use intel_gt as the primary object for handling resets -:1822: WARNING:MEMORY_BARRIER: memory barrier without comment #1822: FILE: drivers/gpu/drm/i915/gt/intel_reset.c:1269: + smp_mb__after_atomic(); -:2047: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'W' - possible side-effects? #2047: FILE: drivers/gpu/drm/i915/gt/intel_reset.h:64: +#define intel_wedge_on_timeout(W, GT, TIMEOUT) \ + for (__intel_init_wedge((W), (GT), (TIMEOUT), __func__);\ +(W)->gt; \ +__intel_fini_wedge((W))) -:2062: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #2062: new file mode 100644 total: 0 errors, 2 warnings, 1 checks, 3276 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for HDCP2.2 Phase II (rev10)
== Series Details ==
Series: HDCP2.2 Phase II (rev10)
URL : https://patchwork.freedesktop.org/series/57232/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6422 -> Patchwork_13541
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_13541 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13541, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13541:
### IGT changes ###
Possible regressions
* igt@gem_workarounds@basic-read:
- fi-icl-dsi: NOTRUN -> [SKIP][1] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-icl-dsi/igt@gem_workarou...@basic-read.html
- fi-cml-u2: [PASS][2] -> [SKIP][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-cml-u2/igt@gem_workarou...@basic-read.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-cml-u2/igt@gem_workarou...@basic-read.html
- fi-icl-u3: NOTRUN -> [SKIP][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-icl-u3/igt@gem_workarou...@basic-read.html
- fi-icl-u2: [PASS][5] -> [SKIP][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-icl-u2/igt@gem_workarou...@basic-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-icl-u2/igt@gem_workarou...@basic-read.html
* {igt@kms_content_protection@srm} (NEW):
- fi-cfl-8109u: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-cfl-8109u/igt@kms_content_protect...@srm.html
- {fi-icl-u4}:NOTRUN -> [SKIP][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-icl-u4/igt@kms_content_protect...@srm.html
- fi-skl-lmem:NOTRUN -> [FAIL][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-skl-lmem/igt@kms_content_protect...@srm.html
- fi-apl-guc: NOTRUN -> [FAIL][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-apl-guc/igt@kms_content_protect...@srm.html
- fi-skl-gvtdvm: NOTRUN -> [FAIL][11]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-skl-gvtdvm/igt@kms_content_protect...@srm.html
- fi-cml-u2: NOTRUN -> [SKIP][12]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-cml-u2/igt@kms_content_protect...@srm.html
Warnings
* igt@gem_workarounds@basic-read:
- fi-hsw-4770r: [SKIP][13] ([fdo#109271]) -> [FAIL][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-hsw-4770r/igt@gem_workarou...@basic-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-hsw-4770r/igt@gem_workarou...@basic-read.html
- fi-snb-2600:[SKIP][15] ([fdo#109271]) -> [FAIL][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-snb-2600/igt@gem_workarou...@basic-read.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-snb-2600/igt@gem_workarou...@basic-read.html
- fi-ivb-3770:[SKIP][17] ([fdo#109271]) -> [FAIL][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-ivb-3770/igt@gem_workarou...@basic-read.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-ivb-3770/igt@gem_workarou...@basic-read.html
- fi-byt-n2820: [SKIP][19] ([fdo#109271]) -> [FAIL][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-byt-n2820/igt@gem_workarou...@basic-read.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-byt-n2820/igt@gem_workarou...@basic-read.html
- fi-hsw-4770:[SKIP][21] ([fdo#109271]) -> [FAIL][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-hsw-4770/igt@gem_workarou...@basic-read.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-hsw-4770/igt@gem_workarou...@basic-read.html
- fi-byt-j1900: [SKIP][23] ([fdo#109271]) -> [FAIL][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-byt-j1900/igt@gem_workarou...@basic-read.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-byt-j1900/igt@gem_workarou...@basic-read.html
- fi-gdg-551: [SKIP][25] ([fdo#109271]) -> [FAIL][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-gdg-551/igt@gem_workarou...@basic-read.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13541/fi-gdg-551/igt@gem_workarou...@basic-read.html
- fi-blb-e6850: [SKIP][27] ([fdo#109271]) -> [FAIL][28]
[27]:
https://intel-gfx-ci.01.org/tree/dr
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP2.2 Phase II (rev10)
== Series Details ==
Series: HDCP2.2 Phase II (rev10)
URL : https://patchwork.freedesktop.org/series/57232/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
896a2370f9fe drm: Add Content protection type property
-:104: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#104: FILE: drivers/gpu/drm/drm_hdcp.c:351:
+};
+DRM_ENUM_NAME_FN(drm_get_hdcp_content_type_name,
-:149: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#149: FILE: drivers/gpu/drm/drm_hdcp.c:404:
+ prop = drm_property_create_enum(dev, 0, "HDCP Content Type",
+ drm_hdcp_content_type_enum_list,
-:150: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#150: FILE: drivers/gpu/drm/drm_hdcp.c:405:
+ ARRAY_SIZE(
total: 0 errors, 0 warnings, 3 checks, 165 lines checked
acf44a9d064f drm/i915: Attach content type property
dbaa63e3c359 drm: uevent for connector status change
02c9c78d915a drm/hdcp: update content protection property with uevent
-:68: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#68: FILE: drivers/gpu/drm/drm_hdcp.c:448:
+ drm_sysfs_connector_status_event(connector,
+dev->mode_config.content_protection_property);
total: 0 errors, 0 warnings, 1 checks, 49 lines checked
ae26d53cd3e2 drm/i915: update the hdcp state with uevent
c96deafcd854 drm/hdcp: reference for srm file format
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Order assert forcewake test (rev2)
== Series Details ==
Series: drm/i915: Order assert forcewake test (rev2)
URL : https://patchwork.freedesktop.org/series/63238/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6422 -> Patchwork_13540
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13540/
Known issues
Here are the changes found in Patchwork_13540 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-threads:
- fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-icl-u3/igt@gem_close_r...@basic-threads.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13540/fi-icl-u3/igt@gem_close_r...@basic-threads.html
* igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [PASS][3] -> [DMESG-WARN][4] ([fdo#111074])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13540/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
- fi-kbl-8809g: [PASS][5] -> [DMESG-WARN][6] ([fdo#111074])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13540/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@gem_basic@create-close:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-icl-u3/igt@gem_ba...@create-close.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13540/fi-icl-u3/igt@gem_ba...@create-close.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][9] ([fdo#102614]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13540/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][11] ([fdo#103167]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6422/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13540/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111074]: https://bugs.freedesktop.org/show_bug.cgi?id=111074
Participating hosts (52 -> 46)
--
Additional (1): fi-icl-dsi
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6422 -> Patchwork_13540
CI_DRM_6422: 830a8c536c3a1c62c30447c646735cfebb19c266 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5084: 9f45069f9b5136d07e053d8086e8df51e14332eb @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13540: d0d57f6a7bc12a7e37b4254e7da2cdc8b43da5ee @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13540/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
d0d57f6a7bc1 drm/i915: Order assert forcewake test
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13540/
___
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_eio: Assert the hanging request is correctly identified
Quoting Chris Wilson (2019-07-02 15:23:39)
> When forcing a reset, it is crucial that the kernel correctly identifies
> the injected hang. Verify this is the case for reset-stress.
>
> Signed-off-by: Chris Wilson
> ---
> Keep the igt_spin_free at the end to avoid issues where we fail to
> bypass the guilty batch.
Ping?
> ---
> tests/i915/gem_eio.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
> index 5396a04e2..dc7afb0fd 100644
> --- a/tests/i915/gem_eio.c
> +++ b/tests/i915/gem_eio.c
> @@ -175,7 +175,7 @@ static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
> unsigned long flags)
> struct igt_spin_factory opts = {
> .ctx = ctx,
> .engine = flags,
> - .flags = IGT_SPIN_FAST,
> + .flags = IGT_SPIN_FAST | IGT_SPIN_FENCE_OUT,
> };
>
> if (gem_can_store_dword(fd, opts.engine))
> @@ -270,12 +270,12 @@ static void check_wait(int fd, uint32_t bo, unsigned
> int wait, igt_stats_t *st)
> igt_stats_push(st, igt_nsec_elapsed(&ts));
> }
>
> -static void check_wait_elapsed(int fd, igt_stats_t *st)
> +static void check_wait_elapsed(const char *prefix, int fd, igt_stats_t *st)
> {
> double med, max, limit;
>
> - igt_info("Completed %d resets, wakeups took %.3f+-%.3fms (min:%.3fms,
> median:%.3fms, max:%.3fms)\n",
> -st->n_values,
> + igt_info("%s: completed %d resets, wakeups took %.3f+-%.3fms
> (min:%.3fms, median:%.3fms, max:%.3fms)\n",
> +prefix, st->n_values,
> igt_stats_get_mean(st)*1e-6,
> igt_stats_get_std_deviation(st)*1e-6,
> igt_stats_get_min(st)*1e-6,
> @@ -715,8 +715,8 @@ static void test_inflight_internal(int fd, unsigned int
> wait)
> close(fd);
> }
>
> -static void reset_stress(int fd,
> -uint32_t ctx0, unsigned int engine,
> +static void reset_stress(int fd, uint32_t ctx0,
> +const char *name, unsigned int engine,
> unsigned int flags)
> {
> const uint32_t bbe = MI_BATCH_BUFFER_END;
> @@ -759,6 +759,7 @@ static void reset_stress(int fd,
>
> /* Wedge after a small delay. */
> check_wait(fd, obj.handle, 100e3, &stats);
> + igt_assert_eq(sync_fence_status(hang->out_fence), -EIO);
>
> /* Unwedge by forcing a reset. */
> igt_assert(i915_reset_control(true));
> @@ -782,7 +783,7 @@ static void reset_stress(int fd,
> igt_spin_free(fd, hang);
> gem_context_destroy(fd, ctx);
> }
> - check_wait_elapsed(fd, &stats);
> + check_wait_elapsed(name, fd, &stats);
> igt_stats_fini(&stats);
>
> gem_close(fd, obj.handle);
> @@ -797,7 +798,7 @@ static void test_reset_stress(int fd, unsigned int flags)
> unsigned int engine;
>
> for_each_engine(fd, engine)
> - reset_stress(fd, ctx0, engine, flags);
> + reset_stress(fd, ctx0, e__->name, engine, flags);
>
> gem_context_destroy(fd, ctx0);
> }
> --
> 2.20.1
>
___
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[Intel-gfx] [PATCH 4/8] drm/i915/gt: Convert timeline tracking to spinlock
Convert the list manipulation of active to use spinlocks so that we can
perform the updates from underneath a quick interrupt callback.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c| 13 ++---
drivers/gpu/drm/i915/gt/intel_timeline.c | 12 +---
drivers/gpu/drm/i915/i915_gem.c | 20 ++--
4 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index c03e56628ee2..cfd41e6c54e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -26,7 +26,7 @@ struct intel_gt {
struct i915_ggtt *ggtt;
struct intel_gt_timelines {
- struct mutex mutex; /* protects list */
+ spinlock_t lock; /* protects active_list */
struct list_head active_list;
/* Pack multiple timelines' seqnos into the same page */
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index adfdb908587f..72002c0f9698 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -858,6 +858,7 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
static bool __i915_gem_unset_wedged(struct drm_i915_private *i915)
{
struct i915_gpu_error *error = &i915->gpu_error;
+ struct intel_gt_timelines *timelines = &i915->gt.timelines;
struct intel_timeline *tl;
if (!test_bit(I915_WEDGED, &error->flags))
@@ -878,14 +879,16 @@ static bool __i915_gem_unset_wedged(struct
drm_i915_private *i915)
*
* No more can be submitted until we reset the wedged bit.
*/
- mutex_lock(&i915->gt.timelines.mutex);
- list_for_each_entry(tl, &i915->gt.timelines.active_list, link) {
+ spin_lock(&timelines->lock);
+ list_for_each_entry(tl, &timelines->active_list, link) {
struct i915_request *rq;
rq = i915_active_request_get_unlocked(&tl->last_request);
if (!rq)
continue;
+ spin_unlock(&timelines->lock);
+
/*
* All internal dependencies (i915_requests) will have
* been flushed by the set-wedge, but we may be stuck waiting
@@ -895,8 +898,12 @@ static bool __i915_gem_unset_wedged(struct
drm_i915_private *i915)
*/
dma_fence_default_wait(&rq->fence, false, MAX_SCHEDULE_TIMEOUT);
i915_request_put(rq);
+
+ /* Restart iteration after droping lock */
+ spin_lock(&timelines->lock);
+ tl = list_entry(&timelines->active_list, typeof(*tl), link);
}
- mutex_unlock(&i915->gt.timelines.mutex);
+ spin_unlock(&timelines->lock);
intel_gt_sanitize(&i915->gt, false);
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 4af0b9801d91..355dfc52c804 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -266,7 +266,7 @@ static void timelines_init(struct intel_gt *gt)
{
struct intel_gt_timelines *timelines = >->timelines;
- mutex_init(&timelines->mutex);
+ spin_lock_init(&timelines->lock);
INIT_LIST_HEAD(&timelines->active_list);
spin_lock_init(&timelines->hwsp_lock);
@@ -345,9 +345,9 @@ void intel_timeline_enter(struct intel_timeline *tl)
return;
GEM_BUG_ON(!tl->active_count); /* overflow? */
- mutex_lock(&timelines->mutex);
+ spin_lock(&timelines->lock);
list_add(&tl->link, &timelines->active_list);
- mutex_unlock(&timelines->mutex);
+ spin_unlock(&timelines->lock);
}
void intel_timeline_exit(struct intel_timeline *tl)
@@ -358,9 +358,9 @@ void intel_timeline_exit(struct intel_timeline *tl)
if (--tl->active_count)
return;
- mutex_lock(&timelines->mutex);
+ spin_lock(&timelines->lock);
list_del(&tl->link);
- mutex_unlock(&timelines->mutex);
+ spin_unlock(&timelines->lock);
/*
* Since this timeline is idle, all bariers upon which we were waiting
@@ -548,8 +548,6 @@ static void timelines_fini(struct intel_gt *gt)
GEM_BUG_ON(!list_empty(&timelines->active_list));
GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
-
- mutex_destroy(&timelines->mutex);
}
void intel_timelines_fini(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7ade42b8ec99..b6f3baa74da4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -909,20 +909,20 @@ static int wait_for_engines(struct drm_i915_private *i915)
static long
wait_for_timelines(struct drm_i915_private *i915,
-
[Intel-gfx] [PATCH 3/8] drm/i915/gt: Track timeline activeness in enter/exit
Lift moving the timeline to/from the active_list on enter/exit in order
to shorten the active tracking span in comparison to the existing
pin/unpin.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 1 -
drivers/gpu/drm/i915/gt/intel_context.c | 2 +
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +
drivers/gpu/drm/i915/gt/intel_timeline.c | 98 +++
drivers/gpu/drm/i915/gt/intel_timeline.h | 3 +-
.../gpu/drm/i915/gt/intel_timeline_types.h| 1 +
drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 -
8 files changed, 46 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 4d774376f5b8..93d188526457 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -38,7 +38,6 @@ static void i915_gem_park(struct drm_i915_private *i915)
i915_gem_batch_pool_fini(&engine->batch_pool);
}
- intel_timelines_park(i915);
i915_vma_parked(i915);
i915_globals_park();
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 1110fc8f657a..0111a18c1f02 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -232,10 +232,12 @@ int __init i915_global_context_init(void)
void intel_context_enter_engine(struct intel_context *ce)
{
intel_engine_pm_get(ce->engine);
+ intel_timeline_enter(ce->ring->timeline);
}
void intel_context_exit_engine(struct intel_context *ce)
{
+ intel_timeline_exit(ce->ring->timeline);
intel_engine_pm_put(ce->engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 84e432abe8e0..9751a02d86bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -88,6 +88,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
/* Check again on the next retirement. */
engine->wakeref_serial = engine->serial + 1;
+ intel_timeline_enter(rq->timeline);
i915_request_add_barriers(rq);
__i915_request_commit(rq);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e1ae1399c72b..473c9ae8818c 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3188,6 +3188,8 @@ static void virtual_context_enter(struct intel_context
*ce)
for (n = 0; n < ve->num_siblings; n++)
intel_engine_pm_get(ve->siblings[n]);
+
+ intel_timeline_enter(ce->ring->timeline);
}
static void virtual_context_exit(struct intel_context *ce)
@@ -3195,6 +3197,8 @@ static void virtual_context_exit(struct intel_context *ce)
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
unsigned int n;
+ intel_timeline_exit(ce->ring->timeline);
+
for (n = 0; n < ve->num_siblings; n++)
intel_engine_pm_put(ve->siblings[n]);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 6daa9eb59e19..4af0b9801d91 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -278,64 +278,11 @@ void intel_timelines_init(struct drm_i915_private *i915)
timelines_init(&i915->gt);
}
-static void timeline_add_to_active(struct intel_timeline *tl)
-{
- struct intel_gt_timelines *gt = &tl->gt->timelines;
-
- mutex_lock(>->mutex);
- list_add(&tl->link, >->active_list);
- mutex_unlock(>->mutex);
-}
-
-static void timeline_remove_from_active(struct intel_timeline *tl)
-{
- struct intel_gt_timelines *gt = &tl->gt->timelines;
-
- mutex_lock(>->mutex);
- list_del(&tl->link);
- mutex_unlock(>->mutex);
-}
-
-static void timelines_park(struct intel_gt *gt)
-{
- struct intel_gt_timelines *timelines = >->timelines;
- struct intel_timeline *timeline;
-
- mutex_lock(&timelines->mutex);
- list_for_each_entry(timeline, &timelines->active_list, link) {
- /*
-* All known fences are completed so we can scrap
-* the current sync point tracking and start afresh,
-* any attempt to wait upon a previous sync point
-* will be skipped as the fence was signaled.
-*/
- i915_syncmap_free(&timeline->sync);
- }
- mutex_unlock(&timelines->mutex);
-}
-
-/**
- * intel_timelines_park - called when the driver idles
- * @i915: the drm_i915_private device
- *
- * When the driver is completely idle, we know that all of our sync points
- * have been signaled and our tracking is then entirely redundant. Any request
- * to wait upon an older sync point will be completed instantly as we know
[Intel-gfx] [PATCH 5/8] drm/i915/gt: Guard timeline pinning with its own mutex
In preparation for removing struct_mutex from around context retirement,
we need to make timeline pinning safe. Since multiple engines/contexts
can share a single timeline, it needs to be protected by a mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 27 +--
.../gpu/drm/i915/gt/intel_timeline_types.h| 2 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 6 ++---
3 files changed, 16 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 355dfc52c804..7b476cd55dac 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -211,9 +211,9 @@ int intel_timeline_init(struct intel_timeline *timeline,
void *vaddr;
kref_init(&timeline->kref);
+ atomic_set(&timeline->pin_count, 0);
timeline->gt = gt;
- timeline->pin_count = 0;
timeline->has_initial_breadcrumb = !hwsp;
timeline->hwsp_cacheline = NULL;
@@ -280,7 +280,7 @@ void intel_timelines_init(struct drm_i915_private *i915)
void intel_timeline_fini(struct intel_timeline *timeline)
{
- GEM_BUG_ON(timeline->pin_count);
+ GEM_BUG_ON(atomic_read(&timeline->pin_count));
GEM_BUG_ON(!list_empty(&timeline->requests));
if (timeline->hwsp_cacheline)
@@ -314,33 +314,31 @@ int intel_timeline_pin(struct intel_timeline *tl)
{
int err;
- if (tl->pin_count++)
+ if (atomic_add_unless(&tl->pin_count, 1, 0))
return 0;
- GEM_BUG_ON(!tl->pin_count);
- GEM_BUG_ON(tl->active_count);
err = i915_vma_pin(tl->hwsp_ggtt, 0, 0, PIN_GLOBAL | PIN_HIGH);
if (err)
- goto unpin;
+ return err;
tl->hwsp_offset =
i915_ggtt_offset(tl->hwsp_ggtt) +
offset_in_page(tl->hwsp_offset);
cacheline_acquire(tl->hwsp_cacheline);
+ if (atomic_fetch_inc(&tl->pin_count)) {
+ cacheline_release(tl->hwsp_cacheline);
+ __i915_vma_unpin(tl->hwsp_ggtt);
+ }
return 0;
-
-unpin:
- tl->pin_count = 0;
- return err;
}
void intel_timeline_enter(struct intel_timeline *tl)
{
struct intel_gt_timelines *timelines = &tl->gt->timelines;
- GEM_BUG_ON(!tl->pin_count);
+ GEM_BUG_ON(!atomic_read(&tl->pin_count));
if (tl->active_count++)
return;
GEM_BUG_ON(!tl->active_count); /* overflow? */
@@ -372,7 +370,7 @@ void intel_timeline_exit(struct intel_timeline *tl)
static u32 timeline_advance(struct intel_timeline *tl)
{
- GEM_BUG_ON(!tl->pin_count);
+ GEM_BUG_ON(!atomic_read(&tl->pin_count));
GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
return tl->seqno += 1 + tl->has_initial_breadcrumb;
@@ -523,11 +521,10 @@ int intel_timeline_read_hwsp(struct i915_request *from,
void intel_timeline_unpin(struct intel_timeline *tl)
{
- GEM_BUG_ON(!tl->pin_count);
- if (--tl->pin_count)
+ GEM_BUG_ON(!atomic_read(&tl->pin_count));
+ if (!atomic_dec_and_test(&tl->pin_count))
return;
- GEM_BUG_ON(tl->active_count);
cacheline_release(tl->hwsp_cacheline);
__i915_vma_unpin(tl->hwsp_ggtt);
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
index b820ee76b7f5..8dd14a2b8781 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
@@ -25,7 +25,7 @@ struct intel_timeline {
struct mutex mutex; /* protects the flow of requests */
- unsigned int pin_count;
+ atomic_t pin_count;
const u32 *hwsp_seqno;
struct i915_vma *hwsp_ggtt;
u32 hwsp_offset;
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index 490ebd121f4c..a48b36d31e65 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -38,13 +38,13 @@ struct mock_ring {
static void mock_timeline_pin(struct intel_timeline *tl)
{
- tl->pin_count++;
+ atomic_inc(&tl->pin_count);
}
static void mock_timeline_unpin(struct intel_timeline *tl)
{
- GEM_BUG_ON(!tl->pin_count);
- tl->pin_count--;
+ GEM_BUG_ON(!atomic_read(&tl->pin_count));
+ atomic_dec(&tl->pin_count);
}
static struct intel_ring *mock_ring(struct intel_engine_cs *engine)
--
2.20.1
___
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[Intel-gfx] [PATCH 2/8] drm/i915: Teach execbuffer to take the engine wakeref not GT
In the next patch, we would like to couple into the engine wakeref to
free the batch pool on idling. The caveat here is that we therefore want
to track the engine wakeref more precisely and to hold it instead of the
broader GT wakeref as we process the ioctl.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 36 ---
drivers/gpu/drm/i915/gt/intel_context.h | 7
2 files changed, 31 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 1c5dfbfad71b..f43eaaa5db5f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2143,13 +2143,35 @@ static int eb_pin_context(struct i915_execbuffer *eb,
struct intel_context *ce)
if (err)
return err;
+ /*
+* Take a local wakeref for preparing to dispatch the execbuf as
+* we expect to access the hardware fairly frequently in the
+* process. Upon first dispatch, we acquire another prolonged
+* wakeref that we hold until the GPU has been idle for at least
+* 100ms.
+*/
+ err = intel_context_timeline_lock(ce);
+ if (err)
+ goto err_unpin;
+
+ intel_context_enter(ce);
+ intel_context_timeline_unlock(ce);
+
eb->engine = ce->engine;
eb->context = ce;
return 0;
+
+err_unpin:
+ intel_context_unpin(ce);
+ return err;
}
static void eb_unpin_context(struct i915_execbuffer *eb)
{
+ __intel_context_timeline_lock(eb->context);
+ intel_context_exit(eb->context);
+ intel_context_timeline_unlock(eb->context);
+
intel_context_unpin(eb->context);
}
@@ -2430,18 +2452,9 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_destroy;
- /*
-* Take a local wakeref for preparing to dispatch the execbuf as
-* we expect to access the hardware fairly frequently in the
-* process. Upon first dispatch, we acquire another prolonged
-* wakeref that we hold until the GPU has been idle for at least
-* 100ms.
-*/
- intel_gt_pm_get(&eb.i915->gt);
-
err = i915_mutex_lock_interruptible(dev);
if (err)
- goto err_rpm;
+ goto err_context;
err = eb_select_engine(&eb, file, args);
if (unlikely(err))
@@ -2606,8 +2619,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
eb_unpin_context(&eb);
err_unlock:
mutex_unlock(&dev->struct_mutex);
-err_rpm:
- intel_gt_pm_put(&eb.i915->gt);
+err_context:
i915_gem_context_put(eb.gem_context);
err_destroy:
eb_destroy(&eb);
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 40cd8320fcc3..065ba4ac4e87 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -126,6 +126,13 @@ static inline void intel_context_put(struct intel_context
*ce)
kref_put(&ce->ref, ce->ops->destroy);
}
+static inline void
+__intel_context_timeline_lock(struct intel_context *ce)
+ __acquires(&ce->ring->timeline->mutex)
+{
+ mutex_lock(&ce->ring->timeline->mutex);
+}
+
static inline int __must_check
intel_context_timeline_lock(struct intel_context *ce)
__acquires(&ce->ring->timeline->mutex)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/8] drm/i915: Replace struct_mutex for batch pool serialisation
Switch to tracking activity via i915_active on individual nodes, only
keeping a list of retired objects in the cache, and reaping the cache
when the engine itself idles.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 58 +++---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 1 -
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 -
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 4 +-
drivers/gpu/drm/i915/gt/intel_engine.h| 1 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 +-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +
drivers/gpu/drm/i915/gt/intel_engine_pool.c | 166 ++
drivers/gpu/drm/i915/gt/intel_engine_pool.h | 34
.../gpu/drm/i915/gt/intel_engine_pool_types.h | 29 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 6 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 3 +
drivers/gpu/drm/i915/i915_debugfs.c | 68 ---
drivers/gpu/drm/i915/i915_gem_batch_pool.c| 132 --
drivers/gpu/drm/i915/i915_gem_batch_pool.h| 26 ---
16 files changed, 279 insertions(+), 265 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_pool.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_pool.h
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_pool_types.h
delete mode 100644 drivers/gpu/drm/i915/i915_gem_batch_pool.c
delete mode 100644 drivers/gpu/drm/i915/i915_gem_batch_pool.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5266dbeab01f..1ae546df284a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -72,6 +72,7 @@ obj-y += gt/
gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
+ gt/intel_engine_pool.o \
gt/intel_engine_cs.o \
gt/intel_engine_pm.o \
gt/intel_gt.o \
@@ -125,7 +126,6 @@ i915-y += \
$(gem-y) \
i915_active.o \
i915_cmd_parser.o \
- i915_gem_batch_pool.o \
i915_gem_evict.o \
i915_gem_fence_reg.o \
i915_gem_gtt.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 80c9c57a302f..0ea2d49bc8b9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -16,6 +16,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pool.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
@@ -1145,25 +1146,26 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
unsigned int len)
{
struct reloc_cache *cache = &eb->reloc_cache;
- struct drm_i915_gem_object *obj;
+ struct intel_engine_pool_node *pool;
struct i915_request *rq;
struct i915_vma *batch;
u32 *cmd;
int err;
- obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ pool = intel_engine_pool_get(&eb->engine->pool, PAGE_SIZE);
+ if (IS_ERR(pool))
+ return PTR_ERR(pool);
- cmd = i915_gem_object_pin_map(obj,
+ cmd = i915_gem_object_pin_map(pool->obj,
cache->has_llc ?
I915_MAP_FORCE_WB :
I915_MAP_FORCE_WC);
- i915_gem_object_unpin_pages(obj);
- if (IS_ERR(cmd))
- return PTR_ERR(cmd);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto out_pool;
+ }
- batch = i915_vma_instance(obj, vma->vm, NULL);
+ batch = i915_vma_instance(pool->obj, vma->vm, NULL);
if (IS_ERR(batch)) {
err = PTR_ERR(batch);
goto err_unmap;
@@ -1179,6 +1181,10 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
goto err_unpin;
}
+ err = intel_engine_pool_mark_active(pool, rq);
+ if (err)
+ goto err_request;
+
err = reloc_move_to_gpu(rq, vma);
if (err)
goto err_request;
@@ -1204,7 +1210,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
cache->rq_size = 0;
/* Return with batch mapping (cmd) still pinned */
- return 0;
+ goto out_pool;
skip_request:
i915_request_skip(rq, err);
@@ -1213,7 +1219,9 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
err_unpin:
i915_vma_unpin(batch);
err_unmap:
- i915_gem_object_unpin_map(obj);
+ i915_gem_object_unpin_map(pool->obj);
+out_pool:
+ intel_engine_pool_put(pool);
return err;
}
@@ -1957,18 +1965,17 @@ static int i915_reset_gen7_sol_offsets(struct
i915_request *rq)
static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master)
[Intel-gfx] [PATCH 6/8] drm/i915: Protect request retirement with timeline->mutex
Forgo the struct_mutex requirement for request retirement as we have
been transitioning over to only using the timeline->mutex for
controlling the lifetime of a request on that timeline.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 192 ++
drivers/gpu/drm/i915/gt/intel_context.h | 25 +--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 -
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 -
drivers/gpu/drm/i915/gt/intel_gt.c| 1 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 -
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 13 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 1 -
drivers/gpu/drm/i915/i915_request.c | 151 +++---
drivers/gpu/drm/i915/i915_request.h | 3 -
11 files changed, 203 insertions(+), 189 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index f43eaaa5db5f..80c9c57a302f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -739,63 +739,6 @@ static int eb_select_context(struct i915_execbuffer *eb)
return 0;
}
-static struct i915_request *__eb_wait_for_ring(struct intel_ring *ring)
-{
- struct i915_request *rq;
-
- /*
-* Completely unscientific finger-in-the-air estimates for suitable
-* maximum user request size (to avoid blocking) and then backoff.
-*/
- if (intel_ring_update_space(ring) >= PAGE_SIZE)
- return NULL;
-
- /*
-* Find a request that after waiting upon, there will be at least half
-* the ring available. The hysteresis allows us to compete for the
-* shared ring and should mean that we sleep less often prior to
-* claiming our resources, but not so long that the ring completely
-* drains before we can submit our next request.
-*/
- list_for_each_entry(rq, &ring->request_list, ring_link) {
- if (__intel_ring_space(rq->postfix,
- ring->emit, ring->size) > ring->size / 2)
- break;
- }
- if (&rq->ring_link == &ring->request_list)
- return NULL; /* weird, we will check again later for real */
-
- return i915_request_get(rq);
-}
-
-static int eb_wait_for_ring(const struct i915_execbuffer *eb)
-{
- struct i915_request *rq;
- int ret = 0;
-
- /*
-* Apply a light amount of backpressure to prevent excessive hogs
-* from blocking waiting for space whilst holding struct_mutex and
-* keeping all of their resources pinned.
-*/
-
- rq = __eb_wait_for_ring(eb->context->ring);
- if (rq) {
- mutex_unlock(&eb->i915->drm.struct_mutex);
-
- if (i915_request_wait(rq,
- I915_WAIT_INTERRUPTIBLE,
- MAX_SCHEDULE_TIMEOUT) < 0)
- ret = -EINTR;
-
- i915_request_put(rq);
-
- mutex_lock(&eb->i915->drm.struct_mutex);
- }
-
- return ret;
-}
-
static int eb_lookup_vmas(struct i915_execbuffer *eb)
{
struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma;
@@ -2122,10 +2065,75 @@ static const enum intel_engine_id user_ring_map[] = {
[I915_EXEC_VEBOX] = VECS0
};
-static int eb_pin_context(struct i915_execbuffer *eb, struct intel_context *ce)
+static struct i915_request *eb_throttle(struct intel_context *ce)
+{
+ struct intel_ring *ring = ce->ring;
+ struct intel_timeline *tl = ring->timeline;
+ struct i915_request *rq;
+
+ /*
+* Completely unscientific finger-in-the-air estimates for suitable
+* maximum user request size (to avoid blocking) and then backoff.
+*/
+ if (intel_ring_update_space(ring) >= PAGE_SIZE)
+ return NULL;
+
+ /*
+* Find a request that after waiting upon, there will be at least half
+* the ring available. The hysteresis allows us to compete for the
+* shared ring and should mean that we sleep less often prior to
+* claiming our resources, but not so long that the ring completely
+* drains before we can submit our next request.
+*/
+ list_for_each_entry(rq, &tl->requests, link) {
+ if (rq->ring != ring)
+ continue;
+
+ if (__intel_ring_space(rq->postfix,
+ ring->emit, ring->size) > ring->size / 2)
+ break;
+ }
+ if (&rq->link == &tl->requests)
+ return NULL; /* weird, we will check again later for real */
+
+ return i915_request_get(rq);
+}
+
+static int
+__eb_pin_context(struct i915_execbuffer *eb, struct intel_context *ce)
{
[Intel-gfx] [PATCH 1/8] drm/i915: Order assert forcewake test
Read the current value before computing the expected to ensure that if
the timer does complete early (against our will), it should not cause a
false positive.
v2: The local irq disable did not prevent the timer from running.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_uncore.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2042c94c9cc9..bb9e0da30e94 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -758,19 +758,18 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
* Check that the caller has an explicit wakeref and we don't mistake
* it for the auto wakeref.
*/
- local_irq_disable();
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
+ unsigned int actual = READ_ONCE(domain->wake_count);
unsigned int expect = 1;
if (hrtimer_active(&domain->timer) && READ_ONCE(domain->active))
expect++; /* pending automatic release */
- if (WARN(domain->wake_count < expect,
+ if (WARN(actual < expect,
"Expected domain %d to be held awake by caller,
count=%d\n",
-domain->id, domain->wake_count))
+domain->id, actual))
break;
}
- local_irq_enable();
}
/* We give fast paths for the really cool registers */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 3/6] drm: uevent for connector status change
DRM API for generating uevent for a status changes of connector's
property.
This uevent will have following details related to the status change:
HOTPLUG=1, CONNECTOR= and PROPERTY=
Need ACK from this uevent from userspace consumer.
v2:
Minor fixes at KDoc comments [Daniel]
v3:
Check the property is really attached with connector [Daniel]
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_sysfs.c | 35 +++
include/drm/drm_sysfs.h | 5 -
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index ad10810bc972..d13a77057045 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -26,6 +26,7 @@
#include
#include "drm_internal.h"
+#include "drm_crtc_internal.h"
#define to_drm_minor(d) dev_get_drvdata(d)
#define to_drm_connector(d) dev_get_drvdata(d)
@@ -325,6 +326,9 @@ void drm_sysfs_lease_event(struct drm_device *dev)
* Send a uevent for the DRM device specified by @dev. Currently we only
* set HOTPLUG=1 in the uevent environment, but this could be expanded to
* deal with other types of events.
+ *
+ * Any new uapi should be using the drm_sysfs_connector_status_event()
+ * for uevents on connector status change.
*/
void drm_sysfs_hotplug_event(struct drm_device *dev)
{
@@ -337,6 +341,37 @@ void drm_sysfs_hotplug_event(struct drm_device *dev)
}
EXPORT_SYMBOL(drm_sysfs_hotplug_event);
+/**
+ * drm_sysfs_connector_status_event - generate a DRM uevent for connector
+ * property status change
+ * @connector: connector on which property status changed
+ * @property: connector property whoes status changed.
+ *
+ * Send a uevent for the DRM device specified by @dev. Currently we
+ * set HOTPLUG=1 and connector id along with the attached property id
+ * related to the status change.
+ */
+void drm_sysfs_connector_status_event(struct drm_connector *connector,
+ struct drm_property *property)
+{
+ struct drm_device *dev = connector->dev;
+ char hotplug_str[] = "HOTPLUG=1", conn_id[30], prop_id[30];
+ char *envp[4] = { hotplug_str, conn_id, prop_id, NULL };
+
+ WARN_ON(!drm_mode_obj_find_prop_id(&connector->base,
+ property->base.id));
+
+ snprintf(conn_id, ARRAY_SIZE(conn_id),
+"CONNECTOR=%u", connector->base.id);
+ snprintf(prop_id, ARRAY_SIZE(prop_id),
+"PROPERTY=%u", property->base.id);
+
+ DRM_DEBUG("generating connector status event\n");
+
+ kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp);
+}
+EXPORT_SYMBOL(drm_sysfs_connector_status_event);
+
static void drm_sysfs_release(struct device *dev)
{
kfree(dev);
diff --git a/include/drm/drm_sysfs.h b/include/drm/drm_sysfs.h
index 4f311e836cdc..d454ef617b2c 100644
--- a/include/drm/drm_sysfs.h
+++ b/include/drm/drm_sysfs.h
@@ -4,10 +4,13 @@
struct drm_device;
struct device;
+struct drm_connector;
+struct drm_property;
int drm_class_device_register(struct device *dev);
void drm_class_device_unregister(struct device *dev);
void drm_sysfs_hotplug_event(struct drm_device *dev);
-
+void drm_sysfs_connector_status_event(struct drm_connector *connector,
+ struct drm_property *property);
#endif
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 5/6] drm/i915: update the hdcp state with uevent
drm function to update the content protection property state and to
generate a uevent is invoked from the intel hdcp property work.
Hence whenever kernel changes the property state, userspace will be
updated with a uevent.
Need a ACK for uevent generating uAPI from userspace.
v2:
state update is moved into drm function [daniel]
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 4580af57bddb..e56969ebdd25 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -865,7 +865,6 @@ static void intel_hdcp_prop_work(struct work_struct *work)
prop_work);
struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
struct drm_device *dev = connector->base.dev;
- struct drm_connector_state *state;
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
mutex_lock(&hdcp->mutex);
@@ -875,10 +874,9 @@ static void intel_hdcp_prop_work(struct work_struct *work)
* those to UNDESIRED is handled by core. If value == UNDESIRED,
* we're running just after hdcp has been disabled, so just exit
*/
- if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
- state = connector->base.state;
- state->content_protection = hdcp->value;
- }
+ if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
+ drm_hdcp_update_content_protection(&connector->base,
+ hdcp->value);
mutex_unlock(&hdcp->mutex);
drm_modeset_unlock(&dev->mode_config.connection_mutex);
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 6/6] drm/hdcp: reference for srm file format
In the kernel documentation, HDCP specifications links are shared as a reference for SRM table format. Signed-off-by: Ramalingam C --- drivers/gpu/drm/drm_hdcp.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c index 77433ee3d652..803bf8283b83 100644 --- a/drivers/gpu/drm/drm_hdcp.c +++ b/drivers/gpu/drm/drm_hdcp.c @@ -271,6 +271,13 @@ static void drm_hdcp_request_srm(struct drm_device *drm_dev) * * SRM should be presented in the name of "display_hdcp_srm.bin". * + * Format of the SRM table that userspace needs to write into the binary file + * is defined at + * 1. Renewability chapter on 55th page of HDCP 1.4 specification + * https://www.digital-cp.com/sites/default/files/specifications/HDCP%20Specification%20Rev1_4_Secure.pdf + * 2. Renewability chapter on 63rd page of HDCP 2.2 specification + * https://www.digital-cp.com/sites/default/files/specifications/HDCP%20on%20HDMI%20Specification%20Rev2_2_Final1.pdf + * * Returns: * TRUE on any of the KSV is revoked, else FALSE. */ -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 2/6] drm/i915: Attach content type property
Attaches the content type property for HDCP2.2 capable connectors.
Implements the update of content type from property and apply the
restriction on HDCP version selection.
Need ACK for content type property from userspace consumer.
v2:
s/cp_content_type/content_protection_type [daniel]
disable at hdcp_atomic_check to avoid check at atomic_set_property
[Maarten]
v3:
s/content_protection_type/hdcp_content_type [Pekka]
v4:
hdcp disable incase of type change is moved into commit [daniel].
v5:
Simplified the Type change procedure. [Daniel]
v6:
Type change with UNDESIRED state is ignored.
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/display/intel_ddi.c | 39
drivers/gpu/drm/i915/display/intel_hdcp.c | 43 +++
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
3 files changed, 62 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4172595c8d8..862907393a6d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3514,7 +3514,8 @@ static void intel_enable_ddi(struct intel_encoder
*encoder,
/* Enable hdcp if it's desired */
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
+ intel_hdcp_enable(to_intel_connector(conn_state->connector),
+ (u8)conn_state->hdcp_content_type);
}
static void intel_disable_ddi_dp(struct intel_encoder *encoder,
@@ -3583,15 +3584,41 @@ static void intel_ddi_update_pipe(struct intel_encoder
*encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ bool content_protection_type_changed =
+ (conn_state->hdcp_content_type != hdcp->content_type &&
+conn_state->content_protection !=
+DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
+
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
+ /*
+* During the HDCP encryption session if Type change is requested,
+* disable the HDCP and reenable it with new TYPE value.
+*/
if (conn_state->content_protection ==
- DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
- else if (conn_state->content_protection ==
-DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
- intel_hdcp_disable(to_intel_connector(conn_state->connector));
+ DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
+ content_protection_type_changed)
+ intel_hdcp_disable(connector);
+
+ /*
+* Mark the hdcp state as DESIRED after the hdcp disable of type
+* change procedure.
+*/
+ if (content_protection_type_changed) {
+ mutex_lock(&hdcp->mutex);
+ hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ schedule_work(&hdcp->prop_work);
+ mutex_unlock(&hdcp->mutex);
+ }
+
+ if (conn_state->content_protection ==
+ DRM_MODE_CONTENT_PROTECTION_DESIRED ||
+ content_protection_type_changed)
+ intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
}
static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 2a4d10952b74..4580af57bddb 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1748,14 +1748,15 @@ static const struct component_ops
i915_hdcp_component_ops = {
.unbind = i915_hdcp_component_unbind,
};
-static inline int initialize_hdcp_port_data(struct intel_connector *connector)
+static inline int initialize_hdcp_port_data(struct intel_connector *connector,
+ const struct intel_hdcp_shim *shim)
{
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
data->port = connector->encoder->port;
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
- data->protocol = (u8)hdcp->shim->protocol;
+ data->protocol = (u8)shim->protocol;
data->k = 1;
if (!data->streams)
@@ -1805,12 +1806,13 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector)
+static vo
[Intel-gfx] [PATCH v8 1/6] drm: Add Content protection type property
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on any HDCP protected display wires.
But Type 1 content can be rendered only on HDCP2.2 protected paths.
So when a userspace sets this property to Type 1 and starts the HDCP
enable, kernel will honour it only if HDCP2.2 authentication is through
for type 1. Else HDCP enable will be failed.
Need ACK for this new conenctor property from userspace consumer.
v2:
cp_content_type is replaced with content_protection_type [daniel]
check at atomic_set_property is removed [Maarten]
v3:
%s/content_protection_type/hdcp_content_type [Pekka]
v4:
property is created for the first requested connector and then reused.
[Danvet]
v5:
kernel doc nits addressed [Daniel]
Rebased as part of patch reordering.
v6:
Kernel docs are modified [pekka]
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 +++
drivers/gpu/drm/drm_connector.c | 22 ++
drivers/gpu/drm/drm_hdcp.c| 36 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++-
include/drm/drm_connector.h | 7 +
include/drm/drm_hdcp.h| 2 +-
include/drm/drm_mode_config.h | 6
include/uapi/drm/drm_mode.h | 4 +++
8 files changed, 82 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index abe38bdf85ae..19ae119f1a5d 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -747,6 +747,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
return -EINVAL;
}
state->content_protection = val;
+ } else if (property == config->hdcp_content_type_property) {
+ state->hdcp_content_type = val;
} else if (property == connector->colorspace_property) {
state->colorspace = val;
} else if (property == config->writeback_fb_id_property) {
@@ -831,6 +833,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
state->hdr_output_metadata->base.id : 0;
} else if (property == config->content_protection_property) {
*val = state->content_protection;
+ } else if (property == config->hdcp_content_type_property) {
+ *val = state->hdcp_content_type;
} else if (property == config->writeback_fb_id_property) {
/* Writeback framebuffer is one-shot, write and forget */
*val = 0;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 068d4b05f1be..17aef88c03a6 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -951,6 +951,28 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
* the value transitions from ENABLED to DESIRED. This signifies the link
* is no longer protected and userspace should take appropriate action
* (whatever that might be).
+ * HDCP Content Type:
+ * This property is used by the userspace to configure the kernel with
+ * to be displayed stream's content type. Content Type of a stream is
+ * decided by the owner of the stream, as "HDCP Type0" or "HDCP Type1".
+ *
+ * The value of the property can be one the below:
+ * - "HDCP Type0": DRM_MODE_HDCP_CONTENT_TYPE0 = 0
+ * HDCP Type0 streams can be transmitted on a link which is
+ * encrypted with HDCP 1.4 or higher versions of HDCP(i.e HDCP2.2
+ * and more).
+ * - "HDCP Type1": DRM_MODE_HDCP_CONTENT_TYPE1 = 1
+ * HDCP Type1 streams can be transmitted on a link which is
+ * encrypted only with HDCP 2.2. In future higher versions also
+ * might support Type1 based on their spec.
+ *
+ * Note that the HDCP Content Type property is introduced at HDCP 2.2, and
+ * defaults to type 0. It is only exposed by drivers supporting HDCP 2.2.
+ * Based on how next versions of HDCP specs are defined content Type could
+ * be used for higher versions too.
+ * If content type is changed when content_protection is not UNDESIRED,
+ * then kernel will disable the HDCP and re-enable with new type in the
+ * same atomic commit
*
* HDR_OUTPUT_METADATA:
* Connector property to enable userspace to send HDR Metadata to
diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
index cd837bd409f7..ce235fd1c844 100644
--- a/drivers/gpu/drm/drm_hdcp.c
+++ b/drivers/gpu/drm/drm_hdcp.c
@@ -344,23 +344,41 @@ static struct drm_prop_enum_list drm_cp_enum_list[] = {
};
DRM_ENUM_NAME_FN(drm_get_content_prote
[Intel-gfx] [PATCH v8 4/6] drm/hdcp: update content protection property with uevent
drm function is defined and exported to update a connector's
content protection property state and to generate a uevent along
with it.
Need ACK for the uevent from userspace consumer.
v2:
Update only when state is different from old one.
v3:
KDoc is added [Daniel]
v4:
KDoc is extended bit more [pekka]
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_hdcp.c | 34 ++
include/drm/drm_hdcp.h | 2 ++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
index ce235fd1c844..77433ee3d652 100644
--- a/drivers/gpu/drm/drm_hdcp.c
+++ b/drivers/gpu/drm/drm_hdcp.c
@@ -374,6 +374,10 @@ DRM_ENUM_NAME_FN(drm_get_hdcp_content_type_name,
*
* The content protection will be set to
&drm_connector_state.content_protection
*
+ * When kernel triggered content protection state change like DESIRED->ENABLED
+ * and ENABLED->DESIRED, will use drm_hdcp_update_content_protection() to
update
+ * the content protection state of a connector.
+ *
* Returns:
* Zero on success, negative errno on failure.
*/
@@ -414,3 +418,33 @@ int drm_connector_attach_content_protection_property(
return 0;
}
EXPORT_SYMBOL(drm_connector_attach_content_protection_property);
+
+/**
+ * drm_hdcp_update_content_protection - Updates the content protection state
+ * of a connector
+ *
+ * @connector: drm_connector on which content protection state needs an update
+ * @val: New state of the content protection property
+ *
+ * This function can be used by display drivers, to update the kernel triggered
+ * content protection state changes of a drm_connector such as DESIRED->ENABLED
+ * and ENABLED->DESIRED. No uevent for DESIRED->UNDESIRED or
ENABLED->UNDESIRED,
+ * as userspace is triggering such state change and kernel performs it without
+ * fail.This function update the new state of the property into the connector's
+ * state and generate an uevent to notify the userspace.
+ */
+void drm_hdcp_update_content_protection(struct drm_connector *connector,
+ u64 val)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_connector_state *state = connector->state;
+
+ WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+ if (state->content_protection == val)
+ return;
+
+ state->content_protection = val;
+ drm_sysfs_connector_status_event(connector,
+dev->mode_config.content_protection_property);
+}
+EXPORT_SYMBOL(drm_hdcp_update_content_protection);
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 2970abdfaf12..dd864ac9ce85 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -292,4 +292,6 @@ bool drm_hdcp_check_ksvs_revoked(struct drm_device *dev,
u8 *ksvs, u32 ksv_count);
int drm_connector_attach_content_protection_property(
struct drm_connector *connector, bool hdcp_content_type);
+void drm_hdcp_update_content_protection(struct drm_connector *connector,
+ u64 val);
#endif
--
2.19.1
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[Intel-gfx] [PATCH v8 0/6] HDCP2.2 Phase II
Rebased the remaining 5 patches from the original series. https://patchwork.freedesktop.org/series/57232/ And as per pekka's review comments few additions are done in the kernel documentation. Test-with: <20190703095446.14092-2-ramalinga...@intel.com> Ramalingam C (6): drm: Add Content protection type property drm/i915: Attach content type property drm: uevent for connector status change drm/hdcp: update content protection property with uevent drm/i915: update the hdcp state with uevent drm/hdcp: reference for srm file format drivers/gpu/drm/drm_atomic_uapi.c | 4 ++ drivers/gpu/drm/drm_connector.c | 22 +++ drivers/gpu/drm/drm_hdcp.c| 77 ++- drivers/gpu/drm/drm_sysfs.c | 35 +++ drivers/gpu/drm/i915/display/intel_ddi.c | 39 ++-- drivers/gpu/drm/i915/display/intel_hdcp.c | 53 ++-- drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- include/drm/drm_connector.h | 7 +++ include/drm/drm_hdcp.h| 4 +- include/drm/drm_mode_config.h | 6 ++ include/drm/drm_sysfs.h | 5 +- include/uapi/drm/drm_mode.h | 4 ++ 12 files changed, 228 insertions(+), 30 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Order assert forcewake test
Read the current value before computing the expected to ensure that if
the timer does complete early (against our will), it should not cause a
false positive.
v2: The local irq disable did not prevent the timer from running.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_uncore.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2042c94c9cc9..bb9e0da30e94 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -758,19 +758,18 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
* Check that the caller has an explicit wakeref and we don't mistake
* it for the auto wakeref.
*/
- local_irq_disable();
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
+ unsigned int actual = READ_ONCE(domain->wake_count);
unsigned int expect = 1;
if (hrtimer_active(&domain->timer) && READ_ONCE(domain->active))
expect++; /* pending automatic release */
- if (WARN(domain->wake_count < expect,
+ if (WARN(actual < expect,
"Expected domain %d to be held awake by caller,
count=%d\n",
-domain->id, domain->wake_count))
+domain->id, actual))
break;
}
- local_irq_enable();
}
/* We give fast paths for the really cool registers */
--
2.20.1
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