Re: [Intel-gfx] [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
On 2019-07-09 at 09:39:24 +0530, Sharma, Shashank wrote:
> Hello Ram,
>
> On 7/2/2019 11:24 AM, Ramalingam C wrote:
>
> > From Gen12 onwards, HDCP HW block is implemented within transcoders.
> > Till Gen11 HDCP HW block was part of DDI.
> >
> > Hence required changes in HW programming is handled here.
> >
> > v2:
> >_MMIO_TRANS is used [Lucas and Daniel]
> >platform check is moved into the caller [Lucas]
> > v3:
> >platform check is moved into a macro [Shashank]
> >
> > Signed-off-by: Ramalingam C
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 155 ++
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +-
> > drivers/gpu/drm/i915/i915_reg.h | 120 +++--
> > drivers/gpu/drm/i915/intel_drv.h | 8 ++
> > 4 files changed, 221 insertions(+), 71 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index bc3a94d491c4..14ba723a3561 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -17,6 +17,7 @@
> > #include "intel_drv.h"
> > #include "intel_hdcp.h"
> > #include "intel_sideband.h"
> > +#include "intel_connector.h"
> > #define KEY_LOAD_TRIES5
> > #define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
> > @@ -104,23 +105,21 @@ bool intel_hdcp2_capable(struct intel_connector
> > *connector)
> > return capable;
> > }
> > -static inline bool intel_hdcp_in_use(struct intel_connector *connector)
> > +static inline bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
> > +enum pipe pipe, enum port port)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > - enum port port = connector->encoder->port;
> > u32 reg;
> > - reg = I915_READ(PORT_HDCP_STATUS(port));
> > + reg = I915_READ(HDCP_STATUS(dev_priv, pipe, port));
> > return reg & HDCP_STATUS_ENC;
> directly return I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
> HDCP_STATUS_ENC; ?
Sure.
> > }
> > -static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
> > +static inline bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
> > + enum pipe pipe, enum port port)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > - enum port port = connector->encoder->port;
> > u32 reg;
> > - reg = I915_READ(HDCP2_STATUS_DDI(port));
> > + reg = I915_READ(HDCP2_STATUS(dev_priv, pipe, port));
> > return reg & LINK_ENCRYPTION_STATUS;
> same here
> > }
> > @@ -253,37 +252,59 @@ static int intel_write_sha_text(struct
> > drm_i915_private *dev_priv, u32 sha_text)
> > }
> > static
> > -u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
> > +u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
> > + enum pipe pipe, enum port port)
> > {
> > - enum port port = intel_dig_port->base.port;
> > - switch (port) {
> > - case PORT_A:
> > - return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
> > - case PORT_B:
> > - return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
> > - case PORT_C:
> > - return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
> > - case PORT_D:
> > - return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
> > - case PORT_E:
> > - return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
> > - default:
> > - break;
> > - }
> > - DRM_ERROR("Unknown port %d\n", port);
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > + switch (pipe) {
> > + case PIPE_A:
> > + return HDCP_TRANSA_REP_PRESENT |
> > + HDCP_TRANSA_SHA1_M0;
> > + case PIPE_B:
> > + return HDCP_TRANSB_REP_PRESENT |
> > + HDCP_TRANSB_SHA1_M0;
> > + case PIPE_C:
> > + return HDCP_TRANSC_REP_PRESENT |
> > + HDCP_TRANSC_SHA1_M0;
> > + /* FIXME: Add a case for PIPE_D */
> > + default:
> > + DRM_ERROR("Unknown pipe %d\n", pipe);
> > + break;
> > + }
>
> return -EINVAL here, then we don't need the else condition
>
> may be something like:
>
> ret = -EINVAL
>
> if (GEN >=12) {
>
> switch(pipe) {
>
> case PIPEA: ret = ; break;
>
> case PIPE_B: ret =; break;
>
> default: DRM_ERROR(); break;
>
> }
>
> return ret;
>
> }
>
> switch (port) {
>
> case PORT_A: ret = ;
>
> case PORT_B: ret =;
>
> default: DRM_ERROR();
>
> }
>
> return ret;
Was not thinking to remove the else part. perhaps will look better
without else.
>
> > + } else {
> > + switch (port) {
> > + case PORT_A:
> > + return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
> > + cas
[Intel-gfx] [PATCH] drm/i915: Fix reporting of size of created GEM object
Commit e163484afa8d ("drm/i915: Update size upon return from
GEM_CREATE") (re)introduced reporting of actual size of created GEM
objects, possibly rounded up on object alignment. Unfortunately, its
implementation resulted in a possible use-after-free bug. The bug has
been fixed by commit 929eec99f5fd ("drm/i915: Avoid use-after-free in
reporting create.size") at the cost of possibly incorrect value being
reported as actual object size.
Safely restore correct reporting by capturing actual size of created
GEM object before a reference to the object is put.
Fixes: 929eec99f5fd ("drm/i915: Avoid use-after-free in reporting create.size")
Signed-off-by: Janusz Krzysztofik
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7ade42b8ec99..16bae5870d6f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -171,6 +171,7 @@ i915_gem_create(struct drm_file *file,
obj = i915_gem_object_create_shmem(dev_priv, size);
if (IS_ERR(obj))
return PTR_ERR(obj);
+ size = obj->base.size;
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
--
2.21.0
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Re: [Intel-gfx] [PATCH v6 03/11] drm/i915/perf: allow for CS OA configs to be created lazily
On 01/07/2019 18:09, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-01 12:34:29)
struct i915_oa_config {
+ struct drm_i915_private *i915;
+
char uuid[UUID_STRING_LEN + 1];
int id;
@@ -1110,6 +1112,10 @@ struct i915_oa_config {
struct attribute *attrs[2];
struct device_attribute sysfs_metric_id;
+ struct drm_i915_gem_object *obj;
+
+ struct list_head vma_link;
+
atomic_t ref_count;
};
-static void free_oa_config(struct drm_i915_private *dev_priv,
- struct i915_oa_config *oa_config)
+static void put_oa_config(struct i915_oa_config *oa_config)
{
+ if (!atomic_dec_and_test(&oa_config->ref_count))
+ return;
I strongly advise that ref_count be replaced by struct kref, just so that
we get the benefit of debugging.
put_oa_config -> kref_put(&oa_config->ref, free_oa_config)
(free_oa_config takes kref as its arg and uses container_of())
This is done in "drm/i915: add a new perf configuration execbuf parameter"
I'll factor it in this commit.
+int i915_perf_get_oa_config(struct drm_i915_private *i915,
+ int metrics_set,
+ struct i915_oa_config **out_config,
+ struct drm_i915_gem_object **out_obj)
+{
+ int ret = 0;
+ struct i915_oa_config *oa_config;
+
+ if (!i915->perf.initialized)
+ return -ENODEV;
+
+ ret = mutex_lock_interruptible(&i915->perf.metrics_lock);
if (ret)
return ret;
- *out_config = idr_find(&dev_priv->perf.metrics_idr, metrics_set);
- if (!*out_config)
- ret = -EINVAL;
- else
- atomic_inc(&(*out_config)->ref_count);
+ if (metrics_set == 1) {
+ oa_config = &i915->perf.oa.test_config;
+ } else {
+ oa_config = idr_find(&i915->perf.metrics_idr, metrics_set);
Why not have the builtin[1] inside the idr?
I think it was just a way to avoid removing it from the idr through
userspace calls.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Fill in a little more of the dummy fence
On 08/07/2019 12:30, Chris Wilson wrote: Initialise the dma_fence innards in preparation for making dma_fence_signal() always check the callback list. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 11f490502ca6..672bdaa66540 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -859,6 +859,10 @@ static struct i915_request *dummy_request(struct intel_engine_cs *engine) i915_sw_fence_init(&rq->submit, dummy_notify); set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); + spin_lock_init(&rq->lock); + rq->fence.lock = &rq->lock; + INIT_LIST_HEAD(&rq->fence.cb_list); + return rq; } Reviewed-by: Tvrtko Ursulin Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Remove presumption of RCS0
On 05/07/2019 13:43, Chris Wilson wrote:
We now track features correctly instead of probing i915->engine[RCS0]
which is much more flexible and avoids any nasty surprises.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index df5932f5f578..bdf279fa3b2e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -448,12 +448,6 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
if (WARN_ON(mask != engine_mask))
device_info->engine_mask = mask;
- /* We always presume we have at least RCS available for later probing */
- if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
- err = -ENODEV;
- goto cleanup;
- }
-
RUNTIME_INFO(i915)->num_engines = hweight32(mask);
intel_gt_check_and_clear_faults(&i915->gt);
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Set igt_spinner.gt for early exit
On 08/07/2019 22:55, Chris Wilson wrote:
Set up a default gt pointer for an early cleanup of igt_spinnter, before
a request is created and igt_spinner.gt set to the active engine's.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/selftests/igt_spinner.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c
b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 0c1f65262a63..89b6552a6497 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -19,6 +19,7 @@ int igt_spinner_init(struct igt_spinner *spin, struct
drm_i915_private *i915)
memset(spin, 0, sizeof(*spin));
spin->i915 = i915;
+ spin->gt = &i915->gt;
spin->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(spin->hws)) {
I thought I audited all call paths but this is certainly safer. Could
drop the conditional something which check gt now.. hm it's not there..
I thought I put "if (spin->gt) igt_gt_chipset_flush(spin->gt);" on the
end path. Strange..
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH] drm/i915/userptr: Acquire the page lock around set_page_dirty()
On 08/07/2019 15:03, Chris Wilson wrote:
set_page_dirty says:
For pages with a mapping this should be done under the page lock
for the benefit of asynchronous memory errors who prefer a
consistent dirty state. This rule can be broken in some special
cases, but should be better not to.
If the mapping doesn't provide a set_page_dirty a_op, then
just fall through and assume that it wants buffer_heads.
Under those rules, it only safe for us to use the plain set_page_dirty()
calls for shmemfs/anonymous memory. Userptr may be used with real
mappings and so needs to use the locked version (set_page_dirty_lock).
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203317
Fixes: 5cc9ed4b9a7a ("drm/i915: Introduce mapping of user pages into video memory
(userptr) ioctl")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 16ccec7fb7da..32d208ede343 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -665,7 +665,15 @@ i915_gem_userptr_put_pages(struct drm_i915_gem_object *obj,
for_each_sgt_page(page, sgt_iter, pages) {
if (obj->mm.dirty)
- set_page_dirty(page);
+ /*
+* As this may not be anonymous memory (e.g. shmem)
+* but exist on a real mapping, we have to lock
+* the page in order to dirty it -- holding
+* the page reference is not sufficient to
+* prevent the inode from being truncated.
+* Play safe and take the lock.
+*/
+ set_page_dirty_lock(page);
mark_page_accessed(page);
put_page(page);
Not an expert but sounds plausible.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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[Intel-gfx] ✓ Fi.CI.IGT: success for Modular FIA (rev2)
== Series Details == Series: Modular FIA (rev2) URL : https://patchwork.freedesktop.org/series/63175/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13569_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13569_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl5/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_mmap_gtt@forked-medium-copy-odd: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl4/igt@gem_mmap_...@forked-medium-copy-odd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-apl6/igt@gem_mmap_...@forked-medium-copy-odd.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl4/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-skl6/igt@gem_soft...@noreloc-s3.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#108569]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb8/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-iclb5/igt@i915_selftest@live_hangcheck.html * igt@kms_draw_crc@draw-method-rgb565-render-xtiled: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#103184] / [fdo#103232]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl2/igt@kms_draw_...@draw-method-rgb565-render-xtiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-skl7/igt@kms_draw_...@draw-method-rgb565-render-xtiled.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-glk4/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-glk9/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend: - shard-snb: [PASS][13] -> [INCOMPLETE][14] ([fdo#105411]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-snb1/igt@kms_f...@flip-vs-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-snb1/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@basic: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb6/igt@kms_frontbuffer_track...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-iclb5/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#103191]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl5/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-skl4/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-kbl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [fdo#110403]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Try to fix encoder possible_clones/crtc
== Series Details == Series: drm: Try to fix encoder possible_clones/crtc URL : https://patchwork.freedesktop.org/series/63399/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13568_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13568_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +6 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl1/igt@i915_susp...@sysfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-apl3/igt@i915_susp...@sysfs-reader.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl5/igt@kms_big...@yf-tiled-32bpp-rotate-0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-apl8/igt@kms_big...@yf-tiled-32bpp-rotate-0.html * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size: - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([fdo#103540]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-hsw6/igt@kms_cursor_leg...@cursorb-vs-flipb-varying-size.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-hsw7/igt@kms_cursor_leg...@cursorb-vs-flipb-varying-size.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb2/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-iclb1/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-iclb4/igt@kms_psr@psr2_sprite_render.html * igt@sw_sync@sync_expired_merge: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb8/igt@sw_sync@sync_expired_merge.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-iclb7/igt@sw_sync@sync_expired_merge.html * igt@tools_test@tools_test: - shard-hsw: [PASS][17] -> [SKIP][18] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-hsw2/igt@tools_test@tools_test.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-hsw8/igt@tools_test@tools_test.html Possible fixes * igt@gem_eio@unwedge-stress: - shard-snb: [FAIL][19] ([fdo#109661]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-snb5/igt@gem_...@unwedge-stress.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-snb1/igt@gem_...@unwedge-stress.html * igt@i915_pm_rpm@i2c: - shard-hsw: [FAIL][21] ([fdo#104097]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-hsw2/igt@i915_pm_...@i2c.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-hsw8/igt@i915_pm_...@i2c.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [FAIL][23] ([fdo#105363]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/shard-skl1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend: - shard-apl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl1/igt@kms_f...@flip-vs-suspend.html [26]: https:/
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Enable HDCP 1.4 and 2.2 on Gen12+
Hello Ram,
On 7/2/2019 11:24 AM, Ramalingam C wrote:
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
v2:
_MMIO_TRANS is used [Lucas and Daniel]
platform check is moved into the caller [Lucas]
v3:
platform check is moved into a macro [Shashank]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 155 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +-
drivers/gpu/drm/i915/i915_reg.h | 120 +++--
drivers/gpu/drm/i915/intel_drv.h | 8 ++
4 files changed, 221 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index bc3a94d491c4..14ba723a3561 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -17,6 +17,7 @@
#include "intel_drv.h"
#include "intel_hdcp.h"
#include "intel_sideband.h"
+#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
@@ -104,23 +105,21 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
return capable;
}
-static inline bool intel_hdcp_in_use(struct intel_connector *connector)
+static inline bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
+enum pipe pipe, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
u32 reg;
- reg = I915_READ(PORT_HDCP_STATUS(port));
+ reg = I915_READ(HDCP_STATUS(dev_priv, pipe, port));
return reg & HDCP_STATUS_ENC;
directly return I915_READ(HDCP_STATUS(dev_priv, pipe, port)) &
HDCP_STATUS_ENC; ?
}
-static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
+static inline bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum port port)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- enum port port = connector->encoder->port;
u32 reg;
- reg = I915_READ(HDCP2_STATUS_DDI(port));
+ reg = I915_READ(HDCP2_STATUS(dev_priv, pipe, port));
return reg & LINK_ENCRYPTION_STATUS;
same here
}
@@ -253,37 +252,59 @@ static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
}
static
-u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
+u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum port port)
{
- enum port port = intel_dig_port->base.port;
- switch (port) {
- case PORT_A:
- return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
- case PORT_B:
- return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
- case PORT_C:
- return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
- case PORT_D:
- return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
- case PORT_E:
- return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
- default:
- break;
- }
- DRM_ERROR("Unknown port %d\n", port);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ switch (pipe) {
+ case PIPE_A:
+ return HDCP_TRANSA_REP_PRESENT |
+ HDCP_TRANSA_SHA1_M0;
+ case PIPE_B:
+ return HDCP_TRANSB_REP_PRESENT |
+ HDCP_TRANSB_SHA1_M0;
+ case PIPE_C:
+ return HDCP_TRANSC_REP_PRESENT |
+ HDCP_TRANSC_SHA1_M0;
+ /* FIXME: Add a case for PIPE_D */
+ default:
+ DRM_ERROR("Unknown pipe %d\n", pipe);
+ break;
+ }
return -EINVAL here, then we don't need the else condition
may be something like:
ret = -EINVAL
if (GEN >=12) {
switch(pipe) {
case PIPEA: ret = ; break;
case PIPE_B: ret =; break;
default: DRM_ERROR(); break;
}
return ret;
}
switch (port) {
case PORT_A: ret = ;
case PORT_B: ret =;
default: DRM_ERROR();
}
return ret;
+ } else {
+ switch (port) {
+ case PORT_A:
+ return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
+ case PORT_B:
+ return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
+ case PORT_C:
+ return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
+ case PORT_D:
+ return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
+ case PORT_E:
+ return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Reorder error cleanup for whitelist checking (rev2)
== Series Details == Series: drm/i915/selftests: Reorder error cleanup for whitelist checking (rev2) URL : https://patchwork.freedesktop.org/series/63394/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13567_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13567_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +6 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl5/igt@gem_workarou...@suspend-resume-context.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-apl1/igt@gem_workarou...@suspend-resume-context.html * igt@kms_draw_crc@draw-method-rgb565-render-xtiled: - shard-skl: [PASS][3] -> [FAIL][4] ([fdo#103184] / [fdo#103232]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl2/igt@kms_draw_...@draw-method-rgb565-render-xtiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-skl7/igt@kms_draw_...@draw-method-rgb565-render-xtiled.html * igt@kms_flip@flip-vs-blocking-wf-vblank: - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#100368]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl4/igt@kms_f...@flip-vs-blocking-wf-vblank.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-skl4/igt@kms_f...@flip-vs-blocking-wf-vblank.html * igt@kms_flip@modeset-vs-vblank-race: - shard-glk: [PASS][7] -> [FAIL][8] ([fdo#103060]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-glk9/igt@kms_f...@modeset-vs-vblank-race.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-glk9/igt@kms_f...@modeset-vs-vblank-race.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-move.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-move.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103191]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl5/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-skl5/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-kbl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-iclb3/igt@kms_psr@psr2_sprite_render.html * igt@kms_setmode@basic: - shard-kbl: [PASS][21] -> [FAIL][22] ([fdo#99912]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl3/igt@kms_setm...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/shard-kbl6/igt@kms_setm...@basic.html * igt@prime_busy@wait-hang-blt: - shard-iclb: [PASS][23] -> [INCOMPLETE][24] ([fdo#107713]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb2/igt@prime_b...@wait-hang-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Explicitly track active fw_domain timers (rev3)
== Series Details == Series: drm/i915: Explicitly track active fw_domain timers (rev3) URL : https://patchwork.freedesktop.org/series/63331/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13566_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13566_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-kbl1/igt@gem_ctx_isolat...@rcs0-s3.html * igt@kms_draw_crc@draw-method-rgb565-render-xtiled: - shard-skl: [PASS][3] -> [FAIL][4] ([fdo#103184] / [fdo#103232]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl2/igt@kms_draw_...@draw-method-rgb565-render-xtiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-skl1/igt@kms_draw_...@draw-method-rgb565-render-xtiled.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#103167]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-spr-indfb-draw-render.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-spr-indfb-draw-render.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#103191]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl5/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-skl1/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-skl1/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103166]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-y.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-iclb1/igt@kms_psr@psr2_sprite_render.html * igt@kms_setmode@basic: - shard-apl: [PASS][15] -> [FAIL][16] ([fdo#99912]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl4/igt@kms_setm...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-apl4/igt@kms_setm...@basic.html - shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl3/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-kbl7/igt@kms_setm...@basic.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-apl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible fixes * igt@gem_eio@unwedge-stress: - shard-snb: [FAIL][21] ([fdo#109661]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-snb5/igt@gem_...@unwedge-stress.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-snb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][23] ([fdo#110854]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb5/igt@gem_exec_balan...@smoke.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/shard-iclb4/igt@gem_exec_balan...@smoke.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [FAIL][25] ([fdo#105363]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/t
Re: [Intel-gfx] [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A.
>
> v2 (Lucas):
> - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
> - Use crtc->dev since new_crtc_state->state may be NULL on atomic
> commit (suggested by Maarten)
As we are reusing would be nice also rename it to something like:
POWER_DOMAIN_TRANSCODER_VDSC_PW2
POWER_DOMAIN_LOW_POWER_TRANSCODER_VDSC /
POWER_DOMAIN_LP_TRANSCODER_VDSC
>
> Cc: Imre Deak
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ffec807b8960..c27912f552f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -459,16 +459,19 @@ int intel_dp_compute_dsc_params(struct intel_dp
> *intel_dp,
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc-
> >dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> - * On ICL VDSC/joining for eDP transcoder uses a separate power
> well PW2
> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate
> power well
> + * PW2. This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power
> domain.
>* For any other transcoder, VDSC/joining uses the power well
> associated
>* with the pipe/transcoder in use. Hence another reference on
> the
>* transcoder power domain will suffice.
>*/
> - if (cpu_transcoder == TRANSCODER_EDP)
> + if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
> + return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> + else if (cpu_transcoder == TRANSCODER_EDP)
> return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> else
> return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks
On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote:
> Transition the remaining uses of intel_port_is_* over to the
> equivalent
> intel_phy_is_* functions and drop the port functions.
Awesome
Reviewed-by: José Roberto de Souza
>
> Cc: José Roberto de Souza
> Signed-off-by: Matt Roper
> ---
> We might want to hold off on merging this one until after TGL lands
> to
> avoid unnecessary conflicts there.
>
> drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 49 -
> --
> drivers/gpu/drm/i915/display/intel_display.c | 38 --
> .../drm/i915/display/intel_display_power.c| 4 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 15 +++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +++--
> drivers/gpu/drm/i915/intel_drv.h | 2 -
> 7 files changed, 61 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 0c9808132d67..4fdbb5c35d87 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -28,6 +28,7 @@
> #include
> #include
>
> +#include "display/intel_display.h"
> #include "display/intel_gmbus.h"
>
> #include "i915_drv.h"
> @@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct
> drm_i915_private *dev_priv)
> for (port = PORT_A; port < I915_MAX_PORTS; port++) {
> struct ddi_vbt_port_info *info =
> &dev_priv->vbt.ddi_port_info[port];
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> /*
>* VBT has the TypeC mode (native,TBT/USB) and we don't
> want
>* to detect it.
>*/
> - if (intel_port_is_tc(dev_priv, port))
> + if (intel_phy_is_tc(dev_priv, phy))
> continue;
>
> info->supports_dvi = (port != PORT_A && port !=
> PORT_E);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 50dd9d731456..37c8cecb9a6a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -868,11 +868,12 @@ icl_get_combo_buf_trans(struct drm_i915_private
> *dev_priv, int type, int rate,
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv,
> enum port port)
> {
> int n_entries, level, default_entry;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(dev_priv,
> INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> @@ -1487,9 +1488,10 @@ static void icl_ddi_clock_get(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dpll_hw_state *pll_state = &pipe_config-
> >dpll_hw_state;
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int link_clock;
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
> } else {
> enum intel_dpll_id pll_id =
> intel_get_shared_dpll_id(dev_priv,
> @@ -2086,6 +2088,7 @@ static void intel_ddi_get_power_domains(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> /*
>* TODO: Add support for MST encoders. Atm, the following
> should never
> @@ -2103,7 +2106,7 @@ static void intel_ddi_get_power_domains(struct
> intel_encoder *encoder,
>* ports.
>*/
> if (intel_crtc_has_dp_encoder(crtc_state) ||
> - intel_port_is_tc(dev_priv, encoder->port))
> + intel_phy_is_tc(dev_priv, phy))
> intel_display_power_get(dev_priv,
> intel_ddi_main_link_aux_domain(
> dig_port));
>
> @@ -2228,10 +2231,11 @@ u8 intel_ddi_dp_voltage_max(struct
> intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int n_entries;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(dev_priv, encoder-
> >type,
>
Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: simplify guc client
On Tue, Jul 02, 2019 at 01:09:46PM -0700, Daniele Ceraolo Spurio wrote:
We originally added support, in some cases partial, for different modes
of operations via guc clients:
- proxy vs direct submission;
- variable engine mask per-client.
We only ever used one flow (all submissions via a single proxy), so the
other code paths haven't been exercised and are most likely
non-functional. The guc firmware interface is also in the process of
being updated to better fit the i915 flow and our client abstraction
will need to change accordingly (or possibly go away entirely), so these
old unused paths can be considered dead and removed.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 73 ++---
drivers/gpu/drm/i915/intel_guc_submission.h | 2 -
drivers/gpu/drm/i915/selftests/intel_guc.c | 12 +---
4 files changed, 8 insertions(+), 82 deletions(-)
The client abstraction is likely going away in when the firmware interface is
reworked so this patch shouldn't interface with any of those changes.
Acked-by: Matthew Brost
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 02eaa15d47c0..65ddb24a0f4b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2028,7 +2028,6 @@ static int i915_guc_stage_pool(struct seq_file *m, void
*data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const struct intel_guc *guc = &dev_priv->guc;
struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
- struct intel_guc_client *client = guc->execbuf_client;
intel_engine_mask_t tmp;
int index;
@@ -2058,7 +2057,7 @@ static int i915_guc_stage_pool(struct seq_file *m, void
*data)
desc->wq_addr, desc->wq_size);
seq_putc(m, '\n');
- for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
+ for_each_engine(engine, dev_priv, tmp) {
u32 guc_engine_id = engine->guc_id;
struct guc_execlist_context *lrc =
&desc->lrc[guc_engine_id];
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 8520bb224175..30692f8289bd 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -363,10 +363,7 @@ static void guc_stage_desc_pool_destroy(struct intel_guc
*guc)
static void guc_stage_desc_init(struct intel_guc_client *client)
{
struct intel_guc *guc = client->guc;
- struct i915_gem_context *ctx = client->owner;
- struct i915_gem_engines_iter it;
struct guc_stage_desc *desc;
- struct intel_context *ce;
u32 gfx_addr;
desc = __get_stage_desc(client);
@@ -380,55 +377,6 @@ static void guc_stage_desc_init(struct intel_guc_client
*client)
desc->priority = client->priority;
desc->db_id = client->doorbell_id;
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- struct guc_execlist_context *lrc;
-
- if (!(ce->engine->mask & client->engines))
- continue;
-
- /* TODO: We have a design issue to be solved here. Only when we
-* receive the first batch, we know which engine is used by the
-* user. But here GuC expects the lrc and ring to be pinned. It
-* is not an issue for default context, which is the only one
-* for now who owns a GuC client. But for future owner of GuC
-* client, need to make sure lrc is pinned prior to enter here.
-*/
- if (!ce->state)
- break; /* XXX: continue? */
-
- /*
-* XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
-* submission or, in other words, not using a direct submission
-* model) the KMD's LRCA is not used for any work submission.
-* Instead, the GuC uses the LRCA of the user mode context (see
-* guc_add_request below).
-*/
- lrc = &desc->lrc[ce->engine->guc_id];
- lrc->context_desc = lower_32_bits(ce->lrc_desc);
-
- /* The state page is after PPHWSP */
- lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
-LRC_STATE_PN * PAGE_SIZE;
-
- /* XXX: In direct submission, the GuC wants the HW context id
-* here. In proxy submission, it wants the stage id
-*/
- lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
- (ce->engine->guc_id << GUC_ELC
Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Remove preemption support for current fw
On Tue, Jul 02, 2019 at 01:09:45PM -0700, Daniele Ceraolo Spurio wrote:
From: Chris Wilson
Preemption via GuC submission is not being supported with its current
legacy incarnation. The current FW does support a similar pre-emption
flow via H2G, but it is class-based instead of being instance-based,
which doesn't fit well with the i915 tracking. To fix this, the
firmware is being updated to better support our needs with a new flow,
so we can safely remove the old code.
v2 (Daniele): resurrect & rebase, reword commit message, remove
preempt_context as well
Signed-off-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 --
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 13 --
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 5 -
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/intel_guc.c | 31 ---
drivers/gpu/drm/i915/intel_guc.h | 9 -
drivers/gpu/drm/i915/intel_guc_submission.c | 220 +--
drivers/gpu/drm/i915/selftests/intel_guc.c | 31 +--
10 files changed, 14 insertions(+), 319 deletions(-)
Nothing in this patch conflicts with the updates to the firmware/driver I'm
working on to better support our needs.
Acked-by: Matthew Brost
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 8a9787cf0cd0..9c695910bc43 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -644,18 +644,12 @@ static void init_contexts(struct drm_i915_private *i915)
init_llist_head(&i915->contexts.free_list);
}
-static bool needs_preempt_context(struct drm_i915_private *i915)
-{
- return USES_GUC_SUBMISSION(i915);
-}
-
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
- GEM_BUG_ON(dev_priv->preempt_context);
intel_engine_init_ctx_wa(dev_priv->engine[RCS0]);
init_contexts(dev_priv);
@@ -677,15 +671,6 @@ int i915_gem_contexts_init(struct drm_i915_private
*dev_priv)
GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count));
dev_priv->kernel_context = ctx;
- /* highest priority; preempting task */
- if (needs_preempt_context(dev_priv)) {
- ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
- if (!IS_ERR(ctx))
- dev_priv->preempt_context = ctx;
- else
- DRM_ERROR("Failed to create preempt context; disabling
preemption\n");
- }
-
DRM_DEBUG_DRIVER("%s context support initialized\n",
DRIVER_CAPS(dev_priv)->has_logical_contexts ?
"logical" : "fake");
@@ -696,8 +681,6 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
{
lockdep_assert_held(&i915->drm.struct_mutex);
- if (i915->preempt_context)
- destroy_kernel_context(&i915->preempt_context);
destroy_kernel_context(&i915->kernel_context);
/* Must free all deferred contexts (via flush_workqueue) first */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d1508f0b4c84..55b11409c1f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -842,15 +842,6 @@ int intel_engine_init_common(struct intel_engine_cs
*engine)
if (ret)
return ret;
- /*
-* Similarly the preempt context must always be available so that
-* we can interrupt the engine at any time. However, as preemption
-* is optional, we allow it to fail.
-*/
- if (i915->preempt_context)
- pin_context(i915->preempt_context, engine,
- &engine->preempt_context);
-
ret = measure_breadcrumb_dw(engine);
if (ret < 0)
goto err_unpin;
@@ -862,8 +853,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
return 0;
err_unpin:
- if (engine->preempt_context)
- intel_context_unpin(engine->preempt_context);
intel_context_unpin(engine->kernel_context);
return ret;
}
@@ -888,8 +877,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
if (engine->default_state)
i915_gem_object_put(engine->default_state);
- if (engine->preempt_context)
- intel_context_unpin(engine->preempt_context);
intel_context_unpin(engine->kernel_context);
GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/driver
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915: Clear the shared PLL from the put_dplls() hook
== Series Details == Series: series starting with [v2,1/2] drm/i915: Clear the shared PLL from the put_dplls() hook URL : https://patchwork.freedesktop.org/series/63384/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13564_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13564_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13564_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13564_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live_mman: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb8/igt@i915_selftest@live_mman.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-iclb5/igt@i915_selftest@live_mman.html Known issues Here are the changes found in Patchwork_13564_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@fifo-blt: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl3/igt@gem_exec_sched...@fifo-blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-apl6/igt@gem_exec_sched...@fifo-blt.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: [PASS][5] -> [SKIP][6] ([fdo#109271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl1/igt@kms_cursor_...@pipe-c-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-apl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_frontbuffer_tracking@basic: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb6/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-iclb8/igt@kms_frontbuffer_track...@basic.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl1/igt@kms_frontbuffer_track...@fbc-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-kbl1/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#103191]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl5/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-skl1/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-skl10/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-skl4/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [22]: http
Re: [Intel-gfx] [PATCH] drm/i915/userptr: Acquire the page lock around set_page_dirty()
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: 5cc9ed4b9a7a drm/i915: Introduce mapping of user pages into
video memory (userptr) ioctl.
The bot has tested the following trees: v5.1.16, v4.19.57, v4.14.132, v4.9.184,
v4.4.184.
v5.1.16: Build OK!
v4.19.57: Build OK!
v4.14.132: Build OK!
v4.9.184: Failed to apply! Possible dependencies:
0e70447605f4 ("drm/i915: Move common code out of i915_gpu_error.c")
1b36595ffb35 ("drm/i915: Show RING registers through debugfs")
275f039db56f ("drm/i915: Move user fault tracking to a separate list")
3594a3e21f1f ("drm/i915: Remove superfluous locking around userfault_list")
3b3f1650b1ca ("drm/i915: Allocate intel_engine_cs structure only for the
enabled engines")
7c108fd8feac ("drm/i915: Move fence cancellation to runtime suspend")
8baa1f04b9ed ("drm/i915: Update debugfs describe_obj() to show
fault-mappable")
96d776345277 ("drm/i915: Use a radixtree for random access to the object's
backing storage")
9c870d03674f ("drm/i915: Use RPM as the barrier for controlling user mmap
access")
a4f5ea64f0a8 ("drm/i915: Refactor object page API")
d636951ec01b ("drm/i915: Cleanup instdone collection")
f8a7fde45610 ("drm/i915: Defer active reference until required")
v4.4.184: Failed to apply! Possible dependencies:
09cbfeaf1a5a ("mm, fs: get rid of PAGE_CACHE_* and page_cache_{get,release}
macros")
0a798eb92e6d ("drm/i915: Refactor duplicate object vmap functions")
0b5372727be3 ("drm/i915/cmdparser: Use cached vmappings")
0e749e54244e ("dax: increase granularity of dax_clear_blocks() operations")
0eb973d31d0a ("drm/i915: Cache ringbuffer GTT VMA")
43394c7d0d36 ("drm/i915: Extract i915_gem_obj_prepare_shmem_write()")
4420cfd3f51c ("staging: lustre: format properly all comment blocks for LNet
core")
52db400fcd50 ("pmem, dax: clean up clear_pmem()")
5fd88337d209 ("staging: lustre: fix all conditional comparison to zero in
LNet layer")
85d1225ec066 ("drm/i915: Introduce & use new lightweight SGL iterators")
a188222b6ed2 ("net: Rename NETIF_F_ALL_CSUM to NETIF_F_CSUM_MASK")
a4f5ea64f0a8 ("drm/i915: Refactor object page API")
b2e0d1625e19 ("dax: fix lifetime of in-kernel dax mappings with
dax_map_atomic()")
b9bcd14a2b91 ("drm/i915: Extract checking for backing struct pages to a
helper")
d1a5f2b4d8a1 ("block: use DAX for partition table reads")
def0c5f6b0cd ("drm/i915: Map the ringbuffer using WB on LLC machines")
e10624f8c097 ("pmem: fail io-requests to known bad blocks")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks,
Sasha
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
On Mon, 2019-07-08 at 23:59 +, Souza, Jose wrote:
> On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote:
> > Our past DDI-based Intel platforms have had a fixed DDI<->PHY
> > mapping.
> > Because of this, both the bspec documentation and our i915 code has
> > used
> > the term "port" when talking about either DDI's or PHY's; it was
> > always
> > easy to tell what terms like "Port A" were referring to from the
> > context.
> >
> > Unfortunately this is starting to break down now that EHL allows
> > PHY-
> > A
> > to be driven by either DDI-A or DDI-D. Is a setup with DDI-D
> > driving
> > PHY-A considered "Port A" or "Port D?" The answer depends on which
> > register we're working with, and even the bspec doesn't do a great
> > job
> > of clarifying this.
> >
> > Let's try to be more explicit about whether we're talking about the
> > DDI
> > or the PHY on gen11+ by using 'port' to refer to the DDI and
> > creating
> > a
> > new 'enum phy' namespace to refer to the PHY in use.
> >
> > This patch just adds the new PHY namespace, new phy-based versions
> > of
> > intel_port_is_*(), and a helper to convert a port to a PHY.
> > Transitioning various areas of the code over to using the PHY
> > namespace
> > will be done in subsequent patches to make review easier. We'll
> > remove
> > the intel_port_is_*() functions at the end of the series when we
> > transition all callers over to using the PHY-based versions.
> >
> > v2:
> > - Convert a few more 'port' uses to 'phy.' (Sparse)
> >
> > v3:
> > - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> > - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use
> > PHY
> >for its bit definitions, even though the register description is
> >given in terms of DDI.
> > - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to
> > using
> >port and create separate ICL+ definitions that work in terms of
> > PHY.
> >
> > v4:
> > - Rebase and resolve conflicts with Imre's TC series.
> > - This patch now just adds the namespace and a few convenience
> >functions; the important changes are now split out into separate
> >patches to make review easier.
> >
> > Suggested-by: Ville Syrjala
> > Cc: José Roberto de Souza
> > Cc: Lucas De Marchi
> > Cc: Ville Syrjälä
> > Cc: Imre Deak
> > Cc: Jani Nikula
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 32
> > +++-
> > drivers/gpu/drm/i915/display/intel_display.h | 16 ++
> > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > 3 files changed, 49 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 919f5ac844c8..4a85abef93e7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct
> > drm_i915_private *dev_priv, enum port port)
> > return false;
> > }
>
> A call to intel_port_is_combophy(PORT_D) would return false on EHL,
> it
> and intel_port_is_tc() should use intel_phy functions, like:
>
> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
> port port)
> {
> return intel_phy_is_combo(dev_priv, intel_port_to_phy(dev_priv,
> port));
> }
>
> Even better would be check if we can replace those with intel_phy
> counterparts.
You did that on patch 4, so I guess you can disconsider this comments.
>
> >
> > +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum
> > phy
> > phy)
> > +{
> > + if (phy == PHY_NONE)
> > + return false;
> > +
> > + if (IS_ELKHARTLAKE(dev_priv))
> > + return phy <= PHY_C;
> > +
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + return phy <= PHY_B;
> > +
> > + return false;
> > +}
> > +
> > bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> > port)
> > {
> > if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> > @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct
> > drm_i915_private
> > *dev_priv, enum port port)
> > return false;
> > }
> >
> > +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> > phy)
> > +{
> > + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> > + return phy >= PHY_C && phy <= PHY_F;
> > +
> > + return false;
> > +}
> > +
> > +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum
> > port
> > port)
> > +{
> > + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> > + return PHY_A;
> > +
> > + return (enum phy)port;
> > +}
> > +
> > enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> > enum port port)
> > {
> > - if (!intel_port_is_tc(dev_priv, port))
> > + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> > port)))
> > return PORT_TC_NONE;
> >
> > return port - PORT_C;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dis
Re: [Intel-gfx] [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote:
> Convert the code that operates directly on gen11 combo PHY's to use
> the
> new namespace. Combo PHY registers are those named "ICL_PORT_*" plus
> ICL_DPHY_CHKN.
>
> Note that a lot of the PHY programming happens in the MIPI DSI code.
> For clarity I've added a for_each_dsi_phy() to loop over the phys
> used
> by DSI. Since DSI always uses A & B on gen11, port=phy in all cases
> so
> it doesn't actually matter which form we use in the DSI code. I've
> used
> the phy iterator in code that's explicitly working with the combo
> PHY,
> but left the rest of the DSI code using the port iterator and
> namespace
> to minimize patch deltas. We can switch the rest of the DSI code
> over
> to use phy terminology later if this winds up being too confusing.
>
> Cc: José Roberto de Souza
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c| 127
> .../gpu/drm/i915/display/intel_combo_phy.c| 143 +---
> --
> .../gpu/drm/i915/display/intel_combo_phy.h| 3 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 45 +++---
> drivers/gpu/drm/i915/display/intel_display.h | 4 +
> .../drm/i915/display/intel_display_power.c| 16 +-
> drivers/gpu/drm/i915/display/intel_dsi.h | 12 +-
> drivers/gpu/drm/i915/i915_reg.h | 74 -
> 8 files changed, 213 insertions(+), 211 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index f574af62888c..575196f892c2 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -202,63 +202,62 @@ static void
> dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - enum port port;
> + enum phy phy;
> u32 tmp;
> int lane;
>
> - for_each_dsi_port(port, intel_dsi->ports) {
> -
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> /*
>* Program voltage swing and pre-emphasis level values
> as per
>* table in BSPEC under DDI buffer programing
>*/
> - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
> tmp |= SCALING_MODE_SEL(0x2);
> tmp |= TAP2_DISABLE | TAP3_DISABLE;
> tmp |= RTERM_SELECT(0x6);
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
>
> - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
> tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
> tmp |= SCALING_MODE_SEL(0x2);
> tmp |= TAP2_DISABLE | TAP3_DISABLE;
> tmp |= RTERM_SELECT(0x6);
> - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
>
> - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
> tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>RCOMP_SCALAR_MASK);
> tmp |= SWING_SEL_UPPER(0x2);
> tmp |= SWING_SEL_LOWER(0x2);
> tmp |= RCOMP_SCALAR(0x98);
> - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
>
> - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
> tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>RCOMP_SCALAR_MASK);
> tmp |= SWING_SEL_UPPER(0x2);
> tmp |= SWING_SEL_LOWER(0x2);
> tmp |= RCOMP_SCALAR(0x98);
> - I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
>
> - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
> tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
>CURSOR_COEFF_MASK);
> tmp |= POST_CURSOR_1(0x0);
> tmp |= POST_CURSOR_2(0x0);
> tmp |= CURSOR_COEFF(0x3f);
> - I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
>
> for (lane = 0; lane <= 3; lane++) {
> /* Bspec: must not use GRP register for write
> */
> - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane,
> port));
> + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
> tmp &= ~(POST_CURSOR_1_MASK |
>
Re: [Intel-gfx] [PATCH v5 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
On Wed, 2019-07-03 at 18:06 -0700, Matt Roper wrote:
> Although the register name implies that it operates on DDI's,
> DPCLKA_CFGCR0_ICL actually needs to be programmed according to the
> PHY
> that's in use. I.e., when using EHL's DDI-D on combo PHY A, the bits
> described as "port A" in the bspec are what we need to set. The
> bspec
> clarifies:
>
> "[For EHL] DDID clock tied to DDIA clock, so DPCLKA_CFGCR0
> DDIA
> Clock Select chooses the PLL for both DDIA and DDID and
> drives
> port A in all cases."
>
> Also, since the CNL DPCLKA_CFGCR0 bit defines are still port-based,
> we
> create separate ICL-specific defines that accept the PHY rather than
> trying to share the same bit definitions between CNL and ICL.
>
Nit: Why not already rename DPCLKA_CFGCR0_ICL to ICL_DPCLKA_CFGCR0? The
bits have the new name, so you are already touching in everyplace that
uses DPCLKA_CFGCR0_ICL.
> v5: Make icl_dpclka_cfgcr0_clk_off() take phy rather than port. When
> splitting the original patch the hunk to handle this wound up too
> late in the series. (Sparse)
Reviewed-by: José Roberto de Souza
>
> Bspec: 33148
> Cc: José Roberto de Souza
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 17 ++---
> drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++---
> --
> drivers/gpu/drm/i915/i915_reg.h | 12 --
> 3 files changed, 50 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b8673debf932..f574af62888c 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -560,11 +560,13 @@ static void gen11_dsi_gate_clocks(struct
> intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> enum port port;
> + enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -577,11 +579,13 @@ static void gen11_dsi_ungate_clocks(struct
> intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> enum port port;
> + enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -595,19 +599,22 @@ static void gen11_dsi_map_pll(struct
> intel_encoder *encoder,
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> enum port port;
> + enum phy phy;
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> + phy = intel_port_to_phy(dev_priv, port);
> + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id,
> phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a4172595c8d8..065feb917db4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2729,12 +2729,13 @@ u32 ddi_signal_levels(struct intel_dp
> *intel_dp)
>
> static inline
> u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> - if (intel_port_is_combophy(dev_priv, port)) {
> - return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> - } else if (intel_port_is_tc(dev_priv, port)) {
> - enum tc_port tc_port = intel_port_to_tc(dev_priv,
> port);
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> + enum tc_port tc_port = intel_port_to_tc(dev_priv,
> +
Re: [Intel-gfx] [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote:
> Our past DDI-based Intel platforms have had a fixed DDI<->PHY
> mapping.
> Because of this, both the bspec documentation and our i915 code has
> used
> the term "port" when talking about either DDI's or PHY's; it was
> always
> easy to tell what terms like "Port A" were referring to from the
> context.
>
> Unfortunately this is starting to break down now that EHL allows PHY-
> A
> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
> PHY-A considered "Port A" or "Port D?" The answer depends on which
> register we're working with, and even the bspec doesn't do a great
> job
> of clarifying this.
>
> Let's try to be more explicit about whether we're talking about the
> DDI
> or the PHY on gen11+ by using 'port' to refer to the DDI and creating
> a
> new 'enum phy' namespace to refer to the PHY in use.
>
> This patch just adds the new PHY namespace, new phy-based versions of
> intel_port_is_*(), and a helper to convert a port to a PHY.
> Transitioning various areas of the code over to using the PHY
> namespace
> will be done in subsequent patches to make review easier. We'll
> remove
> the intel_port_is_*() functions at the end of the series when we
> transition all callers over to using the PHY-based versions.
>
> v2:
> - Convert a few more 'port' uses to 'phy.' (Sparse)
>
> v3:
> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use
> PHY
>for its bit definitions, even though the register description is
>given in terms of DDI.
> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to
> using
>port and create separate ICL+ definitions that work in terms of
> PHY.
>
> v4:
> - Rebase and resolve conflicts with Imre's TC series.
> - This patch now just adds the namespace and a few convenience
>functions; the important changes are now split out into separate
>patches to make review easier.
>
> Suggested-by: Ville Syrjala
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Jani Nikula
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 32
> +++-
> drivers/gpu/drm/i915/display/intel_display.h | 16 ++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 919f5ac844c8..4a85abef93e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct
> drm_i915_private *dev_priv, enum port port)
> return false;
> }
A call to intel_port_is_combophy(PORT_D) would return false on EHL, it
and intel_port_is_tc() should use intel_phy functions, like:
bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
port port)
{
return intel_phy_is_combo(dev_priv, intel_port_to_phy(dev_priv,
port));
}
Even better would be check if we can replace those with intel_phy
counterparts.
>
> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> phy)
> +{
> + if (phy == PHY_NONE)
> + return false;
> +
> + if (IS_ELKHARTLAKE(dev_priv))
> + return phy <= PHY_C;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + return phy <= PHY_B;
> +
> + return false;
> +}
> +
> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port)
> {
> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private
> *dev_priv, enum port port)
> return false;
> }
>
> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> phy)
> +{
> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> + return phy >= PHY_C && phy <= PHY_F;
> +
> + return false;
> +}
> +
> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port
> port)
> +{
> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> + return PHY_A;
> +
> + return (enum phy)port;
> +}
> +
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - if (!intel_port_is_tc(dev_priv, port))
> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> port)))
> return PORT_TC_NONE;
>
> return port - PORT_C;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index d296556ed82e..d53285fb883f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -228,6 +228,21 @@ struct intel_link_m_n {
> u32 link_n;
> };
>
> +enum phy {
> + PHY_NONE = -1,
> +
> + PHY_A = 0,
> + PHY_B,
> + PHY_C,
> + PHY_D,
> + PHY_E,
>
Re: [Intel-gfx] linux-next: manual merge of the drm-intel tree with the pci tree
Hi all,
On Mon, 24 Jun 2019 13:53:52 +1000 Stephen Rothwell
wrote:
>
> On Mon, 17 Jun 2019 13:20:27 +1000 Stephen Rothwell
> wrote:
> >
> > Today's linux-next merge of the drm-intel tree got a conflict in:
> >
> > drivers/gpu/drm/i915/i915_drv.h
> >
> > between commit:
> >
> > 151f4e2bdc7a ("docs: power: convert docs to ReST and rename to *.rst")
> >
> > from the pci tree and commit:
> >
> > 1bf676cc2dba ("drm/i915: move and rename i915_runtime_pm")
> >
> > from the drm-intel tree.
> >
> > I fixed it up (I just removed the struct definition from this files as
> > the latter did - its comment will need to be fixed up in its new file)
> > and can carry the fix as necessary. This is now fixed as far as linux-next
> > is concerned, but any non trivial conflicts should be mentioned to your
> > upstream maintainer when your tree is submitted for merging. You may
> > also want to consider cooperating with the maintainer of the conflicting
> > tree to minimise any particularly complex conflicts.
>
> This is now a conflict between the drm and pci trees.
I am still getting this conflict (the commit ids may have changed).
Just a reminder in case you think Linus may need to know.
--
Cheers,
Stephen Rothwell
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[Intel-gfx] ✓ Fi.CI.BAT: success for Initial support for Tiger Lake (rev2)
== Series Details == Series: Initial support for Tiger Lake (rev2) URL : https://patchwork.freedesktop.org/series/62726/ State : success == Summary == CI Bug Log - changes from CI_DRM_6433 -> Patchwork_13574 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/ Known issues Here are the changes found in Patchwork_13574 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-small-bo-tiledx: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 Participating hosts (53 -> 47) -- Additional (1): fi-icl-guc Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper Build changes - * Linux: CI_DRM_6433 -> Patchwork_13574 CI_DRM_6433: 6da10e343bc0d479ab208c4c291bab18ee11d1ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13574: 0482935d29fee26860b43eab8e6c6efcb40632b5 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 0482935d29fe drm/i915/tgl: Update DPLL clock reference register 47bbfafa8cfc drm/i915/tgl: Add DPLL registers 281046dee43c drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization ce6203f8c68e drm/i915/gen12: MBUS B credit change 2a4b9d250782 drm/i915/tgl: apply Display WA #1178 to fix type C dongles 6c6c34e25091 drm/i915/tgl: Add vbt value mapping for DDC Bus pin dc4c3dc34108 drm/i915/tgl: init ddi port A-C for Tiger Lake 8ccbd571ebbe drm/i915/tgl: extend intel_port_is_combophy/tc 515bc804c4ae drm/i915/tgl: select correct bit for port select 02eb68e95124 drm/i915/tgl: port to ddc pin mapping 480ad7f760d3 drm/i915/tgl: Add gmbus gpio pin to port mapping 9c0c1f90cc5b drm/i915/tgl: update ddi/tc clock_off bits 0c85ba787405 drm/i915/tgl: Add additional ports for Tiger Lake 6f0b3408f127 drm/i915/tgl: Add pll manager d93d40c8620e drm/i915/tgl: Add new pll ids ce8d3b70dd79 drm/i915/tgl: Add power well to support 4th pipe 48e70eb0a8fd drm/i915/tgl: Add power well support c66cb70352e9 drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A 2e99be826cae drm/i915/tgl: Check if pipe D is fused ff15c4352fcc x86/gpu: add TGL stolen memory support 2357168b2a25 drm/i915/tgl: Add TGL PCI IDs 5bae69ddf724 drm/i915/tgl: Add TGL PCH detection in virtualized environment f090ff212c09 drm/i915/tgl: Introduce Tiger Lake PCH 1957212e1a06 drm/i915/tgl: add initial Tiger Lake definitions 00d88902cdbe drm/i915: Add 4th pipe and transcoder == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/userptr: Acquire the page lock around set_page_dirty()
== Series Details == Series: drm/i915/userptr: Acquire the page lock around set_page_dirty() URL : https://patchwork.freedesktop.org/series/63383/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13563_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13563_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-apl1/igt@i915_susp...@sysfs-reader.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-apl4/igt@i915_susp...@sysfs-reader.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][3] -> [FAIL][4] ([fdo#105363]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-glk9/igt@kms_f...@flip-vs-expired-vblank.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-glk5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#103167]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl1/igt@kms_frontbuffer_track...@fbc-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-kbl6/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#103191]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl5/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-skl10/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-b-frame-sequence.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-skl10/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_setmode@basic: - shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-kbl3/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-kbl7/igt@kms_setm...@basic.html * igt@perf@polling: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl4/igt@p...@polling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-skl3/igt@p...@polling.html Possible fixes * igt@gem_eio@unwedge-stress: - shard-snb: [FAIL][21] ([fdo#109661]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-snb5/igt@gem_...@unwedge-stress.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-snb7/igt@gem_...@unwedge-stress.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [FAIL][23] ([fdo#105363]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13563/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@km
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev2)
== Series Details == Series: Initial support for Tiger Lake (rev2) URL : https://patchwork.freedesktop.org/series/62726/ State : warning == Summary == $ dim checkpatch origin/drm-tip 00d88902cdbe drm/i915: Add 4th pipe and transcoder 1957212e1a06 drm/i915/tgl: add initial Tiger Lake definitions f090ff212c09 drm/i915/tgl: Introduce Tiger Lake PCH 5bae69ddf724 drm/i915/tgl: Add TGL PCH detection in virtualized environment 2357168b2a25 drm/i915/tgl: Add TGL PCI IDs -:32: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #32: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) -:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #32: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) total: 1 errors, 0 warnings, 1 checks, 21 lines checked ff15c4352fcc x86/gpu: add TGL stolen memory support 2e99be826cae drm/i915/tgl: Check if pipe D is fused c66cb70352e9 drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A 48e70eb0a8fd drm/i915/tgl: Add power well support ce8d3b70dd79 drm/i915/tgl: Add power well to support 4th pipe d93d40c8620e drm/i915/tgl: Add new pll ids 6f0b3408f127 drm/i915/tgl: Add pll manager 0c85ba787405 drm/i915/tgl: Add additional ports for Tiger Lake 9c0c1f90cc5b drm/i915/tgl: update ddi/tc clock_off bits -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #24: FILE: drivers/gpu/drm/i915/i915_reg.h:9726: +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C ? 24 : \ + (port) + 10)) -:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #26: FILE: drivers/gpu/drm/i915/i915_reg.h:9728: +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ + (tc_port) + 12 : \ + (tc_port) - PORT_TC4 + 21)) total: 0 errors, 0 warnings, 2 checks, 14 lines checked 480ad7f760d3 drm/i915/tgl: Add gmbus gpio pin to port mapping 02eb68e95124 drm/i915/tgl: port to ddc pin mapping 515bc804c4ae drm/i915/tgl: select correct bit for port select 8ccbd571ebbe drm/i915/tgl: extend intel_port_is_combophy/tc dc4c3dc34108 drm/i915/tgl: init ddi port A-C for Tiger Lake 6c6c34e25091 drm/i915/tgl: Add vbt value mapping for DDC Bus pin 2a4b9d250782 drm/i915/tgl: apply Display WA #1178 to fix type C dongles ce6203f8c68e drm/i915/gen12: MBUS B credit change 281046dee43c drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization 47bbfafa8cfc drm/i915/tgl: Add DPLL registers 0482935d29fe drm/i915/tgl: Update DPLL clock reference register ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 18/25] drm/i915/tgl: extend intel_port_is_combophy/tc
From: Mahesh Kumar
TGL has 3 combophy ports, so extend check for tigerlake in
intel_port_is_combophy/tc function.
Cc: Mika Kahola
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d1148786920e..e224dcf60e31 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6676,10 +6676,10 @@ bool intel_port_is_combophy(struct drm_i915_private
*dev_priv, enum port port)
if (port == PORT_NONE)
return false;
- if (IS_ELKHARTLAKE(dev_priv))
+ if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
return port <= PORT_C;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_GEN(dev_priv, 11))
return port <= PORT_B;
return false;
@@ -6687,7 +6687,10 @@ bool intel_port_is_combophy(struct drm_i915_private
*dev_priv, enum port port)
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
{
- if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 12)
+ return port >= PORT_D && port <= PORT_I;
+
+ if (IS_GEN(dev_priv, 11) && !IS_ELKHARTLAKE(dev_priv))
return port >= PORT_C && port <= PORT_F;
return false;
@@ -6698,6 +6701,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private
*dev_priv, enum port port)
if (!intel_port_is_tc(dev_priv, port))
return PORT_TC_NONE;
+ if (INTEL_GEN(dev_priv) >= 12)
+ return port - PORT_D;
+
return port - PORT_C;
}
--
2.21.0
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[Intel-gfx] [PATCH v2 21/25] drm/i915/tgl: apply Display WA #1178 to fix type C dongles
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 11 ---
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 455f9aab188d..be3d4d1eece2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
int pw_idx = power_well->desc->hsw.idx;
enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
u32 val;
+ int wa_idx_max;
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -462,9 +463,13 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well);
- /* Display WA #1178: icl */
- if (IS_ICELAKE(dev_priv) &&
- pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
+ /* Display WA #1178: icl, tgl */
+ if (IS_TIGERLAKE(dev_priv))
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
+ else
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
+
+ if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
!intel_bios_is_port_edp(dev_priv, port)) {
val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ccfb95e2aa03..fbcc7981c8c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9246,9 +9246,11 @@ enum skl_power_gate {
#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
#define _ICL_AUX_ANAOVRD1_A0x162398
#define _ICL_AUX_ANAOVRD1_B0x6C398
+#define _TGL_AUX_ANAOVRD1_C0x160398
#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
_ICL_AUX_ANAOVRD1_A, \
- _ICL_AUX_ANAOVRD1_B))
+ _ICL_AUX_ANAOVRD1_B, \
+ _TGL_AUX_ANAOVRD1_C))
#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
--
2.21.0
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[Intel-gfx] [PATCH v2 12/25] drm/i915/tgl: Add pll manager
From: Vandita Kulkarni
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 67cfe836286e..ae1c552d7afb 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3455,6 +3455,21 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info tgl_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+ /* TODO: Add typeC plls */
+ { },
+};
+
+static const struct intel_dpll_mgr tgl_pll_mgr = {
+ .dpll_info = tgl_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -3468,7 +3483,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_ELKHARTLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 12)
+ dpll_mgr = &tgl_pll_mgr;
+ else if (IS_ELKHARTLAKE(dev_priv))
dpll_mgr = &ehl_pll_mgr;
else if (INTEL_GEN(dev_priv) >= 11)
dpll_mgr = &icl_pll_mgr;
--
2.21.0
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[Intel-gfx] [PATCH v2 20/25] drm/i915/tgl: Add vbt value mapping for DDC Bus pin
From: Mahesh Kumar
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 17 -
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..a08bc4f617c8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1354,12 +1354,27 @@ static const u8 mcc_ddc_pin_map[] = {
[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
};
+static const u8 tgp_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+ [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
+ [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+ [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+ [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+ [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+ [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
+ [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
+};
+
static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
{
const u8 *ddc_pin_map;
int n_entries;
- if (HAS_PCH_MCC(dev_priv)) {
+ if (HAS_PCH_TGP(dev_priv)) {
+ ddc_pin_map = tgp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
+ } else if (HAS_PCH_MCC(dev_priv)) {
ddc_pin_map = mcc_ddc_pin_map;
n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
} else if (HAS_PCH_ICP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2f4894e9a03d..93f5c9d204d6 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -310,10 +310,13 @@ enum vbt_gmbus_ddi {
DDC_BUS_DDI_F,
ICL_DDC_BUS_DDI_A = 0x1,
ICL_DDC_BUS_DDI_B,
+ TGL_DDC_BUS_DDI_C,
ICL_DDC_BUS_PORT_1 = 0x4,
ICL_DDC_BUS_PORT_2,
ICL_DDC_BUS_PORT_3,
ICL_DDC_BUS_PORT_4,
+ TGL_DDC_BUS_PORT_5,
+ TGL_DDC_BUS_PORT_6,
MCC_DDC_BUS_DDI_A = 0x1,
MCC_DDC_BUS_DDI_B,
MCC_DDC_BUS_DDI_C = 0x4,
--
2.21.0
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[Intel-gfx] [PATCH v2 17/25] drm/i915/tgl: select correct bit for port select
From: Mahesh Kumar
Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++-
drivers/gpu/drm/i915/i915_reg.h | 5 +++
2 files changed, 43 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index e72cf0bb48a7..5125c31af6aa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1771,7 +1771,10 @@ void intel_ddi_enable_transcoder_func(const struct
intel_crtc_state *crtc_state)
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = TRANS_DDI_FUNC_ENABLE;
- temp |= TRANS_DDI_SELECT_PORT(port);
+ if (INTEL_GEN(dev_priv) >= 12)
+ temp |= TGL_TRANS_DDI_SELECT_PORT(port);
+ else
+ temp |= TRANS_DDI_SELECT_PORT(port);
switch (crtc_state->pipe_bpp) {
case 18:
@@ -1851,8 +1854,14 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
u32 val = I915_READ(reg);
- val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
- val |= TRANS_DDI_PORT_NONE;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
+TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ } else {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
+TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ val |= TRANS_DDI_PORT_NONE;
+ }
I915_WRITE(reg, val);
if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
@@ -2004,10 +2013,19 @@ static void intel_ddi_get_encoder_pipes(struct
intel_encoder *encoder,
mst_pipe_mask = 0;
for_each_pipe(dev_priv, p) {
enum transcoder cpu_transcoder = (enum transcoder)p;
+ unsigned int port_mask, ddi_select;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ port_mask = TGL_TRANS_DDI_PORT_MASK;
+ ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
+ } else {
+ port_mask = TRANS_DDI_PORT_MASK;
+ ddi_select = TRANS_DDI_SELECT_PORT(port);
+ }
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
+ if ((tmp & port_mask) != ddi_select)
continue;
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
@@ -2123,9 +2141,14 @@ void intel_ddi_enable_pipe_clock(const struct
intel_crtc_state *crtc_state)
enum port port = encoder->port;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_PORT(port));
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_PORT(port));
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_PORT(port));
+ }
}
void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -2133,9 +2156,14 @@ void intel_ddi_disable_pipe_clock(const struct
intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_DISABLED);
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_DISABLED);
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_DISABLED);
+ }
}
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c554df69f289..ccfb95e2aa03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9379,8 +9379,10 @@ enum skl_power_gate {
#define TRANS_DDI_FUNC_ENABLE (1 << 31)
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
#define TRANS_DDI_PORT_MASK (7 << 28)
+#define TGL_TRANS_DDI_PORT_MASK (0xf << 27)
#define TRA
[Intel-gfx] [PATCH v2 07/25] drm/i915/tgl: Check if pipe D is fused
From: José Roberto de Souza
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31c6c168dde2..08dc71e4b818 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7633,6 +7633,7 @@ enum {
#define SKL_DFSM_PIPE_A_DISABLE(1 << 30)
#define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
#define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
+#define TGL_DFSM_PIPE_D_DISABLE(1 << 22)
#define SKL_DSSM _MMIO(0x51004)
#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index e0d9a7a37994..f99c9fd497b2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -938,6 +938,9 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
enabled_mask &= ~BIT(PIPE_B);
if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
enabled_mask &= ~BIT(PIPE_C);
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ (dfsm & TGL_DFSM_PIPE_D_DISABLE))
+ enabled_mask &= ~BIT(PIPE_D);
/*
* At least one pipe should be enabled and if there are
--
2.21.0
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[Intel-gfx] [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.
v2 (Lucas):
- Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
- Use crtc->dev since new_crtc_state->state may be NULL on atomic
commit (suggested by Maarten)
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ffec807b8960..c27912f552f0 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -459,16 +459,19 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
-* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
-* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* On ICL+ VDSC/joining for eDP/A transcoder uses a separate power well
+* PW2. This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
* For any other transcoder, VDSC/joining uses the power well associated
* with the pipe/transcoder in use. Hence another reference on the
* transcoder power domain will suffice.
*/
- if (cpu_transcoder == TRANSCODER_EDP)
+ if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
+ return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ else if (cpu_transcoder == TRANSCODER_EDP)
return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
else
return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
--
2.21.0
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[Intel-gfx] [PATCH v2 19/25] drm/i915/tgl: init ddi port A-C for Tiger Lake
From: Mahesh Kumar
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e224dcf60e31..9ccf58ff4dba 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15302,12 +15302,17 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ /* TODO: initialize TC ports as well */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ } else if (IS_ELKHARTLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
icl_dsi_init(dev_priv);
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (IS_GEN(dev_priv, 11)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.21.0
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[Intel-gfx] [PATCH v2 04/25] drm/i915/tgl: Add TGL PCH detection in virtualized environment
From: Mahesh Kumar Assume PCH_TGP when platform is TGL. Cc: Rodrigo Vivi Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_drv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index bcedd2d8e267..926bbf2d169b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -255,7 +255,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) * make an educated guess as to which PCH is really there. */ - if (IS_ELKHARTLAKE(dev_priv)) + if (IS_TIGERLAKE(dev_priv)) + id = INTEL_PCH_TGP_DEVICE_ID_TYPE; + else if (IS_ELKHARTLAKE(dev_priv)) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; else if (IS_ICELAKE(dev_priv)) id = INTEL_PCH_ICP_DEVICE_ID_TYPE; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 16/25] drm/i915/tgl: port to ddc pin mapping
From: Mahesh Kumar
Create a helper function to get ddc pin according to port number.
Cc: Anusha Srivatsa
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..3b33e7626d7c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2981,6 +2981,18 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return ddc_pin;
}
+static u8 tgp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
+ enum port port)
+{
+ if (intel_port_is_combophy(dev_priv, port))
+ return GMBUS_PIN_1_BXT + port;
+ else if (intel_port_is_tc(dev_priv, port))
+ return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
+
+ WARN(1, "Unknown port:%c\n", port_name(port));
+ return GMBUS_PIN_2_BXT;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3017,7 +3029,9 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
*dev_priv,
return info->alternate_ddc_pin;
}
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ ddc_pin = tgp_port_to_ddc_pin(dev_priv, port);
+ else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_ICP(dev_priv))
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
--
2.21.0
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[Intel-gfx] [PATCH v2 02/25] drm/i915/tgl: add initial Tiger Lake definitions
From: Daniele Ceraolo Spurio
Tiger Lake is a Intel® Processor containing Intel® HD Graphics.
This is just an initial Tiger Lake definition. PCI IDs, generic support
and new features coming in following patches.
v2 (Lucas):
- Remove modular FIA - feature will be re-introduced in future
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 29
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
4 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e05bc3e1014d..2508b1222d2c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2088,6 +2088,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 94b588e0a1dd..da926485845d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -765,6 +765,35 @@ static const struct intel_device_info
intel_elkhartlake_info = {
.ppgtt_size = 36,
};
+#define GEN12_FEATURES \
+ GEN11_FEATURES, \
+ GEN(12), \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }
+
+static const struct intel_device_info intel_tigerlake_12_info = {
+ GEN12_FEATURES,
+ PLATFORM(INTEL_TIGERLAKE),
+ .num_pipes = 4,
+ .require_force_probe = 1,
+ .engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+};
+
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index e64536e1fd1b..e0d9a7a37994 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -58,6 +58,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(CANNONLAKE),
PLATFORM_NAME(ICELAKE),
PLATFORM_NAME(ELKHARTLAKE),
+ PLATFORM_NAME(TIGERLAKE),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index ddafc819bf30..468582484758 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -78,6 +78,8 @@ enum intel_platform {
/* gen11 */
INTEL_ICELAKE,
INTEL_ELKHARTLAKE,
+ /* gen12 */
+ INTEL_TIGERLAKE,
INTEL_MAX_PLATFORMS
};
--
2.21.0
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[Intel-gfx] [PATCH v2 22/25] drm/i915/gen12: MBUS B credit change
From: Rodrigo Vivi
Previously, the recommended B credit for all platforms was 24 / number
of pipes, which would give 6 for newer platforms with 4 pipes. However 6
is not enough and we need 12 on these cases.
We also need a different BW credit for these platforms.
Cc: Arthur J Runyan
Signed-off-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9ccf58ff4dba..9a5d04a2ab3e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6423,8 +6423,14 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
u32 val;
val = MBUS_DBOX_A_CREDIT(2);
- val |= MBUS_DBOX_BW_CREDIT(1);
- val |= MBUS_DBOX_B_CREDIT(8);
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val |= MBUS_DBOX_BW_CREDIT(2);
+ val |= MBUS_DBOX_B_CREDIT(12);
+ } else {
+ val |= MBUS_DBOX_BW_CREDIT(1);
+ val |= MBUS_DBOX_B_CREDIT(8);
+ }
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
--
2.21.0
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[Intel-gfx] [PATCH v2 15/25] drm/i915/tgl: Add gmbus gpio pin to port mapping
From: Mahesh Kumar
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
drivers/gpu/drm/i915/display/intel_gmbus.c | 20 ++--
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 270b1f18dedd..231d8595845a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -45,6 +45,8 @@ enum i915_gpio {
GPIOK,
GPIOL,
GPIOM,
+ GPION,
+ GPIOO,
};
/*
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 4f6a9bd5af47..b42c79aea61a 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] = {
[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
};
+static const struct gmbus_pin gmbus_pins_tgp[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+ [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+ [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+ [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+ [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+ [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ return &gmbus_pins_tgp[pin];
+ else if (HAS_PCH_MCC(dev_priv))
return &gmbus_pins_mcc[pin];
else if (HAS_PCH_ICP(dev_priv))
return &gmbus_pins_icp[pin];
@@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv,
{
unsigned int size;
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ size = ARRAY_SIZE(gmbus_pins_tgp);
+ else if (HAS_PCH_MCC(dev_priv))
size = ARRAY_SIZE(gmbus_pins_mcc);
else if (HAS_PCH_ICP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4588df9e11de..c554df69f289 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3254,8 +3254,10 @@ enum i915_power_well_id {
#define GMBUS_PIN_10_TC2_ICP 10
#define GMBUS_PIN_11_TC3_ICP 11
#define GMBUS_PIN_12_TC4_ICP 12
+#define GMBUS_PIN_13_TC5_TGP 13
+#define GMBUS_PIN_14_TC6_TGP 14
-#define GMBUS_NUM_PINS 13 /* including 0 */
+#define GMBUS_NUM_PINS 15 /* including 0 */
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /*
command/status */
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
--
2.21.0
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[Intel-gfx] [PATCH v2 13/25] drm/i915/tgl: Add additional ports for Tiger Lake
From: Vandita Kulkarni
There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
combophy port. This results in 6 typeC ports and 3 combophy ports.
These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
DP on legacy DP connector or native HDMI on legacy connector.
v2: Rebase on new modular FIA code (Lucas)
Cc: Anusha Srivatsa
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
include/drm/i915_component.h | 2 +-
include/drm/i915_drm.h | 3 +++
4 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 30e48609db1d..e72cf0bb48a7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4297,6 +4297,18 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
intel_dig_port->ddi_io_power_domain =
POWER_DOMAIN_PORT_DDI_F_IO;
break;
+ case PORT_G:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_G_IO;
+ break;
+ case PORT_H:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_H_IO;
+ break;
+ case PORT_I:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_I_IO;
+ break;
default:
MISSING_CASE(port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index e781df463ffa..270b1f18dedd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -189,6 +189,8 @@ enum tc_port {
PORT_TC2,
PORT_TC3,
PORT_TC4,
+ PORT_TC5,
+ PORT_TC6,
I915_MAX_TC_PORTS
};
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index dcb95bd9dee6..55c3b123581b 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -34,7 +34,7 @@ enum i915_component_type {
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
*/
-#define MAX_PORTS 6
+#define MAX_PORTS 9
/**
* struct i915_audio_component - Used for direct communication between i915
and hda drivers
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7523e9a7b6e2..eb30062359d1 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -109,6 +109,9 @@ enum port {
PORT_D,
PORT_E,
PORT_F,
+ PORT_G,
+ PORT_H,
+ PORT_I,
I915_MAX_PORTS
};
--
2.21.0
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[Intel-gfx] [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++
drivers/gpu/drm/i915/i915_reg.h | 15
2 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ae1c552d7afb..330b42a1f54e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3113,8 +3113,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ if (INTEL_GEN(dev_priv) >= 12) {
+ hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
+ } else {
+ hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ }
ret = true;
out:
@@ -3148,10 +3153,19 @@ static void icl_dpll_write(struct drm_i915_private
*dev_priv,
{
struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
const enum intel_dpll_id id = pll->info->id;
+ i915_reg_t cfgcr0_reg, cfgcr1_reg;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ cfgcr0_reg = TGL_DPLL_CFGCR0(id);
+ cfgcr1_reg = TGL_DPLL_CFGCR1(id);
+ } else {
+ cfgcr0_reg = ICL_DPLL_CFGCR0(id);
+ cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+ }
- I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
- I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
- POSTING_READ(ICL_DPLL_CFGCR1(id));
+ I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
+ I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
+ POSTING_READ(cfgcr1_reg);
}
static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbcc7981c8c4..84c04ea67ec8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -9958,6 +9959,20 @@ enum skl_power_gate {
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
_ICL_DPLL1_CFGCR1)
+#define _TGL_DPLL0_CFGCR0 0x164284
+#define _TGL_DPLL1_CFGCR0 0x16428C
+#define _TGL_TBTPLL_CFGCR0 0x16429C
+#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0)
+
+#define _TGL_DPLL0_CFGCR1 0x164288
+#define _TGL_DPLL1_CFGCR1 0x164290
+#define _TGL_TBTPLL_CFGCR1 0x1642A0
+#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1)
+
/* BXT display engine PLL */
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
--
2.21.0
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[Intel-gfx] [PATCH v2 11/25] drm/i915/tgl: Add new pll ids
From: Vandita Kulkarni
Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 4c2c5e93aff3..d0e14ed6e5f8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -112,11 +112,11 @@ enum intel_dpll_id {
/**
-* @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
+* @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
*/
DPLL_ID_ICL_DPLL0 = 0,
/**
-* @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
+* @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
*/
DPLL_ID_ICL_DPLL1 = 1,
/**
@@ -124,27 +124,40 @@ enum intel_dpll_id {
*/
DPLL_ID_EHL_DPLL4 = 2,
/**
-* @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
+* @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
*/
DPLL_ID_ICL_TBTPLL = 2,
/**
-* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
+* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
+* TGL TC PLL 1 port 1 (TC1)
*/
DPLL_ID_ICL_MGPLL1 = 3,
/**
* @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
+* TGL TC PLL 1 port 2 (TC2)
*/
DPLL_ID_ICL_MGPLL2 = 4,
/**
* @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
+* TGL TC PLL 1 port 3 (TC3)
*/
DPLL_ID_ICL_MGPLL3 = 5,
/**
* @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
+* TGL TC PLL 1 port 4 (TC4)
*/
DPLL_ID_ICL_MGPLL4 = 6,
+ /**
+* @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
+*/
+ DPLL_ID_TGL_MGPLL5 = 7,
+ /**
+* @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
+*/
+ DPLL_ID_TGL_MGPLL6 = 8,
};
-#define I915_NUM_PLLS 7
+
+#define I915_NUM_PLLS 9
enum icl_port_dpll_id {
ICL_PORT_DPLL_DEFAULT,
--
2.21.0
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[Intel-gfx] [PATCH v2 23/25] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
According to the spec when initializing the display in TGL we should not
set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-use the
power well hooks from ICL so just check for IS_TIGERLAKE() inside it.
Cc: Imre Deak
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index be3d4d1eece2..f040a74349df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
- val = I915_READ(ICL_PORT_CL_DW12(port));
- I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
+ if (!IS_TIGERLAKE(dev_priv)) {
+ val = I915_READ(ICL_PORT_CL_DW12(port));
+ I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
+ }
hsw_wait_for_power_well_enable(dev_priv, power_well);
@@ -486,8 +488,10 @@ icl_combo_phy_aux_power_well_disable(struct
drm_i915_private *dev_priv,
enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
u32 val;
- val = I915_READ(ICL_PORT_CL_DW12(port));
- I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
+ if (!IS_TIGERLAKE(dev_priv)) {
+ val = I915_READ(ICL_PORT_CL_DW12(port));
+ I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
+ }
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
--
2.21.0
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[Intel-gfx] [PATCH v2 06/25] x86/gpu: add TGL stolen memory support
From: Michel Thierry
Reuse Gen11 stolen memory changes since Tiger Lake uses the same BSM
register (and format).
Cc: Rodrigo Vivi
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
arch/x86/kernel/early-quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6c4f01540833..6f6b1d04dadf 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_CNL_IDS(&gen9_early_ops),
INTEL_ICL_11_IDS(&gen11_early_ops),
INTEL_EHL_IDS(&gen11_early_ops),
+ INTEL_TGL_12_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0,
0);
--
2.21.0
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[Intel-gfx] [PATCH v2 09/25] drm/i915/tgl: Add power well support
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:
- Transcoder#EDP removed from power well#1 (Transcoder#A used in
low-power mode instead)
- Transcoder#A is now backed by power well#1 instead of power well#3
- The DDI#B/C combo PHY ports are now backed by power well#1 instead of
power well#3
- New power well#5 added for pipe#D functionality (TODO)
- 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
specific IO power wells (only for the non-TBT modes) and 4 port
specific AUX power wells (2-2 for TBT vs. non-TBT modes)
- Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
eDP and MIPI DSI (TODO)
On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-B
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI#C-F
Starting from GEN 12 we have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-C
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI TC#1-6
To save some space in the power domain enum the power domain naming in
the driver reflects the above change, that is power domains TC#1-3 are
added as aliases for DDI#D-F and new power domains are reserved for
TC#4-6.
v2 (Lucas):
- Separate out the bits and definitions for TGL from the ICL ones.
Fix use of TRANSCODER_EDP_VDSC, that is now the correct define since
we don't define TRANSCODER_A_VDSC power domain to spare a one bit in
the bitmask (suggested by Ville)
Cc: Ville Syrjälä
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 480 +-
.../drm/i915/display/intel_display_power.h| 26 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 18 +
4 files changed, 508 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7437fc71d289..c3f42169831f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -23,8 +23,11 @@ bool intel_display_power_well_is_enabled(struct
drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain)
+intel_display_power_domain_str(struct drm_i915_private *i915,
+ enum intel_display_power_domain domain)
{
+ bool ddi_tc_ports = IS_GEN(i915, 12);
+
switch (domain) {
case POWER_DOMAIN_DISPLAY_CORE:
return "DISPLAY_CORE";
@@ -61,11 +64,23 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_LANES:
return "PORT_DDI_C_LANES";
case POWER_DOMAIN_PORT_DDI_D_LANES:
- return "PORT_DDI_D_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
+POWER_DOMAIN_PORT_DDI_TC1_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
case POWER_DOMAIN_PORT_DDI_E_LANES:
- return "PORT_DDI_E_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
+POWER_DOMAIN_PORT_DDI_TC2_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
case POWER_DOMAIN_PORT_DDI_F_LANES:
- return "PORT_DDI_F_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
+POWER_DOMAIN_PORT_DDI_TC3_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC4_LANES:
+ return "PORT_DDI_TC4_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC5_LANES:
+ return "PORT_DDI_TC5_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC6_LANES:
+ return "PORT_DDI_TC6_LANES";
case POWER_DOMAIN_PORT_DDI_A_IO:
return "PORT_DDI_A_IO";
case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -73,11 +88,23 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_IO:
return "PORT_DDI_C_IO";
case POWER_DOMAIN_PORT_DDI_D_IO:
- return "PORT_DDI_D_IO";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
+POWER_DOMAIN_PORT_DDI_TC1_IO);
+ return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
case POWER_DOMAIN_PORT_DDI_E_IO:
- return "PORT_DDI_E_IO";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_I
[Intel-gfx] [PATCH v2 25/25] drm/i915/tgl: Update DPLL clock reference register
From: José Roberto de Souza
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 330b42a1f54e..9793039485e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2597,8 +2597,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
*crtc_state,
cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
DPLL_CFGCR1_KDIV(pll_params.kdiv) |
-DPLL_CFGCR1_PDIV(pll_params.pdiv) |
-DPLL_CFGCR1_CENTRAL_FREQ_8400;
+DPLL_CFGCR1_PDIV(pll_params.pdiv);
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
+ else
+ cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
memset(pll_state, 0, sizeof(*pll_state));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84c04ea67ec8..a244e8158aee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9947,6 +9947,7 @@ enum skl_power_gate {
#define DPLL_CFGCR1_PDIV_7(8 << 2)
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
+#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1,
_CNL_DPLL1_CFGCR1)
#define _ICL_DPLL0_CFGCR0 0x164000
--
2.21.0
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[Intel-gfx] [PATCH v2 05/25] drm/i915/tgl: Add TGL PCI IDs
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da926485845d..e83c94cf2744 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -865,6 +865,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CNL_IDS(&intel_cannonlake_info),
INTEL_ICL_11_IDS(&intel_icelake_11_info),
INTEL_EHL_IDS(&intel_elkhartlake_info),
+ INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 6c342ac470c8..a70c982ddff9 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -583,4 +583,14 @@
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info)
+/* TGL */
+#define INTEL_TGL_12_IDS(info) \
+ INTEL_VGA_DEVICE(0x9A49, info), \
+ INTEL_VGA_DEVICE(0x9A40, info), \
+ INTEL_VGA_DEVICE(0x9A59, info), \
+ INTEL_VGA_DEVICE(0x9A60, info), \
+ INTEL_VGA_DEVICE(0x9A68, info), \
+ INTEL_VGA_DEVICE(0x9A70, info), \
+ INTEL_VGA_DEVICE(0x9A78, info)
+
#endif /* _I915_PCIIDS_H */
--
2.21.0
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[Intel-gfx] [PATCH v2 03/25] drm/i915/tgl: Introduce Tiger Lake PCH
From: Radhakrishna Sripada
Add the enum additions to TGP.
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: David Weinehall
Cc: James Ausmus
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 794c6814a6d0..bcedd2d8e267 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -224,6 +224,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
WARN_ON(!IS_ELKHARTLAKE(dev_priv));
return PCH_MCC;
+ case INTEL_PCH_TGP_DEVICE_ID_TYPE:
+ DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
+ WARN_ON(!IS_TIGERLAKE(dev_priv));
+ return PCH_TGP;
default:
return PCH_NONE;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2508b1222d2c..3248f9959227 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -536,6 +536,7 @@ enum intel_pch {
PCH_CNP,/* Cannon/Comet Lake PCH */
PCH_ICP,/* Ice Lake PCH */
PCH_MCC,/* Mule Creek Canyon PCH */
+ PCH_TGP,/* Tiger Lake PCH */
};
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
@@ -2322,6 +2323,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
#define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
+#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
@@ -2329,6 +2331,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
+#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
--
2.21.0
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[Intel-gfx] [PATCH v2 14/25] drm/i915/tgl: update ddi/tc clock_off bits
From: Mahesh Kumar
In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca74eca05a4..4588df9e11de 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9723,9 +9723,11 @@ enum skl_power_gate {
#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 :
\
(port) + 10))
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
- 21 : (tc_port) + 12))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C ? 24 : \
+ (port) + 10))
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+ (tc_port) + 12 : \
+ (tc_port) - PORT_TC4 +
21))
#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
(port) * 2)
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 <<
DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
--
2.21.0
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[Intel-gfx] [PATCH v2 00/25] Initial support for Tiger Lake
v2 of https://patchwork.freedesktop.org/series/62726/ - Remove patches already reviewed - Remove modular FIA - it's handled in a separate series now - Add r-b on some patches - Handle comments on power well definitions Patches are from their original authors, modified as per review on upstream. Daniele Ceraolo Spurio (1): drm/i915/tgl: add initial Tiger Lake definitions Imre Deak (1): drm/i915/tgl: Add power well support José Roberto de Souza (3): drm/i915/tgl: Check if pipe D is fused drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi (5): drm/i915: Add 4th pipe and transcoder drm/i915/tgl: Add TGL PCI IDs drm/i915/tgl: apply Display WA #1178 to fix type C dongles drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization drm/i915/tgl: Add DPLL registers Mahesh Kumar (8): drm/i915/tgl: Add TGL PCH detection in virtualized environment drm/i915/tgl: update ddi/tc clock_off bits drm/i915/tgl: Add gmbus gpio pin to port mapping drm/i915/tgl: port to ddc pin mapping drm/i915/tgl: select correct bit for port select drm/i915/tgl: extend intel_port_is_combophy/tc drm/i915/tgl: init ddi port A-C for Tiger Lake drm/i915/tgl: Add vbt value mapping for DDC Bus pin Michel Thierry (1): x86/gpu: add TGL stolen memory support Mika Kahola (1): drm/i915/tgl: Add power well to support 4th pipe Radhakrishna Sripada (1): drm/i915/tgl: Introduce Tiger Lake PCH Rodrigo Vivi (1): drm/i915/gen12: MBUS B credit change Vandita Kulkarni (3): drm/i915/tgl: Add new pll ids drm/i915/tgl: Add pll manager drm/i915/tgl: Add additional ports for Tiger Lake arch/x86/kernel/early-quirks.c| 1 + drivers/gpu/drm/i915/display/intel_bios.c | 17 +- drivers/gpu/drm/i915/display/intel_ddi.c | 60 +- drivers/gpu/drm/i915/display/intel_display.c | 34 +- drivers/gpu/drm/i915/display/intel_display.h | 8 + .../drm/i915/display/intel_display_power.c| 525 +- .../drm/i915/display/intel_display_power.h| 29 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 51 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +- drivers/gpu/drm/i915/display/intel_gmbus.c| 20 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 + drivers/gpu/drm/i915/display/intel_vdsc.c | 9 +- drivers/gpu/drm/i915/i915_debugfs.c | 3 +- drivers/gpu/drm/i915/i915_drv.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_pci.c | 30 + drivers/gpu/drm/i915/i915_reg.h | 62 ++- drivers/gpu/drm/i915/intel_device_info.c | 4 + drivers/gpu/drm/i915/intel_device_info.h | 2 + include/drm/i915_component.h | 2 +- include/drm/i915_drm.h| 3 + include/drm/i915_pciids.h | 10 + 23 files changed, 852 insertions(+), 72 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 30 ---
.../drm/i915/display/intel_display_power.h| 3 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +-
3 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index c3f42169831f..455f9aab188d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private
*i915,
return "PIPE_B";
case POWER_DOMAIN_PIPE_C:
return "PIPE_C";
+ case POWER_DOMAIN_PIPE_D:
+ return "PIPE_D";
case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
return "PIPE_A_PANEL_FITTER";
case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
return "PIPE_B_PANEL_FITTER";
case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
return "PIPE_C_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
+ return "PIPE_D_PANEL_FITTER";
case POWER_DOMAIN_TRANSCODER_A:
return "TRANSCODER_A";
case POWER_DOMAIN_TRANSCODER_B:
return "TRANSCODER_B";
case POWER_DOMAIN_TRANSCODER_C:
return "TRANSCODER_C";
+ case POWER_DOMAIN_TRANSCODER_D:
+ return "TRANSCODER_D";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
@@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
* - DDI_A
* - FBC
*/
-/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
#define ICL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
@@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
#define ICL_AUX_TBT4_IO_POWER_DOMAINS (\
BIT_ULL(POWER_DOMAIN_AUX_TBT4))
+#define TGL_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
#define TGL_PW_4_POWER_DOMAINS ( \
+ TGL_PW_5_POWER_DOMAINS |\
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
- /* TODO: TRANSCODER_D */\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
@@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
},
{
.name = "power well 4",
- .domains = ICL_PW_4_POWER_DOMAINS,
+ .domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
.hsw.irq_pipe_mask = BIT(PIPE_C),
}
},
- /* TODO: power well 5 for pipe D */
+ {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
};
static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 86afd70c1fb2..ebb397e330ea 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -18,12 +18,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_D,
POWER_DOMAIN_PIPE_A_PANEL_FITTER,
POWER_DOMAIN_PIPE_B_PANEL_FITTER,
POWER_DOMAIN_PIPE_C_PANEL_FITTER,
+ POWER_DOMAIN_PIPE_D_PANEL_FITTER,
POWER_DOMAIN_TRANSCODER_A,
[Intel-gfx] [PATCH v2 01/25] drm/i915: Add 4th pipe and transcoder
Add pipe D and transcoder D to prepare for platforms having them.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.h | 4
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f09eda75711a..d1148786920e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17178,7 +17178,7 @@ struct intel_display_error_state {
u32 vtotal;
u32 vblank;
u32 vsync;
- } transcoder[4];
+ } transcoder[5];
};
struct intel_display_error_state *
@@ -17189,6 +17189,7 @@ intel_display_capture_error_state(struct
drm_i915_private *dev_priv)
TRANSCODER_A,
TRANSCODER_B,
TRANSCODER_C,
+ TRANSCODER_D,
TRANSCODER_EDP,
};
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index d296556ed82e..e781df463ffa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -58,6 +58,7 @@ enum pipe {
PIPE_A = 0,
PIPE_B,
PIPE_C,
+ PIPE_D,
_PIPE_EDP,
I915_MAX_PIPES = _PIPE_EDP
@@ -75,6 +76,7 @@ enum transcoder {
TRANSCODER_A = PIPE_A,
TRANSCODER_B = PIPE_B,
TRANSCODER_C = PIPE_C,
+ TRANSCODER_D = PIPE_D,
/*
* The following transcoders can map to any pipe, their enum value
@@ -98,6 +100,8 @@ static inline const char *transcoder_name(enum transcoder
transcoder)
return "B";
case TRANSCODER_C:
return "C";
+ case TRANSCODER_D:
+ return "D";
case TRANSCODER_EDP:
return "EDP";
case TRANSCODER_DSI_A:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5898f59e3dd7..31c6c168dde2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4217,6 +4217,7 @@ enum {
#define TRANSCODER_B_OFFSET 0x61000
#define TRANSCODER_C_OFFSET 0x62000
#define CHV_TRANSCODER_C_OFFSET 0x63000
+#define TRANSCODER_D_OFFSET 0x63000
#define TRANSCODER_EDP_OFFSET 0x6f000
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
@@ -5763,6 +5764,7 @@ enum {
#define PIPE_A_OFFSET 0x7
#define PIPE_B_OFFSET 0x71000
#define PIPE_C_OFFSET 0x72000
+#define PIPE_D_OFFSET 0x73000
#define CHV_PIPE_C_OFFSET 0x74000
/*
* There's actually no pipe EDP. Some pipe registers have
@@ -9346,6 +9348,7 @@ enum skl_power_gate {
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
#define _TRANS_DDI_FUNC_CTL_C 0x62400
+#define _TRANS_DDI_FUNC_CTL_D 0x63400
#define _TRANS_DDI_FUNC_CTL_EDP0x6F400
#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
--
2.21.0
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Re: [Intel-gfx] [PATCH 8/8] drm/i915/gt: Use intel_gt as the primary object for handling resets
On 7/5/19 12:46 AM, Chris Wilson wrote:
Having taken the first step in encapsulating the functionality by moving
the related files under gt/, the next step is to start encapsulating by
passing around the relevant structs rather than the global
drm_i915_private. In this step, we pass intel_gt to intel_reset.c
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/display/intel_display.c | 21 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 8 +-
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 25 +-
drivers/gpu/drm/i915/gem/i915_gem_throttle.c | 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 20 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 4 +-
.../i915/gem/selftests/i915_gem_coherency.c | 6 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 17 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 2 +-
.../i915/gem/selftests/i915_gem_object_blt.c | 4 +-
drivers/gpu/drm/i915/gt/intel_engine.h| 8 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 +-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 7 +
drivers/gpu/drm/i915/gt/intel_gt.h| 12 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 19 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 12 +
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 67 +--
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 435 +-
drivers/gpu/drm/i915/gt/intel_reset.h | 73 +--
drivers/gpu/drm/i915/gt/intel_reset_types.h | 50 ++
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 107 +++--
drivers/gpu/drm/i915/gt/selftest_lrc.c| 36 +-
drivers/gpu/drm/i915/gt/selftest_reset.c | 50 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 3 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 33 +-
drivers/gpu/drm/i915/i915_debugfs.c | 63 +--
drivers/gpu/drm/i915/i915_drv.c | 5 +-
drivers/gpu/drm/i915/i915_drv.h | 35 +-
drivers/gpu/drm/i915/i915_gem.c | 31 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 52 +--
drivers/gpu/drm/i915/i915_request.c | 5 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_active.c | 3 +-
drivers/gpu/drm/i915/selftests/i915_gem.c | 3 +-
.../gpu/drm/i915/selftests/i915_gem_evict.c | 3 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 4 +-
.../gpu/drm/i915/selftests/i915_selftest.c| 2 +-
.../gpu/drm/i915/selftests/igt_flush_test.c | 5 +-
drivers/gpu/drm/i915/selftests/igt_reset.c| 38 +-
drivers/gpu/drm/i915/selftests/igt_reset.h| 10 +-
drivers/gpu/drm/i915/selftests/igt_wedge_me.h | 58 ---
.../gpu/drm/i915/selftests/mock_gem_device.c | 5 -
48 files changed, 665 insertions(+), 709 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_reset_types.h
delete mode 100644 drivers/gpu/drm/i915/selftests/igt_wedge_me.h
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 919f5ac844c8..4dd6856bf722 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4249,12 +4249,12 @@ void intel_prepare_reset(struct drm_i915_private
*dev_priv)
return;
/* We have a modeset vs reset deadlock, defensively unbreak it. */
- set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
- wake_up_all(&dev_priv->gpu_error.wait_queue);
+ set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
+ wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
The doc for wake_up_bit says that we need a memory barrier before
calling it. Do we have it implicitly somewhere or is it missing?
if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through
wedging\n");
- i915_gem_set_wedged(dev_priv);
+ intel_gt_set_wedged(&dev_priv->gt);
}
/*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index bf085b0cb7c6..8e2eeaec06cb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -123,18 +124,18 @@ static bool switch_to_kernel_context_sync(struct
drm_i915_private *i915)
* Forcibly cancel outstanding work and leave
* the gpu quiet.
*/
- i915_gem_set_wedged(i915);
+ intel_gt_set_wedged(gt);
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Set igt_spinner.gt for early exit
== Series Details == Series: drm/i915/selftests: Set igt_spinner.gt for early exit URL : https://patchwork.freedesktop.org/series/63414/ State : success == Summary == CI Bug Log - changes from CI_DRM_6433 -> Patchwork_13573 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13573/ Known issues Here are the changes found in Patchwork_13573 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_create@basic: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-icl-u3/igt@gem_exec_cre...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13573/fi-icl-u3/igt@gem_exec_cre...@basic.html * igt@gem_exec_suspend@basic-s4-devices: - fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([fdo#105128] / [fdo#107139]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13573/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_pm_rpm@module-reload: - fi-icl-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#108840]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-icl-dsi/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13573/fi-icl-dsi/igt@i915_pm_...@module-reload.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#109635 ]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13573/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13573/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_contexts: - fi-skl-iommu: [INCOMPLETE][11] ([fdo#111050]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-skl-iommu/igt@i915_selftest@live_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13573/fi-skl-iommu/igt@i915_selftest@live_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][13] ([fdo#109485]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13573/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128 [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050 Participating hosts (53 -> 46) -- Additional (1): fi-icl-guc Missing(8): fi-kbl-soraka fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper Build changes - * Linux: CI_DRM_6433 -> Patchwork_13573 CI_DRM_6433: 6da10e343bc0d479ab208c4c291bab18ee11d1ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13573: 41e029d7300e78c47c14387ff67a22738f421837 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13573/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 41e029d7300e drm/i915/selftests: Set igt_spinner.gt for early exit == Logs == For more deta
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Define GuC firmware version for Comet Lake (rev2)
== Series Details ==
Series: drm/i915/guc: Define GuC firmware version for Comet Lake (rev2)
URL : https://patchwork.freedesktop.org/series/62969/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6433 -> Patchwork_13572
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13572/
Known issues
Here are the changes found in Patchwork_13572 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13572/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13572/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][5] ([fdo#111050]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13572/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@hdmi-edid-read:
- {fi-icl-u4}:[FAIL][7] ([fdo#111046 ]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13572/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13572/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (53 -> 46)
--
Additional (1): fi-icl-guc
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper
Build changes
-
* Linux: CI_DRM_6433 -> Patchwork_13572
CI_DRM_6433: 6da10e343bc0d479ab208c4c291bab18ee11d1ea @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13572: 22edd0eb3effa82e733048539d583d611ea090ed @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13572/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
22edd0eb3eff drm/i915/guc: Define GuC firmware version for Comet Lake
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13572/
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[Intel-gfx] [PATCH] drm/i915/selftests: Set igt_spinner.gt for early exit
Set up a default gt pointer for an early cleanup of igt_spinnter, before
a request is created and igt_spinner.gt set to the active engine's.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/selftests/igt_spinner.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c
b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 0c1f65262a63..89b6552a6497 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -19,6 +19,7 @@ int igt_spinner_init(struct igt_spinner *spin, struct
drm_i915_private *i915)
memset(spin, 0, sizeof(*spin));
spin->i915 = i915;
+ spin->gt = &i915->gt;
spin->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(spin->hws)) {
--
2.20.1
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[Intel-gfx] PR- GUC v33 (BXT,SKL,GLK.KBL,ICL)
Hi, Can these i915 changes be merged to the linux-firmware.git? The following changes since commit 70e43940b05e8d6e0c5f15b5e2d67760f1581ece: linux-firmware: rsi: add firmware image for redpine 9116 chipset (2019-06-28 07:41:20 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware guc_v33 for you to fetch changes up to 05dbae6639f09c3e0a02e93de5f803db9aadedd1: drm/i915/firmware: Add v33 of GuC for ICL (2019-07-08 14:40:55 -0700) Anusha Srivatsa (5): drm/i915/firmware: Add v33 of GuC for BXT drm/i915/firmware: Add v33 of GuC for GLK drm/i915/firmware: Add v33 of GuC for SKL drm/i915/firmware: Add v33 of GuC for KBL drm/i915/firmware: Add v33 of GuC for ICL WHENCE | 15 +++ i915/bxt_guc_33.0.0.bin | Bin 0 -> 181888 bytes i915/glk_guc_33.0.0.bin | Bin 0 -> 182336 bytes i915/icl_guc_33.0.0.bin | Bin 0 -> 385280 bytes i915/kbl_guc_33.0.0.bin | Bin 0 -> 182912 bytes i915/skl_guc_33.0.0.bin | Bin 0 -> 182080 bytes 6 files changed, 15 insertions(+) create mode 100644 i915/bxt_guc_33.0.0.bin create mode 100644 i915/glk_guc_33.0.0.bin create mode 100644 i915/icl_guc_33.0.0.bin create mode 100644 i915/kbl_guc_33.0.0.bin create mode 100644 i915/skl_guc_33.0.0.bin Thanks, Anusha ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Remove presumption of RCS0
Quoting Summers, Stuart (2019-07-08 22:11:15)
> On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote:
> > We now track features correctly instead of probing i915->engine[RCS0]
> > which is much more flexible and avoids any nasty surprises.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 --
> > 1 file changed, 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index df5932f5f578..bdf279fa3b2e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -448,12 +448,6 @@ int intel_engines_init_mmio(struct
> > drm_i915_private *i915)
> > if (WARN_ON(mask != engine_mask))
> > device_info->engine_mask = mask;
> >
> > - /* We always presume we have at least RCS available for later
> > probing */
> > - if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
> > - err = -ENODEV;
> > - goto cleanup;
> > - }
> > -
>
> Just going by the series here, we have quite a few other place we are
> touching RCS0 specifically during driver load. Do we really want to get
> rid of this? Or is there an alternative if RCS0 isn't present for some
> reason?
Outside of gvt/ (which I don't dare to try and verify), the only places
where we now mention RCS0 are in direct hw mappings to that engine
(e.g. interrupts and mmio setup). [Excluding selftests/ which are mostly
converted and really just a matter of generalising if applicable or
marking as "no really, this only applies to RCS0".] Assuming the other
couple of patches also land.
-Chris
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[Intel-gfx] [PATCH] drm/i915/guc: Define GuC firmware version for Comet Lake
Load GuC for Comet Lake. Depending on the REVID,
we load either the KBL firmware or the CML firmware.
v2: Use CFL for CML platform check.(Michal)
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index db1e0daca7db..df0dfa49fbc8 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -58,6 +58,13 @@ MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
+#define CML_GUC_FW_PREFIX cml
+#define CML_GUC_FW_MAJOR 33
+#define CML_GUC_FW_MINOR 0
+#define CML_GUC_FW_PATCH 0
+#define CML_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
+MODULE_FIRMWARE(CML_GUC_FIRMWARE_PATH);
+
#define GLK_GUC_FW_PREFIX glk
#define GLK_GUC_FW_MAJOR 33
#define GLK_GUC_FW_MINOR 0
@@ -94,7 +101,17 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = GLK_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
- } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+ } else if (IS_COFFEELAKE(i915)) {
+ if (INTEL_REVID(i915) == 5) {
+ guc_fw->path = CML_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = CML_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = CML_GUC_FW_MINOR;
+ } else {
+ guc_fw->path = KBL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
+ }
+ } else if (IS_KABYLAKE(i915)) {
guc_fw->path = KBL_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
--
2.21.0
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Remove presumption of RCS0
On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote:
> We now track features correctly instead of probing i915->engine[RCS0]
> which is much more flexible and avoids any nasty surprises.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index df5932f5f578..bdf279fa3b2e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -448,12 +448,6 @@ int intel_engines_init_mmio(struct
> drm_i915_private *i915)
> if (WARN_ON(mask != engine_mask))
> device_info->engine_mask = mask;
>
> - /* We always presume we have at least RCS available for later
> probing */
> - if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
> - err = -ENODEV;
> - goto cleanup;
> - }
> -
Just going by the series here, we have quite a few other place we are
touching RCS0 specifically during driver load. Do we really want to get
rid of this? Or is there an alternative if RCS0 isn't present for some
reason?
Thanks,
Stuart
> RUNTIME_INFO(i915)->num_engines = hweight32(mask);
>
> intel_gt_check_and_clear_faults(&i915->gt);
smime.p7s
Description: S/MIME cryptographic signature
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Apply RCS workarounds to the render class
On Fri, 2019-07-05 at 13:43 +0100, Chris Wilson wrote: > Treat all render engines to the RCS workarounds, simply to avoid > using > engine->id when we are trying to think in terms of classes. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index d7da094170be..9e069286d3ce 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1354,7 +1354,7 @@ engine_init_workarounds(struct intel_engine_cs > *engine, struct i915_wa_list *wal > if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8)) > return; > > - if (engine->id == RCS0) > + if (engine->class == RENDER_CLASS) Makes sense. Reviewed-by: Stuart Summers > rcs_engine_wa_init(engine, wal); > else > xcs_engine_wa_init(engine, wal); smime.p7s Description: S/MIME cryptographic signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/28] drm/i915/tgl: Add TRANSCODER_A_VDSC power domain
On Mon, Jul 01, 2019 at 08:32:59PM +0300, Ville Syrjälä wrote:
On Fri, Jun 28, 2019 at 09:31:04AM -0700, Lucas De Marchi wrote:
On Fri, Jun 28, 2019 at 12:55:17PM +0300, Ville Syrjälä wrote:
>On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
>> From: José Roberto de Souza
>>
>> On TGL the special EDP transcoder is gone and it should be handled by
>> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
>> distinction clear and update vdsc code path.
>>
>> Cc: Imre Deak
>> Signed-off-by: José Roberto de Souza
>> Signed-off-by: Lucas De Marchi
>> ---
>> drivers/gpu/drm/i915/display/intel_display_power.c | 2 ++
>> drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 11 ---
>> 3 files changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 0c7d4a363deb..15582841fefc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -58,6 +58,8 @@ intel_display_power_domain_str(struct drm_i915_private
*i915,
>>return "TRANSCODER_EDP";
>>case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
>>return "TRANSCODER_EDP_VDSC";
>> + case POWER_DOMAIN_TRANSCODER_A_VDSC:
>> + return "TRANSCODER_A_VDSC";
>>case POWER_DOMAIN_TRANSCODER_DSI_A:
>>return "TRANSCODER_DSI_A";
>>case POWER_DOMAIN_TRANSCODER_DSI_C:
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index 79262a5bceb4..7761b493608a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -29,6 +29,7 @@ enum intel_display_power_domain {
>>POWER_DOMAIN_TRANSCODER_D,
>>POWER_DOMAIN_TRANSCODER_EDP,
>>POWER_DOMAIN_TRANSCODER_EDP_VDSC,
>> + POWER_DOMAIN_TRANSCODER_A_VDSC,
>
>Two power domains for essentially the same thing seems a bit wasteful.
just reuse the name then?
and on gen12+ check for TRANSCODER_A like below?
That was my initial idea yes. In theory it would be nice to have fully
abstracted power domains but that would lead to a lot of bits getting
used. I suspect we might have to switch to using the kernel bitmask
stuff in that case. Not sure how many bits we have free ATM.
we are currently using 45 and with TGL we will jump to 60. 4 more until
we have to swap out that logic in favor of bitmap.h
Lucas De Marchi
Lucas De Marchi
>
>>POWER_DOMAIN_TRANSCODER_DSI_A,
>>POWER_DOMAIN_TRANSCODER_DSI_C,
>>POWER_DOMAIN_PORT_DDI_A_LANES,
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index ffec807b8960..0c75b408d6ba 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -459,16 +459,21 @@ int intel_dp_compute_dsc_params(struct intel_dp
*intel_dp,
>> enum intel_display_power_domain
>> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
>> {
>> + struct drm_i915_private *dev_priv =
to_i915(crtc_state->base.state->dev);
>>enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>
>>/*
>> - * On ICL VDSC/joining for eDP transcoder uses a separate power well
PW2
>> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
>> + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate power
well
>> + * PW2. This requires
>> + * POWER_DOMAIN_TRANSCODER_EDP_VDSC/POWER_DOMAIN_TRANSCODER_A_VDSC
power
>> + * domain.
>> * For any other transcoder, VDSC/joining uses the power well
associated
>> * with the pipe/transcoder in use. Hence another reference on the
>> * transcoder power domain will suffice.
>> */
>> - if (cpu_transcoder == TRANSCODER_EDP)
>> + if (INTEL_GEN(dev_priv) >= 12 && cpu_transcoder == TRANSCODER_A)
>> + return POWER_DOMAIN_TRANSCODER_A_VDSC;
>> + else if (cpu_transcoder == TRANSCODER_EDP)
>>return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
>>else
>>return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>> --
>> 2.21.0
>>
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>
>--
>Ville Syrjälä
>Intel
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plane cdclk requirements and fp16 for gen4+
== Series Details == Series: drm/i915: Plane cdclk requirements and fp16 for gen4+ URL : https://patchwork.freedesktop.org/series/63373/ State : success == Summary == CI Bug Log - changes from CI_DRM_6429_full -> Patchwork_13562_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13562_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: [PASS][1] -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-kbl7/igt@i915_pm_rc6_reside...@rc6-accuracy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-kbl7/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_atomic_transition@plane-all-transition-nonblocking: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb8/igt@kms_atomic_transit...@plane-all-transition-nonblocking.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-iclb7/igt@kms_atomic_transit...@plane-all-transition-nonblocking.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-kbl1/igt@kms_cursor_...@pipe-c-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-kbl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html * igt@prime_busy@hang-render: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-hsw8/igt@prime_b...@hang-render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-hsw5/igt@prime_b...@hang-render.html Possible fixes * igt@kms_big_fb@linear-64bpp-rotate-180: - shard-apl: [SKIP][17] ([fdo#109271]) -> [PASS][18] +5 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-apl4/igt@kms_big...@linear-64bpp-rotate-180.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-apl7/igt@kms_big...@linear-64bpp-rotate-180.html - shard-glk: [SKIP][19] ([fdo#109271]) -> [PASS][20] +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-glk3/igt@kms_big...@linear-64bpp-rotate-180.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-glk4/igt@kms_big...@linear-64bpp-rotate-180.html - shard-hsw: [SKIP][21] ([fdo#109271]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-hsw4/igt@kms_big...@linear-64bpp-rotate-180.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-hsw1/igt@kms_big...@linear-64bpp-rotate-180.html * igt@kms_big_fb@x-tiled-64bpp-rotate-0: - shard-snb: [SKIP][23] ([fdo#109271]) -> [PASS][24] +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-snb6/igt@kms_big...@x-tiled-64bpp-rotate-0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13562/shard-snb2/igt@kms_big...@x-tiled-64bpp-rotate-0.html * igt@kms_big_fb@x
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hdcp: debug logs for sink related failures
== Series Details == Series: drm/i915/hdcp: debug logs for sink related failures URL : https://patchwork.freedesktop.org/series/63406/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13571 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/ Known issues Here are the changes found in Patchwork_13571 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-small-bo-tiledx: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html * igt@i915_module_load@reload: - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-blb-e6850/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_selftest@live_hangcheck: - fi-kbl-x1275: [PASS][5] -> [DMESG-WARN][6] ([fdo#111074]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@prime_busy@basic-wait-before-default: - fi-icl-dsi: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-dsi/igt@prime_b...@basic-wait-before-default.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/fi-icl-dsi/igt@prime_b...@basic-wait-before-default.html Possible fixes * igt@gem_close_race@basic-process: - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@gem_close_r...@basic-process.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/fi-icl-u3/igt@gem_close_r...@basic-process.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][13] ([fdo#107713] / [fdo#108569]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#111074]: https://bugs.freedesktop.org/show_bug.cgi?id=111074 Participating hosts (53 -> 47) -- Additional (1): fi-pnv-d510 Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6431 -> Patchwork_13571 CI_DRM_6431: 9a40fb28e45261f2fc44a9b271c19faf1f071138 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5090: c6c75e11175baeb6b984e0cc13c6fbe2863a0794 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13571: 18d32230ff2fa44ef5ab269d17fd8333eb290452 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 18d32230ff2f drm/i915/hdcp: debug logs for sink related failures == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13571/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/l
[Intel-gfx] ✓ Fi.CI.BAT: success for HDCP2.2 Phase II (rev11)
== Series Details ==
Series: HDCP2.2 Phase II (rev11)
URL : https://patchwork.freedesktop.org/series/57232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13570
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/
Known issues
Here are the changes found in Patchwork_13570 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#109100])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-blb-e6850/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] /
[fdo#108569])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_close_race@basic-process:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@gem_close_r...@basic-process.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/fi-icl-u3/igt@gem_close_r...@basic-process.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#109485]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (53 -> 46)
--
Additional (1): fi-pnv-d510
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bwr-2160 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6431 -> Patchwork_13570
CI_DRM_6431: 9a40fb28e45261f2fc44a9b271c19faf1f071138 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5090: c6c75e11175baeb6b984e0cc13c6fbe2863a0794 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13570: 584ff79d12eacd58cfd07e6b06351e21464c3fd5 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13570/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/g
Re: [Intel-gfx] use exact allocation for dma coherent memory
On Tue, Jul 02, 2019 at 11:48:44AM +0200, Arend Van Spriel wrote: > You made me look ;-) Actually not touching my drivers so I'm off the hook. > However, I was wondering if drivers could know so I decided to look into > the DMA-API.txt documentation which currently states: > > """ > The flag parameter (dma_alloc_coherent() only) allows the caller to > specify the ``GFP_`` flags (see kmalloc()) for the allocation (the > implementation may choose to ignore flags that affect the location of > the returned memory, like GFP_DMA). > """ > > I do expect you are going to change that description as well now that you > are going to issue a warning on __GFP_COMP. Maybe include that in patch > 15/16 where you introduce that warning. Yes, that description needs an updated, even without this series. I'll make sure it is more clear. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/hdcp: debug logs for sink related failures
Adding few more debug logs to identify the sink specific HDCP failures
along with a out of mem failure.
v2:
Capturing the Bug and a-b
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110991
Signed-off-by: Ramalingam C
cc: Daniel Vetter
Acked-by: Daniel Vetter
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index bc3a94d491c4..a78139f9e847 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -523,12 +523,16 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
* authentication.
*/
num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
- if (num_downstream == 0)
+ if (num_downstream == 0) {
+ DRM_DEBUG_KMS("Repeater with zero downstream devices\n");
return -EINVAL;
+ }
ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL);
- if (!ksv_fifo)
+ if (!ksv_fifo) {
+ DRM_DEBUG_KMS("Out of mem: ksv_fifo\n");
return -ENOMEM;
+ }
ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
if (ret)
@@ -1206,8 +1210,10 @@ static int hdcp2_authentication_key_exchange(struct
intel_connector *connector)
if (ret < 0)
return ret;
- if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL)
+ if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) {
+ DRM_DEBUG_KMS("cert.rx_caps dont claim HDCP2.2\n");
return -EINVAL;
+ }
hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]);
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP2.2 Phase II (rev11)
== Series Details ==
Series: HDCP2.2 Phase II (rev11)
URL : https://patchwork.freedesktop.org/series/57232/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4850c38d571b drm: Add Content protection type property
-:123: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#123: FILE: drivers/gpu/drm/drm_hdcp.c:351:
+};
+DRM_ENUM_NAME_FN(drm_get_hdcp_content_type_name,
-:168: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#168: FILE: drivers/gpu/drm/drm_hdcp.c:404:
+ prop = drm_property_create_enum(dev, 0, "HDCP Content Type",
+ drm_hdcp_content_type_enum_list,
-:169: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#169: FILE: drivers/gpu/drm/drm_hdcp.c:405:
+ ARRAY_SIZE(
total: 0 errors, 0 warnings, 3 checks, 182 lines checked
3bc2f2d69357 drm/i915: Attach content type property
80479a8101ac drm: uevent for connector status change
d37bd325f08f drm/hdcp: update content protection property with uevent
-:99: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#99: FILE: drivers/gpu/drm/drm_hdcp.c:448:
+ drm_sysfs_connector_status_event(connector,
+dev->mode_config.content_protection_property);
total: 0 errors, 0 warnings, 1 checks, 72 lines checked
ee2bd3463203 drm/i915: update the hdcp state with uevent
584ff79d12ea drm/hdcp: reference for srm file format
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 6/6] drm/hdcp: reference for srm file format
In the kernel documentation, HDCP specifications links are shared as a reference for SRM table format. Signed-off-by: Ramalingam C --- drivers/gpu/drm/drm_hdcp.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c index 77433ee3d652..803bf8283b83 100644 --- a/drivers/gpu/drm/drm_hdcp.c +++ b/drivers/gpu/drm/drm_hdcp.c @@ -271,6 +271,13 @@ static void drm_hdcp_request_srm(struct drm_device *drm_dev) * * SRM should be presented in the name of "display_hdcp_srm.bin". * + * Format of the SRM table that userspace needs to write into the binary file + * is defined at + * 1. Renewability chapter on 55th page of HDCP 1.4 specification + * https://www.digital-cp.com/sites/default/files/specifications/HDCP%20Specification%20Rev1_4_Secure.pdf + * 2. Renewability chapter on 63rd page of HDCP 2.2 specification + * https://www.digital-cp.com/sites/default/files/specifications/HDCP%20on%20HDMI%20Specification%20Rev2_2_Final1.pdf + * * Returns: * TRUE on any of the KSV is revoked, else FALSE. */ -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 5/6] drm/i915: update the hdcp state with uevent
drm function to update the content protection property state and to
generate a uevent is invoked from the intel hdcp property work.
Hence whenever kernel changes the property state, userspace will be
updated with a uevent.
Need a ACK for uevent generating uAPI from userspace.
v2:
state update is moved into drm function [daniel]
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 4580af57bddb..e56969ebdd25 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -865,7 +865,6 @@ static void intel_hdcp_prop_work(struct work_struct *work)
prop_work);
struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
struct drm_device *dev = connector->base.dev;
- struct drm_connector_state *state;
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
mutex_lock(&hdcp->mutex);
@@ -875,10 +874,9 @@ static void intel_hdcp_prop_work(struct work_struct *work)
* those to UNDESIRED is handled by core. If value == UNDESIRED,
* we're running just after hdcp has been disabled, so just exit
*/
- if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
- state = connector->base.state;
- state->content_protection = hdcp->value;
- }
+ if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
+ drm_hdcp_update_content_protection(&connector->base,
+ hdcp->value);
mutex_unlock(&hdcp->mutex);
drm_modeset_unlock(&dev->mode_config.connection_mutex);
--
2.19.1
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[Intel-gfx] [PATCH v9 4/6] drm/hdcp: update content protection property with uevent
drm function is defined and exported to update a connector's
content protection property state and to generate a uevent along
with it.
Need ACK for the uevent from userspace consumer.
v2:
Update only when state is different from old one.
v3:
KDoc is added [Daniel]
v4:
KDoc is extended bit more [pekka]
v5:
Uevent usage is documented at kdoc of "Content Protection" also
[pekka]
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_connector.c | 17 +
drivers/gpu/drm/drm_hdcp.c | 34 +
include/drm/drm_hdcp.h | 2 ++
3 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 732f6645643d..6de906ef10b3 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -947,10 +947,19 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
* - If the state is DESIRED, kernel should attempt to re-authenticate the
* link whenever possible. This includes across disable/enable, dpms,
* hotplug, downstream device changes, link status failures, etc..
- * - Userspace is responsible for polling the property to determine when
- * the value transitions from ENABLED to DESIRED. This signifies the link
- * is no longer protected and userspace should take appropriate action
- * (whatever that might be).
+ * - Kernel sends uevent with the connector id and property id through
+ * @drm_hdcp_update_content_protection, upon below kernel triggered
+ * scenarios:
+ * DESIRED -> ENABLED (authentication success)
+ * ENABLED -> DESIRED (termination of authentication)
+ * - Please note no uevents for userspace triggered property state changes,
+ * which can't fail such as
+ * DESIRED/ENABLED -> UNDESIRED
+ * UNDESIRED -> DESIRED
+ * - Userspace is responsible for polling the property or listen to uevents
+ * to determine when the value transitions from ENABLED to DESIRED.
+ * This signifies the link is no longer protected and userspace should
+ * take appropriate action (whatever that might be).
*
* HDCP Content Type:
* This Enum property is used by the userspace to declare the content type
diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
index ce235fd1c844..77433ee3d652 100644
--- a/drivers/gpu/drm/drm_hdcp.c
+++ b/drivers/gpu/drm/drm_hdcp.c
@@ -374,6 +374,10 @@ DRM_ENUM_NAME_FN(drm_get_hdcp_content_type_name,
*
* The content protection will be set to
&drm_connector_state.content_protection
*
+ * When kernel triggered content protection state change like DESIRED->ENABLED
+ * and ENABLED->DESIRED, will use drm_hdcp_update_content_protection() to
update
+ * the content protection state of a connector.
+ *
* Returns:
* Zero on success, negative errno on failure.
*/
@@ -414,3 +418,33 @@ int drm_connector_attach_content_protection_property(
return 0;
}
EXPORT_SYMBOL(drm_connector_attach_content_protection_property);
+
+/**
+ * drm_hdcp_update_content_protection - Updates the content protection state
+ * of a connector
+ *
+ * @connector: drm_connector on which content protection state needs an update
+ * @val: New state of the content protection property
+ *
+ * This function can be used by display drivers, to update the kernel triggered
+ * content protection state changes of a drm_connector such as DESIRED->ENABLED
+ * and ENABLED->DESIRED. No uevent for DESIRED->UNDESIRED or
ENABLED->UNDESIRED,
+ * as userspace is triggering such state change and kernel performs it without
+ * fail.This function update the new state of the property into the connector's
+ * state and generate an uevent to notify the userspace.
+ */
+void drm_hdcp_update_content_protection(struct drm_connector *connector,
+ u64 val)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_connector_state *state = connector->state;
+
+ WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+ if (state->content_protection == val)
+ return;
+
+ state->content_protection = val;
+ drm_sysfs_connector_status_event(connector,
+dev->mode_config.content_protection_property);
+}
+EXPORT_SYMBOL(drm_hdcp_update_content_protection);
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 2970abdfaf12..dd864ac9ce85 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -292,4 +292,6 @@ bool drm_hdcp_check_ksvs_revoked(struct drm_device *dev,
u8 *ksvs, u32 ksv_count);
int drm_connector_attach_content_protection_property(
struct drm_connector *connector, bool hdcp_content_type);
+void drm_hdcp_update_content_protection(struct drm_connector *connector,
+
[Intel-gfx] [PATCH v9 3/6] drm: uevent for connector status change
DRM API for generating uevent for a status changes of connector's
property.
This uevent will have following details related to the status change:
HOTPLUG=1, CONNECTOR= and PROPERTY=
Need ACK from this uevent from userspace consumer.
v2:
Minor fixes at KDoc comments [Daniel]
v3:
Check the property is really attached with connector [Daniel]
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_sysfs.c | 35 +++
include/drm/drm_sysfs.h | 5 -
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index ad10810bc972..d13a77057045 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -26,6 +26,7 @@
#include
#include "drm_internal.h"
+#include "drm_crtc_internal.h"
#define to_drm_minor(d) dev_get_drvdata(d)
#define to_drm_connector(d) dev_get_drvdata(d)
@@ -325,6 +326,9 @@ void drm_sysfs_lease_event(struct drm_device *dev)
* Send a uevent for the DRM device specified by @dev. Currently we only
* set HOTPLUG=1 in the uevent environment, but this could be expanded to
* deal with other types of events.
+ *
+ * Any new uapi should be using the drm_sysfs_connector_status_event()
+ * for uevents on connector status change.
*/
void drm_sysfs_hotplug_event(struct drm_device *dev)
{
@@ -337,6 +341,37 @@ void drm_sysfs_hotplug_event(struct drm_device *dev)
}
EXPORT_SYMBOL(drm_sysfs_hotplug_event);
+/**
+ * drm_sysfs_connector_status_event - generate a DRM uevent for connector
+ * property status change
+ * @connector: connector on which property status changed
+ * @property: connector property whoes status changed.
+ *
+ * Send a uevent for the DRM device specified by @dev. Currently we
+ * set HOTPLUG=1 and connector id along with the attached property id
+ * related to the status change.
+ */
+void drm_sysfs_connector_status_event(struct drm_connector *connector,
+ struct drm_property *property)
+{
+ struct drm_device *dev = connector->dev;
+ char hotplug_str[] = "HOTPLUG=1", conn_id[30], prop_id[30];
+ char *envp[4] = { hotplug_str, conn_id, prop_id, NULL };
+
+ WARN_ON(!drm_mode_obj_find_prop_id(&connector->base,
+ property->base.id));
+
+ snprintf(conn_id, ARRAY_SIZE(conn_id),
+"CONNECTOR=%u", connector->base.id);
+ snprintf(prop_id, ARRAY_SIZE(prop_id),
+"PROPERTY=%u", property->base.id);
+
+ DRM_DEBUG("generating connector status event\n");
+
+ kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp);
+}
+EXPORT_SYMBOL(drm_sysfs_connector_status_event);
+
static void drm_sysfs_release(struct device *dev)
{
kfree(dev);
diff --git a/include/drm/drm_sysfs.h b/include/drm/drm_sysfs.h
index 4f311e836cdc..d454ef617b2c 100644
--- a/include/drm/drm_sysfs.h
+++ b/include/drm/drm_sysfs.h
@@ -4,10 +4,13 @@
struct drm_device;
struct device;
+struct drm_connector;
+struct drm_property;
int drm_class_device_register(struct device *dev);
void drm_class_device_unregister(struct device *dev);
void drm_sysfs_hotplug_event(struct drm_device *dev);
-
+void drm_sysfs_connector_status_event(struct drm_connector *connector,
+ struct drm_property *property);
#endif
--
2.19.1
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[Intel-gfx] [PATCH v9 0/6] HDCP2.2 Phase II
Adding the uAPI support for the HDCP content type is the main focus here. Along with that uevent is implemented for the "Content Protection" state change that got triggered by kernel. v9: KDoc improvements [pekka] Ramalingam C (6): drm: Add Content protection type property drm/i915: Attach content type property drm: uevent for connector status change drm/hdcp: update content protection property with uevent drm/i915: update the hdcp state with uevent drm/hdcp: reference for srm file format drivers/gpu/drm/drm_atomic_uapi.c | 4 ++ drivers/gpu/drm/drm_connector.c | 56 +++-- drivers/gpu/drm/drm_hdcp.c| 77 ++- drivers/gpu/drm/drm_sysfs.c | 35 +++ drivers/gpu/drm/i915/display/intel_ddi.c | 39 ++-- drivers/gpu/drm/i915/display/intel_hdcp.c | 53 ++-- drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- include/drm/drm_connector.h | 7 +++ include/drm/drm_hdcp.h| 4 +- include/drm/drm_mode_config.h | 6 ++ include/drm/drm_sysfs.h | 5 +- include/uapi/drm/drm_mode.h | 4 ++ 12 files changed, 258 insertions(+), 34 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 1/6] drm: Add Content protection type property
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on any HDCP protected display wires.
But Type 1 content can be rendered only on HDCP2.2 protected paths.
So when a userspace sets this property to Type 1 and starts the HDCP
enable, kernel will honour it only if HDCP2.2 authentication is through
for type 1. Else HDCP enable will be failed.
Need ACK for this new conenctor property from userspace consumer.
v2:
cp_content_type is replaced with content_protection_type [daniel]
check at atomic_set_property is removed [Maarten]
v3:
%s/content_protection_type/hdcp_content_type [Pekka]
v4:
property is created for the first requested connector and then reused.
[Danvet]
v5:
kernel doc nits addressed [Daniel]
Rebased as part of patch reordering.
v6:
Kernel docs are modified [pekka]
v7:
More details in Kernel docs. [pekka]
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 +++
drivers/gpu/drm/drm_connector.c | 39 +++
drivers/gpu/drm/drm_hdcp.c| 36 -
drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++-
include/drm/drm_connector.h | 7
include/drm/drm_hdcp.h| 2 +-
include/drm/drm_mode_config.h | 6
include/uapi/drm/drm_mode.h | 4 +++
8 files changed, 99 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index abe38bdf85ae..19ae119f1a5d 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -747,6 +747,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
return -EINVAL;
}
state->content_protection = val;
+ } else if (property == config->hdcp_content_type_property) {
+ state->hdcp_content_type = val;
} else if (property == connector->colorspace_property) {
state->colorspace = val;
} else if (property == config->writeback_fb_id_property) {
@@ -831,6 +833,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
state->hdr_output_metadata->base.id : 0;
} else if (property == config->content_protection_property) {
*val = state->content_protection;
+ } else if (property == config->hdcp_content_type_property) {
+ *val = state->hdcp_content_type;
} else if (property == config->writeback_fb_id_property) {
/* Writeback framebuffer is one-shot, write and forget */
*val = 0;
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 068d4b05f1be..732f6645643d 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -952,6 +952,45 @@ static const struct drm_prop_enum_list hdmi_colorspaces[]
= {
* is no longer protected and userspace should take appropriate action
* (whatever that might be).
*
+ * HDCP Content Type:
+ * This Enum property is used by the userspace to declare the content type
+ * of the display stream, to kernel. Here display stream stands for any
+ * display content that userspace intended to render with HDCP encryption.
+ *
+ * Content Type of a stream is decided by the owner of the stream, as
+ * "HDCP Type0" or "HDCP Type1".
+ *
+ * The value of the property can be one the below:
+ * - "HDCP Type0": DRM_MODE_HDCP_CONTENT_TYPE0 = 0
+ * - "HDCP Type1": DRM_MODE_HDCP_CONTENT_TYPE1 = 1
+ *
+ * When kernel starts the HDCP authentication upon the "DESIRED" state of
+ * the "Content Protection", it refers the "HDCP Content Type" property
+ * state. And perform the HDCP authentication with the display sink for
+ * the content type mentioned by "HDCP Content Type".
+ *
+ * Stream classified as HDCP Type0 can be transmitted on a link which is
+ * encrypted with HDCP 1.4 or higher versions of HDCP(i.e HDCP2.2
+ * and more).
+ *
+ * Streams classified as HDCP Type1 can be transmitted on a link which is
+ * encrypted only with HDCP 2.2. In future, HDCP versions >2.2 also might
+ * support Type1 based on their spec.
+ *
+ * HDCP2.2 authentication protocol itself takes the "Content Type" as a
+ * parameter, which is a input for the DP HDCP2.2 encryption algo.
+ *
+ * Note that the HDCP Content Type property is introduced at HDCP 2.2, and
+ * defaults to type 0. It is only exposed by drivers supporting HDCP 2.2.
+ * Based on how next versions of HDCP specs are defined content Type could
+ * be used for higher versions too.
+ *
+ * If content type is changed
[Intel-gfx] [PATCH v9 2/6] drm/i915: Attach content type property
Attaches the content type property for HDCP2.2 capable connectors.
Implements the update of content type from property and apply the
restriction on HDCP version selection.
Need ACK for content type property from userspace consumer.
v2:
s/cp_content_type/content_protection_type [daniel]
disable at hdcp_atomic_check to avoid check at atomic_set_property
[Maarten]
v3:
s/content_protection_type/hdcp_content_type [Pekka]
v4:
hdcp disable incase of type change is moved into commit [daniel].
v5:
Simplified the Type change procedure. [Daniel]
v6:
Type change with UNDESIRED state is ignored.
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/display/intel_ddi.c | 39
drivers/gpu/drm/i915/display/intel_hdcp.c | 43 +++
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
3 files changed, 62 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4172595c8d8..862907393a6d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3514,7 +3514,8 @@ static void intel_enable_ddi(struct intel_encoder
*encoder,
/* Enable hdcp if it's desired */
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
+ intel_hdcp_enable(to_intel_connector(conn_state->connector),
+ (u8)conn_state->hdcp_content_type);
}
static void intel_disable_ddi_dp(struct intel_encoder *encoder,
@@ -3583,15 +3584,41 @@ static void intel_ddi_update_pipe(struct intel_encoder
*encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ bool content_protection_type_changed =
+ (conn_state->hdcp_content_type != hdcp->content_type &&
+conn_state->content_protection !=
+DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
+
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
+ /*
+* During the HDCP encryption session if Type change is requested,
+* disable the HDCP and reenable it with new TYPE value.
+*/
if (conn_state->content_protection ==
- DRM_MODE_CONTENT_PROTECTION_DESIRED)
- intel_hdcp_enable(to_intel_connector(conn_state->connector));
- else if (conn_state->content_protection ==
-DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
- intel_hdcp_disable(to_intel_connector(conn_state->connector));
+ DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
+ content_protection_type_changed)
+ intel_hdcp_disable(connector);
+
+ /*
+* Mark the hdcp state as DESIRED after the hdcp disable of type
+* change procedure.
+*/
+ if (content_protection_type_changed) {
+ mutex_lock(&hdcp->mutex);
+ hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ schedule_work(&hdcp->prop_work);
+ mutex_unlock(&hdcp->mutex);
+ }
+
+ if (conn_state->content_protection ==
+ DRM_MODE_CONTENT_PROTECTION_DESIRED ||
+ content_protection_type_changed)
+ intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
}
static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 2a4d10952b74..4580af57bddb 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1748,14 +1748,15 @@ static const struct component_ops
i915_hdcp_component_ops = {
.unbind = i915_hdcp_component_unbind,
};
-static inline int initialize_hdcp_port_data(struct intel_connector *connector)
+static inline int initialize_hdcp_port_data(struct intel_connector *connector,
+ const struct intel_hdcp_shim *shim)
{
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
data->port = connector->encoder->port;
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
- data->protocol = (u8)hdcp->shim->protocol;
+ data->protocol = (u8)shim->protocol;
data->k = 1;
if (!data->streams)
@@ -1805,12 +1806,13 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector)
+static vo
[Intel-gfx] ✓ Fi.CI.BAT: success for Modular FIA (rev2)
== Series Details ==
Series: Modular FIA (rev2)
URL : https://patchwork.freedesktop.org/series/63175/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13569
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/
Known issues
Here are the changes found in Patchwork_13569 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][1] -> [INCOMPLETE][2] ([fdo#111050])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/fi-skl-iommu/igt@i915_selftest@live_contexts.html
Possible fixes
* igt@gem_close_race@basic-process:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@gem_close_r...@basic-process.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/fi-icl-u3/igt@gem_close_r...@basic-process.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][5] ([fdo#107713] / [fdo#108569]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (53 -> 47)
--
Additional (1): fi-pnv-d510
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6431 -> Patchwork_13569
CI_DRM_6431: 9a40fb28e45261f2fc44a9b271c19faf1f071138 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5090: c6c75e11175baeb6b984e0cc13c6fbe2863a0794 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13569: 4d0275413be523094414d03d7f2f7026955b0bfe @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
4d0275413be5 drm/i915: Add modular FIA
9718e39adc29 drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c
16541e8db1fc drm/i915: fix include order in intel_tc.*
29a4bcb3052b drm/i915: make new intel_tc.c use uncore accessors
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/oa: Reconfigure contexts on the fly (rev3)
== Series Details == Series: series starting with [1/2] drm/i915/oa: Reconfigure contexts on the fly (rev3) URL : https://patchwork.freedesktop.org/series/63362/ State : success == Summary == CI Bug Log - changes from CI_DRM_6429_full -> Patchwork_13561_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13561_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-apl7/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: [PASS][3] -> [SKIP][4] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-kbl7/igt@i915_pm_rc6_reside...@rc6-accuracy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-kbl7/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#107807]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-skl9/igt@i915_pm_...@system-suspend-execbuf.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-skl3/igt@i915_pm_...@system-suspend-execbuf.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-skl6/igt@kms_f...@flip-vs-expired-vblank.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-skl10/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-kbl3/igt@kms_frontbuffer_track...@fbc-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-kbl1/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html Possible fixes * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][15] ([fdo#110854]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb3/igt@gem_exec_balan...@smoke.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-iclb4/igt@gem_exec_balan...@smoke.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-glk: [INCOMPLETE][17] ([fdo#103359] / [k.org#198133]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-glk2/igt@kms_f...@flip-vs-suspend-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-glk6/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-apl: [DMESG-WARN][19] ([fdo#108566]) -> [PASS][20] +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-apl2/igt@kms_f...@flip-vs-suspend-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-apl5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [FAIL][21] ([fdo#103167]) -> [PASS][22] +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-skl: [INCOMPLETE][23] ([fdo#104108] / [fdo#106978]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-skl7/igt@kms_frontbuffer_track...@psr-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13561/shard-skl3/igt@kms_frontbuffer_track...@psr
[Intel-gfx] [PATCH v2 1/4] drm/i915: make new intel_tc.c use uncore accessors
Let's make the just created intel_tc.c already follow the trend of using
i915 instead of dev_priv and calling the intel_uncore_*() functions.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_tc.c | 57 ++---
1 file changed, 31 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 53103a9aa8a7..1a9dd32fb0a5 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -24,11 +24,12 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = &i915->uncore;
u32 lane_mask;
- lane_mask = I915_READ(PORT_TX_DFLEXDPSP);
+ lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
WARN_ON(lane_mask == 0x);
@@ -38,7 +39,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port
*dig_port)
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
intel_wakeref_t wakeref;
u32 lane_mask;
@@ -46,7 +47,7 @@ int intel_tc_port_fia_max_lane_count(struct
intel_digital_port *dig_port)
return 4;
lane_mask = 0;
- with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
lane_mask = intel_tc_port_get_lane_mask(dig_port);
switch (lane_mask) {
@@ -89,12 +90,13 @@ static void tc_port_fixup_legacy_flag(struct
intel_digital_port *dig_port,
static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = &i915->uncore;
u32 mask = 0;
u32 val;
- val = I915_READ(PORT_TX_DFLEXDPSP);
+ val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
if (val == 0x) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
@@ -107,7 +109,7 @@ static u32 tc_port_live_status_mask(struct
intel_digital_port *dig_port)
if (val & TC_LIVE_STATE_TC(tc_port))
mask |= BIT(TC_PORT_DP_ALT);
- if (I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
+ if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
mask |= BIT(TC_PORT_LEGACY);
/* The sink can be connected only in a single mode. */
@@ -119,11 +121,12 @@ static u32 tc_port_live_status_mask(struct
intel_digital_port *dig_port)
static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = I915_READ(PORT_TX_DFLEXDPPMS);
+ val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
if (val == 0x) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
dig_port->tc_port_name);
@@ -136,11 +139,12 @@ static bool icl_tc_phy_status_complete(struct
intel_digital_port *dig_port)
static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = I915_READ(PORT_TX_DFLEXDPCSSS);
+ val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
if (val == 0x) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to
%s\n",
dig_port->tc_port_name,
@@ -153,7 +157,7 @@ static bool icl_tc_phy
[Intel-gfx] [PATCH v2 3/4] drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c
PORT_TX_DFLEXDPMLE1 is a FIA register so move it to intel_tc.c where we
access other FIA registers. In Tiger Lake we have multiple/modular FIAs
so it makes sense to start moving all access to their registers to a
common place.
While at it, make it clear that we will only ever call this function
for ports with TC phy. Previously we were relying on tc_mode being
TC_PORT_TBT_ALT for combo phy ports. However it's confusing since in
this same function we have checks for is_tc_port. Also, if we manage to
make each phy access only their own field, we may in future add them as
a union inside intel_digital_port.
v2: Fix coding style while moving the code
Signed-off-by: Lucas De Marchi
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 49
drivers/gpu/drm/i915/display/intel_tc.c | 33
drivers/gpu/drm/i915/display/intel_tc.h | 2 +
3 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 30e48609db1d..ad638e7f27bb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3594,37 +3594,6 @@ static void intel_ddi_update_pipe(struct intel_encoder
*encoder,
intel_hdcp_disable(to_intel_connector(conn_state->connector));
}
-static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
-const struct intel_crtc_state
*pipe_config,
-enum port port)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
- u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
- bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
-
- WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
-
- val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
- switch (pipe_config->lane_count) {
- case 1:
- val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
- DFLEXDPMLE1_DPMLETC_ML0(tc_port);
- break;
- case 2:
- val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
- DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
- break;
- case 4:
- val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
- break;
- default:
- MISSING_CASE(pipe_config->lane_count);
- }
- I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
-}
-
static void
intel_ddi_update_prepare(struct intel_atomic_state *state,
struct intel_encoder *encoder,
@@ -3657,7 +3626,6 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
- enum port port = encoder->port;
if (is_tc_port)
intel_tc_port_get_link(dig_port, crtc_state->lane_count);
@@ -3666,18 +3634,15 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
- if (IS_GEN9_LP(dev_priv))
+ if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
+ /*
+* Program the lane count for static/dynamic connections on
+* Type-C ports. Skip this step for TBT.
+*/
+ intel_tc_port_set_fia_lane_count(dig_port,
crtc_state->lane_count);
+ else if (IS_GEN9_LP(dev_priv))
bxt_ddi_phy_set_lane_optim_mask(encoder,
crtc_state->lane_lat_optim_mask);
-
- /*
-* Program the lane count for static/dynamic connections on Type-C
ports.
-* Skip this step for TBT.
-*/
- if (dig_port->tc_mode == TC_PORT_TBT_ALT)
- return;
-
- intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 0c969f6fd714..f44ee4bfe7c8 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -67,6 +67,39 @@ int intel_tc_port_fia_max_lane_count(struct
intel_digital_port *dig_port)
}
}
+void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
+ int required_lanes)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ struct i
[Intel-gfx] [PATCH v2 0/4] Modular FIA
v2: - Fix sparse warning - Do not try to make header self-contained - Fix coding style while moving code Anusha Srivatsa (1): drm/i915: Add modular FIA Lucas De Marchi (3): drm/i915: make new intel_tc.c use uncore accessors drm/i915: fix include order in intel_tc.* drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c drivers/gpu/drm/i915/display/intel_ddi.c | 49 ++--- drivers/gpu/drm/i915/display/intel_tc.c | 125 ++- drivers/gpu/drm/i915/display/intel_tc.h | 7 +- drivers/gpu/drm/i915/i915_reg.h | 13 ++- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + 6 files changed, 121 insertions(+), 75 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/4] drm/i915: fix include order in intel_tc.*
Make intel_tc.h the first include so we guarantee it's self-contained. Sort the rest. Same principle applies for includes in the header. v2: don't make intel_tc.h be the first include Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_tc.c | 2 +- drivers/gpu/drm/i915/display/intel_tc.h | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 1a9dd32fb0a5..0c969f6fd714 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -3,9 +3,9 @@ * Copyright © 2019 Intel Corporation */ +#include "i915_drv.h" #include "intel_display.h" #include "intel_dp_mst.h" -#include "i915_drv.h" #include "intel_tc.h" static const char *tc_port_mode_name(enum tc_port_mode mode) diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h index 0d8411d4a91d..45ae30537b78 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.h +++ b/drivers/gpu/drm/i915/display/intel_tc.h @@ -6,10 +6,11 @@ #ifndef __INTEL_TC_H__ #define __INTEL_TC_H__ -#include -#include #include "intel_drv.h" +#include +#include + bool intel_tc_port_connected(struct intel_digital_port *dig_port); u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port); int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port); -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 4/4] drm/i915: Add modular FIA
From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
then Display Driver will access the additional instances of
FIA based on pre-assigned offset in GTTMADDR space.
Each Modular FIA instance has its own IOSF Sideband Port ID
and it houses only 2 Type-C Port. In SOC that has more than
two Type-C Ports, there are multiple instances of Modular FIA.
Gunit will need to use different destination ID when it access
different pair of Type-C Port.
The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
Modular FIA is used in the SOC, this register bit exists in all the
instances of Modular FIA. IOM FW is required to program only the MF bit
in first FIA instance that houses the Type-C Port 0 and Port 1, for
Display Driver to read from.
v2 (Lucas):
- Move all accesses to FIA to be contained in intel_tc.c, along with
display_fia that is now called tc_phy_fia
- Save the fia instance number on intel_digital_port, so we don't have
to query if modular FIA is used on every access
v3 (Lucas):
- Make function static
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_tc.c | 49
drivers/gpu/drm/i915/i915_reg.h | 13 +--
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index f44ee4bfe7c8..671261b55d11 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -8,6 +8,12 @@
#include "intel_dp_mst.h"
#include "intel_tc.h"
+enum phy_fia {
+ FIA1,
+ FIA2,
+ FIA3,
+};
+
static const char *tc_port_mode_name(enum tc_port_mode mode)
{
static const char * const names[] = {
@@ -22,6 +28,24 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
return names[mode];
}
+static bool has_modular_fia(struct drm_i915_private *i915)
+{
+ if (!INTEL_INFO(i915)->display.has_modular_fia)
+ return false;
+
+ return intel_uncore_read(&i915->uncore,
+PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
+}
+
+static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
+ enum tc_port tc_port)
+{
+ if (!has_modular_fia(i915))
+ return FIA1;
+
+ return tc_port / 2;
+}
+
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -29,7 +53,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port
*dig_port)
struct intel_uncore *uncore = &i915->uncore;
u32 lane_mask;
- lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ lane_mask = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
WARN_ON(lane_mask == 0x);
@@ -78,7 +103,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
switch (required_lanes) {
@@ -97,7 +123,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
MISSING_CASE(required_lanes);
}
- intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
+ intel_uncore_write(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
}
static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
@@ -129,7 +156,8 @@ static u32 tc_port_live_status_mask(struct
intel_digital_port *dig_port)
u32 mask = 0;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
if (val == 0x) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
@@ -159,7 +187,8 @@ static bool icl_tc_phy_status_complete(struct
intel_digital_port *dig_port)
struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
if (val == 0x) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
dig_port->tc_port_name);
@@ -177,7 +206,8 @@ static bool icl_tc_phy_set_safe_mode(struct
intel_digital_port *dig_port,
struct intel_uncore *un
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Try to fix encoder possible_clones/crtc
== Series Details ==
Series: drm: Try to fix encoder possible_clones/crtc
URL : https://patchwork.freedesktop.org/series/63399/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13568
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/
Known issues
Here are the changes found in Patchwork_13568 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-cpu-noreloc:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-dsi/igt@gem_exec_re...@basic-cpu-noreloc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/fi-icl-dsi/igt@gem_exec_re...@basic-cpu-noreloc.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_close_race@basic-process:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@gem_close_r...@basic-process.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/fi-icl-u3/igt@gem_close_r...@basic-process.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][7] ([fdo#107713] / [fdo#108569]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (53 -> 47)
--
Additional (1): fi-pnv-d510
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6431 -> Patchwork_13568
CI_DRM_6431: 9a40fb28e45261f2fc44a9b271c19faf1f071138 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5090: c6c75e11175baeb6b984e0cc13c6fbe2863a0794 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13568: 80085b69f7244160427fc81d76fb6f140c9df15a @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
80085b69f724 drm: Validate encoder->possible_crtcs
619bd5c1b429 drm: Validate encoder->possible_clones
a825a82859a4 drm/i915: s/crtc_mask/pipe_mask/
98e95fb67f51 drm/i915: Simplfy LVDS crtc_mask setup
dc94a4c35ced drm/i915: Clean up encoder->crtc_mask setup
eb3d8b1499b8 drm/i915: Fix DP-MST crtc_mask
4631a1ef7404 drm/i915: Populate possible_crtcs correctly
2289c1b60665 drm/i915: Polish possible_clones setup
7d83c6354420 drm/imx: Remove the bogus possible_clones setup
1b76c2b9729c drm/exynos: Use drm_encoder_mask()
88c7757629da drm/sti: Try to fix up the tvout possible clones
76460d1aa2b5 drm/sti: Remove pointless casts
42670e947cca drm/gma500: Sanitize possible_clones
ef3e94dd4ab1 drm: Include the encoder itself in possible_clones
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13568/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesk
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Reorder error cleanup for whitelist checking (rev2)
== Series Details == Series: drm/i915/selftests: Reorder error cleanup for whitelist checking (rev2) URL : https://patchwork.freedesktop.org/series/63394/ State : success == Summary == CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13567 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/ Known issues Here are the changes found in Patchwork_13567 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-dsi/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/fi-icl-dsi/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload: - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-blb-e6850/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_selftest@live_hangcheck: - fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#108569]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u2/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/fi-icl-u2/igt@i915_selftest@live_hangcheck.html - fi-kbl-7500u: [PASS][7] -> [DMESG-WARN][8] ([fdo#111074]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html Possible fixes * igt@gem_close_race@basic-process: - fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@gem_close_r...@basic-process.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/fi-icl-u3/igt@gem_close_r...@basic-process.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#111074]: https://bugs.freedesktop.org/show_bug.cgi?id=111074 Participating hosts (53 -> 47) -- Additional (1): fi-pnv-d510 Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6431 -> Patchwork_13567 CI_DRM_6431: 9a40fb28e45261f2fc44a9b271c19faf1f071138 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5090: c6c75e11175baeb6b984e0cc13c6fbe2863a0794 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13567: 60a471bdad329d5caa00fd144a75ad51abd533f7 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 60a471bdad32 drm/i915/selftests: Reorder error cleanup for whitelist checking == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13567/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Explicitly track active fw_domain timers (rev3)
== Series Details ==
Series: drm/i915: Explicitly track active fw_domain timers (rev3)
URL : https://patchwork.freedesktop.org/series/63331/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13566
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/
Known issues
Here are the changes found in Patchwork_13566 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-blb-e6850/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][3] -> [INCOMPLETE][4] ([fdo#111050])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-dsi: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@gem_close_race@basic-process:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@gem_close_r...@basic-process.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/fi-icl-u3/igt@gem_close_r...@basic-process.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#109485]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (53 -> 45)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-gdg-551 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6431 -> Patchwork_13566
CI_DRM_6431: 9a40fb28e45261f2fc44a9b271c19faf1f071138 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5090: c6c75e11175baeb6b984e0cc13c6fbe2863a0794 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13566: 2cefe1e71b5add7ce90c86a141f0f1809d3a6b70 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13566/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
2cefe1e71b5a drm/i915: Explicitly track active fw_domain timers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/P
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Fill in a little more of the dummy fence
== Series Details == Series: drm/i915/selftests: Fill in a little more of the dummy fence URL : https://patchwork.freedesktop.org/series/63365/ State : success == Summary == CI Bug Log - changes from CI_DRM_6429_full -> Patchwork_13560_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13560_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-apl7/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-apl3/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_exec_suspend@basic-s3: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-skl4/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-skl1/igt@gem_exec_susp...@basic-s3.html * igt@i915_pm_rpm@i2c: - shard-hsw: [PASS][5] -> [FAIL][6] ([fdo#104097]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-hsw4/igt@i915_pm_...@i2c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-hsw2/igt@i915_pm_...@i2c.html * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([fdo#105541]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-skl9/igt@kms_cursor_leg...@long-nonblocking-modeset-vs-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-skl6/igt@kms_cursor_leg...@long-nonblocking-modeset-vs-cursor-atomic.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb7/igt@kms_frontbuffer_track...@fbc-stridechange.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-iclb7/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-skl6/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([fdo#106885]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-skl1/igt@kms_rotation_...@multiplane-rotation-cropping-top.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-skl2/igt@kms_rotation_...@multiplane-rotation-cropping-top.html * igt@kms_sequence@get-busy: - shard-hsw: [PASS][19] -> [INCOMPLETE][20] ([fdo#103540]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-hsw7/igt@kms_seque...@get-busy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-hsw5/igt@kms_seque...@get-busy.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-kbl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-kbl1/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible fixes * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][23] ([fdo#110854]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6429/shard-iclb3/igt@gem_exec_balan...@smoke.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13560/shard-iclb4/igt@gem_exec_balan...@smoke.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-glk: [INCOMPLETE][25] ([fdo#103359] / [k.org#198133]) -> [PASS][26] [25]: https://intel
[Intel-gfx] [PATCH v2 12/14] drm/i915: s/crtc_mask/pipe_mask/
From: Ville Syrjälä
Rename the encoder->crtc_mask to encoder->pipe_mask to better
reflect what it actually contains.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_crt.c | 4 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c| 6 +++---
drivers/gpu/drm/i915/display/intel_lvds.c| 4 ++--
drivers/gpu/drm/i915/display/intel_sdvo.c| 2 +-
drivers/gpu/drm/i915/display/intel_tv.c | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 6 +++---
drivers/gpu/drm/i915/intel_drv.h | 5 +++--
13 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index b8673debf932..0641bc1a36fb 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1549,7 +1549,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->get_hw_state = gen11_dsi_get_hw_state;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
- encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
+ encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
encoder->power_domain = POWER_DOMAIN_PORT_DSI;
encoder->get_power_domains = gen11_dsi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 68457e8e07aa..c9055e1ea988 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -997,9 +997,9 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
crt->base.type = INTEL_OUTPUT_ANALOG;
crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 <<
INTEL_OUTPUT_HDMI);
if (IS_I830(dev_priv))
- crt->base.crtc_mask = BIT(PIPE_A);
+ crt->base.pipe_mask = BIT(PIPE_A);
else
- crt->base.crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
+ crt->base.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
if (IS_GEN(dev_priv, 2))
connector->interlace_allowed = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 30e48609db1d..9ab6b40e4b61 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4250,7 +4250,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
intel_encoder->port = port;
intel_encoder->cloneable = 0;
for_each_pipe(dev_priv, pipe)
- intel_encoder->crtc_mask |= BIT(pipe);
+ intel_encoder->pipe_mask |= BIT(pipe);
if (INTEL_GEN(dev_priv) >= 11)
intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 93fdd1cbd343..70ec20444255 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15218,7 +15218,7 @@ static u32 intel_encoder_possible_crtcs(struct
intel_encoder *encoder)
u32 possible_crtcs = 0;
for_each_intel_crtc(dev, crtc) {
- if (encoder->crtc_mask & BIT(crtc->pipe))
+ if (encoder->pipe_mask & BIT(crtc->pipe))
possible_crtcs |= drm_crtc_mask(&crtc->base);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6baa537e9849..ef183a90e929 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7283,11 +7283,11 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->power_domain = intel_port_to_power_domain(port);
if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
- intel_encoder->crtc_mask = BIT(PIPE_C);
+ intel_encoder->pipe_mask = BIT(PIPE_C);
else
- intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B);
+ intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
} else {
- intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) |
BIT(PIPE_C);
+ intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) |
BIT(PIPE_C);
}
intel_encoder->cloneable = 0;
intel_encoder->port = port;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index d08e4a47816a..f79842c7be67 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -60
Re: [Intel-gfx] [PATCH v8 6/6] drm/hdcp: reference for srm file format
On 2019-07-08 at 13:16:23 +0300, Pekka Paalanen wrote: > On Fri, 5 Jul 2019 06:16:42 +0530 > Ramalingam C wrote: > > > In the kernel documentation, HDCP specifications links are shared as a > > reference for SRM table format. > > > > Signed-off-by: Ramalingam C > > --- > > drivers/gpu/drm/drm_hdcp.c | 7 +++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c > > index 77433ee3d652..803bf8283b83 100644 > > --- a/drivers/gpu/drm/drm_hdcp.c > > +++ b/drivers/gpu/drm/drm_hdcp.c > > @@ -271,6 +271,13 @@ static void drm_hdcp_request_srm(struct drm_device > > *drm_dev) > > * > > * SRM should be presented in the name of "display_hdcp_srm.bin". > > * > > + * Format of the SRM table that userspace needs to write into the binary > > file > > + * is defined at > > + * 1. Renewability chapter on 55th page of HDCP 1.4 specification > > + * > > https://www.digital-cp.com/sites/default/files/specifications/HDCP%20Specification%20Rev1_4_Secure.pdf > > + * 2. Renewability chapter on 63rd page of HDCP 2.2 specification > > + * > > https://www.digital-cp.com/sites/default/files/specifications/HDCP%20on%20HDMI%20Specification%20Rev2_2_Final1.pdf > > + * > > * Returns: > > * TRUE on any of the KSV is revoked, else FALSE. > > */ > > Hi, > > this look good, publicly accessible spec links even. I'm happy with > this, but I repeat that the Weston work[1] does not directly prove this > UAPI (perhaps not necessary either?). Thanks for helping to improve this part. -Ram > > > [1] https://gitlab.freedesktop.org/wayland/weston/merge_requests/48 > > Thanks, > pq ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 14/14] drm: Validate encoder->possible_crtcs
From: Ville Syrjälä
WARN if the encoder possible_crtcs is effectively empty or contains
bits for non-existing crtcs.
TODO: Or should we perhapst just filter out any bit for a
non-exisiting crtc?
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_encoder.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/drm_encoder.c b/drivers/gpu/drm/drm_encoder.c
index 3ece97a9d029..07191e2db64c 100644
--- a/drivers/gpu/drm/drm_encoder.c
+++ b/drivers/gpu/drm/drm_encoder.c
@@ -106,6 +106,23 @@ static void validate_possible_clones(struct drm_encoder
*encoder)
encoder->possible_clones, encoder_mask);
}
+static void validate_possible_crtcs(struct drm_encoder *encoder)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_crtc *crtc;
+ u32 crtc_mask = 0;
+
+ drm_for_each_crtc(crtc, dev)
+ crtc_mask |= drm_crtc_mask(crtc);
+
+ WARN((encoder->possible_crtcs & crtc_mask) == 0 ||
+(encoder->possible_crtcs & ~crtc_mask) != 0,
+"Bogus possible_crtcs: "
+"[ENCODER:%d:%s] possible_crtcs=0x%x (full crtc mask=0x%x)\n",
+encoder->base.id, encoder->name,
+encoder->possible_crtcs, crtc_mask);
+}
+
int drm_encoder_register_all(struct drm_device *dev)
{
struct drm_encoder *encoder;
@@ -114,6 +131,7 @@ int drm_encoder_register_all(struct drm_device *dev)
fixup_possible_clones(dev);
drm_for_each_encoder(encoder, dev) {
+ validate_possible_crtcs(encoder);
validate_possible_clones(encoder);
if (encoder->funcs->late_register)
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 13/14] drm: Validate encoder->possible_clones
From: Ville Syrjälä
Many drivers are populating encoder->possible_clones wrong. Let's
persuade them to get it right by adding some loud WARNs.
We'll cross check the bits between any two encoders. So either
both encoders can clone with the other, or neither can.
We'll also complain about effectively empty possible_clones, and
possible_clones containing bits for encoders that don't exist.
TODO: Or should we just silently filter out any bits for non-existing
encoders?
v2: encoder->possible_clones now includes the encoder itelf
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_encoder.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/drm_encoder.c b/drivers/gpu/drm/drm_encoder.c
index e87e6fecc1fb..3ece97a9d029 100644
--- a/drivers/gpu/drm/drm_encoder.c
+++ b/drivers/gpu/drm/drm_encoder.c
@@ -78,6 +78,34 @@ static void fixup_possible_clones(struct drm_device *dev)
encoder->possible_clones |= drm_encoder_mask(encoder);
}
+static void validate_possible_clones(struct drm_encoder *encoder)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_encoder *other;
+ u32 encoder_mask = 0;
+
+ drm_for_each_encoder(other, dev) {
+ encoder_mask |= drm_encoder_mask(other);
+
+ WARN(!(encoder->possible_clones & drm_encoder_mask(other)) !=
+!(other->possible_clones & drm_encoder_mask(encoder)),
+"possible_clones mismatch: "
+"[ENCODER:%d:%s] mask=0x%x possible_clones=0x%x vs. "
+"[ENCODER:%d:%s] mask=0x%x possible_clones=0x%x\n",
+encoder->base.id, encoder->name,
+drm_encoder_mask(encoder), encoder->possible_clones,
+other->base.id, other->name,
+drm_encoder_mask(other), other->possible_clones);
+ }
+
+ WARN((encoder->possible_clones & drm_encoder_mask(encoder)) == 0 ||
+(encoder->possible_clones & ~encoder_mask) != 0,
+"Bogus possible_clones: "
+"[ENCODER:%d:%s] possible_clones=0x%x (full encoder mask=0x%x)\n",
+encoder->base.id, encoder->name,
+encoder->possible_clones, encoder_mask);
+}
+
int drm_encoder_register_all(struct drm_device *dev)
{
struct drm_encoder *encoder;
@@ -86,6 +114,8 @@ int drm_encoder_register_all(struct drm_device *dev)
fixup_possible_clones(dev);
drm_for_each_encoder(encoder, dev) {
+ validate_possible_clones(encoder);
+
if (encoder->funcs->late_register)
ret = encoder->funcs->late_register(encoder);
if (ret)
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 10/14] drm/i915: Clean up encoder->crtc_mask setup
From: Ville Syrjälä
Use BIT(pipe) for better legibility when populating the crtc_mask
for encoders.
Also remove the redundant possible_crtcs setup for the TV encoder.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crt.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dvo.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +++---
drivers/gpu/drm/i915/display/intel_lvds.c | 6 +++---
drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
drivers/gpu/drm/i915/display/intel_tv.c | 3 +--
7 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 3fcf2f84bcce..68457e8e07aa 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -997,9 +997,9 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
crt->base.type = INTEL_OUTPUT_ANALOG;
crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 <<
INTEL_OUTPUT_HDMI);
if (IS_I830(dev_priv))
- crt->base.crtc_mask = (1 << 0);
+ crt->base.crtc_mask = BIT(PIPE_A);
else
- crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+ crt->base.crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
if (IS_GEN(dev_priv, 2))
connector->interlace_allowed = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0bdb7ecc5a81..6baa537e9849 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7283,11 +7283,11 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->power_domain = intel_port_to_power_domain(port);
if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
- intel_encoder->crtc_mask = 1 << 2;
+ intel_encoder->crtc_mask = BIT(PIPE_C);
else
- intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+ intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B);
} else {
- intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+ intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) |
BIT(PIPE_C);
}
intel_encoder->cloneable = 0;
intel_encoder->port = port;
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
b/drivers/gpu/drm/i915/display/intel_dvo.c
index 22666d28f4aa..df491f59401b 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -505,7 +505,7 @@ void intel_dvo_init(struct drm_i915_private *dev_priv)
intel_encoder->type = INTEL_OUTPUT_DVO;
intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
intel_encoder->port = port;
- intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+ intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B);
switch (dvo->type) {
case INTEL_DVO_CHIP_TMDS:
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..3a73577ef259 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3202,11 +3202,11 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv,
intel_encoder->port = port;
if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
- intel_encoder->crtc_mask = 1 << 2;
+ intel_encoder->crtc_mask = BIT(PIPE_C);
else
- intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+ intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B);
} else {
- intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+ intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) |
BIT(PIPE_C);
}
intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
b/drivers/gpu/drm/i915/display/intel_lvds.c
index efefed62a7f8..765091a9835c 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -902,11 +902,11 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
intel_encoder->port = PORT_NONE;
intel_encoder->cloneable = 0;
if (HAS_PCH_SPLIT(dev_priv))
- intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+ intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) |
BIT(PIPE_C);
else if (IS_GEN(dev_priv, 4))
- intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+ intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B);
else
- intel_encoder->crtc_mask = (1 << 1);
+ intel_encode
[Intel-gfx] [PATCH v2 11/14] drm/i915: Simplfy LVDS crtc_mask setup
From: Ville Syrjälä We don't need to special case PCH vs. gen4 when setting up the LVDS crtc_mask. Just claim pipes A|B|C work and intel_encoder_crtcs() drop out any crtc that doesn't exist. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_lvds.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 765091a9835c..e79dcc891b80 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -901,10 +901,8 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; intel_encoder->port = PORT_NONE; intel_encoder->cloneable = 0; - if (HAS_PCH_SPLIT(dev_priv)) + if (INTEL_GEN(dev_priv) >= 4) intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); - else if (IS_GEN(dev_priv, 4)) - intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B); else intel_encoder->crtc_mask = BIT(PIPE_B); -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 07/14] drm/i915: Polish possible_clones setup
From: Ville Syrjälä
Replace the hand rolled stuff with drm_encoder_mask() when populating
possible_clones, and rename the function to
intel_encoder_possible_clones() to make it clear what it's used for.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f09eda75711a..503c20a3a49c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15197,21 +15197,18 @@ int intel_get_pipe_from_crtc_id_ioctl(struct
drm_device *dev, void *data,
return 0;
}
-static int intel_encoder_clones(struct intel_encoder *encoder)
+static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
{
struct drm_device *dev = encoder->base.dev;
struct intel_encoder *source_encoder;
- int index_mask = 0;
- int entry = 0;
+ u32 possible_clones = 0;
for_each_intel_encoder(dev, source_encoder) {
if (encoders_cloneable(encoder, source_encoder))
- index_mask |= (1 << entry);
-
- entry++;
+ possible_clones |=
drm_encoder_mask(&source_encoder->base);
}
- return index_mask;
+ return possible_clones;
}
static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
@@ -15505,7 +15502,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
for_each_intel_encoder(&dev_priv->drm, encoder) {
encoder->base.possible_crtcs = encoder->crtc_mask;
encoder->base.possible_clones =
- intel_encoder_clones(encoder);
+ intel_encoder_possible_clones(encoder);
}
intel_init_pch_refclk(dev_priv);
--
2.21.0
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[Intel-gfx] [PATCH v2 09/14] drm/i915: Fix DP-MST crtc_mask
From: Ville Syrjälä Each fake MST encoder is tied to a specific pipe. Fix the encoder's crtc_mask to reflect that fact. Reviewed-by: Dhinakaran Pandiyan Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 60652ebbdf61..d08e4a47816a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -602,7 +602,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum intel_encoder->type = INTEL_OUTPUT_DP_MST; intel_encoder->power_domain = intel_dig_port->base.power_domain; intel_encoder->port = intel_dig_port->base.port; - intel_encoder->crtc_mask = 0x7; + intel_encoder->crtc_mask = BIT(pipe); intel_encoder->cloneable = 0; intel_encoder->compute_config = intel_dp_mst_compute_config; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 06/14] drm/imx: Remove the bogus possible_clones setup
From: Ville Syrjälä It's not at all clear what cloning options this driver supports. So let's just clear possible_clones instead of setting it to some bogus value. Cc: Philipp Zabel Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/imx/imx-drm-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c index bdefaa1635eb..bd650b0c27b2 100644 --- a/drivers/gpu/drm/imx/imx-drm-core.c +++ b/drivers/gpu/drm/imx/imx-drm-core.c @@ -136,7 +136,7 @@ int imx_drm_encoder_parse_of(struct drm_device *drm, encoder->possible_crtcs = crtc_mask; /* FIXME: this is the mask of outputs which can clone this output. */ - encoder->possible_clones = ~0; + encoder->possible_clones = 0; return 0; } -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 08/14] drm/i915: Populate possible_crtcs correctly
From: Ville Syrjälä
Don't advertize non-exisiting crtcs in the encoder possible_crtcs
bitmask.
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 503c20a3a49c..93fdd1cbd343 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15211,6 +15211,20 @@ static u32 intel_encoder_possible_clones(struct
intel_encoder *encoder)
return possible_clones;
}
+static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct intel_crtc *crtc;
+ u32 possible_crtcs = 0;
+
+ for_each_intel_crtc(dev, crtc) {
+ if (encoder->crtc_mask & BIT(crtc->pipe))
+ possible_crtcs |= drm_crtc_mask(&crtc->base);
+ }
+
+ return possible_crtcs;
+}
+
static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
{
if (!IS_MOBILE(dev_priv))
@@ -15500,7 +15514,8 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_psr_init(dev_priv);
for_each_intel_encoder(&dev_priv->drm, encoder) {
- encoder->base.possible_crtcs = encoder->crtc_mask;
+ encoder->base.possible_crtcs =
+ intel_encoder_possible_crtcs(encoder);
encoder->base.possible_clones =
intel_encoder_possible_clones(encoder);
}
--
2.21.0
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[Intel-gfx] [PATCH v2 05/14] drm/exynos: Use drm_encoder_mask()
From: Ville Syrjälä Replace the hand rolled encoder bitmask thing with drm_encoder_mask() Cc: Inki Dae Cc: Joonyoung Shim Cc: Seung-Woo Kim Cc: Kyungmin Park Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/exynos/exynos_drm_drv.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index cc53dcad25e4..140ef553e156 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -264,7 +264,7 @@ static int exynos_drm_bind(struct device *dev) struct drm_encoder *encoder; struct drm_device *drm; unsigned int clone_mask; - int cnt, ret; + int ret; drm = drm_dev_alloc(&exynos_drm_driver, dev); if (IS_ERR(drm)) @@ -287,10 +287,9 @@ static int exynos_drm_bind(struct device *dev) exynos_drm_mode_config_init(drm); /* setup possible_clones. */ - cnt = 0; clone_mask = 0; list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) - clone_mask |= (1 << (cnt++)); + clone_mask |= drm_encoder_mask(encoder); list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) encoder->possible_clones = clone_mask; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 04/14] drm/sti: Try to fix up the tvout possible clones
From: Ville Syrjälä The current possible_clones setup doesn't look sensible. I'm assuming the 0 and 1 are supposed to refer to the indexes of the hdmi and hda encoders? So it kinda looks like we want hda+hdmi cloning, but then dvo also claims to be cloneable with hdmi, but hdmi won't recipricate. Benjamin tells me all encoders should be cloneable with each other, so let's fix up the masks to indicate that. Cc: Benjamin Gaignard Cc: Vincent Abriou Acked-by: Benjamin Gaignard Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/sti/sti_tvout.c | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c index 42f4c264a783..aba79c172512 100644 --- a/drivers/gpu/drm/sti/sti_tvout.c +++ b/drivers/gpu/drm/sti/sti_tvout.c @@ -672,7 +672,6 @@ sti_tvout_create_dvo_encoder(struct drm_device *dev, drm_encoder = &encoder->encoder; drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; - drm_encoder->possible_clones = 1 << 0; drm_encoder_init(dev, drm_encoder, &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_LVDS, @@ -725,7 +724,6 @@ static struct drm_encoder *sti_tvout_create_hda_encoder(struct drm_device *dev, drm_encoder = &encoder->encoder; drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; - drm_encoder->possible_clones = 1 << 0; drm_encoder_init(dev, drm_encoder, &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL); @@ -774,7 +772,6 @@ static struct drm_encoder *sti_tvout_create_hdmi_encoder(struct drm_device *dev, drm_encoder = &encoder->encoder; drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; - drm_encoder->possible_clones = 1 << 1; drm_encoder_init(dev, drm_encoder, &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); @@ -790,6 +787,13 @@ static void sti_tvout_create_encoders(struct drm_device *dev, tvout->hdmi = sti_tvout_create_hdmi_encoder(dev, tvout); tvout->hda = sti_tvout_create_hda_encoder(dev, tvout); tvout->dvo = sti_tvout_create_dvo_encoder(dev, tvout); + + tvout->hdmi->possible_clones = drm_encoder_mask(tvout->hdmi) | + drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo); + tvout->hda->possible_clones = drm_encoder_mask(tvout->hdmi) | + drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo); + tvout->dvo->possible_clones = drm_encoder_mask(tvout->hdmi) | + drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo); } static void sti_tvout_destroy_encoders(struct sti_tvout *tvout) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 03/14] drm/sti: Remove pointless casts
From: Ville Syrjälä There's no point in the cast for accessing the base class. Just take the address of the struct instead. Cc: Benjamin Gaignard Cc: Vincent Abriou Acked-by: Benjamin Gaignard Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/sti/sti_tvout.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c index e1b3c8cb7287..42f4c264a783 100644 --- a/drivers/gpu/drm/sti/sti_tvout.c +++ b/drivers/gpu/drm/sti/sti_tvout.c @@ -669,7 +669,7 @@ sti_tvout_create_dvo_encoder(struct drm_device *dev, encoder->tvout = tvout; - drm_encoder = (struct drm_encoder *)encoder; + drm_encoder = &encoder->encoder; drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; drm_encoder->possible_clones = 1 << 0; @@ -722,7 +722,7 @@ static struct drm_encoder *sti_tvout_create_hda_encoder(struct drm_device *dev, encoder->tvout = tvout; - drm_encoder = (struct drm_encoder *) encoder; + drm_encoder = &encoder->encoder; drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; drm_encoder->possible_clones = 1 << 0; @@ -771,7 +771,7 @@ static struct drm_encoder *sti_tvout_create_hdmi_encoder(struct drm_device *dev, encoder->tvout = tvout; - drm_encoder = (struct drm_encoder *) encoder; + drm_encoder = &encoder->encoder; drm_encoder->possible_crtcs = ENCODER_CRTC_MASK; drm_encoder->possible_clones = 1 << 1; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 01/14] drm: Include the encoder itself in possible_clones
From: Ville Syrjälä
The docs say possible_clones should always include the encoder itself.
Since most drivers don't want to deal with the complexities of cloning
let's allow them to set possible_clones=0 and instead we'll fix that
up in the core.
We can't put this special case into drm_encoder_init() because drivers
will have to fill up possible_clones after adding all the relevant
encoders. Otherwise they wouldn't know the proper encoder indexes to
use. So we'll just do it just before registering the encoders.
TODO: Should we add the bit even if possible_clones was otherwise
populated by the driver?
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_encoder.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_encoder.c b/drivers/gpu/drm/drm_encoder.c
index 7fb47b7b8b44..e87e6fecc1fb 100644
--- a/drivers/gpu/drm/drm_encoder.c
+++ b/drivers/gpu/drm/drm_encoder.c
@@ -65,11 +65,26 @@ static const struct drm_prop_enum_list
drm_encoder_enum_list[] = {
{ DRM_MODE_ENCODER_DPI, "DPI" },
};
+/*
+ * For some reason we want the encoder itself included in
+ * possible_clones. Make life easy for drivers by allowing them
+ * to leave possible_clones unset if no cloning is possible.
+ */
+static void fixup_possible_clones(struct drm_device *dev)
+{
+ struct drm_encoder *encoder;
+
+ drm_for_each_encoder(encoder, dev)
+ encoder->possible_clones |= drm_encoder_mask(encoder);
+}
+
int drm_encoder_register_all(struct drm_device *dev)
{
struct drm_encoder *encoder;
int ret = 0;
+ fixup_possible_clones(dev);
+
drm_for_each_encoder(encoder, dev) {
if (encoder->funcs->late_register)
ret = encoder->funcs->late_register(encoder);
--
2.21.0
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