Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for uC fw path unification + misc clean-up (rev3)

[Chris Wilson]

Quoting Patchwork (2019-07-25 01:57:28)
> == Series Details ==
> 
> Series: uC fw path unification + misc clean-up (rev3)
> URL   : https://patchwork.freedesktop.org/series/64039/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13741
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_13741 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_13741, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_13741:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_module_load@reload-with-fault-injection:
> - fi-snb-2520m:   [PASS][1] -> [INCOMPLETE][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html

That's been cropping up frequently over the last 24 hours, unrelated so
pushed. Thanks,
-Chris
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Re: [Intel-gfx] [PATCH v3 6/8] drm/i915/huc: Copy huc rsa only once

[Michal Wajdeczko]

On Thu, 25 Jul 2019 02:18:11 +0200, Daniele Ceraolo Spurio  
 wrote:



The binary is perma-pinned and the rsa is not going to change, so copy
it only once and not on every load.

v2: onion unwind (Chris)

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Fernando Pacheco 
Reviewed-by: Chris Wilson  #v1


Reviewed-by: Michal Wajdeczko 
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Re: [Intel-gfx] [PATCH v3 4/8] drm/i915/uc: Unify uc_fw status tracking

[Michal Wajdeczko]

On Thu, 25 Jul 2019 02:18:09 +0200, Daniele Ceraolo Spurio  
 wrote:



We currently track fetch and load status separately, but the 2 are
actually sequential in the uc lifetime (fetch must complete before we
can attempt the load!). Unifying the 2 variables we can better follow
the sequential states and improve our trackng of the uC state.

Also, sprinkle some GEM_BUG_ON to make sure we transition correctly
between states.

v2: rename states, add the running state (Michal), drop some logs in
the fetch path (Michal, Chris)

v3: re-rename states, extend early status check to all helpers (Michal)

Suggested-by: Michal Wajdeczko 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
---


Reviewed-by: Michal Wajdeczko 

...


+static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
+{
+   return intel_uc_fw_is_running(&huc->fw);
+}
+


btw, maybe later we can use that instead of intel_huc_check_status() ?
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Re: [Intel-gfx] [PATCH v3 3/8] drm/i915/uc: Unify uC FW selection

[Michal Wajdeczko]

On Thu, 25 Jul 2019 02:18:08 +0200, Daniele Ceraolo Spurio  
 wrote:



Instead of having 2 identical functions for GuC and HuC firmware
selection, we can unify the selection logic and just use different lists
based on FW type.

Note that the revid is not relevant for current blobs, but the upcoming
CML will be identified as CFL rev 5, so by considering the revid we're
ready for that.

v2: rework blob list defs (Michal), add order check (Chris), fuse GuC
and HuC lists into one.

v3: remove difference between no uC HW and no uC FW, simplify related
selection code, check the whole fw list (Michal)

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Anusha Srivatsa 
Cc: Chris Wilson 
Reviewed-by: Chris Wilson  #v2
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  89 +---
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  91 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 156 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  24 +---
 4 files changed, 164 insertions(+), 196 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c  
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

index 17ce78240cf8..99f44d8ae026 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -31,90 +31,6 @@
 #include "intel_guc_fw.h"
 #include "i915_drv.h"
-#define __MAKE_GUC_FW_PATH(KEY) \
-   "i915/" \
-   __stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
-   __stringify(KEY##_GUC_FW_MAJOR) "." \
-   __stringify(KEY##_GUC_FW_MINOR) "." \
-   __stringify(KEY##_GUC_FW_PATCH) ".bin"
-
-#define SKL_GUC_FW_PREFIX skl
-#define SKL_GUC_FW_MAJOR 33
-#define SKL_GUC_FW_MINOR 0
-#define SKL_GUC_FW_PATCH 0
-#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
-MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
-
-#define BXT_GUC_FW_PREFIX bxt
-#define BXT_GUC_FW_MAJOR 33
-#define BXT_GUC_FW_MINOR 0
-#define BXT_GUC_FW_PATCH 0
-#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
-MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
-
-#define KBL_GUC_FW_PREFIX kbl
-#define KBL_GUC_FW_MAJOR 33
-#define KBL_GUC_FW_MINOR 0
-#define KBL_GUC_FW_PATCH 0
-#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
-MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
-
-#define GLK_GUC_FW_PREFIX glk
-#define GLK_GUC_FW_MAJOR 33
-#define GLK_GUC_FW_MINOR 0
-#define GLK_GUC_FW_PATCH 0
-#define GLK_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(GLK)
-MODULE_FIRMWARE(GLK_GUC_FIRMWARE_PATH);
-
-#define ICL_GUC_FW_PREFIX icl
-#define ICL_GUC_FW_MAJOR 33
-#define ICL_GUC_FW_MINOR 0
-#define ICL_GUC_FW_PATCH 0
-#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
-MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
-
-static void guc_fw_select(struct intel_uc_fw *guc_fw)
-{
-   struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
-   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
-   GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
-
-   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
-
-   if (!HAS_GT_UC(i915))
-   return;
-
-   if (i915_modparams.guc_firmware_path) {
-   guc_fw->path = i915_modparams.guc_firmware_path;
-   guc_fw->major_ver_wanted = 0;
-   guc_fw->minor_ver_wanted = 0;
-   } else if (IS_ICELAKE(i915)) {
-   guc_fw->path = ICL_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
-   } else if (IS_GEMINILAKE(i915)) {
-   guc_fw->path = GLK_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
-   } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
-   guc_fw->path = KBL_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
-   } else if (IS_BROXTON(i915)) {
-   guc_fw->path = BXT_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
-   } else if (IS_SKYLAKE(i915)) {
-   guc_fw->path = SKL_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
-   }
-
-   if (guc_fw->path)
-   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
-}
-
 /**
  * intel_guc_fw_init_early() - initializes GuC firmware struct
  * @guc: intel_guc struct
@@ -123,10 +39,7 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
  */
 void intel_guc_fw_init_early(struct intel_guc *guc)
 {
-   struct intel_uc_fw *guc_fw = &guc->fw;
-
-   intel_uc_fw_init_early(guc_fw, INTEL_UC_FW_TYPE_GUC);
-   guc_fw_select(guc_fw);
+	intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC,  
guc_to_gt(guc)->i915);

 }
static void guc_prepare_xfer(struct intel_guc *guc)
diff --git a/

Re: [Intel-gfx] [PATCH v3 2/8] drm/i915: Fix handling of non-supported uC

[Michal Wajdeczko]

On Thu, 25 Jul 2019 02:18:07 +0200, Daniele Ceraolo Spurio  
 wrote:



There are 2 issues around handling of missing uC support:

- We treat lack of uC HW and lack of uC FW definition as 2 different
  cases, but both of them mean that we don't support the uC on the
  platform we're running on.

- We rely on the modparam to decide if we can take uC paths or not, but
  we don't sanitize it if it is set incorrectly on platform with no uC
  support.

To fix both of them, unify the 2 cases in a single one and sanitize the
modparam on invalid configuration (after printing an error message).
The log has been adapted as well, since the user doesn't care why we
don't support GuC/HuC (no HW or no FW), just that we do not. Developers
can easily find the answer based on the platform, so we can simplify the
log.

Correcting the modparam has been preferred over failing the load since
this is what we usually do for non-supported feature (e.g. the now gone
enable_ppgtt would fall back to the highest supported PPGTT mode if the
selected one was not available).

Note that this patch purposely doesn't change the behavior for platforms
that do have uC support, in which case we will still fail if enable_guc
is set and the firmware is not available on the system.

Suggested-by: Michal Wajdeczko 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 


Note that more changes are planned around this code,
Reviewed-by: Michal Wajdeczko 



---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 11 ---
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 11 ---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 37 ---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  8 -
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  5 ---
 5 files changed, 31 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c  
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

index 87169e826747..17ce78240cf8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -80,12 +80,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
-   if (!HAS_GT_UC(i915)) {
-   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
-   return;
-   }
+   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
-   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
+   if (!HAS_GT_UC(i915))
+   return;
if (i915_modparams.guc_firmware_path) {
guc_fw->path = i915_modparams.guc_firmware_path;
@@ -112,6 +110,9 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
}
+
+   if (guc_fw->path)
+   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
 }
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c  
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c

index ff6f7b157ecb..c3a7bd57fb55 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -74,12 +74,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
-   if (!HAS_GT_UC(dev_priv)) {
-   huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
-   return;
-   }
+   huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
-   huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
+   if (!HAS_GT_UC(dev_priv))
+   return;
if (i915_modparams.huc_firmware_path) {
huc_fw->path = i915_modparams.huc_firmware_path;
@@ -106,6 +104,9 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
}
+
+   if (huc_fw->path)
+   huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
 }
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c  
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c

index bdb171c3f36e..3f672ea7456b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -68,7 +68,7 @@ static int __get_platform_enable_guc(struct intel_uc  
*uc)

if (INTEL_GEN(uc_to_gt(uc)->i915) < 11)
return 0;
-   if (intel_uc_fw_is_selected(guc_fw) && intel_uc_fw_is_selected(huc_fw))
+   if (intel_uc_fw_supported(guc_fw) && intel_uc_fw_supported(huc_fw))
enable_guc |= ENABLE_GUC_LOAD_HUC;
return enable_guc;
@@ -123,26 +123,28 @@ static void sanitize_options_early(struct intel_uc  
*uc)

 yesno(intel_uc_is_using_huc(uc)));
/* Verify GuC firmware availability */
-   if (intel_uc_is_using_guc(uc) && !intel_uc_fw_is_selected(guc_fw)) {
-   DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
-"ena

[Intel-gfx] ✗ Fi.CI.BAT: failure for uC fw path unification + misc clean-up (rev3)

[Patchwork]

== Series Details ==

Series: uC fw path unification + misc clean-up (rev3)
URL   : https://patchwork.freedesktop.org/series/64039/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13741


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_13741 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13741, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_13741:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2520m:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html

  
Known issues


  Here are the changes found in Patchwork_13741 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850:   [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html

  * igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u:   [PASS][5] -> [SKIP][6] ([fdo#109271]) +23 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html

  
 Possible fixes 

  * igt@gem_ctx_create@basic-files:
- fi-icl-u2:  [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) -> 
[PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html

  * igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [INCOMPLETE][9] ([fdo#108744]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3:  [FAIL][11] ([fdo#103167]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
- {fi-icl-u4}:[FAIL][13] ([fdo#103167]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13741/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049


Participating hosts (52 -> 43)
--

  Additional (1): fi-skl-gvtdvm 
  Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-gdg-551 fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6545 -> Patchwork_13741

  CI-20190529: 20190529
  CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13741: 64323d6a78ce25f36754be89f68267ba3b96fd31 @ 
git://anongit.freedes

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for uC fw path unification + misc clean-up (rev3)

[Patchwork]

== Series Details ==

Series: uC fw path unification + misc clean-up (rev3)
URL   : https://patchwork.freedesktop.org/series/64039/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/uc: Unify uC platform check
Okay!

Commit: drm/i915: Fix handling of non-supported uC
Okay!

Commit: drm/i915/uc: Unify uC FW selection
Okay!

Commit: drm/i915/uc: Unify uc_fw status tracking
Okay!

Commit: drm/i915/uc: Move xfer rsa logic to common function
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:473:20: warning: expression using 
sizeof(void)
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:473:20: warning: expression using 
sizeof(void)

Commit: drm/i915/huc: Copy huc rsa only once
Okay!

Commit: drm/i915/uc: Plumb the gt through fw_upload
Okay!

Commit: drm/i915/uc: Unify uC firmware upload
Okay!

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for uC fw path unification + misc clean-up (rev3)

[Patchwork]

== Series Details ==

Series: uC fw path unification + misc clean-up (rev3)
URL   : https://patchwork.freedesktop.org/series/64039/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
cbaf15df0ad3 drm/i915/uc: Unify uC platform check
c38f4e39f2fe drm/i915: Fix handling of non-supported uC
245ade6cfe0c drm/i915/uc: Unify uC FW selection
-:254: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#254: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:36:
+#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+   fw_def(ICELAKE,0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
+   fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 
2893)) \
+   fw_def(KABYLAKE,   0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(BROXTON,0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8, 
2893)) \
+   fw_def(SKYLAKE,0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 
1398))

-:254: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible 
side-effects?
#254: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:36:
+#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+   fw_def(ICELAKE,0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
+   fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 
2893)) \
+   fw_def(KABYLAKE,   0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(BROXTON,0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8, 
2893)) \
+   fw_def(SKYLAKE,0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 
1398))

-:254: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'guc_def' - possible 
side-effects?
#254: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:36:
+#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+   fw_def(ICELAKE,0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
+   fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 
2893)) \
+   fw_def(KABYLAKE,   0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(BROXTON,0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8, 
2893)) \
+   fw_def(SKYLAKE,0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 
1398))

-:254: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'huc_def' - possible 
side-effects?
#254: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:36:
+#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+   fw_def(ICELAKE,0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
+   fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 
2893)) \
+   fw_def(KABYLAKE,   0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(BROXTON,0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8, 
2893)) \
+   fw_def(SKYLAKE,0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 
1398))

-:262: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'separator_' - possible 
side-effects?
#262: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:44:
+#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \
+   "i915/" \
+   __stringify(prefix_) name_ \
+   __stringify(major_) separator_ \
+   __stringify(minor_) separator_ \
+   __stringify(patch_) ".bin"

-:276: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements 
should be enclosed in a do - while loop
#276: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:58:
+#define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
+   MODULE_FIRMWARE(guc_); \
+   MODULE_FIRMWARE(huc_);

-:276: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#276: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:58:
+#define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
+   MODULE_FIRMWARE(guc_); \
+   MODULE_FIRMWARE(huc_);

-:292: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'major_' - possible 
side-effects?
#292: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:74:
+#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \
+   UC_FW_BLOB(major_, minor_, \
+  MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_))

-:292: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'minor_' - possible 
side-effects?
#292: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:74:
+#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \
+   UC_FW_BLOB(major_, minor_, \
+  MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_))

-:296: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'major_' - possible 
side-effects?
#296: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:78:
+#define HUC_FW_BLOB(prefix_, major_, minor_, bld_num_) \
+   UC_FW_

[Intel-gfx] [PATCH v3 6/8] drm/i915/huc: Copy huc rsa only once

[Daniele Ceraolo Spurio]

The binary is perma-pinned and the rsa is not going to change, so copy
it only once and not on every load.

v2: onion unwind (Chris)

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Fernando Pacheco 
Reviewed-by: Chris Wilson  #v1
---
 drivers/gpu/drm/i915/gt/uc/intel_huc.c| 27 +++
 drivers/gpu/drm/i915/gt/uc/intel_huc.h|  1 -
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 17 --
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index a45976e56af7..c9535caba844 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -50,6 +50,7 @@ static int intel_huc_rsa_data_create(struct intel_huc *huc)
struct intel_gt *gt = huc_to_gt(huc);
struct intel_guc *guc = >->uc.guc;
struct i915_vma *vma;
+   size_t copied;
void *vaddr;
 
/*
@@ -62,6 +63,7 @@ static int intel_huc_rsa_data_create(struct intel_huc *huc)
 * the authentication since its GGTT offset will be GuC
 * accessible.
 */
+   GEM_BUG_ON(huc->fw.rsa_size > PAGE_SIZE);
vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
if (IS_ERR(vma))
return PTR_ERR(vma);
@@ -72,26 +74,43 @@ static int intel_huc_rsa_data_create(struct intel_huc *huc)
return PTR_ERR(vaddr);
}
 
+   copied = intel_uc_fw_copy_rsa(&huc->fw, vaddr, vma->size);
+   GEM_BUG_ON(copied < huc->fw.rsa_size);
+
+   i915_gem_object_unpin_map(vma->obj);
+
huc->rsa_data = vma;
-   huc->rsa_data_vaddr = vaddr;
 
return 0;
 }
 
 static void intel_huc_rsa_data_destroy(struct intel_huc *huc)
 {
-   i915_vma_unpin_and_release(&huc->rsa_data, I915_VMA_RELEASE_MAP);
+   i915_vma_unpin_and_release(&huc->rsa_data, 0);
 }
 
 int intel_huc_init(struct intel_huc *huc)
 {
int err;
 
-   err = intel_huc_rsa_data_create(huc);
+   err = intel_uc_fw_init(&huc->fw);
if (err)
return err;
 
-   return intel_uc_fw_init(&huc->fw);
+   /*
+* HuC firmware image is outside GuC accessible range.
+* Copy the RSA signature out of the image into
+* a perma-pinned region set aside for it
+*/
+   err = intel_huc_rsa_data_create(huc);
+   if (err)
+   goto out_fini;
+
+   return 0;
+
+out_fini:
+   intel_uc_fw_fini(&huc->fw);
+   return err;
 }
 
 void intel_huc_fini(struct intel_huc *huc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index ea340f85bc46..4465209ce233 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -35,7 +35,6 @@ struct intel_huc {
 
/* HuC-specific additions */
struct i915_vma *rsa_data;
-   void *rsa_data_vaddr;
 
struct {
i915_reg_t reg;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 472568843ccf..7d2d2eb94d22 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -34,21 +34,6 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC, 
huc_to_gt(huc)->i915);
 }
 
-static void huc_xfer_rsa(struct intel_huc *huc)
-{
-   size_t copied;
-
-   /*
-* HuC firmware image is outside GuC accessible range.
-* Copy the RSA signature out of the image into
-* the perma-pinned region set aside for it
-*/
-   GEM_BUG_ON(huc->fw.rsa_size > huc->rsa_data->size);
-   copied = intel_uc_fw_copy_rsa(&huc->fw, huc->rsa_data_vaddr,
- huc->rsa_data->size);
-   GEM_BUG_ON(copied < huc->fw.rsa_size);
-}
-
 static int huc_xfer_ucode(struct intel_huc *huc)
 {
struct intel_uc_fw *huc_fw = &huc->fw;
@@ -108,8 +93,6 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw)
 {
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
 
-   huc_xfer_rsa(huc);
-
return huc_xfer_ucode(huc);
 }
 
-- 
2.22.0

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[Intel-gfx] [PATCH v3 8/8] drm/i915/uc: Unify uC firmware upload

[Daniele Ceraolo Spurio]

The way we load the firmwares is the same for both GuC and HuC, the only
difference is in the wopcm destination address and the dma flags, so we
easily can move the logic to a common function and pass in offset and
flags. The only other difference in the uplaod path are some the extra
steps that guc does before and after the xfer, but those don't require
the guc fw to be pinned in ggtt and can safely be performed before
calling the uc_upload function.

Note that this patch re-introduces the dma xfer wait for guc loading that
was removed with "drm/i915/guc: Propagate the fw xfer timeout". This is
not going to slow us down on a successful load (the dma has to complete
before fw init can start), but could slightly increase the timeout in case
of a fw init error.

v2: use _fw variants for uncore accesses (Chris), fix guc_fw status on
failed wait.

v3: use dev_err and print DMA_CTRL (Chris)

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 107 ++
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  57 +---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  80 
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |   4 +-
 4 files changed, 93 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 3ea0de6f4b73..28735c14b9a0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -84,13 +84,6 @@ static void guc_xfer_rsa(struct intel_uc_fw *guc_fw,
intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
 }
 
-static bool guc_xfer_completed(struct intel_uncore *uncore, u32 *status)
-{
-   /* Did we complete the xfer? */
-   *status = intel_uncore_read(uncore, DMA_CTRL);
-   return !(*status & START_DMA);
-}
-
 /*
  * Read the GuC status register (GUC_STATUS) and store it in the
  * specified location; then return a boolean indicating whether
@@ -137,65 +130,27 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
ret = -ENXIO;
}
 
-   if (ret == 0 && !guc_xfer_completed(uncore, &status)) {
-   DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n",
- status);
-   ret = -ENXIO;
-   }
-
return ret;
 }
 
-/*
- * Transfer the firmware image to RAM for execution by the microcontroller.
+/**
+ * intel_guc_fw_upload() - load GuC uCode to device
+ * @guc: intel_guc structure
  *
- * Architecturally, the DMA engine is bidirectional, and can potentially even
- * transfer between GTT locations. This functionality is left out of the API
- * for now as there is no need for it.
- */
-static int guc_xfer_ucode(struct intel_uc_fw *guc_fw,
- struct intel_gt *gt)
-{
-   struct intel_uncore *uncore = gt->uncore;
-   unsigned long offset;
-
-   /*
-* The header plus uCode will be copied to WOPCM via DMA, excluding any
-* other components
-*/
-   intel_uncore_write(uncore, DMA_COPY_SIZE,
-  guc_fw->header_size + guc_fw->ucode_size);
-
-   /* Set the source address for the new blob */
-   offset = intel_uc_fw_ggtt_offset(guc_fw, gt->ggtt) + 
guc_fw->header_offset;
-   intel_uncore_write(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset));
-   intel_uncore_write(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset) & 
0x);
-
-   /*
-* Set the DMA destination. Current uCode expects the code to be
-* loaded at 8k; locations below this are used for the stack.
-*/
-   intel_uncore_write(uncore, DMA_ADDR_1_LOW, 0x2000);
-   intel_uncore_write(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
-
-   /* Finally start the DMA */
-   intel_uncore_write(uncore, DMA_CTRL,
-  _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
-
-   return guc_wait_ucode(uncore);
-}
-/*
- * Load the GuC firmware blob into the MinuteIA.
+ * Called from intel_uc_init_hw() during driver load, resume from sleep and
+ * after a GPU reset.
+ *
+ * The firmware image should have already been fetched into memory, so only
+ * check that fetch succeeded, and then transfer the image to the h/w.
+ *
+ * Return: non-zero code on error
  */
-static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct intel_gt *gt)
+int intel_guc_fw_upload(struct intel_guc *guc)
 {
+   struct intel_gt *gt = guc_to_gt(guc);
struct intel_uncore *uncore = gt->uncore;
int ret;
 
-   GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
-
-   intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
-
guc_prepare_xfer(uncore);
 
/*
@@ -203,32 +158,24 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct 
intel_gt *gt)
 * by the DMA engine in one operation, whereas the RSA signature is
 * loaded via MMIO.
  

[Intel-gfx] [PATCH v3 0/8] uC fw path unification + misc clean-up

[Daniele Ceraolo Spurio]

I've now unified the no uC HW and no uC FW cases as well, as requested
by Michal. I've also added sanitization of the enable_guc parameter
when we don't have support for GuC/HuC because otherwise we end up paths
we shouldn't be in on a platform with no uC.

Cc: Michal Wajdeczko 
Cc: Chris Wilson 

Daniele Ceraolo Spurio (8):
  drm/i915/uc: Unify uC platform check
  drm/i915: Fix handling of non-supported uC
  drm/i915/uc: Unify uC FW selection
  drm/i915/uc: Unify uc_fw status tracking
  drm/i915/uc: Move xfer rsa logic to common function
  drm/i915/huc: Copy huc rsa only once
  drm/i915/uc: Plumb the gt through fw_upload
  drm/i915/uc: Unify uC firmware upload

 drivers/gpu/drm/i915/gt/intel_reset.c |   2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|   4 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 217 ++-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |   2 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc.c|  35 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc.h|   6 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 172 +
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  49 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 341 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  87 ++---
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c |   4 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   6 +-
 drivers/gpu/drm/i915/i915_drv.h   |  15 +-
 drivers/gpu/drm/i915/i915_gpu_error.c |   4 +-
 drivers/gpu/drm/i915/i915_irq.c   |   2 +-
 drivers/gpu/drm/i915/i915_pci.c   |   4 +-
 drivers/gpu/drm/i915/intel_device_info.h  |   2 +-
 drivers/gpu/drm/i915/intel_pm.c   |   4 +-
 drivers/gpu/drm/i915/intel_wopcm.c|   4 +-
 19 files changed, 433 insertions(+), 527 deletions(-)

-- 
2.22.0

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[Intel-gfx] [PATCH v3 4/8] drm/i915/uc: Unify uc_fw status tracking

[Daniele Ceraolo Spurio]

We currently track fetch and load status separately, but the 2 are
actually sequential in the uc lifetime (fetch must complete before we
can attempt the load!). Unifying the 2 variables we can better follow
the sequential states and improve our trackng of the uC state.

Also, sprinkle some GEM_BUG_ON to make sure we transition correctly
between states.

v2: rename states, add the running state (Michal), drop some logs in
the fetch path (Michal, Chris)

v3: re-rename states, extend early status check to all helpers (Michal)

Suggested-by: Michal Wajdeczko 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  4 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  6 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc.c|  8 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc.h|  5 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 10 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 78 +++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  | 63 ++-
 8 files changed, 92 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index ac6333ad7102..714e9892aaff 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -172,9 +172,9 @@ int intel_guc_suspend(struct intel_guc *guc);
 int intel_guc_resume(struct intel_guc *guc);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
 
-static inline bool intel_guc_is_loaded(struct intel_guc *guc)
+static inline bool intel_guc_is_running(struct intel_guc *guc)
 {
-   return intel_uc_fw_is_loaded(&guc->fw);
+   return intel_uc_fw_is_running(&guc->fw);
 }
 
 static inline int intel_guc_sanitize(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 99f44d8ae026..eec767383e92 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -230,5 +230,9 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
  */
 int intel_guc_fw_upload(struct intel_guc *guc)
 {
-   return intel_uc_fw_upload(&guc->fw, guc_fw_xfer);
+   int ret = intel_uc_fw_upload(&guc->fw, guc_fw_xfer);
+   if (!ret)
+   guc->fw.status = INTEL_UC_FIRMWARE_RUNNING;
+
+   return ret;
 }
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0f2a01365bc..b4238fe16a03 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -941,7 +941,7 @@ static void __guc_client_disable(struct intel_guc_client 
*client)
 * the case, instead of trying (in vain) to communicate with it, let's
 * just cleanup the doorbell HW and our internal state.
 */
-   if (intel_guc_is_loaded(client->guc))
+   if (intel_guc_is_running(client->guc))
destroy_doorbell(client);
else
__fini_doorbell(client);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index ab6c1564b6a7..a45976e56af7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -117,8 +117,8 @@ int intel_huc_auth(struct intel_huc *huc)
struct intel_guc *guc = >->uc.guc;
int ret;
 
-   if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-   return -ENOEXEC;
+   GEM_BUG_ON(!intel_uc_fw_is_loaded(&huc->fw));
+   GEM_BUG_ON(intel_huc_is_authenticated(huc));
 
ret = intel_guc_auth_huc(guc,
 intel_guc_ggtt_offset(guc, huc->rsa_data));
@@ -138,10 +138,12 @@ int intel_huc_auth(struct intel_huc *huc)
goto fail;
}
 
+   huc->fw.status = INTEL_UC_FIRMWARE_RUNNING;
+
return 0;
 
 fail:
-   huc->fw.load_status = INTEL_UC_FIRMWARE_FAIL;
+   huc->fw.status = INTEL_UC_FIRMWARE_FAIL;
 
DRM_ERROR("HuC: Authentication failed %d\n", ret);
return ret;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 9fa3d4629f2e..ea340f85bc46 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -56,4 +56,9 @@ static inline int intel_huc_sanitize(struct intel_huc *huc)
return 0;
 }
 
+static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
+{
+   return intel_uc_fw_is_running(&huc->fw);
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 3f672ea7456b..b1815abecf30 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -560,7 +560,7 @@ void intel_uc_fini_hw(struct intel_uc *uc)
 {
struct intel_guc *guc = &uc->guc;
 
-   if 

[Intel-gfx] [PATCH v3 5/8] drm/i915/uc: Move xfer rsa logic to common function

[Daniele Ceraolo Spurio]

The way we copy the RSA is the same for GuC and HuC, so we can move the
logic in a common function. this will also make any update needed for
local memory easier.

v2: return the number of copied bytes and check it (Chris)

Signed-off-by: Daniele Ceraolo Spurio 
Reviewed-by: Chris Wilson  #v1
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  7 +++
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 10 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 20 
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  1 +
 4 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index eec767383e92..385f6d38bf49 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -75,13 +75,12 @@ static void guc_prepare_xfer(struct intel_guc *guc)
 static void guc_xfer_rsa(struct intel_guc *guc)
 {
struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
-   struct intel_uc_fw *fw = &guc->fw;
-   struct sg_table *pages = fw->obj->mm.pages;
u32 rsa[UOS_RSA_SCRATCH_COUNT];
+   size_t copied;
int i;
 
-   sg_pcopy_to_buffer(pages->sgl, pages->nents,
-  rsa, sizeof(rsa), fw->rsa_offset);
+   copied = intel_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa));
+   GEM_BUG_ON(copied < sizeof(rsa));
 
for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index ba2e1a835830..472568843ccf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -36,17 +36,17 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
 
 static void huc_xfer_rsa(struct intel_huc *huc)
 {
-   struct intel_uc_fw *fw = &huc->fw;
-   struct sg_table *pages = fw->obj->mm.pages;
+   size_t copied;
 
/*
 * HuC firmware image is outside GuC accessible range.
 * Copy the RSA signature out of the image into
 * the perma-pinned region set aside for it
 */
-   sg_pcopy_to_buffer(pages->sgl, pages->nents,
-  huc->rsa_data_vaddr, fw->rsa_size,
-  fw->rsa_offset);
+   GEM_BUG_ON(huc->fw.rsa_size > huc->rsa_data->size);
+   copied = intel_uc_fw_copy_rsa(&huc->fw, huc->rsa_data_vaddr,
+ huc->rsa_data->size);
+   GEM_BUG_ON(copied < huc->fw.rsa_size);
 }
 
 static int huc_xfer_ucode(struct intel_huc *huc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 1e7df2c19265..f60129c17e40 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -458,6 +458,26 @@ void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw)
uc_fw->status = INTEL_UC_FIRMWARE_SELECTED;
 }
 
+/**
+ * intel_uc_fw_copy_rsa - copy fw RSA to buffer
+ *
+ * @uc_fw: uC firmware
+ * @dst: dst buffer
+ * @max_len: max number of bytes to copy
+ *
+ * Return: number of copied bytes.
+ */
+size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len)
+{
+   struct sg_table *pages = uc_fw->obj->mm.pages;
+   u32 size = min_t(u32, uc_fw->rsa_size, max_len);
+
+   GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw));
+
+   return sg_pcopy_to_buffer(pages->sgl, pages->nents,
+ dst, size, uc_fw->rsa_offset);
+}
+
 /**
  * intel_uc_fw_dump - dump information about uC firmware
  * @uc_fw: uC firmware
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
index f6aa2e3e4d1f..c843d00b1b75 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
@@ -176,6 +176,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
 int intel_uc_fw_init(struct intel_uc_fw *uc_fw);
 void intel_uc_fw_fini(struct intel_uc_fw *uc_fw);
 u32 intel_uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw);
+size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len);
 void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p);
 
 #endif
-- 
2.22.0

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 7/8] drm/i915/uc: Plumb the gt through fw_upload

[Daniele Ceraolo Spurio]

The gt is our new central structure for uc-related code, so we can use
that instead of jumping back to i915 via the fw object. Since we have it
in the upload function it is easy to pass it through the lower levels of
the xfer process instead of continuosly jumping via uc_fw->uc->gt, which
will also make things a bit cleaner for the next patch.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
Reviewed-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 35 +++
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 32 -
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 29 ++-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  8 --
 4 files changed, 48 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 385f6d38bf49..3ea0de6f4b73 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -42,10 +42,8 @@ void intel_guc_fw_init_early(struct intel_guc *guc)
intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, 
guc_to_gt(guc)->i915);
 }
 
-static void guc_prepare_xfer(struct intel_guc *guc)
+static void guc_prepare_xfer(struct intel_uncore *uncore)
 {
-   struct intel_gt *gt = guc_to_gt(guc);
-   struct intel_uncore *uncore = gt->uncore;
u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
 GUC_ENABLE_READ_CACHE_LOGIC |
 GUC_ENABLE_MIA_CACHING |
@@ -56,12 +54,12 @@ static void guc_prepare_xfer(struct intel_guc *guc)
/* Must program this register before loading the ucode with DMA */
intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
 
-   if (IS_GEN9_LP(gt->i915))
+   if (IS_GEN9_LP(uncore->i915))
intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, 
GT_DOORBELL_ENABLE);
else
intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, 
GT_DOORBELL_ENABLE);
 
-   if (IS_GEN(gt->i915, 9)) {
+   if (IS_GEN(uncore->i915, 9)) {
/* DOP Clock Gating Enable for GuC clocks */
intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
@@ -72,14 +70,14 @@ static void guc_prepare_xfer(struct intel_guc *guc)
 }
 
 /* Copy RSA signature from the fw image to HW for verification */
-static void guc_xfer_rsa(struct intel_guc *guc)
+static void guc_xfer_rsa(struct intel_uc_fw *guc_fw,
+struct intel_uncore *uncore)
 {
-   struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 rsa[UOS_RSA_SCRATCH_COUNT];
size_t copied;
int i;
 
-   copied = intel_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa));
+   copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
GEM_BUG_ON(copied < sizeof(rsa));
 
for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
@@ -155,10 +153,10 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
  * transfer between GTT locations. This functionality is left out of the API
  * for now as there is no need for it.
  */
-static int guc_xfer_ucode(struct intel_guc *guc)
+static int guc_xfer_ucode(struct intel_uc_fw *guc_fw,
+ struct intel_gt *gt)
 {
-   struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
-   struct intel_uc_fw *guc_fw = &guc->fw;
+   struct intel_uncore *uncore = gt->uncore;
unsigned long offset;
 
/*
@@ -169,7 +167,7 @@ static int guc_xfer_ucode(struct intel_guc *guc)
   guc_fw->header_size + guc_fw->ucode_size);
 
/* Set the source address for the new blob */
-   offset = intel_uc_fw_ggtt_offset(guc_fw) + guc_fw->header_offset;
+   offset = intel_uc_fw_ggtt_offset(guc_fw, gt->ggtt) + 
guc_fw->header_offset;
intel_uncore_write(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset));
intel_uncore_write(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset) & 
0x);
 
@@ -189,26 +187,25 @@ static int guc_xfer_ucode(struct intel_guc *guc)
 /*
  * Load the GuC firmware blob into the MinuteIA.
  */
-static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
+static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct intel_gt *gt)
 {
-   struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
-   struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
+   struct intel_uncore *uncore = gt->uncore;
int ret;
 
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
 
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 
-   guc_prepare_xfer(guc);
+   guc_prepare_xfer(uncore);
 
/*
 * Note that GuC needs the CSS header plus uKernel code to be copied
 * by the DMA engine in one operation, whereas the RSA signature is
 * loaded via MMIO.
 */
-   guc_xfer_rsa(guc);
+   guc_xfer_rsa(guc_fw, uncore);
 
-   ret = guc_xfer_ucode(guc);
+   re

[Intel-gfx] [PATCH v3 1/8] drm/i915/uc: Unify uC platform check

[Daniele Ceraolo Spurio]

We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC
and HAS_HUC, with only 1 exception. Since our HW always has either
both uC or neither of them, just replace all the checks with a unified
HAS_UC.

v2: use HAS_GT_UC (Michal)
v3: fix comment (Michal)

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Acked-by: Chris Wilson 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/gt/intel_reset.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c |  4 ++--
 drivers/gpu/drm/i915/i915_debugfs.c   |  6 +++---
 drivers/gpu/drm/i915/i915_drv.h   | 15 ++-
 drivers/gpu/drm/i915/i915_gpu_error.c |  4 ++--
 drivers/gpu/drm/i915/i915_irq.c   |  2 +-
 drivers/gpu/drm/i915/i915_pci.c   |  4 ++--
 drivers/gpu/drm/i915/intel_device_info.h  |  2 +-
 drivers/gpu/drm/i915/intel_pm.c   |  4 ++--
 drivers/gpu/drm/i915/intel_wopcm.c|  4 ++--
 13 files changed, 21 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 55e2ddcbd215..98c071fe532b 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -595,7 +595,7 @@ int intel_reset_guc(struct intel_gt *gt)
INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
int ret;
 
-   GEM_BUG_ON(!HAS_GUC(gt->i915));
+   GEM_BUG_ON(!HAS_GT_UC(gt->i915));
 
intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
ret = gen6_hw_domain_reset(gt, guc_domain);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 3dfa40fdbe99..87169e826747 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -80,7 +80,7 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
 
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
 
-   if (!HAS_GUC(i915)) {
+   if (!HAS_GT_UC(i915)) {
guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 543854c42d9d..ff6f7b157ecb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -74,7 +74,7 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
 
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 
-   if (!HAS_HUC(dev_priv)) {
+   if (!HAS_GT_UC(dev_priv)) {
huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 25a8ab3bd22c..bdb171c3f36e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -61,7 +61,7 @@ static int __get_platform_enable_guc(struct intel_uc *uc)
struct intel_uc_fw *huc_fw = &uc->huc.fw;
int enable_guc = 0;
 
-   if (!HAS_GUC(uc_to_gt(uc)->i915))
+   if (!HAS_GT_UC(uc_to_gt(uc)->i915))
return 0;
 
/* We don't want to enable GuC/HuC on pre-Gen11 by default */
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c 
b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
index 93f7c930ab18..371f7a60c987 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -134,7 +134,7 @@ static int igt_guc_clients(void *args)
struct intel_guc *guc;
int err = 0;
 
-   GEM_BUG_ON(!HAS_GUC(dev_priv));
+   GEM_BUG_ON(!HAS_GT_UC(dev_priv));
mutex_lock(&dev_priv->drm.struct_mutex);
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
@@ -226,7 +226,7 @@ static int igt_guc_doorbells(void *arg)
int i, err = 0;
u16 db_id;
 
-   GEM_BUG_ON(!HAS_GUC(dev_priv));
+   GEM_BUG_ON(!HAS_GT_UC(dev_priv));
mutex_lock(&dev_priv->drm.struct_mutex);
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6d3911469801..24787bb48c9f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1865,7 +1865,7 @@ static int i915_huc_load_status_info(struct seq_file *m, 
void *data)
intel_wakeref_t wakeref;
struct drm_printer p;
 
-   if (!HAS_HUC(dev_priv))
+   if (!HAS_GT_UC(dev_priv))
return -ENODEV;
 
p = drm_seq_file_printer(m);
@@ -1883,7 +1883,7 @@ static int i915_guc_load_status_info(struct seq_file *m, 
void *data)
intel_wakeref_t wakeref;
struct drm_printer p;
 
-   if (!HAS_GUC(dev_priv))
+   if (!HAS_GT_UC(dev_priv))
return -ENODEV;
 
p = drm_seq_file_printer(m

[Intel-gfx] [PATCH v3 3/8] drm/i915/uc: Unify uC FW selection

[Daniele Ceraolo Spurio]

Instead of having 2 identical functions for GuC and HuC firmware
selection, we can unify the selection logic and just use different lists
based on FW type.

Note that the revid is not relevant for current blobs, but the upcoming
CML will be identified as CFL rev 5, so by considering the revid we're
ready for that.

v2: rework blob list defs (Michal), add order check (Chris), fuse GuC
and HuC lists into one.

v3: remove difference between no uC HW and no uC FW, simplify related
selection code, check the whole fw list (Michal)

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Anusha Srivatsa 
Cc: Chris Wilson 
Reviewed-by: Chris Wilson  #v2
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  89 +---
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  91 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 156 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  24 +---
 4 files changed, 164 insertions(+), 196 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 17ce78240cf8..99f44d8ae026 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -31,90 +31,6 @@
 #include "intel_guc_fw.h"
 #include "i915_drv.h"
 
-#define __MAKE_GUC_FW_PATH(KEY) \
-   "i915/" \
-   __stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
-   __stringify(KEY##_GUC_FW_MAJOR) "." \
-   __stringify(KEY##_GUC_FW_MINOR) "." \
-   __stringify(KEY##_GUC_FW_PATCH) ".bin"
-
-#define SKL_GUC_FW_PREFIX skl
-#define SKL_GUC_FW_MAJOR 33
-#define SKL_GUC_FW_MINOR 0
-#define SKL_GUC_FW_PATCH 0
-#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
-MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
-
-#define BXT_GUC_FW_PREFIX bxt
-#define BXT_GUC_FW_MAJOR 33
-#define BXT_GUC_FW_MINOR 0
-#define BXT_GUC_FW_PATCH 0
-#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
-MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
-
-#define KBL_GUC_FW_PREFIX kbl
-#define KBL_GUC_FW_MAJOR 33
-#define KBL_GUC_FW_MINOR 0
-#define KBL_GUC_FW_PATCH 0
-#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
-MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
-
-#define GLK_GUC_FW_PREFIX glk
-#define GLK_GUC_FW_MAJOR 33
-#define GLK_GUC_FW_MINOR 0
-#define GLK_GUC_FW_PATCH 0
-#define GLK_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(GLK)
-MODULE_FIRMWARE(GLK_GUC_FIRMWARE_PATH);
-
-#define ICL_GUC_FW_PREFIX icl
-#define ICL_GUC_FW_MAJOR 33
-#define ICL_GUC_FW_MINOR 0
-#define ICL_GUC_FW_PATCH 0
-#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
-MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
-
-static void guc_fw_select(struct intel_uc_fw *guc_fw)
-{
-   struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
-   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
-   GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
-
-   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
-
-   if (!HAS_GT_UC(i915))
-   return;
-
-   if (i915_modparams.guc_firmware_path) {
-   guc_fw->path = i915_modparams.guc_firmware_path;
-   guc_fw->major_ver_wanted = 0;
-   guc_fw->minor_ver_wanted = 0;
-   } else if (IS_ICELAKE(i915)) {
-   guc_fw->path = ICL_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
-   } else if (IS_GEMINILAKE(i915)) {
-   guc_fw->path = GLK_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
-   } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
-   guc_fw->path = KBL_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
-   } else if (IS_BROXTON(i915)) {
-   guc_fw->path = BXT_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
-   } else if (IS_SKYLAKE(i915)) {
-   guc_fw->path = SKL_GUC_FIRMWARE_PATH;
-   guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
-   guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
-   }
-
-   if (guc_fw->path)
-   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
-}
-
 /**
  * intel_guc_fw_init_early() - initializes GuC firmware struct
  * @guc: intel_guc struct
@@ -123,10 +39,7 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
  */
 void intel_guc_fw_init_early(struct intel_guc *guc)
 {
-   struct intel_uc_fw *guc_fw = &guc->fw;
-
-   intel_uc_fw_init_early(guc_fw, INTEL_UC_FW_TYPE_GUC);
-   guc_fw_select(guc_fw);
+   intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, 
guc_to_gt(guc)->i915);
 }
 
 static void guc_prepare_xfer(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c 
b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3 2/8] drm/i915: Fix handling of non-supported uC

[Daniele Ceraolo Spurio]

There are 2 issues around handling of missing uC support:

- We treat lack of uC HW and lack of uC FW definition as 2 different
  cases, but both of them mean that we don't support the uC on the
  platform we're running on.

- We rely on the modparam to decide if we can take uC paths or not, but
  we don't sanitize it if it is set incorrectly on platform with no uC
  support.

To fix both of them, unify the 2 cases in a single one and sanitize the
modparam on invalid configuration (after printing an error message).
The log has been adapted as well, since the user doesn't care why we
don't support GuC/HuC (no HW or no FW), just that we do not. Developers
can easily find the answer based on the platform, so we can simplify the
log.

Correcting the modparam has been preferred over failing the load since
this is what we usually do for non-supported feature (e.g. the now gone
enable_ppgtt would fall back to the highest supported PPGTT mode if the
selected one was not available).

Note that this patch purposely doesn't change the behavior for platforms
that do have uC support, in which case we will still fail if enable_guc
is set and the firmware is not available on the system.

Suggested-by: Michal Wajdeczko 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 11 ---
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 11 ---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 37 ---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  8 -
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  5 ---
 5 files changed, 31 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 87169e826747..17ce78240cf8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -80,12 +80,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
 
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
 
-   if (!HAS_GT_UC(i915)) {
-   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
-   return;
-   }
+   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
 
-   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
+   if (!HAS_GT_UC(i915))
+   return;
 
if (i915_modparams.guc_firmware_path) {
guc_fw->path = i915_modparams.guc_firmware_path;
@@ -112,6 +110,9 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
}
+
+   if (guc_fw->path)
+   guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index ff6f7b157ecb..c3a7bd57fb55 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -74,12 +74,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
 
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 
-   if (!HAS_GT_UC(dev_priv)) {
-   huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
-   return;
-   }
+   huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
 
-   huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
+   if (!HAS_GT_UC(dev_priv))
+   return;
 
if (i915_modparams.huc_firmware_path) {
huc_fw->path = i915_modparams.huc_firmware_path;
@@ -106,6 +104,9 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
}
+
+   if (huc_fw->path)
+   huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index bdb171c3f36e..3f672ea7456b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -68,7 +68,7 @@ static int __get_platform_enable_guc(struct intel_uc *uc)
if (INTEL_GEN(uc_to_gt(uc)->i915) < 11)
return 0;
 
-   if (intel_uc_fw_is_selected(guc_fw) && intel_uc_fw_is_selected(huc_fw))
+   if (intel_uc_fw_supported(guc_fw) && intel_uc_fw_supported(huc_fw))
enable_guc |= ENABLE_GUC_LOAD_HUC;
 
return enable_guc;
@@ -123,26 +123,28 @@ static void sanitize_options_early(struct intel_uc *uc)
 yesno(intel_uc_is_using_huc(uc)));
 
/* Verify GuC firmware availability */
-   if (intel_uc_is_using_guc(uc) && !intel_uc_fw_is_selected(guc_fw)) {
-   DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
-"enable_guc", i915_modparams.enable_guc,
-!intel_uc_fw_supported(guc_fw) ?
-   "no GuC hardware" 

Re: [Intel-gfx] [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake

[Lucas De Marchi]

On Thu, Jul 18, 2019 at 10:09:27AM -0700, Daniele Ceraolo Spurio wrote:



On 7/18/19 6:08 AM, Ville Syrjälä wrote:

On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:

From: Tomasz Lis 

The MOCS table is published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.

Two of the 3 legacy entries used for gen9 are no longer expected to work.
Although we are changing the gen11 table, those changes are supposed to
be backward compatible since we are only touching previously undefined
entries.

Cc: Joonas Lahtinen 
Cc: Mika Kuoppala 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Tomasz Lis 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c 
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 290a5e9b90b9..259e7bec0a63 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
 #define GEN11_NUM_MOCS_ENTRIES 64  /* 63-64 are reserved, but configured. */
 /* (e)LLC caching options */
+/*
+ * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
+ * the same as LE_UC
+ */
 #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
 #define LE_1_UC_LE_CACHEABILITY(1)
 #define LE_2_WT_LE_CACHEABILITY(2)
@@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
  * of bspec.
  *
  * Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon.  For the time
- * being they will be initialized to PTE.
+ * userspace is concerned and shouldn't be relied upon.  For Gen < 12
+ * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
+ * PTE. We use the same value, but that actually means Uncached.
  *
  * The last two entries are reserved by the hardware. For ICL+ they
  * should be initialized according to bspec and never used, for older
@@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry 
broxton_mocs_table[] = {
 };
 #define GEN11_MOCS_ENTRIES \
-   /* Base - Uncached (Deprecated) */ \
+   /* Gen11: Base - Uncached (Deprecated) */ \
+   /* Gen12+: Base - Error (Reserved for Non-Use) */ \
MOCS_ENTRY(I915_MOCS_UNCACHED, \
   LE_1_UC | LE_TC_1_LLC, \
   L3_1_UC), \
/* Base - L3 + LeCC:PAT (Deprecated) */ \
+   /* Gen12+: Base - Reserved */ \
MOCS_ENTRY(I915_MOCS_PTE, \
   LE_0_PAGETABLE | LE_TC_1_LLC, \
   L3_3_WB), \
@@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry 
broxton_mocs_table[] = {
MOCS_ENTRY(23, \
   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
   L3_3_WB), \
+   /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \


Why is this marked as reserved? From the looks of things 48-61 should
just be normal entries that userspace can select to get HDC L1$. And
looks like icl already has that stuff. So someone should probably figure
out if Mesa/etc. can make use of the HDC L1$, and if so we should add
the relevant MOCS entries for icl as well.


Here the reserved terminology is indeed misleading. The 48-59 range is 
a "special" range where L1 usage is implicitly enabled by the HW, as 
there is no explicit L1 toggle in the MOCS registers. The reserved 
here means that the range shouldn't be used for "normal" MOCS 
settings, but SW can freely use these entries as needed. Similarly, 
MOCS 60 and 61 are reserved for other special purposes, but are still 
usable by SW. The only entries SW shouldn't touch are 62 and 63.


Regarding ICL, Gen11 HW doesn't have the capability so no new entries 
are required there.





+   MOCS_ENTRY(48, \
+  LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+  L3_3_WB), \
+   /* Gen12+: HW Reserved - HW Special Case (CCS) */ \


The specs have MOCS 49-51 defined as well.


humn... it seems they got added later.

I'm not sure anymore if we should update igt so it doesn't expect those
entries to be set to PTE or if we should stop reusing the same table for
ICL and TGL. Spec doesn't mention the compatibility of this table with
gen 11 anymore. Thoughts?


Lucas De Marchi



Daniele


+   MOCS_ENTRY(60, \
+  LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+  L3_1_UC), \
+   /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
+   MOCS_ENTRY(61, \
+  LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
+  L3_3_WB), \
/* HW Reserved - SW program but never use */ \
MOCS_ENTRY(62, \
   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
--
2.21.0



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Re: [Intel-gfx] [PATCH v7 2/4] drm/panel: set display info in panel attach

[dbasehore .]

Hi Sam, thanks for pointing out the potential conflict.

On Tue, Jul 23, 2019 at 2:19 AM Sam Ravnborg  wrote:
>
> Hi Derek.
>
> On Tue, Jul 09, 2019 at 07:16:57PM -0700, Derek Basehore wrote:
> > Devicetree systems can set panel orientation via a panel binding, but
> > there's no way, as is, to propagate this setting to the connector,
> > where the property need to be added.
> > To address this, this patch sets orientation, as well as other fixed
> > values for the panel, in the drm_panel_attach function. These values
> > are stored from probe in the drm_panel struct.
>
> This approch seems to conflict with work done by Laurent where the
> ownership/creation of the connector will be moved to the display controller.
>
> If I understand it correct then there should not be a 1:1 relation
> between a panel and a connector anymore.


Can you point me to this work? I still see the lone drm_display_info
struct in the drm_connector struct. This seems to indicate that the
kernel still assume one display per connector.

>
> We should not try to work in two different directions with this.
> Laurent, can you comment on this?
>
> If we move forard with this patch, then all fields in drm_panel needs
> kernel-doc - preferably inline.
>
> Sam
>
> >
> > Signed-off-by: Derek Basehore 
> > ---
> >  drivers/gpu/drm/drm_panel.c | 28 
> >  include/drm/drm_panel.h | 14 ++
> >  2 files changed, 42 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
> > index 169bab54d52d..ca01095470a9 100644
> > --- a/drivers/gpu/drm/drm_panel.c
> > +++ b/drivers/gpu/drm/drm_panel.c
> > @@ -104,11 +104,23 @@ EXPORT_SYMBOL(drm_panel_remove);
> >   */
> >  int drm_panel_attach(struct drm_panel *panel, struct drm_connector 
> > *connector)
> >  {
> > + struct drm_display_info *info;
> > +
> >   if (panel->connector)
> >   return -EBUSY;
> >
> >   panel->connector = connector;
> >   panel->drm = connector->dev;
> > + info = &connector->display_info;
> > + info->width_mm = panel->width_mm;
> > + info->height_mm = panel->height_mm;
> > + info->bpc = panel->bpc;
> > + info->panel_orientation = panel->orientation;
> > + info->bus_flags = panel->bus_flags;
> > + if (panel->bus_formats)
> > + drm_display_info_set_bus_formats(&connector->display_info,
> > +  panel->bus_formats,
> > +  panel->num_bus_formats);
> >
> >   return 0;
> >  }
> > @@ -128,6 +140,22 @@ EXPORT_SYMBOL(drm_panel_attach);
> >   */
> >  int drm_panel_detach(struct drm_panel *panel)
> >  {
> > + struct drm_display_info *info;
> > +
> > + if (!panel->connector)
> > + goto out;
> > +
> > + info = &panel->connector->display_info;
> > + info->width_mm = 0;
> > + info->height_mm = 0;
> > + info->bpc = 0;
> > + info->panel_orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
> > + info->bus_flags = 0;
> > + kfree(info->bus_formats);
> > + info->bus_formats = NULL;
> > + info->num_bus_formats = 0;
> > +
> > +out:
> >   panel->connector = NULL;
> >   panel->drm = NULL;
> >
> > diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> > index fc7da55f41d9..a6a881b987dd 100644
> > --- a/include/drm/drm_panel.h
> > +++ b/include/drm/drm_panel.h
> > @@ -39,6 +39,8 @@ enum drm_panel_orientation;
> >   * struct drm_panel_funcs - perform operations on a given panel
> >   * @disable: disable panel (turn off back light, etc.)
> >   * @unprepare: turn off panel
> > + * @detach: detach panel->connector (clear internal state, etc.)
> > + * @attach: attach panel->connector (update internal state, etc.)
> >   * @prepare: turn on panel and perform set up
> >   * @enable: enable panel (turn on back light, etc.)
> >   * @get_modes: add modes to the connector that the panel is attached to and
> > @@ -95,6 +97,18 @@ struct drm_panel {
> >
> >   const struct drm_panel_funcs *funcs;
> >
> > + /*
> > +  * panel information to be set in the connector when the panel is
> > +  * attached.
> > +  */
> > + unsigned int width_mm;
> > + unsigned int height_mm;
> > + unsigned int bpc;
> > + int orientation;
> > + const u32 *bus_formats;
> > + unsigned int num_bus_formats;
> > + u32 bus_flags;
> > +
> >   struct list_head list;
> >  };
> >
> > --
> > 2.22.0.410.gd8fdbe21b5-goog
> >
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Fix GuC documentation links

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Fix GuC documentation links
URL   : https://patchwork.freedesktop.org/series/64190/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13740_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_13740_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@rcs0-s3:
- shard-apl:  [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 
similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-apl7/igt@gem_ctx_isolat...@rcs0-s3.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb:  [PASS][3] -> [SKIP][4] ([fdo#109271])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-snb6/igt@i915_pm_rc6_reside...@rc6-accuracy.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-snb1/igt@i915_pm_rc6_reside...@rc6-accuracy.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw:  [PASS][5] -> [FAIL][6] ([fdo#105767])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw7/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-hsw:  [PASS][7] -> [INCOMPLETE][8] ([fdo#103540])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-hsw5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
- shard-skl:  [PASS][9] -> [FAIL][10] ([fdo#105363])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-skl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
- shard-snb:  [PASS][11] -> [INCOMPLETE][12] ([fdo#105411])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-snb7/igt@kms_f...@flip-vs-suspend.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-snb1/igt@kms_f...@flip-vs-suspend.html

  * igt@kms_flip_tiling@flip-changes-tiling-yf:
- shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713]) +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb7/igt@kms_flip_til...@flip-changes-tiling-yf.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-iclb7/igt@kms_flip_til...@flip-changes-tiling-yf.html

  * igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl:  [PASS][15] -> [FAIL][16] ([fdo#108134])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip_til...@flip-to-x-tiled.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-skl10/igt@kms_flip_til...@flip-to-x-tiled.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +5 similar 
issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167] / [fdo#110378])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-rte.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#106978] / 
[fdo#107713])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-onoff.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/shard-iclb7/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl:  [PASS][23] -> [INCOMPLETE][24] ([fdo#103665])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev 2)

[Summers, Stuart]

On Wed, 2019-07-24 at 21:01 +, Patchwork wrote:
> == Series Details ==
> 
> Series: Refactor to expand subslice mask (rev 2)
> URL   : https://patchwork.freedesktop.org/series/64188/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13739_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_13739_full absolutely
> need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the
> changes
>   introduced in Patchwork_13739_full, please notify your bug team to
> allow them
>   to document this new failure mode, which will reduce false
> positives in CI.
> 
>   
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in
> Patchwork_13739_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_query@query-topology-matches-eu-total:
> - shard-hsw:  [PASS][1] -> [FAIL][2] +3 similar issues
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw7/igt@i915_qu...@query-topology-matches-eu-total.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw1/igt@i915_qu...@query-topology-matches-eu-total.html

Looks like this series is causing a regression on HSW. I'll fix this
issue before posting the next revision. For now, please hold off on
review.

Thanks,
Stuart

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_13739_full that come from
> known issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_ctx_isolation@rcs0-s3:
> - shard-apl:  [PASS][3] -> [DMESG-WARN][4] ([fdo#108566])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html
> 
>   * igt@gem_tiled_swapping@non-threaded:
> - shard-apl:  [PASS][5] -> [DMESG-WARN][6] ([fdo#108686])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl5/igt@gem_tiled_swapp...@non-threaded.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl7/igt@gem_tiled_swapp...@non-threaded.html
> 
>   * igt@i915_pm_rc6_residency@rc6-accuracy:
> - shard-kbl:  [PASS][7] -> [SKIP][8] ([fdo#109271])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html
> 
>   * igt@i915_query@query-topology-coherent-slice-mask:
> - shard-hsw:  [PASS][9] -> [SKIP][10] ([fdo#109271])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@i915_qu...@query-topology-coherent-slice-mask.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw5/igt@i915_qu...@query-topology-coherent-slice-mask.html
> 
>   * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
> - shard-hsw:  [PASS][11] -> [FAIL][12] ([fdo#103355])
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw1/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-skl:  [PASS][13] -> [FAIL][14] ([fdo#105363])
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
> 
>   * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-kbl:  [PASS][15] -> [DMESG-WARN][16]
> ([fdo#108566]) +2 similar issues
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_f...@flip-vs-suspend-interruptible.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_f...@flip-vs-suspend-interruptible.html
> 
>   * igt@kms_flip_tiling@flip-to-x-tiled:
> - shard-skl:  [PASS][17] -> [FAIL][18] ([fdo#108134])
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip_til...@flip-to-x-tiled.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_flip_til...@flip-to-x-tiled.html
> 
>   * igt@kms
> _frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
> - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7
> similar issues
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-render.ht

[Intel-gfx] ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev 2)

[Patchwork]

== Series Details ==

Series: Refactor to expand subslice mask (rev 2)
URL   : https://patchwork.freedesktop.org/series/64188/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13739_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_13739_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13739_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_13739_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_query@query-topology-matches-eu-total:
- shard-hsw:  [PASS][1] -> [FAIL][2] +3 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw7/igt@i915_qu...@query-topology-matches-eu-total.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw1/igt@i915_qu...@query-topology-matches-eu-total.html

  
Known issues


  Here are the changes found in Patchwork_13739_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@rcs0-s3:
- shard-apl:  [PASS][3] -> [DMESG-WARN][4] ([fdo#108566])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html

  * igt@gem_tiled_swapping@non-threaded:
- shard-apl:  [PASS][5] -> [DMESG-WARN][6] ([fdo#108686])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl5/igt@gem_tiled_swapp...@non-threaded.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl7/igt@gem_tiled_swapp...@non-threaded.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl:  [PASS][7] -> [SKIP][8] ([fdo#109271])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html

  * igt@i915_query@query-topology-coherent-slice-mask:
- shard-hsw:  [PASS][9] -> [SKIP][10] ([fdo#109271])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@i915_qu...@query-topology-coherent-slice-mask.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw5/igt@i915_qu...@query-topology-coherent-slice-mask.html

  * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw:  [PASS][11] -> [FAIL][12] ([fdo#103355])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw1/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl:  [PASS][13] -> [FAIL][14] ([fdo#105363])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl:  [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_f...@flip-vs-suspend-interruptible.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_f...@flip-vs-suspend-interruptible.html

  * igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl:  [PASS][17] -> [FAIL][18] ([fdo#108134])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip_til...@flip-to-x-tiled.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_flip_til...@flip-to-x-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7 similar 
issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-render.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-skl:  [PASS][21] -> [INCOMPLETE][22] ([fdo#104108])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl6/igt@kms_frontbuffer_track...@fbc-suspend.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwor

Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915

[Souza, Jose]

On Wed, 2019-07-24 at 22:39 +0200, Paul Bolle wrote:
> Hi Jose,
> 
> Souza, Jose schreef op wo 24-07-2019 om 20:27 [+]:
> > We fixed the patch instead of revert it, it is merged on drm-tip
> > and on
> > his way to linux-stable.
> 
> That should be (drm-tip) commit b5ea9c933700 ("drm/i915/vbt: Fix VBT
> parsing
> for the PSR section"). Correct?

Exactly

> 
> > Huge thanks again
> 
> You're welcome.
> 
> 
> Paul Bolle
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Make caps.scheduler static

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Make caps.scheduler static
URL   : https://patchwork.freedesktop.org/series/64186/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13738_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_13738_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13738_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_13738_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_plane@plane-position-hole-pipe-c-planes:
- shard-glk:  [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-glk4/igt@kms_pl...@plane-position-hole-pipe-c-planes.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-glk4/igt@kms_pl...@plane-position-hole-pipe-c-planes.html

  
Known issues


  Here are the changes found in Patchwork_13738_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl:  [PASS][3] -> [SKIP][4] ([fdo#109271])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-kbl2/igt@i915_pm_rc6_reside...@rc6-accuracy.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl:  [PASS][5] -> [FAIL][6] ([fdo#105363])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-skl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +9 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#106978] / 
[fdo#107713])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-indfb-draw-render.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103166])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-x.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-x.html

  * igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109642] / [fdo#111068])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-iclb3/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr@psr2_dpms.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-iclb4/igt@kms_psr@psr2_dpms.html

  
 Possible fixes 

  * igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][17] ([fdo#110854]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@gem_exec_balan...@smoke.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-iclb1/igt@gem_exec_balan...@smoke.html

  * igt@i915_pm_rpm@i2c:
- shard-hsw:  [FAIL][19] ([fdo#104097]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@i915_pm_...@i2c.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-hsw7/igt@i915_pm_...@i2c.html

  * igt@i915_selftest@live_hangcheck:
- shard-iclb: [INCOMPLETE][21] ([fdo#107713] / [fdo#108569]) -> 
[PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@i915_selftest@live_hangcheck.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/shard-iclb8/igt@i915_selftest@live_hangcheck.html

  * igt@kms_frontbuffer_trac

Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915

[Paul Bolle]

Hi Jose,

Souza, Jose schreef op wo 24-07-2019 om 20:27 [+]:
> We fixed the patch instead of revert it, it is merged on drm-tip and on
> his way to linux-stable.

That should be (drm-tip) commit b5ea9c933700 ("drm/i915/vbt: Fix VBT parsing
for the PSR section"). Correct?

> Huge thanks again

You're welcome.


Paul Bolle

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Flush all user surfaces prior to first use

[Francisco Jerez]

Chris Wilson  writes:

> Since userspace has the ability to bypass the CPU cache from within its
> unprivileged command stream, we have to flush the CPU cache to memory
> in order to overwrite the previous contents on creation.
>
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: stablevger.kernel.org
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 26 ++-
>  1 file changed, 7 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> index d2a1158868e7..f752b326d399 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> @@ -459,7 +459,6 @@ i915_gem_object_create_shmem(struct drm_i915_private 
> *i915, u64 size)
>  {
>   struct drm_i915_gem_object *obj;
>   struct address_space *mapping;
> - unsigned int cache_level;
>   gfp_t mask;
>   int ret;
>  
> @@ -498,24 +497,13 @@ i915_gem_object_create_shmem(struct drm_i915_private 
> *i915, u64 size)
>   obj->write_domain = I915_GEM_DOMAIN_CPU;
>   obj->read_domains = I915_GEM_DOMAIN_CPU;
>  
> - if (HAS_LLC(i915))
> - /* On some devices, we can have the GPU use the LLC (the CPU
> -  * cache) for about a 10% performance improvement
> -  * compared to uncached.  Graphics requests other than
> -  * display scanout are coherent with the CPU in
> -  * accessing this cache.  This means in this mode we
> -  * don't need to clflush on the CPU side, and on the
> -  * GPU side we only need to flush internal caches to
> -  * get data visible to the CPU.
> -  *
> -  * However, we maintain the display planes as UC, and so
> -  * need to rebind when first used as such.
> -  */
> - cache_level = I915_CACHE_LLC;
> - else
> - cache_level = I915_CACHE_NONE;
> -
> - i915_gem_object_set_cache_coherency(obj, cache_level);
> + /*
> +  * Note that userspace has control over cache-bypass
> +  * via its command stream, so even on LLC architectures
> +  * we have to flush out the CPU cache to memory to
> +  * clear previous contents.
> +  */
> + i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
>  

I'm not sure if you've seen my comments about this in an internal thread
you were CC'ed to: I don't think this patch will have the intended
effect.  The various clflushes this could trigger before the first use
of the buffer are conditional on "obj->cache_dirty &
~obj->cache_coherent", which will always be false on LLC platforms
AFAICT, because on those platforms i915_gem_object_set_cache_coherency()
will always set bit 0 of obj->cache_coherent.

I attached a patch with the same purpose as this to that internal thread
which doesn't suffer from this bug, but my patch was specific to Gen12+
where cache bypass is actually exposed to userspace.  Why is this patch
enabling the flushes for all platforms?  AFAICT the only currently
exposed MOCS entries that might allow userspace to bypass the LLC are 16
and 17 on Gen11, which enable the SCF MOCS table bit, which is marked
"S/W should NOT set this field in client platforms" in the Gen9 docs,
and according to the Gen10-11 docs is "Not supported".  Does LLC bypass
actually work on ICL?  I doubt it but it might have been fixed in some
other Gen11 project.  Shouldn't this change be conditional on the
platform supporting LLC bypass?  Do you want me to resend my patch here
with the Gen12+ checks changed to Gen11+?

>   trace_i915_gem_object_create(obj);
>  
> -- 
> 2.22.0
>
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Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915

[Souza, Jose]

Hi Paul

We fixed the patch instead of revert it, it is merged on drm-tip and on
his way to linux-stable.

Huge thanks again

On Wed, 2019-07-24 at 21:23 +0200, Paul Bolle wrote:
> Hi Jose,
> 
> James Bottomley schreef op do 18-07-2019 om 06:29 [+0900]:
> > On Wed, 2019-07-17 at 23:27 +0200, Paul Bolle wrote:
> > > I've just reached a day of uptime with your revert. (The proper
> > > uptime is just a fraction of a day, this being a laptop.) Anyhow,
> > > no
> > > screen freezes occurred during this day.
> > 
> > I'm afraid my status is that I'm in Tokyo doing conference
> > presentations (and kernel demos) so I'm a bit reluctant to mess
> > with my
> > setup until I finish everything on Friday, but I will test it after
> > then, promise.
> 
> By now I'm testing this for a week (currently on top of 5.2.2). Still
> no
> freezes whatsoever. 
> 
> So what's the status of this revert? Unless this is something pretty
> obscure
> that for some odd reason only James and I are able to hit it would be
> nice to
> get this into stable before the main distros switch over to 5.2.y.
> 
> Thanks,
> 
> 
> Paul Bolle
> 
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/uc: Update drawing for firmware layout

[Daniele Ceraolo Spurio]

On 7/24/19 1:09 PM, Michal Wajdeczko wrote:
On Wed, 24 Jul 2019 19:44:46 +0200, Daniele Ceraolo Spurio 
 wrote:





On 7/24/19 10:34 AM, Michal Wajdeczko wrote:

Sphinx was rendering firmware layout as html table, but since
we want to add sizes relations switch to plain text graphics.
 Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
---
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 25 +---
  1 file changed, 11 insertions(+), 14 deletions(-)
 diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h

index 3ca535534151..e25271aac765 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -11,21 +11,18 @@
  /**
   * DOC: GuC Firmware Layout
   *
- * The GuC firmware layout looks like this:
+ * The GuC firmware layout looks like this::
   *
- * +---+
- * | uc_css_header |
- * |   |
- * | contains major/minor version  |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * |  modulus key  |
- * +---+
- * |  exponent val |
- * +---+
+ *  
+==+
+ *  |  Firmware 
blob   |
+ *  
+===+===++++
+ *  |  CSS header   | uCode |    key |  modulus   |  
exponent  |
+ *  
+===+===++++


What about the RSA?


key == RSA key == RSA signature

I followed notation from our header definition which uses "key_size"
but maybe it was too brave. What about "RSA key" to have a match ?



Works for me.

Daniele



Daniele

+ *   <-header size-> <---header size continued 
--->
+ *   <--- size 
--->

+ *   <-key size->
+ *    <-mod size->
+ * 
<-exp size->

   *
   * The firmware may or may not have modulus key and exponent data. 
The header,
   * uCode and RSA signature are must-have components that will be 
used by driver.

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Re: [Intel-gfx] [PATCH 3/3] drm/i915/uc: Update drawing for firmware layout

[Michal Wajdeczko]

On Wed, 24 Jul 2019 19:44:46 +0200, Daniele Ceraolo Spurio  
 wrote:





On 7/24/19 10:34 AM, Michal Wajdeczko wrote:

Sphinx was rendering firmware layout as html table, but since
we want to add sizes relations switch to plain text graphics.
 Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
---
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 25 +---
  1 file changed, 11 insertions(+), 14 deletions(-)
 diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h  
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h

index 3ca535534151..e25271aac765 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -11,21 +11,18 @@
  /**
   * DOC: GuC Firmware Layout
   *
- * The GuC firmware layout looks like this:
+ * The GuC firmware layout looks like this::
   *
- * +---+
- * | uc_css_header |
- * |   |
- * | contains major/minor version  |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * |  modulus key  |
- * +---+
- * |  exponent val |
- * +---+
+ *   
+==+
+ *  |  Firmware  
blob   |
+ *   
+===+===++++
+ *  |  CSS header   | uCode |key |  modulus   |   
exponent  |
+ *   
+===+===++++


What about the RSA?


key == RSA key == RSA signature

I followed notation from our header definition which uses "key_size"
but maybe it was too brave. What about "RSA key" to have a match ?



Daniele

+ *   <-header size-> <---header size continued  
--->
+ *   <--- size  
--->

+ *   <-key size->
+ *<-mod size->
+ *  
<-exp size->

   *
   * The firmware may or may not have modulus key and exponent data.  
The header,
   * uCode and RSA signature are must-have components that will be used  
by driver.

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Re: [Intel-gfx] [PATCH 2/3] drm/i915/uc: Move uc firmware layout definitions to dedicated file

[Daniele Ceraolo Spurio]

On 7/24/19 1:01 PM, Michal Wajdeczko wrote:
On Wed, 24 Jul 2019 19:50:37 +0200, Daniele Ceraolo Spurio 
 wrote:





On 7/24/19 10:34 AM, Michal Wajdeczko wrote:

Generic uc firmware layout definitions are unlikely to change and
are separate to other GuC specific definitions.
 Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 


Keeping things that apply to HuC as well in a generic file seems 
sensible to me.



---
  Documentation/gpu/i915.rst   |  2 +-
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  | 70 -
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  1 +
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 81 
  4 files changed, 83 insertions(+), 71 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
 diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c2173d120492..366cb7f46d17 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -448,7 +448,7 @@ GuC-based command submission
  GuC Firmware Layout
  ---
  -.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
 :doc: GuC Firmware Layout


This is now generic uC firmware layout


    GuC Address Space
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

index 30cca3a29323..06a9bdfb0faf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -121,76 +121,6 @@
    #define GUC_CTL_MAX_DWORDS    (SOFT_SCRATCH_COUNT - 2) /* 
[1..14] */

  -/**
- * DOC: GuC Firmware Layout
- *
- * The GuC firmware layout looks like this:
- *
- * +---+
- * | uc_css_header |
- * |   |
- * | contains major/minor version  |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * |  modulus key  |
- * +---+
- * |  exponent val |
- * +---+
- *
- * The firmware may or may not have modulus key and exponent data. 
The header,
- * uCode and RSA signature are must-have components that will be 
used by driver.
- * Length of each components, which is all in dwords, can be found 
in header.
- * In the case that modulus and exponent are not present in fw, 
a.k.a truncated

- * image, the length value still appears in header.
- *
- * Driver will do some basic fw size validation based on the 
following rules:

- *
- * 1. Header, uCode and RSA are must-have components.
- * 2. All firmware components, if they present, are in the sequence 
illustrated

- *    in the layout table above.
- * 3. Length info of each component can be found in header, in dwords.
- * 4. Modulus and exponent key are not required by driver. They may 
not appear

- *    in fw. So driver will load a truncated firmware in this case.
- *
- * HuC firmware layout is same as GuC firmware.
- * Only HuC version information is saved in a different way.
- */
-
-struct uc_css_header {
-    u32 module_type;
-    /* header_size includes all non-uCode bits, including 
css_header, rsa

- * key, modulus key and exponent data. */
-    u32 header_size_dw;
-    u32 header_version;
-    u32 module_id;
-    u32 module_vendor;
-    u32 date;
-#define CSS_DATE_DAY    (0xFF << 0)
-#define CSS_DATE_MONTH    (0xFF << 8)
-#define CSS_DATE_YEAR    (0x << 16)
-    u32 size_dw; /* uCode plus header_size_dw */
-    u32 key_size_dw;
-    u32 modulus_size_dw;
-    u32 exponent_size_dw;
-    u32 time;
-#define CSS_TIME_HOUR    (0xFF << 0)
-#define CSS_DATE_MIN    (0xFF << 8)
-#define CSS_DATE_SEC    (0x << 16)
-    char username[8];
-    char buildnumber[12];
-    u32 sw_version;
-#define CSS_SW_VERSION_GUC_MAJOR    (0xFF << 16)
-#define CSS_SW_VERSION_GUC_MINOR    (0xFF << 8)
-#define CSS_SW_VERSION_GUC_PATCH    (0xFF << 0)
-#define CSS_SW_VERSION_HUC_MAJOR    (0x << 16)
-#define CSS_SW_VERSION_HUC_MINOR    (0x << 0)
-    u32 reserved[14];
-    u32 header_info;
-} __packed;
-
  /* Work item for submitting workloads into work queue of GuC. */
  struct guc_wq_item {
  u32 header;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

index 8ce7210907c0..d5cb19b4e5c1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -27,6 +27,7 @@
  #include 
    #include "intel_uc_fw.h"
+#include "intel_uc_fw_abi.h"
  #include "i915_drv.h"
    /**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h

new file mode 100644
index ..3ca535534151
--- /dev/null
+++ b/drivers/gpu

Re: [Intel-gfx] [PATCH] drm/i915: Disable atomics in L3 for gen9

[Francisco Jerez]

Chris Wilson  writes:

> Quoting Francisco Jerez (2019-07-23 23:19:13)
>> Chris Wilson  writes:
>> 
>> > Quoting Tvrtko Ursulin (2019-07-22 12:41:36)
>> >> 
>> >> On 20/07/2019 15:31, Chris Wilson wrote:
>> >> > Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as
>> >> > the machine stops responding milliseconds after receipt of the reset
>> >> > request [GDRT]. By disabling the cached atomics, the hang do not occur
>> >> > and we presume the GPU would reset normally for similar hangs.
>> >> > 
>> >> > Reported-by: Jason Ekstrand 
>> >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998
>> >> > Signed-off-by: Chris Wilson 
>> >> > Cc: Jason Ekstrand 
>> >> > Cc: Mika Kuoppala 
>> >> > Cc: Tvrtko Ursulin 
>> >> > ---
>> >> > Jason reports that Windows is not clearing L3SQCREG4:22 and does not
>> >> > suffer the same GPU hang so it is likely some other w/a that interacts
>> >> > badly. Fwiw, these 3 are the only registers I could find that mention
>> >> > atomic ops (and appear to be part of the same chain for memory access).
>> >> 
>> >> Bit-toggling itself looks fine to me and matches what I could find in 
>> >> the docs. (All three bits across three registers should be equal.)
>> >> 
>> >> What I am curious about is what are the other consequences of disabling 
>> >> L3 atomics? Performance drop somewhere?
>> >
>> > The test I have where it goes from dead to passing, that's a considerable
>> > performance improvement ;)
>> >
>> > I imagine not being able to use L3 for atomics is pretty dire, whether that
>> > has any impact, I have no clue.
>> >
>> > It is still very likely that we see this because we are doing something
>> > wrong elsewhere.
>> 
>> This reminds me of f3fc4884ebe6ae649d3723be14b219230d3b7fd2 followed by
>> d351f6d94893f3ba98b1b20c5ef44c35fc1da124 due to the massive impact (of
>> the order of 20x IIRC) using the L3 turned out to have on the
>> performance of HDC atomics, on at least that platform.  It seems
>> unfortunate that we're going to lose L3 atomics on Gen9 now, even though
>> it's only buffer atomics which are broken IIUC, and even though the
>> Windows driver is somehow getting away without disabling them.  Some of
>> our setup must be wrong either in the kernel or in userspace...  Are
>> these registers at least whitelisted so userspace can re-enable L3
>> atomics once the problem is addressed?  Wouldn't it be a more specific
>> workaround for userspace to simply use a non-L3-cacheable MOCS for
>> (rarely used) buffer surfaces, so it could benefit from L3 atomics
>> elsewhere?
>
> If it was the case that disabling L3 atomics was the only way to prevent
> the machine lockup under this scenario, then I think it is
> unquestionably the right thing to do, and we could not leave it to
> userspace to dtrt. We should never add non-context saved unsafe
> registers to the whitelist (if setting a register may cause data
> corruption or worse in another context/process, that is bad) despite our
> repeated transgressions. However, there's no evidence to say that it does
> prevent the machine lockup as it prevents the GPU hang that lead to the
> lockup on reset.
>
> Other than GPGPU requiring a flush around every sneeze, I did not see
> anything in the gen9 w/a list that seemed like a match. Nevertheless, I
> expect there is a more precise w/a than a blanket disable.
> -Chris

Supposedly there is a more precise one (setting the surface state MOCS
to UC for buffer images), but it relies on userspace doing the right
thing for the machine not to lock up.  There is a good chance that the
reason why L3 atomics hang on such buffers is ultimately under userspace
control, in which case we'll eventually have to undo the programming
done in this patch in order to re-enable L3 atomics once the problem is
addressed.  That means that userspace will have the freedom to hang the
machine hard once again, which sounds really bad, but it's no real news
for us (*cough* HSW *cough*), and it might be the only way to match the
performance of the Windows driver.

What can we do here?  Add an i915 option to enable performance features
that can lead to the system hanging hard under malicious (or
incompetent) userspace programming?  Probably only the user can tell
whether the trade-off between performance and security of the system is
acceptable...


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Re: [Intel-gfx] [PATCH 2/3] drm/i915/uc: Move uc firmware layout definitions to dedicated file

[Michal Wajdeczko]

On Wed, 24 Jul 2019 19:50:37 +0200, Daniele Ceraolo Spurio  
 wrote:





On 7/24/19 10:34 AM, Michal Wajdeczko wrote:

Generic uc firmware layout definitions are unlikely to change and
are separate to other GuC specific definitions.
 Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 


Keeping things that apply to HuC as well in a generic file seems  
sensible to me.



---
  Documentation/gpu/i915.rst   |  2 +-
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  | 70 -
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  1 +
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 81 
  4 files changed, 83 insertions(+), 71 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
 diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c2173d120492..366cb7f46d17 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -448,7 +448,7 @@ GuC-based command submission
  GuC Firmware Layout
  ---
  -.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
 :doc: GuC Firmware Layout


This is now generic uC firmware layout


GuC Address Space
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

index 30cca3a29323..06a9bdfb0faf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -121,76 +121,6 @@
#define GUC_CTL_MAX_DWORDS  (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
  -/**
- * DOC: GuC Firmware Layout
- *
- * The GuC firmware layout looks like this:
- *
- * +---+
- * | uc_css_header |
- * |   |
- * | contains major/minor version  |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * |  modulus key  |
- * +---+
- * |  exponent val |
- * +---+
- *
- * The firmware may or may not have modulus key and exponent data. The  
header,
- * uCode and RSA signature are must-have components that will be used  
by driver.
- * Length of each components, which is all in dwords, can be found in  
header.
- * In the case that modulus and exponent are not present in fw, a.k.a  
truncated

- * image, the length value still appears in header.
- *
- * Driver will do some basic fw size validation based on the following  
rules:

- *
- * 1. Header, uCode and RSA are must-have components.
- * 2. All firmware components, if they present, are in the sequence  
illustrated

- *in the layout table above.
- * 3. Length info of each component can be found in header, in dwords.
- * 4. Modulus and exponent key are not required by driver. They may  
not appear

- *in fw. So driver will load a truncated firmware in this case.
- *
- * HuC firmware layout is same as GuC firmware.
- * Only HuC version information is saved in a different way.
- */
-
-struct uc_css_header {
-   u32 module_type;
-   /* header_size includes all non-uCode bits, including css_header, rsa
-* key, modulus key and exponent data. */
-   u32 header_size_dw;
-   u32 header_version;
-   u32 module_id;
-   u32 module_vendor;
-   u32 date;
-#define CSS_DATE_DAY   (0xFF << 0)
-#define CSS_DATE_MONTH (0xFF << 8)
-#define CSS_DATE_YEAR  (0x << 16)
-   u32 size_dw; /* uCode plus header_size_dw */
-   u32 key_size_dw;
-   u32 modulus_size_dw;
-   u32 exponent_size_dw;
-   u32 time;
-#define CSS_TIME_HOUR  (0xFF << 0)
-#define CSS_DATE_MIN   (0xFF << 8)
-#define CSS_DATE_SEC   (0x << 16)
-   char username[8];
-   char buildnumber[12];
-   u32 sw_version;
-#define CSS_SW_VERSION_GUC_MAJOR   (0xFF << 16)
-#define CSS_SW_VERSION_GUC_MINOR   (0xFF << 8)
-#define CSS_SW_VERSION_GUC_PATCH   (0xFF << 0)
-#define CSS_SW_VERSION_HUC_MAJOR   (0x << 16)
-#define CSS_SW_VERSION_HUC_MINOR   (0x << 0)
-   u32 reserved[14];
-   u32 header_info;
-} __packed;
-
  /* Work item for submitting workloads into work queue of GuC. */
  struct guc_wq_item {
u32 header;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

index 8ce7210907c0..d5cb19b4e5c1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -27,6 +27,7 @@
  #include 
#include "intel_uc_fw.h"
+#include "intel_uc_fw_abi.h"
  #include "i915_drv.h"
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h  
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h

new file mode

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Fix premature release of context on reset

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Fix premature release of context on reset
URL   : https://patchwork.freedesktop.org/series/64181/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13737_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_13737_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13737_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_13737_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_color@pipe-c-ctm-0-75:
- shard-glk:  [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-glk8/igt@kms_co...@pipe-c-ctm-0-75.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-glk2/igt@kms_co...@pipe-c-ctm-0-75.html

  
Known issues


  Here are the changes found in Patchwork_13737_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl:  [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +1 
similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-apl5/igt@i915_susp...@fence-restore-tiled2untiled.html

  * igt@i915_suspend@forcewake:
- shard-skl:  [PASS][5] -> [INCOMPLETE][6] ([fdo#104108])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl8/igt@i915_susp...@forcewake.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-skl3/igt@i915_susp...@forcewake.html

  * igt@i915_suspend@sysfs-reader:
- shard-kbl:  [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +1 
similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl2/igt@i915_susp...@sysfs-reader.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-kbl4/igt@i915_susp...@sysfs-reader.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-hsw:  [PASS][9] -> [INCOMPLETE][10] ([fdo#103540])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-hsw8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
- shard-skl:  [PASS][11] -> [INCOMPLETE][12] ([fdo#109507])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl5/igt@kms_f...@flip-vs-suspend.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-skl9/igt@kms_f...@flip-vs-suspend.html

  * igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl:  [PASS][13] -> [FAIL][14] ([fdo#108134])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip_til...@flip-to-x-tiled.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-skl3/igt@kms_flip_til...@flip-to-x-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +8 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl:  [PASS][17] -> [INCOMPLETE][18] ([fdo#103665])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-kbl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-x.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-x.html

  * igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/shard-iclb3/igt@kms_psr2_su@page_flip.html

  * igt@kms_p

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Fix GuC documentation links

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Fix GuC documentation links
URL   : https://patchwork.freedesktop.org/series/64190/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13740


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/

Known issues


  Here are the changes found in Patchwork_13740 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_create@basic:
- fi-icl-u3:  [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@gem_ctx_cre...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-icl-u3/igt@gem_ctx_cre...@basic.html

  * igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u:   [PASS][3] -> [DMESG-WARN][4] ([fdo#105128] / 
[fdo#107139])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html

  * igt@i915_module_load@reload:
- fi-blb-e6850:   [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-blb-e6850/igt@i915_module_l...@reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-blb-e6850/igt@i915_module_l...@reload.html

  * igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u:   [PASS][7] -> [SKIP][8] ([fdo#109271]) +23 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html

  
 Possible fixes 

  * igt@gem_ctx_create@basic-files:
- fi-icl-u2:  [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) -> 
[PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html

  * igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [INCOMPLETE][11] ([fdo#108744]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u:   [WARN][13] ([fdo#109380]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3:  [FAIL][15] ([fdo#103167]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
- {fi-icl-u4}:[FAIL][17] ([fdo#103167]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u:   [SKIP][19] ([fdo#109271]) -> [PASS][20] +23 similar 
issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13740/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#111045]:

[Intel-gfx] ✓ Fi.CI.IGT: success for Associate ddc adapters with connectors (rev2)

[Patchwork]

== Series Details ==

Series: Associate ddc adapters with connectors (rev2)
URL   : https://patchwork.freedesktop.org/series/63558/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13736_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_13736_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_tiled_swapping@non-threaded:
- shard-apl:  [PASS][1] -> [DMESG-WARN][2] ([fdo#108686])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl5/igt@gem_tiled_swapp...@non-threaded.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-apl4/igt@gem_tiled_swapp...@non-threaded.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl:  [PASS][3] -> [SKIP][4] ([fdo#109271])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-kbl2/igt@i915_pm_rc6_reside...@rc6-accuracy.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl:  [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +2 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-hsw:  [PASS][7] -> [INCOMPLETE][8] ([fdo#103540])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw5/igt@kms_atomic_transit...@plane-all-modeset-transition-fencing.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-hsw4/igt@kms_atomic_transit...@plane-all-modeset-transition-fencing.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl:  [PASS][9] -> [INCOMPLETE][10] ([fdo#110741])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-suspend.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-skl8/igt@kms_cursor_...@pipe-b-cursor-suspend.html

  * igt@kms_flip@plain-flip-fb-recreate:
- shard-skl:  [PASS][11] -> [FAIL][12] ([fdo#100368])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl4/igt@kms_f...@plain-flip-fb-recreate.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-skl1/igt@kms_f...@plain-flip-fb-recreate.html

  * igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl:  [PASS][13] -> [FAIL][14] ([fdo#108134])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip_til...@flip-to-x-tiled.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-skl1/igt@kms_flip_til...@flip-to-x-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +2 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb8/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-iclb3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl:  [PASS][19] -> [INCOMPLETE][20] ([fdo#103665])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103166])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-x.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-x.html

  * igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109642] / [fdo#111068])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/shard-iclb3/igt@kms_psr2_su@page_flip.html

  *

[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev 2)

[Patchwork]

== Series Details ==

Series: Refactor to expand subslice mask (rev 2)
URL   : https://patchwork.freedesktop.org/series/64188/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13739


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/

Known issues


  Here are the changes found in Patchwork_13739 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([fdo#105411])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-snb-2600/igt@i915_module_l...@reload-with-fault-injection.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-snb-2600/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@vgem_basic@debugfs:
- fi-icl-u3:  [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@vgem_ba...@debugfs.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-icl-u3/igt@vgem_ba...@debugfs.html

  
 Possible fixes 

  * igt@gem_ctx_create@basic-files:
- fi-icl-u2:  [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> 
[PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html

  * igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [INCOMPLETE][7] ([fdo#108744]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u:   [WARN][9] ([fdo#109380]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3:  [FAIL][11] ([fdo#103167]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
- {fi-icl-u4}:[FAIL][13] ([fdo#103167]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u:   [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049


Participating hosts (52 -> 44)
--

  Additional (1): fi-skl-gvtdvm 
  Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6545 -> Patchwork_13739

  CI-20190529: 20190529
  CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13739: 6c805dfa2b2aa200593b17947e683a2781992c7a @ 
git://an

Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915

[Paul Bolle]

Hi Jose,

James Bottomley schreef op do 18-07-2019 om 06:29 [+0900]:
> On Wed, 2019-07-17 at 23:27 +0200, Paul Bolle wrote:
> > I've just reached a day of uptime with your revert. (The proper
> > uptime is just a fraction of a day, this being a laptop.) Anyhow, no
> > screen freezes occurred during this day.
> 
> I'm afraid my status is that I'm in Tokyo doing conference
> presentations (and kernel demos) so I'm a bit reluctant to mess with my
> setup until I finish everything on Friday, but I will test it after
> then, promise.

By now I'm testing this for a week (currently on top of 5.2.2). Still no
freezes whatsoever. 

So what's the status of this revert? Unless this is something pretty obscure
that for some odd reason only James and I are able to hit it would be nice to
get this into stable before the main distros switch over to 5.2.y.

Thanks,


Paul Bolle

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Split i915_gem_init_hw into GT and i915 parts (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Split i915_gem_init_hw into GT and 
i915 parts (rev2)
URL   : https://patchwork.freedesktop.org/series/64164/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13734_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_13734_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-suspend:
- shard-kbl:  [PASS][1] -> [DMESG-WARN][2] ([fdo#108566])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl2/igt@gem_...@in-flight-suspend.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-kbl4/igt@gem_...@in-flight-suspend.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb:  [PASS][3] -> [SKIP][4] ([fdo#109271])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-snb6/igt@i915_pm_rc6_reside...@rc6-accuracy.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-snb7/igt@i915_pm_rc6_reside...@rc6-accuracy.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw:  [PASS][5] -> [FAIL][6] ([fdo#105767])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +12 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl:  [PASS][9] -> [INCOMPLETE][10] ([fdo#103665])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-kbl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109642] / [fdo#111068])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-iclb3/igt@kms_psr2_su@page_flip.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl:  [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl1/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-apl5/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html

  * igt@perf_pmu@rc6:
- shard-kbl:  [PASS][15] -> [SKIP][16] ([fdo#109271])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl4/igt@perf_...@rc6.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-kbl2/igt@perf_...@rc6.html

  
 Possible fixes 

  * igt@i915_pm_rpm@i2c:
- shard-hsw:  [FAIL][17] ([fdo#104097]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@i915_pm_...@i2c.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-hsw5/igt@i915_pm_...@i2c.html

  * igt@i915_selftest@live_hangcheck:
- shard-iclb: [INCOMPLETE][19] ([fdo#107713] / [fdo#108569]) -> 
[PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@i915_selftest@live_hangcheck.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-iclb4/igt@i915_selftest@live_hangcheck.html

  * igt@kms_flip@flip-vs-expired-vblank:
- shard-skl:  [FAIL][21] ([fdo#105363]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl9/igt@kms_f...@flip-vs-expired-vblank.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][23] ([fdo#103167]) -> [PASS][24] +2 similar 
issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@k

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Make caps.scheduler static

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Make caps.scheduler static
URL   : https://patchwork.freedesktop.org/series/64186/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13738


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/

Known issues


  Here are the changes found in Patchwork_13738 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850:   [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u:   [PASS][3] -> [FAIL][4] ([fdo#109485])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html

  
 Possible fixes 

  * igt@gem_ctx_create@basic-files:
- fi-icl-u2:  [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> 
[PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html

  * igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [INCOMPLETE][7] ([fdo#108744]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u:   [WARN][9] ([fdo#109380]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u:   [SKIP][11] ([fdo#109271]) -> [PASS][12] +23 similar 
issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049


Participating hosts (52 -> 44)
--

  Additional (1): fi-skl-gvtdvm 
  Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6545 -> Patchwork_13738

  CI-20190529: 20190529
  CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13738: 0435e24ed3420e9bfca5cec28ceb83e875371434 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0435e24ed342 drm/i915/gem: Make caps.scheduler static

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13738/
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Fix GuC documentation links

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Fix GuC documentation links
URL   : https://patchwork.freedesktop.org/series/64190/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b6534971a681 drm/i915: Fix GuC documentation links
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#9: 
References: commit 0f261b241d9c ("drm/i915/uc: move GuC and HuC files under 
gt/uc/")

total: 0 errors, 1 warnings, 0 checks, 33 lines checked
482ab78bcf71 drm/i915/uc: Move uc firmware layout definitions to dedicated file
-:120: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#120: 
new file mode 100644

-:176: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#176: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h:52:
+* key, modulus key and exponent data. */

total: 0 errors, 2 warnings, 0 checks, 172 lines checked
d4bd5ea797ae drm/i915/uc: Update drawing for firmware layout

___
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/uc: Move uc firmware layout definitions to dedicated file

[Daniele Ceraolo Spurio]

On 7/24/19 10:34 AM, Michal Wajdeczko wrote:

Generic uc firmware layout definitions are unlikely to change and
are separate to other GuC specific definitions.

Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 


Keeping things that apply to HuC as well in a generic file seems 
sensible to me.



---
  Documentation/gpu/i915.rst   |  2 +-
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  | 70 -
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  1 +
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 81 
  4 files changed, 83 insertions(+), 71 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c2173d120492..366cb7f46d17 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -448,7 +448,7 @@ GuC-based command submission
  GuC Firmware Layout
  ---
  
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
 :doc: GuC Firmware Layout


This is now generic uC firmware layout

  
  GuC Address Space

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 30cca3a29323..06a9bdfb0faf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -121,76 +121,6 @@
  
  #define GUC_CTL_MAX_DWORDS		(SOFT_SCRATCH_COUNT - 2) /* [1..14] */
  
-/**

- * DOC: GuC Firmware Layout
- *
- * The GuC firmware layout looks like this:
- *
- * +---+
- * | uc_css_header |
- * |   |
- * | contains major/minor version  |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * |  modulus key  |
- * +---+
- * |  exponent val |
- * +---+
- *
- * The firmware may or may not have modulus key and exponent data. The header,
- * uCode and RSA signature are must-have components that will be used by 
driver.
- * Length of each components, which is all in dwords, can be found in header.
- * In the case that modulus and exponent are not present in fw, a.k.a truncated
- * image, the length value still appears in header.
- *
- * Driver will do some basic fw size validation based on the following rules:
- *
- * 1. Header, uCode and RSA are must-have components.
- * 2. All firmware components, if they present, are in the sequence illustrated
- *in the layout table above.
- * 3. Length info of each component can be found in header, in dwords.
- * 4. Modulus and exponent key are not required by driver. They may not appear
- *in fw. So driver will load a truncated firmware in this case.
- *
- * HuC firmware layout is same as GuC firmware.
- * Only HuC version information is saved in a different way.
- */
-
-struct uc_css_header {
-   u32 module_type;
-   /* header_size includes all non-uCode bits, including css_header, rsa
-* key, modulus key and exponent data. */
-   u32 header_size_dw;
-   u32 header_version;
-   u32 module_id;
-   u32 module_vendor;
-   u32 date;
-#define CSS_DATE_DAY   (0xFF << 0)
-#define CSS_DATE_MONTH (0xFF << 8)
-#define CSS_DATE_YEAR  (0x << 16)
-   u32 size_dw; /* uCode plus header_size_dw */
-   u32 key_size_dw;
-   u32 modulus_size_dw;
-   u32 exponent_size_dw;
-   u32 time;
-#define CSS_TIME_HOUR  (0xFF << 0)
-#define CSS_DATE_MIN   (0xFF << 8)
-#define CSS_DATE_SEC   (0x << 16)
-   char username[8];
-   char buildnumber[12];
-   u32 sw_version;
-#define CSS_SW_VERSION_GUC_MAJOR   (0xFF << 16)
-#define CSS_SW_VERSION_GUC_MINOR   (0xFF << 8)
-#define CSS_SW_VERSION_GUC_PATCH   (0xFF << 0)
-#define CSS_SW_VERSION_HUC_MAJOR   (0x << 16)
-#define CSS_SW_VERSION_HUC_MINOR   (0x << 0)
-   u32 reserved[14];
-   u32 header_info;
-} __packed;
-
  /* Work item for submitting workloads into work queue of GuC. */
  struct guc_wq_item {
u32 header;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 8ce7210907c0..d5cb19b4e5c1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -27,6 +27,7 @@
  #include 
  
  #include "intel_uc_fw.h"

+#include "intel_uc_fw_abi.h"
  #include "i915_drv.h"
  
  /**

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
new file mode 100644
index ..3ca535534151
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel

Re: [Intel-gfx] [PATCH 3/3] drm/i915/uc: Update drawing for firmware layout

[Daniele Ceraolo Spurio]

On 7/24/19 10:34 AM, Michal Wajdeczko wrote:

Sphinx was rendering firmware layout as html table, but since
we want to add sizes relations switch to plain text graphics.

Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
---
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 25 +---
  1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
index 3ca535534151..e25271aac765 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -11,21 +11,18 @@
  /**
   * DOC: GuC Firmware Layout
   *
- * The GuC firmware layout looks like this:
+ * The GuC firmware layout looks like this::
   *
- * +---+
- * | uc_css_header |
- * |   |
- * | contains major/minor version  |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * |  modulus key  |
- * +---+
- * |  exponent val |
- * +---+
+ *  
+==+
+ *  |  Firmware blob   
|
+ *  
+===+===++++
+ *  |  CSS header   | uCode |key |  modulus   |  exponent  
|
+ *  
+===+===++++


What about the RSA?

Daniele


+ *   <-header size-> <---header size continued --->
+ *   <--- size --->
+ *   <-key size->
+ *<-mod size->
+ * <-exp size->
   *
   * The firmware may or may not have modulus key and exponent data. The header,
   * uCode and RSA signature are must-have components that will be used by 
driver.


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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix GuC documentation links

[Daniele Ceraolo Spurio]

On 7/24/19 10:34 AM, Michal Wajdeczko wrote:

We moved GuC related files to new location but we missed to update
.rst file with links.

References: commit 0f261b241d9c ("drm/i915/uc: move GuC and HuC files under 
gt/uc/")
Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Chris Wilson 


That's all of them (which surprised me since I expected an entry for HuC 
as well).


Reviewed-by: Daniele Ceraolo Spurio 


---
  Documentation/gpu/i915.rst | 10 +-
  1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c38ef0dda605..c2173d120492 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -433,28 +433,28 @@ GuC
  GuC-specific firmware loader
  
  
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c

+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
 :internal:
  
  GuC-based command submission

  
  
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c

+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
 :doc: GuC-based command submission
  
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c

+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
 :internal:
  
  GuC Firmware Layout

  ---
  
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h

+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
 :doc: GuC Firmware Layout
  
  GuC Address Space

  -
  
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c

+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
 :doc: GuC Address Space
  
  Tracing



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Re: [Intel-gfx] [PATCH stable v5.2] drm/i915/vbt: Fix VBT parsing for the PSR section

[Rodrigo Vivi]

On Wed, Jul 24, 2019 at 05:27:42PM +, Souza, Jose wrote:
> On Wed, 2019-07-24 at 14:06 +0200, Greg KH wrote:
> > On Mon, Jul 22, 2019 at 04:13:25PM -0700, Dhinakaran Pandiyan wrote:
> > > A single 32-bit PSR2 training pattern field follows the sixteen
> > > element
> > > array of PSR table entries in the VBT spec. But, we incorrectly
> > > define
> > > this PSR2 field for each of the PSR table entries. As a result, the
> > > PSR1
> > > training pattern duration for any panel_type != 0 will be parsed
> > > incorrectly. Secondly, PSR2 training pattern durations for VBTs
> > > with bdb
> > > version >= 226 will also be wrong.
> > > 
> > > Cc: Rodrigo Vivi 
> > > Cc: José Roberto de Souza 
> > > Cc: sta...@vger.kernel.org
> > > Cc: sta...@vger.kernel.org #v5.2
> > > Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field
> > > with PSR2 TP2/3 wakeup time")
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
> > > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
> > > Signed-off-by: Dhinakaran Pandiyan 
> > > Reviewed-by: Ville Syrjälä 
> > > Reviewed-by: José Roberto de Souza 
> > > Acked-by: Rodrigo Vivi 
> > > Tested-by: François Guerraz 
> > > Signed-off-by: Rodrigo Vivi 
> > > Link: 
> > > https://patchwork.freedesktop.org/patch/msgid/20190717223451.2595-1-dhinakaran.pandi...@intel.com
> > > (cherry picked from commit
> > > b5ea9c9337007d6e700280c8a60b4e10d070fb53)
> > 
> > There is no such commit in Linus's kernel tree :(

not yet... It is queued for 5.3 on drm-intel-next-queued.

This line is automatically added by "dim" tool when
cherry-picking queued stuff for our drm-intel fixes branches.

> > 
> 
> It is still on drm-intel/drm-intel-next-queued -
> ssh://git.freedesktop.org/git/drm-intel
> 
> Rodrigo do you know when is the next pull-request to Linus?

I will start doing the pull requests to Dave and Daniel soon,
but this doesn't reach Linus tree before next merge window.

Eventually it will be there.

If this is a blocker fell free to remove the line and merge the
patch please, because this fix very critical issue that impact users.
So we can continue the discussion in parallel on how to handle
commit links like this in a better way.

Thanks,
Rodrigo.

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[Intel-gfx] [PATCH 3/3] drm/i915/uc: Update drawing for firmware layout

[Michal Wajdeczko]

Sphinx was rendering firmware layout as html table, but since
we want to add sizes relations switch to plain text graphics.

Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 25 +---
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
index 3ca535534151..e25271aac765 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -11,21 +11,18 @@
 /**
  * DOC: GuC Firmware Layout
  *
- * The GuC firmware layout looks like this:
+ * The GuC firmware layout looks like this::
  *
- * +---+
- * | uc_css_header |
- * |   |
- * | contains major/minor version  |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * |  modulus key  |
- * +---+
- * |  exponent val |
- * +---+
+ *  
+==+
+ *  |  Firmware blob   
|
+ *  
+===+===++++
+ *  |  CSS header   | uCode |key |  modulus   |  exponent  
|
+ *  
+===+===++++
+ *   <-header size-> <---header size continued --->
+ *   <--- size --->
+ *   <-key size->
+ *<-mod size->
+ * <-exp size->
  *
  * The firmware may or may not have modulus key and exponent data. The header,
  * uCode and RSA signature are must-have components that will be used by 
driver.
-- 
2.19.2

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[Intel-gfx] [PATCH 1/3] drm/i915: Fix GuC documentation links

[Michal Wajdeczko]

We moved GuC related files to new location but we missed to update
.rst file with links.

References: commit 0f261b241d9c ("drm/i915/uc: move GuC and HuC files under 
gt/uc/")
Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Cc: Chris Wilson 
---
 Documentation/gpu/i915.rst | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c38ef0dda605..c2173d120492 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -433,28 +433,28 @@ GuC
 GuC-specific firmware loader
 
 
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
:internal:
 
 GuC-based command submission
 
 
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
:doc: GuC-based command submission
 
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
:internal:
 
 GuC Firmware Layout
 ---
 
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
:doc: GuC Firmware Layout
 
 GuC Address Space
 -
 
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
:doc: GuC Address Space
 
 Tracing
-- 
2.19.2

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[Intel-gfx] [PATCH 2/3] drm/i915/uc: Move uc firmware layout definitions to dedicated file

[Michal Wajdeczko]

Generic uc firmware layout definitions are unlikely to change and
are separate to other GuC specific definitions.

Signed-off-by: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
---
 Documentation/gpu/i915.rst   |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  | 70 -
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 81 
 4 files changed, 83 insertions(+), 71 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index c2173d120492..366cb7f46d17 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -448,7 +448,7 @@ GuC-based command submission
 GuC Firmware Layout
 ---
 
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
:doc: GuC Firmware Layout
 
 GuC Address Space
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 30cca3a29323..06a9bdfb0faf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -121,76 +121,6 @@
 
 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
 
-/**
- * DOC: GuC Firmware Layout
- *
- * The GuC firmware layout looks like this:
- *
- * +---+
- * | uc_css_header |
- * |   |
- * | contains major/minor version  |
- * +---+
- * | uCode |
- * +---+
- * | RSA signature |
- * +---+
- * |  modulus key  |
- * +---+
- * |  exponent val |
- * +---+
- *
- * The firmware may or may not have modulus key and exponent data. The header,
- * uCode and RSA signature are must-have components that will be used by 
driver.
- * Length of each components, which is all in dwords, can be found in header.
- * In the case that modulus and exponent are not present in fw, a.k.a truncated
- * image, the length value still appears in header.
- *
- * Driver will do some basic fw size validation based on the following rules:
- *
- * 1. Header, uCode and RSA are must-have components.
- * 2. All firmware components, if they present, are in the sequence illustrated
- *in the layout table above.
- * 3. Length info of each component can be found in header, in dwords.
- * 4. Modulus and exponent key are not required by driver. They may not appear
- *in fw. So driver will load a truncated firmware in this case.
- *
- * HuC firmware layout is same as GuC firmware.
- * Only HuC version information is saved in a different way.
- */
-
-struct uc_css_header {
-   u32 module_type;
-   /* header_size includes all non-uCode bits, including css_header, rsa
-* key, modulus key and exponent data. */
-   u32 header_size_dw;
-   u32 header_version;
-   u32 module_id;
-   u32 module_vendor;
-   u32 date;
-#define CSS_DATE_DAY   (0xFF << 0)
-#define CSS_DATE_MONTH (0xFF << 8)
-#define CSS_DATE_YEAR  (0x << 16)
-   u32 size_dw; /* uCode plus header_size_dw */
-   u32 key_size_dw;
-   u32 modulus_size_dw;
-   u32 exponent_size_dw;
-   u32 time;
-#define CSS_TIME_HOUR  (0xFF << 0)
-#define CSS_DATE_MIN   (0xFF << 8)
-#define CSS_DATE_SEC   (0x << 16)
-   char username[8];
-   char buildnumber[12];
-   u32 sw_version;
-#define CSS_SW_VERSION_GUC_MAJOR   (0xFF << 16)
-#define CSS_SW_VERSION_GUC_MINOR   (0xFF << 8)
-#define CSS_SW_VERSION_GUC_PATCH   (0xFF << 0)
-#define CSS_SW_VERSION_HUC_MAJOR   (0x << 16)
-#define CSS_SW_VERSION_HUC_MINOR   (0x << 0)
-   u32 reserved[14];
-   u32 header_info;
-} __packed;
-
 /* Work item for submitting workloads into work queue of GuC. */
 struct guc_wq_item {
u32 header;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 8ce7210907c0..d5cb19b4e5c1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -27,6 +27,7 @@
 #include 
 
 #include "intel_uc_fw.h"
+#include "intel_uc_fw_abi.h"
 #include "i915_drv.h"
 
 /**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
new file mode 100644
index ..3ca535534151
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef _INTEL_UC_FW_ABI_H
+#define _INTEL_UC_FW_ABI_H
+
+#include 
+
+/**
+ *

Re: [Intel-gfx] [PATCH v2 3/8] drm/i915/uc: Unify uc_fw status tracking

[Daniele Ceraolo Spurio]

On 7/24/19 10:24 AM, Michal Wajdeczko wrote:
On Wed, 24 Jul 2019 18:37:52 +0200, Daniele Ceraolo Spurio 
 wrote:



-    uc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
-    DRM_DEBUG_DRIVER("%s fw load %s\n",
- intel_uc_fw_type_repr(uc_fw->type),
- intel_uc_fw_status_repr(uc_fw->load_status));
+    uc_fw->status = INTEL_UC_FIRMWARE_LOADED;


maybe we can slightly modify xfer function agreement and use
-EINPROGRESS to indicate whether fw is just loaded (HuC) or
is already authenticated and running (GuC):

    if (!err)
    uc_fw->status = INTEL_UC_FIRMWARE_RUNNING;
    else if (err == -EINPROGRESS)
    uc_fw->status = INTEL_UC_FIRMWARE_LOADED;
    else
    goto fail;



I've purposely kept the RUNNING state outside because in patch 8 I 
move the wait outside the xfer, so the switch to the running state 
will be done outside of here for both uC. Seemed like less churn to go 
directly with that.


ok, I missed that move in diff 8/8



@@ -35,12 +35,14 @@ struct drm_i915_private;
 #define INTEL_UC_FIRMWARE_URL 
"https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915"; 


enum intel_uc_fw_status {
-    INTEL_UC_FIRMWARE_NOT_SUPPORTED = -2, /* no uc HW */
-    INTEL_UC_FIRMWARE_FAIL = -1,
+    INTEL_UC_FIRMWARE_LOAD_FAIL = -3,
+    INTEL_UC_FIRMWARE_FETCH_FAIL = -2,
+    INTEL_UC_FIRMWARE_NOT_SUPPORTED = -1, /* no uc HW */
 INTEL_UC_FIRMWARE_UNINITIALIZED = 0, /* used to catch checks 
done too early */

-    INTEL_UC_FIRMWARE_NOT_STARTED = 1,
-    INTEL_UC_FIRMWARE_PENDING,
-    INTEL_UC_FIRMWARE_SUCCESS
+    INTEL_UC_FIRMWARE_SELECTION_DONE, /* selection include the "no 
FW" case */


why do you want to keep "No FW" case here ?
when we know that there is no fw, we should not attempt to fetch it.
so this is different state than "fw was selected, awaiting fetch"


We need a way to differentiate for the logging and I didn't want an 
extra state since we check fw->path anyway to make sure the fw was 
actually selected.


But "N/A" state also means that we already pass over init_early step
that includes selection, so we don't need to add any extra state.



Yes, but we wouldn't know if N/A was set because we are on a platform 
with no uC HW or because the FW was not defined. I'm going to drop that 
distinction in the logs and be done with it, it's quite easy to find out 
based on the gen anyway (anything gen9+ has GuC/HuC HW)







+    INTEL_UC_FIRMWARE_AVAILABLE, /* fetch done */
+    INTEL_UC_FIRMWARE_LOADED, /* dma xfer done */
+    INTEL_UC_FIRMWARE_RUNNING /* fw init/auth done */
 };
enum intel_uc_fw_type {
@@ -57,8 +59,7 @@ struct intel_uc_fw {
 const char *path;
 size_t size;
 struct drm_i915_gem_object *obj;
-    enum intel_uc_fw_status fetch_status;
-    enum intel_uc_fw_status load_status;
+    enum intel_uc_fw_status status;
    /*
  * The firmware build process will generate a version header 
file with major and

@@ -83,18 +84,22 @@ static inline
 const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
 switch (status) {
+    case INTEL_UC_FIRMWARE_LOAD_FAIL:
+    return "LOAD FAIL";


sorry for second thoughts, but with these names we could have:

LOADED (user: hurray!) --> NOT_LOADED (user: but we were already loaded?!?)

so maybe plain "FAIL" as this is user facing status ?



ok


+    case INTEL_UC_FIRMWARE_FETCH_FAIL:
+    return "FETCH FAIL";


same here, "fetch" it's name of our internal step,
"MISSING" sounds better imno



ok


 case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
-    return "N/A - uc HW not available";
-    case INTEL_UC_FIRMWARE_FAIL:
-    return "FAIL";
+    return "N/A";
 case INTEL_UC_FIRMWARE_UNINITIALIZED:
 return "UNINITIALIZED";
-    case INTEL_UC_FIRMWARE_NOT_STARTED:
-    return "NOT_STARTED";
-    case INTEL_UC_FIRMWARE_PENDING:
-    return "PENDING";
-    case INTEL_UC_FIRMWARE_SUCCESS:
-    return "SUCCESS";
+    case INTEL_UC_FIRMWARE_SELECTION_DONE:
+    return "SELECTION DONE";


nit: this is not my favorite, what was wrong with
"PENDING" (known, awaiting fetch/load, look it's transient state!)
"SELECTED" (shorter, applies to this fw object vs step)


I wanted to highlight the fact that the selection included the "no FW" 
case, the fw wasn't necessarily "selected". We just know that we've 
run through the selection code.


but from the user pov this is internal detail, not sure if we should expose
that, on other hand, PENDING clearly indicates that we are still going 
to do

something with that firmware (fetch/xfer/auth) until we reach end state.






+    case INTEL_UC_FIRMWARE_AVAILABLE:
+    return "AVAILABLE";
+    case INTEL_UC_FIRMWARE_LOADED:
+    return "LOADED";
+    case INTEL_UC_FIRMWARE_RUNNING:
+    return "RUNNING";


hmm, the difference between LOADED/RUNNING might be unnoticed by the
user, as he may also treat LOADED as full success.

so maybe s/LOADED/TRANSFERRED ?



ok

Daniele


  

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2)

[Patchwork]

== Series Details ==

Series: Refactor to expand subslice mask (rev 2)
URL   : https://patchwork.freedesktop.org/series/64188/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d83520f343cd drm/i915: Use variable for debugfs device status
c7ec1447ee8f drm/i915: Add function to set SSEU info per platform
f98badbf8128 drm/i915: Add subslice stride runtime parameter
c4939aa73937 drm/i915: Add EU stride runtime parameter
4bbfa8ad97d1 drm/i915: Add function to set subslices
e91ccd3ed614 drm/i915: Add function to determine if a slice has a subslice
90de02581fa8 drm/i915: Refactor instdone loops on new subslice functions
-:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice__' - possible 
side-effects?
#60: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:547:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+   (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+intel_sseu_has_subslice(sseu__, 0, subslice__))

-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible 
side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:551:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+   for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+(subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+(slice_) += ((subslice_) == 0)) \
+   for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+   (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+   subslice_)))

-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible 
side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:551:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+   for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+(subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+(slice_) += ((subslice_) == 0)) \
+   for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+   (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+   subslice_)))

-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible 
side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:551:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+   for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+(subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+(slice_) += ((subslice_) == 0)) \
+   for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+   (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+   subslice_)))

-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible 
side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:551:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+   for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+(subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+(slice_) += ((subslice_) == 0)) \
+   for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+   (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+   subslice_)))

total: 0 errors, 0 warnings, 5 checks, 106 lines checked
22e6e3567db7 drm/i915: Add new function to copy subslices for a slice
6c805dfa2b2a drm/i915: Expand subslice mask

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Re: [Intel-gfx] [PATCH stable v5.2] drm/i915/vbt: Fix VBT parsing for the PSR section

[Souza, Jose]

On Wed, 2019-07-24 at 14:06 +0200, Greg KH wrote:
> On Mon, Jul 22, 2019 at 04:13:25PM -0700, Dhinakaran Pandiyan wrote:
> > A single 32-bit PSR2 training pattern field follows the sixteen
> > element
> > array of PSR table entries in the VBT spec. But, we incorrectly
> > define
> > this PSR2 field for each of the PSR table entries. As a result, the
> > PSR1
> > training pattern duration for any panel_type != 0 will be parsed
> > incorrectly. Secondly, PSR2 training pattern durations for VBTs
> > with bdb
> > version >= 226 will also be wrong.
> > 
> > Cc: Rodrigo Vivi 
> > Cc: José Roberto de Souza 
> > Cc: sta...@vger.kernel.org
> > Cc: sta...@vger.kernel.org #v5.2
> > Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field
> > with PSR2 TP2/3 wakeup time")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
> > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
> > Signed-off-by: Dhinakaran Pandiyan 
> > Reviewed-by: Ville Syrjälä 
> > Reviewed-by: José Roberto de Souza 
> > Acked-by: Rodrigo Vivi 
> > Tested-by: François Guerraz 
> > Signed-off-by: Rodrigo Vivi 
> > Link: 
> > https://patchwork.freedesktop.org/patch/msgid/20190717223451.2595-1-dhinakaran.pandi...@intel.com
> > (cherry picked from commit
> > b5ea9c9337007d6e700280c8a60b4e10d070fb53)
> 
> There is no such commit in Linus's kernel tree :(
> 

It is still on drm-intel/drm-intel-next-queued -
ssh://git.freedesktop.org/git/drm-intel

Rodrigo do you know when is the next pull-request to Linus?
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Re: [Intel-gfx] [PATCH v2 3/8] drm/i915/uc: Unify uc_fw status tracking

[Michal Wajdeczko]

On Wed, 24 Jul 2019 18:37:52 +0200, Daniele Ceraolo Spurio  
 wrote:



-uc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
-DRM_DEBUG_DRIVER("%s fw load %s\n",
- intel_uc_fw_type_repr(uc_fw->type),
- intel_uc_fw_status_repr(uc_fw->load_status));
+uc_fw->status = INTEL_UC_FIRMWARE_LOADED;


maybe we can slightly modify xfer function agreement and use
-EINPROGRESS to indicate whether fw is just loaded (HuC) or
is already authenticated and running (GuC):

if (!err)
uc_fw->status = INTEL_UC_FIRMWARE_RUNNING;
else if (err == -EINPROGRESS)
uc_fw->status = INTEL_UC_FIRMWARE_LOADED;
else
goto fail;



I've purposely kept the RUNNING state outside because in patch 8 I move  
the wait outside the xfer, so the switch to the running state will be  
done outside of here for both uC. Seemed like less churn to go directly  
with that.


ok, I missed that move in diff 8/8



@@ -35,12 +35,14 @@ struct drm_i915_private;
 #define INTEL_UC_FIRMWARE_URL  
"https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915";

enum intel_uc_fw_status {
-INTEL_UC_FIRMWARE_NOT_SUPPORTED = -2, /* no uc HW */
-INTEL_UC_FIRMWARE_FAIL = -1,
+INTEL_UC_FIRMWARE_LOAD_FAIL = -3,
+INTEL_UC_FIRMWARE_FETCH_FAIL = -2,
+INTEL_UC_FIRMWARE_NOT_SUPPORTED = -1, /* no uc HW */
 INTEL_UC_FIRMWARE_UNINITIALIZED = 0, /* used to catch checks done  
too early */

-INTEL_UC_FIRMWARE_NOT_STARTED = 1,
-INTEL_UC_FIRMWARE_PENDING,
-INTEL_UC_FIRMWARE_SUCCESS
+INTEL_UC_FIRMWARE_SELECTION_DONE, /* selection include the "no  
FW" case */


why do you want to keep "No FW" case here ?
when we know that there is no fw, we should not attempt to fetch it.
so this is different state than "fw was selected, awaiting fetch"


We need a way to differentiate for the logging and I didn't want an  
extra state since we check fw->path anyway to make sure the fw was  
actually selected.


But "N/A" state also means that we already pass over init_early step
that includes selection, so we don't need to add any extra state.






+INTEL_UC_FIRMWARE_AVAILABLE, /* fetch done */
+INTEL_UC_FIRMWARE_LOADED, /* dma xfer done */
+INTEL_UC_FIRMWARE_RUNNING /* fw init/auth done */
 };
enum intel_uc_fw_type {
@@ -57,8 +59,7 @@ struct intel_uc_fw {
 const char *path;
 size_t size;
 struct drm_i915_gem_object *obj;
-enum intel_uc_fw_status fetch_status;
-enum intel_uc_fw_status load_status;
+enum intel_uc_fw_status status;
/*
  * The firmware build process will generate a version header file  
with major and

@@ -83,18 +84,22 @@ static inline
 const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
 {
 switch (status) {
+case INTEL_UC_FIRMWARE_LOAD_FAIL:
+return "LOAD FAIL";


sorry for second thoughts, but with these names we could have:

LOADED (user: hurray!) --> NOT_LOADED (user: but we were already loaded?!?)

so maybe plain "FAIL" as this is user facing status ?


+case INTEL_UC_FIRMWARE_FETCH_FAIL:
+return "FETCH FAIL";


same here, "fetch" it's name of our internal step,
"MISSING" sounds better imno


 case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
-return "N/A - uc HW not available";
-case INTEL_UC_FIRMWARE_FAIL:
-return "FAIL";
+return "N/A";
 case INTEL_UC_FIRMWARE_UNINITIALIZED:
 return "UNINITIALIZED";
-case INTEL_UC_FIRMWARE_NOT_STARTED:
-return "NOT_STARTED";
-case INTEL_UC_FIRMWARE_PENDING:
-return "PENDING";
-case INTEL_UC_FIRMWARE_SUCCESS:
-return "SUCCESS";
+case INTEL_UC_FIRMWARE_SELECTION_DONE:
+return "SELECTION DONE";


nit: this is not my favorite, what was wrong with
"PENDING" (known, awaiting fetch/load, look it's transient state!)
"SELECTED" (shorter, applies to this fw object vs step)


I wanted to highlight the fact that the selection included the "no FW"  
case, the fw wasn't necessarily "selected". We just know that we've run  
through the selection code.


but from the user pov this is internal detail, not sure if we should expose
that, on other hand, PENDING clearly indicates that we are still going to  
do

something with that firmware (fetch/xfer/auth) until we reach end state.






+case INTEL_UC_FIRMWARE_AVAILABLE:
+return "AVAILABLE";
+case INTEL_UC_FIRMWARE_LOADED:
+return "LOADED";
+case INTEL_UC_FIRMWARE_RUNNING:
+return "RUNNING";


hmm, the difference between LOADED/RUNNING might be unnoticed by the
user, as he may also treat LOADED as full success.

so maybe s/LOADED/TRANSFERRED ?


 }
 return "";
 }

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Re: [Intel-gfx] [PATCH v5 18/24] drm/ast: Provide ddc symlink in connector sysfs directory

[Thomas Zimmermann]

Am 24.07.19 um 15:59 schrieb Andrzej Pietrasiewicz:
> Use the ddc pointer provided by the generic connector.
> 
> Signed-off-by: Andrzej Pietrasiewicz 
> ---
>  drivers/gpu/drm/ast/ast_mode.c | 13 -
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
> index c792362024a5..1c899a6e87b7 100644
> --- a/drivers/gpu/drm/ast/ast_mode.c
> +++ b/drivers/gpu/drm/ast/ast_mode.c
> @@ -867,7 +867,14 @@ static int ast_connector_init(struct drm_device *dev)
>   return -ENOMEM;
>  
>   connector = &ast_connector->base;
> - drm_connector_init(dev, connector, &ast_connector_funcs, 
> DRM_MODE_CONNECTOR_VGA);
> + ast_connector->i2c = ast_i2c_create(dev);
> + if (!ast_connector->i2c)
> + DRM_ERROR("failed to add ddc bus for connector\n");
> +
> + drm_connector_init_with_ddc(dev, connector,
> + &ast_connector_funcs,
> + DRM_MODE_CONNECTOR_VGA,
> + &ast_connector->i2c->adapter);
>  
>   drm_connector_helper_add(connector, &ast_connector_helper_funcs);
>  
> @@ -881,10 +888,6 @@ static int ast_connector_init(struct drm_device *dev)
>   encoder = list_first_entry(&dev->mode_config.encoder_list, struct 
> drm_encoder, head);
>   drm_connector_attach_encoder(connector, encoder);
>  
> - ast_connector->i2c = ast_i2c_create(dev);
> - if (!ast_connector->i2c)
> - DRM_ERROR("failed to add ddc bus for connector\n");
> -
>   return 0;
>  }
>  
> 

Reviewed-by: Thomas Zimmermann 

-- 
Thomas Zimmermann
Graphics Driver Developer
SUSE Linux GmbH, Maxfeldstrasse 5, 90409 Nuernberg, Germany
GF: Felix Imendörffer, Mary Higgins, Sri Rasiah
HRB 21284 (AG Nürnberg)



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Re: [Intel-gfx] [PATCH v5 17/24] drm/mgag200: Provide ddc symlink in connector sysfs directory

[Thomas Zimmermann]

Am 24.07.19 um 15:59 schrieb Andrzej Pietrasiewicz:
> Use the ddc pointer provided by the generic connector.
> 
> Signed-off-by: Andrzej Pietrasiewicz 
> ---
>  drivers/gpu/drm/mgag200/mgag200_mode.c | 13 +++--
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c 
> b/drivers/gpu/drm/mgag200/mgag200_mode.c
> index 822f2a13748f..5e778b5f1a10 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_mode.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
> @@ -1678,18 +1678,19 @@ static struct drm_connector *mga_vga_init(struct 
> drm_device *dev)
>   return NULL;
>  
>   connector = &mga_connector->base;
> + mga_connector->i2c = mgag200_i2c_create(dev);
> + if (!mga_connector->i2c)
> + DRM_ERROR("failed to add ddc bus\n");
>  
> - drm_connector_init(dev, connector,
> -&mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
> + drm_connector_init_with_ddc(dev, connector,
> + &mga_vga_connector_funcs,
> + DRM_MODE_CONNECTOR_VGA,
> + &mga_connector->i2c->adapter);
>  
>   drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
>  
>   drm_connector_register(connector);
>  
> - mga_connector->i2c = mgag200_i2c_create(dev);
> - if (!mga_connector->i2c)
> - DRM_ERROR("failed to add ddc bus\n");
> -
>   return connector;
>  }
>  
> 

Reviewed-by: Thomas Zimmermann 

-- 
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Graphics Driver Developer
SUSE Linux GmbH, Maxfeldstrasse 5, 90409 Nuernberg, Germany
GF: Felix Imendörffer, Mary Higgins, Sri Rasiah
HRB 21284 (AG Nürnberg)



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Re: [Intel-gfx] [PATCH v5 02/24] drm: Add drm_connector_init() variant with ddc

[Thomas Zimmermann]

Hi

Am 24.07.19 um 15:59 schrieb Andrzej Pietrasiewicz:
> Allow passing ddc adapter pointer to the init function. Even if
> drm_connector_init() sometime in the future decides to e.g. memset() all
> connector fields to zeros, the newly added function ensures that at its
> completion the ddc member of connector is correctly set.
> 
> Signed-off-by: Andrzej Pietrasiewicz 
> ---
>  drivers/gpu/drm/drm_connector.c | 19 +++
>  include/drm/drm_connector.h |  5 +
>  2 files changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 068d4b05f1be..06fbfc44fb48 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -296,6 +296,25 @@ int drm_connector_init(struct drm_device *dev,
>  }
>  EXPORT_SYMBOL(drm_connector_init);
>  
> +int drm_connector_init_with_ddc(struct drm_device *dev,
> + struct drm_connector *connector,
> + const struct drm_connector_funcs *funcs,
> + int connector_type,
> + struct i2c_adapter *ddc)
> +{
> + int ret;
> +
> + ret = drm_connector_init(dev, connector, funcs, connector_type);
> + if (ret)
> + return ret;
> +
> + /* provide ddc symlink in sysfs */
> + connector->ddc = ddc;
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(drm_connector_init_with_ddc);
> +

Thanks for including such a function.

Acked-by: Thomas Zimmermann 

>  /**
>   * drm_connector_attach_edid_property - attach edid property.
>   * @connector: the connector
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 33a6fff85fdb..937fda9c1374 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -1410,6 +1410,11 @@ int drm_connector_init(struct drm_device *dev,
>  struct drm_connector *connector,
>  const struct drm_connector_funcs *funcs,
>  int connector_type);
> +int drm_connector_init_with_ddc(struct drm_device *dev,
> + struct drm_connector *connector,
> + const struct drm_connector_funcs *funcs,
> + int connector_type,
> + struct i2c_adapter *ddc);
>  void drm_connector_attach_edid_property(struct drm_connector *connector);
>  int drm_connector_register(struct drm_connector *connector);
>  void drm_connector_unregister(struct drm_connector *connector);
> 

-- 
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[Intel-gfx] [PATCH 4/9] drm/i915: Add EU stride runtime parameter

[Stuart Summers]

Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.

This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.

Signed-off-by: Stuart Summers 
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 1 +
 drivers/gpu/drm/i915/gt/intel_sseu.h | 1 +
 drivers/gpu/drm/i915/i915_query.c| 5 ++---
 drivers/gpu/drm/i915/intel_device_info.c | 9 -
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c 
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 2d9e6fa4ee46..71abf0c9a46b 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -16,6 +16,7 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 
max_slices,
sseu->max_eus_per_subslice = max_eus_per_subslice;
 
sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+   sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
 }
 
 unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h 
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b0101e1c69bd..fe22d5b18e67 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -34,6 +34,7 @@ struct sseu_dev_info {
u8 max_eus_per_subslice;
 
u8 ss_stride;
+   u8 eu_stride;
 
/* We don't have more than 8 eus per subslice at the moment and as we
 * store eus enabled using bits, no need to multiply by eus per
diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index e4aeb7369026..ac8ac59c4860 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private 
*dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
-   u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
 
if (query_item->flags != 0)
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private 
*dev_priv,
 
slice_length = sizeof(sseu->slice_mask);
subslice_length = sseu->max_slices * sseu->ss_stride;
-   eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+   eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
   eu_length;
 
@@ -70,7 +69,7 @@ static int query_topology_info(struct drm_i915_private 
*dev_priv,
topo.subslice_offset = slice_length;
topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
-   topo.eu_stride = eu_stride;
+   topo.eu_stride = sseu->eu_stride;
 
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
   &topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 9a79d9d547c5..7de7b7b540cb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -118,10 +118,9 @@ void intel_device_info_dump_runtime(const struct 
intel_runtime_info *info,
 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
   int subslice)
 {
-   int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
-   int slice_stride = sseu->max_subslices * subslice_stride;
+   int slice_stride = sseu->max_subslices * sseu->eu_stride;
 
-   return slice * slice_stride + subslice * subslice_stride;
+   return slice * slice_stride + subslice * sseu->eu_stride;
 }
 
 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -130,7 +129,7 @@ static u16 sseu_get_eus(const struct sseu_dev_info *sseu, 
int slice,
int i, offset = sseu_eu_idx(sseu, slice, subslice);
u16 eu_mask = 0;
 
-   for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+   for (i = 0; i < sseu->eu_stride; i++) {
eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
(i * BITS_PER_BYTE);
}
@@ -143,7 +142,7 @@ static void sseu_set_eus(struct sseu_dev_info *sseu, int 
slice, int subslice,
 {
int i, offset = sseu_eu_idx(sseu, slice, subslice);
 
-   for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+   for (i = 0; i < sseu->eu_stride; i++) {
sseu->eu_mask[offset + i] =
(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
}
-- 
2.21.0.5.gaeb582a983

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[Intel-gfx] [PATCH 3/9] drm/i915: Add subslice stride runtime parameter

[Stuart Summers]

Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.

This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.

Signed-off-by: Stuart Summers 
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 2 ++
 drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
 drivers/gpu/drm/i915/i915_query.c| 5 ++---
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c 
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 08b74ae40739..2d9e6fa4ee46 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -14,6 +14,8 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 
max_slices,
sseu->max_slices = max_slices;
sseu->max_subslices = max_subslices;
sseu->max_eus_per_subslice = max_eus_per_subslice;
+
+   sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
 }
 
 unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h 
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 64e47dad07be..b0101e1c69bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,6 +33,8 @@ struct sseu_dev_info {
u8 max_subslices;
u8 max_eus_per_subslice;
 
+   u8 ss_stride;
+
/* We don't have more than 8 eus per subslice at the moment and as we
 * store eus enabled using bits, no need to multiply by eus per
 * subslice.
diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 7b7016171057..e4aeb7369026 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private 
*dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
-   u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
 
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private 
*dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
 
slice_length = sizeof(sseu->slice_mask);
-   subslice_length = sseu->max_slices * subslice_stride;
+   subslice_length = sseu->max_slices * sseu->ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
   eu_length;
@@ -69,7 +68,7 @@ static int query_topology_info(struct drm_i915_private 
*dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
 
topo.subslice_offset = slice_length;
-   topo.subslice_stride = subslice_stride;
+   topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
topo.eu_stride = eu_stride;
 
-- 
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[Intel-gfx] [PATCH 1/9] drm/i915: Use variable for debugfs device status

[Stuart Summers]

Use a local variable to find SSEU runtime information
in various debugfs functions.

Signed-off-by: Stuart Summers 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6d3911469801..14eadab4209b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3929,8 +3929,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
 
if (IS_GEN9_BC(dev_priv))
-   sseu->subslice_mask[s] =
-   RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+   sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3957,6 +3956,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
 struct sseu_dev_info *sseu)
 {
+   const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
int s;
 
@@ -3964,10 +3964,10 @@ static void broadwell_sseu_device_status(struct 
drm_i915_private *dev_priv,
 
if (sseu->slice_mask) {
sseu->eu_per_subslice =
-   RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
+   info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++) {
sseu->subslice_mask[s] =
-   RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+   info->sseu.subslice_mask[s];
}
sseu->eu_total = sseu->eu_per_subslice *
 intel_sseu_subslice_total(sseu);
@@ -3975,7 +3975,7 @@ static void broadwell_sseu_device_status(struct 
drm_i915_private *dev_priv,
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
u8 subslice_7eu =
-   RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
+   info->sseu.subslice_7eu[s];
 
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -4022,6 +4022,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool 
is_available_info,
 static int i915_sseu_status(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
 
@@ -4029,14 +4030,13 @@ static int i915_sseu_status(struct seq_file *m, void 
*unused)
return -ENODEV;
 
seq_puts(m, "SSEU Device Info\n");
-   i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
+   i915_print_sseu_info(m, true, &info->sseu);
 
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
-   sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
-   sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
-   sseu.max_eus_per_subslice =
-   RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
+   sseu.max_slices = info->sseu.max_slices;
+   sseu.max_subslices = info->sseu.max_subslices;
+   sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
 
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
-- 
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[Intel-gfx] [PATCH 2/9] drm/i915: Add function to set SSEU info per platform

[Stuart Summers]

Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.

Signed-off-by: Stuart Summers 
---
 drivers/gpu/drm/i915/gt/intel_sseu.c |  8 +
 drivers/gpu/drm/i915/gt/intel_sseu.h |  3 ++
 drivers/gpu/drm/i915/i915_debugfs.c  |  6 ++--
 drivers/gpu/drm/i915/intel_device_info.c | 39 +---
 4 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c 
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index a0756f006f5f..08b74ae40739 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -8,6 +8,14 @@
 #include "intel_lrc_reg.h"
 #include "intel_sseu.h"
 
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+u8 max_subslices, u8 max_eus_per_subslice)
+{
+   sseu->max_slices = max_slices;
+   sseu->max_subslices = max_subslices;
+   sseu->max_eus_per_subslice = max_eus_per_subslice;
+}
+
 unsigned int
 intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
 {
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h 
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b50d0401a4e2..64e47dad07be 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,9 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
 }
 
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+u8 max_subslices, u8 max_eus_per_subslice);
+
 unsigned int
 intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 14eadab4209b..011ed2fd391d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4034,9 +4034,9 @@ static int i915_sseu_status(struct seq_file *m, void 
*unused)
 
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
-   sseu.max_slices = info->sseu.max_slices;
-   sseu.max_subslices = info->sseu.max_subslices;
-   sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
+   intel_sseu_set_info(&sseu, info->sseu.max_slices,
+   info->sseu.max_subslices,
+   info->sseu.max_eus_per_subslice);
 
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..9a79d9d547c5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -191,15 +191,10 @@ static void gen11_sseu_info_init(struct drm_i915_private 
*dev_priv)
u8 eu_en;
int s;
 
-   if (IS_ELKHARTLAKE(dev_priv)) {
-   sseu->max_slices = 1;
-   sseu->max_subslices = 4;
-   sseu->max_eus_per_subslice = 8;
-   } else {
-   sseu->max_slices = 1;
-   sseu->max_subslices = 8;
-   sseu->max_eus_per_subslice = 8;
-   }
+   if (IS_ELKHARTLAKE(dev_priv))
+   intel_sseu_set_info(sseu, 1, 4, 8);
+   else
+   intel_sseu_set_info(sseu, 1, 8, 8);
 
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
@@ -236,11 +231,10 @@ static void gen10_sseu_info_init(struct drm_i915_private 
*dev_priv)
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
 
+   intel_sseu_set_info(sseu, 6, 4, 8);
+
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
-   sseu->max_slices = 6;
-   sseu->max_subslices = 4;
-   sseu->max_eus_per_subslice = 8;
 
subslice_mask = (1 << 4) - 1;
subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
@@ -314,9 +308,7 @@ static void cherryview_sseu_info_init(struct 
drm_i915_private *dev_priv)
fuse = I915_READ(CHV_FUSE_GT);
 
sseu->slice_mask = BIT(0);
-   sseu->max_slices = 1;
-   sseu->max_subslices = 2;
-   sseu->max_eus_per_subslice = 8;
+   intel_sseu_set_info(sseu, 1, 2, 8);
 
if (!(fuse & CHV_FGT_DISABLE_SS0)) {
u8 disabled_mask =
@@ -372,9 +364,8 @@ static void gen9_sseu_info_init(struct drm_i915_private 
*dev_priv)
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 
/* BXT has a single slice and at most 3 subslices. */
-   sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
-   sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
-   sseu->max_eus_per_subslice = 8;
+   intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
+   IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
 
/*
 * The subslice disable field is global, i.e. it applies
@@ -473,9 +464,7 @@ static void broadwell_sseu_inf

[Intel-gfx] [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice

[Stuart Summers]

Add a new function to determine whether a particular slice
has a given subslice.

Signed-off-by: Stuart Summers 
---
 drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++
 drivers/gpu/drm/i915/intel_device_info.c |  9 -
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h 
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 2261d4e7d98b..0ecc1c35a7a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -66,6 +66,16 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
 }
 
+static inline bool
+intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
+   int subslice)
+{
+   u8 mask = sseu->subslice_mask[slice * sseu->ss_stride +
+ subslice / BITS_PER_BYTE];
+
+   return mask & BIT(subslice % BITS_PER_BYTE);
+}
+
 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
 u8 max_subslices, u8 max_eus_per_subslice);
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 22b59fdb31fc..723b1fde5fc4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -210,10 +210,9 @@ static void gen11_sseu_info_init(struct drm_i915_private 
*dev_priv)
intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
  ss_en_mask);
 
-   for (ss = 0; ss < sseu->max_subslices; ss++) {
-   if (sseu->subslice_mask[s] & BIT(ss))
+   for (ss = 0; ss < sseu->max_subslices; ss++)
+   if (intel_sseu_has_subslice(sseu, s, ss))
sseu_set_eus(sseu, s, ss, eu_en);
-   }
}
}
sseu->eu_per_subslice = hweight8(eu_en);
@@ -399,7 +398,7 @@ static void gen9_sseu_info_init(struct drm_i915_private 
*dev_priv)
int eu_per_ss;
u8 eu_disabled_mask;
 
-   if (!(sseu->subslice_mask[s] & BIT(ss)))
+   if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
 
@@ -505,7 +504,7 @@ static void broadwell_sseu_info_init(struct 
drm_i915_private *dev_priv)
u8 eu_disabled_mask;
u32 n_disabled;
 
-   if (!(sseu->subslice_mask[s] & BIT(ss)))
+   if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
 
-- 
2.21.0.5.gaeb582a983

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[Intel-gfx] [PATCH 7/9] drm/i915: Refactor instdone loops on new subslice functions

[Stuart Summers]

Refactor instdone loops to use the new intel_sseu_has_subslice
function.

Signed-off-by: Stuart Summers 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c|  3 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 ++--
 drivers/gpu/drm/i915/gt/intel_hangcheck.c|  3 +-
 drivers/gpu/drm/i915/i915_debugfs.c  |  5 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c|  5 ++--
 5 files changed, 25 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 65cbf1d9118d..c42bc18e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1009,6 +1009,7 @@ void intel_engine_get_instdone(struct intel_engine_cs 
*engine,
   struct intel_instdone *instdone)
 {
struct drm_i915_private *i915 = engine->i915;
+   const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -1026,7 +1027,7 @@ void intel_engine_get_instdone(struct intel_engine_cs 
*engine,
 
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
-   for_each_instdone_slice_subslice(i915, slice, subslice) {
+   for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(engine, slice, subslice,
  GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 8be63019d707..6174b29045f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -540,20 +540,19 @@ intel_engine_is_virtual(const struct intel_engine_cs 
*engine)
return engine->flags & I915_ENGINE_IS_VIRTUAL;
 }
 
-#define instdone_slice_mask(dev_priv__) \
-   (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
-   (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
-   for ((slice__) = 0, (subslice__) = 0; \
-(slice__) < I915_MAX_SLICES; \
-(subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? 
(subslice__) + 1 : 0, \
-  (slice__) += ((subslice__) == 0)) \
-   for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && 
\
-   (BIT(subslice__) & 
instdone_subslice_mask(dev_priv__)))
-
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+   ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \
+   BIT(slice___))
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+   (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+intel_sseu_has_subslice(sseu__, 0, subslice__))
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+   for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+(subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+(slice_) += ((subslice_) == 0)) \
+   for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+   (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+   subslice_)))
 #endif /* __INTEL_ENGINE_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c 
b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index 05d042cdefe2..40f62f780be5 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -53,6 +53,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 
*old_instdone)
 static bool subunits_stuck(struct intel_engine_cs *engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
+   const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_instdone instdone;
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
bool stuck;
@@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
stuck &= instdone_unchanged(instdone.slice_common,
&accu_instdone->slice_common);
 
-   for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+   for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
stuck &= instdone_unchanged(instdone.sampler[slice][subslice],

&accu_instdone->sampler[slice][subslice]);
stuck &= instdone_unchanged(instdone.row[slice][subslice],
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu

[Intel-gfx] [PATCH 0/9] Refactor to expand subslice mask (rev 2)

[Stuart Summers]

Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
  slice * subslice stride + subslice index / 8

Note this is the second iteration of an original patch to implement
the same. There are a couple of minor code changes based on changes
since the first series was posted. Additionally, the original patch
has been split into several smaller patches with more isolated
changes based on review feedback in that first series.

Link to the original series:
https://patchwork.freedesktop.org/series/59742/

v2: Fix 32-bit build

Stuart Summers (9):
  drm/i915: Use variable for debugfs device status
  drm/i915: Add function to set SSEU info per platform
  drm/i915: Add subslice stride runtime parameter
  drm/i915: Add EU stride runtime parameter
  drm/i915: Add function to set subslices
  drm/i915: Add function to determine if a slice has a subslice
  drm/i915: Refactor instdone loops on new subslice functions
  drm/i915: Add new function to copy subslices for a slice
  drm/i915: Expand subslice mask

 drivers/gpu/drm/i915/gt/intel_engine_cs.c|   3 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  31 +++--
 drivers/gpu/drm/i915/gt/intel_hangcheck.c|   3 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c |  48 +++-
 drivers/gpu/drm/i915/gt/intel_sseu.h |  24 +++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c  |   3 +-
 drivers/gpu/drm/i915/i915_debugfs.c  |  47 +---
 drivers/gpu/drm/i915/i915_gpu_error.c|   5 +-
 drivers/gpu/drm/i915/i915_query.c|  10 +-
 drivers/gpu/drm/i915/intel_device_info.c | 118 +--
 10 files changed, 185 insertions(+), 107 deletions(-)

-- 
2.21.0.5.gaeb582a983

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[Intel-gfx] [PATCH 5/9] drm/i915: Add function to set subslices

[Stuart Summers]

Add a new function to set a range of subslices for a
specified slice based on a given mask.

Signed-off-by: Stuart Summers 
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 10 +
 drivers/gpu/drm/i915/gt/intel_sseu.h |  3 ++
 drivers/gpu/drm/i915/intel_device_info.c | 53 ++--
 3 files changed, 45 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c 
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 71abf0c9a46b..607c1447287c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -30,6 +30,16 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
 }
 
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u32 ss_mask)
+{
+   int i, offset = slice * sseu->ss_stride;
+
+   for (i = 0; i < sseu->ss_stride; i++)
+   sseu->subslice_mask[offset + i] =
+   (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
+}
+
 unsigned int
 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
 {
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h 
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index fe22d5b18e67..2261d4e7d98b 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -75,6 +75,9 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
 unsigned int
 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
 
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u32 ss_mask);
+
 u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
 const struct intel_sseu *req_sseu);
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 7de7b7b540cb..22b59fdb31fc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -206,7 +206,10 @@ static void gen11_sseu_info_init(struct drm_i915_private 
*dev_priv)
int ss;
 
sseu->slice_mask |= BIT(s);
-   sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+
+   intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
+ ss_en_mask);
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu->subslice_mask[s] & BIT(ss))
sseu_set_eus(sseu, s, ss, eu_en);
@@ -235,14 +238,6 @@ static void gen10_sseu_info_init(struct drm_i915_private 
*dev_priv)
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
 
-   subslice_mask = (1 << 4) - 1;
-   subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
-  GEN10_F2_SS_DIS_SHIFT);
-
-   /*
-* Slice0 can have up to 3 subslices, but there are only 2 in
-* slice1/2.
-*/
sseu->subslice_mask[0] = subslice_mask;
for (s = 1; s < sseu->max_slices; s++)
sseu->subslice_mask[s] = subslice_mask & 0x3;
@@ -270,14 +265,25 @@ static void gen10_sseu_info_init(struct drm_i915_private 
*dev_priv)
eu_en = ~I915_READ(GEN10_EU_DISABLE3);
sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
 
-   /* Do a second pass where we mark the subslices disabled if all their
-* eus are off.
-*/
+   subslice_mask = (1 << 4) - 1;
+   subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+  GEN10_F2_SS_DIS_SHIFT);
+
for (s = 0; s < sseu->max_slices; s++) {
+   u32 subslice_mask_with_eus = subslice_mask;
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu_get_eus(sseu, s, ss) == 0)
-   sseu->subslice_mask[s] &= ~BIT(ss);
+   subslice_mask_with_eus &= ~BIT(ss);
}
+
+   /*
+* Slice0 can have up to 3 subslices, but there are only 2 in
+* slice1/2.
+*/
+   intel_sseu_set_subslices(sseu, s, s == 0 ?
+ subslice_mask_with_eus :
+ subslice_mask_with_eus & 0x3);
}
 
sseu->eu_total = compute_eu_total(sseu);
@@ -303,6 +309,7 @@ static void cherryview_sseu_info_init(struct 
drm_i915_private *dev_priv)
 {
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse;
+   u8 subslice_mask;
 
fuse = I915_READ(CHV_FUSE_GT);
 
@@ -316,7 +323,7 @@ static void cherryview_sseu_info_init(struct 
drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
 
-   sseu->subslice_mask[0] |= BIT

[Intel-gfx] [PATCH 9/9] drm/i915: Expand subslice mask

[Stuart Summers]

Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
  slice * subslice stride + subslice index / 8

v2: Fix 32-bit build

Signed-off-by: Stuart Summers 
---
 drivers/gpu/drm/i915/gt/intel_sseu.c| 27 -
 drivers/gpu/drm/i915/gt/intel_sseu.h|  5 +++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  3 +--
 drivers/gpu/drm/i915/i915_debugfs.c |  5 +++-
 drivers/gpu/drm/i915/intel_device_info.c|  8 +++---
 5 files changed, 39 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c 
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 607c1447287c..e426f34b4dd6 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -30,6 +30,31 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
 }
 
+u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
+{
+   int i, offset = slice * sseu->ss_stride;
+   u32 mask = 0;
+
+   if (slice >= sseu->max_slices) {
+   DRM_ERROR("%s: invalid slice %d, max: %d\n",
+ __func__, slice, sseu->max_slices);
+   return 0;
+   }
+
+   if (sseu->ss_stride > sizeof(mask)) {
+   DRM_ERROR("%s: invalid subslice stride %d, max: %u\n",
+ __func__, sseu->ss_stride,
+(unsigned int)sizeof(mask));
+   return 0;
+   }
+
+   for (i = 0; i < sseu->ss_stride; i++)
+   mask |= (u32)sseu->subslice_mask[offset + i] <<
+   i * BITS_PER_BYTE;
+
+   return mask;
+}
+
 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
  u32 ss_mask)
 {
@@ -43,7 +68,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int 
slice,
 unsigned int
 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
 {
-   return hweight8(sseu->subslice_mask[slice]);
+   return hweight32(intel_sseu_get_subslices(sseu, slice));
 }
 
 u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h 
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 0ecc1c35a7a1..2291764b7db5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -15,10 +15,11 @@ struct drm_i915_private;
 #define GEN_MAX_SLICES (6) /* CNL upper bound */
 #define GEN_MAX_SUBSLICES  (8) /* ICL upper bound */
 #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
 
 struct sseu_dev_info {
u8 slice_mask;
-   u8 subslice_mask[GEN_MAX_SLICES];
+   u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -85,6 +86,8 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
 unsigned int
 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
 
+u32  intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+
 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
  u32 ss_mask);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..7ec60435d871 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -794,8 +794,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct 
i915_wa_list *wal)
}
 
slice = fls(sseu->slice_mask) - 1;
-   GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
-   subslice = fls(l3_en & sseu->subslice_mask[slice]);
+   subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
if (!subslice) {
DRM_WARN("No common index found between subslice mask %x and L3 
bank mask %x!\n",
 sseu->subslice_mask[slice], l3_en);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7f842506b9ea..96a25a770ade 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3944,13 +3944,16 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
 
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
+   u8 ss_idx = s * info->sseu.ss_stride +
+   ss / BITS_PER_BYTE;
 
if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
/* skip disabled subslice */
continue;
 
-

[Intel-gfx] [PATCH 8/9] drm/i915: Add new function to copy subslices for a slice

[Stuart Summers]

Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status.

Signed-off-by: Stuart Summers 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 21 +++--
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index a61d31fc482f..7f842506b9ea 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3806,6 +3806,15 @@ i915_cache_sharing_set(void *data, u64 val)
return 0;
 }
 
+static void
+intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,
+ u8 *to_mask)
+{
+   int offset = slice * sseu->ss_stride;
+
+   memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
+}
+
 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
i915_cache_sharing_get, i915_cache_sharing_set,
"%llu\n");
@@ -3879,7 +3888,7 @@ static void gen10_sseu_device_status(struct 
drm_i915_private *dev_priv,
continue;
 
sseu->slice_mask |= BIT(s);
-   sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+   intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
 
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3930,7 +3939,8 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
 
if (IS_GEN9_BC(dev_priv))
-   sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+   intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
 
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3966,10 +3976,9 @@ static void broadwell_sseu_device_status(struct 
drm_i915_private *dev_priv,
if (sseu->slice_mask) {
sseu->eu_per_subslice =
info->sseu.eu_per_subslice;
-   for (s = 0; s < fls(sseu->slice_mask); s++) {
-   sseu->subslice_mask[s] =
-   info->sseu.subslice_mask[s];
-   }
+   for (s = 0; s < fls(sseu->slice_mask); s++)
+   intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
sseu->eu_total = sseu->eu_per_subslice *
 intel_sseu_subslice_total(sseu);
 
-- 
2.21.0.5.gaeb582a983

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Fix premature release of context on reset

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Fix premature release of context on reset
URL   : https://patchwork.freedesktop.org/series/64181/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13737


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/

Known issues


  Here are the changes found in Patchwork_13737 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850:   [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_mmap_gtt@basic-small-bo-tiledx:
- fi-icl-u3:  [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 
similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledx.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][5] -> [FAIL][6] ([fdo#109485])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
 Possible fixes 

  * igt@gem_ctx_create@basic-files:
- fi-icl-u2:  [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) -> 
[PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html

  * igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [INCOMPLETE][9] ([fdo#108744]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u:   [WARN][11] ([fdo#109380]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][13] ([fdo#103167]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u:   [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13737/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049


Participating hosts (52 -> 44)
--

  Additional (1): fi-skl-gvtdvm 
  Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6545 -> Patchwork_13737

  CI-20190529: 20190529
  CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patc

Re: [Intel-gfx] [PATCH v2 3/8] drm/i915/uc: Unify uc_fw status tracking

[Daniele Ceraolo Spurio]

On 7/24/2019 5:35 AM, Michal Wajdeczko wrote:
On Wed, 24 Jul 2019 04:21:48 +0200, Daniele Ceraolo Spurio 
 wrote:



We currently track fetch and load status separately, but the 2 are
actually sequential in the uc lifetime (fetch must complete before we
can attempt the load!). Unifying the 2 variables we can better follow
the sequential states and improve our trackng of the uC state.

Also, sprinkle some GEM_BUG_ON to make sure we transition correctly
between states.

v2: rename states, add the running state (Michal), drop some logs in
    the fetch path (Michal, Chris)

Suggested-by: Michal Wajdeczko 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h    |  4 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  6 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc.c    |  8 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc.h    |  5 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 10 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 86 +++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  | 58 -
 8 files changed, 89 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h

index 6852352381ce..f51c4c3c1d0b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -169,9 +169,9 @@ int intel_guc_suspend(struct intel_guc *guc);
 int intel_guc_resume(struct intel_guc *guc);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 
size);

-static inline bool intel_guc_is_loaded(struct intel_guc *guc)
+static inline bool intel_guc_is_running(struct intel_guc *guc)
 {
-    return intel_uc_fw_is_loaded(&guc->fw);
+    return intel_uc_fw_is_running(&guc->fw);
 }
static inline int intel_guc_sanitize(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

index a027deb80330..085e7842ef8a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -232,5 +232,9 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
  */
 int intel_guc_fw_upload(struct intel_guc *guc)
 {
-    return intel_uc_fw_upload(&guc->fw, guc_fw_xfer);
+    int ret = intel_uc_fw_upload(&guc->fw, guc_fw_xfer);
+    if (!ret)
+    guc->fw.status = INTEL_UC_FIRMWARE_RUNNING;


we should already know that in guc_fw_xfer/guc_xfer_ucode
see below for details


+
+    return ret;
 }
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

index a0f2a01365bc..b4238fe16a03 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -941,7 +941,7 @@ static void __guc_client_disable(struct 
intel_guc_client *client)
  * the case, instead of trying (in vain) to communicate with it, 
let's

  * just cleanup the doorbell HW and our internal state.
  */
-    if (intel_guc_is_loaded(client->guc))
+    if (intel_guc_is_running(client->guc))
 destroy_doorbell(client);
 else
 __fini_doorbell(client);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c

index ab6c1564b6a7..7804ea5f699c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -117,8 +117,8 @@ int intel_huc_auth(struct intel_huc *huc)
 struct intel_guc *guc = >->uc.guc;
 int ret;
-    if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-    return -ENOEXEC;
+    GEM_BUG_ON(!intel_uc_fw_is_loaded(&huc->fw));
+    GEM_BUG_ON(intel_huc_is_authenticated(huc));
ret = intel_guc_auth_huc(guc,
  intel_guc_ggtt_offset(guc, huc->rsa_data));
@@ -138,10 +138,12 @@ int intel_huc_auth(struct intel_huc *huc)
 goto fail;
 }
+    huc->fw.status = INTEL_UC_FIRMWARE_RUNNING;
+
 return 0;
fail:
-    huc->fw.load_status = INTEL_UC_FIRMWARE_FAIL;
+    huc->fw.status = INTEL_UC_FIRMWARE_LOAD_FAIL;
DRM_ERROR("HuC: Authentication failed %d\n", ret);
 return ret;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h

index 9fa3d4629f2e..ea340f85bc46 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -56,4 +56,9 @@ static inline int intel_huc_sanitize(struct 
intel_huc *huc)

 return 0;
 }
+static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
+{
+    return intel_uc_fw_is_running(&huc->fw);
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c

index d60c56fd72e5..b761809946b1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -559,7 +559,7 @@ void intel_uc_fini_hw(struct intel_uc *uc)
 {
 struct intel_guc *guc = &uc->guc;
-    if (!intel_guc_i

[Intel-gfx] ✓ Fi.CI.BAT: success for Associate ddc adapters with connectors (rev2)

[Patchwork]

== Series Details ==

Series: Associate ddc adapters with connectors (rev2)
URL   : https://patchwork.freedesktop.org/series/63558/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13736


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/

Known issues


  Here are the changes found in Patchwork_13736 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_module_load@reload-no-display:
- fi-icl-u3:  [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@i915_module_l...@reload-no-display.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/fi-icl-u3/igt@i915_module_l...@reload-no-display.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][3] -> [FAIL][4] ([fdo#109485])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-guc: [PASS][5] -> [FAIL][6] ([fdo#103167])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-guc/igt@kms_frontbuffer_track...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/fi-icl-guc/igt@kms_frontbuffer_track...@basic.html

  
 Possible fixes 

  * igt@gem_ctx_create@basic-files:
- fi-icl-u2:  [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) -> 
[PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u:   [WARN][9] ([fdo#109380]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3:  [FAIL][11] ([fdo#103167]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
- {fi-icl-u4}:[FAIL][13] ([fdo#103167]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u:   [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13736/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049


Participating hosts (52 -> 44)
--

  Additional (1): fi-skl-gvtdvm 
  Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6700k2 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6545 -> Patchwork_13736

  CI-20190529: 20190529
  CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13736: 487373549079a66faee3f96549b7cc375ced6bf8 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

487373549079 drm/i915: Provide ddc symlink in hdmi connector sysfs directory

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Unshare the idle-barrier from other kernel requests (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Unshare the idle-barrier from other kernel requests (rev2)
URL   : https://patchwork.freedesktop.org/series/64171/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13735


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_13735 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13735, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13735/

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_13735:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2520m:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13735/fi-snb-2520m/igt@i915_module_l...@reload-with-fault-injection.html

  
Known issues


  Here are the changes found in Patchwork_13735 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u:   [PASS][3] -> [DMESG-WARN][4] ([fdo#105128] / 
[fdo#107139])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13735/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html

  * igt@kms_busy@basic-flip-a:
- fi-kbl-7567u:   [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278]) 
+2 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13735/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][7] -> [FAIL][8] ([fdo#109485])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13735/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-guc: [PASS][9] -> [FAIL][10] ([fdo#103167])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-guc/igt@kms_frontbuffer_track...@basic.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13735/fi-icl-guc/igt@kms_frontbuffer_track...@basic.html

  
 Possible fixes 

  * igt@gem_ctx_create@basic-files:
- fi-icl-u2:  [INCOMPLETE][11] ([fdo#107713] / [fdo#109100]) -> 
[PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13735/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049


Participating hosts (52 -> 43)
--

  Additional (1): fi-skl-gvtdvm 
  Missing(10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-cfl-8109u fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6545 -> Patchwork_13735

  CI-20190529: 20190529
  CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13735: cf9d7252c06a11879a9cce16ad324a64f7055892 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

cf9d7252c06a drm/i915: Unshare the idle-barrier from oth

Re: [Intel-gfx] [PATCH v2 2/8] drm/i915/uc: Unify uC FW selection

[Daniele Ceraolo Spurio]

On 7/24/2019 4:31 AM, Michal Wajdeczko wrote:
On Wed, 24 Jul 2019 04:21:47 +0200, Daniele Ceraolo Spurio 
 wrote:



Instead of having 2 identical functions for GuC and HuC firmware
selection, we can unify the selection logic and just use different lists
based on FW type.

Note that the revid is not relevant for current blobs, but the upcoming
CML will be identified as CFL rev 5, so by considering the revid we're
ready for that.

v2: rework blob list defs (Michal), add order check (Chris), fuse GuC
    and HuC lists into one.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Anusha Srivatsa 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  86 +---
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  88 +---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 156 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  29 ++--
 4 files changed, 167 insertions(+), 192 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

index 87169e826747..a027deb80330 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -31,89 +31,6 @@
 #include "intel_guc_fw.h"
 #include "i915_drv.h"
-#define __MAKE_GUC_FW_PATH(KEY) \
-    "i915/" \
-    __stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
-    __stringify(KEY##_GUC_FW_MAJOR) "." \
-    __stringify(KEY##_GUC_FW_MINOR) "." \
-    __stringify(KEY##_GUC_FW_PATCH) ".bin"
-
-#define SKL_GUC_FW_PREFIX skl
-#define SKL_GUC_FW_MAJOR 33
-#define SKL_GUC_FW_MINOR 0
-#define SKL_GUC_FW_PATCH 0
-#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
-MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
-
-#define BXT_GUC_FW_PREFIX bxt
-#define BXT_GUC_FW_MAJOR 33
-#define BXT_GUC_FW_MINOR 0
-#define BXT_GUC_FW_PATCH 0
-#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
-MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
-
-#define KBL_GUC_FW_PREFIX kbl
-#define KBL_GUC_FW_MAJOR 33
-#define KBL_GUC_FW_MINOR 0
-#define KBL_GUC_FW_PATCH 0
-#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
-MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
-
-#define GLK_GUC_FW_PREFIX glk
-#define GLK_GUC_FW_MAJOR 33
-#define GLK_GUC_FW_MINOR 0
-#define GLK_GUC_FW_PATCH 0
-#define GLK_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(GLK)
-MODULE_FIRMWARE(GLK_GUC_FIRMWARE_PATH);
-
-#define ICL_GUC_FW_PREFIX icl
-#define ICL_GUC_FW_MAJOR 33
-#define ICL_GUC_FW_MINOR 0
-#define ICL_GUC_FW_PATCH 0
-#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
-MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
-
-static void guc_fw_select(struct intel_uc_fw *guc_fw)
-{
-    struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
-    struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
-    GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
-
-    if (!HAS_GT_UC(i915)) {
-    guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
-    return;
-    }
-
-    guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
-
-    if (i915_modparams.guc_firmware_path) {
-    guc_fw->path = i915_modparams.guc_firmware_path;
-    guc_fw->major_ver_wanted = 0;
-    guc_fw->minor_ver_wanted = 0;
-    } else if (IS_ICELAKE(i915)) {
-    guc_fw->path = ICL_GUC_FIRMWARE_PATH;
-    guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
-    guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
-    } else if (IS_GEMINILAKE(i915)) {
-    guc_fw->path = GLK_GUC_FIRMWARE_PATH;
-    guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
-    guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
-    } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
-    guc_fw->path = KBL_GUC_FIRMWARE_PATH;
-    guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
-    guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
-    } else if (IS_BROXTON(i915)) {
-    guc_fw->path = BXT_GUC_FIRMWARE_PATH;
-    guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
-    guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
-    } else if (IS_SKYLAKE(i915)) {
-    guc_fw->path = SKL_GUC_FIRMWARE_PATH;
-    guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
-    guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
-    }
-}
-
 /**
  * intel_guc_fw_init_early() - initializes GuC firmware struct
  * @guc: intel_guc struct
@@ -124,8 +41,7 @@ void intel_guc_fw_init_early(struct intel_guc *guc)
 {
 struct intel_uc_fw *guc_fw = &guc->fw;
-    intel_uc_fw_init_early(guc_fw, INTEL_UC_FW_TYPE_GUC);
-    guc_fw_select(guc_fw);
+    intel_uc_fw_init_early(guc_to_gt(guc)->i915, guc_fw, 
INTEL_UC_FW_TYPE_GUC);

 }
static void guc_prepare_xfer(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c

index ff6f7b157ecb..fa2151fa3a13 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -23,91 +23,6 @@
  * Note that HuC firmware loading must be done before GuC loading.
  */
-#define BXT_HUC_FW_MAJOR 01
-#define BXT_HUC_FW_MINOR 8
-#define BXT_BLD_N

[Intel-gfx] [PATCH] drm/i915/gem: Make caps.scheduler static

[Chris Wilson]

We do not notify userspace when the scheduler capabilities are changed
(due to wedging the driver) and as such userspace will expect the caps
to be static and unchanging. Make it so, and so we only need to compute
our caps once during driver registration.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c   |  6 +++---
 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c |  4 ++--
 drivers/gpu/drm/i915/gt/intel_reset.c  |  5 +
 drivers/gpu/drm/i915/i915_drv.c|  4 ++--
 drivers/gpu/drm/i915/i915_drv.h|  6 --
 drivers/gpu/drm/i915/i915_gem.c| 13 +++--
 drivers/gpu/drm/i915/i915_request.c|  2 --
 7 files changed, 23 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 3f4c6bdcc3c3..b186bb5bfb44 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -460,12 +460,12 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, 
unsigned long event, void *ptr
 }
 
 /**
- * i915_gem_shrinker_register - Register the i915 shrinker
+ * i915_gem_driver_register__shrinker - Register the i915 shrinker
  * @i915: i915 device
  *
  * This function registers and sets up the i915 shrinker and OOM handler.
  */
-void i915_gem_shrinker_register(struct drm_i915_private *i915)
+void i915_gem_driver_register__shrinker(struct drm_i915_private *i915)
 {
i915->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
i915->mm.shrinker.count_objects = i915_gem_shrinker_count;
@@ -486,7 +486,7 @@ void i915_gem_shrinker_register(struct drm_i915_private 
*i915)
  *
  * This function unregisters the i915 shrinker and OOM handler.
  */
-void i915_gem_shrinker_unregister(struct drm_i915_private *i915)
+void i915_gem_driver_unregister__shrinker(struct drm_i915_private *i915)
 {
WARN_ON(unregister_vmap_purge_notifier(&i915->mm.vmap_notifier));
WARN_ON(unregister_oom_notifier(&i915->mm.oom_notifier));
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 01857c12f12f..50aa7e95124d 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -382,7 +382,7 @@ static bool assert_mmap_offset(struct drm_i915_private 
*i915,
 
 static void disable_retire_worker(struct drm_i915_private *i915)
 {
-   i915_gem_shrinker_unregister(i915);
+   i915_gem_driver_unregister__shrinker(i915);
 
intel_gt_pm_get(&i915->gt);
 
@@ -398,7 +398,7 @@ static void restore_retire_worker(struct drm_i915_private 
*i915)
igt_flush_test(i915, I915_WAIT_LOCKED);
mutex_unlock(&i915->drm.struct_mutex);
 
-   i915_gem_shrinker_register(i915);
+   i915_gem_driver_register__shrinker(i915);
 }
 
 static void mmap_offset_lock(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 55e2ddcbd215..7f51dbcd872f 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -757,11 +757,8 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
__intel_gt_reset(gt, ALL_ENGINES);
 
-   for_each_engine(engine, gt->i915, id) {
+   for_each_engine(engine, gt->i915, id)
engine->submit_request = nop_submit_request;
-   engine->schedule = NULL;
-   }
-   gt->i915->caps.scheduler = 0;
 
/*
 * Make sure no request can slip through without getting completed by
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f2d3d754af37..007bc0d06237 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1712,7 +1712,7 @@ static void i915_driver_register(struct drm_i915_private 
*dev_priv)
 {
struct drm_device *dev = &dev_priv->drm;
 
-   i915_gem_shrinker_register(dev_priv);
+   i915_gem_driver_register(dev_priv);
i915_pmu_register(dev_priv);
 
/*
@@ -1792,7 +1792,7 @@ static void i915_driver_unregister(struct 
drm_i915_private *dev_priv)
i915_teardown_sysfs(dev_priv);
drm_dev_unplug(&dev_priv->drm);
 
-   i915_gem_shrinker_unregister(dev_priv);
+   i915_gem_driver_unregister(dev_priv);
 }
 
 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0e44cc4b2ca1..a77eb242e15b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2491,6 +2491,8 @@ static inline u32 i915_reset_engine_count(struct 
i915_gpu_error *error,
 void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Split i915_gem_init_hw into GT and i915 parts (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Split i915_gem_init_hw into GT and 
i915 parts (rev2)
URL   : https://patchwork.freedesktop.org/series/64164/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13734


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/

Known issues


  Here are the changes found in Patchwork_13734 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@prime_vgem@basic-read:
- fi-icl-u3:  [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 
similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@prime_v...@basic-read.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/fi-icl-u3/igt@prime_v...@basic-read.html

  
 Possible fixes 

  * igt@gem_ctx_create@basic-files:
- fi-icl-u2:  [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) -> 
[PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html

  * igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [INCOMPLETE][5] ([fdo#108744]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3:  [FAIL][7] ([fdo#103167]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
- {fi-icl-u4}:[FAIL][9] ([fdo#103167]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049


Participating hosts (52 -> 45)
--

  Additional (1): fi-skl-gvtdvm 
  Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6545 -> Patchwork_13734

  CI-20190529: 20190529
  CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13734: 2bb6895f13074324ef118f3e334a52c01a8b8263 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2bb6895f1307 drm/i915: Make pm_notify take intel_gt
148551c9968e drm/i915: Avoid round-trip via i915 in intel_gt_park
214d132b3397 drm/i915: Make wait_for_timelines take struct intel_gt
559c263d5ce7 drm/i915: Avoid one round-tip through global i915 when getting to 
gt
fcdfcb9cdc46 drm/i915: Split i915_gem_init_hw into GT and i915 parts

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13734/
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Re: [Intel-gfx] [RFC PATCH] drm/i915/guc: Fix premature release of context on reset

[Chris Wilson]

Quoting Janusz Krzysztofik (2019-07-24 16:05:25)
> When using GuC submission, some execlists originated helper functions
> are reused.  One of them, used inside guc_reset() and
> guc_cancel_requests() callbacks introduced by commit 292ad25c22d9
> ("drm/i915/guc: Implement reset locally"), unfortunately calls
> execlists_schedule_out() helper instead of its GuC specific equivalent.
> As execlists functions maintain context references for themselves, that
> helper releases a context associated with a request being processed as
> soon as the context inflight queue becomes empty.  Since GuC submission
> doesn't keep extra context references, possibly still active contexts
> may be released prematurely, resulting in kernel panic.

Fwiw, that rq->context->inflight = NULL in schedule_out() is not
protected against a dangling dereference. Which, if you are not falling
into the execlists trap, you can remove entirely to avoid the potential
use-after-free.
-Chris
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Re: [Intel-gfx] [RFC PATCH] drm/i915/guc: Fix premature release of context on reset

[Chris Wilson]

Quoting Janusz Krzysztofik (2019-07-24 16:05:25)
> When using GuC submission, some execlists originated helper functions
> are reused.  One of them, used inside guc_reset() and
> guc_cancel_requests() callbacks introduced by commit 292ad25c22d9
> ("drm/i915/guc: Implement reset locally"), unfortunately calls
> execlists_schedule_out() helper instead of its GuC specific equivalent.
> As execlists functions maintain context references for themselves, that
> helper releases a context associated with a request being processed as
> soon as the context inflight queue becomes empty.  Since GuC submission
> doesn't keep extra context references, possibly still active contexts
> may be released prematurely, resulting in kernel panic.
> 
> Fix it by providing a local, modified copy of
> execlists_cancel_port_requests() helper.

Then remove the export and stub.
-Chris
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[Intel-gfx] [RFC PATCH] drm/i915/guc: Fix premature release of context on reset

[Janusz Krzysztofik]

When using GuC submission, some execlists originated helper functions
are reused.  One of them, used inside guc_reset() and
guc_cancel_requests() callbacks introduced by commit 292ad25c22d9
("drm/i915/guc: Implement reset locally"), unfortunately calls
execlists_schedule_out() helper instead of its GuC specific equivalent.
As execlists functions maintain context references for themselves, that
helper releases a context associated with a request being processed as
soon as the context inflight queue becomes empty.  Since GuC submission
doesn't keep extra context references, possibly still active contexts
may be released prematurely, resulting in kernel panic.

Fix it by providing a local, modified copy of
execlists_cancel_port_requests() helper.

Fixes: 292ad25c22d9 ("drm/i915/guc: Implement reset locally")
Signed-off-by: Janusz Krzysztofik 
---
Based on drm-intel-next-queued as of 2019-07-24, can be rebased easily
on top of drm-intel-next-2019-07-08 if needed (source file moved).

 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0f2a01365bc..b1ea7a818d61 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -651,6 +651,21 @@ static void guc_reset_prepare(struct intel_engine_cs 
*engine)
__tasklet_disable_sync_once(&execlists->tasklet);
 }
 
+static void
+cancel_port_requests(struct intel_engine_execlists * const execlists)
+{
+   struct i915_request * const *port, *rq;
+
+   for (port = execlists->pending; (rq = *port); port++)
+   schedule_out(rq);
+   memset(execlists->pending, 0, sizeof(execlists->pending));
+
+   for (port = execlists->active; (rq = *port); port++)
+   schedule_out(rq);
+   execlists->active =
+   memset(execlists->inflight, 0, sizeof(execlists->inflight));
+}
+
 static void guc_reset(struct intel_engine_cs *engine, bool stalled)
 {
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -659,7 +674,7 @@ static void guc_reset(struct intel_engine_cs *engine, bool 
stalled)
 
spin_lock_irqsave(&engine->active.lock, flags);
 
-   execlists_cancel_port_requests(execlists);
+   cancel_port_requests(execlists);
 
/* Push back any incomplete requests for replay after the reset. */
rq = execlists_unwind_incomplete_requests(execlists);
@@ -702,7 +717,7 @@ static void guc_cancel_requests(struct intel_engine_cs 
*engine)
spin_lock_irqsave(&engine->active.lock, flags);
 
/* Cancel the requests on the HW and clear the ELSP tracker. */
-   execlists_cancel_port_requests(execlists);
+   cancel_port_requests(execlists);
 
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, &engine->active.requests, sched.link) {
-- 
2.21.0

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Re: [Intel-gfx] [PATCH] drm/i915: Disable atomics in L3 for gen9

[Chris Wilson]

Quoting Francisco Jerez (2019-07-23 23:19:13)
> Chris Wilson  writes:
> 
> > Quoting Tvrtko Ursulin (2019-07-22 12:41:36)
> >> 
> >> On 20/07/2019 15:31, Chris Wilson wrote:
> >> > Enabling atomic operations in L3 leads to unrecoverable GPU hangs, as
> >> > the machine stops responding milliseconds after receipt of the reset
> >> > request [GDRT]. By disabling the cached atomics, the hang do not occur
> >> > and we presume the GPU would reset normally for similar hangs.
> >> > 
> >> > Reported-by: Jason Ekstrand 
> >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110998
> >> > Signed-off-by: Chris Wilson 
> >> > Cc: Jason Ekstrand 
> >> > Cc: Mika Kuoppala 
> >> > Cc: Tvrtko Ursulin 
> >> > ---
> >> > Jason reports that Windows is not clearing L3SQCREG4:22 and does not
> >> > suffer the same GPU hang so it is likely some other w/a that interacts
> >> > badly. Fwiw, these 3 are the only registers I could find that mention
> >> > atomic ops (and appear to be part of the same chain for memory access).
> >> 
> >> Bit-toggling itself looks fine to me and matches what I could find in 
> >> the docs. (All three bits across three registers should be equal.)
> >> 
> >> What I am curious about is what are the other consequences of disabling 
> >> L3 atomics? Performance drop somewhere?
> >
> > The test I have where it goes from dead to passing, that's a considerable
> > performance improvement ;)
> >
> > I imagine not being able to use L3 for atomics is pretty dire, whether that
> > has any impact, I have no clue.
> >
> > It is still very likely that we see this because we are doing something
> > wrong elsewhere.
> 
> This reminds me of f3fc4884ebe6ae649d3723be14b219230d3b7fd2 followed by
> d351f6d94893f3ba98b1b20c5ef44c35fc1da124 due to the massive impact (of
> the order of 20x IIRC) using the L3 turned out to have on the
> performance of HDC atomics, on at least that platform.  It seems
> unfortunate that we're going to lose L3 atomics on Gen9 now, even though
> it's only buffer atomics which are broken IIUC, and even though the
> Windows driver is somehow getting away without disabling them.  Some of
> our setup must be wrong either in the kernel or in userspace...  Are
> these registers at least whitelisted so userspace can re-enable L3
> atomics once the problem is addressed?  Wouldn't it be a more specific
> workaround for userspace to simply use a non-L3-cacheable MOCS for
> (rarely used) buffer surfaces, so it could benefit from L3 atomics
> elsewhere?

If it was the case that disabling L3 atomics was the only way to prevent
the machine lockup under this scenario, then I think it is
unquestionably the right thing to do, and we could not leave it to
userspace to dtrt. We should never add non-context saved unsafe
registers to the whitelist (if setting a register may cause data
corruption or worse in another context/process, that is bad) despite our
repeated transgressions. However, there's no evidence to say that it does
prevent the machine lockup as it prevents the GPU hang that lead to the
lockup on reset.

Other than GPGPU requiring a flush around every sneeze, I did not see
anything in the gen9 w/a list that seemed like a match. Nevertheless, I
expect there is a more precise w/a than a blanket disable.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Associate ddc adapters with connectors (rev2)

[Patchwork]

== Series Details ==

Series: Associate ddc adapters with connectors (rev2)
URL   : https://patchwork.freedesktop.org/series/63558/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8ca228e56f33 drm: Include ddc adapter pointer in struct drm_connector
c9a7fb60189d drm: Add drm_connector_init() variant with ddc
4adc3b29752a drm/exynos: Provide ddc symlink in connector's sysfs
7395cfe8627d drm: rockchip: Provide ddc symlink in rk3066_hdmi sysfs directory
a1de63da5081 drm: rockchip: Provide ddc symlink in inno_hdmi sysfs directory
9458c216387c drm/msm/hdmi: Provide ddc symlink in hdmi connector sysfs directory
e1ee513d8c74 drm/sun4i: hdmi: Provide ddc symlink in sun4i hdmi connector sysfs 
directory
e50a1716e2a6 drm/mediatek: Provide ddc symlink in hdmi connector sysfs directory
b1070c17513f drm/tegra: Provide ddc symlink in output connector sysfs directory
f1b20c1372ed drm/imx: imx-ldb: Provide ddc symlink in connector's sysfs
c33c830e605c drm/imx: imx-tve: Provide ddc symlink in connector's sysfs
98b2fbe1c2b7 drm/vc4: Provide ddc symlink in connector sysfs directory
975079bf7bd6 drm: zte: Provide ddc symlink in hdmi connector sysfs directory
f891547e71d1 drm: zte: Provide ddc symlink in vga connector sysfs directory
db0fc0b283fb drm/tilcdc: Provide ddc symlink in connector sysfs directory
3be6cd6369b3 drm: sti: Provide ddc symlink in hdmi connector sysfs directory
e942b331112e drm/mgag200: Provide ddc symlink in connector sysfs directory
71c7598ecb86 drm/ast: Provide ddc symlink in connector sysfs directory
7cc49c5721e4 drm/bridge: dumb-vga-dac: Provide ddc symlink in connector sysfs 
directory
d4f140364daa drm/bridge: dw-hdmi: Provide ddc symlink in connector sysfs 
directory
-:63: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#63: FILE: drivers/gpu/drm/bridge/synopsys/dw-hdmi.c:1780:
+   drm_scdc_writeb(ddc, SCDC_SOURCE_VERSION,
min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));

total: 0 errors, 0 warnings, 1 checks, 138 lines checked
fc6b3922897e drm/bridge: ti-tfp410: Provide ddc symlink in connector sysfs 
directory
4fcc4559e922 drm/amdgpu: Provide ddc symlink in connector sysfs directory
-:83: WARNING:LONG_LINE: line over 100 characters
#83: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1681:
+   drm_connector_helper_add(&amdgpu_connector->base, 
&amdgpu_connector_vga_helper_funcs);

-:104: WARNING:LONG_LINE: line over 100 characters
#104: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1706:
+   drm_connector_helper_add(&amdgpu_connector->base, 
&amdgpu_connector_vga_helper_funcs);

-:125: WARNING:LONG_LINE: line over 100 characters
#125: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1736:
+   drm_connector_helper_add(&amdgpu_connector->base, 
&amdgpu_connector_dvi_helper_funcs);

-:146: WARNING:LONG_LINE: line over 100 characters
#146: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1791:
+   drm_connector_helper_add(&amdgpu_connector->base, 
&amdgpu_connector_dvi_helper_funcs);

-:171: WARNING:LONG_LINE: line over 100 characters
#171: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1840:
+   drm_connector_helper_add(&amdgpu_connector->base, 
&amdgpu_connector_dp_helper_funcs);

-:196: WARNING:LONG_LINE: line over 100 characters
#196: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1887:
+   drm_connector_helper_add(&amdgpu_connector->base, 
&amdgpu_connector_dp_helper_funcs);

-:217: WARNING:LONG_LINE: line over 100 characters
#217: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1911:
+   drm_connector_helper_add(&amdgpu_connector->base, 
&amdgpu_connector_lvds_helper_funcs);

total: 0 errors, 7 warnings, 0 checks, 197 lines checked
1b35dc189ae3 drm/radeon: Provide ddc symlink in connector sysfs directory
-:83: WARNING:LONG_LINE: line over 100 characters
#83: FILE: drivers/gpu/drm/radeon/radeon_connectors.c:2064:
+   drm_connector_helper_add(&radeon_connector->base, 
&radeon_vga_connector_helper_funcs);

-:104: WARNING:LONG_LINE: line over 100 characters
#104: FILE: drivers/gpu/drm/radeon/radeon_connectors.c:2094:
+   drm_connector_helper_add(&radeon_connector->base, 
&radeon_vga_connector_helper_funcs);

-:125: WARNING:LONG_LINE: line over 100 characters
#125: FILE: drivers/gpu/drm/radeon/radeon_connectors.c:2130:
+   drm_connector_helper_add(&radeon_connector->base, 
&radeon_dvi_connector_helper_funcs);

-:146: WARNING:LONG_LINE: line over 100 characters
#146: FILE: drivers/gpu/drm/radeon/radeon_connectors.c:2192:
+   drm_connector_helper_add(&radeon_connector->base, 
&radeon_dvi_connector_helper_funcs);

-:171: WARNING:LONG_LINE: line over 100 characters
#171: FILE: drivers/gpu/drm/radeon/radeon_connectors.c:2249:
+   drm_connector_helper_

Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/huc: Copy huc rsa only once

[Chris Wilson]

Quoting Michal Wajdeczko (2019-07-24 13:55:23)
> On Wed, 24 Jul 2019 04:21:50 +0200, Daniele Ceraolo Spurio  
>  wrote:
> 
> > The binary is perma-pinned and the rsa is not going to change, so copy
> > it only once and not on every load.
> 
> as this new location is accessible from the GuC, what if GuC (or whoever
> else) corrupts it ? with stale RSA we will fail to authenticate HuC on
> subsequent resets.

Refusing to run after misbehaviour is reasonable, and probably better
than running with a successful adversary. We can equally conjecture how
to respond to an attack against any other GGTT or even ppGTT object,
where we have no idea on the identity of the culprit. That's before we
even start on hidden hypervisors and microcontrollers.
-Chris
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[Intel-gfx] [PATCH v5 24/24] drm/i915: Provide ddc symlink in hdmi connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 9bf28de10401..9948a8a1833a 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3077,8 +3077,13 @@ void intel_hdmi_init_connector(struct intel_digital_port 
*intel_dig_port,
 intel_dig_port->max_lanes, port_name(port)))
return;
 
-   drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
-  DRM_MODE_CONNECTOR_HDMIA);
+   intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
+   connector->ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
+
+   drm_connector_init_with_ddc(dev, connector,
+   &intel_hdmi_connector_funcs,
+   DRM_MODE_CONNECTOR_HDMIA,
+   connector->ddc);
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 
connector->interlace_allowed = 1;
@@ -3088,8 +3093,6 @@ void intel_hdmi_init_connector(struct intel_digital_port 
*intel_dig_port,
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
connector->ycbcr_420_allowed = true;
 
-   intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
-
if (WARN_ON(port == PORT_A))
return;
intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
-- 
2.17.1

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[Intel-gfx] [PATCH v5 23/24] drm/radeon: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 141 +++--
 1 file changed, 105 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index c60d1a44d22a..1b743edb3fbe 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1947,17 +1947,21 @@ radeon_add_atom_connector(struct drm_device *dev,
radeon_connector->con_priv = radeon_dig_connector;
if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, 
i2c_bus);
-   if (radeon_connector->ddc_bus)
+   if (radeon_connector->ddc_bus) {
has_aux = true;
-   else
+   connector->ddc = 
&radeon_connector->ddc_bus->adapter;
+   } else {
DRM_ERROR("DP: Failed to assign ddc bus! Check 
dmesg for i2c errors.\n");
+   }
}
switch (connector_type) {
case DRM_MODE_CONNECTOR_VGA:
case DRM_MODE_CONNECTOR_DVIA:
default:
-   drm_connector_init(dev, &radeon_connector->base,
-  &radeon_dp_connector_funcs, 
connector_type);
+   drm_connector_init_with_ddc(dev, 
&radeon_connector->base,
+   &radeon_dp_connector_funcs,
+   connector_type,
+   radeon_connector->base.ddc);
drm_connector_helper_add(&radeon_connector->base,
 
&radeon_dp_connector_helper_funcs);
connector->interlace_allowed = true;
@@ -1979,8 +1983,10 @@ radeon_add_atom_connector(struct drm_device *dev,
case DRM_MODE_CONNECTOR_HDMIA:
case DRM_MODE_CONNECTOR_HDMIB:
case DRM_MODE_CONNECTOR_DisplayPort:
-   drm_connector_init(dev, &radeon_connector->base,
-  &radeon_dp_connector_funcs, 
connector_type);
+   drm_connector_init_with_ddc(dev, 
&radeon_connector->base,
+   &radeon_dp_connector_funcs,
+   connector_type,
+   radeon_connector->base.ddc);
drm_connector_helper_add(&radeon_connector->base,
 
&radeon_dp_connector_helper_funcs);
drm_object_attach_property(&radeon_connector->base.base,
@@ -2027,8 +2033,10 @@ radeon_add_atom_connector(struct drm_device *dev,
break;
case DRM_MODE_CONNECTOR_LVDS:
case DRM_MODE_CONNECTOR_eDP:
-   drm_connector_init(dev, &radeon_connector->base,
-  &radeon_lvds_bridge_connector_funcs, 
connector_type);
+   drm_connector_init_with_ddc(dev, 
&radeon_connector->base,
+   
&radeon_lvds_bridge_connector_funcs,
+   connector_type,
+   radeon_connector->base.ddc);
drm_connector_helper_add(&radeon_connector->base,
 
&radeon_dp_connector_helper_funcs);
drm_object_attach_property(&radeon_connector->base.base,
@@ -2042,13 +2050,18 @@ radeon_add_atom_connector(struct drm_device *dev,
} else {
switch (connector_type) {
case DRM_MODE_CONNECTOR_VGA:
-   drm_connector_init(dev, &radeon_connector->base, 
&radeon_vga_connector_funcs, connector_type);
-   drm_connector_helper_add(&radeon_connector->base, 
&radeon_vga_connector_helper_funcs);
if (i2c_bus->valid) {
radeon_connector->ddc_bus = 
radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus)
DRM_ERROR("VGA: Failed to assign ddc 
bus! Check dmesg for i2c errors.\n");
+   else
+   connector->ddc = 
&radeon_connector->ddc_bus->adapter;
}
+   drm_connector_init_with_ddc(dev, 
&radeon_connector->base,
+   &radeon_vga_connector_funcs,
+   

[Intel-gfx] [PATCH v5 20/24] drm/bridge: dw-hdmi: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 46 ---
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 218a7b2308f7..1ff6d2cf6f3a 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -161,7 +161,6 @@ struct dw_hdmi {
 
struct drm_display_mode previous_mode;
 
-   struct i2c_adapter *ddc;
void __iomem *regs;
bool sink_is_hdmi;
bool sink_has_audio;
@@ -1133,7 +1132,7 @@ static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
return false;
 
/* Disable if no DDC bus */
-   if (!hdmi->ddc)
+   if (!hdmi->connector.ddc)
return false;
 
/* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
@@ -1171,10 +1170,11 @@ void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi 
*hdmi)
 
/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
if (dw_hdmi_support_scdc(hdmi)) {
+   struct i2c_adapter *ddc = hdmi->connector.ddc;
if (mtmdsclock > HDMI14_MAX_TMDSCLK)
-   drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
+   drm_scdc_set_high_tmds_clock_ratio(ddc, 1);
else
-   drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
+   drm_scdc_set_high_tmds_clock_ratio(ddc, 0);
}
 }
 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
@@ -1765,6 +1765,7 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
if (dw_hdmi_support_scdc(hdmi)) {
if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
hdmi_info->scdc.scrambling.low_rates) {
+   struct i2c_adapter *ddc = hdmi->connector.ddc;
/*
 * HDMI2.0 Specifies the following procedure:
 * After the Source Device has determined that
@@ -1774,13 +1775,12 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
 * Source Devices compliant shall set the
 * Source Version = 1.
 */
-   drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
-  &bytes);
-   drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
+   drm_scdc_readb(ddc, SCDC_SINK_VERSION, &bytes);
+   drm_scdc_writeb(ddc, SCDC_SOURCE_VERSION,
min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
 
/* Enabled Scrambling in the Sink */
-   drm_scdc_set_scrambling(hdmi->ddc, 1);
+   drm_scdc_set_scrambling(hdmi->connector.ddc, 1);
 
/*
 * To activate the scrambler feature, you must ensure
@@ -1796,7 +1796,7 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
HDMI_MC_SWRSTZ);
-   drm_scdc_set_scrambling(hdmi->ddc, 0);
+   drm_scdc_set_scrambling(hdmi->connector.ddc, 0);
}
}
 
@@ -2142,10 +2142,10 @@ static int dw_hdmi_connector_get_modes(struct 
drm_connector *connector)
struct edid *edid;
int ret = 0;
 
-   if (!hdmi->ddc)
+   if (!hdmi->connector.ddc)
return 0;
 
-   edid = drm_get_edid(connector, hdmi->ddc);
+   edid = drm_get_edid(connector, hdmi->connector.ddc);
if (edid) {
dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
edid->width_cm, edid->height_cm);
@@ -2200,8 +2200,10 @@ static int dw_hdmi_bridge_attach(struct drm_bridge 
*bridge)
 
drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
 
-   drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
-  DRM_MODE_CONNECTOR_HDMIA);
+   drm_connector_init_with_ddc(bridge->dev, connector,
+   &dw_hdmi_connector_funcs,
+   DRM_MODE_CONNECTOR_HDMIA,
+   connector->ddc);
 
drm_connector_attach_encoder(connector, encoder);
 
@@ -2563,9 +2565,9 @@ __dw_hdmi_probe(struct platform_device *pdev,
 
ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
if (ddc_node) {
-   hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
+   hdmi->connector.ddc = of_get_i2c_adapter_by_node(ddc_node);
of_node_put(ddc_node);
-   if (!hdmi->ddc) {
+   if (!hdmi->connecto

[Intel-gfx] [PATCH v5 21/24] drm/bridge: ti-tfp410: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/bridge/ti-tfp410.c | 25 +
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/bridge/ti-tfp410.c 
b/drivers/gpu/drm/bridge/ti-tfp410.c
index dbf35c7bc85e..ca8e2f382851 100644
--- a/drivers/gpu/drm/bridge/ti-tfp410.c
+++ b/drivers/gpu/drm/bridge/ti-tfp410.c
@@ -26,7 +26,6 @@ struct tfp410 {
unsigned intconnector_type;
 
u32 bus_format;
-   struct i2c_adapter  *ddc;
struct gpio_desc*hpd;
int hpd_irq;
struct delayed_work hpd_work;
@@ -55,10 +54,10 @@ static int tfp410_get_modes(struct drm_connector *connector)
struct edid *edid;
int ret;
 
-   if (!dvi->ddc)
+   if (!dvi->connector.ddc)
goto fallback;
 
-   edid = drm_get_edid(connector, dvi->ddc);
+   edid = drm_get_edid(connector, dvi->connector.ddc);
if (!edid) {
DRM_INFO("EDID read failed. Fallback to standard modes\n");
goto fallback;
@@ -98,8 +97,8 @@ tfp410_connector_detect(struct drm_connector *connector, bool 
force)
return connector_status_disconnected;
}
 
-   if (dvi->ddc) {
-   if (drm_probe_ddc(dvi->ddc))
+   if (dvi->connector.ddc) {
+   if (drm_probe_ddc(dvi->connector.ddc))
return connector_status_connected;
else
return connector_status_disconnected;
@@ -134,8 +133,10 @@ static int tfp410_attach(struct drm_bridge *bridge)
 
drm_connector_helper_add(&dvi->connector,
 &tfp410_con_helper_funcs);
-   ret = drm_connector_init(bridge->dev, &dvi->connector,
-&tfp410_con_funcs, dvi->connector_type);
+   ret = drm_connector_init_with_ddc(bridge->dev, &dvi->connector,
+ &tfp410_con_funcs,
+ dvi->connector_type,
+ dvi->connector.ddc);
if (ret) {
dev_err(dvi->dev, "drm_connector_init() failed: %d\n", ret);
return ret;
@@ -297,8 +298,8 @@ static int tfp410_get_connector_properties(struct tfp410 
*dvi)
if (!ddc_phandle)
goto fail;
 
-   dvi->ddc = of_get_i2c_adapter_by_node(ddc_phandle);
-   if (dvi->ddc)
+   dvi->connector.ddc = of_get_i2c_adapter_by_node(ddc_phandle);
+   if (dvi->connector.ddc)
dev_info(dvi->dev, "Connector's ddc i2c bus found\n");
else
ret = -EPROBE_DEFER;
@@ -367,7 +368,7 @@ static int tfp410_init(struct device *dev, bool i2c)
 
return 0;
 fail:
-   i2c_put_adapter(dvi->ddc);
+   i2c_put_adapter(dvi->connector.ddc);
if (dvi->hpd)
gpiod_put(dvi->hpd);
return ret;
@@ -382,8 +383,8 @@ static int tfp410_fini(struct device *dev)
 
drm_bridge_remove(&dvi->bridge);
 
-   if (dvi->ddc)
-   i2c_put_adapter(dvi->ddc);
+   if (dvi->connector.ddc)
+   i2c_put_adapter(dvi->connector.ddc);
if (dvi->hpd)
gpiod_put(dvi->hpd);
 
-- 
2.17.1

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[Intel-gfx] [PATCH v5 22/24] drm/amdgpu: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 95 ++-
 1 file changed, 69 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 73b2ede773d3..e16e553e7f21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -1574,17 +1574,21 @@ amdgpu_connector_add(struct amdgpu_device *adev,
amdgpu_connector->con_priv = amdgpu_dig_connector;
if (i2c_bus->valid) {
amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, 
i2c_bus);
-   if (amdgpu_connector->ddc_bus)
+   if (amdgpu_connector->ddc_bus) {
has_aux = true;
-   else
+   connector->ddc = 
&amdgpu_connector->ddc_bus->adapter;
+   } else {
DRM_ERROR("DP: Failed to assign ddc bus! Check 
dmesg for i2c errors.\n");
+   }
}
switch (connector_type) {
case DRM_MODE_CONNECTOR_VGA:
case DRM_MODE_CONNECTOR_DVIA:
default:
-   drm_connector_init(dev, &amdgpu_connector->base,
-  &amdgpu_connector_dp_funcs, 
connector_type);
+   drm_connector_init_with_ddc(dev, 
&amdgpu_connector->base,
+   &amdgpu_connector_dp_funcs,
+   connector_type,
+   amdgpu_connector->base.ddc);
drm_connector_helper_add(&amdgpu_connector->base,
 
&amdgpu_connector_dp_helper_funcs);
connector->interlace_allowed = true;
@@ -1602,8 +1606,10 @@ amdgpu_connector_add(struct amdgpu_device *adev,
case DRM_MODE_CONNECTOR_HDMIA:
case DRM_MODE_CONNECTOR_HDMIB:
case DRM_MODE_CONNECTOR_DisplayPort:
-   drm_connector_init(dev, &amdgpu_connector->base,
-  &amdgpu_connector_dp_funcs, 
connector_type);
+   drm_connector_init_with_ddc(dev, 
&amdgpu_connector->base,
+   &amdgpu_connector_dp_funcs,
+   connector_type,
+   amdgpu_connector->base.ddc);
drm_connector_helper_add(&amdgpu_connector->base,
 
&amdgpu_connector_dp_helper_funcs);
drm_object_attach_property(&amdgpu_connector->base.base,
@@ -1644,8 +1650,10 @@ amdgpu_connector_add(struct amdgpu_device *adev,
break;
case DRM_MODE_CONNECTOR_LVDS:
case DRM_MODE_CONNECTOR_eDP:
-   drm_connector_init(dev, &amdgpu_connector->base,
-  &amdgpu_connector_edp_funcs, 
connector_type);
+   drm_connector_init_with_ddc(dev, 
&amdgpu_connector->base,
+   &amdgpu_connector_edp_funcs,
+   connector_type,
+   amdgpu_connector->base.ddc);
drm_connector_helper_add(&amdgpu_connector->base,
 
&amdgpu_connector_dp_helper_funcs);
drm_object_attach_property(&amdgpu_connector->base.base,
@@ -1659,13 +1667,18 @@ amdgpu_connector_add(struct amdgpu_device *adev,
} else {
switch (connector_type) {
case DRM_MODE_CONNECTOR_VGA:
-   drm_connector_init(dev, &amdgpu_connector->base, 
&amdgpu_connector_vga_funcs, connector_type);
-   drm_connector_helper_add(&amdgpu_connector->base, 
&amdgpu_connector_vga_helper_funcs);
if (i2c_bus->valid) {
amdgpu_connector->ddc_bus = 
amdgpu_i2c_lookup(adev, i2c_bus);
if (!amdgpu_connector->ddc_bus)
DRM_ERROR("VGA: Failed to assign ddc 
bus! Check dmesg for i2c errors.\n");
+   else
+   connector->ddc = 
&amdgpu_connector->ddc_bus->adapter;
}
+   drm_connector_init_with_ddc(dev, 
&amdgpu_connector->base,
+   &amdgpu_connector_vga_funcs,
+ 

[Intel-gfx] [PATCH v5 19/24] drm/bridge: dumb-vga-dac: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/bridge/dumb-vga-dac.c | 25 +
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c 
b/drivers/gpu/drm/bridge/dumb-vga-dac.c
index d32885b906ae..ec04402eca38 100644
--- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
+++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
@@ -20,7 +20,6 @@ struct dumb_vga {
struct drm_bridge   bridge;
struct drm_connectorconnector;
 
-   struct i2c_adapter  *ddc;
struct regulator*vdd;
 };
 
@@ -42,10 +41,10 @@ static int dumb_vga_get_modes(struct drm_connector 
*connector)
struct edid *edid;
int ret;
 
-   if (IS_ERR(vga->ddc))
+   if (IS_ERR(vga->connector.ddc))
goto fallback;
 
-   edid = drm_get_edid(connector, vga->ddc);
+   edid = drm_get_edid(connector, vga->connector.ddc);
if (!edid) {
DRM_INFO("EDID readout failed, falling back to standard 
modes\n");
goto fallback;
@@ -84,7 +83,7 @@ dumb_vga_connector_detect(struct drm_connector *connector, 
bool force)
 * wire the DDC pins, or the I2C bus might not be working at
 * all.
 */
-   if (!IS_ERR(vga->ddc) && drm_probe_ddc(vga->ddc))
+   if (!IS_ERR(vga->connector.ddc) && drm_probe_ddc(vga->connector.ddc))
return connector_status_connected;
 
return connector_status_unknown;
@@ -111,8 +110,10 @@ static int dumb_vga_attach(struct drm_bridge *bridge)
 
drm_connector_helper_add(&vga->connector,
 &dumb_vga_con_helper_funcs);
-   ret = drm_connector_init(bridge->dev, &vga->connector,
-&dumb_vga_con_funcs, DRM_MODE_CONNECTOR_VGA);
+   ret = drm_connector_init_with_ddc(bridge->dev, &vga->connector,
+ &dumb_vga_con_funcs,
+ DRM_MODE_CONNECTOR_VGA,
+ vga->connector.ddc);
if (ret) {
DRM_ERROR("Failed to initialize connector\n");
return ret;
@@ -190,14 +191,14 @@ static int dumb_vga_probe(struct platform_device *pdev)
dev_dbg(&pdev->dev, "No vdd regulator found: %d\n", ret);
}
 
-   vga->ddc = dumb_vga_retrieve_ddc(&pdev->dev);
-   if (IS_ERR(vga->ddc)) {
-   if (PTR_ERR(vga->ddc) == -ENODEV) {
+   vga->connector.ddc = dumb_vga_retrieve_ddc(&pdev->dev);
+   if (IS_ERR(vga->connector.ddc)) {
+   if (PTR_ERR(vga->connector.ddc) == -ENODEV) {
dev_dbg(&pdev->dev,
"No i2c bus specified. Disabling EDID 
readout\n");
} else {
dev_err(&pdev->dev, "Couldn't retrieve i2c bus\n");
-   return PTR_ERR(vga->ddc);
+   return PTR_ERR(vga->connector.ddc);
}
}
 
@@ -216,8 +217,8 @@ static int dumb_vga_remove(struct platform_device *pdev)
 
drm_bridge_remove(&vga->bridge);
 
-   if (!IS_ERR(vga->ddc))
-   i2c_put_adapter(vga->ddc);
+   if (!IS_ERR(vga->connector.ddc))
+   i2c_put_adapter(vga->connector.ddc);
 
return 0;
 }
-- 
2.17.1

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[Intel-gfx] [PATCH v5 18/24] drm/ast: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/ast/ast_mode.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index c792362024a5..1c899a6e87b7 100644
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -867,7 +867,14 @@ static int ast_connector_init(struct drm_device *dev)
return -ENOMEM;
 
connector = &ast_connector->base;
-   drm_connector_init(dev, connector, &ast_connector_funcs, 
DRM_MODE_CONNECTOR_VGA);
+   ast_connector->i2c = ast_i2c_create(dev);
+   if (!ast_connector->i2c)
+   DRM_ERROR("failed to add ddc bus for connector\n");
+
+   drm_connector_init_with_ddc(dev, connector,
+   &ast_connector_funcs,
+   DRM_MODE_CONNECTOR_VGA,
+   &ast_connector->i2c->adapter);
 
drm_connector_helper_add(connector, &ast_connector_helper_funcs);
 
@@ -881,10 +888,6 @@ static int ast_connector_init(struct drm_device *dev)
encoder = list_first_entry(&dev->mode_config.encoder_list, struct 
drm_encoder, head);
drm_connector_attach_encoder(connector, encoder);
 
-   ast_connector->i2c = ast_i2c_create(dev);
-   if (!ast_connector->i2c)
-   DRM_ERROR("failed to add ddc bus for connector\n");
-
return 0;
 }
 
-- 
2.17.1

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[Intel-gfx] [PATCH v5 17/24] drm/mgag200: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/mgag200/mgag200_mode.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c 
b/drivers/gpu/drm/mgag200/mgag200_mode.c
index 822f2a13748f..5e778b5f1a10 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -1678,18 +1678,19 @@ static struct drm_connector *mga_vga_init(struct 
drm_device *dev)
return NULL;
 
connector = &mga_connector->base;
+   mga_connector->i2c = mgag200_i2c_create(dev);
+   if (!mga_connector->i2c)
+   DRM_ERROR("failed to add ddc bus\n");
 
-   drm_connector_init(dev, connector,
-  &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
+   drm_connector_init_with_ddc(dev, connector,
+   &mga_vga_connector_funcs,
+   DRM_MODE_CONNECTOR_VGA,
+   &mga_connector->i2c->adapter);
 
drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
 
drm_connector_register(connector);
 
-   mga_connector->i2c = mgag200_i2c_create(dev);
-   if (!mga_connector->i2c)
-   DRM_ERROR("failed to add ddc bus\n");
-
return connector;
 }
 
-- 
2.17.1

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[Intel-gfx] [PATCH v5 14/24] drm: zte: Provide ddc symlink in vga connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/zte/zx_vga.c | 31 +--
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/zte/zx_vga.c b/drivers/gpu/drm/zte/zx_vga.c
index 9b67e419280c..1bc6e9bce7e0 100644
--- a/drivers/gpu/drm/zte/zx_vga.c
+++ b/drivers/gpu/drm/zte/zx_vga.c
@@ -25,15 +25,11 @@ struct zx_vga_pwrctrl {
u32 mask;
 };
 
-struct zx_vga_i2c {
-   struct i2c_adapter adap;
-   struct mutex lock;
-};
-
 struct zx_vga {
struct drm_connector connector;
struct drm_encoder encoder;
-   struct zx_vga_i2c *ddc;
+   /* protects ddc access */
+   struct mutex ddc_lock;
struct device *dev;
void __iomem *mmio;
struct clk *i2c_wclk;
@@ -88,7 +84,7 @@ static int zx_vga_connector_get_modes(struct drm_connector 
*connector)
 */
zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, 0);
 
-   edid = drm_get_edid(connector, &vga->ddc->adap);
+   edid = drm_get_edid(connector, connector->ddc);
if (!edid) {
/*
 * If EDID reading fails, we set the device state into
@@ -165,8 +161,10 @@ static int zx_vga_register(struct drm_device *drm, struct 
zx_vga *vga)
 
vga->connector.polled = DRM_CONNECTOR_POLL_HPD;
 
-   ret = drm_connector_init(drm, connector, &zx_vga_connector_funcs,
-DRM_MODE_CONNECTOR_VGA);
+   ret = drm_connector_init_with_ddc(drm, connector,
+ &zx_vga_connector_funcs,
+ DRM_MODE_CONNECTOR_VGA,
+ connector->ddc);
if (ret) {
DRM_DEV_ERROR(dev, "failed to init connector: %d\n", ret);
goto clean_encoder;
@@ -284,11 +282,10 @@ static int zx_vga_i2c_xfer(struct i2c_adapter *adap, 
struct i2c_msg *msgs,
   int num)
 {
struct zx_vga *vga = i2c_get_adapdata(adap);
-   struct zx_vga_i2c *ddc = vga->ddc;
int ret = 0;
int i;
 
-   mutex_lock(&ddc->lock);
+   mutex_lock(&vga->ddc_lock);
 
for (i = 0; i < num; i++) {
if (msgs[i].flags & I2C_M_RD)
@@ -303,7 +300,7 @@ static int zx_vga_i2c_xfer(struct i2c_adapter *adap, struct 
i2c_msg *msgs,
if (!ret)
ret = num;
 
-   mutex_unlock(&ddc->lock);
+   mutex_unlock(&vga->ddc_lock);
 
return ret;
 }
@@ -322,17 +319,15 @@ static int zx_vga_ddc_register(struct zx_vga *vga)
 {
struct device *dev = vga->dev;
struct i2c_adapter *adap;
-   struct zx_vga_i2c *ddc;
int ret;
 
-   ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
-   if (!ddc)
+   adap = devm_kzalloc(dev, sizeof(*adap), GFP_KERNEL);
+   if (!adap)
return -ENOMEM;
 
-   vga->ddc = ddc;
-   mutex_init(&ddc->lock);
+   vga->connector.ddc = adap;
+   mutex_init(&vga->ddc_lock);
 
-   adap = &ddc->adap;
adap->owner = THIS_MODULE;
adap->class = I2C_CLASS_DDC;
adap->dev.parent = dev;
-- 
2.17.1

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[Intel-gfx] [PATCH v5 16/24] drm: sti: Provide ddc symlink in hdmi connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/sti/sti_hdmi.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c
index f03d617edc4c..33d06e0a9168 100644
--- a/drivers/gpu/drm/sti/sti_hdmi.c
+++ b/drivers/gpu/drm/sti/sti_hdmi.c
@@ -1284,8 +1284,10 @@ static int sti_hdmi_bind(struct device *dev, struct 
device *master, void *data)
 
drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
 
-   drm_connector_init(drm_dev, drm_connector,
-   &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
+   drm_connector_init_with_ddc(drm_dev, drm_connector,
+   &sti_hdmi_connector_funcs,
+   DRM_MODE_CONNECTOR_HDMIA,
+   hdmi->ddc_adapt);
drm_connector_helper_add(drm_connector,
&sti_hdmi_connector_helper_funcs);
 
-- 
2.17.1

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[Intel-gfx] [PATCH v5 15/24] drm/tilcdc: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c 
b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
index c6e4e52f32bc..d51776dd7a03 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
@@ -222,8 +222,10 @@ static struct drm_connector 
*tfp410_connector_create(struct drm_device *dev,
 
connector = &tfp410_connector->base;
 
-   drm_connector_init(dev, connector, &tfp410_connector_funcs,
-   DRM_MODE_CONNECTOR_DVID);
+   drm_connector_init_with_ddc(dev, connector,
+   &tfp410_connector_funcs,
+   DRM_MODE_CONNECTOR_DVID,
+   mod->i2c);
drm_connector_helper_add(connector, &tfp410_connector_helper_funcs);
 
connector->polled = DRM_CONNECTOR_POLL_CONNECT |
-- 
2.17.1

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[Intel-gfx] [PATCH v5 12/24] drm/vc4: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 26 +++---
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index ee7d4e7b0ee3..671018c9ecc9 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -76,7 +76,6 @@ struct vc4_hdmi {
 
struct vc4_hdmi_audio audio;
 
-   struct i2c_adapter *ddc;
void __iomem *hdmicore_regs;
void __iomem *hd_regs;
int hpd_gpio;
@@ -207,7 +206,7 @@ vc4_hdmi_connector_detect(struct drm_connector *connector, 
bool force)
return connector_status_disconnected;
}
 
-   if (drm_probe_ddc(vc4->hdmi->ddc))
+   if (drm_probe_ddc(connector->ddc))
return connector_status_connected;
 
if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
@@ -233,7 +232,7 @@ static int vc4_hdmi_connector_get_modes(struct 
drm_connector *connector)
int ret = 0;
struct edid *edid;
 
-   edid = drm_get_edid(connector, vc4->hdmi->ddc);
+   edid = drm_get_edid(connector, connector->ddc);
cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
if (!edid)
return -ENODEV;
@@ -267,7 +266,8 @@ static const struct drm_connector_helper_funcs 
vc4_hdmi_connector_helper_funcs =
 };
 
 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
-struct drm_encoder 
*encoder)
+struct drm_encoder 
*encoder,
+struct i2c_adapter *ddc)
 {
struct drm_connector *connector;
struct vc4_hdmi_connector *hdmi_connector;
@@ -281,8 +281,10 @@ static struct drm_connector 
*vc4_hdmi_connector_init(struct drm_device *dev,
 
hdmi_connector->encoder = encoder;
 
-   drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
-  DRM_MODE_CONNECTOR_HDMIA);
+   drm_connector_init_with_ddc(dev, connector,
+   &vc4_hdmi_connector_funcs,
+   DRM_MODE_CONNECTOR_HDMIA,
+   ddc);
drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 
/* Create and attach TV margin props to this connector. */
@@ -1291,6 +1293,7 @@ static int vc4_hdmi_bind(struct device *dev, struct 
device *master, void *data)
struct vc4_hdmi *hdmi;
struct vc4_hdmi_encoder *vc4_hdmi_encoder;
struct device_node *ddc_node;
+   struct i2c_adapter *ddc;
u32 value;
int ret;
 
@@ -1338,9 +1341,9 @@ static int vc4_hdmi_bind(struct device *dev, struct 
device *master, void *data)
return -ENODEV;
}
 
-   hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
+   ddc = of_find_i2c_adapter_by_node(ddc_node);
of_node_put(ddc_node);
-   if (!hdmi->ddc) {
+   if (ddc) {
DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
return -EPROBE_DEFER;
}
@@ -1395,7 +1398,7 @@ static int vc4_hdmi_bind(struct device *dev, struct 
device *master, void *data)
 DRM_MODE_ENCODER_TMDS, NULL);
drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
 
-   hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
+   hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder, ddc);
if (IS_ERR(hdmi->connector)) {
ret = PTR_ERR(hdmi->connector);
goto err_destroy_encoder;
@@ -1452,7 +1455,7 @@ static int vc4_hdmi_bind(struct device *dev, struct 
device *master, void *data)
clk_disable_unprepare(hdmi->hsm_clock);
pm_runtime_disable(dev);
 err_put_i2c:
-   put_device(&hdmi->ddc->dev);
+   put_device(&ddc->dev);
 
return ret;
 }
@@ -1463,6 +1466,7 @@ static void vc4_hdmi_unbind(struct device *dev, struct 
device *master,
struct drm_device *drm = dev_get_drvdata(master);
struct vc4_dev *vc4 = drm->dev_private;
struct vc4_hdmi *hdmi = vc4->hdmi;
+   struct i2c_adapter *ddc = hdmi->connector->ddc;
 
cec_unregister_adapter(hdmi->cec_adap);
vc4_hdmi_connector_destroy(hdmi->connector);
@@ -1471,7 +1475,7 @@ static void vc4_hdmi_unbind(struct device *dev, struct 
device *master,
clk_disable_unprepare(hdmi->hsm_clock);
pm_runtime_disable(dev);
 
-   put_device(&hdmi->ddc->dev);
+   put_device(&ddc->dev);
 
vc4->hdmi = NULL;
 }
-- 
2.17.1

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[Intel-gfx] [PATCH v5 13/24] drm: zte: Provide ddc symlink in hdmi connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/zte/zx_hdmi.c | 31 +--
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/zte/zx_hdmi.c b/drivers/gpu/drm/zte/zx_hdmi.c
index a50f5a1f09b8..502d357b40a5 100644
--- a/drivers/gpu/drm/zte/zx_hdmi.c
+++ b/drivers/gpu/drm/zte/zx_hdmi.c
@@ -29,15 +29,11 @@
 #define ZX_HDMI_INFOFRAME_SIZE 31
 #define DDC_SEGMENT_ADDR   0x30
 
-struct zx_hdmi_i2c {
-   struct i2c_adapter adap;
-   struct mutex lock;
-};
-
 struct zx_hdmi {
struct drm_connector connector;
struct drm_encoder encoder;
-   struct zx_hdmi_i2c *ddc;
+   /* protects ddc access */
+   struct mutex ddc_lock;
struct device *dev;
struct drm_device *drm;
void __iomem *mmio;
@@ -264,7 +260,7 @@ static int zx_hdmi_connector_get_modes(struct drm_connector 
*connector)
struct edid *edid;
int ret;
 
-   edid = drm_get_edid(connector, &hdmi->ddc->adap);
+   edid = drm_get_edid(connector, connector->ddc);
if (!edid)
return 0;
 
@@ -319,8 +315,10 @@ static int zx_hdmi_register(struct drm_device *drm, struct 
zx_hdmi *hdmi)
 
hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
 
-   drm_connector_init(drm, &hdmi->connector, &zx_hdmi_connector_funcs,
-  DRM_MODE_CONNECTOR_HDMIA);
+   drm_connector_init_with_ddc(drm, &hdmi->connector,
+   &zx_hdmi_connector_funcs,
+   DRM_MODE_CONNECTOR_HDMIA,
+   hdmi->connector.ddc);
drm_connector_helper_add(&hdmi->connector,
 &zx_hdmi_connector_helper_funcs);
 
@@ -562,10 +560,9 @@ static int zx_hdmi_i2c_xfer(struct i2c_adapter *adap, 
struct i2c_msg *msgs,
int num)
 {
struct zx_hdmi *hdmi = i2c_get_adapdata(adap);
-   struct zx_hdmi_i2c *ddc = hdmi->ddc;
int i, ret = 0;
 
-   mutex_lock(&ddc->lock);
+   mutex_lock(&hdmi->ddc_lock);
 
/* Enable DDC master access */
hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, HW_DDC_MASTER);
@@ -590,7 +587,7 @@ static int zx_hdmi_i2c_xfer(struct i2c_adapter *adap, 
struct i2c_msg *msgs,
/* Disable DDC master access */
hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, 0);
 
-   mutex_unlock(&ddc->lock);
+   mutex_unlock(&hdmi->ddc_lock);
 
return ret;
 }
@@ -608,17 +605,15 @@ static const struct i2c_algorithm zx_hdmi_algorithm = {
 static int zx_hdmi_ddc_register(struct zx_hdmi *hdmi)
 {
struct i2c_adapter *adap;
-   struct zx_hdmi_i2c *ddc;
int ret;
 
-   ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
-   if (!ddc)
+   adap = devm_kzalloc(hdmi->dev, sizeof(*adap), GFP_KERNEL);
+   if (!adap)
return -ENOMEM;
 
-   hdmi->ddc = ddc;
-   mutex_init(&ddc->lock);
+   hdmi->connector.ddc = adap;
+   mutex_init(&hdmi->ddc_lock);
 
-   adap = &ddc->adap;
adap->owner = THIS_MODULE;
adap->class = I2C_CLASS_DDC;
adap->dev.parent = hdmi->dev;
-- 
2.17.1

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[Intel-gfx] [PATCH v5 10/24] drm/imx: imx-ldb: Provide ddc symlink in connector's sysfs

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/imx/imx-ldb.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index de62a4cd4827..94945dd937cc 100644
--- a/drivers/gpu/drm/imx/imx-ldb.c
+++ b/drivers/gpu/drm/imx/imx-ldb.c
@@ -57,7 +57,6 @@ struct imx_ldb_channel {
struct drm_bridge *bridge;
 
struct device_node *child;
-   struct i2c_adapter *ddc;
int chno;
void *edid;
int edid_len;
@@ -133,8 +132,8 @@ static int imx_ldb_connector_get_modes(struct drm_connector 
*connector)
return num_modes;
}
 
-   if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
-   imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
+   if (!imx_ldb_ch->edid && connector->ddc)
+   imx_ldb_ch->edid = drm_get_edid(connector, connector->ddc);
 
if (imx_ldb_ch->edid) {
drm_connector_update_edid_property(connector,
@@ -462,9 +461,10 @@ static int imx_ldb_register(struct drm_device *drm,
 */
drm_connector_helper_add(&imx_ldb_ch->connector,
&imx_ldb_connector_helper_funcs);
-   drm_connector_init(drm, &imx_ldb_ch->connector,
-   &imx_ldb_connector_funcs,
-   DRM_MODE_CONNECTOR_LVDS);
+   drm_connector_init_with_ddc(drm, &imx_ldb_ch->connector,
+   &imx_ldb_connector_funcs,
+   DRM_MODE_CONNECTOR_LVDS,
+   imx_ldb_ch->connector.ddc);
drm_connector_attach_encoder(&imx_ldb_ch->connector, encoder);
}
 
@@ -552,15 +552,15 @@ static int imx_ldb_panel_ddc(struct device *dev,
 
ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
if (ddc_node) {
-   channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
+   channel->connector.ddc = of_find_i2c_adapter_by_node(ddc_node);
of_node_put(ddc_node);
-   if (!channel->ddc) {
+   if (!channel->connector.ddc) {
dev_warn(dev, "failed to get ddc i2c adapter\n");
return -EPROBE_DEFER;
}
}
 
-   if (!channel->ddc) {
+   if (!channel->connector.ddc) {
/* if no DDC available, fallback to hardcoded EDID */
dev_dbg(dev, "no ddc available\n");
 
@@ -727,7 +727,7 @@ static void imx_ldb_unbind(struct device *dev, struct 
device *master,
drm_panel_detach(channel->panel);
 
kfree(channel->edid);
-   i2c_put_adapter(channel->ddc);
+   i2c_put_adapter(channel->connector.ddc);
}
 }
 
-- 
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[Intel-gfx] [PATCH v5 11/24] drm/imx: imx-tve: Provide ddc symlink in connector's sysfs

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/imx/imx-tve.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c
index 649515868f86..e25df9bba393 100644
--- a/drivers/gpu/drm/imx/imx-tve.c
+++ b/drivers/gpu/drm/imx/imx-tve.c
@@ -111,7 +111,6 @@ struct imx_tve {
 
struct regmap *regmap;
struct regulator *dac_reg;
-   struct i2c_adapter *ddc;
struct clk *clk;
struct clk *di_sel_clk;
struct clk_hw clk_hw_di;
@@ -220,14 +219,13 @@ static int tve_setup_vga(struct imx_tve *tve)
 
 static int imx_tve_connector_get_modes(struct drm_connector *connector)
 {
-   struct imx_tve *tve = con_to_tve(connector);
struct edid *edid;
int ret = 0;
 
-   if (!tve->ddc)
+   if (!connector->ddc)
return 0;
 
-   edid = drm_get_edid(connector, tve->ddc);
+   edid = drm_get_edid(connector, connector->ddc);
if (edid) {
drm_connector_update_edid_property(connector, edid);
ret = drm_add_edid_modes(connector, edid);
@@ -484,8 +482,10 @@ static int imx_tve_register(struct drm_device *drm, struct 
imx_tve *tve)
 
drm_connector_helper_add(&tve->connector,
&imx_tve_connector_helper_funcs);
-   drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
-  DRM_MODE_CONNECTOR_VGA);
+   drm_connector_init_with_ddc(drm, &tve->connector,
+   &imx_tve_connector_funcs,
+   DRM_MODE_CONNECTOR_VGA,
+   tve->connector.ddc);
 
drm_connector_attach_encoder(&tve->connector, &tve->encoder);
 
@@ -553,7 +553,7 @@ static int imx_tve_bind(struct device *dev, struct device 
*master, void *data)
 
ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
if (ddc_node) {
-   tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
+   tve->connector.ddc = of_find_i2c_adapter_by_node(ddc_node);
of_node_put(ddc_node);
}
 
-- 
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[Intel-gfx] [PATCH v5 08/24] drm/mediatek: Provide ddc symlink in hdmi connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c 
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index ce91b61364eb..cc4ab8b070a4 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -150,7 +150,6 @@ struct mtk_hdmi {
struct device *dev;
struct phy *phy;
struct device *cec_dev;
-   struct i2c_adapter *ddc_adpt;
struct clk *clk[MTK_HDMI_CLK_COUNT];
struct drm_display_mode mode;
bool dvi_mode;
@@ -1217,10 +1216,10 @@ static int mtk_hdmi_conn_get_modes(struct drm_connector 
*conn)
struct edid *edid;
int ret;
 
-   if (!hdmi->ddc_adpt)
+   if (!conn->ddc)
return -ENODEV;
 
-   edid = drm_get_edid(conn, hdmi->ddc_adpt);
+   edid = drm_get_edid(conn, conn->ddc);
if (!edid)
return -ENODEV;
 
@@ -1299,9 +1298,10 @@ static int mtk_hdmi_bridge_attach(struct drm_bridge 
*bridge)
struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
int ret;
 
-   ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn,
-&mtk_hdmi_connector_funcs,
-DRM_MODE_CONNECTOR_HDMIA);
+   ret = drm_connector_init_with_ddc(bridge->encoder->dev, &hdmi->conn,
+ &mtk_hdmi_connector_funcs,
+ DRM_MODE_CONNECTOR_HDMIA,
+ hdmi->conn.ddc);
if (ret) {
dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
return ret;
@@ -1513,9 +1513,9 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
}
of_node_put(remote);
 
-   hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
+   hdmi->conn.ddc = of_find_i2c_adapter_by_node(i2c_np);
of_node_put(i2c_np);
-   if (!hdmi->ddc_adpt) {
+   if (!hdmi->conn.ddc) {
dev_err(dev, "Failed to get ddc i2c adapter by node\n");
return -EINVAL;
}
-- 
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[Intel-gfx] [PATCH v5 06/24] drm/msm/hdmi: Provide ddc symlink in hdmi connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index 07b4cb877d82..1f03262b8a52 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -450,8 +450,10 @@ struct drm_connector *msm_hdmi_connector_init(struct hdmi 
*hdmi)
 
connector = &hdmi_connector->base;
 
-   drm_connector_init(hdmi->dev, connector, &hdmi_connector_funcs,
-   DRM_MODE_CONNECTOR_HDMIA);
+   drm_connector_init_with_ddc(hdmi->dev, connector,
+   &hdmi_connector_funcs,
+   DRM_MODE_CONNECTOR_HDMIA,
+   hdmi->i2c);
drm_connector_helper_add(connector, &msm_hdmi_connector_helper_funcs);
 
connector->polled = DRM_CONNECTOR_POLL_CONNECT |
-- 
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[Intel-gfx] [PATCH v5 09/24] drm/tegra: Provide ddc symlink in output connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/tegra/drm.h|  1 -
 drivers/gpu/drm/tegra/hdmi.c   |  7 ---
 drivers/gpu/drm/tegra/output.c | 12 ++--
 drivers/gpu/drm/tegra/sor.c| 13 +++--
 4 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 86daa19fcf24..9bf72bcd3ec1 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -120,7 +120,6 @@ struct tegra_output {
struct device *dev;
 
struct drm_panel *panel;
-   struct i2c_adapter *ddc;
const struct edid *edid;
struct cec_notifier *cec;
unsigned int hpd_irq;
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 334c4d7d238b..aac871847be4 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -1425,9 +1425,10 @@ static int tegra_hdmi_init(struct host1x_client *client)
 
hdmi->output.dev = client->dev;
 
-   drm_connector_init(drm, &hdmi->output.connector,
-  &tegra_hdmi_connector_funcs,
-  DRM_MODE_CONNECTOR_HDMIA);
+   drm_connector_init_with_ddc(drm, &hdmi->output.connector,
+   &tegra_hdmi_connector_funcs,
+   DRM_MODE_CONNECTOR_HDMIA,
+   hdmi->output.connector.ddc);
drm_connector_helper_add(&hdmi->output.connector,
 &tegra_hdmi_connector_helper_funcs);
hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
diff --git a/drivers/gpu/drm/tegra/output.c b/drivers/gpu/drm/tegra/output.c
index 274cb955e2e1..0b5037a29c63 100644
--- a/drivers/gpu/drm/tegra/output.c
+++ b/drivers/gpu/drm/tegra/output.c
@@ -30,8 +30,8 @@ int tegra_output_connector_get_modes(struct drm_connector 
*connector)
 
if (output->edid)
edid = kmemdup(output->edid, sizeof(*edid), GFP_KERNEL);
-   else if (output->ddc)
-   edid = drm_get_edid(connector, output->ddc);
+   else if (connector->ddc)
+   edid = drm_get_edid(connector, connector->ddc);
 
cec_notifier_set_phys_addr_from_edid(output->cec, edid);
drm_connector_update_edid_property(connector, edid);
@@ -111,8 +111,8 @@ int tegra_output_probe(struct tegra_output *output)
 
ddc = of_parse_phandle(output->of_node, "nvidia,ddc-i2c-bus", 0);
if (ddc) {
-   output->ddc = of_find_i2c_adapter_by_node(ddc);
-   if (!output->ddc) {
+   output->connector.ddc = of_find_i2c_adapter_by_node(ddc);
+   if (!output->connector.ddc) {
err = -EPROBE_DEFER;
of_node_put(ddc);
return err;
@@ -174,8 +174,8 @@ void tegra_output_remove(struct tegra_output *output)
if (output->hpd_gpio)
free_irq(output->hpd_irq, output);
 
-   if (output->ddc)
-   put_device(&output->ddc->dev);
+   if (output->connector.ddc)
+   put_device(&output->connector.ddc->dev);
 }
 
 int tegra_output_init(struct drm_device *drm, struct tegra_output *output)
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 4ffe3794e6d3..63b6cfbbd17e 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -2311,7 +2311,7 @@ static void tegra_sor_hdmi_disable_scrambling(struct 
tegra_sor *sor)
 
 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
 {
-   struct i2c_adapter *ddc = sor->output.ddc;
+   struct i2c_adapter *ddc = sor->output.connector.ddc;
 
drm_scdc_set_high_tmds_clock_ratio(ddc, false);
drm_scdc_set_scrambling(ddc, false);
@@ -2339,7 +2339,7 @@ static void tegra_sor_hdmi_enable_scrambling(struct 
tegra_sor *sor)
 
 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
 {
-   struct i2c_adapter *ddc = sor->output.ddc;
+   struct i2c_adapter *ddc = sor->output.connector.ddc;
 
drm_scdc_set_high_tmds_clock_ratio(ddc, true);
drm_scdc_set_scrambling(ddc, true);
@@ -2350,7 +2350,7 @@ static void tegra_sor_hdmi_scdc_enable(struct tegra_sor 
*sor)
 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
 {
struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
-   struct i2c_adapter *ddc = sor->output.ddc;
+   struct i2c_adapter *ddc = sor->output.connector.ddc;
 
if (!drm_scdc_get_scrambling_status(ddc)) {
DRM_DEBUG_KMS("SCDC not scrambled\n");
@@ -2832,9 +2832,10 @@ static int tegra_sor_init(struct host1x_client *client)
 
sor->output.dev = sor->dev;
 
-   drm_connector_init(drm, &sor->output.connector,
-  &tegra_sor_connector_funcs,
-  connector);
+   drm_connector_init_with_ddc(drm, &sor->output.connector,
+   

[Intel-gfx] [PATCH v5 07/24] drm/sun4i: hdmi: Provide ddc symlink in sun4i hdmi connector sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi.h |  1 -
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 21 +++--
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index 7ad3f06c127e..1649273b1493 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -265,7 +265,6 @@ struct sun4i_hdmi {
struct clk  *tmds_clk;
 
struct i2c_adapter  *i2c;
-   struct i2c_adapter  *ddc_i2c;
 
/* Regmap fields for I2C adapter */
struct regmap_field *field_ddc_en;
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index b2df76addc75..4cc0bb232f6a 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -214,7 +214,7 @@ static int sun4i_hdmi_get_modes(struct drm_connector 
*connector)
struct edid *edid;
int ret;
 
-   edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c);
+   edid = drm_get_edid(connector, connector->ddc ?: hdmi->i2c);
if (!edid)
return 0;
 
@@ -599,11 +599,11 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
goto err_disable_mod_clk;
}
 
-   hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev);
-   if (IS_ERR(hdmi->ddc_i2c)) {
-   ret = PTR_ERR(hdmi->ddc_i2c);
+   hdmi->connector.ddc = sun4i_hdmi_get_ddc(dev);
+   if (IS_ERR(hdmi->connector.ddc)) {
+   ret = PTR_ERR(hdmi->connector.ddc);
if (ret == -ENODEV)
-   hdmi->ddc_i2c = NULL;
+   hdmi->connector.ddc = NULL;
else
goto err_del_i2c_adapter;
}
@@ -640,9 +640,10 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
 
drm_connector_helper_add(&hdmi->connector,
 &sun4i_hdmi_connector_helper_funcs);
-   ret = drm_connector_init(drm, &hdmi->connector,
-&sun4i_hdmi_connector_funcs,
-DRM_MODE_CONNECTOR_HDMIA);
+   ret = drm_connector_init_with_ddc(drm, &hdmi->connector,
+ &sun4i_hdmi_connector_funcs,
+ DRM_MODE_CONNECTOR_HDMIA,
+ hdmi->connector.ddc);
if (ret) {
dev_err(dev,
"Couldn't initialise the HDMI connector\n");
@@ -664,7 +665,7 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
cec_delete_adapter(hdmi->cec_adap);
drm_encoder_cleanup(&hdmi->encoder);
 err_put_ddc_i2c:
-   i2c_put_adapter(hdmi->ddc_i2c);
+   i2c_put_adapter(hdmi->connector.ddc);
 err_del_i2c_adapter:
i2c_del_adapter(hdmi->i2c);
 err_disable_mod_clk:
@@ -685,7 +686,7 @@ static void sun4i_hdmi_unbind(struct device *dev, struct 
device *master,
drm_connector_cleanup(&hdmi->connector);
drm_encoder_cleanup(&hdmi->encoder);
i2c_del_adapter(hdmi->i2c);
-   i2c_put_adapter(hdmi->ddc_i2c);
+   i2c_put_adapter(hdmi->connector.ddc);
clk_disable_unprepare(hdmi->mod_clk);
clk_disable_unprepare(hdmi->bus_clk);
 }
-- 
2.17.1

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[Intel-gfx] [PATCH v5 04/24] drm: rockchip: Provide ddc symlink in rk3066_hdmi sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/rockchip/rk3066_hdmi.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c 
b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
index 85fc5f01f761..06511296ceaa 100644
--- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c
+++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
@@ -49,7 +49,6 @@ struct rk3066_hdmi {
struct drm_encoder encoder;
 
struct rk3066_hdmi_i2c *i2c;
-   struct i2c_adapter *ddc;
 
unsigned int tmdsclk;
 
@@ -470,10 +469,10 @@ static int rk3066_hdmi_connector_get_modes(struct 
drm_connector *connector)
struct edid *edid;
int ret = 0;
 
-   if (!hdmi->ddc)
+   if (!connector->ddc)
return 0;
 
-   edid = drm_get_edid(connector, hdmi->ddc);
+   edid = drm_get_edid(connector, connector->ddc);
if (edid) {
hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
drm_connector_update_edid_property(connector, edid);
@@ -564,9 +563,10 @@ rk3066_hdmi_register(struct drm_device *drm, struct 
rk3066_hdmi *hdmi)
 
drm_connector_helper_add(&hdmi->connector,
 &rk3066_hdmi_connector_helper_funcs);
-   drm_connector_init(drm, &hdmi->connector,
-  &rk3066_hdmi_connector_funcs,
-  DRM_MODE_CONNECTOR_HDMIA);
+   drm_connector_init_with_ddc(drm, &hdmi->connector,
+   &rk3066_hdmi_connector_funcs,
+   DRM_MODE_CONNECTOR_HDMIA,
+   hdmi->connector.ddc);
 
drm_connector_attach_encoder(&hdmi->connector, encoder);
 
@@ -789,10 +789,10 @@ static int rk3066_hdmi_bind(struct device *dev, struct 
device *master,
/* internal hclk = hdmi_hclk / 25 */
hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25);
 
-   hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi);
-   if (IS_ERR(hdmi->ddc)) {
-   ret = PTR_ERR(hdmi->ddc);
-   hdmi->ddc = NULL;
+   hdmi->connector.ddc = rk3066_hdmi_i2c_adapter(hdmi);
+   if (IS_ERR(hdmi->connector.ddc)) {
+   ret = PTR_ERR(hdmi->connector.ddc);
+   hdmi->connector.ddc = NULL;
goto err_disable_hclk;
}
 
@@ -824,7 +824,7 @@ static int rk3066_hdmi_bind(struct device *dev, struct 
device *master,
hdmi->connector.funcs->destroy(&hdmi->connector);
hdmi->encoder.funcs->destroy(&hdmi->encoder);
 err_disable_i2c:
-   i2c_put_adapter(hdmi->ddc);
+   i2c_put_adapter(hdmi->connector.ddc);
 err_disable_hclk:
clk_disable_unprepare(hdmi->hclk);
 
@@ -839,7 +839,7 @@ static void rk3066_hdmi_unbind(struct device *dev, struct 
device *master,
hdmi->connector.funcs->destroy(&hdmi->connector);
hdmi->encoder.funcs->destroy(&hdmi->encoder);
 
-   i2c_put_adapter(hdmi->ddc);
+   i2c_put_adapter(hdmi->connector.ddc);
clk_disable_unprepare(hdmi->hclk);
 }
 
-- 
2.17.1

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[Intel-gfx] [PATCH v5 05/24] drm: rockchip: Provide ddc symlink in inno_hdmi sysfs directory

[Andrzej Pietrasiewicz]

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/rockchip/inno_hdmi.c | 23 ---
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c 
b/drivers/gpu/drm/rockchip/inno_hdmi.c
index ed344a795b4d..0f7ed664600f 100644
--- a/drivers/gpu/drm/rockchip/inno_hdmi.c
+++ b/drivers/gpu/drm/rockchip/inno_hdmi.c
@@ -58,7 +58,6 @@ struct inno_hdmi {
struct drm_encoder  encoder;
 
struct inno_hdmi_i2c *i2c;
-   struct i2c_adapter *ddc;
 
unsigned int tmds_rate;
 
@@ -551,10 +550,10 @@ static int inno_hdmi_connector_get_modes(struct 
drm_connector *connector)
struct edid *edid;
int ret = 0;
 
-   if (!hdmi->ddc)
+   if (!hdmi->connector.ddc)
return 0;
 
-   edid = drm_get_edid(connector, hdmi->ddc);
+   edid = drm_get_edid(connector, hdmi->connector.ddc);
if (edid) {
hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid);
@@ -624,8 +623,10 @@ static int inno_hdmi_register(struct drm_device *drm, 
struct inno_hdmi *hdmi)
 
drm_connector_helper_add(&hdmi->connector,
 &inno_hdmi_connector_helper_funcs);
-   drm_connector_init(drm, &hdmi->connector, &inno_hdmi_connector_funcs,
-  DRM_MODE_CONNECTOR_HDMIA);
+   drm_connector_init_with_ddc(drm, &hdmi->connector,
+   &inno_hdmi_connector_funcs,
+   DRM_MODE_CONNECTOR_HDMIA,
+   hdmi->connector.ddc);
 
drm_connector_attach_encoder(&hdmi->connector, encoder);
 
@@ -849,10 +850,10 @@ static int inno_hdmi_bind(struct device *dev, struct 
device *master,
 
inno_hdmi_reset(hdmi);
 
-   hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
-   if (IS_ERR(hdmi->ddc)) {
-   ret = PTR_ERR(hdmi->ddc);
-   hdmi->ddc = NULL;
+   hdmi->connector.ddc = inno_hdmi_i2c_adapter(hdmi);
+   if (IS_ERR(hdmi->connector.ddc)) {
+   ret = PTR_ERR(hdmi->connector.ddc);
+   hdmi->connector.ddc = NULL;
goto err_disable_clk;
}
 
@@ -885,7 +886,7 @@ static int inno_hdmi_bind(struct device *dev, struct device 
*master,
hdmi->connector.funcs->destroy(&hdmi->connector);
hdmi->encoder.funcs->destroy(&hdmi->encoder);
 err_put_adapter:
-   i2c_put_adapter(hdmi->ddc);
+   i2c_put_adapter(hdmi->connector.ddc);
 err_disable_clk:
clk_disable_unprepare(hdmi->pclk);
return ret;
@@ -899,7 +900,7 @@ static void inno_hdmi_unbind(struct device *dev, struct 
device *master,
hdmi->connector.funcs->destroy(&hdmi->connector);
hdmi->encoder.funcs->destroy(&hdmi->encoder);
 
-   i2c_put_adapter(hdmi->ddc);
+   i2c_put_adapter(hdmi->connector.ddc);
clk_disable_unprepare(hdmi->pclk);
 }
 
-- 
2.17.1

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[Intel-gfx] [PATCH v5 03/24] drm/exynos: Provide ddc symlink in connector's sysfs

[Andrzej Pietrasiewicz]

Switch to using the ddc provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index bc1565f1822a..dda94de4afe0 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -125,7 +125,6 @@ struct hdmi_context {
void __iomem*regs;
void __iomem*regs_hdmiphy;
struct i2c_client   *hdmiphy_port;
-   struct i2c_adapter  *ddc_adpt;
struct gpio_desc*hpd_gpio;
int irq;
struct regmap   *pmureg;
@@ -871,10 +870,10 @@ static int hdmi_get_modes(struct drm_connector *connector)
struct edid *edid;
int ret;
 
-   if (!hdata->ddc_adpt)
+   if (!connector->ddc)
return -ENODEV;
 
-   edid = drm_get_edid(connector, hdata->ddc_adpt);
+   edid = drm_get_edid(connector, connector->ddc);
if (!edid)
return -ENODEV;
 
@@ -940,8 +939,10 @@ static int hdmi_create_connector(struct drm_encoder 
*encoder)
connector->interlace_allowed = true;
connector->polled = DRM_CONNECTOR_POLL_HPD;
 
-   ret = drm_connector_init(hdata->drm_dev, connector,
-   &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
+   ret = drm_connector_init_with_ddc(hdata->drm_dev, connector,
+ &hdmi_connector_funcs,
+ DRM_MODE_CONNECTOR_HDMIA,
+ connector->ddc);
if (ret) {
DRM_DEV_ERROR(hdata->dev,
  "Failed to initialize connector with drm\n");
@@ -1892,7 +1893,7 @@ static int hdmi_get_ddc_adapter(struct hdmi_context 
*hdata)
return -EPROBE_DEFER;
}
 
-   hdata->ddc_adpt = adpt;
+   hdata->connector.ddc = adpt;
 
return 0;
 }
@@ -2044,7 +2045,7 @@ static int hdmi_probe(struct platform_device *pdev)
if (hdata->regs_hdmiphy)
iounmap(hdata->regs_hdmiphy);
 err_ddc:
-   put_device(&hdata->ddc_adpt->dev);
+   put_device(&hdata->connector.ddc->dev);
 
return ret;
 }
@@ -2071,7 +2072,7 @@ static int hdmi_remove(struct platform_device *pdev)
if (hdata->regs_hdmiphy)
iounmap(hdata->regs_hdmiphy);
 
-   put_device(&hdata->ddc_adpt->dev);
+   put_device(&hdata->connector.ddc->dev);
 
mutex_destroy(&hdata->mutex);
 
-- 
2.17.1

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[Intel-gfx] [PATCH v5 02/24] drm: Add drm_connector_init() variant with ddc

[Andrzej Pietrasiewicz]

Allow passing ddc adapter pointer to the init function. Even if
drm_connector_init() sometime in the future decides to e.g. memset() all
connector fields to zeros, the newly added function ensures that at its
completion the ddc member of connector is correctly set.

Signed-off-by: Andrzej Pietrasiewicz 
---
 drivers/gpu/drm/drm_connector.c | 19 +++
 include/drm/drm_connector.h |  5 +
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 068d4b05f1be..06fbfc44fb48 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -296,6 +296,25 @@ int drm_connector_init(struct drm_device *dev,
 }
 EXPORT_SYMBOL(drm_connector_init);
 
+int drm_connector_init_with_ddc(struct drm_device *dev,
+   struct drm_connector *connector,
+   const struct drm_connector_funcs *funcs,
+   int connector_type,
+   struct i2c_adapter *ddc)
+{
+   int ret;
+
+   ret = drm_connector_init(dev, connector, funcs, connector_type);
+   if (ret)
+   return ret;
+
+   /* provide ddc symlink in sysfs */
+   connector->ddc = ddc;
+
+   return ret;
+}
+EXPORT_SYMBOL(drm_connector_init_with_ddc);
+
 /**
  * drm_connector_attach_edid_property - attach edid property.
  * @connector: the connector
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 33a6fff85fdb..937fda9c1374 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1410,6 +1410,11 @@ int drm_connector_init(struct drm_device *dev,
   struct drm_connector *connector,
   const struct drm_connector_funcs *funcs,
   int connector_type);
+int drm_connector_init_with_ddc(struct drm_device *dev,
+   struct drm_connector *connector,
+   const struct drm_connector_funcs *funcs,
+   int connector_type,
+   struct i2c_adapter *ddc);
 void drm_connector_attach_edid_property(struct drm_connector *connector);
 int drm_connector_register(struct drm_connector *connector);
 void drm_connector_unregister(struct drm_connector *connector);
-- 
2.17.1

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