Re: [Intel-gfx] [PATCH 0/5] kbuild: allow big modules to sub-divide Makefiles
Hi Masahiro On Tue, Aug 06, 2019 at 03:39:18PM +0900, Masahiro Yamada wrote: > > Recently, Jani Nikula requests a better build system support > for drivers spanning multiple directories. > (better kbuild support for drivers spanning multiple directories?) > > I implemented it, so please take a look at it. > > Note: > The single targets do not work correctly. > > The single targets have never worked correctly: It works in most cases, but now always. I dunno how much it is used. Myself I almost always do make /drivers/foo/bar/ > > [1] For instance, "make drivers/foo/bar/baz.o" will descend into > drivers/foo/bar/Makefile, which may not necessarily specify > the build rule of baz.o > > It is possible for drivers/foo/Makefile having > obj-$(CONFIG_BAZ) += bar/baz.o > > [2] subdir-ccflags-y does not work. > > The single targets directly descend into the directory of > that file resides. > > It missed subdir-ccflags-y if it is specifies in parent > Makefiles. > > Perhaps, I will have to manage correct implementation of single targets. The day that kbuild has a separate step to read all Makefiles and then without using recursive make can build the kernel we can have this fixed. Until then we can accpet it as is - as fixing this may not be simple. Sam ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness
Hi Anshuman, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [cannot apply to v5.3-rc3 next-20190809] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Anshuman-Gupta/DC3CO-Support-for-TGL/20190810-121051 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-randconfig-d002-201931 (attached as .config) compiler: gcc-7 (Debian 7.4.0-10) 7.4.0 reproduce: # save the attached .config to linux build tree make ARCH=i386 If you fix the issue, kindly add following tag Reported-by: kbuild test robot All errors (new ones prefixed by >>): ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! >> ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined! --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] dma-buf: add reservation_object_fences helper
== Series Details == Series: series starting with [1/4] dma-buf: add reservation_object_fences helper URL : https://patchwork.freedesktop.org/series/64955/ State : success == Summary == CI Bug Log - changes from CI_DRM_6667_full -> Patchwork_13941_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13941_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@reset-stress: - shard-apl: [PASS][1] -> [FAIL][2] ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl6/igt@gem_...@reset-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-apl3/igt@gem_...@reset-stress.html * igt@gem_exec_await@wide-all: - shard-iclb: [PASS][3] -> [FAIL][4] ([fdo#110946]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_exec_aw...@wide-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-iclb1/igt@gem_exec_aw...@wide-all.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_exec_sched...@preemptive-hang-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_workarounds@suspend-resume: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-kbl1/igt@gem_workarou...@suspend-resume.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-kbl4/igt@gem_workarou...@suspend-resume.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl5/igt@kms_cursor_...@pipe-c-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-apl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#104873]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-glk1/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html * igt@kms_flip@2x-modeset-vs-vblank-race: - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#103060]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-glk2/igt@kms_f...@2x-modeset-vs-vblank-race.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-glk4/igt@kms_f...@2x-modeset-vs-vblank-race.html * igt@kms_flip@flip-vs-panning-vs-hang: - shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-hsw4/igt@kms_f...@flip-vs-panning-vs-hang.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-hsw5/igt@kms_f...@flip-vs-panning-vs-hang.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-onoff.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-onoff.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [fdo#110403]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13941/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441])
Re: [Intel-gfx] [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness
Hi Anshuman, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [cannot apply to v5.3-rc3 next-20190809] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Anshuman-Gupta/DC3CO-Support-for-TGL/20190810-121051 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-defconfig (attached as .config) compiler: gcc-7 (Debian 7.4.0-10) 7.4.0 reproduce: # save the attached .config to linux build tree make ARCH=i386 If you fix the issue, kindly add following tag Reported-by: kbuild test robot All errors (new ones prefixed by >>): ld: drivers/gpu/drm/i915/display/intel_display_power.o: in function `intel_get_frame_time_us.part.34': >> intel_display_power.c:(.text+0x29fb): undefined reference to `__udivdi3' --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Remove redundant user_access_end() from __copy_from_user() error path
On Fri, 9 Aug 2019, Sedat Dilek wrote: > On Fri, Aug 9, 2019 at 1:03 AM Nick Desaulniers > wrote: > > > > On Thu, Aug 8, 2019 at 1:22 PM Thomas Gleixner wrote: > > > > tglx just picked up 2 other patches of mine, bumping just in case he's > > > > not picking up patches while on vacation. ;) > > > > > > I'm only half on vacation :) > > > > > > So I can pick it up. > > > > Thanks, will send half margaritas. > > > > Sends some Turkish Cay. One day, I'm going to collect all the things people promised to send or buy me in the past 15 years. That's going to be a really huge party :) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for put_user_pages(): miscellaneous call sites
== Series Details == Series: put_user_pages(): miscellaneous call sites URL : https://patchwork.freedesktop.org/series/64950/ State : success == Summary == CI Bug Log - changes from CI_DRM_6667_full -> Patchwork_13939_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13939_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +13 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-iclb3/igt@gem_exec_sched...@preempt-queue-bsd2.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl4/igt@gem_soft...@noreloc-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-skl4/igt@gem_soft...@noreloc-s3.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-skl5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#109507]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl4/igt@kms_f...@flip-vs-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-skl8/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-kbl4/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-kbl4/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_setmode@basic: - shard-apl: [PASS][23] -> [FAIL][24] ([fdo#99912]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl6/igt@kms_setm...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13939/shard-apl6/igt@kms_setm...@basic.html Possible fixes * igt@gem_ctx_isolation@vecs0-s3: - shard-apl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] [25]: https://intel-gfx-ci.
[Intel-gfx] ✗ Fi.CI.IGT: failure for dma-buf: make dma_fence structure a bit smaller (rev3)
== Series Details == Series: dma-buf: make dma_fence structure a bit smaller (rev3) URL : https://patchwork.freedesktop.org/series/64953/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6667_full -> Patchwork_13938_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13938_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13938_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13938_full: ### IGT changes ### Possible regressions * igt@gem_softpin@noreloc-interruptible: - shard-skl: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl5/igt@gem_soft...@noreloc-interruptible.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-skl1/igt@gem_soft...@noreloc-interruptible.html Known issues Here are the changes found in Patchwork_13938_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl2/igt@gem_ctx_isolat...@bcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-apl1/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110841]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_await@wide-all: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#110946]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_exec_aw...@wide-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-iclb1/igt@gem_exec_aw...@wide-all.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +17 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-iclb6/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl4/igt@gem_soft...@noreloc-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-skl10/igt@gem_soft...@noreloc-s3.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-kbl7/igt@kms_frontbuffer_track...@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-kbl4/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13938/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwo
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Check for a second VCS engine more carefully (rev2)
== Series Details == Series: drm/i915: Check for a second VCS engine more carefully (rev2) URL : https://patchwork.freedesktop.org/series/64938/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6667_full -> Patchwork_13935_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13935_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13935_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13935_full: ### IGT changes ### Possible regressions * igt@gem_ctx_exec@basic-invalid-context-vcs0: - shard-glk: [PASS][1] -> [FAIL][2] +9 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-glk3/igt@gem_ctx_e...@basic-invalid-context-vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-glk2/igt@gem_ctx_e...@basic-invalid-context-vcs0.html * igt@gem_eio@in-flight-contexts-10ms: - shard-skl: [PASS][3] -> [FAIL][4] +7 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl8/igt@gem_...@in-flight-contexts-10ms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-skl5/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@in-flight-contexts-1us: - shard-iclb: [PASS][5] -> [FAIL][6] +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@gem_...@in-flight-contexts-1us.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-iclb8/igt@gem_...@in-flight-contexts-1us.html - shard-apl: NOTRUN -> [FAIL][7] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-apl4/igt@gem_...@in-flight-contexts-1us.html * igt@gem_exec_parallel@contexts: - shard-apl: [PASS][8] -> [FAIL][9] +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl7/igt@gem_exec_paral...@contexts.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-apl5/igt@gem_exec_paral...@contexts.html * igt@gem_exec_parallel@vcs0-fds: - shard-hsw: [PASS][10] -> [FAIL][11] +5 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-hsw2/igt@gem_exec_paral...@vcs0-fds.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-hsw2/igt@gem_exec_paral...@vcs0-fds.html * igt@prime_vgem@busy-bsd: - shard-iclb: NOTRUN -> [SKIP][12] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-iclb5/igt@prime_v...@busy-bsd.html * igt@prime_vgem@sync-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb1/igt@prime_v...@sync-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-iclb5/igt@prime_v...@sync-bsd.html Warnings * igt@gem_ctx_shared@q-independent-bsd: - shard-iclb: [SKIP][15] ([fdo#110839]) -> [SKIP][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_ctx_sha...@q-independent-bsd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-iclb3/igt@gem_ctx_sha...@q-independent-bsd.html Known issues Here are the changes found in Patchwork_13935_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#110841]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@preempt-hang-blt: - shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([fdo#107713] / [fdo#109100]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_exec_sched...@preempt-hang-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-iclb7/igt@gem_exec_sched...@preempt-hang-blt.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109276]) +20 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13935/shard-iclb3/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@preempt-queue-chain-bsd: - shard-glk: [PASS][23] -> [SKIP][24] ([fdo#109271])
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Replace global bsd_dispatch_index with random seed (rev2)
== Series Details == Series: drm/i915: Replace global bsd_dispatch_index with random seed (rev2) URL : https://patchwork.freedesktop.org/series/64891/ State : success == Summary == CI Bug Log - changes from CI_DRM_6665_full -> Patchwork_13933_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13933_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-iclb6/igt@gem_exec_sched...@preempt-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-iclb2/igt@gem_exec_sched...@preempt-bsd.html * igt@gem_exec_suspend@basic-s3: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-skl6/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-skl9/igt@gem_exec_susp...@basic-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-kbl3/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-kbl4/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#105604] / [fdo#105763]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-kbl3/igt@kms_big...@x-tiled-32bpp-rotate-180.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-kbl2/igt@kms_big...@x-tiled-32bpp-rotate-180.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103184] / [fdo#103232] / [fdo#108472]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-skl9/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-skl2/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-untiled.html * igt@kms_flip@flip-vs-dpms-off-vs-modeset: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([fdo#103313] / [fdo#105345]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-kbl3/igt@kms_f...@flip-vs-dpms-off-vs-modeset.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-kbl2/igt@kms_f...@flip-vs-dpms-off-vs-modeset.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#109247]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-rgb565-draw-mmap-cpu.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-rgb565-draw-mmap-cpu.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([fdo#107713]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-iclb2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-max.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-iclb7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13933/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [fdo#110403]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6665/shard-skl9/igt@kms_plane_al
[Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce memory region concept (including device local memory) (rev3)
== Series Details == Series: Introduce memory region concept (including device local memory) (rev3) URL : https://patchwork.freedesktop.org/series/56683/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6670 -> Patchwork_13957 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13957 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13957, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13957: ### IGT changes ### Possible regressions * igt@gem_mmap_gtt@basic-copy: - fi-skl-gvtdvm: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-gvtdvm/igt@gem_mmap_...@basic-copy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-skl-gvtdvm/igt@gem_mmap_...@basic-copy.html - fi-kbl-8809g: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-8809g/igt@gem_mmap_...@basic-copy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-kbl-8809g/igt@gem_mmap_...@basic-copy.html - fi-kbl-7500u: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7500u/igt@gem_mmap_...@basic-copy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-kbl-7500u/igt@gem_mmap_...@basic-copy.html - fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-hsw-peppy/igt@gem_mmap_...@basic-copy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-hsw-peppy/igt@gem_mmap_...@basic-copy.html - fi-bdw-gvtdvm: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-bdw-gvtdvm/igt@gem_mmap_...@basic-copy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-bdw-gvtdvm/igt@gem_mmap_...@basic-copy.html - fi-bxt-j4205: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-bxt-j4205/igt@gem_mmap_...@basic-copy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-bxt-j4205/igt@gem_mmap_...@basic-copy.html - fi-gdg-551: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-gdg-551/igt@gem_mmap_...@basic-copy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-gdg-551/igt@gem_mmap_...@basic-copy.html - fi-kbl-guc: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-guc/igt@gem_mmap_...@basic-copy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-kbl-guc/igt@gem_mmap_...@basic-copy.html - fi-pnv-d510:[PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-pnv-d510/igt@gem_mmap_...@basic-copy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-pnv-d510/igt@gem_mmap_...@basic-copy.html - fi-skl-6600u: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-6600u/igt@gem_mmap_...@basic-copy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-skl-6600u/igt@gem_mmap_...@basic-copy.html - fi-bwr-2160:[PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-bwr-2160/igt@gem_mmap_...@basic-copy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-bwr-2160/igt@gem_mmap_...@basic-copy.html - fi-apl-guc: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-apl-guc/igt@gem_mmap_...@basic-copy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-apl-guc/igt@gem_mmap_...@basic-copy.html - fi-blb-e6850: [PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-blb-e6850/igt@gem_mmap_...@basic-copy.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-blb-e6850/igt@gem_mmap_...@basic-copy.html * igt@gem_mmap_gtt@basic-write: - fi-snb-2520m: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-snb-2520m/igt@gem_mmap_...@basic-write.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13957/fi-snb-2520m/igt@gem_mmap_...@basic-write.html * igt@i915_selftest@live_mman: - fi-skl-6260u: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Cancel non-persistent contexts on close
Quoting Chris Wilson (2019-08-06 14:47:25) > Normally, we rely on our hangcheck to prevent persistent batches from > hogging the GPU. However, if the user disables hangcheck, this mechanism > breaks down. Despite our insistence that this is unsafe, the users are > equally insistent that they want to use endless batches and will disable > the hangcheck mechanism. We are looking are perhaps replacing hangcheck > with a softer mechanism, that sends a pulse down the engine to check if > it is well. We can use the same preemptive pulse to flush an active > persistent context off the GPU upon context close, preventing resources > being lost and unkillable requests remaining on the GPU, after process > termination. To avoid changing the ABI and accidentally breaking > existing userspace, we make the persistence of a context explicit and > enable it by default. Userspace can opt out of persistent mode (forcing > requests to be cancelled when the context is closed by process > termination or explicitly) by a context parameter, or to facilitate > existing use-cases by disabling hangcheck (i915.enable_hangcheck=0). > (Note, one of the outcomes for supporting endless mode will be the > removal of hangchecking, at which point opting into persistent mode will > be mandatory, or maybe the default.) For the record, I've finally run into examples of desktop clients exiting before their rendering is shown. No longer hypothetical. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce memory region concept (including device local memory) (rev3)
== Series Details == Series: Introduce memory region concept (including device local memory) (rev3) URL : https://patchwork.freedesktop.org/series/56683/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: buddy allocator +drivers/gpu/drm/i915/selftests/i915_buddy.c:292:13: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_buddy.c:292:13: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_buddy.c:647:24: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_buddy.c:647:24: warning: expression using sizeof(void) +./include/linux/slab.h:672:13: error: not a function +./include/linux/slab.h:672:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:672:13: warning: call with no type! Commit: drm/i915: introduce intel_memory_region +drivers/gpu/drm/i915/gem/i915_gem_region.c:65:21: error: undefined identifier '__builtin_add_overflow_p' +drivers/gpu/drm/i915/gem/i915_gem_region.c:65:21: warning: call with no type! Commit: drm/i915/region: support basic eviction Okay! Commit: drm/i915/region: support continuous allocations Okay! Commit: drm/i915/region: support volatile objects Okay! Commit: drm/i915: Add memory region information to device_info Okay! Commit: drm/i915: support creating LMEM objects Okay! Commit: drm/i915: setup io-mapping for LMEM Okay! Commit: drm/i915/lmem: support kernel mapping +drivers/gpu/drm/i915/gem/i915_gem_pages.c:176:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:176:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:176:42: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:253:51:expected void * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:253:51:got void [noderef] * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:253:51: warning: incorrect type in return expression (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:334:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:334:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:334:42: warning: incorrect type in argument 1 (different address spaces) Commit: drm/i915/blt: don't assume pinned intel_context Okay! Commit: drm/i915/blt: bump size restriction - +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:47:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:47:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:29:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:29:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:35:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:35:26: warning: expression using sizeof(void) Commit: drm/i915/blt: support copying objects +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:214:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:214:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:120:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:120:26: warning: expression using sizeof(void) Commit: drm/i915/selftests: move gpu-write-dw into utils Okay! Commit: drm/i915/selftests: add write-dword test for LMEM Okay! Commit: drm/i915/selftest: extend coverage to include LMEM huge-pages Okay! Commit: drm/i915/lmem: support CPU relocations +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1104:15:expected void *vaddr +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1104:15:got void [noderef] * +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1104:15: warning: incorrect type in assignment (different address spaces) -drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o: warning: objtool: .altinstr_replacement+0x41: redundant UACCESS disable +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o: warning: objtool: .altinstr_replacement+0x43: redundant UACCESS disable Commit: drm/i915/lmem: support pread Okay! Commit: drm/i915/lmem: support pwrite Okay! Commit: drm/i915: enumerate and init each supported region Okay! Commit: drm/i915: treat shmem as a region Okay! Commit: drm/i915: treat stolen as a region Okay! Commit: drm/i915: define HAS_MAPPABLE_APERTURE Okay! Commit: drm/i915: do not map aperture if it is not available. Okay! Commit: drm/i915: set num_fence_regs to 0 if there is no aperture Okay! Commit: drm/i915/selftests: check for missing aperture Okay! Commit: drm/i915: error capture with no ggtt slot +drivers/gpu/drm/i915/i915_gpu_error.c:1017:27:expected void *s +drivers/gpu/drm/i915/i915_gpu_error.c:1017:27:got void [noderef] * +drivers/gpu/drm/i915/i915_
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce memory region concept (including device local memory) (rev3)
== Series Details ==
Series: Introduce memory region concept (including device local memory) (rev3)
URL : https://patchwork.freedesktop.org/series/56683/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
45cebf7cea76 drm/i915: buddy allocator
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#29:
new file mode 100644
-:456: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#456: FILE: drivers/gpu/drm/i915/i915_buddy.c:423:
+ if (buddy && (i915_buddy_block_is_free(block) &&
+ i915_buddy_block_is_free(buddy)))
total: 0 errors, 1 warnings, 1 checks, 1303 lines checked
fe10a81166ca drm/i915: introduce intel_memory_region
-:59: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#59:
new file mode 100644
-:167: ERROR:SPACING: spaces required around that '=' (ctx:VxW)
#167: FILE: drivers/gpu/drm/i915/gem/i915_gem_region.c:104:
+ obj->mm.region= mem;
^
-:580: WARNING:TYPO_SPELLING: 'UKNOWN' may be misspelled - perhaps 'UNKNOWN'?
#580: FILE: drivers/gpu/drm/i915/intel_memory_region.h:33:
+ INTEL_MEMORY_UKNOWN, /* Should be last */
-:589: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'r' may be better as '(r)' to
avoid precedence issues
#589: FILE: drivers/gpu/drm/i915/intel_memory_region.h:42:
+#define MEMORY_TYPE_FROM_REGION(r) (ilog2(r >> INTEL_MEMORY_TYPE_SHIFT))
-:590: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'r' may be better as '(r)' to
avoid precedence issues
#590: FILE: drivers/gpu/drm/i915/intel_memory_region.h:43:
+#define MEMORY_INSTANCE_FROM_REGION(r) (ilog2(r & 0x))
-:602: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#602: FILE: drivers/gpu/drm/i915/intel_memory_region.h:55:
+ int (*init)(struct intel_memory_region *);
-:603: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#603: FILE: drivers/gpu/drm/i915/intel_memory_region.h:56:
+ void (*release)(struct intel_memory_region *);
-:605: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#605: FILE: drivers/gpu/drm/i915/intel_memory_region.h:58:
+ struct drm_i915_gem_object *
-:605: WARNING:FUNCTION_ARGUMENTS: function definition argument
'resource_size_t' should also have an identifier name
#605: FILE: drivers/gpu/drm/i915/intel_memory_region.h:58:
+ struct drm_i915_gem_object *
-:605: WARNING:FUNCTION_ARGUMENTS: function definition argument 'unsigned int'
should also have an identifier name
#605: FILE: drivers/gpu/drm/i915/intel_memory_region.h:58:
+ struct drm_i915_gem_object *
-:620: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#620: FILE: drivers/gpu/drm/i915/intel_memory_region.h:73:
+ struct mutex mm_lock;
-:639: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#639: FILE: drivers/gpu/drm/i915/intel_memory_region.h:92:
+__intel_memory_region_get_block_buddy(struct intel_memory_region *mem,
+resource_size_t size);
-:641: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#641: FILE: drivers/gpu/drm/i915/intel_memory_region.h:94:
+void __intel_memory_region_put_pages_buddy(struct intel_memory_region *mem,
+ struct list_head *blocks);
-:739: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'igt_mock_fill', this function's name, in a string
#739: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:70:
+ pr_err("igt_mock_fill failed, space still left in
region\n");
total: 1 errors, 8 warnings, 5 checks, 785 lines checked
bdd5924075d5 drm/i915/region: support basic eviction
3ddf8bf0a6da drm/i915/region: support continuous allocations
9f4b2e059975 drm/i915/region: support volatile objects
929250f59fbd drm/i915: Add memory region information to device_info
0aec24bbc1d0 drm/i915: support creating LMEM objects
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#35:
new file mode 100644
-:117: WARNING:TYPO_SPELLING: 'UKNOWN' may be misspelled - perhaps 'UNKNOWN'?
#117: FILE: drivers/gpu/drm/i915/i915_drv.h:1374:
+ struct intel_memory_region *regions[INTEL_MEMORY_UKNOWN];
total: 0 errors, 2 warnings, 0 checks, 219 lines checked
50a84a2e349b drm/i915: setup io-mapping for LMEM
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 34 lines checked
d4a527f69e88 drm/i915/lmem: support kernel mapping
-:289: ERROR:CODE_INDENT: code indent should use tabs where possible
#289: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:422:
+^I^I^Ival);$
-:289: CHECK:PARENTHESIS_ALIGNME
Re: [Intel-gfx] [PATCH v3 24/37] drm/i915: set num_fence_regs to 0 if there is no aperture
On 8/9/19 3:26 PM, Matthew Auld wrote: From: Daniele Ceraolo Spurio We can't fence anything without aperture. When I wrote this patch (before LMEM was in the picture) mappable aperture was supposed to only be missing in headless scenarios so I didn't consider the display case. Do we still need/use fences for direct access from display HW to LMEM? if so, we should drop this. Daniele Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index bcac359ec661..bb7d9321cadf 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -808,8 +808,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) detect_bit_6_swizzle(i915); - if (INTEL_GEN(i915) >= 7 && - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) + if (!HAS_MAPPABLE_APERTURE(i915)) + num_fences = 0; + else if (INTEL_GEN(i915) >= 7 && +!(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) num_fences = 32; else if (INTEL_GEN(i915) >= 4 || IS_I945G(i915) || IS_I945GM(i915) || ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 36/37] drm/i915/query: Expose memory regions through the query uAPI
From: Abdiel Janulgue
Returns the available memory region areas supported by the HW.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_query.c | 57 +++
include/uapi/drm/i915_drm.h | 39 +
2 files changed, 96 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index ad9240a0817a..69a2a906feef 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -142,10 +142,67 @@ query_engine_info(struct drm_i915_private *i915,
return len;
}
+static int query_memregion_info(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+ struct drm_i915_query_memory_region_info __user *query_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_memory_region_info __user *info_ptr =
+ &query_ptr->regions[0];
+ struct drm_i915_memory_region_info info = { };
+ struct drm_i915_query_memory_region_info query;
+ u32 total_length;
+ int ret, i;
+
+ if (query_item->flags != 0)
+ return -EINVAL;
+
+ total_length = sizeof(struct drm_i915_query_memory_region_info);
+ for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) {
+ struct intel_memory_region *region = dev_priv->regions[i];
+
+ if (!region)
+ continue;
+
+ total_length += sizeof(struct drm_i915_memory_region_info);
+ }
+
+ ret = copy_query_item(&query, sizeof(query), total_length,
+ query_item);
+ if (ret != 0)
+ return ret;
+
+ if (query.num_regions || query.rsvd[0] || query.rsvd[1] ||
+ query.rsvd[2])
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) {
+ struct intel_memory_region *region = dev_priv->regions[i];
+
+ if (!region)
+ continue;
+
+ info.id = region->id;
+ info.size = resource_size(®ion->region);
+
+ if (__copy_to_user(info_ptr, &info, sizeof(info)))
+ return -EFAULT;
+
+ query.num_regions++;
+ info_ptr++;
+ }
+
+ if (__copy_to_user(query_ptr, &query, sizeof(query)))
+ return -EFAULT;
+
+ return total_length;
+}
+
static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item)
= {
query_topology_info,
query_engine_info,
+ query_memregion_info,
};
int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 75d79c17e91b..7ef037f58e1b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2038,6 +2038,7 @@ struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO1
#define DRM_I915_QUERY_ENGINE_INFO 2
+#define DRM_I915_QUERY_MEMREGION_INFO 3
/* Must be kept compact -- no holes and well documented */
/*
@@ -2177,6 +2178,44 @@ struct drm_i915_query_engine_info {
struct drm_i915_engine_info engines[];
};
+struct drm_i915_memory_region_info {
+
+ /** Base type of a region
+*/
+#define I915_SYSTEM_MEMORY 0
+#define I915_DEVICE_MEMORY 1
+
+ /** The region id is encoded in a layout which makes it possible to
+* retrieve the following information:
+*
+* Base type: log2(ID >> 16)
+* Instance: log2(ID & 0x)
+*/
+ __u32 id;
+
+ /** Reserved field. MBZ */
+ __u32 rsvd0;
+
+ /** Unused for now. MBZ */
+ __u64 flags;
+
+ __u64 size;
+
+ /** Reserved fields must be cleared to zero. */
+ __u64 rsvd1[4];
+};
+
+struct drm_i915_query_memory_region_info {
+
+ /** Number of struct drm_i915_memory_region_info structs */
+ __u32 num_regions;
+
+ /** MBZ */
+ __u32 rsvd[3];
+
+ struct drm_i915_memory_region_info regions[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.20.1
___
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[Intel-gfx] [PATCH v3 26/37] drm/i915: error capture with no ggtt slot
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
drivers/gpu/drm/i915/i915_gpu_error.c | 64 ++-
2 files changed, 63 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index dd28c54527e3..0819ac9837dc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2630,7 +2630,8 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
{
ggtt_release_guc_top(ggtt);
- drm_mm_remove_node(&ggtt->error_capture);
+ if (drm_mm_node_allocated(&ggtt->error_capture))
+ drm_mm_remove_node(&ggtt->error_capture);
}
static int init_ggtt(struct i915_ggtt *ggtt)
@@ -2661,13 +2662,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
if (ret)
return ret;
- /* Reserve a mappable slot for our lockless error capture */
- ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
- PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
- 0, ggtt->mappable_end,
- DRM_MM_INSERT_LOW);
- if (ret)
- return ret;
+ if (HAS_MAPPABLE_APERTURE(ggtt->vm.i915)) {
+ /* Reserve a mappable slot for our lockless error capture */
+ ret = drm_mm_insert_node_in_range(&ggtt->vm.mm,
&ggtt->error_capture,
+ PAGE_SIZE, 0,
I915_COLOR_UNEVICTABLE,
+ 0, ggtt->mappable_end,
+ DRM_MM_INSERT_LOW);
+ if (ret)
+ return ret;
+ }
/*
* The upper portion of the GuC address space has a sizeable hole
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 92986d3f6995..19eb5ccba387 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -40,6 +40,7 @@
#include "display/intel_overlay.h"
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "i915_gpu_error.h"
@@ -235,6 +236,7 @@ struct compress {
struct pagevec pool;
struct z_stream_s zstream;
void *tmp;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -292,7 +294,7 @@ static int compress_page(struct compress *c,
struct z_stream_s *zstream = &c->zstream;
zstream->next_in = src;
- if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
+ if (c->wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
zstream->next_in = c->tmp;
zstream->avail_in = PAGE_SIZE;
@@ -367,6 +369,7 @@ static void err_compression_marker(struct
drm_i915_error_state_buf *m)
struct compress {
struct pagevec pool;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -389,7 +392,7 @@ static int compress_page(struct compress *c,
if (!ptr)
return -ENOMEM;
- if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
+ if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
memcpy(ptr, src, PAGE_SIZE);
dst->pages[dst->page_count++] = ptr;
@@ -963,7 +966,6 @@ i915_error_object_create(struct drm_i915_private *i915,
struct drm_i915_error_object *dst;
unsigned long num_pages;
struct sgt_iter iter;
- dma_addr_t dma;
int ret;
might_sleep();
@@ -988,17 +990,53 @@ i915_error_object_create(struct drm_i915_private *i915,
dst->page_count = 0;
dst->unused = 0;
+ compress->wc = i915_gem_object_is_lmem(vma->obj) ||
+ drm_mm_node_allocated(&ggtt->error_capture);
+
ret = -EINVAL;
- for_each_sgt_dma(dma, iter, vma->pages) {
+ if (drm_mm_node_allocated(&ggtt->error_capture)) {
void __iomem *s;
+ dma_addr_t dma;
- ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
+ for_each_sgt_dma(dma, iter, vma->pages) {
+ ggtt->vm.insert_page(&ggtt->vm, dma, slot,
+I915_CACHE_NONE, 0);
- s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
- ret = compress_page(compress, (void __force *)s, dst);
- io_mapping_unmap(s);
- if (ret)
- break;
+ s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
+ ret = compress_page(compress, (void __force *)s, dst);
+
[Intel-gfx] [PATCH v3 33/37] drm/i915: cpu-map based dumb buffers
From: Abdiel Janulgue
If there is no aperture we can't use map_gtt to map dumb buffers, so we
need a cpu-map based path to do it. We prefer map_gtt on platforms that
do have aperture.
Signed-off-by: Abdiel Janulgue
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 18 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 2 +-
4 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 304ea578fd30..4fe83e31c1b3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -500,7 +500,8 @@ static void i915_gem_object_release_mmap_offset(struct
drm_i915_gem_object *obj)
list_for_each_entry(mmo, &obj->mmap_offsets, offset) {
if (mmo->mmap_type == I915_MMAP_TYPE_OFFSET_WC ||
mmo->mmap_type == I915_MMAP_TYPE_OFFSET_WB ||
- mmo->mmap_type == I915_MMAP_TYPE_OFFSET_UC)
+ mmo->mmap_type == I915_MMAP_TYPE_OFFSET_UC ||
+ mmo->mmap_type == I915_MMAP_TYPE_DUMB_WC)
drm_vma_node_unmap(&mmo->vma_node,
obj->base.dev->anon_inode->i_mapping);
}
@@ -602,6 +603,19 @@ __assign_gem_object_mmap_data(struct drm_file *file,
return ret;
}
+int
+i915_gem_mmap_dumb(struct drm_file *file,
+ struct drm_device *dev,
+ u32 handle,
+ u64 *offset)
+{
+ struct drm_i915_private *i915 = dev->dev_private;
+ enum i915_mmap_type mmap_type = HAS_MAPPABLE_APERTURE(i915) ?
+ I915_MMAP_TYPE_GTT : I915_MMAP_TYPE_DUMB_WC;
+
+ return __assign_gem_object_mmap_data(file, handle, mmap_type, offset);
+}
+
/**
* i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
* @dev: DRM device
@@ -714,6 +728,7 @@ static void set_vmdata_mmap_offset(struct i915_mmap_offset
*mmo, struct vm_area_
{
switch (mmo->mmap_type) {
case I915_MMAP_TYPE_OFFSET_WC:
+ case I915_MMAP_TYPE_DUMB_WC:
vma->vm_page_prot =
pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
break;
@@ -801,6 +816,7 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct
*vma)
case I915_MMAP_TYPE_OFFSET_WC:
case I915_MMAP_TYPE_OFFSET_WB:
case I915_MMAP_TYPE_OFFSET_UC:
+ case I915_MMAP_TYPE_DUMB_WC:
set_vmdata_mmap_offset(mmo, vma);
break;
case I915_MMAP_TYPE_GTT:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 4ea78d3c92a9..d280267689f9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -67,6 +67,7 @@ enum i915_mmap_type {
I915_MMAP_TYPE_OFFSET_WC,
I915_MMAP_TYPE_OFFSET_WB,
I915_MMAP_TYPE_OFFSET_UC,
+ I915_MMAP_TYPE_DUMB_WC,
};
struct i915_mmap_offset {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cf390092c927..f6a3daf696f6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2762,7 +2762,7 @@ static struct drm_driver driver = {
.get_scanout_position = i915_get_crtc_scanoutpos,
.dumb_create = i915_gem_dumb_create,
- .dumb_map_offset = i915_gem_mmap_gtt,
+ .dumb_map_offset = i915_gem_mmap_dumb,
.ioctls = i915_ioctls,
.num_ioctls = ARRAY_SIZE(i915_ioctls),
.fops = &i915_driver_fops,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a5b90670e16..f93f55947b7c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2363,7 +2363,7 @@ i915_mutex_lock_interruptible(struct drm_device *dev)
int i915_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
-int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
+int i915_gem_mmap_dumb(struct drm_file *file_priv, struct drm_device *dev,
u32 handle, u64 *offset);
int i915_gem_mmap_gtt_version(void);
--
2.20.1
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[Intel-gfx] [PATCH v3 37/37] HAX drm/i915: add the fake lmem region
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the aperture and 1:1 it map to the stolen region.
To enable simply set i915_fake_lmem_start= on the kernel cmdline with the
start of reserved region(see memmap=). The size of the region we can
use is determined by the size of the mappable aperture, so the size of
reserved region should be >= mappable_end.
eg. memmap=2G$16G i915_fake_lmem_start=0x4
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
arch/x86/kernel/early-quirks.c | 26
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 3 +
drivers/gpu/drm/i915/i915_drv.c| 8 +++
drivers/gpu/drm/i915/i915_gem_gtt.c| 3 +
drivers/gpu/drm/i915/intel_memory_region.h | 4 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 69 ++
drivers/gpu/drm/i915/intel_region_lmem.h | 5 ++
include/drm/i915_drm.h | 3 +
8 files changed, 121 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6f6b1d04dadf..9b04655e3926 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -603,6 +603,32 @@ static void __init intel_graphics_quirks(int num, int
slot, int func)
}
}
+struct resource intel_graphics_fake_lmem_res __ro_after_init =
DEFINE_RES_MEM(0, 0);
+EXPORT_SYMBOL(intel_graphics_fake_lmem_res);
+
+static int __init early_i915_fake_lmem_init(char *s)
+{
+ u64 start;
+ int ret;
+
+ if (*s == '=')
+ s++;
+
+ ret = kstrtoull(s, 16, &start);
+ if (ret)
+ return ret;
+
+ intel_graphics_fake_lmem_res.start = start;
+ intel_graphics_fake_lmem_res.end = SZ_2G; /* Placeholder; depends on
aperture size */
+
+ printk(KERN_INFO "Intel graphics fake LMEM starts at %pa\n",
+ &intel_graphics_fake_lmem_res.start);
+
+ return 0;
+}
+
+early_param("i915_fake_lmem_start", early_i915_fake_lmem_init);
+
static void __init force_disable_hpet(int num, int slot, int func)
{
#ifdef CONFIG_HPET_TIMER
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 2194e2c3bdcd..bcdc7fd099af 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -252,6 +252,7 @@ void __iomem *i915_gem_object_lmem_io_map_page(struct
drm_i915_gem_object *obj,
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= intel_graphics_fake_lmem_res.start;
return io_mapping_map_wc(&obj->mm.region->iomap, offset, PAGE_SIZE);
}
@@ -262,6 +263,7 @@ void __iomem
*i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= intel_graphics_fake_lmem_res.start;
return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
}
@@ -275,6 +277,7 @@ void __iomem *i915_gem_object_lmem_io_map(struct
drm_i915_gem_object *obj,
GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= intel_graphics_fake_lmem_res.start;
return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 845e80c2acc0..f71685a6d49b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1474,6 +1474,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
+ /* Check if we support fake LMEM -- enable for live selftests */
+ if (INTEL_GEN(dev_priv) >= 9 && i915_selftest.live &&
+ intel_graphics_fake_lmem_res.start) {
+ mkwrite_device_info(dev_priv)->memory_regions =
+ REGION_SMEM | REGION_LMEM;
+ GEM_BUG_ON(!HAS_LMEM(dev_priv));
+ }
+
ret = pci_enable_device(pdev);
if (ret)
goto out_fini;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0819ac9837dc..355268d85374 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2747,6 +2747,9 @@ int i915_gem_init_memory_regions(struct drm_i915_private
*i915)
case INTEL_STOLEN:
mem = i915_gem_stolen_setup(i915);
break;
+ case INTEL_LMEM:
+ mem = intel_setup_fake_lmem(i915);
+ break;
[Intel-gfx] [PATCH v3 34/37] drm/i915: support basic object migration
We are going want to able to move objects between different regions
like system memory and local memory. In the future everything should
be just another region.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 140 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 +
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
.../drm/i915/selftests/intel_memory_region.c | 129
4 files changed, 278 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 24f737b00e84..5982aeaaa2e3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -28,6 +28,8 @@
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_object.h"
+#include "i915_gem_object_blt.h"
+#include "i915_gem_region.h"
#include "i915_globals.h"
#include "i915_trace.h"
@@ -170,6 +172,144 @@ static void __i915_gem_free_object_rcu(struct rcu_head
*head)
atomic_dec(&i915->mm.free_count);
}
+
+int i915_gem_object_prepare_move(struct drm_i915_gem_object *obj)
+{
+ int err;
+
+ lockdep_assert_held(&obj->base.dev->struct_mutex);
+
+ if (obj->mm.madv != I915_MADV_WILLNEED)
+ return -EINVAL;
+
+ if (i915_gem_object_needs_bit17_swizzle(obj))
+ return -EINVAL;
+
+ if (atomic_read(&obj->mm.pages_pin_count) >
+ atomic_read(&obj->bind_count))
+ return -EBUSY;
+
+ if (obj->pin_global)
+ return -EBUSY;
+
+ i915_gem_object_release_mmap(obj);
+
+ GEM_BUG_ON(obj->mm.mapping);
+ GEM_BUG_ON(obj->base.filp && mapping_mapped(obj->base.filp->f_mapping));
+
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_LOCKED |
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ if (err)
+ return err;
+
+ return i915_gem_object_unbind(obj,
+ I915_GEM_OBJECT_UNBIND_ACTIVE);
+}
+
+int i915_gem_object_migrate(struct drm_i915_gem_object *obj,
+ struct intel_context *ce,
+ enum intel_region_id id)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct drm_i915_gem_object *donor;
+ struct intel_memory_region *mem;
+ struct sg_table *pages = NULL;
+ unsigned int page_sizes;
+ int err = 0;
+
+ lockdep_assert_held(&i915->drm.struct_mutex);
+
+ GEM_BUG_ON(id >= INTEL_MEMORY_UKNOWN);
+ GEM_BUG_ON(obj->mm.region->id == id);
+ GEM_BUG_ON(obj->mm.madv != I915_MADV_WILLNEED);
+
+ mem = i915->regions[id];
+
+ donor = i915_gem_object_create_region(mem, obj->base.size, 0);
+ if (IS_ERR(donor))
+ return PTR_ERR(donor);
+
+ /* Copy backing-pages if we have to */
+ if (i915_gem_object_has_pages(obj)) {
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto err_put_donor;
+
+ err = i915_gem_object_copy_blt(obj, donor, ce);
+ if (err)
+ goto err_put_donor;
+
+ i915_gem_object_lock(donor);
+ err = i915_gem_object_set_to_cpu_domain(donor, false);
+ i915_gem_object_unlock(donor);
+ if (err)
+ goto err_put_donor;
+
+ i915_retire_requests(i915);
+
+ i915_gem_object_unbind(donor, 0);
+ err = i915_gem_object_unbind(obj, 0);
+ if (err)
+ goto err_put_donor;
+
+ mutex_lock(&obj->mm.lock);
+
+ pages = __i915_gem_object_unset_pages(obj);
+ obj->ops->put_pages(obj, pages);
+
+ mutex_unlock(&obj->mm.lock);
+
+ page_sizes = donor->mm.page_sizes.phys;
+ pages = __i915_gem_object_unset_pages(donor);
+ }
+
+ if (obj->ops->release)
+ obj->ops->release(obj);
+
+ mutex_lock(&obj->mm.lock);
+
+ /* We need still need a little special casing for shmem */
+ if (obj->base.filp)
+ fput(fetch_and_zero(&obj->base.filp));
+ else if (donor->base.filp) {
+ atomic_long_inc(&donor->base.filp->f_count);
+ obj->base.filp = donor->base.filp;
+ }
+
+ obj->base.size = donor->base.size;
+ obj->mm.region = mem;
+ obj->flags = donor->flags;
+ obj->ops = donor->ops;
+ obj->cache_level = donor->cache_level;
+ obj->cache_coherent = donor->cache_coherent;
+ obj->cache_dirty = donor->cache_dirty;
+
+ list_replace_init(&donor->mm.blocks, &obj-
[Intel-gfx] [PATCH v3 28/37] drm/i915: check for missing aperture in insert_mappable_node
From: CQ Tang
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2aa4fbe7edc0..af63d1a0af14 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -64,6 +64,9 @@ static int
insert_mappable_node(struct i915_ggtt *ggtt,
struct drm_mm_node *node, u32 size)
{
+ if (!ggtt->mappable_end)
+ return -ENOSPC;
+
memset(node, 0, sizeof(*node));
return drm_mm_insert_node_in_range(&ggtt->vm.mm, node,
size, 0, I915_COLOR_UNEVICTABLE,
--
2.20.1
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[Intel-gfx] [PATCH v3 35/37] drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION
From: Abdiel Janulgue
This call will specify which memory region an object should be placed.
Note that changing the object's backing storage should be immediately
done after an object is created or if it's not yet in use, otherwise
this will fail on a busy object.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 +++
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_object.c | 115
drivers/gpu/drm/i915/i915_drv.c | 2 +-
include/uapi/drm/i915_drm.h | 23
6 files changed, 160 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index b407baaf0014..572033ac6e3b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -76,6 +76,7 @@
#include "i915_globals.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
+#include "i915_gem_ioctls.h"
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
@@ -2308,6 +2309,22 @@ int i915_gem_context_setparam_ioctl(struct drm_device
*dev, void *data,
return ret;
}
+int i915_gem_setparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_i915_gem_context_param *args = data;
+ u32 object_class = upper_32_bits(args->param);
+
+ switch (object_class) {
+ case 0:
+ return i915_gem_context_setparam_ioctl(dev, data, file);
+ case 1:
+ return i915_gem_object_setparam_ioctl(dev, data, file);
+
+ }
+ return -EINVAL;
+}
+
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 106e2ccf7a4c..1cfcf1e6bbb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -157,6 +157,8 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+int i915_gem_setparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file);
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
index 5abd5b2172f2..af7465bceebd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
@@ -32,6 +32,8 @@ int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void
*data,
struct drm_file *file);
int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
+int i915_gem_object_setparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 5982aeaaa2e3..52ea65f203a1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -506,6 +506,121 @@ int __init i915_global_objects_init(void)
return 0;
}
+static enum intel_region_id
+__region_id(u32 region)
+{
+ enum intel_region_id id;
+
+ for (id = 0; id < INTEL_MEMORY_UKNOWN; ++id) {
+ if (intel_region_map[id] == region)
+ return id;
+ }
+
+ return INTEL_MEMORY_UKNOWN;
+}
+
+static int i915_gem_object_region_select(struct drm_i915_private *dev_priv,
+struct drm_i915_gem_object_param *args,
+struct drm_file *file,
+struct drm_i915_gem_object *obj)
+{
+ struct intel_context *ce = dev_priv->engine[BCS0]->kernel_context;
+ u32 __user *uregions = u64_to_user_ptr(args->data);
+ u32 uregions_copy[INTEL_MEMORY_UKNOWN];
+ int i, ret;
+
+ if (args->size > INTEL_MEMORY_UKNOWN)
+ return -EINVAL;
+
+ memset(uregions_copy, 0, sizeof(uregions_copy));
+ for (i = 0; i < args->size; i++) {
+ u32 region;
+
+ ret = get_user(region, uregions);
+ if (ret)
+ return ret;
+
+ uregions_copy[i] = region
[Intel-gfx] [PATCH v3 27/37] drm/i915: Don't try to place HWS in non-existing mappable region
From: Michal Wajdeczko HWS placement restrictions can't just rely on HAS_LLC flag. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 634ef45b77da..46658ecd8975 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -512,7 +512,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && HAS_MAPPABLE_APERTURE(engine->i915)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena. -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 29/37] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core
From: Abdiel Janulgue
This enables us to store extra data within vma->vm_private_data and assign
the pagefault ops for each mmap instance.
We replace the core drm_gem_mmap implementation to overcome the limitation
in having only a single offset node per gem object, allowing us to have
multiple offsets per object. This enables a mapping instance to use unique
fault-hadlers, per object.
Signed-off-by: Abdiel Janulgue
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 183 --
drivers/gpu/drm/i915/gem/i915_gem_object.c| 16 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 7 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 18 ++
.../drm/i915/gem/selftests/i915_gem_mman.c| 12 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 13 +-
drivers/gpu/drm/i915/i915_drv.c | 9 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_vma.c | 21 +-
9 files changed, 244 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 1e7311493530..d4a9d59803a7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -221,7 +221,8 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
{
#define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
struct vm_area_struct *area = vmf->vma;
- struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
+ struct i915_mmap_offset *priv = area->vm_private_data;
+ struct drm_i915_gem_object *obj = priv->obj;
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *i915 = to_i915(dev);
struct intel_runtime_pm *rpm = &i915->runtime_pm;
@@ -373,13 +374,15 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj)
{
struct i915_vma *vma;
+ struct i915_mmap_offset *mmo;
GEM_BUG_ON(!obj->userfault_count);
obj->userfault_count = 0;
list_del(&obj->userfault_link);
- drm_vma_node_unmap(&obj->base.vma_node,
- obj->base.dev->anon_inode->i_mapping);
+ list_for_each_entry(mmo, &obj->mmap_offsets, offset)
+ drm_vma_node_unmap(&mmo->vma_node,
+ obj->base.dev->anon_inode->i_mapping);
for_each_ggtt_vma(vma, obj)
i915_vma_unset_userfault(vma);
@@ -433,14 +436,31 @@ void i915_gem_object_release_mmap(struct
drm_i915_gem_object *obj)
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
}
-static int create_mmap_offset(struct drm_i915_gem_object *obj)
+static void init_mmap_offset(struct drm_i915_gem_object *obj,
+struct i915_mmap_offset *mmo)
+{
+ mutex_lock(&obj->mmo_lock);
+ kref_init(&mmo->ref);
+ list_add(&mmo->offset, &obj->mmap_offsets);
+ mutex_unlock(&obj->mmo_lock);
+}
+
+static int create_mmap_offset(struct drm_i915_gem_object *obj,
+ struct i915_mmap_offset *mmo)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct drm_device *dev = obj->base.dev;
int err;
- err = drm_gem_create_mmap_offset(&obj->base);
- if (likely(!err))
+ drm_vma_node_reset(&mmo->vma_node);
+ if (mmo->file)
+ drm_vma_node_allow(&mmo->vma_node, mmo->file);
+ err = drm_vma_offset_add(dev->vma_offset_manager, &mmo->vma_node,
+obj->base.size / PAGE_SIZE);
+ if (likely(!err)) {
+ init_mmap_offset(obj, mmo);
return 0;
+ }
/* Attempt to reap some mmap space from dead objects */
do {
@@ -451,32 +471,49 @@ static int create_mmap_offset(struct drm_i915_gem_object
*obj)
break;
i915_gem_drain_freed_objects(i915);
- err = drm_gem_create_mmap_offset(&obj->base);
- if (!err)
+ err = drm_vma_offset_add(dev->vma_offset_manager,
&mmo->vma_node,
+obj->base.size / PAGE_SIZE);
+ if (!err) {
+ init_mmap_offset(obj, mmo);
break;
+ }
} while (flush_delayed_work(&i915->gem.retire_work));
return err;
}
-int
-i915_gem_mmap_gtt(struct drm_file *file,
- struct drm_device *dev,
- u32 handle,
- u64 *offset)
+static int
+__assign_gem_object_mmap_data(struct drm_file *file,
+ u32 handle,
+ enum i915_mmap_type mmap_type,
+ u64 *offset)
{
struct drm_i915_gem_object *obj;
+ struct i915_mmap_offset *mmo;
int ret;
obj = i915_gem_object_lookup(file, handle);
if (!obj)
[Intel-gfx] [PATCH v3 31/37] drm/i915/lmem: add helper to get CPU accessible offset
From: Abdiel Janulgue
LMEM can be accessed by the CPU through a BAR. The mapping itself should
be 1:1.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 16
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 3 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index f00078ac331e..8d0251af5dfc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -225,6 +225,22 @@ void __iomem *i915_gem_object_lmem_io_map(struct
drm_i915_gem_object *obj,
return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
}
+resource_size_t i915_gem_object_lmem_io_offset(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ dma_addr_t daddr;
+
+ /*
+* XXX: It's not a dma address, more a device address or physical
+* offset, so we are clearly abusing the semantics of the sg_table
+* here, and elsewhere like in the gtt paths.
+*/
+ daddr = i915_gem_object_get_dma_address(obj, n);
+
+ return mem->io_start + daddr;
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
struct intel_memory_region *region = obj->mm.region;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index 31a6462bdbb6..43e6e715eeed 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -21,6 +21,9 @@ void __iomem *
i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
unsigned long n);
+resource_size_t i915_gem_object_lmem_io_offset(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 24/37] drm/i915: set num_fence_regs to 0 if there is no aperture
From: Daniele Ceraolo Spurio We can't fence anything without aperture. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index bcac359ec661..bb7d9321cadf 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -808,8 +808,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) detect_bit_6_swizzle(i915); - if (INTEL_GEN(i915) >= 7 && - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) + if (!HAS_MAPPABLE_APERTURE(i915)) + num_fences = 0; + else if (INTEL_GEN(i915) >= 7 && +!(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) num_fences = 32; else if (INTEL_GEN(i915) >= 4 || IS_I945G(i915) || IS_I945GM(i915) || -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 32/37] drm/i915: Add cpu and lmem fault handlers
From: Abdiel Janulgue
Fault handler to handle missing pages to be filled depending on an
object's backing storage. Handle also changes needed to refault pages
depending on fault handler usage.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 54 +++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 3 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 155 +++--
drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c| 2 +-
5 files changed, 201 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 8d0251af5dfc..2194e2c3bdcd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -6,6 +6,7 @@
#include "intel_memory_region.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_lmem.h"
+#include "gt/intel_gt.h"
#include "i915_drv.h"
static int lmem_pread(struct drm_i915_gem_object *obj,
@@ -179,6 +180,59 @@ static int lmem_pwrite(struct drm_i915_gem_object *obj,
return ret;
}
+vm_fault_t i915_gem_fault_lmem(struct vm_fault *vmf)
+{
+ struct vm_area_struct *area = vmf->vma;
+ struct i915_mmap_offset *priv = area->vm_private_data;
+ struct drm_i915_gem_object *obj = priv->obj;
+ struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ unsigned long size = area->vm_end - area->vm_start;
+ bool write = area->vm_flags & VM_WRITE;
+ vm_fault_t vmf_ret;
+ int i, ret;
+
+ /* Sanity check that we allow writing into this object */
+ if (i915_gem_object_is_readonly(obj) && write)
+ return VM_FAULT_SIGBUS;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ goto err;
+
+ for (i = 0; i < size >> PAGE_SHIFT; i++) {
+ vmf_ret = vmf_insert_pfn(area,
+(unsigned long)area->vm_start + i *
PAGE_SIZE,
+i915_gem_object_lmem_io_offset(obj, i)
>> PAGE_SHIFT);
+ if (vmf_ret & VM_FAULT_ERROR) {
+ ret = vm_fault_to_errno(vmf_ret, 0);
+ goto err;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+err:
+ switch (ret) {
+ case -EIO:
+ if (!intel_gt_is_wedged(&i915->gt))
+ return VM_FAULT_SIGBUS;
+ /* fallthrough */
+ case -EAGAIN:
+ case 0:
+ case -ERESTARTSYS:
+ case -EINTR:
+ case -EBUSY:
+ return VM_FAULT_NOPAGE;
+ case -ENOMEM:
+ return VM_FAULT_OOM;
+ case -ENOSPC:
+ case -EFAULT:
+ return VM_FAULT_SIGBUS;
+ default:
+ WARN_ONCE(ret, "unhandled error in %s: %i\n", __func__, ret);
+ return VM_FAULT_SIGBUS;
+ }
+}
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.flags = I915_GEM_OBJECT_IS_MAPPABLE,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index 43e6e715eeed..c3255eb6daa5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -7,6 +7,7 @@
#define __I915_GEM_LMEM_H
#include
+#include
struct drm_i915_private;
struct drm_i915_gem_object;
@@ -24,6 +25,8 @@ i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object *obj,
resource_size_t i915_gem_object_lmem_io_offset(struct drm_i915_gem_object *obj,
unsigned long n);
+vm_fault_t i915_gem_fault_lmem(struct vm_fault *vmf);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index a62657a1f011..304ea578fd30 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include "gt/intel_gt.h"
@@ -12,6 +13,7 @@
#include "i915_drv.h"
#include "i915_gem_gtt.h"
#include "i915_gem_ioctls.h"
+#include "i915_gem_lmem.h"
#include "i915_gem_object.h"
#include "i915_trace.h"
#include "i915_vma.h"
@@ -371,7 +373,62 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
}
}
-void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj)
+static vm_fault_t i915_gem_fault_cpu(struct vm_fault *vmf)
+{
+ struct vm_area_struct *area = vmf->vma;
+ struct i915_mmap_offset *priv = area->vm_private_data;
+ struct drm_i915_gem_object *obj = priv->obj;
+ struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ vm_fault_t vmf_ret;
+ unsigned long size = area->vm_end - area->vm_start;
+
[Intel-gfx] [PATCH v3 30/37] drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET
From: Abdiel Janulgue
Add a new CPU mmap implementation that allows multiple fault handlers
that depends on the object's backing pages.
Note that we multiplex mmap_gtt and mmap_offset through the same ioctl,
and use the zero extending behaviour of drm to differentiate between
them, when we inspect the flags.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_ioctls.h| 2 ++
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 30 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_getparam.c | 1 +
include/uapi/drm/i915_drm.h | 31 +++
6 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
index ddc7f2a52b3e..5abd5b2172f2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
@@ -30,6 +30,8 @@ int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
+int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index d4a9d59803a7..a62657a1f011 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -538,12 +538,42 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void
*data,
struct drm_file *file)
{
struct drm_i915_gem_mmap_offset *args = data;
+ struct drm_i915_private *i915 = to_i915(dev);
+
+ if (args->flags & I915_MMAP_OFFSET_FLAGS)
+ return i915_gem_mmap_offset_ioctl(dev, data, file);
+
+ if (!HAS_MAPPABLE_APERTURE(i915)) {
+ DRM_ERROR("No aperture, cannot mmap via legacy GTT\n");
+ return -ENODEV;
+ }
return __assign_gem_object_mmap_data(file, args->handle,
I915_MMAP_TYPE_GTT,
&args->offset);
}
+int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_i915_gem_mmap_offset *args = data;
+ enum i915_mmap_type type;
+
+ if ((args->flags & (I915_MMAP_OFFSET_WC | I915_MMAP_OFFSET_WB)) &&
+ !boot_cpu_has(X86_FEATURE_PAT))
+ return -ENODEV;
+
+ if (args->flags & I915_MMAP_OFFSET_WC)
+ type = I915_MMAP_TYPE_OFFSET_WC;
+ else if (args->flags & I915_MMAP_OFFSET_WB)
+ type = I915_MMAP_TYPE_OFFSET_WB;
+ else if (args->flags & I915_MMAP_OFFSET_UC)
+ type = I915_MMAP_TYPE_OFFSET_UC;
+
+ return __assign_gem_object_mmap_data(file, args->handle, type,
+&args->offset);
+}
+
void i915_mmap_offset_object_release(struct kref *ref)
{
struct i915_mmap_offset *mmo = container_of(ref,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index a3745f7d57a1..4ea78d3c92a9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -64,6 +64,9 @@ struct drm_i915_gem_object_ops {
enum i915_mmap_type {
I915_MMAP_TYPE_GTT = 0,
+ I915_MMAP_TYPE_OFFSET_WC,
+ I915_MMAP_TYPE_OFFSET_WB,
+ I915_MMAP_TYPE_OFFSET_UC,
};
struct i915_mmap_offset {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fcee06ed3469..cf390092c927 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2710,7 +2710,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
- DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_gtt_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl,
DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915
[Intel-gfx] [PATCH v3 13/37] drm/i915/selftests: move gpu-write-dw into utils
Using the gpu to write to some dword over a number of pages is rather
useful, and we already have two copies of such a thing, and we don't
want a third so move it to utils. There is probably some other stuff
also...
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 120 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 134 ++---
.../drm/i915/gem/selftests/igt_gem_utils.c| 135 ++
.../drm/i915/gem/selftests/igt_gem_utils.h| 16 +++
4 files changed, 169 insertions(+), 236 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 6ead53455c51..c36cef61ce3c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -952,126 +952,22 @@ static int igt_mock_ppgtt_64K(void *arg)
return err;
}
-static struct i915_vma *
-gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
-{
- struct drm_i915_private *i915 = vma->vm->i915;
- const int gen = INTEL_GEN(i915);
- unsigned int count = vma->size >> PAGE_SHIFT;
- struct drm_i915_gem_object *obj;
- struct i915_vma *batch;
- unsigned int size;
- u32 *cmd;
- int n;
- int err;
-
- size = (1 + 4 * count) * sizeof(u32);
- size = round_up(size, PAGE_SIZE);
- obj = i915_gem_object_create_internal(i915, size);
- if (IS_ERR(obj))
- return ERR_CAST(obj);
-
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
- if (IS_ERR(cmd)) {
- err = PTR_ERR(cmd);
- goto err;
- }
-
- offset += vma->node.start;
-
- for (n = 0; n < count; n++) {
- if (gen >= 8) {
- *cmd++ = MI_STORE_DWORD_IMM_GEN4;
- *cmd++ = lower_32_bits(offset);
- *cmd++ = upper_32_bits(offset);
- *cmd++ = val;
- } else if (gen >= 4) {
- *cmd++ = MI_STORE_DWORD_IMM_GEN4 |
- (gen < 6 ? MI_USE_GGTT : 0);
- *cmd++ = 0;
- *cmd++ = offset;
- *cmd++ = val;
- } else {
- *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
- *cmd++ = offset;
- *cmd++ = val;
- }
-
- offset += PAGE_SIZE;
- }
-
- *cmd = MI_BATCH_BUFFER_END;
- intel_gt_chipset_flush(vma->vm->gt);
-
- i915_gem_object_unpin_map(obj);
-
- batch = i915_vma_instance(obj, vma->vm, NULL);
- if (IS_ERR(batch)) {
- err = PTR_ERR(batch);
- goto err;
- }
-
- err = i915_vma_pin(batch, 0, 0, PIN_USER);
- if (err)
- goto err;
-
- return batch;
-
-err:
- i915_gem_object_put(obj);
-
- return ERR_PTR(err);
-}
-
static int gpu_write(struct i915_vma *vma,
struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
-u32 dword,
-u32 value)
+u32 dw,
+u32 val)
{
- struct i915_request *rq;
- struct i915_vma *batch;
int err;
- GEM_BUG_ON(!intel_engine_can_store_dword(engine));
-
- batch = gpu_write_dw(vma, dword * sizeof(u32), value);
- if (IS_ERR(batch))
- return PTR_ERR(batch);
-
- rq = igt_request_alloc(ctx, engine);
- if (IS_ERR(rq)) {
- err = PTR_ERR(rq);
- goto err_batch;
- }
-
- i915_vma_lock(batch);
- err = i915_vma_move_to_active(batch, rq, 0);
- i915_vma_unlock(batch);
- if (err)
- goto err_request;
-
- i915_vma_lock(vma);
- err = i915_gem_object_set_to_gtt_domain(vma->obj, false);
- if (err == 0)
- err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
+ i915_gem_object_lock(vma->obj);
+ err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ i915_gem_object_unlock(vma->obj);
if (err)
- goto err_request;
-
- err = engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
- 0);
-err_request:
- if (err)
- i915_request_skip(rq, err);
- i915_request_add(rq);
-err_batch:
- i915_vma_unpin(batch);
- i915_vma_close(batch);
- i915_vma_put(batch);
+ return err;
- return err;
+ return igt_gpu_fill_dw(vma, ctx, engine, dw * sizeof(u32),
+ vma->size >> PAGE_SHIFT, val);
}
static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/
[Intel-gfx] [PATCH v3 15/37] drm/i915/selftest: extend coverage to include LMEM huge-pages
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index c36cef61ce3c..4bac15363020 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -9,6 +9,7 @@
#include "i915_selftest.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
@@ -970,7 +971,7 @@ static int gpu_write(struct i915_vma *vma,
vma->size >> PAGE_SHIFT, val);
}
-static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+static int __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
{
unsigned int needs_flush;
unsigned long n;
@@ -1002,6 +1003,51 @@ static int cpu_check(struct drm_i915_gem_object *obj,
u32 dword, u32 val)
return err;
}
+static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ if (i915_gem_object_has_struct_page(obj))
+ return __cpu_check_shmem(obj, dword, val);
+ else if (i915_gem_object_is_lmem(obj))
+ return __cpu_check_lmem(obj, dword, val);
+
+ return -ENODEV;
+}
+
static int __igt_write_huge(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
struct drm_i915_gem_object *obj,
@@ -1382,6 +1428,78 @@ static int igt_ppgtt_gemfs_huge(void *arg)
return err;
}
+static int igt_ppgtt_lmem_huge(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ static const unsigned int sizes[] = {
+ SZ_64K,
+ SZ_512K,
+ SZ_1M,
+ SZ_2M,
+ };
+ int i;
+ int err;
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /*
+* Sanity check that the HW uses huge pages correctly through LMEM
+* -- ensure that our writes land in the right place.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+ unsigned int size = sizes[i];
+
+ obj = i915_gem_object_create_lmem(i915, size,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ pr_info("object too big for region!\n");
+ return 0;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM unable to allocate huge-page(s) with
size=%u\n",
+ size);
+ goto out_unpin;
+ }
+
+ err = igt_write_huge(ctx, obj);
+ if (err) {
+ pr_err("LMEM write-huge failed with size=%u\n", size);
+ goto out_unpin;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+ }
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1732,6 +1850,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i91
[Intel-gfx] [PATCH v3 20/37] drm/i915: treat shmem as a region
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 14 +++-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 68 ++-
drivers/gpu/drm/i915/i915_drv.c | 5 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 13 +---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_pci.c | 29 +---
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
9 files changed, 99 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 768356908160..f0e5e0df00ef 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -16,6 +16,7 @@
#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_object.h"
+#include "i915_gem_region.h"
#include "i915_scatterlist.h"
static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
@@ -191,8 +192,11 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj, int align)
/* Perma-pin (until release) the physical set of pages */
__i915_gem_object_pin_pages(obj);
- if (!IS_ERR_OR_NULL(pages))
+ if (!IS_ERR_OR_NULL(pages)) {
i915_gem_shmem_ops.put_pages(obj, pages);
+ /* XXX: where is the fput now though? */
+ i915_gem_object_release_memory_region(obj);
+ }
mutex_unlock(&obj->mm.lock);
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 0d09da9f7168..592012bb9b14 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -6,6 +6,7 @@
#include "intel_memory_region.h"
#include "i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_trace.h"
void
i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
@@ -143,11 +144,22 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
GEM_BUG_ON(!size);
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
+ /*
+* There is a prevalence of the assumption that we fit the object's
+* page count inside a 32bit _signed_ variable. Let's document this and
+* catch if we ever need to fix it. In the meantime, if you do spot
+* such a local variable, please consider fixing!
+*/
+
if (size >> PAGE_SHIFT > INT_MAX)
return ERR_PTR(-E2BIG);
if (overflows_type(size, obj->base.size))
return ERR_PTR(-E2BIG);
- return mem->ops->create_object(mem, size, flags);
+ obj = mem->ops->create_object(mem, size, flags);
+ if (!IS_ERR(obj))
+ trace_i915_gem_object_create(obj);
+
+ return obj;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 9f5d903f7793..ac7a552349b4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -7,7 +7,9 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_gemfs.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
@@ -26,6 +28,7 @@ static void check_release_pagevec(struct pagevec *pvec)
static int shmem_get_pages(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_memory_region *mem = obj->mm.region;
const unsigned long page_count = obj->base.size / PAGE_SIZE;
unsigned long i;
struct address_space *mapping;
@@ -52,7 +55,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
* If there's no chance of allocating enough pages for the whole
* object, bail early.
*/
- if (page_count > totalram_pages())
+ if (obj->base.size > resource_size(&mem->region))
return -ENOMEM;
st = kmalloc(sizeof(*st), GFP_KERNEL);
@@ -417,6 +420,8 @@ shmem_pwrite(struct drm_i915_gem_object *obj,
static void shmem_release(struct drm_i915_gem_object *obj)
{
+ i915_gem_object_release_memory_region(obj);
+
fput(obj->base.filp);
}
@@ -435,7 +440,7 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.release = shmem_release,
};
-static int create_shmem(struct drm_i915_private *i915,
+static int __create_shmem(struct drm_i915_private *i915,
struct drm_gem_object *obj,
size_t size)
{
@@ -456,31 +461,23 @@ static int create_shmem(struct drm_i915_private *i915,
return 0;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_shmem(struct drm_i915_private *i915, u64 size)
+static struct drm_i915_gem_object *
+create_shmem(struct intel_memor
[Intel-gfx] [PATCH v3 25/37] drm/i915/selftests: check for missing aperture
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 3 +++
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 ++
drivers/gpu/drm/i915/selftests/i915_gem.c | 3 +++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
5 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index a1a4b53cdc4a..42db49ff9b8e 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -244,7 +244,10 @@ static bool always_valid(struct drm_i915_private *i915)
static bool needs_fence_registers(struct drm_i915_private *i915)
{
- return !intel_gt_is_wedged(&i915->gt);
+ if (intel_gt_is_wedged(&i915->gt))
+ return false;
+
+ return i915->ggtt.num_fences;
}
static bool needs_mi_store_dword(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 50aa7e95124d..fa83745abcc0 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -184,6 +184,9 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
/* We want to check the page mapping and fencing of a large object
* mmapped through the GTT. The object we create is larger than can
* possibly be mmaped as a whole, and so we must use partial GGTT vma.
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 4484b4447db1..233810da5387 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1179,8 +1179,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
struct i915_request *rq;
struct evict_vma arg;
struct hang h;
+ unsigned int pin_flags;
int err;
+ if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE)
+ return 0;
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1217,10 +1221,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
goto out_obj;
}
- err = i915_vma_pin(arg.vma, 0, 0,
- i915_vma_is_ggtt(arg.vma) ?
- PIN_GLOBAL | PIN_MAPPABLE :
- PIN_USER);
+ pin_flags = i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER;
+
+ if (flags & EXEC_OBJECT_NEEDS_FENCE)
+ pin_flags |= PIN_MAPPABLE;
+
+ err = i915_vma_pin(arg.vma, 0, 0, pin_flags);
if (err) {
i915_request_add(rq);
goto out_obj;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index bb6dd54a6ff3..0e62d5e07fcc 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -42,6 +42,9 @@ static void trash_stolen(struct drm_i915_private *i915)
unsigned long page;
u32 prng = 0x12345678;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return;
+
for (page = 0; page < size; page += PAGE_SIZE) {
const dma_addr_t dma = i915->dsm.start + page;
u32 __iomem *s;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 81850e3a7d2d..2b72276d4e97 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1147,6 +1147,9 @@ static int igt_ggtt_page(void *arg)
unsigned int *order, n;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
mutex_lock(&i915->drm.struct_mutex);
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 11/37] drm/i915/blt: bump size restriction
Reported-by: Chris Wilson
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 31 +++-
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 139 ++
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 9 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 16 +-
.../i915/gem/selftests/i915_gem_object_blt.c | 22 ++-
5 files changed, 170 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 08a84c940d8d..4b096309a97e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -5,6 +5,8 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
@@ -156,7 +158,9 @@ static void clear_pages_worker(struct work_struct *work)
struct drm_i915_private *i915 = w->ce->engine->i915;
struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
struct i915_vma *vma = w->sleeve->vma;
+ struct intel_engine_pool_node *pool;
struct i915_request *rq;
+ struct i915_vma *batch;
int err = w->dma.error;
if (unlikely(err))
@@ -176,10 +180,17 @@ static void clear_pages_worker(struct work_struct *work)
if (unlikely(err))
goto out_unlock;
+ intel_engine_pm_get(w->ce->engine);
+ batch = intel_emit_vma_fill_blt(&pool, w->ce, vma, w->value);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_unpin;
+ }
+
rq = intel_context_create_request(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- goto out_unpin;
+ goto out_batch;
}
/* There's no way the fence has signalled */
@@ -187,6 +198,16 @@ static void clear_pages_worker(struct work_struct *work)
clear_pages_dma_fence_cb))
GEM_BUG_ON(1);
+ i915_vma_lock(batch);
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (unlikely(err))
+ goto out_request;
+
+ err = intel_engine_pool_mark_active(pool, rq);
+ if (unlikely(err))
+ goto out_request;
+
if (w->ce->engine->emit_init_breadcrumb) {
err = w->ce->engine->emit_init_breadcrumb(rq);
if (unlikely(err))
@@ -202,7 +223,9 @@ static void clear_pages_worker(struct work_struct *work)
if (err)
goto out_request;
- err = intel_emit_vma_fill_blt(rq, vma, w->value);
+ err = w->ce->engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
out_request:
if (unlikely(err)) {
i915_request_skip(rq, err);
@@ -210,7 +233,11 @@ static void clear_pages_worker(struct work_struct *work)
}
i915_request_add(rq);
+out_batch:
+ i915_vma_unpin(batch);
+ intel_engine_pool_put(pool);
out_unpin:
+ intel_engine_pm_put(w->ce->engine);
i915_vma_unpin(vma);
out_unlock:
mutex_unlock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index fa90c38c8b07..c1e5edd1e359 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -5,49 +5,103 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
+#include "gt/intel_gt.h"
#include "i915_gem_clflush.h"
#include "i915_gem_object_blt.h"
-int intel_emit_vma_fill_blt(struct i915_request *rq,
- struct i915_vma *vma,
- u32 value)
+struct i915_vma *intel_emit_vma_fill_blt(struct intel_engine_pool_node **p,
+struct intel_context *ce,
+struct i915_vma *vma,
+u32 value)
{
- u32 *cs;
-
- cs = intel_ring_begin(rq, 8);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- if (INTEL_GEN(rq->i915) >= 8) {
- *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
- *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
- *cs++ = 0;
- *cs++ = vma->size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
- *cs++ = value;
- *cs++ = MI_NOOP;
- } else {
- *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
- *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
- *cs++ = 0;
- *cs++ = vma->
[Intel-gfx] [PATCH v3 12/37] drm/i915/blt: support copying objects
We can already clear an object with the blt, so try to do the same to
support copying from one object backing store to another. Really this is
just object -> object, which is not that useful yet, what we really want
is two backing stores, but that will require some vma rework first,
otherwise we are stuck with "tmp" objects.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue vm->i915;
+ const u32 block_size = S16_MAX * PAGE_SIZE;
+ struct intel_engine_pool_node *pool;
+ struct i915_vma *batch;
+ u64 src_offset, dst_offset;
+ u64 count;
+ u64 rem;
+ u32 size;
+ u32 *cmd;
+ int err;
+
+ GEM_BUG_ON(src->size != dst->size);
+
+ count = div_u64(dst->size, block_size);
+ size = (1 + 11 * count) * sizeof(u32);
+ size = round_up(size, PAGE_SIZE);
+ pool = intel_engine_pool_get(&ce->engine->pool, size);
+ if (IS_ERR(pool))
+ return ERR_CAST(pool);
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto out_put;
+ }
+
+ rem = src->size;
+ src_offset = src->node.start;
+ dst_offset = dst->node.start;
+
+ do {
+ u32 size = min_t(u64, rem, block_size);
+
+ GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
+
+ if (INTEL_GEN(i915) >= 9) {
+ *cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
+ *cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = lower_32_bits(dst_offset);
+ *cmd++ = upper_32_bits(dst_offset);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src_offset);
+ *cmd++ = upper_32_bits(src_offset);
+ } else if (INTEL_GEN(i915) >= 8) {
+ *cmd++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 -
2);
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = lower_32_bits(dst_offset);
+ *cmd++ = upper_32_bits(dst_offset);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src_offset);
+ *cmd++ = upper_32_bits(src_offset);
+ } else {
+ *cmd++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE;
+ *cmd++ = dst_offset;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = src_offset;
+ }
+
+ /* Allow ourselves to be preempted in between blocks. */
+ *cmd++ = MI_ARB_CHECK;
+
+ src_offset += size;
+ dst_offset += size;
+ rem -= size;
+ } while (rem);
+
+ *cmd = MI_BATCH_BUFFER_END;
+ intel_gt_chipset_flush(ce->vm->gt);
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_put;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (unlikely(err))
+ goto out_put;
+
+ *p = pool;
+ return batch;
+
+out_put:
+ intel_engine_pool_put(pool);
+ return ERR_PTR(err);
+}
+
+int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
+struct drm_i915_gem_object *dst,
+struct intel_context *ce)
+{
+ struct drm_gem_object *objs[] = { &src->base, &dst->base };
+ struct i915_address_space *vm = ce->vm;
+ struct intel_engine_pool_node *pool;
+ struct ww_acquire_ctx acquire;
+ struct i915_vma *vma_src, *vma_dst;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ int err;
+
+ vma_src = i915_vma_instance(src, vm, NULL);
+ if (IS_ERR(vma_src))
+ return PTR_ERR(vma_src);
+
+ err = i915_vma_pin(vma_src, 0, 0, PIN_USER);
+ if (unlikely(err))
+ return err;
+
+ vma_dst = i915_vma_instance(dst, vm, NULL);
+ if (IS_ERR(vma_dst))
+ goto out_unpin_src;
+
+ err = i915_vma_pin(vma_dst, 0, 0, PIN_USER);
+ if (unlikely(err))
+ goto out_unpin_src;
+
+ intel_engine_pm_get(ce->engine);
+ batch = intel_emit_vma_copy_blt(&pool, ce, vma_src, vma_dst);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_unpin_ds
[Intel-gfx] [PATCH v3 14/37] drm/i915/selftests: add write-dword test for LMEM
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 179 ++
1 file changed, 179 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 2570fa93e286..4123e81a2bda 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -7,6 +7,7 @@
#include "../i915_selftest.h"
+
#include "mock_drm.h"
#include "mock_gem_device.h"
#include "mock_region.h"
@@ -14,9 +15,11 @@
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_object_blt.h"
+#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
#include "selftests/igt_flush_test.h"
+#include "selftests/i915_random.h"
static void close_objects(struct list_head *objects)
{
@@ -354,6 +357,128 @@ static int igt_mock_volatile(void *arg)
return err;
}
+static int igt_gpu_write_dw(struct i915_vma *vma,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ u32 dword,
+ u32 value)
+{
+ int err;
+
+ i915_gem_object_lock(vma->obj);
+ err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ i915_gem_object_unlock(vma->obj);
+ if (err)
+ return err;
+
+ return igt_gpu_fill_dw(vma, ctx, engine, dword * sizeof(u32),
+ vma->size >> PAGE_SHIFT, value);
+}
+
+static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int igt_gpu_write(struct i915_gem_context *ctx,
+struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
+ static struct intel_engine_cs *engines[I915_NUM_ENGINES];
+ struct intel_engine_cs *engine;
+ IGT_TIMEOUT(end_time);
+ I915_RND_STATE(prng);
+ struct i915_vma *vma;
+ unsigned int id;
+ int *order;
+ int i, n;
+ int err;
+
+ n = 0;
+ for_each_engine(engine, i915, id) {
+ if (!intel_engine_can_store_dword(engine)) {
+ pr_info("store-dword-imm not supported on engine=%u\n",
+ id);
+ continue;
+ }
+ engines[n++] = engine;
+ }
+
+ if (!n)
+ return 0;
+
+ order = i915_random_order(n * I915_NUM_ENGINES, &prng);
+ if (!order)
+ return -ENOMEM;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_free;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_free;
+
+ i = 0;
+ do {
+ u32 rng = prandom_u32_state(&prng);
+ u32 dword = offset_in_page(rng) / 4;
+
+ engine = engines[order[i] % n];
+ i = (i + 1) % (n * I915_NUM_ENGINES);
+
+ err = igt_gpu_write_dw(vma, ctx, engine, dword, rng);
+ if (err)
+ break;
+
+ err = igt_cpu_check(obj, dword, rng);
+ if (err)
+ break;
+ } while (!__igt_timeout(end_time, NULL));
+
+ i915_vma_unpin(vma);
+out_free:
+ kfree(order);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_lmem_create(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -375,6 +500,59 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_write_gpu(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem
[Intel-gfx] [PATCH v3 17/37] drm/i915/lmem: support pread
We need to add support for pread'ing an LMEM object.
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 88 +++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 6 ++
3 files changed, 96 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 8d957135afa4..f5a13994dc2a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -8,12 +8,100 @@
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
+static int lmem_pread(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *arg)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_runtime_pm *rpm = &i915->runtime_pm;
+ intel_wakeref_t wakeref;
+ struct dma_fence *fence;
+ char __user *user_data;
+ unsigned int offset;
+ unsigned long idx;
+ u64 remain;
+ int ret;
+
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ return ret;
+
+ i915_gem_object_lock(obj);
+ ret = i915_gem_object_set_to_wc_domain(obj, false);
+ if (ret) {
+ i915_gem_object_unlock(obj);
+ goto out_unpin;
+ }
+
+ fence = i915_gem_object_lock_fence(obj);
+ i915_gem_object_unlock(obj);
+ if (!fence) {
+ ret = -ENOMEM;
+ goto out_unpin;
+ }
+
+ wakeref = intel_runtime_pm_get(rpm);
+
+ remain = arg->size;
+ user_data = u64_to_user_ptr(arg->data_ptr);
+ offset = offset_in_page(arg->offset);
+ for (idx = arg->offset >> PAGE_SHIFT; remain; idx++) {
+ unsigned long unwritten;
+ void __iomem *vaddr;
+ int length;
+
+ length = remain;
+ if (offset + length > PAGE_SIZE)
+ length = PAGE_SIZE - offset;
+
+ vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, idx);
+ if (!vaddr) {
+ ret = -ENOMEM;
+ goto out_put;
+ }
+ unwritten = __copy_to_user_inatomic(user_data,
+ (void __force *)vaddr +
offset,
+ length);
+ io_mapping_unmap_atomic(vaddr);
+ if (unwritten) {
+ vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
+ unwritten = copy_to_user(user_data,
+(void __force *)vaddr + offset,
+length);
+ io_mapping_unmap(vaddr);
+ }
+ if (unwritten) {
+ ret = -EFAULT;
+ goto out_put;
+ }
+
+ remain -= length;
+ user_data += length;
+ offset = 0;
+ }
+
+out_put:
+ intel_runtime_pm_put(rpm, wakeref);
+ i915_gem_object_unlock_fence(obj, fence);
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+
+ return ret;
+}
+
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.flags = I915_GEM_OBJECT_IS_MAPPABLE,
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
+
+ .pread = lmem_pread,
};
/* XXX: Time to vfunc your life up? */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 19c3f9804b68..cd06051eb797 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -53,6 +53,8 @@ struct drm_i915_gem_object_ops {
void (*truncate)(struct drm_i915_gem_object *obj);
void (*writeback)(struct drm_i915_gem_object *obj);
+ int (*pread)(struct drm_i915_gem_object *,
+const struct drm_i915_gem_pread *arg);
int (*pwrite)(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pwrite *arg);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8735dea74809..96e143d133d1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -465,6 +465,12 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
trace_i915_gem_object_pread(obj, args->offset, args->size);
+ ret = -ENODEV;
+ if (obj->ops->pread)
+ ret = obj->ops->pread(ob
[Intel-gfx] [PATCH v3 22/37] drm/i915: define HAS_MAPPABLE_APERTURE
From: Daniele Ceraolo Spurio The following patches in the series will use it to avoid certain operations when aperture is not available in HW. Signed-off-by: Daniele Ceraolo Spurio Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0f94f1f3ccaa..182ed6b46aa5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2168,6 +2168,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ (INTEL_INFO(dev_priv)->display.overlay_needs_physical) +#define HAS_MAPPABLE_APERTURE(dev_priv) (dev_priv->ggtt.mappable_end > 0) + /* Early gen2 have a totally busted CS tlb and require pinned batches. */ #define HAS_BROKEN_CS_TLB(dev_priv)(IS_I830(dev_priv) || IS_I845G(dev_priv)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 23/37] drm/i915: do not map aperture if it is not available.
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 ++---
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5bcf71b18e5f..dd28c54527e3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2795,8 +2795,10 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
mutex_unlock(&i915->drm.struct_mutex);
- arch_phys_wc_del(ggtt->mtrr);
- io_mapping_fini(&ggtt->iomap);
+ if (HAS_MAPPABLE_APERTURE(i915)) {
+ arch_phys_wc_del(ggtt->mtrr);
+ io_mapping_fini(&ggtt->iomap);
+ }
}
/**
@@ -2992,10 +2994,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
int err;
/* TODO: We're not aware of mappable constraints on gen8 yet */
- ggtt->gmadr =
- (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
-pci_resource_len(pdev, 2));
- ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ /* FIXME: We probably need to add do device_info or runtime_info */
+ if (!HAS_LMEM(dev_priv)) {
+ ggtt->gmadr =
+ (struct resource)
DEFINE_RES_MEM(pci_resource_start(pdev, 2),
+pci_resource_len(pdev,
2));
+ ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ }
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
if (!err)
@@ -3220,15 +3225,18 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
- if (!io_mapping_init_wc(&ggtt->iomap,
- ggtt->gmadr.start,
- ggtt->mappable_end)) {
- ggtt->vm.cleanup(&ggtt->vm);
- ret = -EIO;
- goto out;
- }
+ if (HAS_MAPPABLE_APERTURE(i915)) {
+ if (!io_mapping_init_wc(&ggtt->iomap,
+ ggtt->gmadr.start,
+ ggtt->mappable_end)) {
+ ggtt->vm.cleanup(&ggtt->vm);
+ ret = -EIO;
+ goto out;
+ }
- ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
+ ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
+ ggtt->mappable_end);
+ }
i915_ggtt_init_fences(ggtt);
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 19/37] drm/i915: enumerate and init each supported region
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +--
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 ++
3 files changed, 72 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f7be8cee4709..3d7da69f0d1b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2436,6 +2436,9 @@ int __must_check i915_gem_evict_for_node(struct
i915_address_space *vm,
unsigned int flags);
int i915_gem_evict_vm(struct i915_address_space *vm);
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915);
+int i915_gem_init_memory_regions(struct drm_i915_private *i915);
+
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 83a02e773c58..a1dd3e7e1ad9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2713,6 +2713,66 @@ int i915_init_ggtt(struct drm_i915_private *i915)
return 0;
}
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915)
+{
+ int i;
+
+ i915_gem_cleanup_stolen(i915);
+
+ for (i = 0; i < ARRAY_SIZE(i915->regions); ++i) {
+ struct intel_memory_region *region = i915->regions[i];
+
+ if (region)
+ intel_memory_region_destroy(region);
+ }
+}
+
+int i915_gem_init_memory_regions(struct drm_i915_private *i915)
+{
+ int err, i;
+
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ /* XXX: stolen will become a region at some point */
+ err = i915_gem_init_stolen(i915);
+ if (err)
+ return err;
+
+ for (i = 0; i < INTEL_MEMORY_UKNOWN; i++) {
+ struct intel_memory_region *mem = NULL;
+ u32 type;
+
+ if (!HAS_REGION(i915, BIT(i)))
+ continue;
+
+ type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
+ switch (type) {
+ default:
+ break;
+ }
+
+ if (IS_ERR(mem)) {
+ err = PTR_ERR(mem);
+ DRM_ERROR("Failed to setup region(%d) type=%d\n", err,
type);
+ goto out_cleanup;
+ }
+
+ mem->id = intel_region_map[i];
+ mem->type = type;
+ mem->instance =
MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
+
+ i915->regions[i] = mem;
+ }
+
+ return 0;
+
+out_cleanup:
+ i915_gem_cleanup_memory_regions(i915);
+ return err;
+}
+
static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
{
struct drm_i915_private *i915 = ggtt->vm.i915;
@@ -2754,6 +2814,8 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
{
struct pagevec *pvec;
+ i915_gem_cleanup_memory_regions(i915);
+
fini_aliasing_ppgtt(&i915->ggtt);
ggtt_cleanup_hw(&i915->ggtt);
@@ -2763,8 +2825,6 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
set_pages_array_wb(pvec->pages, pvec->nr);
__pagevec_release(pvec);
}
-
- i915_gem_cleanup_stolen(i915);
}
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3204,11 +3264,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- /*
-* Initialise stolen early so that we may reserve preallocated
-* objects for the BIOS to KMS transition.
-*/
- ret = i915_gem_init_stolen(dev_priv);
+ ret = i915_gem_init_memory_regions(dev_priv);
if (ret)
goto out_gtt_cleanup;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index cc0fe0a79330..c6944e17a2c5 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -82,6 +82,8 @@ static void mock_device_release(struct drm_device *dev)
i915_gemfs_fini(i915);
+ i915_gem_cleanup_memory_regions(i915);
+
drm_mode_config_cleanup(&i915->drm);
drm_dev_fini(&i915->drm);
@@ -219,6 +221,10 @@ struct drm_i915_private *mock_gem_device(void)
WARN_ON(i915_gemfs_init(i915));
+ err = i915_gem_init_memory_regions(i915);
+ if (err)
+ goto err_context;
+
return i915;
err_context:
--
2.20.1
___
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Intel-gfx@lists.fr
[Intel-gfx] [PATCH v3 21/37] drm/i915: treat stolen as a region
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 71 +++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 14 +
drivers/gpu/drm/i915/i915_pci.c| 2 +-
5 files changed, 68 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 592012bb9b14..b6f18c3b9eed 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -158,7 +158,7 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
return ERR_PTR(-E2BIG);
obj = mem->ops->create_object(mem, size, flags);
- if (!IS_ERR(obj))
+ if (!IS_ERR_OR_NULL(obj))
trace_i915_gem_object_create(obj);
return obj;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 696dea5ec7c6..c93a3fac90f6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -10,6 +10,7 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
@@ -150,7 +151,7 @@ static int i915_adjust_stolen(struct drm_i915_private
*dev_priv,
return 0;
}
-void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
+static void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
{
if (!drm_mm_initialized(&dev_priv->mm.stolen))
return;
@@ -355,7 +356,7 @@ static void icl_get_stolen_reserved(struct drm_i915_private
*i915,
}
}
-int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
+static int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
{
resource_size_t reserved_base, stolen_top;
resource_size_t reserved_total, reserved_size;
@@ -532,6 +533,9 @@ i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj)
i915_gem_stolen_remove_node(dev_priv, stolen);
kfree(stolen);
+
+ if (obj->mm.region)
+ i915_gem_object_release_memory_region(obj);
}
static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
@@ -541,8 +545,9 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_stolen_ops = {
};
static struct drm_i915_gem_object *
-_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- struct drm_mm_node *stolen)
+__i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ struct drm_mm_node *stolen,
+ struct intel_memory_region *mem)
{
struct drm_i915_gem_object *obj;
unsigned int cache_level;
@@ -559,6 +564,9 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE;
i915_gem_object_set_cache_coherency(obj, cache_level);
+ if (mem)
+ i915_gem_object_init_memory_region(obj, mem, 0);
+
if (i915_gem_object_pin_pages(obj))
goto cleanup;
@@ -569,10 +577,12 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- resource_size_t size)
+static struct drm_i915_gem_object *
+_i915_gem_object_create_stolen(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags)
{
+ struct drm_i915_private *dev_priv = mem->i915;
struct drm_i915_gem_object *obj;
struct drm_mm_node *stolen;
int ret;
@@ -593,7 +603,7 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
- obj = _i915_gem_object_create_stolen(dev_priv, stolen);
+ obj = __i915_gem_object_create_stolen(dev_priv, stolen, mem);
if (obj)
return obj;
@@ -602,6 +612,49 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
+struct drm_i915_gem_object *
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ resource_size_t size)
+{
+ struct drm_i915_gem_object *obj;
+
+ obj =
i915_gem_object_create_region(dev_priv->regions[INTEL_MEMORY_STOLEN],
+ size, I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj))
+ return NULL;
+
+ return obj;
+}
+
+static int init_stolen(struct intel_memory_region *mem)
+{
+ /*
+* Initialise stolen early so that we may reserve
[Intel-gfx] [PATCH v3 18/37] drm/i915/lmem: support pwrite
We need to add support for pwrite'ing an LMEM object.
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 87
1 file changed, 87 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index f5a13994dc2a..f00078ac331e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -94,6 +94,92 @@ static int lmem_pread(struct drm_i915_gem_object *obj,
return ret;
}
+static int lmem_pwrite(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *arg)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_runtime_pm *rpm = &i915->runtime_pm;
+ intel_wakeref_t wakeref;
+ struct dma_fence *fence;
+ char __user *user_data;
+ unsigned int offset;
+ unsigned long idx;
+ u64 remain;
+ int ret;
+
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ return ret;
+
+ i915_gem_object_lock(obj);
+ ret = i915_gem_object_set_to_wc_domain(obj, true);
+ if (ret) {
+ i915_gem_object_unlock(obj);
+ goto out_unpin;
+ }
+
+ fence = i915_gem_object_lock_fence(obj);
+ i915_gem_object_unlock(obj);
+ if (!fence) {
+ ret = -ENOMEM;
+ goto out_unpin;
+ }
+
+ wakeref = intel_runtime_pm_get(rpm);
+
+ remain = arg->size;
+ user_data = u64_to_user_ptr(arg->data_ptr);
+ offset = offset_in_page(arg->offset);
+ for (idx = arg->offset >> PAGE_SHIFT; remain; idx++) {
+ unsigned long unwritten;
+ void __iomem *vaddr;
+ int length;
+
+ length = remain;
+ if (offset + length > PAGE_SIZE)
+ length = PAGE_SIZE - offset;
+
+ vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, idx);
+ if (!vaddr) {
+ ret = -ENOMEM;
+ goto out_put;
+ }
+
+ unwritten = __copy_from_user_inatomic_nocache((void
__force*)vaddr + offset,
+ user_data,
length);
+ io_mapping_unmap_atomic(vaddr);
+ if (unwritten) {
+ vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
+ unwritten = copy_from_user((void __force*)vaddr +
offset,
+ user_data, length);
+ io_mapping_unmap(vaddr);
+ }
+ if (unwritten) {
+ ret = -EFAULT;
+ goto out_put;
+ }
+
+ remain -= length;
+ user_data += length;
+ offset = 0;
+ }
+
+out_put:
+ intel_runtime_pm_put(rpm, wakeref);
+ i915_gem_object_unlock_fence(obj, fence);
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+
+ return ret;
+}
+
+
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.flags = I915_GEM_OBJECT_IS_MAPPABLE,
@@ -102,6 +188,7 @@ const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops
= {
.release = i915_gem_object_release_memory_region,
.pread = lmem_pread,
+ .pwrite = lmem_pwrite,
};
/* XXX: Time to vfunc your life up? */
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 16/37] drm/i915/lmem: support CPU relocations
Add LMEM support for the CPU reloc path. When doing relocations we have
both a GPU and CPU reloc path, as well as some debugging options to force a
particular path. The GPU reloc path is preferred when the object
is not currently idle, otherwise we use the CPU reloc path. Since we
can't kmap the object, and the mappable aperture might not be available,
add support for mapping it through LMEMBAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Cc: Rodrigo Vivi
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 55 +--
1 file changed, 51 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 2fa08357944e..d70b3e6dc12d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -15,6 +15,7 @@
#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_ioctls.h"
+#include "gem/i915_gem_lmem.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pool.h"
#include "gt/intel_gt.h"
@@ -251,6 +252,7 @@ struct i915_execbuffer {
bool has_llc : 1;
bool has_fence : 1;
bool needs_unfenced : 1;
+ bool is_lmem : 1;
struct i915_request *rq;
u32 *rq_cmd;
@@ -959,6 +961,7 @@ static void reloc_cache_init(struct reloc_cache *cache,
cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
cache->has_fence = cache->gen < 4;
cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
+ cache->is_lmem = false;
cache->node.allocated = false;
cache->rq = NULL;
cache->rq_size = 0;
@@ -1017,10 +1020,14 @@ static void reloc_cache_reset(struct reloc_cache *cache)
} else {
struct i915_ggtt *ggtt = cache_to_ggtt(cache);
- intel_gt_flush_ggtt_writes(ggtt->vm.gt);
+ if (!cache->is_lmem)
+ intel_gt_flush_ggtt_writes(ggtt->vm.gt);
io_mapping_unmap_atomic((void __iomem *)vaddr);
- if (cache->node.allocated) {
+ if (cache->is_lmem) {
+ i915_gem_object_unpin_pages((struct drm_i915_gem_object
*)cache->node.mm);
+ cache->is_lmem = false;
+ } else if (cache->node.allocated) {
ggtt->vm.clear_range(&ggtt->vm,
cache->node.start,
cache->node.size);
@@ -1066,6 +1073,42 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,
return vaddr;
}
+static void *reloc_lmem(struct drm_i915_gem_object *obj,
+ struct reloc_cache *cache,
+ unsigned long page)
+{
+ void *vaddr;
+ int err;
+
+ GEM_BUG_ON(use_cpu_reloc(cache, obj));
+
+ if (cache->vaddr) {
+ io_mapping_unmap_atomic((void __force __iomem *)
unmask_page(cache->vaddr));
+ } else {
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return ERR_PTR(err);
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, true);
+ i915_gem_object_unlock(obj);
+ if (err) {
+ i915_gem_object_unpin_pages(obj);
+ return ERR_PTR(err);
+ }
+
+ cache->node.mm = (void *)obj;
+ cache->is_lmem = true;
+ }
+
+ vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, page);
+
+ cache->vaddr = (unsigned long)vaddr;
+ cache->page = page;
+
+ return vaddr;
+}
+
static void *reloc_iomap(struct drm_i915_gem_object *obj,
struct reloc_cache *cache,
unsigned long page)
@@ -1142,8 +1185,12 @@ static void *reloc_vaddr(struct drm_i915_gem_object *obj,
vaddr = unmask_page(cache->vaddr);
} else {
vaddr = NULL;
- if ((cache->vaddr & KMAP) == 0)
- vaddr = reloc_iomap(obj, cache, page);
+ if ((cache->vaddr & KMAP) == 0) {
+ if (i915_gem_object_is_lmem(obj))
+ vaddr = reloc_lmem(obj, cache, page);
+ else
+ vaddr = reloc_iomap(obj, cache, page);
+ }
if (!vaddr)
vaddr = reloc_kmap(obj, cache, page);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 10/37] drm/i915/blt: don't assume pinned intel_context
Currently we just pass in bcs0->engine_context so it matters not, but in
the future we may want to pass in something that is not a
kernel_context, so try to be a bit more generic.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_client_blt.c | 3 ++-
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index de6616bdb3a6..08a84c940d8d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "gt/intel_context.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
@@ -175,7 +176,7 @@ static void clear_pages_worker(struct work_struct *work)
if (unlikely(err))
goto out_unlock;
- rq = i915_request_create(w->ce);
+ rq = intel_context_create_request(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_unpin;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 837dd6636dd1..fa90c38c8b07 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "gt/intel_context.h"
#include "i915_gem_clflush.h"
#include "i915_gem_object_blt.h"
@@ -64,7 +65,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
i915_gem_object_unlock(obj);
}
- rq = i915_request_create(ce);
+ rq = intel_context_create_request(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_unpin;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 08/37] drm/i915: setup io-mapping for LMEM
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index ca906d1ff631..7f1543e2759c 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -41,8 +41,32 @@ lmem_create_object(struct intel_memory_region *mem,
return obj;
}
+static void
+region_lmem_release(struct intel_memory_region *mem)
+{
+ io_mapping_fini(&mem->iomap);
+ intel_memory_region_release_buddy(mem);
+}
+
+static int
+region_lmem_init(struct intel_memory_region *mem)
+{
+ int ret;
+
+ if (!io_mapping_init_wc(&mem->iomap,
+ mem->io_start,
+ resource_size(&mem->region)))
+ return -EIO;
+
+ ret = intel_memory_region_init_buddy(mem);
+ if (ret)
+ io_mapping_fini(&mem->iomap);
+
+ return ret;
+}
+
const struct intel_memory_region_ops intel_region_lmem_ops = {
- .init = intel_memory_region_init_buddy,
- .release = intel_memory_region_release_buddy,
+ .init = region_lmem_init,
+ .release = region_lmem_release,
.create_object = lmem_create_object,
};
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 09/37] drm/i915/lmem: support kernel mapping
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 36 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 8 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 20 -
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 +-
.../drm/i915/gem/selftests/huge_gem_object.c | 4 +-
.../drm/i915/selftests/intel_memory_region.c | 76 +++
9 files changed, 152 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index 5e72cb1cc2d3..c2e237702e8c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -140,7 +140,9 @@ static void i915_gem_object_put_pages_internal(struct
drm_i915_gem_object *obj,
static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
-I915_GEM_OBJECT_IS_SHRINKABLE,
+I915_GEM_OBJECT_IS_SHRINKABLE |
+I915_GEM_OBJECT_IS_MAPPABLE,
+
.get_pages = i915_gem_object_get_pages_internal,
.put_pages = i915_gem_object_put_pages_internal,
};
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index ac5a15db1d27..8d957135afa4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -9,11 +9,47 @@
#include "i915_drv.h"
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .flags = I915_GEM_OBJECT_IS_MAPPABLE,
+
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
};
+/* XXX: Time to vfunc your life up? */
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, PAGE_SIZE);
+}
+
+void __iomem *i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
+}
+
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
struct intel_memory_region *region = obj->mm.region;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index ebc15fe24f58..31a6462bdbb6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -13,6 +13,14 @@ struct drm_i915_gem_object;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n, unsigned long size);
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n);
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 1af838050d6c..1cbc63470212 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -158,6 +158,12 @@ i915_gem_object_is_proxy(const struct drm_i915_gem_object
*obj)
return obj->ops->flags & I915_GEM_OBJECT_IS_PROXY;
}
+static inline bool
+i915_gem_object_is_mappable(const struct drm_i915_gem_object *obj)
+{
+ return obj->ops->flags & I915_GEM_OBJECT_IS_MAPPABLE;
+}
+
static inline bool
i915_gem_object_needs_async_cancel(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drive
[Intel-gfx] [PATCH v3 04/37] drm/i915/region: support continuous allocations
Some objects may need to be allocated as a continuous block, thinking
ahead the various kernel io_mapping interfaces seem to expect it.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 4 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 10 +-
drivers/gpu/drm/i915/gem/i915_gem_region.h| 3 +-
.../drm/i915/selftests/intel_memory_region.c | 152 +-
drivers/gpu/drm/i915/selftests/mock_region.c | 5 +-
5 files changed, 166 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 5e2fa37e9bc0..eb92243d473b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -116,6 +116,10 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
+ unsigned long flags;
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+
/*
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index be126e70c90f..d9cd722b5dbf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -42,6 +42,9 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
return -ENOMEM;
}
+ if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
+ flags = I915_ALLOC_CONTIGUOUS;
+
ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
if (ret)
goto err_free_sg;
@@ -98,10 +101,12 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
}
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem)
+ struct intel_memory_region *mem,
+ unsigned long flags)
{
INIT_LIST_HEAD(&obj->mm.blocks);
obj->mm.region= mem;
+ obj->flags = flags;
mutex_lock(&mem->obj_lock);
list_add(&obj->mm.region_link, &mem->objects);
@@ -125,6 +130,9 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
if (!mem)
return ERR_PTR(-ENODEV);
+ if (flags & ~I915_BO_ALLOC_FLAGS)
+ return ERR_PTR(-EINVAL);
+
size = round_up(size, mem->min_page_size);
GEM_BUG_ON(!size);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h
b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index ebddc86d78f7..f2ff6f8bff74 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -17,7 +17,8 @@ void i915_gem_object_put_pages_buddy(struct
drm_i915_gem_object *obj,
struct sg_table *pages);
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem);
+ struct intel_memory_region *mem,
+ unsigned long flags);
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 2f13e4c1d999..70b467d4e811 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -81,17 +81,17 @@ static int igt_mock_fill(void *arg)
static void igt_mark_evictable(struct drm_i915_gem_object *obj)
{
- i915_gem_object_unpin_pages(obj);
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
obj->mm.madv = I915_MADV_DONTNEED;
list_move(&obj->mm.region_link, &obj->mm.region->purgeable);
}
-static int igt_mock_shrink(void *arg)
+static int igt_frag_region(struct intel_memory_region *mem,
+ struct list_head *objects)
{
- struct intel_memory_region *mem = arg;
struct drm_i915_gem_object *obj;
unsigned long n_objects;
- LIST_HEAD(objects);
resource_size_t target;
resource_size_t total;
int err = 0;
@@ -109,7 +109,7 @@ static int igt_mock_shrink(void *arg)
goto err_close_objects;
}
- list_add(&obj->st_link, &objects);
+ list_add(&obj->st_link, objects);
err = i915_gem_object_pin_pages(obj);
if (err)
@@ -123,6 +123,39 @@ static int igt_mock_shrink(void *arg)
igt_mark_evictable(obj);
}
+ return 0;
+
+err_close_objects:
+ close_object
[Intel-gfx] [PATCH v3 03/37] drm/i915/region: support basic eviction
Support basic eviction for regions.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 7 ++
drivers/gpu/drm/i915/gem/i915_gem_region.c| 11 +++
drivers/gpu/drm/i915/gem/i915_gem_region.h| 1 +
drivers/gpu/drm/i915/i915_gem.c | 17 +
drivers/gpu/drm/i915/intel_memory_region.c| 73 +-
drivers/gpu/drm/i915/intel_memory_region.h| 5 ++
.../drm/i915/selftests/intel_memory_region.c | 76 +++
drivers/gpu/drm/i915/selftests/mock_region.c | 1 +
8 files changed, 187 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index a32066e66271..5e2fa37e9bc0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -168,6 +168,13 @@ struct drm_i915_gem_object {
* List of memory region blocks allocated for this object.
*/
struct list_head blocks;
+ /**
+* Element within memory_region->objects or
+* memory_region->purgeable if the object is marked as
+* DONTNEED. Access is protected by memory_region->obj_lock.
+*/
+ struct list_head region_link;
+ struct list_head tmp_link;
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 3cd1bf15e25b..be126e70c90f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -102,6 +102,17 @@ void i915_gem_object_init_memory_region(struct
drm_i915_gem_object *obj,
{
INIT_LIST_HEAD(&obj->mm.blocks);
obj->mm.region= mem;
+
+ mutex_lock(&mem->obj_lock);
+ list_add(&obj->mm.region_link, &mem->objects);
+ mutex_unlock(&mem->obj_lock);
+}
+
+void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj)
+{
+ mutex_lock(&obj->mm.region->obj_lock);
+ list_del(&obj->mm.region_link);
+ mutex_unlock(&obj->mm.region->obj_lock);
}
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h
b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index da5a2ca1a0fb..ebddc86d78f7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -18,6 +18,7 @@ void i915_gem_object_put_pages_buddy(struct
drm_i915_gem_object *obj,
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
struct intel_memory_region *mem);
+void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
i915_gem_object_create_region(struct intel_memory_region *mem,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6ff01a404346..8735dea74809 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1105,6 +1105,23 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void
*data,
!i915_gem_object_has_pages(obj))
i915_gem_object_truncate(obj);
+ if (obj->mm.region) {
+ mutex_lock(&obj->mm.region->obj_lock);
+
+ switch (obj->mm.madv) {
+ case I915_MADV_WILLNEED:
+ list_move(&obj->mm.region_link,
+ &obj->mm.region->objects);
+ break;
+ default:
+ list_move(&obj->mm.region_link,
+ &obj->mm.region->purgeable);
+ break;
+ }
+
+ mutex_unlock(&obj->mm.region->obj_lock);
+ }
+
args->retained = obj->mm.madv != __I915_MADV_PURGED;
mutex_unlock(&obj->mm.lock);
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index ef12e462acb8..3a3caaadea1f 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -12,6 +12,51 @@ const u32 intel_region_map[] = {
[INTEL_MEMORY_STOLEN] = BIT(INTEL_STOLEN + INTEL_MEMORY_TYPE_SHIFT) |
BIT(0),
};
+static int
+intel_memory_region_evict(struct intel_memory_region *mem,
+ resource_size_t target,
+ unsigned int flags)
+{
+ struct drm_i915_gem_object *obj;
+ resource_size_t found;
+ int err;
+
+ err = 0;
+ found = 0;
+
+ mutex_lock(&mem->obj_lock);
+ list_for_each_entry(obj, &mem->purgeable, mm.region_link) {
+ if (!i915_gem_object_has_pages(obj))
+ continue;
+
+ if (READ_ONCE(obj->pin_global))
+ continue;
+
+ if (atomic_read(&obj-
[Intel-gfx] [PATCH v3 02/37] drm/i915: introduce intel_memory_region
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and of course device. At some point we are probably going to want
use a common struct here, such that we are better aligned with say TTM.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Niranjana Vishwanathapura
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile | 2 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 129 +
drivers/gpu/drm/i915/gem/i915_gem_region.h| 27 +++
.../gpu/drm/i915/gem/selftests/huge_pages.c | 78
drivers/gpu/drm/i915/i915_buddy.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_memory_region.c| 175 ++
drivers/gpu/drm/i915/intel_memory_region.h| 107 +++
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 114
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
drivers/gpu/drm/i915/selftests/mock_region.c | 60 ++
drivers/gpu/drm/i915/selftests/mock_region.h | 16 ++
14 files changed, 722 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h
create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3962d9728dd7..e9cf87696bde 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -50,6 +50,7 @@ i915-y += i915_drv.o \
i915_utils.o \
intel_csr.o \
intel_device_info.o \
+ intel_memory_region.o \
intel_pch.o \
intel_pm.o \
intel_runtime_pm.o \
@@ -115,6 +116,7 @@ gem-y += \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
gem/i915_gem_pm.o \
+ gem/i915_gem_region.o \
gem/i915_gem_shmem.o \
gem/i915_gem_shrinker.o \
gem/i915_gem_stolen.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index d474c6ac4100..a32066e66271 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -160,6 +160,15 @@ struct drm_i915_gem_object {
struct mutex lock; /* protects the pages and their use */
atomic_t pages_pin_count;
+ /**
+* Memory region for this object.
+*/
+ struct intel_memory_region *region;
+ /**
+* List of memory region blocks allocated for this object.
+*/
+ struct list_head blocks;
+
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
new file mode 100644
index ..3cd1bf15e25b
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "i915_gem_region.h"
+#include "i915_drv.h"
+
+void
+i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
+ struct sg_table *pages)
+{
+ __intel_memory_region_put_pages_buddy(obj->mm.region, &obj->mm.blocks);
+
+ obj->mm.dirty = false;
+ sg_free_table(pages);
+ kfree(pages);
+}
+
+int
+i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ struct list_head *blocks = &obj->mm.blocks;
+ resource_size_t size = obj->base.size;
+ resource_size_t prev_end;
+ struct i915_buddy_block *block;
+ unsigned int flags = 0;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ unsigned int sg_page_sizes;
+ unsigned long i;
+ int ret;
+
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ if (sg_alloc_table(st, size >> ilog2(mem->mm.chunk_size), GFP_KERNEL)) {
+ kfree(st);
+ return -ENOMEM;
+ }
+
+ ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
+ if (ret)
+ goto err_free_sg;
+
+ GEM_BUG_ON(list_empty(blocks));
+
+ sg = st->sgl;
+
[Intel-gfx] [PATCH v3 06/37] drm/i915: Add memory region information to device_info
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 39cdf4eac2a6..d947f7415861 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2212,6 +2212,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
/* Having GuC is not the same as using GuC */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 92e0c2e0954c..3166f38910f7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -159,6 +159,8 @@ struct intel_device_info {
unsigned int page_sizes; /* page sizes supported by the HW */
+ u32 memory_regions; /* regions supported by the HW */
+
u32 display_mmio_offset;
u8 num_pipes;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 07/37] drm/i915: support creating LMEM objects
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 31
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 23 +
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 48 +++
drivers/gpu/drm/i915/intel_region_lmem.h | 11 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 45 +
8 files changed, 166 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e9cf87696bde..17394fd0c7f8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -112,6 +112,7 @@ gem-y += \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_object_blt.o \
+ gem/i915_gem_lmem.o \
gem/i915_gem_mman.o \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
@@ -140,6 +141,7 @@ i915-y += \
i915_scheduler.o \
i915_trace_points.o \
i915_vma.o \
+ intel_region_lmem.o \
intel_wopcm.o
# general-purpose microcontroller (GuC) support
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
new file mode 100644
index ..ac5a15db1d27
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
+#include "i915_drv.h"
+
+const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .get_pages = i915_gem_object_get_pages_buddy,
+ .put_pages = i915_gem_object_put_pages_buddy,
+ .release = i915_gem_object_release_memory_region,
+};
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *region = obj->mm.region;
+
+ return region && region->type == INTEL_LMEM;
+}
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags)
+{
+ return i915_gem_object_create_region(i915->regions[INTEL_MEMORY_LMEM],
+size, flags);
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
new file mode 100644
index ..ebc15fe24f58
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __I915_GEM_LMEM_H
+#define __I915_GEM_LMEM_H
+
+#include
+
+struct drm_i915_private;
+struct drm_i915_gem_object;
+
+extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags);
+
+#endif /* !__I915_GEM_LMEM_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d947f7415861..f7be8cee4709 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -98,6 +98,8 @@
#include "i915_vma.h"
#include "i915_irq.h"
+#include "intel_region_lmem.h"
+
#include "intel_gvt.h"
/* General customization:
@@ -1369,6 +1371,8 @@ struct drm_i915_private {
*/
resource_size_t stolen_usable_size; /* Total size minus reserved
ranges */
+ struct intel_memory_region *regions[INTEL_MEMORY_UKNOWN];
+
struct intel_uncore uncore;
struct i915_virtual_gpu vgpu;
@@ -2213,6 +2217,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
new file mode 100644
index ..ca906d1ff631
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#inclu
[Intel-gfx] [PATCH v3 01/37] drm/i915: buddy allocator
Simple buddy allocator. We want to allocate properly aligned
power-of-two blocks to promote usage of huge-pages for the GTT, so 64K,
2M and possibly even 1G. While we do support allocating stuff at a
specific offset, it is more intended for preallocating portions of the
address space, say for an initial framebuffer, for other uses drm_mm is
probably a much better fit. Anyway, hopefully this can all be thrown
away if we eventually move to having the core MM manage device memory.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_buddy.c | 433 +++
drivers/gpu/drm/i915/i915_buddy.h | 126 +++
drivers/gpu/drm/i915/i915_globals.c | 1 +
drivers/gpu/drm/i915/i915_globals.h | 1 +
drivers/gpu/drm/i915/selftests/i915_buddy.c | 719 ++
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
7 files changed, 1282 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_buddy.c
create mode 100644 drivers/gpu/drm/i915/i915_buddy.h
create mode 100644 drivers/gpu/drm/i915/selftests/i915_buddy.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d3ca46dc54ae..3962d9728dd7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -126,6 +126,7 @@ gem-y += \
i915-y += \
$(gem-y) \
i915_active.o \
+ i915_buddy.o \
i915_cmd_parser.o \
i915_gem_evict.o \
i915_gem_fence_reg.o \
diff --git a/drivers/gpu/drm/i915/i915_buddy.c
b/drivers/gpu/drm/i915/i915_buddy.c
new file mode 100644
index ..e3039e1273ef
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_buddy.c
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+
+#include "i915_buddy.h"
+
+#include "i915_gem.h"
+#include "i915_globals.h"
+#include "i915_utils.h"
+
+static struct i915_global_block {
+ struct i915_global base;
+ struct kmem_cache *slab_blocks;
+} global;
+
+static void i915_global_buddy_shrink(void)
+{
+ kmem_cache_shrink(global.slab_blocks);
+}
+
+static void i915_global_buddy_exit(void)
+{
+ kmem_cache_destroy(global.slab_blocks);
+}
+
+static struct i915_global_block global = { {
+ .shrink = i915_global_buddy_shrink,
+ .exit = i915_global_buddy_exit,
+} };
+
+int __init i915_global_buddy_init(void)
+{
+ global.slab_blocks = KMEM_CACHE(i915_buddy_block, SLAB_HWCACHE_ALIGN);
+ if (!global.slab_blocks)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static struct i915_buddy_block *i915_block_alloc(struct i915_buddy_block
*parent,
+unsigned int order,
+u64 offset)
+{
+ struct i915_buddy_block *block;
+
+ block = kmem_cache_zalloc(global.slab_blocks, GFP_KERNEL);
+ if (!block)
+ return NULL;
+
+ block->header = offset;
+ block->header |= order;
+ block->parent = parent;
+
+ return block;
+}
+
+static void i915_block_free(struct i915_buddy_block *block)
+{
+ kmem_cache_free(global.slab_blocks, block);
+}
+
+static void mark_allocated(struct i915_buddy_block *block)
+{
+ block->header &= ~I915_BUDDY_HEADER_STATE;
+ block->header |= I915_BUDDY_ALLOCATED;
+
+ list_del(&block->link);
+}
+
+static void mark_free(struct i915_buddy_mm *mm,
+ struct i915_buddy_block *block)
+{
+ block->header &= ~I915_BUDDY_HEADER_STATE;
+ block->header |= I915_BUDDY_FREE;
+
+ list_add(&block->link,
+&mm->free_list[i915_buddy_block_order(block)]);
+}
+
+static void mark_split(struct i915_buddy_block *block)
+{
+ block->header &= ~I915_BUDDY_HEADER_STATE;
+ block->header |= I915_BUDDY_SPLIT;
+
+ list_del(&block->link);
+}
+
+int i915_buddy_init(struct i915_buddy_mm *mm, u64 size, u64 chunk_size)
+{
+ unsigned int i;
+ u64 offset;
+
+ if (size < chunk_size)
+ return -EINVAL;
+
+ if (chunk_size < PAGE_SIZE)
+ return -EINVAL;
+
+ if (!is_power_of_2(chunk_size))
+ return -EINVAL;
+
+ size = round_down(size, chunk_size);
+
+ mm->size = size;
+ mm->chunk_size = chunk_size;
+ mm->max_order = ilog2(size) - ilog2(chunk_size);
+
+ GEM_BUG_ON(mm->max_order > I915_BUDDY_MAX_ORDER);
+
+ mm->free_list = kmalloc_array(mm->max_order + 1,
+ sizeof(struct list_head),
+ GFP_KERNEL);
+ if (!mm->free_list)
+ return -ENOMEM;
+
+ for (i = 0; i <= mm->max_order; ++i)
+ INIT_LIST_HEAD(&mm->free_list[i]);
+
+ mm->n_roots = hweight64(size);
+
+ mm->roots = kmalloc_array(mm->n_roots,
+ sizeof(struct i915_buddy_block *),
+
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Push the wakeref->count deferral to the backend
== Series Details == Series: series starting with [1/2] drm/i915: Push the wakeref->count deferral to the backend URL : https://patchwork.freedesktop.org/series/64995/ State : success == Summary == CI Bug Log - changes from CI_DRM_6670 -> Patchwork_13956 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/ Known issues Here are the changes found in Patchwork_13956 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-write-gtt-noreloc: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt-noreloc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/fi-icl-u3/igt@gem_exec_re...@basic-write-gtt-noreloc.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#109485]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_cpu_reloc@basic: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@gem_cpu_re...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/fi-icl-u3/igt@gem_cpu_re...@basic.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][7] ([fdo#08]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [WARN][9] ([fdo#109380]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [SKIP][11] ([fdo#109271]) -> [PASS][12] +23 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 Participating hosts (53 -> 46) -- Additional (1): fi-bsw-n3050 Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6670 -> Patchwork_13956 CI-20190529: 20190529 CI_DRM_6670: dca4867439f21c056afbde56cd4eb241b50f35d4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13956: ab133ab66633a073ef56d96a3a8eea8e6ef0d4b4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ab133ab66633 drm/i915/guc: Keep the engine awake until the tasklet is idle 7aa800e51d90 drm/i915: Push the wakeref->count deferral to the backend == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 05/37] drm/i915/region: support volatile objects
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 17 +++---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 ++
drivers/gpu/drm/i915/gem/i915_gem_region.c| 7 ++-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 12 ++--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 5 +-
.../drm/i915/selftests/intel_memory_region.c | 56 +++
8 files changed, 91 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index 0c41e04ab8fa..5e72cb1cc2d3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -117,13 +117,6 @@ static int i915_gem_object_get_pages_internal(struct
drm_i915_gem_object *obj)
goto err;
}
- /* Mark the pages as dontneed whilst they are still pinned. As soon
-* as they are unpinned they are allowed to be reaped by the shrinker,
-* and the caller is expected to repopulate - the contents of this
-* object are only valid whilst active and pinned.
-*/
- obj->mm.madv = I915_MADV_DONTNEED;
-
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
@@ -143,7 +136,6 @@ static void i915_gem_object_put_pages_internal(struct
drm_i915_gem_object *obj,
internal_free_pages(pages);
obj->mm.dirty = false;
- obj->mm.madv = I915_MADV_WILLNEED;
}
static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
@@ -188,6 +180,15 @@ i915_gem_object_create_internal(struct drm_i915_private
*i915,
drm_gem_private_object_init(&i915->drm, &obj->base, size);
i915_gem_object_init(obj, &i915_gem_object_internal_ops);
+ /*
+* Mark the object as volatile, such that the pages are marked as
+* dontneed whilst they are still pinned. As soon as they are unpinned
+* they are allowed to be reaped by the shrinker, and the caller is
+* expected to repopulate - the contents of this object are only valid
+* whilst active and pinned.
+*/
+ obj->flags = I915_BO_ALLOC_VOLATILE;
+
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3714cf234d64..1af838050d6c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -122,6 +122,12 @@ i915_gem_object_lock_fence(struct drm_i915_gem_object
*obj);
void i915_gem_object_unlock_fence(struct drm_i915_gem_object *obj,
struct dma_fence *fence);
+static inline bool
+i915_gem_object_is_volatile(const struct drm_i915_gem_object *obj)
+{
+ return obj->flags & I915_BO_ALLOC_VOLATILE;
+}
+
static inline void
i915_gem_object_set_readonly(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index eb92243d473b..2142d74a57ea 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -118,7 +118,8 @@ struct drm_i915_gem_object {
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | I915_BO_ALLOC_VOLATILE)
/*
* Is the object to be mapped as read-only to the GPU
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 18f0ce0135c1..d3f0debdb875 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -18,6 +18,9 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
lockdep_assert_held(&obj->mm.lock);
+ if (i915_gem_object_is_volatile(obj))
+ obj->mm.madv = I915_MADV_DONTNEED;
+
/* Make the pages coherent with the GPU (flushing any swapin). */
if (obj->cache_dirty) {
obj->write_domain = 0;
@@ -159,6 +162,9 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
if (IS_ERR_OR_NULL(pages))
return pages;
+ if (i915_gem_object_is_volatile(obj))
+ obj->mm.madv = I915_MADV_WILLNEED;
+
i915_gem_object_make_unshrinkable(obj);
if (obj->mm.mapping) {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index d9cd722b5dbf..0d09da9f7168 100644
--- a/driver
[Intel-gfx] [PATCH v3 00/37] Introduce memory region concept (including device local memory)
In preparation for upcoming devices with device local memory, introduce the concept of different memory regions, and a simple buddy allocator to manage them in i915. One of the concerns raised from v1 was around not using enough of TTM, which is a fair criticism, so trying to get better alignment here is something we are investigating, though currently that is still WIP so in the meantime v3 still continues to push more of the low-level details forward, but not yet the TTM interactions. Sidenote: Daniel raised a fair point with the whole mmap_offset uAPI and whether we can just get away with using gtt_mmap, it looks like it should work and would simplify a few things and possibly allow us to drop a couple patches. Thoughts? Abdiel Janulgue (11): drm/i915: Add memory region information to device_info drm/i915: setup io-mapping for LMEM drm/i915/lmem: support kernel mapping drm/i915: enumerate and init each supported region drm/i915: Allow i915 to manage the vma offset nodes instead of drm core drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET drm/i915/lmem: add helper to get CPU accessible offset drm/i915: Add cpu and lmem fault handlers drm/i915: cpu-map based dumb buffers drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION drm/i915/query: Expose memory regions through the query uAPI CQ Tang (1): drm/i915: check for missing aperture in insert_mappable_node Daniele Ceraolo Spurio (4): drm/i915: define HAS_MAPPABLE_APERTURE drm/i915: do not map aperture if it is not available. drm/i915: set num_fence_regs to 0 if there is no aperture drm/i915: error capture with no ggtt slot Matthew Auld (20): drm/i915: buddy allocator drm/i915: introduce intel_memory_region drm/i915/region: support basic eviction drm/i915/region: support continuous allocations drm/i915/region: support volatile objects drm/i915: support creating LMEM objects drm/i915/blt: don't assume pinned intel_context drm/i915/blt: bump size restriction drm/i915/blt: support copying objects drm/i915/selftests: move gpu-write-dw into utils drm/i915/selftests: add write-dword test for LMEM drm/i915/selftest: extend coverage to include LMEM huge-pages drm/i915/lmem: support CPU relocations drm/i915/lmem: support pread drm/i915/lmem: support pwrite drm/i915: treat shmem as a region drm/i915: treat stolen as a region drm/i915/selftests: check for missing aperture drm/i915: support basic object migration HAX drm/i915: add the fake lmem region Michal Wajdeczko (1): drm/i915: Don't try to place HWS in non-existing mappable region arch/x86/kernel/early-quirks.c| 26 + drivers/gpu/drm/i915/Makefile | 5 + .../gpu/drm/i915/gem/i915_gem_client_blt.c| 34 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 + drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 55 +- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_ioctls.h| 4 + drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 315 +++ drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 37 + drivers/gpu/drm/i915/gem/i915_gem_mman.c | 376 +++- drivers/gpu/drm/i915/gem/i915_gem_object.c| 271 ++ drivers/gpu/drm/i915/gem/i915_gem_object.h| 29 +- .../gpu/drm/i915/gem/i915_gem_object_blt.c| 349 +++- .../gpu/drm/i915/gem/i915_gem_object_blt.h| 18 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 48 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 28 +- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_region.c| 165 drivers/gpu/drm/i915/gem/i915_gem_region.h| 29 + drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 71 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 71 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.h| 3 +- .../drm/i915/gem/selftests/huge_gem_object.c | 4 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 331 --- .../i915/gem/selftests/i915_gem_client_blt.c | 16 +- .../i915/gem/selftests/i915_gem_coherency.c | 5 +- .../drm/i915/gem/selftests/i915_gem_context.c | 134 +-- .../drm/i915/gem/selftests/i915_gem_mman.c| 15 +- .../i915/gem/selftests/i915_gem_object_blt.c | 128 ++- .../drm/i915/gem/selftests/igt_gem_utils.c| 135 +++ .../drm/i915/gem/selftests/igt_gem_utils.h| 16 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 5 +- drivers/gpu/drm/i915/gt/intel_reset.c | 13 +- drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 2 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 +- drivers/gpu/drm/i915/i915_buddy.c | 433 ++ drivers/gpu/drm/i915/i915_buddy.h | 128 +++ drivers/gpu/drm/i915/i915_drv.c | 28 +- drivers/gpu/drm/i915/i915_drv.h | 20 +- drivers/gpu/drm/i915/i915_gem.c | 41
Re: [Intel-gfx] [PATCH 3/3] drm/i915/blt: bump the size restriction
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tang, CQ
> Sent: Friday, August 9, 2019 3:21 PM
> To: Chris Wilson ; Auld, Matthew
> ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/blt: bump the size restriction
>
>
>
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> > Behalf Of Chris Wilson
> > Sent: Friday, August 9, 2019 2:18 PM
> > To: Auld, Matthew ; intel-
> > g...@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/blt: bump the size
> > restriction
> >
> > Quoting Matthew Auld (2019-08-09 21:29:26)
> > > As pointed out by Chris, with our current approach we are actually
> > > limited to S16_MAX * PAGE_SIZE for our size when using the blt to
> > > clear pages. Keeping things simple try to fix this by reducing the
> > > copy to a sequence of S16_MAX * PAGE_SIZE blocks.
>
> Just a general question. If the address space is limited to 1G, for example,
> and we want to copy between two 1G-size objects.
> Do we do fragmentation inside the blitter copying routine?
>
> This could happen during swapping. We pre-allocate 1G PPGTT, and reserve
> the rest of address space, so only 1G space can be used.
Or, can we add offset and size into the copying object, like the pread/pwrite
to specify offset/size to read/write.
Then we can do loop in caller. But prefer to do fragmentation inside.
--CQ
>
> --CQ
>
>
> > >
> > > Reported-by: Chris Wilson
> > > Signed-off-by: Matthew Auld
> > > Cc: Chris Wilson
> > > ---
> > > .../gpu/drm/i915/gem/i915_gem_client_blt.c| 31 +++-
> > > .../gpu/drm/i915/gem/i915_gem_object_blt.c| 139 ++-
> --
> > -
> > > .../gpu/drm/i915/gem/i915_gem_object_blt.h| 9 +-
> > > .../i915/gem/selftests/i915_gem_client_blt.c | 16 +-
> > > .../i915/gem/selftests/i915_gem_object_blt.c | 22 ++-
> > > 5 files changed, 170 insertions(+), 47 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> > > index 08a84c940d8d..4b096309a97e 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> > > @@ -5,6 +5,8 @@
> > >
> > > #include "i915_drv.h"
> > > #include "gt/intel_context.h"
> > > +#include "gt/intel_engine_pm.h"
> > > +#include "gt/intel_engine_pool.h"
> > > #include "i915_gem_client_blt.h"
> > > #include "i915_gem_object_blt.h"
> > >
> > > @@ -156,7 +158,9 @@ static void clear_pages_worker(struct
> > > work_struct
> > *work)
> > > struct drm_i915_private *i915 = w->ce->engine->i915;
> > > struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
> > > struct i915_vma *vma = w->sleeve->vma;
> > > + struct intel_engine_pool_node *pool;
> > > struct i915_request *rq;
> > > + struct i915_vma *batch;
> > > int err = w->dma.error;
> > >
> > > if (unlikely(err))
> > > @@ -176,10 +180,17 @@ static void clear_pages_worker(struct
> > work_struct *work)
> > > if (unlikely(err))
> > > goto out_unlock;
> > >
> > > + intel_engine_pm_get(w->ce->engine);
> > > + batch = intel_emit_vma_fill_blt(&pool, w->ce, vma,
> > > + w->value);
> >
> > I had to search for where pool was being set!
> >
> > Hmm, batch is from pool right? So we are the owner of the batch, and
> > we could set batch->private = pool.
> >
> > > + if (IS_ERR(batch)) {
> > > + err = PTR_ERR(batch);
> > > + goto out_unpin;
> > > + }
> > > +
> > > rq = intel_context_create_request(w->ce);
> > > if (IS_ERR(rq)) {
> > > err = PTR_ERR(rq);
> > > - goto out_unpin;
> > > + goto out_batch;
> > > }
> > >
> > > /* There's no way the fence has signalled */ @@ -187,6
> > > +198,16 @@ static void clear_pages_worker(struct work_struct *work)
> > >clear_pages_dma_fence_cb))
> > > GEM_BUG_ON(1);
> > >
> > > + i915_vma_lock(batch);
> > > + err = i915_vma_move_to_active(batch, rq, 0);
> > > + i915_vma_unlock(batch);
> > > + if (unlikely(err))
> > > + goto out_request;
> > > +
> > > + err = intel_engine_pool_mark_active(pool, rq);
> > > + if (unlikely(err))
> > > + goto out_request;
> > > +
> > > if (w->ce->engine->emit_init_breadcrumb) {
> > > err = w->ce->engine->emit_init_breadcrumb(rq);
> > > if (unlikely(err))
> > > @@ -202,7 +223,9 @@ static void clear_pages_worker(struct
> > > work_struct
> > *work)
> > > if (err)
> > > goto out_request;
> > >
> > > - err = intel_emit_vma_fill_blt(rq, vma, w->value);
> > > + err = w->ce->engine->emit_bb_start(rq,
> > > + batc
Re: [Intel-gfx] [PATCH 3/3] drm/i915/blt: bump the size restriction
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Chris Wilson
> Sent: Friday, August 9, 2019 2:18 PM
> To: Auld, Matthew ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/blt: bump the size restriction
>
> Quoting Matthew Auld (2019-08-09 21:29:26)
> > As pointed out by Chris, with our current approach we are actually
> > limited to S16_MAX * PAGE_SIZE for our size when using the blt to
> > clear pages. Keeping things simple try to fix this by reducing the
> > copy to a sequence of S16_MAX * PAGE_SIZE blocks.
Just a general question. If the address space is limited to 1G, for example,
and we want to copy between two 1G-size objects.
Do we do fragmentation inside the blitter copying routine?
This could happen during swapping. We pre-allocate 1G PPGTT, and reserve the
rest of address space, so only 1G space can be used.
--CQ
> >
> > Reported-by: Chris Wilson
> > Signed-off-by: Matthew Auld
> > Cc: Chris Wilson
> > ---
> > .../gpu/drm/i915/gem/i915_gem_client_blt.c| 31 +++-
> > .../gpu/drm/i915/gem/i915_gem_object_blt.c| 139 ++---
> -
> > .../gpu/drm/i915/gem/i915_gem_object_blt.h| 9 +-
> > .../i915/gem/selftests/i915_gem_client_blt.c | 16 +-
> > .../i915/gem/selftests/i915_gem_object_blt.c | 22 ++-
> > 5 files changed, 170 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> > index 08a84c940d8d..4b096309a97e 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> > @@ -5,6 +5,8 @@
> >
> > #include "i915_drv.h"
> > #include "gt/intel_context.h"
> > +#include "gt/intel_engine_pm.h"
> > +#include "gt/intel_engine_pool.h"
> > #include "i915_gem_client_blt.h"
> > #include "i915_gem_object_blt.h"
> >
> > @@ -156,7 +158,9 @@ static void clear_pages_worker(struct work_struct
> *work)
> > struct drm_i915_private *i915 = w->ce->engine->i915;
> > struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
> > struct i915_vma *vma = w->sleeve->vma;
> > + struct intel_engine_pool_node *pool;
> > struct i915_request *rq;
> > + struct i915_vma *batch;
> > int err = w->dma.error;
> >
> > if (unlikely(err))
> > @@ -176,10 +180,17 @@ static void clear_pages_worker(struct
> work_struct *work)
> > if (unlikely(err))
> > goto out_unlock;
> >
> > + intel_engine_pm_get(w->ce->engine);
> > + batch = intel_emit_vma_fill_blt(&pool, w->ce, vma, w->value);
>
> I had to search for where pool was being set!
>
> Hmm, batch is from pool right? So we are the owner of the batch, and we
> could set batch->private = pool.
>
> > + if (IS_ERR(batch)) {
> > + err = PTR_ERR(batch);
> > + goto out_unpin;
> > + }
> > +
> > rq = intel_context_create_request(w->ce);
> > if (IS_ERR(rq)) {
> > err = PTR_ERR(rq);
> > - goto out_unpin;
> > + goto out_batch;
> > }
> >
> > /* There's no way the fence has signalled */ @@ -187,6 +198,16
> > @@ static void clear_pages_worker(struct work_struct *work)
> >clear_pages_dma_fence_cb))
> > GEM_BUG_ON(1);
> >
> > + i915_vma_lock(batch);
> > + err = i915_vma_move_to_active(batch, rq, 0);
> > + i915_vma_unlock(batch);
> > + if (unlikely(err))
> > + goto out_request;
> > +
> > + err = intel_engine_pool_mark_active(pool, rq);
> > + if (unlikely(err))
> > + goto out_request;
> > +
> > if (w->ce->engine->emit_init_breadcrumb) {
> > err = w->ce->engine->emit_init_breadcrumb(rq);
> > if (unlikely(err))
> > @@ -202,7 +223,9 @@ static void clear_pages_worker(struct work_struct
> *work)
> > if (err)
> > goto out_request;
> >
> > - err = intel_emit_vma_fill_blt(rq, vma, w->value);
> > + err = w->ce->engine->emit_bb_start(rq,
> > + batch->node.start,
> > batch->node.size,
> > + 0);
> > out_request:
> > if (unlikely(err)) {
> > i915_request_skip(rq, err); @@ -210,7 +233,11 @@
> > static void clear_pages_worker(struct work_struct *work)
> > }
> >
> > i915_request_add(rq);
> > +out_batch:
> > + i915_vma_unpin(batch);
> > + intel_engine_pool_put(pool);
> > out_unpin:
> > + intel_engine_pm_put(w->ce->engine);
> > i915_vma_unpin(vma);
> > out_unlock:
> > mutex_unlock(&i915->drm.struct_mutex);
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> > index fa90c38c8b07..c1e5edd1e359 100644
> > --- a/drivers/gp
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Backtrack along timeline
== Series Details == Series: drm/i915/execlists: Backtrack along timeline URL : https://patchwork.freedesktop.org/series/64942/ State : success == Summary == CI Bug Log - changes from CI_DRM_6663_full -> Patchwork_13932_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13932_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@independent-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-iclb5/igt@gem_exec_sched...@independent-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-iclb2/igt@gem_exec_sched...@independent-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-apl7/igt@gem_workarou...@suspend-resume-context.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-apl6/igt@gem_workarou...@suspend-resume-context.html * igt@i915_selftest@mock_fence: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-iclb7/igt@i915_selftest@mock_fence.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-iclb7/igt@i915_selftest@mock_fence.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend: - shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#102365]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-snb5/igt@kms_f...@flip-vs-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-snb6/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#109507]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-skl6/igt@kms_f...@flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-skl4/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-iclb1/igt@kms_frontbuffer_track...@fbc-rgb565-draw-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-iclb7/igt@kms_frontbuffer_track...@fbc-rgb565-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-kbl7/igt@kms_frontbuffer_track...@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-kbl3/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-iclb2/igt@kms_psr2...@frontbuffer.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-iclb4/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#108341]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-iclb2/igt@kms_psr@no_drrs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13932/shard-iclb7/igt@kms_psr@psr2_primary_mmap_cpu.html * igt@perf_pmu@rc6-runtime-pm-long: - shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#105010]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6663/shard-iclb3/igt@perf_...@rc6-runtime-pm-long.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patch
[Intel-gfx] ✓ Fi.CI.BAT: success for Some bits from the LMEM series
== Series Details == Series: Some bits from the LMEM series URL : https://patchwork.freedesktop.org/series/64994/ State : success == Summary == CI Bug Log - changes from CI_DRM_6670 -> Patchwork_13955 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/ Known issues Here are the changes found in Patchwork_13955 that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-all: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@gem_b...@busy-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/fi-icl-u3/igt@gem_b...@busy-all.html * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [PASS][3] -> [SKIP][4] ([fdo#109271] / [fdo#109278]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][5] -> [DMESG-WARN][6] ([fdo#102614]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_cpu_reloc@basic: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@gem_cpu_re...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/fi-icl-u3/igt@gem_cpu_re...@basic.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#08]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [WARN][11] ([fdo#109380]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [SKIP][13] ([fdo#109271]) -> [PASS][14] +23 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 Participating hosts (53 -> 47) -- Additional (1): fi-bsw-n3050 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6670 -> Patchwork_13955 CI-20190529: 20190529 CI_DRM_6670: dca4867439f21c056afbde56cd4eb241b50f35d4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13955: 2dafb186902e64ceaf531ee27bd58f985ced2886 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2dafb186902e drm/i915/blt: bump the size restriction 891750b1695e drm/i915/blt: don't assume pinned intel_context 94ffded7068a drm/i915: buddy allocator == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Keep the engine awake until the tasklet is idle
== Series Details == Series: drm/i915/guc: Keep the engine awake until the tasklet is idle URL : https://patchwork.freedesktop.org/series/64992/ State : success == Summary == CI Bug Log - changes from CI_DRM_6670 -> Patchwork_13954 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/ Known issues Here are the changes found in Patchwork_13954 that come from known issues: ### IGT changes ### Possible fixes * igt@gem_cpu_reloc@basic: - fi-icl-u3: [DMESG-WARN][1] ([fdo#107724]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@gem_cpu_re...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/fi-icl-u3/igt@gem_cpu_re...@basic.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][3] ([fdo#08]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: [WARN][5] ([fdo#109380]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-kbl-7567u: [SKIP][7] ([fdo#109271]) -> [PASS][8] +23 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 Participating hosts (53 -> 47) -- Additional (1): fi-bsw-n3050 Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6670 -> Patchwork_13954 CI-20190529: 20190529 CI_DRM_6670: dca4867439f21c056afbde56cd4eb241b50f35d4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13954: 69008bcff2dc3862d89ef9a72d32c916471ac490 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 69008bcff2dc drm/i915/guc: Keep the engine awake until the tasklet is idle == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Some bits from the LMEM series
== Series Details == Series: Some bits from the LMEM series URL : https://patchwork.freedesktop.org/series/64994/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: buddy allocator +drivers/gpu/drm/i915/selftests/i915_buddy.c:292:13: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_buddy.c:292:13: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_buddy.c:647:24: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_buddy.c:647:24: warning: expression using sizeof(void) +./include/linux/slab.h:672:13: error: not a function +./include/linux/slab.h:672:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:672:13: warning: call with no type! Commit: drm/i915/blt: don't assume pinned intel_context Okay! Commit: drm/i915/blt: bump the size restriction - +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:47:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:47:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:29:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:29:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:35:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:35:26: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gtt: enable GTT cache by default
== Series Details ==
Series: series starting with [1/2] drm/i915/gtt: enable GTT cache by default
URL : https://patchwork.freedesktop.org/series/64988/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6670 -> Patchwork_13953
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/
Known issues
Here are the changes found in Patchwork_13953 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@gem_mmap_...@basic-short.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/fi-icl-u3/igt@gem_mmap_...@basic-short.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@i915_selftest@live_reset:
- fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u2/igt@i915_selftest@live_reset.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/fi-icl-u2/igt@i915_selftest@live_reset.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][7] -> [SKIP][8] ([fdo#109271] / [fdo#109278])
+2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
Possible fixes
* igt@gem_cpu_reloc@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@gem_cpu_re...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/fi-icl-u3/igt@gem_cpu_re...@basic.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][11] ([fdo#08]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][13] ([fdo#109380]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (53 -> 46)
--
Additional (1): fi-bsw-n3050
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900
fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6670 -> Patchwork_13953
CI-20190529: 20190529
CI_DRM_6670: dca4867439f21c056afbde56cd4eb241b50f35d4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13953: eb54982251516e5f23026117d322bc483dd9dc06 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
eb5498225151 drm/i915/gtt: disable 2M pages for pre-gen11
861f4ecb4ba5 drm/i915/gtt: enable GTT cache by default
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Some bits from the LMEM series
== Series Details == Series: Some bits from the LMEM series URL : https://patchwork.freedesktop.org/series/64994/ State : warning == Summary == $ dim checkpatch origin/drm-tip 94ffded7068a drm/i915: buddy allocator -:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #30: new file mode 100644 -:457: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #457: FILE: drivers/gpu/drm/i915/i915_buddy.c:423: + if (buddy && (i915_buddy_block_is_free(block) && + i915_buddy_block_is_free(buddy))) total: 0 errors, 1 warnings, 1 checks, 1303 lines checked 891750b1695e drm/i915/blt: don't assume pinned intel_context 2dafb186902e drm/i915/blt: bump the size restriction ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: buddy allocator
Quoting Matthew Auld (2019-08-09 21:29:24)
> +int i915_buddy_alloc_range(struct i915_buddy_mm *mm,
> + struct list_head *blocks,
> + u64 start, u64 size)
> +{
> + struct i915_buddy_block *block;
> + struct i915_buddy_block *buddy;
> + LIST_HEAD(allocated);
> + LIST_HEAD(dfs);
> + u64 end;
> + int err;
> + int i;
> +
> + if (size < mm->chunk_size)
> + return -EINVAL;
> +
> + if (!IS_ALIGNED(start, mm->chunk_size))
> + return -EINVAL;
> +
> + if (!size || !IS_ALIGNED(size, mm->chunk_size))
> + return -EINVAL;
chunk_size can't be 0 and size can't be less than chunk_size, ergo size
is non-zero.
if (!IS_ALIGNED(start | size, mm->chunk_size))
return -EINVAL;
My last brain cell dies happy,
-Chris
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/blt: bump the size restriction
Quoting Matthew Auld (2019-08-09 21:29:26)
> As pointed out by Chris, with our current approach we are actually
> limited to S16_MAX * PAGE_SIZE for our size when using the blt to clear
> pages. Keeping things simple try to fix this by reducing the copy to a
> sequence of S16_MAX * PAGE_SIZE blocks.
>
> Reported-by: Chris Wilson
> Signed-off-by: Matthew Auld
> Cc: Chris Wilson
> ---
> .../gpu/drm/i915/gem/i915_gem_client_blt.c| 31 +++-
> .../gpu/drm/i915/gem/i915_gem_object_blt.c| 139 ++
> .../gpu/drm/i915/gem/i915_gem_object_blt.h| 9 +-
> .../i915/gem/selftests/i915_gem_client_blt.c | 16 +-
> .../i915/gem/selftests/i915_gem_object_blt.c | 22 ++-
> 5 files changed, 170 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> index 08a84c940d8d..4b096309a97e 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
> @@ -5,6 +5,8 @@
>
> #include "i915_drv.h"
> #include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +#include "gt/intel_engine_pool.h"
> #include "i915_gem_client_blt.h"
> #include "i915_gem_object_blt.h"
>
> @@ -156,7 +158,9 @@ static void clear_pages_worker(struct work_struct *work)
> struct drm_i915_private *i915 = w->ce->engine->i915;
> struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
> struct i915_vma *vma = w->sleeve->vma;
> + struct intel_engine_pool_node *pool;
> struct i915_request *rq;
> + struct i915_vma *batch;
> int err = w->dma.error;
>
> if (unlikely(err))
> @@ -176,10 +180,17 @@ static void clear_pages_worker(struct work_struct *work)
> if (unlikely(err))
> goto out_unlock;
>
> + intel_engine_pm_get(w->ce->engine);
> + batch = intel_emit_vma_fill_blt(&pool, w->ce, vma, w->value);
I had to search for where pool was being set!
Hmm, batch is from pool right? So we are the owner of the batch, and we
could set batch->private = pool.
> + if (IS_ERR(batch)) {
> + err = PTR_ERR(batch);
> + goto out_unpin;
> + }
> +
> rq = intel_context_create_request(w->ce);
> if (IS_ERR(rq)) {
> err = PTR_ERR(rq);
> - goto out_unpin;
> + goto out_batch;
> }
>
> /* There's no way the fence has signalled */
> @@ -187,6 +198,16 @@ static void clear_pages_worker(struct work_struct *work)
>clear_pages_dma_fence_cb))
> GEM_BUG_ON(1);
>
> + i915_vma_lock(batch);
> + err = i915_vma_move_to_active(batch, rq, 0);
> + i915_vma_unlock(batch);
> + if (unlikely(err))
> + goto out_request;
> +
> + err = intel_engine_pool_mark_active(pool, rq);
> + if (unlikely(err))
> + goto out_request;
> +
> if (w->ce->engine->emit_init_breadcrumb) {
> err = w->ce->engine->emit_init_breadcrumb(rq);
> if (unlikely(err))
> @@ -202,7 +223,9 @@ static void clear_pages_worker(struct work_struct *work)
> if (err)
> goto out_request;
>
> - err = intel_emit_vma_fill_blt(rq, vma, w->value);
> + err = w->ce->engine->emit_bb_start(rq,
> + batch->node.start,
> batch->node.size,
> + 0);
> out_request:
> if (unlikely(err)) {
> i915_request_skip(rq, err);
> @@ -210,7 +233,11 @@ static void clear_pages_worker(struct work_struct *work)
> }
>
> i915_request_add(rq);
> +out_batch:
> + i915_vma_unpin(batch);
> + intel_engine_pool_put(pool);
> out_unpin:
> + intel_engine_pm_put(w->ce->engine);
> i915_vma_unpin(vma);
> out_unlock:
> mutex_unlock(&i915->drm.struct_mutex);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> index fa90c38c8b07..c1e5edd1e359 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> @@ -5,49 +5,103 @@
>
> #include "i915_drv.h"
> #include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +#include "gt/intel_engine_pool.h"
> +#include "gt/intel_gt.h"
> #include "i915_gem_clflush.h"
> #include "i915_gem_object_blt.h"
>
> -int intel_emit_vma_fill_blt(struct i915_request *rq,
> - struct i915_vma *vma,
> - u32 value)
> +struct i915_vma *intel_emit_vma_fill_blt(struct intel_engine_pool_node **p,
> +struct intel_context *ce,
> +struct i915_vma *vma,
> +u32 value)
> {
> - u32 *cs;
> -
> - cs = intel_ring_begin(rq, 8);
> -
Re: [Intel-gfx] [PATCH 2/3] drm/i915/blt: don't assume pinned intel_context
Quoting Matthew Auld (2019-08-09 21:29:25) > Currently we just pass in bcs0->engine_context so it matters not, but in > the future we may want to pass in something that is not a > kernel_context, so try to be a bit more generic. > > Suggested-by: Chris Wilson > Signed-off-by: Matthew Auld > Cc: Chris Wilson Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/guc: Keep the engine awake until the tasklet is idle
For the guc, we need to keep the engine awake (and not parked) and not just the gt. If we let the engine park, we disable the irq and stop processing the tasklet, leaving state outstanding inside the tasklet. Reported-by: Daniele Ceraolo Spurio Signed-off-by: Chris Wilson Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 8b83750cf96c..577de8639c83 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -539,7 +539,7 @@ static struct i915_request *schedule_in(struct i915_request *rq, int idx) if (!rq->hw_context->inflight) rq->hw_context->inflight = rq->engine; intel_context_inflight_inc(rq->hw_context); - intel_gt_pm_get(rq->engine->gt); + intel_engine_pm_get(rq->engine); return i915_request_get(rq); } @@ -552,7 +552,7 @@ static void schedule_out(struct i915_request *rq) if (!intel_context_inflight_count(rq->hw_context)) rq->hw_context->inflight = NULL; - intel_gt_pm_put(rq->engine->gt); + intel_engine_pm_put(rq->engine); i915_request_put(rq); } -- 2.23.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Push the wakeref->count deferral to the backend
If the backend wishes to defer the wakeref parking, make it responsible
for unlocking the wakeref (i.e. bumping the counter). This allows it to
time the unlock much more carefully in case it happens to needs the
wakeref to be active during its deferral.
For instance, during engine parking we may choose to emit an idle
barrier (a request). To do so, we borrow the engine->kernel_context
timeline and to ensure exclusive access we keep the
engine->wakeref.count as 0. However, to submit that request to HW may
require a intel_engine_pm_get() (e.g. to keep the submission tasklet
alive) and before we allow that we have to rewake our wakeref to avoid a
recursive deadlock.
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +++-
drivers/gpu/drm/i915/i915_request.c | 10 --
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/intel_wakeref.c | 4 +---
4 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 6b15e3335dd6..ca12938d9f8d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -68,9 +68,11 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
/* Check again on the next retirement. */
engine->wakeref_serial = engine->serial + 1;
-
i915_request_add_active_barriers(rq);
+
__i915_request_commit(rq);
+ atomic_inc(&engine->wakeref.count);
+ __i915_request_queue(rq);
return false;
}
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 43175bada09e..3a0760ad56eb 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1186,6 +1186,13 @@ struct i915_request *__i915_request_commit(struct
i915_request *rq)
list_add(&ring->active_link, &rq->i915->gt.active_rings);
rq->emitted_jiffies = jiffies;
+ return prev;
+}
+
+void __i915_request_queue(struct i915_request *rq)
+{
+ struct intel_engine_cs *engine = rq->engine;
+
/*
* Let the backend know a new request has arrived that may need
* to adjust the existing execution schedule due to a high priority
@@ -1230,8 +1237,6 @@ struct i915_request *__i915_request_commit(struct
i915_request *rq)
}
i915_sw_fence_commit(&rq->submit);
local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
-
- return prev;
}
void i915_request_add(struct i915_request *rq)
@@ -1244,6 +1249,7 @@ void i915_request_add(struct i915_request *rq)
trace_i915_request_add(rq);
prev = __i915_request_commit(rq);
+ __i915_request_queue(rq);
/*
* In typical scenarios, we do not expect the previous request on
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 313df3c37158..984c8205a185 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -251,6 +251,7 @@ struct i915_request * __must_check
i915_request_create(struct intel_context *ce);
struct i915_request *__i915_request_commit(struct i915_request *request);
+void __i915_request_queue(struct i915_request *rq);
void i915_request_retire_upto(struct i915_request *rq);
diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
b/drivers/gpu/drm/i915/intel_wakeref.c
index d4443e81c1c8..868cc78048d0 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -57,12 +57,10 @@ static void intel_wakeref_put_last(struct intel_wakeref
*wf)
if (!atomic_dec_and_test(&wf->count))
goto unlock;
+ /* ops->put() must reschedule its own release on error/deferral */
if (likely(!wf->ops->put(wf))) {
rpm_put(wf);
wake_up_var(&wf->wakeref);
- } else {
- /* ops->put() must schedule its own release on deferral */
- atomic_set_release(&wf->count, 1);
}
unlock:
--
2.23.0.rc1
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[Intel-gfx] Plan B
A bit fragile, perhaps? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/blt: don't assume pinned intel_context
Currently we just pass in bcs0->engine_context so it matters not, but in
the future we may want to pass in something that is not a
kernel_context, so try to be a bit more generic.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_client_blt.c | 3 ++-
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index de6616bdb3a6..08a84c940d8d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "gt/intel_context.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
@@ -175,7 +176,7 @@ static void clear_pages_worker(struct work_struct *work)
if (unlikely(err))
goto out_unlock;
- rq = i915_request_create(w->ce);
+ rq = intel_context_create_request(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_unpin;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 837dd6636dd1..fa90c38c8b07 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "gt/intel_context.h"
#include "i915_gem_clflush.h"
#include "i915_gem_object_blt.h"
@@ -64,7 +65,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
i915_gem_object_unlock(obj);
}
- rq = i915_request_create(ce);
+ rq = intel_context_create_request(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_unpin;
--
2.20.1
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[Intel-gfx] [PATCH 0/3] Some bits from the LMEM series
We are going to want the blt improvements and they can go in without everything else. Also the buddy allocator is fairly standalone at this point, and includes a set of selftests(some donated by Chris) and is unlikely to change much. Matthew Auld (3): drm/i915: buddy allocator drm/i915/blt: don't assume pinned intel_context drm/i915/blt: bump the size restriction drivers/gpu/drm/i915/Makefile | 1 + .../gpu/drm/i915/gem/i915_gem_client_blt.c| 34 +- .../gpu/drm/i915/gem/i915_gem_object_blt.c| 142 +++- .../gpu/drm/i915/gem/i915_gem_object_blt.h| 9 +- .../i915/gem/selftests/i915_gem_client_blt.c | 16 +- .../i915/gem/selftests/i915_gem_object_blt.c | 22 +- drivers/gpu/drm/i915/i915_buddy.c | 433 +++ drivers/gpu/drm/i915/i915_buddy.h | 126 +++ drivers/gpu/drm/i915/i915_globals.c | 1 + drivers/gpu/drm/i915/i915_globals.h | 1 + drivers/gpu/drm/i915/selftests/i915_buddy.c | 719 ++ .../drm/i915/selftests/i915_mock_selftests.h | 1 + 12 files changed, 1456 insertions(+), 49 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_buddy.c create mode 100644 drivers/gpu/drm/i915/i915_buddy.h create mode 100644 drivers/gpu/drm/i915/selftests/i915_buddy.c -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: buddy allocator
Simple buddy allocator. We want to allocate properly aligned
power-of-two blocks to promote usage of huge-pages for the GTT, so 64K,
2M and possibly even 1G. While we do support allocating stuff at a
specific offset, it is more intended for preallocating portions of the
address space, say for an initial framebuffer, for other uses drm_mm is
probably a much better fit. Anyway, hopefully this can all be thrown
away if we eventually move to having the core MM manage device memory.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_buddy.c | 433 +++
drivers/gpu/drm/i915/i915_buddy.h | 126 +++
drivers/gpu/drm/i915/i915_globals.c | 1 +
drivers/gpu/drm/i915/i915_globals.h | 1 +
drivers/gpu/drm/i915/selftests/i915_buddy.c | 719 ++
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
7 files changed, 1282 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_buddy.c
create mode 100644 drivers/gpu/drm/i915/i915_buddy.h
create mode 100644 drivers/gpu/drm/i915/selftests/i915_buddy.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d3ca46dc54ae..3962d9728dd7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -126,6 +126,7 @@ gem-y += \
i915-y += \
$(gem-y) \
i915_active.o \
+ i915_buddy.o \
i915_cmd_parser.o \
i915_gem_evict.o \
i915_gem_fence_reg.o \
diff --git a/drivers/gpu/drm/i915/i915_buddy.c
b/drivers/gpu/drm/i915/i915_buddy.c
new file mode 100644
index ..e3039e1273ef
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_buddy.c
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+
+#include "i915_buddy.h"
+
+#include "i915_gem.h"
+#include "i915_globals.h"
+#include "i915_utils.h"
+
+static struct i915_global_block {
+ struct i915_global base;
+ struct kmem_cache *slab_blocks;
+} global;
+
+static void i915_global_buddy_shrink(void)
+{
+ kmem_cache_shrink(global.slab_blocks);
+}
+
+static void i915_global_buddy_exit(void)
+{
+ kmem_cache_destroy(global.slab_blocks);
+}
+
+static struct i915_global_block global = { {
+ .shrink = i915_global_buddy_shrink,
+ .exit = i915_global_buddy_exit,
+} };
+
+int __init i915_global_buddy_init(void)
+{
+ global.slab_blocks = KMEM_CACHE(i915_buddy_block, SLAB_HWCACHE_ALIGN);
+ if (!global.slab_blocks)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static struct i915_buddy_block *i915_block_alloc(struct i915_buddy_block
*parent,
+unsigned int order,
+u64 offset)
+{
+ struct i915_buddy_block *block;
+
+ block = kmem_cache_zalloc(global.slab_blocks, GFP_KERNEL);
+ if (!block)
+ return NULL;
+
+ block->header = offset;
+ block->header |= order;
+ block->parent = parent;
+
+ return block;
+}
+
+static void i915_block_free(struct i915_buddy_block *block)
+{
+ kmem_cache_free(global.slab_blocks, block);
+}
+
+static void mark_allocated(struct i915_buddy_block *block)
+{
+ block->header &= ~I915_BUDDY_HEADER_STATE;
+ block->header |= I915_BUDDY_ALLOCATED;
+
+ list_del(&block->link);
+}
+
+static void mark_free(struct i915_buddy_mm *mm,
+ struct i915_buddy_block *block)
+{
+ block->header &= ~I915_BUDDY_HEADER_STATE;
+ block->header |= I915_BUDDY_FREE;
+
+ list_add(&block->link,
+&mm->free_list[i915_buddy_block_order(block)]);
+}
+
+static void mark_split(struct i915_buddy_block *block)
+{
+ block->header &= ~I915_BUDDY_HEADER_STATE;
+ block->header |= I915_BUDDY_SPLIT;
+
+ list_del(&block->link);
+}
+
+int i915_buddy_init(struct i915_buddy_mm *mm, u64 size, u64 chunk_size)
+{
+ unsigned int i;
+ u64 offset;
+
+ if (size < chunk_size)
+ return -EINVAL;
+
+ if (chunk_size < PAGE_SIZE)
+ return -EINVAL;
+
+ if (!is_power_of_2(chunk_size))
+ return -EINVAL;
+
+ size = round_down(size, chunk_size);
+
+ mm->size = size;
+ mm->chunk_size = chunk_size;
+ mm->max_order = ilog2(size) - ilog2(chunk_size);
+
+ GEM_BUG_ON(mm->max_order > I915_BUDDY_MAX_ORDER);
+
+ mm->free_list = kmalloc_array(mm->max_order + 1,
+ sizeof(struct list_head),
+ GFP_KERNEL);
+ if (!mm->free_list)
+ return -ENOMEM;
+
+ for (i = 0; i <= mm->max_order; ++i)
+ INIT_LIST_HEAD(&mm->free_list[i]);
+
+ mm->n_roots = hweight64(size);
+
+ mm->roots = kmalloc_array(mm->n_roots,
+ sizeof(struct i915_buddy_block *),
+
[Intel-gfx] [PATCH 3/3] drm/i915/blt: bump the size restriction
As pointed out by Chris, with our current approach we are actually
limited to S16_MAX * PAGE_SIZE for our size when using the blt to clear
pages. Keeping things simple try to fix this by reducing the copy to a
sequence of S16_MAX * PAGE_SIZE blocks.
Reported-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 31 +++-
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 139 ++
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 9 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 16 +-
.../i915/gem/selftests/i915_gem_object_blt.c | 22 ++-
5 files changed, 170 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 08a84c940d8d..4b096309a97e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -5,6 +5,8 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
@@ -156,7 +158,9 @@ static void clear_pages_worker(struct work_struct *work)
struct drm_i915_private *i915 = w->ce->engine->i915;
struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
struct i915_vma *vma = w->sleeve->vma;
+ struct intel_engine_pool_node *pool;
struct i915_request *rq;
+ struct i915_vma *batch;
int err = w->dma.error;
if (unlikely(err))
@@ -176,10 +180,17 @@ static void clear_pages_worker(struct work_struct *work)
if (unlikely(err))
goto out_unlock;
+ intel_engine_pm_get(w->ce->engine);
+ batch = intel_emit_vma_fill_blt(&pool, w->ce, vma, w->value);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_unpin;
+ }
+
rq = intel_context_create_request(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- goto out_unpin;
+ goto out_batch;
}
/* There's no way the fence has signalled */
@@ -187,6 +198,16 @@ static void clear_pages_worker(struct work_struct *work)
clear_pages_dma_fence_cb))
GEM_BUG_ON(1);
+ i915_vma_lock(batch);
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (unlikely(err))
+ goto out_request;
+
+ err = intel_engine_pool_mark_active(pool, rq);
+ if (unlikely(err))
+ goto out_request;
+
if (w->ce->engine->emit_init_breadcrumb) {
err = w->ce->engine->emit_init_breadcrumb(rq);
if (unlikely(err))
@@ -202,7 +223,9 @@ static void clear_pages_worker(struct work_struct *work)
if (err)
goto out_request;
- err = intel_emit_vma_fill_blt(rq, vma, w->value);
+ err = w->ce->engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
out_request:
if (unlikely(err)) {
i915_request_skip(rq, err);
@@ -210,7 +233,11 @@ static void clear_pages_worker(struct work_struct *work)
}
i915_request_add(rq);
+out_batch:
+ i915_vma_unpin(batch);
+ intel_engine_pool_put(pool);
out_unpin:
+ intel_engine_pm_put(w->ce->engine);
i915_vma_unpin(vma);
out_unlock:
mutex_unlock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index fa90c38c8b07..c1e5edd1e359 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -5,49 +5,103 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
+#include "gt/intel_gt.h"
#include "i915_gem_clflush.h"
#include "i915_gem_object_blt.h"
-int intel_emit_vma_fill_blt(struct i915_request *rq,
- struct i915_vma *vma,
- u32 value)
+struct i915_vma *intel_emit_vma_fill_blt(struct intel_engine_pool_node **p,
+struct intel_context *ce,
+struct i915_vma *vma,
+u32 value)
{
- u32 *cs;
-
- cs = intel_ring_begin(rq, 8);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- if (INTEL_GEN(rq->i915) >= 8) {
- *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
- *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
- *cs++ = 0;
- *cs++ = vma->size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
-
Re: [Intel-gfx] [PATCH] drm/i915: Remove redundant user_access_end() from __copy_from_user() error path
On Fri, Aug 9, 2019 at 1:03 AM Nick Desaulniers wrote: > > On Thu, Aug 8, 2019 at 1:22 PM Thomas Gleixner wrote: > > > tglx just picked up 2 other patches of mine, bumping just in case he's > > > not picking up patches while on vacation. ;) > > > > I'm only half on vacation :) > > > > So I can pick it up. > > Thanks, will send half margaritas. > Sends some Turkish Cay. - Sedat - ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Stop reconfiguring our shmemfs mountpoint
On Fri, Aug 9, 2019 at 8:52 PM Chris Wilson wrote: > > Quoting Matthew Auld (2019-08-09 19:47:02) > > On Thu, 8 Aug 2019 at 18:23, Chris Wilson wrote: > > > > > > The filesystem reconfigure API is undergoing a transition, breaking our > > > current code. As we only set the default options, we can simply remove > > > the call to s_op->remount_fs(). In the future, when HW permits, we can > > > try re-enabling huge page support, albeit as suggested with new per-file > > > controls. > > > > > > Reported-by: Sergey Senozhatsky > > > Reported-by: Sedat Dilek > > > Suggested-by: Hugh Dickins > > > Signed-off-by: Chris Wilson > > > Cc: Matthew Auld > > > Cc: Hugh Dickins > > > Cc: Al Viro > > > Cc: Sergey Senozhatsky > > Reviewed-by: Matthew Auld > > Thanks, picked up with the s/within/within_size/ fix. > -Chris For the records and followers: [1] https://cgit.freedesktop.org/drm-intel/commit/?h=for-linux-next&id=72e67f04637432f91e4cc5e8e4f7eb4e38461e8e
[Intel-gfx] [PATCH] drm/i915/guc: Keep the engine awake until the tasklet is idle
For the guc, we need to keep the engine awake (and not parked) and not just the gt. If we let the engine park, we disable the irq and stop processing the tasklet, leaving state outstanding inside the tasklet. Reported-by: Daniele Ceraolo Spurio Signed-off-by: Chris Wilson Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 8b83750cf96c..577de8639c83 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -539,7 +539,7 @@ static struct i915_request *schedule_in(struct i915_request *rq, int idx) if (!rq->hw_context->inflight) rq->hw_context->inflight = rq->engine; intel_context_inflight_inc(rq->hw_context); - intel_gt_pm_get(rq->engine->gt); + intel_engine_pm_get(rq->engine); return i915_request_get(rq); } @@ -552,7 +552,7 @@ static void schedule_out(struct i915_request *rq) if (!intel_context_inflight_count(rq->hw_context)) rq->hw_context->inflight = NULL; - intel_gt_pm_put(rq->engine->gt); + intel_engine_pm_put(rq->engine); i915_request_put(rq); } -- 2.23.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: disable 2M pages for pre-gen11
Quoting Matthew Auld (2019-08-09 20:34:56) > We currently disable THP(Transparent-Huge-Pages) for our shmem objects > due to a performance regression with read BW in some internal > benchmarks. Given that this is our main source of 2M pages, there really > isn't much point in enabling 2M GTT pages, especially this that comes at > the cost of disabling the GTT cache. However from gen11 it looks like we > should hopefully see the HW issue resolved. Given this opt for only > enabling 2M GTT pages from gen11 onwards. > > Signed-off-by: Matthew Auld > Cc: Joonas Lahtinen > Cc: Chris Wilson Gone, but not forgotten. Reviewed-by: Chris Wilson Now we just need some time on gen11... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/gtt: enable GTT cache by default
Quoting Matthew Auld (2019-08-09 20:34:55)
> For some platforms the GTT cache is by default not enabled, and
> currently where we explicitly enable it, we make it conditional on 2M GTT
> page support, since the BSpec states that we must disable it if we
> enable 2M/1G pages. To make this more consistent opt for blanket
> enabling the GTT cache for all relevant gens in a single place, while
> still keeping the same behaviour of checking for 2M support.
>
> BSpec: 9314
> BSpec: 423
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +
> drivers/gpu/drm/i915/intel_pm.c | 12
> 2 files changed, 21 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 83a02e773c58..72a227c43e35 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2035,6 +2035,27 @@ static void gtt_write_workarounds(struct intel_gt *gt)
> GEN8_GAMW_ECO_DEV_RW_IA,
> 0,
> GAMW_ECO_ENABLE_64K_IPS_FIELD);
> +
> + if (IS_GEN_RANGE(i915, 8, 11)) {
> + bool can_use_gtt_cache = true;
> +
> + /*
> +* According to the BSpec if we use 2M/1G pages then we also
> +* need to disable the GTT cache. At least on BDW we can see
> +* visual corruption when using 2M pages, and not disabling
> the
> +* GTT cache.
> +*/
> + if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M))
> + can_use_gtt_cache = false;
> +
> + /* WaGttCachingOffByDefault */
> + intel_uncore_write(uncore,
> + HSW_GTT_CACHE_EN,
> + can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
> + WARN_ON_ONCE(can_use_gtt_cache &&
> +intel_uncore_read(uncore,
> + HSW_GTT_CACHE_EN) == 0);
I would opt for GEM_DEBUG_WARN_ON() and adding it to the error state.
This is a much more sensible place.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH 2/2] drm/i915/gtt: disable 2M pages for pre-gen11
We currently disable THP(Transparent-Huge-Pages) for our shmem objects
due to a performance regression with read BW in some internal
benchmarks. Given that this is our main source of 2M pages, there really
isn't much point in enabling 2M GTT pages, especially this that comes at
the cost of disabling the GTT cache. However from gen11 it looks like we
should hopefully see the HW issue resolved. Given this opt for only
enabling 2M GTT pages from gen11 onwards.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1febda2a90e7..1974e4c78a43 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -522,8 +522,6 @@ static const struct intel_device_info
intel_haswell_gt3_info = {
#define GEN8_FEATURES \
G75_FEATURES, \
GEN(8), \
- .page_sizes = I915_GTT_PAGE_SIZE_4K | \
- I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
.ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 48, \
@@ -586,8 +584,7 @@ static const struct intel_device_info intel_cherryview_info
= {
#define GEN9_DEFAULT_PAGE_SIZES \
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
- I915_GTT_PAGE_SIZE_64K | \
- I915_GTT_PAGE_SIZE_2M
+ I915_GTT_PAGE_SIZE_64K
#define GEN9_FEATURES \
GEN8_FEATURES, \
@@ -727,8 +724,14 @@ static const struct intel_device_info
intel_cannonlake_info = {
.gt = 2,
};
+#define GEN11_DEFAULT_PAGE_SIZES \
+ .page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ I915_GTT_PAGE_SIZE_64K | \
+ I915_GTT_PAGE_SIZE_2M
+
#define GEN11_FEATURES \
GEN10_FEATURES, \
+ GEN11_DEFAULT_PAGE_SIZES, \
.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
--
2.20.1
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[Intel-gfx] [PATCH 1/2] drm/i915/gtt: enable GTT cache by default
For some platforms the GTT cache is by default not enabled, and
currently where we explicitly enable it, we make it conditional on 2M GTT
page support, since the BSpec states that we must disable it if we
enable 2M/1G pages. To make this more consistent opt for blanket
enabling the GTT cache for all relevant gens in a single place, while
still keeping the same behaviour of checking for 2M support.
BSpec: 9314
BSpec: 423
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 83a02e773c58..72a227c43e35 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2035,6 +2035,27 @@ static void gtt_write_workarounds(struct intel_gt *gt)
GEN8_GAMW_ECO_DEV_RW_IA,
0,
GAMW_ECO_ENABLE_64K_IPS_FIELD);
+
+ if (IS_GEN_RANGE(i915, 8, 11)) {
+ bool can_use_gtt_cache = true;
+
+ /*
+* According to the BSpec if we use 2M/1G pages then we also
+* need to disable the GTT cache. At least on BDW we can see
+* visual corruption when using 2M pages, and not disabling the
+* GTT cache.
+*/
+ if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M))
+ can_use_gtt_cache = false;
+
+ /* WaGttCachingOffByDefault */
+ intel_uncore_write(uncore,
+ HSW_GTT_CACHE_EN,
+ can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
+ WARN_ON_ONCE(can_use_gtt_cache &&
+intel_uncore_read(uncore,
+ HSW_GTT_CACHE_EN) == 0);
+ }
}
int i915_ppgtt_init_hw(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 780df8db2eba..aca676e79948 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9169,9 +9169,6 @@ static void skl_init_clock_gating(struct drm_i915_private
*dev_priv)
static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
{
- /* The GTT cache must be disabled if the system is using 2M pages. */
- bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
-I915_GTT_PAGE_SIZE_2M);
enum pipe pipe;
/* WaSwitchSolVfFArbitrationPriority:bdw */
@@ -9204,9 +9201,6 @@ static void bdw_init_clock_gating(struct drm_i915_private
*dev_priv)
/* WaProgramL3SqcReg1Default:bdw */
gen8_set_l3sqc_credits(dev_priv, 30, 2);
- /* WaGttCachingOffByDefault:bdw */
- I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
-
/* WaKVMNotificationOnConfigChange:bdw */
I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
| KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
@@ -9471,12 +9465,6 @@ static void chv_init_clock_gating(struct
drm_i915_private *dev_priv)
* LSQC Setting Recommendations.
*/
gen8_set_l3sqc_credits(dev_priv, 38, 2);
-
- /*
-* GTT cache may not work with big pages, so if those
-* are ever enabled GTT cache may need to be disabled.
-*/
- I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
}
static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for DC3CO Support for TGL (rev2)
== Series Details ==
Series: DC3CO Support for TGL (rev2)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6668 -> Patchwork_13952
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/
Known issues
Here are the changes found in Patchwork_13952 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([fdo#108511])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278])
+2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#109485])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_exec_reloc@basic-gtt:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-icl-u3/igt@gem_exec_re...@basic-gtt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-icl-u3/igt@gem_exec_re...@basic-gtt.html
* igt@gem_mmap@basic-small-bo:
- fi-glk-dsi: [INCOMPLETE][11] ([fdo#103359] / [k.org#198133]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-glk-dsi/igt@gem_m...@basic-small-bo.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-glk-dsi/igt@gem_m...@basic-small-bo.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][13] ([fdo#109380]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][15] ([fdo#109485]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][17] ([fdo#102614]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][19] ([fdo#109271]) -> [PASS][20] +23 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: split out uncore_mmio_debug
== Series Details == Series: drm/i915: split out uncore_mmio_debug URL : https://patchwork.freedesktop.org/series/64941/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6661_full -> Patchwork_13931_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13931_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13931_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13931_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live_execlists: - shard-skl: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-skl4/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-skl10/igt@i915_selftest@live_execlists.html Known issues Here are the changes found in Patchwork_13931_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-iclb3/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-iclb1/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-skl9/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-skl1/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-glk2/igt@gem_tiled_swapp...@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-glk6/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-kbl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-kbl1/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-skl2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#109507]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-skl4/igt@kms_f...@flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-skl1/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-apl2/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-apl8/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@plain-flip-ts-check: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#100368]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-skl4/igt@kms_f...@plain-flip-ts-check.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-skl8/igt@kms_f...@plain-flip-ts-check.html * igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-iclb1/igt@kms_frontbuffer_track...@fbc-indfb-scaledprimary.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-iclb4/igt@kms_frontbuffer_track...@fbc-indfb-scaledprimary.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103665]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6661/shard-kbl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13931/shard-kbl1/igt@kms_pl...@pla
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL (rev2)
== Series Details == Series: DC3CO Support for TGL (rev2) URL : https://patchwork.freedesktop.org/series/64923/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/tgl: Add DC3CO required register and bits Okay! Commit: drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Okay! Commit: drm/i915/tgl: Add power well to enable DC3CO state +drivers/gpu/drm/i915/display/intel_display_power.c:813:6: warning: symbol 'bxt_enable_dc9' was not declared. Should it be static? Commit: drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 Okay! Commit: drm/i915/tgl: Add helper function to prefer dc3co over dc5 Okay! Commit: drm/i915/tgl: Add VIDEO power domain Okay! Commit: drm/i915/tgl: DC3CO PSR2 helper +drivers/gpu/drm/i915/display/intel_psr.c:557:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_psr.c:558:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_psr.c:558:23: warning: expression using sizeof(void) Commit: drm/i915/tgl: switch between dc3co and dc5 based on display idleness Okay! Commit: drm/i915/tgl: Add DC3CO counter in i915_dmc_info Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev2)
== Series Details == Series: DC3CO Support for TGL (rev2) URL : https://patchwork.freedesktop.org/series/64923/ State : warning == Summary == $ dim checkpatch origin/drm-tip 15a54f3bbd2d drm/i915/tgl: Add DC3CO required register and bits fdc2aa531791 drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask d3de049eb81d drm/i915/tgl: Add power well to enable DC3CO state -:53: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #53: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:810: + udelay(200); total: 0 errors, 0 warnings, 1 checks, 103 lines checked 33b33a568003 drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 93607c38915a drm/i915/tgl: Add helper function to prefer dc3co over dc5 805147a87236 drm/i915/tgl: Add VIDEO power domain a3fb8832856a drm/i915/tgl: DC3CO PSR2 helper d56b369fa284 drm/i915/tgl: switch between dc3co and dc5 based on display idleness 8658e38e3d18 drm/i915/tgl: Add DC3CO counter in i915_dmc_info ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915: Remove i915_gem_context_create_gvt()
== Series Details == Series: series starting with [CI,1/4] drm/i915: Remove i915_gem_context_create_gvt() URL : https://patchwork.freedesktop.org/series/64985/ State : success == Summary == CI Bug Log - changes from CI_DRM_6668 -> Patchwork_13951 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/ Known issues Here are the changes found in Patchwork_13951 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-icl-u3/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/fi-icl-u3/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [PASS][3] -> [DMESG-FAIL][4] ([fdo#08]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_exec_reloc@basic-gtt: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-icl-u3/igt@gem_exec_re...@basic-gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/fi-icl-u3/igt@gem_exec_re...@basic-gtt.html * igt@gem_mmap@basic-small-bo: - fi-glk-dsi: [INCOMPLETE][9] ([fdo#103359] / [k.org#198133]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-glk-dsi/igt@gem_m...@basic-small-bo.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/fi-glk-dsi/igt@gem_m...@basic-small-bo.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7567u: [FAIL][11] ([fdo#109485]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [DMESG-WARN][13] ([fdo#102614]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (54 -> 47) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6668 -> Patchwork_13951 CI-20190529: 20190529 CI_DRM_6668: 8bb86058e927a93ec2d79fcb48a4ddd752003621 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13951: a1acef6408d4cd8701bf7232ff1ca86bcad9f4b1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a1acef6408d4 drm/i915: Lift timeline into intel_context 78b3f749709f drm/i915: Push the ring creation flags to the backend 2789fe11c56a drm/i915/gt: Make deferred context allocation explicit 56ddb3db5da6 drm/i915: Remove i915_gem_context_create_gvt() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Stop reconfiguring our shmemfs mountpoint
Quoting Matthew Auld (2019-08-09 19:47:02) > On Thu, 8 Aug 2019 at 18:23, Chris Wilson wrote: > > > > The filesystem reconfigure API is undergoing a transition, breaking our > > current code. As we only set the default options, we can simply remove > > the call to s_op->remount_fs(). In the future, when HW permits, we can > > try re-enabling huge page support, albeit as suggested with new per-file > > controls. > > > > Reported-by: Sergey Senozhatsky > > Reported-by: Sedat Dilek > > Suggested-by: Hugh Dickins > > Signed-off-by: Chris Wilson > > Cc: Matthew Auld > > Cc: Hugh Dickins > > Cc: Al Viro > > Cc: Sergey Senozhatsky > Reviewed-by: Matthew Auld Thanks, picked up with the s/within/within_size/ fix. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Stop reconfiguring our shmemfs mountpoint
On Thu, 8 Aug 2019 at 18:23, Chris Wilson wrote: > > The filesystem reconfigure API is undergoing a transition, breaking our > current code. As we only set the default options, we can simply remove > the call to s_op->remount_fs(). In the future, when HW permits, we can > try re-enabling huge page support, albeit as suggested with new per-file > controls. > > Reported-by: Sergey Senozhatsky > Reported-by: Sedat Dilek > Suggested-by: Hugh Dickins > Signed-off-by: Chris Wilson > Cc: Matthew Auld > Cc: Hugh Dickins > Cc: Al Viro > Cc: Sergey Senozhatsky Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bddbbd959d1b..b2b310b4f6dc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2431,6 +2431,12 @@ static int i915_dmc_info(struct seq_file *m, void
*unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
+ /*
+* TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter.
+*/
+ if (IS_TIGERLAKE(dev_priv))
+ seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
if (INTEL_GEN(dev_priv) >= 12) {
dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3e0783ebbbe6..bd91c6fd030f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7280,6 +7280,8 @@ enum {
#define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
#define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
+#define DMC_DEBUG3 _MMIO(0x101090)
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE(1 << 29)
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 0/9] DC3CO Support for TGL
This revision is rebased on latest drm-tip as earlier v4 series had CI failures due to merge conflicts, there are no functional changes with this v5 series. one patch of this series "tgl-DC3CO-PSR2-helper" will require rebase after https://patchwork.freedesktop.org/series/62416/ series will merged to drm-tip. TGL supports DC3CO only on PipeA in LPSP mpde, so DC3CO doesn't depends on TGL PSR "Transcoder B" feature. B.Specs:49196 DC3CO requirements: *Audio codec idle and disabled. *External displays disabled. WD transcoders and DP/HDMI transcoders must be disabled. *Backlight cannot be driven from the display utility pin. It can be driven from the south display. *This feature should be enabled only in Display Video playback on eDP. *DC5 and DC6 not allowed when this feature is enabled. *PSR2 deep sleep disabled (PSR2_CTL Idle Frames = b) *Disable DC3co before mode set, or other Aux, PLL, and DBUF programming, and do not re-enable until after that programming is completed. *DC3co must not be enabled until after PSR2 is enabled. *DC3co must be disabled before PSR2 is disabled. Anshuman Gupta (9): drm/i915/tgl: Add DC3CO required register and bits drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask drm/i915/tgl: Add power well to enable DC3CO state drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 drm/i915/tgl: Add helper function to prefer dc3co over dc5 drm/i915/tgl: Add VIDEO power domain drm/i915/tgl: DC3CO PSR2 helper drm/i915/tgl: switch between dc3co and dc5 based on display idleness drm/i915/tgl: Add DC3CO counter in i915_dmc_info drivers/gpu/drm/i915/display/intel_display.c | 9 + .../drm/i915/display/intel_display_power.c| 291 +- .../drm/i915/display/intel_display_power.h| 11 + drivers/gpu/drm/i915/display/intel_psr.c | 44 +++ drivers/gpu/drm/i915/display/intel_psr.h | 2 + drivers/gpu/drm/i915/i915_debugfs.c | 6 + drivers/gpu/drm/i915/i915_drv.h | 8 + drivers/gpu/drm/i915/i915_params.c| 3 +- drivers/gpu/drm/i915/i915_reg.h | 10 + drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_pm.h | 2 + 11 files changed, 376 insertions(+), 12 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 ++-
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e3bea2b74ce2..e2ef202aeeef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -717,7 +717,11 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
- if (INTEL_GEN(dev_priv) >= 11)
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+ | DC_STATE_EN_DC9;
+ else if (IS_GEN(dev_priv, 11))
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
@@ -3946,14 +3950,17 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
- if (INTEL_GEN(dev_priv) >= 11) {
- max_dc = 2;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
* suspend/resume, so allow it unconditionally.
*/
mask = DC_STATE_EN_DC9;
+ } else if (IS_GEN(dev_priv, 11)) {
+ max_dc = 2;
+ mask = DC_STATE_EN_DC9;
} else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
max_dc = 2;
mask = 0;
@@ -3972,7 +3979,7 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
requested_dc = enable_dc;
} else if (enable_dc == -1) {
requested_dc = max_dc;
- } else if (enable_dc > max_dc && enable_dc <= 2) {
+ } else if (enable_dc > max_dc && enable_dc <= 4) {
DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
enable_dc, max_dc);
requested_dc = max_dc;
@@ -3981,10 +3988,16 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
requested_dc = max_dc;
}
- if (requested_dc > 1)
- mask |= DC_STATE_EN_UPTO_DC6;
- if (requested_dc > 0)
- mask |= DC_STATE_EN_UPTO_DC5;
+ if (requested_dc == 4) {
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+ } else if (requested_dc == 3) {
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+ } else {
+ if (requested_dc > 1)
+ mask |= DC_STATE_EN_UPTO_DC6;
+ if (requested_dc > 0)
+ mask |= DC_STATE_EN_UPTO_DC5;
+ }
DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..4f1806f65040 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
- "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+ "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+ "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
i915_param_named_unsafe(enable_fbc, int, 0600,
"Enable frame buffer compression for power savings "
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
DC5 and DC6 saves more power, but can't be entered during video
playback because there are not enough idle frames in a row to meet
most PSR2 panel deep sleep entry requirement typically 4 frames.
It will be worthy to enable DC3CO after completion of each flip
and switch back to DC5 when display is idle, as driver doesn't
differentiate between video playback and a normal flip.
It is safer to allow DC5 after 6 idle frame, as PSR2 requires
minimum 6 idle frame.
v2: calculated s/w state to switch over dc3co when there is an
update. [Imre]
used cancel_delayed_work_sync() in order to avoid any race
with already scheduled delayed work. [Imre]
v3: cancel_delayed_work_sync() may blocked the commit work.
Hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +
.../drm/i915/display/intel_display_power.c| 77 +++
.../drm/i915/display/intel_display_power.h| 5 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 87 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1ec204c14a10..906a8e6ec9e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14082,6 +14082,8 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET,
wakeref);
}
+
+ tgl_switch_to_dc3co_after_flip(dev_priv);
intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
/*
@@ -16157,6 +16159,7 @@ int intel_modeset_init(struct drm_device *dev)
init_llist_head(&dev_priv->atomic_helper.free_list);
INIT_WORK(&dev_priv->atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
+ INIT_DELAYED_WORK(&dev_priv->csr.idle_work, intel_dc5_idle_thread);
intel_init_quirks(dev_priv);
@@ -17100,6 +17103,7 @@ void intel_modeset_driver_remove(struct drm_device *dev)
flush_workqueue(dev_priv->modeset_wq);
flush_work(&dev_priv->atomic_helper.free_work);
+ flush_delayed_work(&dev_priv->csr.idle_work);
WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2667d205fa36..31d0f389ac17 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,7 @@
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_pm.h"
+#include "intel_psr.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -825,6 +826,46 @@ void tgl_enable_psr2_transcoder_exitline(struct
intel_crtc_state *cstate)
I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
}
+void tgl_switch_to_dc3co_after_flip(struct drm_i915_private *dev_priv)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *cstate;
+ u32 delay;
+
+ if (!dev_priv->csr.prefer_dc3co)
+ return;
+
+ mutex_lock(&dev_priv->psr.lock);
+ if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
+ goto unlock;
+
+ /*
+* As every flip go through intel_atomic_commit, so tracking a
+* atomic commit will be a hint for idle frames.
+* Delayed work for 6 idle frames will be enough to allow dc6
+* over dc3co for deepest power savings.
+* At every atomic commit first cancel the delayed work ,
+* when delayed schedules that means display has been idle
+* for the 6 idle frame.
+*/
+ cancel_delayed_work(&dev_priv->csr.idle_work);
+ mutex_lock(&dev_priv->csr.dc5_mutex);
+ if (!dev_priv->csr.dc5_wakeref) {
+ dev_priv->csr.dc5_wakeref =
+ intel_display_power_get(dev_priv, POWER_DOMAIN_VIDEO);
+ tgl_psr2_deep_sleep_disable(dev_priv);
+ }
+ mutex_unlock(&dev_priv->csr.dc5_mutex);
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ cstate = to_intel_crtc_state(crtc->base.state);
+
+ delay = DC5_REQ_IDLE_FRAMES * intel_get_frame_time_us(cstate);
+ schedule_delayed_work(&dev_priv->csr.idle_work,
+ usecs_to_jiffies(delay));
+unlock:
+ mutex_unlock(&dev_priv->psr.lock);
+}
+
[Intel-gfx] [PATCH v5 7/9] drm/i915/tgl: DC3CO PSR2 helper
Add dc3co helper functions to enable/disable psr2 deep sleep.
Disallow DC3CO state before PSR2 exit, it essentially does
that by putting a reference to POWER_DOMAIN_VIDEO before
PSR2 exit.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 44
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index ad7044ea1efe..42f27df8445d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -533,6 +533,49 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
I915_WRITE(EDP_PSR2_CTL, val);
}
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+ int idle_frames = 0;
+
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL);
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+ int idle_frames;
+
+ /*
+* Let's use 6 as the minimum to cover all known cases including the
+* off-by-one issue that HW has in some cases.
+*/
+ idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+ idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL);
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+{
+ intel_wakeref_t wakeref __maybe_unused;
+
+ /* Before PSR2 exit disallow dc3co*/
+ mutex_lock(&dev_priv->csr.dc5_mutex);
+ wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+ if (wakeref)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO,
+ dev_priv->csr.dc5_wakeref);
+ mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
@@ -789,6 +832,7 @@ static void intel_psr_exit(struct drm_i915_private
*dev_priv)
}
if (dev_priv->psr.psr2_enabled) {
+ tgl_disallow_dc3co_on_psr2_exit(dev_priv);
val = I915_READ(EDP_PSR2_CTL);
WARN_ON(!(val & EDP_PSR2_ENABLE));
I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index dc818826f36d..6fb4c385489c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value);
bool intel_psr_enabled(struct intel_dp *intel_dp);
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PSR_H__ */
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these power domains will disallow
DC3CO when any external displays are connected and at
time of modeset and aux programming.
Renaming "DC Off" power well to "DC5 Off" power well.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 69 ++-
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e2ef202aeeef..c9e92d48cdab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
-static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+* Delay of 200us DC3CO Exit time B.Spec 49196
+*/
+ udelay(200);
+}
+
+void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct
drm_i915_private *dev_priv,
gen9_enable_dc5(dev_priv);
}
+static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ tgl_disallow_dc3co(dev_priv);
+}
+
+static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
+struct i915_power_well *power_well)
+{
+ if (!dev_priv->psr.sink_psr2_support)
+ return;
+
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_allow_dc3co(dev_priv);
+}
+
+static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
+struct i915_power_well *power_well)
+{
+ /*
+* Checking alone DC_STATE_EN is not enough as DC5 power well also
+* allow/disallow DC3CO to make sure both are not enabled at same time
+*/
+ return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
+}
+
static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \
+ TGL_PW_2_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
TGL_PW_2_POWER_DOMAINS |\
BIT_ULL(POWER_DOMAIN_MODESET) | \
@@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops
gen9_dc_off_power_well_ops = {
.is_enabled = gen9_dc_off_power_well_enabled,
};
+static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = tgl_dc3co_power_well_enable,
+ .disable = tgl_dc3co_power_well_disable,
+ .is_enabled = tgl_dc3co_power_well_enabled,
+};
+
static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = bxt_dpio_cmn_power_well_enable,
@@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
},
},
{
- .name = "DC off",
+ .name = "DC5 off",
.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = DISP_PW_ID_NONE,
},
+
[Intel-gfx] [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5
We need to have a S/W flag based upon which driver can switch to DC3CO.
If it is only edp display connected and it has psr2 capability,
then set a prefer_dc3co flag to true, which will be used to
switch to dc3co as well as to program DC3CO PSR2 transcoder
early exitline event.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915/display/intel_display_power.c| 105 ++
.../drm/i915/display/intel_display_power.h| 5 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_pm.h | 2 +
6 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 647f49ca86ff..1ec204c14a10 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6448,6 +6448,9 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
if (WARN_ON(intel_crtc->active))
return;
+ /* Enable PSR2 transcoder exit line */
+ if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
+ tgl_enable_psr2_transcoder_exitline(pipe_config);
intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
@@ -13685,6 +13688,8 @@ static int intel_atomic_check(struct drm_device *dev,
"[modeset]" : "[fastset]");
}
+ tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
+
return 0;
fail:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 167839060154..04a02c88ff93 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -18,6 +18,7 @@
#include "intel_hotplug.h"
#include "intel_sideband.h"
#include "intel_tc.h"
+#include "intel_pm.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -791,6 +792,110 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate)
+{
+ u32 linetime_us, val, exit_scanlines;
+ u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+ if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
+ return;
+
+ linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
+ if (WARN_ON(!linetime_us))
+ return;
+ /*
+* DC3CO Exit time 200us B.Spec 49196
+* PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+* Exit line event need to program above calculated scan lines before
+* next VBLANK.
+*/
+ exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
+ if (WARN_ON(exit_scanlines > crtc_vdisplay))
+ return;
+
+ exit_scanlines = crtc_vdisplay - exit_scanlines;
+ exit_scanlines <<= EXITLINE_SHIFT;
+ val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+ val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+ val |= exit_scanlines;
+ val |= EXITLINE_ENABLE;
+ I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state)
+{
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_connector *connector, *edp_connector = NULL;
+ struct drm_connector_state *connector_state;
+ int i;
+
+ for_each_new_connector_in_state(state, connector, connector_state, i) {
+ if (connector_state->crtc != &crtc->base)
+ continue;
+
+ if (connector->status == connector_status_connected &&
+ connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+ return false;
+ else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
+connector->status == connector_status_connected)
+ edp_connector = connector;
+ }
+
+ if (edp_connector)
+ return true;
+
+ return false;
+}
+
+/*
+ * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
+ * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
+ * edp display should be connected.
+ * TODO: Prefer DC3CO over DC5 only in video playback.
+ */
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+struct intel_atomic_state *state)
+
[Intel-gfx] [PATCH v5 1/9] drm/i915/tgl: Add DC3CO required register and bits
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a947bd0a294..3e0783ebbbe6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4198,6 +4198,7 @@ enum {
#define _VTOTAL_A 0x6000c
#define _VBLANK_A 0x60010
#define _VSYNC_A 0x60014
+#define _EXITLINE_A0x60018
#define _PIPEASRC 0x6001c
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
@@ -4244,11 +4245,16 @@ enum {
#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans)_MMIO_TRANS2(trans, _EXITLINE_A)
#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
+#define EXITLINE_ENABLE (1 << 31)
+#define EXITLINE_MASK (0x1fff)
+#define EXITLINE_SHIFT0
+
/* HSW+ eDP PSR registers */
#define HSW_EDP_PSR_BASE 0x64800
#define BDW_EDP_PSR_BASE 0x6f800
@@ -10040,6 +10046,8 @@ enum skl_power_gate {
/* GEN9 DC */
#define DC_STATE_EN_MMIO(0x45504)
#define DC_STATE_DISABLE 0
+#define DC_STATE_EN_DC3CO (1 << 30)
+#define DC_STATE_DC3CO_STATUS (1 << 29)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
--
2.21.0
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[Intel-gfx] [PATCH v5 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
As per B.Specs DC5 and DC6 not allowed when DC3CO is enabled and DC3CO should be enabled only during VIDEO playback. Which essentially means both can DC5 and DC3CO can not be enabled at same time, it makes DC3CO and DC5 mutual exclusive. Cc: Jani Nikula Cc: Imre Deak Cc: Animesh Manna Cc: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_display_power.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index c9e92d48cdab..167839060154 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -996,6 +996,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + /* DC3CO and DC5/6 are mutually exclusive */ + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO) + tgl_allow_dc3co(dev_priv); + dev_priv->display.get_cdclk(dev_priv, &cdclk_state); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); @@ -1020,6 +1024,10 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, if (!dev_priv->csr.dmc_payload) return; + /* DC3CO and DC5/6 are mutually exclusive */ + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO) + tgl_disallow_dc3co(dev_priv); + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) skl_enable_dc6(dev_priv); else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 6/9] drm/i915/tgl: Add VIDEO power domain
The Power domain name VIDEO is inspired from the fact that
DC3CO should be enabled only during VIDEO playback.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well,
which can disallow DC5/6 and allow DC3CO.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
drivers/gpu/drm/i915/i915_drv.h| 6 ++
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 04a02c88ff93..2667d205fa36 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -122,6 +122,8 @@ intel_display_power_domain_str(struct drm_i915_private
*i915,
return "VGA";
case POWER_DOMAIN_AUDIO:
return "AUDIO";
+ case POWER_DOMAIN_VIDEO:
+ return "VIDEO";
case POWER_DOMAIN_AUX_A:
return "AUX_A";
case POWER_DOMAIN_AUX_B:
@@ -2778,6 +2780,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
TGL_PW_2_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_VIDEO) | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 46e1bcfa490a..7f4dc8bd2ee4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -66,6 +66,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_OTHER,
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO,
+ POWER_DOMAIN_VIDEO,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7ca0703209a4..0a025c692118 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -333,6 +333,12 @@ struct intel_csr {
u32 allowed_dc_mask;
intel_wakeref_t wakeref;
bool prefer_dc3co;
+ intel_wakeref_t dc5_wakeref;
+ /*
+* Mutex to protect dc5_wakeref which make maintain proper
+* power domain reference count of POWER_DOMAIN_VIDEO
+*/
+ struct mutex dc5_mutex;
};
enum i915_cache_level {
--
2.21.0
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[Intel-gfx] [CI 4/4] drm/i915: Lift timeline into intel_context
Move the timeline from being inside the intel_ring to intel_context
itself. This saves much pointer dancing and makes the relations of the
context to its timeline much clearer.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 35 ---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/gt/intel_context.c | 21 +--
drivers/gpu/drm/i915/gt/intel_context.h | 8 +--
drivers/gpu/drm/i915/gt/intel_context_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine.h| 4 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 -
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 33 --
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 63 +--
drivers/gpu/drm/i915/gt/mock_engine.c | 62 +++---
drivers/gpu/drm/i915/gt/selftest_context.c| 2 +-
drivers/gpu/drm/i915/i915_active.c| 6 +-
drivers/gpu/drm/i915/i915_request.c | 10 +--
.../gpu/drm/i915/selftests/i915_gem_evict.c | 19 +++---
15 files changed, 140 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 628d69a4d368..5dbd8989a424 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -489,6 +489,29 @@ static void __assign_ppgtt(struct i915_gem_context *ctx,
i915_vm_put(vm);
}
+static void __set_timeline(struct intel_timeline **dst,
+ struct intel_timeline *src)
+{
+ struct intel_timeline *old = *dst;
+
+ *dst = src ? intel_timeline_get(src) : NULL;
+
+ if (old)
+ intel_timeline_put(old);
+}
+
+static void __apply_timeline(struct intel_context *ce, void *timeline)
+{
+ __set_timeline(&ce->timeline, timeline);
+}
+
+static void __assign_timeline(struct i915_gem_context *ctx,
+ struct intel_timeline *timeline)
+{
+ __set_timeline(&ctx->timeline, timeline);
+ context_apply_all(ctx, __apply_timeline, timeline);
+}
+
static struct i915_gem_context *
i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags)
{
@@ -531,7 +554,8 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
unsigned int flags)
return ERR_CAST(timeline);
}
- ctx->timeline = timeline;
+ __assign_timeline(ctx, timeline);
+ intel_timeline_put(timeline);
}
trace_i915_context_create(ctx);
@@ -1931,13 +1955,8 @@ static int clone_sseu(struct i915_gem_context *dst,
static int clone_timeline(struct i915_gem_context *dst,
struct i915_gem_context *src)
{
- if (src->timeline) {
- GEM_BUG_ON(src->timeline == dst->timeline);
-
- if (dst->timeline)
- intel_timeline_put(dst->timeline);
- dst->timeline = intel_timeline_get(src->timeline);
- }
+ if (src->timeline)
+ __assign_timeline(dst, src->timeline);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 2fa08357944e..1bd2187ac8d6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2182,7 +2182,7 @@ static int eb_pin_context(struct i915_execbuffer *eb,
struct intel_context *ce)
static void eb_unpin_context(struct i915_execbuffer *eb)
{
struct intel_context *ce = eb->context;
- struct intel_timeline *tl = ce->ring->timeline;
+ struct intel_timeline *tl = ce->timeline;
mutex_lock(&tl->mutex);
intel_context_exit(ce);
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 6d1d4e8dbfc9..77833f1558a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -68,7 +68,7 @@ int __intel_context_do_pin(struct intel_context *ce)
goto err;
GEM_TRACE("%s context:%llx pin ring:{head:%04x, tail:%04x}\n",
- ce->engine->name, ce->ring->timeline->fence_context,
+ ce->engine->name, ce->timeline->fence_context,
ce->ring->head, ce->ring->tail);
i915_gem_context_get(ce->gem_context); /* for ctx->ppgtt */
@@ -98,7 +98,7 @@ void intel_context_unpin(struct intel_context *ce)
if (likely(atomic_dec_and_test(&ce->pin_count))) {
GEM_TRACE("%s context:%llx retire\n",
- ce->engine->name, ce->ring->timeline->fence_context);
+ ce->engine->name, ce->timeline->fence_context);
ce->ops->unpin(ce);
@@ -143,11 +143,12 @@ static void __intel_context_reti
[Intel-gfx] [CI 1/4] drm/i915: Remove i915_gem_context_create_gvt()
As we are phasing out using the GEM context for internal clients that
need to manipulate logical context state directly, remove the
constructor for the GVT context. We are not using it for anything other
than default setup and allocation of an i915_ppgtt.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 47 -
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 -
drivers/gpu/drm/i915/gvt/scheduler.c| 22 +++---
3 files changed, 17 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index b407baaf0014..afd994391ad7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -529,53 +529,6 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
unsigned int flags)
return ctx;
}
-/**
- * i915_gem_context_create_gvt - create a GVT GEM context
- * @dev: drm device *
- *
- * This function is used to create a GVT specific GEM context.
- *
- * Returns:
- * pointer to i915_gem_context on success, error pointer if failed
- *
- */
-struct i915_gem_context *
-i915_gem_context_create_gvt(struct drm_device *dev)
-{
- struct i915_gem_context *ctx;
- int ret;
-
- if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
- return ERR_PTR(-ENODEV);
-
- ret = i915_mutex_lock_interruptible(dev);
- if (ret)
- return ERR_PTR(ret);
-
- ctx = i915_gem_create_context(to_i915(dev), 0);
- if (IS_ERR(ctx))
- goto out;
-
- ret = i915_gem_context_pin_hw_id(ctx);
- if (ret) {
- context_close(ctx);
- ctx = ERR_PTR(ret);
- goto out;
- }
-
- ctx->file_priv = ERR_PTR(-EBADF);
- i915_gem_context_set_closed(ctx); /* not user accessible */
- i915_gem_context_clear_bannable(ctx);
- i915_gem_context_set_force_single_submission(ctx);
- if (!USES_GUC_SUBMISSION(to_i915(dev)))
- ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
-
- GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
-out:
- mutex_unlock(&dev->struct_mutex);
- return ctx;
-}
-
static void
destroy_kernel_context(struct i915_gem_context **ctxp)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 106e2ccf7a4c..176978608b6f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -141,8 +141,6 @@ int i915_gem_context_open(struct drm_i915_private *i915,
void i915_gem_context_close(struct drm_file *file);
void i915_gem_context_release(struct kref *ctx_ref);
-struct i915_gem_context *
-i915_gem_context_create_gvt(struct drm_device *dev);
int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 5b29f22dc75a..a38ddb57e786 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1212,19 +1212,28 @@ i915_context_ppgtt_root_save(struct
intel_vgpu_submission *s,
*/
int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
{
+ struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
struct intel_vgpu_submission *s = &vgpu->submission;
struct intel_engine_cs *engine;
struct i915_gem_context *ctx;
enum intel_engine_id i;
int ret;
- ctx = i915_gem_context_create_gvt(&vgpu->gvt->dev_priv->drm);
- if (IS_ERR(ctx))
- return PTR_ERR(ctx);
+ mutex_lock(&i915->drm.struct_mutex);
+
+ ctx = i915_gem_context_create_kernel(i915, I915_PRIORITY_MAX);
+ if (IS_ERR(ctx)) {
+ ret = PTR_ERR(ctx);
+ goto out_unlock;
+ }
+
+ i915_gem_context_set_force_single_submission(ctx);
+ if (!USES_GUC_SUBMISSION(i915))
+ ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
i915_context_ppgtt_root_save(s, i915_vm_to_ppgtt(ctx->vm));
- for_each_engine(engine, vgpu->gvt->dev_priv, i) {
+ for_each_engine(engine, i915, i) {
struct intel_context *ce;
INIT_LIST_HEAD(&s->workload_q_head[i]);
@@ -1262,11 +1271,12 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
i915_gem_context_put(ctx);
+ mutex_unlock(&i915->drm.struct_mutex);
return 0;
out_shadow_ctx:
i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(ctx->vm));
- for_each_engine(engine, vgpu->gvt->dev_priv, i) {
+ for_each_engine(engine, i915, i) {
if (IS_ERR(s->shadow[i]))
break;
@@ -1274,6 +1284,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
intel_context_put(s->shadow
[Intel-gfx] [CI 2/4] drm/i915/gt: Make deferred context allocation explicit
Refactor the backends to handle the deferred context allocation in a
consistent manner, and allow calling it as an explicit first step in
pinning a context for the first time. This should make it easier for
backends to keep track of partially constructed contexts from
initialisation.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_context.c | 8 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 5
drivers/gpu/drm/i915/gt/intel_lrc.c | 29 ---
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 15 --
drivers/gpu/drm/i915/gt/mock_engine.c | 17 +++
5 files changed, 55 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index c8777e222b12..41d38e661de7 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -53,6 +53,14 @@ int __intel_context_do_pin(struct intel_context *ce)
if (likely(!atomic_read(&ce->pin_count))) {
intel_wakeref_t wakeref;
+ if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))) {
+ err = ce->ops->alloc(ce);
+ if (unlikely(err))
+ goto err;
+
+ __set_bit(CONTEXT_ALLOC_BIT, &ce->flags);
+ }
+
err = 0;
with_intel_runtime_pm(&ce->engine->i915->runtime_pm, wakeref)
err = ce->ops->pin(ce);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 68a7e979b1a9..cff6238c213a 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -23,6 +23,8 @@ struct intel_context;
struct intel_ring;
struct intel_context_ops {
+ int (*alloc)(struct intel_context *ce);
+
int (*pin)(struct intel_context *ce);
void (*unpin)(struct intel_context *ce);
@@ -52,6 +54,9 @@ struct intel_context {
struct i915_vma *state;
struct intel_ring *ring;
+ unsigned long flags;
+#define CONTEXT_ALLOC_BIT 0
+
u32 *lrc_reg_state;
u64 lrc_desc;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 14c5bfbe0a74..a986ea87fbd9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -219,8 +219,9 @@ static struct virtual_engine *to_virtual_engine(struct
intel_engine_cs *engine)
return container_of(engine, struct virtual_engine, base);
}
-static int execlists_context_deferred_alloc(struct intel_context *ce,
- struct intel_engine_cs *engine);
+static int __execlists_context_alloc(struct intel_context *ce,
+struct intel_engine_cs *engine);
+
static void execlists_init_reg_state(u32 *reg_state,
struct intel_context *ce,
struct intel_engine_cs *engine,
@@ -1614,9 +1615,6 @@ __execlists_context_pin(struct intel_context *ce,
void *vaddr;
int ret;
- ret = execlists_context_deferred_alloc(ce, engine);
- if (ret)
- goto err;
GEM_BUG_ON(!ce->state);
ret = intel_context_active_acquire(ce);
@@ -1655,6 +1653,11 @@ static int execlists_context_pin(struct intel_context
*ce)
return __execlists_context_pin(ce, ce->engine);
}
+static int execlists_context_alloc(struct intel_context *ce)
+{
+ return __execlists_context_alloc(ce, ce->engine);
+}
+
static void execlists_context_reset(struct intel_context *ce)
{
/*
@@ -1678,6 +1681,8 @@ static void execlists_context_reset(struct intel_context
*ce)
}
static const struct intel_context_ops execlists_context_ops = {
+ .alloc = execlists_context_alloc,
+
.pin = execlists_context_pin,
.unpin = execlists_context_unpin,
@@ -3075,8 +3080,8 @@ get_timeline(struct i915_gem_context *ctx, struct
intel_gt *gt)
return intel_timeline_create(gt, NULL);
}
-static int execlists_context_deferred_alloc(struct intel_context *ce,
- struct intel_engine_cs *engine)
+static int __execlists_context_alloc(struct intel_context *ce,
+struct intel_engine_cs *engine)
{
struct drm_i915_gem_object *ctx_obj;
struct i915_vma *vma;
@@ -3085,9 +3090,7 @@ static int execlists_context_deferred_alloc(struct
intel_context *ce,
struct intel_timeline *timeline;
int ret;
- if (ce->state)
- return 0;
-
+ GEM_BUG_ON(ce->state);
context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
/*
@@ -3533,6 +3536,12 @@ intel_execlists_create_virtual(struct i915_gem_context
*ctx,
ve->base.flags |= I915_ENGIN
[Intel-gfx] [CI 3/4] drm/i915: Push the ring creation flags to the backend
Push the ring creation flags from the outer GEM context to the inner
intel_context to avoid an unsightly back-reference from inside the
backend.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 38 ---
.../gpu/drm/i915/gem/i915_gem_context_types.h | 3 --
drivers/gpu/drm/i915/gt/intel_context.c | 1 +
drivers/gpu/drm/i915/gt/intel_context.h | 5 +++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +--
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 2 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 8 +++-
drivers/gpu/drm/i915/i915_debugfs.c | 23 +++
10 files changed, 58 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index afd994391ad7..628d69a4d368 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -436,8 +436,6 @@ __create_context(struct drm_i915_private *i915)
i915_gem_context_set_bannable(ctx);
i915_gem_context_set_recoverable(ctx);
- ctx->ring_size = 4 * PAGE_SIZE;
-
for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
@@ -448,22 +446,34 @@ __create_context(struct drm_i915_private *i915)
return ERR_PTR(err);
}
+static void
+context_apply_all(struct i915_gem_context *ctx,
+ void (*fn)(struct intel_context *ce, void *data),
+ void *data)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it)
+ fn(ce, data);
+ i915_gem_context_unlock_engines(ctx);
+}
+
+static void __apply_ppgtt(struct intel_context *ce, void *vm)
+{
+ i915_vm_put(ce->vm);
+ ce->vm = i915_vm_get(vm);
+}
+
static struct i915_address_space *
__set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm)
{
struct i915_address_space *old = ctx->vm;
- struct i915_gem_engines_iter it;
- struct intel_context *ce;
GEM_BUG_ON(old && i915_vm_is_4lvl(vm) != i915_vm_is_4lvl(old));
ctx->vm = i915_vm_get(vm);
-
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- i915_vm_put(ce->vm);
- ce->vm = i915_vm_get(vm);
- }
- i915_gem_context_unlock_engines(ctx);
+ context_apply_all(ctx, __apply_ppgtt, vm);
return old;
}
@@ -560,7 +570,6 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
i915_gem_context_clear_bannable(ctx);
ctx->sched.priority = I915_USER_PRIORITY(prio);
- ctx->ring_size = PAGE_SIZE;
GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
@@ -1544,6 +1553,7 @@ set_engines(struct i915_gem_context *ctx,
for (n = 0; n < num_engines; n++) {
struct i915_engine_class_instance ci;
struct intel_engine_cs *engine;
+ struct intel_context *ce;
if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) {
__free_engines(set.engines, n);
@@ -1566,11 +1576,13 @@ set_engines(struct i915_gem_context *ctx,
return -ENOENT;
}
- set.engines->engines[n] = intel_context_create(ctx, engine);
- if (!set.engines->engines[n]) {
+ ce = intel_context_create(ctx, engine);
+ if (!ce) {
__free_engines(set.engines, n);
return -ENOMEM;
}
+
+ set.engines->engines[n] = ce;
}
set.engines->num_engines = num_engines;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index a02d98494078..260d59cc3de8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -169,9 +169,6 @@ struct i915_gem_context {
struct i915_sched_attr sched;
- /** ring_size: size for allocating the per-engine ring buffer */
- u32 ring_size;
-
/** guilty_count: How many times this context has caused a GPU hang. */
atomic_t guilty_count;
/**
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 41d38e661de7..6d1d4e8dbfc9 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -222,6 +222,7 @@ intel_context_init(struct intel_context *ce,
ce->engine = engine;
ce->ops = engine->cops;
ce->sseu = engine->sseu;
+ ce->ring = __intel_context_ring_size(SZ_16K);
INIT_LIST_HEAD(&ce->signal_link);
INIT_L
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Remove i915_gem_context_create_gvt() (rev2)
== Series Details ==
Series: series starting with [1/4] drm/i915: Remove
i915_gem_context_create_gvt() (rev2)
URL : https://patchwork.freedesktop.org/series/64979/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6668 -> Patchwork_13950
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/
Known issues
Here are the changes found in Patchwork_13950 that come from known issues:
### IGT changes ###
Issues hit
* igt@vgem_basic@debugfs:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-icl-u3/igt@vgem_ba...@debugfs.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/fi-icl-u3/igt@vgem_ba...@debugfs.html
Possible fixes
* igt@gem_exec_reloc@basic-gtt:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4] +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-icl-u3/igt@gem_exec_re...@basic-gtt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/fi-icl-u3/igt@gem_exec_re...@basic-gtt.html
* igt@gem_mmap@basic-small-bo:
- fi-glk-dsi: [INCOMPLETE][5] ([fdo#103359] / [k.org#198133]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-glk-dsi/igt@gem_m...@basic-small-bo.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/fi-glk-dsi/igt@gem_m...@basic-small-bo.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][7] ([fdo#109380]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][9] ([fdo#109485]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][11] ([fdo#102614]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (54 -> 46)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6668 -> Patchwork_13950
CI-20190529: 20190529
CI_DRM_6668: 8bb86058e927a93ec2d79fcb48a4ddd752003621 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13950: 18818bb6d47162b177f1d89c6c5f1ba9c9883208 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
18818bb6d471 drm/i915: Lift timeline into intel_context
759341886bf9 drm/i915: Push the ring creation flags to the backend
ed054ca50622 drm/i915/gt: Make deferred context allocation explicit
03f58d17688d drm/i915: Remove i915_gem_context_create_
