Re: [Intel-gfx] [PATCH v3 03/37] drm/i915/region: support basic eviction
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Chris Wilson
> Sent: Saturday, August 10, 2019 3:19 AM
> To: Auld, Matthew ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v3 03/37] drm/i915/region: support basic
> eviction
>
> Quoting Matthew Auld (2019-08-09 23:26:09)
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c index 6ff01a404346..8735dea74809
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -1105,6 +1105,23 @@ i915_gem_madvise_ioctl(struct drm_device
> *dev, void *data,
> > !i915_gem_object_has_pages(obj))
> > i915_gem_object_truncate(obj);
> >
> > + if (obj->mm.region) {
> > + mutex_lock(&obj->mm.region->obj_lock);
> > +
> > + switch (obj->mm.madv) {
> > + case I915_MADV_WILLNEED:
> > + list_move(&obj->mm.region_link,
> > + &obj->mm.region->objects);
> > + break;
> > + default:
> > + list_move(&obj->mm.region_link,
> > + &obj->mm.region->purgeable);
> > + break;
> > + }
> > +
> > + mutex_unlock(&obj->mm.region->obj_lock);
> > + }
> > +
> > args->retained = obj->mm.madv != __I915_MADV_PURGED;
>
> Little bit of an impedance mismatch, I hope this turns out fine when
> everything is a memory region.
>
> > mutex_unlock(&obj->mm.lock);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
> > b/drivers/gpu/drm/i915/intel_memory_region.c
> > index ef12e462acb8..3a3caaadea1f 100644
> > --- a/drivers/gpu/drm/i915/intel_memory_region.c
> > +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> > @@ -12,6 +12,51 @@ const u32 intel_region_map[] = {
> > [INTEL_MEMORY_STOLEN] = BIT(INTEL_STOLEN +
> > INTEL_MEMORY_TYPE_SHIFT) | BIT(0), };
> >
> > +static int
> > +intel_memory_region_evict(struct intel_memory_region *mem,
> > + resource_size_t target,
> > + unsigned int flags) {
> > + struct drm_i915_gem_object *obj;
> > + resource_size_t found;
> > + int err;
> > +
> > + err = 0;
> > + found = 0;
> > +
> > + mutex_lock(&mem->obj_lock);
> > + list_for_each_entry(obj, &mem->purgeable, mm.region_link) {
> > + if (!i915_gem_object_has_pages(obj))
> > + continue;
> > +
> > + if (READ_ONCE(obj->pin_global))
> > + continue;
> > +
> > + if (atomic_read(&obj->bind_count))
> > + continue;
> > +
> > + mutex_unlock(&mem->obj_lock);
> > +
> > + __i915_gem_object_put_pages(obj, I915_MM_SHRINKER);
>
> So we don't really care about the object being bound then? As all we care
> about is the page's pin_count.
>
> So instead of obj->pin_global, obj->bind_bound, you just want
>
> if (atomic_read(&obj->pages.pin_count))
> continue;
>
> as the quick check to see if it is worth preceding.
>
> > + mutex_lock_nested(&obj->mm.lock, I915_MM_SHRINKER);
> > + if (!i915_gem_object_has_pages(obj)) {
> > + obj->mm.madv = __I915_MADV_PURGED;
> > + found += obj->base.size;
> > + }
> > + mutex_unlock(&obj->mm.lock);
>
> The locking here accomplishes what? You just want a boolean from
> put_pages().
I have the same question. But looked the i915_gem_shrink() function, it has
similar code. Do we prevent any race condition here?
I want to use this function for swapping so hope to understand more.
--CQ
>
> > +
> > + if (found >= target)
> > + return 0;
> > +
> > + mutex_lock(&mem->obj_lock);
> > + }
> > +
> > + err = -ENOSPC;
> > + mutex_unlock(&mem->obj_lock);
> > + return err;
> > +}
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: move gpu-write-dw into utils
== Series Details == Series: drm/i915/selftests: move gpu-write-dw into utils URL : https://patchwork.freedesktop.org/series/65013/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6672_full -> Patchwork_13960_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13960_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13960_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13960_full: ### IGT changes ### Possible regressions * igt@i915_pm_rps@reset: - shard-hsw: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-hsw1/igt@i915_pm_...@reset.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-hsw2/igt@i915_pm_...@reset.html * igt@i915_selftest@live_execlists: - shard-skl: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-skl1/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-skl3/igt@i915_selftest@live_execlists.html Known issues Here are the changes found in Patchwork_13960_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110841]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_flush@basic-wb-rw-default: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-iclb2/igt@gem_exec_fl...@basic-wb-rw-default.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-iclb7/igt@gem_exec_fl...@basic-wb-rw-default.html * igt@gem_exec_schedule@preempt-contexts-bsd2: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +11 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-iclb1/igt@gem_exec_sched...@preempt-contexts-bsd2.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-iclb7/igt@gem_exec_sched...@preempt-contexts-bsd2.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#111325]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-iclb5/igt@gem_exec_sched...@reorder-wide-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108686]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-apl4/igt@gem_tiled_swapp...@non-threaded.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-apl7/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-apl7/igt@gem_workarou...@suspend-resume-context.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-apl7/igt@gem_workarou...@suspend-resume-context.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#105363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-skl2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-skl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-panning-vs-hang: - shard-snb: [PASS][19] -> [INCOMPLETE][20] ([fdo#105411]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-snb7/igt@kms_f...@flip-vs-panning-vs-hang.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-snb1/igt@kms_f...@flip-vs-panning-vs-hang.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#109507]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/shard-skl1/igt@kms_f...@flip-vs-suspend-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/shard-skl9/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - s
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915/blt: don't assume pinned intel_context (rev2)
== Series Details == Series: series starting with [CI,1/2] drm/i915/blt: don't assume pinned intel_context (rev2) URL : https://patchwork.freedesktop.org/series/65008/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6670_full -> Patchwork_13959_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13959_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13959_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13959_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live_execlists: - shard-skl: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl4/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-skl1/igt@i915_selftest@live_execlists.html Known issues Here are the changes found in Patchwork_13959_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb3/igt@gem_exec_as...@concurrent-writes-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#108569]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb7/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-iclb4/igt@i915_selftest@live_hangcheck.html * igt@kms_big_fb@linear-32bpp-rotate-0: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-snb2/igt@kms_big...@linear-32bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-snb2/igt@kms_big...@linear-32bpp-rotate-0.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103184] / [fdo#103232] / [fdo#108472]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl5/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-skl5/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-untiled.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl6/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-kbl2/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-kbl6/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/shard-skl6/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_suspend: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DR
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Push the wakeref->count deferral to the backend
== Series Details == Series: series starting with [1/2] drm/i915: Push the wakeref->count deferral to the backend URL : https://patchwork.freedesktop.org/series/64995/ State : success == Summary == CI Bug Log - changes from CI_DRM_6670_full -> Patchwork_13956_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13956_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-range-active: - shard-skl: [PASS][1] -> [DMESG-WARN][2] ([fdo#106107]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl7/igt@gem_exec_re...@basic-range-active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-skl5/igt@gem_exec_re...@basic-range-active.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb5/igt@gem_exec_sched...@reorder-wide-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-kbl6/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-kbl3/igt@gem_soft...@noreloc-s3.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-apl5/igt@gem_workarou...@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-apl8/igt@gem_workarou...@suspend-resume-context.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#109507]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl2/igt@kms_f...@flip-vs-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-skl10/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#100368]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl6/igt@kms_f...@plain-flip-ts-check-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-skl4/igt@kms_f...@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-msflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-msflip-blt.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb8/igt@kms_plane_low...@pipe-a-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-iclb5/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_suspend: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb2/igt@kms_psr@psr2_suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-iclb3/igt@kms_psr@psr2_suspend.html * igt@perf@blocking: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#110728]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl6/igt@p...@blocking.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-skl4/igt@p...@blocking.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109276]) +18 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb1/igt@prime_v...@fence-wait-bsd2.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13956/shard-iclb6/igt@prime_v...@fence-wait-bsd2.html Possible fixes * igt@gem_ctx_isolation@bcs0-s3: - shard-kbl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +1 similar issue [25]: https://intel-gfx-ci.0
[Intel-gfx] ✓ Fi.CI.IGT: success for Some bits from the LMEM series
== Series Details == Series: Some bits from the LMEM series URL : https://patchwork.freedesktop.org/series/64994/ State : success == Summary == CI Bug Log - changes from CI_DRM_6670_full -> Patchwork_13955_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_6670_full and Patchwork_13955_full: ### New IGT tests (1) ### * igt@i915_selftest@mock_buddy: - Statuses : 7 pass(s) - Exec time: [0.10, 22.81] s Known issues Here are the changes found in Patchwork_13955_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb5/igt@gem_exec_sched...@reorder-wide-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-apl8/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-kbl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-kbl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([fdo#105541]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl1/igt@kms_cursor_leg...@long-nonblocking-modeset-vs-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-skl7/igt@kms_cursor_leg...@long-nonblocking-modeset-vs-cursor-atomic.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl6/igt@kms_f...@flip-vs-expired-vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#103060]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-glk2/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-glk2/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb4/igt@kms_f...@plain-flip-ts-check-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-iclb7/igt@kms_f...@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#104108]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl10/igt@kms_frontbuffer_track...@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-skl10/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-skl6/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13955/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_cpu.html * igt@kms_vblank@pipe-a-accuracy-idle:
Re: [Intel-gfx] [PATCH 4/4] dma-buf: nuke reservation_object seq number
Am 07.08.19 um 16:17 schrieb Chris Wilson:
Quoting Christian König (2019-08-07 14:53:12)
The only remaining use for this is to protect against setting a new exclusive
fence while we grab both exclusive and shared. That can also be archived by
looking if the exclusive fence has changed or not after completing the
operation.
v2: switch setting excl fence to rcu_assign_pointer
Signed-off-by: Christian König
---
drivers/dma-buf/reservation.c | 24 +---
include/linux/reservation.h | 9 ++---
2 files changed, 7 insertions(+), 26 deletions(-)
diff --git a/drivers/dma-buf/reservation.c b/drivers/dma-buf/reservation.c
index 90bc6ef03598..f7f4a0858c2a 100644
--- a/drivers/dma-buf/reservation.c
+++ b/drivers/dma-buf/reservation.c
@@ -49,12 +49,6 @@
DEFINE_WD_CLASS(reservation_ww_class);
EXPORT_SYMBOL(reservation_ww_class);
-struct lock_class_key reservation_seqcount_class;
-EXPORT_SYMBOL(reservation_seqcount_class);
-
-const char reservation_seqcount_string[] = "reservation_seqcount";
-EXPORT_SYMBOL(reservation_seqcount_string);
-
/**
* reservation_object_list_alloc - allocate fence list
* @shared_max: number of fences we need space for
@@ -103,9 +97,6 @@ static void reservation_object_list_free(struct
reservation_object_list *list)
void reservation_object_init(struct reservation_object *obj)
{
ww_mutex_init(&obj->lock, &reservation_ww_class);
-
- __seqcount_init(&obj->seq, reservation_seqcount_string,
- &reservation_seqcount_class);
RCU_INIT_POINTER(obj->fence, NULL);
RCU_INIT_POINTER(obj->fence_excl, NULL);
}
@@ -282,12 +273,10 @@ void reservation_object_add_excl_fence(struct
reservation_object *obj,
dma_fence_get(fence);
preempt_disable();
- write_seqcount_begin(&obj->seq);
- /* write_seqcount_begin provides the necessary memory barrier */
- RCU_INIT_POINTER(obj->fence_excl, fence);
+ rcu_assign_pointer(obj->fence_excl, fence);
+ /* pointer update must be visible before we modify the shared_count */
if (old)
- old->shared_count = 0;
- write_seqcount_end(&obj->seq);
+ smp_store_mb(old->shared_count, 0);
preempt_enable();
/* inplace update, no shared fences */
@@ -368,11 +357,8 @@ int reservation_object_copy_fences(struct
reservation_object *dst,
old = reservation_object_get_excl(dst);
preempt_disable();
- write_seqcount_begin(&dst->seq);
- /* write_seqcount_begin provides the necessary memory barrier */
- RCU_INIT_POINTER(dst->fence_excl, new);
- RCU_INIT_POINTER(dst->fence, dst_list);
- write_seqcount_end(&dst->seq);
+ rcu_assign_pointer(dst->fence_excl, new);
+ rcu_assign_pointer(dst->fence, dst_list);
preempt_enable();
reservation_object_list_free(src_list);
diff --git a/include/linux/reservation.h b/include/linux/reservation.h
index 044a5cd4af50..fd29baad0be3 100644
--- a/include/linux/reservation.h
+++ b/include/linux/reservation.h
@@ -46,8 +46,6 @@
#include
extern struct ww_class reservation_ww_class;
-extern struct lock_class_key reservation_seqcount_class;
-extern const char reservation_seqcount_string[];
/**
* struct reservation_object_list - a list of shared fences
@@ -71,7 +69,6 @@ struct reservation_object_list {
*/
struct reservation_object {
struct ww_mutex lock;
- seqcount_t seq;
struct dma_fence __rcu *fence_excl;
struct reservation_object_list __rcu *fence;
@@ -156,14 +153,12 @@ reservation_object_fences(struct reservation_object *obj,
struct reservation_object_list **list,
u32 *shared_count)
{
- unsigned int seq;
-
do {
- seq = read_seqcount_begin(&obj->seq);
*excl = rcu_dereference(obj->fence_excl);
*list = rcu_dereference(obj->fence);
*shared_count = *list ? (*list)->shared_count : 0;
- } while (read_seqcount_retry(&obj->seq, seq));
+ smp_rmb(); /* See reservation_object_add_excl_fence */
+ } while (rcu_access_pointer(obj->fence_excl) != *excl);
}
Reviewed-by: Chris Wilson
I think this is correct. Now see if we can convince Daniel!
Daniel any objections to this? IGTs look good as well, so if not I'm
going to push it.
Christian.
-Chris
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Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
Souza, Jose schreef op vr 09-08-2019 om 17:16 [+]: > Fix released on Linux 5.2.8 Linux 5.2.8 doesn't have the pretty obvious freezes so this fix works for me too. Thanks for letting me know! Paul Bolle
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Keep the engine awake until the tasklet is idle
== Series Details == Series: drm/i915/guc: Keep the engine awake until the tasklet is idle URL : https://patchwork.freedesktop.org/series/64992/ State : success == Summary == CI Bug Log - changes from CI_DRM_6670_full -> Patchwork_13954_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13954_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb3/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-iclb2/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108686]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-apl4/igt@gem_tiled_swapp...@non-threaded.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-apl1/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-apl5/igt@gem_workarou...@suspend-resume-context.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-apl6/igt@gem_workarou...@suspend-resume-context.html * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb3/igt@kms_b...@extended-modeset-hang-newfb-render-a.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-iclb7/igt@kms_b...@extended-modeset-hang-newfb-render-a.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][9] -> [FAIL][10] ([fdo#105767]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([fdo#106107]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl1/igt@kms_fbcon_...@psr-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-skl5/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip@modeset-vs-vblank-race: - shard-snb: [PASS][13] -> [FAIL][14] ([fdo#103060]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-snb2/igt@kms_f...@modeset-vs-vblank-race.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-snb7/igt@kms_f...@modeset-vs-vblank-race.html * igt@kms_flip@plain-flip-fb-recreate: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#100368]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl7/igt@kms_f...@plain-flip-fb-recreate.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-skl2/igt@kms_f...@plain-flip-fb-recreate.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-kbl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-kbl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-skl4/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_suspend: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb2/igt@kms_psr@psr2_suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-iclb3/igt@kms_psr@psr2_suspend.html * igt@perf@blocking: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#110728]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl6/igt@p...@blocking.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13954/shard-skl3/igt@p...@blocking.html * igt@perf@short-reads: - shard-glk: [PASS][25] -> [FAIL][26]
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Prevent the timeslice expiring during suppression tests
== Series Details ==
Series: drm/i915/selftests: Prevent the timeslice expiring during suppression
tests
URL : https://patchwork.freedesktop.org/series/65032/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6675 -> Patchwork_13964
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/
Known issues
Here are the changes found in Patchwork_13964 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_cpu_reloc@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-icl-u3/igt@gem_cpu_re...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-icl-u3/igt@gem_cpu_re...@basic.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [PASS][3] -> [WARN][4] ([fdo#109380])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-kbl-7567u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [PASS][7] -> [SKIP][8] ([fdo#109271]) +23 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-kbl-7567u/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-ilk-650: [DMESG-WARN][9] ([fdo#106387]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-ilk-650/igt@debugfs_test@read_all_entries.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-ilk-650/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_reloc@basic-cpu-read-noreloc:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-icl-u3/igt@gem_exec_re...@basic-cpu-read-noreloc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-icl-u3/igt@gem_exec_re...@basic-cpu-read-noreloc.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [SKIP][13] ([fdo#109271] / [fdo#109278]) ->
[PASS][14] +2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#109485]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [SKIP][17] ([fdo#109271]) -> [PASS][18] +23 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][19] ([fdo#102505] / [fdo#110390]) ->
[FAIL][20] ([fdo#109483])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13964/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=1103
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gtt: enable GTT cache by default
== Series Details == Series: series starting with [1/2] drm/i915/gtt: enable GTT cache by default URL : https://patchwork.freedesktop.org/series/64988/ State : success == Summary == CI Bug Log - changes from CI_DRM_6670_full -> Patchwork_13953_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13953_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-gtt-cpu-active: - shard-skl: [PASS][1] -> [DMESG-WARN][2] ([fdo#106107]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl10/igt@gem_exec_re...@basic-gtt-cpu-active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-skl9/igt@gem_exec_re...@basic-gtt-cpu-active.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb5/igt@gem_exec_sched...@reorder-wide-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-apl5/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-apl2/igt@gem_soft...@noreloc-s3.html - shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103665]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-kbl6/igt@gem_soft...@noreloc-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-kbl4/igt@gem_soft...@noreloc-s3.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-kbl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-kbl1/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103184] / [fdo#103232] / [fdo#108472]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl5/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-skl1/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-untiled.html * igt@kms_flip@2x-flip-vs-suspend-interruptible: - shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-hsw6/igt@kms_f...@2x-flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-hsw2/igt@kms_f...@2x-flip-vs-suspend-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#105363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-skl8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-skl3/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-skl10/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr@psr2_suspend: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-iclb2/igt@kms_psr@psr2_suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-iclb3/igt@kms_psr@psr2_suspend.html * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: - shard-snb: [PASS][23] -> [SKIP][24] ([fdo#109271]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/shard-snb4/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13953/shard-snb2/igt@kms_vbl...@pipe-b-ts-continuati
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/blt: support copying objects
== Series Details == Series: drm/i915/blt: support copying objects URL : https://patchwork.freedesktop.org/series/65031/ State : success == Summary == CI Bug Log - changes from CI_DRM_6675 -> Patchwork_13963 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13963/ Known issues Here are the changes found in Patchwork_13963 that come from known issues: ### IGT changes ### Issues hit * igt@gem_flink_basic@basic: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-icl-u3/igt@gem_flink_ba...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13963/fi-icl-u3/igt@gem_flink_ba...@basic.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-ilk-650: [DMESG-WARN][3] ([fdo#106387]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-ilk-650/igt@debugfs_test@read_all_entries.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13963/fi-ilk-650/igt@debugfs_test@read_all_entries.html * igt@gem_exec_reloc@basic-cpu-read-noreloc: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-icl-u3/igt@gem_exec_re...@basic-cpu-read-noreloc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13963/fi-icl-u3/igt@gem_exec_re...@basic-cpu-read-noreloc.html * igt@kms_busy@basic-flip-c: - fi-kbl-7500u: [SKIP][7] ([fdo#109271] / [fdo#109278]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13963/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13963/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-fence-flip: - fi-kbl-7500u: [SKIP][11] ([fdo#109271]) -> [PASS][12] +23 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13963/fi-kbl-7500u/igt@prime_v...@basic-fence-flip.html [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 Participating hosts (54 -> 47) -- Additional (1): fi-pnv-d510 Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6675 -> Patchwork_13963 CI-20190529: 20190529 CI_DRM_6675: cfacb6e14c0b7fc929565f9876f204e325a71b13 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13963: ec83ea1eb4509fd34205a020f4a4b19baf35893b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ec83ea1eb450 drm/i915/blt: support copying objects == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13963/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/blt: support copying objects
== Series Details == Series: drm/i915/blt: support copying objects URL : https://patchwork.freedesktop.org/series/65031/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/blt: support copying objects +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:232:24: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:232:24: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:120:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:120:26: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/blt: support copying objects
== Series Details == Series: drm/i915/blt: support copying objects URL : https://patchwork.freedesktop.org/series/65031/ State : warning == Summary == $ dim checkpatch origin/drm-tip ec83ea1eb450 drm/i915/blt: support copying objects -:14: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Abdiel Janulgue https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Prevent the timeslice expiring during suppression tests
When testing whether we prevent suppressing preemption, it helps to
avoid a time slice expiring prematurely.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=08
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 91f1c9012489..b797be1627e9 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -913,6 +913,8 @@ static int live_suppress_self_preempt(void *arg)
goto err_wedged;
}
+ /* Keep postponing the timer to avoid premature slicing */
+ mod_timer(&engine->execlists.timer, jiffies + HZ);
for (depth = 0; depth < 8; depth++) {
rq_b = spinner_create_request(&b.spin,
b.ctx, engine,
@@ -938,7 +940,8 @@ static int live_suppress_self_preempt(void *arg)
igt_spinner_end(&a.spin);
if (engine->execlists.preempt_hang.count) {
- pr_err("Preemption recorded x%d, depth %d; should have
been suppressed!\n",
+ pr_err("Preemption on %s recorded x%d, depth %d; should
have been suppressed!\n",
+ engine->name,
engine->execlists.preempt_hang.count,
depth);
err = -EINVAL;
--
2.23.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/blt: support copying objects
From: Matthew Auld
We can already clear an object with the blt, so try to do the same to
support copying from one object backing store to another. Really this is
just object -> object, which is not that useful yet, what we really want
is two backing stores, but that will require some vma rework first,
otherwise we are stuck with "tmp" objects.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue engine->pool, size);
- if (IS_ERR(pool))
+ if (IS_ERR(pool)) {
+ err = PTR_ERR(pool);
goto out_pm;
+ }
cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC);
if (IS_ERR(cmd)) {
@@ -189,6 +191,207 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object
*obj,
return err;
}
+struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
+struct i915_vma *src,
+struct i915_vma *dst)
+{
+ struct drm_i915_private *i915 = ce->vm->i915;
+ const u32 block_size = S16_MAX * PAGE_SIZE;
+ struct intel_engine_pool_node *pool;
+ struct i915_vma *batch;
+ u64 src_offset, dst_offset;
+ u64 count, rem;
+ u32 size, *cmd;
+ int err;
+
+ GEM_BUG_ON(src->size != dst->size);
+
+ GEM_BUG_ON(intel_engine_is_virtual(ce->engine));
+ intel_engine_pm_get(ce->engine);
+
+ count = div_u64(dst->size, block_size);
+ size = (1 + 11 * count) * sizeof(u32);
+ size = round_up(size, PAGE_SIZE);
+ pool = intel_engine_pool_get(&ce->engine->pool, size);
+ if (IS_ERR(pool)) {
+ err = PTR_ERR(pool);
+ goto out_pm;
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto out_put;
+ }
+
+ rem = src->size;
+ src_offset = src->node.start;
+ dst_offset = dst->node.start;
+
+ do {
+ size = min_t(u64, rem, block_size);
+ GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
+
+ if (INTEL_GEN(i915) >= 9) {
+ *cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
+ *cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = lower_32_bits(dst_offset);
+ *cmd++ = upper_32_bits(dst_offset);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src_offset);
+ *cmd++ = upper_32_bits(src_offset);
+ } else if (INTEL_GEN(i915) >= 8) {
+ *cmd++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 -
2);
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = lower_32_bits(dst_offset);
+ *cmd++ = upper_32_bits(dst_offset);
+ *cmd++ = 0;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = lower_32_bits(src_offset);
+ *cmd++ = upper_32_bits(src_offset);
+ } else {
+ *cmd++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE;
+ *cmd++ = dst_offset;
+ *cmd++ = PAGE_SIZE;
+ *cmd++ = src_offset;
+ }
+
+ /* Allow ourselves to be preempted in between blocks. */
+ *cmd++ = MI_ARB_CHECK;
+
+ src_offset += size;
+ dst_offset += size;
+ rem -= size;
+ } while (rem);
+
+ *cmd = MI_BATCH_BUFFER_END;
+ intel_gt_chipset_flush(ce->vm->gt);
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_put;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (unlikely(err))
+ goto out_put;
+
+ batch->private = pool;
+ return batch;
+
+out_put:
+ intel_engine_pool_put(pool);
+out_pm:
+ intel_engine_pm_put(ce->engine);
+ return ERR_PTR(err);
+}
+
+static int move_to_gpu(struct i915_vma *vma, struct i915_request *rq, bool
write)
+{
+ struct drm_i915_gem_object *obj = vma->obj;
+
+ if (obj->cache_dirty & ~obj->cache_coherent)
+ i915_gem_clflush_object(obj, 0);
+
+ return i915_request_await_object(rq, obj, write);
+}
+
+int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
+struct
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] dma-fence: Propagate errors to dma-fence-array container
== Series Details == Series: series starting with [1/4] dma-fence: Propagate errors to dma-fence-array container URL : https://patchwork.freedesktop.org/series/65027/ State : success == Summary == CI Bug Log - changes from CI_DRM_6675 -> Patchwork_13962 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13962/ Known issues Here are the changes found in Patchwork_13962 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-blb-e6850/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13962/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [PASS][3] -> [SKIP][4] ([fdo#109271] / [fdo#109278]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13962/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13962/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html * igt@prime_vgem@basic-fence-flip: - fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-icl-u3/igt@prime_v...@basic-fence-flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13962/fi-icl-u3/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-ilk-650: [DMESG-WARN][9] ([fdo#106387]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-ilk-650/igt@debugfs_test@read_all_entries.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13962/fi-ilk-650/igt@debugfs_test@read_all_entries.html * igt@gem_exec_reloc@basic-cpu-read-noreloc: - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6675/fi-icl-u3/igt@gem_exec_re...@basic-cpu-read-noreloc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13962/fi-icl-u3/igt@gem_exec_re...@basic-cpu-read-noreloc.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (54 -> 46) -- Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6675 -> Patchwork_13962 CI-20190529: 20190529 CI_DRM_6675: cfacb6e14c0b7fc929565f9876f204e325a71b13 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13962: c522abf3342df26cefc038573afb9039c66542f8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c522abf3342d dma-fence: Always execute signal callbacks 476f7f51e0c0 dma-fence: Refactor signaling for manual invocation dcf1085c9b2f dma-fence: Report the composite sync_file status ff8f4c9b5c1d dma-fence: Propagate errors to dma-fence-array container == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13962/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for DC3CO Support for TGL (rev2)
== Series Details == Series: DC3CO Support for TGL (rev2) URL : https://patchwork.freedesktop.org/series/64923/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6668_full -> Patchwork_13952_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13952_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13952_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13952_full: ### IGT changes ### Possible regressions * igt@perf_pmu@busy-no-semaphores-rcs0: - shard-apl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl7/igt@perf_...@busy-no-semaphores-rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-apl1/igt@perf_...@busy-no-semaphores-rcs0.html * igt@runner@aborted: - shard-apl: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-apl1/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_13952_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([fdo#108566]) +7 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl4/igt@gem_ctx_isolat...@rcs0-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +11 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb8/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb5/igt@gem_exec_sched...@preemptive-hang-bsd.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][10] -> [DMESG-WARN][11] ([fdo#108686]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-glk5/igt@gem_tiled_swapp...@non-threaded.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-glk7/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-iclb: [PASS][12] -> [INCOMPLETE][13] ([fdo#107713]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb1/igt@kms_b...@extended-modeset-hang-newfb-render-c.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb7/igt@kms_b...@extended-modeset-hang-newfb-render-c.html * igt@kms_cursor_crc@pipe-a-cursor-256x256-random: - shard-skl: [PASS][14] -> [FAIL][15] ([fdo#103232]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-256x256-random.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-skl4/igt@kms_cursor_...@pipe-a-cursor-256x256-random.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([fdo#110741]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][18] -> [FAIL][19] ([fdo#105767]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-kbl: [PASS][20] -> [FAIL][21] ([fdo#103060]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl3/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-kbl3/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-glk: [PASS][22] -> [FAIL][23] ([fdo#100368]) [22]: https://intel-gfx-ci.01.org/tree/drm
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/tgl: Fix the read of the DDI that transcoder is attached to
Quoting José Roberto de Souza (2019-08-08 01:49:35)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d760830cfd7b..3d1c30a82302 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9432,6 +9432,8 @@ enum skl_power_gate {
> #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
> #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
> #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) <<
> TGL_TRANS_DDI_PORT_SHIFT)
> +#define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)(((val) &
> TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
> +#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) &
> TGL_TRANS_DDI_PORT_MASK >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
drivers/gpu/drm/i915/display/intel_display.c:10361 haswell_get_ddi_port_state()
warn: shift has higher precedence than mask
I presume you wanted (((val) & mask) >> shift) - 1) but I'm not sure.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] dma-fence: Propagate errors to dma-fence-array container
== Series Details == Series: series starting with [1/4] dma-fence: Propagate errors to dma-fence-array container URL : https://patchwork.freedesktop.org/series/65027/ State : warning == Summary == $ dim checkpatch origin/drm-tip ff8f4c9b5c1d dma-fence: Propagate errors to dma-fence-array container dcf1085c9b2f dma-fence: Report the composite sync_file status 476f7f51e0c0 dma-fence: Refactor signaling for manual invocation -:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #33: new file mode 100644 -:38: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #38: FILE: drivers/dma-buf/dma-fence-trace.c:1: +/* -:292: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #292: FILE: include/linux/dma-fence-types.h:1: +/* -:373: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #373: FILE: include/linux/dma-fence-types.h:82: + spinlock_t *lock; total: 0 errors, 3 warnings, 1 checks, 739 lines checked c522abf3342d dma-fence: Always execute signal callbacks ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] dma-fence: Refactor signaling for manual invocation
Move the duplicated code within dma-fence.c into the header for wider
reuse. In the process apply a small micro-optimisation to only prune the
fence->cb_list once rather than use list_del on every entry.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/dma-buf/Makefile| 10 +-
drivers/dma-buf/dma-fence-trace.c | 28 +++
drivers/dma-buf/dma-fence.c | 33 +--
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 32 +--
include/linux/dma-fence-impl.h | 83 +++
include/linux/dma-fence-types.h | 258
include/linux/dma-fence.h | 228 +
7 files changed, 386 insertions(+), 286 deletions(-)
create mode 100644 drivers/dma-buf/dma-fence-trace.c
create mode 100644 include/linux/dma-fence-impl.h
create mode 100644 include/linux/dma-fence-types.h
diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index e8c7310cb800..65c43778e571 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
-reservation.o seqno-fence.o
+obj-y := \
+ dma-buf.o \
+ dma-fence.o \
+ dma-fence-array.o \
+ dma-fence-chain.o \
+ dma-fence-trace.o \
+ reservation.o \
+ seqno-fence.o
obj-$(CONFIG_SYNC_FILE)+= sync_file.o
obj-$(CONFIG_SW_SYNC) += sw_sync.o sync_debug.o
obj-$(CONFIG_UDMABUF) += udmabuf.o
diff --git a/drivers/dma-buf/dma-fence-trace.c
b/drivers/dma-buf/dma-fence-trace.c
new file mode 100644
index ..eb6f282be4c0
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-trace.c
@@ -0,0 +1,28 @@
+/*
+ * Fence mechanism for dma-buf and to allow for asynchronous dma access
+ *
+ * Copyright (C) 2012 Canonical Ltd
+ * Copyright (C) 2012 Texas Instruments
+ *
+ * Authors:
+ * Rob Clark
+ * Maarten Lankhorst
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include
+
+#define CREATE_TRACE_POINTS
+#include
+
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 59ac96ec7ba8..027a6a894abd 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -14,15 +14,9 @@
#include
#include
#include
+#include
#include
-#define CREATE_TRACE_POINTS
-#include
-
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
-EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
-
static DEFINE_SPINLOCK(dma_fence_stub_lock);
static struct dma_fence dma_fence_stub;
@@ -128,7 +122,6 @@ EXPORT_SYMBOL(dma_fence_context_alloc);
*/
int dma_fence_signal_locked(struct dma_fence *fence)
{
- struct dma_fence_cb *cur, *tmp;
int ret = 0;
lockdep_assert_held(fence->lock);
@@ -136,7 +129,7 @@ int dma_fence_signal_locked(struct dma_fence *fence)
if (WARN_ON(!fence))
return -EINVAL;
- if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
+ if (!__dma_fence_signal(fence)) {
ret = -EINVAL;
/*
@@ -144,15 +137,10 @@ int dma_fence_signal_locked(struct dma_fence *fence)
* still run through all callbacks
*/
} else {
- fence->timestamp = ktime_get();
- set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags);
- trace_dma_fence_signaled(fence);
+ __dma_fence_signal__timestamp(fence, ktime_get());
}
- list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) {
- list_del_init(&cur->node);
- cur->func(fence, cur);
- }
+ __dma_fence_signal__notify(fence);
return ret;
}
EXPORT_SYMBOL(dma_fence_signal_locked);
@@ -177,21 +165,14 @@ int dma_fence_signal(struct dma_fence *fence)
if (!fence)
return -EINVAL;
- if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+ if (!__dma_fence_signal(fence))
return -EINVAL;
- fence->timestamp = ktime_get();
- set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags);
- trace_dma_fence_signaled(fence);
+ __dma_fence_signal__timestamp(fence, ktime_get());
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags)) {
- struct dma_fence_cb *cur, *tmp;
-
spin_lock
[Intel-gfx] [PATCH 4/4] dma-fence: Always execute signal callbacks
Allow for some users to surreptitiously insert lazy signal callbacks that
do not depend on enabling the signaling mechanism around every fence.
(The cost of interrupts is too darn high, to revive an old meme.)
This means that we may have a cb_list even if the signaling bit is not
enabled, so always notify the callbacks.
The cost is that dma_fence_signal() must always acquire the spinlock to
ensure that the cb_list is flushed.
Signed-off-by: Chris Wilson
---
drivers/dma-buf/dma-fence.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 027a6a894abd..ab4a456bba04 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -170,11 +170,9 @@ int dma_fence_signal(struct dma_fence *fence)
__dma_fence_signal__timestamp(fence, ktime_get());
- if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags)) {
- spin_lock_irqsave(fence->lock, flags);
- __dma_fence_signal__notify(fence);
- spin_unlock_irqrestore(fence->lock, flags);
- }
+ spin_lock_irqsave(fence->lock, flags);
+ __dma_fence_signal__notify(fence);
+ spin_unlock_irqrestore(fence->lock, flags);
return 0;
}
EXPORT_SYMBOL(dma_fence_signal);
--
2.23.0.rc1
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[Intel-gfx] [PATCH 2/4] dma-fence: Report the composite sync_file status
Same as for the individual fences, we want to report the actual status
of the fence when queried.
Reported-by: Petri Latvala
Signed-off-by: Chris Wilson
Cc: Sumit Semwal
Cc: Gustavo Padovan
Cc: Petri Latvala
---
drivers/dma-buf/sync_file.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma-buf/sync_file.c b/drivers/dma-buf/sync_file.c
index ee4d1a96d779..25c5c071645b 100644
--- a/drivers/dma-buf/sync_file.c
+++ b/drivers/dma-buf/sync_file.c
@@ -419,7 +419,7 @@ static long sync_file_ioctl_fence_info(struct sync_file
*sync_file,
* info->num_fences.
*/
if (!info.num_fences) {
- info.status = dma_fence_is_signaled(sync_file->fence);
+ info.status = dma_fence_get_status(sync_file->fence);
goto no_fences;
} else {
info.status = 1;
--
2.23.0.rc1
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[Intel-gfx] [PATCH 1/4] dma-fence: Propagate errors to dma-fence-array container
When one of the array of fences is signaled, propagate its errors to the
parent fence-array (keeping the first error to be raised).
v2: Opencode cmpxchg_local to avoid compiler freakout.
Signed-off-by: Chris Wilson
Cc: Sumit Semwal
Cc: Gustavo Padovan
---
drivers/dma-buf/dma-fence-array.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-array.c
b/drivers/dma-buf/dma-fence-array.c
index 12c6f64c0bc2..d90675bb4fcc 100644
--- a/drivers/dma-buf/dma-fence-array.c
+++ b/drivers/dma-buf/dma-fence-array.c
@@ -13,6 +13,12 @@
#include
#include
+static void fence_set_error_once(struct dma_fence *fence, int error)
+{
+ if (!fence->error && error)
+ dma_fence_set_error(fence, error);
+}
+
static const char *dma_fence_array_get_driver_name(struct dma_fence *fence)
{
return "dma_fence_array";
@@ -38,6 +44,13 @@ static void dma_fence_array_cb_func(struct dma_fence *f,
container_of(cb, struct dma_fence_array_cb, cb);
struct dma_fence_array *array = array_cb->array;
+ /*
+* Propagate the first error reported by any of our fences, but only
+* before we ourselves are signaled.
+*/
+ if (atomic_read(&array->num_pending) > 0)
+ fence_set_error_once(&array->base, f->error);
+
if (atomic_dec_and_test(&array->num_pending))
irq_work_queue(&array->work);
else
@@ -63,6 +76,8 @@ static bool dma_fence_array_enable_signaling(struct dma_fence
*fence)
dma_fence_get(&array->base);
if (dma_fence_add_callback(array->fences[i], &cb[i].cb,
dma_fence_array_cb_func)) {
+ fence_set_error_once(&array->base,
+array->fences[i]->error);
dma_fence_put(&array->base);
if (atomic_dec_and_test(&array->num_pending))
return false;
--
2.23.0.rc1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/4] drm/i915: Remove i915_gem_context_create_gvt()
== Series Details == Series: series starting with [CI,1/4] drm/i915: Remove i915_gem_context_create_gvt() URL : https://patchwork.freedesktop.org/series/64985/ State : success == Summary == CI Bug Log - changes from CI_DRM_6668_full -> Patchwork_13951_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13951_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb8/igt@gem_exec_as...@concurrent-writes-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-iclb2/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-iclb7/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_pread@uncached: - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl4/igt@gem_pr...@uncached.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-apl4/igt@gem_pr...@uncached.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl7/igt@gem_tiled_swapp...@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-apl2/igt@gem_tiled_swapp...@non-threaded.html - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108686]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl7/igt@gem_tiled_swapp...@non-threaded.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-kbl6/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl1/igt@kms_f...@flip-vs-suspend-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-kbl6/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb8/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-iclb2/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl7/igt@kms_frontbuffer_track...@fbc-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-apl5/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#104108]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-skl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-skl10/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_sequence@queue-idle: - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb2/igt@kms_seque...@queue-idle.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-iclb7/igt@kms_seque...@queue-idle.html * igt@kms_setmode@basic: - shard-apl: [PASS][23] -> [FAIL][24] ([fdo#99912]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl6/igt@kms_setm...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13951/shard-apl5/igt@kms_setm...@basic.html * igt@perf@blocking: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#110728]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Remove i915_gem_context_create_gvt() (rev2)
== Series Details == Series: series starting with [1/4] drm/i915: Remove i915_gem_context_create_gvt() (rev2) URL : https://patchwork.freedesktop.org/series/64979/ State : success == Summary == CI Bug Log - changes from CI_DRM_6668_full -> Patchwork_13950_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13950_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@pi-ringfull-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb6/igt@gem_exec_sched...@pi-ringfull-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-iclb4/igt@gem_exec_sched...@pi-ringfull-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +11 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-iclb6/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl6/igt@gem_workarou...@suspend-resume-fd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-kbl2/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107807]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-skl4/igt@i915_pm_...@system-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-skl9/igt@i915_pm_...@system-suspend.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl1/igt@i915_susp...@sysfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-apl3/igt@i915_susp...@sysfs-reader.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-apl: [PASS][15] -> [FAIL][16] ([fdo#99912]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl6/igt@kms_setm...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-apl5/igt@kms_setm...@basic.html * igt@perf_pmu@rc6: - shard-kbl: [PASS][17] -> [SKIP][18] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl4/igt@perf_...@rc6.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-kbl7/igt@perf_...@rc6.html Possible fixes * igt@gem_ctx_isolation@vcs1-none: - shard-iclb: [SKIP][19] ([fdo#109276]) -> [PASS][20] +10 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb6/igt@gem_ctx_isolat...@vcs1-none.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-iclb4/igt@gem_ctx_isolat...@vcs1-none.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [SKIP][21] ([fdo#110841]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_flush@basic-wb-rw-default: - shard-apl: [INCOMPLETE][23] ([fdo#103927]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl5/igt@gem_exec_fl...@basic-wb-rw-default.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13950/shard-apl4/igt@gem_exec_fl...@basic-wb-rw-default.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [SKIP][25] ([fdo#111325]) -> [PASS][26] +4 similar issues [25]: https://intel-gfx-ci
[Intel-gfx] [PATCH i-g-t] i915/gem_mmap_gtt: Test mmap_offset lifetime
Closing the object on another file should not affect the local
mmap_offset.
Signed-off-by: Chris Wilson
Cc: Abdiel Janulgue
---
tests/i915/gem_mmap_gtt.c | 40 +++
1 file changed, 40 insertions(+)
diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_gtt.c
index 6f3a9c36e..8eff91850 100644
--- a/tests/i915/gem_mmap_gtt.c
+++ b/tests/i915/gem_mmap_gtt.c
@@ -322,6 +322,44 @@ test_pf_nonblock(int i915)
igt_spin_free(i915, spin);
}
+static void
+test_isolation(int i915)
+{
+ struct drm_i915_gem_mmap_gtt mmap_arg;
+ int A = gem_reopen_driver(i915);
+ int B = gem_reopen_driver(i915);
+ uint64_t offset_a, offset_b;
+ uint32_t a, b;
+ void *ptr;
+
+ a = gem_create(A, 4096);
+ b = gem_open(B, gem_flink(A, a));
+
+ mmap_arg.handle = a;
+ do_ioctl(A, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg);
+ offset_a = mmap_arg.offset;
+
+ mmap_arg.handle = b;
+ do_ioctl(B, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg);
+ offset_b = mmap_arg.offset;
+
+ igt_info("A: {fd:%d, handle:%d, offset:%"PRIx64"}\n",
+A, a, offset_a);
+ igt_info("B: {fd:%d, handle:%d, offset:%"PRIx64"}\n",
+B, b, offset_b);
+
+ close(B);
+
+ ptr = mmap64(0, 4096, PROT_READ, MAP_SHARED, A, offset_a);
+ igt_assert(ptr != MAP_FAILED);
+ munmap(ptr, 4096);
+
+ close(A);
+
+ ptr = mmap64(0, 4096, PROT_READ, MAP_SHARED, A, offset_a);
+ igt_assert(ptr == MAP_FAILED);
+}
+
static void
test_write_gtt(int fd)
{
@@ -945,6 +983,8 @@ igt_main
test_write_cpu_read_gtt(fd);
igt_subtest("basic-wc")
test_wc(fd);
+ igt_subtest("isolation")
+ test_isolation(fd);
igt_subtest("pf-nonblock")
test_pf_nonblock(fd);
--
2.23.0.rc1
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: move gpu-write-dw into utils
== Series Details == Series: drm/i915/selftests: move gpu-write-dw into utils URL : https://patchwork.freedesktop.org/series/65013/ State : success == Summary == CI Bug Log - changes from CI_DRM_6672 -> Patchwork_13960 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/ Known issues Here are the changes found in Patchwork_13960 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/fi-icl-u3/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/fi-icl-u3/igt@debugfs_test@read_all_entries.html * igt@i915_module_load@reload: - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/fi-blb-e6850/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@i915_selftest@live_requests: - fi-byt-j1900: [PASS][5] -> [INCOMPLETE][6] ([fdo#102657]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/fi-byt-j1900/igt@i915_selftest@live_requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/fi-byt-j1900/igt@i915_selftest@live_requests.html Possible fixes * igt@kms_chamelium@dp-edid-read: - fi-kbl-7500u: [WARN][7] ([fdo#109483]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6672/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 Participating hosts (55 -> 46) -- Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6672 -> Patchwork_13960 CI-20190529: 20190529 CI_DRM_6672: 5d0a06cd532c02ae0c4a81edb9d0857719453927 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13960: a0222d56bf53c3c83f936e61a43157a3628eb5b1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a0222d56bf53 drm/i915/selftests: move gpu-write-dw into utils == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13960/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 36/37] drm/i915/query: Expose memory regions through the query uAPI
Quoting Matthew Auld (2019-08-09 23:26:42)
> From: Abdiel Janulgue
>
> Returns the available memory region areas supported by the HW.
And how does one use this information?
How does this relate to the information presented by Vulkan or OpenCL
Testcase: igt/...?
New uAPI should always come with a testcase.
> Signed-off-by: Abdiel Janulgue
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_query.c | 57 +++
> include/uapi/drm/i915_drm.h | 39 +
> 2 files changed, 96 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_query.c
> b/drivers/gpu/drm/i915/i915_query.c
> index ad9240a0817a..69a2a906feef 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -142,10 +142,67 @@ query_engine_info(struct drm_i915_private *i915,
> return len;
> }
>
> +static int query_memregion_info(struct drm_i915_private *dev_priv,
> + struct drm_i915_query_item *query_item)
> +{
> + struct drm_i915_query_memory_region_info __user *query_ptr =
> + u64_to_user_ptr(query_item->data_ptr);
> + struct drm_i915_memory_region_info __user *info_ptr =
> + &query_ptr->regions[0];
> + struct drm_i915_memory_region_info info = { };
> + struct drm_i915_query_memory_region_info query;
> + u32 total_length;
> + int ret, i;
> +
> + if (query_item->flags != 0)
> + return -EINVAL;
> +
> + total_length = sizeof(struct drm_i915_query_memory_region_info);
> + for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) {
> + struct intel_memory_region *region = dev_priv->regions[i];
> +
> + if (!region)
> + continue;
> +
> + total_length += sizeof(struct drm_i915_memory_region_info);
> + }
> +
> + ret = copy_query_item(&query, sizeof(query), total_length,
> + query_item);
> + if (ret != 0)
> + return ret;
> +
> + if (query.num_regions || query.rsvd[0] || query.rsvd[1] ||
> + query.rsvd[2])
> + return -EINVAL;
> +
> + for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) {
> + struct intel_memory_region *region = dev_priv->regions[i];
> +
> + if (!region)
> + continue;
> +
> + info.id = region->id;
> + info.size = resource_size(®ion->region);
> +
> + if (__copy_to_user(info_ptr, &info, sizeof(info)))
> + return -EFAULT;
> +
> + query.num_regions++;
> + info_ptr++;
> + }
> +
> + if (__copy_to_user(query_ptr, &query, sizeof(query)))
> + return -EFAULT;
> +
> + return total_length;
> +}
> +
> static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
> struct drm_i915_query_item
> *query_item) = {
> query_topology_info,
> query_engine_info,
> + query_memregion_info,
> };
>
> int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file
> *file)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 75d79c17e91b..7ef037f58e1b 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2038,6 +2038,7 @@ struct drm_i915_query_item {
> __u64 query_id;
> #define DRM_I915_QUERY_TOPOLOGY_INFO1
> #define DRM_I915_QUERY_ENGINE_INFO 2
> +#define DRM_I915_QUERY_MEMREGION_INFO 3
> /* Must be kept compact -- no holes and well documented */
>
> /*
> @@ -2177,6 +2178,44 @@ struct drm_i915_query_engine_info {
> struct drm_i915_engine_info engines[];
> };
>
> +struct drm_i915_memory_region_info {
> +
> + /** Base type of a region
> +*/
> +#define I915_SYSTEM_MEMORY 0
> +#define I915_DEVICE_MEMORY 1
> +
> + /** The region id is encoded in a layout which makes it possible to
> +* retrieve the following information:
> +*
> +* Base type: log2(ID >> 16)
> +* Instance: log2(ID & 0x)
> +*/
> + __u32 id;
You still haven't given userspace the basics such as total size and chunk size.
> + /** Reserved field. MBZ */
> + __u32 rsvd0;
> +
> + /** Unused for now. MBZ */
> + __u64 flags;
> +
> + __u64 size;
> +
> + /** Reserved fields must be cleared to zero. */
> + __u64 rsvd1[4];
> +};
> +
> +struct drm_i915_query_memory_region_info {
> +
> + /** Number of struct drm_i915_memory_region_info structs */
> + __u32 num_regions;
> +
> + /** MBZ */
> + __u32 rsvd[3];
> +
> + struct drm_i915_memory_region_info regions[];
> +};
> +
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.20.1
>
> ___
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> Intel-gfx@lists.
Re: [Intel-gfx] [PATCH v3 35/37] drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION
Quoting Matthew Auld (2019-08-09 23:26:41)
> From: Abdiel Janulgue
>
> This call will specify which memory region an object should be placed.
>
> Note that changing the object's backing storage should be immediately
> done after an object is created or if it's not yet in use, otherwise
> this will fail on a busy object.
>
> Signed-off-by: Abdiel Janulgue
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 +++
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +
> drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | 2 +
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 115
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> include/uapi/drm/i915_drm.h | 23
> 6 files changed, 160 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index b407baaf0014..572033ac6e3b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -76,6 +76,7 @@
> #include "i915_globals.h"
> #include "i915_trace.h"
> #include "i915_user_extensions.h"
> +#include "i915_gem_ioctls.h"
>
> #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
>
> @@ -2308,6 +2309,22 @@ int i915_gem_context_setparam_ioctl(struct drm_device
> *dev, void *data,
> return ret;
> }
>
> +int i915_gem_setparam_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file)
This does not need to be in i915_gem_context.c
> +{
> + struct drm_i915_gem_context_param *args = data;
> +
switch(upper_32_bits(args->param)) {
> + case 0:
> + return i915_gem_context_setparam_ioctl(dev, data, file);
> + case 1:
> + return i915_gem_object_setparam_ioctl(dev, data, file);
> +
> + }
> + return -EINVAL;
> +}
> +
> int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
>void *data, struct drm_file *file)
> {
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index 106e2ccf7a4c..1cfcf1e6bbb9 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -157,6 +157,8 @@ int i915_gem_context_getparam_ioctl(struct drm_device
> *dev, void *data,
> struct drm_file *file_priv);
> int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file_priv);
> +int i915_gem_setparam_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file);
> int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
>struct drm_file *file);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
> b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
> index 5abd5b2172f2..af7465bceebd 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
> @@ -32,6 +32,8 @@ int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void
> *data,
> struct drm_file *file);
> int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
>struct drm_file *file_priv);
> +int i915_gem_object_setparam_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file_priv);
> int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 5982aeaaa2e3..52ea65f203a1 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -506,6 +506,121 @@ int __init i915_global_objects_init(void)
> return 0;
> }
>
> +static enum intel_region_id
> +__region_id(u32 region)
> +{
> + enum intel_region_id id;
> +
> + for (id = 0; id < INTEL_MEMORY_UKNOWN; ++id) {
> + if (intel_region_map[id] == region)
> + return id;
> + }
> +
> + return INTEL_MEMORY_UKNOWN;
> +}
> +
> +static int i915_gem_object_region_select(struct drm_i915_private *dev_priv,
> +struct drm_i915_gem_object_param
> *args,
> +struct drm_file *file,
> +struct drm_i915_gem_object *obj)
> +{
> + struct intel_context *ce = dev_priv->engine[BCS0]->kernel_context;
> + u32 __user *uregions = u64_to_user_ptr(args->data);
> + u32 uregions_copy[INTEL_MEMORY_UKNOWN];
> + int i, ret;
> +
> + if (args->size > INTEL_MEMORY_UKNOWN)
> + return -EINVA
Re: [Intel-gfx] [PATCH v3 34/37] drm/i915: support basic object migration
Quoting Matthew Auld (2019-08-09 23:26:40)
> We are going want to able to move objects between different regions
> like system memory and local memory. In the future everything should
> be just another region.
>
> Signed-off-by: Matthew Auld
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: CQ Tang
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object.c| 140 ++
> drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 +
> drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
> .../drm/i915/selftests/intel_memory_region.c | 129
> 4 files changed, 278 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 24f737b00e84..5982aeaaa2e3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -28,6 +28,8 @@
> #include "i915_gem_clflush.h"
> #include "i915_gem_context.h"
> #include "i915_gem_object.h"
> +#include "i915_gem_object_blt.h"
> +#include "i915_gem_region.h"
> #include "i915_globals.h"
> #include "i915_trace.h"
>
> @@ -170,6 +172,144 @@ static void __i915_gem_free_object_rcu(struct rcu_head
> *head)
> atomic_dec(&i915->mm.free_count);
> }
>
> +
> +int i915_gem_object_prepare_move(struct drm_i915_gem_object *obj)
> +{
> + int err;
> +
> + lockdep_assert_held(&obj->base.dev->struct_mutex);
No, straight up no.
-Chris
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Re: [Intel-gfx] [PATCH v3 33/37] drm/i915: cpu-map based dumb buffers
Quoting Matthew Auld (2019-08-09 23:26:39)
> From: Abdiel Janulgue
>
> If there is no aperture we can't use map_gtt to map dumb buffers, so we
> need a cpu-map based path to do it. We prefer map_gtt on platforms that
> do have aperture.
>
> Signed-off-by: Abdiel Janulgue
> Cc: Daniele Ceraolo Spurio
> Cc: Tvrtko Ursulin
> Cc: Matthew Auld
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 18 +-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> drivers/gpu/drm/i915/i915_drv.c| 2 +-
> drivers/gpu/drm/i915/i915_drv.h| 2 +-
> 4 files changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index 304ea578fd30..4fe83e31c1b3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -500,7 +500,8 @@ static void i915_gem_object_release_mmap_offset(struct
> drm_i915_gem_object *obj)
> list_for_each_entry(mmo, &obj->mmap_offsets, offset) {
> if (mmo->mmap_type == I915_MMAP_TYPE_OFFSET_WC ||
> mmo->mmap_type == I915_MMAP_TYPE_OFFSET_WB ||
> - mmo->mmap_type == I915_MMAP_TYPE_OFFSET_UC)
> + mmo->mmap_type == I915_MMAP_TYPE_OFFSET_UC ||
> + mmo->mmap_type == I915_MMAP_TYPE_DUMB_WC)
Why even special case it???
Even at three logical-ors I suggest you start encoding flags into
mmap_type.
In this case, why isn't it something like
if (has_node(&mmo->vma_node))
> drm_vma_node_unmap(&mmo->vma_node,
>
> obj->base.dev->anon_inode->i_mapping);
> }
> @@ -602,6 +603,19 @@ __assign_gem_object_mmap_data(struct drm_file *file,
> return ret;
> }
>
> +int
> +i915_gem_mmap_dumb(struct drm_file *file,
> + struct drm_device *dev,
> + u32 handle,
> + u64 *offset)
> +{
> + struct drm_i915_private *i915 = dev->dev_private;
> + enum i915_mmap_type mmap_type = HAS_MAPPABLE_APERTURE(i915) ?
> + I915_MMAP_TYPE_GTT : I915_MMAP_TYPE_DUMB_WC;
It's a linear buffer, you can always do WC now that you can return an
offset for WC.
> +
> + return __assign_gem_object_mmap_data(file, handle, mmap_type, offset);
> +}
> +
> /**
> * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
> * @dev: DRM device
> @@ -714,6 +728,7 @@ static void set_vmdata_mmap_offset(struct
> i915_mmap_offset *mmo, struct vm_area_
> {
> switch (mmo->mmap_type) {
> case I915_MMAP_TYPE_OFFSET_WC:
> + case I915_MMAP_TYPE_DUMB_WC:
> vma->vm_page_prot =
> pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
> break;
> @@ -801,6 +816,7 @@ int i915_gem_mmap(struct file *filp, struct
> vm_area_struct *vma)
> case I915_MMAP_TYPE_OFFSET_WC:
> case I915_MMAP_TYPE_OFFSET_WB:
> case I915_MMAP_TYPE_OFFSET_UC:
> + case I915_MMAP_TYPE_DUMB_WC:
Yup, that was quite redundant.
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Re: [Intel-gfx] [PATCH v3 32/37] drm/i915: Add cpu and lmem fault handlers
Quoting Matthew Auld (2019-08-09 23:26:38)
> -void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj)
> +static vm_fault_t i915_gem_fault_cpu(struct vm_fault *vmf)
> +{
> + struct vm_area_struct *area = vmf->vma;
> + struct i915_mmap_offset *priv = area->vm_private_data;
> + struct drm_i915_gem_object *obj = priv->obj;
> + struct drm_device *dev = obj->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + vm_fault_t vmf_ret;
> + unsigned long size = area->vm_end - area->vm_start;
> + bool write = area->vm_flags & VM_WRITE;
> + int i, ret;
> +
> + /* Sanity check that we allow writing into this object */
> + if (i915_gem_object_is_readonly(obj) && write)
> + return VM_FAULT_SIGBUS;
> +
> + ret = i915_gem_object_pin_pages(obj);
if (err)
return i915_error_to_vmf_fault(err);
> + goto err;
> +
> + for (i = 0; i < size >> PAGE_SHIFT; i++) {
> + struct page *page = i915_gem_object_get_page(obj, i);
> + vmf_ret = vmf_insert_pfn(area,
> +(unsigned long)area->vm_start + i *
> PAGE_SIZE,
> +page_to_pfn(page));
> + if (vmf_ret & VM_FAULT_ERROR) {
> + ret = vm_fault_to_errno(vmf_ret, 0);
> + break;
> + }
> + }
> +
> + i915_gem_object_unpin_pages(obj);
return vmf_ret;
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Re: [Intel-gfx] [PATCH v3 30/37] drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET
Quoting Matthew Auld (2019-08-09 23:26:36)
> From: Abdiel Janulgue
>
> Add a new CPU mmap implementation that allows multiple fault handlers
> that depends on the object's backing pages.
>
> Note that we multiplex mmap_gtt and mmap_offset through the same ioctl,
> and use the zero extending behaviour of drm to differentiate between
> them, when we inspect the flags.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/gem/i915_gem_ioctls.h| 2 ++
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 30 ++
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 3 ++
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_getparam.c | 1 +
> include/uapi/drm/i915_drm.h | 31 +++
> 6 files changed, 68 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
> b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
> index ddc7f2a52b3e..5abd5b2172f2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
> @@ -30,6 +30,8 @@ int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> +int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file_priv);
mmap_offset_ioctl is replacing mmap_gtt_ioctl, you don't need to keep
the old one public.
(Or vice versa apparently.)
> int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index d4a9d59803a7..a62657a1f011 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -538,12 +538,42 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void
> *data,
> struct drm_file *file)
> {
> struct drm_i915_gem_mmap_offset *args = data;
> + struct drm_i915_private *i915 = to_i915(dev);
> +
> + if (args->flags & I915_MMAP_OFFSET_FLAGS)
> + return i915_gem_mmap_offset_ioctl(dev, data, file);
> +
> + if (!HAS_MAPPABLE_APERTURE(i915)) {
> + DRM_ERROR("No aperture, cannot mmap via legacy GTT\n");
> + return -ENODEV;
> + }
>
> return __assign_gem_object_mmap_data(file, args->handle,
> I915_MMAP_TYPE_GTT,
> &args->offset);
> }
>
> +int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file)
> +{
> + struct drm_i915_gem_mmap_offset *args = data;
> + enum i915_mmap_type type;
> +
> + if ((args->flags & (I915_MMAP_OFFSET_WC | I915_MMAP_OFFSET_WB)) &&
> + !boot_cpu_has(X86_FEATURE_PAT))
> + return -ENODEV;
> +
> + if (args->flags & I915_MMAP_OFFSET_WC)
> + type = I915_MMAP_TYPE_OFFSET_WC;
> + else if (args->flags & I915_MMAP_OFFSET_WB)
> + type = I915_MMAP_TYPE_OFFSET_WB;
> + else if (args->flags & I915_MMAP_OFFSET_UC)
> + type = I915_MMAP_TYPE_OFFSET_UC;
> +
> + return __assign_gem_object_mmap_data(file, args->handle, type,
> +&args->offset);
> +}
> +
> void i915_mmap_offset_object_release(struct kref *ref)
> {
> struct i915_mmap_offset *mmo = container_of(ref,
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index a3745f7d57a1..4ea78d3c92a9 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -64,6 +64,9 @@ struct drm_i915_gem_object_ops {
>
> enum i915_mmap_type {
> I915_MMAP_TYPE_GTT = 0,
> + I915_MMAP_TYPE_OFFSET_WC,
> + I915_MMAP_TYPE_OFFSET_WB,
> + I915_MMAP_TYPE_OFFSET_UC,
> };
>
> struct i915_mmap_offset {
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index fcee06ed3469..cf390092c927 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2710,7 +2710,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
> DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
> DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
> DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl,
> DRM_RENDER_ALLOW),
> - DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl,
> DRM_RENDER_ALLOW),
> + DRM_IOCTL_DE
Re: [Intel-gfx] [PATCH v3 29/37] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core
Quoting Matthew Auld (2019-08-09 23:26:35)
> From: Abdiel Janulgue
>
> This enables us to store extra data within vma->vm_private_data and assign
> the pagefault ops for each mmap instance.
>
> We replace the core drm_gem_mmap implementation to overcome the limitation
> in having only a single offset node per gem object, allowing us to have
> multiple offsets per object. This enables a mapping instance to use unique
> fault-hadlers, per object.
>
> Signed-off-by: Abdiel Janulgue
> Cc: Joonas Lahtinen
> Signed-off-by: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 183 --
> drivers/gpu/drm/i915/gem/i915_gem_object.c| 16 ++
> drivers/gpu/drm/i915/gem/i915_gem_object.h| 7 +-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 18 ++
> .../drm/i915/gem/selftests/i915_gem_mman.c| 12 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 13 +-
> drivers/gpu/drm/i915/i915_drv.c | 9 +-
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_vma.c | 21 +-
> 9 files changed, 244 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index 1e7311493530..d4a9d59803a7 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -221,7 +221,8 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
> {
> #define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
> struct vm_area_struct *area = vmf->vma;
> - struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
> + struct i915_mmap_offset *priv = area->vm_private_data;
> + struct drm_i915_gem_object *obj = priv->obj;
> struct drm_device *dev = obj->base.dev;
> struct drm_i915_private *i915 = to_i915(dev);
> struct intel_runtime_pm *rpm = &i915->runtime_pm;
> @@ -373,13 +374,15 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
> void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj)
> {
> struct i915_vma *vma;
> + struct i915_mmap_offset *mmo;
>
> GEM_BUG_ON(!obj->userfault_count);
>
> obj->userfault_count = 0;
> list_del(&obj->userfault_link);
> - drm_vma_node_unmap(&obj->base.vma_node,
> - obj->base.dev->anon_inode->i_mapping);
> + list_for_each_entry(mmo, &obj->mmap_offsets, offset)
> + drm_vma_node_unmap(&mmo->vma_node,
> + obj->base.dev->anon_inode->i_mapping);
>
> for_each_ggtt_vma(vma, obj)
> i915_vma_unset_userfault(vma);
> @@ -433,14 +436,31 @@ void i915_gem_object_release_mmap(struct
> drm_i915_gem_object *obj)
> intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> }
>
> -static int create_mmap_offset(struct drm_i915_gem_object *obj)
> +static void init_mmap_offset(struct drm_i915_gem_object *obj,
> +struct i915_mmap_offset *mmo)
> +{
> + mutex_lock(&obj->mmo_lock);
> + kref_init(&mmo->ref);
> + list_add(&mmo->offset, &obj->mmap_offsets);
> + mutex_unlock(&obj->mmo_lock);
> +}
> +
> +static int create_mmap_offset(struct drm_i915_gem_object *obj,
> + struct i915_mmap_offset *mmo)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> + struct drm_device *dev = obj->base.dev;
> int err;
>
> - err = drm_gem_create_mmap_offset(&obj->base);
> - if (likely(!err))
> + drm_vma_node_reset(&mmo->vma_node);
> + if (mmo->file)
> + drm_vma_node_allow(&mmo->vma_node, mmo->file);
> + err = drm_vma_offset_add(dev->vma_offset_manager, &mmo->vma_node,
> +obj->base.size / PAGE_SIZE);
> + if (likely(!err)) {
> + init_mmap_offset(obj, mmo);
> return 0;
> + }
>
> /* Attempt to reap some mmap space from dead objects */
> do {
> @@ -451,32 +471,49 @@ static int create_mmap_offset(struct
> drm_i915_gem_object *obj)
> break;
>
> i915_gem_drain_freed_objects(i915);
> - err = drm_gem_create_mmap_offset(&obj->base);
> - if (!err)
> + err = drm_vma_offset_add(dev->vma_offset_manager,
> &mmo->vma_node,
> +obj->base.size / PAGE_SIZE);
> + if (!err) {
> + init_mmap_offset(obj, mmo);
> break;
> + }
>
> } while (flush_delayed_work(&i915->gem.retire_work));
>
> return err;
> }
>
> -int
> -i915_gem_mmap_gtt(struct drm_file *file,
> - struct drm_device *dev,
> - u32 handle,
> - u64 *offset)
> +static int
> +__assign_gem_object_mmap_data(struct drm_file *file,
> + u32 handle
Re: [Intel-gfx] [PATCH v3 28/37] drm/i915: check for missing aperture in insert_mappable_node
Quoting Matthew Auld (2019-08-09 23:26:34)
> From: CQ Tang
>
> Signed-off-by: CQ Tang
> Signed-off-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_gem.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 2aa4fbe7edc0..af63d1a0af14 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -64,6 +64,9 @@ static int
> insert_mappable_node(struct i915_ggtt *ggtt,
> struct drm_mm_node *node, u32 size)
> {
> + if (!ggtt->mappable_end)
> + return -ENOSPC;
How did you get here? This should remain the BUG for the programming
error.
-Chris
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Re: [Intel-gfx] [PATCH v3 27/37] drm/i915: Don't try to place HWS in non-existing mappable region
Quoting Matthew Auld (2019-08-09 23:26:33) > From: Michal Wajdeczko > > HWS placement restrictions can't just rely on HAS_LLC flag. > > Signed-off-by: Michal Wajdeczko > Cc: Daniele Ceraolo Spurio > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 634ef45b77da..46658ecd8975 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -512,7 +512,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs > *engine, > unsigned int flags; > > flags = PIN_GLOBAL; > - if (!HAS_LLC(engine->i915)) > + if (!HAS_LLC(engine->i915) && HAS_MAPPABLE_APERTURE(engine->i915)) Should we risk IS_GEN() <= 9 instead? > /* > * On g33, we cannot place HWS above 256MiB, so > * restrict its pinning to the low mappable arena. > -- > 2.20.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 26/37] drm/i915: error capture with no ggtt slot
Quoting Matthew Auld (2019-08-09 23:26:32)
> From: Daniele Ceraolo Spurio
>
> If the aperture is not available in HW we can't use a ggtt slot and wc
> copy, so fall back to regular kmap.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Abdiel Janulgue
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 19
> drivers/gpu/drm/i915/i915_gpu_error.c | 64 ++-
> 2 files changed, 63 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index dd28c54527e3..0819ac9837dc 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2630,7 +2630,8 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
> static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
> {
> ggtt_release_guc_top(ggtt);
> - drm_mm_remove_node(&ggtt->error_capture);
> + if (drm_mm_node_allocated(&ggtt->error_capture))
> + drm_mm_remove_node(&ggtt->error_capture);
> }
>
> static int init_ggtt(struct i915_ggtt *ggtt)
> @@ -2661,13 +2662,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
> if (ret)
> return ret;
>
> - /* Reserve a mappable slot for our lockless error capture */
> - ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
> - PAGE_SIZE, 0,
> I915_COLOR_UNEVICTABLE,
> - 0, ggtt->mappable_end,
> - DRM_MM_INSERT_LOW);
> - if (ret)
> - return ret;
> + if (HAS_MAPPABLE_APERTURE(ggtt->vm.i915)) {
> + /* Reserve a mappable slot for our lockless error capture */
> + ret = drm_mm_insert_node_in_range(&ggtt->vm.mm,
> &ggtt->error_capture,
> + PAGE_SIZE, 0,
> I915_COLOR_UNEVICTABLE,
> + 0, ggtt->mappable_end,
> + DRM_MM_INSERT_LOW);
> + if (ret)
> + return ret;
> + }
>
> /*
> * The upper portion of the GuC address space has a sizeable hole
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 92986d3f6995..19eb5ccba387 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -40,6 +40,7 @@
> #include "display/intel_overlay.h"
>
> #include "gem/i915_gem_context.h"
> +#include "gem/i915_gem_lmem.h"
>
> #include "i915_drv.h"
> #include "i915_gpu_error.h"
> @@ -235,6 +236,7 @@ struct compress {
> struct pagevec pool;
> struct z_stream_s zstream;
> void *tmp;
> + bool wc;
> };
>
> static bool compress_init(struct compress *c)
> @@ -292,7 +294,7 @@ static int compress_page(struct compress *c,
> struct z_stream_s *zstream = &c->zstream;
>
> zstream->next_in = src;
> - if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
> + if (c->wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
> zstream->next_in = c->tmp;
> zstream->avail_in = PAGE_SIZE;
>
> @@ -367,6 +369,7 @@ static void err_compression_marker(struct
> drm_i915_error_state_buf *m)
>
> struct compress {
> struct pagevec pool;
> + bool wc;
> };
>
> static bool compress_init(struct compress *c)
> @@ -389,7 +392,7 @@ static int compress_page(struct compress *c,
> if (!ptr)
> return -ENOMEM;
>
> - if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
> + if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
> memcpy(ptr, src, PAGE_SIZE);
> dst->pages[dst->page_count++] = ptr;
>
> @@ -963,7 +966,6 @@ i915_error_object_create(struct drm_i915_private *i915,
> struct drm_i915_error_object *dst;
> unsigned long num_pages;
> struct sgt_iter iter;
> - dma_addr_t dma;
> int ret;
>
> might_sleep();
> @@ -988,17 +990,53 @@ i915_error_object_create(struct drm_i915_private *i915,
> dst->page_count = 0;
> dst->unused = 0;
>
> + compress->wc = i915_gem_object_is_lmem(vma->obj) ||
We need to talk about this fixation you appear to have on vma->obj!
> + drm_mm_node_allocated(&ggtt->error_capture);
> +
> ret = -EINVAL;
> - for_each_sgt_dma(dma, iter, vma->pages) {
> + if (drm_mm_node_allocated(&ggtt->error_capture)) {
> void __iomem *s;
> + dma_addr_t dma;
>
> - ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE,
> 0);
> + for_each_sgt_dma(dma, iter, vma->pages) {
> + ggtt->vm.insert_page(&ggtt->vm, dma, slot,
> +I915_CACHE_NONE, 0);
>
> - s = io
Re: [Intel-gfx] [PATCH v3 23/37] drm/i915: do not map aperture if it is not available.
Quoting Matthew Auld (2019-08-09 23:26:29)
> From: Daniele Ceraolo Spurio
>
> Skip both setup and cleanup of the aperture mapping if the HW doesn't
> have an aperture bar.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 36 ++---
> 1 file changed, 22 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 5bcf71b18e5f..dd28c54527e3 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2795,8 +2795,10 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
>
> mutex_unlock(&i915->drm.struct_mutex);
>
> - arch_phys_wc_del(ggtt->mtrr);
> - io_mapping_fini(&ggtt->iomap);
> + if (HAS_MAPPABLE_APERTURE(i915)) {
I feel here it should be less shouting.
> + arch_phys_wc_del(ggtt->mtrr);
wc_del() doesn't care if we call it without a mtrr (nothing has been
using an mtrr since PAT).
if (ggtt->iomap.size)
> + io_mapping_fini(&ggtt->iomap);
> + }
> }
>
> /**
> @@ -2992,10 +2994,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> int err;
>
> /* TODO: We're not aware of mappable constraints on gen8 yet */
> - ggtt->gmadr =
> - (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
> -pci_resource_len(pdev, 2));
> - ggtt->mappable_end = resource_size(&ggtt->gmadr);
> + /* FIXME: We probably need to add do device_info or runtime_info */
> + if (!HAS_LMEM(dev_priv)) {
> + ggtt->gmadr =
> + (struct resource)
> DEFINE_RES_MEM(pci_resource_start(pdev, 2),
> +
> pci_resource_len(pdev, 2));
> + ggtt->mappable_end = resource_size(&ggtt->gmadr);
> + }
>
> err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
> if (!err)
> @@ -3220,15 +3225,18 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
> if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
> ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
>
> - if (!io_mapping_init_wc(&ggtt->iomap,
> - ggtt->gmadr.start,
> - ggtt->mappable_end)) {
> - ggtt->vm.cleanup(&ggtt->vm);
> - ret = -EIO;
> - goto out;
> - }
> + if (HAS_MAPPABLE_APERTURE(i915)) {
> + if (!io_mapping_init_wc(&ggtt->iomap,
if (ggtt->mappable_end) {
In this file, we are dealing with the low level details so I would
prefer less obfuscation.
> + ggtt->gmadr.start,
> + ggtt->mappable_end)) {
> + ggtt->vm.cleanup(&ggtt->vm);
> + ret = -EIO;
> + goto out;
> + }
>
> - ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
> + ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
> + ggtt->mappable_end);
> + }
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Re: [Intel-gfx] [PATCH v3 19/37] drm/i915: enumerate and init each supported region
Quoting Matthew Auld (2019-08-09 23:26:25)
> From: Abdiel Janulgue
>
> Nothing to enumerate yet...
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +--
> .../gpu/drm/i915/selftests/mock_gem_device.c | 6 ++
> 3 files changed, 72 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f7be8cee4709..3d7da69f0d1b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2436,6 +2436,9 @@ int __must_check i915_gem_evict_for_node(struct
> i915_address_space *vm,
> unsigned int flags);
> int i915_gem_evict_vm(struct i915_address_space *vm);
>
> +void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915);
> +int i915_gem_init_memory_regions(struct drm_i915_private *i915);
> +
> /* i915_gem_internal.c */
> struct drm_i915_gem_object *
> i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 83a02e773c58..a1dd3e7e1ad9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
Note this is not a GEM file. This is a hardware interface that I haven't
renamed due to expected conflicted...
> @@ -2713,6 +2713,66 @@ int i915_init_ggtt(struct drm_i915_private *i915)
> return 0;
> }
>
> +void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915)
> +{
> + int i;
> +
> + i915_gem_cleanup_stolen(i915);
> +
> + for (i = 0; i < ARRAY_SIZE(i915->regions); ++i) {
> + struct intel_memory_region *region = i915->regions[i];
> +
> + if (region)
> + intel_memory_region_destroy(region);
> + }
> +}
> +
> +int i915_gem_init_memory_regions(struct drm_i915_private *i915)
> +{
> + int err, i;
> +
> + /*
> +* Initialise stolen early so that we may reserve preallocated
> +* objects for the BIOS to KMS transition.
> +*/
> + /* XXX: stolen will become a region at some point */
> + err = i915_gem_init_stolen(i915);
> + if (err)
> + return err;
> +
> + for (i = 0; i < INTEL_MEMORY_UKNOWN; i++) {
> + struct intel_memory_region *mem = NULL;
> + u32 type;
> +
> + if (!HAS_REGION(i915, BIT(i)))
> + continue;
> +
> + type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
> + switch (type) {
> + default:
> + break;
> + }
> +
> + if (IS_ERR(mem)) {
> + err = PTR_ERR(mem);
> + DRM_ERROR("Failed to setup region(%d) type=%d\n",
> err, type);
> + goto out_cleanup;
> + }
> +
> + mem->id = intel_region_map[i];
> + mem->type = type;
> + mem->instance =
> MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
> +
> + i915->regions[i] = mem;
> + }
> +
> + return 0;
> +
> +out_cleanup:
> + i915_gem_cleanup_memory_regions(i915);
> + return err;
> +}
> +
> static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
> {
> struct drm_i915_private *i915 = ggtt->vm.i915;
> @@ -2754,6 +2814,8 @@ void i915_ggtt_driver_release(struct drm_i915_private
> *i915)
> {
> struct pagevec *pvec;
>
> + i915_gem_cleanup_memory_regions(i915);
What are you doing here? Just because ggtt and stolen were related?
-Chris
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Re: [Intel-gfx] [PATCH v3 16/37] drm/i915/lmem: support CPU relocations
Quoting Matthew Auld (2019-08-09 23:26:22)
> @@ -1017,10 +1020,14 @@ static void reloc_cache_reset(struct reloc_cache
> *cache)
> } else {
> struct i915_ggtt *ggtt = cache_to_ggtt(cache);
>
> - intel_gt_flush_ggtt_writes(ggtt->vm.gt);
> + if (!cache->is_lmem)
> + intel_gt_flush_ggtt_writes(ggtt->vm.gt);
I love an optimist. At the least you might need the wmb(). But we have
yet to see how many mistakes they've carried over into the new
implementation ;)
-Chris
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[Intel-gfx] [CI] drm/i915/selftests: move gpu-write-dw into utils
From: Matthew Auld
Using the gpu to write to some dword over a number of pages is rather
useful, and we already have two copies of such a thing, and we don't
want a third so move it to utils. There is probably some other stuff
also...
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 120 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 134 ++---
.../drm/i915/gem/selftests/igt_gem_utils.c| 135 ++
.../drm/i915/gem/selftests/igt_gem_utils.h| 16 +++
4 files changed, 169 insertions(+), 236 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 6cbd4a668c9a..8de83c6d81f5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -879,126 +879,22 @@ static int igt_mock_ppgtt_64K(void *arg)
return err;
}
-static struct i915_vma *
-gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
-{
- struct drm_i915_private *i915 = vma->vm->i915;
- const int gen = INTEL_GEN(i915);
- unsigned int count = vma->size >> PAGE_SHIFT;
- struct drm_i915_gem_object *obj;
- struct i915_vma *batch;
- unsigned int size;
- u32 *cmd;
- int n;
- int err;
-
- size = (1 + 4 * count) * sizeof(u32);
- size = round_up(size, PAGE_SIZE);
- obj = i915_gem_object_create_internal(i915, size);
- if (IS_ERR(obj))
- return ERR_CAST(obj);
-
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
- if (IS_ERR(cmd)) {
- err = PTR_ERR(cmd);
- goto err;
- }
-
- offset += vma->node.start;
-
- for (n = 0; n < count; n++) {
- if (gen >= 8) {
- *cmd++ = MI_STORE_DWORD_IMM_GEN4;
- *cmd++ = lower_32_bits(offset);
- *cmd++ = upper_32_bits(offset);
- *cmd++ = val;
- } else if (gen >= 4) {
- *cmd++ = MI_STORE_DWORD_IMM_GEN4 |
- (gen < 6 ? MI_USE_GGTT : 0);
- *cmd++ = 0;
- *cmd++ = offset;
- *cmd++ = val;
- } else {
- *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
- *cmd++ = offset;
- *cmd++ = val;
- }
-
- offset += PAGE_SIZE;
- }
-
- *cmd = MI_BATCH_BUFFER_END;
- intel_gt_chipset_flush(vma->vm->gt);
-
- i915_gem_object_unpin_map(obj);
-
- batch = i915_vma_instance(obj, vma->vm, NULL);
- if (IS_ERR(batch)) {
- err = PTR_ERR(batch);
- goto err;
- }
-
- err = i915_vma_pin(batch, 0, 0, PIN_USER);
- if (err)
- goto err;
-
- return batch;
-
-err:
- i915_gem_object_put(obj);
-
- return ERR_PTR(err);
-}
-
static int gpu_write(struct i915_vma *vma,
struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
-u32 dword,
-u32 value)
+u32 dw,
+u32 val)
{
- struct i915_request *rq;
- struct i915_vma *batch;
int err;
- GEM_BUG_ON(!intel_engine_can_store_dword(engine));
-
- batch = gpu_write_dw(vma, dword * sizeof(u32), value);
- if (IS_ERR(batch))
- return PTR_ERR(batch);
-
- rq = igt_request_alloc(ctx, engine);
- if (IS_ERR(rq)) {
- err = PTR_ERR(rq);
- goto err_batch;
- }
-
- i915_vma_lock(batch);
- err = i915_vma_move_to_active(batch, rq, 0);
- i915_vma_unlock(batch);
- if (err)
- goto err_request;
-
- i915_vma_lock(vma);
- err = i915_gem_object_set_to_gtt_domain(vma->obj, false);
- if (err == 0)
- err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
+ i915_gem_object_lock(vma->obj);
+ err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ i915_gem_object_unlock(vma->obj);
if (err)
- goto err_request;
-
- err = engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
- 0);
-err_request:
- if (err)
- i915_request_skip(rq, err);
- i915_request_add(rq);
-err_batch:
- i915_vma_unpin(batch);
- i915_vma_close(batch);
- i915_vma_put(batch);
+ return err;
- return err;
+ return igt_gpu_fill_dw(vma, ctx, engine, dw * sizeof(u32),
+ vma->size >> PAGE_SHIFT, val);
}
static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
diff --git a/drivers/gpu/drm/i915/gem/selftests
Re: [Intel-gfx] [PATCH v3 13/37] drm/i915/selftests: move gpu-write-dw into utils
Quoting Matthew Auld (2019-08-09 23:26:19) > Using the gpu to write to some dword over a number of pages is rather > useful, and we already have two copies of such a thing, and we don't > want a third so move it to utils. There is probably some other stuff > also... > > Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 12/37] drm/i915/blt: support copying objects
Quoting Matthew Auld (2019-08-09 23:26:18)
> +struct i915_vma *intel_emit_vma_copy_blt(struct intel_engine_pool_node **p,
> +struct intel_context *ce,
> +struct i915_vma *src,
> +struct i915_vma *dst)
> +{
> + struct drm_i915_private *i915 = ce->vm->i915;
> + const u32 block_size = S16_MAX * PAGE_SIZE;
> + struct intel_engine_pool_node *pool;
> + struct i915_vma *batch;
> + u64 src_offset, dst_offset;
> + u64 count;
> + u64 rem;
> + u32 size;
> + u32 *cmd;
> + int err;
> +
> + GEM_BUG_ON(src->size != dst->size);
> +
> + count = div_u64(dst->size, block_size);
> + size = (1 + 11 * count) * sizeof(u32);
> + size = round_up(size, PAGE_SIZE);
> + pool = intel_engine_pool_get(&ce->engine->pool, size);
> + if (IS_ERR(pool))
> + return ERR_CAST(pool);
> +
> + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC);
> + if (IS_ERR(cmd)) {
> + err = PTR_ERR(cmd);
> + goto out_put;
> + }
> +
> + rem = src->size;
> + src_offset = src->node.start;
> + dst_offset = dst->node.start;
> +
> + do {
> + u32 size = min_t(u64, rem, block_size);
> +
> + GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
> +
> + if (INTEL_GEN(i915) >= 9) {
> + *cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
> + *cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
> + *cmd++ = 0;
> + *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
> + *cmd++ = lower_32_bits(dst_offset);
> + *cmd++ = upper_32_bits(dst_offset);
> + *cmd++ = 0;
> + *cmd++ = PAGE_SIZE;
> + *cmd++ = lower_32_bits(src_offset);
> + *cmd++ = upper_32_bits(src_offset);
> + } else if (INTEL_GEN(i915) >= 8) {
> + *cmd++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 -
> 2);
> + *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
> + *cmd++ = 0;
> + *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
> + *cmd++ = lower_32_bits(dst_offset);
> + *cmd++ = upper_32_bits(dst_offset);
> + *cmd++ = 0;
> + *cmd++ = PAGE_SIZE;
> + *cmd++ = lower_32_bits(src_offset);
> + *cmd++ = upper_32_bits(src_offset);
> + } else {
> + *cmd++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
> + *cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
> + *cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE;
> + *cmd++ = dst_offset;
> + *cmd++ = PAGE_SIZE;
> + *cmd++ = src_offset;
> + }
> +
> + /* Allow ourselves to be preempted in between blocks. */
> + *cmd++ = MI_ARB_CHECK;
> +
> + src_offset += size;
> + dst_offset += size;
> + rem -= size;
> + } while (rem);
> +
> + *cmd = MI_BATCH_BUFFER_END;
> + intel_gt_chipset_flush(ce->vm->gt);
> +
> + i915_gem_object_unpin_map(pool->obj);
> +
> + batch = i915_vma_instance(pool->obj, ce->vm, NULL);
> + if (IS_ERR(batch)) {
> + err = PTR_ERR(batch);
> + goto out_put;
> + }
> +
> + err = i915_vma_pin(batch, 0, 0, PIN_USER);
> + if (unlikely(err))
> + goto out_put;
> +
> + *p = pool;
> + return batch;
> +
> +out_put:
> + intel_engine_pool_put(pool);
> + return ERR_PTR(err);
> +}
> +
> +int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
> +struct drm_i915_gem_object *dst,
> +struct intel_context *ce)
> +{
> + struct drm_gem_object *objs[] = { &src->base, &dst->base };
> + struct i915_address_space *vm = ce->vm;
> + struct intel_engine_pool_node *pool;
> + struct ww_acquire_ctx acquire;
> + struct i915_vma *vma_src, *vma_dst;
> + struct i915_vma *batch;
> + struct i915_request *rq;
> + int err;
> +
> + vma_src = i915_vma_instance(src, vm, NULL);
> + if (IS_ERR(vma_src))
> + return PTR_ERR(vma_src);
> +
> + err = i915_vma_pin(vma_src, 0, 0, PIN_USER);
> + if (unlikely(err))
> + return err;
> +
> + vma_dst = i915_vma_instance(dst, vm, NULL);
> + if (IS_ERR(vma_dst))
> + goto out_unpin_src;
> +
> + err = i915_vma_pin(vma_dst, 0, 0, PIN_USER);
> + if (unlikely(err))
> + goto out_
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Extend non readable mcr range
== Series Details == Series: drm/i915: Extend non readable mcr range URL : https://patchwork.freedesktop.org/series/64976/ State : success == Summary == CI Bug Log - changes from CI_DRM_6667_full -> Patchwork_13947_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13947_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl2/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-apl5/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@gem_ctx_isolat...@vcs1-dirty-create.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_schedule@preempt-self-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb8/igt@gem_exec_sched...@preempt-self-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-iclb1/igt@gem_exec_sched...@preempt-self-bsd.html * igt@kms_cursor_legacy@all-pipes-torture-bo: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb7/igt@kms_cursor_leg...@all-pipes-torture-bo.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-iclb7/igt@kms_cursor_leg...@all-pipes-torture-bo.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-glk2/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-glk9/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_plane@plane-panning-bottom-right-pipe-c-planes: - shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-pipe-c-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-apl3/igt@kms_pl...@plane-panning-bottom-right-pipe-c-planes.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_setmode@basic: - shard-apl: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl6/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-apl2/igt@kms_setm...@basic.html * igt@perf@blocking: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl7/igt@p...@blocking.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-skl8/igt@p...@blocking.html Possible fixes * igt@gem_ctx_isolation@vecs0-s3: - shard-apl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl5/igt@gem_ctx_isolat...@vecs0-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-apl2/igt@gem_ctx_isolat...@vecs0-s3.html * igt@gem_exec_blt@dumb-buf-min: - shard-apl: [INCOMPLETE][23] ([fdo#103927]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl1/igt@gem_exec_...@dumb-buf-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13947/shard-apl5/igt@gem_exec_...@dumb-buf-min.html * igt@gem_exec_schedule@preempt-contexts-bsd2: - shard-iclb: [SKIP][25] ([fdo#109276]) -> [PASS][26] +9 similar issues [25]: https://intel-gfx-ci.01.org/tree/dr
Re: [Intel-gfx] [PATCH v3 07/37] drm/i915: support creating LMEM objects
Quoting Matthew Auld (2019-08-09 23:26:13)
> @@ -1369,6 +1371,8 @@ struct drm_i915_private {
> */
> resource_size_t stolen_usable_size; /* Total size minus reserved
> ranges */
>
> + struct intel_memory_region *regions[INTEL_MEMORY_UKNOWN];
If there was ever an object to put inside i915_mm, this is sorely the
one!
> struct intel_uncore uncore;
>
> struct i915_virtual_gpu vgpu;
> @@ -2213,6 +2217,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_IPC(dev_priv)
> (INTEL_INFO(dev_priv)->display.has_ipc)
>
> #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
> +#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
>
> #define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
>
> diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
> b/drivers/gpu/drm/i915/intel_region_lmem.c
> new file mode 100644
> index ..ca906d1ff631
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_region_lmem.c
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_memory_region.h"
> +#include "gem/i915_gem_lmem.h"
> +#include "gem/i915_gem_region.h"
> +#include "intel_region_lmem.h"
> +
> +static struct drm_i915_gem_object *
> +lmem_create_object(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
> +{
> + struct drm_i915_private *i915 = mem->i915;
> + struct drm_i915_gem_object *obj;
> + unsigned int cache_level;
> +
> + if (flags & I915_BO_ALLOC_CONTIGUOUS)
> + size = roundup_pow_of_two(size);
? I would say that is not your decision to make. The flag says that the
allocation should one contiguous block.
> +
> + if (size > BIT(mem->mm.max_order) * mem->mm.chunk_size)
> + return ERR_PTR(-E2BIG);
> +
> + obj = i915_gem_object_alloc();
> + if (!obj)
> + return ERR_PTR(-ENOMEM);
> +
> + drm_gem_private_object_init(&i915->drm, &obj->base, size);
> + i915_gem_object_init(obj, &i915_gem_lmem_obj_ops);
> +
> + obj->read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
Is it really? Device local memory starts off inside the CPU cache?
> + cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE;
This seems to be a false generalisation. You should be asking the
memory region?
Besides, the current thinking is not to mark any object as cacheable
until the user commands it.
-Chris
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Re: [Intel-gfx] [PATCH v3 06/37] drm/i915: Add memory region information to device_info
Quoting Matthew Auld (2019-08-09 23:26:12)
> From: Abdiel Janulgue
>
> Exposes available regions for the platform. Shared memory will
> always be available.
>
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 39cdf4eac2a6..d947f7415861 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2212,6 +2212,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_IPC(dev_priv)
> (INTEL_INFO(dev_priv)->display.has_ipc)
>
> +#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
> +
> #define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
>
> /* Having GuC is not the same as using GuC */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 92e0c2e0954c..3166f38910f7 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -159,6 +159,8 @@ struct intel_device_info {
>
> unsigned int page_sizes; /* page sizes supported by the HW */
>
> + u32 memory_regions; /* regions supported by the HW */
> +
> u32 display_mmio_offset;
>
> u8 num_pipes;
If shared memory is always available, why is it absent?
Do you plan to distinguish scrubbed and zeroed system pages, private
pools to the process etc?
-Chris
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Re: [Intel-gfx] [PATCH v3 05/37] drm/i915/region: support volatile objects
Quoting Matthew Auld (2019-08-09 23:26:11) > Volatile objects are marked as DONTNEED while pinned, therefore once > unpinned the backing store can be discarded. Do we also have the concept of non-volatile backing store, e.g. shmemfs (non-volatile) vs stolen (volatile)? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 05/37] drm/i915/region: support volatile objects
Quoting Matthew Auld (2019-08-09 23:26:11) > Volatile objects are marked as DONTNEED while pinned, therefore once > unpinned the backing store can be discarded. > Signed-off-by: Matthew Auld > Signed-off-by: CQ Tang > Cc: Joonas Lahtinen > Cc: Abdiel Janulgue I think that's quite a nice generalisation. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 04/37] drm/i915/region: support continuous allocations
Quoting Matthew Auld (2019-08-09 23:26:10)
> Some objects may need to be allocated as a continuous block, thinking
> ahead the various kernel io_mapping interfaces seem to expect it.
But we could always use scattergather over top...
> @@ -98,10 +101,12 @@ i915_gem_object_get_pages_buddy(struct
> drm_i915_gem_object *obj)
> }
>
> void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
> - struct intel_memory_region *mem)
> + struct intel_memory_region *mem,
> + unsigned long flags)
> {
> INIT_LIST_HEAD(&obj->mm.blocks);
> obj->mm.region= mem;
> + obj->flags = flags;
>
> mutex_lock(&mem->obj_lock);
> list_add(&obj->mm.region_link, &mem->objects);
> @@ -125,6 +130,9 @@ i915_gem_object_create_region(struct intel_memory_region
> *mem,
> if (!mem)
> return ERR_PTR(-ENODEV);
>
> + if (flags & ~I915_BO_ALLOC_FLAGS)
> + return ERR_PTR(-EINVAL);
This is a programmer error not a user.
> +
> size = round_up(size, mem->min_page_size);
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Re: [Intel-gfx] [PATCH v3 03/37] drm/i915/region: support basic eviction
Quoting Matthew Auld (2019-08-09 23:26:09)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 6ff01a404346..8735dea74809 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1105,6 +1105,23 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void
> *data,
> !i915_gem_object_has_pages(obj))
> i915_gem_object_truncate(obj);
>
> + if (obj->mm.region) {
> + mutex_lock(&obj->mm.region->obj_lock);
> +
> + switch (obj->mm.madv) {
> + case I915_MADV_WILLNEED:
> + list_move(&obj->mm.region_link,
> + &obj->mm.region->objects);
> + break;
> + default:
> + list_move(&obj->mm.region_link,
> + &obj->mm.region->purgeable);
> + break;
> + }
> +
> + mutex_unlock(&obj->mm.region->obj_lock);
> + }
> +
> args->retained = obj->mm.madv != __I915_MADV_PURGED;
Little bit of an impedance mismatch, I hope this turns out fine when
everything is a memory region.
> mutex_unlock(&obj->mm.lock);
>
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
> b/drivers/gpu/drm/i915/intel_memory_region.c
> index ef12e462acb8..3a3caaadea1f 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -12,6 +12,51 @@ const u32 intel_region_map[] = {
> [INTEL_MEMORY_STOLEN] = BIT(INTEL_STOLEN + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> };
>
> +static int
> +intel_memory_region_evict(struct intel_memory_region *mem,
> + resource_size_t target,
> + unsigned int flags)
> +{
> + struct drm_i915_gem_object *obj;
> + resource_size_t found;
> + int err;
> +
> + err = 0;
> + found = 0;
> +
> + mutex_lock(&mem->obj_lock);
> + list_for_each_entry(obj, &mem->purgeable, mm.region_link) {
> + if (!i915_gem_object_has_pages(obj))
> + continue;
> +
> + if (READ_ONCE(obj->pin_global))
> + continue;
> +
> + if (atomic_read(&obj->bind_count))
> + continue;
> +
> + mutex_unlock(&mem->obj_lock);
> +
> + __i915_gem_object_put_pages(obj, I915_MM_SHRINKER);
So we don't really care about the object being bound then? As all we
care about is the page's pin_count.
So instead of obj->pin_global, obj->bind_bound, you just want
if (atomic_read(&obj->pages.pin_count))
continue;
as the quick check to see if it is worth preceding.
> + mutex_lock_nested(&obj->mm.lock, I915_MM_SHRINKER);
> + if (!i915_gem_object_has_pages(obj)) {
> + obj->mm.madv = __I915_MADV_PURGED;
> + found += obj->base.size;
> + }
> + mutex_unlock(&obj->mm.lock);
The locking here accomplishes what? You just want a boolean from
put_pages().
> +
> + if (found >= target)
> + return 0;
> +
> + mutex_lock(&mem->obj_lock);
> + }
> +
> + err = -ENOSPC;
> + mutex_unlock(&mem->obj_lock);
> + return err;
> +}
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/blt: don't assume pinned intel_context (rev2)
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/blt: don't assume pinned
intel_context (rev2)
URL : https://patchwork.freedesktop.org/series/65008/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6670 -> Patchwork_13959
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/
Known issues
Here are the changes found in Patchwork_13959 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][7] -> [FAIL][8] ([fdo#110627])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#109485])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][11] -> [DMESG-WARN][12] ([fdo#102614])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_cpu_reloc@basic:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-icl-u3/igt@gem_cpu_re...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/fi-icl-u3/igt@gem_cpu_re...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
Participating hosts (53 -> 47)
--
Additional (1): fi-bsw-n3050
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6670 -> Patchwork_13959
CI-20190529: 20190529
CI_DRM_6670: dca4867439f21c056afbde56cd4eb241b50f35d4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13959: dd5949a8dac17037d767b0813820960774e2d814 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dd5949a8dac1 drm/i915/blt: bump the size restriction
299d6e08343c drm/i915/blt: don't assume pinned intel_context
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13959/
___
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Re: [Intel-gfx] [PATCH v3 02/37] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-08-09 23:26:08)
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
> b/drivers/gpu/drm/i915/intel_memory_region.c
> new file mode 100644
> index ..ef12e462acb8
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -0,0 +1,175 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include "intel_memory_region.h"
> +#include "i915_drv.h"
> +
> +const u32 intel_region_map[] = {
> + [INTEL_MEMORY_SMEM] = BIT(INTEL_SMEM + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> + [INTEL_MEMORY_LMEM] = BIT(INTEL_LMEM + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> + [INTEL_MEMORY_STOLEN] = BIT(INTEL_STOLEN + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
This table isn't used? So the meaning of BIT(0) is impenetrable. Should
we defer adding the region_map until it is used?
-Chris
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Remove unused debugfs/i915_emon_status
== Series Details == Series: series starting with [1/2] drm/i915: Remove unused debugfs/i915_emon_status URL : https://patchwork.freedesktop.org/series/65007/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6670 -> Patchwork_13958 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13958 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13958, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13958: ### IGT changes ### Possible regressions * igt@i915_selftest@live_uncore: - fi-skl-iommu: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-iommu/igt@i915_selftest@live_uncore.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-skl-iommu/igt@i915_selftest@live_uncore.html - fi-skl-gvtdvm: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-gvtdvm/igt@i915_selftest@live_uncore.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-skl-gvtdvm/igt@i915_selftest@live_uncore.html - fi-kbl-x1275: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-x1275/igt@i915_selftest@live_uncore.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-kbl-x1275/igt@i915_selftest@live_uncore.html - fi-skl-guc: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-guc/igt@i915_selftest@live_uncore.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-skl-guc/igt@i915_selftest@live_uncore.html - fi-kbl-8809g: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-8809g/igt@i915_selftest@live_uncore.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-kbl-8809g/igt@i915_selftest@live_uncore.html - fi-kbl-7500u: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-kbl-7500u/igt@i915_selftest@live_uncore.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-kbl-7500u/igt@i915_selftest@live_uncore.html - fi-cfl-8700k: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-cfl-8700k/igt@i915_selftest@live_uncore.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-cfl-8700k/igt@i915_selftest@live_uncore.html - fi-skl-6600u: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-6600u/igt@i915_selftest@live_uncore.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-skl-6600u/igt@i915_selftest@live_uncore.html - fi-skl-lmem:[PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-lmem/igt@i915_selftest@live_uncore.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-skl-lmem/igt@i915_selftest@live_uncore.html - fi-cfl-guc: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-cfl-guc/igt@i915_selftest@live_uncore.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-cfl-guc/igt@i915_selftest@live_uncore.html - fi-skl-6770hq: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-6770hq/igt@i915_selftest@live_uncore.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-skl-6770hq/igt@i915_selftest@live_uncore.html - fi-skl-6700k2: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-6700k2/igt@i915_selftest@live_uncore.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-skl-6700k2/igt@i915_selftest@live_uncore.html - fi-skl-6260u: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-skl-6260u/igt@i915_selftest@live_uncore.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-skl-6260u/igt@i915_selftest@live_uncore.html - fi-cfl-8109u: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6670/fi-cfl-8109u/igt@i915_selftest@live_uncore.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13958/fi-cfl-8109u/igt@i915_selftest@live_uncore.html - fi-kbl-r: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/C
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with drm/i915: Check for a second VCS engine more carefully (rev2)
== Series Details == Series: series starting with drm/i915: Check for a second VCS engine more carefully (rev2) URL : https://patchwork.freedesktop.org/series/64948/ State : success == Summary == CI Bug Log - changes from CI_DRM_6667_full -> Patchwork_13946_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13946_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +17 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-iclb8/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@promotion-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_exec_sched...@promotion-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-iclb2/igt@gem_exec_sched...@promotion-bsd.html * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl7/igt@i915_pm_backlight@fade_with_suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-skl5/igt@i915_pm_backlight@fade_with_suspend.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl3/igt@i915_susp...@sysfs-reader.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-apl7/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb5/igt@kms_cursor_...@pipe-c-cursor-256x85-offscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-iclb7/igt@kms_cursor_...@pipe-c-cursor-256x85-offscreen.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#102670]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-hsw: [PASS][17] -> [FAIL][18] ([fdo#102887]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-hsw5/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-hsw5/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#105363]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl4/igt@kms_f...@flip-vs-expired-vblank.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13946/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [fdo#110403]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/2] drm/i915/blt: don't assume pinned intel_context (rev2)
== Series Details == Series: series starting with [CI,1/2] drm/i915/blt: don't assume pinned intel_context (rev2) URL : https://patchwork.freedesktop.org/series/65008/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/blt: don't assume pinned intel_context Okay! Commit: drm/i915/blt: bump the size restriction - +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:49:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/i915_gem_object_blt.c:49:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:29:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c:29:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:35:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:35:26: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: buddy allocator
Quoting Matthew Auld (2019-08-09 21:29:24) > Simple buddy allocator. We want to allocate properly aligned > power-of-two blocks to promote usage of huge-pages for the GTT, so 64K, > 2M and possibly even 1G. While we do support allocating stuff at a > specific offset, it is more intended for preallocating portions of the > address space, say for an initial framebuffer, for other uses drm_mm is > probably a much better fit. Anyway, hopefully this can all be thrown > away if we eventually move to having the core MM manage device memory. > > Signed-off-by: Matthew Auld > Cc: Chris Wilson It does what it says on the tin. Some debate over the overall motivation of the patch, but in regards to implementing a very simple buddy allocator that can stand amongst the many other allocations (that unfortunately are tied to their users, despite the kernel having many advanced allocators e.g. slub, none are available for managing a driver address block -- quite a number of drivers have their own drm_mm equivalents, including vmalloc!) it looks useful. I regard this as being more lib/ material than anything else. Maybe once we have the eviction schemes fleshed out, we can lift it to lib/ I would liked to have a bit more on the theory of operation (how) inside the buddy.c and some more of the why inside the buddy.h, especially for libification where potential users need to see if it fits, and I would like a suite of perf metrics (builtin performance tests, supplemental fragmentation statistics)... So I think there is a bit more work to be done to make it suitable for lib/, i.e. something that other people will want to use! Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/blt: bump the size restriction
From: Matthew Auld
As pointed out by Chris, with our current approach we are actually
limited to S16_MAX * PAGE_SIZE for our size when using the blt to clear
pages. Keeping things simple try to fix this by reducing the copy to a
sequence of S16_MAX * PAGE_SIZE blocks.
Reported-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
[ickle: hide the details of the engine pool inside emit_vma]
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 21 ++-
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 153 ++
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 17 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 16 +-
.../i915/gem/selftests/i915_gem_object_blt.c | 22 ++-
5 files changed, 180 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 08a84c940d8d..ac14677dd537 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -5,6 +5,8 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
@@ -157,6 +159,7 @@ static void clear_pages_worker(struct work_struct *work)
struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
struct i915_vma *vma = w->sleeve->vma;
struct i915_request *rq;
+ struct i915_vma *batch;
int err = w->dma.error;
if (unlikely(err))
@@ -176,10 +179,16 @@ static void clear_pages_worker(struct work_struct *work)
if (unlikely(err))
goto out_unlock;
+ batch = intel_emit_vma_fill_blt(w->ce, vma, w->value);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_unpin;
+ }
+
rq = intel_context_create_request(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- goto out_unpin;
+ goto out_batch;
}
/* There's no way the fence has signalled */
@@ -187,6 +196,10 @@ static void clear_pages_worker(struct work_struct *work)
clear_pages_dma_fence_cb))
GEM_BUG_ON(1);
+ err = intel_emit_vma_mark_active(batch, rq);
+ if (unlikely(err))
+ goto out_request;
+
if (w->ce->engine->emit_init_breadcrumb) {
err = w->ce->engine->emit_init_breadcrumb(rq);
if (unlikely(err))
@@ -202,7 +215,9 @@ static void clear_pages_worker(struct work_struct *work)
if (err)
goto out_request;
- err = intel_emit_vma_fill_blt(rq, vma, w->value);
+ err = w->ce->engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
out_request:
if (unlikely(err)) {
i915_request_skip(rq, err);
@@ -210,6 +225,8 @@ static void clear_pages_worker(struct work_struct *work)
}
i915_request_add(rq);
+out_batch:
+ intel_emit_vma_release(w->ce, batch);
out_unpin:
i915_vma_unpin(vma);
out_unlock:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index fa90c38c8b07..d3c2639558d1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -5,42 +5,118 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
+#include "gt/intel_gt.h"
#include "i915_gem_clflush.h"
#include "i915_gem_object_blt.h"
-int intel_emit_vma_fill_blt(struct i915_request *rq,
- struct i915_vma *vma,
- u32 value)
+struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
+struct i915_vma *vma,
+u32 value)
{
- u32 *cs;
-
- cs = intel_ring_begin(rq, 8);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- if (INTEL_GEN(rq->i915) >= 8) {
- *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
- *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
- *cs++ = 0;
- *cs++ = vma->size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
- *cs++ = value;
- *cs++ = MI_NOOP;
- } else {
- *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
- *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
- *cs++ = 0;
- *cs++ = vma->size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
- *cs++ = vma->node.start;
- *cs++ = value;
-
[Intel-gfx] [CI 1/2] drm/i915/blt: don't assume pinned intel_context
From: Matthew Auld
Currently we just pass in bcs0->engine_context so it matters not, but in
the future we may want to pass in something that is not a
kernel_context, so try to be a bit more generic.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_client_blt.c | 3 ++-
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index de6616bdb3a6..08a84c940d8d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "gt/intel_context.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
@@ -175,7 +176,7 @@ static void clear_pages_worker(struct work_struct *work)
if (unlikely(err))
goto out_unlock;
- rq = i915_request_create(w->ce);
+ rq = intel_context_create_request(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_unpin;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 837dd6636dd1..fa90c38c8b07 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "gt/intel_context.h"
#include "i915_gem_clflush.h"
#include "i915_gem_object_blt.h"
@@ -64,7 +65,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
i915_gem_object_unlock(obj);
}
- rq = i915_request_create(ce);
+ rq = intel_context_create_request(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_unpin;
--
2.23.0.rc1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] drm/i915/blt: bump the size restriction
From: Matthew Auld
As pointed out by Chris, with our current approach we are actually
limited to S16_MAX * PAGE_SIZE for our size when using the blt to clear
pages. Keeping things simple try to fix this by reducing the copy to a
sequence of S16_MAX * PAGE_SIZE blocks.
Reported-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
[ickle: hide the details of the engine pool inside emit_vma]
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 28 +++-
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 140 ++
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 27 +++-
.../i915/gem/selftests/i915_gem_client_blt.c | 16 +-
.../i915/gem/selftests/i915_gem_object_blt.c | 22 ++-
5 files changed, 184 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 08a84c940d8d..fc02e0157fc6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -5,6 +5,8 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
@@ -157,6 +159,7 @@ static void clear_pages_worker(struct work_struct *work)
struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
struct i915_vma *vma = w->sleeve->vma;
struct i915_request *rq;
+ struct i915_vma *batch;
int err = w->dma.error;
if (unlikely(err))
@@ -176,10 +179,16 @@ static void clear_pages_worker(struct work_struct *work)
if (unlikely(err))
goto out_unlock;
+ batch = intel_emit_vma_fill_blt(w->ce, vma, w->value);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_unpin;
+ }
+
rq = intel_context_create_request(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- goto out_unpin;
+ goto out_batch;
}
/* There's no way the fence has signalled */
@@ -187,6 +196,16 @@ static void clear_pages_worker(struct work_struct *work)
clear_pages_dma_fence_cb))
GEM_BUG_ON(1);
+ i915_vma_lock(batch);
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (unlikely(err))
+ goto out_request;
+
+ err = intel_emit_vma_mark_active(batch, rq);
+ if (unlikely(err))
+ goto out_request;
+
if (w->ce->engine->emit_init_breadcrumb) {
err = w->ce->engine->emit_init_breadcrumb(rq);
if (unlikely(err))
@@ -202,7 +221,9 @@ static void clear_pages_worker(struct work_struct *work)
if (err)
goto out_request;
- err = intel_emit_vma_fill_blt(rq, vma, w->value);
+ err = w->ce->engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
out_request:
if (unlikely(err)) {
i915_request_skip(rq, err);
@@ -210,6 +231,9 @@ static void clear_pages_worker(struct work_struct *work)
}
i915_request_add(rq);
+out_batch:
+ i915_vma_unpin(batch);
+ intel_emit_vma_release(w->ce, batch);
out_unpin:
i915_vma_unpin(vma);
out_unlock:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index fa90c38c8b07..1019e6952d43 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -5,42 +5,98 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
+#include "gt/intel_gt.h"
#include "i915_gem_clflush.h"
#include "i915_gem_object_blt.h"
-int intel_emit_vma_fill_blt(struct i915_request *rq,
- struct i915_vma *vma,
- u32 value)
+struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
+struct i915_vma *vma,
+u32 value)
{
- u32 *cs;
-
- cs = intel_ring_begin(rq, 8);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- if (INTEL_GEN(rq->i915) >= 8) {
- *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
- *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
- *cs++ = 0;
- *cs++ = vma->size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
- *cs++ = lower_32_bits(vma->node.start);
- *cs++ = upper_32_bits(vma->node.start);
- *cs++ = value;
- *cs++ = MI_NOOP;
- } else {
- *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
- *cs++ = BLT_DEPTH_32
[Intel-gfx] [PATCH 1/2] drm/i915: Remove unused debugfs/i915_emon_status
Before we start upon our great GT interrupt refactor, throw out the
cruft! In this case, it is an unloved debugfs showing the current ips
status, a fairly meaningless bunch of numbers that we are not checking.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 -
1 file changed, 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3d9cd97e1526..b616ba0e0da0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1442,30 +1442,6 @@ static int i915_sr_status(struct seq_file *m, void
*unused)
return 0;
}
-static int i915_emon_status(struct seq_file *m, void *unused)
-{
- struct drm_i915_private *i915 = node_to_i915(m->private);
- intel_wakeref_t wakeref;
-
- if (!IS_GEN(i915, 5))
- return -ENODEV;
-
- with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
- unsigned long temp, chipset, gfx;
-
- temp = i915_mch_val(i915);
- chipset = i915_chipset_val(i915);
- gfx = i915_gfx_val(i915);
-
- seq_printf(m, "GMCH temp: %ld\n", temp);
- seq_printf(m, "Chipset power: %ld\n", chipset);
- seq_printf(m, "GFX power: %ld\n", gfx);
- seq_printf(m, "Total power: %ld\n", chipset + gfx);
- }
-
- return 0;
-}
-
static int i915_ring_freq_table(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4349,7 +4325,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
- {"i915_emon_status", i915_emon_status, 0},
{"i915_ring_freq_table", i915_ring_freq_table, 0},
{"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
{"i915_fbc_status", i915_fbc_status, 0},
--
2.23.0.rc1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Verify the engine setup after recording the defaults
Check that the engine w/a persist after we performed a context switch and record those w/a into the default context state. Signed-off-by: Chris Wilson Cc: Andi Shyti --- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6ff01a404346..aff9885e443f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1486,11 +1486,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv) */ intel_init_clock_gating(dev_priv); - ret = intel_engines_verify_workarounds(dev_priv); + ret = __intel_engines_record_defaults(dev_priv); if (ret) goto err_gt; - ret = __intel_engines_record_defaults(dev_priv); + ret = intel_engines_verify_workarounds(dev_priv); if (ret) goto err_gt; -- 2.23.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Free the imported shmemfs file for phys objects
== Series Details == Series: drm/i915: Free the imported shmemfs file for phys objects URL : https://patchwork.freedesktop.org/series/64963/ State : success == Summary == CI Bug Log - changes from CI_DRM_6667_full -> Patchwork_13945_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13945_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_await@wide-all: - shard-iclb: [PASS][1] -> [FAIL][2] ([fdo#110946]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb6/igt@gem_exec_aw...@wide-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-iclb1/igt@gem_exec_aw...@wide-all.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +17 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-iclb5/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713] / [fdo#108569]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb1/igt@i915_selftest@live_hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-iclb8/igt@i915_selftest@live_hangcheck.html * igt@i915_suspend@forcewake: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-kbl1/igt@i915_susp...@forcewake.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-kbl4/igt@i915_susp...@forcewake.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-skl1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb3/igt@kms_frontbuffer_track...@fbc-rgb565-draw-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-iclb2/igt@kms_frontbuffer_track...@fbc-rgb565-draw-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713] / [fdo#110042]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-iclb3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-skl3/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_setmode@basic: - shard-apl: [PASS][23] -> [FAIL][24] ([fdo#99912]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl6/igt@kms_setm...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13945/shard-apl5/igt@kms_setm...@basic.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][25] -> [DMESG-WARN]
[Intel-gfx] ✓ Fi.CI.IGT: success for put_user_pages(): miscellaneous call sites
== Series Details == Series: put_user_pages(): miscellaneous call sites URL : https://patchwork.freedesktop.org/series/64952/ State : success == Summary == CI Bug Log - changes from CI_DRM_6667_full -> Patchwork_13944_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13944_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-apl2/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-kbl3/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-kbl2/igt@gem_soft...@noreloc-s3.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl10/igt@kms_fbcon_...@psr-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-skl1/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip@absolute-wf_vblank: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#103558] / [fdo#105602]) +25 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-kbl6/igt@kms_flip@absolute-wf_vblank.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-kbl6/igt@kms_flip@absolute-wf_vblank.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-rgb565-draw-pwrite.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-rgb565-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_setmode@basic: - shard-apl: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl6/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-apl6/igt@kms_setm...@basic.html * igt@prime_busy@hang-bsd2: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109276]) +22 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb1/igt@prime_b...@hang-bsd2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-iclb7/igt@prime_b...@hang-bsd2.html Possible fixes * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [SKIP][21] ([fdo#111325]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-iclb5/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_blt@dumb-buf-min: - shard-apl: [INCOMPLETE][23] ([fdo#103927]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-apl1/igt@gem_exec_...@dumb-buf-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13944/shard-apl8/igt@gem_exec_...@dumb-buf-min.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled: - shard-skl: [FAIL][25] ([fdo#103184] / [fdo#103232] / [fdo#108472]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6667/shard-skl1/igt@kms_draw_...@draw-method-xrgb2101010
