[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Switch intel_legacy_cursor_update() to intel_ types
== Series Details == Series: series starting with [1/5] drm/i915: Switch intel_legacy_cursor_update() to intel_ types URL : https://patchwork.freedesktop.org/series/67337/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6969_full -> Patchwork_14566_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14566_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14566_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14566_full: ### IGT changes ### Possible regressions * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-kbl7/igt@gem_persistent_rel...@forked-faulting-reloc-thrashing.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-kbl1/igt@gem_persistent_rel...@forked-faulting-reloc-thrashing.html Known issues Here are the changes found in Patchwork_14566_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-apl4/igt@gem_ctx_isolat...@bcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-apl7/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-iclb6/igt@gem_exec_as...@concurrent-writes-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-iclb2/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +14 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-iclb6/igt@gem_exec_sched...@preempt-queue-bsd2.html * igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-snb6/igt@kms_cursor_...@pipe-b-cursor-64x64-offscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-snb2/igt@kms_cursor_...@pipe-b-cursor-64x64-offscreen.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-glk8/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-glk6/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#109507]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-skl5/igt@kms_f...@flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-skl9/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-skl4/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14566/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@perf@polling: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#110728]) [21]: https://intel-gfx-ci
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v2,1/2] drm/i915: Move SAGV block time to dev_priv
== Series Details ==
Series: series starting with [CI,v2,1/2] drm/i915: Move SAGV block time to
dev_priv
URL : https://patchwork.freedesktop.org/series/67359/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14577
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14577/index.html
Known issues
Here are the changes found in Patchwork_14577 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-blb-e6850/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14577/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@kms_addfb_basic@no-handle:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u3/igt@kms_addfb_ba...@no-handle.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14577/fi-icl-u3/igt@kms_addfb_ba...@no-handle.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#109635 ])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14577/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14577/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u3/igt@gem_m...@basic-small-bo.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14577/fi-icl-u3/igt@gem_m...@basic-small-bo.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (53 -> 45)
--
Missing(8): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6973 -> Patchwork_14577
CI-20190529: 20190529
CI_DRM_6973: 7462c58bba0fb6e85bd380591c3fd86e298c0f95 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14577: d4f15098372ec98d1c16b0b2abce2cf53c75c0d6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d4f15098372e drm/i915/tgl: Read SAGV block time from PCODE
be9b536ad361 drm/i915: Move SAGV block time to dev_priv
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14577/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v2,1/2] drm/i915: Move SAGV block time to dev_priv
== Series Details ==
Series: series starting with [CI,v2,1/2] drm/i915: Move SAGV block time to
dev_priv
URL : https://patchwork.freedesktop.org/series/67359/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
be9b536ad361 drm/i915: Move SAGV block time to dev_priv
-:56: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#56: FILE: drivers/gpu/drm/i915/intel_pm.c:3657:
+ return;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 69 lines checked
d4f15098372e drm/i915/tgl: Read SAGV block time from PCODE
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Clear Color Support for TGL Render Decompression (rev3)
== Series Details == Series: Clear Color Support for TGL Render Decompression (rev3) URL : https://patchwork.freedesktop.org/series/66814/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14576 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14576 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14576, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14576: ### IGT changes ### Possible regressions * igt@kms_addfb_basic@bo-too-small-due-to-tiling: - fi-blb-e6850: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-blb-e6850/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-blb-e6850/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-kbl-x1275: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-x1275/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-x1275/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-apl-guc: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-apl-guc/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-apl-guc/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-bsw-kefka: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bsw-kefka/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-bsw-kefka/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-bdw-5557u: [PASS][9] -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bdw-5557u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-bdw-5557u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-bwr-2160:[PASS][11] -> [FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bwr-2160/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-bwr-2160/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-skl-6770hq: [PASS][13] -> [FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-6770hq/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-6770hq/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-skl-6600u: [PASS][15] -> [FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-6600u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-6600u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-kbl-guc: [PASS][17] -> [FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-guc/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-guc/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-kbl-8809g: [PASS][19] -> [FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-8809g/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-8809g/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-skl-lmem:[PASS][21] -> [FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-lmem/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-lmem/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-kbl-r: [PASS][23] -> [FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-r/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-kbl-r/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-skl-6260u: [PASS][25] -> [FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-skl-6260u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14576/fi-skl-6260u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-byt-n2820: [PASS][27
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev3)
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev3)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fa405794ca6b drm/framebuffer: Format modifier for Intel Gen-12 render
compression
dc89777e0306 drm/i915: Use intel_tile_height() instead of re-implementing
a54ed04cc4d8 drm/i915: Move CCS stride alignment W/A inside
intel_fb_stride_alignment
9d840b1281fb drm/i915/tgl: Gen-12 render decompression
d752e75805e5 drm/i915: Extract framebufer CCS offset checks into a function
8f42a26a0fb0 drm/framebuffer: Format modifier for Intel Gen-12 media compression
3db40490ca8f drm/i915: Skip rotated offset adjustment for unsupported modifiers
32f56db73bf2 drm/fb: Extend format_info member arrays to handle four planes
6e5a61ea78da Gen-12 display can decompress surfaces compressed by the media
engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2704:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct
drm_framebuffer *fb, int color_plane)
-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2711:
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2,
16}, .vsub = {1, 32, 2, 32} };
total: 0 errors, 3 warnings, 0 checks, 509 lines checked
f872ae0f29f7 drm/framebuffer/tgl: Format modifier for Intel Gen 12 render
compression with Clear Color
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#7:
Gen12 display can decompress surfaces compressed by render engine with Clear
Color, add
total: 0 errors, 1 warnings, 0 checks, 17 lines checked
82473beafe08 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
-:251: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible
side-effects?
#251: FILE: drivers/gpu/drm/i915/i915_reg.h:6782:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 198 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Add microcontrollers documentation section
== Series Details ==
Series: series starting with [1/3] drm/i915: Add microcontrollers documentation
section
URL : https://patchwork.freedesktop.org/series/67356/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14575
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14575 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14575, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14575:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-kbl-r: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14575 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927] /
[fdo#111381])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-blb-e6850/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#109635 ] / [fdo#110387])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111045] / [fdo#111096])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-icl-u3: [PASS][11] -> [DMESG-WARN][12] ([fdo#107724]) +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u3/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-icl-u3/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html
Possible fixes
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u3/igt@gem_m...@basic-small-bo.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-icl-u3/igt@gem_m...@basic-small-bo.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
Participating hosts (53 -> 45)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6973 -> Patchwork_14575
CI-20190529: 20190529
CI_DRM_6973: 7462c58bba0fb6e85bd380591c3fd86e298c0f95 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14575: 61eab783ca84603326cd35cda16c3f4fcb9365ff @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
61eab783ca84 drm/i915/huc: improve documentation
1b0401f1d
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Update references to previously renamed files (rev2)
== Series Details == Series: drm/i915: Update references to previously renamed files (rev2) URL : https://patchwork.freedesktop.org/series/67295/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6967_full -> Patchwork_14565_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14565_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14565_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14565_full: ### IGT changes ### Possible regressions * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-glk6/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-glk4/igt@kms_f...@2x-modeset-vs-vblank-race-interruptible.html Known issues Here are the changes found in Patchwork_14565_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@reset-stress: - shard-snb: [PASS][3] -> [FAIL][4] ([fdo#109661]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-snb1/igt@gem_...@reset-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-snb6/igt@gem_...@reset-stress.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-apl5/igt@gem_workarou...@suspend-resume-context.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-apl6/igt@gem_workarou...@suspend-resume-context.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-skl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-badstride: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-iclb2/igt@kms_frontbuffer_track...@fbc-badstride.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-iclb6/igt@kms_frontbuffer_track...@fbc-badstride.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-skl4/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#108341]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-iclb2/igt@kms_psr@no_drrs.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html * igt@kms_setmode@basic: - shard-hsw: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-hsw1/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-hsw2/igt@kms_setm...@basic.html * igt@perf@blocking: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-skl8/igt@p...@blocking.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-skl3/igt@p...@blocking.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109276]) +17 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-iclb2/igt@prime_v...@fence-wait-bsd2.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14565/shard-iclb3/igt@prime_v...@fence-wait-bsd2.html Possible fixes * igt@drm_read@invalid-buffer: - shard-snb: [SKIP][23] ([fdo#109271]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.or
[Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..6a45df9dad9c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8869,6 +8869,7 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
#define GEN6_PCODE_DATA_MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b413a7f3bc5d..13721ba44013 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
static void
skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ u32 val = 0;
+ int ret;
+
+ ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+&val, NULL);
+ if (!ret) {
+ dev_priv->sagv_block_time_us = val;
+ return;
+ }
+
+ DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+ } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
--
2.22.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI v2 1/2] drm/i915: Move SAGV block time to dev_priv
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.
v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
---
Resending for CI, as I evidently confused Patchwork...
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 33 -
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 337d8306416a..87a835a0210b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1579,6 +1579,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
+ int sagv_block_time_us;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..b413a7f3bc5d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+ if (IS_GEN(dev_priv, 11)) {
+ dev_priv->sagv_block_time_us = 10;
+ return;
+ } else if (IS_GEN(dev_priv, 10)) {
+ dev_priv->sagv_block_time_us = 20;
+ return;
+ } else if (IS_GEN(dev_priv, 9)) {
+ dev_priv->sagv_block_time_us = 30;
+ return;
+ } else {
+ MISSING_CASE(INTEL_GEN(dev_priv));
+ }
+
+ /* Default to an unusable block time */
+ dev_priv->sagv_block_time_us = 1000;
+}
+
/*
* SAGV dynamically adjusts the system agent voltage and clock frequencies
* depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
- int sagv_block_time_us;
if (!intel_has_sagv(dev_priv))
return false;
- if (IS_GEN(dev_priv, 9))
- sagv_block_time_us = 30;
- else if (IS_GEN(dev_priv, 10))
- sagv_block_time_us = 20;
- else
- sagv_block_time_us = 10;
-
/*
* If there are no active CRTCs, no additional checks need be performed
*/
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us)
return false;
}
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
+ if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+ skl_setup_sagv_block_time(dev_priv);
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
--
2.22.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Extract GT render sleep (rc6) management (rev2)
== Series Details == Series: drm/i915: Extract GT render sleep (rc6) management (rev2) URL : https://patchwork.freedesktop.org/series/66937/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6967_full -> Patchwork_14564_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14564_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14564_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14564_full: ### IGT changes ### Possible regressions * igt@i915_selftest@mock_timelines: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-skl2/igt@i915_selftest@mock_timelines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-skl2/igt@i915_selftest@mock_timelines.html * igt@runner@aborted: - shard-kbl: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-kbl1/igt@run...@aborted.html - shard-apl: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-apl1/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_14564_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-contexts-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +21 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-iclb2/igt@gem_exec_sched...@preempt-contexts-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-iclb8/igt@gem_exec_sched...@preempt-contexts-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@i915_selftest@mock_timelines: - shard-glk: [PASS][9] -> [INCOMPLETE][10] ([fdo#103359] / [k.org#198133]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-glk7/igt@i915_selftest@mock_timelines.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-glk4/igt@i915_selftest@mock_timelines.html - shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-hsw2/igt@i915_selftest@mock_timelines.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-hsw4/igt@i915_selftest@mock_timelines.html - shard-kbl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103665]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-kbl1/igt@i915_selftest@mock_timelines.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-kbl1/igt@i915_selftest@mock_timelines.html - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-iclb2/igt@i915_selftest@mock_timelines.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-iclb8/igt@i915_selftest@mock_timelines.html - shard-snb: [PASS][17] -> [INCOMPLETE][18] ([fdo#105411]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-snb1/igt@i915_selftest@mock_timelines.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-snb7/igt@i915_selftest@mock_timelines.html - shard-apl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103927]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-apl1/igt@i915_selftest@mock_timelines.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-apl1/igt@i915_selftest@mock_timelines.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-kbl4/igt@kms_frontbuffer_track...@fbc-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14564/shard-kbl1/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6967/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [24]: htt
[Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjala
Cc: Shashank Sharma
Cc: Rafael Antognolli
Cc: Matt Roper
Cc: Nanley G Chery
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++
.../drm/i915/display/intel_display_types.h| 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4971c296f951..822237e98f00 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[]
= {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels
in
+ * the main surface. Additional surface is used to pass the Clear Color
+ * structure for the driver to program the DE.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@
[Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv
In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.
v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
---
Ville - with the amount of v1..v2 change in this first patch, I wasn't
comfortable applying your R-b, could you take another look? Patch 2 just
has the trivial changes you suggested, so I kept that one.
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 33 -
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 337d8306416a..87a835a0210b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1579,6 +1579,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
+ int sagv_block_time_us;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..b413a7f3bc5d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+ if (IS_GEN(dev_priv, 11)) {
+ dev_priv->sagv_block_time_us = 10;
+ return;
+ } else if (IS_GEN(dev_priv, 10)) {
+ dev_priv->sagv_block_time_us = 20;
+ return;
+ } else if (IS_GEN(dev_priv, 9)) {
+ dev_priv->sagv_block_time_us = 30;
+ return;
+ } else {
+ MISSING_CASE(INTEL_GEN(dev_priv));
+ }
+
+ /* Default to an unusable block time */
+ dev_priv->sagv_block_time_us = 1000;
+}
+
/*
* SAGV dynamically adjusts the system agent voltage and clock frequencies
* depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
- int sagv_block_time_us;
if (!intel_has_sagv(dev_priv))
return false;
- if (IS_GEN(dev_priv, 9))
- sagv_block_time_us = 30;
- else if (IS_GEN(dev_priv, 10))
- sagv_block_time_us = 20;
- else
- sagv_block_time_us = 10;
-
/*
* If there are no active CRTCs, no additional checks need be performed
*/
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us)
return false;
}
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
+ if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+ skl_setup_sagv_block_time(dev_priv);
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
--
2.22.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE
Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.
BSpec: 49326
v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Cc: Lucas De Marchi
Signed-off-by: James Ausmus
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..6a45df9dad9c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8869,6 +8869,7 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
#define GEN6_PCODE_DATA_MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b413a7f3bc5d..13721ba44013 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
static void
skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ u32 val = 0;
+ int ret;
+
+ ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+&val, NULL);
+ if (!ret) {
+ dev_priv->sagv_block_time_us = val;
+ return;
+ }
+
+ DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+ } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
--
2.22.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Pass intel_gt to has-reset?
== Series Details ==
Series: series starting with [1/3] drm/i915: Pass intel_gt to has-reset?
URL : https://patchwork.freedesktop.org/series/67355/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6971 -> Patchwork_14574
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14574/index.html
Known issues
Here are the changes found in Patchwork_14574 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14574/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-u3/igt@gem_mmap_...@basic-write.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14574/fi-icl-u3/igt@gem_mmap_...@basic-write.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][5] -> [DMESG-WARN][6] ([fdo#102614])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14574/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-cml-s}: [INCOMPLETE][7] ([fdo#110566]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-cml-s/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14574/fi-cml-s/igt@gem_ctx_cre...@basic-files.html
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14574/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-dsi}: [DMESG-FAIL][11] ([fdo#111678]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14574/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
Participating hosts (50 -> 45)
--
Additional (2): fi-bsw-kefka fi-icl-guc
Missing(7): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6971 -> Patchwork_14574
CI-20190529: 20190529
CI_DRM_6971: b891ecf6856b90013c667c0d8becb7edb2f0c0d1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14574: 70a7be14c49994ad76e4d80abe0af7bb9121e04c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
70a7be14c499 drm/i915/selftests: Provide a mock GPU reset routine
6cd52efc03c7 drm/i915/selftests: Distinguish mock device from no wakeref
1a9dfddf63c4 drm/i915: Pass intel_gt to has-reset?
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14574/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Do not try to sanitize mock HW
== Series Details ==
Series: drm/i915/selftests: Do not try to sanitize mock HW
URL : https://patchwork.freedesktop.org/series/67354/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6971 -> Patchwork_14573
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/index.html
Known issues
Here are the changes found in Patchwork_14573 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#110566] /
[fdo#111381])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-cml-u2/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/fi-cml-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
* igt@gem_mmap_gtt@basic-write-gtt:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][7] -> [FAIL][8] ([fdo#103167])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [PASS][9] -> [INCOMPLETE][10] ([fdo#107718])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u2}:[INCOMPLETE][11] ([fdo#111735]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-dsi}: [DMESG-FAIL][15] ([fdo#111678]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14573/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (50 -> 45)
--
Additional (2): fi-bsw-kefka fi-icl-guc
Missing(7): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6971 -> Patchwork_14573
CI-20190529: 20190529
CI_DRM_6971: b891ecf6856b90013c667c0d8becb7edb2f0c0d1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14573: 9e015ed6
Re: [Intel-gfx] [PATCH 3/3] drm/i915/selftests: Provide a mock GPU reset routine
On Fri, Sep 27, 2019 at 10:17:49PM +0100, Chris Wilson wrote: > For those mock tests that may wish to pretend triggering a GPU reset and > processing the cleanup. > > Signed-off-by: Chris Wilson > Cc: Andi Shyti looks better! Thanks! Reviewed-by: Andi Shyti Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915/selftests: Distinguish mock device from no wakeref
On Fri, Sep 27, 2019 at 10:17:48PM +0100, Chris Wilson wrote:
> On systems that have no runtime-pm, we mark the wakeref as being -1. We
> therefore cannot use that value for the mock-gt indicator, so opt for
> -ENODEV instead. The wakeref should never be an error value -- one
> hopes!
-1 (EPERM) is an error value as well, -ENODEV looks cleaner and
more appropriate, in any case:
Reviewed-by: Andi Shyti
Thanks,
Andi
> Signed-off-by: Chris Wilson
> Cc: Andi Shyti
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.h| 2 +-
> drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +--
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> index ab794e853356..997770d3a968 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> @@ -57,7 +57,7 @@ int intel_gt_runtime_resume(struct intel_gt *gt);
>
> static inline bool is_mock_gt(const struct intel_gt *gt)
> {
> - return I915_SELFTEST_ONLY(gt->awake == -1);
> + return I915_SELFTEST_ONLY(gt->awake == -ENODEV);
> }
>
> #endif /* INTEL_GT_PM_H */
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 91f15fa728cd..2448067822af 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -182,6 +182,7 @@ struct drm_i915_private *mock_gem_device(void)
> i915_gem_init__mm(i915);
> intel_gt_init_early(&i915->gt, i915);
> atomic_inc(&i915->gt.wakeref.count); /* disable; no hw support */
> + i915->gt.awake = -ENODEV;
>
> i915->wq = alloc_ordered_workqueue("mock", 0);
> if (!i915->wq)
> @@ -192,8 +193,6 @@ struct drm_i915_private *mock_gem_device(void)
> INIT_DELAYED_WORK(&i915->gem.retire_work, mock_retire_work_handler);
> INIT_WORK(&i915->gem.idle_work, mock_idle_work_handler);
>
> - i915->gt.awake = -1;
> -
> intel_timelines_init(i915);
>
> mutex_lock(&i915->drm.struct_mutex);
> --
> 2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Pass intel_gt to has-reset?
Hi Chris, On Fri, Sep 27, 2019 at 10:17:47PM +0100, Chris Wilson wrote: > As we execute GPU results on a gt/ basis, and use the intel_gt as the > primary for all other reset functions, also use it for the has-reset? > predicated. Gradually simplifying the churn of pointers. > > Signed-off-by: Chris Wilson > Cc: Andi Shyti Thanks! Reviewed-by: Andi Shyti Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: Add microcontrollers documentation section
To better organize the information, add a microcontrollers section and move/link the GuC, HuC and DMC documentation under it. Also add a small intro. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko --- Documentation/gpu/i915.rst | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 465779670fd4..f1bae7867045 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -415,6 +415,15 @@ Object Tiling IOCTLs .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c :doc: buffer object tiling +Microcontrollers + + +Starting from gen9, three microcontrollers are available on the HW: the +graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the +display microcontroller (DMC). The driver is responsible for loading the +firmwares on the microcontrollers; the GuC and HuC firmwares are transferred +to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. + WOPCM - @@ -454,6 +463,15 @@ GuC Address Space .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c :doc: GuC Address Space +HuC +--- +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c + :doc: HuC Firmware + +DMC +--- +See `CSR firmware support for DMC`_ + Tracing === -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/guc: improve documentation
Add a short description of what we expect from GuC and some minor
improvements to existing documentation. Also remove a comment about a
difference between GuC and HuC that is not true anymore.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Matthew Brost
---
Documentation/gpu/i915.rst| 22 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 26 +--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 3 ---
4 files changed, 44 insertions(+), 13 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index f1bae7867045..357e9dfa7de1 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -436,12 +436,24 @@ WOPCM Layout
GuC
---
-Firmware Layout
-~~~
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
+ :doc: GuC
+
+GuC Firmware Layout
+~~~
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
:doc: Firmware Layout
+GuC Memory Management
+~
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
+ :doc: GuC Memory Management
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
+ :functions: intel_guc_allocate_vma
+
+
GuC-specific firmware loader
@@ -457,12 +469,6 @@ GuC-based command submission
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
:internal:
-GuC Address Space
-~
-
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
- :doc: GuC Address Space
-
HuC
---
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 249c747e9756..c6f018099fd0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -9,6 +9,22 @@
#include "intel_guc_submission.h"
#include "i915_drv.h"
+/**
+ * DOC: GuC
+ *
+ * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC
is
+ * designed to offload some of the functionality usually run on the host
driver;
+ * currently the main operations it can take care of are:
+ *
+ * - Authentication of the HuC, which is required to fully enable HuC usage.
+ * - Low latency graphics context scheduling (a.k.a. GuC submission).
+ * - GT Power management.
+ *
+ * The enable_guc module parameter can be used to select which of those
+ * operations to enable within GuC. Note that not all the operations are
+ * supported on all gen9+ platforms.
+ */
+
static void gen8_guc_raise_irq(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -548,9 +564,15 @@ int intel_guc_resume(struct intel_guc *guc)
}
/**
- * DOC: GuC Address Space
+ * DOC: GuC Memory Management
*
- * The layout of GuC address space is shown below:
+ * GuC can't allocate any memory for its own usage, so all the allocations must
+ * be handled by the host driver. GuC accesses the memory via the GGTT, with
the
+ * exception of the top and bottom parts of the 4GB address space, which are
+ * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM)
+ * or other parts of the HW. The driver must take care not to place objects
that
+ * the GuC is going to access in these reserved ranges. The layout of the GuC
+ * address space is shown below:
*
* ::
*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f325d3dd564f..849a44add424 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -29,6 +29,12 @@ enum {
/**
* DOC: GuC-based command submission
*
+ * IMPORTANT NOTE: GuC submission is currently not supported in i915. The GuC
+ * firmware is moving to an updated submission interface and we plan to
+ * turn submission back on when that lands. The below documentation (and
related
+ * code) matches the old submission model and will be updated as part of the
+ * upgrade to the new flow.
+ *
* GuC client:
* A intel_guc_client refers to a submission path through GuC. Currently, there
* is only one client, which is charged with all submissions to the GuC. This
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
index f8f6c91a0df6..029214cdedd5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -39,9 +39,6 @@
* 3. Length info of each component can be found in header, in dwords.
* 4. Modulus and exponent key are not required by driver. They may not appear
*in fw. So driver will load a truncated firmware in this case.
- *
- * The only difference between GuC and HuC firmwares is how the version
- * information is saved.
*/
struct uc_css_header {
--
2.23.0
___
Intel-gfx mailing list
Intel-gf
[Intel-gfx] [PATCH 3/3] drm/i915/huc: improve documentation
Better explain the usage of the microcontroller and what i915 is
responsible of. While at it, fix the documentation for the auth
function, which doesn't do any pinning anymore.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
Documentation/gpu/i915.rst| 10 --
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 19 +++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 ---
3 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 357e9dfa7de1..bfb64337db66 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -471,8 +471,14 @@ GuC-based command submission
HuC
---
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
- :doc: HuC Firmware
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+ :doc: HuC
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+ :functions: intel_huc_auth
+
+HuC Firmware Layout
+~~~
+The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
DMC
---
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index d4625c97b4f9..6e10fe898c90 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -9,6 +9,18 @@
#include "intel_huc.h"
#include "i915_drv.h"
+/**
+ * DOC: HuC
+ *
+ * The HuC is a dedicated microcontroller for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can directly use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ * The kernel driver is only responsible for loading the HuC firmware and
+ * triggering its security authentication, which is performed by the GuC. For
+ * The GuC to correctly perform the authentication, the HuC binary must be
+ * loaded before the GuC one.
+ */
+
void intel_huc_init_early(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
@@ -118,10 +130,9 @@ void intel_huc_fini(struct intel_huc *huc)
*
* Called after HuC and GuC firmware loading during intel_uc_init_hw().
*
- * This function pins HuC firmware image object into GGTT.
- * Then it invokes GuC action to authenticate passing the offset to RSA
- * signature through intel_guc_auth_huc(). It then waits for 50ms for
- * firmware verification ACK and unpins the object.
+ * This function invokes the GuC action to authenticate the HuC firmware,
+ * passing the offset of the RSA signature to intel_guc_auth_huc(). It then
+ * waits for up to 50ms for firmware verification ACK.
*/
int intel_huc_auth(struct intel_huc *huc)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 74602487ed67..d654340d4d03 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -7,21 +7,6 @@
#include "intel_huc_fw.h"
#include "i915_drv.h"
-/**
- * DOC: HuC Firmware
- *
- * Motivation:
- * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
- * Efficiency Video Coding) operations. Userspace can use the firmware
- * capabilities by adding HuC specific commands to batch buffers.
- *
- * Implementation:
- * The same firmware loader is used as the GuC. However, the actual
- * loading to HW is deferred until GEM initialization is done.
- *
- * Note that HuC firmware loading must be done before GuC loading.
- */
-
/**
* intel_huc_fw_init_early() - initializes HuC firmware struct
* @huc: intel_huc struct
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Update H2G enable logging action definition
On 9/27/19 11:04 AM, Robert M. Fosha wrote:
GuC enable logging H2G action definition changed some time ago from 0xE000
to 0x40. All current GuC FW blobs use this definition, so fix the action
definition in driver to match.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
Reviewed-by: Daniele Ceraolo Spurio
We really need to add some proper testing for the guc log relay,
otherwise we'll only notice bugs in there (like this one) when we need
to use the relay for debug of other issues.
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 1d3cdd67ca2f..a26a85d50209 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -548,6 +548,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
+ INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,
INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
@@ -556,7 +557,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
- INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
INTEL_GUC_ACTION_LIMIT
};
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: Pass intel_gt to has-reset?
As we execute GPU results on a gt/ basis, and use the intel_gt as the
primary for all other reset functions, also use it for the has-reset?
predicated. Gradually simplifying the churn of pointers.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 21 ---
drivers/gpu/drm/i915/gt/intel_reset.h | 5 ++---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 12 +--
drivers/gpu/drm/i915/gt/selftest_lrc.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_reset.c | 4 ++--
.../gpu/drm/i915/gt/selftest_workarounds.c| 8 +++
drivers/gpu/drm/i915/i915_getparam.c | 4 ++--
8 files changed, 31 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bbe088b9d057..f1328c08f4ad 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4273,7 +4273,7 @@ __intel_display_resume(struct drm_device *dev,
static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
{
return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
- intel_has_gpu_reset(dev_priv));
+ intel_has_gpu_reset(&dev_priv->gt));
}
void intel_prepare_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index d08226f5bea5..ea5cf3a28fbe 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -546,8 +546,10 @@ typedef int (*reset_func)(struct intel_gt *,
intel_engine_mask_t engine_mask,
unsigned int retry);
-static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
+static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
+
if (INTEL_GEN(i915) >= 8)
return gen8_reset_engines;
else if (INTEL_GEN(i915) >= 6)
@@ -571,7 +573,7 @@ int __intel_gt_reset(struct intel_gt *gt,
intel_engine_mask_t engine_mask)
int ret = -ETIMEDOUT;
int retry;
- reset = intel_get_gpu_reset(gt->i915);
+ reset = intel_get_gpu_reset(gt);
if (!reset)
return -ENODEV;
@@ -591,17 +593,20 @@ int __intel_gt_reset(struct intel_gt *gt,
intel_engine_mask_t engine_mask)
return ret;
}
-bool intel_has_gpu_reset(struct drm_i915_private *i915)
+bool intel_has_gpu_reset(const struct intel_gt *gt)
{
if (!i915_modparams.reset)
return NULL;
- return intel_get_gpu_reset(i915);
+ return intel_get_gpu_reset(gt);
}
-bool intel_has_reset_engine(struct drm_i915_private *i915)
+bool intel_has_reset_engine(const struct intel_gt *gt)
{
- return INTEL_INFO(i915)->has_reset_engine && i915_modparams.reset >= 2;
+ if (i915_modparams.reset < 2)
+ return false;
+
+ return INTEL_INFO(gt->i915)->has_reset_engine;
}
int intel_reset_guc(struct intel_gt *gt)
@@ -958,7 +963,7 @@ void intel_gt_reset(struct intel_gt *gt,
awake = reset_prepare(gt);
- if (!intel_has_gpu_reset(gt->i915)) {
+ if (!intel_has_gpu_reset(gt)) {
if (i915_modparams.reset)
dev_err(gt->i915->drm.dev, "GPU reset not supported\n");
else
@@ -1179,7 +1184,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
* Try engine reset when available. We fall back to full reset if
* single reset fails.
*/
- if (intel_has_reset_engine(gt->i915) && !intel_gt_is_wedged(gt)) {
+ if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h
b/drivers/gpu/drm/i915/gt/intel_reset.h
index 0b6ff1ee7f06..8e8d5f761166 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -14,7 +14,6 @@
#include "intel_engine_types.h"
#include "intel_reset_types.h"
-struct drm_i915_private;
struct i915_request;
struct intel_engine_cs;
struct intel_gt;
@@ -80,7 +79,7 @@ static inline bool __intel_reset_failed(const struct
intel_reset *reset)
return unlikely(test_bit(I915_WEDGED, &reset->flags));
}
-bool intel_has_gpu_reset(struct drm_i915_private *i915);
-bool intel_has_reset_engine(struct drm_i915_private *i915);
+bool intel_has_gpu_reset(const struct intel_gt *gt);
+bool intel_has_reset_engine(const struct intel_gt *gt);
#endif /* I915_RESET_H */
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index a0098fc35921..9c0c84
[Intel-gfx] [PATCH 2/3] drm/i915/selftests: Distinguish mock device from no wakeref
On systems that have no runtime-pm, we mark the wakeref as being -1. We
therefore cannot use that value for the mock-gt indicator, so opt for
-ENODEV instead. The wakeref should never be an error value -- one
hopes!
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_pm.h| 2 +-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index ab794e853356..997770d3a968 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -57,7 +57,7 @@ int intel_gt_runtime_resume(struct intel_gt *gt);
static inline bool is_mock_gt(const struct intel_gt *gt)
{
- return I915_SELFTEST_ONLY(gt->awake == -1);
+ return I915_SELFTEST_ONLY(gt->awake == -ENODEV);
}
#endif /* INTEL_GT_PM_H */
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 91f15fa728cd..2448067822af 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -182,6 +182,7 @@ struct drm_i915_private *mock_gem_device(void)
i915_gem_init__mm(i915);
intel_gt_init_early(&i915->gt, i915);
atomic_inc(&i915->gt.wakeref.count); /* disable; no hw support */
+ i915->gt.awake = -ENODEV;
i915->wq = alloc_ordered_workqueue("mock", 0);
if (!i915->wq)
@@ -192,8 +193,6 @@ struct drm_i915_private *mock_gem_device(void)
INIT_DELAYED_WORK(&i915->gem.retire_work, mock_retire_work_handler);
INIT_WORK(&i915->gem.idle_work, mock_idle_work_handler);
- i915->gt.awake = -1;
-
intel_timelines_init(i915);
mutex_lock(&i915->drm.struct_mutex);
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915/selftests: Provide a mock GPU reset routine
For those mock tests that may wish to pretend triggering a GPU reset and
processing the cleanup.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_reset.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index ea5cf3a28fbe..76938fa3a1b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -542,6 +542,13 @@ static int gen8_reset_engines(struct intel_gt *gt,
return ret;
}
+static int mock_reset(struct intel_gt *gt,
+ intel_engine_mask_t mask,
+ unsigned int retry)
+{
+ return 0;
+}
+
typedef int (*reset_func)(struct intel_gt *,
intel_engine_mask_t engine_mask,
unsigned int retry);
@@ -550,7 +557,9 @@ static reset_func intel_get_gpu_reset(const struct intel_gt
*gt)
{
struct drm_i915_private *i915 = gt->i915;
- if (INTEL_GEN(i915) >= 8)
+ if (is_mock_gt(gt))
+ return mock_reset;
+ else if (INTEL_GEN(i915) >= 8)
return gen8_reset_engines;
else if (INTEL_GEN(i915) >= 6)
return gen6_reset_engines;
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Provide a mock GPU reset routine
Quoting Chris Wilson (2019-09-27 20:14:42)
> -static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
> +static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
> {
> - if (INTEL_GEN(i915) >= 8)
> + struct drm_i915_private *i915 = gt->i915;
> +
> + if (is_mock_gt(gt))
Actually this highlights an issue with using gt->awake == -1 as our
indicator.
Hmm. I wonder...
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/selftests: Do not try to sanitize mock HW
If we are mocking the device, skip trying to sanitize the pm HW state.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 42f175d9b98c..29fa1dabbc2e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -137,7 +137,8 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
void intel_gt_pm_disable(struct intel_gt *gt)
{
- intel_sanitize_gt_powersave(gt->i915);
+ if (!is_mock_gt(gt))
+ intel_sanitize_gt_powersave(gt->i915);
}
void intel_gt_pm_fini(struct intel_gt *gt)
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config
Ville, Maarten
In this patch, I added a WARN ON for the case where the same trans could be
configured as master and slave.
Does this look good?
Manasi
On Thu, Sep 26, 2019 at 05:11:10PM -0700, Manasi Navare wrote:
> After the state is committed, we readout the HW registers and compare
> the HW state with the SW state that we just committed.
> For Transcdoer port sync, we add master_transcoder and the
> salves bitmask to the crtc_state, hence we need to read those during
> the HW state readout to avoid pipe state mismatch.
>
> v6:
> * Go through both parts of HW readout (Maarten)
> * Add a WARN if the same trans configured as
> master and slave (Ville, Maarten)
> v5:
> * Add return INVALID in defaut case (Maarten)
> v4:
> * Get power domains in master loop for get_config (Ville)
> v3:
> * Add TRANSCODER_D (Maarten)
> * v3 Reviewed-by: Maarten Lankhorst
> v2:
> * Add Transcoder_D and MISSING_CASE (Maarten)
>
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Cc: Matt Roper
> Cc: Jani Nikula
> Signed-off-by: Manasi Navare
> Reviewed-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 69
> 1 file changed, 69 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index af6b8f10f132..6e4af6ded6f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10510,6 +10510,72 @@ static void haswell_get_ddi_port_state(struct
> intel_crtc *crtc,
> }
> }
>
> +static enum transcoder transcoder_master(struct drm_i915_private *dev_priv,
> + enum transcoder cpu_transcoder)
> +{
> + u32 trans_port_sync, master_select;
> +
> + trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
> +
> + if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
> + return INVALID_TRANSCODER;
> +
> + master_select = trans_port_sync &
> + PORT_SYNC_MODE_MASTER_SELECT_MASK;
> + switch (master_select) {
> + case 1:
> + return TRANSCODER_A;
> + case 2:
> + return TRANSCODER_B;
> + case 3:
> + return TRANSCODER_C;
> + case 4:
> + return TRANSCODER_D;
> + default:
> + MISSING_CASE(master_select);
> + return INVALID_TRANSCODER;
> + }
> +}
> +
> +static void icelake_get_trans_port_sync_config(struct intel_crtc *crtc,
> +struct intel_crtc_state
> *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + u32 transcoders;
> + enum transcoder cpu_transcoder;
> +
> + pipe_config->master_transcoder = transcoder_master(dev_priv,
> +
> pipe_config->cpu_transcoder);
> + if (pipe_config->master_transcoder != INVALID_TRANSCODER)
> + pipe_config->sync_mode_slaves_mask = 0;
> +
> + transcoders = BIT(TRANSCODER_A) |
> + BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) |
> + BIT(TRANSCODER_D);
> + for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> + enum intel_display_power_domain power_domain;
> + intel_wakeref_t trans_wakeref;
> +
> + power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> + trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
> +
> power_domain);
> +
> + if (!trans_wakeref)
> + continue;
> +
> + if (transcoder_master(dev_priv, cpu_transcoder) ==
> + pipe_config->cpu_transcoder)
> + pipe_config->sync_mode_slaves_mask |=
> BIT(cpu_transcoder);
> +
> + intel_display_power_put(dev_priv, power_domain, trans_wakeref);
> + }
> +
> + WARN_ON(pipe_config->master_transcoder != INVALID_TRANSCODER &&
> + pipe_config->sync_mode_slaves_mask);
> +}
> +
> static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> @@ -10629,6 +10695,9 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
> pipe_config->pixel_multiplier = 1;
> }
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + icelake_get_trans_port_sync_config(crtc, pipe_config);
> +
> out:
> for_each_power_domain(power_domain, power_domain_mask)
> intel_display_power_put(dev_priv,
> --
> 2.19.1
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Provide a mock GPU reset routine
Quoting Andi Shyti (2019-09-27 21:41:19) > Hi Chris, > > On Fri, Sep 27, 2019 at 08:14:42PM +0100, Chris Wilson wrote: > > For those mock tests that may wish to pretend triggering a GPU reset and > > processing the cleanup. > > The patch is OK, per se, but I think it should be split in two > parts: > > - the i915 to gt conversion (that is the biggest part of the >patch) > - the mock-reset part (baskically the function) > > right? But you read it all already... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/22] drm/i915/selftests: check for missing aperture
Quoting Matthew Auld (2019-09-27 18:34:05) > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c > b/drivers/gpu/drm/i915/selftests/i915_gem.c > index 37593831b539..4951957a4d8d 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_gem.c > +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c > @@ -42,6 +42,9 @@ static void trash_stolen(struct drm_i915_private *i915) > unsigned long page; > u32 prng = 0x12345678; > > + if (!HAS_MAPPABLE_APERTURE(i915)) > + return; That's a bit of a nasty loss in coverage. Note we need to extend this test to trash lmem as well. Ideas? (Possibly using the GPU to trash everything but itself?) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 17/22] drm/i915: set num_fence_regs to 0 if there is no aperture
Quoting Matthew Auld (2019-09-27 18:34:04) > From: Daniele Ceraolo Spurio > > We can't fence anything without aperture. > > Signed-off-by: Daniele Ceraolo Spurio > Signed-off-by: Stuart Summers > Cc: Matthew Auld > --- > drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c > b/drivers/gpu/drm/i915/i915_gem_fence_reg.c > index 615a9f4ef30c..e15e4e247576 100644 > --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c > +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c > @@ -828,8 +828,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) > > detect_bit_6_swizzle(i915); > > - if (INTEL_GEN(i915) >= 7 && > - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) > + if (!HAS_MAPPABLE_APERTURE(i915)) You have the actual i915_ggtt! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 14/27] drm/i915: Expose engine properties via sysfs
On Wed, Sep 25, 2019 at 11:01:24AM +0100, Chris Wilson wrote:
> Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
> that we can expose properties on each engine to the sysadmin.
>
> To start with we have basic analogues of the i915_query ioctl so that we
> can pretty print engine discovery from the shell, and flesh out the
> directory structure. Later we will add writeable sysadmin properties such
> as per-engine timeout controls.
>
> An example tree of the engine properties on Braswell:
> /sys/class/drm/card0
> └── engine
> ├── bcs0
> │ ├── class
> │ ├── heartbeat_interval_ms
> │ ├── instance
> │ ├── mmio_base
> │ └── name
> ├── rcs0
> │ ├── class
> │ ├── heartbeat_interval_ms
> │ ├── instance
> │ ├── mmio_base
> │ └── name
> ├── vcs0
> │ ├── class
> │ ├── heartbeat_interval_ms
> │ ├── instance
> │ ├── mmio_base
> │ └── name
> └── vecs0
> ├── class
> ├── heartbeat_interval_ms
> ├── instance
> ├── mmio_base
> └── name
>
Acked-by: Rodrigo Vivi
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Tvrtko Ursulin
> Cc: Daniele Ceraolo Spurio
> Cc: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile| 3 +-
> drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 119 +++
> drivers/gpu/drm/i915/gt/intel_engine_sysfs.h | 14 +++
> drivers/gpu/drm/i915/i915_sysfs.c| 4 +
> 4 files changed, 139 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_sysfs.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index cba19470feb5..ba98a2067433 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -76,8 +76,9 @@ gt-y += \
> gt/intel_breadcrumbs.o \
> gt/intel_context.o \
> gt/intel_engine_cs.o \
> - gt/intel_engine_pool.o \
> gt/intel_engine_pm.o \
> + gt/intel_engine_pool.o \
> + gt/intel_engine_sysfs.o \
> gt/intel_engine_user.o \
> gt/intel_gt.o \
> gt/intel_gt_irq.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
> new file mode 100644
> index ..cbe9ec59beeb
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
> @@ -0,0 +1,119 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include
> +#include
> +
> +#include "i915_drv.h"
> +#include "intel_engine.h"
> +#include "intel_engine_sysfs.h"
> +
> +struct kobj_engine {
> + struct kobject base;
> + struct intel_engine_cs *engine;
> +};
> +
> +static struct intel_engine_cs *kobj_to_engine(struct kobject *kobj)
> +{
> + return container_of(kobj, struct kobj_engine, base)->engine;
> +}
> +
> +static ssize_t
> +name_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> +{
> + return sprintf(buf, "%s\n", kobj_to_engine(kobj)->name);
> +}
> +
> +static ssize_t
> +class_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> +{
> + return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
> +}
> +
> +static ssize_t
> +inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> +{
> + return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
> +}
> +
> +static ssize_t
> +mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> +{
> + return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
> +}
> +
> +static struct kobj_attribute name_attr = __ATTR(name, 0444, name_show, NULL);
> +static struct kobj_attribute class_attr = __ATTR(class, 0444, class_show,
> NULL);
> +static struct kobj_attribute inst_attr = __ATTR(instance, 0444, inst_show,
> NULL);
> +static struct kobj_attribute mmio_attr = __ATTR(mmio_base, 0444, mmio_show,
> NULL);
> +
> +static void kobj_engine_release(struct kobject *kobj)
> +{
> + kfree(kobj);
> +}
> +
> +static struct kobj_type kobj_engine_type = {
> + .release = kobj_engine_release,
> + .sysfs_ops = &kobj_sysfs_ops
> +};
> +
> +static struct kobject *
> +kobj_engine(struct kobject *dir, struct intel_engine_cs *engine)
> +{
> + struct kobj_engine *ke;
> +
> + ke = kzalloc(sizeof(*ke), GFP_KERNEL);
> + if (!ke)
> + return NULL;
> +
> + kobject_init(&ke->base, &kobj_engine_type);
> + ke->engine = engine;
> +
> + if (kobject_add(&ke->base, dir, "%s", engine->name)) {
> + kobject_put(&ke->base);
> + return NULL;
> + }
> +
> + /* xfer ownership to sysfs tree */
> + return &ke->base;
> +}
> +
> +void intel_engines_add_sysfs(struct drm_i915_private *i915)
> +{
> + static const struct at
Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests; Do not try to sanitize mock HW
Hi Chris,
On Fri, Sep 27, 2019 at 08:14:43PM +0100, Chris Wilson wrote:
> If we are mocking the device, skip trying to sanitize the pm HW state.
>
> Signed-off-by: Chris Wilson
> Cc: Andi Shyti
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index 42f175d9b98c..29fa1dabbc2e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -137,7 +137,8 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
>
> void intel_gt_pm_disable(struct intel_gt *gt)
> {
> - intel_sanitize_gt_powersave(gt->i915);
> + if (!is_mock_gt(gt))
> + intel_sanitize_gt_powersave(gt->i915);
Cool!
Reviewed-by: Andi Shyti
Andi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/22] drm/i915: enumerate and init each supported region
Quoting Matthew Auld (2019-09-27 18:33:59) > + mem->id = intel_region_map[i]; > + mem->type = type; > + mem->instance = > MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]); So why 3xu32 for a single u32 of information? Either one or two u32 would do, depending on frequency of use. And why was it BIT(inst)? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/22] drm/i915/selftests: add write-dword test for LMEM
Quoting Matthew Auld (2019-09-27 18:33:57)
> + i = 0;
> + engines = i915_gem_context_lock_engines(ctx);
> + do {
> + u32 rng = prandom_u32_state(&prng);
> + u32 dword = offset_in_page(rng) / 4;
> +
> + ce = engines->engines[order[i] % engines->num_engines];
> + i = (i + 1) % (count * count);
> + if (!ce || !intel_engine_can_store_dword(ce->engine))
> + continue;
> +
> + err = igt_gpu_write_dw(ce, vma, dword, rng);
> + if (err)
> + break;
Do you have a test that does
dword,
64B or cacheline,
page
random width&strides of the above
before doing the read back of a random dword from those?
Think nasty cache artifacts, PCI transfers, and timing.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Provide a mock GPU reset routine
Hi Chris,
On Fri, Sep 27, 2019 at 08:14:42PM +0100, Chris Wilson wrote:
> For those mock tests that may wish to pretend triggering a GPU reset and
> processing the cleanup.
The patch is OK, per se, but I think it should be split in two
parts:
- the i915 to gt conversion (that is the biggest part of the
patch)
- the mock-reset part (baskically the function)
right?
Andi
>
> Signed-off-by: Chris Wilson
> Cc: Andi Shyti
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 32 +--
> drivers/gpu/drm/i915/gt/intel_reset.h | 5 ++-
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 12 +++
> drivers/gpu/drm/i915/gt/selftest_lrc.c| 2 +-
> drivers/gpu/drm/i915/gt/selftest_reset.c | 4 +--
> .../gpu/drm/i915/gt/selftest_workarounds.c| 8 ++---
> drivers/gpu/drm/i915/i915_getparam.c | 4 +--
> 8 files changed, 41 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8f125f1624bd..7758a3744626 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4273,7 +4273,7 @@ __intel_display_resume(struct drm_device *dev,
> static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
> {
> return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
> - intel_has_gpu_reset(dev_priv));
> + intel_has_gpu_reset(&dev_priv->gt));
> }
>
> void intel_prepare_reset(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index d08226f5bea5..76938fa3a1b9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -542,13 +542,24 @@ static int gen8_reset_engines(struct intel_gt *gt,
> return ret;
> }
>
> +static int mock_reset(struct intel_gt *gt,
> + intel_engine_mask_t mask,
> + unsigned int retry)
> +{
> + return 0;
> +}
> +
> typedef int (*reset_func)(struct intel_gt *,
> intel_engine_mask_t engine_mask,
> unsigned int retry);
>
> -static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
> +static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
> {
> - if (INTEL_GEN(i915) >= 8)
> + struct drm_i915_private *i915 = gt->i915;
> +
> + if (is_mock_gt(gt))
> + return mock_reset;
> + else if (INTEL_GEN(i915) >= 8)
> return gen8_reset_engines;
> else if (INTEL_GEN(i915) >= 6)
> return gen6_reset_engines;
> @@ -571,7 +582,7 @@ int __intel_gt_reset(struct intel_gt *gt,
> intel_engine_mask_t engine_mask)
> int ret = -ETIMEDOUT;
> int retry;
>
> - reset = intel_get_gpu_reset(gt->i915);
> + reset = intel_get_gpu_reset(gt);
> if (!reset)
> return -ENODEV;
>
> @@ -591,17 +602,20 @@ int __intel_gt_reset(struct intel_gt *gt,
> intel_engine_mask_t engine_mask)
> return ret;
> }
>
> -bool intel_has_gpu_reset(struct drm_i915_private *i915)
> +bool intel_has_gpu_reset(const struct intel_gt *gt)
> {
> if (!i915_modparams.reset)
> return NULL;
>
> - return intel_get_gpu_reset(i915);
> + return intel_get_gpu_reset(gt);
> }
>
> -bool intel_has_reset_engine(struct drm_i915_private *i915)
> +bool intel_has_reset_engine(const struct intel_gt *gt)
> {
> - return INTEL_INFO(i915)->has_reset_engine && i915_modparams.reset >= 2;
> + if (i915_modparams.reset < 2)
> + return false;
> +
> + return INTEL_INFO(gt->i915)->has_reset_engine;
> }
>
> int intel_reset_guc(struct intel_gt *gt)
> @@ -958,7 +972,7 @@ void intel_gt_reset(struct intel_gt *gt,
>
> awake = reset_prepare(gt);
>
> - if (!intel_has_gpu_reset(gt->i915)) {
> + if (!intel_has_gpu_reset(gt)) {
> if (i915_modparams.reset)
> dev_err(gt->i915->drm.dev, "GPU reset not supported\n");
> else
> @@ -1179,7 +1193,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
>* Try engine reset when available. We fall back to full reset if
>* single reset fails.
>*/
> - if (intel_has_reset_engine(gt->i915) && !intel_gt_is_wedged(gt)) {
> + if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
> for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
> BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
> if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h
> b/drivers/gpu/drm/i915/gt/intel_reset.h
> index 0b6ff1ee7f06..8e8d5f761166 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.h
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.h
> @@ -14,7 +14,6 @@
>
Re: [Intel-gfx] [PATCH 09/22] drm/i915/lmem: support kernel mapping
Quoting Matthew Auld (2019-09-27 18:33:56)
> +static int igt_lmem_write_cpu(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + struct intel_context *ce = i915->engine[BCS0]->kernel_context;
> + struct drm_i915_gem_object *obj;
> + struct rnd_state prng;
> + u32 *vaddr;
> + u32 dword;
> + u32 val;
> + u32 sz;
> + int err;
> +
> + if (!HAS_ENGINE(i915, BCS0))
> + return 0;
Too late. You've already *i915->engine[BCS0]
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync (rev4)
== Series Details ==
Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev4)
URL : https://patchwork.freedesktop.org/series/67043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6971 -> Patchwork_14572
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14572/index.html
Known issues
Here are the changes found in Patchwork_14572 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14572/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@kms_busy@basic-flip-a:
- fi-cml-u2: [PASS][3] -> [DMESG-WARN][4] ([fdo#105763])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-cml-u2/igt@kms_b...@basic-flip-a.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14572/fi-cml-u2/igt@kms_b...@basic-flip-a.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-cml-s}: [INCOMPLETE][5] ([fdo#110566]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-cml-s/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14572/fi-cml-s/igt@gem_ctx_cre...@basic-files.html
- {fi-tgl-u2}:[INCOMPLETE][7] ([fdo#111735]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14572/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (50 -> 43)
--
Additional (2): fi-bsw-kefka fi-icl-guc
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2
fi-skl-6600u fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6700k2
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6971 -> Patchwork_14572
CI-20190529: 20190529
CI_DRM_6971: b891ecf6856b90013c667c0d8becb7edb2f0c0d1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14572: 6f6828eb81f7110381aff173ea01129bb9b21cb4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6f6828eb81f7 drm/i915/display/icl: In port sync mode disable slaves first then
master
55b798a89124 drm/i915/display/icl: Disable transcoder port sync as part of
crtc_disable() sequence
198940813403 drm/i915/display/icl: Enable master-slaves in trans port sync
1406ade015dd drm/i915/display/icl: HW state readout for transcoder port sync
config
280be1656548 drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled
displays across separate ports
0fad8ae432c5 drm/i915/display/icl: Save Master transcoder in slave's crtc_state
for Transcoder Port Sync
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14572/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/22] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-09-27 18:33:50)
> +struct drm_i915_gem_object *
> +i915_gem_object_create_region(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
> +{
> + struct drm_i915_gem_object *obj;
> +
> + if (!mem)
> + return ERR_PTR(-ENODEV);
What scenarios do you have in mind that this is not a programmer bug?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/22] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-09-27 18:33:50)
> +void
> +__intel_memory_region_put_block_buddy(struct i915_buddy_block *block)
> +{
> + struct list_head blocks;
LIST_HEAD(blocks); (and no INIT_LIST_HEAD required)
> +
> + INIT_LIST_HEAD(&blocks);
> + list_add(&block->link, &blocks);
> + __intel_memory_region_put_pages_buddy(block->private, &blocks);
> +}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/selftests: Provide a mock GPU reset routine
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Provide a mock GPU reset
routine
URL : https://patchwork.freedesktop.org/series/67353/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6971 -> Patchwork_14571
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14571 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14571, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14571:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-blb-e6850: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-blb-e6850/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-blb-e6850/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-snb-2520m: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-snb-2520m/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-snb-2520m/igt@i915_selftest@live_hangcheck.html
- fi-ilk-650: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-ilk-650/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-ilk-650/igt@i915_selftest@live_hangcheck.html
- fi-elk-e7500: [PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-elk-e7500/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-elk-e7500/igt@i915_selftest@live_hangcheck.html
- fi-blb-e6850: [PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-blb-e6850/igt@i915_selftest@live_hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-blb-e6850/igt@i915_selftest@live_hangcheck.html
- fi-ivb-3770:[PASS][11] -> [DMESG-FAIL][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-ivb-3770/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-ivb-3770/igt@i915_selftest@live_hangcheck.html
- fi-snb-2600:[PASS][13] -> [DMESG-FAIL][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-snb-2600/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-snb-2600/igt@i915_selftest@live_hangcheck.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][15]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-blb-e6850/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14571 that come from known issues:
### IGT changes ###
Issues hit
* igt@prime_vgem@basic-wait-default:
- fi-icl-u3: [PASS][16] -> [DMESG-WARN][17] ([fdo#107724]) +4
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-u3/igt@prime_v...@basic-wait-default.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-icl-u3/igt@prime_v...@basic-wait-default.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-cml-s}: [INCOMPLETE][18] ([fdo#110566]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-cml-s/igt@gem_ctx_cre...@basic-files.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-cml-s/igt@gem_ctx_cre...@basic-files.html
- {fi-tgl-u2}:[INCOMPLETE][20] ([fdo#111735]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [DMESG-WARN][22] ([fdo#107724]) -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-dsi}: [DMESG-FAIL][24] ([fdo#111678]) -> [PASS][25]
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6971/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14571/fi-icl-dsi/igt@i915_selftest@live_hangc
[Intel-gfx] [PULL] drm-intel-next-fixes
Hi Dave and Daniel, This should've gone out yesterday, but apparently I had some issue with my mutt here. Anyway, nothing that couldn't wait for rc2 Here goes drm-intel-next-fixes-2019-09-26: - Fix concurrence on cases where requests where getting retired at same time as resubmitted to HW - Fix gen9 display resolutions by setting the right max plane width - Fix GPU hang on preemption - Mark contents as dirty on a write fault. This was breaking cursor sprite with dumb buffers. Thanks, Rodrigo. The following changes since commit 6e5c5272ca00809aae20817efb6f25881268b50b: drm/i915: Use NOEVICT for first pass on attemping to pin a GGTT mmap (2019-09-06 09:53:15 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2019-09-26 for you to fetch changes up to 458863e08e13ecf22b9ba1ee6d4baba0ce9990ea: drm/i915: Mark contents as dirty on a write fault (2019-09-24 09:57:28 -0700) - Fix concurrence on cases where requests where getting retired at same time as resubmitted to HW - Fix gen9 display resolutions by setting the right max plane width - Fix GPU hang on preemption - Mark contents as dirty on a write fault. This was breaking cursor sprite with dumb buffers. Chris Wilson (8): drm/i915: Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for skl+ drm/i915/execlists: Remove incorrect BUG_ON for schedule-out drm/i915: Perform GGTT restore much earlier during resume drm/i915: Don't mix srcu tag and negative error codes drm/i915: Extend Haswell GT1 PSMI workaround to all drm/i915: Verify the engine after acquiring the active.lock drm/i915: Prevent bonded requests from overtaking each other on preemption drm/i915: Mark contents as dirty on a write fault Kenneth Graunke (1): drm/i915: Whitelist COMMON_SLICE_CHICKEN2 Ville Syrjälä (1): drm/i915: Bump skl+ max plane width to 5k for linear/x-tiled drivers/gpu/drm/i915/display/intel_display.c | 15 ++- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 12 +++- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 3 --- drivers/gpu/drm/i915/gt/intel_lrc.c | 21 - drivers/gpu/drm/i915/gt/intel_reset.c| 8 +++- drivers/gpu/drm/i915/gt/intel_reset.h| 2 +- drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +++- drivers/gpu/drm/i915/i915_drv.c | 5 + drivers/gpu/drm/i915/i915_request.c | 25 ++--- drivers/gpu/drm/i915/selftests/i915_gem.c| 6 ++ 11 files changed, 74 insertions(+), 33 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH xf86-video-intel 00/21] Compiler warn elimination
Quoting Ville Syrjala (2019-09-19 17:30:52) > From: Ville Syrjälä > > Random smattering of patches to eliminate compiler warnings. > Some I just suppressed out of lazyness, others I tried to > silence by adjusting the code a bit. Some of the aliasing pointer avoidance looked silly, but silly compiler is silly. > Afterwards the build is clean on my gcc 8.3, though with > a bunch of stuff still suppressed I'm not 100% sure that's > a good thing. Definitely quieter which is much less offputting. Thanks, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 14/22] drm/i915: treat stolen as a region
Quoting Matthew Auld (2019-09-27 18:34:01) > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c > b/drivers/gpu/drm/i915/gem/i915_gem_region.c > index 0aeaebb41050..77e89fabbddf 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_region.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c > @@ -159,7 +159,7 @@ i915_gem_object_create_region(struct intel_memory_region > *mem, > return ERR_PTR(-E2BIG); > > obj = mem->ops->create_object(mem, size, flags); > - if (!IS_ERR(obj)) > + if (!IS_ERR_OR_NULL(obj)) Have a prep patch to bring stolen function signature into line. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/22] drm/i915/selftests: add write-dword test for LMEM
Quoting Matthew Auld (2019-09-27 18:33:57)
> +static int igt_gpu_write_dw(struct intel_context *ce,
> + struct i915_vma *vma,
> + u32 dword,
> + u32 value)
> +{
> + int err;
> +
> + i915_gem_object_lock(vma->obj);
> + err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
> + i915_gem_object_unlock(vma->obj);
> + if (err)
> + return err;
Your cpu check doesn't leave the caches dirty so this is overkill, and
worse may hide a coherency problem?
> + return igt_gpu_fill_dw(ce, vma, dword * sizeof(u32),
> + vma->size >> PAGE_SHIFT, value);
> +}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/22] drm/i915/lmem: support kernel mapping
Quoting Matthew Auld (2019-09-27 18:33:56)
> static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
> .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
> -I915_GEM_OBJECT_IS_SHRINKABLE,
> +I915_GEM_OBJECT_IS_SHRINKABLE |
> +I915_GEM_OBJECT_IS_MAPPABLE,
> +
> const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
> .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
> -I915_GEM_OBJECT_IS_SHRINKABLE,
> +I915_GEM_OBJECT_IS_SHRINKABLE |
> +I915_GEM_OBJECT_IS_MAPPABLE,
> static const struct drm_i915_gem_object_ops huge_ops = {
> .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
> -I915_GEM_OBJECT_IS_SHRINKABLE,
> +I915_GEM_OBJECT_IS_SHRINKABLE |
> +I915_GEM_OBJECT_IS_MAPPABLE,
Where's huge_pages and userptr?
In short any that HAS_STRUCT_PAGE is also mappable by your definition
(we can use kmap on them). I suggest maybe using HAS_IOMEM and then
if (!(obj->ops->flags & (HAS_STRUCT_PAGE | HAS_IOMEM))
?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Update H2G enable logging action definition
== Series Details ==
Series: drm/i915/guc: Update H2G enable logging action definition
URL : https://patchwork.freedesktop.org/series/67351/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6970 -> Patchwork_14570
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14570:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_requests:
- {fi-tgl-u2}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-tgl-u2/igt@i915_selftest@live_requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/fi-tgl-u2/igt@i915_selftest@live_requests.html
Known issues
Here are the changes found in Patchwork_14570 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927] /
[fdo#111381])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u2}:[DMESG-WARN][9] ([fdo#111600]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_reloc@basic-cpu:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-icl-u3/igt@gem_exec_re...@basic-cpu.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/fi-icl-u3/igt@gem_exec_re...@basic-cpu.html
* igt@kms_chamelium@dp-edid-read:
- {fi-icl-u4}:[FAIL][13] ([fdo#111045]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-icl-u4/igt@kms_chamel...@dp-edid-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/fi-icl-u4/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14570/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (53 -> 46)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6970 -> Patchwork_14570
CI-20190529: 20190529
CI_DRM_6970: ee94847f064c84de51b33d8d843aa6bde51a8af6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14570: dd46ccd6797dfc6474e57ca0b4fc160fe7c66f7c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dd46ccd6797d drm/i915/guc: Update H2G enable logging action definition
== Logs ==
For more details see:
https://intel-gfx-ci.01.org
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Provide a mock GPU reset routine
For those mock tests that may wish to pretend triggering a GPU reset and
processing the cleanup.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 32 +--
drivers/gpu/drm/i915/gt/intel_reset.h | 5 ++-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 12 +++
drivers/gpu/drm/i915/gt/selftest_lrc.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_reset.c | 4 +--
.../gpu/drm/i915/gt/selftest_workarounds.c| 8 ++---
drivers/gpu/drm/i915/i915_getparam.c | 4 +--
8 files changed, 41 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8f125f1624bd..7758a3744626 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4273,7 +4273,7 @@ __intel_display_resume(struct drm_device *dev,
static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
{
return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
- intel_has_gpu_reset(dev_priv));
+ intel_has_gpu_reset(&dev_priv->gt));
}
void intel_prepare_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index d08226f5bea5..76938fa3a1b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -542,13 +542,24 @@ static int gen8_reset_engines(struct intel_gt *gt,
return ret;
}
+static int mock_reset(struct intel_gt *gt,
+ intel_engine_mask_t mask,
+ unsigned int retry)
+{
+ return 0;
+}
+
typedef int (*reset_func)(struct intel_gt *,
intel_engine_mask_t engine_mask,
unsigned int retry);
-static reset_func intel_get_gpu_reset(struct drm_i915_private *i915)
+static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
{
- if (INTEL_GEN(i915) >= 8)
+ struct drm_i915_private *i915 = gt->i915;
+
+ if (is_mock_gt(gt))
+ return mock_reset;
+ else if (INTEL_GEN(i915) >= 8)
return gen8_reset_engines;
else if (INTEL_GEN(i915) >= 6)
return gen6_reset_engines;
@@ -571,7 +582,7 @@ int __intel_gt_reset(struct intel_gt *gt,
intel_engine_mask_t engine_mask)
int ret = -ETIMEDOUT;
int retry;
- reset = intel_get_gpu_reset(gt->i915);
+ reset = intel_get_gpu_reset(gt);
if (!reset)
return -ENODEV;
@@ -591,17 +602,20 @@ int __intel_gt_reset(struct intel_gt *gt,
intel_engine_mask_t engine_mask)
return ret;
}
-bool intel_has_gpu_reset(struct drm_i915_private *i915)
+bool intel_has_gpu_reset(const struct intel_gt *gt)
{
if (!i915_modparams.reset)
return NULL;
- return intel_get_gpu_reset(i915);
+ return intel_get_gpu_reset(gt);
}
-bool intel_has_reset_engine(struct drm_i915_private *i915)
+bool intel_has_reset_engine(const struct intel_gt *gt)
{
- return INTEL_INFO(i915)->has_reset_engine && i915_modparams.reset >= 2;
+ if (i915_modparams.reset < 2)
+ return false;
+
+ return INTEL_INFO(gt->i915)->has_reset_engine;
}
int intel_reset_guc(struct intel_gt *gt)
@@ -958,7 +972,7 @@ void intel_gt_reset(struct intel_gt *gt,
awake = reset_prepare(gt);
- if (!intel_has_gpu_reset(gt->i915)) {
+ if (!intel_has_gpu_reset(gt)) {
if (i915_modparams.reset)
dev_err(gt->i915->drm.dev, "GPU reset not supported\n");
else
@@ -1179,7 +1193,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
* Try engine reset when available. We fall back to full reset if
* single reset fails.
*/
- if (intel_has_reset_engine(gt->i915) && !intel_gt_is_wedged(gt)) {
+ if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h
b/drivers/gpu/drm/i915/gt/intel_reset.h
index 0b6ff1ee7f06..8e8d5f761166 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -14,7 +14,6 @@
#include "intel_engine_types.h"
#include "intel_reset_types.h"
-struct drm_i915_private;
struct i915_request;
struct intel_engine_cs;
struct intel_gt;
@@ -80,7 +79,7 @@ static inline bool __intel_reset_failed(const struct
intel_reset *reset)
return unlikely(test_bit(I915_WEDGED, &reset->flags));
}
-bool intel_has_gpu_reset(struct drm_i915_private *i915);
-bool intel_has_reset_engine(struct drm_i915_private *i915);
[Intel-gfx] [PATCH 2/2] drm/i915/selftests; Do not try to sanitize mock HW
If we are mocking the device, skip trying to sanitize the pm HW state.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 42f175d9b98c..29fa1dabbc2e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -137,7 +137,8 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
void intel_gt_pm_disable(struct intel_gt *gt)
{
- intel_sanitize_gt_powersave(gt->i915);
+ if (!is_mock_gt(gt))
+ intel_sanitize_gt_powersave(gt->i915);
}
void intel_gt_pm_fini(struct intel_gt *gt)
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync (rev3)
== Series Details == Series: series starting with [v3,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync (rev3) URL : https://patchwork.freedesktop.org/series/67043/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6966_full -> Patchwork_14562_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14562_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14562_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14562_full: ### IGT changes ### Possible regressions * igt@perf_pmu@busy-idle-no-semaphores-bcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-kbl2/igt@perf_...@busy-idle-no-semaphores-bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-kbl6/igt@perf_...@busy-idle-no-semaphores-bcs0.html Known issues Here are the changes found in Patchwork_14562_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@in-order-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +14 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb2/igt@gem_exec_sched...@in-order-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-iclb8/igt@gem_exec_sched...@in-order-bsd2.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb5/igt@gem_exec_sched...@preempt-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-iclb2/igt@gem_exec_sched...@preempt-bsd.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl2/igt@gem_soft...@noreloc-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-skl3/igt@gem_soft...@noreloc-s3.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl5/igt@i915_susp...@sysfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-apl7/igt@i915_susp...@sysfs-reader.html * igt@kms_flip@2x-flip-vs-dpms-interruptible: - shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-hsw1/igt@kms_f...@2x-flip-vs-dpms-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-hsw4/igt@kms_f...@2x-flip-vs-dpms-interruptible.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl2/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#103313]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-kbl2/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-kbl2/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111764]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14562/shard-iclb2/igt@kms_vbl
[Intel-gfx] ✓ Fi.CI.BAT: success for LMEM basics
== Series Details ==
Series: LMEM basics
URL : https://patchwork.freedesktop.org/series/67350/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6970 -> Patchwork_14569
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14569/index.html
New tests
-
New tests have been introduced between CI_DRM_6970 and Patchwork_14569:
### New IGT tests (1) ###
* igt@i915_selftest@live_memory_region:
- Statuses : 46 pass(s)
- Exec time: [0.36, 2.33] s
Known issues
Here are the changes found in Patchwork_14569 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14569/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#103167])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14569/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u2}:[DMESG-WARN][5] ([fdo#111600]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14569/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_reloc@basic-cpu:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-icl-u3/igt@gem_exec_re...@basic-cpu.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14569/fi-icl-u3/igt@gem_exec_re...@basic-cpu.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [FAIL][10] ([fdo#111045]
/ [fdo#111096])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6970/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14569/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (53 -> 46)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6970 -> Patchwork_14569
CI-20190529: 20190529
CI_DRM_6970: ee94847f064c84de51b33d8d843aa6bde51a8af6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14569: e2124597ca45de1ae9d5166f4df166817780c8fd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e2124597ca45 HAX drm/i915: add the fake lmem region
2f657bf00d3c drm/i915: check for missing aperture in GTT pread/pwrite paths
097c34ca5081 drm/i915: Don't try to place HWS in non-existing mappable region
f722fde71ba0 drm/i915: error capture with no ggtt slot
9d82c4a319bc drm/i915/selftests: check for missing aperture
4a7487273a64 drm/i915: set num_fence_regs to 0 if there is no aperture
2199f453f083 drm/i915: do not map aperture if it is not available.
8355d01685d9 drm/i915: define HAS_MAPPABLE_APERTURE
82bde2d03644 drm/i915: treat stolen as a region
19270051b021 drm/i915: treat shmem as a region
91e43c262159 drm/i915: enumerate and init each supported region
970fd335c3b3 drm/i915/selftest: extend coverage to include LMEM huge-pages
76154df5dd82 drm/i915/selftests: add write-dword test for LMEM
1dd672af1e42 drm/i915/lmem: support kernel mapping
63ad9888746c drm/i915: setup io-mapping for LMEM
a066bf23d40b drm/i915: support creating LMEM objects
b5655dcc6d84 drm/i915: Add memory region information to device_info
c6f24f30618c drm/i915/region: support volatile objects
6d8c4bbbc790 drm/i915/region: support continuous allocations
f52b9b0685d8 drm/i915: introduce intel_memory_region
dbbfe24cafca drm/i915: simplify i915_gem_init_early
ccc51e3ac24e drm/i915: check fo
Re: [Intel-gfx] [PATCH 04/22] drm/i915/region: support continuous allocations
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Matthew Auld
>Sent: Friday, September 27, 2019 1:34 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: daniel.vet...@ffwll.ch
>Subject: [Intel-gfx] [PATCH 04/22] drm/i915/region: support continuous
>allocations
>
>Some kernel internal objects may need to be allocated as a continuous
Nit:
You refer to the "continuous block", but the then you create the "CONTIGUOUS"
allocations.
s/continuous/contiguous?
Mike
>block, also thinking ahead the various kernel io_mapping interfaces seem
>to expect it, although this is purely a limitation in the kernel
>API...so perhaps something to be improved.
>
>Signed-off-by: Matthew Auld
>Cc: Joonas Lahtinen
>Cc: Abdiel Janulgue
>---
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 4 +
> drivers/gpu/drm/i915/gem/i915_gem_region.c| 15 +-
> drivers/gpu/drm/i915/gem/i915_gem_region.h| 3 +-
> .../gpu/drm/i915/gem/selftests/huge_pages.c | 3 +-
> drivers/gpu/drm/i915/intel_memory_region.c| 13 +-
> drivers/gpu/drm/i915/intel_memory_region.h| 3 +-
> .../drm/i915/selftests/intel_memory_region.c | 163 ++
> drivers/gpu/drm/i915/selftests/mock_region.c | 2 +-
> 8 files changed, 197 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>index d36c860c9c6f..7acd383f174f 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>@@ -117,6 +117,10 @@ struct drm_i915_gem_object {
>
> I915_SELFTEST_DECLARE(struct list_head st_link);
>
>+ unsigned long flags;
>+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
>+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
>+
> /*
>* Is the object to be mapped as read-only to the GPU
>* Only honoured if hardware has relevant pte bit
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
>b/drivers/gpu/drm/i915/gem/i915_gem_region.c
>index 5c3bfc121921..b317a5c84144 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
>@@ -23,10 +23,10 @@ i915_gem_object_get_pages_buddy(struct
>drm_i915_gem_object *obj)
> {
> struct intel_memory_region *mem = obj->mm.region;
> struct list_head *blocks = &obj->mm.blocks;
>- unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
> resource_size_t size = obj->base.size;
> resource_size_t prev_end;
> struct i915_buddy_block *block;
>+ unsigned int flags;
> struct sg_table *st;
> struct scatterlist *sg;
> unsigned int sg_page_sizes;
>@@ -42,6 +42,10 @@ i915_gem_object_get_pages_buddy(struct
>drm_i915_gem_object *obj)
> return -ENOMEM;
> }
>
>+ flags = I915_ALLOC_MIN_PAGE_SIZE;
>+ if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
>+ flags |= I915_ALLOC_CONTIGUOUS;
>+
> ret = __intel_memory_region_get_pages_buddy(mem, size, flags,
>blocks);
> if (ret)
> goto err_free_sg;
>@@ -56,7 +60,8 @@ i915_gem_object_get_pages_buddy(struct
>drm_i915_gem_object *obj)
> list_for_each_entry(block, blocks, link) {
> u64 block_size, offset;
>
>- block_size = i915_buddy_block_size(&mem->mm, block);
>+ block_size = min_t(u64, size,
>+ i915_buddy_block_size(&mem->mm,
>block));
> offset = i915_buddy_block_offset(block);
>
> GEM_BUG_ON(overflows_type(block_size, sg->length));
>@@ -98,10 +103,12 @@ i915_gem_object_get_pages_buddy(struct
>drm_i915_gem_object *obj)
> }
>
> void i915_gem_object_init_memory_region(struct drm_i915_gem_object
>*obj,
>- struct intel_memory_region *mem)
>+ struct intel_memory_region *mem,
>+ unsigned long flags)
> {
> INIT_LIST_HEAD(&obj->mm.blocks);
> obj->mm.region = mem;
>+ obj->flags = flags;
> }
>
> void i915_gem_object_release_memory_region(struct
>drm_i915_gem_object *obj)
>@@ -115,6 +122,8 @@ i915_gem_object_create_region(struct
>intel_memory_region *mem,
> {
> struct drm_i915_gem_object *obj;
>
>+ GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
>+
> if (!mem)
> return ERR_PTR(-ENODEV);
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h
>b/drivers/gpu/drm/i915/gem/i915_gem_region.h
>index ebddc86d78f7..f2ff6f8bff74 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
>@@ -17,7 +17,8 @@ void i915_gem_object_put_pages_buddy(struct
>drm_i915_gem_object *obj,
>struct sg_table *pages);
>
> void i915_gem_object_init_memory_region(struct drm_i915_gem_object
>*obj,
>- struct intel_memory_region *mem);
>+ st
Re: [Intel-gfx] [PATCH 07/22] drm/i915: support creating LMEM objects
Quoting Matthew Auld (2019-09-27 18:33:54)
> +const u32 intel_region_map[] = {
> + [INTEL_MEMORY_SMEM] = BIT(INTEL_SMEM + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> + [INTEL_MEMORY_LMEM] = BIT(INTEL_LMEM + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> + [INTEL_MEMORY_STOLEN] = BIT(INTEL_STOLEN + INTEL_MEMORY_TYPE_SHIFT) |
> BIT(0),
> +};
#define REGION_MAP(type, inst) \
BIT(type + SHIFT) | BIT(inst)
BIT(inst) looks odd.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for LMEM basics
== Series Details == Series: LMEM basics URL : https://patchwork.freedesktop.org/series/67350/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: check for kernel_context Okay! Commit: drm/i915: simplify i915_gem_init_early Okay! Commit: drm/i915: introduce intel_memory_region Okay! Commit: drm/i915/region: support continuous allocations +drivers/gpu/drm/i915/selftests/intel_memory_region.c:118:6: warning: symbol 'igt_object_release' was not declared. Should it be static? Commit: drm/i915/region: support volatile objects Okay! Commit: drm/i915: Add memory region information to device_info Okay! Commit: drm/i915: support creating LMEM objects Okay! Commit: drm/i915: setup io-mapping for LMEM Okay! Commit: drm/i915/lmem: support kernel mapping +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51:expected void * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51:got void [noderef] * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51: warning: incorrect type in return expression (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:335:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:335:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:335:42: warning: incorrect type in argument 1 (different address spaces) Commit: drm/i915/selftests: add write-dword test for LMEM Okay! Commit: drm/i915/selftest: extend coverage to include LMEM huge-pages Okay! Commit: drm/i915: enumerate and init each supported region Okay! Commit: drm/i915: treat shmem as a region Okay! Commit: drm/i915: treat stolen as a region Okay! Commit: drm/i915: define HAS_MAPPABLE_APERTURE Okay! Commit: drm/i915: do not map aperture if it is not available. Okay! Commit: drm/i915: set num_fence_regs to 0 if there is no aperture Okay! Commit: drm/i915/selftests: check for missing aperture Okay! Commit: drm/i915: error capture with no ggtt slot - +drivers/gpu/drm/i915/i915_gpu_error.c:1027:55:expected void *src +drivers/gpu/drm/i915/i915_gpu_error.c:1027:55:got void [noderef] *[assigned] s +drivers/gpu/drm/i915/i915_gpu_error.c:1027:55: warning: incorrect type in argument 2 (different address spaces) Commit: drm/i915: Don't try to place HWS in non-existing mappable region Okay! Commit: drm/i915: check for missing aperture in GTT pread/pwrite paths Okay! Commit: HAX drm/i915: add the fake lmem region Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/22] drm/i915/region: support continuous allocations
Quoting Matthew Auld (2019-09-27 18:33:51)
> struct drm_i915_gem_object *
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index 4e1805aaeb99..f9fbf2865782 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -471,7 +471,8 @@ static int igt_mock_memory_region_huge_pages(void *arg)
> unsigned int page_size = BIT(bit);
> resource_size_t phys;
>
> - obj = i915_gem_object_create_region(mem, page_size, 0);
> + obj = i915_gem_object_create_region(mem, page_size,
> + I915_BO_ALLOC_CONTIGUOUS);
Seems a good opportunity to test both?
> if (IS_ERR(obj)) {
> err = PTR_ERR(obj);
> goto out_destroy_device;
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
> b/drivers/gpu/drm/i915/intel_memory_region.c
> index e48d5c37c4df..7a66872d9eac 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -47,8 +47,8 @@ __intel_memory_region_get_pages_buddy(struct
> intel_memory_region *mem,
> unsigned int flags,
> struct list_head *blocks)
> {
> - unsigned long n_pages = size >> ilog2(mem->mm.chunk_size);
> unsigned int min_order = 0;
> + unsigned long n_pages;
>
> GEM_BUG_ON(!IS_ALIGNED(size, mem->mm.chunk_size));
> GEM_BUG_ON(!list_empty(blocks));
> @@ -58,6 +58,13 @@ __intel_memory_region_get_pages_buddy(struct
> intel_memory_region *mem,
> ilog2(mem->mm.chunk_size);
> }
>
> + if (flags & I915_ALLOC_CONTIGUOUS) {
> + size = roundup_pow_of_two(size);
> + min_order = ilog2(size) - ilog2(mem->mm.chunk_size);
> + }
> +
> + n_pages = size >> ilog2(mem->mm.chunk_size);
> +
> mutex_lock(&mem->mm_lock);
>
> do {
> @@ -104,7 +111,9 @@ __intel_memory_region_get_block_buddy(struct
> intel_memory_region *mem,
> int ret;
>
> INIT_LIST_HEAD(&blocks);
> - ret = __intel_memory_region_get_pages_buddy(mem, size, 0, &blocks);
> + ret = __intel_memory_region_get_pages_buddy(mem, size,
> + I915_ALLOC_CONTIGUOUS,
> + &blocks);
This chunk looks odd. Quick explanation why we don't pass flags here?
> if (ret)
> return ERR_PTR(ret);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for LMEM basics
== Series Details ==
Series: LMEM basics
URL : https://patchwork.freedesktop.org/series/67350/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ccc51e3ac24e drm/i915: check for kernel_context
dbbfe24cafca drm/i915: simplify i915_gem_init_early
f52b9b0685d8 drm/i915: introduce intel_memory_region
-:59: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#59:
new file mode 100644
-:562: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#562: FILE: drivers/gpu/drm/i915/intel_memory_region.h:25:
+ int (*init)(struct intel_memory_region *);
-:563: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#563: FILE: drivers/gpu/drm/i915/intel_memory_region.h:26:
+ void (*release)(struct intel_memory_region *);
-:565: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#565: FILE: drivers/gpu/drm/i915/intel_memory_region.h:28:
+ struct drm_i915_gem_object *
-:565: WARNING:FUNCTION_ARGUMENTS: function definition argument
'resource_size_t' should also have an identifier name
#565: FILE: drivers/gpu/drm/i915/intel_memory_region.h:28:
+ struct drm_i915_gem_object *
-:565: WARNING:FUNCTION_ARGUMENTS: function definition argument 'unsigned int'
should also have an identifier name
#565: FILE: drivers/gpu/drm/i915/intel_memory_region.h:28:
+ struct drm_i915_gem_object *
-:580: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#580: FILE: drivers/gpu/drm/i915/intel_memory_region.h:43:
+ struct mutex mm_lock;
-:599: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#599: FILE: drivers/gpu/drm/i915/intel_memory_region.h:62:
+__intel_memory_region_get_block_buddy(struct intel_memory_region *mem,
+resource_size_t size);
-:601: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#601: FILE: drivers/gpu/drm/i915/intel_memory_region.h:64:
+void __intel_memory_region_put_pages_buddy(struct intel_memory_region *mem,
+ struct list_head *blocks);
-:709: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'igt_mock_fill', this function's name, in a string
#709: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:80:
+ pr_err("igt_mock_fill failed, space still left in
region\n");
total: 0 errors, 7 warnings, 3 checks, 759 lines checked
6d8c4bbbc790 drm/i915/region: support continuous allocations
-:227: WARNING:LINE_SPACING: Missing a blank line after declarations
#227: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:133:
+ LIST_HEAD(holes);
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 307 lines checked
c6f24f30618c drm/i915/region: support volatile objects
b5655dcc6d84 drm/i915: Add memory region information to device_info
a066bf23d40b drm/i915: support creating LMEM objects
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#35:
new file mode 100644
-:117: WARNING:TYPO_SPELLING: 'UKNOWN' may be misspelled - perhaps 'UNKNOWN'?
#117: FILE: drivers/gpu/drm/i915/i915_drv.h:684:
+ struct intel_memory_region *regions[INTEL_MEMORY_UKNOWN];
-:168: WARNING:TYPO_SPELLING: 'UKNOWN' may be misspelled - perhaps 'UNKNOWN'?
#168: FILE: drivers/gpu/drm/i915/intel_memory_region.h:33:
+ INTEL_MEMORY_UKNOWN, /* Should be last */
-:177: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'r' may be better as '(r)' to
avoid precedence issues
#177: FILE: drivers/gpu/drm/i915/intel_memory_region.h:42:
+#define MEMORY_TYPE_FROM_REGION(r) (ilog2(r >> INTEL_MEMORY_TYPE_SHIFT))
-:178: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'r' may be better as '(r)' to
avoid precedence issues
#178: FILE: drivers/gpu/drm/i915/intel_memory_region.h:43:
+#define MEMORY_INSTANCE_FROM_REGION(r) (ilog2(r & 0x))
total: 0 errors, 3 warnings, 2 checks, 265 lines checked
63ad9888746c drm/i915: setup io-mapping for LMEM
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 34 lines checked
1dd672af1e42 drm/i915/lmem: support kernel mapping
-:289: ERROR:CODE_INDENT: code indent should use tabs where possible
#289: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:323:
+^I^I^Ival);$
-:289: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#289: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:323:
+ pr_err("vaddr[%u]=%u, val=%u\n", dword, vaddr[dword],
+ val);
-:301: ERROR:CODE_INDENT: code indent should use tabs where possible
#301: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:335:
+^I^I^Ival ^ 0x
Re: [Intel-gfx] [PATCH 03/22] drm/i915: introduce intel_memory_region
Quoting Chris Wilson (2019-09-27 19:24:43)
> Quoting Matthew Auld (2019-09-27 18:33:50)
> > +static void close_objects(struct list_head *objects)
> > +{
> > + struct drm_i915_private *i915 = NULL;
> > + struct drm_i915_gem_object *obj, *on;
> > +
> > + list_for_each_entry_safe(obj, on, objects, st_link) {
> > + i915 = to_i915(obj->base.dev);
> > + if (i915_gem_object_has_pinned_pages(obj))
> > + i915_gem_object_unpin_pages(obj);
> > + /* No polluting the memory region between tests */
> > + __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
> > + i915_gem_object_put(obj);
> > + list_del(&obj->st_link);
> > + }
> > +
> > + if (i915) {
>
> That's on the ugly side. You will have a mem in each subtest, so why not
> supply it here and use the mem->i915 from that?
The further thought, was to have an mem test runner that drained the
pages between each subtest. That's an area that we need to improve.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/22] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-09-27 18:33:50)
> +static void close_objects(struct list_head *objects)
> +{
> + struct drm_i915_private *i915 = NULL;
> + struct drm_i915_gem_object *obj, *on;
> +
> + list_for_each_entry_safe(obj, on, objects, st_link) {
> + i915 = to_i915(obj->base.dev);
> + if (i915_gem_object_has_pinned_pages(obj))
> + i915_gem_object_unpin_pages(obj);
> + /* No polluting the memory region between tests */
> + __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
> + i915_gem_object_put(obj);
> + list_del(&obj->st_link);
> + }
> +
> + if (i915) {
That's on the ugly side. You will have a mem in each subtest, so why not
supply it here and use the mem->i915 from that?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/22] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-09-27 18:33:50)
> +void
> +intel_memory_region_destroy(struct intel_memory_region *mem)
> +{
> + if (mem->ops->release)
> + mem->ops->release(mem);
> +
mutex_destroy(&mem->mm_lock);
> + kfree(mem);
> +}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Read SAGV block time from PCODE
On Wed, Sep 25, 2019 at 01:33:51PM -0700, James Ausmus wrote:
> Starting from TGL, we now need to read the SAGV block time via a PCODE
> mailbox, rather than having a static value.
>
> BSpec: 49326
>
> Cc: Ville Syrjälä
Wrong address. I ignore all patches going there, so it's not doing you
any good.
> Cc: Stanislav Lisovskiy
> Cc: Lucas De Marchi
> Signed-off-by: James Ausmus
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 20 +++-
> 2 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e752de9470bd..84ae6553485b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8865,6 +8865,7 @@ enum {
> #define GEN9_SAGV_DISABLE0x0
> #define GEN9_SAGV_IS_DISABLED0x1
> #define GEN9_SAGV_ENABLE 0x3
> +#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> #define GEN6_PCODE_DATA _MMIO(0x138128)
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5ad72dcb0faa..ca2bec09edb5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3665,16 +3665,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> static int
> intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
> {
> - int sagv_block_time_us = 1000; /* Default to unusable block time */
> + uint val = 0;
> + int ret, sagv_block_time_us = 1000; /* Default to unusable block time */
>
> - if (IS_GEN(dev_priv, 11))
> + if (INTEL_GEN(dev_priv) >= 12) {
> + ret = sandybridge_pcode_read(dev_priv,
> +
> GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> + &val, NULL);
> + if (!ret)
> + sagv_block_time_us = val;
> + else
> + DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
> + } else if (IS_GEN(dev_priv, 11)) {
> sagv_block_time_us = 10;
> - else if (IS_GEN(dev_priv, 10))
> + } else if (IS_GEN(dev_priv, 10)) {
> sagv_block_time_us = 20;
> - else if (IS_GEN(dev_priv, 9))
> + } else if (IS_GEN(dev_priv, 9)) {
> sagv_block_time_us = 30;
> - else
> + } else {
> MISSING_CASE(INTEL_GEN(dev_priv));
> + }
>
> return sagv_block_time_us;
> }
> --
> 2.22.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/guc: Update H2G enable logging action definition
GuC enable logging H2G action definition changed some time ago from 0xE000
to 0x40. All current GuC FW blobs use this definition, so fix the action
definition in driver to match.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 1d3cdd67ca2f..a26a85d50209 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -548,6 +548,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
+ INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,
INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
@@ -556,7 +557,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
- INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
INTEL_GUC_ACTION_LIMIT
};
--
2.21.0.5.gaeb582a983
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/22] drm/i915: introduce intel_memory_region
Quoting Matthew Auld (2019-09-27 18:33:50)
> +struct drm_i915_gem_object *
> +i915_gem_object_create_region(struct intel_memory_region *mem,
> + resource_size_t size,
> + unsigned int flags)
> +{
> + struct drm_i915_gem_object *obj;
> +
> + if (!mem)
> + return ERR_PTR(-ENODEV);
> +
> + size = round_up(size, mem->min_page_size);
> +
> + GEM_BUG_ON(!size);
> + GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
> +
> + if (size >> PAGE_SHIFT > INT_MAX)
> + return ERR_PTR(-E2BIG);
It's probably past time we fixed up the remaining int num_pages.
Hmm, I know gcc has warned for constants > type. Can we get it to warn
for unguarded type restrictions, i.e.
int num_pages = resource_size_t >> PAGE_SIZE;
Or maybe we go on a rampage and just ban obj->base.size and force
ourselves to use a wrapper in order to catch any offenders.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Read SAGV block time from PCODE
On Wed, Sep 25, 2019 at 01:33:51PM -0700, James Ausmus wrote:
> Starting from TGL, we now need to read the SAGV block time via a PCODE
> mailbox, rather than having a static value.
>
> BSpec: 49326
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Cc: Lucas De Marchi
> Signed-off-by: James Ausmus
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 20 +++-
> 2 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e752de9470bd..84ae6553485b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8865,6 +8865,7 @@ enum {
> #define GEN9_SAGV_DISABLE0x0
> #define GEN9_SAGV_IS_DISABLED0x1
> #define GEN9_SAGV_ENABLE 0x3
> +#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> #define GEN6_PCODE_DATA _MMIO(0x138128)
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5ad72dcb0faa..ca2bec09edb5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3665,16 +3665,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> static int
> intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
> {
> - int sagv_block_time_us = 1000; /* Default to unusable block time */
> + uint val = 0;
uint?
> + int ret, sagv_block_time_us = 1000; /* Default to unusable block time */
val+ret could live in a tighter scope.
>
> - if (IS_GEN(dev_priv, 11))
> + if (INTEL_GEN(dev_priv) >= 12) {
> + ret = sandybridge_pcode_read(dev_priv,
> +
> GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> + &val, NULL);
We should probably stash this somewhere so we don't have to keep
asking pcode about it every single time.
Magic numbers look correct
Reviewed-by: Ville Syrjälä
> + if (!ret)
> + sagv_block_time_us = val;
> + else
> + DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
> + } else if (IS_GEN(dev_priv, 11)) {
> sagv_block_time_us = 10;
> - else if (IS_GEN(dev_priv, 10))
> + } else if (IS_GEN(dev_priv, 10)) {
> sagv_block_time_us = 20;
> - else if (IS_GEN(dev_priv, 9))
> + } else if (IS_GEN(dev_priv, 9)) {
> sagv_block_time_us = 30;
> - else
> + } else {
> MISSING_CASE(INTEL_GEN(dev_priv));
> + }
>
> return sagv_block_time_us;
> }
> --
> 2.22.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dmc: Update ICL DMC version to v1.09 (rev2)
And pushed. Daniele On 9/26/19 8:30 AM, Patchwork wrote: == Series Details == Series: drm/i915/dmc: Update ICL DMC version to v1.09 (rev2) URL : https://patchwork.freedesktop.org/series/66560/ State : success == Summary == CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14538_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14538_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-apl4/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb6/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_eio@reset-stress: - shard-snb: [PASS][5] -> [FAIL][6] ([fdo#109661]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-snb6/igt@gem_...@reset-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-snb1/igt@gem_...@reset-stress.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb5/igt@gem_exec_as...@concurrent-writes-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-iclb2/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([fdo#108686]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-glk9/igt@gem_tiled_swapp...@non-threaded.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-glk2/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-kbl6/igt@gem_workarou...@suspend-resume-fd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_pm_rpm@pm-tiling: - shard-skl: [PASS][13] -> [SKIP][14] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl10/igt@i915_pm_...@pm-tiling.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-skl2/igt@i915_pm_...@pm-tiling.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108] / [fdo#107807]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl3/igt@i915_pm_...@system-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-skl7/igt@i915_pm_...@system-suspend.html * igt@i915_pm_rpm@universal-planes-dpms: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#103313]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-kbl4/igt@i915_pm_...@universal-planes-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-kbl2/igt@i915_pm_...@universal-planes-dpms.html * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-snb: [PASS][19] -> [SKIP][20] ([fdo#109271] / [fdo#109278]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-snb4/igt@kms_b...@extended-modeset-hang-newfb-render-a.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-snb2/igt@kms_b...@extended-modeset-hang-newfb-render-a.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding: - shard-apl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103927]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-apl7/igt@kms_cursor_...@pipe-a-cursor-128x42-sliding.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-128x42-sliding.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-snb: [PASS][23] -> [SKIP][24] ([fdo#109271]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-snb4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14538/shard-snb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracki
Re: [Intel-gfx] [PATCH 21/22] drm/i915: check for missing aperture in GTT pread/pwrite paths
Quoting Matthew Auld (2019-09-27 18:34:08) > From: CQ Tang > > drm_mm_insert_node_in_range() treats range_start > range_end as a > programmer error, such that we explode in insert_mappable_node. For now > simply check for missing aperture on such paths. range_start is 0. range_end is 0. drm_mm_insert_node_in_range(): DRM_MM_BUG_ON(range_start > range_end); if (size == 0 || range_end - range_start < size) return -ENOSPC; This patch is superfluous. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/huc: fix version parsing from CSS header
On 9/26/19 12:37 AM, Michal Wajdeczko wrote:
On Thu, 26 Sep 2019 01:03:20 +0200, Summers, Stuart
wrote:
On Wed, 2019-09-25 at 15:21 -0700, Daniele Ceraolo Spurio wrote:
The HuC FW has silently switched to encoding the version the same way
as
the GuC FW does, i.e. major.minor.patch instead of just major.minor.
All
the current blobs follow the new scheme, but since minor and patch
are
both zero there is no difference in the end results and we happily
load
them. New binaries, however, will have non-zero values in there, so
we
need to make sure to parse them correctly.
Signed-off-by: Daniele Ceraolo Spurio <
daniele.ceraolospu...@intel.com>
I don't have insight into the HuC change, so just taking your word
here. The code below looks sane and is an obvious improvement.
It might be interesting to get a look from someone a little closer to
this for a HuC perspective. With that disclaimer:
Reviewed-by: Stuart Summers
Double checked offline with HuC team, so
Acked-by: Michal Wajdeczko
Thanks for the double check and the review, pushed.
Daniele
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 23
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 8 +++
2 files changed, 7 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index ea9a807abd4f..bb878119f06c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -339,25 +339,10 @@ int intel_uc_fw_fetch(struct intel_uc_fw
*uc_fw, struct drm_i915_private *i915)
}
/* Get version numbers from the CSS header */
- switch (uc_fw->type) {
- case INTEL_UC_FW_TYPE_GUC:
- uc_fw->major_ver_found =
FIELD_GET(CSS_SW_VERSION_GUC_MAJOR,
- css->sw_version);
- uc_fw->minor_ver_found =
FIELD_GET(CSS_SW_VERSION_GUC_MINOR,
- css->sw_version);
- break;
-
- case INTEL_UC_FW_TYPE_HUC:
- uc_fw->major_ver_found =
FIELD_GET(CSS_SW_VERSION_HUC_MAJOR,
- css->sw_version);
- uc_fw->minor_ver_found =
FIELD_GET(CSS_SW_VERSION_HUC_MINOR,
- css->sw_version);
- break;
-
- default:
- MISSING_CASE(uc_fw->type);
- break;
- }
+ uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MAJOR,
+ css->sw_version);
+ uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MINOR,
+ css->sw_version);
if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
index ae58e8a8c53b..f8f6c91a0df6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -69,11 +69,9 @@ struct uc_css_header {
char username[8];
char buildnumber[12];
u32 sw_version;
-#define CSS_SW_VERSION_GUC_MAJOR (0xFF << 16)
-#define CSS_SW_VERSION_GUC_MINOR (0xFF << 8)
-#define CSS_SW_VERSION_GUC_PATCH (0xFF << 0)
-#define CSS_SW_VERSION_HUC_MAJOR (0x << 16)
-#define CSS_SW_VERSION_HUC_MINOR (0x << 0)
+#define CSS_SW_VERSION_UC_MAJOR (0xFF << 16)
+#define CSS_SW_VERSION_UC_MINOR (0xFF << 8)
+#define CSS_SW_VERSION_UC_PATCH (0xFF << 0)
u32 reserved[14];
u32 header_info;
} __packed;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 19/22] drm/i915: error capture with no ggtt slot
Quoting Matthew Auld (2019-09-27 18:34:06)
> @@ -2692,13 +2693,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
> if (ret)
> return ret;
>
> - /* Reserve a mappable slot for our lockless error capture */
> - ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
> - PAGE_SIZE, 0,
> I915_COLOR_UNEVICTABLE,
> - 0, ggtt->mappable_end,
> - DRM_MM_INSERT_LOW);
> - if (ret)
> - return ret;
> + if (HAS_MAPPABLE_APERTURE(ggtt->vm.i915)) {
Uh. If only we had the answer to hand...
if (ggtt->mappable_end) {
Or make HAS_MAPPABLE_APERTURE take ggtt. Though I'd vote for less
shouting.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Extract SAGV block time function
On Wed, Sep 25, 2019 at 01:33:50PM -0700, James Ausmus wrote:
> In prep for newer platforms having more complicated ways to determine
> the SAGV block time, extract the setting to a separate function. While
> we're at it, update the if ladder to follow the new gen -> old gen order
> preference, and warn on any non-specified gen.
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Cc: Lucas De Marchi
> Signed-off-by: James Ausmus
> ---
> drivers/gpu/drm/i915/intel_pm.c | 24 ++--
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6bed2ed14574..5ad72dcb0faa 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3662,6 +3662,23 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> }
>
> +static int
> +intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
The "_get_" in the name seems a bit superfluous.
> +{
> + int sagv_block_time_us = 1000; /* Default to unusable block time */
> +
> + if (IS_GEN(dev_priv, 11))
> + sagv_block_time_us = 10;
> + else if (IS_GEN(dev_priv, 10))
> + sagv_block_time_us = 20;
> + else if (IS_GEN(dev_priv, 9))
> + sagv_block_time_us = 30;
> + else
> + MISSING_CASE(INTEL_GEN(dev_priv));
> +
> + return sagv_block_time_us;
Could just return directly w/o the temp variable.
Reviewed-by: Ville Syrjälä
> +}
> +
> /*
> * SAGV dynamically adjusts the system agent voltage and clock frequencies
> * depending on power and performance requirements. The display engine access
> @@ -3755,12 +3772,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
> if (!intel_has_sagv(dev_priv))
> return false;
>
> - if (IS_GEN(dev_priv, 9))
> - sagv_block_time_us = 30;
> - else if (IS_GEN(dev_priv, 10))
> - sagv_block_time_us = 20;
> - else
> - sagv_block_time_us = 10;
> + sagv_block_time_us = intel_get_sagv_block_time_us(dev_priv);
>
> /*
>* If there are no active CRTCs, no additional checks need be performed
> --
> 2.22.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
On Fri, 2019-09-27 at 17:24 +, Patchwork wrote: > == Series Details == > > Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE > programming > URL : https://patchwork.freedesktop.org/series/67312/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6966_full -> Patchwork_14561_full > > > Summary > --- > > **SUCCESS** > > No regressions found. Pushed to dinq, thanks for the reviews Imre and Lucas. > > > > Known issues > > > Here are the changes found in Patchwork_14561_full that come from > known issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_schedule@promotion-bsd1: > - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +16 > similar issues >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@gem_exec_sched...@promotion-bsd1.html > > * igt@gem_exec_schedule@reorder-wide-bsd: > - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4 > similar issues >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@gem_exec_sched...@reorder-wide-bsd.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html > > * igt@gem_tiled_wc: > - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) > +1 similar issue >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb3/igt@gem_tiled_wc.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb7/igt@gem_tiled_wc.html > > * igt@i915_pm_rpm@system-suspend-execbuf: > - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] > / [fdo#107807]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl2/igt@i915_pm_...@system-suspend-execbuf.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl5/igt@i915_pm_...@system-suspend-execbuf.html > > * igt@i915_suspend@sysfs-reader: > - shard-apl: [PASS][9] -> [DMESG-WARN][10] > ([fdo#108566]) +5 similar issues >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl5/igt@i915_susp...@sysfs-reader.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl4/igt@i915_susp...@sysfs-reader.html > > * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: > - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 > similar issues >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html > > * igt@kms_plane_lowres@pipe-a-tiling-x: > - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-x.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-x.html > > * igt@kms_psr@psr2_sprite_mmap_gtt: > - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 > similar issues >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html > > * igt@kms_vblank@pipe-a-ts-continuation-suspend: > - shard-apl: [PASS][17] -> [INCOMPLETE][18] > ([fdo#103927]) +3 similar issues >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl1/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html > - shard-skl: [PASS][19] -> [INCOMPLETE][20] > ([fdo#104108]) >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl10/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl8/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html > > * igt@kms_vblank@pipe-c-ts-continuation-suspend: > - shard-iclb: [PASS][21] -> [DMESG-WARN][22] > ([fdo#111764]) >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb7/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html > > > Possible fixes > > * igt@gem_ctx_isolation@vcs1-dirty-create: > - shard-iclb: [SKIP][23] ([fdo#109276]) -> [PASS][24] +11 > simil
Re: [Intel-gfx] [PATCH V2 6/8] mdev: introduce virtio device and its device ops
Hi Alex,
> -Original Message-
> From: Alex Williamson
> Sent: Tuesday, September 24, 2019 6:07 PM
> To: Jason Wang
> Cc: k...@vger.kernel.org; linux-s...@vger.kernel.org; linux-
> ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org;
> kwankh...@nvidia.com; m...@redhat.com; tiwei@intel.com;
> virtualizat...@lists.linux-foundation.org; net...@vger.kernel.org;
> coh...@redhat.com; maxime.coque...@redhat.com;
> cunming.li...@intel.com; zhihong.w...@intel.com;
> rob.mil...@broadcom.com; xiao.w.w...@intel.com;
> haotian.w...@sifive.com; zhen...@linux.intel.com; zhi.a.w...@intel.com;
> jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com;
> rodrigo.v...@intel.com; airl...@linux.ie; dan...@ffwll.ch;
> far...@linux.ibm.com; pa...@linux.ibm.com; seb...@linux.ibm.com;
> ober...@linux.ibm.com; heiko.carst...@de.ibm.com; g...@linux.ibm.com;
> borntrae...@de.ibm.com; akrow...@linux.ibm.com; fre...@linux.ibm.com;
> lingshan@intel.com; Ido Shamay ;
> epere...@redhat.com; l...@redhat.com; Parav Pandit
> ; christophe.de.dinec...@gmail.com;
> kevin.t...@intel.com
> Subject: Re: [PATCH V2 6/8] mdev: introduce virtio device and its device ops
>
> On Tue, 24 Sep 2019 21:53:30 +0800
> Jason Wang wrote:
>
> > This patch implements basic support for mdev driver that supports
> > virtio transport for kernel virtio driver.
> >
> > Signed-off-by: Jason Wang
> > ---
> > include/linux/mdev.h| 2 +
> > include/linux/virtio_mdev.h | 145
> >
> > 2 files changed, 147 insertions(+)
> > create mode 100644 include/linux/virtio_mdev.h
> >
> > diff --git a/include/linux/mdev.h b/include/linux/mdev.h index
> > 3414307311f1..73ac27b3b868 100644
> > --- a/include/linux/mdev.h
> > +++ b/include/linux/mdev.h
> > @@ -126,6 +126,8 @@ struct mdev_device *mdev_from_dev(struct device
> > *dev);
> >
> > enum {
> > MDEV_ID_VFIO = 1,
> > + MDEV_ID_VIRTIO = 2,
> > + MDEV_ID_VHOST = 3,
>
> MDEV_ID_VHOST isn't used yet here. Also, given the strong interdependence
> between the class_id and the ops structure, we might wand to define them in
> the same place. Thanks,
>
When mlx5_core creates mdevs (parent->ops->create() and it wants to bind to
mlx5 mdev driver (which does mdev_register_driver()),
mlx5 core driver will publish MDEV_ID_MLX5_NET defined in central place as
include/linux/mdev.h without any ops structure.
Because such ops are not relevant. It uses usual, standard ops probe() remove()
on the mdev (similar to a regular PCI device).
So for VHOST case ops may be closely related to ID, but not for other type of
ID.
Just want to make sure, that scope of ID covers this case.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/22] drm/i915: simplify i915_gem_init_early
Quoting Matthew Auld (2019-09-27 18:33:49) > i915_gem_init_early doesn't need to return anything. > > Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/22] drm/i915: check for kernel_context
Quoting Matthew Auld (2019-09-27 18:33:48) > Explosions during early driver init on the error path. Make sure we fail > gracefully. Joonas would complain about the clearly not onion unwind here, but we have thrown it in as a catch-all cleanup for what is quite a complicated setup. > [ 9547.672258] BUG: kernel NULL pointer dereference, address: 007c > [ 9547.672288] #PF: supervisor read access in kernel mode > [ 9547.672292] #PF: error_code(0x) - not-present page > [ 9547.672296] PGD 800846b41067 P4D 800846b41067 PUD 797034067 PMD 0 > [ 9547.672303] Oops: [#1] SMP PTI > [ 9547.672307] CPU: 1 PID: 25634 Comm: i915_selftest Tainted: G U >5.3.0-rc8+ #73 > [ 9547.672313] Hardware name: /NUC6i7KYB, BIOS > KYSKLi70.86A.0050.2017.0831.1924 08/31/2017 > [ 9547.672395] RIP: 0010:intel_context_unpin+0x9/0x100 [i915] > [ 9547.672400] Code: 6b 60 00 e9 17 ff ff ff bd fc ff ff ff e9 7c ff ff ff 66 > 66 2e 0f 1f 84 00 00 00 00 > 00 0f 1f 40 00 0f 1f 44 00 00 41 54 55 53 <8b> 47 7c 83 f8 01 74 26 8d 48 ff > f0 0f b1 4f 7c 48 8d 57 7c > 75 05 > [ 9547.672413] RSP: 0018:ae8ac24ff878 EFLAGS: 00010246 > [ 9547.672417] RAX: 944a1b7842d0 RBX: 944a1b784000 RCX: > 944a12dd6fa8 > [ 9547.672422] RDX: 944a1b7842c0 RSI: 944a12dd5328 RDI: > > [ 9547.672428] RBP: R08: 944a11e5d840 R09: > > [ 9547.672433] R10: R11: R12: > > [ 9547.672438] R13: c11aaf00 R14: ffe4 R15: > 944a0e29bf38 > [ 9547.672443] FS: 7fc259b88ac0() GS:944a1f88() > knlGS: > [ 9547.672449] CS: 0010 DS: ES: CR0: 80050033 > [ 9547.672454] CR2: 007c CR3: 000853346003 CR4: > 003606e0 > [ 9547.672459] DR0: DR1: DR2: > > [ 9547.672464] DR3: DR6: fffe0ff0 DR7: > 0400 > [ 9547.672469] Call Trace: > [ 9547.672518] intel_engine_cleanup_common+0xe3/0x270 [i915] > [ 9547.672567] execlists_destroy+0xe/0x30 [i915] > [ 9547.672669] intel_engines_init+0x94/0xf0 [i915] > [ 9547.672749] i915_gem_init+0x191/0x950 [i915] > > Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/22] drm/i915: support creating LMEM objects
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 31 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 23 ++
drivers/gpu/drm/i915/i915_drv.h | 5 +++
drivers/gpu/drm/i915/intel_memory_region.c| 6 +++
drivers/gpu/drm/i915/intel_memory_region.h| 30 +
drivers/gpu/drm/i915/intel_region_lmem.c | 43 ++
drivers/gpu/drm/i915/intel_region_lmem.h | 11 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 45 +++
10 files changed, 197 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d849dff31f76..ccf4223ed3f9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -115,6 +115,7 @@ gem-y += \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_object_blt.o \
+ gem/i915_gem_lmem.o \
gem/i915_gem_mman.o \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
@@ -143,6 +144,7 @@ i915-y += \
i915_scheduler.o \
i915_trace_points.o \
i915_vma.o \
+ intel_region_lmem.o \
intel_wopcm.o
# general-purpose microcontroller (GuC) support
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
new file mode 100644
index ..26a23304df32
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
+#include "i915_drv.h"
+
+const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .get_pages = i915_gem_object_get_pages_buddy,
+ .put_pages = i915_gem_object_put_pages_buddy,
+ .release = i915_gem_object_release_memory_region,
+};
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *region = obj->mm.region;
+
+ return region && region->type == INTEL_LMEM;
+}
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags)
+{
+ return
i915_gem_object_create_region(i915->mm.regions[INTEL_MEMORY_LMEM],
+size, flags);
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
new file mode 100644
index ..ebc15fe24f58
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __I915_GEM_LMEM_H
+#define __I915_GEM_LMEM_H
+
+#include
+
+struct drm_i915_private;
+struct drm_i915_gem_object;
+
+extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags);
+
+#endif /* !__I915_GEM_LMEM_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 93116cc8b149..05a6491690f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -100,6 +100,8 @@
#include "i915_vma.h"
#include "i915_irq.h"
+#include "intel_region_lmem.h"
+
#include "intel_gvt.h"
/* General customization:
@@ -686,6 +688,8 @@ struct i915_gem_mm {
*/
struct vfsmount *gemfs;
+ struct intel_memory_region *regions[INTEL_MEMORY_UKNOWN];
+
struct notifier_block oom_notifier;
struct notifier_block vmap_notifier;
struct shrinker shrinker;
@@ -2171,6 +2175,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index fba07f71d9bd..703c615331c0 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/driver
[Intel-gfx] [PATCH 21/22] drm/i915: check for missing aperture in GTT pread/pwrite paths
From: CQ Tang drm_mm_insert_node_in_range() treats range_start > range_end as a programmer error, such that we explode in insert_mappable_node. For now simply check for missing aperture on such paths. Signed-off-by: CQ Tang Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fd329b6b475c..82daaab022d8 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -337,6 +337,9 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj, u64 remain, offset; int ret; + if (!HAS_MAPPABLE_APERTURE(i915)) + return -ENOSPC; + ret = mutex_lock_interruptible(&i915->drm.struct_mutex); if (ret) return ret; @@ -530,6 +533,9 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, void __user *user_data; int ret; + if (!HAS_MAPPABLE_APERTURE(i915)) + return -ENOSPC; + ret = mutex_lock_interruptible(&i915->drm.struct_mutex); if (ret) return ret; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/22] drm/i915: enumerate and init each supported region
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +--
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 ++
3 files changed, 72 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 05a6491690f7..cd1414f2bcb5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2394,6 +2394,9 @@ int __must_check i915_gem_evict_for_node(struct
i915_address_space *vm,
unsigned int flags);
int i915_gem_evict_vm(struct i915_address_space *vm);
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915);
+int i915_gem_init_memory_regions(struct drm_i915_private *i915);
+
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e62e9d1a1307..a2963677861d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2744,6 +2744,66 @@ int i915_init_ggtt(struct drm_i915_private *i915)
return 0;
}
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915)
+{
+ int i;
+
+ i915_gem_cleanup_stolen(i915);
+
+ for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
+ struct intel_memory_region *region = i915->mm.regions[i];
+
+ if (region)
+ intel_memory_region_destroy(region);
+ }
+}
+
+int i915_gem_init_memory_regions(struct drm_i915_private *i915)
+{
+ int err, i;
+
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ /* XXX: stolen will become a region at some point */
+ err = i915_gem_init_stolen(i915);
+ if (err)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
+ struct intel_memory_region *mem = NULL;
+ u32 type;
+
+ if (!HAS_REGION(i915, BIT(i)))
+ continue;
+
+ type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
+ switch (type) {
+ default:
+ break;
+ }
+
+ if (IS_ERR(mem)) {
+ err = PTR_ERR(mem);
+ DRM_ERROR("Failed to setup region(%d) type=%d\n", err,
type);
+ goto out_cleanup;
+ }
+
+ mem->id = intel_region_map[i];
+ mem->type = type;
+ mem->instance =
MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
+
+ i915->mm.regions[i] = mem;
+ }
+
+ return 0;
+
+out_cleanup:
+ i915_gem_cleanup_memory_regions(i915);
+ return err;
+}
+
static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
{
struct drm_i915_private *i915 = ggtt->vm.i915;
@@ -2785,6 +2845,8 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
{
struct pagevec *pvec;
+ i915_gem_cleanup_memory_regions(i915);
+
fini_aliasing_ppgtt(&i915->ggtt);
ggtt_cleanup_hw(&i915->ggtt);
@@ -2794,8 +2856,6 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
set_pages_array_wb(pvec->pages, pvec->nr);
__pagevec_release(pvec);
}
-
- i915_gem_cleanup_stolen(i915);
}
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3251,11 +3311,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- /*
-* Initialise stolen early so that we may reserve preallocated
-* objects for the BIOS to KMS transition.
-*/
- ret = i915_gem_init_stolen(dev_priv);
+ ret = i915_gem_init_memory_regions(dev_priv);
if (ret)
goto out_gtt_cleanup;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 32e32b1cd566..f210b5043112 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -82,6 +82,8 @@ static void mock_device_release(struct drm_device *dev)
i915_gemfs_fini(i915);
+ i915_gem_cleanup_memory_regions(i915);
+
drm_mode_config_cleanup(&i915->drm);
drm_dev_fini(&i915->drm);
@@ -219,6 +221,10 @@ struct drm_i915_private *mock_gem_device(void)
WARN_ON(i915_gemfs_init(i915));
+ err = i915_gem_init_memory_regions(i915);
+ if (err)
+ goto err_context;
+
return i915;
err_context:
--
2.20.1
___
Intel-gfx mailing list
[Intel-gfx] [PATCH 22/22] HAX drm/i915: add the fake lmem region
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the aperture and 1:1 it map to the stolen region.
To enable simply set i915_fake_lmem_start= on the kernel cmdline with the
start of reserved region(see memmap=). The size of the region we can
use is determined by the size of the mappable aperture, so the size of
reserved region should be >= mappable_end.
eg. memmap=2G$16G i915_fake_lmem_start=0x4
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
arch/x86/kernel/early-quirks.c | 26 +++
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 3 +
drivers/gpu/drm/i915/i915_drv.c| 8 ++
drivers/gpu/drm/i915/i915_gem_gtt.c| 3 +
drivers/gpu/drm/i915/intel_memory_region.h | 6 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 90 ++
drivers/gpu/drm/i915/intel_region_lmem.h | 5 ++
include/drm/i915_drm.h | 3 +
8 files changed, 144 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6f6b1d04dadf..9b04655e3926 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -603,6 +603,32 @@ static void __init intel_graphics_quirks(int num, int
slot, int func)
}
}
+struct resource intel_graphics_fake_lmem_res __ro_after_init =
DEFINE_RES_MEM(0, 0);
+EXPORT_SYMBOL(intel_graphics_fake_lmem_res);
+
+static int __init early_i915_fake_lmem_init(char *s)
+{
+ u64 start;
+ int ret;
+
+ if (*s == '=')
+ s++;
+
+ ret = kstrtoull(s, 16, &start);
+ if (ret)
+ return ret;
+
+ intel_graphics_fake_lmem_res.start = start;
+ intel_graphics_fake_lmem_res.end = SZ_2G; /* Placeholder; depends on
aperture size */
+
+ printk(KERN_INFO "Intel graphics fake LMEM starts at %pa\n",
+ &intel_graphics_fake_lmem_res.start);
+
+ return 0;
+}
+
+early_param("i915_fake_lmem_start", early_i915_fake_lmem_init);
+
static void __init force_disable_hpet(int num, int slot, int func)
{
#ifdef CONFIG_HPET_TIMER
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index d7ec74ed5b88..c5e75c2f2511 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -23,6 +23,7 @@ void __iomem *i915_gem_object_lmem_io_map_page(struct
drm_i915_gem_object *obj,
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
return io_mapping_map_wc(&obj->mm.region->iomap, offset, PAGE_SIZE);
}
@@ -33,6 +34,7 @@ void __iomem *i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
}
@@ -46,6 +48,7 @@ void __iomem *i915_gem_object_lmem_io_map(struct
drm_i915_gem_object *obj,
GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 91aae56b4280..98fa1932c4aa 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1546,6 +1546,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
+ /* Check if we support fake LMEM -- enable for live selftests */
+ if (INTEL_GEN(dev_priv) >= 9 && i915_selftest.live &&
+ intel_graphics_fake_lmem_res.start) {
+ mkwrite_device_info(dev_priv)->memory_regions =
+ REGION_SMEM | REGION_LMEM;
+ GEM_BUG_ON(!HAS_LMEM(dev_priv));
+ }
+
ret = pci_enable_device(pdev);
if (ret)
goto out_fini;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 29f9c43b2c68..02d2a6266b8c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2778,6 +2778,9 @@ int i915_gem_init_memory_regions(struct drm_i915_private
*i915)
case INTEL_STOLEN:
mem = i915_gem_stolen_setup(i915);
break;
+ case INTEL_LMEM:
+ mem = intel_setup_fake_lmem(i915);
+ break;
}
if
[Intel-gfx] [PATCH 16/22] drm/i915: do not map aperture if it is not available.
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ++---
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 51b2087b214f..1be7b236f234 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2827,7 +2827,9 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
mutex_unlock(&i915->drm.struct_mutex);
arch_phys_wc_del(ggtt->mtrr);
- io_mapping_fini(&ggtt->iomap);
+
+ if (ggtt->iomap.size)
+ io_mapping_fini(&ggtt->iomap);
}
/**
@@ -3038,10 +3040,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
int err;
/* TODO: We're not aware of mappable constraints on gen8 yet */
- ggtt->gmadr =
- (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
-pci_resource_len(pdev, 2));
- ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ /* FIXME: We probably need to add do device_info or runtime_info */
+ if (!HAS_LMEM(dev_priv)) {
+ ggtt->gmadr =
+ (struct resource)
DEFINE_RES_MEM(pci_resource_start(pdev, 2),
+pci_resource_len(pdev,
2));
+ ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ }
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
if (!err)
@@ -3267,15 +3272,18 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
- if (!io_mapping_init_wc(&ggtt->iomap,
- ggtt->gmadr.start,
- ggtt->mappable_end)) {
- ggtt->vm.cleanup(&ggtt->vm);
- ret = -EIO;
- goto out;
- }
+ if (ggtt->mappable_end) {
+ if (!io_mapping_init_wc(&ggtt->iomap,
+ ggtt->gmadr.start,
+ ggtt->mappable_end)) {
+ ggtt->vm.cleanup(&ggtt->vm);
+ ret = -EIO;
+ goto out;
+ }
- ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
+ ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
+ ggtt->mappable_end);
+ }
i915_ggtt_init_fences(ggtt);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/22] drm/i915: treat shmem as a region
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 14 +++-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 68 ++-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 9 ---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_pci.c | 29 +---
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
8 files changed, 95 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 768356908160..8043ff63d73f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -16,6 +16,7 @@
#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_object.h"
+#include "i915_gem_region.h"
#include "i915_scatterlist.h"
static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
@@ -191,8 +192,10 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj, int align)
/* Perma-pin (until release) the physical set of pages */
__i915_gem_object_pin_pages(obj);
- if (!IS_ERR_OR_NULL(pages))
+ if (!IS_ERR_OR_NULL(pages)) {
i915_gem_shmem_ops.put_pages(obj, pages);
+ i915_gem_object_release_memory_region(obj);
+ }
mutex_unlock(&obj->mm.lock);
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index e9550e0364cc..0aeaebb41050 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -6,6 +6,7 @@
#include "intel_memory_region.h"
#include "i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_trace.h"
void
i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
@@ -144,11 +145,22 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
GEM_BUG_ON(!size);
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
+ /*
+* There is a prevalence of the assumption that we fit the object's
+* page count inside a 32bit _signed_ variable. Let's document this and
+* catch if we ever need to fix it. In the meantime, if you do spot
+* such a local variable, please consider fixing!
+*/
+
if (size >> PAGE_SHIFT > INT_MAX)
return ERR_PTR(-E2BIG);
if (overflows_type(size, obj->base.size))
return ERR_PTR(-E2BIG);
- return mem->ops->create_object(mem, size, flags);
+ obj = mem->ops->create_object(mem, size, flags);
+ if (!IS_ERR(obj))
+ trace_i915_gem_object_create(obj);
+
+ return obj;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 9f5d903f7793..696e15e8c410 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -7,7 +7,9 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_gemfs.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
@@ -26,6 +28,7 @@ static void check_release_pagevec(struct pagevec *pvec)
static int shmem_get_pages(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_memory_region *mem = obj->mm.region;
const unsigned long page_count = obj->base.size / PAGE_SIZE;
unsigned long i;
struct address_space *mapping;
@@ -52,7 +55,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
* If there's no chance of allocating enough pages for the whole
* object, bail early.
*/
- if (page_count > totalram_pages())
+ if (obj->base.size > resource_size(&mem->region))
return -ENOMEM;
st = kmalloc(sizeof(*st), GFP_KERNEL);
@@ -417,6 +420,8 @@ shmem_pwrite(struct drm_i915_gem_object *obj,
static void shmem_release(struct drm_i915_gem_object *obj)
{
+ i915_gem_object_release_memory_region(obj);
+
fput(obj->base.filp);
}
@@ -435,7 +440,7 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.release = shmem_release,
};
-static int create_shmem(struct drm_i915_private *i915,
+static int __create_shmem(struct drm_i915_private *i915,
struct drm_gem_object *obj,
size_t size)
{
@@ -456,31 +461,23 @@ static int create_shmem(struct drm_i915_private *i915,
return 0;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_shmem(struct drm_i915_private *i915, u64 size)
+static struct drm_i915_gem_object *
+create_shmem(struct intel_memory_region *mem,
+resource_size_t size,
+unsigned flags)
{
+ struct drm_i915_private
[Intel-gfx] [PATCH 15/22] drm/i915: define HAS_MAPPABLE_APERTURE
From: Daniele Ceraolo Spurio The following patches in the series will use it to avoid certain operations when aperture is not available in HW. Signed-off-by: Daniele Ceraolo Spurio Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6cf13e98794a..d6303045f546 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2126,6 +2126,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ (INTEL_INFO(dev_priv)->display.overlay_needs_physical) +#define HAS_MAPPABLE_APERTURE(dev_priv) (dev_priv->ggtt.mappable_end > 0) + /* Early gen2 have a totally busted CS tlb and require pinned batches. */ #define HAS_BROKEN_CS_TLB(dev_priv)(IS_I830(dev_priv) || IS_I845G(dev_priv)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/22] drm/i915/selftests: check for missing aperture
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 ++
drivers/gpu/drm/i915/selftests/i915_gem.c | 3 +++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
5 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 0ff7a89aadca..07faeada86eb 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -246,7 +246,10 @@ static bool always_valid(struct drm_i915_private *i915)
static bool needs_fence_registers(struct drm_i915_private *i915)
{
- return !intel_gt_is_wedged(&i915->gt);
+ if (intel_gt_is_wedged(&i915->gt))
+ return false;
+
+ return i915->ggtt.num_fences;
}
static bool needs_mi_store_dword(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index aefe557527f8..cb880d73ef73 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -301,6 +301,9 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
/* We want to check the page mapping and fencing of a large object
* mmapped through the GTT. The object we create is larger than can
* possibly be mmaped as a whole, and so we must use partial GGTT vma.
@@ -433,6 +436,9 @@ static int igt_smoke_tiling(void *arg)
IGT_TIMEOUT(end);
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
/*
* igt_partial_tiling() does an exhastive check of partial tiling
* chunking, but will undoubtably run out of time. Here, we do a
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index a0098fc35921..35cc2c68b32f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1189,8 +1189,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
struct i915_request *rq;
struct evict_vma arg;
struct hang h;
+ unsigned int pin_flags;
int err;
+ if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE)
+ return 0;
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1227,10 +1231,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
goto out_obj;
}
- err = i915_vma_pin(arg.vma, 0, 0,
- i915_vma_is_ggtt(arg.vma) ?
- PIN_GLOBAL | PIN_MAPPABLE :
- PIN_USER);
+ pin_flags = i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER;
+
+ if (flags & EXEC_OBJECT_NEEDS_FENCE)
+ pin_flags |= PIN_MAPPABLE;
+
+ err = i915_vma_pin(arg.vma, 0, 0, pin_flags);
if (err) {
i915_request_add(rq);
goto out_obj;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index 37593831b539..4951957a4d8d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -42,6 +42,9 @@ static void trash_stolen(struct drm_i915_private *i915)
unsigned long page;
u32 prng = 0x12345678;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return;
+
for (page = 0; page < size; page += PAGE_SIZE) {
const dma_addr_t dma = i915->dsm.start + page;
u32 __iomem *s;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index f4d7b254c9a7..57dd237cd220 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1152,6 +1152,9 @@ static int igt_ggtt_page(void *arg)
unsigned int *order, n;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
mutex_lock(&i915->drm.struct_mutex);
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/22] drm/i915/lmem: support kernel mapping
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 36 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 8 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 20 -
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 +-
.../drm/i915/gem/selftests/huge_gem_object.c | 4 +-
.../drm/i915/selftests/intel_memory_region.c | 76 +++
9 files changed, 152 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index 5e72cb1cc2d3..c2e237702e8c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -140,7 +140,9 @@ static void i915_gem_object_put_pages_internal(struct
drm_i915_gem_object *obj,
static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
-I915_GEM_OBJECT_IS_SHRINKABLE,
+I915_GEM_OBJECT_IS_SHRINKABLE |
+I915_GEM_OBJECT_IS_MAPPABLE,
+
.get_pages = i915_gem_object_get_pages_internal,
.put_pages = i915_gem_object_put_pages_internal,
};
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 26a23304df32..d7ec74ed5b88 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -9,11 +9,47 @@
#include "i915_drv.h"
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .flags = I915_GEM_OBJECT_IS_MAPPABLE,
+
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
};
+/* XXX: Time to vfunc your life up? */
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, PAGE_SIZE);
+}
+
+void __iomem *i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
+}
+
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
struct intel_memory_region *region = obj->mm.region;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index ebc15fe24f58..31a6462bdbb6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -13,6 +13,14 @@ struct drm_i915_gem_object;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n, unsigned long size);
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n);
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index d5839cbd82c0..e8cc776581d0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -158,6 +158,12 @@ i915_gem_object_is_proxy(const struct drm_i915_gem_object
*obj)
return obj->ops->flags & I915_GEM_OBJECT_IS_PROXY;
}
+static inline bool
+i915_gem_object_is_mappable(const struct drm_i915_gem_object *obj)
+{
+ return obj->ops->flags & I915_GEM_OBJECT_IS_MAPPABLE;
+}
+
static inline bool
i915_gem_object_needs_async_cancel(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drive
[Intel-gfx] [PATCH 19/22] drm/i915: error capture with no ggtt slot
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
drivers/gpu/drm/i915/i915_gpu_error.c | 65 ++-
2 files changed, 64 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1be7b236f234..29f9c43b2c68 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2661,7 +2661,8 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
{
ggtt_release_guc_top(ggtt);
- drm_mm_remove_node(&ggtt->error_capture);
+ if (drm_mm_node_allocated(&ggtt->error_capture))
+ drm_mm_remove_node(&ggtt->error_capture);
}
static int init_ggtt(struct i915_ggtt *ggtt)
@@ -2692,13 +2693,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
if (ret)
return ret;
- /* Reserve a mappable slot for our lockless error capture */
- ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
- PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
- 0, ggtt->mappable_end,
- DRM_MM_INSERT_LOW);
- if (ret)
- return ret;
+ if (HAS_MAPPABLE_APERTURE(ggtt->vm.i915)) {
+ /* Reserve a mappable slot for our lockless error capture */
+ ret = drm_mm_insert_node_in_range(&ggtt->vm.mm,
&ggtt->error_capture,
+ PAGE_SIZE, 0,
I915_COLOR_UNEVICTABLE,
+ 0, ggtt->mappable_end,
+ DRM_MM_INSERT_LOW);
+ if (ret)
+ return ret;
+ }
/*
* The upper portion of the GuC address space has a sizeable hole
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 6384a06aa5bf..c6c96f0c6b28 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -40,6 +40,7 @@
#include "display/intel_overlay.h"
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "i915_gpu_error.h"
@@ -235,6 +236,7 @@ struct compress {
struct pagevec pool;
struct z_stream_s zstream;
void *tmp;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -292,7 +294,7 @@ static int compress_page(struct compress *c,
struct z_stream_s *zstream = &c->zstream;
zstream->next_in = src;
- if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
+ if (c->wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
zstream->next_in = c->tmp;
zstream->avail_in = PAGE_SIZE;
@@ -367,6 +369,7 @@ static void err_compression_marker(struct
drm_i915_error_state_buf *m)
struct compress {
struct pagevec pool;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -389,7 +392,7 @@ static int compress_page(struct compress *c,
if (!ptr)
return -ENOMEM;
- if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
+ if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
memcpy(ptr, src, PAGE_SIZE);
dst->pages[dst->page_count++] = ptr;
@@ -970,7 +973,6 @@ i915_error_object_create(struct drm_i915_private *i915,
struct drm_i915_error_object *dst;
unsigned long num_pages;
struct sgt_iter iter;
- dma_addr_t dma;
int ret;
might_sleep();
@@ -996,17 +998,54 @@ i915_error_object_create(struct drm_i915_private *i915,
dst->page_count = 0;
dst->unused = 0;
+ compress->wc = i915_gem_object_is_lmem(vma->obj) ||
+ drm_mm_node_allocated(&ggtt->error_capture);
+
ret = -EINVAL;
- for_each_sgt_daddr(dma, iter, vma->pages) {
+ if (drm_mm_node_allocated(&ggtt->error_capture)) {
void __iomem *s;
+ dma_addr_t dma;
- ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
+ for_each_sgt_daddr(dma, iter, vma->pages) {
+ ggtt->vm.insert_page(&ggtt->vm, dma, slot,
+I915_CACHE_NONE, 0);
- s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
- ret = compress_page(compress, (void __force *)s, dst);
- io_mapping_unmap(s);
- if (ret)
- break;
+ s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
+ ret = compress_page(compr
[Intel-gfx] [PATCH 17/22] drm/i915: set num_fence_regs to 0 if there is no aperture
From: Daniele Ceraolo Spurio We can't fence anything without aperture. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 615a9f4ef30c..e15e4e247576 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -828,8 +828,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) detect_bit_6_swizzle(i915); - if (INTEL_GEN(i915) >= 7 && - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) + if (!HAS_MAPPABLE_APERTURE(i915)) + num_fences = 0; + else if (INTEL_GEN(i915) >= 7 && +!(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) num_fences = 32; else if (INTEL_GEN(i915) >= 4 || IS_I945G(i915) || IS_I945GM(i915) || -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/22] drm/i915: Don't try to place HWS in non-existing mappable region
From: Michal Wajdeczko HWS placement restrictions can't just rely on HAS_LLC flag. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index f97686bdc28b..2e3f7a7507ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -513,7 +513,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && HAS_MAPPABLE_APERTURE(engine->i915)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena. -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/22] drm/i915: treat stolen as a region
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 71 +++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 14 +
drivers/gpu/drm/i915/i915_pci.c| 2 +-
5 files changed, 68 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 0aeaebb41050..77e89fabbddf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -159,7 +159,7 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
return ERR_PTR(-E2BIG);
obj = mem->ops->create_object(mem, size, flags);
- if (!IS_ERR(obj))
+ if (!IS_ERR_OR_NULL(obj))
trace_i915_gem_object_create(obj);
return obj;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index bfbc3e3daf92..1ee8f1790144 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -10,6 +10,7 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
@@ -150,7 +151,7 @@ static int i915_adjust_stolen(struct drm_i915_private
*dev_priv,
return 0;
}
-void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
+static void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
{
if (!drm_mm_initialized(&dev_priv->mm.stolen))
return;
@@ -355,7 +356,7 @@ static void icl_get_stolen_reserved(struct drm_i915_private
*i915,
}
}
-int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
+static int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
{
resource_size_t reserved_base, stolen_top;
resource_size_t reserved_total, reserved_size;
@@ -539,6 +540,9 @@ i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj)
i915_gem_stolen_remove_node(dev_priv, stolen);
kfree(stolen);
+
+ if (obj->mm.region)
+ i915_gem_object_release_memory_region(obj);
}
static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
@@ -548,8 +552,9 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_stolen_ops = {
};
static struct drm_i915_gem_object *
-_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- struct drm_mm_node *stolen)
+__i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ struct drm_mm_node *stolen,
+ struct intel_memory_region *mem)
{
struct drm_i915_gem_object *obj;
unsigned int cache_level;
@@ -566,6 +571,9 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE;
i915_gem_object_set_cache_coherency(obj, cache_level);
+ if (mem)
+ i915_gem_object_init_memory_region(obj, mem, 0);
+
if (i915_gem_object_pin_pages(obj))
goto cleanup;
@@ -576,10 +584,12 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- resource_size_t size)
+static struct drm_i915_gem_object *
+_i915_gem_object_create_stolen(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags)
{
+ struct drm_i915_private *dev_priv = mem->i915;
struct drm_i915_gem_object *obj;
struct drm_mm_node *stolen;
int ret;
@@ -600,7 +610,7 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
- obj = _i915_gem_object_create_stolen(dev_priv, stolen);
+ obj = __i915_gem_object_create_stolen(dev_priv, stolen, mem);
if (obj)
return obj;
@@ -609,6 +619,49 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
+struct drm_i915_gem_object *
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ resource_size_t size)
+{
+ struct drm_i915_gem_object *obj;
+
+ obj =
i915_gem_object_create_region(dev_priv->mm.regions[INTEL_MEMORY_STOLEN],
+ size, I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj))
+ return NULL;
+
+ return obj;
+}
+
+static int init_stolen(struct intel_memory_region *mem)
+{
+ /*
+* Initialise stolen early so that we may rese
[Intel-gfx] [PATCH 10/22] drm/i915/selftests: add write-dword test for LMEM
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 179 ++
1 file changed, 179 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index ba98e8254b80..8d7d8b9e00da 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -7,13 +7,16 @@
#include "../i915_selftest.h"
+
#include "mock_drm.h"
#include "mock_gem_device.h"
#include "mock_region.h"
+#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_object_blt.h"
+#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
#include "selftests/igt_flush_test.h"
@@ -255,6 +258,133 @@ static int igt_mock_continuous(void *arg)
return err;
}
+static int igt_gpu_write_dw(struct intel_context *ce,
+ struct i915_vma *vma,
+ u32 dword,
+ u32 value)
+{
+ int err;
+
+ i915_gem_object_lock(vma->obj);
+ err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+ i915_gem_object_unlock(vma->obj);
+ if (err)
+ return err;
+
+ return igt_gpu_fill_dw(ce, vma, dword * sizeof(u32),
+ vma->size >> PAGE_SHIFT, value);
+}
+
+static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int igt_gpu_write(struct i915_gem_context *ctx,
+struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
+ struct i915_gem_engines *engines;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ I915_RND_STATE(prng);
+ IGT_TIMEOUT(end_time);
+ unsigned int count;
+ struct i915_vma *vma;
+ int *order;
+ int i, n;
+ int err = 0;
+
+ GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+
+ n = 0;
+ count = 0;
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ count++;
+ if (!intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ n++;
+ }
+ i915_gem_context_unlock_engines(ctx);
+ if (!n)
+ return 0;
+
+ order = i915_random_order(count * count, &prng);
+ if (!order)
+ return -ENOMEM;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_free;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_free;
+
+ i = 0;
+ engines = i915_gem_context_lock_engines(ctx);
+ do {
+ u32 rng = prandom_u32_state(&prng);
+ u32 dword = offset_in_page(rng) / 4;
+
+ ce = engines->engines[order[i] % engines->num_engines];
+ i = (i + 1) % (count * count);
+ if (!ce || !intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ err = igt_gpu_write_dw(ce, vma, dword, rng);
+ if (err)
+ break;
+
+ err = igt_cpu_check(obj, dword, rng);
+ if (err)
+ break;
+ } while (!__igt_timeout(end_time, NULL));
+ i915_gem_context_unlock_engines(ctx);
+
+out_free:
+ kfree(order);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_lmem_create(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -276,6 +406,54 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_write_gpu(void *a
[Intel-gfx] [PATCH 11/22] drm/i915/selftest: extend coverage to include LMEM huge-pages
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index b6dc90030156..434c1fc57adf 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -9,6 +9,7 @@
#include "i915_selftest.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
@@ -970,7 +971,7 @@ static int gpu_write(struct intel_context *ce,
vma->size >> PAGE_SHIFT, val);
}
-static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+static int __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
{
unsigned int needs_flush;
unsigned long n;
@@ -1002,6 +1003,51 @@ static int cpu_check(struct drm_i915_gem_object *obj,
u32 dword, u32 val)
return err;
}
+static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ if (i915_gem_object_has_struct_page(obj))
+ return __cpu_check_shmem(obj, dword, val);
+ else if (i915_gem_object_is_lmem(obj))
+ return __cpu_check_lmem(obj, dword, val);
+
+ return -ENODEV;
+}
+
static int __igt_write_huge(struct intel_context *ce,
struct drm_i915_gem_object *obj,
u64 size, u64 offset,
@@ -1386,6 +1432,78 @@ static int igt_ppgtt_gemfs_huge(void *arg)
return err;
}
+static int igt_ppgtt_lmem_huge(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ static const unsigned int sizes[] = {
+ SZ_64K,
+ SZ_512K,
+ SZ_1M,
+ SZ_2M,
+ };
+ int i;
+ int err;
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /*
+* Sanity check that the HW uses huge pages correctly through LMEM
+* -- ensure that our writes land in the right place.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+ unsigned int size = sizes[i];
+
+ obj = i915_gem_object_create_lmem(i915, size,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ pr_info("object too big for region!\n");
+ return 0;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM unable to allocate huge-page(s) with
size=%u\n",
+ size);
+ goto out_unpin;
+ }
+
+ err = igt_write_huge(ctx, obj);
+ if (err) {
+ pr_err("LMEM write-huge failed with size=%u\n", size);
+ goto out_unpin;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+ }
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1742,6 +1860,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
[Intel-gfx] [PATCH 02/22] drm/i915: simplify i915_gem_init_early
i915_gem_init_early doesn't need to return anything.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c | 5 +
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 4 +---
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a9ee73b61f4d..91aae56b4280 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -589,9 +589,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
intel_gt_init_early(&dev_priv->gt, dev_priv);
- ret = i915_gem_init_early(dev_priv);
- if (ret < 0)
- goto err_gt;
+ i915_gem_init_early(dev_priv);
/* This must be called before any calls to HAS_PCH_* */
intel_detect_pch(dev_priv);
@@ -613,7 +611,6 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
err_gem:
i915_gem_cleanup_early(dev_priv);
-err_gt:
intel_gt_driver_late_release(&dev_priv->gt);
vlv_free_s0ix_state(dev_priv);
err_workqueues:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b3c7dbc1832a..0dc504fc6ffc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2250,7 +2250,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void
*data,
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
void i915_gem_sanitize(struct drm_i915_private *i915);
-int i915_gem_init_early(struct drm_i915_private *dev_priv);
+void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
int i915_gem_freeze(struct drm_i915_private *dev_priv);
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e2897a666225..3d3fda4cae99 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1533,7 +1533,7 @@ static void i915_gem_init__mm(struct drm_i915_private
*i915)
i915_gem_init__objects(i915);
}
-int i915_gem_init_early(struct drm_i915_private *dev_priv)
+void i915_gem_init_early(struct drm_i915_private *dev_priv)
{
int err;
@@ -1545,8 +1545,6 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
err = i915_gemfs_init(dev_priv);
if (err)
DRM_NOTE("Unable to create a private tmpfs mount, hugepage
support will be disabled(%d).\n", err);
-
- return 0;
}
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/22] drm/i915/region: support continuous allocations
Some kernel internal objects may need to be allocated as a continuous
block, also thinking ahead the various kernel io_mapping interfaces seem
to expect it, although this is purely a limitation in the kernel
API...so perhaps something to be improved.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 4 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 15 +-
drivers/gpu/drm/i915/gem/i915_gem_region.h| 3 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 3 +-
drivers/gpu/drm/i915/intel_memory_region.c| 13 +-
drivers/gpu/drm/i915/intel_memory_region.h| 3 +-
.../drm/i915/selftests/intel_memory_region.c | 163 ++
drivers/gpu/drm/i915/selftests/mock_region.c | 2 +-
8 files changed, 197 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index d36c860c9c6f..7acd383f174f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -117,6 +117,10 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
+ unsigned long flags;
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+
/*
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 5c3bfc121921..b317a5c84144 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -23,10 +23,10 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
{
struct intel_memory_region *mem = obj->mm.region;
struct list_head *blocks = &obj->mm.blocks;
- unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
resource_size_t size = obj->base.size;
resource_size_t prev_end;
struct i915_buddy_block *block;
+ unsigned int flags;
struct sg_table *st;
struct scatterlist *sg;
unsigned int sg_page_sizes;
@@ -42,6 +42,10 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
return -ENOMEM;
}
+ flags = I915_ALLOC_MIN_PAGE_SIZE;
+ if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
+ flags |= I915_ALLOC_CONTIGUOUS;
+
ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
if (ret)
goto err_free_sg;
@@ -56,7 +60,8 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
list_for_each_entry(block, blocks, link) {
u64 block_size, offset;
- block_size = i915_buddy_block_size(&mem->mm, block);
+ block_size = min_t(u64, size,
+ i915_buddy_block_size(&mem->mm, block));
offset = i915_buddy_block_offset(block);
GEM_BUG_ON(overflows_type(block_size, sg->length));
@@ -98,10 +103,12 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
}
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem)
+ struct intel_memory_region *mem,
+ unsigned long flags)
{
INIT_LIST_HEAD(&obj->mm.blocks);
obj->mm.region = mem;
+ obj->flags = flags;
}
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj)
@@ -115,6 +122,8 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
{
struct drm_i915_gem_object *obj;
+ GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
+
if (!mem)
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h
b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index ebddc86d78f7..f2ff6f8bff74 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -17,7 +17,8 @@ void i915_gem_object_put_pages_buddy(struct
drm_i915_gem_object *obj,
struct sg_table *pages);
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem);
+ struct intel_memory_region *mem,
+ unsigned long flags);
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 4e1805aaeb99..f9fbf2865782 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -471,7 +471,8 @@ static int igt_mock
[Intel-gfx] [PATCH 03/22] drm/i915: introduce intel_memory_region
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and of course device. At some point we are probably going to want
use a common struct here, such that we are better aligned with say TTM.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Niranjana Vishwanathapura
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile | 2 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 133 ++
drivers/gpu/drm/i915/gem/i915_gem_region.h| 28 +++
.../gpu/drm/i915/gem/selftests/huge_pages.c | 78
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_memory_region.c| 173 ++
drivers/gpu/drm/i915/intel_memory_region.h| 77
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 124 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
drivers/gpu/drm/i915/selftests/mock_region.c | 59 ++
drivers/gpu/drm/i915/selftests/mock_region.h | 16 ++
13 files changed, 702 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h
create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6313e7b4bd78..d849dff31f76 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -50,6 +50,7 @@ i915-y += i915_drv.o \
i915_utils.o \
intel_csr.o \
intel_device_info.o \
+ intel_memory_region.o \
intel_pch.o \
intel_pm.o \
intel_runtime_pm.o \
@@ -118,6 +119,7 @@ gem-y += \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
gem/i915_gem_pm.o \
+ gem/i915_gem_region.o \
gem/i915_gem_shmem.o \
gem/i915_gem_shrinker.o \
gem/i915_gem_stolen.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index d695f187b790..d36c860c9c6f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -158,6 +158,15 @@ struct drm_i915_gem_object {
atomic_t pages_pin_count;
atomic_t shrink_pin;
+ /**
+* Memory region for this object.
+*/
+ struct intel_memory_region *region;
+ /**
+* List of memory region blocks allocated for this object.
+*/
+ struct list_head blocks;
+
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
new file mode 100644
index ..5c3bfc121921
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "i915_gem_region.h"
+#include "i915_drv.h"
+
+void
+i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
+ struct sg_table *pages)
+{
+ __intel_memory_region_put_pages_buddy(obj->mm.region, &obj->mm.blocks);
+
+ obj->mm.dirty = false;
+ sg_free_table(pages);
+ kfree(pages);
+}
+
+int
+i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ struct list_head *blocks = &obj->mm.blocks;
+ unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
+ resource_size_t size = obj->base.size;
+ resource_size_t prev_end;
+ struct i915_buddy_block *block;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ unsigned int sg_page_sizes;
+ unsigned long i;
+ int ret;
+
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ if (sg_alloc_table(st, size >> ilog2(mem->mm.chunk_size), GFP_KERNEL)) {
+ kfree(st);
+ return -ENOMEM;
+ }
+
+ ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
+ if (ret)
+ goto err_free_sg;
+
+ GEM_BUG_ON(list_empty(blocks));
+
+ sg = st->sgl;
+ st->nents = 0;
+ sg_page_sizes = 0;
+ i = 0;
+
+
[Intel-gfx] [PATCH 08/22] drm/i915: setup io-mapping for LMEM
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index 7a3f96e1f766..051069664074 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -36,8 +36,32 @@ lmem_create_object(struct intel_memory_region *mem,
return obj;
}
+static void
+region_lmem_release(struct intel_memory_region *mem)
+{
+ io_mapping_fini(&mem->iomap);
+ intel_memory_region_release_buddy(mem);
+}
+
+static int
+region_lmem_init(struct intel_memory_region *mem)
+{
+ int ret;
+
+ if (!io_mapping_init_wc(&mem->iomap,
+ mem->io_start,
+ resource_size(&mem->region)))
+ return -EIO;
+
+ ret = intel_memory_region_init_buddy(mem);
+ if (ret)
+ io_mapping_fini(&mem->iomap);
+
+ return ret;
+}
+
const struct intel_memory_region_ops intel_region_lmem_ops = {
- .init = intel_memory_region_init_buddy,
- .release = intel_memory_region_release_buddy,
+ .init = region_lmem_init,
+ .release = region_lmem_release,
.create_object = lmem_create_object,
};
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/22] drm/i915/region: support volatile objects
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded. This is limited to kernel
internal objects.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c| 17 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 6 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h| 9 -
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 ++
drivers/gpu/drm/i915/gem/i915_gem_region.c | 12
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 12
drivers/gpu/drm/i915/intel_memory_region.c | 4
drivers/gpu/drm/i915/intel_memory_region.h | 5 +
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 5 ++---
9 files changed, 56 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index 0c41e04ab8fa..5e72cb1cc2d3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -117,13 +117,6 @@ static int i915_gem_object_get_pages_internal(struct
drm_i915_gem_object *obj)
goto err;
}
- /* Mark the pages as dontneed whilst they are still pinned. As soon
-* as they are unpinned they are allowed to be reaped by the shrinker,
-* and the caller is expected to repopulate - the contents of this
-* object are only valid whilst active and pinned.
-*/
- obj->mm.madv = I915_MADV_DONTNEED;
-
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
@@ -143,7 +136,6 @@ static void i915_gem_object_put_pages_internal(struct
drm_i915_gem_object *obj,
internal_free_pages(pages);
obj->mm.dirty = false;
- obj->mm.madv = I915_MADV_WILLNEED;
}
static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
@@ -188,6 +180,15 @@ i915_gem_object_create_internal(struct drm_i915_private
*i915,
drm_gem_private_object_init(&i915->drm, &obj->base, size);
i915_gem_object_init(obj, &i915_gem_object_internal_ops);
+ /*
+* Mark the object as volatile, such that the pages are marked as
+* dontneed whilst they are still pinned. As soon as they are unpinned
+* they are allowed to be reaped by the shrinker, and the caller is
+* expected to repopulate - the contents of this object are only valid
+* whilst active and pinned.
+*/
+ obj->flags = I915_BO_ALLOC_VOLATILE;
+
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 29b9eddc4c7f..d5839cbd82c0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -122,6 +122,12 @@ i915_gem_object_lock_fence(struct drm_i915_gem_object
*obj);
void i915_gem_object_unlock_fence(struct drm_i915_gem_object *obj,
struct dma_fence *fence);
+static inline bool
+i915_gem_object_is_volatile(const struct drm_i915_gem_object *obj)
+{
+ return obj->flags & I915_BO_ALLOC_VOLATILE;
+}
+
static inline void
i915_gem_object_set_readonly(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 7acd383f174f..0d934b67e547 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -119,7 +119,8 @@ struct drm_i915_gem_object {
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | I915_BO_ALLOC_VOLATILE)
/*
* Is the object to be mapped as read-only to the GPU
@@ -170,6 +171,12 @@ struct drm_i915_gem_object {
* List of memory region blocks allocated for this object.
*/
struct list_head blocks;
+ /**
+* Element within memory_region->objects or region->purgeable
+* if the object is marked as DONTNEED. Access is protected by
+* region->obj_lock.
+*/
+ struct list_head region_link;
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 2e941f093a20..b0ec0959c13f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -18,6 +18,9 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
lockdep_assert_held(&obj->mm.lock);
+ if (i915_gem_object_is_volatile
[Intel-gfx] [PATCH 06/22] drm/i915: Add memory region information to device_info
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8ed4b8c2484f..93116cc8b149 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2170,6 +2170,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
/* Having GuC is not the same as using GuC */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0cdc2465534b..e9940f932d26 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -160,6 +160,8 @@ struct intel_device_info {
unsigned int page_sizes; /* page sizes supported by the HW */
+ u32 memory_regions; /* regions supported by the HW */
+
u32 display_mmio_offset;
u8 pipe_mask;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/22] LMEM basics
The basic LMEM bits, minus the uAPI, pruning, etc. The goal is to support basic LMEM object creation within the kernel. From there we can start with the dumb buffer support, and then the other display related bits. We still have a few patches that deal with lack of MAPPABLE_APERTURE support, though we can probably split that into its own series. Patches 1-2 are just noise. Patches 3-6 are the basic intel_memory_region bits + basic mock_selftests. Patches 7-11 are the basic LMEM region bits + basic live_selftests. Patches 12-14 try to turn stolen + shmem into intel_region_regions. Patches 15-21 implement the !MAPPABLE_APERTURE bits. The fake LMEM patch allows us to run the live_selftests with LMEM enabled and !HAS_MAPPABLE_APERTURE in CI. Abdiel Janulgue (4): drm/i915: Add memory region information to device_info drm/i915: setup io-mapping for LMEM drm/i915/lmem: support kernel mapping drm/i915: enumerate and init each supported region CQ Tang (1): drm/i915: check for missing aperture in GTT pread/pwrite paths Daniele Ceraolo Spurio (4): drm/i915: define HAS_MAPPABLE_APERTURE drm/i915: do not map aperture if it is not available. drm/i915: set num_fence_regs to 0 if there is no aperture drm/i915: error capture with no ggtt slot Matthew Auld (12): drm/i915: check for kernel_context drm/i915: simplify i915_gem_init_early drm/i915: introduce intel_memory_region drm/i915/region: support continuous allocations drm/i915/region: support volatile objects drm/i915: support creating LMEM objects drm/i915/selftests: add write-dword test for LMEM drm/i915/selftest: extend coverage to include LMEM huge-pages drm/i915: treat shmem as a region drm/i915: treat stolen as a region drm/i915/selftests: check for missing aperture HAX drm/i915: add the fake lmem region Michal Wajdeczko (1): drm/i915: Don't try to place HWS in non-existing mappable region arch/x86/kernel/early-quirks.c| 26 + drivers/gpu/drm/i915/Makefile | 4 + drivers/gpu/drm/i915/gem/i915_gem_internal.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 70 +++ drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 31 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 12 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 23 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 26 +- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +- drivers/gpu/drm/i915/gem/i915_gem_region.c| 166 + drivers/gpu/drm/i915/gem/i915_gem_region.h| 29 + drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 71 ++- drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 71 ++- drivers/gpu/drm/i915/gem/i915_gem_stolen.h| 3 +- .../drm/i915/gem/selftests/huge_gem_object.c | 4 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 212 ++- .../i915/gem/selftests/i915_gem_coherency.c | 5 +- .../drm/i915/gem/selftests/i915_gem_mman.c| 6 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 +- drivers/gpu/drm/i915/i915_drv.c | 13 +- drivers/gpu/drm/i915/i915_drv.h | 17 +- drivers/gpu/drm/i915/i915_gem.c | 19 +- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 119 +++- drivers/gpu/drm/i915/i915_gpu_error.c | 65 +- drivers/gpu/drm/i915/i915_pci.c | 29 +- drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/intel_memory_region.c| 192 ++ drivers/gpu/drm/i915/intel_memory_region.h| 119 drivers/gpu/drm/i915/intel_region_lmem.c | 157 + drivers/gpu/drm/i915/intel_region_lmem.h | 16 + drivers/gpu/drm/i915/selftests/i915_gem.c | 3 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 8 +- .../drm/i915/selftests/i915_live_selftests.h | 1 + .../drm/i915/selftests/i915_mock_selftests.h | 1 + .../drm/i915/selftests/intel_memory_region.c | 587 ++ .../gpu/drm/i915/selftests/mock_gem_device.c | 9 +- drivers/gpu/drm/i915/selftests/mock_region.c | 59 ++ drivers/gpu/drm/i915/selftests/mock_region.h | 16 + include/drm/i915_drm.h| 3 + 41 files changed, 2115 insertions(+), 134 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h -- 2.
[Intel-gfx] [PATCH 01/22] drm/i915: check for kernel_context
Explosions during early driver init on the error path. Make sure we fail
gracefully.
[ 9547.672258] BUG: kernel NULL pointer dereference, address: 007c
[ 9547.672288] #PF: supervisor read access in kernel mode
[ 9547.672292] #PF: error_code(0x) - not-present page
[ 9547.672296] PGD 800846b41067 P4D 800846b41067 PUD 797034067 PMD 0
[ 9547.672303] Oops: [#1] SMP PTI
[ 9547.672307] CPU: 1 PID: 25634 Comm: i915_selftest Tainted: G U
5.3.0-rc8+ #73
[ 9547.672313] Hardware name: /NUC6i7KYB, BIOS
KYSKLi70.86A.0050.2017.0831.1924 08/31/2017
[ 9547.672395] RIP: 0010:intel_context_unpin+0x9/0x100 [i915]
[ 9547.672400] Code: 6b 60 00 e9 17 ff ff ff bd fc ff ff ff e9 7c ff ff ff 66
66 2e 0f 1f 84 00 00 00 00
00 0f 1f 40 00 0f 1f 44 00 00 41 54 55 53 <8b> 47 7c 83 f8 01 74 26 8d 48 ff
f0 0f b1 4f 7c 48 8d 57 7c
75 05
[ 9547.672413] RSP: 0018:ae8ac24ff878 EFLAGS: 00010246
[ 9547.672417] RAX: 944a1b7842d0 RBX: 944a1b784000 RCX: 944a12dd6fa8
[ 9547.672422] RDX: 944a1b7842c0 RSI: 944a12dd5328 RDI:
[ 9547.672428] RBP: R08: 944a11e5d840 R09:
[ 9547.672433] R10: R11: R12:
[ 9547.672438] R13: c11aaf00 R14: ffe4 R15: 944a0e29bf38
[ 9547.672443] FS: 7fc259b88ac0() GS:944a1f88()
knlGS:
[ 9547.672449] CS: 0010 DS: ES: CR0: 80050033
[ 9547.672454] CR2: 007c CR3: 000853346003 CR4: 003606e0
[ 9547.672459] DR0: DR1: DR2:
[ 9547.672464] DR3: DR6: fffe0ff0 DR7: 0400
[ 9547.672469] Call Trace:
[ 9547.672518] intel_engine_cleanup_common+0xe3/0x270 [i915]
[ 9547.672567] execlists_destroy+0xe/0x30 [i915]
[ 9547.672669] intel_engines_init+0x94/0xf0 [i915]
[ 9547.672749] i915_gem_init+0x191/0x950 [i915]
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f451d5076bde..f97686bdc28b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -820,8 +820,11 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
if (engine->default_state)
i915_gem_object_put(engine->default_state);
- intel_context_unpin(engine->kernel_context);
- intel_context_put(engine->kernel_context);
+ if (engine->kernel_context) {
+ intel_context_unpin(engine->kernel_context);
+ intel_context_put(engine->kernel_context);
+ }
+
GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
intel_wa_list_free(&engine->ctx_wa_list);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming
== Series Details == Series: series starting with [CI,1/4] drm/i915/tc: Update DP_MODE programming URL : https://patchwork.freedesktop.org/series/67312/ State : success == Summary == CI Bug Log - changes from CI_DRM_6966_full -> Patchwork_14561_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14561_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +16 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@gem_exec_sched...@reorder-wide-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_tiled_wc: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb3/igt@gem_tiled_wc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb7/igt@gem_tiled_wc.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107807]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl2/igt@i915_pm_...@system-suspend-execbuf.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl5/igt@i915_pm_...@system-suspend-execbuf.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl5/igt@i915_susp...@sysfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl4/igt@i915_susp...@sysfs-reader.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-x.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-apl1/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-apl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-skl10/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-skl8/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111764]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb1/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb7/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html Possible fixes * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [SKIP][23] ([fdo#109276]) -> [PASS][24] +11 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6966/shard-iclb6/igt@gem_ctx_isolat...@vcs1-dirty-create.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14561/shard-iclb2/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][25] ([fdo#110854]) ->
Re: [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV
On Thu, Sep 26, 2019 at 03:34:35PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 25, 2019 at 01:33:52PM -0700, James Ausmus wrote:
> > For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
> > active. Update intel_can_enable_sagv to allow this, and loop through all
> > active planes on all active crtcs to check against the interlaced and
> > latency restrictions.
> >
> > BSpec: 49325
> >
> > Cc: Ville Syrjälä
> > Cc: Stanislav Lisovskiy
> > Cc: Lucas De Marchi
> > Signed-off-by: James Ausmus
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 63 +
> > 1 file changed, 32 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index ca2bec09edb5..cb50c697a6b8 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3775,7 +3775,6 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> > *state)
> > struct intel_crtc *crtc;
> > struct intel_plane *plane;
> > struct intel_crtc_state *crtc_state;
> > - enum pipe pipe;
> > int level, latency;
> > int sagv_block_time_us;
> >
> > @@ -3791,47 +3790,49 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > return true;
> >
> > /*
> > -* SKL+ workaround: bspec recommends we disable SAGV when we have
> > +* SKL-ICL workaround: bspec recommends we disable SAGV when we have
> > * more then one pipe enabled
> > */
> > - if (hweight8(state->active_pipes) > 1)
> > + if (INTEL_GEN(dev_priv) < 12 && hweight8(state->active_pipes) > 1)
> > return false;
> >
> > - /* Since we're now guaranteed to only have one active CRTC... */
> > - pipe = ffs(state->active_pipes) - 1;
> > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > + for_each_intel_crtc(&dev_priv->drm, crtc) {
> > + crtc_state = to_intel_crtc_state(crtc->base.state);
> > + if (!crtc_state->base.active)
> > + continue;
> >
> > - if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > - return false;
> > + if (crtc->base.state->adjusted_mode.flags &
> > + DRM_MODE_FLAG_INTERLACE)
> > + return false;
> >
> > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > - struct skl_plane_wm *wm =
> > - &crtc_state->wm.skl.optimal.planes[plane->id];
> > + for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > + struct skl_plane_wm *wm =
> > + &crtc_state->wm.skl.optimal.planes[plane->id];
>
> This whole loop is bothering me. I'd much rather we move to a scheme
> where each plane computes it's SAGV friendlyness when computing the
> watermarks. We'll anyway need that since we need to caclulate the
> watermarks differently for the SAGV on vs. off cases.
Hmm, I'll have to look in to this. In the meantime, I'd like to get
patches 1 & 2 of this series moving forward, as those should be what's
really necessary to be able to turn on SAGV for TGL once we're ready, so
I'll send those as a separate series, and leave relaxing the 1 pipe
restriction as it's own work.
-James
>
> >
> > - /* Skip this plane if it's not enabled */
> > - if (!wm->wm[0].plane_en)
> > - continue;
> > + /* Skip this plane if it's not enabled */
> > + if (!wm->wm[0].plane_en)
> > + continue;
> >
> > - /* Find the highest enabled wm level for this plane */
> > - for (level = ilk_wm_max_level(dev_priv);
> > -!wm->wm[level].plane_en; --level)
> > -{ }
> > + /* Find the highest enabled wm level for this plane */
> > + for (level = ilk_wm_max_level(dev_priv);
> > +!wm->wm[level].plane_en; --level)
> > +{ }
> >
> > - latency = dev_priv->wm.skl_latency[level];
> > + latency = dev_priv->wm.skl_latency[level];
> >
> > - if (skl_needs_memory_bw_wa(dev_priv) &&
> > - plane->base.state->fb->modifier ==
> > - I915_FORMAT_MOD_X_TILED)
> > - latency += 15;
> > + if (skl_needs_memory_bw_wa(dev_priv) &&
> > + plane->base.state->fb->modifier ==
> > + I915_FORMAT_MOD_X_TILED)
> > + latency += 15;
> >
> > - /*
> > -* If any of the planes on this pipe don't enable wm levels that
> > -* incur memory latencies higher than sagv_block_time_us we
> > -* can't enable SAGV.
> > -*/
> > - if (latency < sagv_block_time_us)
> > - return false;
> > + /*
> > +
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/userptr: Never allow userptr into the mappable GGTT
== Series Details ==
Series: drm/i915/userptr: Never allow userptr into the mappable GGTT
URL : https://patchwork.freedesktop.org/series/67349/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6969 -> Patchwork_14568
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14568/index.html
Known issues
Here are the changes found in Patchwork_14568 that come from known issues:
### IGT changes ###
Issues hit
* igt@prime_busy@basic-wait-before-default:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/fi-icl-u3/igt@prime_b...@basic-wait-before-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14568/fi-icl-u3/igt@prime_b...@basic-wait-before-default.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][3] ([fdo#103927] / [fdo#111381]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14568/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14568/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_module_load@reload:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724] / [fdo#111214]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/fi-icl-u3/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14568/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [FAIL][9] ([fdo#107707]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14568/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/fi-icl-u3/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14568/fi-icl-u3/igt@i915_pm_...@module-reload.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#111045]
/ [fdo#111096])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6969/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14568/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (51 -> 45)
--
Additional (2): fi-hsw-peppy fi-skl-guc
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6969 -> Patchwork_14568
CI-20190529: 20190529
CI_DRM_6969: ad0d6a2a5bb90cccef673bf3722a8ee08647cf7f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14568: e7fbf6cde45c8cf137b60ab119d7400609829120 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e7fbf6cde45c drm/i915/userptr: Never allow userptr into the mappable GGTT
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14568/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v9 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info
On 2019-09-27 at 19:38:49 +0300, Imre Deak wrote:
> On Thu, Sep 26, 2019 at 08:26:21PM +0530, Anshuman Gupta wrote:
> > Adding DC3CO counter in i915_dmc_info debugfs will be
> > useful for DC3CO validation.
> > DMC firmware uses DMC_DEBUG3 register as DC3CO counter
> > register on TGL, as per B.Specs DMC_DEBUG3 is general
> > purpose register.
> >
> > Cc: Jani Nikula
> > Cc: Imre Deak
> > Cc: Animesh Manna
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index b5b449a88cf1..8a16bbd31212 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2407,6 +2407,12 @@ static int i915_dmc_info(struct seq_file *m, void
> > *unused)
> > seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> >CSR_VERSION_MINOR(csr->version));
> >
> > + /*
> > +* TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter.
> > +*/
>
> The above is obvious from the code itself, so we don't need a comment
> for it. Please also consider removing all other comments in the patchset
> that state only what is obvious from the code.
DMC_DEBUG3 is a DMC general purpose register, B.Specs doesn't specify
it as DC3CO counter unlike DC5 and DC6, that is why i have added
this comment. Shall i remove this comment considering DMC_DEBUG3
as general purpose register?
>
> > + if (IS_TIGERLAKE(dev_priv))
>
> The above should match the check in get_allowed_dc_mask().
IS_TIGERLAKE is being checked for the same reason as TGL
DMC is using DMC_DEBUG3 for DC3CO counter. It may not be true
for other Gen12 platfrom.
Thanks,
Anshuman Gupta.
>
> > + seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
> > +
> > if (INTEL_GEN(dev_priv) >= 12) {
> > dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 3ee9720af207..af810f6ed652 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7263,6 +7263,8 @@ enum {
> > #define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
> > #define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
> >
> > +#define DMC_DEBUG3 _MMIO(0x101090)
> > +
> > /* interrupts */
> > #define DE_MASTER_IRQ_CONTROL (1 << 31)
> > #define DE_SPRITEB_FLIP_DONE(1 << 29)
> > --
> > 2.21.0
> >
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/21] drm/i915: Mark up address spaces that may need to allocate
Quoting Tvrtko Ursulin (2019-09-25 16:59:26)
>
> On 25/09/2019 09:23, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-23 09:10:26)
> >>
> >> On 20/09/2019 17:35, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2019-09-20 17:22:42)
>
> On 02/09/2019 05:02, Chris Wilson wrote:
> > Since we cannot allocate underneath the vm->mutex (it is used in the
> > direct-reclaim paths), we need to shift the allocations off into a
> > mutexless worker with fence recursion prevention. To know when we need
> > this protection, we mark up the address spaces that do allocate before
> > insertion.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +++
> > drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 9095f017162e..56d27cf09a3d 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -1500,6 +1500,7 @@ static struct i915_ppgtt
> > *gen8_ppgtt_create(struct drm_i915_private *i915)
> > goto err_free_pd;
> > }
> >
> > + ppgtt->vm.bind_alloc = I915_VMA_LOCAL_BIND;
>
> So this is re-using I915_VMA_LOCAL_BIND as a trick? Is it clear how that
> works from these call sites? Should it be called bind_alloc*s*?
> bind_allocates? Or be a boolean which is converted to a trick flag in
> i915_vma_bind where a comment can be put explaining the trick?
> >>>
> >>> Is it a trick? We need to differentiate between requests for LOCAL_BIND,
> >>> GLOBAL_BIND, LOCAL_BIND | GLOBAL_BIND, for different types of vm. Then I
> >>> have a plan on using the worker for GLOBAL_BIND on bsw/bxt to defer the
> >>> stop_machine().
> >>
> >> What's the connection between "mark up the address spaces that do
> >> allocate before insertion" and I915_VMA_LOCAL_BIND?
> >
> > Full-ppgtt is only accessible by PIN_USER.
> >
> > Aliasing-ppgtt is accessible from global-gtt as PIN_USER. Only if we
> > have an aliasing-gtt behind ggtt do we want to allocate for ggtt for
> > local binds.
> >
> > global-gtt by itself never allocates and is expected to be synchronous.
> > However, we do use stop_machine() for bxt/bsw and that unfortunately is
> > marked as an allocating mutex so one idea I had for avoiding that
> > lockdep splat was to make bxt/bsw PIN_GLOBAL async.
>
> I think we are not understanding each other from the very start.
>
> My point was that "vm.bind_alloc = I915_VMA_LOCAL_BIND", at least my
> understanding, effectively means "use the worker when pinning/binding
> PIN_USER/I915_VMA_LOCAL_BIND". And that is I think non-obvious. Where
> you have in the code:
>
> if (flags & vma->vm->bind_alloc)
>
> It is a shorter hacky way of saying:
>
> if (*flags & I915_VMA_LOCAL_BIND) &&
> vma->vm->bind_allocates)
>
> Or where you have:
>
> if (work && (bind_flags & ~vma_flags) & vma->vm->bind_alloc) {
>
> This would be:
>
> if (work &&
> vma->vm->bind_allocates &&
> (bind_flags & I915_VMA_LOCAL_BIND) &&
> !(vma_flags & I915_VMA_LOCAL_BIND)) {
>
> But I think I see now what your code is actually saying, you are having
> vm->bind_alloc mean vm->bind_flags_which_allocate. Did I get your
> thinking right now? If so compromise with renaming to vm->bind_alloc_flags?
vm->bind_alloc_flags it is.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
