[Intel-gfx] ✗ Fi.CI.IGT: failure for DP Phy compliace auto test.
== Series Details ==
Series: DP Phy compliace auto test.
URL : https://patchwork.freedesktop.org/series/67546/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6998_full -> Patchwork_14653_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14653_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14653_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14653_full:
### IGT changes ###
Possible regressions
* igt@gem_mmap_gtt@basic-small-copy:
- shard-hsw: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw5/igt@gem_mmap_...@basic-small-copy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-hsw1/igt@gem_mmap_...@basic-small-copy.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@pm-tiling:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb5/igt@i915_pm_...@pm-tiling.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-tglb1/igt@i915_pm_...@pm-tiling.html
Known issues
Here are the changes found in Patchwork_14653_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb7/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-iclb2/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
* igt@gem_userptr_blits@coherency-sync:
- shard-hsw: [PASS][7] -> [DMESG-WARN][8] ([fdo#111870]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw2/igt@gem_userptr_bl...@coherency-sync.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-hsw6/igt@gem_userptr_bl...@coherency-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-kbl4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-kbl7/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
- shard-glk: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-glk5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-glk9/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#109385] /
[fdo#111870])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl8/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-apl8/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108682])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl6/igt@kms_co...@pipe-a-ctm-0-75.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-skl10/igt@kms_co...@pipe-a-ctm-0-75.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-apl: [PASS][19] -> [FAIL][20] ([fdo#103232])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-256x85-onscreen.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/shard-apl2/igt@kms_cursor_...@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#110741])
[21]:
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling) (rev9)
== Series Details ==
Series: series starting with [v3] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling) (rev9)
URL : https://patchwork.freedesktop.org/series/67529/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6998_full -> Patchwork_14652_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14652_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_crc@pipe-b-cursor-64x64-random:
- {shard-tglb}: [FAIL][1] ([fdo#103232] / [fdo#111703]) ->
[INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb1/igt@kms_cursor_...@pipe-b-cursor-64x64-random.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-tglb3/igt@kms_cursor_...@pipe-b-cursor-64x64-random.html
* igt@perf_pmu@cpu-hotplug:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4] +3 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb7/igt@perf_...@cpu-hotplug.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-tglb8/igt@perf_...@cpu-hotplug.html
Known issues
Here are the changes found in Patchwork_14652_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +6
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-apl4/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +12 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_userptr_blits@sync-unmap:
- shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw7/igt@gem_userptr_bl...@sync-unmap.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-hsw6/igt@gem_userptr_bl...@sync-unmap.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-snb1/igt@gem_userptr_bl...@sync-unmap-cycles.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl4/igt@kms_atomic_transit...@plane-all-modeset-transition-fencing.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-apl3/igt@kms_atomic_transit...@plane-all-modeset-transition-fencing.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-random:
- shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb4/igt@kms_cursor_...@pipe-b-cursor-64x64-random.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-iclb7/igt@kms_cursor_...@pipe-b-cursor-64x64-random.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#103184] / [fdo#103232])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl6/igt@kms_draw_...@draw-method-xrgb2101010-mmap-wc-untiled.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-skl3/igt@kms_draw_...@draw-method-xrgb2101010-mmap-wc-untiled.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-apl: [PASS][19] -> [FAIL][20] ([fdo#111609])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl4/igt@kms_f...@dpms-vs-vblank-race.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-apl6/igt@kms_f...@dpms-vs-vblank-race.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +2 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb8/igt@kms_frontbuffer_track...@fbc-suspend.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/shard-iclb4/igt@kms_frontbuffer_track...@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
-
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Implement a better i945gm vblank irq vs. C-states workaround
== Series Details ==
Series: drm/i915: Implement a better i945gm vblank irq vs. C-states workaround
URL : https://patchwork.freedesktop.org/series/67541/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6998_full -> Patchwork_14651_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14651_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14651_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14651_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@in-flight-suspend:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb7/igt@gem_...@in-flight-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-iclb4/igt@gem_...@in-flight-suspend.html
* igt@gem_mmap_gtt@basic-small-copy:
- shard-hsw: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw5/igt@gem_mmap_...@basic-small-copy.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-hsw6/igt@gem_mmap_...@basic-small-copy.html
* igt@i915_selftest@live_execlists:
- shard-iclb: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb8/igt@i915_selftest@live_execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-iclb1/igt@i915_selftest@live_execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_nop@basic-parallel:
- {shard-tglb}: [PASS][7] -> [INCOMPLETE][8] +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-tglb4/igt@gem_exec_...@basic-parallel.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-tglb1/igt@gem_exec_...@basic-parallel.html
Known issues
Here are the changes found in Patchwork_14651_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-iclb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111764])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb7/igt@gem_ctx_isolat...@rcs0-s3.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-iclb4/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_switch@vecs0-heavy-queue:
- shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl7/igt@gem_ctx_swi...@vecs0-heavy-queue.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-apl4/igt@gem_ctx_swi...@vecs0-heavy-queue.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#111325]) +9 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-bsd.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_exec_suspend@basic-s3:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl5/igt@gem_exec_susp...@basic-s3.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-skl5/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@hang:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#109385])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-apl2/igt@gem_mmap_...@hang.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-apl2/igt@gem_mmap_...@hang.html
* igt@gem_userptr_blits@coherency-sync:
- shard-hsw: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +1
similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-hsw2/igt@gem_userptr_bl...@coherency-sync.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-hsw4/igt@gem_userptr_bl...@coherency-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/shard-skl7/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/shard-skl2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
- shard-kbl: [PASS][23] ->
[Intel-gfx] linux-next: manual merge of the drm-misc tree with the admgpu tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
between commit:
2f232cf29e03 ("drm/amdgpu/dm/mst: Don't create MST topology managers for eDP
ports")
from the admgpu tree and commit:
ae85b0df124f ("drm_dp_cec: add connector info support.")
from the drm-misc tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 3af2b429ff1b,5ec14efd4d8c..
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@@ -414,11 -416,7 +414,11 @@@ void amdgpu_dm_initialize_dp_connector(
drm_dp_aux_register(>dm_dp_aux.aux);
drm_dp_cec_register_connector(>dm_dp_aux.aux,
- aconnector->base.name, dm->adev->dev);
+ >base);
+
+ if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
+ return;
+
aconnector->mst_mgr.cbs = _mst_cbs;
drm_dp_mst_topology_mgr_init(
>mst_mgr,
pgpVGc8HpYTCn.pgp
Description: OpenPGP digital signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
> On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote:
> > There's very little variation in non-privileged registers for Tigerlake,
> > so we can mostly inherit the set from gen11. There is no whitelist at
> > present, so we do not need to add any special registers.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> > Signed-off-by: Chris Wilson
> > ---
> > tests/i915/gem_ctx_isolation.c | 11 ++-
> > 1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > index df1d655ae..819daafc3 100644
> > --- a/tests/i915/gem_ctx_isolation.c
> > +++ b/tests/i915/gem_ctx_isolation.c
> > @@ -55,10 +55,11 @@ enum {
> > #define GEN9 (ALL << 9)
> > #define GEN10 (ALL << 10)
> > #define GEN11 (ALL << 11)
> > +#define GEN12 (ALL << 12)
> >
> > #define NOCTX 0
> >
> > -#define LAST_KNOWN_GEN 11
> > +#define LAST_KNOWN_GEN 12
> >
> > static const struct named_register {
> > const char *name;
> > @@ -116,9 +117,9 @@ static const struct named_register {
> > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> > - { "L3_Config", GEN8, RCS0, 0x7034 },
> > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
> > - { "TD_CTL2", GEN8, RCS0, 0xe404 },
> > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
> > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
> > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> > @@ -852,7 +853,7 @@ igt_main
> > gen = intel_gen(intel_get_drm_devid(fd));
> >
> > igt_warn_on_f(gen > LAST_KNOWN_GEN,
> > - "GEN not recognized! Test needs to be
> > updated to run.");
> > + "GEN not recognized! Test needs to be updated to
> > run.");
> > igt_skip_on(gen > LAST_KNOWN_GEN);
On 2019-10-02 14:38:31, Petri Latvala wrote:
> Thanks to this editorial change, we're able to see that this string is
> missing a newline character.
Your patch looks good (as does Petri's comment).
I had identified the same registers as in the patch, but had one additional
register. Should it be included?
+ { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked =
true },
I did some testing on a TGL with your patch. There are two pre-existing
issues, both of which I have encountered before. These are that the S3/S4 test
never wakes up, and errors reported by nonpriv for vcs'2 registers. See below.
Because of the S3/S4 issues, running gem_ctx_isolation for Gen12 will require
subsequent reboot. Should gem_ctx_isolation temporarily disable the S3/S4
tests for Gen12 until this problem is resolved?
I have been doing some work to address the vcs issue, which I will send
to the mailing list soon. The vcs issue is due to confusion between the
physical engine really being vcs'2, and the kernel presenting the engine to
usermode as vcs1. The test refers to the vcs'2 registers via the mmio_base
expected for vcs1 and therefore fails. Planned solution: "MMIO Remapping"
for ICL and later.
Results for gem_ctx_isolation
Never wakes from rcs0-S3 or rcs0-S4. (Probably also true for *-S3 and *-s4).
Starting subtest: rcs0-S3
[cmd] rtcwake: assuming RTC uses UTC ...
rtcwake: wakeup from "mem" using /dev/rtc0 at Thu Oct 3 17:45:41 2019
The following diagnostic is due to confusion between the physical engine
really being vcs'2, and the kernel presenting the engine to usermode as vcs1.
The test refers to the registers via the mmio_base expected for vcs1 and
therefore fails.
Starting subtest: vcs1-nonpriv
(gem_ctx_isolation:2152) WARNING: Register 0x1c4600 (VCS1_GPR[0]):
A= B=
(gem_ctx_isolation:2152) WARNING: Register 0x1c4604 (VCS1_GPR[1]):
A= B=
...and so on
Tested with:
-
Local kernel branch:
Based on git://anongit.freedesktop.org/drm-tip
Branch drm-tip
fd44976bff7a drm-tip: 2019y-10m-03d-15h-13m-54s UTC integration manifest
-
Local igt branch:
Based on https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
branch master:
74f55119 (public/master) i915/gem_eio: Relax timeout for forced resets
Plus your patch:
i915/gem_ctx_isolation: Bump support for Tigerlake
Plus a test patch to bypass S3 and S4 tests so other results could be seen:
tests/i915/gem_ctx_isolation.c - Suppress suspend/resume tests
-Dale
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for TGL HAX drm/i915/tgl: Interrupts are overrated (rev2)
== Series Details ==
Series: TGL HAX drm/i915/tgl: Interrupts are overrated (rev2)
URL : https://patchwork.freedesktop.org/series/67558/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7000 -> Patchwork_14660
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14660/index.html
Known issues
Here are the changes found in Patchwork_14660 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-process:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@gem_close_r...@basic-process.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14660/fi-icl-u3/igt@gem_close_r...@basic-process.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111735]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14660/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
- {fi-icl-dsi}: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14660/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-guc/igt@i915_selftest@live_execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14660/fi-icl-guc/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111045] / [fdo#111096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14660/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_self_import@basic-with_fd_dup:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14660/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7000 -> Patchwork_14660
CI-20190529: 20190529
CI_DRM_7000: a6af6b11a94cb1c70dbab04ef1e13d79e4ae @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5211: 1601e1571eb0f29a06b64494040b3ea7859a650f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14660: f7cb0f2c6b9e3c87c2c434992bfd94e10f18b228 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f7cb0f2c6b9e TGL HAX drm/i915/tgl: Interrupts are overrated
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14660/index.html
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/execlists: Skip redundant resubmission
== Series Details ==
Series: series starting with [1/5] drm/i915/execlists: Skip redundant
resubmission
URL : https://patchwork.freedesktop.org/series/67566/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7000 -> Patchwork_14659
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14659/index.html
Known issues
Here are the changes found in Patchwork_14659 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@bad-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@gem_ba...@bad-close.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14659/fi-icl-u3/igt@gem_ba...@bad-close.html
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#111381])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14659/fi-icl-u3/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14659/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111735]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14659/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14659/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-guc/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14659/fi-icl-guc/igt@i915_selftest@live_execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (52 -> 44)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7000 -> Patchwork_14659
CI-20190529: 20190529
CI_DRM_7000: a6af6b11a94cb1c70dbab04ef1e13d79e4ae @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5211: 1601e1571eb0f29a06b64494040b3ea7859a650f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14659: 45a8b0a2ec910228fa0ab99fdce0073fbfb8d9bc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
45a8b0a2ec91 drm/mm: Use clear_bit_unlock() for releasing the drm_mm_node()
84f0e5825415 drm/mm: Convert drm_mm_node booleans to bitops
554fc3753c90 drm/mm: Use helpers for drm_mm_node booleans
b34677b475f8 dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
8852b84cf9e7 drm/i915/execlists: Skip redundant resubmission
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14659/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/execlists: Skip redundant resubmission
== Series Details ==
Series: drm/i915/execlists: Skip redundant resubmission
URL : https://patchwork.freedesktop.org/series/67537/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6997_full -> Patchwork_14650_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14650_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14650_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14650_full:
### IGT changes ###
Possible regressions
* igt@gem_mmap_gtt@hang:
- shard-skl: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-skl1/igt@gem_mmap_...@hang.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-skl2/igt@gem_mmap_...@hang.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@fbc-suspend:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4] +2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-tglb6/igt@kms_frontbuffer_track...@fbc-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-tglb5/igt@kms_frontbuffer_track...@fbc-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-tglb4/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-a.html
Known issues
Here are the changes found in Patchwork_14650_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_async@concurrent-writes-blt:
- shard-apl: [PASS][6] -> [INCOMPLETE][7] ([fdo#103927]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-apl8/igt@gem_exec_as...@concurrent-writes-blt.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-apl2/igt@gem_exec_as...@concurrent-writes-blt.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +2 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-iclb8/igt@gem_exec_as...@concurrent-writes-bsd.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-iclb4/igt@gem_exec_as...@concurrent-writes-bsd.html
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +14 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-iclb1/igt@gem_exec_sched...@preempt-contexts-bsd2.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-iclb5/igt@gem_exec_sched...@preempt-contexts-bsd2.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-blt:
- shard-iclb: [PASS][12] -> [INCOMPLETE][13] ([fdo#107713])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-iclb7/igt@gem_exec_sched...@preempt-queue-contexts-chain-blt.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-iclb7/igt@gem_exec_sched...@preempt-queue-contexts-chain-blt.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-hsw: [PASS][14] -> [DMESG-WARN][15] ([fdo#111870])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-gup:
- shard-skl: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-skl2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-gup.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-skl6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-gup.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-snb4/igt@gem_userptr_bl...@sync-unmap-cycles.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([fdo#109385] /
[fdo#111870])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-apl8/igt@gem_userptr_bl...@sync-unmap-cycles.html
[21]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915/execlists: Skip redundant resubmission
== Series Details ==
Series: series starting with [1/5] drm/i915/execlists: Skip redundant
resubmission
URL : https://patchwork.freedesktop.org/series/67566/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8852b84cf9e7 drm/i915/execlists: Skip redundant resubmission
b34677b475f8 dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 0fc89b6802ba ("dma-fence: Simply
wrap dma_fence_signal_locked with dma_fence_signal")'
#14:
See also 0fc89b6802ba ("dma-fence: Simply wrap dma_fence_signal_locked
total: 1 errors, 0 warnings, 0 checks, 120 lines checked
554fc3753c90 drm/mm: Use helpers for drm_mm_node booleans
84f0e5825415 drm/mm: Convert drm_mm_node booleans to bitops
45a8b0a2ec91 drm/mm: Use clear_bit_unlock() for releasing the drm_mm_node()
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for LMEM basics (rev2)
== Series Details ==
Series: LMEM basics (rev2)
URL : https://patchwork.freedesktop.org/series/67350/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7000 -> Patchwork_14658
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/index.html
New tests
-
New tests have been introduced between CI_DRM_7000 and Patchwork_14658:
### New IGT tests (1) ###
* igt@i915_selftest@live_memory_region:
- Statuses : 44 pass(s)
- Exec time: [0.39, 2.61] s
Known issues
Here are the changes found in Patchwork_14658 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +4
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#109483])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111735]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-guc/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/fi-icl-guc/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][13] ([fdo#109483]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
- fi-kbl-7500u: [FAIL][15] ([fdo#111045] / [fdo#111096]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_self_import@basic-with_fd_dup:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18] +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14658/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7000 -> Patchwork_14658
CI-20190529: 20190529
CI_DRM_7000: a6af6b11a94cb1c70dbab04ef1e13d79e4ae @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5211: 1601e1571eb0f29a06b64494040b3ea7859a650f @
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for LMEM basics (rev2)
== Series Details == Series: LMEM basics (rev2) URL : https://patchwork.freedesktop.org/series/67350/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/stolen: make the object creation interface consistent Okay! Commit: drm/i915: introduce intel_memory_region Okay! Commit: drm/i915/region: support contiguous allocations +drivers/gpu/drm/i915/selftests/intel_memory_region.c:116:6: warning: symbol 'igt_object_release' was not declared. Should it be static? Commit: drm/i915/region: support volatile objects Okay! Commit: drm/i915: Add memory region information to device_info Okay! Commit: drm/i915: support creating LMEM objects Okay! Commit: drm/i915: setup io-mapping for LMEM Okay! Commit: drm/i915/lmem: support kernel mapping +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51:expected void * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51:got void [noderef] * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51: warning: incorrect type in return expression (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42: warning: incorrect type in argument 1 (different address spaces) Commit: drm/i915/selftests: add write-dword test for LMEM Okay! Commit: drm/i915/selftests: extend coverage to include LMEM huge-pages Okay! Commit: drm/i915: enumerate and init each supported region Okay! Commit: drm/i915: treat shmem as a region Okay! Commit: drm/i915: treat stolen as a region Okay! Commit: drm/i915: define HAS_MAPPABLE_APERTURE Okay! Commit: drm/i915: do not map aperture if it is not available. Okay! Commit: drm/i915: set num_fence_regs to 0 if there is no aperture Okay! Commit: drm/i915: error capture with no ggtt slot - +drivers/gpu/drm/i915/i915_gpu_error.c:1027:55:expected void *src +drivers/gpu/drm/i915/i915_gpu_error.c:1027:55:got void [noderef] *[assigned] s +drivers/gpu/drm/i915/i915_gpu_error.c:1027:55: warning: incorrect type in argument 2 (different address spaces) Commit: drm/i915: Don't try to place HWS in non-existing mappable region Okay! Commit: drm/i915: don't allocate the ring in stolen if we lack aperture Okay! Commit: drm/i915/selftests: fallback to using the gpu to trash stolen Okay! Commit: drm/i915/selftests: check for missing aperture Okay! Commit: HAX drm/i915: add the fake lmem region Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] TGL HAX drm/i915/tgl: Interrupts are overrated
Why sleep when you can busywait for an interrupt? Throw out the old irq
handlers, and use irq_poll instead.
References: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Kconfig.debug | 5 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 10 +++---
drivers/gpu/drm/i915/gt/intel_lrc.c | 35
drivers/gpu/drm/i915/i915_irq.c | 7 +++-
drivers/gpu/drm/i915/i915_pci.c | 1 -
7 files changed, 56 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 0d21402945ab..bf2b27b6ebf2 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -13,6 +13,7 @@ config DRM_I915
select DRM_PANEL
select DRM_MIPI_DSI
select RELAY
+ select IRQ_POLL
select IRQ_WORK
# i915 depends on ACPI_VIDEO when ACPI is enabled
# but for select to work, need to select ACPI_VIDEO's dependencies, ick
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 4a800faa275c..4d23a84ac2c4 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -44,6 +44,7 @@ config DRM_I915_DEBUG
select DRM_I915_SELFTEST
select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_DEBUG_MMIO
+ select TIGERLAKE_DEBUG_IRQ
default n
help
Choose this option to turn on extra driver debugging that may affect
@@ -220,3 +221,7 @@ config DRM_I915_DEBUG_RUNTIME_PM
driver loading, suspend and resume operations.
If in doubt, say "N"
+
+config TIGERLAKE_DEBUG_IRQ
+ bool "[TGL] Reduce IRQ functionality for stability"
+ default n
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 943f0663837e..53265add81ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -8,6 +8,7 @@
#define __INTEL_ENGINE_TYPES__
#include
+#include
#include
#include
#include
@@ -330,6 +331,8 @@ struct intel_engine_cs {
struct drm_i915_gem_object *default_state;
void *pinned_default_state;
+ struct irq_poll irq_poll;
+
struct {
struct intel_ring *ring;
struct intel_timeline *timeline;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 34a4fb624bf7..110cd8e1c05f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -209,12 +209,14 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
void gen11_gt_irq_postinstall(struct intel_gt *gt)
{
- const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
struct intel_uncore *uncore = gt->uncore;
- const u32 dmask = irqs << 16 | irqs;
- const u32 smask = irqs << 16;
+ u32 irqs, dmask, smask;
- BUILD_BUG_ON(irqs & 0x);
+ irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+ if (IS_ENABLED(CONFIG_TIGERLAKE_DEBUG_IRQ) && IS_TIGERLAKE(gt->i915))
+ irqs = 0; /* XXX lalalala */
+ smask = irqs << 16;
+ dmask = smask | irqs;
/* Enable RCS, BCS, VCS and VECS class interrupts. */
intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 431d3b8c3371..ffa99ba9eaec 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1944,6 +1944,8 @@ static void process_csb(struct intel_engine_cs *engine)
GEM_BUG_ON(execlists->active - execlists->inflight >
execlists_num_ports(execlists));
+
+ intel_engine_queue_breadcrumbs(engine);
}
} while (head != tail);
@@ -1987,6 +1989,27 @@ static void execlists_submission_tasklet(unsigned long
data)
}
}
+static int iop_handler(struct irq_poll *iop, int budget)
+{
+ struct intel_engine_cs *engine =
+ container_of(iop, typeof(*engine), irq_poll);
+ struct intel_engine_execlists *execlists = >execlists;
+ struct tasklet_struct *t = >tasklet;
+
+ if (execlists->csb_head == READ_ONCE(*execlists->csb_write))
+ return 0;
+
+ if (!tasklet_trylock(t))
+ return 0;
+
+ /* Must wait for any GPU reset in progress. */
+ if (__tasklet_is_enabled(t))
+ t->func(t->data);
+
+ tasklet_unlock(t);
+ return 0;
+}
+
static void execlists_submission_timer(struct timer_list *timer)
{
struct intel_engine_cs *engine =
@@ -3414,9 +3437,16 @@
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for LMEM basics (rev2)
== Series Details ==
Series: LMEM basics (rev2)
URL : https://patchwork.freedesktop.org/series/67350/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
617461d66e9a drm/i915/stolen: make the object creation interface consistent
-:89: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!obj"
#89: FILE: drivers/gpu/drm/i915/gem/i915_gem_stolen.c:602:
+ if (obj == NULL) {
total: 0 errors, 0 warnings, 1 checks, 145 lines checked
26e73b4fb28d drm/i915: introduce intel_memory_region
-:59: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#59:
new file mode 100644
-:577: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#577: FILE: drivers/gpu/drm/i915/intel_memory_region.h:26:
+ int (*init)(struct intel_memory_region *);
-:578: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#578: FILE: drivers/gpu/drm/i915/intel_memory_region.h:27:
+ void (*release)(struct intel_memory_region *);
-:580: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct
intel_memory_region *' should also have an identifier name
#580: FILE: drivers/gpu/drm/i915/intel_memory_region.h:29:
+ struct drm_i915_gem_object *
-:580: WARNING:FUNCTION_ARGUMENTS: function definition argument
'resource_size_t' should also have an identifier name
#580: FILE: drivers/gpu/drm/i915/intel_memory_region.h:29:
+ struct drm_i915_gem_object *
-:580: WARNING:FUNCTION_ARGUMENTS: function definition argument 'unsigned int'
should also have an identifier name
#580: FILE: drivers/gpu/drm/i915/intel_memory_region.h:29:
+ struct drm_i915_gem_object *
-:595: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#595: FILE: drivers/gpu/drm/i915/intel_memory_region.h:44:
+ struct mutex mm_lock;
-:616: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#616: FILE: drivers/gpu/drm/i915/intel_memory_region.h:65:
+__intel_memory_region_get_block_buddy(struct intel_memory_region *mem,
+resource_size_t size,
-:619: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#619: FILE: drivers/gpu/drm/i915/intel_memory_region.h:68:
+void __intel_memory_region_put_pages_buddy(struct intel_memory_region *mem,
+ struct list_head *blocks);
-:727: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'igt_mock_fill', this function's name, in a string
#727: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:78:
+ pr_err("igt_mock_fill failed, space still left in
region\n");
total: 0 errors, 7 warnings, 3 checks, 773 lines checked
00c236d8b5a6 drm/i915/region: support contiguous allocations
-:291: WARNING:LINE_SPACING: Missing a blank line after declarations
#291: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:131:
+ LIST_HEAD(holes);
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 372 lines checked
b68b1af935fc drm/i915/region: support volatile objects
7aa479268146 drm/i915: Add memory region information to device_info
e89ff1eeb7bc drm/i915: support creating LMEM objects
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#35:
new file mode 100644
-:117: WARNING:TYPO_SPELLING: 'UKNOWN' may be misspelled - perhaps 'UNKNOWN'?
#117: FILE: drivers/gpu/drm/i915/i915_drv.h:684:
+ struct intel_memory_region *regions[INTEL_MEMORY_UKNOWN];
-:139: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#139: FILE: drivers/gpu/drm/i915/intel_memory_region.c:10:
+#define REGION_MAP(type, inst) \
+ BIT((type) + INTEL_MEMORY_TYPE_SHIFT) | BIT(inst)
-:172: WARNING:TYPO_SPELLING: 'UKNOWN' may be misspelled - perhaps 'UNKNOWN'?
#172: FILE: drivers/gpu/drm/i915/intel_memory_region.h:34:
+ INTEL_MEMORY_UKNOWN, /* Should be last */
-:181: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'r' may be better as '(r)' to
avoid precedence issues
#181: FILE: drivers/gpu/drm/i915/intel_memory_region.h:43:
+#define MEMORY_TYPE_FROM_REGION(r) (ilog2(r >> INTEL_MEMORY_TYPE_SHIFT))
-:182: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'r' may be better as '(r)' to
avoid precedence issues
#182: FILE: drivers/gpu/drm/i915/intel_memory_region.h:44:
+#define MEMORY_INSTANCE_FROM_REGION(r) (ilog2(r & 0x))
total: 1 errors, 3 warnings, 2 checks, 269 lines checked
141deddcedec drm/i915: setup io-mapping for LMEM
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 34 lines checked
22b5c737a2e5 drm/i915/lmem: support kernel mapping
-:200: WARNING:LINE_SPACING: Missing a blank line after declarations
#200: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:283:
+
[Intel-gfx] ✓ Fi.CI.BAT: success for TGL HAX drm/i915/tgl: Interrupts are overrated
== Series Details ==
Series: TGL HAX drm/i915/tgl: Interrupts are overrated
URL : https://patchwork.freedesktop.org/series/67558/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7000 -> Patchwork_14657
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/index.html
Known issues
Here are the changes found in Patchwork_14657 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-write-gtt:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-blb-e6850/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/fi-blb-e6850/igt@i915_module_l...@reload.html
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724] /
[fdo#111214])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-guc/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/fi-icl-guc/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][13] ([fdo#109483]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_self_import@basic-with_fd_dup:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111045] / [fdo#111096]) ->
[FAIL][18] ([fdo#111407])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14657/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (52 -> 43)
--
Missing(9): fi-icl-u4 fi-tgl-u fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7000 -> Patchwork_14657
CI-20190529: 20190529
CI_DRM_7000: a6af6b11a94cb1c70dbab04ef1e13d79e4ae @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5211: 1601e1571eb0f29a06b64494040b3ea7859a650f @
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Add the Thunderbolt PLL divider values (rev3)
== Series Details ==
Series: drm/i915/tgl: Add the Thunderbolt PLL divider values (rev3)
URL : https://patchwork.freedesktop.org/series/67498/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6997_full -> Patchwork_14649_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14649_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-tilingchange.html
Known issues
Here are the changes found in Patchwork_14649_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][2] -> [FAIL][3] ([fdo#109661])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-snb4/igt@gem_...@reset-stress.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-snb5/igt@gem_...@reset-stress.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#109276]) +16 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-iclb2/igt@gem_exec_sched...@independent-bsd2.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-iclb6/igt@gem_exec_sched...@independent-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#111325]) +5 similar
issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-skl: [PASS][8] -> [DMESG-WARN][9] ([fdo#111870]) +1
similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-skl7/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-skl10/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([fdo#111870])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-kbl1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-kbl3/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][12] -> [DMESG-WARN][13] ([fdo#111870])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-snb4/igt@gem_userptr_bl...@sync-unmap-cycles.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html
- shard-hsw: [PASS][14] -> [DMESG-WARN][15] ([fdo#111870])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-hsw1/igt@gem_userptr_bl...@sync-unmap-cycles.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-hsw8/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@kms_busy@basic-modeset-c:
- shard-hsw: [PASS][16] -> [INCOMPLETE][17] ([fdo#103540])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-hsw4/igt@kms_b...@basic-modeset-c.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-hsw8/igt@kms_b...@basic-modeset-c.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [PASS][18] -> [FAIL][19] ([fdo#108682])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-skl6/igt@kms_co...@pipe-a-ctm-0-75.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-skl4/igt@kms_co...@pipe-a-ctm-0-75.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][20] -> [FAIL][21] ([fdo#105363])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/shard-skl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][22] -> [DMESG-WARN][23] ([fdo#108566]) +3
similar issues
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/shard-apl4/igt@kms_f...@flip-vs-suspend-interruptible.html
[23]:
Re: [Intel-gfx] [RFC v3 3/9] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
On Wed, 2019-10-02 at 15:29 -0700, Matt Roper wrote:
> On Mon, Sep 23, 2019 at 03:29:29AM -0700, Dhinakaran Pandiyan wrote:
> > Easier to read if all the alignment changes are in one place and contained
> > within a function.
> >
> > Cc: Ville Syrjälä
> > Cc: Matt Roper
> > Signed-off-by: Dhinakaran Pandiyan
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 31 ++--
> > 1 file changed, 16 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index a94d145dd048..c437f00c2072 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2551,7 +2551,22 @@ intel_fb_stride_alignment(const struct
> > drm_framebuffer *fb, int
> > color_plane)
> > else
> > return 64;
> > } else {
> > - return intel_tile_width_bytes(fb, color_plane);
> > + u32 tile_width = intel_tile_width_bytes(fb, color_plane);
> > +
> > + /*
> > +* Display WA #0531: skl,bxt,kbl,glk
> > +*
> > +* Render decompression and plane width > 3840
> > +* combined with horizontal panning requires the
> > +* plane stride to be a multiple of 4. We'll just
> > +* require the entire fb to accommodate that to avoid
> > +* potential runtime errors at plane configuration time.
> > +*/
> > + if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
> > + color_plane == 0 && fb->width > 3840)
> > + tile_width *= 4;
>
> I realize you're only moving this, but I find this workaround
> description confusing since the wording is somewhat ambiguous as to
> whether it's expecting the plane stride to be a multiple of 4 bytes or 4
> tiles. On casual read, I think most people would assume that we're
> talking about bytes here. Only once you realize that the PLANE_STRIDE
> register itself gets programmed in units of tile width does the wording
> here become clear. Maybe we could clarify the comment while moving it?
I remember wanting to rewrite that comment for the exact reason, but forgot to
do so. Thanks for the
review, I'll fix it.
>
> Also it might be slightly more clear to do a "return tile_width * 4"
> here instead of modifying tile_width since that's a bit more intuitive
> description of what we're trying to do.
>
> Either way,
>
> Reviewed-by: Matt Roper
>
>
> Matt
>
>
> > +
> > + return tile_width;
> > }
> > }
> >
> > @@ -15705,20 +15720,6 @@ static int intel_framebuffer_init(struct
> > intel_framebuffer *intel_fb,
> > }
> >
> > stride_alignment = intel_fb_stride_alignment(fb, i);
> > -
> > - /*
> > -* Display WA #0531: skl,bxt,kbl,glk
> > -*
> > -* Render decompression and plane width > 3840
> > -* combined with horizontal panning requires the
> > -* plane stride to be a multiple of 4. We'll just
> > -* require the entire fb to accommodate that to avoid
> > -* potential runtime errors at plane configuration time.
> > -*/
> > - if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
> > - is_ccs_modifier(fb->modifier))
> > - stride_alignment *= 4;
> > -
> > if (fb->pitches[i] & (stride_alignment - 1)) {
> > DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u
> > byte aligned\n",
> > i, fb->pitches[i], stride_alignment);
> > --
> > 2.17.1
> >
>
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Add getfb2 ioctl
== Series Details ==
Series: drm: Add getfb2 ioctl
URL : https://patchwork.freedesktop.org/series/67553/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7000 -> Patchwork_14656
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/index.html
Known issues
Here are the changes found in Patchwork_14656 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-a.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/fi-icl-u3/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-a.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111735]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
- {fi-icl-dsi}: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-guc/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/fi-icl-guc/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][11] ([fdo#109483]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
- fi-kbl-7500u: [FAIL][13] ([fdo#111045] / [fdo#111096]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_self_import@basic-with_fd_dup:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7000/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (52 -> 44)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-skl-6260u fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7000 -> Patchwork_14656
CI-20190529: 20190529
CI_DRM_7000: a6af6b11a94cb1c70dbab04ef1e13d79e4ae @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5211: 1601e1571eb0f29a06b64494040b3ea7859a650f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14656: 83b146de852e77e9c1090a4d9cc2c88177872b24 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
83b146de852e drm: Add getfb2 ioctl
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14656/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC v3 7/9] drm/i915: Skip rotated offset adjustment for unsupported modifiers
On Mon, 2019-09-23 at 03:29 -0700, Dhinakaran Pandiyan wrote:
> During framebuffer creation, we pre-compute offsets for 90/270 plane
> rotation. However, only Y and Yf modifiers support 90/270 rotation. So,
> skip the calculations for other modifiers.
>
> Cc: Matt Roper
> Cc: Ville Syrjälä
> Signed-off-by: Dhinakaran Pandiyan
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 7447001c1f85..6f0f38157697 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2784,7 +2784,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> tile_size);
> offset /= tile_size;
>
> - if (!is_surface_linear(fb->modifier, i)) {
> + /* Y or Yf modifiers required for 90/270 rotation */
> + if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> + fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
This is wrong, as CI results clearly show
igt@kms_addfb_basic@bo-too-small-due-to-tiling fails.
Please ignore this patch.
-DK
> unsigned int tile_width, tile_height;
> unsigned int pitch_tiles;
> struct drm_rect r;
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/mm: Convert drm_mm_node booleans to bitops
A straightforward conversion of assignment and checking of the boolean
state flags (allocated, scanned) into non-atomic bitops. The caller
remains responsible for all locking around the drm_mm and its nodes.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_mm.c | 18 +-
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c| 4 ++--
include/drm/drm_mm.h | 7 ---
4 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 99312bdc6273..a9cab5e53731 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -426,7 +426,7 @@ int drm_mm_reserve_node(struct drm_mm *mm, struct
drm_mm_node *node)
list_add(>node_list, >node_list);
drm_mm_interval_tree_add_node(hole, node);
- node->allocated = true;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
node->hole_size = 0;
rm_hole(hole);
@@ -545,7 +545,7 @@ int drm_mm_insert_node_in_range(struct drm_mm * const mm,
list_add(>node_list, >node_list);
drm_mm_interval_tree_add_node(hole, node);
- node->allocated = true;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
rm_hole(hole);
if (adj_start > hole_start)
@@ -563,7 +563,7 @@ EXPORT_SYMBOL(drm_mm_insert_node_in_range);
static inline bool drm_mm_node_scanned_block(const struct drm_mm_node *node)
{
- return node->scanned_block;
+ return test_bit(DRM_MM_NODE_SCANNED_BIT, >flags);
}
/**
@@ -589,7 +589,7 @@ void drm_mm_remove_node(struct drm_mm_node *node)
drm_mm_interval_tree_remove(node, >interval_tree);
list_del(>node_list);
- node->allocated = false;
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
if (drm_mm_hole_follows(prev_node))
rm_hole(prev_node);
@@ -627,8 +627,8 @@ void drm_mm_replace_node(struct drm_mm_node *old, struct
drm_mm_node *new)
>holes_addr);
}
- old->allocated = false;
- new->allocated = true;
+ __clear_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
}
EXPORT_SYMBOL(drm_mm_replace_node);
@@ -738,7 +738,7 @@ bool drm_mm_scan_add_block(struct drm_mm_scan *scan,
DRM_MM_BUG_ON(node->mm != mm);
DRM_MM_BUG_ON(!drm_mm_node_allocated(node));
DRM_MM_BUG_ON(drm_mm_node_scanned_block(node));
- node->scanned_block = true;
+ __set_bit(DRM_MM_NODE_SCANNED_BIT, >flags);
mm->scan_active++;
/* Remove this block from the node_list so that we enlarge the hole
@@ -824,7 +824,7 @@ bool drm_mm_scan_remove_block(struct drm_mm_scan *scan,
DRM_MM_BUG_ON(node->mm != scan->mm);
DRM_MM_BUG_ON(!drm_mm_node_scanned_block(node));
- node->scanned_block = false;
+ __clear_bit(DRM_MM_NODE_SCANNED_BIT, >flags);
DRM_MM_BUG_ON(!node->mm->scan_active);
node->mm->scan_active--;
@@ -922,7 +922,7 @@ void drm_mm_init(struct drm_mm *mm, u64 start, u64 size)
/* Clever trick to avoid a special case in the free hole tracking. */
INIT_LIST_HEAD(>head_node.node_list);
- mm->head_node.allocated = false;
+ mm->head_node.flags = 0;
mm->head_node.mm = mm;
mm->head_node.start = start + size;
mm->head_node.size = -size;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 20d8a6297985..c049199a1df5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -906,7 +906,7 @@ static void reloc_cache_init(struct reloc_cache *cache,
cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
cache->has_fence = cache->gen < 4;
cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
- cache->node.allocated = false;
+ cache->node.flags = 0;
cache->ce = NULL;
cache->rq = NULL;
cache->rq_size = 0;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fa8e028ac0b5..7046067f70c1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -351,7 +351,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
PIN_NOEVICT);
if (!IS_ERR(vma)) {
node.start = i915_ggtt_offset(vma);
- node.allocated = false;
+ node.flags = 0;
} else {
ret = insert_mappable_node(ggtt, , PAGE_SIZE);
if (ret)
@@ -561,7 +561,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
PIN_NOEVICT);
if (!IS_ERR(vma)) {
node.start = i915_ggtt_offset(vma);
-
[Intel-gfx] [PATCH 3/5] drm/mm: Use helpers for drm_mm_node booleans
In preparation for rearranging the booleans into a flags field, ensure
all the current users are using the inline helpers and not directly
accessing the members.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_mm.c | 19 ---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 12 ++--
drivers/gpu/drm/i915/i915_gem_evict.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 2 +-
drivers/gpu/drm/i915/i915_vma.h | 4 ++--
drivers/gpu/drm/selftests/test-drm_mm.c | 14 +++---
drivers/gpu/drm/vc4/vc4_crtc.c| 2 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 2 +-
drivers/gpu/drm/vc4/vc4_plane.c | 4 ++--
11 files changed, 36 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 4581c5387372..99312bdc6273 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -174,7 +174,7 @@ static void drm_mm_interval_tree_add_node(struct
drm_mm_node *hole_node,
node->__subtree_last = LAST(node);
- if (hole_node->allocated) {
+ if (drm_mm_node_allocated(hole_node)) {
rb = _node->rb;
while (rb) {
parent = rb_entry(rb, struct drm_mm_node, rb);
@@ -561,6 +561,11 @@ int drm_mm_insert_node_in_range(struct drm_mm * const mm,
}
EXPORT_SYMBOL(drm_mm_insert_node_in_range);
+static inline bool drm_mm_node_scanned_block(const struct drm_mm_node *node)
+{
+ return node->scanned_block;
+}
+
/**
* drm_mm_remove_node - Remove a memory node from the allocator.
* @node: drm_mm_node to remove
@@ -574,8 +579,8 @@ void drm_mm_remove_node(struct drm_mm_node *node)
struct drm_mm *mm = node->mm;
struct drm_mm_node *prev_node;
- DRM_MM_BUG_ON(!node->allocated);
- DRM_MM_BUG_ON(node->scanned_block);
+ DRM_MM_BUG_ON(!drm_mm_node_allocated(node));
+ DRM_MM_BUG_ON(drm_mm_node_scanned_block(node));
prev_node = list_prev_entry(node, node_list);
@@ -605,7 +610,7 @@ void drm_mm_replace_node(struct drm_mm_node *old, struct
drm_mm_node *new)
{
struct drm_mm *mm = old->mm;
- DRM_MM_BUG_ON(!old->allocated);
+ DRM_MM_BUG_ON(!drm_mm_node_allocated(old));
*new = *old;
@@ -731,8 +736,8 @@ bool drm_mm_scan_add_block(struct drm_mm_scan *scan,
u64 adj_start, adj_end;
DRM_MM_BUG_ON(node->mm != mm);
- DRM_MM_BUG_ON(!node->allocated);
- DRM_MM_BUG_ON(node->scanned_block);
+ DRM_MM_BUG_ON(!drm_mm_node_allocated(node));
+ DRM_MM_BUG_ON(drm_mm_node_scanned_block(node));
node->scanned_block = true;
mm->scan_active++;
@@ -818,7 +823,7 @@ bool drm_mm_scan_remove_block(struct drm_mm_scan *scan,
struct drm_mm_node *prev_node;
DRM_MM_BUG_ON(node->mm != scan->mm);
- DRM_MM_BUG_ON(!node->scanned_block);
+ DRM_MM_BUG_ON(!drm_mm_node_scanned_block(node));
node->scanned_block = false;
DRM_MM_BUG_ON(!node->mm->scan_active);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 27dbcb508055..20d8a6297985 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -968,7 +968,7 @@ static void reloc_cache_reset(struct reloc_cache *cache)
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
io_mapping_unmap_atomic((void __iomem *)vaddr);
- if (cache->node.allocated) {
+ if (drm_mm_node_allocated(>node)) {
ggtt->vm.clear_range(>vm,
cache->node.start,
cache->node.size);
@@ -1061,7 +1061,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
}
offset = cache->node.start;
- if (cache->node.allocated) {
+ if (drm_mm_node_allocated(>node)) {
ggtt->vm.insert_page(>vm,
i915_gem_object_get_dma_address(obj, page),
offset, I915_CACHE_NONE, 0);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index bb878119f06c..bb4889d2346d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -387,7 +387,7 @@ static u32 uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw,
struct i915_ggtt *ggtt)
{
struct drm_mm_node *node = >uc_fw;
- GEM_BUG_ON(!node->allocated);
+ GEM_BUG_ON(!drm_mm_node_allocated(node));
GEM_BUG_ON(upper_32_bits(node->start));
GEM_BUG_ON(upper_32_bits(node->start + node->size - 1));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index
[Intel-gfx] [PATCH 5/5] drm/mm: Use clear_bit_unlock() for releasing the drm_mm_node()
A few callers need to serialise the destruction of their drm_mm_node and
ensure it is removed from the drm_mm before freeing. However, to be
completely sure that any access from another thread is complete before
we free the struct, we require the RELEASE semantics of
clear_bit_unlock().
This allows the conditional locking such as
Thread AThread B
mutex_lock(mm_lock);if (drm_mm_node_allocated(node)) {
drm_mm_node_remove(node); mutex_lock(mm_lock);
mutex_unlock(mm_lock); drm_mm_node_remove(node);
mutex_unlock(mm_lock);
}
kfree(node);
to serialise correctly without any lingering accesses from A to the
freed node. Allocation / insertion of the node is assumed never to race
with removal or eviction scanning.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_mm.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index a9cab5e53731..2a6e34663146 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -424,9 +424,9 @@ int drm_mm_reserve_node(struct drm_mm *mm, struct
drm_mm_node *node)
node->mm = mm;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
list_add(>node_list, >node_list);
drm_mm_interval_tree_add_node(hole, node);
- __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
node->hole_size = 0;
rm_hole(hole);
@@ -543,9 +543,9 @@ int drm_mm_insert_node_in_range(struct drm_mm * const mm,
node->color = color;
node->hole_size = 0;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
list_add(>node_list, >node_list);
drm_mm_interval_tree_add_node(hole, node);
- __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
rm_hole(hole);
if (adj_start > hole_start)
@@ -589,11 +589,12 @@ void drm_mm_remove_node(struct drm_mm_node *node)
drm_mm_interval_tree_remove(node, >interval_tree);
list_del(>node_list);
- __clear_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
if (drm_mm_hole_follows(prev_node))
rm_hole(prev_node);
add_hole(prev_node);
+
+ clear_bit_unlock(DRM_MM_NODE_ALLOCATED_BIT, >flags);
}
EXPORT_SYMBOL(drm_mm_remove_node);
@@ -614,6 +615,7 @@ void drm_mm_replace_node(struct drm_mm_node *old, struct
drm_mm_node *new)
*new = *old;
+ __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
list_replace(>node_list, >node_list);
rb_replace_node_cached(>rb, >rb, >interval_tree);
@@ -627,8 +629,7 @@ void drm_mm_replace_node(struct drm_mm_node *old, struct
drm_mm_node *new)
>holes_addr);
}
- __clear_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
- __set_bit(DRM_MM_NODE_ALLOCATED_BIT, >flags);
+ clear_bit_unlock(DRM_MM_NODE_ALLOCATED_BIT, >flags);
}
EXPORT_SYMBOL(drm_mm_replace_node);
--
2.23.0
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[Intel-gfx] [PATCH 2/5] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)
Make dma_fence_enable_sw_signaling() behave like its
dma_fence_add_callback() and dma_fence_default_wait() counterparts and
perform the test to enable signaling under the fence->lock, along with
the action to do so. This ensure that should an implementation be trying
to flush the cb_list (by signaling) on retirement before freeing the
fence, it can do so in a race-free manner.
See also 0fc89b6802ba ("dma-fence: Simply wrap dma_fence_signal_locked
with dma_fence_signal").
v2: Refactor all 3 enable_signaling paths to use a common function.
Signed-off-by: Chris Wilson
---
drivers/dma-buf/dma-fence.c | 78 +
1 file changed, 35 insertions(+), 43 deletions(-)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 2c136aee3e79..b58528c1cc9d 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -273,6 +273,30 @@ void dma_fence_free(struct dma_fence *fence)
}
EXPORT_SYMBOL(dma_fence_free);
+static bool __dma_fence_enable_signaling(struct dma_fence *fence)
+{
+ bool was_set;
+
+ lockdep_assert_held(fence->lock);
+
+ was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
+ >flags);
+
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
+ return false;
+
+ if (!was_set && fence->ops->enable_signaling) {
+ if (!fence->ops->enable_signaling(fence)) {
+ dma_fence_signal_locked(fence);
+ return false;
+ }
+
+ trace_dma_fence_enable_signal(fence);
+ }
+
+ return true;
+}
+
/**
* dma_fence_enable_sw_signaling - enable signaling on fence
* @fence: the fence to enable
@@ -285,19 +309,12 @@ void dma_fence_enable_sw_signaling(struct dma_fence
*fence)
{
unsigned long flags;
- if (!test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
- >flags) &&
- !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags) &&
- fence->ops->enable_signaling) {
- trace_dma_fence_enable_signal(fence);
-
- spin_lock_irqsave(fence->lock, flags);
-
- if (!fence->ops->enable_signaling(fence))
- dma_fence_signal_locked(fence);
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
+ return;
- spin_unlock_irqrestore(fence->lock, flags);
- }
+ spin_lock_irqsave(fence->lock, flags);
+ __dma_fence_enable_signaling(fence);
+ spin_unlock_irqrestore(fence->lock, flags);
}
EXPORT_SYMBOL(dma_fence_enable_sw_signaling);
@@ -331,7 +348,6 @@ int dma_fence_add_callback(struct dma_fence *fence, struct
dma_fence_cb *cb,
{
unsigned long flags;
int ret = 0;
- bool was_set;
if (WARN_ON(!fence || !func))
return -EINVAL;
@@ -343,25 +359,14 @@ int dma_fence_add_callback(struct dma_fence *fence,
struct dma_fence_cb *cb,
spin_lock_irqsave(fence->lock, flags);
- was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
- >flags);
-
- if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
- ret = -ENOENT;
- else if (!was_set && fence->ops->enable_signaling) {
- trace_dma_fence_enable_signal(fence);
-
- if (!fence->ops->enable_signaling(fence)) {
- dma_fence_signal_locked(fence);
- ret = -ENOENT;
- }
- }
-
- if (!ret) {
+ if (__dma_fence_enable_signaling(fence)) {
cb->func = func;
list_add_tail(>node, >cb_list);
- } else
+ } else {
INIT_LIST_HEAD(>node);
+ ret = -ENOENT;
+ }
+
spin_unlock_irqrestore(fence->lock, flags);
return ret;
@@ -461,7 +466,6 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr,
signed long timeout)
struct default_wait_cb cb;
unsigned long flags;
signed long ret = timeout ? timeout : 1;
- bool was_set;
if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
return ret;
@@ -473,21 +477,9 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr,
signed long timeout)
goto out;
}
- was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
- >flags);
-
- if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
+ if (!__dma_fence_enable_signaling(fence))
goto out;
- if (!was_set && fence->ops->enable_signaling) {
- trace_dma_fence_enable_signal(fence);
-
- if (!fence->ops->enable_signaling(fence)) {
- dma_fence_signal_locked(fence);
- goto out;
- }
- }
-
if (!timeout) {
ret = 0;
goto out;
--
2.23.0
[Intel-gfx] [PATCH 1/5] drm/i915/execlists: Skip redundant resubmission
If we unwind the active requests, and on resubmission discover that we
intend to preempt the active context with itself, simply skip the ELSP
submission.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 431d3b8c3371..3cfea1758fd2 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1739,11 +1739,26 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
if (submit) {
*port = execlists_schedule_in(last, port - execlists->pending);
- memset(port + 1, 0, (last_port - port) * sizeof(*port));
execlists->switch_priority_hint =
switch_prio(engine, *execlists->pending);
+
+ /*
+* Skip if we ended up with exactly the same set of requests,
+* e.g. trying to timeslice a pair of ordered contexts
+*/
+ if (!memcmp(execlists->active, execlists->pending,
+ (port - execlists->pending + 1) * sizeof(*port))) {
+ do
+ execlists_schedule_out(fetch_and_zero(port));
+ while (port-- != execlists->pending);
+
+ goto skip_submit;
+ }
+
+ memset(port + 1, 0, (last_port - port) * sizeof(*port));
execlists_submit_ports(engine);
} else {
+skip_submit:
ring_set_paused(engine, 0);
}
}
--
2.23.0
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[Intel-gfx] [PATCH 04/11] drm: convert drm_mm_interval_tree to half closed intervals
The drm_mm interval tree really wants [a, b) intervals, not
fully closed as it is now. As such convert it to use the new
interval_tree_gen.h.
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Daniel Vetter
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Davidlohr Bueso
---
drivers/gpu/drm/drm_mm.c | 8
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
drivers/gpu/drm/selftests/test-drm_mm.c | 2 +-
include/drm/drm_mm.h | 6 +++---
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 4581c5387372..17feb00e7d80 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -43,7 +43,7 @@
*/
#include
-#include
+#include
#include
#include
#include
@@ -150,11 +150,11 @@ static void show_leaks(struct drm_mm *mm) { }
#endif
#define START(node) ((node)->start)
-#define LAST(node) ((node)->start + (node)->size - 1)
+#define END(node) ((node)->start + (node)->size)
INTERVAL_TREE_DEFINE(struct drm_mm_node, rb,
u64, __subtree_last,
-START, LAST, static inline, drm_mm_interval_tree)
+START, END, static inline, drm_mm_interval_tree)
struct drm_mm_node *
__drm_mm_interval_first(const struct drm_mm *mm, u64 start, u64 last)
@@ -172,7 +172,7 @@ static void drm_mm_interval_tree_add_node(struct
drm_mm_node *hole_node,
struct drm_mm_node *parent;
bool leftmost;
- node->__subtree_last = LAST(node);
+ node->__subtree_last = END(node);
if (hole_node->allocated) {
rb = _node->rb;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 3e6f4a65d356..af40d3bfa065 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1150,7 +1150,7 @@ static int check_scratch(struct i915_gem_context *ctx,
u64 offset)
{
struct drm_mm_node *node =
__drm_mm_interval_first(>vm->mm,
- offset, offset + sizeof(u32) - 1);
+ offset, offset + sizeof(u32));
if (!node || node->start > offset)
return 0;
diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c
b/drivers/gpu/drm/selftests/test-drm_mm.c
index 388f9844f4ba..f34f975c1570 100644
--- a/drivers/gpu/drm/selftests/test-drm_mm.c
+++ b/drivers/gpu/drm/selftests/test-drm_mm.c
@@ -853,7 +853,7 @@ static bool assert_contiguous_in_range(struct drm_mm *mm,
}
if (start > 0) {
- node = __drm_mm_interval_first(mm, 0, start - 1);
+ node = __drm_mm_interval_first(mm, 0, start);
if (node->allocated) {
pr_err("node before start: node=%llx+%llu,
start=%llx\n",
node->start, node->size, start);
diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h
index 2c3bbb43c7d1..0eda6180e1ef 100644
--- a/include/drm/drm_mm.h
+++ b/include/drm/drm_mm.h
@@ -485,19 +485,19 @@ __drm_mm_interval_first(const struct drm_mm *mm, u64
start, u64 last);
* @node__: drm_mm_node structure to assign to in each iteration step
* @mm__: drm_mm allocator to walk
* @start__: starting offset, the first node will overlap this
- * @end__: ending offset, the last node will start before this (but may
overlap)
+ * @end__: ending offset, the last node will start before this
*
* This iterator walks over all nodes in the range allocator that lie
* between @start and @end. It is implemented similarly to list_for_each(),
* but using the internal interval tree to accelerate the search for the
* starting node, and so not safe against removal of elements. It assumes
* that @end is within (or is the upper limit of) the drm_mm allocator.
- * If [@start, @end] are beyond the range of the drm_mm, the iterator may walk
+ * If [@start, @end) are beyond the range of the drm_mm, the iterator may walk
* over the special _unallocated_ _mm.head_node, and may even continue
* indefinitely.
*/
#define drm_mm_for_each_node_in_range(node__, mm__, start__, end__)\
- for (node__ = __drm_mm_interval_first((mm__), (start__), (end__)-1); \
+ for (node__ = __drm_mm_interval_first((mm__), (start__), (end__)); \
node__->start < (end__); \
node__ = list_next_entry(node__, node_list))
--
2.16.4
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Re: [Intel-gfx] [PATCH v2 20/22] drm/i915/selftests: fallback to using the gpu to trash stolen
Quoting Matthew Auld (2019-10-03 20:24:42)
> @@ -148,6 +190,21 @@ static int igt_gem_suspend(void *arg)
> if (err)
> goto out;
>
> + /*
> +* If we lack the mappable aperture we can't really access stolen from
> +* the cpu, but we can always trash it from the gpu, we just need to
> do
> +* so early, before we start suspending stuff. We shouldn't see any
> +* hangs doing this so early, since things like ring state won't be
> +* allocated in stolen if we can't access it from the cpu. Although if
> +* that's the case maybe there is not much point in bothering with
> this
> +* anyway...
> +*/
> + if (!HAS_MAPPABLE_APERTURE(i915)) {
> + err = trash_stolen_gpu(ctx);
> + if (err)
> + goto out;
> + }
The goal here is that later on we will need to migrate anything in lmem
to swap over suspend/hibernation and restore it on resume. The challenge
is then to corrupt state such that we can detect forgotten objects. (So
there will be usually a bug or two where we redesign the test to cover
more corner cases.) I'm not yet convinced trashing before suspend does
what I want it to do. I think we may need to do a minimal resume cycle
in the middle of the full suspend/resume test that bypasses the GEM
layer to do the trashing. :|
-Chris
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Re: [Intel-gfx] [PATCH v2 19/22] drm/i915: don't allocate the ring in stolen if we lack aperture
Quoting Matthew Auld (2019-10-03 20:24:41) > Since we have no way access it from the CPU. For such cases just > fallback to internal objects. > > Signed-off-by: Matthew Auld > --- > drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > index e220c09c6f32..c48f1d20af5f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > @@ -1273,7 +1273,9 @@ static struct i915_vma *create_ring_vma(struct > i915_ggtt *ggtt, int size) ^ There's a ggtt right there -- > struct drm_i915_gem_object *obj; > struct i915_vma *vma; > > - obj = i915_gem_object_create_stolen(i915, size); > + obj = ERR_PTR(-ENODEV); > + if (HAS_MAPPABLE_APERTURE(i915)) > + obj = i915_gem_object_create_stolen(i915, size); > if (IS_ERR(obj)) > obj = i915_gem_object_create_internal(i915, size); > if (IS_ERR(obj)) > -- > 2.20.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 14/22] drm/i915: define HAS_MAPPABLE_APERTURE
Quoting Matthew Auld (2019-10-03 20:24:36) > From: Daniele Ceraolo Spurio > > The following patches in the series will use it to avoid certain > operations when aperture is not available in HW. > > Signed-off-by: Daniele Ceraolo Spurio > Cc: Matthew Auld > --- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 2c5cb2feda27..7824a31ee448 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2119,6 +2119,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ > (INTEL_INFO(dev_priv)->display.overlay_needs_physical) > > +#define HAS_MAPPABLE_APERTURE(dev_priv) (dev_priv->ggtt.mappable_end > 0) I'm just not liking tying this to i915 and not ggtt. :| Also (dev_priv) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] drm-intel-fixes
On Thu, Oct 03, 2019 at 10:37:11PM +0300, Ville Syrjälä wrote: > On Thu, Oct 03, 2019 at 12:30:51PM -0700, Rodrigo Vivi wrote: > > Hi Dave and Daniel, > > > > This v2 contains a critical DP-MST fix that it would be really good to be > > propagated as soon as possible. > > > > Besides all the drm-intel-next-fixes that I mentioned on previous email. > > > > Here goes drm-intel-fixes-2019-10-03-1: > > - Fix DP-MST crtc_mask > > - Fix dsc dpp calculations > > - Fix g4x sprite scaling stride check with GTT remapping > > > > Short summary of fixes pull (less than what git shortlog provides): > > - explain anything non-fixes (e.g. cleanups) and why it's appropriate > > - highlight regressions > > - summarize pull requests contained > > This shouldn't be more than a few lines (or it indicates your fixes pull is > > a > > bit too big). > > > > Thanks, > > Rodrigo. > > > > The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: > > > > Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) > > > > are available in the Git repository at: > > > > git://anongit.freedesktop.org/drm/drm-intel > > tags/drm-intel-fixes-2019-10-03-1 > > > > for you to fetch changes up to 485f682be9fc8d41376936a3b01423edd07b9a75: > > > > Revert "drm/i915: Fix DP-MST crtc_mask" (2019-10-03 12:23:07 -0700) > > > > > > - Fix DP-MST crtc_mask > > - Fix dsc dpp calculations > > - Fix g4x sprite scaling stride check with GTT remapping > > > > Short summary of fixes pull (less than what git shortlog provides): > > - explain anything non-fixes (e.g. cleanups) and why it's appropriate > > - highlight regressions > > - summarize pull requests contained > > This shouldn't be more than a few lines (or it indicates your fixes pull is > > a > > bit too big). > > > > > > Maarten Lankhorst (1): > > drm/i915/dp: Fix dsc bpp calculations, v5. > > > > Ville Syrjälä (2): > > drm/i915: Fix g4x sprite scaling stride check with GTT remapping > > Revert "drm/i915: Fix DP-MST crtc_mask" > > Now I can sleep better :) Thanks for respinning. Thanks for the heads up. It seems that we will need to fix dim cherry-pick functions to consider Reverts as Fixes without depending on the Fixes: tag. But for now it seems the safest approach is to add Fixes tags even on reverts so neither of us loose sleep now or later ;) Thanks a lot Rodrigo. > > > > > drivers/gpu/drm/i915/display/intel_display.c | 12 +- > > drivers/gpu/drm/i915/display/intel_display.h | 2 +- > > drivers/gpu/drm/i915/display/intel_dp.c | 184 > > ++- > > drivers/gpu/drm/i915/display/intel_dp.h | 6 +- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +- > > drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- > > 6 files changed, 111 insertions(+), 102 deletions(-) > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 08/22] drm/i915/lmem: support kernel mapping
Quoting Matthew Auld (2019-10-03 20:24:30)
> +void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
> + unsigned long n,
> + unsigned long size)
> +{
> + resource_size_t offset;
> +
> + GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
GEM_BUG_ON(!i915_gem_object_is_contiguous(obj));
Just reads more clearly for me. Might just be me.
-Chris
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Re: [Intel-gfx] [PATCH v2 06/22] drm/i915: support creating LMEM objects
Quoting Matthew Auld (2019-10-03 20:24:28)
> +const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
> + .get_pages = i915_gem_object_get_pages_buddy,
> + .put_pages = i915_gem_object_put_pages_buddy,
> + .release = i915_gem_object_release_memory_region,
> +};
> +
> +bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
> +{
> + struct intel_memory_region *region = obj->mm.region;
> +
> + return region && region->type == INTEL_LMEM;
Hmm, a more classic approach would be
return obj->ops == _obj_ops;
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Re: [Intel-gfx] [PATCH v2 13/22] drm/i915: treat stolen as a region
> -Original Message-
> From: Intel-gfx On Behalf Of
> Matthew Auld
> Sent: Thursday, October 3, 2019 12:25 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 13/22] drm/i915: treat stolen as a region
>
> Convert stolen memory over to a region object. Still leaves open the
> question with what to do with pre-allocated objects...
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 66
> +++--- drivers/gpu/drm/i915/gem/i915_gem_stolen.h
> | 3 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c| 14 +
> drivers/gpu/drm/i915/i915_pci.c| 2 +-
> 4 files changed, 62 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 3dd295bb61f6..a91ef9fe98cd 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -10,6 +10,7 @@
> #include
> #include
>
> +#include "gem/i915_gem_region.h"
> #include "i915_drv.h"
> #include "i915_gem_stolen.h"
>
> @@ -150,7 +151,7 @@ static int i915_adjust_stolen(struct drm_i915_private
> *dev_priv,
> return 0;
> }
>
> -void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
> +static void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
> {
> if (!drm_mm_initialized(_priv->mm.stolen))
> return;
> @@ -355,7 +356,7 @@ static void icl_get_stolen_reserved(struct
> drm_i915_private *i915,
> }
> }
>
> -int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
> +static int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
> {
> resource_size_t reserved_base, stolen_top;
> resource_size_t reserved_total, reserved_size; @@ -539,6 +540,9
> @@ i915_gem_object_release_stolen(struct drm_i915_gem_object *obj)
>
> i915_gem_stolen_remove_node(dev_priv, stolen);
> kfree(stolen);
> +
> + if (obj->mm.region)
> + i915_gem_object_release_memory_region(obj);
We fully support memory region concept for both bios stolen system memory and
local stolen memory, we don't need such kind of checking.
This looks to upstream code before latest DG1 code. I am not sure if we want to
upstream this intermediate code.
--CQ
> }
>
> static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops
> = { @@ -548,8 +552,9 @@ static const struct drm_i915_gem_object_ops
> i915_gem_object_stolen_ops = { };
>
> static struct drm_i915_gem_object *
> -_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
> -struct drm_mm_node *stolen)
> +__i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
> + struct drm_mm_node *stolen,
> + struct intel_memory_region *mem)
> {
> struct drm_i915_gem_object *obj;
> unsigned int cache_level;
> @@ -566,6 +571,9 @@ _i915_gem_object_create_stolen(struct
> drm_i915_private *dev_priv,
> cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC :
> I915_CACHE_NONE;
> i915_gem_object_set_cache_coherency(obj, cache_level);
>
> + if (mem)
> + i915_gem_object_init_memory_region(obj, mem, 0);
> +
> if (i915_gem_object_pin_pages(obj))
> goto cleanup;
>
> @@ -576,10 +584,12 @@ _i915_gem_object_create_stolen(struct
> drm_i915_private *dev_priv,
> return NULL;
> }
>
> -struct drm_i915_gem_object *
> -i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
> - resource_size_t size)
> +static struct drm_i915_gem_object *
> +_i915_gem_object_create_stolen(struct intel_memory_region *mem,
> +resource_size_t size,
> +unsigned int flags)
> {
> + struct drm_i915_private *dev_priv = mem->i915;
> struct drm_i915_gem_object *obj;
> struct drm_mm_node *stolen;
> int ret;
> @@ -598,7 +608,7 @@ i915_gem_object_create_stolen(struct
> drm_i915_private *dev_priv,
> if (ret)
> goto err_free;
>
> - obj = _i915_gem_object_create_stolen(dev_priv, stolen);
> + obj = __i915_gem_object_create_stolen(dev_priv, stolen, mem);
> if (obj == NULL) {
> ret = -ENOMEM;
> goto err_remove;
> @@ -613,6 +623,44 @@ i915_gem_object_create_stolen(struct
> drm_i915_private *dev_priv,
> return ERR_PTR(ret);
> }
>
> +struct drm_i915_gem_object *
> +i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
> + resource_size_t size)
> +{
> +
> + return i915_gem_object_create_region(dev_priv-
> >mm.regions[INTEL_MEMORY_STOLEN],
> + size,
> I915_BO_ALLOC_CONTIGUOUS); }
> +
> +static int init_stolen(struct intel_memory_region *mem) {
> + /*
> + * Initialise stolen early so that we may reserve preallocated
> +
Re: [Intel-gfx] [PATCH v2 04/22] drm/i915/region: support volatile objects
Quoting Matthew Auld (2019-10-03 20:24:26)
> static const struct drm_i915_gem_object_ops fake_ops = {
> @@ -131,6 +128,8 @@ fake_dma_object(struct drm_i915_private *i915, u64 size)
> drm_gem_private_object_init(>drm, >base, size);
> i915_gem_object_init(obj, _ops);
>
> + obj->flags = I915_BO_ALLOC_VOLATILE;
obj->flags |= I915_BO_ALLOC_VOLATILE
even during early init, then we will not be caught out if we add an
earlier flag.
i915_gem_object_set_volatile()
i915_gem_object_is_volatile()
helpers?
-Chris
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Re: [Intel-gfx] [PATCH v2 19/22] drm/i915: don't allocate the ring in stolen if we lack aperture
> -Original Message- > From: Intel-gfx On Behalf Of > Matthew Auld > Sent: Thursday, October 3, 2019 12:25 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 19/22] drm/i915: don't allocate the ring in > stolen if we lack aperture > > Since we have no way access it from the CPU. For such cases just fallback to > internal objects. > > Signed-off-by: Matthew Auld > --- > drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > index e220c09c6f32..c48f1d20af5f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > @@ -1273,7 +1273,9 @@ static struct i915_vma *create_ring_vma(struct > i915_ggtt *ggtt, int size) > struct drm_i915_gem_object *obj; > struct i915_vma *vma; > > - obj = i915_gem_object_create_stolen(i915, size); > + obj = ERR_PTR(-ENODEV); > + if (HAS_MAPPABLE_APERTURE(i915)) > + obj = i915_gem_object_create_stolen(i915, size); Don't we already support local stolen memory region? In this case, if it has aperture, it is bios stolen system memory, if no aperture, it is local stolen memory, the same call to i915_gem_object_create_stolen() will work in both cases. --CQ > if (IS_ERR(obj)) > obj = i915_gem_object_create_internal(i915, size); > if (IS_ERR(obj)) > -- > 2.20.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] drm-intel-fixes
On Thu, Oct 03, 2019 at 12:30:51PM -0700, Rodrigo Vivi wrote: > Hi Dave and Daniel, > > This v2 contains a critical DP-MST fix that it would be really good to be > propagated as soon as possible. > > Besides all the drm-intel-next-fixes that I mentioned on previous email. > > Here goes drm-intel-fixes-2019-10-03-1: > - Fix DP-MST crtc_mask > - Fix dsc dpp calculations > - Fix g4x sprite scaling stride check with GTT remapping > > Short summary of fixes pull (less than what git shortlog provides): > - explain anything non-fixes (e.g. cleanups) and why it's appropriate > - highlight regressions > - summarize pull requests contained > This shouldn't be more than a few lines (or it indicates your fixes pull is a > bit too big). > > Thanks, > Rodrigo. > > The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: > > Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-intel > tags/drm-intel-fixes-2019-10-03-1 > > for you to fetch changes up to 485f682be9fc8d41376936a3b01423edd07b9a75: > > Revert "drm/i915: Fix DP-MST crtc_mask" (2019-10-03 12:23:07 -0700) > > > - Fix DP-MST crtc_mask > - Fix dsc dpp calculations > - Fix g4x sprite scaling stride check with GTT remapping > > Short summary of fixes pull (less than what git shortlog provides): > - explain anything non-fixes (e.g. cleanups) and why it's appropriate > - highlight regressions > - summarize pull requests contained > This shouldn't be more than a few lines (or it indicates your fixes pull is a > bit too big). > > > Maarten Lankhorst (1): > drm/i915/dp: Fix dsc bpp calculations, v5. > > Ville Syrjälä (2): > drm/i915: Fix g4x sprite scaling stride check with GTT remapping > Revert "drm/i915: Fix DP-MST crtc_mask" Now I can sleep better :) Thanks for respinning. > > drivers/gpu/drm/i915/display/intel_display.c | 12 +- > drivers/gpu/drm/i915/display/intel_display.h | 2 +- > drivers/gpu/drm/i915/display/intel_dp.c | 184 > ++- > drivers/gpu/drm/i915/display/intel_dp.h | 6 +- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +- > drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- > 6 files changed, 111 insertions(+), 102 deletions(-) > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, This v2 contains a critical DP-MST fix that it would be really good to be propagated as soon as possible. Besides all the drm-intel-next-fixes that I mentioned on previous email. Here goes drm-intel-fixes-2019-10-03-1: - Fix DP-MST crtc_mask - Fix dsc dpp calculations - Fix g4x sprite scaling stride check with GTT remapping Short summary of fixes pull (less than what git shortlog provides): - explain anything non-fixes (e.g. cleanups) and why it's appropriate - highlight regressions - summarize pull requests contained This shouldn't be more than a few lines (or it indicates your fixes pull is a bit too big). Thanks, Rodrigo. The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-10-03-1 for you to fetch changes up to 485f682be9fc8d41376936a3b01423edd07b9a75: Revert "drm/i915: Fix DP-MST crtc_mask" (2019-10-03 12:23:07 -0700) - Fix DP-MST crtc_mask - Fix dsc dpp calculations - Fix g4x sprite scaling stride check with GTT remapping Short summary of fixes pull (less than what git shortlog provides): - explain anything non-fixes (e.g. cleanups) and why it's appropriate - highlight regressions - summarize pull requests contained This shouldn't be more than a few lines (or it indicates your fixes pull is a bit too big). Maarten Lankhorst (1): drm/i915/dp: Fix dsc bpp calculations, v5. Ville Syrjälä (2): drm/i915: Fix g4x sprite scaling stride check with GTT remapping Revert "drm/i915: Fix DP-MST crtc_mask" drivers/gpu/drm/i915/display/intel_display.c | 12 +- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 184 ++- drivers/gpu/drm/i915/display/intel_dp.h | 6 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- 6 files changed, 111 insertions(+), 102 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 01/22] drm/i915/stolen: make the object creation interface consistent
Quoting Matthew Auld (2019-10-03 20:24:23)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index d6167dd592e9..dcf189f26624 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -299,7 +299,7 @@ static int vlv_rc6_init(struct intel_rc6 *rc6)
>
> pcbr_offset,
>
> I915_GTT_OFFSET_NONE,
>
> pctx_size);
> - if (!pctx)
> + if (IS_ERR(pctx))
> return -ENOMEM;
>
> goto out;
> @@ -316,7 +316,7 @@ static int vlv_rc6_init(struct intel_rc6 *rc6)
> * memory, or any other relevant ranges.
> */
> pctx = i915_gem_object_create_stolen(i915, pctx_size);
> - if (!pctx) {
> + if (IS_ERR(pctx)) {
> DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
> return -ENOMEM;
You might as well make use of the actual error now that you know it.
With that minor tweak,
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH v2 19/22] drm/i915: don't allocate the ring in stolen if we lack aperture
Since we have no way access it from the CPU. For such cases just fallback to internal objects. Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c index e220c09c6f32..c48f1d20af5f 100644 --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c @@ -1273,7 +1273,9 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) struct drm_i915_gem_object *obj; struct i915_vma *vma; - obj = i915_gem_object_create_stolen(i915, size); + obj = ERR_PTR(-ENODEV); + if (HAS_MAPPABLE_APERTURE(i915)) + obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); if (IS_ERR(obj)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 20/22] drm/i915/selftests: fallback to using the gpu to trash stolen
If we lack a mappable aperture, opt for nuking stolen memory with the
blitter engine.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/selftests/i915_gem.c | 95 +++
1 file changed, 80 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index 37593831b539..c4d7599af4f7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -6,6 +6,8 @@
#include
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_object_blt.h"
#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
@@ -34,14 +36,25 @@ static int switch_to_context(struct drm_i915_private *i915,
return 0;
}
-static void trash_stolen(struct drm_i915_private *i915)
+static void trash_stolen_cpu(struct drm_i915_private *i915)
{
struct i915_ggtt *ggtt = >ggtt;
const u64 slot = ggtt->error_capture.start;
const resource_size_t size = resource_size(>dsm);
+ intel_wakeref_t wakeref;
unsigned long page;
u32 prng = 0x12345678;
+ /*
+* As a final sting in the tail, invalidate stolen. Under a real S4,
+* stolen is lost and needs to be refilled on resume. However, under
+* CI we merely do S4-device testing (as full S4 is too unreliable
+* for automated testing across a cluster), so to simulate the effect
+* of stolen being trashed across S4, we trash it ourselves.
+*/
+
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+
for (page = 0; page < size; page += PAGE_SIZE) {
const dma_addr_t dma = i915->dsm.start + page;
u32 __iomem *s;
@@ -58,24 +71,53 @@ static void trash_stolen(struct drm_i915_private *i915)
}
ggtt->vm.clear_range(>vm, slot, PAGE_SIZE);
+
+ intel_runtime_pm_put(>runtime_pm, wakeref);
}
-static void simulate_hibernate(struct drm_i915_private *i915)
+static int trash_stolen_gpu(struct i915_gem_context *ctx)
{
- intel_wakeref_t wakeref;
+ struct drm_i915_private *i915 = ctx->vm->i915;
+ const resource_size_t size = resource_size(>dsm);
+ struct intel_memory_region *clone;
+ struct drm_i915_gem_object *obj;
+ struct intel_context *ce;
+ u32 prng = 0x12345678;
+ int err;
- wakeref = intel_runtime_pm_get(>runtime_pm);
+ if (!HAS_ENGINE(i915, BCS0))
+ return 0;
- /*
-* As a final sting in the tail, invalidate stolen. Under a real S4,
-* stolen is lost and needs to be refilled on resume. However, under
-* CI we merely do S4-device testing (as full S4 is too unreliable
-* for automated testing across a cluster), so to simulate the effect
-* of stolen being trashed across S4, we trash it ourselves.
-*/
- trash_stolen(i915);
+ if (!size)
+ return 0;
- intel_runtime_pm_put(>runtime_pm, wakeref);
+ clone = mock_region_create(i915, i915->dsm.start, size, PAGE_SIZE, 0);
+ if (IS_ERR(clone))
+ return PTR_ERR(clone);
+
+ obj = i915_gem_object_create_region(clone, size, 0);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto out_region;
+ }
+
+ ce = i915_gem_context_get_engine(ctx, BCS0);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out_put;
+ }
+
+ mutex_lock(>drm.struct_mutex);
+ err = i915_gem_object_fill_blt(obj, ce, prng);
+ mutex_unlock(>drm.struct_mutex);
+
+ intel_context_put(ce);
+out_put:
+ i915_gem_object_put(obj);
+out_region:
+ intel_memory_region_put(clone);
+
+ return err;
}
static int pm_prepare(struct drm_i915_private *i915)
@@ -148,6 +190,21 @@ static int igt_gem_suspend(void *arg)
if (err)
goto out;
+ /*
+* If we lack the mappable aperture we can't really access stolen from
+* the cpu, but we can always trash it from the gpu, we just need to do
+* so early, before we start suspending stuff. We shouldn't see any
+* hangs doing this so early, since things like ring state won't be
+* allocated in stolen if we can't access it from the cpu. Although if
+* that's the case maybe there is not much point in bothering with this
+* anyway...
+*/
+ if (!HAS_MAPPABLE_APERTURE(i915)) {
+ err = trash_stolen_gpu(ctx);
+ if (err)
+ goto out;
+ }
+
err = pm_prepare(i915);
if (err)
goto out;
@@ -155,7 +212,8 @@ static int igt_gem_suspend(void *arg)
pm_suspend(i915);
/* Here be dragons! Note that with S3RST any S3 may become S4! */
- simulate_hibernate(i915);
+ if (HAS_MAPPABLE_APERTURE(i915))
+ trash_stolen_cpu(i915);
[Intel-gfx] [PATCH v2 21/22] drm/i915/selftests: check for missing aperture
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 ++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
4 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 0ff7a89aadca..07faeada86eb 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -246,7 +246,10 @@ static bool always_valid(struct drm_i915_private *i915)
static bool needs_fence_registers(struct drm_i915_private *i915)
{
- return !intel_gt_is_wedged(>gt);
+ if (intel_gt_is_wedged(>gt))
+ return false;
+
+ return i915->ggtt.num_fences;
}
static bool needs_mi_store_dword(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index aefe557527f8..cb880d73ef73 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -301,6 +301,9 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
/* We want to check the page mapping and fencing of a large object
* mmapped through the GTT. The object we create is larger than can
* possibly be mmaped as a whole, and so we must use partial GGTT vma.
@@ -433,6 +436,9 @@ static int igt_smoke_tiling(void *arg)
IGT_TIMEOUT(end);
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
/*
* igt_partial_tiling() does an exhastive check of partial tiling
* chunking, but will undoubtably run out of time. Here, we do a
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 9c0c8441c22a..0378e59c803e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1189,8 +1189,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
struct i915_request *rq;
struct evict_vma arg;
struct hang h;
+ unsigned int pin_flags;
int err;
+ if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE)
+ return 0;
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1227,10 +1231,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
goto out_obj;
}
- err = i915_vma_pin(arg.vma, 0, 0,
- i915_vma_is_ggtt(arg.vma) ?
- PIN_GLOBAL | PIN_MAPPABLE :
- PIN_USER);
+ pin_flags = i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER;
+
+ if (flags & EXEC_OBJECT_NEEDS_FENCE)
+ pin_flags |= PIN_MAPPABLE;
+
+ err = i915_vma_pin(arg.vma, 0, 0, pin_flags);
if (err) {
i915_request_add(rq);
goto out_obj;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 3a84d1083289..6a9cb3bb5962 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1152,6 +1152,9 @@ static int igt_ggtt_page(void *arg)
unsigned int *order, n;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
mutex_lock(>drm.struct_mutex);
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 08/22] drm/i915/lmem: support kernel mapping
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 36 ++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 8 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 22 +++-
.../drm/i915/selftests/intel_memory_region.c | 118 ++
5 files changed, 185 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 26a23304df32..1a045858b3b2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -9,11 +9,47 @@
#include "i915_drv.h"
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .flags = I915_GEM_OBJECT_HAS_IOMEM,
+
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
};
+/* XXX: Time to vfunc your life up? */
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(>mm.region->iomap, offset, PAGE_SIZE);
+}
+
+void __iomem *i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_atomic_wc(>mm.region->iomap, offset);
+}
+
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(>mm.region->iomap, offset, size);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
struct intel_memory_region *region = obj->mm.region;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index ebc15fe24f58..31a6462bdbb6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -13,6 +13,14 @@ struct drm_i915_gem_object;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n, unsigned long size);
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n);
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 9a8579b67357..b75a14a61d24 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -30,10 +30,11 @@ struct i915_lut_handle {
struct drm_i915_gem_object_ops {
unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGEBIT(0)
-#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
-#define I915_GEM_OBJECT_IS_PROXY BIT(2)
-#define I915_GEM_OBJECT_NO_GGTTBIT(3)
-#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(4)
+#define I915_GEM_OBJECT_HAS_IOMEM BIT(1)
+#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(2)
+#define I915_GEM_OBJECT_IS_PROXY BIT(3)
+#define I915_GEM_OBJECT_NO_GGTTBIT(4)
+#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(5)
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index b0ec0959c13f..cf7f5a3cb210 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
+#include "i915_gem_lmem.h"
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages,
@@ -172,7 +173,9 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
void *ptr;
ptr = page_mask_bits(obj->mm.mapping);
- if
[Intel-gfx] [PATCH v2 10/22] drm/i915/selftests: extend coverage to include LMEM huge-pages
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 1772d4cbf3d2..85de3a6fd7a8 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -9,6 +9,7 @@
#include "i915_selftest.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
@@ -971,7 +972,7 @@ static int gpu_write(struct intel_context *ce,
vma->size >> PAGE_SHIFT, val);
}
-static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+static int __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
{
unsigned int needs_flush;
unsigned long n;
@@ -1003,6 +1004,51 @@ static int cpu_check(struct drm_i915_gem_object *obj,
u32 dword, u32 val)
return err;
}
+static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ if (i915_gem_object_has_struct_page(obj))
+ return __cpu_check_shmem(obj, dword, val);
+ else if (i915_gem_object_is_lmem(obj))
+ return __cpu_check_lmem(obj, dword, val);
+
+ return -ENODEV;
+}
+
static int __igt_write_huge(struct intel_context *ce,
struct drm_i915_gem_object *obj,
u64 size, u64 offset,
@@ -1387,6 +1433,78 @@ static int igt_ppgtt_gemfs_huge(void *arg)
return err;
}
+static int igt_ppgtt_lmem_huge(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ static const unsigned int sizes[] = {
+ SZ_64K,
+ SZ_512K,
+ SZ_1M,
+ SZ_2M,
+ };
+ int i;
+ int err;
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /*
+* Sanity check that the HW uses huge pages correctly through LMEM
+* -- ensure that our writes land in the right place.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+ unsigned int size = sizes[i];
+
+ obj = i915_gem_object_create_lmem(i915, size,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ pr_info("object too big for region!\n");
+ return 0;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM unable to allocate huge-page(s) with
size=%u\n",
+ size);
+ goto out_unpin;
+ }
+
+ err = igt_write_huge(ctx, obj);
+ if (err) {
+ pr_err("LMEM write-huge failed with size=%u\n", size);
+ goto out_unpin;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+ }
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1743,6 +1861,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
[Intel-gfx] [PATCH v2 22/22] HAX drm/i915: add the fake lmem region
Intended for upstream testing so that we can still exercise the LMEM
plumbing and !HAS_MAPPABLE_APERTURE paths. Smoke tested on Skull Canyon
device. This works by allocating an intel_memory_region for a reserved
portion of system memory, which we treat like LMEM. For the LMEMBAR we
steal the aperture and 1:1 it map to the stolen region.
To enable simply set i915_fake_lmem_start= on the kernel cmdline with the
start of reserved region(see memmap=). The size of the region we can
use is determined by the size of the mappable aperture, so the size of
reserved region should be >= mappable_end.
eg. memmap=2G$16G i915_fake_lmem_start=0x4
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
arch/x86/kernel/early-quirks.c | 26 +++
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 3 +
drivers/gpu/drm/i915/i915_drv.c| 8 ++
drivers/gpu/drm/i915/i915_gem_gtt.c| 3 +
drivers/gpu/drm/i915/intel_memory_region.h | 6 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 90 ++
drivers/gpu/drm/i915/intel_region_lmem.h | 5 ++
include/drm/i915_drm.h | 3 +
8 files changed, 144 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6f6b1d04dadf..9b04655e3926 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -603,6 +603,32 @@ static void __init intel_graphics_quirks(int num, int
slot, int func)
}
}
+struct resource intel_graphics_fake_lmem_res __ro_after_init =
DEFINE_RES_MEM(0, 0);
+EXPORT_SYMBOL(intel_graphics_fake_lmem_res);
+
+static int __init early_i915_fake_lmem_init(char *s)
+{
+ u64 start;
+ int ret;
+
+ if (*s == '=')
+ s++;
+
+ ret = kstrtoull(s, 16, );
+ if (ret)
+ return ret;
+
+ intel_graphics_fake_lmem_res.start = start;
+ intel_graphics_fake_lmem_res.end = SZ_2G; /* Placeholder; depends on
aperture size */
+
+ printk(KERN_INFO "Intel graphics fake LMEM starts at %pa\n",
+ _graphics_fake_lmem_res.start);
+
+ return 0;
+}
+
+early_param("i915_fake_lmem_start", early_i915_fake_lmem_init);
+
static void __init force_disable_hpet(int num, int slot, int func)
{
#ifdef CONFIG_HPET_TIMER
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 1a045858b3b2..a8c3d52eb44c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -23,6 +23,7 @@ void __iomem *i915_gem_object_lmem_io_map_page(struct
drm_i915_gem_object *obj,
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
return io_mapping_map_wc(>mm.region->iomap, offset, PAGE_SIZE);
}
@@ -33,6 +34,7 @@ void __iomem *i915_gem_object_lmem_io_map_page_atomic(struct
drm_i915_gem_object
resource_size_t offset;
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
return io_mapping_map_atomic_wc(>mm.region->iomap, offset);
}
@@ -46,6 +48,7 @@ void __iomem *i915_gem_object_lmem_io_map(struct
drm_i915_gem_object *obj,
GEM_BUG_ON(!(obj->flags & I915_BO_ALLOC_CONTIGUOUS));
offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
return io_mapping_map_wc(>mm.region->iomap, offset, size);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3306c6bb515a..e53e70b4fd39 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1526,6 +1526,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
+ /* Check if we support fake LMEM -- enable for live selftests */
+ if (INTEL_GEN(dev_priv) >= 9 && i915_selftest.live &&
+ intel_graphics_fake_lmem_res.start) {
+ mkwrite_device_info(dev_priv)->memory_regions =
+ REGION_SMEM | REGION_LMEM | REGION_STOLEN;
+ GEM_BUG_ON(!HAS_LMEM(dev_priv));
+ }
+
ret = pci_enable_device(pdev);
if (ret)
goto out_fini;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 096f50f1dda5..e7832dc1e7d3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2778,6 +2778,9 @@ int i915_gem_init_memory_regions(struct drm_i915_private
*i915)
case INTEL_STOLEN:
mem = i915_gem_stolen_setup(i915);
break;
+ case INTEL_LMEM:
+ mem = intel_setup_fake_lmem(i915);
+ break;
}
if
[Intel-gfx] [PATCH v2 15/22] drm/i915: do not map aperture if it is not available.
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ++---
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 209686c23d21..64bf47eaa2a1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2827,7 +2827,9 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
mutex_unlock(>drm.struct_mutex);
arch_phys_wc_del(ggtt->mtrr);
- io_mapping_fini(>iomap);
+
+ if (ggtt->iomap.size)
+ io_mapping_fini(>iomap);
}
/**
@@ -3038,10 +3040,13 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
int err;
/* TODO: We're not aware of mappable constraints on gen8 yet */
- ggtt->gmadr =
- (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
-pci_resource_len(pdev, 2));
- ggtt->mappable_end = resource_size(>gmadr);
+ /* FIXME: We probably need to add do device_info or runtime_info */
+ if (!HAS_LMEM(dev_priv)) {
+ ggtt->gmadr =
+ (struct resource)
DEFINE_RES_MEM(pci_resource_start(pdev, 2),
+pci_resource_len(pdev,
2));
+ ggtt->mappable_end = resource_size(>gmadr);
+ }
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
if (!err)
@@ -3267,15 +3272,18 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
- if (!io_mapping_init_wc(>iomap,
- ggtt->gmadr.start,
- ggtt->mappable_end)) {
- ggtt->vm.cleanup(>vm);
- ret = -EIO;
- goto out;
- }
+ if (ggtt->mappable_end) {
+ if (!io_mapping_init_wc(>iomap,
+ ggtt->gmadr.start,
+ ggtt->mappable_end)) {
+ ggtt->vm.cleanup(>vm);
+ ret = -EIO;
+ goto out;
+ }
- ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
+ ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
+ ggtt->mappable_end);
+ }
i915_ggtt_init_fences(ggtt);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 07/22] drm/i915: setup io-mapping for LMEM
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index 7a3f96e1f766..051069664074 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -36,8 +36,32 @@ lmem_create_object(struct intel_memory_region *mem,
return obj;
}
+static void
+region_lmem_release(struct intel_memory_region *mem)
+{
+ io_mapping_fini(>iomap);
+ intel_memory_region_release_buddy(mem);
+}
+
+static int
+region_lmem_init(struct intel_memory_region *mem)
+{
+ int ret;
+
+ if (!io_mapping_init_wc(>iomap,
+ mem->io_start,
+ resource_size(>region)))
+ return -EIO;
+
+ ret = intel_memory_region_init_buddy(mem);
+ if (ret)
+ io_mapping_fini(>iomap);
+
+ return ret;
+}
+
const struct intel_memory_region_ops intel_region_lmem_ops = {
- .init = intel_memory_region_init_buddy,
- .release = intel_memory_region_release_buddy,
+ .init = region_lmem_init,
+ .release = region_lmem_release,
.create_object = lmem_create_object,
};
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 16/22] drm/i915: set num_fence_regs to 0 if there is no aperture
From: Daniele Ceraolo Spurio We can't fence anything without aperture. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 615a9f4ef30c..0f1507285128 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -828,8 +828,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) detect_bit_6_swizzle(i915); - if (INTEL_GEN(i915) >= 7 && - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) + if (!ggtt->mappable_end) + num_fences = 0; + else if (INTEL_GEN(i915) >= 7 && +!(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) num_fences = 32; else if (INTEL_GEN(i915) >= 4 || IS_I945G(i915) || IS_I945GM(i915) || -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 18/22] drm/i915: Don't try to place HWS in non-existing mappable region
From: Michal Wajdeczko HWS placement restrictions can't just rely on HAS_LLC flag. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 80fd072ac719..c64f91bbdf3b 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -513,7 +513,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && HAS_MAPPABLE_APERTURE(engine->i915)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena. -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 12/22] drm/i915: treat shmem as a region
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 14 +++-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 68 ++-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 9 ---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_pci.c | 29 +---
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
8 files changed, 95 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 768356908160..8043ff63d73f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -16,6 +16,7 @@
#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_object.h"
+#include "i915_gem_region.h"
#include "i915_scatterlist.h"
static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
@@ -191,8 +192,10 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj, int align)
/* Perma-pin (until release) the physical set of pages */
__i915_gem_object_pin_pages(obj);
- if (!IS_ERR_OR_NULL(pages))
+ if (!IS_ERR_OR_NULL(pages)) {
i915_gem_shmem_ops.put_pages(obj, pages);
+ i915_gem_object_release_memory_region(obj);
+ }
mutex_unlock(>mm.lock);
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 663254b3da21..0c03c2c40dbc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -6,6 +6,7 @@
#include "intel_memory_region.h"
#include "i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_trace.h"
void
i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
@@ -146,11 +147,22 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
GEM_BUG_ON(!size);
GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
+ /*
+* There is a prevalence of the assumption that we fit the object's
+* page count inside a 32bit _signed_ variable. Let's document this and
+* catch if we ever need to fix it. In the meantime, if you do spot
+* such a local variable, please consider fixing!
+*/
+
if (size >> PAGE_SHIFT > INT_MAX)
return ERR_PTR(-E2BIG);
if (overflows_type(size, obj->base.size))
return ERR_PTR(-E2BIG);
- return mem->ops->create_object(mem, size, flags);
+ obj = mem->ops->create_object(mem, size, flags);
+ if (!IS_ERR(obj))
+ trace_i915_gem_object_create(obj);
+
+ return obj;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 4c4954e8ce0a..554504349eb0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -7,7 +7,9 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_gemfs.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
@@ -26,6 +28,7 @@ static void check_release_pagevec(struct pagevec *pvec)
static int shmem_get_pages(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_memory_region *mem = obj->mm.region;
const unsigned long page_count = obj->base.size / PAGE_SIZE;
unsigned long i;
struct address_space *mapping;
@@ -52,7 +55,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
* If there's no chance of allocating enough pages for the whole
* object, bail early.
*/
- if (page_count > totalram_pages())
+ if (obj->base.size > resource_size(>region))
return -ENOMEM;
st = kmalloc(sizeof(*st), GFP_KERNEL);
@@ -417,6 +420,8 @@ shmem_pwrite(struct drm_i915_gem_object *obj,
static void shmem_release(struct drm_i915_gem_object *obj)
{
+ i915_gem_object_release_memory_region(obj);
+
fput(obj->base.filp);
}
@@ -434,7 +439,7 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.release = shmem_release,
};
-static int create_shmem(struct drm_i915_private *i915,
+static int __create_shmem(struct drm_i915_private *i915,
struct drm_gem_object *obj,
size_t size)
{
@@ -455,31 +460,23 @@ static int create_shmem(struct drm_i915_private *i915,
return 0;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_shmem(struct drm_i915_private *i915, u64 size)
+static struct drm_i915_gem_object *
+create_shmem(struct intel_memory_region *mem,
+resource_size_t size,
+unsigned flags)
{
+ struct drm_i915_private *i915 =
[Intel-gfx] [PATCH v2 09/22] drm/i915/selftests: add write-dword test for LMEM
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
---
.../drm/i915/selftests/intel_memory_region.c | 171 ++
1 file changed, 171 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 1ad755e75e57..afb248f175df 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -7,13 +7,16 @@
#include "../i915_selftest.h"
+
#include "mock_drm.h"
#include "mock_gem_device.h"
#include "mock_region.h"
+#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_object_blt.h"
+#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
#include "selftests/igt_flush_test.h"
@@ -255,6 +258,125 @@ static int igt_mock_contiguous(void *arg)
return err;
}
+static int igt_gpu_write_dw(struct intel_context *ce,
+ struct i915_vma *vma,
+ u32 dword,
+ u32 value)
+{
+ return igt_gpu_fill_dw(ce, vma, dword * sizeof(u32),
+ vma->size >> PAGE_SHIFT, value);
+}
+
+static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int igt_gpu_write(struct i915_gem_context *ctx,
+struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct i915_address_space *vm = ctx->vm ?: >ggtt.vm;
+ struct i915_gem_engines *engines;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ I915_RND_STATE(prng);
+ IGT_TIMEOUT(end_time);
+ unsigned int count;
+ struct i915_vma *vma;
+ int *order;
+ int i, n;
+ int err = 0;
+
+ GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+
+ n = 0;
+ count = 0;
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ count++;
+ if (!intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ n++;
+ }
+ i915_gem_context_unlock_engines(ctx);
+ if (!n)
+ return 0;
+
+ order = i915_random_order(count * count, );
+ if (!order)
+ return -ENOMEM;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_free;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_free;
+
+ i = 0;
+ engines = i915_gem_context_lock_engines(ctx);
+ do {
+ u32 rng = prandom_u32_state();
+ u32 dword = offset_in_page(rng) / 4;
+
+ ce = engines->engines[order[i] % engines->num_engines];
+ i = (i + 1) % (count * count);
+ if (!ce || !intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ err = igt_gpu_write_dw(ce, vma, dword, rng);
+ if (err)
+ break;
+
+ err = igt_cpu_check(obj, dword, rng);
+ if (err)
+ break;
+ } while (!__igt_timeout(end_time, NULL));
+ i915_gem_context_unlock_engines(ctx);
+
+out_free:
+ kfree(order);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_lmem_create(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -276,6 +398,54 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_write_gpu(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ struct i915_gem_context *ctx;
+ struct drm_file *file;
+ I915_RND_STATE(prng);
+ u32 sz;
+ int err;
+
+
[Intel-gfx] [PATCH v2 17/22] drm/i915: error capture with no ggtt slot
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
drivers/gpu/drm/i915/i915_gpu_error.c | 65 ++-
2 files changed, 64 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 64bf47eaa2a1..096f50f1dda5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2661,7 +2661,8 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
{
ggtt_release_guc_top(ggtt);
- drm_mm_remove_node(>error_capture);
+ if (drm_mm_node_allocated(>error_capture))
+ drm_mm_remove_node(>error_capture);
}
static int init_ggtt(struct i915_ggtt *ggtt)
@@ -2692,13 +2693,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
if (ret)
return ret;
- /* Reserve a mappable slot for our lockless error capture */
- ret = drm_mm_insert_node_in_range(>vm.mm, >error_capture,
- PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
- 0, ggtt->mappable_end,
- DRM_MM_INSERT_LOW);
- if (ret)
- return ret;
+ if (ggtt->mappable_end) {
+ /* Reserve a mappable slot for our lockless error capture */
+ ret = drm_mm_insert_node_in_range(>vm.mm,
>error_capture,
+ PAGE_SIZE, 0,
I915_COLOR_UNEVICTABLE,
+ 0, ggtt->mappable_end,
+ DRM_MM_INSERT_LOW);
+ if (ret)
+ return ret;
+ }
/*
* The upper portion of the GuC address space has a sizeable hole
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 6384a06aa5bf..c6c96f0c6b28 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -40,6 +40,7 @@
#include "display/intel_overlay.h"
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "i915_gpu_error.h"
@@ -235,6 +236,7 @@ struct compress {
struct pagevec pool;
struct z_stream_s zstream;
void *tmp;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -292,7 +294,7 @@ static int compress_page(struct compress *c,
struct z_stream_s *zstream = >zstream;
zstream->next_in = src;
- if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
+ if (c->wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
zstream->next_in = c->tmp;
zstream->avail_in = PAGE_SIZE;
@@ -367,6 +369,7 @@ static void err_compression_marker(struct
drm_i915_error_state_buf *m)
struct compress {
struct pagevec pool;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -389,7 +392,7 @@ static int compress_page(struct compress *c,
if (!ptr)
return -ENOMEM;
- if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
+ if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
memcpy(ptr, src, PAGE_SIZE);
dst->pages[dst->page_count++] = ptr;
@@ -970,7 +973,6 @@ i915_error_object_create(struct drm_i915_private *i915,
struct drm_i915_error_object *dst;
unsigned long num_pages;
struct sgt_iter iter;
- dma_addr_t dma;
int ret;
might_sleep();
@@ -996,17 +998,54 @@ i915_error_object_create(struct drm_i915_private *i915,
dst->page_count = 0;
dst->unused = 0;
+ compress->wc = i915_gem_object_is_lmem(vma->obj) ||
+ drm_mm_node_allocated(>error_capture);
+
ret = -EINVAL;
- for_each_sgt_daddr(dma, iter, vma->pages) {
+ if (drm_mm_node_allocated(>error_capture)) {
void __iomem *s;
+ dma_addr_t dma;
- ggtt->vm.insert_page(>vm, dma, slot, I915_CACHE_NONE, 0);
+ for_each_sgt_daddr(dma, iter, vma->pages) {
+ ggtt->vm.insert_page(>vm, dma, slot,
+I915_CACHE_NONE, 0);
- s = io_mapping_map_wc(>iomap, slot, PAGE_SIZE);
- ret = compress_page(compress, (void __force *)s, dst);
- io_mapping_unmap(s);
- if (ret)
- break;
+ s = io_mapping_map_wc(>iomap, slot, PAGE_SIZE);
+ ret = compress_page(compress, (void __force *)s, dst);
+ io_mapping_unmap(s);
+
[Intel-gfx] [PATCH v2 11/22] drm/i915: enumerate and init each supported region
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +--
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 ++
3 files changed, 72 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2673f41d93b..26966b34c731 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2387,6 +2387,9 @@ int __must_check i915_gem_evict_for_node(struct
i915_address_space *vm,
unsigned int flags);
int i915_gem_evict_vm(struct i915_address_space *vm);
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915);
+int i915_gem_init_memory_regions(struct drm_i915_private *i915);
+
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e62e9d1a1307..f1e42c2e18d7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2744,6 +2744,66 @@ int i915_init_ggtt(struct drm_i915_private *i915)
return 0;
}
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915)
+{
+ int i;
+
+ i915_gem_cleanup_stolen(i915);
+
+ for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
+ struct intel_memory_region *region = i915->mm.regions[i];
+
+ if (region)
+ intel_memory_region_put(region);
+ }
+}
+
+int i915_gem_init_memory_regions(struct drm_i915_private *i915)
+{
+ int err, i;
+
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ /* XXX: stolen will become a region at some point */
+ err = i915_gem_init_stolen(i915);
+ if (err)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
+ struct intel_memory_region *mem = NULL;
+ u32 type;
+
+ if (!HAS_REGION(i915, BIT(i)))
+ continue;
+
+ type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
+ switch (type) {
+ default:
+ break;
+ }
+
+ if (IS_ERR(mem)) {
+ err = PTR_ERR(mem);
+ DRM_ERROR("Failed to setup region(%d) type=%d\n", err,
type);
+ goto out_cleanup;
+ }
+
+ mem->id = intel_region_map[i];
+ mem->type = type;
+ mem->instance =
MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
+
+ i915->mm.regions[i] = mem;
+ }
+
+ return 0;
+
+out_cleanup:
+ i915_gem_cleanup_memory_regions(i915);
+ return err;
+}
+
static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
{
struct drm_i915_private *i915 = ggtt->vm.i915;
@@ -2785,6 +2845,8 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
{
struct pagevec *pvec;
+ i915_gem_cleanup_memory_regions(i915);
+
fini_aliasing_ppgtt(>ggtt);
ggtt_cleanup_hw(>ggtt);
@@ -2794,8 +2856,6 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
set_pages_array_wb(pvec->pages, pvec->nr);
__pagevec_release(pvec);
}
-
- i915_gem_cleanup_stolen(i915);
}
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3251,11 +3311,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- /*
-* Initialise stolen early so that we may reserve preallocated
-* objects for the BIOS to KMS transition.
-*/
- ret = i915_gem_init_stolen(dev_priv);
+ ret = i915_gem_init_memory_regions(dev_priv);
if (ret)
goto out_gtt_cleanup;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 9809b17083de..4ceaaa529da7 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -82,6 +82,8 @@ static void mock_device_release(struct drm_device *dev)
i915_gemfs_fini(i915);
+ i915_gem_cleanup_memory_regions(i915);
+
drm_mode_config_cleanup(>drm);
drm_dev_fini(>drm);
@@ -218,6 +220,10 @@ struct drm_i915_private *mock_gem_device(void)
WARN_ON(i915_gemfs_init(i915));
+ err = i915_gem_init_memory_regions(i915);
+ if (err)
+ goto err_context;
+
return i915;
err_context:
--
2.20.1
___
Intel-gfx mailing list
[Intel-gfx] [PATCH v2 14/22] drm/i915: define HAS_MAPPABLE_APERTURE
From: Daniele Ceraolo Spurio The following patches in the series will use it to avoid certain operations when aperture is not available in HW. Signed-off-by: Daniele Ceraolo Spurio Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2c5cb2feda27..7824a31ee448 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2119,6 +2119,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ (INTEL_INFO(dev_priv)->display.overlay_needs_physical) +#define HAS_MAPPABLE_APERTURE(dev_priv) (dev_priv->ggtt.mappable_end > 0) + /* Early gen2 have a totally busted CS tlb and require pinned batches. */ #define HAS_BROKEN_CS_TLB(dev_priv)(IS_I830(dev_priv) || IS_I845G(dev_priv)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 13/22] drm/i915: treat stolen as a region
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 66 +++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 14 +
drivers/gpu/drm/i915/i915_pci.c| 2 +-
4 files changed, 62 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 3dd295bb61f6..a91ef9fe98cd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -10,6 +10,7 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
@@ -150,7 +151,7 @@ static int i915_adjust_stolen(struct drm_i915_private
*dev_priv,
return 0;
}
-void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
+static void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
{
if (!drm_mm_initialized(_priv->mm.stolen))
return;
@@ -355,7 +356,7 @@ static void icl_get_stolen_reserved(struct drm_i915_private
*i915,
}
}
-int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
+static int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
{
resource_size_t reserved_base, stolen_top;
resource_size_t reserved_total, reserved_size;
@@ -539,6 +540,9 @@ i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj)
i915_gem_stolen_remove_node(dev_priv, stolen);
kfree(stolen);
+
+ if (obj->mm.region)
+ i915_gem_object_release_memory_region(obj);
}
static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
@@ -548,8 +552,9 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_stolen_ops = {
};
static struct drm_i915_gem_object *
-_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- struct drm_mm_node *stolen)
+__i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ struct drm_mm_node *stolen,
+ struct intel_memory_region *mem)
{
struct drm_i915_gem_object *obj;
unsigned int cache_level;
@@ -566,6 +571,9 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE;
i915_gem_object_set_cache_coherency(obj, cache_level);
+ if (mem)
+ i915_gem_object_init_memory_region(obj, mem, 0);
+
if (i915_gem_object_pin_pages(obj))
goto cleanup;
@@ -576,10 +584,12 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return NULL;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- resource_size_t size)
+static struct drm_i915_gem_object *
+_i915_gem_object_create_stolen(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags)
{
+ struct drm_i915_private *dev_priv = mem->i915;
struct drm_i915_gem_object *obj;
struct drm_mm_node *stolen;
int ret;
@@ -598,7 +608,7 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
if (ret)
goto err_free;
- obj = _i915_gem_object_create_stolen(dev_priv, stolen);
+ obj = __i915_gem_object_create_stolen(dev_priv, stolen, mem);
if (obj == NULL) {
ret = -ENOMEM;
goto err_remove;
@@ -613,6 +623,44 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return ERR_PTR(ret);
}
+struct drm_i915_gem_object *
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ resource_size_t size)
+{
+
+ return
i915_gem_object_create_region(dev_priv->mm.regions[INTEL_MEMORY_STOLEN],
+size, I915_BO_ALLOC_CONTIGUOUS);
+}
+
+static int init_stolen(struct intel_memory_region *mem)
+{
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ return i915_gem_init_stolen(mem->i915);
+}
+
+static void release_stolen(struct intel_memory_region *mem)
+{
+ i915_gem_cleanup_stolen(mem->i915);
+}
+
+static const struct intel_memory_region_ops i915_region_stolen_ops = {
+ .init = init_stolen,
+ .release = release_stolen,
+ .create_object = _i915_gem_object_create_stolen,
+};
+
+struct intel_memory_region *i915_gem_stolen_setup(struct drm_i915_private
*i915)
+{
+ return intel_memory_region_create(i915,
+ intel_graphics_stolen_res.start,
+
[Intel-gfx] [PATCH v2 03/22] drm/i915/region: support contiguous allocations
Some kernel internal objects may need to be allocated as a contiguous
block, also thinking ahead the various kernel io_mapping interfaces seem
to expect it, although this is purely a limitation in the kernel
API...so perhaps something to be improved.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Cc: Michael J Ruhl
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 4 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 15 +-
drivers/gpu/drm/i915/gem/i915_gem_region.h| 3 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 63 ---
drivers/gpu/drm/i915/intel_memory_region.c| 9 +-
drivers/gpu/drm/i915/intel_memory_region.h| 3 +-
.../drm/i915/selftests/intel_memory_region.c | 165 ++
drivers/gpu/drm/i915/selftests/mock_region.c | 2 +-
8 files changed, 229 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index cff527e79661..2960aa0c79f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -118,6 +118,10 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
+ unsigned long flags;
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+
/*
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 5fc6e4540f82..04cb9f72945e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -23,10 +23,10 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
{
struct intel_memory_region *mem = obj->mm.region;
struct list_head *blocks = >mm.blocks;
- unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
resource_size_t size = obj->base.size;
resource_size_t prev_end;
struct i915_buddy_block *block;
+ unsigned int flags;
struct sg_table *st;
struct scatterlist *sg;
unsigned int sg_page_sizes;
@@ -42,6 +42,10 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
return -ENOMEM;
}
+ flags = I915_ALLOC_MIN_PAGE_SIZE;
+ if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
+ flags |= I915_ALLOC_CONTIGUOUS;
+
ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
if (ret)
goto err_free_sg;
@@ -56,7 +60,8 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
list_for_each_entry(block, blocks, link) {
u64 block_size, offset;
- block_size = i915_buddy_block_size(>mm, block);
+ block_size = min_t(u64, size,
+ i915_buddy_block_size(>mm, block));
offset = i915_buddy_block_offset(block);
GEM_BUG_ON(overflows_type(block_size, sg->length));
@@ -98,10 +103,12 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object
*obj)
}
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem)
+ struct intel_memory_region *mem,
+ unsigned long flags)
{
INIT_LIST_HEAD(>mm.blocks);
obj->mm.region = intel_memory_region_get(mem);
+ obj->flags = flags;
}
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj)
@@ -116,6 +123,8 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
{
struct drm_i915_gem_object *obj;
+ GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
+
if (!mem)
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h
b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index ebddc86d78f7..f2ff6f8bff74 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -17,7 +17,8 @@ void i915_gem_object_put_pages_buddy(struct
drm_i915_gem_object *obj,
struct sg_table *pages);
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mem);
+ struct intel_memory_region *mem,
+ unsigned long flags);
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 1313c7f93ef8..2549c233465c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@
[Intel-gfx] [PATCH v2 02/22] drm/i915: introduce intel_memory_region
Support memory regions, as defined by a given (start, end), and allow
creating GEM objects which are backed by said region. The immediate goal
here is to have something to represent our device memory, but later on
we also want to represent every memory domain with a region, so stolen,
shmem, and of course device. At some point we are probably going to want
use a common struct here, such that we are better aligned with say TTM.
Signed-off-by: Matthew Auld
Signed-off-by: Abdiel Janulgue
Signed-off-by: Niranjana Vishwanathapura
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile | 2 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +
drivers/gpu/drm/i915/gem/i915_gem_region.c| 134
drivers/gpu/drm/i915/gem/i915_gem_region.h| 28 +++
.../gpu/drm/i915/gem/selftests/huge_pages.c | 73 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_memory_region.c| 191 ++
drivers/gpu/drm/i915/intel_memory_region.h| 83
.../drm/i915/selftests/i915_mock_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 118 +++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
drivers/gpu/drm/i915/selftests/mock_region.c | 59 ++
drivers/gpu/drm/i915/selftests/mock_region.h | 16 ++
13 files changed, 716 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h
create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d2b53b5add81..da61b0dfe105 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -50,6 +50,7 @@ i915-y += i915_drv.o \
i915_utils.o \
intel_csr.o \
intel_device_info.o \
+ intel_memory_region.o \
intel_pch.o \
intel_pm.o \
intel_runtime_pm.o \
@@ -119,6 +120,7 @@ gem-y += \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
gem/i915_gem_pm.o \
+ gem/i915_gem_region.o \
gem/i915_gem_shmem.o \
gem/i915_gem_shrinker.o \
gem/i915_gem_stolen.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e1aab2fd1cd9..cff527e79661 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -159,6 +159,15 @@ struct drm_i915_gem_object {
atomic_t pages_pin_count;
atomic_t shrink_pin;
+ /**
+* Memory region for this object.
+*/
+ struct intel_memory_region *region;
+ /**
+* List of memory region blocks allocated for this object.
+*/
+ struct list_head blocks;
+
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
new file mode 100644
index ..5fc6e4540f82
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "i915_gem_region.h"
+#include "i915_drv.h"
+
+void
+i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
+ struct sg_table *pages)
+{
+ __intel_memory_region_put_pages_buddy(obj->mm.region, >mm.blocks);
+
+ obj->mm.dirty = false;
+ sg_free_table(pages);
+ kfree(pages);
+}
+
+int
+i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mem = obj->mm.region;
+ struct list_head *blocks = >mm.blocks;
+ unsigned int flags = I915_ALLOC_MIN_PAGE_SIZE;
+ resource_size_t size = obj->base.size;
+ resource_size_t prev_end;
+ struct i915_buddy_block *block;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ unsigned int sg_page_sizes;
+ unsigned long i;
+ int ret;
+
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ return -ENOMEM;
+
+ if (sg_alloc_table(st, size >> ilog2(mem->mm.chunk_size), GFP_KERNEL)) {
+ kfree(st);
+ return -ENOMEM;
+ }
+
+ ret = __intel_memory_region_get_pages_buddy(mem, size, flags, blocks);
+ if (ret)
+ goto err_free_sg;
+
+ GEM_BUG_ON(list_empty(blocks));
+
+ sg = st->sgl;
+ st->nents = 0;
+ sg_page_sizes = 0;
+ i = 0;
+
+
[Intel-gfx] [PATCH v2 05/22] drm/i915: Add memory region information to device_info
From: Abdiel Janulgue
Exposes available regions for the platform. Shared memory will
always be available.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a32f9e00905..f7b56a07a035 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2163,6 +2163,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
/* Having GuC is not the same as using GuC */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0cdc2465534b..e9940f932d26 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -160,6 +160,8 @@ struct intel_device_info {
unsigned int page_sizes; /* page sizes supported by the HW */
+ u32 memory_regions; /* regions supported by the HW */
+
u32 display_mmio_offset;
u8 pipe_mask;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 04/22] drm/i915/region: support volatile objects
Volatile objects are marked as DONTNEED while pinned, therefore once
unpinned the backing store can be discarded. This is limited to kernel
internal objects.
Signed-off-by: Matthew Auld
Signed-off-by: CQ Tang
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c| 17 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 6 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h| 9 -
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 ++
drivers/gpu/drm/i915/gem/i915_gem_region.c | 13 +
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 12
drivers/gpu/drm/i915/intel_memory_region.c | 4
drivers/gpu/drm/i915/intel_memory_region.h | 5 +
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 5 ++---
9 files changed, 57 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index 0c41e04ab8fa..5e72cb1cc2d3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -117,13 +117,6 @@ static int i915_gem_object_get_pages_internal(struct
drm_i915_gem_object *obj)
goto err;
}
- /* Mark the pages as dontneed whilst they are still pinned. As soon
-* as they are unpinned they are allowed to be reaped by the shrinker,
-* and the caller is expected to repopulate - the contents of this
-* object are only valid whilst active and pinned.
-*/
- obj->mm.madv = I915_MADV_DONTNEED;
-
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
@@ -143,7 +136,6 @@ static void i915_gem_object_put_pages_internal(struct
drm_i915_gem_object *obj,
internal_free_pages(pages);
obj->mm.dirty = false;
- obj->mm.madv = I915_MADV_WILLNEED;
}
static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = {
@@ -188,6 +180,15 @@ i915_gem_object_create_internal(struct drm_i915_private
*i915,
drm_gem_private_object_init(>drm, >base, size);
i915_gem_object_init(obj, _gem_object_internal_ops);
+ /*
+* Mark the object as volatile, such that the pages are marked as
+* dontneed whilst they are still pinned. As soon as they are unpinned
+* they are allowed to be reaped by the shrinker, and the caller is
+* expected to repopulate - the contents of this object are only valid
+* whilst active and pinned.
+*/
+ obj->flags = I915_BO_ALLOC_VOLATILE;
+
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 53c7069ba3e8..0c24436049e4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -122,6 +122,12 @@ i915_gem_object_lock_fence(struct drm_i915_gem_object
*obj);
void i915_gem_object_unlock_fence(struct drm_i915_gem_object *obj,
struct dma_fence *fence);
+static inline bool
+i915_gem_object_is_volatile(const struct drm_i915_gem_object *obj)
+{
+ return obj->flags & I915_BO_ALLOC_VOLATILE;
+}
+
static inline void
i915_gem_object_set_readonly(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 2960aa0c79f4..9a8579b67357 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -120,7 +120,8 @@ struct drm_i915_gem_object {
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | I915_BO_ALLOC_VOLATILE)
/*
* Is the object to be mapped as read-only to the GPU
@@ -171,6 +172,12 @@ struct drm_i915_gem_object {
* List of memory region blocks allocated for this object.
*/
struct list_head blocks;
+ /**
+* Element within memory_region->objects or region->purgeable
+* if the object is marked as DONTNEED. Access is protected by
+* region->obj_lock.
+*/
+ struct list_head region_link;
struct sg_table *pages;
void *mapping;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 2e941f093a20..b0ec0959c13f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -18,6 +18,9 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
lockdep_assert_held(>mm.lock);
+ if (i915_gem_object_is_volatile(obj))
+
[Intel-gfx] [PATCH v2 00/22] LMEM basics
The basic LMEM bits, minus the uAPI, pruning, etc. The goal is to support basic LMEM object creation within the kernel. From there we can start with the dumb buffer support, and then the other display related bits. Abdiel Janulgue (4): drm/i915: Add memory region information to device_info drm/i915: setup io-mapping for LMEM drm/i915/lmem: support kernel mapping drm/i915: enumerate and init each supported region CQ Tang (1): drm/i915/stolen: make the object creation interface consistent Daniele Ceraolo Spurio (4): drm/i915: define HAS_MAPPABLE_APERTURE drm/i915: do not map aperture if it is not available. drm/i915: set num_fence_regs to 0 if there is no aperture drm/i915: error capture with no ggtt slot Matthew Auld (12): drm/i915: introduce intel_memory_region drm/i915/region: support contiguous allocations drm/i915/region: support volatile objects drm/i915: support creating LMEM objects drm/i915/selftests: add write-dword test for LMEM drm/i915/selftests: extend coverage to include LMEM huge-pages drm/i915: treat shmem as a region drm/i915: treat stolen as a region drm/i915: don't allocate the ring in stolen if we lack aperture drm/i915/selftests: fallback to using the gpu to trash stolen drm/i915/selftests: check for missing aperture HAX drm/i915: add the fake lmem region Michal Wajdeczko (1): drm/i915: Don't try to place HWS in non-existing mappable region arch/x86/kernel/early-quirks.c| 26 + drivers/gpu/drm/i915/Makefile | 4 + drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_fbdev.c| 4 +- drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 17 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 70 ++ drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 31 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 29 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 28 +- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +- drivers/gpu/drm/i915/gem/i915_gem_region.c| 168 + drivers/gpu/drm/i915/gem/i915_gem_region.h| 29 + drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 68 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 100 ++- drivers/gpu/drm/i915/gem/i915_gem_stolen.h| 3 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 213 +- .../i915/gem/selftests/i915_gem_coherency.c | 5 +- .../drm/i915/gem/selftests/i915_gem_mman.c| 6 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c| 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +- drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 6 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 +- drivers/gpu/drm/i915/i915_drv.c | 8 + drivers/gpu/drm/i915/i915_drv.h | 15 + drivers/gpu/drm/i915/i915_gem.c | 9 - drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 119 +++- drivers/gpu/drm/i915/i915_gpu_error.c | 65 +- drivers/gpu/drm/i915/i915_pci.c | 29 +- drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/intel_memory_region.c| 212 ++ drivers/gpu/drm/i915/intel_memory_region.h| 125 drivers/gpu/drm/i915/intel_region_lmem.c | 157 + drivers/gpu/drm/i915/intel_region_lmem.h | 16 + drivers/gpu/drm/i915/selftests/i915_gem.c | 95 ++- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 8 +- .../drm/i915/selftests/i915_live_selftests.h | 1 + .../drm/i915/selftests/i915_mock_selftests.h | 1 + .../drm/i915/selftests/intel_memory_region.c | 617 ++ .../gpu/drm/i915/selftests/mock_gem_device.c | 9 +- drivers/gpu/drm/i915/selftests/mock_region.c | 59 ++ drivers/gpu/drm/i915/selftests/mock_region.h | 16 + include/drm/i915_drm.h| 3 + 46 files changed, 2253 insertions(+), 163 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_region.h create mode 100644 drivers/gpu/drm/i915/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/intel_memory_region.h create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h create mode 100644 drivers/gpu/drm/i915/selftests/intel_memory_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.c create mode 100644 drivers/gpu/drm/i915/selftests/mock_region.h -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 06/22] drm/i915: support creating LMEM objects
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 31 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 23 ++
drivers/gpu/drm/i915/i915_drv.h | 5 +++
drivers/gpu/drm/i915/intel_memory_region.c| 10 +
drivers/gpu/drm/i915/intel_memory_region.h| 30 +
drivers/gpu/drm/i915/intel_region_lmem.c | 43 ++
drivers/gpu/drm/i915/intel_region_lmem.h | 11 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 45 +++
10 files changed, 201 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index da61b0dfe105..07b1d3a6955c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -116,6 +116,7 @@ gem-y += \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_object_blt.o \
+ gem/i915_gem_lmem.o \
gem/i915_gem_mman.o \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
@@ -144,6 +145,7 @@ i915-y += \
i915_scheduler.o \
i915_trace_points.o \
i915_vma.o \
+ intel_region_lmem.o \
intel_wopcm.o
# general-purpose microcontroller (GuC) support
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
new file mode 100644
index ..26a23304df32
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
+#include "i915_drv.h"
+
+const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .get_pages = i915_gem_object_get_pages_buddy,
+ .put_pages = i915_gem_object_put_pages_buddy,
+ .release = i915_gem_object_release_memory_region,
+};
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *region = obj->mm.region;
+
+ return region && region->type == INTEL_LMEM;
+}
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags)
+{
+ return
i915_gem_object_create_region(i915->mm.regions[INTEL_MEMORY_LMEM],
+size, flags);
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
new file mode 100644
index ..ebc15fe24f58
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __I915_GEM_LMEM_H
+#define __I915_GEM_LMEM_H
+
+#include
+
+struct drm_i915_private;
+struct drm_i915_gem_object;
+
+extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags);
+
+#endif /* !__I915_GEM_LMEM_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f7b56a07a035..a2673f41d93b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -100,6 +100,8 @@
#include "i915_vma.h"
#include "i915_irq.h"
+#include "intel_region_lmem.h"
+
#include "intel_gvt.h"
/* General customization:
@@ -679,6 +681,8 @@ struct i915_gem_mm {
*/
struct vfsmount *gemfs;
+ struct intel_memory_region *regions[INTEL_MEMORY_UKNOWN];
+
struct notifier_block oom_notifier;
struct notifier_block vmap_notifier;
struct shrinker shrinker;
@@ -2164,6 +2168,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index fe808899cbf8..920f9590f410 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++
[Intel-gfx] [PATCH v2 01/22] drm/i915/stolen: make the object creation interface consistent
From: CQ Tang
Our other backends return an actual error value upon failure. Do the
same for stolen objects, which currently just return NULL on failure.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 4 +--
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 36 +++-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +--
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +-
7 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c3ac5a5c5185..3a7e324fab26 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3071,7 +3071,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
base_aligned,
size_aligned);
mutex_unlock(>struct_mutex);
- if (!obj)
+ if (IS_ERR(obj))
return false;
switch (plane_config->tiling) {
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 68338669f054..8e31f254b0d9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -141,10 +141,10 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
/* If the FB is too big, just don't use it since fbdev is not very
* important and we should probably use that space with FBC or other
* features. */
- obj = NULL;
+ obj = ERR_PTR(-ENODEV);
if (size * 2 < dev_priv->stolen_usable_size)
obj = i915_gem_object_create_stolen(dev_priv, size);
- if (obj == NULL)
+ if (IS_ERR(obj))
obj = i915_gem_object_create_shmem(dev_priv, size);
if (IS_ERR(obj)) {
DRM_ERROR("failed to allocate framebuffer\n");
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 5efef9babadb..fb4e2047efdb 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -1306,7 +1306,7 @@ static int get_registers(struct intel_overlay *overlay,
bool use_phys)
mutex_lock(>drm.struct_mutex);
obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
- if (obj == NULL)
+ if (IS_ERR(obj))
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index bfbc3e3daf92..3dd295bb61f6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -585,28 +585,32 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
int ret;
if (!drm_mm_initialized(_priv->mm.stolen))
- return NULL;
+ return ERR_PTR(-ENODEV);
if (size == 0)
- return NULL;
+ return ERR_PTR(-EINVAL);
stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
if (!stolen)
- return NULL;
+ return ERR_PTR(-ENOMEM);
ret = i915_gem_stolen_insert_node(dev_priv, stolen, size, 4096);
- if (ret) {
- kfree(stolen);
- return NULL;
- }
+ if (ret)
+ goto err_free;
obj = _i915_gem_object_create_stolen(dev_priv, stolen);
- if (obj)
- return obj;
+ if (obj == NULL) {
+ ret = -ENOMEM;
+ goto err_remove;
+ }
+ return obj;
+
+err_remove:
i915_gem_stolen_remove_node(dev_priv, stolen);
+err_free:
kfree(stolen);
- return NULL;
+ return ERR_PTR(ret);
}
struct drm_i915_gem_object *
@@ -622,7 +626,7 @@ i915_gem_object_create_stolen_for_preallocated(struct
drm_i915_private *dev_priv
int ret;
if (!drm_mm_initialized(_priv->mm.stolen))
- return NULL;
+ return ERR_PTR(-ENODEV);
lockdep_assert_held(_priv->drm.struct_mutex);
@@ -633,11 +637,11 @@ i915_gem_object_create_stolen_for_preallocated(struct
drm_i915_private *dev_priv
if (WARN_ON(size == 0) ||
WARN_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)) ||
WARN_ON(!IS_ALIGNED(stolen_offset, I915_GTT_MIN_ALIGNMENT)))
- return NULL;
+ return ERR_PTR(-EINVAL);
stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
if (!stolen)
- return NULL;
+ return ERR_PTR(-ENOMEM);
stolen->start = stolen_offset;
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: remove static variable for aux last status (rev3)
== Series Details ==
Series: drm/i915/dp: remove static variable for aux last status (rev3)
URL : https://patchwork.freedesktop.org/series/67499/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6996_full -> Patchwork_14647_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14647_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14647_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14647_full:
### IGT changes ###
Possible regressions
* igt@gem_mmap_gtt@hang:
- shard-skl: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-skl6/igt@gem_mmap_...@hang.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-skl6/igt@gem_mmap_...@hang.html
* igt@perf@short-reads:
- shard-iclb: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb2/igt@p...@short-reads.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-iclb4/igt@p...@short-reads.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_pm_dc@dc6-dpms}:
- shard-skl: [FAIL][5] ([fdo#110548]) -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-skl10/igt@i915_pm...@dc6-dpms.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-skl7/igt@i915_pm...@dc6-dpms.html
Known issues
Here are the changes found in Patchwork_14647_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@in-order-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +13 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb1/igt@gem_exec_sched...@in-order-bsd2.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-iclb5/igt@gem_exec_sched...@in-order-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +7 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb3/igt@gem_exec_sched...@preemptive-hang-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_fence_thrash@bo-copy:
- shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-hsw1/igt@gem_fence_thr...@bo-copy.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-hsw8/igt@gem_fence_thr...@bo-copy.html
* igt@gem_userptr_blits@coherency-sync:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-hsw6/igt@gem_userptr_bl...@coherency-sync.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-hsw7/igt@gem_userptr_bl...@coherency-sync.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-snb5/igt@gem_userptr_bl...@sync-unmap-cycles.html
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#109385] /
[fdo#111870])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-apl3/igt@gem_userptr_bl...@sync-unmap-cycles.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-apl1/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-apl: [PASS][19] -> [FAIL][20] ([fdo#103232])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-apl6/igt@kms_cursor_...@pipe-a-cursor-256x85-onscreen.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-apl7/igt@kms_cursor_...@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_legacy@pipe-c-forked-bo:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb4/igt@kms_cursor_leg...@pipe-c-forked-bo.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14647/shard-iclb7/igt@kms_cursor_leg...@pipe-c-forked-bo.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [PASS][23] ->
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v6,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
== Series Details ==
Series: series starting with [CI,v6,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync
URL : https://patchwork.freedesktop.org/series/67551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6999 -> Patchwork_14655
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/index.html
Known issues
Here are the changes found in Patchwork_14655 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6999/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724] /
[fdo#111214])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6999/fi-icl-u3/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-hsw-4770:[PASS][5] -> [SKIP][6] ([fdo#109271]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6999/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_flip@basic-plain-flip:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +2
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6999/fi-icl-u3/igt@kms_f...@basic-plain-flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/fi-icl-u3/igt@kms_f...@basic-plain-flip.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6999/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6999/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-guc: [INCOMPLETE][13] ([fdo#111700]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6999/fi-skl-guc/igt@i915_selftest@live_gem_contexts.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/fi-skl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_requests:
- {fi-tgl-u}: [INCOMPLETE][15] ([fdo#111867]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6999/fi-tgl-u/igt@i915_selftest@live_requests.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/fi-tgl-u/igt@i915_selftest@live_requests.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111045] / [fdo#111096]) ->
[FAIL][18] ([fdo#111407])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6999/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14655/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700
[fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
Participating hosts (52 -> 44)
--
Missing(8): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6999 -> Patchwork_14655
CI-20190529:
Re: [Intel-gfx] [PATCH] TGL HAX drm/i915/tgl: Interrupts are overrated
Quoting Chris Wilson (2019-10-03 19:56:13) > Why sleep when you can busywait for an interrupt? Throw out the old irq > handlers, and use irq_poll instead. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=111880 > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > --- Fwiw, enabling rps is still a death sentence with this. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] TGL HAX drm/i915/tgl: Interrupts are overrated
Why sleep when you can busywait for an interrupt? Throw out the old irq
handlers, and use irq_poll instead.
References: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 10 +++---
drivers/gpu/drm/i915/gt/intel_lrc.c | 34
4 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 0d21402945ab..bf2b27b6ebf2 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -13,6 +13,7 @@ config DRM_I915
select DRM_PANEL
select DRM_MIPI_DSI
select RELAY
+ select IRQ_POLL
select IRQ_WORK
# i915 depends on ACPI_VIDEO when ACPI is enabled
# but for select to work, need to select ACPI_VIDEO's dependencies, ick
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 943f0663837e..53265add81ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -8,6 +8,7 @@
#define __INTEL_ENGINE_TYPES__
#include
+#include
#include
#include
#include
@@ -330,6 +331,8 @@ struct intel_engine_cs {
struct drm_i915_gem_object *default_state;
void *pinned_default_state;
+ struct irq_poll irq_poll;
+
struct {
struct intel_ring *ring;
struct intel_timeline *timeline;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 34a4fb624bf7..76ad58268f61 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -209,12 +209,14 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
void gen11_gt_irq_postinstall(struct intel_gt *gt)
{
- const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
struct intel_uncore *uncore = gt->uncore;
- const u32 dmask = irqs << 16 | irqs;
- const u32 smask = irqs << 16;
+ u32 irqs, dmask, smask;
- BUILD_BUG_ON(irqs & 0x);
+ irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+ if (IS_TIGERLAKE(gt->i915))
+ irqs = 0; /* XXX lalalala */
+ smask = irqs << 16;
+ dmask = smask | irqs;
/* Enable RCS, BCS, VCS and VECS class interrupts. */
intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 431d3b8c3371..08c144708af7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1944,6 +1944,8 @@ static void process_csb(struct intel_engine_cs *engine)
GEM_BUG_ON(execlists->active - execlists->inflight >
execlists_num_ports(execlists));
+
+ intel_engine_queue_breadcrumbs(engine);
}
} while (head != tail);
@@ -1987,6 +1989,27 @@ static void execlists_submission_tasklet(unsigned long
data)
}
}
+static int iop_handler(struct irq_poll *iop, int budget)
+{
+ struct intel_engine_cs *engine =
+ container_of(iop, typeof(*engine), irq_poll);
+ struct intel_engine_execlists *execlists = >execlists;
+ struct tasklet_struct *t = >tasklet;
+
+ if (execlists->csb_head == READ_ONCE(*execlists->csb_write))
+ return 0;
+
+ if (!tasklet_trylock(t))
+ return 0;
+
+ /* Must wait for any GPU reset in progress. */
+ if (__tasklet_is_enabled(t))
+ t->func(t->data);
+
+ tasklet_unlock(t);
+ return 0;
+}
+
static void execlists_submission_timer(struct timer_list *timer)
{
struct intel_engine_cs *engine =
@@ -3414,9 +3437,16 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request
*request, u32 *cs)
return gen12_emit_fini_breadcrumb_footer(request, cs);
}
+static void tgl_unpark(struct intel_engine_cs *engine)
+{
+ clear_bit(IRQ_POLL_F_DISABLE, >irq_poll.state);
+ irq_poll_sched(>irq_poll);
+}
+
static void execlists_park(struct intel_engine_cs *engine)
{
del_timer(>execlists.timer);
+ set_bit(IRQ_POLL_F_DISABLE, >irq_poll.state);
}
void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
@@ -3432,6 +3462,8 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->park = execlists_park;
engine->unpark = NULL;
+ if (IS_TIGERLAKE(engine->i915))
+ engine->unpark = tgl_unpark;
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
if (!intel_vgpu_active(engine->i915)) {
@@ -3446,6 +3478,7 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
[Intel-gfx] [PATCH i-g-t v2 1/2] tests/kms_getfb: Add getfb2 tests
From: Daniel Stone
Mirroring addfb2, add tests for the new ioctl which will return us
information about framebuffers containing multiple buffers, as well as
modifiers.
Changes since v1:
- Add test that uses getfb2 output to call addfb2 as suggested by Ville
Signed-off-by: Daniel Stone
Signed-off-by: Juston Li
---
tests/kms_getfb.c | 103 ++
1 file changed, 103 insertions(+)
diff --git a/tests/kms_getfb.c b/tests/kms_getfb.c
index ca0b01c05e5c..848b896b7556 100644
--- a/tests/kms_getfb.c
+++ b/tests/kms_getfb.c
@@ -228,6 +228,106 @@ static void test_duplicate_handles(int fd)
}
}
+static void test_getfb2(int fd)
+{
+ struct drm_mode_fb_cmd2 add_basic = {};
+
+ igt_fixture {
+ struct drm_mode_fb_cmd2 get = {};
+
+ add_basic.width = 1024;
+ add_basic.height = 1024;
+ add_basic.pixel_format = DRM_FORMAT_XRGB;
+ add_basic.pitches[0] = 1024*4;
+ add_basic.handles[0] = igt_create_bo_with_dimensions(fd, 1024,
1024,
+ DRM_FORMAT_XRGB, 0, 0, NULL, NULL, NULL);
+ igt_assert(add_basic.handles[0]);
+ do_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, _basic);
+
+ get.fb_id = add_basic.fb_id;
+ do_ioctl(fd, DRM_IOCTL_MODE_GETFB2, );
+ igt_assert_neq_u32(get.handles[0], 0);
+ gem_close(fd, get.handles[0]);
+ }
+
+ igt_subtest("getfb2-handle-zero") {
+ struct drm_mode_fb_cmd2 get = {};
+ do_ioctl_err(fd, DRM_IOCTL_MODE_GETFB2, , ENOENT);
+ }
+
+ igt_subtest("getfb2-handle-closed") {
+ struct drm_mode_fb_cmd2 add = add_basic;
+ struct drm_mode_fb_cmd2 get = { };
+
+ add.handles[0] = igt_create_bo_with_dimensions(fd, 1024, 1024,
+ DRM_FORMAT_XRGB, 0, 0, NULL, NULL, NULL);
+ igt_assert(add.handles[0]);
+ do_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, );
+ do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _id);
+
+ get.fb_id = add.fb_id;
+ do_ioctl_err(fd, DRM_IOCTL_MODE_GETFB2, , ENOENT);
+ gem_close(fd, add.handles[0]);
+ }
+
+ igt_subtest("getfb2-handle-not-fb") {
+ struct drm_mode_fb_cmd get = { .fb_id = get_any_prop_id(fd) };
+ igt_require(get.fb_id > 0);
+ do_ioctl_err(fd, DRM_IOCTL_MODE_GETFB, , ENOENT);
+ }
+
+ igt_subtest("getfb2-accept-ccs") {
+ struct drm_mode_fb_cmd2 add_ccs = { };
+ struct drm_mode_fb_cmd2 get = { };
+ int i;
+
+ get_ccs_fb(fd, _ccs);
+ igt_require(add_ccs.fb_id != 0);
+ get.fb_id = add_ccs.fb_id;
+ do_ioctl(fd, DRM_IOCTL_MODE_GETFB2, );
+
+ igt_assert_eq_u32(get.width, add_ccs.width);
+ igt_assert_eq_u32(get.height, add_ccs.height);
+ igt_assert(get.flags & DRM_MODE_FB_MODIFIERS);
+
+ for (i = 0; i < ARRAY_SIZE(get.handles); i++) {
+ igt_assert_eq_u32(get.pitches[i], add_ccs.pitches[i]);
+ igt_assert_eq_u32(get.offsets[i], add_ccs.offsets[i]);
+ if (add_ccs.handles[i] != 0) {
+ igt_assert_neq_u32(get.handles[i], 0);
+ igt_assert_neq_u32(get.handles[i],
+ add_ccs.handles[i]);
+ igt_assert_eq_u64(get.modifier[i],
+ add_ccs.modifier[i]);
+ } else {
+ igt_assert_eq_u32(get.handles[i], 0);
+ igt_assert_eq_u64(get.modifier[i], 0);
+ }
+ }
+ igt_assert_eq_u32(get.handles[0], get.handles[1]);
+
+ do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _id);
+ gem_close(fd, add_ccs.handles[0]);
+ gem_close(fd, get.handles[0]);
+ }
+
+ igt_subtest("getfb2-into-addfb2") {
+ struct drm_mode_fb_cmd2 cmd = { };
+
+ cmd.fb_id = add_basic.fb_id;
+ do_ioctl(fd, DRM_IOCTL_MODE_GETFB2, );
+ do_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, );
+
+ do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _id);
+ gem_close(fd, cmd.handles[0]);
+ }
+
+ igt_fixture {
+ do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _basic.fb_id);
+ gem_close(fd, add_basic.handles[0]);
+ }
+}
+
igt_main
{
int fd;
@@ -243,6 +343,9 @@ igt_main
igt_subtest_group
test_duplicate_handles(fd);
+ igt_subtest_group
+ test_getfb2(fd);
+
igt_fixture
close(fd);
}
--
2.21.0
___
Intel-gfx
[Intel-gfx] [PATCH i-g-t v2 2/2] NOMERGE: Import drm.h up to 54ecb8f7028c
Depends on ummerged kernel code for getfb2
Rest of drm.h taken from:
commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c
Author: Linus Torvalds
Date: Mon Sep 30 10:35:40 2019 -0700
Linux 5.4-rc1
Signed-off-by: Juston Li
---
include/drm-uapi/drm.h | 39 +++
1 file changed, 39 insertions(+)
diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h
index 85c685a2075e..0b02f4c92d1e 100644
--- a/include/drm-uapi/drm.h
+++ b/include/drm-uapi/drm.h
@@ -643,6 +643,7 @@ struct drm_gem_open {
#define DRM_CAP_PAGE_FLIP_TARGET 0x11
#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
#define DRM_CAP_SYNCOBJ0x13
+#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
@@ -729,8 +730,18 @@ struct drm_syncobj_handle {
__u32 pad;
};
+struct drm_syncobj_transfer {
+ __u32 src_handle;
+ __u32 dst_handle;
+ __u64 src_point;
+ __u64 dst_point;
+ __u32 flags;
+ __u32 pad;
+};
+
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point
to become available */
struct drm_syncobj_wait {
__u64 handles;
/* absolute timeout */
@@ -741,12 +752,33 @@ struct drm_syncobj_wait {
__u32 pad;
};
+struct drm_syncobj_timeline_wait {
+ __u64 handles;
+ /* wait on specific timeline point for every handles*/
+ __u64 points;
+ /* absolute timeout */
+ __s64 timeout_nsec;
+ __u32 count_handles;
+ __u32 flags;
+ __u32 first_signaled; /* only valid when not waiting all */
+ __u32 pad;
+};
+
+
struct drm_syncobj_array {
__u64 handles;
__u32 count_handles;
__u32 pad;
};
+struct drm_syncobj_timeline_array {
+ __u64 handles;
+ __u64 points;
+ __u32 count_handles;
+ __u32 pad;
+};
+
+
/* Query current scanout sequence number */
struct drm_crtc_get_sequence {
__u32 crtc_id; /* requested crtc_id */
@@ -903,6 +935,13 @@ extern "C" {
#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct
drm_mode_get_lease)
#define DRM_IOCTL_MODE_REVOKE_LEASEDRM_IOWR(0xC9, struct
drm_mode_revoke_lease)
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAITDRM_IOWR(0xCA, struct
drm_syncobj_timeline_wait)
+#define DRM_IOCTL_SYNCOBJ_QUERYDRM_IOWR(0xCB, struct
drm_syncobj_timeline_array)
+#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct
drm_syncobj_transfer)
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct
drm_syncobj_timeline_array)
+
+#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
+
/**
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Add Sphinx-compatible references to struct fields
== Series Details == Series: drm/i915: Add Sphinx-compatible references to struct fields URL : https://patchwork.freedesktop.org/series/67550/ State : failure == Summary == Applying: drm/i915: Add Sphinx-compatible references to struct fields Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_drv.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_drv.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_drv.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Add Sphinx-compatible references to struct fields When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RESEND PATCH v2] drm: Add getfb2 ioctl
From: Daniel Stone
getfb2 allows us to pass multiple planes and modifiers, just like addfb2
over addfb.
Changes since v1:
- unused modifiers set to 0 instead of DRM_FORMAT_MOD_INVALID
- update ioctl number
Signed-off-by: Daniel Stone
Signed-off-by: Juston Li
---
drivers/gpu/drm/drm_crtc_internal.h | 2 +
drivers/gpu/drm/drm_framebuffer.c | 110
drivers/gpu/drm/drm_ioctl.c | 1 +
include/uapi/drm/drm.h | 2 +
4 files changed, 115 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc_internal.h
b/drivers/gpu/drm/drm_crtc_internal.h
index c7d5e4c21423..16f2413403aa 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -216,6 +216,8 @@ int drm_mode_rmfb_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_getfb(struct drm_device *dev,
void *data, struct drm_file *file_priv);
+int drm_mode_getfb2_ioctl(struct drm_device *dev,
+ void *data, struct drm_file *file_priv);
int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/drm_framebuffer.c
b/drivers/gpu/drm/drm_framebuffer.c
index 57564318ceea..6db54f177443 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include
#include
@@ -548,7 +549,116 @@ int drm_mode_getfb(struct drm_device *dev,
out:
drm_framebuffer_put(fb);
+ return ret;
+}
+
+/**
+ * drm_mode_getfb2 - get extended FB info
+ * @dev: drm device for the ioctl
+ * @data: data pointer for the ioctl
+ * @file_priv: drm file for the ioctl call
+ *
+ * Lookup the FB given its ID and return info about it.
+ *
+ * Called by the user via ioctl.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_mode_getfb2_ioctl(struct drm_device *dev,
+ void *data, struct drm_file *file_priv)
+{
+ struct drm_mode_fb_cmd2 *r = data;
+ struct drm_framebuffer *fb;
+ unsigned int i;
+ int ret;
+
+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ return -EINVAL;
+
+ fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id);
+ if (!fb)
+ return -ENOENT;
+
+ /* For multi-plane framebuffers, we require the driver to place the
+* GEM objects directly in the drm_framebuffer. For single-plane
+* framebuffers, we can fall back to create_handle.
+*/
+ if (!fb->obj[0] &&
+ (fb->format->num_planes > 1 || !fb->funcs->create_handle)) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ r->height = fb->height;
+ r->width = fb->width;
+ r->pixel_format = fb->format->format;
+
+ r->flags = 0;
+ if (dev->mode_config.allow_fb_modifiers)
+ r->flags |= DRM_MODE_FB_MODIFIERS;
+
+ for (i = 0; i < ARRAY_SIZE(r->handles); i++) {
+ r->handles[i] = 0;
+ r->pitches[i] = 0;
+ r->offsets[i] = 0;
+ r->modifier[i] = 0;
+ }
+ for (i = 0; i < fb->format->num_planes; i++) {
+ int j;
+
+ r->pitches[i] = fb->pitches[i];
+ r->offsets[i] = fb->offsets[i];
+ if (dev->mode_config.allow_fb_modifiers)
+ r->modifier[i] = fb->modifier;
+
+ /* If we reuse the same object for multiple planes, also
+* return the same handle.
+*/
+ for (j = 0; j < i; j++) {
+ if (fb->obj[i] == fb->obj[j]) {
+ r->handles[i] = r->handles[j];
+ break;
+ }
+ }
+
+ if (r->handles[i])
+ continue;
+
+ if (fb->obj[i]) {
+ ret = drm_gem_handle_create(file_priv, fb->obj[i],
+ >handles[i]);
+ } else {
+ WARN_ON(i > 0);
+ ret = fb->funcs->create_handle(fb, file_priv,
+ >handles[i]);
+ }
+
+ if (ret != 0)
+ goto out;
+ }
+
+out:
+ if (ret != 0) {
+ /* Delete any previously-created handles on failure. */
+ for (i = 0; i < ARRAY_SIZE(r->handles); i++) {
+ int j;
+
+ if (r->handles[i])
+ drm_gem_handle_delete(file_priv, r->handles[i]);
+
+ /* Zero out any handles identical to the one we just
+* deleted.
+*/
+ for (j = i + 1; j < ARRAY_SIZE(r->handles); j++) {
+
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915: Fix audio power up sequence for gen10+ display
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Fix audio power up sequence for
gen10+ display
URL : https://patchwork.freedesktop.org/series/67528/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6996_full -> Patchwork_14644_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14644_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14644_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14644_full:
### IGT changes ###
Possible regressions
* igt@gem_mmap_gtt@hang:
- shard-skl: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-skl6/igt@gem_mmap_...@hang.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-skl4/igt@gem_mmap_...@hang.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_pm_dc@dc5-psr}:
- shard-iclb: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb8/igt@i915_pm...@dc5-psr.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-iclb5/igt@i915_pm...@dc5-psr.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-tglb8/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html
Known issues
Here are the changes found in Patchwork_14644_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-iclb: [PASS][6] -> [DMESG-WARN][7] ([fdo#111764])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb3/igt@gem_ctx_isolat...@rcs0-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-iclb7/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_exec_reloc@basic-wc-cpu-active:
- shard-skl: [PASS][8] -> [DMESG-WARN][9] ([fdo#106107])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-skl3/igt@gem_exec_re...@basic-wc-cpu-active.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-skl4/igt@gem_exec_re...@basic-wc-cpu-active.html
* igt@gem_exec_schedule@deep-bsd2:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +12 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb4/igt@gem_exec_sched...@deep-bsd2.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-iclb7/igt@gem_exec_sched...@deep-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#111325]) +4 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html
* igt@gem_mmap_gtt@hang:
- shard-apl: [PASS][14] -> [DMESG-WARN][15] ([fdo#109385])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-apl2/igt@gem_mmap_...@hang.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-apl3/igt@gem_mmap_...@hang.html
* igt@gem_userptr_blits@coherency-sync:
- shard-hsw: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-hsw6/igt@gem_userptr_bl...@coherency-sync.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-hsw8/igt@gem_userptr_bl...@coherency-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870]) +1
similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@sync-unmap:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([fdo#111870])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-glk9/igt@gem_userptr_bl...@sync-unmap.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14644/shard-glk6/igt@gem_userptr_bl...@sync-unmap.html
- shard-skl: [PASS][22] -> [DMESG-WARN][23] ([fdo#111870])
[22]:
[Intel-gfx] [CI v6 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().
v2:
* Directly write the trans_port_sync reg value (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 22
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 34572fa6512a..0ffacfa71179 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4469,6 +4469,25 @@ static void icl_enable_trans_port_sync(const struct
intel_crtc_state *crtc_state
trans_ddi_func_ctl2_val);
}
+static void icl_disable_transcoder_port_sync(const struct intel_crtc_state
*old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ i915_reg_t reg;
+ u32 trans_ddi_func_ctl2_val;
+
+ if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
+ return;
+
+ DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
+ transcoder_name(old_crtc_state->cpu_transcoder));
+
+ reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
+ trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
+ PORT_SYNC_MODE_MASTER_SELECT_MASK);
+ I915_WRITE(reg, trans_ddi_func_ctl2_val);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state,
const struct intel_crtc_state
*new_crtc_state)
{
@@ -6718,6 +6737,9 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_disable_transcoder_port_sync(old_crtc_state);
+
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI v6 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state mismatch.
v7:
* NDont read HW state for DSI
v6:
* Go through both parts of HW readout (Maarten)
* Add a WARN if the same trans configured as
master and slave (Ville, Maarten)
v5:
* Add return INVALID in defaut case (Maarten)
v4:
* Get power domains in master loop for get_config (Ville)
v3:
* Add TRANSCODER_D (Maarten)
* v3 Reviewed-by: Maarten Lankhorst
v2:
* Add Transcoder_D and MISSING_CASE (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 70
1 file changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8ae617d3f030..b8f773af16d5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10510,6 +10510,72 @@ static void haswell_get_ddi_port_state(struct
intel_crtc *crtc,
}
}
+static enum transcoder transcoder_master(struct drm_i915_private *dev_priv,
+enum transcoder cpu_transcoder)
+{
+ u32 trans_port_sync, master_select;
+
+ trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
+
+ if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
+ return INVALID_TRANSCODER;
+
+ master_select = trans_port_sync &
+ PORT_SYNC_MODE_MASTER_SELECT_MASK;
+ switch (master_select) {
+ case 1:
+ return TRANSCODER_A;
+ case 2:
+ return TRANSCODER_B;
+ case 3:
+ return TRANSCODER_C;
+ case 4:
+ return TRANSCODER_D;
+ default:
+ MISSING_CASE(master_select);
+ return INVALID_TRANSCODER;
+ }
+}
+
+static void icelake_get_trans_port_sync_config(struct intel_crtc *crtc,
+ struct intel_crtc_state
*pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ u32 transcoders;
+ enum transcoder cpu_transcoder;
+
+ pipe_config->master_transcoder = transcoder_master(dev_priv,
+
pipe_config->cpu_transcoder);
+ if (pipe_config->master_transcoder != INVALID_TRANSCODER)
+ pipe_config->sync_mode_slaves_mask = 0;
+
+ transcoders = BIT(TRANSCODER_A) |
+ BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) |
+ BIT(TRANSCODER_D);
+ for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+ enum intel_display_power_domain power_domain;
+ intel_wakeref_t trans_wakeref;
+
+ power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+ trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
+
power_domain);
+
+ if (!trans_wakeref)
+ continue;
+
+ if (transcoder_master(dev_priv, cpu_transcoder) ==
+ pipe_config->cpu_transcoder)
+ pipe_config->sync_mode_slaves_mask |=
BIT(cpu_transcoder);
+
+ intel_display_power_put(dev_priv, power_domain, trans_wakeref);
+ }
+
+ WARN_ON(pipe_config->master_transcoder != INVALID_TRANSCODER &&
+ pipe_config->sync_mode_slaves_mask);
+}
+
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -10629,6 +10695,10 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
pipe_config->pixel_multiplier = 1;
}
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ !transcoder_is_dsi(pipe_config->cpu_transcoder))
+ icelake_get_trans_port_sync_config(crtc, pipe_config);
+
out:
for_each_power_domain(power_domain, power_domain_mask)
intel_display_power_put(dev_priv,
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI v6 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the transcoder port sync mode is configured and enabled
and the Vblanks of both ports are synchronized so then set DP_TP_CTL
for the slave and master to Normal and do post crtc enable updates.
v6:
* Modeset implies active_changed, remove one condition (Maarten)
v5:
* Fix checkpatch warning (Manasi)
v4:
* Reuse skl_commit_modeset_enables() hook (Maarten)
* Obtain slave crtc and states from master (Maarten)
v3:
* Rebase on drm-tip (Manasi)
v2:
* Create a icl_update_crtcs hook (Maarten, Danvet)
* This sequence only for CRTCs in trans port sync mode (Maarten)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 141 ++-
drivers/gpu/drm/i915/display/intel_display.h | 2 +
3 files changed, 142 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3c1e885e0187..97d383d8856a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3489,7 +3489,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder
*encoder,
true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
- if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
+ if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
+ !is_trans_port_sync_mode(dev_priv, crtc_state))
intel_dp_stop_link_train(intel_dp);
intel_ddi_enable_fec(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b8f773af16d5..34572fa6512a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13985,6 +13985,30 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_finish_crtc_commit(state, crtc);
}
+static struct intel_crtc *intel_get_slave_crtc(struct drm_i915_private
*dev_priv,
+ struct intel_crtc_state
*new_crtc_state)
+{
+ if (new_crtc_state->sync_mode_slaves_mask &
+ BIT(TRANSCODER_A))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_A);
+ else if (new_crtc_state->sync_mode_slaves_mask &
+BIT(TRANSCODER_B))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_B);
+ else if (new_crtc_state->sync_mode_slaves_mask &
+BIT(TRANSCODER_C))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_C);
+ else if (new_crtc_state->sync_mode_slaves_mask &
+BIT(TRANSCODER_D))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_D);
+ /* should never happen */
+ WARN_ON(1);
+ return NULL;
+}
+
static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state
*new_crtc_state,
@@ -14063,6 +14087,104 @@ static void intel_commit_modeset_enables(struct
intel_atomic_state *state)
}
}
+static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state
*new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ update_scanline_offset(new_crtc_state);
+ dev_priv->display.crtc_enable(new_crtc_state, state);
+ intel_crtc_enable_pipe_crc(crtc);
+}
+
+static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
+ struct intel_atomic_state *state)
+{
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ struct intel_dp *intel_dp;
+ int i;
+
+ for_each_new_connector_in_state(>base, conn, conn_state, i) {
+ if (conn_state->crtc == >base)
+ break;
+ }
+ intel_dp = enc_to_intel_dp(_attached_encoder(conn)->base);
+ intel_dp_stop_link_train(intel_dp);
+}
+
+static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+
[Intel-gfx] [CI v6 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave transcoder
and the master transcoder is unaware that it is operating
in this mode.
This has been tested with tiled display connected to ICL.
v5:
* Add TRANSCODER_D case and MISSING_CASE (Maarten)
v4:
Rebase
v3:
* Check of DP_MST moved to atomic_check (Maarten)
v2:
* Do not use RMW, just write to the register in commit (Jani N)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 46
1 file changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 567eb2574295..8ae617d3f030 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4426,6 +4426,49 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
I915_WRITE(PIPE_CHICKEN(pipe), tmp);
}
+static void icl_enable_trans_port_sync(const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 trans_ddi_func_ctl2_val;
+ u8 master_select;
+
+ /*
+* Configure the master select and enable Transcoder Port Sync for
+* Slave CRTCs transcoder.
+*/
+ if (crtc_state->master_transcoder == INVALID_TRANSCODER)
+ return;
+
+ switch (crtc_state->master_transcoder) {
+ case TRANSCODER_A:
+ master_select = 1;
+ break;
+ case TRANSCODER_B:
+ master_select = 2;
+ break;
+ case TRANSCODER_C:
+ master_select = 3;
+ break;
+ case TRANSCODER_D:
+ master_select = 4;
+ break;
+ case TRANSCODER_EDP:
+ default:
+ MISSING_CASE(crtc_state->master_transcoder);
+ master_select = 0;
+ }
+ /* Set the master select bits for Tranascoder Port Sync */
+ trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
+ PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
+ PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
+ /* Enable Transcoder Port Sync */
+ trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
+
+ I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
+ trans_ddi_func_ctl2_val);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state,
const struct intel_crtc_state
*new_crtc_state)
{
@@ -6494,6 +6537,9 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
if (!transcoder_is_dsi(cpu_transcoder))
intel_set_pipe_timings(pipe_config);
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_enable_trans_port_sync(pipe_config);
+
intel_set_pipe_src_size(pipe_config);
if (cpu_transcoder != TRANSCODER_EDP &&
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI v6 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical tile that needs to be genlocked with
all other slave tiles.
This patch identifies saves the master transcoder in all the slave
CRTC states. This is needed to select the master CRTC/transcoder
while configuring transcoder port sync for the corresponding slaves.
v4:
* Rebase
v3:
* Use master_tramscoder instead of master_crtc for valid
HW state readouts (Ville)
v2:
* Move this to intel_mode_set_pipe_config(Jani N, Ville)
* Use slave_bitmask to save associated slaves in master crtc state (Ville)
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 123 ++
drivers/gpu/drm/i915/display/intel_display.h | 3 +
.../drm/i915/display/intel_display_types.h| 6 +
3 files changed, 132 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 65d71851c89d..567eb2574295 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -521,6 +521,24 @@ needs_modeset(const struct intel_crtc_state *state)
return drm_atomic_crtc_needs_modeset(>base);
}
+bool
+is_trans_port_sync_mode(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *state)
+{
+ return (INTEL_GEN(dev_priv) >= 11 &&
+ (state->master_transcoder != INVALID_TRANSCODER ||
+state->sync_mode_slaves_mask));
+}
+
+static bool
+is_trans_port_sync_master(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *state)
+{
+ return (INTEL_GEN(dev_priv) >= 11 &&
+ (state->master_transcoder == INVALID_TRANSCODER &&
+state->sync_mode_slaves_mask));
+}
+
/*
* Platform specific helpers to calculate the port PLL loopback- (clock.m),
* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
@@ -11828,6 +11846,91 @@ static bool c8_planes_changed(const struct
intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int icl_add_sync_mode_crtcs(struct drm_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_connector *master_connector, *connector;
+ struct drm_connector_state *connector_state;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_crtc *master_crtc = NULL;
+ struct drm_crtc_state *master_crtc_state;
+ struct intel_crtc_state *master_pipe_config;
+ int i, tile_group_id;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return 0;
+
+ /*
+* In case of tiled displays there could be one or more slaves but
there is
+* only one master. Lets make the CRTC used by the connector
corresponding
+* to the last horizonal and last vertical tile a master/genlock CRTC.
+* All the other CRTCs corresponding to other tiles of the same Tile
group
+* are the slave CRTCs and hold a pointer to their genlock CRTC.
+*/
+ for_each_new_connector_in_state(state, connector, connector_state, i) {
+ if (connector_state->crtc != crtc)
+ continue;
+ if (!connector->has_tile)
+ continue;
+ if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
+ crtc_state->base.mode.vdisplay != connector->tile_v_size)
+ return 0;
+ if (connector->tile_h_loc == connector->num_h_tile - 1 &&
+ connector->tile_v_loc == connector->num_v_tile - 1)
+ continue;
+ crtc_state->sync_mode_slaves_mask = 0;
+ tile_group_id = connector->tile_group->id;
+ drm_connector_list_iter_begin(_priv->drm, _iter);
+ drm_for_each_connector_iter(master_connector, _iter) {
+ struct drm_connector_state *master_conn_state = NULL;
+
+ if (!master_connector->has_tile)
+ continue;
+ if (master_connector->tile_h_loc !=
master_connector->num_h_tile - 1 ||
+ master_connector->tile_v_loc !=
master_connector->num_v_tile - 1)
+ continue;
+ if (master_connector->tile_group->id != tile_group_id)
+ continue;
+
[Intel-gfx] [CI v6 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v4:
* Obtain slave state from master (Maarten)
v3:
* Rebase
v2:
* Use the intel_old_crtc_state_disables() helper
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 62 ++--
1 file changed, 56 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0ffacfa71179..cba1dba02822 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14066,8 +14066,42 @@ static void intel_old_crtc_state_disables(struct
intel_atomic_state *state,
new_crtc_state);
}
+static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state
*state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state
*old_crtc_state,
+ struct intel_crtc_state
*new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *slave_crtc = intel_get_slave_crtc(dev_priv,
+new_crtc_state);
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave_crtc);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave_crtc);
+
+ WARN_ON(!slave_crtc || !new_slave_crtc_state ||
+ !old_slave_crtc_state);
+
+ /* Disable Slave first */
+ intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
+ if (old_slave_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_slave_crtc_state,
+ new_slave_crtc_state,
+ slave_crtc);
+
+ /* Disable Master */
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+}
+
static void intel_commit_modeset_disables(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_crtc *crtc;
int i;
@@ -14084,13 +14118,29 @@ static void intel_commit_modeset_disables(struct
intel_atomic_state *state)
if (!needs_modeset(new_crtc_state))
continue;
- intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ /* In case of Transcoder port Sync master slave CRTCs can be
+* assigned in any order and we need to make sure that
+* slave CRTCs are disabled first and then master CRTC since
+* Slave vblanks are masked till Master Vblanks.
+*/
+ if (is_trans_port_sync_mode(dev_priv, new_crtc_state)) {
+ if (is_trans_port_sync_master(dev_priv,
+ new_crtc_state))
+ intel_trans_port_sync_modeset_disables(state,
+ crtc,
+
old_crtc_state,
+
new_crtc_state);
+ else
+ continue;
+ } else {
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
- if (old_crtc_state->base.active)
- intel_old_crtc_state_disables(state,
- old_crtc_state,
- new_crtc_state,
- crtc);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+ }
}
}
--
2.19.1
Re: [Intel-gfx] [PULL] drm-intel-fixes
On Thu, Oct 03, 2019 at 10:58:52AM -0700, Rodrigo Vivi wrote:
> Hi Dave and Daniel,
>
> I know you are on XDC and I was even considering not send any this week,
> but let me send this before I forget.
>
> There are the drm-intel-next-fixes pull requests that I had sent
> that are still needed and it would be good if you could pull those.
>
> Besides we have more 2 fixes here.
>
> If necessary and easier I can send all fixes together next week, including
> the ones missed on -rc1 and these ones here plus any upcoming.
>
> Just let me know how you prefer.
>
> Here goes drm-intel-fixes-2019-10-03:
>
> - Fix dsc dpp calculations
> - Fix g4x sprite scaling stride check with GTT remapping
Where is e838bfa8e170 ("Revert "drm/i915: Fix DP-MST crtc_mask"") ?
I can't see it in any fixes branch. That needs to get in ASAP.
>
> Thanks,
> Rodrigo.
>
> The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c:
>
> Linux 5.4-rc1 (2019-09-30 10:35:40 -0700)
>
> are available in the Git repository at:
>
> git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-10-03
>
> for you to fetch changes up to eb0192fed016db1c5a9701cd6ca47233ff4a43e5:
>
> drm/i915: Fix g4x sprite scaling stride check with GTT remapping
> (2019-10-02 22:20:33 -0700)
>
>
> - Fix dsc dpp calculations
> - Fix g4x sprite scaling stride check with GTT remapping
>
>
> Maarten Lankhorst (1):
> drm/i915/dp: Fix dsc bpp calculations, v5.
>
> Ville Syrjälä (1):
> drm/i915: Fix g4x sprite scaling stride check with GTT remapping
>
> drivers/gpu/drm/i915/display/intel_display.c | 12 +-
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 184
> ++-
> drivers/gpu/drm/i915/display/intel_dp.h | 6 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
> 6 files changed, 110 insertions(+), 101 deletions(-)
> ___
> dim-tools mailing list
> dim-to...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dim-tools
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, I know you are on XDC and I was even considering not send any this week, but let me send this before I forget. There are the drm-intel-next-fixes pull requests that I had sent that are still needed and it would be good if you could pull those. Besides we have more 2 fixes here. If necessary and easier I can send all fixes together next week, including the ones missed on -rc1 and these ones here plus any upcoming. Just let me know how you prefer. Here goes drm-intel-fixes-2019-10-03: - Fix dsc dpp calculations - Fix g4x sprite scaling stride check with GTT remapping Thanks, Rodrigo. The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-10-03 for you to fetch changes up to eb0192fed016db1c5a9701cd6ca47233ff4a43e5: drm/i915: Fix g4x sprite scaling stride check with GTT remapping (2019-10-02 22:20:33 -0700) - Fix dsc dpp calculations - Fix g4x sprite scaling stride check with GTT remapping Maarten Lankhorst (1): drm/i915/dp: Fix dsc bpp calculations, v5. Ville Syrjälä (1): drm/i915: Fix g4x sprite scaling stride check with GTT remapping drivers/gpu/drm/i915/display/intel_display.c | 12 +- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 184 ++- drivers/gpu/drm/i915/display/intel_dp.h | 6 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- 6 files changed, 110 insertions(+), 101 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliace auto test.
== Series Details ==
Series: DP Phy compliace auto test.
URL : https://patchwork.freedesktop.org/series/67546/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6998 -> Patchwork_14653
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/index.html
Known issues
Here are the changes found in Patchwork_14653 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][1] -> [FAIL][2] ([fdo#103167])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live_execlists:
- fi-bsw-kefka: [DMESG-FAIL][3] ([fdo#111895]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-bsw-kefka/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/fi-bsw-kefka/igt@i915_selftest@live_execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
[fdo#111895]: https://bugs.freedesktop.org/show_bug.cgi?id=111895
Participating hosts (51 -> 44)
--
Additional (1): fi-kbl-soraka
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bwr-2160 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6998 -> Patchwork_14653
CI-20190529: 20190529
CI_DRM_6998: fd44976bff7ae3cdf72245ac33d92d2186e57e9b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5210: 74f55119f9920b65996535210a09147997804136 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14653: 77cab7c63700d1785248d4bd2fe16bd47133e1ac @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
77cab7c63700 drm/i915/dp: Program vswing, pre-emphasis, test-pattern
37e871ded5f0 drm/i915/dp: Update the pattern as per request.
a922ee94741a drm/i915/dp: Register definition for DP compliance register.
ee56d9460821 drm/i915/dp: Preparation for DP phy compliance auto test.
7eb9c2d46a96 drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
0c3427b6dd5d drm/dp: get/set phy compliance pattern.
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14653/index.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915/vga: rename intel_vga_msr_write() to intel_vga_reset_io_mem() (rev2)
== Series Details ==
Series: series starting with [1/4] drm/i915/vga: rename intel_vga_msr_write()
to intel_vga_reset_io_mem() (rev2)
URL : https://patchwork.freedesktop.org/series/67493/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6996_full -> Patchwork_14643_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14643_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14643_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14643_full:
### IGT changes ###
Possible regressions
* igt@kms_psr@sprite_render:
- shard-skl: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-skl5/igt@kms_psr@sprite_render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-skl7/igt@kms_psr@sprite_render.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_schedule@preempt-hang-vebox:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4] +2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-tglb5/igt@gem_exec_sched...@preempt-hang-vebox.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-tglb7/igt@gem_exec_sched...@preempt-hang-vebox.html
Known issues
Here are the changes found in Patchwork_14643_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110841])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +4 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb8/igt@gem_exec_as...@concurrent-writes-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-iclb2/igt@gem_exec_as...@concurrent-writes-bsd.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +17 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb2/igt@gem_exec_sched...@independent-bsd2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html
* igt@gem_userptr_blits@coherency-sync:
- shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-hsw6/igt@gem_userptr_bl...@coherency-sync.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-hsw6/igt@gem_userptr_bl...@coherency-sync.html
* igt@gem_userptr_blits@sync-unmap:
- shard-glk: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-glk9/igt@gem_userptr_bl...@sync-unmap.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-glk6/igt@gem_userptr_bl...@sync-unmap.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#109385] /
[fdo#111870]) +1 similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-apl3/igt@gem_userptr_bl...@sync-unmap-cycles.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-apl4/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14643/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +2
similar issues
[21]:
[Intel-gfx] [PULL] drm-misc-fixes
Hi, Here is another attempt at a PR for drm-misc-fixes, after the attempt I did yesterday. Maxime drm-misc-fixes-2019-10-03: - One include fix for tilcdc - A clock fix for OMAP - A memory leak fix for Komeda - Some fixes for resources cleanups with writeback The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2019-10-03 for you to fetch changes up to b6559bf3ac32acfe34e17c73d68581e7f7415785: Merge drm-misc-next-fixes-2019-10-02 into drm-misc-fixes (2019-10-03 10:00:13 +0200) - One include fix for tilcdc - A clock fix for OMAP - A memory leak fix for Komeda - Some fixes for resources cleanups with writeback Arnd Bergmann (1): drm/tilcdc: include linux/pinctrl/consumer.h again Lowry Li (Arm Technology China) (2): drm: Free the writeback_job when it with an empty fb drm: Clear the fence pointer when writeback job signaled Maxime Ripard (2): Merge drm/drm-fixes into drm-misc-fixes Merge drm-misc-next-fixes-2019-10-02 into drm-misc-fixes Navid Emamdoost (1): drm/komeda: prevent memory leak in komeda_wb_connector_add Tomi Valkeinen (1): drm/omap: fix max fclk divider for omap36xx .../drm/arm/display/komeda/komeda_wb_connector.c | 7 --- drivers/gpu/drm/arm/malidp_mw.c| 4 ++-- drivers/gpu/drm/drm_atomic.c | 13 drivers/gpu/drm/drm_writeback.c| 23 ++ drivers/gpu/drm/omapdrm/dss/dss.c | 2 +- drivers/gpu/drm/rcar-du/rcar_du_writeback.c| 4 ++-- drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 1 + drivers/gpu/drm/vc4/vc4_txp.c | 5 ++--- 8 files changed, 36 insertions(+), 23 deletions(-) signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add Sphinx-compatible references to struct fields
This fixes the following kernel-doc warnings and makes the corrsponding fields
show up in the generated HTML:
./drivers/gpu/drm/i915/i915_drv.h:1143: warning: Incorrect use of kernel-doc
format: * State of the OA buffer.
./drivers/gpu/drm/i915/i915_drv.h:1154: warning: Incorrect use of kernel-doc
format: * Locks reads and writes to all head/tail state
./drivers/gpu/drm/i915/i915_drv.h:1176: warning: Incorrect use of kernel-doc
format: * One 'aging' tail pointer and one 'aged' tail pointer
ready to
./drivers/gpu/drm/i915/i915_drv.h:1188: warning: Incorrect use of kernel-doc
format: * Index for the aged tail ready to read() data up to.
./drivers/gpu/drm/i915/i915_drv.h:1193: warning: Incorrect use of kernel-doc
format: * A monotonic timestamp for when the current aging
tail pointer
./drivers/gpu/drm/i915/i915_drv.h:1199: warning: Incorrect use of kernel-doc
format: * Although we can always read back the head pointer
register,
Signed-off-by: Jonathan Neuschäfer
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 772154e4073e..55782e78f026 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1140,7 +1140,7 @@ struct i915_perf_stream {
int period_exponent;
/**
-* State of the OA buffer.
+* @oa_buffer: State of the OA buffer.
*/
struct {
struct i915_vma *vma;
@@ -1151,6 +1151,7 @@ struct i915_perf_stream {
int size_exponent;
/**
+* @oa_buffer.ptr_lock:
* Locks reads and writes to all head/tail state
*
* Consider: the head and tail pointer state needs to be read
@@ -1173,6 +1174,7 @@ struct i915_perf_stream {
spinlock_t ptr_lock;
/**
+* @oa_buffer.tails:
* One 'aging' tail pointer and one 'aged' tail pointer ready to
* used for reading.
*
@@ -1185,17 +1187,20 @@ struct i915_perf_stream {
} tails[2];
/**
+* @oa_buffer.aged_tail_idx:
* Index for the aged tail ready to read() data up to.
*/
unsigned int aged_tail_idx;
/**
+* @oa_buffer.aging_timestamp:
* A monotonic timestamp for when the current aging tail pointer
* was read; used to determine when it is old enough to trust.
*/
u64 aging_timestamp;
/**
+* @oa_buffer.head:
* Although we can always read back the head pointer register,
* we prefer to avoid trusting the HW state, just to avoid any
* risk that some hardware condition could * somehow bump the
--
2.20.1
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Re: [Intel-gfx] [PATCH V6] drm/drm_vblank: Change EINVAL by the correct errno
On Wed, 2 Oct 2019 11:05:16 -0300 Rodrigo Siqueira wrote: > For historical reasons, the function drm_wait_vblank_ioctl always return > -EINVAL if something gets wrong. This scenario limits the flexibility > for the userspace to make detailed verification of any problem and take > some action. In particular, the validation of “if (!dev->irq_enabled)” > in the drm_wait_vblank_ioctl is responsible for checking if the driver > support vblank or not. If the driver does not support VBlank, the > function drm_wait_vblank_ioctl returns EINVAL, which does not represent > the real issue; this patch changes this behavior by return EOPNOTSUPP. > Additionally, drm_crtc_get_sequence_ioctl and > drm_crtc_queue_sequence_ioctl, also returns EINVAL if vblank is not > supported; this patch also changes the return value to EOPNOTSUPP in > these functions. Lastly, these functions are invoked by libdrm, which is > used by many compositors; because of this, it is important to check if > this change breaks any compositor. In this sense, the following projects > were examined: > > * Drm-hwcomposer > * Kwin > * Sway > * Wlroots > * Wayland > * Weston > * Mutter > * Xorg (67 different drivers) > > For each repository the verification happened in three steps: > > * Update the main branch > * Look for any occurrence of "drmCrtcQueueSequence", > "drmCrtcGetSequence", and "drmWaitVBlank" with the command git grep -n > "STRING". > * Look in the git history of the project with the command > git log -S > > None of the above projects validate the use of EINVAL when using > drmWaitVBlank(), which make safe, at least for these projects, to change > the return values. On the other hand, mesa and xserver project uses > drmCrtcQueueSequence() and drmCrtcGetSequence(); this change is harmless > for both projects. > > Change since V5 (Pekka Paalanen): > - Check if the change also affects Mutter > > Change since V4 (Daniel): > - Also return EOPNOTSUPP in drm_crtc_[get|queue]_sequence_ioctl > > Change since V3: > - Return EINVAL for _DRM_VBLANK_SIGNAL (Daniel) > > Change since V2: > Daniel Vetter and Chris Wilson > - Replace ENOTTY by EOPNOTSUPP > - Return EINVAL if the parameters are wrong > > Cc: Keith Packard > Cc: Maarten Lankhorst > Cc: Ville Syrjälä > Cc: Chris Wilson > Cc: Daniel Vetter > Cc: Pekka Paalanen > Signed-off-by: Rodrigo Siqueira > --- > drivers/gpu/drm/drm_vblank.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c > index 9c6899758bc9..71cf2633ac58 100644 > --- a/drivers/gpu/drm/drm_vblank.c > +++ b/drivers/gpu/drm/drm_vblank.c > @@ -1610,7 +1610,7 @@ int drm_wait_vblank_ioctl(struct drm_device *dev, void > *data, > unsigned int flags, pipe, high_pipe; > > if (!dev->irq_enabled) > - return -EINVAL; > + return -EOPNOTSUPP; > > if (vblwait->request.type & _DRM_VBLANK_SIGNAL) > return -EINVAL; Hi, this part looks safe for Weston indeed, so this part: Acked-by: Pekka Paalanen There is no need to check the "Wayland" project, it will never do anything with DRM. (What looks extremely suspicious though is the libdrm implementation of drmWaitVblank() in case the ioctl returns EINTR, but that's unrelated.) Thanks, pq pgpMz5NmS9VSs.pgp Description: OpenPGP digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] drm-misc-fixes
Hi, On Wed, Oct 02, 2019 at 10:06:04PM +0200, Maxime Ripard wrote: > Hi Dave, Daniel, > > I hope that you enjoy XDC if you could make it this year :) > > Here's the first round of fixes for drm-misc > > Maxime > > drm-misc-fixes-2019-10-02: > - One include fix for tilcdc > - A memory leak fix for Komeda > - Some fixes for resources cleanups with writeback So it turns out that while that tag was pushed, I forgot to push the branch first, and now we have a conflict. Let's drop this PR, I'll do another one. Maxime signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling) (rev9)
== Series Details == Series: series starting with [v3] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling) (rev9) URL : https://patchwork.freedesktop.org/series/67529/ State : success == Summary == CI Bug Log - changes from CI_DRM_6998 -> Patchwork_14652 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/index.html Known issues Here are the changes found in Patchwork_14652 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-snb-2600:[PASS][1] -> [DMESG-WARN][2] ([fdo#102365]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html Possible fixes * igt@gem_exec_gttfill@basic: - fi-apl-guc: [DMESG-WARN][3] ([fdo#109385] / [fdo#111652 ]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-apl-guc/igt@gem_exec_gttf...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/fi-apl-guc/igt@gem_exec_gttf...@basic.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [FAIL][5] ([fdo#109483]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365 [fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#111652 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111652 Participating hosts (51 -> 42) -- Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-pnv-d510 fi-icl-y fi-bsw-kefka fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6998 -> Patchwork_14652 CI-20190529: 20190529 CI_DRM_6998: fd44976bff7ae3cdf72245ac33d92d2186e57e9b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5210: 74f55119f9920b65996535210a09147997804136 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14652: 1751db2acb703d3cb5b08640142d85b64ae3fa24 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1751db2acb70 drm/i915: Drop struct_mutex from around GEM initialisation 5453664ed056 drm/i915/selftests: Drop vestigal struct_mutex guards e99a32f6517f drm/i915: Drop struct_mutex from suspend state save/restore 5c3fcc75fb6d drm/i915: Remove struct_mutex guard for debugfs/opregion ea6f30bd5c40 drm/i915: Drop struct_mutex guard from debugfs/framebuffer_info f8cbd175469f drm/i915/overlay: Drop struct_mutex guard 380def66354c drm/i915: Move context management under GEM f5f264a161d1 drm/i915: Remove logical HW ID 68f2e26a9e9d drm/i915: Move global activity tracking from GEM to GT 171ae0156aa8 drm/i915: Move request runtime management onto gt c55fc6046ccb drm/i915/gem: Retire directly for mmap-offset shrinking d82b5ebf7f9a drm/i915: Merge wait_for_timelines with retire_request 3c5819a7483e drm/i915: Remove the GEM idle worker 15a26e4acbdd drm/i915: Drop struct_mutex from around i915_retire_requests() 63ad1da00046 drm/i915: Move idle barrier cleanup into engine-pm d3abaae7a5d5 drm/i915: Coordinate i915_active with its own mutex baf28fe7b3d7 drm/i915: Push the i915_active.retire into a worker 66d1f961a834 drm/i915: Pull i915_vma_pin under the vm->mutex 0edbb84633d0 drm/i915: Mark up address spaces that may need to allocate 33df3a359fd0 drm/i915: Only track bound elements of the GTT 40e1178004ae drm/mm: Pack allocated/scanned boolean into a bitfield d8ea554e76ab dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14652/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Implement a better i945gm vblank irq vs. C-states workaround
== Series Details ==
Series: drm/i915: Implement a better i945gm vblank irq vs. C-states workaround
URL : https://patchwork.freedesktop.org/series/67541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6998 -> Patchwork_14651
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/index.html
Known issues
Here are the changes found in Patchwork_14651 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] ([fdo#107807])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-skl-6600u/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/fi-skl-6600u/igt@i915_pm_...@module-reload.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live_execlists:
- fi-bsw-kefka: [DMESG-FAIL][5] ([fdo#111895]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-bsw-kefka/igt@i915_selftest@live_execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/fi-bsw-kefka/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][7] ([fdo#109483]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6998/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111895]: https://bugs.freedesktop.org/show_bug.cgi?id=111895
Participating hosts (51 -> 43)
--
Additional (1): fi-kbl-soraka
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3
fi-icl-y fi-blb-e6850 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6998 -> Patchwork_14651
CI-20190529: 20190529
CI_DRM_6998: fd44976bff7ae3cdf72245ac33d92d2186e57e9b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5210: 74f55119f9920b65996535210a09147997804136 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14651: 7e3c560176a1e65252615e5128447d29e15c351a @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7e3c560176a1 drm/i915: Implement a better i945gm vblank irq vs. C-states
workaround
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14651/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling) (rev9)
== Series Details ==
Series: series starting with [v3] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling) (rev9)
URL : https://patchwork.freedesktop.org/series/67529/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d8ea554e76ab dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 0fc89b6802ba ("dma-fence: Simply
wrap dma_fence_signal_locked with dma_fence_signal")'
#14:
See also 0fc89b6802ba ("dma-fence: Simply wrap dma_fence_signal_locked
total: 1 errors, 0 warnings, 0 checks, 120 lines checked
40e1178004ae drm/mm: Pack allocated/scanned boolean into a bitfield
33df3a359fd0 drm/i915: Only track bound elements of the GTT
0edbb84633d0 drm/i915: Mark up address spaces that may need to allocate
66d1f961a834 drm/i915: Pull i915_vma_pin under the vm->mutex
baf28fe7b3d7 drm/i915: Push the i915_active.retire into a worker
d3abaae7a5d5 drm/i915: Coordinate i915_active with its own mutex
-:1340: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#1340: FILE: drivers/gpu/drm/i915/i915_active_types.h:49:
+ struct mutex mutex;
total: 0 errors, 0 warnings, 1 checks, 1481 lines checked
63ad1da00046 drm/i915: Move idle barrier cleanup into engine-pm
15a26e4acbdd drm/i915: Drop struct_mutex from around i915_retire_requests()
3c5819a7483e drm/i915: Remove the GEM idle worker
d82b5ebf7f9a drm/i915: Merge wait_for_timelines with retire_request
c55fc6046ccb drm/i915/gem: Retire directly for mmap-offset shrinking
171ae0156aa8 drm/i915: Move request runtime management onto gt
-:236: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#236:
new file mode 100644
-:241: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#241: FILE: drivers/gpu/drm/i915/gt/intel_gt_requests.c:1:
+/*
-:242: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#242: FILE: drivers/gpu/drm/i915/gt/intel_gt_requests.c:2:
+ * SPDX-License-Identifier: MIT
-:370: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#370: FILE: drivers/gpu/drm/i915/gt/intel_gt_requests.h:1:
+/*
-:371: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#371: FILE: drivers/gpu/drm/i915/gt/intel_gt_requests.h:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 5 warnings, 0 checks, 725 lines checked
68f2e26a9e9d drm/i915: Move global activity tracking from GEM to GT
f5f264a161d1 drm/i915: Remove logical HW ID
380def66354c drm/i915: Move context management under GEM
-:1348: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#1348: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:985:
+#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
^
total: 0 errors, 0 warnings, 1 checks, 2142 lines checked
f8cbd175469f drm/i915/overlay: Drop struct_mutex guard
ea6f30bd5c40 drm/i915: Drop struct_mutex guard from debugfs/framebuffer_info
5c3fcc75fb6d drm/i915: Remove struct_mutex guard for debugfs/opregion
e99a32f6517f drm/i915: Drop struct_mutex from suspend state save/restore
5453664ed056 drm/i915/selftests: Drop vestigal struct_mutex guards
1751db2acb70 drm/i915: Drop struct_mutex from around GEM initialisation
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for DC3CO Support for TGL test with DC3CO IGT
== Series Details ==
Series: DC3CO Support for TGL test with DC3CO IGT
URL : https://patchwork.freedesktop.org/series/67525/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6996_full -> Patchwork_14642_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14642_full:
### IGT changes ###
Possible regressions
* {igt@i915_pm_dc@dc3co-vpb-simulation} (NEW):
- shard-iclb: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-iclb8/igt@i915_pm...@dc3co-vpb-simulation.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_edge_walk@pipe-a-128x128-bottom-edge:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-tglb4/igt@kms_cursor_edge_w...@pipe-a-128x128-bottom-edge.html
New tests
-
New tests have been introduced between CI_DRM_6996_full and
Patchwork_14642_full:
### New IGT tests (1) ###
* igt@i915_pm_dc@dc3co-vpb-simulation:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_14642_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@bcs0-s3:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#109100])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb1/igt@gem_ctx_isolat...@bcs0-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-iclb1/igt@gem_ctx_isolat...@bcs0-s3.html
* igt@gem_eio@unwedge-stress:
- shard-apl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-apl1/igt@gem_...@unwedge-stress.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-apl6/igt@gem_...@unwedge-stress.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +21 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb2/igt@gem_exec_sched...@independent-bsd2.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-iclb7/igt@gem_exec_sched...@independent-bsd2.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +3 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-snb7/igt@gem_userptr_bl...@dmabuf-sync.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-hsw6/igt@gem_userptr_bl...@sync-unmap-after-close.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-hsw1/igt@gem_userptr_bl...@sync-unmap-after-close.html
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-skl5/igt@gem_userptr_bl...@sync-unmap-after-close.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-skl1/igt@gem_userptr_bl...@sync-unmap-after-close.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#109385] /
[fdo#111870]) +1 similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-apl3/igt@gem_userptr_bl...@sync-unmap-cycles.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-apl6/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +5
similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6996/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14642/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#103232])
[21]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Skip redundant resubmission
== Series Details == Series: drm/i915/execlists: Skip redundant resubmission URL : https://patchwork.freedesktop.org/series/67537/ State : success == Summary == CI Bug Log - changes from CI_DRM_6997 -> Patchwork_14650 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/index.html Known issues Here are the changes found in Patchwork_14650 that come from known issues: ### IGT changes ### Issues hit * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][1] -> [DMESG-WARN][2] ([fdo#102614]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@i915_selftest@live_gtt: - fi-glk-dsi: [DMESG-FAIL][3] -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/fi-glk-dsi/igt@i915_selftest@live_gtt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/fi-glk-dsi/igt@i915_selftest@live_gtt.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][5] ([fdo#103167]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 Participating hosts (49 -> 44) -- Additional (1): fi-snb-2600 Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6997 -> Patchwork_14650 CI-20190529: 20190529 CI_DRM_6997: 428a87c2d4a199a35dc4bd8ac0f10d4c29dd6b43 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5210: 74f55119f9920b65996535210a09147997804136 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14650: 2de391d25a07380e6dd6d3076447a22d82a1fcb0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2de391d25a07 drm/i915/execlists: Skip redundant resubmission == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14650/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/6] drm/i915/mst: Document the userspace fail with possible_crtcs
On Wed, Oct 02, 2019 at 07:25:05PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > To avoid accidentally breaking things in the future add a > comment explaining why we misconfigure the pipe_mask. > > Also toss in a TODO for investigating a single encoder > approach as opposed to the encoder-per-pipe approach. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 12 > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 7be82cf926ca..cb3047fe2d02 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -615,6 +615,18 @@ intel_dp_create_fake_mst_encoder(struct > intel_digital_port *intel_dig_port, enum > intel_encoder->power_domain = intel_dig_port->base.power_domain; > intel_encoder->port = intel_dig_port->base.port; > intel_encoder->cloneable = 0; > + /* > + * This is wrong, but broken userspace uses the intersection > + * of possible_crtcs of all the encoders of a given connector > + * to figure out which crtcs can drive said connector. What > + * should be used instead is the union of possible_crtcs. > + * To keep such userspace functioning we must misconfigure > + * this to make sure the intersection is not empty :( > + * > + * TODO: figure out if we could eliminate the per-pipe > + * encoders here and just have a single encoder for each > + * MST connector. That would sidestep the userspace bug. That of course won't work since we can't register encoders dynamically. I guess we'll just have to live with this slight discrepancy with the possible_crtcs. We could make the encoder<->pipe assignment totally flexible but that wouldn't actually change anything. We still get to pick one based on whatever reason we can think of, and using the pipe for that seems as good a reason as any. What we could try to remove is having separate MST encoders for each DDI port. But that would make encoder->port not work for MST again. So defintiely has downsides, and doens't do anything for the possible_crtcs thing. Bah. I'll just drop the TODO. > + */ > intel_encoder->pipe_mask = ~0; > > intel_encoder->compute_config = intel_dp_mst_compute_config; > -- > 2.21.0 -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915_hangman: Force error capture
For fast preempt-resets, error capture is skipped, so disable
preempt-resets before checking the error state. While thinking ahead, be
prepared for when the modparams are not accessible.
Signed-off-by: Chris Wilson
---
lib/igt_gt.c | 7 ---
tests/i915/i915_hangman.c | 7 ---
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 78e3cd089..5ca77471c 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -162,6 +162,7 @@ igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned
flags)
struct drm_i915_gem_context_param param = {
.ctx_id = ctx,
};
+ int allow_reset;
unsigned ban;
/*
@@ -177,9 +178,7 @@ igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned
flags)
if (!igt_check_boolean_env_var("IGT_HANG_WITHOUT_RESET", false))
igt_require(has_gpu_reset(fd));
- igt_require(igt_sysfs_set_parameter
- (fd, "reset", "%d", INT_MAX /* any reset method */));
-
+ allow_reset = 1;
if ((flags & HANG_ALLOW_CAPTURE) == 0) {
param.param = I915_CONTEXT_PARAM_NO_ERROR_CAPTURE;
param.value = 1;
@@ -188,7 +187,9 @@ igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned
flags)
* the right one).
*/
__gem_context_set_param(fd, );
+ allow_reset = INT_MAX; /* any reset method */
}
+ igt_require(igt_sysfs_set_parameter(fd, "reset", "%d", allow_reset));
ban = context_get_ban(fd, ctx);
if ((flags & HANG_ALLOW_BAN) == 0)
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 58141fc92..7a158d8db 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -140,12 +140,13 @@ static void check_error_state(const char
*expected_ring_name,
size_t line_size = 0;
bool found = false;
- igt_debug("%s(expected ring name=%s, expected offset=%"PRIx64")\n",
- __func__, expected_ring_name, expected_offset);
igt_debugfs_dump(device, "i915_error_state");
igt_assert(getline(, _size, file) != -1);
- igt_assert(strcasecmp(line, "No error state collected"));
+ igt_require(strcasecmp(line, "No error state collected"));
+
+ igt_debug("%s(expected ring name=%s, expected offset=%"PRIx64")\n",
+ __func__, expected_ring_name, expected_offset);
while (getline(, _size, file) > 0) {
char *dashes;
--
2.23.0
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[Intel-gfx] [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test.
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 29 +++
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 976669f01a8c..5d6d44fa2594 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1142,6 +1142,7 @@ struct intel_dp_compliance_data {
u8 video_pattern;
u16 hdisplay, vdisplay;
u8 bpc;
+ struct drm_dp_phy_test_params phytest;
};
struct intel_dp_compliance {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7d33e20dfc87..a19141fc672e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4738,9 +4738,38 @@ static u8 intel_dp_autotest_edid(struct intel_dp
*intel_dp)
return test_result;
}
+static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
+{
+ struct drm_dp_phy_test_params *data =
+ _dp->compliance.test_data.phytest;
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ if (!drm_dp_get_phy_test_pattern(_dp->aux, data)) {
+ DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+ return DP_TEST_NAK;
+ }
+
+ if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ DRM_DEBUG_KMS("failed to get link status\n");
+ return DP_TEST_NAK;
+ }
+
+ intel_dp->link_mst = false;
+
+ /* retrieve vswing & pre-emphasis setting */
+ intel_get_adjust_train(intel_dp, link_status);
+
+ return DP_TEST_ACK;
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
+
+ test_result = intel_dp_prepare_phytest(intel_dp);
+ if (test_result != DP_TEST_ACK)
+ DRM_ERROR("Phy test preparation failed\n");
+
return test_result;
}
--
2.22.0
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[Intel-gfx] [RFC 1/6] drm/dp: get/set phy compliance pattern.
During phy complaince auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/drm_dp_helper.c | 77 +
include/drm/drm_dp_helper.h | 28
2 files changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f373798d82f6..3cb7170e55f4 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1484,3 +1484,80 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+/**
+ * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data)
+{
+ int err;
+
+ err = drm_dp_link_probe(aux, >link);
+ if (err < 0)
+ return err;
+
+ err = drm_dp_dpcd_read(aux, DP_TEST_PHY_PATTERN, >phy_pattern, 1);
+ if (err < 0)
+ return err;
+
+ switch (data->phy_pattern) {
+ case DP_TEST_PHY_PATTERN_80BIT_CUSTOM:
+ err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
+ >custom80, 10);
+ if (err < 0)
+ return err;
+
+ break;
+ case DP_TEST_PHY_PATTERN_CP2520:
+ err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
+ >hbr2_reset, 2);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
+
+/**
+ * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
+ * @aux: DisplayPort AUX channel
+ * @data: DP phy compliance test parameters.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data)
+{
+ int err, i;
+ u8 test_pattern;
+
+ err = drm_dp_link_configure(aux, >link);
+ if (err < 0)
+ return err;
+
+ test_pattern = data->phy_pattern;
+ if (data->link.revision < 0x12) {
+ test_pattern = (test_pattern << 2) &
+ DP_LINK_QUAL_PATTERN_11_MASK;
+ err = drm_dp_dpcd_write(aux, DP_TRAINING_PATTERN_SET,
+ _pattern, 1);
+ if (err < 0)
+ return err;
+ } else {
+ for (i = 0; i < data->link.num_lanes; i++) {
+ err = drm_dp_dpcd_write(aux, DP_LINK_QUAL_LANE0_SET + i,
+ _pattern, 1);
+ if (err < 0)
+ return err;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index ed1a985745ba..77dcf5879beb 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -691,6 +691,14 @@
# define DP_TEST_COUNT_MASK0xf
#define DP_TEST_PHY_PATTERN 0x248
+# define DP_TEST_PHY_PATTERN_NONE 0
+# define DP_TEST_PHY_PATTERN_D10_2 1
+# define DP_TEST_PHY_PATTERN_ERROR_COUNT2
+# define DP_TEST_PHY_PATTERN_PRBS7 3
+# define DP_TEST_PHY_PATTERN_80BIT_CUSTOM 4
+# define DP_TEST_PHY_PATTERN_CP2520 5
+
+#define DP_TEST_HBR2_SCRAMBLER_RESET0x24A
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250
#defineDP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
#defineDP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
@@ -1523,4 +1531,24 @@ static inline void drm_dp_cec_unset_edid(struct
drm_dp_aux *aux)
#endif
+/**
+ * struct drm_dp_phy_test_params - DP Phy Compliance parameters
+ * @link: Link information.
+ * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
+ * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
+ *0x24A and 0x24B (sink)
+ * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
+ * through 0x259.
+ */
+struct drm_dp_phy_test_params {
+ struct drm_dp_link link;
+ u8 phy_pattern;
+ u8 hbr2_reset[2];
+ u8 custom80[10];
+};
+
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data);
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
+ struct drm_dp_phy_test_params *data);
#endif /*
[Intel-gfx] [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.
No functional change.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 +++
drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
.../drm/i915/display/intel_dp_link_training.c | 32 ---
3 files changed, 35 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1aa39e92f0df..7d33e20dfc87 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4026,6 +4026,38 @@ ivb_cpu_edp_signal_levels(u8 train_set)
}
}
+void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 *link_status)
+{
+ u8 v = 0;
+ u8 p = 0;
+ int lane;
+ u8 voltage_max;
+ u8 preemph_max;
+
+ for (lane = 0; lane < intel_dp->lane_count; lane++) {
+ u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
lane);
+ u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
lane);
+
+ if (this_v > v)
+ v = this_v;
+ if (this_p > p)
+ p = this_p;
+ }
+
+ voltage_max = intel_dp_voltage_max(intel_dp);
+ if (v >= voltage_max)
+ v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+ preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+ if (p >= preemph_max)
+ p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+ for (lane = 0; lane < 4; lane++)
+ intel_dp->train_set[lane] = v | p;
+}
+
void
intel_dp_set_signal_levels(struct intel_dp *intel_dp)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index a194b5b6da05..8f8333afd43d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -91,6 +91,9 @@ void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
u8 dp_train_pat);
void
+intel_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 *link_status);
+void
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..1e38584e7d56 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8
link_status[DP_LINK_STATUS_SIZE])
link_status[3], link_status[4], link_status[5]);
}
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
- const u8 link_status[DP_LINK_STATUS_SIZE])
-{
- u8 v = 0;
- u8 p = 0;
- int lane;
- u8 voltage_max;
- u8 preemph_max;
-
- for (lane = 0; lane < intel_dp->lane_count; lane++) {
- u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
lane);
- u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
lane);
-
- if (this_v > v)
- v = this_v;
- if (this_p > p)
- p = this_p;
- }
-
- voltage_max = intel_dp_voltage_max(intel_dp);
- if (v >= voltage_max)
- v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
-
- preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
- if (p >= preemph_max)
- p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
- for (lane = 0; lane < 4; lane++)
- intel_dp->train_set[lane] = v | p;
-}
-
static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
u8 dp_train_pat)
--
2.22.0
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[Intel-gfx] [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 62 +
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 93b1ce80c174..dd4c3a81c11d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4817,14 +4817,76 @@ static inline void intel_dp_phy_pattern_update(struct
intel_dp *intel_dp)
}
}
+static void
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum port port = intel_dig_port->base.port;
+ u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+ ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+ dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
+ trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+ ddi_buf_ctl_value&= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
+ dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
+ trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
+ DDI_PORT_WIDTH_MASK);
+
+ I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+ I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
+ I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+}
+
+static void
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum port port = intel_dig_port->base.port;
+ u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+
+ ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
+ dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
+ trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+
+ ddi_buf_ctl_value|= DDI_BUF_CTL_ENABLE |
+ DDI_PORT_WIDTH(lane_cnt);
+ dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
+ trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
+ DDI_PORT_WIDTH(lane_cnt);
+
+ I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+ I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
+ I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
+ struct drm_dp_phy_test_params *data =
+ _dp->compliance.test_data.phytest;
test_result = intel_dp_prepare_phytest(intel_dp);
if (test_result != DP_TEST_ACK)
DRM_ERROR("Phy test preparation failed\n");
+ intel_dp_autotest_phy_ddi_disable(intel_dp);
+
+ intel_dp_set_signal_levels(intel_dp);
+
+ intel_dp_phy_pattern_update(intel_dp);
+
+ intel_dp_autotest_phy_ddi_enable(intel_dp, data->link.num_lanes);
+
+ drm_dp_set_phy_test_pattern(_dp->aux, data);
+
+ /* Set test active flag here so userspace doesn't interrupt things */
+ intel_dp->compliance.test_active = 1;
+
return test_result;
}
--
2.22.0
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[Intel-gfx] [RFC 4/6] drm/i915/dp: Register definition for DP compliance register.
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eefd789b9a28..38dacfddbd42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9621,6 +9621,26 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE(1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A,
_DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define DDI_DP_COMP_CTL_A 0x605f0
+#define DDI_DP_COMP_CTL_B 0x615f0
+#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
+DDI_DP_COMP_CTL_B)
+#define DDI_DP_COMP_CTL_ENABLE(1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET(0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define DDI_DP_COMP_PAT_A 0x605f4
+#define DDI_DP_COMP_PAT_B 0x615f4
+#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
+DDI_DP_COMP_PAT_B) + (i) * 4)
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
2.22.0
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[Intel-gfx] [RFC 5/6] drm/i915/dp: Update the pattern as per request.
set pattern in DP_COMP_CTL.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a19141fc672e..93b1ce80c174 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4762,6 +4762,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp
*intel_dp)
return DP_TEST_ACK;
}
+static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_dp_phy_test_params *data =
+ _dp->compliance.test_data.phytest;
+ u32 temp;
+
+ switch (data->phy_pattern) {
+ case DP_TEST_PHY_PATTERN_NONE:
+ DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0);
+ break;
+ case DP_TEST_PHY_PATTERN_D10_2:
+ DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
+ break;
+ case DP_TEST_PHY_PATTERN_ERROR_COUNT:
+ DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE |
+ DDI_DP_COMP_CTL_SCRAMBLED_0);
+ break;
+ case DP_TEST_PHY_PATTERN_PRBS7:
+ DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
+ break;
+ case DP_TEST_PHY_PATTERN_80BIT_CUSTOM:
+ DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n");
+ temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) |
+ (data->custom80[2] << 8) | (data->custom80[3]));
+ I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp);
+ temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) |
+ (data->custom80[6] << 8) | (data->custom80[7]));
+ I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp);
+ temp = ((data->custom80[8] << 8) | data->custom80[9]);
+ I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp);
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80);
+ break;
+ case DP_TEST_PHY_PATTERN_CP2520:
+ DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
+ temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]);
+ I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
+ DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
+ temp);
+ break;
+ default:
+ DRM_ERROR("Invalid Phy Test PAttern\n");
+ }
+}
+
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
{
u8 test_result = DP_TEST_NAK;
--
2.22.0
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[Intel-gfx] [RFC 0/6] DP Phy compliace auto test.
Driver changes mainly to process the request coming from Test equipment as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis Complete auto test suite takes much lesser time than manual run. Overall design: -- Automate test request will come to source device as HDP short pulse interrupt from test scope. Read DPCD 0x201, Check for bit 1 for automated test request. If set continue and read DPCD 0x218. Check for bit 3 for phy test pattern, If set continue. Get the requested test pattern through DPCD 0x248. Compute requested voltage swing level and pre-emphasis level from DPCD 0x206 and 0x207 Set signal level through vswing programming sequence. Write DDI_COMP_CTL and DDI_COMP_PATx as per requested pattern. Configure the link and write the new test pattern through DPCD. High level patch description. - patch 1: drm level api added to get/set test pattern as per vesa DP spec. This maybe useful for other driver so added in drm layer. patch 2: vswing/preemphasis adjustment calculation is needed during phy compliance request processing along with existing link training process, so moved the same function in intel_dp.c. patch 3: Parse the test scope request regarding test rquested pattern, vswing level, preemphasis level. patch 4: Register difnition of DP compliance register added. patch 5: Funcion added to update the pattern in source side. patch 6: This patch os mainly processing the request. Currently through prototyping patch able to run DP compliance where vswing, preemphasis and test pattern is changing fine but complete test is under process. In parallel want to start design discussion so sending the above patches as RFC. Animesh Manna (6): drm/dp: get/set phy compliance pattern. drm/i915/dp: Move vswing/pre-emphasis adjustment calculation drm/i915/dp: Preparation for DP phy compliance auto test. drm/i915/dp: Register definition for DP compliance register. drm/i915/dp: Update the pattern as per request. drm/i915/dp: Program vswing, pre-emphasis, test-pattern drivers/gpu/drm/drm_dp_helper.c | 77 .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 178 ++ drivers/gpu/drm/i915/display/intel_dp.h | 3 + .../drm/i915/display/intel_dp_link_training.c | 32 drivers/gpu/drm/i915/i915_reg.h | 20 ++ include/drm/drm_dp_helper.h | 28 +++ 7 files changed, 307 insertions(+), 32 deletions(-) -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/tc: Implement the TC cold exit sequence
On Mon, Sep 30, 2019 at 05:55:36PM -0700, José Roberto de Souza wrote:
> This is required for legacy/static TC ports as IOM is not aware of
> the connection and will not trigger the TC cold exit.
>
> BSpec: 21750
> BSpsc: 49294
> Cc: Imre Deak
> Cc: Lucas De Marchi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 34 -
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 7773169b7331..09b78027bdd5 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -7,6 +7,7 @@
> #include "intel_display.h"
> #include "intel_display_types.h"
> #include "intel_dp_mst.h"
> +#include "intel_sideband.h"
> #include "intel_tc.h"
>
> static const char *tc_port_mode_name(enum tc_port_mode mode)
> @@ -169,6 +170,22 @@ static void tc_port_fixup_legacy_flag(struct
> intel_digital_port *dig_port,
> dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
> }
>
> +static int tc_cold_exit_request(struct drm_i915_private *dev_priv)
> +{
> + int ret;
> +
> + do {
> + ret = sandybridge_pcode_write_timeout(dev_priv,
> + ICL_PCODE_EXIT_TCCOLD, 0,
> + 250, 1);
> +
> + } while (ret == -EAGAIN);
> +
> + DRM_DEBUG_KMS("tccold exit %s\n", ret == 0 ? "succeeded" : "failed");
> +
> + return ret;
> +}
> +
> static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -177,13 +194,21 @@ static u32 tc_port_live_status_mask(struct
> intel_digital_port *dig_port)
> u32 mask = 0;
> u32 val;
>
> + if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
> + mask |= BIT(TC_PORT_LEGACY);
> +
> val = intel_uncore_read(uncore,
> PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>
> if (val == 0x) {
> - DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
> - dig_port->tc_port_name);
> - return mask;
> + if (mask)
> + tc_cold_exit_request(i915);
The semantic of the mbox command this needs is inherently racy on
systems with preemption, the instruction to use it is:
"""
Issue GT Driver mailbox command to exit TCCOLD, then complete steps b-d
within 500 milliseconds to prevent re-entry.
"""
We'd have to reach the point where we enable the AUX power in 500ms,
which can't be guaranteed. Moreover TCCOLD could be entered just after
reading PORT_TX_DFLEXDPSP, so we may not detect it.
What we can do - after discussing with HW folks - is to first request
AUX power and then issue the mbox command, which prevents TCCOLD
re-entry until releasing the AUX power request. This also needs ignoring
the timeout of the AUX power enabling ACK, since it will only be ACKed
after exiting TCCOLD.
So I think we should block TCCOLD this way in __intel_tc_port_lock():
if tc_link_refcount==0:
intel_display_power_get(POWER_DOMAIN_AUX_)
tc_cold_exit_request()
if intel_tc_port_needs_reset():
intel_tc_port_reset_mode()
if tc_mode != LEGACY:
intel_display_power_put(POWER_DOMAIN_AUX_)
then unblock TCCOLD in intel_tc_port_unlock():
if tc_link_refcount==0 and tc_mode == LEGACY:
intel_display_power_put(POWER_DOMAIN_AUX_)
> +
> + if (val == 0x) {
> + DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing
> connected\n",
> + dig_port->tc_port_name);
> + return mask;
> + }
> }
>
> if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx))
> @@ -191,9 +216,6 @@ static u32 tc_port_live_status_mask(struct
> intel_digital_port *dig_port)
> if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
> mask |= BIT(TC_PORT_DP_ALT);
>
> - if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
> - mask |= BIT(TC_PORT_LEGACY);
> -
> /* The sink can be connected only in a single mode. */
> if (!WARN_ON(hweight32(mask) > 1))
> tc_port_fixup_legacy_flag(dig_port, mask);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 058aa5ca8b73..35c3724b7fef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8860,6 +8860,7 @@ enum {
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) <<
> 16) | (0x1 << 8))
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add the Thunderbolt PLL divider values (rev3)
== Series Details ==
Series: drm/i915/tgl: Add the Thunderbolt PLL divider values (rev3)
URL : https://patchwork.freedesktop.org/series/67498/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6997 -> Patchwork_14649
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/index.html
Known issues
Here are the changes found in Patchwork_14649 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live_gtt:
- fi-glk-dsi: [DMESG-FAIL][1] -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/fi-glk-dsi/igt@i915_selftest@live_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/fi-glk-dsi/igt@i915_selftest@live_gtt.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][3] ([fdo#103167]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6997/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (49 -> 44)
--
Additional (2): fi-icl-u3 fi-snb-2600
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6997 -> Patchwork_14649
CI-20190529: 20190529
CI_DRM_6997: 428a87c2d4a199a35dc4bd8ac0f10d4c29dd6b43 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5210: 74f55119f9920b65996535210a09147997804136 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14649: 2a79d1c605b467bc1d2ac020a05980153dc28e25 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2a79d1c605b4 drm/i915/tgl: Add the Thunderbolt PLL divider values
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14649/index.html
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Re: [Intel-gfx] [PATCH v3] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)
On 03/10/2019 15:18, Chris Wilson wrote:
Quoting Ruhl, Michael J (2019-10-03 15:12:38)
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Chris Wilson
Sent: Thursday, October 3, 2019 9:24 AM
To: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
Make dma_fence_enable_sw_signaling() behave like its
dma_fence_add_callback() and dma_fence_default_wait() counterparts and
perform the test to enable signaling under the fence->lock, along with
the action to do so. This ensure that should an implementation be trying
to flush the cb_list (by signaling) on retirement before freeing the
fence, it can do so in a race-free manner.
See also 0fc89b6802ba ("dma-fence: Simply wrap dma_fence_signal_locked
with dma_fence_signal").
v2: Refactor all 3 enable_signaling paths to use a common function.
Signed-off-by: Chris Wilson
---
Return false for "could not _enable_ signaling as it was already
signaled"
---
drivers/dma-buf/dma-fence.c | 78 +
1 file changed, 35 insertions(+), 43 deletions(-)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 2c136aee3e79..b58528c1cc9d 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -273,6 +273,30 @@ void dma_fence_free(struct dma_fence *fence)
}
EXPORT_SYMBOL(dma_fence_free);
+static bool __dma_fence_enable_signaling(struct dma_fence *fence)
+{
+ bool was_set;
+
+ lockdep_assert_held(fence->lock);
With this held...
+ was_set =
test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
+ >flags);
+
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
+ return false;
Would making these the non-atomic versions be useful (and/or reasonable)?
That depends on all modifications to the dword (not just the bit) being
serialised by the same lock (or otherwise guaranteed to be serial and
coherent), which as Tvrtko rediscovered is not the case. dma_fence.flags
is also home to a number of user flags.
Michael, for completeness of the reference - I fell into the same trap -
https://patchwork.freedesktop.org/series/67532/. Check the results. :)
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH v3] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)
>-Original Message-
>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>Sent: Thursday, October 3, 2019 10:19 AM
>To: Ruhl, Michael J ; intel-
>g...@lists.freedesktop.org
>Cc: dri-de...@lists.freedesktop.org
>Subject: RE: [Intel-gfx] [PATCH v3] dma-fence: Serialise signal enabling
>(dma_fence_enable_sw_signaling)
>
>Quoting Ruhl, Michael J (2019-10-03 15:12:38)
>> >-Original Message-
>> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
>Of
>> >Chris Wilson
>> >Sent: Thursday, October 3, 2019 9:24 AM
>> >To: intel-gfx@lists.freedesktop.org
>> >Cc: dri-de...@lists.freedesktop.org
>> >Subject: [Intel-gfx] [PATCH v3] dma-fence: Serialise signal enabling
>> >(dma_fence_enable_sw_signaling)
>> >
>> >Make dma_fence_enable_sw_signaling() behave like its
>> >dma_fence_add_callback() and dma_fence_default_wait() counterparts
>and
>> >perform the test to enable signaling under the fence->lock, along with
>> >the action to do so. This ensure that should an implementation be trying
>> >to flush the cb_list (by signaling) on retirement before freeing the
>> >fence, it can do so in a race-free manner.
>> >
>> >See also 0fc89b6802ba ("dma-fence: Simply wrap
>dma_fence_signal_locked
>> >with dma_fence_signal").
>> >
>> >v2: Refactor all 3 enable_signaling paths to use a common function.
>> >
>> >Signed-off-by: Chris Wilson
>> >---
>> >Return false for "could not _enable_ signaling as it was already
>> >signaled"
>> >---
>> > drivers/dma-buf/dma-fence.c | 78 +
>> > 1 file changed, 35 insertions(+), 43 deletions(-)
>> >
>> >diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
>> >index 2c136aee3e79..b58528c1cc9d 100644
>> >--- a/drivers/dma-buf/dma-fence.c
>> >+++ b/drivers/dma-buf/dma-fence.c
>> >@@ -273,6 +273,30 @@ void dma_fence_free(struct dma_fence *fence)
>> > }
>> > EXPORT_SYMBOL(dma_fence_free);
>> >
>> >+static bool __dma_fence_enable_signaling(struct dma_fence *fence)
>> >+{
>> >+ bool was_set;
>> >+
>> >+ lockdep_assert_held(fence->lock);
>>
>> With this held...
>>
>> >+ was_set =
>> >test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
>> >+ >flags);
>> >+
>> >+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >flags))
>> >+ return false;
>>
>> Would making these the non-atomic versions be useful (and/or
>reasonable)?
>
>That depends on all modifications to the dword (not just the bit) being
>serialised by the same lock (or otherwise guaranteed to be serial and
>coherent), which as Tvrtko rediscovered is not the case. dma_fence.flags
>is also home to a number of user flags.
Ah got it.
In the future, I will think a bit outside the patch. (sorry for the pun...)
Thanks,
Mike
>-Chris
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