[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Flush any i915_active callback work as well
== Series Details == Series: drm/i915/selftests: Flush any i915_active callback work as well URL : https://patchwork.freedesktop.org/series/68487/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7167_full -> Patchwork_14958_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14958_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14958_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14958_full: ### IGT changes ### Possible regressions * igt@gem_ctx_shared@q-promotion-bsd1: - shard-apl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-apl2/igt@gem_ctx_sha...@q-promotion-bsd1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-apl1/igt@gem_ctx_sha...@q-promotion-bsd1.html * igt@gem_exec_parallel@fds: - shard-kbl: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl6/igt@gem_exec_paral...@fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-kbl4/igt@gem_exec_paral...@fds.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-skl: NOTRUN -> [FAIL][5] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-skl2/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html - shard-iclb: NOTRUN -> [FAIL][6] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-iclb7/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-contexts-render: - shard-skl: [PASS][7] -> [FAIL][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-skl9/igt@gem_exec_sched...@preempt-queue-contexts-render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-skl2/igt@gem_exec_sched...@preempt-queue-contexts-render.html Known issues Here are the changes found in Patchwork_14958_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276] / [fdo#112080]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb1/igt@gem_ctx_isolat...@vcs1-dirty-create.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#110854]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb2/igt@gem_exec_balan...@smoke.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112080]) +9 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb2/igt@gem_exec_paral...@vcs1-fds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-iclb3/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#111325]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb5/igt@gem_exec_sched...@preempt-bsd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-iclb1/igt@gem_exec_sched...@preempt-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd2: - shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl6/igt@gem_exec_sched...@preempt-queue-bsd2.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-kbl4/igt@gem_exec_sched...@preempt-queue-bsd2.html * igt@gem_mmap_gtt@hang: - shard-snb: [PASS][19] -> [INCOMPLETE][20] ([fdo#105411]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-snb7/igt@gem_mmap_...@hang.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-snb5/igt@gem_mmap_...@hang.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-kbl: [PASS][21] -> [FAIL][22] ([fdo#112037]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl2/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/shard-kbl6/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_ringfill@basic-default-hang: -
Re: [Intel-gfx] [PATCH V5 4/6] mdev: introduce virtio device and its device ops
On 2019/10/25 上午4:44, Alex Williamson wrote:
On Thu, 24 Oct 2019 11:51:35 +0800
Jason Wang wrote:
On 2019/10/24 上午5:57, Alex Williamson wrote:
On Wed, 23 Oct 2019 21:07:50 +0800
Jason Wang wrote:
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/mdev_core.c| 20
drivers/vfio/mdev/mdev_private.h | 2 +
include/linux/mdev.h | 6 ++
include/linux/virtio_mdev_ops.h | 159 +++
4 files changed, 187 insertions(+)
create mode 100644 include/linux/virtio_mdev_ops.h
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index 555bd61d8c38..9b00c3513120 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -76,6 +76,26 @@ const struct vfio_mdev_device_ops *mdev_get_vfio_ops(struct
mdev_device *mdev)
}
EXPORT_SYMBOL(mdev_get_vfio_ops);
+/* Specify the virtio device ops for the mdev device, this
+ * must be called during create() callback for virtio mdev device.
+ */
+void mdev_set_virtio_ops(struct mdev_device *mdev,
+const struct virtio_mdev_device_ops *virtio_ops)
+{
+ mdev_set_class(mdev, MDEV_CLASS_ID_VIRTIO);
+ mdev->virtio_ops = virtio_ops;
+}
+EXPORT_SYMBOL(mdev_set_virtio_ops);
+
+/* Get the virtio device ops for the mdev device. */
+const struct virtio_mdev_device_ops *
+mdev_get_virtio_ops(struct mdev_device *mdev)
+{
+ WARN_ON(mdev->class_id != MDEV_CLASS_ID_VIRTIO);
+ return mdev->virtio_ops;
+}
+EXPORT_SYMBOL(mdev_get_virtio_ops);
+
struct device *mdev_dev(struct mdev_device *mdev)
{
return >dev;
diff --git a/drivers/vfio/mdev/mdev_private.h b/drivers/vfio/mdev/mdev_private.h
index 0770410ded2a..7b47890c34e7 100644
--- a/drivers/vfio/mdev/mdev_private.h
+++ b/drivers/vfio/mdev/mdev_private.h
@@ -11,6 +11,7 @@
#define MDEV_PRIVATE_H
#include
+#include
int mdev_bus_register(void);
void mdev_bus_unregister(void);
@@ -38,6 +39,7 @@ struct mdev_device {
u16 class_id;
union {
const struct vfio_mdev_device_ops *vfio_ops;
+ const struct virtio_mdev_device_ops *virtio_ops;
};
};
diff --git a/include/linux/mdev.h b/include/linux/mdev.h
index 4625f1a11014..9b69b0bbebfd 100644
--- a/include/linux/mdev.h
+++ b/include/linux/mdev.h
@@ -17,6 +17,7 @@
struct mdev_device;
struct vfio_mdev_device_ops;
+struct virtio_mdev_device_ops;
/*
* Called by the parent device driver to set the device which represents
@@ -112,6 +113,10 @@ void mdev_set_class(struct mdev_device *mdev, u16 id);
void mdev_set_vfio_ops(struct mdev_device *mdev,
const struct vfio_mdev_device_ops *vfio_ops);
const struct vfio_mdev_device_ops *mdev_get_vfio_ops(struct mdev_device
*mdev);
+void mdev_set_virtio_ops(struct mdev_device *mdev,
+const struct virtio_mdev_device_ops *virtio_ops);
+const struct virtio_mdev_device_ops *
+mdev_get_virtio_ops(struct mdev_device *mdev);
extern struct bus_type mdev_bus_type;
@@ -127,6 +132,7 @@ struct mdev_device *mdev_from_dev(struct device *dev);
enum {
MDEV_CLASS_ID_VFIO = 1,
+ MDEV_CLASS_ID_VIRTIO = 2,
/* New entries must be added here */
};
diff --git a/include/linux/virtio_mdev_ops.h b/include/linux/virtio_mdev_ops.h
new file mode 100644
index ..d417b41f2845
--- /dev/null
+++ b/include/linux/virtio_mdev_ops.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Virtio mediated device driver
+ *
+ * Copyright 2019, Red Hat Corp.
+ * Author: Jason Wang
+ */
+#ifndef _LINUX_VIRTIO_MDEV_H
+#define _LINUX_VIRTIO_MDEV_H
+
+#include
+#include
+#include
+
+#define VIRTIO_MDEV_DEVICE_API_STRING "virtio-mdev"
+#define VIRTIO_MDEV_F_VERSION_1 0x1
+
+struct virtio_mdev_callback {
+ irqreturn_t (*callback)(void *data);
+ void *private;
+};
+
+/**
+ * struct vfio_mdev_device_ops - Structure to be registered for each
+ * mdev device to register the device for virtio/vhost drivers.
+ *
+ * The device ops that is supported by VIRTIO_MDEV_F_VERSION_1, the
+ * callbacks are mandatory unless explicity mentioned.
If the version of the callbacks is returned by a callback within the
structure defined by the version... isn't that a bit circular? This
seems redundant to me versus the class id. The fact that the parent
driver defines the device as MDEV_CLASS_ID_VIRTIO should tell us this
already. If it was incremented, we'd need an MDEV_CLASS_ID_VIRTIOv2,
which the virtio-mdev bus driver could add to its id table and handle
differently.
My understanding is versions are only allowed to increase monotonically,
this seems less flexible than features. E.g we have features A, B, C,
mdev device can choose to support only a subset. E.g when mdev device
can support dirty
Re: [Intel-gfx] [PATCH V5 2/6] modpost: add support for mdev class id
On 2019/10/25 上午3:54, Alex Williamson wrote:
On Thu, 24 Oct 2019 11:31:04 +0800
Jason Wang wrote:
On 2019/10/24 上午5:42, Alex Williamson wrote:
On Wed, 23 Oct 2019 21:07:48 +0800
Jason Wang wrote:
Add support to parse mdev class id table.
Reviewed-by: Parav Pandit
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/vfio_mdev.c | 2 ++
scripts/mod/devicetable-offsets.c | 3 +++
scripts/mod/file2alias.c | 10 ++
3 files changed, 15 insertions(+)
diff --git a/drivers/vfio/mdev/vfio_mdev.c b/drivers/vfio/mdev/vfio_mdev.c
index 7b24ee9cb8dd..cb701cd646f0 100644
--- a/drivers/vfio/mdev/vfio_mdev.c
+++ b/drivers/vfio/mdev/vfio_mdev.c
@@ -125,6 +125,8 @@ static const struct mdev_class_id id_table[] = {
{ 0 },
};
+MODULE_DEVICE_TABLE(mdev, id_table);
+
Two questions, first we have:
#define MODULE_DEVICE_TABLE(type, name) \
extern typeof(name) __mod_##type##__##name##_device_table \
__attribute__ ((unused, alias(__stringify(name
Therefore we're defining __mod_mdev__id_table_device_table with alias
id_table. When the virtio mdev bus driver is added in 5/6 it uses the
same name value. I see virtio types all register this way (virtio,
id_table), so I assume there's no conflict, but pci types mostly (not
entirely) seem to use unique names. Is there a preference to one way
or the other or it simply doesn't matter?
It looks to me that those symbol were local, so it doesn't matter. But
if you wish I can switch to use unique name.
I don't have a strong opinion, I'm just trying to make sure we're not
doing something obviously broken.
Yes, to be more safe I will switch to unique names here.
static struct mdev_driver vfio_mdev_driver = {
.name = "vfio_mdev",
.probe = vfio_mdev_probe,
diff --git a/scripts/mod/devicetable-offsets.c
b/scripts/mod/devicetable-offsets.c
index 054405b90ba4..6cbb1062488a 100644
--- a/scripts/mod/devicetable-offsets.c
+++ b/scripts/mod/devicetable-offsets.c
@@ -231,5 +231,8 @@ int main(void)
DEVID(wmi_device_id);
DEVID_FIELD(wmi_device_id, guid_string);
+ DEVID(mdev_class_id);
+ DEVID_FIELD(mdev_class_id, id);
+
return 0;
}
diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index c91eba751804..d365dfe7c718 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -1335,6 +1335,15 @@ static int do_wmi_entry(const char *filename, void
*symval, char *alias)
return 1;
}
+/* looks like: "mdev:cN" */
+static int do_mdev_entry(const char *filename, void *symval, char *alias)
+{
+ DEF_FIELD(symval, mdev_class_id, id);
+
+ sprintf(alias, "mdev:c%02X", id);
A lot of entries call add_wildcard() here, should we? Sorry for the
basic questions, I haven't played in this code. Thanks,
It's really good question. My understanding is we won't have a module
that can deal with all kinds of classes like CLASS_ID_ANY. So there's
probably no need for the wildcard.
The comment for add_wildcard() indicates future extension, so it's hard
to know what we might need in the future until we do need it. The
majority of modules.alias entries on my laptop (even if I exclude pci
aliases) end with a wildcard. Thanks,
Yes, so I will add that for future extension.
Thanks
Alex
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Flush interrupts before disabling tasklets
== Series Details == Series: drm/i915/selftests: Flush interrupts before disabling tasklets URL : https://patchwork.freedesktop.org/series/68486/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7167_full -> Patchwork_14957_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14957_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14957_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14957_full: ### IGT changes ### Possible regressions * igt@gem_ctx_shared@q-promotion-bsd1: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-glk5/igt@gem_ctx_sha...@q-promotion-bsd1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-glk5/igt@gem_ctx_sha...@q-promotion-bsd1.html * igt@gem_exec_parallel@fds: - shard-skl: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-skl7/igt@gem_exec_paral...@fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-skl10/igt@gem_exec_paral...@fds.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-skl: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-skl10/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html Known issues Here are the changes found in Patchwork_14957_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_exec@basic-invalid-context-vcs1: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#112080]) +7 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-iclb5/igt@gem_ctx_e...@basic-invalid-context-vcs1.html * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-apl3/igt@gem_ctx_isolat...@bcs0-s3.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-apl1/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276] / [fdo#112080]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb1/igt@gem_ctx_isolat...@vcs1-dirty-create.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-iclb5/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_ctx_param@vm: - shard-kbl: [PASS][12] -> [INCOMPLETE][13] ([fdo#103665]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl2/igt@gem_ctx_pa...@vm.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-kbl1/igt@gem_ctx_pa...@vm.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#111325]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb3/igt@gem_exec_sched...@preemptive-hang-bsd.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-hsw: [PASS][16] -> [FAIL][17] ([fdo#112037]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-hsw5/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-hsw6/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_userptr_blits@dmabuf-sync: - shard-snb: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-snb6/igt@gem_userptr_bl...@dmabuf-sync.html * igt@i915_pm_rpm@basic-rte: - shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([fdo#107713] / [fdo#108840]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb8/igt@i915_pm_...@basic-rte.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/shard-iclb7/igt@i915_pm_...@basic-rte.html * igt@kms_busy@extended-pageflip-hang-newfb-render-c: - shard-skl: [PASS][22] -> [SKIP][23] ([fdo#109271]) +3 similar issues [22]:
Re: [Intel-gfx] [PATCH V5 1/6] mdev: class id support
On 2019/10/25 上午4:13, Alex Williamson wrote:
On Thu, 24 Oct 2019 13:46:36 -0600
Alex Williamson wrote:
On Thu, 24 Oct 2019 11:27:36 +0800
Jason Wang wrote:
On 2019/10/24 上午5:42, Alex Williamson wrote:
On Wed, 23 Oct 2019 21:07:47 +0800
Jason Wang wrote:
Mdev bus only supports vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
the first driver could be virtio-mdev. This means we need to add
device class id support in bus match method to pair the mdev device
and mdev driver correctly.
So this patch adds id_table to mdev_driver and class_id for mdev
device with the match method for mdev bus.
Signed-off-by: Jason Wang
---
.../driver-api/vfio-mediated-device.rst | 5 +
drivers/gpu/drm/i915/gvt/kvmgt.c | 1 +
drivers/s390/cio/vfio_ccw_ops.c | 1 +
drivers/s390/crypto/vfio_ap_ops.c | 1 +
drivers/vfio/mdev/mdev_core.c | 18 +++
drivers/vfio/mdev/mdev_driver.c | 22 +++
drivers/vfio/mdev/mdev_private.h | 1 +
drivers/vfio/mdev/vfio_mdev.c | 6 +
include/linux/mdev.h | 8 +++
include/linux/mod_devicetable.h | 8 +++
samples/vfio-mdev/mbochs.c| 1 +
samples/vfio-mdev/mdpy.c | 1 +
samples/vfio-mdev/mtty.c | 1 +
13 files changed, 74 insertions(+)
diff --git a/Documentation/driver-api/vfio-mediated-device.rst
b/Documentation/driver-api/vfio-mediated-device.rst
index 25eb7d5b834b..6709413bee29 100644
--- a/Documentation/driver-api/vfio-mediated-device.rst
+++ b/Documentation/driver-api/vfio-mediated-device.rst
@@ -102,12 +102,14 @@ structure to represent a mediated device's driver::
* @probe: called when new device created
* @remove: called when device removed
* @driver: device driver structure
+ * @id_table: the ids serviced by this driver
*/
struct mdev_driver {
const char *name;
int (*probe) (struct device *dev);
void (*remove) (struct device *dev);
struct device_driverdriver;
+const struct mdev_class_id *id_table;
};
A mediated bus driver for mdev should use this structure in the function calls
@@ -170,6 +172,9 @@ that a driver should use to unregister itself with the mdev
core driver::
extern void mdev_unregister_device(struct device *dev);
+It is also required to specify the class_id in create() callback through::
+
+ int mdev_set_class(struct mdev_device *mdev, u16 id);
Mediated Device Management Interface Through sysfs
==
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 343d79c1cb7e..6420f0dbd31b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -678,6 +678,7 @@ static int intel_vgpu_create(struct kobject *kobj, struct
mdev_device *mdev)
dev_name(mdev_dev(mdev)));
ret = 0;
+ mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
out:
return ret;
}
diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
index f0d71ab77c50..cf2c013ae32f 100644
--- a/drivers/s390/cio/vfio_ccw_ops.c
+++ b/drivers/s390/cio/vfio_ccw_ops.c
@@ -129,6 +129,7 @@ static int vfio_ccw_mdev_create(struct kobject *kobj,
struct mdev_device *mdev)
private->sch->schid.ssid,
private->sch->schid.sch_no);
+ mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
return 0;
}
diff --git a/drivers/s390/crypto/vfio_ap_ops.c b/drivers/s390/crypto/vfio_ap_ops.c
index 5c0f53c6dde7..07c31070afeb 100644
--- a/drivers/s390/crypto/vfio_ap_ops.c
+++ b/drivers/s390/crypto/vfio_ap_ops.c
@@ -343,6 +343,7 @@ static int vfio_ap_mdev_create(struct kobject *kobj, struct
mdev_device *mdev)
list_add(_mdev->node, _dev->mdev_list);
mutex_unlock(_dev->lock);
+ mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
return 0;
}
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index b558d4cfd082..3a9c52d71b4e 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -45,6 +45,16 @@ void mdev_set_drvdata(struct mdev_device *mdev, void *data)
}
EXPORT_SYMBOL(mdev_set_drvdata);
+/* Specify the class for the mdev device, this must be called during
+ * create() callback.
+ */
+void mdev_set_class(struct mdev_device *mdev, u16 id)
+{
+ WARN_ON(mdev->class_id);
+ mdev->class_id = id;
+}
+EXPORT_SYMBOL(mdev_set_class);
+
struct device *mdev_dev(struct mdev_device *mdev)
{
return >dev;
@@ -135,6 +145,7 @@ static int mdev_device_remove_cb(struct device *dev, void
*data)
* mdev_register_device :
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Extract GT render power state management
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Extract GT render power state
management
URL : https://patchwork.freedesktop.org/series/68541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7178 -> Patchwork_14975
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14975/index.html
Known issues
Here are the changes found in Patchwork_14975 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_cpu_reloc@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7178/fi-icl-u3/igt@gem_cpu_re...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14975/fi-icl-u3/igt@gem_cpu_re...@basic.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][3] ([fdo#103927] / [fdo#111381]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7178/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14975/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_ctx_switch@rcs0:
- fi-apl-guc: [INCOMPLETE][5] ([fdo#103927]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7178/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14975/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_reloc@basic-gtt-read:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7178/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14975/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-skl-6770hq: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7178/fi-skl-6770hq/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14975/fi-skl-6770hq/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [FAIL][11] ([fdo#109635 ] / [fdo#110387]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7178/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14975/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (51 -> 44)
--
Missing(7): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7178 -> Patchwork_14975
CI-20190529: 20190529
CI_DRM_7178: dc01a8491d7335012c5c1a25742ee68acfc74843 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5238: b82351ff958ea7932e6bb55b7619ce6178fe99c9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14975: 97942795388d0af61d4eac9b48fd96eb4bc1abe1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
97942795388d drm/i915: Extract the GuC interrupt handlers
eaacb0193172 drm/i915: Extract GT render power state management
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14975/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display/psr: Print in debugfs if PSR is not enabled because of sink
On Fri, 2019-10-25 at 00:50 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display/psr: Print in debugfs if PSR is not enabled
> because of sink
> URL : https://patchwork.freedesktop.org/series/68482/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7167_full -> Patchwork_14955_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14955_full absolutely
> need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the
> changes
> introduced in Patchwork_14955_full, please notify your bug team to
> allow them
> to document this new failure mode, which will reduce false
> positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14955_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
> - shard-skl: NOTRUN -> [FAIL][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-skl1/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
>
> * igt@gem_exec_schedule@preempt-queue-contexts-render:
> - shard-skl: [PASS][2] -> [FAIL][3] +1 similar issue
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-skl9/igt@gem_exec_sched...@preempt-queue-contexts-render.html
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-skl1/igt@gem_exec_sched...@preempt-queue-contexts-render.html
>
>
All gem failures, not related at all with display and PSR so patches
pushed to dinq, thanks for the reviews Ramalingam and Matt.
> Suppressed
>
> The following results come from untrusted machines, tests, or
> statuses.
> They do not affect the overall result.
>
> * igt@gem_exec_schedule@wide-bsd2:
> - {shard-tglb}: [PASS][4] -> [FAIL][5]
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-tglb6/igt@gem_exec_sched...@wide-bsd2.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-tglb6/igt@gem_exec_sched...@wide-bsd2.html
>
> * {igt@i915_selftest@live_gt_pm}:
> - shard-iclb: [PASS][6] -> [DMESG-FAIL][7]
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb3/igt@i915_selftest@live_gt_pm.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb6/igt@i915_selftest@live_gt_pm.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14955_full that come from
> known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_exec@basic-invalid-context-vcs1:
> - shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +10
> similar issues
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb8/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
>
> * igt@gem_ctx_isolation@vcs1-dirty-create:
> - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276] /
> [fdo#112080]) +2 similar issues
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb1/igt@gem_ctx_isolat...@vcs1-dirty-create.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-create.html
>
> * igt@gem_ctx_isolation@vecs0-s3:
> - shard-apl: [PASS][12] -> [DMESG-WARN][13]
> ([fdo#108566]) +1 similar issue
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-apl2/igt@gem_ctx_isolat...@vecs0-s3.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-apl1/igt@gem_ctx_isolat...@vecs0-s3.html
>
> * igt@gem_exec_blt@dumb-buf-max:
> - shard-iclb: [PASS][14] -> [INCOMPLETE][15]
> ([fdo#107713])
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb2/igt@gem_exec_...@dumb-buf-max.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb7/igt@gem_exec_...@dumb-buf-max.html
>
> * igt@gem_exec_schedule@preempt-other-bsd:
> - shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#111325]) +1
> similar issue
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb3/igt@gem_exec_sched...@preempt-other-bsd.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb2/igt@gem_exec_sched...@preempt-other-bsd.html
>
> * igt@gem_exec_schedule@wide-blt:
> - shard-kbl: [PASS][18] -> [INCOMPLETE][19]
> ([fdo#103665])
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl6/igt@gem_exec_sched...@wide-blt.html
>[19]:
>
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Extract GT render power state management
== Series Details == Series: series starting with [CI,1/2] drm/i915: Extract GT render power state management URL : https://patchwork.freedesktop.org/series/68541/ State : warning == Summary == $ dim checkpatch origin/drm-tip eaacb0193172 drm/i915: Extract GT render power state management -:284: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #284: new file mode 100644 -:289: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #289: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:1: +/* -:290: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #290: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:2: + * SPDX-License-Identifier: MIT -:2167: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #2167: FILE: drivers/gpu/drm/i915/gt/intel_rps.h:1: +/* -:2168: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #2168: FILE: drivers/gpu/drm/i915/gt/intel_rps.h:2: + * SPDX-License-Identifier: MIT -:2210: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #2210: FILE: drivers/gpu/drm/i915/gt/intel_rps_types.h:1: +/* -:2211: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #2211: FILE: drivers/gpu/drm/i915/gt/intel_rps_types.h:2: + * SPDX-License-Identifier: MIT -:2285: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #2285: FILE: drivers/gpu/drm/i915/gt/intel_rps_types.h:76: + struct mutex mutex; -:2329: WARNING:LONG_LINE: line over 100 characters #2329: FILE: drivers/gpu/drm/i915/gt/selftest_llc.c:50: + intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)), -:2338: WARNING:LONG_LINE: line over 100 characters #2338: FILE: drivers/gpu/drm/i915/gt/selftest_llc.c:60: + intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)), -:5710: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Andi Shyti ' total: 0 errors, 10 warnings, 1 checks, 5499 lines checked 97942795388d drm/i915: Extract the GuC interrupt handlers ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display/psr: Print in debugfs if PSR is not enabled because of sink
== Series Details ==
Series: drm/i915/display/psr: Print in debugfs if PSR is not enabled because of
sink
URL : https://patchwork.freedesktop.org/series/68482/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7167_full -> Patchwork_14955_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14955_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14955_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14955_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-skl: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-skl1/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-contexts-render:
- shard-skl: [PASS][2] -> [FAIL][3] +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-skl9/igt@gem_exec_sched...@preempt-queue-contexts-render.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-skl1/igt@gem_exec_sched...@preempt-queue-contexts-render.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_schedule@wide-bsd2:
- {shard-tglb}: [PASS][4] -> [FAIL][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-tglb6/igt@gem_exec_sched...@wide-bsd2.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-tglb6/igt@gem_exec_sched...@wide-bsd2.html
* {igt@i915_selftest@live_gt_pm}:
- shard-iclb: [PASS][6] -> [DMESG-FAIL][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb3/igt@i915_selftest@live_gt_pm.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb6/igt@i915_selftest@live_gt_pm.html
Known issues
Here are the changes found in Patchwork_14955_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +10 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb8/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276] /
[fdo#112080]) +2 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb1/igt@gem_ctx_isolat...@vcs1-dirty-create.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-create.html
* igt@gem_ctx_isolation@vecs0-s3:
- shard-apl: [PASS][12] -> [DMESG-WARN][13] ([fdo#108566]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-apl2/igt@gem_ctx_isolat...@vecs0-s3.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-apl1/igt@gem_ctx_isolat...@vecs0-s3.html
* igt@gem_exec_blt@dumb-buf-max:
- shard-iclb: [PASS][14] -> [INCOMPLETE][15] ([fdo#107713])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb2/igt@gem_exec_...@dumb-buf-max.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb7/igt@gem_exec_...@dumb-buf-max.html
* igt@gem_exec_schedule@preempt-other-bsd:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#111325]) +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb3/igt@gem_exec_sched...@preempt-other-bsd.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-iclb2/igt@gem_exec_sched...@preempt-other-bsd.html
* igt@gem_exec_schedule@wide-blt:
- shard-kbl: [PASS][18] -> [INCOMPLETE][19] ([fdo#103665])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl6/igt@gem_exec_sched...@wide-blt.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-kbl1/igt@gem_exec_sched...@wide-blt.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [PASS][20] -> [DMESG-WARN][21] ([fdo#111870])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-snb2/igt@gem_userptr_bl...@sync-unmap.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/shard-snb5/igt@gem_userptr_bl...@sync-unmap.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw:
Re: [Intel-gfx] [PATCH] drm/i915: Catch GTT fault errors for gen11+ planes
On Thu, Oct 24, 2019 at 02:17:34PM -0700, Souza, Jose wrote:
> On Tue, 2019-10-08 at 14:17 -0700, Matt Roper wrote:
> > Gen11+ has more hardware planes than gen9 so we need to test
> > additional
> > pipe interrupt register bits to recognize any GTT faults that happen
> > on
> > these extra planes.
>
> Reviewed-by: José Roberto de Souza
Applied to dinq, thanks for the review.
Matt
>
> >
> > Bspec: 50335
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 4 +++-
> > drivers/gpu/drm/i915/i915_reg.h | 8
> > 2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index f2371b6083c6..5499450c1524 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2589,7 +2589,9 @@ static u32 gen8_de_port_aux_mask(struct
> > drm_i915_private *dev_priv)
> >
> > static u32 gen8_de_pipe_fault_mask(struct drm_i915_private
> > *dev_priv)
> > {
> > - if (INTEL_GEN(dev_priv) >= 9)
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
> > + else if (INTEL_GEN(dev_priv) >= 9)
> > return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> > else
> > return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 6d67bd238cfe..24311fee7009 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7373,6 +7373,9 @@ enum {
> > #define GEN8_PIPE_VSYNC (1 << 1)
> > #define GEN8_PIPE_VBLANK (1 << 0)
> > #define GEN9_PIPE_CURSOR_FAULT(1 << 11)
> > +#define GEN11_PIPE_PLANE7_FAULT (1 << 22)
> > +#define GEN11_PIPE_PLANE6_FAULT (1 << 21)
> > +#define GEN11_PIPE_PLANE5_FAULT (1 << 20)
> > #define GEN9_PIPE_PLANE4_FAULT(1 << 10)
> > #define GEN9_PIPE_PLANE3_FAULT(1 << 9)
> > #define GEN9_PIPE_PLANE2_FAULT(1 << 8)
> > @@ -7392,6 +7395,11 @@ enum {
> > GEN9_PIPE_PLANE3_FAULT | \
> > GEN9_PIPE_PLANE2_FAULT | \
> > GEN9_PIPE_PLANE1_FAULT)
> > +#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
> > + (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
> > +GEN11_PIPE_PLANE7_FAULT | \
> > +GEN11_PIPE_PLANE6_FAULT | \
> > +GEN11_PIPE_PLANE5_FAULT)
> >
> > #define GEN8_DE_PORT_ISR _MMIO(0x0)
> > #define GEN8_DE_PORT_IMR _MMIO(0x4)
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix PCH reference clock for FDI on HSW/BDW (rev2)
== Series Details ==
Series: drm/i915: Fix PCH reference clock for FDI on HSW/BDW (rev2)
URL : https://patchwork.freedesktop.org/series/68411/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7167_full -> Patchwork_14953_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14953_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14953_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14953_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_shared@q-promotion-bsd1:
- shard-apl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-apl2/igt@gem_ctx_sha...@q-promotion-bsd1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-apl1/igt@gem_ctx_sha...@q-promotion-bsd1.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-skl: NOTRUN -> [FAIL][3] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-skl8/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
- shard-iclb: NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-iclb3/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_parallel@bcs0:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-tglb1/igt@gem_exec_paral...@bcs0.html
* igt@gem_exec_schedule@wide-bsd2:
- {shard-tglb}: [PASS][6] -> [FAIL][7] +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-tglb6/igt@gem_exec_sched...@wide-bsd2.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-tglb4/igt@gem_exec_sched...@wide-bsd2.html
Known issues
Here are the changes found in Patchwork_14953_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +9 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-iclb7/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
* igt@gem_ctx_isolation@vcs1-s3:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276] / [fdo#112080])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb4/igt@gem_ctx_isolat...@vcs1-s3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-iclb6/igt@gem_ctx_isolat...@vcs1-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd1:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276]) +14 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd1.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd1.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#111325]) +3 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb6/igt@gem_exec_as...@concurrent-writes-bsd.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-iclb4/igt@gem_exec_as...@concurrent-writes-bsd.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-skl: [PASS][16] -> [DMESG-WARN][17] ([fdo#106107])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-skl7/igt@gem_exec_re...@basic-write-read-active.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-skl7/igt@gem_exec_re...@basic-write-read-active.html
* igt@gem_exec_schedule@wide-bsd2:
- shard-kbl: [PASS][18] -> [INCOMPLETE][19] ([fdo#103665])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl2/igt@gem_exec_sched...@wide-bsd2.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/shard-kbl3/igt@gem_exec_sched...@wide-bsd2.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-snb: [PASS][20] -> [FAIL][21] ([fdo#112037])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-snb6/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
[21]:
Re: [Intel-gfx] [PATCH 02/11] drm/i915: Put future HW and their uAPIs under STAGING & BROKEN
On Thu, Oct 24, 2019 at 12:40:19PM +0100, Chris Wilson wrote: > We would like some freedom to break the user API/ABI for future HW but > yet still expose the driver for upstream development on that HW. > Currently, we have the i915.force_probe module parameter to avoid binding > to HW while the driver is under development, but that is still a little > too soft with respect to the stringent no-regression rules if we also > plan to be redesigning the uAPI to go along with the new HW. > > To allow the uAPI to be changed during development, only expose that API > and in development HW under STAGING (and BROKEN). Hopefully, making it > explicit that such interfaces to that HW are under development and not > to be blindly enabled by distributions. > > Signed-off-by: Chris Wilson > Cc: Daniel Vetter > Cc: Joonas Lahtinen > Cc: Jani Nikula > Cc: Rodrigo Vivi > Cc: Dave Airlie Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/Kconfig | 8 > drivers/gpu/drm/i915/Kconfig.debug| 1 + > drivers/gpu/drm/i915/Kconfig.unstable | 20 > 3 files changed, 29 insertions(+) > create mode 100644 drivers/gpu/drm/i915/Kconfig.unstable > > diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig > index 3c6d57df262d..1fd9e665b742 100644 > --- a/drivers/gpu/drm/i915/Kconfig > +++ b/drivers/gpu/drm/i915/Kconfig > @@ -148,3 +148,11 @@ menu "drm/i915 Profile Guided Optimisation" > depends on DRM_I915 > source "drivers/gpu/drm/i915/Kconfig.profile" > endmenu > + > +menu "drm/i915 Ustable Evolution" > + visible if EXPERT > + visible if STAGING > + visible if BROKEN > + depends on DRM_I915 > + source "drivers/gpu/drm/i915/Kconfig.unstable" > +endmenu > diff --git a/drivers/gpu/drm/i915/Kconfig.debug > b/drivers/gpu/drm/i915/Kconfig.debug > index d2ba8f7e5e50..ef123eb29168 100644 > --- a/drivers/gpu/drm/i915/Kconfig.debug > +++ b/drivers/gpu/drm/i915/Kconfig.debug > @@ -44,6 +44,7 @@ config DRM_I915_DEBUG > select DRM_I915_SELFTEST > select DRM_I915_DEBUG_RUNTIME_PM > select DRM_I915_DEBUG_MMIO > + select BROKEN # for prototype uAPI > default n > help > Choose this option to turn on extra driver debugging that may affect > diff --git a/drivers/gpu/drm/i915/Kconfig.unstable > b/drivers/gpu/drm/i915/Kconfig.unstable > new file mode 100644 > index ..ecc8458b5a32 > --- /dev/null > +++ b/drivers/gpu/drm/i915/Kconfig.unstable > @@ -0,0 +1,20 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +config DRM_I915_UNSTABLE > + bool "Enable unstable API for early prototype development" > + depends on EXPERT > + depends on STAGING > + depends on BROKEN # should never be enabled by distros! > + # We use the dependency on !COMPILE_TEST to not be enabled in > + # allmodconfig or allyesconfig configurations > + depends on !COMPILE_TEST > + default n > + help > + Enable prototype uAPI under general discussion before they are > + finalized. Such prototypes may be withdrawn or substantially > + changed before release. They are only enabled here so that a wide > + number of interested parties (userspace driver developers) can > + verify that the uAPI meet their expectations. > + > + Recommended for driver developers _only_. > + > + If in the slightest bit of doubt, say "N". > -- > 2.24.0.rc0 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/11] drm/i915: Put future HW and their uAPIs under STAGING & BROKEN
Acked-by: Dave Airlie On Thu, Oct 24, 2019 at 9:40 PM Chris Wilson wrote: > > We would like some freedom to break the user API/ABI for future HW but > yet still expose the driver for upstream development on that HW. > Currently, we have the i915.force_probe module parameter to avoid binding > to HW while the driver is under development, but that is still a little > too soft with respect to the stringent no-regression rules if we also > plan to be redesigning the uAPI to go along with the new HW. > > To allow the uAPI to be changed during development, only expose that API > and in development HW under STAGING (and BROKEN). Hopefully, making it > explicit that such interfaces to that HW are under development and not > to be blindly enabled by distributions. > > Signed-off-by: Chris Wilson > Cc: Daniel Vetter > Cc: Joonas Lahtinen > Cc: Jani Nikula > Cc: Rodrigo Vivi > Cc: Dave Airlie > --- > drivers/gpu/drm/i915/Kconfig | 8 > drivers/gpu/drm/i915/Kconfig.debug| 1 + > drivers/gpu/drm/i915/Kconfig.unstable | 20 > 3 files changed, 29 insertions(+) > create mode 100644 drivers/gpu/drm/i915/Kconfig.unstable > > diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig > index 3c6d57df262d..1fd9e665b742 100644 > --- a/drivers/gpu/drm/i915/Kconfig > +++ b/drivers/gpu/drm/i915/Kconfig > @@ -148,3 +148,11 @@ menu "drm/i915 Profile Guided Optimisation" > depends on DRM_I915 > source "drivers/gpu/drm/i915/Kconfig.profile" > endmenu > + > +menu "drm/i915 Ustable Evolution" > + visible if EXPERT > + visible if STAGING > + visible if BROKEN > + depends on DRM_I915 > + source "drivers/gpu/drm/i915/Kconfig.unstable" > +endmenu > diff --git a/drivers/gpu/drm/i915/Kconfig.debug > b/drivers/gpu/drm/i915/Kconfig.debug > index d2ba8f7e5e50..ef123eb29168 100644 > --- a/drivers/gpu/drm/i915/Kconfig.debug > +++ b/drivers/gpu/drm/i915/Kconfig.debug > @@ -44,6 +44,7 @@ config DRM_I915_DEBUG > select DRM_I915_SELFTEST > select DRM_I915_DEBUG_RUNTIME_PM > select DRM_I915_DEBUG_MMIO > + select BROKEN # for prototype uAPI > default n > help > Choose this option to turn on extra driver debugging that may affect > diff --git a/drivers/gpu/drm/i915/Kconfig.unstable > b/drivers/gpu/drm/i915/Kconfig.unstable > new file mode 100644 > index ..ecc8458b5a32 > --- /dev/null > +++ b/drivers/gpu/drm/i915/Kconfig.unstable > @@ -0,0 +1,20 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +config DRM_I915_UNSTABLE > + bool "Enable unstable API for early prototype development" > + depends on EXPERT > + depends on STAGING > + depends on BROKEN # should never be enabled by distros! > + # We use the dependency on !COMPILE_TEST to not be enabled in > + # allmodconfig or allyesconfig configurations > + depends on !COMPILE_TEST > + default n > + help > + Enable prototype uAPI under general discussion before they are > + finalized. Such prototypes may be withdrawn or substantially > + changed before release. They are only enabled here so that a wide > + number of interested parties (userspace driver developers) can > + verify that the uAPI meet their expectations. > + > + Recommended for driver developers _only_. > + > + If in the slightest bit of doubt, say "N". > -- > 2.24.0.rc0 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: Add is_dgfx to device info
On Thu, Oct 24, 2019 at 03:08:59PM -0700, Lucas De Marchi wrote:
> On Thu, Oct 24, 2019 at 12:51:19PM -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza
> >
> > This will be helpful to diferentiate a set of GPUs
> > with the same GEN version.
> >
> > Signed-off-by: José Roberto de Souza
> > Signed-off-by: Lucas De Marchi
>
>
> Reviewed-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
>
> Lucas De Marchi
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 674e9e921839..12646b94af87 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1544,6 +1544,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > }
> >
> > #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
> > +#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
> >
> > #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
> > #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index e9940f932d26..78a383f63957 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -107,6 +107,7 @@ enum intel_ppgtt_type {
> > func(is_mobile); \
> > func(is_lp); \
> > func(require_force_probe); \
> > + func(is_dgfx); \
> > /* Keep has_* in alphabetical order */ \
> > func(has_64bit_reloc); \
> > func(gpu_reset_clobbers_display); \
> > --
> > 2.23.0
> >
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Add is_dgfx to device info
== Series Details ==
Series: series starting with [1/4] drm/i915: Add is_dgfx to device info
URL : https://patchwork.freedesktop.org/series/68535/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7176 -> Patchwork_14974
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14974/index.html
Known issues
Here are the changes found in Patchwork_14974 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_wait@basic-await-all:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_w...@basic-await-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14974/fi-icl-u3/igt@gem_w...@basic-await-all.html
Possible fixes
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4] +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_mmap_...@basic-write-cpu-read-gtt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14974/fi-icl-u3/igt@gem_mmap_...@basic-write-cpu-read-gtt.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-x1275: [DMESG-FAIL][5] ([fdo#112096]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14974/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112057]: https://bugs.freedesktop.org/show_bug.cgi?id=112057
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (49 -> 45)
--
Additional (2): fi-bxt-dsi fi-icl-dsi
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7176 -> Patchwork_14974
CI-20190529: 20190529
CI_DRM_7176: 9c250db49037a2ef0dc499d6cd2f9712fcbdf8c0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14974: 5e76020d0a7f5592415eefe90ad947f90947fa7d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5e76020d0a7f drm/i915: split gen11_irq_handler to make it shareable
90014b1e5efb drm/i915: do not set MOCS control values on dgfx
5822be50ff35 drm/i915: add new gen12 dgfx platform macro
a706b75f5303 drm/i915: Add is_dgfx to device info
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14974/index.html
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Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm: Add support for integrated privacy screens
On Thu, Oct 24, 2019 at 12:01 AM Jani Nikula wrote: > > On Thu, 24 Oct 2019, Patchwork wrote: > > == Series Details == > > > > Series: drm: Add support for integrated privacy screens > > URL : https://patchwork.freedesktop.org/series/68472/ > > State : failure > > > > == Summary == > > > > CALLscripts/checksyscalls.sh > > CALLscripts/atomic/check-atomics.sh > > DESCEND objtool > > CHK include/generated/compile.h > > Kernel: arch/x86/boot/bzImage is ready (#1) > > Building modules, stage 2. > > MODPOST 122 modules > > ERROR: "drm_privacy_screen_present" [drivers/gpu/drm/i915/i915.ko] > > undefined! > > This means you need to EXPORT_SYMBOL(drm_privacy_screen_present). Sorry, will do. > > BR, > Jani. > > > scripts/Makefile.modpost:93: recipe for target '__modpost' failed > > make[1]: *** [__modpost] Error 1 > > Makefile:1282: recipe for target 'modules' failed > > make: *** [modules] Error 2 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
On 2019-10-23 8:00 p.m., Manasi Navare wrote:
> Adaptive Sync is a VESA feature so add a DRM core helper to parse
> the EDID's detailed descritors to obtain the adaptive sync monitor range.
> Store this info as part fo drm_display_info so it can be used
> across all drivers.
> This part of the code is stripped out of amdgpu's function
> amdgpu_dm_update_freesync_caps() to make it generic and be used
> across all DRM drivers
>
Please CC Nick on these as well. Added him now.
Would it be possible to add a patch to update amdgpu to call this function?
Harry
> Cc: Ville Syrjälä
> Cc: Harry Wentland
> Cc: Clinton A Taylor
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/drm_edid.c | 49 +
> include/drm/drm_connector.h | 25 +++
> include/drm/drm_edid.h | 2 ++
> 3 files changed, 76 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 474ac04d5600..97dd1200773e 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct drm_connector
> *connector,
> }
> }
>
> +void drm_get_adaptive_sync_limits(struct drm_connector *connector,
> + const struct edid *edid)
> +{
> + struct drm_display_info *info = >display_info;
> + const struct detailed_timing *timing;
> + const struct detailed_non_pixel *data;
> + const struct detailed_data_monitor_range *range;
> + int i;
> +
> + /*
> + * Restrict Adaptive Sync only for dp and edp
> + */
> + if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
> + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> + return;
> +
> + if (edid->version <= 1 && !(edid->version == 1 && edid->revision > 1))
> + return;
> +
> + for (i = 0; i < 4; i++) {
> + timing = >detailed_timings[i];
> + data= >data.other_data;
> + range = >data.range;
> + /*
> + * Check if monitor has continuous frequency mode
> + */
> + if (data->type != EDID_DETAIL_MONITOR_RANGE)
> + continue;
> + /*
> + * Check for flag range limits only. If flag == 1 then
> + * no additional timing information provided.
> + * Default GTF, GTF Secondary curve and CVT are not
> + * supported
> + */
> + if (range->flags != 1)
> + continue;
> +
> + info->adaptive_sync.min_vfreq = range->min_vfreq;
> + info->adaptive_sync.max_vfreq = range->max_vfreq;
> + info->adaptive_sync.pixel_clock_mhz =
> + range->pixel_clock_mhz * 10;
> + break;
> + }
> +}
> +EXPORT_SYMBOL(drm_get_adaptive_sync_limits);
> +
> /* A connector has no EDID information, so we've got no EDID to compute
> quirks from. Reset
> * all of the values which would have been set from EDID
> */
> @@ -4728,6 +4774,7 @@ drm_reset_display_info(struct drm_connector *connector)
> memset(>hdmi, 0, sizeof(info->hdmi));
>
> info->non_desktop = 0;
> + memset(>adaptive_sync, 0, sizeof(info->adaptive_sync));
> }
>
> u32 drm_add_display_info(struct drm_connector *connector, const struct edid
> *edid)
> @@ -4743,6 +4790,8 @@ u32 drm_add_display_info(struct drm_connector
> *connector, const struct edid *edi
>
> info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
>
> + drm_get_adaptive_sync_limits(connector, edid);
> +
> DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
>
> if (edid->revision < 3)
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 5f8c3389d46f..a27a84270d8d 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -254,6 +254,26 @@ enum drm_panel_orientation {
> DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
> };
>
> +/**
> + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for
> + * _display_info
> + *
> + * This struct is used to store a Panel's Adaptive Sync capabilities
> + * as parsed from EDID's detailed monitor range descriptor block.
> + *
> + * @min_vfreq: This is the min supported refresh rate in Hz from
> + * EDID's detailed monitor range.
> + * @max_vfreq: This is the max supported refresh rate in Hz from
> + * EDID's detailed monitor range
> + * @pixel_clock_mhz: This is the dotclock in MHz from
> + * EDID's detailed monitor range
> + */
> +struct drm_adaptive_sync_info {
> + int min_vfreq;
> + int max_vfreq;
> + int pixel_clock_mhz;
> +};
> +
> /*
> * This is a consolidated colorimetry list supported by HDMI and
> * DP protocol standard. The respective connectors will register
> @@ -465,6 +485,11 @@ struct drm_display_info {
>* @non_desktop: Non
Re: [Intel-gfx] [PATCH v6 1/2] drm/i915: Refactor intel_can_enable_sagv
On Wed, Oct 23, 2019 at 12:08:03PM +0300, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
>
> v2:
> - Rework watermark calculation algorithm to
> attempt to calculate Level 0 watermark
> with added sagv block time latency and
> check if it fits in DBuf in order to
> determine if SAGV can be enabled already
> at this stage, just as BSpec 49325 states.
> if that fails rollback to usual Level 0
> latency and disable SAGV.
> - Remove unneeded tabs(James Ausmus)
>
> v3: Rebased the patch
>
> Signed-off-by: Stanislav Lisovskiy
> Cc: Ville Syrjälä
> Cc: James Ausmus
> ---
> .../drm/i915/display/intel_display_types.h| 8 +
> drivers/gpu/drm/i915/intel_pm.c | 228 +-
> 2 files changed, 228 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8358152e403e..f09c80c96470 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -490,6 +490,13 @@ struct intel_atomic_state {
>*/
> u8 active_pipe_changes;
>
> + /*
> + * For Gen12 only after calculating watermarks with
> + * additional latency, we can determine if SAGV can be enabled
> + * or not for that particular configuration.
> + */
> + bool gen12_can_sagv;
> +
> u8 active_pipes;
> /* minimum acceptable cdclk for each pipe */
> int min_cdclk[I915_MAX_PIPES];
> @@ -642,6 +649,7 @@ struct skl_plane_wm {
> struct skl_wm_level wm[8];
> struct skl_wm_level uv_wm[8];
> struct skl_wm_level trans_wm;
> + struct skl_wm_level sagv_wm_l0;
> bool is_planar;
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 362234449087..c0419e4d83de 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3751,7 +3751,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +bool skl_can_enable_sagv(struct intel_atomic_state *state)
> {
> struct drm_device *dev = state->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3817,6 +3817,75 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
> return true;
> }
>
> +bool icl_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int level, latency;
> + int i;
> + int plane_id;
> +
> + if (!intel_has_sagv(dev_priv))
> + return false;
> +
> + /*
> + * If there are no active CRTCs, no additional checks need be performed
> + */
> + if (hweight8(state->active_pipes) == 0)
> + return true;
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> +
> + if (crtc->base.state->adjusted_mode.flags &
> DRM_MODE_FLAG_INTERLACE)
> + return false;
> +
> + if (!new_crtc_state->base.enable)
> + continue;
> +
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + struct skl_plane_wm *wm =
> +
> _crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + /* Skip this plane if it's not enabled */
> + if (!wm->wm[0].plane_en)
> + continue;
> +
> + /* Find the highest enabled wm level for this plane */
> + for (level = ilk_wm_max_level(dev_priv);
> + !wm->wm[level].plane_en; --level)
> + { }
> +
> + latency = dev_priv->wm.skl_latency[level];
> +
> + /*
> + * If any of the planes on this pipe don't enable wm
> levels that
> + * incur memory latencies higher than
> sagv_block_time_us we
> + * can't enable SAGV.
> + */
> + if (latency < dev_priv->sagv_block_time_us)
> + return false;
> + }
> + }
> +
> + return true;
> +}
> +
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + return state->gen12_can_sagv;
This loses the interlaced mode check that the skl and
[Intel-gfx] ✗ Fi.CI.BAT: failure for Update VSC SDP / HDR Metadata SDP states on pipe updates.
== Series Details ==
Series: Update VSC SDP / HDR Metadata SDP states on pipe updates.
URL : https://patchwork.freedesktop.org/series/68531/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7176 -> Patchwork_14973
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14973 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14973, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14973:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_uncore:
- fi-kbl-r: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-r/igt@i915_selftest@live_uncore.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-kbl-r/igt@i915_selftest@live_uncore.html
Known issues
Here are the changes found in Patchwork_14973 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@bad-close:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_ba...@bad-close.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-icl-u3/igt@gem_ba...@bad-close.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][5] -> [DMESG-FAIL][6] ([fdo#112050 ])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Possible fixes
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_mmap_...@basic-write-cpu-read-gtt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-icl-u3/igt@gem_mmap_...@basic-write-cpu-read-gtt.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-x1275: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][11] ([fdo#111600]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#111045]
/ [fdo#111096])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (49 -> 45)
--
Additional (2): fi-bxt-dsi fi-icl-dsi
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7176 -> Patchwork_14973
CI-20190529: 20190529
CI_DRM_7176: 9c250db49037a2ef0dc499d6cd2f9712fcbdf8c0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14973: 4e64e33c758a1d6adc26972ac5f5ca5ef41897c6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4e64e33c758a drm/i915/dp: Call dp_vsc_enable() /
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Add is_dgfx to device info
== Series Details == Series: series starting with [1/4] drm/i915: Add is_dgfx to device info URL : https://patchwork.freedesktop.org/series/68535/ State : warning == Summary == $ dim checkpatch origin/drm-tip a706b75f5303 drm/i915: Add is_dgfx to device info 5822be50ff35 drm/i915: add new gen12 dgfx platform macro 90014b1e5efb drm/i915: do not set MOCS control values on dgfx 5e76020d0a7f drm/i915: split gen11_irq_handler to make it shareable -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: pointers. This allows to share the interrupt handler even if the enable/disable total: 0 errors, 1 warnings, 0 checks, 45 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Remove nonpriv flags when srm/lrm
Quoting Lionel Landwerlin (2019-10-24 16:23:01) > On 24/10/2019 14:37, Chris Wilson wrote: > > Quoting Mika Kuoppala (2019-10-24 12:03:31) > >> On testing the whitelists, using any of the nonpriv > >> flags when trying to access the register offset will lead > >> to failure. > >> > >> Define address mask to get the mmio offset in order > >> to guard against any current and future flag usage. > >> > >> v2: apply also on scrub_whitelisted_registers (Lionel) > >> > >> Cc: Tapani Pälli > >> Cc: Chris Wilson > >> Cc: Lionel Landwerlin > >> Signed-off-by: Mika Kuoppala > > Reviewed-by: Chris Wilson > > -Chris > > > Reviewed-by: Lionel Landwerlin And pushed, thanks for the fixup and the original patch! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add CHICKEN_TRANS_D
On Thu, 2019-10-24 at 15:21 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add CHICKEN_TRANS definition for transcoder D.
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 38071d0c8020..50c2fa0f2cab 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7620,11 +7620,13 @@ enum {
> #define _CHICKEN_TRANS_B 0x420c4
> #define _CHICKEN_TRANS_C 0x420c8
> #define _CHICKEN_TRANS_EDP 0x420cc
> +#define _CHICKEN_TRANS_D 0x420d8
> #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> [TRANSCODER_EDP] =
> _CHICKEN_TRANS_EDP, \
> [TRANSCODER_A] =
> _CHICKEN_TRANS_A, \
> [TRANSCODER_B] =
> _CHICKEN_TRANS_B, \
> - [TRANSCODER_C] =
> _CHICKEN_TRANS_C))
> + [TRANSCODER_C] =
> _CHICKEN_TRANS_C, \
> + [TRANSCODER_D] =
> _CHICKEN_TRANS_D))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and
> CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE(1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
On Thu, 2019-10-24 at 15:21 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make CHICKEN_TRANS() a bit less special looking by using _PICK().
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++---
> drivers/gpu/drm/i915/display/intel_psr.c | 22 +-
> drivers/gpu/drm/i915/i915_reg.h | 13 +
> 3 files changed, 17 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1a49266f4f57..127dd2d736d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3870,12 +3870,12 @@ static i915_reg_t
> gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - static const i915_reg_t regs[] = {
> - [PORT_A] = CHICKEN_TRANS_EDP,
> - [PORT_B] = CHICKEN_TRANS_A,
> - [PORT_C] = CHICKEN_TRANS_B,
> - [PORT_D] = CHICKEN_TRANS_C,
> - [PORT_E] = CHICKEN_TRANS_A,
> + static const enum transcoder trans[] = {
> + [PORT_A] = TRANSCODER_EDP,
> + [PORT_B] = TRANSCODER_A,
> + [PORT_C] = TRANSCODER_B,
> + [PORT_D] = TRANSCODER_C,
> + [PORT_E] = TRANSCODER_A,
> };
>
> WARN_ON(INTEL_GEN(dev_priv) < 9);
> @@ -3883,7 +3883,7 @@ gen9_chicken_trans_reg_by_port(struct
> drm_i915_private *dev_priv,
> if (WARN_ON(port < PORT_A || port > PORT_E))
> port = PORT_A;
>
> - return regs[port];
> + return CHICKEN_TRANS(trans[port]);
> }
>
> static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index dfbedff98ea8..1643c35484d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -740,25 +740,6 @@ static void intel_psr_activate(struct intel_dp
> *intel_dp)
> dev_priv->psr.active = true;
> }
>
> -static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private
> *dev_priv,
> - enum transcoder
> cpu_transcoder)
> -{
> - static const i915_reg_t regs[] = {
> - [TRANSCODER_A] = CHICKEN_TRANS_A,
> - [TRANSCODER_B] = CHICKEN_TRANS_B,
> - [TRANSCODER_C] = CHICKEN_TRANS_C,
> - [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
> - };
> -
> - WARN_ON(INTEL_GEN(dev_priv) < 9);
> -
> - if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
> - !regs[cpu_transcoder].reg))
> - cpu_transcoder = TRANSCODER_A;
> -
> - return regs[cpu_transcoder];
> -}
> -
> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> const struct intel_crtc_state
> *crtc_state)
> {
> @@ -774,8 +755,7 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
>
> if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> !IS_GEMINILAKE(dev_priv))) {
> - i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
> - cpu_transcoder)
> ;
> + i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> u32 chicken = I915_READ(reg);
>
> chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..38071d0c8020 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7616,10 +7616,15 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD(1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A,
> _CHICKEN_PIPESL_1_B)
>
> -#define CHICKEN_TRANS_A _MMIO(0x420c0)
> -#define CHICKEN_TRANS_B _MMIO(0x420c4)
> -#define CHICKEN_TRANS_C _MMIO(0x420c8)
> -#define CHICKEN_TRANS_EDP_MMIO(0x420cc)
> +#define _CHICKEN_TRANS_A 0x420c0
> +#define _CHICKEN_TRANS_B 0x420c4
> +#define _CHICKEN_TRANS_C 0x420c8
> +#define _CHICKEN_TRANS_EDP 0x420cc
> +#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> + [TRANSCODER_EDP] =
> _CHICKEN_TRANS_EDP, \
> + [TRANSCODER_A] =
> _CHICKEN_TRANS_A, \
> + [TRANSCODER_B] =
> _CHICKEN_TRANS_B, \
> + [TRANSCODER_C] =
> _CHICKEN_TRANS_C))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and
> CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE(1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
___
Intel-gfx mailing list
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/property: Enforce more lifetime rules
== Series Details ==
Series: series starting with [1/2] drm/property: Enforce more lifetime rules
URL : https://patchwork.freedesktop.org/series/68467/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7167_full -> Patchwork_14952_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14952_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14952_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14952_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_shared@q-promotion-bsd1:
- shard-iclb: NOTRUN -> [FAIL][1] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-iclb5/igt@gem_ctx_sha...@q-promotion-bsd1.html
- shard-apl: [PASS][2] -> [FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-apl2/igt@gem_ctx_sha...@q-promotion-bsd1.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-apl8/igt@gem_ctx_sha...@q-promotion-bsd1.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
- {shard-tglb}: [PASS][4] -> [INCOMPLETE][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-tglb1/igt@kms_plane_alpha_bl...@pipe-a-alpha-transparant-fb.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-tglb2/igt@kms_plane_alpha_bl...@pipe-a-alpha-transparant-fb.html
Known issues
Here are the changes found in Patchwork_14952_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276] / [fdo#112080])
+1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb1/igt@gem_ctx_isolat...@vcs1-dirty-create.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-iclb6/igt@gem_ctx_isolat...@vcs1-dirty-create.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][8] -> [INCOMPLETE][9] ([fdo#104108])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-skl1/igt@gem_...@in-flight-suspend.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-skl9/igt@gem_...@in-flight-suspend.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#110854])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb2/igt@gem_exec_balan...@smoke.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-iclb5/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#112080]) +7 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb2/igt@gem_exec_paral...@vcs1-fds.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-iclb5/igt@gem_exec_paral...@vcs1-fds.html
* igt@gem_exec_schedule@pi-ringfull-render:
- shard-kbl: [PASS][14] -> [INCOMPLETE][15] ([fdo#103665])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl6/igt@gem_exec_sched...@pi-ringfull-render.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-kbl2/igt@gem_exec_sched...@pi-ringfull-render.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#111325]) +5 similar
issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb3/igt@gem_exec_sched...@preemptive-hang-bsd.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-hsw: [PASS][20] -> [DMESG-WARN][21] ([fdo#111870])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][22] ->
Re: [Intel-gfx] [PATCH 1/4] drm/i915: Add is_dgfx to device info
On Thu, Oct 24, 2019 at 12:51:19PM -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
This will be helpful to diferentiate a set of GPUs
with the same GEN version.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 674e9e921839..12646b94af87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1544,6 +1544,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
}
#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
+#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index e9940f932d26..78a383f63957 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -107,6 +107,7 @@ enum intel_ppgtt_type {
func(is_mobile); \
func(is_lp); \
func(require_force_probe); \
+ func(is_dgfx); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(gpu_reset_clobbers_display); \
--
2.23.0
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update VSC SDP / HDR Metadata SDP states on pipe updates.
== Series Details ==
Series: Update VSC SDP / HDR Metadata SDP states on pipe updates.
URL : https://patchwork.freedesktop.org/series/68531/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d3e19ea1104d drm/i915: Add whether or not to enable an each of Video DIP
-:71: CHECK:BRACES: Unbalanced braces around else statement
#71: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:616:
+ else {
-:73: WARNING:LINE_SPACING: Missing a blank line after declarations
#73: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:618:
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ DRM_DEBUG_KMS("GEN%d enable_infoframe() callback is not
implemented!",
total: 0 errors, 1 warnings, 1 checks, 71 lines checked
b396335c33e9 drm/i915: Add checking a specific Video DIP is enabled or not
f32dfb7a6a6c drm/i915/dp: Stop sending of VSC SDP when it is not needed
f98d7188544e drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not
needed
-:25: WARNING:TABSTOP: Statements should start on a tabstop
#25: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4760:
+ if (intel_infoframe_enabled(encoder, crtc_state,
total: 0 errors, 1 warnings, 0 checks, 17 lines checked
4e64e33c758a drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe
updates
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Handle AUX interrupts for TC ports (rev2)
== Series Details ==
Series: drm/i915/tgl: Handle AUX interrupts for TC ports (rev2)
URL : https://patchwork.freedesktop.org/series/68528/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7176 -> Patchwork_14972
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/index.html
Known issues
Here are the changes found in Patchwork_14972 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_create@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_exec_cre...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/fi-icl-u3/igt@gem_exec_cre...@basic.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4] ([fdo#105876])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-bsw-n3050/igt@i915_module_l...@reload-with-fault-injection.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/fi-bsw-n3050/igt@i915_module_l...@reload-with-fault-injection.html
Possible fixes
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_mmap_...@basic-write-cpu-read-gtt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/fi-icl-u3/igt@gem_mmap_...@basic-write-cpu-read-gtt.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-x1275: [DMESG-FAIL][7] ([fdo#112096]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111887]: https://bugs.freedesktop.org/show_bug.cgi?id=111887
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (49 -> 43)
--
Additional (2): fi-bxt-dsi fi-icl-dsi
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7176 -> Patchwork_14972
CI-20190529: 20190529
CI_DRM_7176: 9c250db49037a2ef0dc499d6cd2f9712fcbdf8c0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14972: 9a707b1f35c1cf87fe7a82158548e13e8487fc07 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9a707b1f35c1 drm/i915/tgl: Handle AUX interrupts for TC ports
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: register vga switcheroo later, unregister earlier (rev2)
== Series Details ==
Series: drm/i915: register vga switcheroo later, unregister earlier (rev2)
URL : https://patchwork.freedesktop.org/series/67644/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7167_full -> Patchwork_14951_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14951_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14951_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14951_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_shared@q-promotion-bsd1:
- shard-iclb: NOTRUN -> [FAIL][1] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-iclb3/igt@gem_ctx_sha...@q-promotion-bsd1.html
- shard-apl: [PASS][2] -> [FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-apl2/igt@gem_ctx_sha...@q-promotion-bsd1.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-apl6/igt@gem_ctx_sha...@q-promotion-bsd1.html
* igt@gem_exec_parallel@fds:
- shard-kbl: [PASS][4] -> [FAIL][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl6/igt@gem_exec_paral...@fds.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-kbl3/igt@gem_exec_paral...@fds.html
- shard-skl: [PASS][6] -> [FAIL][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-skl7/igt@gem_exec_paral...@fds.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-skl4/igt@gem_exec_paral...@fds.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-skl: NOTRUN -> [FAIL][8] +1 similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-skl4/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_shared@q-promotion-bsd1:
- {shard-tglb}: [PASS][9] -> [FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-tglb6/igt@gem_ctx_sha...@q-promotion-bsd1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-tglb3/igt@gem_ctx_sha...@q-promotion-bsd1.html
Known issues
Here are the changes found in Patchwork_14951_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +8 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-iclb8/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +3
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-apl3/igt@gem_ctx_isolat...@bcs0-s3.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-apl1/igt@gem_ctx_isolat...@bcs0-s3.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109276] /
[fdo#112080]) +1 similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb1/igt@gem_ctx_isolat...@vcs1-dirty-create.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-iclb7/igt@gem_ctx_isolat...@vcs1-dirty-create.html
* igt@gem_exec_schedule@preempt-other-bsd:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#111325]) +2 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb3/igt@gem_exec_sched...@preempt-other-bsd.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-iclb1/igt@gem_exec_sched...@preempt-other-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd2:
- shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103665])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl6/igt@gem_exec_sched...@preempt-queue-bsd2.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/shard-kbl3/igt@gem_exec_sched...@preempt-queue-bsd2.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +4
similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl4/igt@gem_exec_susp...@basic-s3.html
[22]:
Re: [Intel-gfx] [PATCH] drm/i915: Catch GTT fault errors for gen11+ planes
On Tue, 2019-10-08 at 14:17 -0700, Matt Roper wrote:
> Gen11+ has more hardware planes than gen9 so we need to test
> additional
> pipe interrupt register bits to recognize any GTT faults that happen
> on
> these extra planes.
Reviewed-by: José Roberto de Souza
>
> Bspec: 50335
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_irq.c | 4 +++-
> drivers/gpu/drm/i915/i915_reg.h | 8
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index f2371b6083c6..5499450c1524 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2589,7 +2589,9 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
>
> static u32 gen8_de_pipe_fault_mask(struct drm_i915_private
> *dev_priv)
> {
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (INTEL_GEN(dev_priv) >= 11)
> + return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
> + else if (INTEL_GEN(dev_priv) >= 9)
> return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> else
> return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 6d67bd238cfe..24311fee7009 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7373,6 +7373,9 @@ enum {
> #define GEN8_PIPE_VSYNC (1 << 1)
> #define GEN8_PIPE_VBLANK(1 << 0)
> #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
> +#define GEN11_PIPE_PLANE7_FAULT (1 << 22)
> +#define GEN11_PIPE_PLANE6_FAULT (1 << 21)
> +#define GEN11_PIPE_PLANE5_FAULT (1 << 20)
> #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
> #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
> #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
> @@ -7392,6 +7395,11 @@ enum {
>GEN9_PIPE_PLANE3_FAULT | \
>GEN9_PIPE_PLANE2_FAULT | \
>GEN9_PIPE_PLANE1_FAULT)
> +#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
> + (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
> + GEN11_PIPE_PLANE7_FAULT | \
> + GEN11_PIPE_PLANE6_FAULT | \
> + GEN11_PIPE_PLANE5_FAULT)
>
> #define GEN8_DE_PORT_ISR _MMIO(0x0)
> #define GEN8_DE_PORT_IMR _MMIO(0x4)
___
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[Intel-gfx] [CI 2/2] drm/i915: Extract the GuC interrupt handlers
From: Andi Shyti
Pull the GuC interrupt handlers out of i915_irq.c. They now use the GT
interrupt facilities rather than the central dispatch.
Based on a patch by Chris Wilson.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 89
drivers/gpu/drm/i915/i915_irq.c| 93 --
drivers/gpu/drm/i915/i915_irq.h| 9 ---
3 files changed, 89 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 37f7bcbf7dac..f12959182182 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -4,6 +4,8 @@
*/
#include "gt/intel_gt.h"
+#include "gt/intel_gt_irq.h"
+#include "gt/intel_gt_pm_irq.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
@@ -77,6 +79,93 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
guc->send_regs.fw_domains = fw_domains;
}
+static void gen9_reset_guc_interrupts(struct intel_guc *guc)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ assert_rpm_wakelock_held(>i915->runtime_pm);
+
+ spin_lock_irq(>irq_lock);
+ gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
+ spin_unlock_irq(>irq_lock);
+}
+
+static void gen9_enable_guc_interrupts(struct intel_guc *guc)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ assert_rpm_wakelock_held(>i915->runtime_pm);
+
+ spin_lock_irq(>irq_lock);
+ if (!guc->interrupts.enabled) {
+ WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+gt->pm_guc_events);
+ guc->interrupts.enabled = true;
+ gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
+ }
+ spin_unlock_irq(>irq_lock);
+}
+
+static void gen9_disable_guc_interrupts(struct intel_guc *guc)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ assert_rpm_wakelock_held(>i915->runtime_pm);
+
+ spin_lock_irq(>irq_lock);
+ guc->interrupts.enabled = false;
+
+ gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
+
+ spin_unlock_irq(>irq_lock);
+ intel_synchronize_irq(gt->i915);
+
+ gen9_reset_guc_interrupts(guc);
+}
+
+static void gen11_reset_guc_interrupts(struct intel_guc *guc)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ spin_lock_irq(>irq_lock);
+ gen11_gt_reset_one_iir(gt, 0, GEN11_GUC);
+ spin_unlock_irq(>irq_lock);
+}
+
+static void gen11_enable_guc_interrupts(struct intel_guc *guc)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ spin_lock_irq(>irq_lock);
+ if (!guc->interrupts.enabled) {
+ u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
+
+ WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
+ intel_uncore_write(gt->uncore,
+ GEN11_GUC_SG_INTR_ENABLE, events);
+ intel_uncore_write(gt->uncore,
+ GEN11_GUC_SG_INTR_MASK, ~events);
+ guc->interrupts.enabled = true;
+ }
+ spin_unlock_irq(>irq_lock);
+}
+
+static void gen11_disable_guc_interrupts(struct intel_guc *guc)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ spin_lock_irq(>irq_lock);
+ guc->interrupts.enabled = false;
+
+ intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+ intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
+
+ spin_unlock_irq(>irq_lock);
+ intel_synchronize_irq(gt->i915);
+
+ gen11_reset_guc_interrupts(guc);
+}
+
void intel_guc_init_early(struct intel_guc *guc)
{
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 598924b3c556..eeea99a11b0c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -321,99 +321,6 @@ void ilk_update_display_irq(struct drm_i915_private
*dev_priv,
}
}
-static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
-{
- WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
-
- return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
-}
-
-void gen9_reset_guc_interrupts(struct intel_guc *guc)
-{
- struct intel_gt *gt = guc_to_gt(guc);
-
- assert_rpm_wakelock_held(gt->uncore->rpm);
-
- spin_lock_irq(>irq_lock);
- gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
- spin_unlock_irq(>irq_lock);
-}
-
-void gen9_enable_guc_interrupts(struct intel_guc *guc)
-{
- struct intel_gt *gt = guc_to_gt(guc);
-
- assert_rpm_wakelock_held(gt->uncore->rpm);
-
- spin_lock_irq(>irq_lock);
- if (!guc->interrupts.enabled) {
- WARN_ON_ONCE(intel_uncore_read(gt->uncore,
- gen6_pm_iir(gt->i915)) &
-gt->pm_guc_events);
- guc->interrupts.enabled =
Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Handle AUX interrupts for TC ports
On Thu, 2019-10-24 at 10:30 -0700, Matt Roper wrote:
> We're currently only processing AUX interrupts on the combo ports;
> make
> sure we handle the TC ports as well.
>
> v2: Drop stale comment
Reviewed-by: José Roberto de Souza
>
> Fixes: f663769a5eef ("drm/i915/tgl: initialize TC and TBT ports")
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_irq.c | 10 --
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index a048c79a6a55..2e67734a6d2a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2575,10 +2575,16 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
> u32 mask;
>
> if (INTEL_GEN(dev_priv) >= 12)
> - /* TODO: Add AUX entries for USBC */
> return TGL_DE_PORT_AUX_DDIA |
> TGL_DE_PORT_AUX_DDIB |
> - TGL_DE_PORT_AUX_DDIC;
> + TGL_DE_PORT_AUX_DDIC |
> + TGL_DE_PORT_AUX_USBC1 |
> + TGL_DE_PORT_AUX_USBC2 |
> + TGL_DE_PORT_AUX_USBC3 |
> + TGL_DE_PORT_AUX_USBC4 |
> + TGL_DE_PORT_AUX_USBC5 |
> + TGL_DE_PORT_AUX_USBC6;
> +
>
> mask = GEN8_AUX_CHANNEL_A;
> if (INTEL_GEN(dev_priv) >= 9)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 07cf67d42735..a7ba8100f13e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7436,6 +7436,12 @@ enum {
> #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
> #define BXT_DE_PORT_GMBUS (1 << 1)
> #define GEN8_AUX_CHANNEL_A (1 << 0)
> +#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
> +#define TGL_DE_PORT_AUX_USBC5 (1 << 12)
> +#define TGL_DE_PORT_AUX_USBC4 (1 << 11)
> +#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
> +#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
> +#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
> #define TGL_DE_PORT_AUX_DDIC(1 << 2)
> #define TGL_DE_PORT_AUX_DDIB(1 << 1)
> #define TGL_DE_PORT_AUX_DDIA(1 << 0)
___
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Re: [Intel-gfx] [PATCH V5 4/6] mdev: introduce virtio device and its device ops
On Thu, 24 Oct 2019 11:51:35 +0800
Jason Wang wrote:
> On 2019/10/24 上午5:57, Alex Williamson wrote:
> > On Wed, 23 Oct 2019 21:07:50 +0800
> > Jason Wang wrote:
> >
> >> This patch implements basic support for mdev driver that supports
> >> virtio transport for kernel virtio driver.
> >>
> >> Signed-off-by: Jason Wang
> >> ---
> >> drivers/vfio/mdev/mdev_core.c| 20
> >> drivers/vfio/mdev/mdev_private.h | 2 +
> >> include/linux/mdev.h | 6 ++
> >> include/linux/virtio_mdev_ops.h | 159 +++
> >> 4 files changed, 187 insertions(+)
> >> create mode 100644 include/linux/virtio_mdev_ops.h
> >>
> >> diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
> >> index 555bd61d8c38..9b00c3513120 100644
> >> --- a/drivers/vfio/mdev/mdev_core.c
> >> +++ b/drivers/vfio/mdev/mdev_core.c
> >> @@ -76,6 +76,26 @@ const struct vfio_mdev_device_ops
> >> *mdev_get_vfio_ops(struct mdev_device *mdev)
> >> }
> >> EXPORT_SYMBOL(mdev_get_vfio_ops);
> >>
> >> +/* Specify the virtio device ops for the mdev device, this
> >> + * must be called during create() callback for virtio mdev device.
> >> + */
> >> +void mdev_set_virtio_ops(struct mdev_device *mdev,
> >> + const struct virtio_mdev_device_ops *virtio_ops)
> >> +{
> >> + mdev_set_class(mdev, MDEV_CLASS_ID_VIRTIO);
> >> + mdev->virtio_ops = virtio_ops;
> >> +}
> >> +EXPORT_SYMBOL(mdev_set_virtio_ops);
> >> +
> >> +/* Get the virtio device ops for the mdev device. */
> >> +const struct virtio_mdev_device_ops *
> >> +mdev_get_virtio_ops(struct mdev_device *mdev)
> >> +{
> >> + WARN_ON(mdev->class_id != MDEV_CLASS_ID_VIRTIO);
> >> + return mdev->virtio_ops;
> >> +}
> >> +EXPORT_SYMBOL(mdev_get_virtio_ops);
> >> +
> >> struct device *mdev_dev(struct mdev_device *mdev)
> >> {
> >>return >dev;
> >> diff --git a/drivers/vfio/mdev/mdev_private.h
> >> b/drivers/vfio/mdev/mdev_private.h
> >> index 0770410ded2a..7b47890c34e7 100644
> >> --- a/drivers/vfio/mdev/mdev_private.h
> >> +++ b/drivers/vfio/mdev/mdev_private.h
> >> @@ -11,6 +11,7 @@
> >> #define MDEV_PRIVATE_H
> >>
> >> #include
> >> +#include
> >>
> >> int mdev_bus_register(void);
> >> void mdev_bus_unregister(void);
> >> @@ -38,6 +39,7 @@ struct mdev_device {
> >>u16 class_id;
> >>union {
> >>const struct vfio_mdev_device_ops *vfio_ops;
> >> + const struct virtio_mdev_device_ops *virtio_ops;
> >>};
> >> };
> >>
> >> diff --git a/include/linux/mdev.h b/include/linux/mdev.h
> >> index 4625f1a11014..9b69b0bbebfd 100644
> >> --- a/include/linux/mdev.h
> >> +++ b/include/linux/mdev.h
> >> @@ -17,6 +17,7 @@
> >>
> >> struct mdev_device;
> >> struct vfio_mdev_device_ops;
> >> +struct virtio_mdev_device_ops;
> >>
> >> /*
> >>* Called by the parent device driver to set the device which represents
> >> @@ -112,6 +113,10 @@ void mdev_set_class(struct mdev_device *mdev, u16 id);
> >> void mdev_set_vfio_ops(struct mdev_device *mdev,
> >> const struct vfio_mdev_device_ops *vfio_ops);
> >> const struct vfio_mdev_device_ops *mdev_get_vfio_ops(struct mdev_device
> >> *mdev);
> >> +void mdev_set_virtio_ops(struct mdev_device *mdev,
> >> + const struct virtio_mdev_device_ops *virtio_ops);
> >> +const struct virtio_mdev_device_ops *
> >> +mdev_get_virtio_ops(struct mdev_device *mdev);
> >>
> >> extern struct bus_type mdev_bus_type;
> >>
> >> @@ -127,6 +132,7 @@ struct mdev_device *mdev_from_dev(struct device *dev);
> >>
> >> enum {
> >>MDEV_CLASS_ID_VFIO = 1,
> >> + MDEV_CLASS_ID_VIRTIO = 2,
> >>/* New entries must be added here */
> >> };
> >>
> >> diff --git a/include/linux/virtio_mdev_ops.h
> >> b/include/linux/virtio_mdev_ops.h
> >> new file mode 100644
> >> index ..d417b41f2845
> >> --- /dev/null
> >> +++ b/include/linux/virtio_mdev_ops.h
> >> @@ -0,0 +1,159 @@
> >> +/* SPDX-License-Identifier: GPL-2.0-only */
> >> +/*
> >> + * Virtio mediated device driver
> >> + *
> >> + * Copyright 2019, Red Hat Corp.
> >> + * Author: Jason Wang
> >> + */
> >> +#ifndef _LINUX_VIRTIO_MDEV_H
> >> +#define _LINUX_VIRTIO_MDEV_H
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +
> >> +#define VIRTIO_MDEV_DEVICE_API_STRING "virtio-mdev"
> >> +#define VIRTIO_MDEV_F_VERSION_1 0x1
> >> +
> >> +struct virtio_mdev_callback {
> >> + irqreturn_t (*callback)(void *data);
> >> + void *private;
> >> +};
> >> +
> >> +/**
> >> + * struct vfio_mdev_device_ops - Structure to be registered for each
> >> + * mdev device to register the device for virtio/vhost drivers.
> >> + *
> >> + * The device ops that is supported by VIRTIO_MDEV_F_VERSION_1, the
> >> + * callbacks are mandatory unless explicity mentioned.
> > If the version of the callbacks is returned by a callback within the
> > structure defined by the version... isn't that a bit circular? This
> > seems redundant
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
== Series Details ==
Series: drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
URL : https://patchwork.freedesktop.org/series/68526/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7175 -> Patchwork_14971
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14971/index.html
Known issues
Here are the changes found in Patchwork_14971 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][1] -> [DMESG-WARN][2] ([fdo#102614])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14971/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-wait-default:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-icl-u3/igt@prime_v...@basic-wait-default.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14971/fi-icl-u3/igt@prime_v...@basic-wait-default.html
Possible fixes
* igt@gem_basic@create-close:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-icl-u3/igt@gem_ba...@create-close.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14971/fi-icl-u3/igt@gem_ba...@create-close.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [DMESG-FAIL][7] ([fdo#112050 ]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14971/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][9] ([fdo#111600]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14971/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [WARN][11] ([fdo#109483]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14971/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14971/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
[fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050
Participating hosts (51 -> 43)
--
Additional (1): fi-tgl-u
Missing(9): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7175 -> Patchwork_14971
CI-20190529: 20190529
CI_DRM_7175: 29ffd6b6aac24cdf361aa11a5a18e2ebc95b3180 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14971: ec048a07dfe678ac7728c210ed859f9c08a19efc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ec048a07dfe6 drm/i914/guc: Fix resume on platforms w/o GuC submission but
enabled
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14971/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for mdev based hardware virtio offloading support (rev6)
== Series Details ==
Series: mdev based hardware virtio offloading support (rev6)
URL : https://patchwork.freedesktop.org/series/66989/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7167_full -> Patchwork_14949_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14949_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14949_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14949_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_shared@q-promotion-bsd1:
- shard-iclb: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-iclb2/igt@gem_ctx_sha...@q-promotion-bsd1.html
- shard-apl: [PASS][2] -> [FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-apl2/igt@gem_ctx_sha...@q-promotion-bsd1.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-apl8/igt@gem_ctx_sha...@q-promotion-bsd1.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-skl: NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-skl10/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-contexts-render:
- shard-skl: [PASS][5] -> [FAIL][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-skl9/igt@gem_exec_sched...@preempt-queue-contexts-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-skl10/igt@gem_exec_sched...@preempt-queue-contexts-render.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_shared@q-promotion-bsd1:
- {shard-tglb}: [PASS][7] -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-tglb6/igt@gem_ctx_sha...@q-promotion-bsd1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-tglb4/igt@gem_ctx_sha...@q-promotion-bsd1.html
* igt@gem_persistent_relocs@forked-thrashing:
- {shard-tglb}: [PASS][9] -> [INCOMPLETE][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-tglb3/igt@gem_persistent_rel...@forked-thrashing.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-tglb1/igt@gem_persistent_rel...@forked-thrashing.html
Known issues
Here are the changes found in Patchwork_14949_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276] / [fdo#112080])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb1/igt@gem_ctx_isolat...@vcs1-dirty-create.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-iclb3/igt@gem_ctx_isolat...@vcs1-dirty-create.html
* igt@gem_exec_parallel@vcs1:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112080]) +3 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb2/igt@gem_exec_paral...@vcs1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-iclb6/igt@gem_exec_paral...@vcs1.html
* igt@gem_exec_schedule@preempt-bsd:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#111325])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-iclb5/igt@gem_exec_sched...@preempt-bsd.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-iclb1/igt@gem_exec_sched...@preempt-bsd.html
* igt@gem_exec_schedule@wide-blt:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-kbl6/igt@gem_exec_sched...@wide-blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-kbl6/igt@gem_exec_sched...@wide-blt.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-hsw7/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
* igt@i915_suspend@debugfs-reader:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108]) +1
similar issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/shard-skl8/igt@i915_susp...@debugfs-reader.html
[22]:
Re: [Intel-gfx] [PATCH 2/4] drm/i915: add new gen12 dgfx platform macro
On Thu, 2019-10-24 at 12:51 -0700, Lucas De Marchi wrote:
> From: Stuart Summers
>
> Add a new macro for GEN12 platforms to be grouped under dgfx feature
> set.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Stuart Summers
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_pci.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index f9a3bfe68689..04307e111f57 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -822,6 +822,10 @@ static const struct intel_device_info
> intel_tigerlake_12_info = {
> .has_rps = false, /* XXX disabled for debugging */
> };
>
> +#define GEN12_DGFX_FEATURES \
> + GEN12_FEATURES, \
> + .is_dgfx = 1
> +
> #undef GEN
> #undef PLATFORM
>
___
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Making loglevel of PSR2/SU logs same.
On Thu, 2019-10-24 at 00:35 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Making loglevel of PSR2/SU logs same.
> URL : https://patchwork.freedesktop.org/series/68439/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14940_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
Merged, thanks for the patch
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14940_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or
> statuses.
> They do not affect the overall result.
>
> * igt@gem_fence_thrash@bo-write-verify-threaded-y:
> - {shard-tglb}: [PASS][1] -> [INCOMPLETE][2] +1 similar
> issue
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb6/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-tglb4/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14940_full that come from
> known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_isolation@vcs1-none:
> - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] /
> [fdo#112080]) +1 similar issue
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@gem_ctx_isolat...@vcs1-none.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-iclb6/igt@gem_ctx_isolat...@vcs1-none.html
>
> * igt@gem_ctx_switch@vcs1:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +5
> similar issues
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@gem_ctx_swi...@vcs1.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-iclb6/igt@gem_ctx_swi...@vcs1.html
>
> * igt@gem_eio@reset-stress:
> - shard-snb: [PASS][7] -> [FAIL][8] ([fdo#109661])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb2/igt@gem_...@reset-stress.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-snb2/igt@gem_...@reset-stress.html
>
> * igt@gem_exec_reloc@basic-cpu-gtt-active:
> - shard-skl: [PASS][9] -> [DMESG-WARN][10]
> ([fdo#106107])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl6/igt@gem_exec_re...@basic-cpu-gtt-active.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-skl8/igt@gem_exec_re...@basic-cpu-gtt-active.html
>
> * igt@gem_exec_schedule@preempt-queue-bsd2:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +15
> similar issues
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd2.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-iclb5/igt@gem_exec_sched...@preempt-queue-bsd2.html
>
> * igt@gem_exec_schedule@preempt-self-bsd:
> - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#111325]) +3
> similar issues
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@gem_exec_sched...@preempt-self-bsd.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-iclb1/igt@gem_exec_sched...@preempt-self-bsd.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-busy:
> - shard-hsw: [PASS][15] -> [DMESG-WARN][16]
> ([fdo#111870]) +1 similar issue
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
> - shard-snb: [PASS][17] -> [DMESG-WARN][18]
> ([fdo#111870]) +1 similar issue
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-snb7/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
>
> * igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
> - shard-apl: [PASS][19] -> [INCOMPLETE][20]
> ([fdo#103927])
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl2/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-apl6/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
> - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#102670] /
> [fdo#106081])
>[21]:
>
Re: [Intel-gfx] [PATCH V5 1/6] mdev: class id support
On Thu, 24 Oct 2019 13:46:36 -0600
Alex Williamson wrote:
> On Thu, 24 Oct 2019 11:27:36 +0800
> Jason Wang wrote:
>
> > On 2019/10/24 上午5:42, Alex Williamson wrote:
> > > On Wed, 23 Oct 2019 21:07:47 +0800
> > > Jason Wang wrote:
> > >
> > >> Mdev bus only supports vfio driver right now, so it doesn't implement
> > >> match method. But in the future, we may add drivers other than vfio,
> > >> the first driver could be virtio-mdev. This means we need to add
> > >> device class id support in bus match method to pair the mdev device
> > >> and mdev driver correctly.
> > >>
> > >> So this patch adds id_table to mdev_driver and class_id for mdev
> > >> device with the match method for mdev bus.
> > >>
> > >> Signed-off-by: Jason Wang
> > >> ---
> > >> .../driver-api/vfio-mediated-device.rst | 5 +
> > >> drivers/gpu/drm/i915/gvt/kvmgt.c | 1 +
> > >> drivers/s390/cio/vfio_ccw_ops.c | 1 +
> > >> drivers/s390/crypto/vfio_ap_ops.c | 1 +
> > >> drivers/vfio/mdev/mdev_core.c | 18 +++
> > >> drivers/vfio/mdev/mdev_driver.c | 22 +++
> > >> drivers/vfio/mdev/mdev_private.h | 1 +
> > >> drivers/vfio/mdev/vfio_mdev.c | 6 +
> > >> include/linux/mdev.h | 8 +++
> > >> include/linux/mod_devicetable.h | 8 +++
> > >> samples/vfio-mdev/mbochs.c| 1 +
> > >> samples/vfio-mdev/mdpy.c | 1 +
> > >> samples/vfio-mdev/mtty.c | 1 +
> > >> 13 files changed, 74 insertions(+)
> > >>
> > >> diff --git a/Documentation/driver-api/vfio-mediated-device.rst
> > >> b/Documentation/driver-api/vfio-mediated-device.rst
> > >> index 25eb7d5b834b..6709413bee29 100644
> > >> --- a/Documentation/driver-api/vfio-mediated-device.rst
> > >> +++ b/Documentation/driver-api/vfio-mediated-device.rst
> > >> @@ -102,12 +102,14 @@ structure to represent a mediated device's driver::
> > >> * @probe: called when new device created
> > >> * @remove: called when device removed
> > >> * @driver: device driver structure
> > >> + * @id_table: the ids serviced by this driver
> > >> */
> > >>struct mdev_driver {
> > >> const char *name;
> > >> int (*probe) (struct device *dev);
> > >> void (*remove) (struct device *dev);
> > >> struct device_driverdriver;
> > >> + const struct mdev_class_id *id_table;
> > >>};
> > >>
> > >> A mediated bus driver for mdev should use this structure in the
> > >> function calls
> > >> @@ -170,6 +172,9 @@ that a driver should use to unregister itself with
> > >> the mdev core driver::
> > >>
> > >> extern void mdev_unregister_device(struct device *dev);
> > >>
> > >> +It is also required to specify the class_id in create() callback
> > >> through::
> > >> +
> > >> +int mdev_set_class(struct mdev_device *mdev, u16 id);
> > >>
> > >> Mediated Device Management Interface Through sysfs
> > >> ==
> > >> diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c
> > >> b/drivers/gpu/drm/i915/gvt/kvmgt.c
> > >> index 343d79c1cb7e..6420f0dbd31b 100644
> > >> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> > >> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> > >> @@ -678,6 +678,7 @@ static int intel_vgpu_create(struct kobject *kobj,
> > >> struct mdev_device *mdev)
> > >> dev_name(mdev_dev(mdev)));
> > >> ret = 0;
> > >>
> > >> +mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> > >> out:
> > >> return ret;
> > >> }
> > >> diff --git a/drivers/s390/cio/vfio_ccw_ops.c
> > >> b/drivers/s390/cio/vfio_ccw_ops.c
> > >> index f0d71ab77c50..cf2c013ae32f 100644
> > >> --- a/drivers/s390/cio/vfio_ccw_ops.c
> > >> +++ b/drivers/s390/cio/vfio_ccw_ops.c
> > >> @@ -129,6 +129,7 @@ static int vfio_ccw_mdev_create(struct kobject
> > >> *kobj, struct mdev_device *mdev)
> > >> private->sch->schid.ssid,
> > >> private->sch->schid.sch_no);
> > >>
> > >> +mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> > >> return 0;
> > >> }
> > >>
> > >> diff --git a/drivers/s390/crypto/vfio_ap_ops.c
> > >> b/drivers/s390/crypto/vfio_ap_ops.c
> > >> index 5c0f53c6dde7..07c31070afeb 100644
> > >> --- a/drivers/s390/crypto/vfio_ap_ops.c
> > >> +++ b/drivers/s390/crypto/vfio_ap_ops.c
> > >> @@ -343,6 +343,7 @@ static int vfio_ap_mdev_create(struct kobject *kobj,
> > >> struct mdev_device *mdev)
> > >> list_add(_mdev->node, _dev->mdev_list);
> > >> mutex_unlock(_dev->lock);
> > >>
> > >> +mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> > >> return 0;
> > >> }
> > >>
> > >> diff --git a/drivers/vfio/mdev/mdev_core.c
> > >>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Mock the engine sorting for easy validation
== Series Details ==
Series: drm/i915/selftests: Mock the engine sorting for easy validation
URL : https://patchwork.freedesktop.org/series/68521/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7175 -> Patchwork_14970
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14970/index.html
Known issues
Here are the changes found in Patchwork_14970 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-icl-u3/igt@gem_ctx_cre...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14970/fi-icl-u3/igt@gem_ctx_cre...@basic.html
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#109100])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14970/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
Possible fixes
* igt@gem_basic@create-close:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-icl-u3/igt@gem_ba...@create-close.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14970/fi-icl-u3/igt@gem_ba...@create-close.html
* igt@i915_selftest@live_client:
- fi-pnv-d510:[DMESG-WARN][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-pnv-d510/igt@i915_selftest@live_client.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14970/fi-pnv-d510/igt@i915_selftest@live_client.html
* igt@kms_chamelium@hdmi-edid-read:
- {fi-icl-u4}:[FAIL][9] ([fdo#111045]) -> [PASS][10] +1 similar
issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14970/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111407]) -> [FAIL][12] ([fdo#111045]
/ [fdo#111096])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14970/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
Participating hosts (51 -> 45)
--
Additional (1): fi-tgl-u
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7175 -> Patchwork_14970
CI-20190529: 20190529
CI_DRM_7175: 29ffd6b6aac24cdf361aa11a5a18e2ebc95b3180 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14970: 96ce4ba1e34216970739c95417740775868781ae @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
96ce4ba1e342 drm/i915/selftests: Mock the engine sorting for easy validation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14970/index.html
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Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
> On Thu, 2019-10-24 at 09:29 -0700, don.hi...@intel.com wrote:
> > From: Don Hiatt
> >
> > Check to see if GuC submission is enabled before requesting the
> > EXIT_S_STATE action.
> >
> > On some platforms (e.g. KBL) that do not support GuC submission, but
> > the user enabled the GuC communication (e.g for HuC authentication)
> > calling the GuC EXIT_S_STATE action results in lose of ability to
> > enter RC6. Guard against this by only requesting the GuC action on
> > platforms that support GuC submission.
> >
> > I've verfied that intel_guc_resume() only gets called when driver
> > is loaded with: guc_enable={1,2,3}, all other cases (no args,
> > guc_enable={0,-1} the intel_guc_resume() is not called.
> >
> > Signed-off-by: Don Hiatt
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > index 37f7bcbf7dac..33318ed135c0 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > @@ -565,7 +565,10 @@ int intel_guc_resume(struct intel_guc *guc)
> > GUC_POWER_D0,
> > };
> >
> > - return intel_guc_send(guc, action, ARRAY_SIZE(action));
> > + if (guc->submission_supported)
>
> Hey Don,
>
> I might be missing something here, but glancing over the code for
> submission_supported, it looks like this relies on the availability of
> the firmware for the intended platform. Looking at the GuC table for
> KBL, I do see this present (using KBL per your commit above). So
> wouldn't this return true here if enable_guc is set to 1 or 3?
>
> Thanks,
> Stuart
Hi Stuart,
KBL does not support GuC submission, just HuC authentication. I've instrumented
the code and verified that all guc->submission_supported is always false when
guc_enable
is set for KBL.
Thanks,
don
>
> > + return intel_guc_send(guc, action, ARRAY_SIZE(action));
> > +
> > + return 0;
> > }
> >
> > /**
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [RFC,1/5] drm/i915: Drop GEM context as a direct link from i915_request
== Series Details == Series: series starting with [RFC,1/5] drm/i915: Drop GEM context as a direct link from i915_request URL : https://patchwork.freedesktop.org/series/68520/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7175 -> Patchwork_14969 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14969 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14969, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14969: ### IGT changes ### Possible regressions * igt@i915_module_load@reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-byt-j1900/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-byt-j1900/igt@i915_module_l...@reload.html - fi-snb-2520m: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-snb-2520m/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-snb-2520m/igt@i915_module_l...@reload.html - fi-hsw-4770:[PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-hsw-4770/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-hsw-4770/igt@i915_module_l...@reload.html - fi-ivb-3770:[PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-ivb-3770/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-ivb-3770/igt@i915_module_l...@reload.html - fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-hsw-peppy/igt@i915_module_l...@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-hsw-peppy/igt@i915_module_l...@reload.html - fi-byt-n2820: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-byt-n2820/igt@i915_module_l...@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-byt-n2820/igt@i915_module_l...@reload.html - fi-snb-2600:[PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-snb-2600/igt@i915_module_l...@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-snb-2600/igt@i915_module_l...@reload.html * igt@i915_selftest@live_gt_contexts: - fi-bsw-kefka: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-bsw-kefka/igt@i915_selftest@live_gt_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-bsw-kefka/igt@i915_selftest@live_gt_contexts.html - fi-bsw-n3050: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-bsw-n3050/igt@i915_selftest@live_gt_contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-bsw-n3050/igt@i915_selftest@live_gt_contexts.html * igt@i915_selftest@live_reset: - fi-bsw-n3050: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-bsw-n3050/igt@i915_selftest@live_reset.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-bsw-n3050/igt@i915_selftest@live_reset.html - fi-bsw-kefka: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7175/fi-bsw-kefka/igt@i915_selftest@live_reset.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14969/fi-bsw-kefka/igt@i915_selftest@live_reset.html Participating hosts (51 -> 9) -- ERROR: It appears as if the changes made in Patchwork_14969 prevented too many machines from booting. Missing(42): fi-kbl-soraka fi-skl-6770hq fi-bdw-gvtdvm fi-icl-u2 fi-apl-guc fi-icl-u3 fi-pnv-d510 fi-icl-y fi-skl-lmem fi-blb-e6850 fi-icl-guc fi-icl-dsi fi-skl-6600u fi-cml-u2 fi-icl-u4 fi-bxt-dsi fi-bdw-5557u fi-cml-s fi-tgl-u2 fi-glk-dsi fi-bwr-2160 fi-ilk-650 fi-kbl-7500u fi-gdg-551 fi-elk-e7500 fi-skl-6700k2 fi-kbl-r fi-ilk-m540 fi-skl-guc fi-cfl-8700k fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-whl-u fi-kbl-x1275 fi-cfl-8109u fi-skl-iommu fi-kbl-8809g fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7175 -> Patchwork_14969 CI-20190529: 20190529 CI_DRM_7175:
Re: [Intel-gfx] [PATCH 4/4] drm/i915: split gen11_irq_handler to make it shareable
On Thu, Oct 24, 2019 at 12:51:22PM -0700, Lucas De Marchi wrote:
Split gen11_irq_handler() to receive as parameter the function
pointers. This allows to share the interrupt handler even if the enable/disable
functions are different.
Make sure it's always inlined to avoid the extra indirect call on the
hot path. Checking with gcc 9 this produce the exact same code as of
now:
$ size drivers/gpu/drm/i915/i915_irq*.o
text data bss dec hex filename
47511 560 0 48071bbc7 drivers/gpu/drm/i915/i915_irq.o
47511 560 0 48071bbc7 drivers/gpu/drm/i915/i915_irq_new.o
$ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq.o' -ex 'disassemble
gen11_irq_handler' > /tmp/old.s
$ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq_new.o' -ex 'disassemble
gen11_irq_handler' > /tmp/new.s
$ git diff --no-index /tmp/{old,new}.s
$
So, no change in behavior, just a simple refactor.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 572a5c37cc61..8eb7d02b4a55 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2859,9 +2859,11 @@ static inline void gen11_master_intr_enable(void __iomem
* const regs)
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
}
-static irqreturn_t gen11_irq_handler(int irq, void *arg)
+static __always_inline irqreturn_t
+__gen11_irq_handler(struct drm_i915_private * const i915,
+ u32 (*intr_disable)(void __iomem * const regs),
+ void (*intr_enable)(void __iomem * const regs))
offline review from Chris:
Hmm. __always_inline indeed should avoid the compiler using vfuncs here,
no matter how may times we use the same base handler.
Reviewed-by: Chris Wilson
Lucas De Marchi
{
- struct drm_i915_private * const i915 = arg;
void __iomem * const regs = i915->uncore.regs;
struct intel_gt *gt = >gt;
u32 master_ctl;
@@ -2870,9 +2872,9 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
if (!intel_irqs_enabled(i915))
return IRQ_NONE;
- master_ctl = gen11_master_intr_disable(regs);
+ master_ctl = intr_disable(regs);
if (!master_ctl) {
- gen11_master_intr_enable(regs);
+ intr_enable(regs);
return IRQ_NONE;
}
@@ -2894,13 +2896,20 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
- gen11_master_intr_enable(regs);
+ intr_enable(regs);
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
return IRQ_HANDLED;
}
+static irqreturn_t gen11_irq_handler(int irq, void *arg)
+{
+ return __gen11_irq_handler(arg,
+ gen11_master_intr_disable,
+ gen11_master_intr_enable);
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
--
2.23.0
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Re: [Intel-gfx] [PATCH 2/4] drm/i915: add new gen12 dgfx platform macro
On Thu, Oct 24, 2019 at 12:51:20PM -0700, Lucas De Marchi wrote:
From: Stuart Summers
Add a new macro for GEN12 platforms to be grouped under dgfx feature
set.
Signed-off-by: Stuart Summers
Signed-off-by: Lucas De Marchi
this should actually be
Signed-off-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f9a3bfe68689..04307e111f57 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -822,6 +822,10 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
.has_rps = false, /* XXX disabled for debugging */
};
+#define GEN12_DGFX_FEATURES \
+ GEN12_FEATURES, \
+ .is_dgfx = 1
+
#undef GEN
#undef PLATFORM
--
2.23.0
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Re: [Intel-gfx] [PATCH V5 2/6] modpost: add support for mdev class id
On Thu, 24 Oct 2019 11:31:04 +0800
Jason Wang wrote:
> On 2019/10/24 上午5:42, Alex Williamson wrote:
> > On Wed, 23 Oct 2019 21:07:48 +0800
> > Jason Wang wrote:
> >
> >> Add support to parse mdev class id table.
> >>
> >> Reviewed-by: Parav Pandit
> >> Signed-off-by: Jason Wang
> >> ---
> >> drivers/vfio/mdev/vfio_mdev.c | 2 ++
> >> scripts/mod/devicetable-offsets.c | 3 +++
> >> scripts/mod/file2alias.c | 10 ++
> >> 3 files changed, 15 insertions(+)
> >>
> >> diff --git a/drivers/vfio/mdev/vfio_mdev.c b/drivers/vfio/mdev/vfio_mdev.c
> >> index 7b24ee9cb8dd..cb701cd646f0 100644
> >> --- a/drivers/vfio/mdev/vfio_mdev.c
> >> +++ b/drivers/vfio/mdev/vfio_mdev.c
> >> @@ -125,6 +125,8 @@ static const struct mdev_class_id id_table[] = {
> >>{ 0 },
> >> };
> >>
> >> +MODULE_DEVICE_TABLE(mdev, id_table);
> >> +
> > Two questions, first we have:
> >
> > #define MODULE_DEVICE_TABLE(type, name) \
> > extern typeof(name) __mod_##type##__##name##_device_table \
> >__attribute__ ((unused, alias(__stringify(name
> >
> > Therefore we're defining __mod_mdev__id_table_device_table with alias
> > id_table. When the virtio mdev bus driver is added in 5/6 it uses the
> > same name value. I see virtio types all register this way (virtio,
> > id_table), so I assume there's no conflict, but pci types mostly (not
> > entirely) seem to use unique names. Is there a preference to one way
> > or the other or it simply doesn't matter?
>
>
> It looks to me that those symbol were local, so it doesn't matter. But
> if you wish I can switch to use unique name.
I don't have a strong opinion, I'm just trying to make sure we're not
doing something obviously broken.
> >> static struct mdev_driver vfio_mdev_driver = {
> >>.name = "vfio_mdev",
> >>.probe = vfio_mdev_probe,
> >> diff --git a/scripts/mod/devicetable-offsets.c
> >> b/scripts/mod/devicetable-offsets.c
> >> index 054405b90ba4..6cbb1062488a 100644
> >> --- a/scripts/mod/devicetable-offsets.c
> >> +++ b/scripts/mod/devicetable-offsets.c
> >> @@ -231,5 +231,8 @@ int main(void)
> >>DEVID(wmi_device_id);
> >>DEVID_FIELD(wmi_device_id, guid_string);
> >>
> >> + DEVID(mdev_class_id);
> >> + DEVID_FIELD(mdev_class_id, id);
> >> +
> >>return 0;
> >> }
> >> diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
> >> index c91eba751804..d365dfe7c718 100644
> >> --- a/scripts/mod/file2alias.c
> >> +++ b/scripts/mod/file2alias.c
> >> @@ -1335,6 +1335,15 @@ static int do_wmi_entry(const char *filename, void
> >> *symval, char *alias)
> >>return 1;
> >> }
> >>
> >> +/* looks like: "mdev:cN" */
> >> +static int do_mdev_entry(const char *filename, void *symval, char *alias)
> >> +{
> >> + DEF_FIELD(symval, mdev_class_id, id);
> >> +
> >> + sprintf(alias, "mdev:c%02X", id);
> > A lot of entries call add_wildcard() here, should we? Sorry for the
> > basic questions, I haven't played in this code. Thanks,
>
>
> It's really good question. My understanding is we won't have a module
> that can deal with all kinds of classes like CLASS_ID_ANY. So there's
> probably no need for the wildcard.
The comment for add_wildcard() indicates future extension, so it's hard
to know what we might need in the future until we do need it. The
majority of modules.alias entries on my laptop (even if I exclude pci
aliases) end with a wildcard. Thanks,
Alex
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[Intel-gfx] [PATCH 1/4] drm/i915: Add is_dgfx to device info
From: José Roberto de Souza
This will be helpful to diferentiate a set of GPUs
with the same GEN version.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 674e9e921839..12646b94af87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1544,6 +1544,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
}
#define IS_MOBILE(dev_priv)(INTEL_INFO(dev_priv)->is_mobile)
+#define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index e9940f932d26..78a383f63957 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -107,6 +107,7 @@ enum intel_ppgtt_type {
func(is_mobile); \
func(is_lp); \
func(require_force_probe); \
+ func(is_dgfx); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(gpu_reset_clobbers_display); \
--
2.23.0
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[Intel-gfx] [PATCH 2/4] drm/i915: add new gen12 dgfx platform macro
From: Stuart Summers
Add a new macro for GEN12 platforms to be grouped under dgfx feature
set.
Signed-off-by: Stuart Summers
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f9a3bfe68689..04307e111f57 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -822,6 +822,10 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
.has_rps = false, /* XXX disabled for debugging */
};
+#define GEN12_DGFX_FEATURES \
+ GEN12_FEATURES, \
+ .is_dgfx = 1
+
#undef GEN
#undef PLATFORM
--
2.23.0
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[Intel-gfx] [PATCH 4/4] drm/i915: split gen11_irq_handler to make it shareable
Split gen11_irq_handler() to receive as parameter the function
pointers. This allows to share the interrupt handler even if the enable/disable
functions are different.
Make sure it's always inlined to avoid the extra indirect call on the
hot path. Checking with gcc 9 this produce the exact same code as of
now:
$ size drivers/gpu/drm/i915/i915_irq*.o
textdata bss dec hex filename
47511 560 0 48071bbc7 drivers/gpu/drm/i915/i915_irq.o
47511 560 0 48071bbc7 drivers/gpu/drm/i915/i915_irq_new.o
$ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq.o' -ex 'disassemble
gen11_irq_handler' > /tmp/old.s
$ gdb -batch -ex 'file drivers/gpu/drm/i915/i915_irq_new.o' -ex 'disassemble
gen11_irq_handler' > /tmp/new.s
$ git diff --no-index /tmp/{old,new}.s
$
So, no change in behavior, just a simple refactor.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 572a5c37cc61..8eb7d02b4a55 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2859,9 +2859,11 @@ static inline void gen11_master_intr_enable(void __iomem
* const regs)
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
}
-static irqreturn_t gen11_irq_handler(int irq, void *arg)
+static __always_inline irqreturn_t
+__gen11_irq_handler(struct drm_i915_private * const i915,
+ u32 (*intr_disable)(void __iomem * const regs),
+ void (*intr_enable)(void __iomem * const regs))
{
- struct drm_i915_private * const i915 = arg;
void __iomem * const regs = i915->uncore.regs;
struct intel_gt *gt = >gt;
u32 master_ctl;
@@ -2870,9 +2872,9 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
if (!intel_irqs_enabled(i915))
return IRQ_NONE;
- master_ctl = gen11_master_intr_disable(regs);
+ master_ctl = intr_disable(regs);
if (!master_ctl) {
- gen11_master_intr_enable(regs);
+ intr_enable(regs);
return IRQ_NONE;
}
@@ -2894,13 +2896,20 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
- gen11_master_intr_enable(regs);
+ intr_enable(regs);
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
return IRQ_HANDLED;
}
+static irqreturn_t gen11_irq_handler(int irq, void *arg)
+{
+ return __gen11_irq_handler(arg,
+ gen11_master_intr_disable,
+ gen11_master_intr_enable);
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/i915: do not set MOCS control values on dgfx
On dgfx there's no LLC and eDRAM control table. Since now this also means the device has global MOCS, just return early on the initialization function. L3 settings still apply and still need to be tweaked. Bspec: 45101 Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_mocs.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 932833e5b712..9e19637e0225 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -462,6 +462,12 @@ static void intel_mocs_init_global(struct intel_gt *gt) struct drm_i915_mocs_table table; unsigned int index; + /* +* LLC and eDRAM control values are not only applicable to dgfx +*/ + if (IS_DGFX(gt->i915)) + return; + GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915)); if (!get_mocs_settings(gt->i915, )) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Mock the engine sorting for easy validation
== Series Details == Series: drm/i915/selftests: Mock the engine sorting for easy validation URL : https://patchwork.freedesktop.org/series/68521/ State : warning == Summary == $ dim checkpatch origin/drm-tip 96ce4ba1e342 drm/i915/selftests: Mock the engine sorting for easy validation -:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #27: new file mode 100644 -:32: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #32: FILE: drivers/gpu/drm/i915/gt/selftest_engine_user.c:1: +/* -:33: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #33: FILE: drivers/gpu/drm/i915/gt/selftest_engine_user.c:2: + * SPDX-License-Identifier: MIT total: 0 errors, 3 warnings, 0 checks, 102 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V5 1/6] mdev: class id support
On Thu, 24 Oct 2019 11:27:36 +0800
Jason Wang wrote:
> On 2019/10/24 上午5:42, Alex Williamson wrote:
> > On Wed, 23 Oct 2019 21:07:47 +0800
> > Jason Wang wrote:
> >
> >> Mdev bus only supports vfio driver right now, so it doesn't implement
> >> match method. But in the future, we may add drivers other than vfio,
> >> the first driver could be virtio-mdev. This means we need to add
> >> device class id support in bus match method to pair the mdev device
> >> and mdev driver correctly.
> >>
> >> So this patch adds id_table to mdev_driver and class_id for mdev
> >> device with the match method for mdev bus.
> >>
> >> Signed-off-by: Jason Wang
> >> ---
> >> .../driver-api/vfio-mediated-device.rst | 5 +
> >> drivers/gpu/drm/i915/gvt/kvmgt.c | 1 +
> >> drivers/s390/cio/vfio_ccw_ops.c | 1 +
> >> drivers/s390/crypto/vfio_ap_ops.c | 1 +
> >> drivers/vfio/mdev/mdev_core.c | 18 +++
> >> drivers/vfio/mdev/mdev_driver.c | 22 +++
> >> drivers/vfio/mdev/mdev_private.h | 1 +
> >> drivers/vfio/mdev/vfio_mdev.c | 6 +
> >> include/linux/mdev.h | 8 +++
> >> include/linux/mod_devicetable.h | 8 +++
> >> samples/vfio-mdev/mbochs.c| 1 +
> >> samples/vfio-mdev/mdpy.c | 1 +
> >> samples/vfio-mdev/mtty.c | 1 +
> >> 13 files changed, 74 insertions(+)
> >>
> >> diff --git a/Documentation/driver-api/vfio-mediated-device.rst
> >> b/Documentation/driver-api/vfio-mediated-device.rst
> >> index 25eb7d5b834b..6709413bee29 100644
> >> --- a/Documentation/driver-api/vfio-mediated-device.rst
> >> +++ b/Documentation/driver-api/vfio-mediated-device.rst
> >> @@ -102,12 +102,14 @@ structure to represent a mediated device's driver::
> >> * @probe: called when new device created
> >> * @remove: called when device removed
> >> * @driver: device driver structure
> >> + * @id_table: the ids serviced by this driver
> >> */
> >>struct mdev_driver {
> >> const char *name;
> >> int (*probe) (struct device *dev);
> >> void (*remove) (struct device *dev);
> >> struct device_driverdriver;
> >> + const struct mdev_class_id *id_table;
> >>};
> >>
> >> A mediated bus driver for mdev should use this structure in the function
> >> calls
> >> @@ -170,6 +172,9 @@ that a driver should use to unregister itself with the
> >> mdev core driver::
> >>
> >>extern void mdev_unregister_device(struct device *dev);
> >>
> >> +It is also required to specify the class_id in create() callback through::
> >> +
> >> + int mdev_set_class(struct mdev_device *mdev, u16 id);
> >>
> >> Mediated Device Management Interface Through sysfs
> >> ==
> >> diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c
> >> b/drivers/gpu/drm/i915/gvt/kvmgt.c
> >> index 343d79c1cb7e..6420f0dbd31b 100644
> >> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> >> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> >> @@ -678,6 +678,7 @@ static int intel_vgpu_create(struct kobject *kobj,
> >> struct mdev_device *mdev)
> >> dev_name(mdev_dev(mdev)));
> >>ret = 0;
> >>
> >> + mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> >> out:
> >>return ret;
> >> }
> >> diff --git a/drivers/s390/cio/vfio_ccw_ops.c
> >> b/drivers/s390/cio/vfio_ccw_ops.c
> >> index f0d71ab77c50..cf2c013ae32f 100644
> >> --- a/drivers/s390/cio/vfio_ccw_ops.c
> >> +++ b/drivers/s390/cio/vfio_ccw_ops.c
> >> @@ -129,6 +129,7 @@ static int vfio_ccw_mdev_create(struct kobject *kobj,
> >> struct mdev_device *mdev)
> >> private->sch->schid.ssid,
> >> private->sch->schid.sch_no);
> >>
> >> + mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> >>return 0;
> >> }
> >>
> >> diff --git a/drivers/s390/crypto/vfio_ap_ops.c
> >> b/drivers/s390/crypto/vfio_ap_ops.c
> >> index 5c0f53c6dde7..07c31070afeb 100644
> >> --- a/drivers/s390/crypto/vfio_ap_ops.c
> >> +++ b/drivers/s390/crypto/vfio_ap_ops.c
> >> @@ -343,6 +343,7 @@ static int vfio_ap_mdev_create(struct kobject *kobj,
> >> struct mdev_device *mdev)
> >>list_add(_mdev->node, _dev->mdev_list);
> >>mutex_unlock(_dev->lock);
> >>
> >> + mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> >>return 0;
> >> }
> >>
> >> diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
> >> index b558d4cfd082..3a9c52d71b4e 100644
> >> --- a/drivers/vfio/mdev/mdev_core.c
> >> +++ b/drivers/vfio/mdev/mdev_core.c
> >> @@ -45,6 +45,16 @@ void mdev_set_drvdata(struct mdev_device *mdev, void
> >> *data)
> >> }
> >> EXPORT_SYMBOL(mdev_set_drvdata);
> >>
> >> +/* Specify the class for the mdev device, this must be called during
> >> + * create() callback.
> >> + */
> >> +void
Re: [Intel-gfx] [PATCH] drm: Add support for integrated privacy screens
Hi Rajat, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on linus/master] [cannot apply to v5.4-rc4 next-20191024] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Rajat-Jain/drm-Add-support-for-integrated-privacy-screens/20191025-020550 base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git f116b96685a046a89c25d4a6ba2da489145c reproduce: make htmldocs If you fix the issue, kindly add following tag Reported-by: kbuild test robot All warnings (new ones prefixed by >>): include/linux/input/sparse-keymap.h:43: warning: Function parameter or member 'sw' not described in 'key_entry' include/linux/skbuff.h:888: warning: Function parameter or member 'dev_scratch' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'list' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'ip_defrag_offset' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'skb_mstamp_ns' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member '__cloned_offset' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'head_frag' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member '__pkt_type_offset' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'encapsulation' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'encap_hdr_csum' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'csum_valid' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member '__pkt_vlan_present_offset' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'vlan_present' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'csum_complete_sw' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'csum_level' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'inner_protocol_type' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'remcsum_offload' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'sender_cpu' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'reserved_tailroom' not described in 'sk_buff' include/linux/skbuff.h:888: warning: Function parameter or member 'inner_ipproto' not described in 'sk_buff' include/net/sock.h:233: warning: Function parameter or member 'skc_addrpair' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_portpair' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_ipv6only' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_net_refcnt' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_v6_daddr' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_v6_rcv_saddr' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_cookie' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_listener' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_tw_dr' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_rcv_wnd' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_tw_rcv_nxt' not described in 'sock_common' include/net/sock.h:515: warning: Function parameter or member 'sk_rx_skb_cache' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_wq_raw' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'tcp_rtx_queue' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_tx_skb_cache' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_route_forced_caps' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_txtime_report_errors' not described in 'sock' include/net/sock.h:515: warning: Function par
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [RFC,1/5] drm/i915: Drop GEM context as a direct link from i915_request
== Series Details == Series: series starting with [RFC,1/5] drm/i915: Drop GEM context as a direct link from i915_request URL : https://patchwork.freedesktop.org/series/68520/ State : warning == Summary == $ dim checkpatch origin/drm-tip 51d5bce1245c drm/i915: Drop GEM context as a direct link from i915_request 0049df987a24 drm/i915: Push the use-semaphore marker onto the intel_context cdbf6fda2381 drm/i915: Remove i915->kernel_context e4c1cb1a3d7f drm/i915: Drop GEM context reference while pinned 8d4d6ce1978c drm/i915: No ce->gem_context for kernel_context -:958: WARNING:LONG_LINE: line over 100 characters #958: FILE: drivers/gpu/drm/i915/i915_request.c:76: + return to_request(fence)->context ? to_request(fence)->context->gem_context->name : "[i915]"; total: 0 errors, 1 warnings, 0 checks, 859 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/14] drm/i915: Rework watermark readout to use plane api
== Series Details == Series: series starting with [01/14] drm/i915: Rework watermark readout to use plane api URL : https://patchwork.freedesktop.org/series/68519/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7174 -> Patchwork_14968 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14968 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14968, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14968: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html - fi-kbl-r: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html - fi-byt-n2820: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-byt-n2820/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-byt-n2820/igt@gem_exec_susp...@basic-s3.html - fi-snb-2600:[PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html - fi-ilk-650: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-ilk-650/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-ilk-650/igt@gem_exec_susp...@basic-s3.html - fi-elk-e7500: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-elk-e7500/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-elk-e7500/igt@gem_exec_susp...@basic-s3.html - fi-bdw-gvtdvm: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s3.html - fi-glk-dsi: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-glk-dsi/igt@gem_exec_susp...@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-glk-dsi/igt@gem_exec_susp...@basic-s3.html - fi-snb-2520m: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-snb-2520m/igt@gem_exec_susp...@basic-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-snb-2520m/igt@gem_exec_susp...@basic-s3.html - fi-pnv-d510:NOTRUN -> [DMESG-WARN][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-pnv-d510/igt@gem_exec_susp...@basic-s3.html - fi-kbl-x1275: [PASS][20] -> [DMESG-WARN][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-kbl-x1275/igt@gem_exec_susp...@basic-s3.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-kbl-x1275/igt@gem_exec_susp...@basic-s3.html - fi-kbl-soraka: [PASS][22] -> [DMESG-WARN][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-kbl-soraka/igt@gem_exec_susp...@basic-s3.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-kbl-soraka/igt@gem_exec_susp...@basic-s3.html - fi-bxt-dsi: [PASS][24] -> [DMESG-WARN][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-bxt-dsi/igt@gem_exec_susp...@basic-s3.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-bxt-dsi/igt@gem_exec_susp...@basic-s3.html - fi-cml-u2: [PASS][26] -> [DMESG-WARN][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-cml-u2/igt@gem_exec_susp...@basic-s3.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14968/fi-cml-u2/igt@gem_exec_susp...@basic-s3.html - fi-bsw-n3050: [PASS][28] -> [DMESG-WARN][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-bsw-n3050/igt@gem_exec_susp...@basic-s3.html [29]:
Re: [Intel-gfx] [PATCH] drm: Add support for integrated privacy screens
Hi Rajat,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[cannot apply to v5.4-rc4 next-20191024]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Rajat-Jain/drm-Add-support-for-integrated-privacy-screens/20191025-020550
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
f116b96685a046a89c25d4a6ba2da489145c
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All warnings (new ones prefixed by >>):
In file included from include/linux/printk.h:7:0,
from include/linux/kernel.h:15,
from include/linux/list.h:9,
from include/linux/kobject.h:19,
from include/linux/of.h:17,
from include/linux/irqdomain.h:35,
from include/linux/acpi.h:13,
from drivers/gpu//drm/drm_privacy_screen.c:8:
drivers/gpu//drm/drm_privacy_screen.c: In function
'drm_privacy_screen_present':
>> include/linux/kern_levels.h:5:18: warning: format '%s' expects argument of
>> type 'char *', but argument 2 has type 'struct device *' [-Wformat=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:12:22: note: in expansion of macro 'KERN_SOH'
#define KERN_WARNING KERN_SOH "4" /* warning conditions */
^~~~
>> include/drm/drm_print.h:290:15: note: in expansion of macro 'KERN_WARNING'
printk##once(KERN_##level "[" DRM_NAME "] " fmt, ##__VA_ARGS__)
^
include/drm/drm_print.h:297:2: note: in expansion of macro '_DRM_PRINTK'
_DRM_PRINTK(, WARNING, fmt, ##__VA_ARGS__)
^~~
>> drivers/gpu//drm/drm_privacy_screen.c:170:3: note: in expansion of macro
>> 'DRM_WARN'
DRM_WARN("%s: Odd, connector ACPI node but no privacy scrn?\n",
^~~~
drivers/gpu//drm/drm_privacy_screen.c:170:14: note: format string is defined
here
DRM_WARN("%s: Odd, connector ACPI node but no privacy scrn?\n",
~^
--
In file included from include/linux/printk.h:7:0,
from include/linux/kernel.h:15,
from include/linux/list.h:9,
from include/linux/kobject.h:19,
from include/linux/of.h:17,
from include/linux/irqdomain.h:35,
from include/linux/acpi.h:13,
from drivers/gpu/drm/drm_privacy_screen.c:8:
drivers/gpu/drm/drm_privacy_screen.c: In function
'drm_privacy_screen_present':
>> include/linux/kern_levels.h:5:18: warning: format '%s' expects argument of
>> type 'char *', but argument 2 has type 'struct device *' [-Wformat=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:12:22: note: in expansion of macro 'KERN_SOH'
#define KERN_WARNING KERN_SOH "4" /* warning conditions */
^~~~
>> include/drm/drm_print.h:290:15: note: in expansion of macro 'KERN_WARNING'
printk##once(KERN_##level "[" DRM_NAME "] " fmt, ##__VA_ARGS__)
^
include/drm/drm_print.h:297:2: note: in expansion of macro '_DRM_PRINTK'
_DRM_PRINTK(, WARNING, fmt, ##__VA_ARGS__)
^~~
drivers/gpu/drm/drm_privacy_screen.c:170:3: note: in expansion of macro
'DRM_WARN'
DRM_WARN("%s: Odd, connector ACPI node but no privacy scrn?\n",
^~~~
drivers/gpu/drm/drm_privacy_screen.c:170:14: note: format string is defined
here
DRM_WARN("%s: Odd, connector ACPI node but no privacy scrn?\n",
~^
vim +/KERN_WARNING +290 include/drm/drm_print.h
02c9656b2f0d69 Haneen Mohammed 2017-10-17 288
02c9656b2f0d69 Haneen Mohammed 2017-10-17 289 #define _DRM_PRINTK(once,
level, fmt, ...) \
db87086492581c Joe Perches 2018-03-16 @290
printk##once(KERN_##level "[" DRM_NAME "] " fmt, ##__VA_ARGS__)
02c9656b2f0d69 Haneen Mohammed 2017-10-17 291
:: The code at line 290 was first introduced by commit
:: db87086492581c87f768b7d17d01308153ecffc1 drm: Reduce object size of
DRM_DEV_ uses
:: TO: Joe Perches
:: CC: Daniel Vetter
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbui
Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
On Thu, 2019-10-24 at 09:29 -0700, don.hi...@intel.com wrote:
> From: Don Hiatt
>
> Check to see if GuC submission is enabled before requesting the
> EXIT_S_STATE action.
>
> On some platforms (e.g. KBL) that do not support GuC submission, but
> the user enabled the GuC communication (e.g for HuC authentication)
> calling the GuC EXIT_S_STATE action results in lose of ability to
> enter RC6. Guard against this by only requesting the GuC action on
> platforms that support GuC submission.
>
> I've verfied that intel_guc_resume() only gets called when driver
> is loaded with: guc_enable={1,2,3}, all other cases (no args,
> guc_enable={0,-1} the intel_guc_resume() is not called.
>
> Signed-off-by: Don Hiatt
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 37f7bcbf7dac..33318ed135c0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -565,7 +565,10 @@ int intel_guc_resume(struct intel_guc *guc)
> GUC_POWER_D0,
> };
>
> - return intel_guc_send(guc, action, ARRAY_SIZE(action));
> + if (guc->submission_supported)
Hey Don,
I might be missing something here, but glancing over the code for
submission_supported, it looks like this relies on the availability of
the firmware for the intended platform. Looking at the GuC table for
KBL, I do see this present (using KBL per your commit above). So
wouldn't this return true here if enable_guc is set to 1 or 3?
Thanks,
Stuart
> + return intel_guc_send(guc, action, ARRAY_SIZE(action));
> +
> + return 0;
> }
>
> /**
smime.p7s
Description: S/MIME cryptographic signature
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/14] drm/i915: Rework watermark readout to use plane api
== Series Details ==
Series: series starting with [01/14] drm/i915: Rework watermark readout to use
plane api
URL : https://patchwork.freedesktop.org/series/68519/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
22333473c76c drm/i915: Rework watermark readout to use plane api
198f3ae74f1a drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
-:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#87: FILE: drivers/gpu/drm/i915/display/intel_atomic.c:387:
+ DRM_DEBUG_KMS("Failed to add [PLANE:%d]
to drm_state: %li\n",
+ plane->base.base.id,
PTR_ERR(plane_state));
total: 0 errors, 1 warnings, 1 checks, 185 lines checked
083b2450c140 drm/i915: Handle a few more cases for crtc hw/uapi split, v3.
b48dff12ef91 drm/i915: Add aliases for uapi and hw to crtc_state
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/display/intel_display.h:453:
+
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state,
>base
total: 0 errors, 1 warnings, 0 checks, 83 lines checked
6d9fcb9131c2 drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
1e26da0561d3 drm/i915: Perform automated conversions for crtc uapi/hw split,
base -> hw.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
-:1424: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#1424: FILE: drivers/gpu/drm/i915/display/intel_display.c:17104:
+ crtc_state->hw.active = crtc_state->hw.enable =
total: 0 errors, 1 warnings, 1 checks, 2089 lines checked
702358ac8359 drm/i915: Perform automated conversions for crtc uapi/hw split,
base -> uapi.
-:2409: ERROR:CODE_INDENT: code indent should use tabs where possible
#2409: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+^I^I^I^I new_crtc_state->uapi.event);$
-:2409: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2409: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+ drm_crtc_arm_vblank_event(>base,
+ new_crtc_state->uapi.event);
total: 1 errors, 0 warnings, 1 checks, 2568 lines checked
bab1c99201bb drm/i915: Complete crtc hw/uapi split, v3.
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#15:
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
total: 0 errors, 1 warnings, 0 checks, 217 lines checked
ca8f0c896f5f drm/i915: Add aliases for uapi and hw to plane_state
-:49: WARNING:LINE_SPACING: Missing a blank line after declarations
#49: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.c:112:
+ struct intel_plane_state *plane_state = to_intel_plane_state(state);
+ WARN_ON(plane_state->vma);
total: 0 errors, 1 warnings, 0 checks, 59 lines checked
d999f2905a18 drm/i915: Perform manual conversions for plane uapi/hw split
5fe68e3dbc52 drm/i915: Perform automated conversions for plane uapi/hw split,
base -> hw.
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#11:
identifier x =~
"^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
-:832: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
"plane_state->hw.fb"
#832: FILE: drivers/gpu/drm/i915/intel_pm.c:814:
+ return plane_state->hw.fb != NULL;
total: 0 errors, 1 warnings, 1 checks, 836 lines checked
511cefb79332 drm/i915: Perform automated conversions for plane uapi/hw split,
base -> uapi.
-:731: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#731: FILE: drivers/gpu/drm/i915/display/intel_display.c:11105:
+ unsigned width = drm_rect_width(_state->uapi.dst);
-:732: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#732: FILE: drivers/gpu/drm/i915/display/intel_display.c:11106:
+ unsigned height = drm_rect_height(_state->uapi.dst);
-:800: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#800: FILE: drivers/gpu/drm/i915/display/intel_display.c:11708:
+ plane_state->uapi.visible = visible = false;
-:1528: WARNING:LONG_LINE: line over 100 characters
#1528: FILE: drivers/gpu/drm/i915/intel_pm.c:3113:
+ (drm_rect_width(>uapi.dst) !=
drm_rect_width(>uapi.src) >> 16 ||
-:1529: WARNING:LONG_LINE: line over 100 characters
#1529: FILE: drivers/gpu/drm/i915/intel_pm.c:3114:
+
[Intel-gfx] [PATCH 1/5] drm/i915: Add whether or not to enable an each of Video DIP
Because DP ports don't use set_infoframes() / intel_write_infoframe()
machanisms, DP ports requires a handling of enabling/disabling of each
Video DIP when a changing usage of video DIP for SDP transmission such as
whether or not to use HDR.
For now it only adds enable_infoframe() callback for hsw platform.
Signed-off-by: Gwan-gyeong Mun
---
.../drm/i915/display/intel_display_types.h| 4 +++
drivers/gpu/drm/i915/display/intel_hdmi.c | 35 +++
drivers/gpu/drm/i915/display/intel_hdmi.h | 3 ++
3 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index bac40482a2aa..a541c8cc8d83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1305,6 +1305,10 @@ struct intel_digital_port {
const struct intel_crtc_state *crtc_state,
unsigned int type,
void *frame, ssize_t len);
+ void (*enable_infoframe)(struct intel_encoder *encoder,
+bool enable,
+const struct intel_crtc_state *crtc_state,
+unsigned int type);
void (*set_infoframes)(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b54ccbb5aad5..3c2aea93ae02 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -559,6 +559,24 @@ static void hsw_read_infoframe(struct intel_encoder
*encoder,
type, i >> 2));
}
+static void hsw_enable_infoframe(struct intel_encoder *encoder,
+bool enable,
+const struct intel_crtc_state *crtc_state,
+unsigned int type)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
+ u32 val = I915_READ(ctl_reg);
+
+ if (enable)
+ val |= hsw_infoframe_enable(type);
+ else
+ val &= ~hsw_infoframe_enable(type);
+
+ I915_WRITE(ctl_reg, val);
+ POSTING_READ(ctl_reg);
+}
+
static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
@@ -586,6 +604,22 @@ static const u8 infoframe_type_to_idx[] = {
HDMI_INFOFRAME_TYPE_DRM,
};
+void intel_enable_infoframe(struct intel_encoder *encoder,
+ bool enable,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(>base);
+
+ if (dig_port->enable_infoframe)
+ dig_port->enable_infoframe(encoder, enable, crtc_state, type);
+ else {
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ DRM_DEBUG_KMS("GEN%d enable_infoframe() callback is not
implemented!",
+ INTEL_GEN(dev_priv));
+ }
+}
+
u32 intel_hdmi_infoframe_enable(unsigned int type)
{
int i;
@@ -3104,6 +3138,7 @@ void intel_infoframe_init(struct intel_digital_port
*intel_dig_port)
} else {
intel_dig_port->write_infoframe = hsw_write_infoframe;
intel_dig_port->read_infoframe = hsw_read_infoframe;
+ intel_dig_port->enable_infoframe = hsw_enable_infoframe;
intel_dig_port->set_infoframes = hsw_set_infoframes;
intel_dig_port->infoframes_enabled =
hsw_infoframes_enabled;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
b/drivers/gpu/drm/i915/display/intel_hdmi.h
index cf1ea5427639..86f925526514 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -48,5 +48,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
enum hdmi_infoframe_type type,
union hdmi_infoframe *frame);
+void intel_enable_infoframe(struct intel_encoder *encoder, bool enable,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type);
#endif /* __INTEL_HDMI_H__ */
--
2.23.0
___
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[Intel-gfx] [PATCH 2/5] drm/i915: Add checking a specific Video DIP is enabled or not
Because DP ports don't use intel_hdmi_infoframes_enabled() machanism,
DP ports requires a way to check a specific infoframe (aka. Video DIP )
is enabled or not.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 21 +
drivers/gpu/drm/i915/display/intel_hdmi.h | 3 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 3c2aea93ae02..aed06a5da489 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -620,6 +620,27 @@ void intel_enable_infoframe(struct intel_encoder *encoder,
}
}
+bool intel_infoframe_enabled(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+unsigned int type)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(>base);
+ u32 val = 0;
+
+ val = dig_port->infoframes_enabled(encoder, crtc_state);
+
+ if (HAS_DDI(dev_priv)) {
+ if (val & hsw_infoframe_enable(type))
+ return true;
+ } else {
+ if (val & g4x_infoframe_enable(type))
+ return true;
+ }
+
+ return false;
+}
+
u32 intel_hdmi_infoframe_enable(unsigned int type)
{
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 86f925526514..96d50f591b69 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -51,5 +51,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
void intel_enable_infoframe(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
unsigned int type);
+bool intel_infoframe_enabled(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+unsigned int type);
#endif /* __INTEL_HDMI_H__ */
--
2.23.0
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[Intel-gfx] [PATCH 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates.
It calls intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe updates to make sure that we enable sending of VSC SDP and HDR Metadata Infoframe SDP packet (when applicable) on fastsets. In order to set an enabled state of VSC SDP and HDR Metadata Infoframe SDP, It adds intel_enable_infoframe() function to handle enabling/disabling of each Video DIP. And it add intel_infoframe_enabled() function to get an enabled state of a specific infoframe. Gwan-gyeong Mun (5): drm/i915: Add whether or not to enable an each of Video DIP drm/i915: Add checking a specific Video DIP is enabled or not drm/i915/dp: Stop sending of VSC SDP when it is not needed drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates drivers/gpu/drm/i915/display/intel_ddi.c | 2 + .../drm/i915/display/intel_display_types.h| 4 ++ drivers/gpu/drm/i915/display/intel_dp.c | 20 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 56 +++ drivers/gpu/drm/i915/display/intel_hdmi.h | 6 ++ 5 files changed, 86 insertions(+), 2 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915/dp: Stop sending of VSC SDP when it is not needed
It prevents sending VSC SDP Packet to a receiver when VSC SDP is not
needed. Because VSC SDP is used for PSR, YCbCr 420, HDR BT.2020 and etc,
it checks PSR is enabled or not.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 521ce23f38ac..ed6845485b41 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4735,8 +4735,16 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+ if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ struct intel_digital_port *intel_dig_port =
dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = _dig_port->base;
+
+ if (!intel_psr_enabled(intel_dp) &&
+ intel_infoframe_enabled(encoder, crtc_state, DP_SDP_VSC))
+ intel_enable_infoframe(encoder, false, crtc_state,
DP_SDP_VSC);
+
return;
+ }
intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
}
--
2.23.0
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[Intel-gfx] [PATCH 5/5] drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates
Call intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe updates to make sure that we enable sending of VSC SDP and HDR Metadata Infoframe SDP packet (when applicable) on fastsets. These functions check pipe state and when the features does not need, they disable the features. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 1a49266f4f57..e07591ff2a6e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4020,6 +4020,8 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, intel_ddi_set_dp_msa(crtc_state, conn_state); intel_psr_update(intel_dp, crtc_state); + intel_dp_vsc_enable(intel_dp, crtc_state, conn_state); + intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state); intel_edp_drrs_enable(intel_dp, crtc_state); intel_panel_update_backlight(encoder, crtc_state, conn_state); -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed
It prevents sending HDR Metadata Infoframe SDP packet to a receiver when
HDR Metadata Infoframe SDP is not needed.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ed6845485b41..729f1e8cb49a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4753,8 +4753,16 @@ void intel_dp_hdr_metadata_enable(struct intel_dp
*intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- if (!conn_state->hdr_output_metadata)
+ if (!conn_state->hdr_output_metadata) {
+ struct intel_digital_port *intel_dig_port =
dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = _dig_port->base;
+
+ if (intel_infoframe_enabled(encoder, crtc_state,
+
HDMI_PACKET_TYPE_GAMUT_METADATA))
+ intel_enable_infoframe(encoder, false, crtc_state,
+ HDMI_PACKET_TYPE_GAMUT_METADATA);
return;
+ }
intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
crtc_state,
--
2.23.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
== Series Details ==
Series: series starting with [1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
URL : https://patchwork.freedesktop.org/series/68517/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7174 -> Patchwork_14967
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/index.html
Known issues
Here are the changes found in Patchwork_14967 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#109635 ] / [fdo#110387])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-8809g: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
- {fi-cml-s}: [DMESG-FAIL][11] ([fdo#112096]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-cml-s/igt@i915_selftest@live_gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-cml-s/igt@i915_selftest@live_gt_heartbeat.html
* igt@vgem_basic@debugfs:
- {fi-icl-dsi}: [DMESG-WARN][13] ([fdo#106107]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-dsi/igt@vgem_ba...@debugfs.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-icl-dsi/igt@vgem_ba...@debugfs.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
[fdo#112046]: https://bugs.freedesktop.org/show_bug.cgi?id=112046
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (50 -> 44)
--
Additional (2): fi-hsw-peppy fi-pnv-d510
Missing(8): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7174 -> Patchwork_14967
CI-20190529: 20190529
CI_DRM_7174: c320b9b5667a773952b1d6dfdc0fff5aac2d0fb1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14967: 6de246f804ed25b6cb50a49a1cff95764056bb29 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6de246f804ed drm/i915: Fix frame start delay programming
0e839c74920b drm/i915: Add CHICKEN_TRANS_D
521a17601844 drm/i915: Use _PICK() for CHICKEN_TRANS()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] kernel-doc: rename the kernel-doc directive 'functions' to 'identifiers'
On Sun, 20 Oct 2019 21:17:17 +0800
Changbin Du wrote:
> The 'functions' directive is not only for functions, but also works for
> structs/unions. So the name is misleading. This patch renames it to
> 'identifiers', which specific the functions/types to be included in
> documentation. We keep the old name as an alias of the new one before
> all documentation are updated.
>
> Signed-off-by: Changbin Du
So I think this is basically OK, but I have one more request...
[...]
> diff --git a/Documentation/sphinx/kerneldoc.py
> b/Documentation/sphinx/kerneldoc.py
> index 1159405cb920..0689f9c37f1e 100644
> --- a/Documentation/sphinx/kerneldoc.py
> +++ b/Documentation/sphinx/kerneldoc.py
> @@ -59,9 +59,10 @@ class KernelDocDirective(Directive):
> optional_arguments = 4
> option_spec = {
> 'doc': directives.unchanged_required,
> -'functions': directives.unchanged,
> 'export': directives.unchanged,
> 'internal': directives.unchanged,
> +'identifiers': directives.unchanged,
> +'functions': directives.unchanged, # alias of 'identifiers'
> }
> has_content = False
>
> @@ -71,6 +72,7 @@ class KernelDocDirective(Directive):
>
> filename = env.config.kerneldoc_srctree + '/' + self.arguments[0]
> export_file_patterns = []
> +identifiers = None
>
> # Tell sphinx of the dependency
> env.note_dependency(os.path.abspath(filename))
> @@ -86,19 +88,22 @@ class KernelDocDirective(Directive):
> export_file_patterns = str(self.options.get('internal')).split()
> elif 'doc' in self.options:
> cmd += ['-function', str(self.options.get('doc'))]
> +elif 'identifiers' in self.options:
> +identifiers = self.options.get('identifiers').split()
> elif 'functions' in self.options:
> -functions = self.options.get('functions').split()
> -if functions:
> -for f in functions:
> -cmd += ['-function', f]
> -else:
> -cmd += ['-no-doc-sections']
> +identifiers = self.options.get('functions').split()
Rather than do this, can you just change the elif line to read:
elif ('identifiers' in self.options) or ('functions' in self.options):
...then leave the rest of the code intact? It keeps the logic together,
and avoids the confusing distinction between identifiers=='' and
identifiers==None .
Thanks,
jon
> for pattern in export_file_patterns:
> for f in glob.glob(env.config.kerneldoc_srctree + '/' + pattern):
> env.note_dependency(os.path.abspath(f))
> cmd += ['-export-file', f]
>
> +if identifiers:
> +for i in identifiers:
> +cmd += ['-function', i]
> +elif identifiers is not None:
> +cmd += ['-no-doc-sections']
> +
> cmd += [filename]
>
> try:
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Make context persistence optional
== Series Details ==
Series: drm/i915/gem: Make context persistence optional
URL : https://patchwork.freedesktop.org/series/68515/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7174 -> Patchwork_14966
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14966/index.html
Known issues
Here are the changes found in Patchwork_14966 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#111407])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14966/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_prop_blob@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-u3/igt@kms_prop_b...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14966/fi-icl-u3/igt@kms_prop_b...@basic.html
Possible fixes
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14966/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [DMESG-FAIL][7] ([fdo#112050 ]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14966/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-8809g: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14966/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
- {fi-cml-s}: [DMESG-FAIL][11] ([fdo#112096]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-cml-s/igt@i915_selftest@live_gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14966/fi-cml-s/igt@i915_selftest@live_gt_heartbeat.html
* igt@vgem_basic@debugfs:
- {fi-icl-dsi}: [DMESG-WARN][13] ([fdo#106107]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-dsi/igt@vgem_ba...@debugfs.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14966/fi-icl-dsi/igt@vgem_ba...@debugfs.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050
[fdo#112055]: https://bugs.freedesktop.org/show_bug.cgi?id=112055
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (50 -> 45)
--
Additional (2): fi-hsw-peppy fi-pnv-d510
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7174 -> Patchwork_14966
CI-20190529: 20190529
CI_DRM_7174: c320b9b5667a773952b1d6dfdc0fff5aac2d0fb1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14966: 6cdb6db4cff92f5d26431135d55049f05c491c25 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6cdb6db4cff9 drm/i915/gem: Make context persistence optional
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14966/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/tgl: Handle AUX interrupts for TC ports
We're currently only processing AUX interrupts on the combo ports; make
sure we handle the TC ports as well.
v2: Drop stale comment
Fixes: f663769a5eef ("drm/i915/tgl: initialize TC and TBT ports")
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 10 --
drivers/gpu/drm/i915/i915_reg.h | 6 ++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a048c79a6a55..2e67734a6d2a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2575,10 +2575,16 @@ static u32 gen8_de_port_aux_mask(struct
drm_i915_private *dev_priv)
u32 mask;
if (INTEL_GEN(dev_priv) >= 12)
- /* TODO: Add AUX entries for USBC */
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
- TGL_DE_PORT_AUX_DDIC;
+ TGL_DE_PORT_AUX_DDIC |
+ TGL_DE_PORT_AUX_USBC1 |
+ TGL_DE_PORT_AUX_USBC2 |
+ TGL_DE_PORT_AUX_USBC3 |
+ TGL_DE_PORT_AUX_USBC4 |
+ TGL_DE_PORT_AUX_USBC5 |
+ TGL_DE_PORT_AUX_USBC6;
+
mask = GEN8_AUX_CHANNEL_A;
if (INTEL_GEN(dev_priv) >= 9)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07cf67d42735..a7ba8100f13e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7436,6 +7436,12 @@ enum {
#define GEN8_PORT_DP_A_HOTPLUG(1 << 3)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A(1 << 0)
+#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
+#define TGL_DE_PORT_AUX_USBC5 (1 << 12)
+#define TGL_DE_PORT_AUX_USBC4 (1 << 11)
+#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
+#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
+#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
#define TGL_DE_PORT_AUX_DDIC (1 << 2)
#define TGL_DE_PORT_AUX_DDIB (1 << 1)
#define TGL_DE_PORT_AUX_DDIA (1 << 0)
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
On Thu, Oct 24, 2019 at 05:20:32PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 24, 2019 at 03:54:41PM +0200, Thierry Reding wrote:
> > On Thu, Oct 24, 2019 at 02:34:00PM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 24, 2019 at 12:31:06PM +0200, Thierry Reding wrote:
> > > > On Wed, Oct 23, 2019 at 05:00:41PM -0700, Manasi Navare wrote:
> > > > > Adaptive Sync is a VESA feature so add a DRM core helper to parse
> > > > > the EDID's detailed descritors to obtain the adaptive sync monitor
> > > > > range.
> > > > > Store this info as part fo drm_display_info so it can be used
> > > > > across all drivers.
> > > > > This part of the code is stripped out of amdgpu's function
> > > > > amdgpu_dm_update_freesync_caps() to make it generic and be used
> > > > > across all DRM drivers
> > > > >
> > > > > Cc: Ville Syrjälä
> > > > > Cc: Harry Wentland
> > > > > Cc: Clinton A Taylor
> > > > > Signed-off-by: Manasi Navare
> > > > > ---
> > > > > drivers/gpu/drm/drm_edid.c | 49
> > > > > +
> > > > > include/drm/drm_connector.h | 25 +++
> > > > > include/drm/drm_edid.h | 2 ++
> > > > > 3 files changed, 76 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > > > index 474ac04d5600..97dd1200773e 100644
> > > > > --- a/drivers/gpu/drm/drm_edid.c
> > > > > +++ b/drivers/gpu/drm/drm_edid.c
> > > > > @@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct
> > > > > drm_connector *connector,
> > > > > }
> > > > > }
> > > > >
> > > > > +void drm_get_adaptive_sync_limits(struct drm_connector *connector,
> > > > > + const struct edid *edid)
> > > > > +{
> > > > > + struct drm_display_info *info = >display_info;
> > > > > + const struct detailed_timing *timing;
> > > > > + const struct detailed_non_pixel *data;
> > > > > + const struct detailed_data_monitor_range *range;
> > > > > + int i;
> > > >
> > > > This can be unsigned int.
> > >
> > > Please no. A loop iterator called 'i' should always be a normal signed
> > > int.
> >
> > What? Where's that rule written down? In my experience it's always
> > better to use as restrictive a type as possible. It's really annoying
> > when GCC suddenly starts complaining about comparison between signed and
> > unsigned. So if a variable can never contain a signed value, why risk
> > the ambiguity? The value goes from 0 to 4, the sign bit is useless.
>
> Dunno if it's really written down anywhere. It's just something
> experience has taught. IIRC there's also a rant from Linus about this
> somewhere. Hm, can't find that one right now, but Andrew Morton also
> seems to agree: https://lwn.net/Articles/309279/
> Ah, here is one Linus rant about unsigned array indexes:
> https://yarchive.net/comp/linux/gcc.html
>
> My opinion: unsigned is an very *dangerous* keyword in C that demands
> your respect. You should never use it without thinking first what the
> ramifications are. You always have to have the promotion rules clear
> in you mind when you do any kind of arithmetic with >= unsigned int
> type. And common idioms such as 'int i' should be respected so as to
> not cause unexpected hair loss to other developers when they decide
> to make the loop iterate backwards.
>
> >
> > > > > + /*
> > > > > + * Restrict Adaptive Sync only for dp and edp
> > > > > + */
> > > > > + if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort
> > > > > &&
> > > > > + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> > > > > + return;
> > > > > +
> > > > > + if (edid->version <= 1 && !(edid->version == 1 &&
> > > > > edid->revision > 1))
> > > > > + return;
> > > > > +
> > > > > + for (i = 0; i < 4; i++) {
> > > > > + timing = >detailed_timings[i];
> > > > > + data= >data.other_data;
> > > > > + range = >data.range;
> > > > > + /*
> > > > > + * Check if monitor has continuous frequency mode
> > > > > + */
> > > > > + if (data->type != EDID_DETAIL_MONITOR_RANGE)
> > > > > + continue;
> > > > > + /*
> > > > > + * Check for flag range limits only. If flag == 1 then
> > > > > + * no additional timing information provided.
> > > > > + * Default GTF, GTF Secondary curve and CVT are not
> > > > > + * supported
> > > > > + */
> > > > > + if (range->flags != 1)
> > > > > + continue;
> > > > > +
> > > > > + info->adaptive_sync.min_vfreq = range->min_vfreq;
> > > > > + info->adaptive_sync.max_vfreq = range->max_vfreq;
> > > > > + info->adaptive_sync.pixel_clock_mhz =
> > > > > + range->pixel_clock_mhz * 10;
> > > > > + break;
> > > > > + }
> > > > > +}
> > > > >
[Intel-gfx] [PATCH] drm/i915/tgl: Handle AUX interrupts for TC ports
We're currently only processing AUX interrupts on the combo ports; make
sure we handle the TC ports as well.
Fixes: f663769a5eef ("drm/i915/tgl: initialize TC and TBT ports")
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 9 -
drivers/gpu/drm/i915/i915_reg.h | 6 ++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a048c79a6a55..0d90e06f833d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2578,7 +2578,14 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
/* TODO: Add AUX entries for USBC */
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
- TGL_DE_PORT_AUX_DDIC;
+ TGL_DE_PORT_AUX_DDIC |
+ TGL_DE_PORT_AUX_USBC1 |
+ TGL_DE_PORT_AUX_USBC2 |
+ TGL_DE_PORT_AUX_USBC3 |
+ TGL_DE_PORT_AUX_USBC4 |
+ TGL_DE_PORT_AUX_USBC5 |
+ TGL_DE_PORT_AUX_USBC6;
+
mask = GEN8_AUX_CHANNEL_A;
if (INTEL_GEN(dev_priv) >= 9)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07cf67d42735..a7ba8100f13e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7436,6 +7436,12 @@ enum {
#define GEN8_PORT_DP_A_HOTPLUG(1 << 3)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A(1 << 0)
+#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
+#define TGL_DE_PORT_AUX_USBC5 (1 << 12)
+#define TGL_DE_PORT_AUX_USBC4 (1 << 11)
+#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
+#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
+#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
#define TGL_DE_PORT_AUX_DDIC (1 << 2)
#define TGL_DE_PORT_AUX_DDIB (1 << 1)
#define TGL_DE_PORT_AUX_DDIA (1 << 0)
--
2.21.0
___
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Re: [Intel-gfx] [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
On Thu, Oct 24, 2019 at 12:31:06PM +0200, Thierry Reding wrote:
> On Wed, Oct 23, 2019 at 05:00:41PM -0700, Manasi Navare wrote:
> > Adaptive Sync is a VESA feature so add a DRM core helper to parse
> > the EDID's detailed descritors to obtain the adaptive sync monitor range.
> > Store this info as part fo drm_display_info so it can be used
> > across all drivers.
> > This part of the code is stripped out of amdgpu's function
> > amdgpu_dm_update_freesync_caps() to make it generic and be used
> > across all DRM drivers
> >
> > Cc: Ville Syrjälä
> > Cc: Harry Wentland
> > Cc: Clinton A Taylor
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/drm_edid.c | 49 +
> > include/drm/drm_connector.h | 25 +++
> > include/drm/drm_edid.h | 2 ++
> > 3 files changed, 76 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 474ac04d5600..97dd1200773e 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct drm_connector
> > *connector,
> > }
> > }
> >
> > +void drm_get_adaptive_sync_limits(struct drm_connector *connector,
> > + const struct edid *edid)
> > +{
> > + struct drm_display_info *info = >display_info;
> > + const struct detailed_timing *timing;
> > + const struct detailed_non_pixel *data;
> > + const struct detailed_data_monitor_range *range;
> > + int i;
>
> This can be unsigned int.
Yes this can be unsigned, will change this
>
> > +
> > + /*
> > +* Restrict Adaptive Sync only for dp and edp
> > +*/
> > + if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
> > + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> > + return;
> > +
> > + if (edid->version <= 1 && !(edid->version == 1 && edid->revision > 1))
> > + return;
> > +
> > + for (i = 0; i < 4; i++) {
> > + timing = >detailed_timings[i];
> > + data= >data.other_data;
> > + range = >data.range;
> > + /*
> > +* Check if monitor has continuous frequency mode
> > +*/
> > + if (data->type != EDID_DETAIL_MONITOR_RANGE)
> > + continue;
> > + /*
> > +* Check for flag range limits only. If flag == 1 then
> > +* no additional timing information provided.
> > +* Default GTF, GTF Secondary curve and CVT are not
> > +* supported
> > +*/
> > + if (range->flags != 1)
> > + continue;
> > +
> > + info->adaptive_sync.min_vfreq = range->min_vfreq;
> > + info->adaptive_sync.max_vfreq = range->max_vfreq;
> > + info->adaptive_sync.pixel_clock_mhz =
> > + range->pixel_clock_mhz * 10;
> > + break;
> > + }
> > +}
> > +EXPORT_SYMBOL(drm_get_adaptive_sync_limits);
> > +
> > /* A connector has no EDID information, so we've got no EDID to compute
> > quirks from. Reset
> > * all of the values which would have been set from EDID
> > */
> > @@ -4728,6 +4774,7 @@ drm_reset_display_info(struct drm_connector
> > *connector)
> > memset(>hdmi, 0, sizeof(info->hdmi));
> >
> > info->non_desktop = 0;
> > + memset(>adaptive_sync, 0, sizeof(info->adaptive_sync));
> > }
> >
> > u32 drm_add_display_info(struct drm_connector *connector, const struct
> > edid *edid)
> > @@ -4743,6 +4790,8 @@ u32 drm_add_display_info(struct drm_connector
> > *connector, const struct edid *edi
> >
> > info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
> >
> > + drm_get_adaptive_sync_limits(connector, edid);
> > +
> > DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
> >
> > if (edid->revision < 3)
> > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> > index 5f8c3389d46f..a27a84270d8d 100644
> > --- a/include/drm/drm_connector.h
> > +++ b/include/drm/drm_connector.h
> > @@ -254,6 +254,26 @@ enum drm_panel_orientation {
> > DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
> > };
> >
> > +/**
> > + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for
> > + * _display_info
> > + *
> > + * This struct is used to store a Panel's Adaptive Sync capabilities
> > + * as parsed from EDID's detailed monitor range descriptor block.
> > + *
> > + * @min_vfreq: This is the min supported refresh rate in Hz from
> > + * EDID's detailed monitor range.
> > + * @max_vfreq: This is the max supported refresh rate in Hz from
> > + * EDID's detailed monitor range
> > + * @pixel_clock_mhz: This is the dotclock in MHz from
> > + * EDID's detailed monitor range
> > + */
> > +struct drm_adaptive_sync_info {
> > + int min_vfreq;
> > + int max_vfreq;
> > + int pixel_clock_mhz;
>
> Any reason why these can't be unsigned? Also,
Re: [Intel-gfx] [PATCH] drm/i915/bios: add compression parameter block definition
On Thu, Oct 24, 2019 at 10:51:20AM +0300, Jani Nikula wrote:
> On Wed, 23 Oct 2019, Manasi Navare wrote:
> > On Tue, Oct 22, 2019 at 05:03:00PM +0300, Jani Nikula wrote:
> >> Add definition for block 56, the compression parameters.
> >>
> >
> > Would this be used on DP connectors for DSC as well?
>
> I think only if needed; with DSI it's not possible to query the
> parameters from the display.
>
Ok got it! So then for DP we do get everything from the DPCDs
Thanks for the clarification.
Regards
Manasi
> BR,
> Jani.
>
> >
> > Manasi
> >
> >> Cc: Vandita Kulkarni
> >> Signed-off-by: Jani Nikula
> >> ---
> >> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 50 +++
> >> 1 file changed, 50 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> >> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> >> index e3045ced4bfe..7f222196d2d5 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> >> @@ -114,6 +114,7 @@ enum bdb_block_id {
> >>BDB_LVDS_POWER = 44,
> >>BDB_MIPI_CONFIG = 52,
> >>BDB_MIPI_SEQUENCE = 53,
> >> + BDB_COMPRESSION_PARAMETERS = 56,
> >>BDB_SKIP= 254, /* VBIOS private block, ignore */
> >> };
> >>
> >> @@ -811,4 +812,53 @@ struct bdb_mipi_sequence {
> >>u8 data[0]; /* up to 6 variable length blocks */
> >> } __packed;
> >>
> >> +/*
> >> + * Block 56 - Compression Parameters
> >> + */
> >> +
> >> +#define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0
> >> +#define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1
> >> +#define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2
> >> +#define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3
> >> +
> >> +#define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /*
> >> bits */
> >> +#define VBT_DSC_MAX_BPP(vbt_value)(6 + (vbt_value) * 2)
> >> +
> >> +struct dsc_compression_parameters_entry {
> >> + u8 version_major:4;
> >> + u8 version_minor:4;
> >> +
> >> + u8 rc_buffer_block_size:2;
> >> + u8 reserved1:6;
> >> +
> >> + /*
> >> + * Buffer size in bytes:
> >> + *
> >> + * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes
> >> + */
> >> + u8 rc_buffer_size;
> >> + u32 slices_per_line;
> >> +
> >> + u8 line_buffer_depth:4;
> >> + u8 reserved2:4;
> >> +
> >> + /* Flag Bits 1 */
> >> + u8 block_prediction_enable:1;
> >> + u8 reserved3:7;
> >> +
> >> + u8 max_bpp; /* mapping */
> >> +
> >> + /* Color depth capabilities */
> >> + u8 reserved4:1;
> >> + u8 support_8bpc:1;
> >> + u8 support_10bpc:1;
> >> + u8 support_12bpc:1;
> >> + u8 reserved5:4;
> >> +} __packed;
> >> +
> >> +struct bdb_compression_parameters {
> >> + u16 entry_size;
> >> + struct dsc_compression_parameters_entry data[16];
> >> +} __packed;
> >> +
> >> #endif /* _INTEL_VBT_DEFS_H_ */
> >> --
> >> 2.20.1
> >>
> >> ___
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Graphics Center
___
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Add coverage of mocs registers
On Thu, Oct 24, 2019 at 08:13:29AM +0100, Chris Wilson wrote: > Quoting Kumar Valsan, Prathap (2019-10-23 22:03:40) > > On Tue, Oct 22, 2019 at 12:57:05PM +0100, Chris Wilson wrote: > > > Probe the mocs registers for new contexts and across GPU resets. Similar > > > to intel_workarounds, we have tables of what register values we expect > > > to see, so verify that user contexts are affected by them. In the > > > future, we should add tests similar to intel_sseu to cover dynamic > > > reconfigurations. > > > > > > Signed-off-by: Chris Wilson > > > Cc: Prathap Kumar Valsan > > > Cc: Mika Kuoppala > > > > s/for_each_engine/for_each_uabi_engine ? > > No, we are inside the gt compartment, so we only operate within our > little enclosure. Think parallelism... Ok. Thanks. > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915/gt: Try to more gracefully quiesce the system before resets
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/gt: Try to more gracefully
quiesce the system before resets
URL : https://patchwork.freedesktop.org/series/68457/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7165_full -> Patchwork_14948_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14948_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14948_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14948_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_shared@q-promotion-bsd1:
- shard-apl: [PASS][1] -> [FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/shard-apl6/igt@gem_ctx_sha...@q-promotion-bsd1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/shard-apl2/igt@gem_ctx_sha...@q-promotion-bsd1.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-glk: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/shard-glk6/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/shard-glk6/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-contexts-render:
- shard-skl: [PASS][5] -> [FAIL][6] +4 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/shard-skl9/igt@gem_exec_sched...@preempt-queue-contexts-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/shard-skl6/igt@gem_exec_sched...@preempt-queue-contexts-render.html
Warnings
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-iclb: [SKIP][7] ([fdo#111325]) -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/shard-iclb1/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/shard-iclb5/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_schedule@wide-bsd2:
- {shard-tglb}: [PASS][9] -> [FAIL][10] +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/shard-tglb8/igt@gem_exec_sched...@wide-bsd2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/shard-tglb6/igt@gem_exec_sched...@wide-bsd2.html
* {igt@kms_cursor_crc@pipe-d-cursor-64x64-offscreen}:
- {shard-tglb}: [PASS][11] -> [INCOMPLETE][12] +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/shard-tglb1/igt@kms_cursor_...@pipe-d-cursor-64x64-offscreen.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/shard-tglb7/igt@kms_cursor_...@pipe-d-cursor-64x64-offscreen.html
### Piglit changes ###
Possible regressions
* spec@arb_shader_image_load_store@shader-mem-barrier (NEW):
- pig-glk-j5005: NOTRUN -> [FAIL][13]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/pig-glk-j5005/spec@arb_shader_image_load_st...@shader-mem-barrier.html
New tests
-
New tests have been introduced between CI_DRM_7165_full and
Patchwork_14948_full:
### New Piglit tests (1) ###
* spec@arb_shader_image_load_store@shader-mem-barrier:
- Statuses : 1 fail(s)
- Exec time: [2.75] s
Known issues
Here are the changes found in Patchwork_14948_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112080]) +16 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/shard-iclb7/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([fdo#108566]) +4
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/shard-kbl4/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109276] / [fdo#112080])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/shard-iclb2/igt@gem_ctx_isolat...@vcs1-dirty-create.html
[19]:
[Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
From: Don Hiatt
Check to see if GuC submission is enabled before requesting the
EXIT_S_STATE action.
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. Guard against this by only requesting the GuC action on
platforms that support GuC submission.
I've verfied that intel_guc_resume() only gets called when driver
is loaded with: guc_enable={1,2,3}, all other cases (no args,
guc_enable={0,-1} the intel_guc_resume() is not called.
Signed-off-by: Don Hiatt
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 37f7bcbf7dac..33318ed135c0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -565,7 +565,10 @@ int intel_guc_resume(struct intel_guc *guc)
GUC_POWER_D0,
};
- return intel_guc_send(guc, action, ARRAY_SIZE(action));
+ if (guc->submission_supported)
+ return intel_guc_send(guc, action, ARRAY_SIZE(action));
+
+ return 0;
}
/**
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Remove nonpriv flags when srm/lrm (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915: Remove nonpriv flags when srm/lrm
(rev2)
URL : https://patchwork.freedesktop.org/series/68506/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7173 -> Patchwork_14965
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/index.html
Known issues
Here are the changes found in Patchwork_14965 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_tiled_blits@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-icl-u3/igt@gem_tiled_bl...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/fi-icl-u3/igt@gem_tiled_bl...@basic.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4] ([fdo#112050 ])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u2}:[INCOMPLETE][7] ([fdo#111735]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- {fi-icl-guc}: [INCOMPLETE][11] ([fdo#107713] / [fdo#111381]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +3
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-x1275: [DMESG-FAIL][15] ([fdo#112096]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7173 -> Patchwork_14965
CI-20190529: 20190529
CI_DRM_7173: 0e7609c32df689d5196c3b9e3f820c37dc03b192 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14965: b34090d8a268a35a792e9a48778be6c0d465589a @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b34090d8a268 drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
56ea118779e3 drm/i915: Remove nonpriv flags when srm/lrm
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14965/index.html
___
Intel-gfx mailing list
[Intel-gfx] [PULL] drm-misc-next
Hi Dave & Daniel, Here's the pull for last week and this week. As you know we had some trouble with the OMAP_BO* additions last week, those have since been reverted. Speaking of UAPI, we have a new DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED flag from AMD to get the last signaled timeline value from the kernel. It's used by the AMD implementation of timeline semaphores [1]. The kernel patch was reviewed by Lionel, but the userspace portion was not reviewed in the open (and not even posted before the kernel patch was reviewed). Overall the process was lacking on this submission (as well as the commit message and the kerneldoc), but the addition itself seems fine. Other than that, relatively quiet week overall. [1]- https://github.com/GPUOpen-Drivers/pal/commit/66e78b997748d03d77e1d706c10f1f17e18e5654 drm-misc-next-2019-10-24-2: drm-misc-next for 5.5: UAPI Changes: -syncobj: allow querying the last submitted timeline value (David) -fourcc: explicitly defineDRM_FORMAT_BIG_ENDIAN as unsigned (Adam) -omap: revert the OMAP_BO_* flags that were added -- no userspace (Sean) Cross-subsystem Changes: -MAINTAINERS: add Mihail as komeda co-maintainer (Mihail) Core Changes: -edid: a few cleanups, add AVI infoframe bar info (Ville) -todo: remove i915 device_link item and add difficulty levels (Daniel) -dp_helpers: add a few new helpers to parse dpcd (Thierry) Driver Changes: -gma500: fix a few memory disclosure leaks (Kangjie) -qxl: convert to use the new drm_gem_object_funcs.mmap (Gerd) -various: open code dp_link helpers in preparation for helper removal (Thierry) Cc: Chunming Zhou Cc: Adam Jackson Cc: Sean Paul Cc: Ville Syrjälä Cc: Kangjie Lu Cc: Mihail Atanassov Cc: Daniel Vetter Cc: Thierry Reding Cheers, Sean The following changes since commit 2e79e22e092acd55da0b2db066e4826d7d152c41: Merge v5.4-rc4 into drm-next (2019-10-23 12:10:05 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-10-24-2 for you to fetch changes up to 9a42c7c647a9ad0f7ebb147a52eda3dcb7c84292: drm/tegra: Move drm_dp_link helpers to Tegra DRM (2019-10-23 18:22:10 +0200) drm-misc-next for 5.5: UAPI Changes: -syncobj: allow querying the last submitted timeline value (David) -fourcc: explicitly defineDRM_FORMAT_BIG_ENDIAN as unsigned (Adam) -omap: revert the OMAP_BO_* flags that were added -- no userspace (Sean) Cross-subsystem Changes: -MAINTAINERS: add Mihail as komeda co-maintainer (Mihail) Core Changes: -edid: a few cleanups, add AVI infoframe bar info (Ville) -todo: remove i915 device_link item and add difficulty levels (Daniel) -dp_helpers: add a few new helpers to parse dpcd (Thierry) Driver Changes: -gma500: fix a few memory disclosure leaks (Kangjie) -qxl: convert to use the new drm_gem_object_funcs.mmap (Gerd) -various: open code dp_link helpers in preparation for helper removal (Thierry) Cc: Chunming Zhou Cc: Adam Jackson Cc: Sean Paul Cc: Ville Syrjälä Cc: Kangjie Lu Cc: Mihail Atanassov Cc: Daniel Vetter Cc: Thierry Reding Adam Jackson (1): drm/fourcc: Fix undefined left shift in DRM_FORMAT_BIG_ENDIAN macros Andy Shevchenko (1): drm/mipi_dbi: Use simple right shift instead of double negation Ben Dooks (3): drm/scheduler: make unexported items static drm/rockchip: include rockchip_drm_drv.h drm/rockchip: make rockchip_gem_alloc_object static Ben Dooks (Codethink) (1): drm/arm: make undeclared items static Brian Masney (1): drm/bridge: analogix-anx78xx: add support for 7808 addresses Chunming Zhou (1): drm/syncobj: extend syncobj query ability v3 Colin Ian King (1): drm/komeda: remove redundant assignment to pointer disable_done Daniel Kurtz (1): drm/bridge: dw-hdmi: Restore audio when setting a mode Daniel Vetter (4): drm/dp-mst: Drop connection_mutex check drm/doc: Drop misleading comment on drm_mode_config_cleanup drm/todo: Remove i915 device_link task drm/todo: Add levels Dariusz Marcinkiewicz (1): drm: tda998x: use cec_notifier_conn_(un)register Douglas Anderson (1): drm/rockchip: Round up _before_ giving to the clock framework Ezequiel Garcia (2): dt-bindings: display: rockchip: document VOP gamma LUT address drm/rockchip: Add optional support for CRTC gamma LUT Gerd Hoffmann (18): drm: add mmap() to drm_gem_object_funcs drm/shmem: switch shmem helper to _gem_object_funcs.mmap drm/shmem: drop VM_DONTDUMP drm/shmem: drop VM_IO drm/shmem: drop DEFINE_DRM_GEM_SHMEM_FOPS drm/ttm: factor out ttm_bo_mmap_vma_setup drm/ttm: rename ttm_fbdev_mmap drm/ttm: add drm_gem_ttm_mmap() drm/vram: switch vram helper to _gem_object_funcs.mmap() drm/vram: drop verify_access drm/vram: drop DRM_VRAM_MM_FILE_OPERATIONS drm/qxl: drop
[Intel-gfx] [PATCH i-g-t] lib: Restore i915.reset before testing it in igt_allow_hang()
igt_allow_hang() checks that the GPU can be reset before allowing the
test to cause a GPU hang (which would need the reset to recover).
However, our checking for allowing a hang depends on i915.reset which we
later restore. Do that restoration before the check so that this test is
not affected by earlier fails.
Signed-off-by: Chris Wilson
---
lib/igt_gt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 5ca77471c..256c7cbc0 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -175,8 +175,6 @@ igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned
flags)
if (!igt_check_boolean_env_var("IGT_HANG", true))
igt_skip("hang injection disabled by user");
gem_context_require_bannable(fd);
- if (!igt_check_boolean_env_var("IGT_HANG_WITHOUT_RESET", false))
- igt_require(has_gpu_reset(fd));
allow_reset = 1;
if ((flags & HANG_ALLOW_CAPTURE) == 0) {
@@ -191,6 +189,9 @@ igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned
flags)
}
igt_require(igt_sysfs_set_parameter(fd, "reset", "%d", allow_reset));
+ if (!igt_check_boolean_env_var("IGT_HANG_WITHOUT_RESET", false))
+ igt_require(has_gpu_reset(fd));
+
ban = context_get_ban(fd, ctx);
if ((flags & HANG_ALLOW_BAN) == 0)
context_set_ban(fd, ctx, 0);
--
2.24.0.rc0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow gen11 to use over 32k long strides (rev2)
== Series Details ==
Series: drm/i915: Allow gen11 to use over 32k long strides (rev2)
URL : https://patchwork.freedesktop.org/series/67077/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7173 -> Patchwork_14964
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14964/index.html
Known issues
Here are the changes found in Patchwork_14964 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14964/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14964/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u2}:[INCOMPLETE][5] ([fdo#111735]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14964/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
- {fi-icl-dsi}: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14964/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713] / [fdo#111381]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14964/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14964/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-x1275: [DMESG-FAIL][13] ([fdo#112096]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7173/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14964/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7173 -> Patchwork_14964
CI-20190529: 20190529
CI_DRM_7173: 0e7609c32df689d5196c3b9e3f820c37dc03b192 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14964: 0e6c1e47c7571d558c40cadceefd8ad8c4a4d068 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0e6c1e47c757 drm/i915: Allow gen11 to use over 32k long strides
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14964/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Remove nonpriv flags when srm/lrm (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915: Remove nonpriv flags when srm/lrm
(rev2)
URL : https://patchwork.freedesktop.org/series/68506/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
56ea118779e3 drm/i915: Remove nonpriv flags when srm/lrm
b34090d8a268 drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3fe0107e45ab ("drm/i915/icl:
whitelist PS_(DEPTH|INVOCATION)_COUNT")'
#9:
As with commit 3fe0107e45ab, this change fixes multiple tests that are
total: 1 errors, 0 warnings, 0 checks, 26 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Remove nonpriv flags when srm/lrm
On 24/10/2019 14:37, Chris Wilson wrote: Quoting Mika Kuoppala (2019-10-24 12:03:31) On testing the whitelists, using any of the nonpriv flags when trying to access the register offset will lead to failure. Define address mask to get the mmio offset in order to guard against any current and future flag usage. v2: apply also on scrub_whitelisted_registers (Lionel) Cc: Tapani Pälli Cc: Chris Wilson Cc: Lionel Landwerlin Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris Reviewed-by: Lionel Landwerlin ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] doc: Update header files names
On 22/10/2019 13:09, Anna Karas wrote: Update header files containing i915_perf_stream, i915_perf_stream_ops and i915_oa_ops definitions since they have been moved from i915_drv.h to i915_perf_types.h. Cc: Robert Bragg Cc: Lionel Landwerlin Signed-off-by: Anna Karas Reviewed-by: Lionel Landwerlin --- Documentation/gpu/i915.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 465779670fd4..70e5fffa561a 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -514,9 +514,9 @@ i915 Perf Stream This section covers the stream-semantics-agnostic structures and functions for representing an i915 perf stream FD and associated file operations. -.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h +.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h :functions: i915_perf_stream -.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h +.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h :functions: i915_perf_stream_ops .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c @@ -541,7 +541,7 @@ for representing an i915 perf stream FD and associated file operations. i915 Perf Observation Architecture Stream - -.. kernel-doc:: drivers/gpu/drm/i915/i915_drv.h +.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h :functions: i915_oa_ops .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/14] drm/i915: Complete crtc hw/uapi split, v3.
On Thu, Oct 24, 2019 at 02:47:59PM +0200, Maarten Lankhorst wrote:
> Now that we separated everything into uapi and hw, it's
> time to make the split definitive. Remove the union and
> make a copy of the hw state on modeset and fastset.
>
> Color blobs are copied in crtc atomic_check(), right
> before color management is checked.
>
> Changes since v1:
> - Copy all blobs immediately after drm_atomic_helper_check_modeset().
> - Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
> Changes since v2:
> - Use intel_crtc_free_hw_state + clear in intel_crtc_disable_noatomic().
> - Make a intel_crtc_prepare_state() function that clears the crtc_state
> and copies hw members.
> - Remove setting uapi.adjusted_mode, we now have a direct call to
> drm_calc_timestamping_constants().
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 44 +++
> drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 56 +++
> .../drm/i915/display/intel_display_types.h| 9 +--
> 4 files changed, 95 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 7cf13b9c7d38..266d0ce9d03d 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>
> __drm_atomic_helper_crtc_duplicate_state(crtc, _state->uapi);
>
> + /* copy color blobs */
> + if (crtc_state->hw.degamma_lut)
> + drm_property_blob_get(crtc_state->hw.degamma_lut);
> + if (crtc_state->hw.ctm)
> + drm_property_blob_get(crtc_state->hw.ctm);
> + if (crtc_state->hw.gamma_lut)
> + drm_property_blob_get(crtc_state->hw.gamma_lut);
> +
> crtc_state->update_pipe = false;
> crtc_state->disable_lp_wm = false;
> crtc_state->disable_cxsr = false;
> @@ -208,6 +216,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> return _state->uapi;
> }
>
> +static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
> +{
> + drm_property_blob_put(crtc_state->hw.degamma_lut);
> + drm_property_blob_put(crtc_state->hw.gamma_lut);
> + drm_property_blob_put(crtc_state->hw.ctm);
> +}
> +
> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> +{
> + intel_crtc_put_color_blobs(crtc_state);
> +}
> +
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
This is only used in intel_display.c so should perhaps live there?
> +{
> + intel_crtc_put_color_blobs(crtc_state);
> +
> + if (crtc_state->uapi.degamma_lut)
> + crtc_state->hw.degamma_lut =
> + drm_property_blob_get(crtc_state->uapi.degamma_lut);
> + else
> + crtc_state->hw.degamma_lut = NULL;
> +
> + if (crtc_state->uapi.gamma_lut)
> + crtc_state->hw.gamma_lut =
> + drm_property_blob_get(crtc_state->uapi.gamma_lut);
> + else
> + crtc_state->hw.gamma_lut = NULL;
> +
> + if (crtc_state->uapi.ctm)
> + crtc_state->hw.ctm =
> + drm_property_blob_get(crtc_state->uapi.ctm);
> + else
> + crtc_state->hw.ctm = NULL;
> +}
> +
> /**
> * intel_crtc_destroy_state - destroy crtc state
> * @crtc: drm crtc
> @@ -223,6 +266,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
>
> __drm_atomic_helper_crtc_destroy_state(_state->uapi);
> + intel_crtc_free_hw_state(crtc_state);
> kfree(crtc_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 58065d3161a3..42be91e0772a 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -35,6 +35,8 @@ intel_digital_connector_duplicate_state(struct
> drm_connector *connector);
> struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> void intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state);
> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 11dd7a182543..2dbc1df9505a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7110,6 +7110,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
> *crtc,
> crtc->enabled = false;
>
Re: [Intel-gfx] [PATCH 01/14] drm/i915: Rework watermark readout to use plane api
Op 24-10-2019 om 16:33 schreef Ville Syrjälä:
> On Thu, Oct 24, 2019 at 02:47:52PM +0200, Maarten Lankhorst wrote:
>> Instead of unconditionally verifying the cursor plane, handle it in the
>> same way as any other plane, and use our existing api to verify.
>>
>> While at it, ensure that on gen9+ we verify active_planes mask as well.
>> This should give the correct results for planar YUV planes too, as we
>> update active_planes for them.
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 83 ++--
>> 1 file changed, 23 insertions(+), 60 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 579655675b08..4e4273c4ae57 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -13183,7 +13183,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
>> struct skl_pipe_wm *sw_wm;
>> struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
>> const enum pipe pipe = crtc->pipe;
>> -int plane, level, max_level = ilk_wm_max_level(dev_priv);
>> +int level, max_level = ilk_wm_max_level(dev_priv);
>> +struct intel_plane *plane;
>>
>> if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
>> return;
>> @@ -13207,63 +13208,25 @@ static void verify_wm_state(struct intel_crtc
>> *crtc,
>>hw->ddb.enabled_slices);
>>
>> /* planes */
>> -for_each_universal_plane(dev_priv, pipe, plane) {
>> +for_each_intel_plane_on_crtc(_priv->drm, crtc, plane) {
>> struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
>> +enum pipe plane_pipe = pipe;
>>
>> -hw_plane_wm = >wm.planes[plane];
>> -sw_plane_wm = _wm->planes[plane];
>> -
>> -/* Watermarks */
>> -for (level = 0; level <= max_level; level++) {
>> -if (skl_wm_level_equals(_plane_wm->wm[level],
>> -_plane_wm->wm[level]))
>> -continue;
>> -
>> -DRM_ERROR("mismatch in WM pipe %c plane %d level %d
>> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
>> - pipe_name(pipe), plane + 1, level,
>> - sw_plane_wm->wm[level].plane_en,
>> - sw_plane_wm->wm[level].plane_res_b,
>> - sw_plane_wm->wm[level].plane_res_l,
>> - hw_plane_wm->wm[level].plane_en,
>> - hw_plane_wm->wm[level].plane_res_b,
>> - hw_plane_wm->wm[level].plane_res_l);
>> -}
>> +hw_plane_wm = >wm.planes[plane->id];
>> +sw_plane_wm = _wm->planes[plane->id];
>>
>> -if (!skl_wm_level_equals(_plane_wm->trans_wm,
>> - _plane_wm->trans_wm)) {
>> -DRM_ERROR("mismatch in trans WM pipe %c plane %d
>> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
>> - pipe_name(pipe), plane + 1,
>> - sw_plane_wm->trans_wm.plane_en,
>> - sw_plane_wm->trans_wm.plane_res_b,
>> - sw_plane_wm->trans_wm.plane_res_l,
>> - hw_plane_wm->trans_wm.plane_en,
>> - hw_plane_wm->trans_wm.plane_res_b,
>> - hw_plane_wm->trans_wm.plane_res_l);
>> -}
>> -
>> -/* DDB */
>> -hw_ddb_entry = >ddb_y[plane];
>> -sw_ddb_entry = _crtc_state->wm.skl.plane_ddb_y[plane];
>> -
>> -if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
>> -DRM_ERROR("mismatch in DDB state pipe %c plane %d
>> (expected (%u,%u), found (%u,%u))\n",
>> - pipe_name(pipe), plane + 1,
>> - sw_ddb_entry->start, sw_ddb_entry->end,
>> - hw_ddb_entry->start, hw_ddb_entry->end);
>> +if (!plane->get_hw_state(plane, _pipe)) {
>> +WARN(new_crtc_state->active_planes & BIT(plane->id),
>> + "pipe %c %s should be visible, but isn't\n",
>> + pipe_name(pipe), plane->base.name);
>> +continue;
>> }
> As mentioned the idea was to make sure we validate this stuff even for
> disabled planes. A bit of paranoia is good since ddb overlaps can be
> so dangerous. So I don't want such a check in this function.
Yeah should be ok.
>
>> -}
>>
>> -/*
>> - * cursor
>> - * If the cursor plane isn't active, we may not have updated it's ddb
>> - * allocation. In that case since the ddb allocation will be updated
>> - * once the plane becomes visible, we can skip this
Re: [Intel-gfx] [PATCH] drm: Add support for integrated privacy screens
On Tue 2019-10-22 17:12:06, Rajat Jain wrote: > Certain laptops now come with panels that have integrated privacy > screens on them. This patch adds support for such panels by adding > a privacy-screen property to the drm_connector for the panel, that > the userspace can then use to control and check the status. The idea > was discussed here: Much better than separate /sys interface, thanks! Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany signature.asc Description: Digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Allow gen11 to use over 32k long strides (rev2)
== Series Details == Series: drm/i915: Allow gen11 to use over 32k long strides (rev2) URL : https://patchwork.freedesktop.org/series/67077/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0e6c1e47c757 drm/i915: Allow gen11 to use over 32k long strides -:33: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV) #33: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:344: + max_stride_bytes = 65536-64; ^ total: 0 errors, 0 warnings, 1 checks, 40 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
On Thu, Oct 24, 2019 at 05:20:32PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 24, 2019 at 03:54:41PM +0200, Thierry Reding wrote:
> > On Thu, Oct 24, 2019 at 02:34:00PM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 24, 2019 at 12:31:06PM +0200, Thierry Reding wrote:
> > > > On Wed, Oct 23, 2019 at 05:00:41PM -0700, Manasi Navare wrote:
> > > > > Adaptive Sync is a VESA feature so add a DRM core helper to parse
> > > > > the EDID's detailed descritors to obtain the adaptive sync monitor
> > > > > range.
> > > > > Store this info as part fo drm_display_info so it can be used
> > > > > across all drivers.
> > > > > This part of the code is stripped out of amdgpu's function
> > > > > amdgpu_dm_update_freesync_caps() to make it generic and be used
> > > > > across all DRM drivers
> > > > >
> > > > > Cc: Ville Syrjälä
> > > > > Cc: Harry Wentland
> > > > > Cc: Clinton A Taylor
> > > > > Signed-off-by: Manasi Navare
> > > > > ---
> > > > > drivers/gpu/drm/drm_edid.c | 49
> > > > > +
> > > > > include/drm/drm_connector.h | 25 +++
> > > > > include/drm/drm_edid.h | 2 ++
> > > > > 3 files changed, 76 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > > > index 474ac04d5600..97dd1200773e 100644
> > > > > --- a/drivers/gpu/drm/drm_edid.c
> > > > > +++ b/drivers/gpu/drm/drm_edid.c
> > > > > @@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct
> > > > > drm_connector *connector,
> > > > > }
> > > > > }
> > > > >
> > > > > +void drm_get_adaptive_sync_limits(struct drm_connector *connector,
> > > > > + const struct edid *edid)
> > > > > +{
> > > > > + struct drm_display_info *info = >display_info;
> > > > > + const struct detailed_timing *timing;
> > > > > + const struct detailed_non_pixel *data;
> > > > > + const struct detailed_data_monitor_range *range;
> > > > > + int i;
> > > >
> > > > This can be unsigned int.
> > >
> > > Please no. A loop iterator called 'i' should always be a normal signed
> > > int.
> >
> > What? Where's that rule written down? In my experience it's always
> > better to use as restrictive a type as possible. It's really annoying
> > when GCC suddenly starts complaining about comparison between signed and
> > unsigned. So if a variable can never contain a signed value, why risk
> > the ambiguity? The value goes from 0 to 4, the sign bit is useless.
>
> Dunno if it's really written down anywhere. It's just something
> experience has taught. IIRC there's also a rant from Linus about this
> somewhere. Hm, can't find that one right now, but Andrew Morton also
> seems to agree: https://lwn.net/Articles/309279/
> Ah, here is one Linus rant about unsigned array indexes:
> https://yarchive.net/comp/linux/gcc.html
It's interesting that none of those actually give a real reason why
unsigned int shouldn't be used for variables called i.
> My opinion: unsigned is an very *dangerous* keyword in C that demands
> your respect. You should never use it without thinking first what the
> ramifications are. You always have to have the promotion rules clear
> in you mind when you do any kind of arithmetic with >= unsigned int
> type. And common idioms such as 'int i' should be respected so as to
> not cause unexpected hair loss to other developers when they decide
> to make the loop iterate backwards.
I would argue that when you do things like make a loop iterate backwards
you better know what variable types you're dealing with.
Anyway, this is clearly very subjective, so feel free to let this be int
if you prefer.
> > > > > + /*
> > > > > + * Restrict Adaptive Sync only for dp and edp
> > > > > + */
> > > > > + if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort
> > > > > &&
> > > > > + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> > > > > + return;
> > > > > +
> > > > > + if (edid->version <= 1 && !(edid->version == 1 &&
> > > > > edid->revision > 1))
> > > > > + return;
> > > > > +
> > > > > + for (i = 0; i < 4; i++) {
> > > > > + timing = >detailed_timings[i];
> > > > > + data= >data.other_data;
> > > > > + range = >data.range;
> > > > > + /*
> > > > > + * Check if monitor has continuous frequency mode
> > > > > + */
> > > > > + if (data->type != EDID_DETAIL_MONITOR_RANGE)
> > > > > + continue;
> > > > > + /*
> > > > > + * Check for flag range limits only. If flag == 1 then
> > > > > + * no additional timing information provided.
> > > > > + * Default GTF, GTF Secondary curve and CVT are not
> > > > > + * supported
> > > > > + */
> > > > > + if (range->flags != 1)
> > > > > + continue;
> > > > > +
> > > > > +
Re: [Intel-gfx] [PATCH 01/14] drm/i915: Rework watermark readout to use plane api
On Thu, Oct 24, 2019 at 02:47:52PM +0200, Maarten Lankhorst wrote:
> Instead of unconditionally verifying the cursor plane, handle it in the
> same way as any other plane, and use our existing api to verify.
>
> While at it, ensure that on gen9+ we verify active_planes mask as well.
> This should give the correct results for planar YUV planes too, as we
> update active_planes for them.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 83 ++--
> 1 file changed, 23 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 579655675b08..4e4273c4ae57 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13183,7 +13183,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
> struct skl_pipe_wm *sw_wm;
> struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> const enum pipe pipe = crtc->pipe;
> - int plane, level, max_level = ilk_wm_max_level(dev_priv);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> + struct intel_plane *plane;
>
> if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
> return;
> @@ -13207,63 +13208,25 @@ static void verify_wm_state(struct intel_crtc *crtc,
> hw->ddb.enabled_slices);
>
> /* planes */
> - for_each_universal_plane(dev_priv, pipe, plane) {
> + for_each_intel_plane_on_crtc(_priv->drm, crtc, plane) {
> struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> + enum pipe plane_pipe = pipe;
>
> - hw_plane_wm = >wm.planes[plane];
> - sw_plane_wm = _wm->planes[plane];
> -
> - /* Watermarks */
> - for (level = 0; level <= max_level; level++) {
> - if (skl_wm_level_equals(_plane_wm->wm[level],
> - _plane_wm->wm[level]))
> - continue;
> -
> - DRM_ERROR("mismatch in WM pipe %c plane %d level %d
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> - pipe_name(pipe), plane + 1, level,
> - sw_plane_wm->wm[level].plane_en,
> - sw_plane_wm->wm[level].plane_res_b,
> - sw_plane_wm->wm[level].plane_res_l,
> - hw_plane_wm->wm[level].plane_en,
> - hw_plane_wm->wm[level].plane_res_b,
> - hw_plane_wm->wm[level].plane_res_l);
> - }
> + hw_plane_wm = >wm.planes[plane->id];
> + sw_plane_wm = _wm->planes[plane->id];
>
> - if (!skl_wm_level_equals(_plane_wm->trans_wm,
> - _plane_wm->trans_wm)) {
> - DRM_ERROR("mismatch in trans WM pipe %c plane %d
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> - pipe_name(pipe), plane + 1,
> - sw_plane_wm->trans_wm.plane_en,
> - sw_plane_wm->trans_wm.plane_res_b,
> - sw_plane_wm->trans_wm.plane_res_l,
> - hw_plane_wm->trans_wm.plane_en,
> - hw_plane_wm->trans_wm.plane_res_b,
> - hw_plane_wm->trans_wm.plane_res_l);
> - }
> -
> - /* DDB */
> - hw_ddb_entry = >ddb_y[plane];
> - sw_ddb_entry = _crtc_state->wm.skl.plane_ddb_y[plane];
> -
> - if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> - DRM_ERROR("mismatch in DDB state pipe %c plane %d
> (expected (%u,%u), found (%u,%u))\n",
> - pipe_name(pipe), plane + 1,
> - sw_ddb_entry->start, sw_ddb_entry->end,
> - hw_ddb_entry->start, hw_ddb_entry->end);
> + if (!plane->get_hw_state(plane, _pipe)) {
> + WARN(new_crtc_state->active_planes & BIT(plane->id),
> + "pipe %c %s should be visible, but isn't\n",
> + pipe_name(pipe), plane->base.name);
> + continue;
> }
As mentioned the idea was to make sure we validate this stuff even for
disabled planes. A bit of paranoia is good since ddb overlaps can be
so dangerous. So I don't want such a check in this function.
> - }
>
> - /*
> - * cursor
> - * If the cursor plane isn't active, we may not have updated it's ddb
> - * allocation. In that case since the ddb allocation will be updated
> - * once the plane becomes visible, we can skip this check
> - */
> - if (1) {
> - struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> +
Re: [Intel-gfx] [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
On Thu, Oct 24, 2019 at 03:54:41PM +0200, Thierry Reding wrote:
> On Thu, Oct 24, 2019 at 02:34:00PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 24, 2019 at 12:31:06PM +0200, Thierry Reding wrote:
> > > On Wed, Oct 23, 2019 at 05:00:41PM -0700, Manasi Navare wrote:
> > > > Adaptive Sync is a VESA feature so add a DRM core helper to parse
> > > > the EDID's detailed descritors to obtain the adaptive sync monitor
> > > > range.
> > > > Store this info as part fo drm_display_info so it can be used
> > > > across all drivers.
> > > > This part of the code is stripped out of amdgpu's function
> > > > amdgpu_dm_update_freesync_caps() to make it generic and be used
> > > > across all DRM drivers
> > > >
> > > > Cc: Ville Syrjälä
> > > > Cc: Harry Wentland
> > > > Cc: Clinton A Taylor
> > > > Signed-off-by: Manasi Navare
> > > > ---
> > > > drivers/gpu/drm/drm_edid.c | 49 +
> > > > include/drm/drm_connector.h | 25 +++
> > > > include/drm/drm_edid.h | 2 ++
> > > > 3 files changed, 76 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > > index 474ac04d5600..97dd1200773e 100644
> > > > --- a/drivers/gpu/drm/drm_edid.c
> > > > +++ b/drivers/gpu/drm/drm_edid.c
> > > > @@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct
> > > > drm_connector *connector,
> > > > }
> > > > }
> > > >
> > > > +void drm_get_adaptive_sync_limits(struct drm_connector *connector,
> > > > + const struct edid *edid)
> > > > +{
> > > > + struct drm_display_info *info = >display_info;
> > > > + const struct detailed_timing *timing;
> > > > + const struct detailed_non_pixel *data;
> > > > + const struct detailed_data_monitor_range *range;
> > > > + int i;
> > >
> > > This can be unsigned int.
> >
> > Please no. A loop iterator called 'i' should always be a normal signed int.
>
> What? Where's that rule written down? In my experience it's always
> better to use as restrictive a type as possible. It's really annoying
> when GCC suddenly starts complaining about comparison between signed and
> unsigned. So if a variable can never contain a signed value, why risk
> the ambiguity? The value goes from 0 to 4, the sign bit is useless.
Dunno if it's really written down anywhere. It's just something
experience has taught. IIRC there's also a rant from Linus about this
somewhere. Hm, can't find that one right now, but Andrew Morton also
seems to agree: https://lwn.net/Articles/309279/
Ah, here is one Linus rant about unsigned array indexes:
https://yarchive.net/comp/linux/gcc.html
My opinion: unsigned is an very *dangerous* keyword in C that demands
your respect. You should never use it without thinking first what the
ramifications are. You always have to have the promotion rules clear
in you mind when you do any kind of arithmetic with >= unsigned int
type. And common idioms such as 'int i' should be respected so as to
not cause unexpected hair loss to other developers when they decide
to make the loop iterate backwards.
>
> > > > + /*
> > > > +* Restrict Adaptive Sync only for dp and edp
> > > > +*/
> > > > + if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort
> > > > &&
> > > > + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> > > > + return;
> > > > +
> > > > + if (edid->version <= 1 && !(edid->version == 1 &&
> > > > edid->revision > 1))
> > > > + return;
> > > > +
> > > > + for (i = 0; i < 4; i++) {
> > > > + timing = >detailed_timings[i];
> > > > + data= >data.other_data;
> > > > + range = >data.range;
> > > > + /*
> > > > +* Check if monitor has continuous frequency mode
> > > > +*/
> > > > + if (data->type != EDID_DETAIL_MONITOR_RANGE)
> > > > + continue;
> > > > + /*
> > > > +* Check for flag range limits only. If flag == 1 then
> > > > +* no additional timing information provided.
> > > > +* Default GTF, GTF Secondary curve and CVT are not
> > > > +* supported
> > > > +*/
> > > > + if (range->flags != 1)
> > > > + continue;
> > > > +
> > > > + info->adaptive_sync.min_vfreq = range->min_vfreq;
> > > > + info->adaptive_sync.max_vfreq = range->max_vfreq;
> > > > + info->adaptive_sync.pixel_clock_mhz =
> > > > + range->pixel_clock_mhz * 10;
> > > > + break;
> > > > + }
> > > > +}
> > > > +EXPORT_SYMBOL(drm_get_adaptive_sync_limits);
> > > > +
> > > > /* A connector has no EDID information, so we've got no EDID to
> > > > compute quirks from. Reset
> > > > * all of the values which would have been set
Re: [Intel-gfx] [PATCH] drm/i915/perf: Describe structure members in documentation
Quoting Lionel Landwerlin (2019-10-22 11:21:43) > On 22/10/2019 13:13, Anna Karas wrote: > > Add missing descriptions of i915_perf_stream structure members > > to documentation. > > > > Cc: Umesh Nerlige Ramappa > > Cc: Lionel Landwerlin > > Cc: Robert Bragg > > Signed-off-by: Anna Karas > > > Looks good: Reviewed-by: Lionel Landwerlin Patchwork was thrown by the 'good:' and did not recognise the r-b. Pushed, thanks all. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
On Thu, Oct 24, 2019 at 02:34:00PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 24, 2019 at 12:31:06PM +0200, Thierry Reding wrote:
> > On Wed, Oct 23, 2019 at 05:00:41PM -0700, Manasi Navare wrote:
> > > Adaptive Sync is a VESA feature so add a DRM core helper to parse
> > > the EDID's detailed descritors to obtain the adaptive sync monitor range.
> > > Store this info as part fo drm_display_info so it can be used
> > > across all drivers.
> > > This part of the code is stripped out of amdgpu's function
> > > amdgpu_dm_update_freesync_caps() to make it generic and be used
> > > across all DRM drivers
> > >
> > > Cc: Ville Syrjälä
> > > Cc: Harry Wentland
> > > Cc: Clinton A Taylor
> > > Signed-off-by: Manasi Navare
> > > ---
> > > drivers/gpu/drm/drm_edid.c | 49 +
> > > include/drm/drm_connector.h | 25 +++
> > > include/drm/drm_edid.h | 2 ++
> > > 3 files changed, 76 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > index 474ac04d5600..97dd1200773e 100644
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct drm_connector
> > > *connector,
> > > }
> > > }
> > >
> > > +void drm_get_adaptive_sync_limits(struct drm_connector *connector,
> > > + const struct edid *edid)
> > > +{
> > > + struct drm_display_info *info = >display_info;
> > > + const struct detailed_timing *timing;
> > > + const struct detailed_non_pixel *data;
> > > + const struct detailed_data_monitor_range *range;
> > > + int i;
> >
> > This can be unsigned int.
>
> Please no. A loop iterator called 'i' should always be a normal signed int.
What? Where's that rule written down? In my experience it's always
better to use as restrictive a type as possible. It's really annoying
when GCC suddenly starts complaining about comparison between signed and
unsigned. So if a variable can never contain a signed value, why risk
the ambiguity? The value goes from 0 to 4, the sign bit is useless.
> > > + /*
> > > + * Restrict Adaptive Sync only for dp and edp
> > > + */
> > > + if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
> > > + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> > > + return;
> > > +
> > > + if (edid->version <= 1 && !(edid->version == 1 && edid->revision > 1))
> > > + return;
> > > +
> > > + for (i = 0; i < 4; i++) {
> > > + timing = >detailed_timings[i];
> > > + data= >data.other_data;
> > > + range = >data.range;
> > > + /*
> > > + * Check if monitor has continuous frequency mode
> > > + */
> > > + if (data->type != EDID_DETAIL_MONITOR_RANGE)
> > > + continue;
> > > + /*
> > > + * Check for flag range limits only. If flag == 1 then
> > > + * no additional timing information provided.
> > > + * Default GTF, GTF Secondary curve and CVT are not
> > > + * supported
> > > + */
> > > + if (range->flags != 1)
> > > + continue;
> > > +
> > > + info->adaptive_sync.min_vfreq = range->min_vfreq;
> > > + info->adaptive_sync.max_vfreq = range->max_vfreq;
> > > + info->adaptive_sync.pixel_clock_mhz =
> > > + range->pixel_clock_mhz * 10;
> > > + break;
> > > + }
> > > +}
> > > +EXPORT_SYMBOL(drm_get_adaptive_sync_limits);
> > > +
> > > /* A connector has no EDID information, so we've got no EDID to compute
> > > quirks from. Reset
> > > * all of the values which would have been set from EDID
> > > */
> > > @@ -4728,6 +4774,7 @@ drm_reset_display_info(struct drm_connector
> > > *connector)
> > > memset(>hdmi, 0, sizeof(info->hdmi));
> > >
> > > info->non_desktop = 0;
> > > + memset(>adaptive_sync, 0, sizeof(info->adaptive_sync));
> > > }
> > >
> > > u32 drm_add_display_info(struct drm_connector *connector, const struct
> > > edid *edid)
> > > @@ -4743,6 +4790,8 @@ u32 drm_add_display_info(struct drm_connector
> > > *connector, const struct edid *edi
> > >
> > > info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
> > >
> > > + drm_get_adaptive_sync_limits(connector, edid);
> > > +
> > > DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
> > >
> > > if (edid->revision < 3)
> > > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> > > index 5f8c3389d46f..a27a84270d8d 100644
> > > --- a/include/drm/drm_connector.h
> > > +++ b/include/drm/drm_connector.h
> > > @@ -254,6 +254,26 @@ enum drm_panel_orientation {
> > > DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
> > > };
> > >
> > > +/**
> > > + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for
> > > + * _display_info
> > > + *
> > > + * This struct is used to store a Panel's Adaptive Sync capabilities
> > > + * as parsed from EDID's
[Intel-gfx] [PATCH] drm/i915/selftests: Mock the engine sorting for easy validation
To make exploration of different sorting orders and presentation of the
engines via the uabi easier, wrap the basic engine registration into a
mock (aka standalone) selftest.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 +
.../gpu/drm/i915/gt/selftest_engine_user.c| 86 +++
.../drm/i915/selftests/i915_mock_selftests.h | 3 +-
3 files changed, 92 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_user.c
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 7f7150a733f4..15bb05aa1986 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -293,3 +293,7 @@ unsigned int intel_engines_has_context_isolation(struct
drm_i915_private *i915)
return which;
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_engine_user.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_user.c
b/drivers/gpu/drm/i915/gt/selftest_engine_user.c
new file mode 100644
index ..d11cc6a4af09
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_user.c
@@ -0,0 +1,86 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+static void destroy_engines(struct drm_i915_private *i915)
+{
+ struct intel_engine_cs *engine, *next;
+
+ rbtree_postorder_for_each_entry_safe(engine, next,
+>uabi_engines, uabi_node)
+ kfree(engine);
+}
+
+static int mock_uabi_engines(void *arg)
+{
+ static const u8 limits[] = {
+ [RENDER_CLASS] = 1,
+ [COPY_ENGINE_CLASS] = 1,
+ [VIDEO_DECODE_CLASS] = I915_MAX_VCS,
+ [VIDEO_ENHANCEMENT_CLASS] = I915_MAX_VECS,
+ };
+ struct intel_engine_cs *engine;
+ struct drm_i915_private *i915;
+ unsigned long num_engines;
+ unsigned long found;
+ int c, i;
+ int err = 0;
+
+ i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
+ if (!i915)
+ return -ENOMEM;
+
+ num_engines = 0;
+ for (c = 0; c < ARRAY_SIZE(limits); c++) {
+ for (i = 0; i < limits[c]; i++) {
+ engine = kzalloc(sizeof(*engine), GFP_KERNEL);
+ if (!engine)
+ goto err;
+
+ engine->i915 = i915;
+
+ engine->class = c;
+ engine->instance = i;
+
+ intel_engine_add_user(engine);
+ num_engines++;
+ }
+ }
+
+err:
+ /* Check as far as we got up to -- will explode if not quite right */
+ intel_engines_driver_register(i915);
+
+ found = 0;
+ for_each_uabi_engine(engine, i915) {
+ pr_info("%s (%d, %d) -> [%d, %d]\n",
+ engine->name,
+ engine->uabi_class,
+ engine->uabi_instance,
+ engine->class,
+ engine->instance);
+ found++;
+ }
+ if (found != num_engines) {
+ pr_err("Registered %lu engines; only found %lu uABI engines\n",
+ num_engines, found);
+ err = -EINVAL;
+ }
+
+ destroy_engines(i915);
+ kfree(i915);
+ return err;
+}
+
+int intel_engine_user_mock_selftests(void)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(mock_uabi_engines),
+ };
+
+ return i915_subtests(tests, NULL);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
index aa5a0e7f5d9e..9a2dd8350650 100644
--- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
@@ -14,7 +14,8 @@ selftest(fence, i915_sw_fence_mock_selftests)
selftest(scatterlist, scatterlist_mock_selftests)
selftest(syncmap, i915_syncmap_mock_selftests)
selftest(uncore, intel_uncore_mock_selftests)
-selftest(engine, intel_engine_cs_mock_selftests)
+selftest(engine_cs, intel_engine_cs_mock_selftests)
+selftest(engine_user, intel_engine_user_mock_selftests)
selftest(timelines, intel_timeline_mock_selftests)
selftest(requests, i915_request_mock_selftests)
selftest(objects, i915_gem_object_mock_selftests)
--
2.24.0.rc0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 1/1] drm/i915/dsi: Add dsi_state in crtc_state
On Wed, Oct 16, 2019 at 06:22:36PM +0530, Vandita Kulkarni wrote:
> This patch add dsi_state which provides
> dsi operation mode and the link mode.
> These are needed in order to check if they
> were differently configured by GOP.
>
> In present case the GOP enables dsi in
> periodic update mode, whereas we need
> to enable it in TE_GATE command mode.
> In which case a disable-enable sequence
> would be required.
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c| 39 +++
> .../drm/i915/display/intel_display_types.h| 12 ++
> 2 files changed, 51 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 6e398c33a524..0a9323e95866 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1238,6 +1238,37 @@ static void gen11_dsi_get_timings(struct intel_encoder
> *encoder,
> adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
> }
>
> +static bool
> +gen11_dsi_dual_link_enabled(struct drm_i915_private *dev_priv)
> +{
> + u32 val1, val2;
> +
> + val1 = I915_READ(PIPECONF(TRANSCODER_DSI_0)) &
> + I915_READ(PIPECONF(TRANSCODER_DSI_1));
> + val1 &= PIPECONF_ENABLE;
> +
> + val2 = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
> + val2 &= PORT_SYNC_MODE_ENABLE;
> +
> + return (val1 && val2);
> +}
> +
> +static enum dsi_op_mode
> +gen11_dsi_get_op_mode(struct drm_i915_private *dev_priv,
> + struct intel_dsi *intel_dsi)
> +{
> + u32 val;
> + enum transcoder dsi_trans;
> +
> + if (intel_dsi->ports == BIT(PORT_B))
> + dsi_trans = TRANSCODER_DSI_1;
> + else
> + dsi_trans = TRANSCODER_DSI_0;
> +
> + val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
> + return ((val &= OP_MODE_MASK) >> OP_MODE_SHIFT);
> +}
> +
> static void gen11_dsi_get_config(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config)
> {
> @@ -1250,6 +1281,12 @@ static void gen11_dsi_get_config(struct intel_encoder
> *encoder,
> cnl_calc_wrpll_link(dev_priv, _config->dpll_hw_state);
>
> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> +
> + pipe_config->dsi_state.dual_link_mode =
> + gen11_dsi_dual_link_enabled(dev_priv);
> + pipe_config->dsi_state.op_mode =
> + gen11_dsi_get_op_mode(dev_priv, intel_dsi);
> +
> if (intel_dsi->dual_link)
> pipe_config->base.adjusted_mode.crtc_clock *= 2;
>
> @@ -1283,6 +1320,8 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,
> else
> pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
>
> + pipe_config->dsi_state.op_mode = DSI_CMD_MODE_NO_GATE;
> + pipe_config->dsi_state.dual_link_mode = intel_dsi->dual_link;
> pipe_config->clock_set = true;
> pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 40390d855815..f89917eb4b94 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -75,6 +75,13 @@ enum hdmi_force_audio {
> HDMI_AUDIO_ON, /* force turn on HDMI audio */
> };
>
> +enum dsi_op_mode {
> + DSI_CMD_MODE_NO_GATE,
> + DSI_CMD_MODE_TE_GATE,
> + DSI_CMD_MODE_PERIODIC,
> + DSI_VIDEO_MODE,
> + };
> +
> /* "Broadcast RGB" property */
> enum intel_broadcast_rgb {
> INTEL_BROADCAST_RGB_AUTO,
> @@ -861,6 +868,11 @@ struct intel_crtc_state {
> u32 ctrl, div;
> } dsi_pll;
>
> + struct {
> + enum dsi_op_mode op_mode;
> + bool dual_link_mode;
'dual_link' seems sufficient. And we should share that with LVDS.
Another easy target for moving to the crtc state is the lane count.
In fact we already have it in the state, but the DSI code has just
stubbornly decided to ingore it.
> + } dsi_state;
> +
> int pipe_bpp;
> struct intel_link_m_n dp_m_n;
>
> --
> 2.21.0.5.gaeb582a
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 5/5] drm/i915: No ce->gem_context for kernel_context
Having weaned GT from requiring ce->gem_context, we can stop referencing
it entirely. This also means we no longer have to create random and
unnecessary GEM contexts for internal use. GEM contexts are now entirely
for tracking GEM clients, and intel_context the execution environment on
the GPU.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 53 +++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 -
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 3 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 2 +-
.../gpu/drm/i915/gem/selftests/mock_context.c | 11 ++-
drivers/gpu/drm/i915/gt/intel_context.c | 26 ++
drivers/gpu/drm/i915/gt/intel_context.h | 4 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 15 ++--
drivers/gpu/drm/i915/gt/intel_lrc.h | 6 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 6 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_context.c| 45 +++---
.../drm/i915/gt/selftest_engine_heartbeat.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 85 ---
drivers/gpu/drm/i915/gvt/scheduler.c | 16 ++--
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 8 +-
drivers/gpu/drm/i915/i915_request.c | 49 +--
19 files changed, 132 insertions(+), 211 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 5ea962c19f22..132b341a5381 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -170,6 +170,24 @@ lookup_user_engine(struct i915_gem_context *ctx,
return i915_gem_context_get_engine(ctx, idx);
}
+static void intel_context_set_gem(struct intel_context *ce,
+ struct i915_gem_context *ctx)
+{
+ ce->gem_context = ctx;
+
+ if (ctx->vm) {
+ i915_vm_put(ce->vm);
+ ce->vm = i915_vm_get(ctx->vm);
+ }
+
+ if (ctx->timeline)
+ ce->timeline = intel_timeline_get(ctx->timeline);
+
+ if (ctx->sched.priority >= I915_PRIORITY_NORMAL &&
+ intel_engine_has_semaphores(ce->engine))
+ __set_bit(CONTEXT_USE_SEMAPHORES, >flags);
+}
+
static void __free_engines(struct i915_gem_engines *e, unsigned int count)
{
while (count--) {
@@ -212,12 +230,14 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES);
GEM_BUG_ON(e->engines[engine->legacy_idx]);
- ce = intel_context_create(ctx, engine);
+ ce = intel_context_create(engine);
if (IS_ERR(ce)) {
__free_engines(e, e->num_engines + 1);
return ERR_CAST(ce);
}
+ intel_context_set_gem(ce, ctx);
+
e->engines[engine->legacy_idx] = ce;
e->num_engines = max(e->num_engines, engine->legacy_idx);
}
@@ -605,23 +625,6 @@ i915_gem_create_context(struct drm_i915_private *i915,
unsigned int flags)
return ctx;
}
-struct i915_gem_context *
-i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
-{
- struct i915_gem_context *ctx;
-
- ctx = i915_gem_create_context(i915, 0);
- if (IS_ERR(ctx))
- return ctx;
-
- i915_gem_context_clear_bannable(ctx);
- ctx->sched.priority = I915_USER_PRIORITY(prio);
-
- GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
-
- return ctx;
-}
-
static void init_contexts(struct i915_gem_contexts *gc)
{
spin_lock_init(>lock);
@@ -1394,12 +1397,14 @@ set_engines__load_balance(struct i915_user_extension
__user *base, void *data)
}
}
- ce = intel_execlists_create_virtual(set->ctx, siblings, n);
+ ce = intel_execlists_create_virtual(siblings, n);
if (IS_ERR(ce)) {
err = PTR_ERR(ce);
goto out_siblings;
}
+ intel_context_set_gem(ce, set->ctx);
+
if (cmpxchg(>engines->engines[idx], NULL, ce)) {
intel_context_put(ce);
err = -EEXIST;
@@ -1569,12 +1574,14 @@ set_engines(struct i915_gem_context *ctx,
return -ENOENT;
}
- ce = intel_context_create(ctx, engine);
+ ce = intel_context_create(engine);
if (IS_ERR(ce)) {
__free_engines(set.engines, n);
return PTR_ERR(ce);
}
+ intel_context_set_gem(ce, ctx);
+
set.engines->engines[n] = ce;
}
set.engines->num_engines = num_engines;
@@ -1861,13 +1868,15 @@ static int clone_engines(struct i915_gem_context
[Intel-gfx] [RFC 3/5] drm/i915: Remove i915->kernel_context
Allocate only an internal intel_context for the kernel_context, forgoing
a global GEM context for internal use as we only require a separate
address space (for our own protection).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 35 +--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 5 ++-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 11 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 3 --
drivers/gpu/drm/i915/i915_gem.c | 16 ++---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++---
drivers/gpu/drm/i915/i915_perf.c | 3 --
drivers/gpu/drm/i915/i915_request.c | 5 ++-
drivers/gpu/drm/i915/selftests/i915_request.c | 6 +---
.../gpu/drm/i915/selftests/mock_gem_device.c | 8 +
13 files changed, 29 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index f34dc440b37e..5ea962c19f22 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -605,19 +605,6 @@ i915_gem_create_context(struct drm_i915_private *i915,
unsigned int flags)
return ctx;
}
-static void
-destroy_kernel_context(struct i915_gem_context **ctxp)
-{
- struct i915_gem_context *ctx;
-
- /* Keep the context ref so that we can free it immediately ourselves */
- ctx = i915_gem_context_get(fetch_and_zero(ctxp));
- GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
-
- context_close(ctx);
- i915_gem_context_free(ctx);
-}
-
struct i915_gem_context *
i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
{
@@ -644,32 +631,12 @@ static void init_contexts(struct i915_gem_contexts *gc)
init_llist_head(>free_list);
}
-int i915_gem_init_contexts(struct drm_i915_private *i915)
+void i915_gem_init_contexts(struct drm_i915_private *i915)
{
- struct i915_gem_context *ctx;
-
- /* Reassure ourselves we are only called once */
- GEM_BUG_ON(i915->kernel_context);
-
init_contexts(>gem.contexts);
-
- /* lowest priority; idle task */
- ctx = i915_gem_context_create_kernel(i915, I915_PRIORITY_MIN);
- if (IS_ERR(ctx)) {
- DRM_ERROR("Failed to create default global context\n");
- return PTR_ERR(ctx);
- }
- i915->kernel_context = ctx;
-
DRM_DEBUG_DRIVER("%s context support initialized\n",
DRIVER_CAPS(i915)->has_logical_contexts ?
"logical" : "fake");
- return 0;
-}
-
-void i915_gem_driver_release__contexts(struct drm_i915_private *i915)
-{
- destroy_kernel_context(>kernel_context);
}
static int context_idr_cleanup(int id, void *p, void *data)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 6d2263658edb..3844b1b14849 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -100,8 +100,7 @@ static inline bool i915_gem_context_is_kernel(struct
i915_gem_context *ctx)
}
/* i915_gem_context.c */
-int __must_check i915_gem_init_contexts(struct drm_i915_private *i915);
-void i915_gem_driver_release__contexts(struct drm_i915_private *i915);
+void i915_gem_init_contexts(struct drm_i915_private *i915);
int i915_gem_context_open(struct drm_i915_private *i915,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 1e045c337044..70df7c97b55d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -759,9 +759,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
* On almost all of the older hw, we cannot tell the GPU that
* a page is readonly.
*/
- vm = rcu_dereference_protected(dev_priv->kernel_context->vm,
- true); /* static vm */
- if (!vm || !vm->has_read_only)
+ vm = dev_priv->gt.kernel_vm;
+ if (!vm->has_read_only)
return -ENODEV;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f14f877719c7..db9736cb06e4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -754,11 +754,12 @@ create_kernel_context(struct intel_engine_cs *engine)
struct intel_context *ce;
int err;
- ce = intel_context_create(engine->i915->kernel_context, engine);
+ ce = intel_context_create(NULL, engine);
if (IS_ERR(ce))
return ce;
ce->ring =
[Intel-gfx] [RFC 2/5] drm/i915: Push the use-semaphore marker onto the intel_context
Instead of rummaging through the intel_context to peek at the GEM
context in the middle of request submission to decide whether to use
semaphores, store that information on the intel_context itself.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 52 +--
drivers/gpu/drm/i915/gt/intel_context.c | 3 ++
drivers/gpu/drm/i915/gt/intel_context.h | 15 ++
drivers/gpu/drm/i915/gt/intel_context_types.h | 7 +--
drivers/gpu/drm/i915/i915_request.c | 8 ++-
5 files changed, 60 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index efa4f7c762c3..f34dc440b37e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1738,6 +1738,40 @@ get_engines(struct i915_gem_context *ctx,
return err;
}
+static void __apply_priority(struct intel_context *ce, void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+
+ if (intel_context_use_semaphores(ce) &&
+ ctx->sched.priority < I915_PRIORITY_NORMAL)
+ intel_context_clear_use_semaphores(ce);
+}
+
+static int set_priority(struct i915_gem_context *ctx,
+ const struct drm_i915_gem_context_param *args)
+{
+ s64 priority = args->value;
+
+ if (args->size)
+ return -EINVAL;
+
+ if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
+ return -ENODEV;
+
+ if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
+ priority < I915_CONTEXT_MIN_USER_PRIORITY)
+ return -EINVAL;
+
+ if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
+ !capable(CAP_SYS_NICE))
+ return -EPERM;
+
+ ctx->sched.priority = I915_USER_PRIORITY(priority);
+ context_apply_all(ctx, __apply_priority, ctx);
+
+ return 0;
+}
+
static int ctx_setparam(struct drm_i915_file_private *fpriv,
struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -1784,23 +1818,7 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
break;
case I915_CONTEXT_PARAM_PRIORITY:
- {
- s64 priority = args->value;
-
- if (args->size)
- ret = -EINVAL;
- else if (!(ctx->i915->caps.scheduler &
I915_SCHEDULER_CAP_PRIORITY))
- ret = -ENODEV;
- else if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
-priority < I915_CONTEXT_MIN_USER_PRIORITY)
- ret = -EINVAL;
- else if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
-!capable(CAP_SYS_NICE))
- ret = -EPERM;
- else
- ctx->sched.priority =
- I915_USER_PRIORITY(priority);
- }
+ ret = set_priority(ctx, args);
break;
case I915_CONTEXT_PARAM_SSEU:
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 625f75f7825d..7075d03f508f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -238,6 +238,9 @@ intel_context_init(struct intel_context *ce,
rcu_read_unlock();
if (ctx->timeline)
ce->timeline = intel_timeline_get(ctx->timeline);
+ if (ctx->sched.priority >= I915_PRIORITY_NORMAL &&
+ intel_engine_has_semaphores(engine))
+ __set_bit(CONTEXT_USE_SEMAPHORES, >flags);
ce->engine = engine;
ce->ops = engine->cops;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 1e607343d256..d7b667a26e08 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -155,6 +155,21 @@ static inline struct intel_ring
*__intel_context_ring_size(u64 sz)
return u64_to_ptr(struct intel_ring, sz);
}
+static inline bool intel_context_use_semaphores(const struct intel_context *ce)
+{
+ return test_bit(CONTEXT_USE_SEMAPHORES, >flags);
+}
+
+static inline void intel_context_set_use_semaphores(struct intel_context *ce)
+{
+ set_bit(CONTEXT_USE_SEMAPHORES, >flags);
+}
+
+static inline void intel_context_clear_use_semaphores(struct intel_context *ce)
+{
+ clear_bit(CONTEXT_USE_SEMAPHORES, >flags);
+}
+
static inline bool intel_context_is_banned(const struct intel_context *ce)
{
return test_bit(CONTEXT_BANNED, >flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 0251edc8f568..264c1efde772 100644
---
[Intel-gfx] [RFC 4/5] drm/i915: Drop GEM context reference while pinned
Ostensibly, as far recorded at least, we take a reference to our GEM context parent to keep the ppgtt alive as long as we are pinned. Now that the context holds a reference to the ppgtt itself, we should no longer need the back reference. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_context.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 7075d03f508f..7b04a3ca19bd 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -72,8 +72,6 @@ int __intel_context_do_pin(struct intel_context *ce) ce->engine->name, ce->timeline->fence_context, ce->ring->head, ce->ring->tail); - i915_gem_context_get(ce->gem_context); /* for ctx->ppgtt */ - smp_mb__before_atomic(); /* flush pin before it is visible */ } @@ -103,7 +101,6 @@ void intel_context_unpin(struct intel_context *ce) ce->ops->unpin(ce); - i915_gem_context_put(ce->gem_context); intel_context_active_release(ce); } -- 2.24.0.rc0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 1/5] drm/i915: Drop GEM context as a direct link from i915_request
Keep the intel_context as being the primary state for i915_request, with
the GEM context a backpointer from the low level state for the rarer
cases we need client information. Our goal is to remove such references
to clients from the backend, and leave the HW submission agnostic to
client interfaces and self-contained.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++
drivers/gpu/drm/i915/gem/i915_gem_context.h | 38 ---
.../gpu/drm/i915/gem/i915_gem_context_types.h | 7 +--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 ++--
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context.h | 42
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +--
drivers/gpu/drm/i915/gt/intel_lrc.c | 48 +--
drivers/gpu/drm/i915/gt/intel_reset.c | 38 ---
.../gpu/drm/i915/gt/intel_ring_submission.c | 10 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c| 20
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +--
drivers/gpu/drm/i915/gvt/scheduler.c | 27 +--
drivers/gpu/drm/i915/i915_gem.c | 6 +--
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++--
drivers/gpu/drm/i915/i915_perf.c | 4 +-
drivers/gpu/drm/i915/i915_request.c | 15 +++---
drivers/gpu/drm/i915/i915_request.h | 3 +-
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
21 files changed, 159 insertions(+), 158 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 55f1f93c0925..efa4f7c762c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -69,6 +69,7 @@
#include
+#include "gt/intel_context.h"
#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_lrc_reg.h"
@@ -364,15 +365,6 @@ static void kill_context(struct i915_gem_context *ctx)
struct i915_gem_engines_iter it;
struct intel_context *ce;
- /*
-* If we are already banned, it was due to a guilty request causing
-* a reset and the entire context being evicted from the GPU.
-*/
- if (i915_gem_context_is_banned(ctx))
- return;
-
- i915_gem_context_set_banned(ctx);
-
/*
* Map the user's engine back to the actual engines; one virtual
* engine will be mapped to multiple engines, and using ctx->engine[]
@@ -384,6 +376,9 @@ static void kill_context(struct i915_gem_context *ctx)
struct intel_engine_cs *engine;
struct dma_fence *fence;
+ if (!intel_context_set_banned(ce))
+ continue;
+
if (!ce->timeline)
continue;
@@ -996,7 +991,7 @@ static void set_ppgtt_barrier(void *data)
static int emit_ppgtt_update(struct i915_request *rq, void *data)
{
- struct i915_address_space *vm = rq->hw_context->vm;
+ struct i915_address_space *vm = rq->context->vm;
struct intel_engine_cs *engine = rq->engine;
u32 base = engine->mmio_base;
u32 *cs;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index cfe80590f0ed..6d2263658edb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -76,26 +76,6 @@ static inline void i915_gem_context_clear_recoverable(struct
i915_gem_context *c
clear_bit(UCONTEXT_RECOVERABLE, >user_flags);
}
-static inline bool i915_gem_context_is_banned(const struct i915_gem_context
*ctx)
-{
- return test_bit(CONTEXT_BANNED, >flags);
-}
-
-static inline void i915_gem_context_set_banned(struct i915_gem_context *ctx)
-{
- set_bit(CONTEXT_BANNED, >flags);
-}
-
-static inline bool i915_gem_context_force_single_submission(const struct
i915_gem_context *ctx)
-{
- return test_bit(CONTEXT_FORCE_SINGLE_SUBMISSION, >flags);
-}
-
-static inline void i915_gem_context_set_force_single_submission(struct
i915_gem_context *ctx)
-{
- __set_bit(CONTEXT_FORCE_SINGLE_SUBMISSION, >flags);
-}
-
static inline bool
i915_gem_context_user_engines(const struct i915_gem_context *ctx)
{
@@ -114,24 +94,6 @@ i915_gem_context_clear_user_engines(struct i915_gem_context
*ctx)
clear_bit(CONTEXT_USER_ENGINES, >flags);
}
-static inline bool
-i915_gem_context_nopreempt(const struct i915_gem_context *ctx)
-{
- return test_bit(CONTEXT_NOPREEMPT, >flags);
-}
-
-static inline void
-i915_gem_context_set_nopreempt(struct i915_gem_context *ctx)
-{
- set_bit(CONTEXT_NOPREEMPT, >flags);
-}
-
-static inline void
-i915_gem_context_clear_nopreempt(struct i915_gem_context *ctx)
-{
- clear_bit(CONTEXT_NOPREEMPT,
[Intel-gfx] [PATCH 12/14] drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi.
Split up plane_state->base to uapi. This is done using the following patch,
ran after the previous commit that splits out any hw references:
@@
struct intel_plane_state *T;
identifier x;
@@
-T->base.x
+T->uapi.x
@@
struct intel_plane_state *T;
@@
-T->base
+T->uapi
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 28 +-
drivers/gpu/drm/i915/display/intel_display.c | 296 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 12 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 114 +++
drivers/gpu/drm/i915/intel_pm.c | 57 ++--
7 files changed, 257 insertions(+), 254 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 9ba50fd1116c..4783d7ff4fcf 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -299,7 +299,7 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
if (plane_state && plane_state->hw.fb &&
plane_state->hw.fb->format->is_yuv &&
plane_state->hw.fb->format->num_planes > 1) {
- struct intel_plane *plane =
to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane =
to_intel_plane(plane_state->uapi.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
mode = SKL_PS_SCALER_MODE_NV12;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index fd5a8012859c..e4044abc2d21 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -56,7 +56,7 @@ struct intel_plane *intel_plane_alloc(void)
return ERR_PTR(-ENOMEM);
}
- __drm_atomic_helper_plane_reset(>base, _state->base);
+ __drm_atomic_helper_plane_reset(>base, _state->uapi);
plane_state->scaler_id = -1;
return plane;
@@ -88,12 +88,12 @@ intel_plane_duplicate_state(struct drm_plane *plane)
if (!intel_state)
return NULL;
- __drm_atomic_helper_plane_duplicate_state(plane, _state->base);
+ __drm_atomic_helper_plane_duplicate_state(plane, _state->uapi);
intel_state->vma = NULL;
intel_state->flags = 0;
- return _state->base;
+ return _state->uapi;
}
/**
@@ -111,7 +111,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
struct intel_plane_state *plane_state = to_intel_plane_state(state);
WARN_ON(plane_state->vma);
- __drm_atomic_helper_plane_destroy_state(_state->base);
+ __drm_atomic_helper_plane_destroy_state(_state->uapi);
kfree(plane_state);
}
@@ -121,7 +121,7 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
cpp = fb->format->cpp[0];
@@ -143,7 +143,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state
*new_plane_state)
{
- struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
const struct drm_framebuffer *fb = new_plane_state->hw.fb;
int ret;
@@ -151,7 +151,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
new_crtc_state->data_rate[plane->id] = 0;
- new_plane_state->base.visible = false;
+ new_plane_state->uapi.visible = false;
if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
@@ -161,18 +161,18 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
return ret;
/* FIXME pre-g4x don't work like this */
- if (new_plane_state->base.visible)
+ if (new_plane_state->uapi.visible)
new_crtc_state->active_planes |= BIT(plane->id);
- if (new_plane_state->base.visible &&
+ if (new_plane_state->uapi.visible &&
drm_format_info_is_yuv_semiplanar(fb->format))
new_crtc_state->nv12_planes |= BIT(plane->id);
- if (new_plane_state->base.visible &&
+ if (new_plane_state->uapi.visible &&
fb->format->format == DRM_FORMAT_C8)
new_crtc_state->c8_planes |= BIT(plane->id);
- if
[Intel-gfx] [PATCH 06/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
@@
struct intel_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->hw.x
@@
struct drm_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-to_intel_crtc_state(T)->base.x
+to_intel_crtc_state(T)->hw.x
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c| 12 +-
drivers/gpu/drm/i915/display/intel_audio.c| 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c| 8 +-
drivers/gpu/drm/i915/display/intel_color.c| 108
drivers/gpu/drm/i915/display/intel_crt.c | 18 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +-
drivers/gpu/drm/i915/display/intel_display.c | 262 +-
drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 12 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 4 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 8 +-
drivers/gpu/drm/i915/display/intel_panel.c| 8 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 12 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 16 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 8 +-
drivers/gpu/drm/i915/display/intel_tv.c | 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
drivers/gpu/drm/i915/display/vlv_dsi.c| 10 +-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/intel_pm.c | 62 ++---
24 files changed, 321 insertions(+), 317 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6e398c33a524..4ec493e4755b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder
*encoder,
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
const struct drm_display_mode *adjusted_mode =
- _config->base.adjusted_mode;
+ _config->hw.adjusted_mode;
u32 dss_ctl2;
u16 hactive = adjusted_mode->crtc_hdisplay;
u16 dl_buffer_depth;
@@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
const struct drm_display_mode *adjusted_mode =
- _config->base.adjusted_mode;
+ _config->hw.adjusted_mode;
enum port port;
enum transcoder dsi_trans;
/* horizontal timings */
@@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder
*encoder,
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
struct drm_display_mode *adjusted_mode =
- _config->base.adjusted_mode;
+ _config->hw.adjusted_mode;
if (intel_dsi->dual_link) {
adjusted_mode->crtc_hdisplay *= 2;
@@ -1249,9 +1249,9 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
pipe_config->port_clock =
cnl_calc_wrpll_link(dev_priv, _config->dpll_hw_state);
- pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+ pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
if (intel_dsi->dual_link)
- pipe_config->base.adjusted_mode.crtc_clock *= 2;
+ pipe_config->hw.adjusted_mode.crtc_clock *= 2;
gen11_dsi_get_timings(encoder, pipe_config);
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
@@ -1269,7 +1269,7 @@ static int gen11_dsi_compute_config(struct intel_encoder
*encoder,
const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode =
- _config->base.adjusted_mode;
+ _config->hw.adjusted_mode;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index ed18511befa3..6a58e8ad86f8 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -233,7 +233,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
static
[Intel-gfx] [PATCH 03/14] drm/i915: Handle a few more cases for crtc hw/uapi split, v3.
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead.
Changes since v1:
- Move to before uapi/hw split.
- Add hunks for intel_pm.c as well.
Changes since v2:
- Incorporate Ville's feedback.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 15 ---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 12
drivers/gpu/drm/i915/display/intel_psr.c | 16 +++-
drivers/gpu/drm/i915/intel_pm.c | 6 ++
4 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4e4273c4ae57..0c0dae8097b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16528,8 +16528,7 @@ static int intel_initial_commit(struct drm_device *dev)
{
struct drm_atomic_state *state = NULL;
struct drm_modeset_acquire_ctx ctx;
- struct drm_crtc *crtc;
- struct drm_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
int ret = 0;
state = drm_atomic_state_alloc(dev);
@@ -16541,15 +16540,17 @@ static int intel_initial_commit(struct drm_device
*dev)
retry:
state->acquire_ctx =
- drm_for_each_crtc(crtc, dev) {
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ for_each_intel_crtc(dev, crtc) {
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_crtc_state(state, crtc);
+
if (IS_ERR(crtc_state)) {
ret = PTR_ERR(crtc_state);
goto out;
}
- if (crtc_state->active) {
- ret = drm_atomic_add_affected_planes(state, crtc);
+ if (crtc_state->base.active) {
+ ret = drm_atomic_add_affected_planes(state,
>base);
if (ret)
goto out;
@@ -16559,7 +16560,7 @@ static int intel_initial_commit(struct drm_device *dev)
* having a proper LUT loaded. Remove once we
* have readout for pipe gamma enable.
*/
- crtc_state->color_mgmt_changed = true;
+ crtc_state->base.color_mgmt_changed = true;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index bbcab27644dc..bb1b3180ccfd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -168,7 +168,6 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
struct intel_connector *intel_connector =
to_intel_connector(connector);
struct drm_crtc *new_crtc = new_conn_state->crtc;
- struct drm_crtc_state *crtc_state;
struct drm_dp_mst_topology_mgr *mgr;
int ret;
@@ -183,11 +182,16 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
* connector
*/
if (new_crtc) {
- crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(state);
+ struct intel_crtc *intel_crtc = to_intel_crtc(new_crtc);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(intel_state,
+ intel_crtc);
if (!crtc_state ||
- !drm_atomic_crtc_needs_modeset(crtc_state) ||
- crtc_state->enable)
+ !drm_atomic_crtc_needs_modeset(_state->base) ||
+ crtc_state->base.enable)
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index dfbedff98ea8..a8f3edc9c482 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include "display/intel_dp.h"
#include "i915_drv.h"
+#include "intel_atomic.h"
#include "intel_display_types.h"
#include "intel_psr.h"
#include "intel_sprite.h"
@@ -1116,7 +1117,7 @@ static int intel_psr_fastset_force(struct
drm_i915_private *dev_priv)
struct drm_device *dev = _priv->drm;
struct drm_modeset_acquire_ctx ctx;
struct drm_atomic_state *state;
- struct drm_crtc *crtc;
+ struct intel_crtc *crtc;
int err;
state = drm_atomic_state_alloc(dev);
@@ -1127,21 +1128,18 @@ static int intel_psr_fastset_force(struct
drm_i915_private *dev_priv)
state->acquire_ctx =
retry:
- drm_for_each_crtc(crtc, dev) {
- struct drm_crtc_state *crtc_state;
- struct
[Intel-gfx] [PATCH 05/14] drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
intel_get_load_detect_pipe() needs to set uapi active,
uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
so we can remove it.
intel_pipe_config_compare() needs to look at hw state, but I didn't
change spatch to look at it. It's easy enough to do manually.
intel_atomic_check() definitely needs to check for uapi enable,
otherwise intel_modeset_pipe_config cannot copy uapi state to hw.
Changes since v1:
- Actually set uapi.active in get_load_detect_pipe().
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 42 ++--
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 03d958b13789..71d38457df36 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11357,7 +11357,7 @@ int intel_get_load_detect_pipe(struct drm_connector
*connector,
goto fail;
}
- crtc_state->base.active = crtc_state->base.enable = true;
+ crtc_state->uapi.active = true;
if (!mode)
mode = _detect_mode;
@@ -13002,19 +13002,19 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(output_types);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(output_format);
@@ -13031,17 +13031,17 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_INTERLACE);
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PVSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NVSYNC);
}
@@ -13080,7 +13080,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
if (bp_gamma)
- PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut,
bp_gamma);
+ PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut,
bp_gamma);
}
@@ -13125,7 +13125,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
PIPE_CONF_CHECK_I(min_voltage_level);
@@ -13823,7 +13823,7 @@ static int intel_atomic_check(struct drm_device *dev,
if
[Intel-gfx] [PATCH 14/14] drm/i915: Remove special case slave handling during hw programming, v3.
Now that we split plane_state which I didn't want to do yet, we can
program the slave plane without requiring the master plane.
This is useful for programming bigjoiner slave planes as well. We
will no longer need the master's plane_state.
Changes since v1:
- set src/dst rectangles after copy_uapi_to_hw_state.
Changes since v2:
- Use the correct color_plane for pre-gen11 by using planar_linked_plane !=
NULL.
- Use drm_format_info_is_yuv_semiplanar in skl_plane_check() to fix gen11+.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 30 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 -
drivers/gpu/drm/i915/display/intel_display.c | 18 ++
.../drm/i915/display/intel_display_types.h| 6 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 57 ++-
5 files changed, 40 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d9b65e9c45fc..54d112408716 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -309,16 +309,6 @@ void intel_update_plane(struct intel_plane *plane,
plane->update_plane(plane, crtc_state, plane_state);
}
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
- trace_intel_update_plane(>base, crtc);
- plane->update_slave(plane, crtc_state, plane_state);
-}
-
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@@ -351,25 +341,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
- if (new_plane_state->uapi.visible) {
+ if (new_plane_state->uapi.visible ||
+ new_plane_state->planar_slave) {
intel_update_plane(plane, new_crtc_state,
new_plane_state);
- } else if (new_plane_state->planar_slave) {
- struct intel_plane *master =
- new_plane_state->planar_linked_plane;
-
- /*
-* We update the slave plane from this function because
-* programming it from the master plane's update_plane
-* callback runs into issues when the Y plane is
-* reassigned, disabled or used by a different plane.
-*
-* The slave plane is updated with the master plane's
-* plane_state.
-*/
- new_plane_state =
- intel_atomic_get_new_plane_state(state, master);
-
- intel_update_slave(plane, new_crtc_state,
new_plane_state);
} else {
intel_disable_plane(plane, new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 123404a9cf23..726ececd6abd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -25,9 +25,6 @@ void intel_plane_copy_uapi_to_hw_state(struct
intel_plane_state *plane_state,
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state);
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state);
struct intel_plane *intel_plane_alloc(void);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2330ac24fd4d..6374258b959e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11911,6 +11911,24 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
crtc_state->active_planes |= BIT(linked->id);
crtc_state->update_planes |= BIT(linked->id);
DRM_DEBUG_KMS("Using %s as Y plane for %s\n",
linked->base.name, plane->base.name);
+
+ /* Copy parameters to slave plane */
+ linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
+ linked_state->color_ctl = plane_state->color_ctl;
+
