Re: [Intel-gfx] [PATCH] drm/i915/perf: Configure OAR controls for specific context

[Lionel Landwerlin]

On 08/11/2019 01:34, Umesh Nerlige Ramappa wrote:

It turns out that the OAR CONTROL register is not getting configured
correctly in conjunction with the context save/restore bit. When
measuring work for a single context, the OAR counters do not increment.

- Configure OAR format and enable OAR counters at the same time as
   enabling context save/restore for OAR counters.
- Make SAMPLE_OA_REPORT optional from gen12.

v2: Update commit message

Signed-off-by: Umesh Nerlige Ramappa 
---
  drivers/gpu/drm/i915/i915_perf.c | 23 +++
  1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c380aba1ce9..527a16637689 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2219,26 +2219,33 @@ static int gen8_configure_context(struct 
i915_gem_context *ctx,
return err;
  }
  
-static int gen12_emit_oar_config(struct intel_context *ce, bool enable)

+static int gen12_emit_oar_config(struct i915_perf_stream *stream, bool enable)
  {
struct i915_request *rq;
+   struct intel_context *ce = stream->pinned_ctx;
u32 *cs;
+   u32 format = stream->oa_buffer.format;
int err = 0;
  
  	rq = i915_request_create(ce);

if (IS_ERR(rq))
return PTR_ERR(rq);
  
-	cs = intel_ring_begin(rq, 4);

+   cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
goto out;
}
  
-	*cs++ = MI_LOAD_REGISTER_IMM(1);

+   *cs++ = MI_LOAD_REGISTER_IMM(2);
+   /* Enable context save/restore of OAR counters */
*cs++ = 
i915_mmio_reg_offset(RING_CONTEXT_CONTROL(ce->engine->mmio_base));
*cs++ = _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
  enable ? GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : 0);
+   /* Enable OAR counters */
+   *cs++ = i915_mmio_reg_offset(GEN12_OAR_OACONTROL);
+   *cs++ = (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
+   (enable ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0);
*cs++ = MI_NOOP;



It's probably a good idea to configure OAR in this function indeed :)


But we're already supposed to program it through context image 
modification in lrc_configure_all_contexts().


So it probably means we have the wrong offset?


We should probably remove it from lrc_configure_all_contexts() then. 
It's probably trashing some other bit of the context image.




  
  	intel_ring_advance(rq, cs);

@@ -2474,8 +2481,7 @@ static int gen12_enable_metric_set(struct 
i915_perf_stream *stream)
 * requested this.
 */
if (stream->ctx) {
-   ret = gen12_emit_oar_config(stream->pinned_ctx,
-   oa_config != NULL);
+   ret = gen12_emit_oar_config(stream, oa_config != NULL);
if (ret)
return ret;
}
@@ -2513,7 +2519,7 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)
  
  	/* disable the context save/restore or OAR counters */

if (stream->ctx)
-   gen12_emit_oar_config(stream->pinned_ctx, false);
+   gen12_emit_oar_config(stream, false);
  
  	/* Make sure we disable noa to save power. */

intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
@@ -2713,7 +2719,8 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
return -EINVAL;
}
  
-	if (!(props->sample_flags & SAMPLE_OA_REPORT)) {

+   if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
+   (INTEL_GEN(perf->i915) < 12 || !stream->ctx)) {



Good point, but this should probably go into another patch.

Note that we could also consider not sampling the OA buffer a non 
privileged operation on Gen12+, since the counters are per context 
saved/restored.



Thanks,


-Lionel


DRM_DEBUG("Only OA report sampling supported\n");
return -EINVAL;
}
@@ -2745,7 +2752,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
  
  	format_size = perf->oa_formats[props->oa_format].size;
  
-	stream->sample_flags |= SAMPLE_OA_REPORT;

+   stream->sample_flags = props->sample_flags;
stream->sample_size += format_size;
  
  	stream->oa_buffer.format_size = format_size;



___
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Re: [Intel-gfx] [PATCH 1/2] kbuild: remove header compile test

[yamada.masahiro]

Hi Jani,

> -Original Message-
> From: Jani Nikula 
> Sent: Thursday, November 07, 2019 5:46 PM
> To: Linus Torvalds ; Yamada, Masahiro/山田
> 真弘 ; linux-kbu...@vger.kernel.org
> Cc: linux-ker...@vger.kernel.org; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] kbuild: remove header compile test
> 
> On Thu, 07 Nov 2019, Masahiro Yamada 
> wrote:
> > There are both positive and negative options about this feature.
> > At first, I thought it was a good idea, but actually Linus stated a
> > negative opinion (https://lkml.org/lkml/2019/9/29/227). I admit it
> > is ugly and annoying.
> 
> Linus, we used to have a homebrew local version of this in i915 because
> we have loads of include files, they are a mess with a decade of
> organigally grown cruft, and it has been helpful in ensuring we don't
> break stuff while we refactor and disentangle the whole mess. The
> implementation in kbuild is far superior to what we can do in driver
> Makefiles.

Could check the attached three patches?

i915 is the only driver passionate about the header self-contained'ness.
It would not be horrible to implement a own build rule in i915 Makefile.

0003 decreases the amount of code.

0001 and 0002 are trivial and can go in independently.
( I just send them to intel-gfx ML)

Thanks.

Masahiro Yamada



> Could we please leave the feature be, and let drivers and subsystems use
> it as they see fit, instead of nuking it from kbuild altogether? Just
> drop the automatic checking of include/. And perhaps change the
> implementation to use dot prefixed filenames?
> 
> Note that in i915 we enabled the whole thing only in our own CI and
> build test config, disabled by default and depends on !COMPILE_TEST to
> hide it from the rest of the world. But it was useful to *us*.
> 
> 
> BR,
> Jani.
> 
> 
> >
> > The baseline I'd like to keep is the compile-test of uapi headers.
> > (Otherwise, kernel developers have no way to ensure the correctness
> > of the exported headers.)
> >
> > I will maintain a small build rule in usr/include/Makefile.
> > Remove the other header test functionality.
> >
> > Signed-off-by: Masahiro Yamada 
> > ---
> >
> >  Documentation/kbuild/makefiles.rst |   17 -
> >  Makefile   |1 -
> >  drivers/gpu/drm/i915/Kconfig.debug |1 -
> >  include/Kbuild | 1185 
> >  init/Kconfig   |   22 +-
> >  scripts/Makefile.build |9 -
> >  scripts/Makefile.lib   |   14 -
> >  usr/include/Makefile   |   12 +-
> >  8 files changed, 9 insertions(+), 1252 deletions(-)
> >  delete mode 100644 include/Kbuild
> >
> > diff --git a/Documentation/kbuild/makefiles.rst
> b/Documentation/kbuild/makefiles.rst
> > index b89c88168d6a..b9b50553bfc5 100644
> > --- a/Documentation/kbuild/makefiles.rst
> > +++ b/Documentation/kbuild/makefiles.rst
> > @@ -1115,23 +1115,6 @@ When kbuild executes, the following steps are
> followed (roughly):
> > In this example, extra-y is used to list object files that
> > shall be built, but shall not be linked as part of built-in.a.
> >
> > -header-test-y
> > -
> > -   header-test-y specifies headers (`*.h`) in the current directory that
> > -   should be compile tested to ensure they are self-contained,
> > -   i.e. compilable as standalone units. If CONFIG_HEADER_TEST is
> enabled,
> > -   this builds them as part of extra-y.
> > -
> > -header-test-pattern-y
> > -
> > -   This works as a weaker version of header-test-y, and accepts wildcard
> > -   patterns. The typical usage is::
> > -
> > -   header-test-pattern-y += *.h
> > -
> > -   This specifies all the files that matches to `*.h` in the current
> > -   directory, but the files in 'header-test-' are excluded.
> > -
> >  6.7 Commands useful for building a boot image
> >  -
> >
> > diff --git a/Makefile b/Makefile
> > index b37d0e8fc61d..225884bd0d86 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -618,7 +618,6 @@ ifeq ($(KBUILD_EXTMOD),)
> >  init-y := init/
> >  drivers-y  := drivers/ sound/
> >  drivers-$(CONFIG_SAMPLES) += samples/
> > -drivers-$(CONFIG_KERNEL_HEADER_TEST) += include/
> >  net-y  := net/
> >  libs-y := lib/
> >  core-y := usr/
> > diff --git a/drivers/gpu/drm/i915/Kconfig.debug
> b/drivers/gpu/drm/i915/Kconfig.debug
> > index 00786a142ff0..41c8e39a73ba 100644
> > --- a/drivers/gpu/drm/i915/Kconfig.debug
> > +++ b/drivers/gpu/drm/i915/Kconfig.debug
> > @@ -7,7 +7,6 @@ config DRM_I915_WERROR
> >  # We use the dependency on !COMPILE_TEST to not be enabled in
> >  # allmodconfig or allyesconfig configurations
> >  depends on !COMPILE_TEST
> > -   select HEADER_TEST
> >  default n
> >  help
> >Add -Werror to the build flags for (and only for) i915.ko.
> > diff --git a/include/Kbuild b/include/Kbuild
> > deleted file mode 1006

Re: [Intel-gfx] [PATCH 2/2] drm/i915: make more headers self-contained

[Masahiro Yamada]

On Fri, Nov 8, 2019 at 2:15 PM Masahiro Yamada
 wrote:
>
> The headers in the gem/selftests/, gt/selftests, gvt/, selftests/
> directories have never been compile-tested, but it would be possible
> to make them self-contained.
>
> This commit only addresses missing  and forward
> struct declarations.
>
> Signed-off-by: Masahiro Yamada 
> ---

I confirmed this patch is applicable to next-20191107
but CI fails to apply it.

Which branch should I base my patch on?


>
>  drivers/gpu/drm/i915/gem/selftests/mock_context.h | 3 +++
>  drivers/gpu/drm/i915/gt/selftests/mock_timeline.h | 2 ++
>  drivers/gpu/drm/i915/gvt/cmd_parser.h | 4 
>  drivers/gpu/drm/i915/gvt/display.h| 5 +
>  drivers/gpu/drm/i915/gvt/edid.h   | 4 
>  drivers/gpu/drm/i915/gvt/execlist.h   | 2 ++
>  drivers/gpu/drm/i915/gvt/fb_decoder.h | 2 ++
>  drivers/gpu/drm/i915/gvt/hypercall.h  | 4 
>  drivers/gpu/drm/i915/gvt/interrupt.h  | 3 +++
>  drivers/gpu/drm/i915/gvt/mmio.h   | 2 ++
>  drivers/gpu/drm/i915/gvt/page_track.h | 3 +++
>  drivers/gpu/drm/i915/gvt/sched_policy.h   | 3 +++
>  drivers/gpu/drm/i915/selftests/mock_drm.h | 2 ++
>  drivers/gpu/drm/i915/selftests/mock_gtt.h | 3 +++
>  drivers/gpu/drm/i915/selftests/mock_region.h  | 5 +
>  drivers/gpu/drm/i915/selftests/mock_uncore.h  | 3 +++
>  16 files changed, 50 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.h 
> b/drivers/gpu/drm/i915/gem/selftests/mock_context.h
> index 0b926653914f..45de09ec28d1 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.h
> +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.h
> @@ -7,6 +7,9 @@
>  #ifndef __MOCK_CONTEXT_H
>  #define __MOCK_CONTEXT_H
>
> +struct drm_file;
> +struct drm_i915_private;
> +
>  void mock_init_contexts(struct drm_i915_private *i915);
>
>  struct i915_gem_context *
> diff --git a/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h 
> b/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
> index 689efc66c908..d2bcc3df6183 100644
> --- a/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
> +++ b/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
> @@ -7,6 +7,8 @@
>  #ifndef __MOCK_TIMELINE__
>  #define __MOCK_TIMELINE__
>
> +#include 
> +
>  struct intel_timeline;
>
>  void mock_timeline_init(struct intel_timeline *timeline, u64 context);
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.h 
> b/drivers/gpu/drm/i915/gvt/cmd_parser.h
> index 286703643002..ab25d151932a 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.h
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.h
> @@ -38,6 +38,10 @@
>
>  #define GVT_CMD_HASH_BITS 7
>
> +struct intel_gvt;
> +struct intel_shadow_wa_ctx;
> +struct intel_vgpu_workload;
> +
>  void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt);
>
>  int intel_gvt_init_cmd_parser(struct intel_gvt *gvt);
> diff --git a/drivers/gpu/drm/i915/gvt/display.h 
> b/drivers/gpu/drm/i915/gvt/display.h
> index a87f33e6a23c..b59b34046e1e 100644
> --- a/drivers/gpu/drm/i915/gvt/display.h
> +++ b/drivers/gpu/drm/i915/gvt/display.h
> @@ -35,6 +35,11 @@
>  #ifndef _GVT_DISPLAY_H_
>  #define _GVT_DISPLAY_H_
>
> +#include 
> +
> +struct intel_gvt;
> +struct intel_vgpu;
> +
>  #define SBI_REG_MAX20
>  #define DPCD_SIZE  0x700
>
> diff --git a/drivers/gpu/drm/i915/gvt/edid.h b/drivers/gpu/drm/i915/gvt/edid.h
> index f6dfc8b795ec..dfe0cbc6aad8 100644
> --- a/drivers/gpu/drm/i915/gvt/edid.h
> +++ b/drivers/gpu/drm/i915/gvt/edid.h
> @@ -35,6 +35,10 @@
>  #ifndef _GVT_EDID_H_
>  #define _GVT_EDID_H_
>
> +#include 
> +
> +struct intel_vgpu;
> +
>  #define EDID_SIZE  128
>  #define EDID_ADDR  0x50 /* Linux hvm EDID addr */
>
> diff --git a/drivers/gpu/drm/i915/gvt/execlist.h 
> b/drivers/gpu/drm/i915/gvt/execlist.h
> index 5ccc2c695848..5c0c1fd30c83 100644
> --- a/drivers/gpu/drm/i915/gvt/execlist.h
> +++ b/drivers/gpu/drm/i915/gvt/execlist.h
> @@ -35,6 +35,8 @@
>  #ifndef _GVT_EXECLIST_H_
>  #define _GVT_EXECLIST_H_
>
> +#include 
> +
>  struct execlist_ctx_descriptor_format {
> union {
> u32 ldw;
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h 
> b/drivers/gpu/drm/i915/gvt/fb_decoder.h
> index 60c155085029..67b6ede9e707 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.h
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h
> @@ -36,6 +36,8 @@
>  #ifndef _GVT_FB_DECODER_H_
>  #define _GVT_FB_DECODER_H_
>
> +#include 
> +
>  #define _PLANE_CTL_FORMAT_SHIFT24
>  #defi

[Intel-gfx] [PATCH 0/1] dg1: enable dsb back

[Lucas De Marchi]

Commit  a096883dda2c ("drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object 
VMA")
fixed it, remove the hack.

---
baseline: f681b0ac20073c08e34f5987800b35f45fb69e29
pile-commit: 3f2a85eed3a5be81b1ab3e02426c368f20e5be82
range-diff:
156:  31c4b0cc66c6 <   -:   INTEL_DII: drm/i915/dg1: HACK: disable 
dsb
204:  15fa3c0ae1b4 ! 203:  d0e5019e1e45 INTEL_DII: drm/i915: add new gen12.5 
macro

 series |  1 -
 ...-INTEL_DII-drm-i915-add-new-gen12.5-macro.patch |  4 +-
 0001-INTEL_DII-drm-i915-dg1-HACK-disable-dsb.patch | 61 --
 3 files changed, 2 insertions(+), 64 deletions(-)

diff --git a/series b/series
index bf01fc9aced5..9b4350b74d96 100644
--- a/series
+++ b/series
@@ -155,7 +155,6 @@
 0001-INTEL_DII-START-dg1-DG1-enabling.patch
 0001-INTEL_DII-drm-i915-Add-has_master_unit_irq-flag.patch
 0001-INTEL_DII-drm-i915-dg1-add-initial-DG-1-definitions.patch
-0001-INTEL_DII-drm-i915-dg1-HACK-disable-dsb.patch
 0001-INTEL_DII-drm-i915-dg1-Add-DG1-PCI-IDs.patch
 0001-INTEL_DII-drm-i915-dg1-Add-fake-PCH.patch
 0001-INTEL_DII-drm-i915-dg1-Initialize-RAWCLK-properly.patch
diff --git a/0001-INTEL_DII-drm-i915-add-new-gen12.5-macro.patch 
b/0001-INTEL_DII-drm-i915-add-new-gen12.5-macro.patch
index 47d092d0d081..3270503a5da3 100644
--- a/0001-INTEL_DII-drm-i915-add-new-gen12.5-macro.patch
+++ b/0001-INTEL_DII-drm-i915-add-new-gen12.5-macro.patch
@@ -20,8 +20,8 @@ Signed-off-by: Stuart Summers 
 diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
 --- a/drivers/gpu/drm/i915/i915_pci.c
 +++ b/drivers/gpu/drm/i915/i915_pci.c
-@@ -868,6 +868,9 @@ static const struct intel_device_info intel_dg1_info = {
-   .display.has_dsb = 0, /* HACK */
+@@ -867,6 +867,9 @@ static const struct intel_device_info intel_dg1_info = {
+   .ppgtt_size = 47, /* for dual-ctx, see comment in TGL info */
  };
  
 +#define GEN12_5_FEATURES \
diff --git a/0001-INTEL_DII-drm-i915-dg1-HACK-disable-dsb.patch 
b/0001-INTEL_DII-drm-i915-dg1-HACK-disable-dsb.patch
deleted file mode 100644
index dc08e527df89..
--- a/0001-INTEL_DII-drm-i915-dg1-HACK-disable-dsb.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From  Mon Sep 17 00:00:00 2001
-From: Lucas De Marchi 
-Date: Fri, 1 Nov 2019 10:43:10 -0700
-Subject: [PATCH] INTEL_DII: drm/i915/dg1: HACK: disable dsb
-
-[   18.779601] [drm:intel_dsb_get [i915]] *ERROR* Vma creation failed
-[   18.780131] [ cut here ]
-[   18.780132] WARN_ON(atomic_read(&dsb->refcount) == 0)
-[   18.780180] WARNING: CPU: 1 PID: 456 at 
drivers/gpu/drm/i915/display/intel_dsb.c:161 intel_dsb_put+0x56/0x60 [i915]
-[   18.780181] Modules linked in: i915(+) snd_hda_codec_hdmi prime_numbers 
snd_hda_intel snd_intel_nhlt snd_hda_codec btusb snd_hwdep x86_pkg_temp_thermal 
btrtl snd_hda_core coretemp btbcm btintel kvm_intel bluetooth snd_pcm kvm 
mei_me ec
-dh_generic e1000e ecc mei irqbypass i2c_i801 crct10dif_pclmul crc32_pclmul 
ghash_clmulni_intel
-[   18.780192] CPU: 1 PID: 456 Comm: modprobe Not tainted 5.4.0-rc5+ #7
-[   18.780194] Hardware name: Gigabyte Technology Co., Ltd. GB-Z390 
Garuda/GB-Z390 Garuda-CF, BIOS IG1b 09/10/2019
-[   18.780223] RIP: 0010:intel_dsb_put+0x56/0x60 [i915]
-[   18.780225] Code: e8 5f 6b fb ff 48 c7 43 08 00 00 00 00 48 c7 43 18 00 00 
00 00 5b c3 48 c7 c6 50 74 3d a0 48 c7 c7 e8 06 3f a0 e8 3a 61 d7 e0 <0f> 0b 5b 
c3 66 0f 1f 44 00 00 48 8b 47 08 48 85 c0 75 1f 48 8b 87
-[   18.780226] RSP: 0018:c957f800 EFLAGS: 00010286
-[   18.780228] RAX:  RBX: 888495812688 RCX: 
0001
-[   18.780229] RDX: 190a RSI: 88849fe10928 RDI: 
8213edf9
-[   18.780230] RBP: 888493966800 R08: 88849fe10928 R09: 

-[   18.780231] R10:  R11:  R12: 
88849589c000
-[   18.780232] R13: 88848fae6800 R14: 88848b8c0340 R15: 
888493966858
-[   18.780234] FS:  7f556fcb8740() GS:8884ad88() 
knlGS:
-[   18.780235] CS:  0010 DS:  ES:  CR0: 80050033
-[   18.780236] CR2: 55f6d80c71f0 CR3: 0004977e6004 CR4: 
003606e0
-[   18.780237] DR0:  DR1:  DR2: 

-[   18.780238] DR3:  DR6: fffe0ff0 DR7: 
0400
-[   18.780239] Call Trace:
-[   18.780270]  intel_atomic_commit_tail+0x3a6/0x14c0 [i915]
-[   18.780273]  ? mark_held_locks+0x49/0x70
-[   18.780276]  ? queue_work_on+0x31/0x70
-[   18.780278]  ? lockdep_hardirqs_on+0xe3/0x1c0
-[   18.780308]  ? intel_atomic_commit_ready+0x3f/0x50 [i915]
-[   18.780332]  ? __i915_sw_fence_complete+0x1a0/0x250 [i915]
-[   18.780363]  intel_atomic_commit+0x31d/0x350 [i915]
-[   18.780393]  intel_initial_commit+0xb1/0x130 [i915]
-[   18.780426]  intel_modeset_init+0x9fd/0x1c80 [i915]
-[   18.780451]  i915_driver_probe+0xc45/0x16b0 [i915]
-[   18.780478]  i915_pci_probe+0

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: change to_mock() to an inline function

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: change to_mock() to an inline 
function
URL   : https://patchwork.freedesktop.org/series/69169/
State : failure

== Summary ==

Applying: drm/i915: change to_mock() to an inline function
Applying: drm/i915: make more headers self-contained
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/selftests/mock_drm.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/selftests/mock_drm.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/selftests/mock_drm.h
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0002 drm/i915: make more headers self-contained
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Cleanup heartbeat systole first

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Cleanup heartbeat systole first
URL   : https://patchwork.freedesktop.org/series/69095/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7277_full -> Patchwork_15167_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_15167_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +10 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-iclb6/igt@gem_ctx_e...@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@rcs0-s3:
- shard-apl:  [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-apl1/igt@gem_ctx_isolat...@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-s3:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#111832]) +1 
similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-tglb2/igt@gem_ctx_isolat...@vcs1-s3.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-tglb4/igt@gem_ctx_isolat...@vcs1-s3.html

  * igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) 
+4 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb1/igt@gem_ctx_persiste...@vcs1-queued.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-iclb5/igt@gem_ctx_persiste...@vcs1-queued.html

  * igt@gem_exec_schedule@preempt-queue-contexts-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +7 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb1/igt@gem_exec_sched...@preempt-queue-contexts-bsd2.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-iclb8/igt@gem_exec_sched...@preempt-queue-contexts-bsd2.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html

  * igt@gem_exec_suspend@basic-s3:
- shard-kbl:  [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-kbl7/igt@gem_exec_susp...@basic-s3.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-kbl1/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_sync@basic-all:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111647])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-tglb2/igt@gem_s...@basic-all.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-tglb6/igt@gem_s...@basic-all.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-snb:  [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +2 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-snb7/igt@gem_userptr_bl...@dmabuf-sync.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-snb7/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw:  [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html

  * igt@gem_wait@basic-busy-all:
- shard-hsw:  [PASS][21] -> [INCOMPLETE][22] ([fdo#103540]) +1 
similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-hsw1/igt@gem_w...@basic-busy-all.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-hsw5/igt@gem_w...@basic-busy-all.html

  * igt@i915_pm_rps@waitboost:
- shard-glk:  [PASS][23] -> [FAIL][24] ([fdo#102250])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-glk3/igt@i915_pm_...@waitboost.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15167/shard-glk2/igt@i915_pm_...@waitboost.html
- shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#102250])
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb2/igt@i915_pm_...@waitboost.html
   [26]: 
https:

[Intel-gfx] [PATCH 1/2] drm/i915: change to_mock() to an inline function

[Masahiro Yamada]

Since this function is defined in a header file, it should be
'static inline' instead of 'static'.

Signed-off-by: Masahiro Yamada 
---

 drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h 
b/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
index f0f8bbd82dfc..22818bbb139d 100644
--- a/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
+++ b/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
@@ -14,7 +14,7 @@ struct mock_dmabuf {
struct page *pages[];
 };
 
-static struct mock_dmabuf *to_mock(struct dma_buf *buf)
+static inline struct mock_dmabuf *to_mock(struct dma_buf *buf)
 {
return buf->priv;
 }
-- 
2.17.1

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[Intel-gfx] [PATCH 2/2] drm/i915: make more headers self-contained

[Masahiro Yamada]

The headers in the gem/selftests/, gt/selftests, gvt/, selftests/
directories have never been compile-tested, but it would be possible
to make them self-contained.

This commit only addresses missing  and forward
struct declarations.

Signed-off-by: Masahiro Yamada 
---

 drivers/gpu/drm/i915/gem/selftests/mock_context.h | 3 +++
 drivers/gpu/drm/i915/gt/selftests/mock_timeline.h | 2 ++
 drivers/gpu/drm/i915/gvt/cmd_parser.h | 4 
 drivers/gpu/drm/i915/gvt/display.h| 5 +
 drivers/gpu/drm/i915/gvt/edid.h   | 4 
 drivers/gpu/drm/i915/gvt/execlist.h   | 2 ++
 drivers/gpu/drm/i915/gvt/fb_decoder.h | 2 ++
 drivers/gpu/drm/i915/gvt/hypercall.h  | 4 
 drivers/gpu/drm/i915/gvt/interrupt.h  | 3 +++
 drivers/gpu/drm/i915/gvt/mmio.h   | 2 ++
 drivers/gpu/drm/i915/gvt/page_track.h | 3 +++
 drivers/gpu/drm/i915/gvt/sched_policy.h   | 3 +++
 drivers/gpu/drm/i915/selftests/mock_drm.h | 2 ++
 drivers/gpu/drm/i915/selftests/mock_gtt.h | 3 +++
 drivers/gpu/drm/i915/selftests/mock_region.h  | 5 +
 drivers/gpu/drm/i915/selftests/mock_uncore.h  | 3 +++
 16 files changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.h 
b/drivers/gpu/drm/i915/gem/selftests/mock_context.h
index 0b926653914f..45de09ec28d1 100644
--- a/drivers/gpu/drm/i915/gem/selftests/mock_context.h
+++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.h
@@ -7,6 +7,9 @@
 #ifndef __MOCK_CONTEXT_H
 #define __MOCK_CONTEXT_H
 
+struct drm_file;
+struct drm_i915_private;
+
 void mock_init_contexts(struct drm_i915_private *i915);
 
 struct i915_gem_context *
diff --git a/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h 
b/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
index 689efc66c908..d2bcc3df6183 100644
--- a/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
+++ b/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
@@ -7,6 +7,8 @@
 #ifndef __MOCK_TIMELINE__
 #define __MOCK_TIMELINE__
 
+#include 
+
 struct intel_timeline;
 
 void mock_timeline_init(struct intel_timeline *timeline, u64 context);
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.h 
b/drivers/gpu/drm/i915/gvt/cmd_parser.h
index 286703643002..ab25d151932a 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.h
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.h
@@ -38,6 +38,10 @@
 
 #define GVT_CMD_HASH_BITS 7
 
+struct intel_gvt;
+struct intel_shadow_wa_ctx;
+struct intel_vgpu_workload;
+
 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt);
 
 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt);
diff --git a/drivers/gpu/drm/i915/gvt/display.h 
b/drivers/gpu/drm/i915/gvt/display.h
index a87f33e6a23c..b59b34046e1e 100644
--- a/drivers/gpu/drm/i915/gvt/display.h
+++ b/drivers/gpu/drm/i915/gvt/display.h
@@ -35,6 +35,11 @@
 #ifndef _GVT_DISPLAY_H_
 #define _GVT_DISPLAY_H_
 
+#include 
+
+struct intel_gvt;
+struct intel_vgpu;
+
 #define SBI_REG_MAX20
 #define DPCD_SIZE  0x700
 
diff --git a/drivers/gpu/drm/i915/gvt/edid.h b/drivers/gpu/drm/i915/gvt/edid.h
index f6dfc8b795ec..dfe0cbc6aad8 100644
--- a/drivers/gpu/drm/i915/gvt/edid.h
+++ b/drivers/gpu/drm/i915/gvt/edid.h
@@ -35,6 +35,10 @@
 #ifndef _GVT_EDID_H_
 #define _GVT_EDID_H_
 
+#include 
+
+struct intel_vgpu;
+
 #define EDID_SIZE  128
 #define EDID_ADDR  0x50 /* Linux hvm EDID addr */
 
diff --git a/drivers/gpu/drm/i915/gvt/execlist.h 
b/drivers/gpu/drm/i915/gvt/execlist.h
index 5ccc2c695848..5c0c1fd30c83 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.h
+++ b/drivers/gpu/drm/i915/gvt/execlist.h
@@ -35,6 +35,8 @@
 #ifndef _GVT_EXECLIST_H_
 #define _GVT_EXECLIST_H_
 
+#include 
+
 struct execlist_ctx_descriptor_format {
union {
u32 ldw;
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h 
b/drivers/gpu/drm/i915/gvt/fb_decoder.h
index 60c155085029..67b6ede9e707 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.h
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h
@@ -36,6 +36,8 @@
 #ifndef _GVT_FB_DECODER_H_
 #define _GVT_FB_DECODER_H_
 
+#include 
+
 #define _PLANE_CTL_FORMAT_SHIFT24
 #define _PLANE_CTL_TILED_SHIFT 10
 #define _PIPE_V_SRCSZ_SHIFT0
diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h 
b/drivers/gpu/drm/i915/gvt/hypercall.h
index 4862fb12778e..9599c0a762b2 100644
--- a/drivers/gpu/drm/i915/gvt/hypercall.h
+++ b/drivers/gpu/drm/i915/gvt/hypercall.h
@@ -33,6 +33,10 @@
 #ifndef _GVT_HYPERCALL_H_
 #define _GVT_HYPERCALL_H_
 
+#include 
+
+struct device;
+
 enum hypervisor_type {
INTEL_GVT_HYPERVISOR_XEN = 0,
INTEL_GVT_HYPERVISOR_KVM,
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.h 
b/drivers/gpu/drm/i915/gvt/interrupt.h
index 5313fb1b33e1..fcd663811d37 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.h
+++ b/drivers/gpu/drm/i915/gvt/interrupt.h
@@ -32,6 +32,8 @@
 #ifndef _GVT_INTERRUPT_H_
 #define _GVT_INTERRUPT_H_
 
+#include 
+
 enum intel_gvt_event_typ

[Intel-gfx] ✓ Fi.CI.IGT: success for Start removing legacy guc code

[Patchwork]

== Series Details ==

Series: Start removing legacy guc code
URL   : https://patchwork.freedesktop.org/series/69094/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7277_full -> Patchwork_15166_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_15166_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +15 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-iclb8/igt@gem_ctx_e...@basic-invalid-context-vcs1.html

  * igt@gem_ctx_isolation@vcs1-s3:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([fdo#111832])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-tglb2/igt@gem_ctx_isolat...@vcs1-s3.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-tglb2/igt@gem_ctx_isolat...@vcs1-s3.html

  * igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) 
+4 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb1/igt@gem_ctx_persiste...@vcs1-queued.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-iclb6/igt@gem_ctx_persiste...@vcs1-queued.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb3/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html

  * igt@gem_exec_await@wide-contexts:
- shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([fdo#111736])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-tglb6/igt@gem_exec_aw...@wide-contexts.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-tglb6/igt@gem_exec_aw...@wide-contexts.html

  * igt@gem_exec_schedule@preempt-queue-contexts-vebox:
- shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([fdo#111677])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-tglb3/igt@gem_exec_sched...@preempt-queue-contexts-vebox.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-tglb6/igt@gem_exec_sched...@preempt-queue-contexts-vebox.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +4 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb6/igt@gem_exec_sched...@preemptive-hang-bsd.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#112037])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-iclb2/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-iclb3/igt@gem_persistent_rel...@forked-interruptible-thrashing.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-snb:  [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-snb7/igt@gem_userptr_bl...@dmabuf-sync.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-snb5/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw:  [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +1 
similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html

  * igt@i915_selftest@mock_requests:
- shard-skl:  [PASS][21] -> [DMESG-WARN][22] ([fdo#111086])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-skl4/igt@i915_selftest@mock_requests.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-skl10/igt@i915_selftest@mock_requests.html

  * igt@kms_color@pipe-a-ctm-0-75:
- shard-skl:  [PASS][23] -> [DMESG-WARN][24] ([fdo#106107])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7277/shard-skl3/igt@kms_co...@pipe-a-ctm-0-75.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15166/shard-skl10/igt@kms_co...@pipe-a-ctm-0-75.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl:  [PASS][25] -> [DMESG-WARN][2

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Leave the aliasing-ppgtt size alone

[Patchwork]

== Series Details ==

Series: drm/i915: Leave the aliasing-ppgtt size alone
URL   : https://patchwork.freedesktop.org/series/69093/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7276_full -> Patchwork_15165_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_15165_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +11 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-iclb4/igt@gem_b...@busy-vcs1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-iclb6/igt@gem_b...@busy-vcs1.html

  * igt@gem_ctx_isolation@vecs0-s3:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([fdo#111832])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-tglb7/igt@gem_ctx_isolat...@vecs0-s3.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-tglb2/igt@gem_ctx_isolat...@vecs0-s3.html

  * igt@gem_ctx_persistence@vcs1-mixed-process:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) 
+3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-iclb4/igt@gem_ctx_persiste...@vcs1-mixed-process.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-iclb6/igt@gem_ctx_persiste...@vcs1-mixed-process.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html

  * igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +7 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-iclb5/igt@gem_exec_sched...@in-order-bsd.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-iclb4/igt@gem_exec_sched...@in-order-bsd.html

  * igt@gem_exec_schedule@preempt-queue-chain-blt:
- shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([fdo#111606] / 
[fdo#111677])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-tglb7/igt@gem_exec_sched...@preempt-queue-chain-blt.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-tglb6/igt@gem_exec_sched...@preempt-queue-chain-blt.html

  * 
igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-snb:  [PASS][13] -> [TIMEOUT][14] ([fdo#112068 ])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-snb1/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrash-inactive.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-snb1/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrash-inactive.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw:  [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([fdo#111832] / 
[fdo#111850])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-tglb8/igt@gem_workarou...@suspend-resume-fd.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-tglb3/igt@gem_workarou...@suspend-resume-fd.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl:  [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk:  [PASS][21] -> [FAIL][22] ([fdo#104873])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-glk1/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15165/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-tglb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +6 similar 
issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-tglb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/opregion: fix leaking fw on error path

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/opregion: fix leaking fw on error 
path
URL   : https://patchwork.freedesktop.org/series/69167/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7290 -> Patchwork_15190


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15190/index.html

Known issues


  Here are the changes found in Patchwork_15190 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  [PASS][1] -> [FAIL][2] ([fdo#109483])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15190/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111736]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15190/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@gem_exec_suspend@basic-s3:
- fi-cml-s:   [DMESG-WARN][5] ([fdo#111764]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15190/fi-cml-s/igt@gem_exec_susp...@basic-s3.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764


Participating hosts (50 -> 45)
--

  Additional (1): fi-hsw-4770r 
  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-byt-squawks 
fi-bsw-cyan fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7290 -> Patchwork_15190

  CI-20190529: 20190529
  CI_DRM_7290: 869abae66a356231cfa6645cf491adde3590cba8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15190: 6c4afeac18aea52418f2f73899a4dda47fc456e3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6c4afeac18ae drm/i915/bios: do not discard address space
468f511e0df0 drm/i915/bios: make sure to check vbt size
57ae972e104c drm/i915/bios: rename bios to oprom when mapping pci rom
578cdda6a749 drm/i915/opregion: fix leaking fw on error path

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15190/index.html
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/opregion: fix leaking fw on error path

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/opregion: fix leaking fw on error 
path
URL   : https://patchwork.freedesktop.org/series/69167/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/opregion: fix leaking fw on error path
Okay!

Commit: drm/i915/bios: rename bios to oprom when mapping pci rom
Okay!

Commit: drm/i915/bios: make sure to check vbt size
Okay!

Commit: drm/i915/bios: do not discard address space
-
+drivers/gpu/drm/i915/display/intel_bios.c:1809:14: warning: symbol 'find_vbt' 
was not declared. Should it be static?

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Configure OAR controls for specific context (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/perf: Configure OAR controls for specific context (rev2)
URL   : https://patchwork.freedesktop.org/series/69165/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7290 -> Patchwork_15189


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15189/index.html

Known issues


  Here are the changes found in Patchwork_15189 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_execlists:
- fi-glk-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] / 
[k.org#198133])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-glk-dsi/igt@i915_selftest@live_execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15189/fi-glk-dsi/igt@i915_selftest@live_execlists.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][3] -> [FAIL][4] ([fdo#111407])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15189/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-u4:  [PASS][5] -> [FAIL][6] ([fdo#103167])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15189/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111736]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15189/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq:  [FAIL][9] ([fdo#108511]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15189/fi-skl-6770hq/igt@i915_pm_...@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (50 -> 46)
--

  Additional (1): fi-hsw-4770r 
  Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7290 -> Patchwork_15189

  CI-20190529: 20190529
  CI_DRM_7290: 869abae66a356231cfa6645cf491adde3590cba8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15189: 351573b952cc6c29d4acfabf6ece5438464490f7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

351573b952cc drm/i915/perf: Configure OAR controls for specific context

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15189/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/guc: Add GuC method to determine if submission is active.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/guc: Add GuC method to determine if 
submission is active.
URL   : https://patchwork.freedesktop.org/series/69086/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7276_full -> Patchwork_15163_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_15163_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15163_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_15163_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_flip_tiling@flip-to-yf-tiled:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-skl6/igt@kms_flip_til...@flip-to-yf-tiled.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-skl2/igt@kms_flip_til...@flip-to-yf-tiled.html

  
Known issues


  Here are the changes found in Patchwork_15163_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@bcs0-s3:
- shard-apl:  [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-apl1/igt@gem_ctx_isolat...@bcs0-s3.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-apl1/igt@gem_ctx_isolat...@bcs0-s3.html

  * igt@gem_ctx_isolation@vecs0-s3:
- shard-skl:  [PASS][5] -> [INCOMPLETE][6] ([fdo#104108])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-skl5/igt@gem_ctx_isolat...@vecs0-s3.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-skl7/igt@gem_ctx_isolat...@vecs0-s3.html

  * igt@gem_ctx_persistence@vcs1-cleanup:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) 
+2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-iclb1/igt@gem_ctx_persiste...@vcs1-cleanup.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-iclb6/igt@gem_ctx_persiste...@vcs1-cleanup.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([fdo#111677])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-tglb2/igt@gem_exec_sched...@preempt-queue-bsd1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-tglb6/igt@gem_exec_sched...@preempt-queue-bsd1.html

  * igt@gem_exec_schedule@preempt-queue-chain-blt:
- shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([fdo#111606] / 
[fdo#111677])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-tglb7/igt@gem_exec_sched...@preempt-queue-chain-blt.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-tglb6/igt@gem_exec_sched...@preempt-queue-chain-blt.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +4 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-bsd.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html

  * igt@gem_persistent_relocs@forked-thrashing:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#112068 ])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-tglb7/igt@gem_persistent_rel...@forked-thrashing.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-tglb8/igt@gem_persistent_rel...@forked-thrashing.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw:  [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb:  [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-snb7/igt@gem_userptr_bl...@sync-unmap-cycles.html

  * igt@kms_color@pipe-a-ctm-0-5:
- shard-skl:  [PASS][21] -> [DMESG-WARN][22] ([fdo#106107])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7276/shard-skl6/igt@kms_co...@pipe-a-ctm-0-5.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15163/shard-skl2/igt@kms_co.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: Configure OAR controls for specific context (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/perf: Configure OAR controls for specific context (rev2)
URL   : https://patchwork.freedesktop.org/series/69165/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
351573b952cc drm/i915/perf: Configure OAR controls for specific context
-:65: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "oa_config"
#65: FILE: drivers/gpu/drm/i915/i915_perf.c:2484:
+   ret = gen12_emit_oar_config(stream, oa_config != NULL);

total: 0 errors, 0 warnings, 1 checks, 70 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Mark up sole accessor to ctx->vm as being protected

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Mark up sole accessor to ctx->vm as being protected
URL   : https://patchwork.freedesktop.org/series/69161/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7290 -> Patchwork_15188


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15188/index.html

Known issues


  Here are the changes found in Patchwork_15188 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][1] -> [FAIL][2] ([fdo#111407])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15188/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111736]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15188/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq:  [FAIL][5] ([fdo#108511]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15188/fi-skl-6770hq/igt@i915_pm_...@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (50 -> 46)
--

  Additional (1): fi-hsw-4770r 
  Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7290 -> Patchwork_15188

  CI-20190529: 20190529
  CI_DRM_7290: 869abae66a356231cfa6645cf491adde3590cba8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15188: b8b88b29712fcb6bd9360556846e7e392f32d58d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b8b88b29712f drm/i915/selftests: Mark up sole accessor to ctx->vm as being 
protected

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15188/index.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/display: Fix 
TRANS_DDI_MST_TRANSPORT_SELECT definition
URL   : https://patchwork.freedesktop.org/series/69160/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7290 -> Patchwork_15187


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html

Known issues


  Here are the changes found in Patchwork_15187 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_blt:
- fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([fdo#112176])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-bsw-nick/igt@i915_selftest@live_blt.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-bsw-nick/igt@i915_selftest@live_blt.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][3] -> [FAIL][4] ([fdo#111407])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111736]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq:  [FAIL][7] ([fdo#108511]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/fi-skl-6770hq/igt@i915_pm_...@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176


Participating hosts (50 -> 46)
--

  Additional (1): fi-hsw-4770r 
  Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7290 -> Patchwork_15187

  CI-20190529: 20190529
  CI_DRM_7290: 869abae66a356231cfa6645cf491adde3590cba8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15187: d3bc4af38ceb942887aac7fe9b4cf145882dd59e @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d3bc4af38ceb drm/i915/display/mst: Enable virtual channel payload allocation 
earlier
23526380578b drm/i915/display/dsi: Add support to pipe D
a7de06e7e7d4 drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15187/index.html
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Re: [Intel-gfx] [PATCH v5] drm/i915: Enable second dbuf slice for ICL and TGL

[Matt Roper]

On Thu, Nov 07, 2019 at 11:22:34PM +0200, Stanislav Lisovskiy wrote:
> Also implemented algorithm for choosing DBuf slice configuration
> based on active pipes, pipe ratio as stated in BSpec 12716.
> 
> Now pipe allocation still stays proportional to pipe width as before,
> however within allowed DBuf slice for this particular configuration.
> 
> v2: Remove unneeded check from commit as ddb enabled slices might
> now differ from hw state.
> 
> v3: - Added new field "supported_slices" to ddb to separate max
>   supported slices vs currently enabled, to avoid confusion.
> - Removed obsolete comments and code related to DBuf(Matthew Roper).
> - Some code style and long line removal(Matthew Roper).
> - Added WARN_ON to new ddb range offset calc function(Matthew Roper).
> - Removed platform specific call to calc pipe ratio from ddb
>   allocation function and fixed the return value(Matthew Roper)
> - Refactored DBUF slice allocation table to improve readability
> - Added DBUF slice allocation for TGL as well.
> - ICL(however not TGL) seems to voluntarily enable second DBuf slice
>   after pm suspend/resume causing a mismatch failure, because we
>   update DBuf slices only if we do a modeset, however this check
>   is done always. Fixed it to be done only when modeset for ICL.
> 
> v4: - Now enabled slices is not actually a number, but a bitmask,
>   because we might need to enable second slice only and number
>   of slices would still 1 and that current code doesn't allow.
> - Remove redundant duplicate code to have some unified way of
>   enabling dbuf slices instead of hardcoding.
> 
> v5: - Fix failing gen9_assert_dbuf_enabled as it was naively thinking
>   that we have only one DBUF_CTL slice. Now another version for
>   gen11 will check both slices as only second one can be enabled,
>   to keep CI happy.
> 
> Signed-off-by: Stanislav Lisovskiy 
> Cc: Matthew Roper 
> Cc: Ville Syrjälä 
> Cc: James Ausmus 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  22 +-
>  .../drm/i915/display/intel_display_power.c| 103 +++--
>  .../drm/i915/display/intel_display_power.h|   2 +
>  drivers/gpu/drm/i915/i915_drv.c   |   5 +
>  drivers/gpu/drm/i915/i915_drv.h   |   3 +-
>  drivers/gpu/drm/i915/i915_reg.h   |   2 +
>  drivers/gpu/drm/i915/intel_pm.c   | 391 --
>  7 files changed, 441 insertions(+), 87 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 876fc25968bf..ee63da18772a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13386,8 +13386,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
>   sw_ddb = &dev_priv->wm.skl_hw.ddb;
>  
>   if (INTEL_GEN(dev_priv) >= 11 &&
> - hw->ddb.enabled_slices != sw_ddb->enabled_slices)
> - DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
> + hw->ddb.enabled_slices != sw_ddb->enabled_slices &&
> + needs_modeset(new_crtc_state))
> + DRM_ERROR("mismatch in DBUF Slices (expected %x, got %x)\n",
> sw_ddb->enabled_slices,
> hw->ddb.enabled_slices);

Is this related to your changelog comment above?

- ICL(however not TGL) seems to voluntarily enable second DBuf slice
  after pm suspend/resume causing a mismatch failure, because we
  update DBuf slices only if we do a modeset, however this check
  is done always. Fixed it to be done only when modeset for ICL.

It looks like you added an icl_dbuf_slices_restore() function that tries
to sanitize the dbuf programming on resume; is that not sufficient to
address this?

>  
> @@ -14613,16 +14614,21 @@ static void skl_commit_modeset_enables(struct 
> intel_atomic_state *state)
>   int i;
>   u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
>   u8 required_slices = state->wm_results.ddb.enabled_slices;
> - struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
> + u8 slices_union = hw_enabled_slices | required_slices;
> + u8 slices_intersection = slices_union & required_slices;

Isn't this the same as "slices_intersection = required_slices?"

>  
> + struct skl_ddb_entry entries[I915_MAX_PIPES] = {};

Did you mean to move this line (and add a space before it but not
after)?

>   for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 
> new_crtc_state, i)
>   /* ignore allocations for crtc's that have been turned off. */
>   if (new_crtc_state->hw.active)
>   entries[i] = old_crtc_state->wm.skl.ddb;
>  
> - /* If 2nd DBuf slice required, enable it here */
> - if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
> - icl_dbuf_slices_update(dev_priv, required_slices);
> + DR

Re: [Intel-gfx] linux-next: manual merge of the drm tree with the drm-intel-fixes tree

[Stephen Rothwell]

Hi all,

This is now a conflict between the drm tree and Linus' tree.

On Thu, 31 Oct 2019 11:33:15 +1100 Stephen Rothwell  
wrote:
>
> Today's linux-next merge of the drm tree got a conflict in:
> 
>   drivers/gpu/drm/i915/i915_drv.h
> 
> between commit:
> 
>   59cd826fb5e7 ("drm/i915: Fix PCH reference clock for FDI on HSW/BDW")
> 
> from the drm-intel-fixes tree and commit:
> 
>   7d423af9bfb1 ("drm/i915: Implement a better i945gm vblank irq vs. C-states 
> workaround")
> 
> from the drm tree.
> 
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
> 
> -- 
> Cheers,
> Stephen Rothwell
> 
> diff --cc drivers/gpu/drm/i915/i915_drv.h
> index 953e1d12c23c,8882c0908c3b..
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@@ -1704,34 -1339,17 +1339,19 @@@ struct drm_i915_private 
>   struct {
>   struct notifier_block pm_notifier;
>   
> - /**
> -  * We leave the user IRQ off as much as possible,
> -  * but this means that requests will finish and never
> -  * be retired once the system goes idle. Set a timer to
> -  * fire periodically while the ring is running. When it
> -  * fires, go retire requests.
> -  */
> - struct delayed_work retire_work;
> - 
> - /**
> -  * When we detect an idle GPU, we want to turn on
> -  * powersaving features. So once we see that there
> -  * are no more requests outstanding and no more
> -  * arrive within a small period of time, we fire
> -  * off the idle_work.
> -  */
> - struct work_struct idle_work;
> + struct i915_gem_contexts {
> + spinlock_t lock; /* locks list */
> + struct list_head list;
> + 
> + struct llist_head free_list;
> + struct work_struct free_work;
> + } contexts;
>   } gem;
>   
>  +u8 pch_ssc_use;
>  +
> - /* For i945gm vblank irq vs. C3 workaround */
> - struct {
> - struct work_struct work;
> - struct pm_qos_request pm_qos;
> - u8 c3_disable_latency;
> - u8 enabled;
> - } i945gm_vblank;
> + /* For i915gm/i945gm vblank irq workaround */
> + u8 vblank_enabled;
>   
>   /* perform PHY state sanity checks? */
>   bool chv_phy_assert[2];

-- 
Cheers,
Stephen Rothwell


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[Intel-gfx] [PATCH 2/4] drm/i915/bios: rename bios to oprom when mapping pci rom

[Lucas De Marchi]

oprom is actually a better name to use when using
pci_map_rom(). "bios"  is way too generic and confusing.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index a03f56b7b4ef..1f83616cfc32 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1804,7 +1804,7 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t size)
return vbt;
 }
 
-static const struct vbt_header *find_vbt(void __iomem *bios, size_t size)
+static const struct vbt_header *find_vbt(void __iomem *oprom, size_t size)
 {
size_t i;
 
@@ -1812,14 +1812,14 @@ static const struct vbt_header *find_vbt(void __iomem 
*bios, size_t size)
for (i = 0; i + 4 < size; i++) {
void *vbt;
 
-   if (ioread32(bios + i) != *((const u32 *) "$VBT"))
+   if (ioread32(oprom + i) != *((const u32 *)"$VBT"))
continue;
 
/*
 * This is the one place where we explicitly discard the address
 * space (__iomem) of the BIOS/VBT.
 */
-   vbt = (void __force *) bios + i;
+   vbt = (void __force *)oprom + i;
if (intel_bios_is_valid_vbt(vbt, size - i))
return vbt;
 
@@ -1842,7 +1842,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
struct pci_dev *pdev = dev_priv->drm.pdev;
const struct vbt_header *vbt = dev_priv->opregion.vbt;
const struct bdb_header *bdb;
-   u8 __iomem *bios = NULL;
+   u8 __iomem *oprom = NULL;
 
if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) {
DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
@@ -1855,11 +1855,11 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
if (!vbt) {
size_t size;
 
-   bios = pci_map_rom(pdev, &size);
-   if (!bios)
+   oprom = pci_map_rom(pdev, &size);
+   if (!oprom)
goto out;
 
-   vbt = find_vbt(bios, size);
+   vbt = find_vbt(oprom, size);
if (!vbt)
goto out;
 
@@ -1893,8 +1893,8 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
init_vbt_missing_defaults(dev_priv);
}
 
-   if (bios)
-   pci_unmap_rom(pdev, bios);
+   if (oprom)
+   pci_unmap_rom(pdev, oprom);
 }
 
 /**
-- 
2.23.0

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[Intel-gfx] [PATCH 3/4] drm/i915/bios: make sure to check vbt size

[Lucas De Marchi]

When we call intel_bios_is_valid_vbt(), size may not actually be the
size of the VBT, but rather the size of the blob the VBT is contained
in. For example, when mapping the PCI oprom, size will be the entire
oprom size. We don't want to read beyond what is reported to be the
VBT. So make sure we vbt->vbt_size makes sense and use that for
the latter checks.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 1f83616cfc32..671bbce6ba5b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1777,11 +1777,13 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t 
size)
if (!vbt)
return false;
 
-   if (sizeof(struct vbt_header) > size) {
+   if (sizeof(struct vbt_header) > size || vbt->vbt_size > size) {
DRM_DEBUG_DRIVER("VBT header incomplete\n");
return false;
}
 
+   size = vbt->vbt_size;
+
if (memcmp(vbt->signature, "$VBT", 4)) {
DRM_DEBUG_DRIVER("VBT invalid signature\n");
return false;
-- 
2.23.0

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[Intel-gfx] [PATCH 1/4] drm/i915/opregion: fix leaking fw on error path

[Lucas De Marchi]

Convert the code to return-early style and fix missing calls
to release_firmware() if vbt is not valid.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 28 +++
 1 file changed, 17 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
b/drivers/gpu/drm/i915/display/intel_opregion.c
index 969ade623691..9738511147b1 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -872,23 +872,29 @@ static int intel_load_vbt_firmware(struct 
drm_i915_private *dev_priv)
return ret;
}
 
-   if (intel_bios_is_valid_vbt(fw->data, fw->size)) {
-   opregion->vbt_firmware = kmemdup(fw->data, fw->size, 
GFP_KERNEL);
-   if (opregion->vbt_firmware) {
-   DRM_DEBUG_KMS("Found valid VBT firmware \"%s\"\n", 
name);
-   opregion->vbt = opregion->vbt_firmware;
-   opregion->vbt_size = fw->size;
-   ret = 0;
-   } else {
-   ret = -ENOMEM;
-   }
-   } else {
+   if (!intel_bios_is_valid_vbt(fw->data, fw->size)) {
DRM_DEBUG_KMS("Invalid VBT firmware \"%s\"\n", name);
ret = -EINVAL;
+   goto err_release_fw;
+   }
+
+   opregion->vbt_firmware = kmemdup(fw->data, fw->size, GFP_KERNEL);
+   if (!opregion->vbt_firmware) {
+   ret = -ENOMEM;
+   goto err_release_fw;
}
 
+   opregion->vbt = opregion->vbt_firmware;
+   opregion->vbt_size = fw->size;
+
+   DRM_DEBUG_KMS("Found valid VBT firmware \"%s\"\n", name);
+
release_firmware(fw);
 
+   return 0;
+
+err_release_fw:
+   release_firmware(fw);
return ret;
 }
 
-- 
2.23.0

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[Intel-gfx] [PATCH 4/4] drm/i915/bios: do not discard address space

[Lucas De Marchi]

When we are mapping the VBT through pci_map_rom() we may not be allowed
to simply discard the address space and go on reading the memory. After
checking on my test system that dumping the rom via sysfs I could
actually get the correct vbt, I decided to change the implementation to
use the same approach, by calling memcpy_fromio().

In order to avoid copying the entire oprom this implements a simple
memmem() searching for "$VBT". Contrary to the previous implementation
this also takes care of not issuing unaligned PCI reads that would
otherwise get translated into more even more reads. I also vaguely
remember unaligned reads failing in the past with some devices.

Also make sure we copy only the VBT and not the entire oprom that is
usually much larger.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 95 +++
 1 file changed, 79 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 671bbce6ba5b..c401e90b7cf1 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1806,31 +1806,88 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t 
size)
return vbt;
 }
 
-static const struct vbt_header *find_vbt(void __iomem *oprom, size_t size)
+void __iomem *find_vbt(void __iomem *oprom, size_t size)
 {
-   size_t i;
+   const u32 MAGIC = *((const u32 *)"$VBT");
+   size_t done = 0, cur = 0;
+   void __iomem *p;
+   u8 buf[128];
+   u32 val;
 
-   /* Scour memory looking for the VBT signature. */
-   for (i = 0; i + 4 < size; i++) {
-   void *vbt;
+   /*
+* poor's man memmem() with sizeof(buf) window to avoid frequent
+* wrap-arounds and using u32 for comparison. This gives us 4
+* comparisons per ioread32() and avoids unaligned io reads (although it
+* still does unaligned cpu access).
+*/
+   for (p = oprom; p < oprom + size; p += 4) {
+   *(u32 *)(&buf[done]) = ioread32(p);
+   done += 4;
 
-   if (ioread32(oprom + i) != *((const u32 *)"$VBT"))
-   continue;
+   while (cur + 4 <= done) {
+   val = *(u32 *)(buf + cur);
+   if (val == MAGIC)
+   return p - (done - cur) + 4;
 
-   /*
-* This is the one place where we explicitly discard the address
-* space (__iomem) of the BIOS/VBT.
-*/
-   vbt = (void __force *)oprom + i;
-   if (intel_bios_is_valid_vbt(vbt, size - i))
-   return vbt;
+   cur++;
+   }
 
-   break;
+   /* wrap-around */
+   if (done + 4 >= sizeof(buf)) {
+   buf[0] = buf[done - 3];
+   buf[1] = buf[done - 2];
+   buf[2] = buf[done - 1];
+   cur = 0;
+   done = 3;
+   }
}
 
+   /* Read the entire oprom and no VBT found */
return NULL;
 }
 
+/*
+ * Copy vbt to a new allocated buffer and update @psize to match the VBT
+ * size
+ */
+static struct vbt_header *copy_vbt(void __iomem *oprom, size_t *psize)
+{
+   off_t vbt_size_offset = offsetof(struct vbt_header, vbt_size);
+   struct vbt_header *vbt;
+   void __iomem *p;
+   u16 vbt_size;
+   size_t size;
+
+   size = *psize;
+   p = find_vbt(oprom, size);
+   if (!p)
+   return NULL;
+
+   size -= p - oprom;
+
+   /*
+* We need to at least be able to read the size and make sure it doesn't
+* overflow the oprom. The rest will be validated later.
+*/
+   if (sizeof(*vbt) > size) {
+   DRM_DEBUG_DRIVER("VBT header incomplete\n");
+   return NULL;
+   }
+
+   vbt_size = ioread16(p + vbt_size_offset);
+   if (vbt_size > size) {
+   DRM_DEBUG_DRIVER("VBT incomplete\n");
+   return NULL;
+   }
+
+   vbt = kmalloc(vbt_size, GFP_KERNEL);
+   memcpy_fromio(vbt, p, vbt_size);
+
+   *psize = vbt_size;
+
+   return vbt;
+}
+
 /**
  * intel_bios_init - find VBT and initialize settings from the BIOS
  * @dev_priv: i915 device instance
@@ -1861,10 +1918,13 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
if (!oprom)
goto out;
 
-   vbt = find_vbt(oprom, size);
+   vbt = copy_vbt(oprom, &size);
if (!vbt)
goto out;
 
+   if (!intel_bios_is_valid_vbt(vbt, size))
+   goto out;
+
DRM_DEBUG_KMS("Found valid VBT in PCI ROM\n");
}
 
@@ -1897,6 +1957,9 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
 
if (oprom)
 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Complete transition to a real struct file mock

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Complete transition to a real struct file mock
URL   : https://patchwork.freedesktop.org/series/69159/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7290 -> Patchwork_15186


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15186/index.html

Known issues


  Here are the changes found in Patchwork_15186 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][1] -> [FAIL][2] ([fdo#111045] / [fdo#111096])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15186/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq:  [FAIL][3] ([fdo#108511]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15186/fi-skl-6770hq/igt@i915_pm_...@module-reload.html

  
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096


Participating hosts (50 -> 45)
--

  Additional (1): fi-hsw-4770r 
  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-whl-u 
fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7290 -> Patchwork_15186

  CI-20190529: 20190529
  CI_DRM_7290: 869abae66a356231cfa6645cf491adde3590cba8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15186: 7013ed43c85d401ab86bc97918b5db358bea01f6 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7013ed43c85d drm/i915/selftests: Complete transition to a real struct file mock

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15186/index.html
___
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Re: [Intel-gfx] [PATCH 03/13] drm/exynos: Provide ddc symlink in connector's sysfs

[Inki Dae]

19. 8. 1. 오전 1:58에 Andrzej Pietrasiewicz 이(가) 쓴 글:
> Switch to using the ddc provided by the generic connector.
> 
> Signed-off-by: Andrzej Pietrasiewicz 
> Acked-by: Sam Ravnborg 
> Reviewed-by: Emil Velikov 

Acked-by: Inki Dae 

Thanks,
Inki Dae

> ---
>  drivers/gpu/drm/exynos/exynos_hdmi.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
> b/drivers/gpu/drm/exynos/exynos_hdmi.c
> index bc1565f1822a..d4a9c9e17436 100644
> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
> @@ -940,8 +940,10 @@ static int hdmi_create_connector(struct drm_encoder 
> *encoder)
>   connector->interlace_allowed = true;
>   connector->polled = DRM_CONNECTOR_POLL_HPD;
>  
> - ret = drm_connector_init(hdata->drm_dev, connector,
> - &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
> + ret = drm_connector_init_with_ddc(hdata->drm_dev, connector,
> +   &hdmi_connector_funcs,
> +   DRM_MODE_CONNECTOR_HDMIA,
> +   hdata->ddc_adpt);
>   if (ret) {
>   DRM_DEV_ERROR(hdata->dev,
> "Failed to initialize connector with drm\n");
> 
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable second dbuf slice for ICL and TGL (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable second dbuf slice for ICL and TGL (rev2)
URL   : https://patchwork.freedesktop.org/series/69124/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7290 -> Patchwork_15185


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_15185 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15185, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_15185:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-icl-guc: [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-guc/igt@i915_pm_...@basic-pci-d3-state.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/fi-icl-guc/igt@i915_pm_...@basic-pci-d3-state.html
- fi-icl-u2:  [PASS][3] -> [DMESG-WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-u2/igt@i915_pm_...@basic-pci-d3-state.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/fi-icl-u2/igt@i915_pm_...@basic-pci-d3-state.html
- fi-icl-u3:  [PASS][5] -> [DMESG-WARN][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-u3/igt@i915_pm_...@basic-pci-d3-state.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/fi-icl-u3/igt@i915_pm_...@basic-pci-d3-state.html
- fi-icl-y:   [PASS][7] -> [DMESG-WARN][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-y/igt@i915_pm_...@basic-pci-d3-state.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/fi-icl-y/igt@i915_pm_...@basic-pci-d3-state.html
- fi-icl-u4:  [PASS][9] -> [DMESG-WARN][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-u4/igt@i915_pm_...@basic-pci-d3-state.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/fi-icl-u4/igt@i915_pm_...@basic-pci-d3-state.html
- fi-icl-dsi: [PASS][11] -> [DMESG-WARN][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-dsi/igt@i915_pm_...@basic-pci-d3-state.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/fi-icl-dsi/igt@i915_pm_...@basic-pci-d3-state.html

  
Known issues


  Here are the changes found in Patchwork_15185 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][13] ([fdo#111736]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq:  [FAIL][15] ([fdo#108511]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/fi-skl-6770hq/igt@i915_pm_...@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (50 -> 46)
--

  Additional (1): fi-hsw-4770r 
  Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7290 -> Patchwork_15185

  CI-20190529: 20190529
  CI_DRM_7290: 869abae66a356231cfa6645cf491adde3590cba8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15185: f9ab97f3257e18df1979b29fc904b49ad3909ffb @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f9ab97f3257e drm/i915: Enable second dbuf slice for ICL and TGL

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15185/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Complete transition to a real struct file mock

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Complete transition to a real struct file mock
URL   : https://patchwork.freedesktop.org/series/69159/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7013ed43c85d drm/i915/selftests: Complete transition to a real struct file mock
-:84: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#84: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c:506:
+static int file_add_object(struct file *file,
struct drm_i915_gem_object *obj)

-:573: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#573: 
deleted file mode 100644

total: 0 errors, 1 warnings, 1 checks, 467 lines checked

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: fix dropping obj reference twice

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: fix dropping obj reference twice
URL   : https://patchwork.freedesktop.org/series/69084/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7275_full -> Patchwork_15162_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_15162_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +10 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-iclb2/igt@gem_b...@busy-vcs1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-iclb7/igt@gem_b...@busy-vcs1.html

  * igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) 
+2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-iclb1/igt@gem_ctx_persiste...@vcs1-queued.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-iclb7/igt@gem_ctx_persiste...@vcs1-queued.html

  * igt@gem_ctx_shared@q-smoketest-all:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#111735])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-tglb5/igt@gem_ctx_sha...@q-smoketest-all.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-tglb9/igt@gem_ctx_sha...@q-smoketest-all.html

  * igt@gem_exec_gttfill@basic:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111593])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-tglb1/igt@gem_exec_gttf...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-tglb8/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +6 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-iclb8/igt@gem_exec_sched...@in-order-bsd.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-iclb2/igt@gem_exec_sched...@in-order-bsd.html

  * igt@gem_fenced_exec_thrash@no-spare-fences:
- shard-snb:  [PASS][11] -> [INCOMPLETE][12] ([fdo#105411])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-snb7/igt@gem_fenced_exec_thr...@no-spare-fences.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-snb1/igt@gem_fenced_exec_thr...@no-spare-fences.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-snb:  [PASS][13] -> [DMESG-WARN][14] ([fdo#111870])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-snb5/igt@gem_userptr_bl...@dmabuf-sync.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@i915_pm_rps@waitboost:
- shard-glk:  [PASS][15] -> [FAIL][16] ([fdo#102250])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-glk9/igt@i915_pm_...@waitboost.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-glk8/igt@i915_pm_...@waitboost.html

  * igt@i915_selftest@mock_requests:
- shard-skl:  [PASS][17] -> [INCOMPLETE][18] ([fdo#108972])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-skl2/igt@i915_selftest@mock_requests.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-skl8/igt@i915_selftest@mock_requests.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([fdo#111832] / 
[fdo#111850]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-tglb4/igt@i915_susp...@fence-restore-tiled2untiled.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-tglb5/igt@i915_susp...@fence-restore-tiled2untiled.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw:  [PASS][21] -> [FAIL][22] ([fdo#105767])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_flip@flip-vs-suspend:
- shard-skl:  [PASS][23] -> [INCOMPLETE][24] ([fdo#109507])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-skl3/igt@kms_f...@flip-vs-suspend.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15162/shard-skl10/igt@kms_f...@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
- shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103167]) +3 similar 
issues
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-dra

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Enable second dbuf slice for ICL and TGL (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable second dbuf slice for ICL and TGL (rev2)
URL   : https://patchwork.freedesktop.org/series/69124/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Enable second dbuf slice for ICL and TGL
+drivers/gpu/drm/i915/intel_pm.c:4253:1: warning: symbol 
'skl_pipe_downscale_amount' was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_pm.c:4274:1: warning: symbol 'icl_get_pipe_ratio' 
was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_pm.c:4371:30: warning: symbol 'icl_allowed_dbufs' 
was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_pm.c:4395:30: warning: symbol 'tgl_allowed_dbufs' 
was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_pm.c:4465:5: warning: symbol 
'i915_get_allowed_dbuf_mask' was not declared. Should it be static?

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable second dbuf slice for ICL and TGL (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable second dbuf slice for ICL and TGL (rev2)
URL   : https://patchwork.freedesktop.org/series/69124/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f9ab97f3257e drm/i915: Enable second dbuf slice for ICL and TGL
-:260: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (8, 0)
#260: FILE: drivers/gpu/drm/i915/display/intel_display_power.h:311:
for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
[...]
+u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv);

-:506: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#506: FILE: drivers/gpu/drm/i915/intel_pm.c:3953:
+   u32 pipe_dbuf_slice_mask = \

-:508: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#508: FILE: drivers/gpu/drm/i915/intel_pm.c:3955:
+   i915_get_allowed_dbuf_mask(dev_priv,
+   pipe,

-:624: CHECK:LINE_SPACING: Please don't use multiple blank lines
#624: FILE: drivers/gpu/drm/i915/intel_pm.c:4303:
+
+

-:628: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#628: FILE: drivers/gpu/drm/i915/intel_pm.c:4307:
+   DRM_DEBUG_KMS("Pipe %d downscale amount %d.%d\n",
+  crtc->pipe, pipe_downscale.val >> 16,

-:647: CHECK:LINE_SPACING: Please don't use multiple blank lines
#647: FILE: drivers/gpu/drm/i915/intel_pm.c:4326:
+
+

-:648: CHECK:CAMELCASE: Avoid CamelCase: 
#648: FILE: drivers/gpu/drm/i915/intel_pm.c:4327:
+#define ICL_PIPE_A_DBUF_SLICES(DBuf1)  \

-:656: CHECK:CAMELCASE: Avoid CamelCase: 
#656: FILE: drivers/gpu/drm/i915/intel_pm.c:4335:
+#define ICL_PIPE_AB_DBUF_SLICES(DBuf1, DBuf2)   \

-:668: CHECK:CAMELCASE: Avoid CamelCase: 
#668: FILE: drivers/gpu/drm/i915/intel_pm.c:4347:
+#define ICL_PIPE_ABC_DBUF_SLICES(DBuf1, DBuf2, DBuf3)  \

-:678: CHECK:CAMELCASE: Avoid CamelCase: 
#678: FILE: drivers/gpu/drm/i915/intel_pm.c:4357:
+#define ICL_PIPE_ABCD_DBUF_SLICES(DBuf1, DBuf2, DBuf3, DBuf4)  \

-:787: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#787: FILE: drivers/gpu/drm/i915/intel_pm.c:4466:
+u32 i915_get_allowed_dbuf_mask(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,

total: 0 errors, 2 warnings, 9 checks, 712 lines checked

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Re: [Intel-gfx] [PATCH] drm/i915/perf: Configure OAR controls for specific context

[Umesh Nerlige Ramappa]

On Thu, Nov 07, 2019 at 11:30:51PM +, Chris Wilson wrote:

Quoting Umesh Nerlige Ramappa (2019-11-07 23:22:34)

It turns out that the OAR CONTROL register is not getting configured
correctly in conjunction with the context save/restore bit. When
measuring work for a single context, the OAR counters do not increment.

Configure OAR format and enable OAR counters at the same time as
enabling context save/restore for OAR counters.


Did you write a test case to capture this bug for posterity? If so,
please include a Testcase: link. If not, please do so :)


I did, although the test is also up for review here in an igt series - 
https://patchwork.freedesktop.org/patch/339514/


Thanks,
Umesh


-Chris

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[Intel-gfx] [PATCH] drm/i915/perf: Configure OAR controls for specific context

[Umesh Nerlige Ramappa]

It turns out that the OAR CONTROL register is not getting configured
correctly in conjunction with the context save/restore bit. When
measuring work for a single context, the OAR counters do not increment.

- Configure OAR format and enable OAR counters at the same time as
  enabling context save/restore for OAR counters.
- Make SAMPLE_OA_REPORT optional from gen12.

v2: Update commit message

Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_perf.c | 23 +++
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c380aba1ce9..527a16637689 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2219,26 +2219,33 @@ static int gen8_configure_context(struct 
i915_gem_context *ctx,
return err;
 }
 
-static int gen12_emit_oar_config(struct intel_context *ce, bool enable)
+static int gen12_emit_oar_config(struct i915_perf_stream *stream, bool enable)
 {
struct i915_request *rq;
+   struct intel_context *ce = stream->pinned_ctx;
u32 *cs;
+   u32 format = stream->oa_buffer.format;
int err = 0;
 
rq = i915_request_create(ce);
if (IS_ERR(rq))
return PTR_ERR(rq);
 
-   cs = intel_ring_begin(rq, 4);
+   cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
goto out;
}
 
-   *cs++ = MI_LOAD_REGISTER_IMM(1);
+   *cs++ = MI_LOAD_REGISTER_IMM(2);
+   /* Enable context save/restore of OAR counters */
*cs++ = 
i915_mmio_reg_offset(RING_CONTEXT_CONTROL(ce->engine->mmio_base));
*cs++ = _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
  enable ? GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : 0);
+   /* Enable OAR counters */
+   *cs++ = i915_mmio_reg_offset(GEN12_OAR_OACONTROL);
+   *cs++ = (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
+   (enable ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0);
*cs++ = MI_NOOP;
 
intel_ring_advance(rq, cs);
@@ -2474,8 +2481,7 @@ static int gen12_enable_metric_set(struct 
i915_perf_stream *stream)
 * requested this.
 */
if (stream->ctx) {
-   ret = gen12_emit_oar_config(stream->pinned_ctx,
-   oa_config != NULL);
+   ret = gen12_emit_oar_config(stream, oa_config != NULL);
if (ret)
return ret;
}
@@ -2513,7 +2519,7 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)
 
/* disable the context save/restore or OAR counters */
if (stream->ctx)
-   gen12_emit_oar_config(stream->pinned_ctx, false);
+   gen12_emit_oar_config(stream, false);
 
/* Make sure we disable noa to save power. */
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
@@ -2713,7 +2719,8 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
return -EINVAL;
}
 
-   if (!(props->sample_flags & SAMPLE_OA_REPORT)) {
+   if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
+   (INTEL_GEN(perf->i915) < 12 || !stream->ctx)) {
DRM_DEBUG("Only OA report sampling supported\n");
return -EINVAL;
}
@@ -2745,7 +2752,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 
format_size = perf->oa_formats[props->oa_format].size;
 
-   stream->sample_flags |= SAMPLE_OA_REPORT;
+   stream->sample_flags = props->sample_flags;
stream->sample_size += format_size;
 
stream->oa_buffer.format_size = format_size;
-- 
2.20.1

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Re: [Intel-gfx] [PATCH] drm/i915/perf: Configure OAR controls for specific context

[Chris Wilson]

Quoting Umesh Nerlige Ramappa (2019-11-07 23:22:34)
> It turns out that the OAR CONTROL register is not getting configured
> correctly in conjunction with the context save/restore bit. When
> measuring work for a single context, the OAR counters do not increment.
> 
> Configure OAR format and enable OAR counters at the same time as
> enabling context save/restore for OAR counters.

Did you write a test case to capture this bug for posterity? If so,
please include a Testcase: link. If not, please do so :)
-Chris
-
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Re: [Intel-gfx] [PATCH] drm/i915: Split a setting of MSA to MST and SST

[Lucas De Marchi]

On Wed, Nov 06, 2019 at 11:26:36PM +0200, Gwan-gyeong Mun wrote:

The setting of MSA is done by the DDI .pre_enable() hook. And when we are
using MST, the MSA is only set to first mst stream by calling of
DDI .pre_eanble() hook. It raies issues to non-first mst streams.
Wrong MSA or missed MSA packets might show scrambled screen or wrong
screen.

This splits a setting of MSA to MST and SST cases. And In the MST case it
will call a setting of MSA after an allocating of Virtual Channel from
MST encoder pre_enable callback.

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112212
Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry to DP 
MSA")
Fixes: d4a415dcda35 ("drm/i915: Fix MST oops due to MSA changes")
Signed-off-by: Gwan-gyeong Mun 
---
drivers/gpu/drm/i915/display/intel_ddi.c| 10 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c |  3 +++
2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c91521bcf06a..ef41fa0f77f0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state 
*crtc_state,
 * of Color Encoding Format and Content Color Gamut] while sending
 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
-*
-* FIXME MST doesn't pass in the conn_state
 */
-   if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+   if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
temp |= DP_MSA_MISC_COLOR_VSC_SDP;

I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
@@ -3606,7 +3604,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
else
hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);

-   intel_ddi_set_dp_msa(crtc_state, conn_state);
+   /* MST will call a setting of MSA after an allocating of Virtual Channel
+* from MST encoder pre_enable callback.
+*/
+   if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
+   intel_ddi_set_dp_msa(crtc_state, conn_state);
}

static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5e267c5b4c20..cb77f8072820 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -345,6 +345,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder,
 */
if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream)
intel_ddi_enable_pipe_clock(pipe_config);
+
+   intel_ddi_set_dp_msa(pipe_config, conn_state);
+


extra new line here, otherwise


Reviewed-by: Lucas De Marchi 

Lucas De Marchi


}

static void intel_mst_enable_dp(struct intel_encoder *encoder,
--
2.23.0

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[Intel-gfx] [PATCH] drm/i915/perf: Configure OAR controls for specific context

[Umesh Nerlige Ramappa]

It turns out that the OAR CONTROL register is not getting configured
correctly in conjunction with the context save/restore bit. When
measuring work for a single context, the OAR counters do not increment.

Configure OAR format and enable OAR counters at the same time as
enabling context save/restore for OAR counters.

Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_perf.c | 23 +++
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c380aba1ce9..527a16637689 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2219,26 +2219,33 @@ static int gen8_configure_context(struct 
i915_gem_context *ctx,
return err;
 }
 
-static int gen12_emit_oar_config(struct intel_context *ce, bool enable)
+static int gen12_emit_oar_config(struct i915_perf_stream *stream, bool enable)
 {
struct i915_request *rq;
+   struct intel_context *ce = stream->pinned_ctx;
u32 *cs;
+   u32 format = stream->oa_buffer.format;
int err = 0;
 
rq = i915_request_create(ce);
if (IS_ERR(rq))
return PTR_ERR(rq);
 
-   cs = intel_ring_begin(rq, 4);
+   cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
goto out;
}
 
-   *cs++ = MI_LOAD_REGISTER_IMM(1);
+   *cs++ = MI_LOAD_REGISTER_IMM(2);
+   /* Enable context save/restore of OAR counters */
*cs++ = 
i915_mmio_reg_offset(RING_CONTEXT_CONTROL(ce->engine->mmio_base));
*cs++ = _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
  enable ? GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : 0);
+   /* Enable OAR counters */
+   *cs++ = i915_mmio_reg_offset(GEN12_OAR_OACONTROL);
+   *cs++ = (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
+   (enable ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0);
*cs++ = MI_NOOP;
 
intel_ring_advance(rq, cs);
@@ -2474,8 +2481,7 @@ static int gen12_enable_metric_set(struct 
i915_perf_stream *stream)
 * requested this.
 */
if (stream->ctx) {
-   ret = gen12_emit_oar_config(stream->pinned_ctx,
-   oa_config != NULL);
+   ret = gen12_emit_oar_config(stream, oa_config != NULL);
if (ret)
return ret;
}
@@ -2513,7 +2519,7 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)
 
/* disable the context save/restore or OAR counters */
if (stream->ctx)
-   gen12_emit_oar_config(stream->pinned_ctx, false);
+   gen12_emit_oar_config(stream, false);
 
/* Make sure we disable noa to save power. */
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
@@ -2713,7 +2719,8 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
return -EINVAL;
}
 
-   if (!(props->sample_flags & SAMPLE_OA_REPORT)) {
+   if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
+   (INTEL_GEN(perf->i915) < 12 || !stream->ctx)) {
DRM_DEBUG("Only OA report sampling supported\n");
return -EINVAL;
}
@@ -2745,7 +2752,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 
format_size = perf->oa_formats[props->oa_format].size;
 
-   stream->sample_flags |= SAMPLE_OA_REPORT;
+   stream->sample_flags = props->sample_flags;
stream->sample_size += format_size;
 
stream->oa_buffer.format_size = format_size;
-- 
2.20.1

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Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier

[Souza, Jose]

On Thu, 2019-11-07 at 15:10 -0800, Lucas De Marchi wrote:
> On Thu, Nov 07, 2019 at 10:56:09PM +, Jose Souza wrote:
> > On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
> > > On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
> > > > This register was being enabled after enable TRANS_DDI_FUNC_CTL
> > > > and
> > > > PIPECONF/TRANS_CONF while BSpec states that it should be set
> > > > when
> > > > enabling TRANS_DDI_FUNC_CTL.
> > > > 
> > > > BSpec: 49190
> > > 
> > > not what I read here.
> > > 
> > > 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
> > > configured.
> > > Then configure and enable TRANS_DDI_FUNC_CTL.
> > 
> > We call icl_enable_trans_port_sync() in haswell_crtc_enable() and
> > then
> > a few lines later intel_ddi_enable_transcoder_func(), if not do
> > that
> > right away was a problem people working in port sync would get this
> > issue.
> 
> not what I meant. I meant the spec says to enable TRANS_DDI_FUNC_CTL,
> do step 8k, and then enable pipe VC payload allocation.
> 
> We aren't doing step 8k anywhere though, as I noted below.

8k is a VRR step that we don't support yet.

> 
> Lucas De Marchi
> 
> > > 8l. If DisplayPort multistream - Enable pipe VC payload
> > > allocation in
> > > TRANS_DDI_FUNC_CTL
> > > 
> > > But yes, this needs to be done before TRANS_CONF.
> > > 
> > > > BSpec: 22243
> > > 
> > > same here.  But as long as we don't do step 8k, I think they can
> > > in
> > > fact
> > > be combined.
> > > 
> > > These cover TGL and ICL only, while the code goes until haswell.
> > > Are
> > > you
> > > sure it's safe for the others?
> > > 
> > 
> > I had only checked if the register exist since HSW but now I
> > checked
> > HSW, BDW and SKL sequence all of then requires this.
> > 
> > BSpec: 4223
> > BSpec: 4163
> > BSpec: 4231
> > 
> > 
> > > thanks
> > > Lucas De Marchi
> > > 
> > > > Cc: Lucas De Marchi 
> > > > Signed-off-by: José Roberto de Souza 
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++---
> > > > 
> > > > -
> > > > drivers/gpu/drm/i915/display/intel_display.c |  6 --
> > > > 2 files changed, 2 insertions(+), 22 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > index 398c6f054a6e..3d5fce878600 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
> > > > intel_crtc_state *crtc_state,
> > > > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> > > > }
> > > > 
> > > > -void intel_ddi_set_vc_payload_alloc(const struct
> > > > intel_crtc_state
> > > > *crtc_state,
> > > > -   bool state)
> > > > -{
> > > > -   struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> > > > >uapi.crtc);
> > > > -   struct drm_i915_private *dev_priv = to_i915(crtc-
> > > > >base.dev);
> > > > -   enum transcoder cpu_transcoder = crtc_state-
> > > > >cpu_transcoder;
> > > > -   u32 temp;
> > > > -
> > > > -   temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > > > -   if (state == true)
> > > > -   temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > > > -   else
> > > > -   temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > > > -   I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > > > -}
> > > > -
> > > > /*
> > > >  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> > > >  *
> > > > @@ -1924,6 +1908,8 @@ void
> > > > intel_ddi_enable_transcoder_func(const
> > > > struct intel_crtc_state *crtc_state)
> > > > u32 temp;
> > > > 
> > > > temp =
> > > > intel_ddi_transcoder_func_reg_val_get(crtc_state);
> > > > +   if (intel_crtc_has_type(crtc_state,
> > > > INTEL_OUTPUT_DP_MST))
> > > > +   temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > > > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > > > }
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 551de2baa569..3b4aea253f8c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
> > > > intel_crtc_state *pipe_config,
> > > > if (pipe_config->has_pch_encoder)
> > > > lpt_pch_enable(state, pipe_config);
> > > > 
> > > > -   if (intel_crtc_has_type(pipe_config,
> > > > INTEL_OUTPUT_DP_MST))
> > > > -   intel_ddi_set_vc_payload_alloc(pipe_config,
> > > > true);
> > > > -
> > > > assert_vblank_disabled(crtc);
> > > > intel_crtc_vblank_on(pipe_config);
> > > > 
> > > > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
> > > > intel_crtc_state *old_crtc_state,
> > > > if (!transcoder_is_dsi(cpu_transcoder))
>

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't test plane stride with !INTEL_DISPLAY_ENABLED

[Patchwork]

== Series Details ==

Series: drm/i915: Don't test plane stride with !INTEL_DISPLAY_ENABLED
URL   : https://patchwork.freedesktop.org/series/69155/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7290 -> Patchwork_15184


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15184/index.html

Known issues


  Here are the changes found in Patchwork_15184 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_blt:
- fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([fdo#112176])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-bsw-nick/igt@i915_selftest@live_blt.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15184/fi-bsw-nick/igt@i915_selftest@live_blt.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2:  [PASS][3] -> [FAIL][4] ([fdo#109570])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15184/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2:  [PASS][5] -> [DMESG-WARN][6] ([fdo#110390])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15184/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111736]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15184/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@i915_module_load@reload:
- fi-icl-u2:  [DMESG-WARN][9] ([fdo#110595]) -> [PASS][10] +2 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-u2/igt@i915_module_l...@reload.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15184/fi-icl-u2/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq:  [FAIL][11] ([fdo#108511]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15184/fi-skl-6770hq/igt@i915_pm_...@module-reload.html

  
 Warnings 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2:  [DMESG-WARN][13] ([fdo#102505] / [fdo#110390]) -> 
[FAIL][14] ([fdo#111045])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7290/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15184/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#109570]: https://bugs.freedesktop.org/show_bug.cgi?id=109570
  [fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
  [fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176


Participating hosts (50 -> 44)
--

  Missing(6): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7290 -> Patchwork_15184

  CI-20190529: 20190529
  CI_DRM_7290: 869abae66a356231cfa6645cf491adde3590cba8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15184: 1f159d93035f8f7df028b601afe7b068856f0554 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1f159d93035f drm/i915: Don't test plane stride with !INTEL_DISPLAY_ENABLED

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15184/index.html
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier

[Lucas De Marchi]

On Thu, Nov 07, 2019 at 10:56:09PM +, Jose Souza wrote:

On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:

On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
> This register was being enabled after enable TRANS_DDI_FUNC_CTL and
> PIPECONF/TRANS_CONF while BSpec states that it should be set when
> enabling TRANS_DDI_FUNC_CTL.
>
> BSpec: 49190

not what I read here.

8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
configured.
Then configure and enable TRANS_DDI_FUNC_CTL.


We call icl_enable_trans_port_sync() in haswell_crtc_enable() and then
a few lines later intel_ddi_enable_transcoder_func(), if not do that
right away was a problem people working in port sync would get this
issue.


not what I meant. I meant the spec says to enable TRANS_DDI_FUNC_CTL,
do step 8k, and then enable pipe VC payload allocation.

We aren't doing step 8k anywhere though, as I noted below.

Lucas De Marchi





8l. If DisplayPort multistream - Enable pipe VC payload allocation in
TRANS_DDI_FUNC_CTL

But yes, this needs to be done before TRANS_CONF.

> BSpec: 22243

same here.  But as long as we don't do step 8k, I think they can in
fact
be combined.

These cover TGL and ICL only, while the code goes until haswell. Are
you
sure it's safe for the others?



I had only checked if the register exist since HSW but now I checked
HSW, BDW and SKL sequence all of then requires this.

BSpec: 4223
BSpec: 4163
BSpec: 4231



thanks
Lucas De Marchi

> Cc: Lucas De Marchi 
> Signed-off-by: José Roberto de Souza 
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++---
> -
> drivers/gpu/drm/i915/display/intel_display.c |  6 --
> 2 files changed, 2 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 398c6f054a6e..3d5fce878600 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
> intel_crtc_state *crtc_state,
>I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> }
>
> -void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
> *crtc_state,
> -  bool state)
> -{
> -  struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -  struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -  enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -  u32 temp;
> -
> -  temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> -  if (state == true)
> -  temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> -  else
> -  temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> -  I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> -}
> -
> /*
>  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
>  *
> @@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const
> struct intel_crtc_state *crtc_state)
>u32 temp;
>
>temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
> +  if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
> +  temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
>I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 551de2baa569..3b4aea253f8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
> intel_crtc_state *pipe_config,
>if (pipe_config->has_pch_encoder)
>lpt_pch_enable(state, pipe_config);
>
> -  if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> -  intel_ddi_set_vc_payload_alloc(pipe_config, true);
> -
>assert_vblank_disabled(crtc);
>intel_crtc_vblank_on(pipe_config);
>
> @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
> intel_crtc_state *old_crtc_state,
>if (!transcoder_is_dsi(cpu_transcoder))
>intel_disable_pipe(old_crtc_state);
>
> -  if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
> -  intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
> -
>if (INTEL_GEN(dev_priv) >= 11)
>icl_disable_transcoder_port_sync(old_crtc_state);
>
> --
> 2.24.0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Don't oops in dumb_create ioctl if we have no crtcs

[Patchwork]

== Series Details ==

Series: drm/i915: Don't oops in dumb_create ioctl if we have no crtcs
URL   : https://patchwork.freedesktop.org/series/69081/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7275_full -> Patchwork_15160_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_15160_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@vcs1-cleanup:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) 
+1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-iclb2/igt@gem_ctx_persiste...@vcs1-cleanup.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-iclb7/igt@gem_ctx_persiste...@vcs1-cleanup.html

  * igt@gem_ctx_switch@vcs1-queue:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([fdo#111735])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-tglb9/igt@gem_ctx_swi...@vcs1-queue.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-tglb7/igt@gem_ctx_swi...@vcs1-queue.html

  * igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112146]) +7 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-iclb6/igt@gem_exec_as...@concurrent-writes-bsd.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-iclb4/igt@gem_exec_as...@concurrent-writes-bsd.html

  * igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +10 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-iclb3/igt@gem_exec_paral...@vcs1-fds.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb:  [PASS][9] -> [DMESG-WARN][10] ([fdo#111870])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-snb4/igt@gem_userptr_bl...@sync-unmap-cycles.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html

  * igt@i915_pm_rps@waitboost:
- shard-glk:  [PASS][11] -> [FAIL][12] ([fdo#102250])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-glk9/igt@i915_pm_...@waitboost.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-glk5/igt@i915_pm_...@waitboost.html

  * igt@i915_selftest@live_hangcheck:
- shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111747])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-tglb2/igt@i915_selftest@live_hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-tglb3/igt@i915_selftest@live_hangcheck.html

  * igt@i915_suspend@debugfs-reader:
- shard-apl:  [PASS][15] -> [DMESG-WARN][16] ([fdo#108566])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-apl8/igt@i915_susp...@debugfs-reader.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-apl4/igt@i915_susp...@debugfs-reader.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-tglb: [PASS][17] -> [TIMEOUT][18] ([fdo#112168])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-tglb1/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-tglb4/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
- shard-skl:  [PASS][19] -> [DMESG-WARN][20] ([fdo#105541])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-skl5/igt@kms_cursor_leg...@long-nonblocking-modeset-vs-cursor-atomic.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-skl4/igt@kms_cursor_leg...@long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +5 similar 
issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-iclb2/igt@kms_frontbuffer_track...@fbc-rgb565-draw-blt.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-iclb2/igt@kms_frontbuffer_track...@fbc-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-tglb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +2 similar 
issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7275/shard-tglb4/igt@kms_frontbuffer_track...@fbc-stridechange.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15160/shard-tglb9/igt@kms_frontbuffer_track...@fbc-stridechange.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl:  [PASS][25] -> [INCOMPLETE][2

Re: [Intel-gfx] [PATCH] drm/i915: disable set/get_tiling ioctl on gen12+

[Brian Welty]

On 8/28/2019 11:50 PM, Daniel Vetter wrote:
> On Wed, Aug 28, 2019 at 08:31:27PM +, Souza, Jose wrote:
>> On Wed, 2019-08-28 at 21:13 +0100, Chris Wilson wrote:
>>> Quoting Souza, Jose (2019-08-28 21:11:53)
 Reviewed-by: José Roberto de Souza 
>>>
>>> It's using a non-standard for i915 error code, and get_tiling is not
>>
>> Huum should it use ENOTSUPP then?!
> 
> https://dri.freedesktop.org/docs/drm/gpu/drm-uapi.html#recommended-ioctl-return-values
> 
> Per above "feature not supported" -> EOPNOTSUPP.
> 
>>> affected, it will always return LINEAR. You cannot set tiling as 
>>
>> Following this set_tiling() LINEAR should be allowed too.
>> I prefer the current approach of returning error.
> 
> I'm not seeing the value in keeping get_tiling supported. Either userspace
> still uses the legacy backhannel and dri2, in which case it needs to be
> fixed no matter what. Or it's using modifiers, in which case this is dead
> code. Only other user I can think of is takeover for fastboot, but if you
> get anything else than untiled it's also broken (we don't have an ioctl to
> read out the modifiers, heck even all the planes, there's no getfb2).
> 
> So really not seeing the point in keeping that working.

Daniel,  I came across usage of GET_TILING in libdrm.
Is used in drm_intel_bo_gem_create_from_name() and 
drm_intel_bo_gem_create_from_prime().
Should these be updated so they don't fail when EOPNOTSUPP is returned on 
gen12+?
Maybe libdrm should just set tiling_mode to 0 on EOPNOTSUPP error instead of 
those calls failing?

-Brian

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Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier

[Souza, Jose]

On Thu, 2019-11-07 at 14:44 -0800, Lucas De Marchi wrote:
> On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:
> > This register was being enabled after enable TRANS_DDI_FUNC_CTL and
> > PIPECONF/TRANS_CONF while BSpec states that it should be set when
> > enabling TRANS_DDI_FUNC_CTL.
> > 
> > BSpec: 49190
> 
> not what I read here.
> 
> 8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be
> configured.
> Then configure and enable TRANS_DDI_FUNC_CTL.

We call icl_enable_trans_port_sync() in haswell_crtc_enable() and then
a few lines later intel_ddi_enable_transcoder_func(), if not do that
right away was a problem people working in port sync would get this
issue.

> 
> 8l. If DisplayPort multistream - Enable pipe VC payload allocation in
> TRANS_DDI_FUNC_CTL
> 
> But yes, this needs to be done before TRANS_CONF.
> 
> > BSpec: 22243
> 
> same here.  But as long as we don't do step 8k, I think they can in
> fact
> be combined.
> 
> These cover TGL and ICL only, while the code goes until haswell. Are
> you
> sure it's safe for the others?
> 

I had only checked if the register exist since HSW but now I checked
HSW, BDW and SKL sequence all of then requires this.

BSpec: 4223
BSpec: 4163
BSpec: 4231


> thanks
> Lucas De Marchi
> 
> > Cc: Lucas De Marchi 
> > Signed-off-by: José Roberto de Souza 
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++---
> > -
> > drivers/gpu/drm/i915/display/intel_display.c |  6 --
> > 2 files changed, 2 insertions(+), 22 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 398c6f054a6e..3d5fce878600 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct
> > intel_crtc_state *crtc_state,
> > I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> > }
> > 
> > -void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
> > *crtc_state,
> > -   bool state)
> > -{
> > -   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > -   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > -   u32 temp;
> > -
> > -   temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > -   if (state == true)
> > -   temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > -   else
> > -   temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > -   I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > -}
> > -
> > /*
> >  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> >  *
> > @@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const
> > struct intel_crtc_state *crtc_state)
> > u32 temp;
> > 
> > temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
> > +   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
> > +   temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > }
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 551de2baa569..3b4aea253f8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct
> > intel_crtc_state *pipe_config,
> > if (pipe_config->has_pch_encoder)
> > lpt_pch_enable(state, pipe_config);
> > 
> > -   if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> > -   intel_ddi_set_vc_payload_alloc(pipe_config, true);
> > -
> > assert_vblank_disabled(crtc);
> > intel_crtc_vblank_on(pipe_config);
> > 
> > @@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct
> > intel_crtc_state *old_crtc_state,
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_disable_pipe(old_crtc_state);
> > 
> > -   if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
> > -   intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
> > -
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_disable_transcoder_port_sync(old_crtc_state);
> > 
> > -- 
> > 2.24.0
> > 
> > ___
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier

[Lucas De Marchi]

On Thu, Nov 07, 2019 at 01:45:59PM -0800, Jose Souza wrote:

This register was being enabled after enable TRANS_DDI_FUNC_CTL and
PIPECONF/TRANS_CONF while BSpec states that it should be set when
enabling TRANS_DDI_FUNC_CTL.

BSpec: 49190


not what I read here.

8j. Configure TRANS_DDI_FUNC_CTL2 if port sync mode needs to be configured.
Then configure and enable TRANS_DDI_FUNC_CTL.

8l. If DisplayPort multistream - Enable pipe VC payload allocation in 
TRANS_DDI_FUNC_CTL

But yes, this needs to be done before TRANS_CONF.


BSpec: 22243


same here.  But as long as we don't do step 8k, I think they can in fact
be combined.

These cover TGL and ICL only, while the code goes until haswell. Are you
sure it's safe for the others?

thanks
Lucas De Marchi


Cc: Lucas De Marchi 
Signed-off-by: José Roberto de Souza 
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++
drivers/gpu/drm/i915/display/intel_display.c |  6 --
2 files changed, 2 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 398c6f054a6e..3d5fce878600 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state 
*crtc_state,
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}

-void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
-   bool state)
-{
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-   u32 temp;
-
-   temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
-   if (state == true)
-   temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
-   else
-   temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
-   I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
-}
-
/*
 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 *
@@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
u32 temp;

temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
+   temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 551de2baa569..3b4aea253f8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct intel_crtc_state 
*pipe_config,
if (pipe_config->has_pch_encoder)
lpt_pch_enable(state, pipe_config);

-   if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
-   intel_ddi_set_vc_payload_alloc(pipe_config, true);
-
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);

@@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct intel_crtc_state 
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_disable_pipe(old_crtc_state);

-   if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
-   intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
-
if (INTEL_GEN(dev_priv) >= 11)
icl_disable_transcoder_port_sync(old_crtc_state);

--
2.24.0

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Re: [Intel-gfx] [PATCH] drm/i915: Expand documentation for gen12 DP pre-enable sequence

[Matt Roper]

On Thu, Nov 07, 2019 at 12:16:13PM -0800, Souza, Jose wrote:
> On Thu, 2019-11-07 at 09:45 -0800, Matt Roper wrote:
> > Rather than just specifying the bullet numbers from the bspec (e.g.,
> > "4.b") actually include the description of what the bspec wants us to
> > do.  Steps can be renumbered or moved so including the description
> > will
> > help us match the code up to the spec.  Plus if we add support for
> > new
> > platforms, some of the steps may be added/removed so more descriptive
> > comments will be useful for ensuring all of the bspec requirements
> > are
> > met.
> > 
> > Cc: José Roberto de Souza 
> > Cc: Lucas De Marchi 
> > Signed-off-by: Matt Roper 
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 92 ++--
> > 
> >  1 file changed, 72 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 398c6f054a6e..ad39cd608011 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3438,48 +3438,86 @@ static void tgl_ddi_pre_enable_dp(struct
> > intel_encoder *encoder,
> > intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
> > intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
> >  
> > -   /* 1.a got on intel_atomic_commit_tail() */
> > +   /*
> > +* 1. Enable Power Wells
> > +*
> > +* This was handled at the beginning of
> > intel_atomic_commit_tail(),
> > +* before we called down into this function.
> > +*/
> >  
> > -   /* 2. */
> > +   /* 2. Enable Panel Power if PPS is required */
> > intel_edp_panel_on(intel_dp);
> >  
> > /*
> > -* 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
> > -* haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
> > -* haswell_crtc_enable()->intel_enable_shared_dpll()
> > +* 3. For non-TBT Type-C ports, set FIA lane count
> > +* (DFLEXDPSP.DPX4TXLATC)
> > +*
> > +* This was done before tgl_ddi_pre_enable_dp by
> > +* haswell_crtc_enable()->intel_encoders_pre_pll_enable().
> >  */
> >  
> > -   /* 4.b */
> > +   /*
> > +* 4. Enable the port PLL.
> > +*
> > +* The PLL enabling itself was already done before this
> > function by
> > +* haswell_crtc_enable()->intel_enable_shared_dpll().  We need
> > only
> > +* configure the PLL to port mapping here.
> > +*/
> > intel_ddi_clk_select(encoder, crtc_state);
> >  
> > -   /* 5. */
> > +   /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO
> > Power */
> > if (!intel_phy_is_tc(dev_priv, phy) ||
> > dig_port->tc_mode != TC_PORT_TBT_ALT)
> > intel_display_power_get(dev_priv,
> > dig_port->ddi_io_power_domain);
> >  
> > -   /* 6. */
> > +   /* 6. Program DP_MODE */
> > icl_program_mg_dp_mode(dig_port, crtc_state);
> >  
> > /*
> > -* 7.a - single stream or multi-stream master transcoder:
> > Configure
> > -* Transcoder Clock Select. For additional MST streams this
> > will be done
> > -* by intel_mst_pre_enable_dp() after programming VC Payload ID
> > through
> > -* AUX.
> > +* 7. The rest of the below are substeps under the bspec's
> > "Enable and
> > +* Train Display Port" step.  Note that steps that are specific
> > to
> > +* MST will be handled by intel_mst_pre_enable_dp()
> > before/after it
> > +* calls into this function.  Also intel_mst_pre_enable_dp()
> > only calls
> > +* us when active_mst_links==0, so any steps designated for
> > "single
> > +* stream or multi-stream master transcoder" can just be
> > performed
> > +* unconditionally here.
> > +*/
> > +
> > +   /*
> > +* 7a. Configure Transcoder Clock Select to direct the Port
> > clock to the
> > +* Transcoder.
> 
> Before push, please fix:
> s/7a/7.a
> s/7b/7.b
> ...
> 
> To keep consistent with the steps above

Made this tweak and pushed to dinq.  Thanks Jose and Lucas for the
reviews.

Technically only BAT results have come back at this point, but since
this commit only touches comments and no code there shouldn't be any
behavioral changes.


Matt

> 
> Other than that:
> 
> Reviewed-by: José Roberto de Souza 
> 
> >  */
> > intel_ddi_enable_pipe_clock(crtc_state);
> >  
> > -   /* 7.b */
> > +   /*
> > +* 7b. Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select
> > & MST
> > +* Transport Select
> > +*/
> > intel_ddi_config_transcoder_func(crtc_state);
> >  
> > -   /* 7.d */
> > +   /*
> > +* 7c. Configure & enable DP_TP_CTL with link training pattern
> > 1
> > +* selected
> > +*
> > +* This will be handled by the intel_dp_start_link_train()
> > farther
> > +* down this function.
> > +*/
> > +
> > +   /*
> > +* 7d. Type C with DP alternate or fixed/legacy/static
> > connection -
> > +* Disable PHY clock gating per Type-C DDI Buffer page
> > +*/
> > icl_p

Re: [Intel-gfx] [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition

[Lucas De Marchi]

On Thu, Nov 07, 2019 at 01:45:57PM -0800, Jose Souza wrote:

TRANS_DDI_MST_TRANSPORT_SELECT is 2 bits wide not 3, it was taking
one bit from EDP/DSI Input Select.

Fixes: b3545e086877 ("drm/i915/tgl: add support to one DP-MST stream")
Cc: Lucas De Marchi 
Signed-off-by: José Roberto de Souza 


ugh, facepalm

Double checked that it matches the spec.

Reviewed-by: Lucas De Marchi 

thanks
Lucas De Marchi


---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..70459a3d93e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9665,7 +9665,7 @@ enum skl_power_gate {
#define  TRANS_DDI_EDP_INPUT_A_ONOFF(4 << 12)
#define  TRANS_DDI_EDP_INPUT_B_ONOFF(5 << 12)
#define  TRANS_DDI_EDP_INPUT_C_ONOFF(6 << 12)
-#define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK   REG_GENMASK(12, 10)
+#define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK   REG_GENMASK(11, 10)
#define  TRANS_DDI_MST_TRANSPORT_SELECT(trans)  \
REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
#define  TRANS_DDI_HDCP_SIGNALLING  (1 << 9)
--
2.24.0

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[Intel-gfx] [PATCH] drm/i915/selftests: Mark up sole accessor to ctx->vm as being protected

[Chris Wilson]

In the selftests, where we are accessing a private ctx from within the
confines of a single test, we know that the ctx->vm pointer is static
and bounded by the lifetime of the test. We can use a simple helper to
provide the RCU annotations to keep sparse happy.

Signed-off-by: Chris Wilson 
---
 .../drm/i915/gem/selftests/i915_gem_context.c | 24 +++
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 0d4cdf38d5f9..13ae8f66bed6 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -26,6 +26,12 @@
 
 #define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))
 
+static inline struct i915_address_space *ctx_vm(struct i915_gem_context *ctx)
+{
+   /* single threaded, private ctx */
+   return rcu_dereference_protected(ctx->vm, true);
+}
+
 static int live_nop_switch(void *arg)
 {
const unsigned int nctx = 1024;
@@ -787,14 +793,15 @@ static int igt_shared_ctx_exec(void *arg)
}
 
mutex_lock(&ctx->mutex);
-   __assign_ppgtt(ctx, parent->vm);
+   __assign_ppgtt(ctx, ctx_vm(parent));
mutex_unlock(&ctx->mutex);
 
ce = i915_gem_context_get_engine(ctx, 
engine->legacy_idx);
GEM_BUG_ON(IS_ERR(ce));
 
if (!obj) {
-   obj = create_test_object(parent->vm, file, 
&objects);
+   obj = create_test_object(ctx_vm(parent),
+file, &objects);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
intel_context_put(ce);
@@ -1344,14 +1351,11 @@ static int igt_ctx_readonly(void *arg)
goto out_file;
}
 
-   rcu_read_lock();
-   vm = rcu_dereference(ctx->vm) ?: &i915->ggtt.alias->vm;
+   vm = ctx_vm(ctx) ?: &i915->ggtt.alias->vm;
if (!vm || !vm->has_read_only) {
-   rcu_read_unlock();
err = 0;
goto out_file;
}
-   rcu_read_unlock();
 
ndwords = 0;
dw = 0;
@@ -1381,7 +1385,7 @@ static int igt_ctx_readonly(void *arg)
pr_err("Failed to fill dword %lu [%lu/%lu] with 
gpu (%s) [full-ppgtt? %s], err=%d\n",
   ndwords, dw, max_dwords(obj),
   ce->engine->name,
-  yesno(!!rcu_access_pointer(ctx->vm)),
+  yesno(!!ctx_vm(ctx)),
   err);
i915_gem_context_unlock_engines(ctx);
goto out_file;
@@ -1699,11 +1703,11 @@ static int igt_vm_isolation(void *arg)
}
 
/* We can only test vm isolation, if the vm are distinct */
-   if (ctx_a->vm == ctx_b->vm)
+   if (ctx_vm(ctx_a) == ctx_vm(ctx_b))
goto out_file;
 
-   vm_total = ctx_a->vm->total;
-   GEM_BUG_ON(ctx_b->vm->total != vm_total);
+   vm_total = ctx_vm(ctx_a)->total;
+   GEM_BUG_ON(ctx_vm(ctx_b)->total != vm_total);
vm_total -= I915_GTT_PAGE_SIZE;
 
count = 0;
-- 
2.24.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Split a setting of MSA to MST and SST (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Split a setting of MSA to MST and SST (rev3)
URL   : https://patchwork.freedesktop.org/series/69092/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15183


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/index.html

Known issues


  Here are the changes found in Patchwork_15183 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_gem_contexts:
- fi-bsw-n3050:   [PASS][1] -> [INCOMPLETE][2] ([fdo# 111542])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111736]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@gem_exec_suspend@basic-s3:
- fi-cml-s:   [DMESG-WARN][5] ([fdo#111764]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/fi-cml-s/igt@gem_exec_susp...@basic-s3.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][7] ([fdo#111407]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][9] ([fdo#104108]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764


Participating hosts (51 -> 44)
--

  Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-gdg-551 fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15183

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15183: ad95549dfc69251f568c5c24728eb94f02341ca6 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ad95549dfc69 drm/i915: Split a setting of MSA to MST and SST

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15183/index.html
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[Intel-gfx] [PATCH 3/3] drm/i915/display/mst: Enable virtual channel payload allocation earlier

[José Roberto de Souza]

This register was being enabled after enable TRANS_DDI_FUNC_CTL and
PIPECONF/TRANS_CONF while BSpec states that it should be set when
enabling TRANS_DDI_FUNC_CTL.

BSpec: 49190
BSpec: 22243
Cc: Lucas De Marchi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++
 drivers/gpu/drm/i915/display/intel_display.c |  6 --
 2 files changed, 2 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 398c6f054a6e..3d5fce878600 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1803,22 +1803,6 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state 
*crtc_state,
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 }
 
-void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
-   bool state)
-{
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-   u32 temp;
-
-   temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
-   if (state == true)
-   temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
-   else
-   temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
-   I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
-}
-
 /*
  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
  *
@@ -1924,6 +1908,8 @@ void intel_ddi_enable_transcoder_func(const struct 
intel_crtc_state *crtc_state)
u32 temp;
 
temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
+   temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 551de2baa569..3b4aea253f8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6670,9 +6670,6 @@ static void haswell_crtc_enable(struct intel_crtc_state 
*pipe_config,
if (pipe_config->has_pch_encoder)
lpt_pch_enable(state, pipe_config);
 
-   if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
-   intel_ddi_set_vc_payload_alloc(pipe_config, true);
-
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
 
@@ -6783,9 +6780,6 @@ static void haswell_crtc_disable(struct intel_crtc_state 
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_disable_pipe(old_crtc_state);
 
-   if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
-   intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
-
if (INTEL_GEN(dev_priv) >= 11)
icl_disable_transcoder_port_sync(old_crtc_state);
 
-- 
2.24.0

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[Intel-gfx] [PATCH 2/3] drm/i915/display/dsi: Add support to pipe D

[José Roberto de Souza]

Adding pipe D support to DSI transcoder.
Not adding it for EDP transcoder code paths as only TGL has 4 pipes
and it do not have a EDP transcoder.

Cc: Lucas De Marchi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++
 drivers/gpu/drm/i915/i915_reg.h| 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8eb2d7f29c82..f688207932e0 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -745,6 +745,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder 
*encoder,
case PIPE_C:
tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
break;
+   case PIPE_D:
+   tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
+   break;
}
 
/* enable DDI buffer */
@@ -1325,6 +1328,9 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder 
*encoder,
case TRANS_DDI_EDP_INPUT_C_ONOFF:
*pipe = PIPE_C;
break;
+   case TRANS_DDI_EDP_INPUT_D_ONOFF:
+   *pipe = PIPE_D;
+   break;
default:
DRM_ERROR("Invalid PIPE input\n");
goto out;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70459a3d93e3..88d1430a6800 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9665,6 +9665,7 @@ enum skl_power_gate {
 #define  TRANS_DDI_EDP_INPUT_A_ONOFF   (4 << 12)
 #define  TRANS_DDI_EDP_INPUT_B_ONOFF   (5 << 12)
 #define  TRANS_DDI_EDP_INPUT_C_ONOFF   (6 << 12)
+#define  TRANS_DDI_EDP_INPUT_D_ONOFF   (7 << 12)
 #define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK   REG_GENMASK(11, 10)
 #define  TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
-- 
2.24.0

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[Intel-gfx] [PATCH 1/3] drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition

[José Roberto de Souza]

TRANS_DDI_MST_TRANSPORT_SELECT is 2 bits wide not 3, it was taking
one bit from EDP/DSI Input Select.

Fixes: b3545e086877 ("drm/i915/tgl: add support to one DP-MST stream")
Cc: Lucas De Marchi 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..70459a3d93e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9665,7 +9665,7 @@ enum skl_power_gate {
 #define  TRANS_DDI_EDP_INPUT_A_ONOFF   (4 << 12)
 #define  TRANS_DDI_EDP_INPUT_B_ONOFF   (5 << 12)
 #define  TRANS_DDI_EDP_INPUT_C_ONOFF   (6 << 12)
-#define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK   REG_GENMASK(12, 10)
+#define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK   REG_GENMASK(11, 10)
 #define  TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
 #define  TRANS_DDI_HDCP_SIGNALLING (1 << 9)
-- 
2.24.0

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[Intel-gfx] [PATCH] drm/i915/selftests: Complete transition to a real struct file mock

[Chris Wilson]

Since drm provided us with a real struct file we can use for our
anonymous internal clients (mock_file), complete our transition to using
that as the primary interface (and not the mocked up struct drm_file we
previous were using).

Signed-off-by: Chris Wilson 
Cc: Matthew Auld 
---
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  4 +-
 .../drm/i915/gem/selftests/i915_gem_context.c | 31 +++
 .../i915/gem/selftests/i915_gem_object_blt.c  |  8 ++--
 .../gpu/drm/i915/gem/selftests/mock_context.c |  5 ++-
 .../gpu/drm/i915/gem/selftests/mock_context.h |  2 +-
 drivers/gpu/drm/i915/gt/selftest_context.c|  8 ++--
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  | 16 
 .../gpu/drm/i915/gt/selftest_workarounds.c|  4 +-
 drivers/gpu/drm/i915/i915_drv.c   |  4 --
 drivers/gpu/drm/i915/selftests/i915_gem.c |  8 ++--
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |  4 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  8 ++--
 drivers/gpu/drm/i915/selftests/i915_request.c |  4 +-
 .../drm/i915/selftests/intel_memory_region.c  |  4 +-
 drivers/gpu/drm/i915/selftests/mock_drm.c | 38 ---
 drivers/gpu/drm/i915/selftests/mock_drm.h | 15 ++--
 16 files changed, 65 insertions(+), 98 deletions(-)
 delete mode 100644 drivers/gpu/drm/i915/selftests/mock_drm.c

diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 2310ed9b8f89..3f992491f537 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1912,9 +1912,9 @@ int i915_gem_huge_page_live_selftests(struct 
drm_i915_private *i915)
SUBTEST(igt_ppgtt_smoke_huge),
SUBTEST(igt_ppgtt_sanity_check),
};
-   struct drm_file *file;
struct i915_gem_context *ctx;
struct i915_address_space *vm;
+   struct file *file;
int err;
 
if (!HAS_PPGTT(i915)) {
@@ -1944,6 +1944,6 @@ int i915_gem_huge_page_live_selftests(struct 
drm_i915_private *i915)
err = i915_subtests(tests, ctx);
 
 out_file:
-   mock_file_put(file);
+   fput(file);
return err;
 }
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 47890c92534c..18ae2cfa62ed 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -33,7 +33,7 @@ static int live_nop_switch(void *arg)
struct intel_engine_cs *engine;
struct i915_gem_context **ctx;
struct igt_live_test t;
-   struct drm_file *file;
+   struct file *file;
unsigned long n;
int err = -ENODEV;
 
@@ -149,7 +149,7 @@ static int live_nop_switch(void *arg)
}
 
 out_file:
-   mock_file_put(file);
+   fput(file);
return err;
 }
 
@@ -255,7 +255,7 @@ static int live_parallel_switch(void *arg)
int (* const *fn)(void *arg);
struct i915_gem_context *ctx;
struct intel_context *ce;
-   struct drm_file *file;
+   struct file *file;
int n, m, count;
int err = 0;
 
@@ -377,7 +377,7 @@ static int live_parallel_switch(void *arg)
}
kfree(data);
 out_file:
-   mock_file_put(file);
+   fput(file);
return err;
 }
 
@@ -502,7 +502,7 @@ static noinline int cpu_check(struct drm_i915_gem_object 
*obj,
return err;
 }
 
-static int file_add_object(struct drm_file *file,
+static int file_add_object(struct file *file,
struct drm_i915_gem_object *obj)
 {
int err;
@@ -510,7 +510,8 @@ static int file_add_object(struct drm_file *file,
GEM_BUG_ON(obj->base.handle_count);
 
/* tie the object to the drm_file for easy reaping */
-   err = idr_alloc(&file->object_idr, &obj->base, 1, 0, GFP_KERNEL);
+   err = idr_alloc(&to_drm_file(file)->object_idr,
+   &obj->base, 1, 0, GFP_KERNEL);
if (err < 0)
return  err;
 
@@ -521,7 +522,7 @@ static int file_add_object(struct drm_file *file,
 
 static struct drm_i915_gem_object *
 create_test_object(struct i915_address_space *vm,
-  struct drm_file *file,
+  struct file *file,
   struct list_head *objects)
 {
struct drm_i915_gem_object *obj;
@@ -621,9 +622,9 @@ static int igt_ctx_exec(void *arg)
unsigned long ncontexts, ndwords, dw;
struct i915_request *tq[5] = {};
struct igt_live_test t;
-   struct drm_file *file;
IGT_TIMEOUT(end_time);
LIST_HEAD(objects);
+   struct file *file;
 
if (!intel_engine_can_store_dword(engine))
continue;
@@ -716,7 +717,7 @@ static int igt_ctx_exec(void *arg)
if (igt_live_test_end(&t))
err = -EIO;
 
-   mo

[Intel-gfx] [PATCH v5] drm/i915: Enable second dbuf slice for ICL and TGL

[Stanislav Lisovskiy]

Also implemented algorithm for choosing DBuf slice configuration
based on active pipes, pipe ratio as stated in BSpec 12716.

Now pipe allocation still stays proportional to pipe width as before,
however within allowed DBuf slice for this particular configuration.

v2: Remove unneeded check from commit as ddb enabled slices might
now differ from hw state.

v3: - Added new field "supported_slices" to ddb to separate max
  supported slices vs currently enabled, to avoid confusion.
- Removed obsolete comments and code related to DBuf(Matthew Roper).
- Some code style and long line removal(Matthew Roper).
- Added WARN_ON to new ddb range offset calc function(Matthew Roper).
- Removed platform specific call to calc pipe ratio from ddb
  allocation function and fixed the return value(Matthew Roper)
- Refactored DBUF slice allocation table to improve readability
- Added DBUF slice allocation for TGL as well.
- ICL(however not TGL) seems to voluntarily enable second DBuf slice
  after pm suspend/resume causing a mismatch failure, because we
  update DBuf slices only if we do a modeset, however this check
  is done always. Fixed it to be done only when modeset for ICL.

v4: - Now enabled slices is not actually a number, but a bitmask,
  because we might need to enable second slice only and number
  of slices would still 1 and that current code doesn't allow.
- Remove redundant duplicate code to have some unified way of
  enabling dbuf slices instead of hardcoding.

v5: - Fix failing gen9_assert_dbuf_enabled as it was naively thinking
  that we have only one DBUF_CTL slice. Now another version for
  gen11 will check both slices as only second one can be enabled,
  to keep CI happy.

Signed-off-by: Stanislav Lisovskiy 
Cc: Matthew Roper 
Cc: Ville Syrjälä 
Cc: James Ausmus 
---
 drivers/gpu/drm/i915/display/intel_display.c  |  22 +-
 .../drm/i915/display/intel_display_power.c| 103 +++--
 .../drm/i915/display/intel_display_power.h|   2 +
 drivers/gpu/drm/i915/i915_drv.c   |   5 +
 drivers/gpu/drm/i915/i915_drv.h   |   3 +-
 drivers/gpu/drm/i915/i915_reg.h   |   2 +
 drivers/gpu/drm/i915/intel_pm.c   | 391 --
 7 files changed, 441 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 876fc25968bf..ee63da18772a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13386,8 +13386,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
sw_ddb = &dev_priv->wm.skl_hw.ddb;
 
if (INTEL_GEN(dev_priv) >= 11 &&
-   hw->ddb.enabled_slices != sw_ddb->enabled_slices)
-   DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
+   hw->ddb.enabled_slices != sw_ddb->enabled_slices &&
+   needs_modeset(new_crtc_state))
+   DRM_ERROR("mismatch in DBUF Slices (expected %x, got %x)\n",
  sw_ddb->enabled_slices,
  hw->ddb.enabled_slices);
 
@@ -14613,16 +14614,21 @@ static void skl_commit_modeset_enables(struct 
intel_atomic_state *state)
int i;
u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
u8 required_slices = state->wm_results.ddb.enabled_slices;
-   struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
+   u8 slices_union = hw_enabled_slices | required_slices;
+   u8 slices_intersection = slices_union & required_slices;
 
+   struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 
new_crtc_state, i)
/* ignore allocations for crtc's that have been turned off. */
if (new_crtc_state->hw.active)
entries[i] = old_crtc_state->wm.skl.ddb;
 
-   /* If 2nd DBuf slice required, enable it here */
-   if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
-   icl_dbuf_slices_update(dev_priv, required_slices);
+   DRM_DEBUG_KMS("DBuf req slices %d hw slices %d\n",
+ required_slices, hw_enabled_slices);
+
+   /* If some other DBuf slice required, enable it here */
+   if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
+   icl_dbuf_slices_update(dev_priv, slices_union);
 
/*
 * Whenever the number of active pipes changes, we need to make sure we
@@ -14682,8 +14688,8 @@ static void skl_commit_modeset_enables(struct 
intel_atomic_state *state)
} while (progress);
 
/* If 2nd DBuf slice is no more required disable it */
-   if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
-   icl_dbuf_slices_update(dev_priv, required_slices);
+   if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm: Move EXPORT_SYMBOL_FOR_TESTS_ONLY under a separate Kconfig

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/5] drm: Move EXPORT_SYMBOL_FOR_TESTS_ONLY 
under a separate Kconfig
URL   : https://patchwork.freedesktop.org/series/69147/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15182


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15182/index.html

Known issues


  Here are the changes found in Patchwork_15182 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][1] ([fdo#111736]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15182/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][3] ([fdo#104108]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15182/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
 Warnings 

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][5] ([fdo#111407]) -> [FAIL][6] ([fdo#111045] / 
[fdo#111096])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15182/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (51 -> 45)
--

  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15182

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15182: 3074dbdd402770d6043c1f4fe9ecc666057f5573 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3074dbdd4027 drm/i915/selftests: Verify mmap_gtt revocation on unbinding
17c7b4b955b3 drm/i915/selftests: Wrap vm_mmap() around GEM objects
8783f21fe2d7 drm/i915/selftests: Replace mock_file hackery with drm's true fake
15c2da6271d1 drm: Expose a method for creating anonymous struct file around 
drm_minor
fe079a2c7f06 drm: Move EXPORT_SYMBOL_FOR_TESTS_ONLY under a separate Kconfig

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15182/index.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/2] drm/i915: lookup for mem_region of a mem_type

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/2] drm/i915: lookup for mem_region of a 
mem_type
URL   : https://patchwork.freedesktop.org/series/69075/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7274_full -> Patchwork_15158_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_15158_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl:  [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-kbl6/igt@gem_ctx_isolat...@rcs0-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) 
+2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-iclb2/igt@gem_ctx_isolat...@vcs1-none.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-iclb6/igt@gem_ctx_isolat...@vcs1-none.html

  * igt@gem_exec_create@madvise:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#111747])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-tglb2/igt@gem_exec_cre...@madvise.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-tglb6/igt@gem_exec_cre...@madvise.html

  * igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +11 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-iclb2/igt@gem_exec_paral...@vcs1-fds.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-iclb5/igt@gem_exec_paral...@vcs1-fds.html

  * igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +24 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-iclb1/igt@gem_exec_sched...@independent-bsd2.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +2 similar 
issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html

  * igt@gem_softpin@noreloc-s3:
- shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111832])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-tglb6/igt@gem_soft...@noreloc-s3.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-tglb3/igt@gem_soft...@noreloc-s3.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw:  [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb:  [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-snb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html

  * igt@gem_workarounds@suspend-resume-context:
- shard-apl:  [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +1 
similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-apl3/igt@gem_workarou...@suspend-resume-context.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-apl6/igt@gem_workarou...@suspend-resume-context.html

  * igt@i915_pm_rpm@drm-resources-equal:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713] / 
[fdo#108840])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-iclb4/igt@i915_pm_...@drm-resources-equal.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-iclb2/igt@i915_pm_...@drm-resources-equal.html

  * igt@i915_selftest@live_gt_heartbeat:
- shard-apl:  [PASS][23] -> [DMESG-FAIL][24] ([fdo#112096])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7274/shard-apl1/igt@i915_selftest@live_gt_heartbeat.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15158/shard-apl6/igt@i915_selftest@live_gt_heartbeat.html

  * igt@kms_atomic_transition@1x-modeset-transitions:
- shard-snb:  [PASS][25] -> [S

Re: [Intel-gfx] [PATCH] drm/i915: Split a setting of MSA to MST and SST

[Souza, Jose]

On Wed, 2019-11-06 at 23:26 +0200, Gwan-gyeong Mun wrote:
> The setting of MSA is done by the DDI .pre_enable() hook. And when we
> are
> using MST, the MSA is only set to first mst stream by calling of
> DDI .pre_eanble() hook. It raies issues to non-first mst streams.
> Wrong MSA or missed MSA packets might show scrambled screen or wrong
> screen.
> 
> This splits a setting of MSA to MST and SST cases. And In the MST
> case it
> will call a setting of MSA after an allocating of Virtual Channel
> from
> MST encoder pre_enable callback.

Reviewed-by: José Roberto de Souza 

> 
> Cc: Ville Syrjälä 
> Cc: Stanislav Lisovskiy 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112212
> Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry
> to DP MSA")
> Fixes: d4a415dcda35 ("drm/i915: Fix MST oops due to MSA changes")
> Signed-off-by: Gwan-gyeong Mun 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c| 10 ++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  3 +++
>  2 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c91521bcf06a..ef41fa0f77f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1794,10 +1794,8 @@ void intel_ddi_set_dp_msa(const struct
> intel_crtc_state *crtc_state,
>* of Color Encoding Format and Content Color Gamut] while
> sending
>* YCBCR 420, HDR BT.2020 signals we should program MSA MISC1
> fields
>* which indicate VSC SDP for the Pixel Encoding/Colorimetry
> Format.
> -  *
> -  * FIXME MST doesn't pass in the conn_state
>*/
> - if (conn_state && intel_dp_needs_vsc_sdp(crtc_state,
> conn_state))
> + if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
>   temp |= DP_MSA_MISC_COLOR_VSC_SDP;
>  
>   I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> @@ -3606,7 +3604,11 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>   else
>   hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
>  
> - intel_ddi_set_dp_msa(crtc_state, conn_state);
> + /* MST will call a setting of MSA after an allocating of
> Virtual Channel
> +  * from MST encoder pre_enable callback.
> +  */
> + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
> + intel_ddi_set_dp_msa(crtc_state, conn_state);
>  }
>  
>  static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 5e267c5b4c20..cb77f8072820 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -345,6 +345,9 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
>*/
>   if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream)
>   intel_ddi_enable_pipe_clock(pipe_config);
> +
> + intel_ddi_set_dp_msa(pipe_config, conn_state);
> +
>  }
>  
>  static void intel_mst_enable_dp(struct intel_encoder *encoder,
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Re: [Intel-gfx] [ANNOUNCEMENT] Documenting tests with igt_describe()

[Chris Wilson]

Quoting Arkadiusz Hiler (2019-11-07 17:38:20)
> We don't want you to translate C into English, we want you to provide a bit of
> that extra information that you would have put in the comments anyway.

The comments should exist and are _inline_ with the code. In all the
examples of igt_describe() I have seen, it is nowhere near the code so
is useless; the information conveyed does not assist anyone in
diagnosing or debugging the problem, so I yet to understand how it
helps. What is more useful, a link to the kernel coverage of the test
and link to the test source code, or waffle?
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm: Move EXPORT_SYMBOL_FOR_TESTS_ONLY under a separate Kconfig

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/5] drm: Move EXPORT_SYMBOL_FOR_TESTS_ONLY 
under a separate Kconfig
URL   : https://patchwork.freedesktop.org/series/69147/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fe079a2c7f06 drm: Move EXPORT_SYMBOL_FOR_TESTS_ONLY under a separate Kconfig
15c2da6271d1 drm: Expose a method for creating anonymous struct file around 
drm_minor
8783f21fe2d7 drm/i915/selftests: Replace mock_file hackery with drm's true fake
17c7b4b955b3 drm/i915/selftests: Wrap vm_mmap() around GEM objects
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:698:
+#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))

-:95: ERROR:SPACING: space required before that '*' (ctx:VxV)
#95: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:751:
+   u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof*(ux)));
^

-:151: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#151: 
new file mode 100644

-:156: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier 
tag in line 1
#156: FILE: drivers/gpu/drm/i915/selftests/igt_mmap.c:1:
+/*

-:157: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use 
line 1 instead
#157: FILE: drivers/gpu/drm/i915/selftests/igt_mmap.c:2:
+ * SPDX-License-Identifier: MIT

-:201: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier 
tag in line 1
#201: FILE: drivers/gpu/drm/i915/selftests/igt_mmap.h:1:
+/*

-:202: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use 
line 1 instead
#202: FILE: drivers/gpu/drm/i915/selftests/igt_mmap.h:2:
+ * SPDX-License-Identifier: MIT

total: 1 errors, 5 warnings, 1 checks, 183 lines checked
3074dbdd4027 drm/i915/selftests: Verify mmap_gtt revocation on unbinding
-:68: WARNING:LINE_SPACING: Missing a blank line after declarations
#68: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:840:
+   int err = __get_user(c, addr);
+   if (err)

total: 0 errors, 1 warnings, 0 checks, 122 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Expand documentation for gen12 DP pre-enable sequence

[Patchwork]

== Series Details ==

Series: drm/i915: Expand documentation for gen12 DP pre-enable sequence
URL   : https://patchwork.freedesktop.org/series/69146/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15181


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15181/index.html

Known issues


  Here are the changes found in Patchwork_15181 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic:
- fi-icl-u2:  [PASS][1] -> [FAIL][2] ([fdo#111699])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-u2/igt@gem_exec_susp...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15181/fi-icl-u2/igt@gem_exec_susp...@basic.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111736]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15181/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][5] ([fdo#104108]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15181/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111699]: https://bugs.freedesktop.org/show_bug.cgi?id=111699
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (51 -> 44)
--

  Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15181

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15181: b0207f4cc864c03146d6c8999d635f3e5abceb79 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b0207f4cc864 drm/i915: Expand documentation for gen12 DP pre-enable sequence

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15181/index.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/bios: store child devices in a list

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/bios: store child devices in a 
list
URL   : https://patchwork.freedesktop.org/series/69143/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15179


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15179/index.html

Known issues


  Here are the changes found in Patchwork_15179 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_blt:
- fi-hsw-peppy:   [PASS][1] -> [DMESG-FAIL][2] ([fdo#112147])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15179/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111736]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15179/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][5] ([fdo#104108]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15179/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147


Participating hosts (51 -> 45)
--

  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15179

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15179: b1c648957d6ca291c9c72a09c6424740f316809d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b1c648957d6c drm/i915/bios: pass devdata to parse_ddi_port
b4595815ed9d drm/i915/bios: store child devices in a list

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15179/index.html
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[Intel-gfx] [PATCH] drm/i915: Don't test plane stride with !INTEL_DISPLAY_ENABLED

[Matt Roper]

If INTEL_DISPLAY_ENABLED is false, then the modesetting resources were
never initialized.  Userspace may still call DRM_IOCTL_MODE_CREATE_DUMB
which will eventually lead i915_gem_dumb_create() to try to dereference
a non-existent pipe A primary plane while figuring out a proper pitch.

We could force dumb buffer creation to fail in cases where display isn't
enabled (since there isn't really a definition of a "suitable for
scanout" buffer in that case), but it's easier (and probably less
invasive to IGT tests) to just drop the attempt to align to plane max
stride in cases where the display isn't enabled.

Cc: Lucas De Marchi 
Cc: Jani Nikula 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/i915_gem.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 143a8952b736..f022a17328b0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -229,7 +229,8 @@ i915_gem_dumb_create(struct drm_file *file,
args->pitch = ALIGN(args->width * cpp, 64);
 
/* align stride to page size so that we can remap */
-   if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
+   if (INTEL_DISPLAY_ENABLED(to_i915(dev)) &&
+   args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
DRM_FORMAT_MOD_LINEAR))
args->pitch = ALIGN(args->pitch, 4096);
 
-- 
2.21.0

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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Taint the kernel on dumping the GEM ftrace buffer

[Patchwork]

== Series Details ==

Series: drm/i915: Taint the kernel on dumping the GEM ftrace buffer
URL   : https://patchwork.freedesktop.org/series/69144/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK include/generated/compile.h
  AR  drivers/gpu/drm/i915/built-in.a
  CC [M]  drivers/gpu/drm/i915/gt/intel_context.o
In file included from ./drivers/gpu/drm/i915/gt/intel_engine_types.h:20:0,
 from ./drivers/gpu/drm/i915/gt/intel_context_types.h:17,
 from ./drivers/gpu/drm/i915/gem/i915_gem_context_types.h:20,
 from ./drivers/gpu/drm/i915/gem/i915_gem_context.h:10,
 from drivers/gpu/drm/i915/gt/intel_context.c:7:
drivers/gpu/drm/i915/gt/selftest_context.c: In function ‘__live_active_context’:
./drivers/gpu/drm/i915/i915_gem.h:72:30: error: implicit declaration of 
function ‘set_taint_for_CI’; did you mean ‘add_taint_for_CI’? 
[-Werror=implicit-function-declaration]
  do { ftrace_dump(DUMP_ALL); set_taint_for_CI(TAIN_WARN); } while (0)
  ^
drivers/gpu/drm/i915/gt/selftest_context.c:275:3: note: in expansion of macro 
‘GEM_TRACE_DUMP’
   GEM_TRACE_DUMP();
   ^~
./drivers/gpu/drm/i915/i915_gem.h:72:47: error: ‘TAIN_WARN’ undeclared (first 
use in this function); did you mean ‘TAINT_WARN’?
  do { ftrace_dump(DUMP_ALL); set_taint_for_CI(TAIN_WARN); } while (0)
   ^
drivers/gpu/drm/i915/gt/selftest_context.c:275:3: note: in expansion of macro 
‘GEM_TRACE_DUMP’
   GEM_TRACE_DUMP();
   ^~
./drivers/gpu/drm/i915/i915_gem.h:72:47: note: each undeclared identifier is 
reported only once for each function it appears in
  do { ftrace_dump(DUMP_ALL); set_taint_for_CI(TAIN_WARN); } while (0)
   ^
drivers/gpu/drm/i915/gt/selftest_context.c:275:3: note: in expansion of macro 
‘GEM_TRACE_DUMP’
   GEM_TRACE_DUMP();
   ^~
cc1: all warnings being treated as errors
scripts/Makefile.build:265: recipe for target 
'drivers/gpu/drm/i915/gt/intel_context.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_context.o] Error 1
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1649: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: [Intel-gfx] [PATCH] drm/i915: Expand documentation for gen12 DP pre-enable sequence

[Souza, Jose]

On Thu, 2019-11-07 at 09:45 -0800, Matt Roper wrote:
> Rather than just specifying the bullet numbers from the bspec (e.g.,
> "4.b") actually include the description of what the bspec wants us to
> do.  Steps can be renumbered or moved so including the description
> will
> help us match the code up to the spec.  Plus if we add support for
> new
> platforms, some of the steps may be added/removed so more descriptive
> comments will be useful for ensuring all of the bspec requirements
> are
> met.
> 
> Cc: José Roberto de Souza 
> Cc: Lucas De Marchi 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 92 ++--
> 
>  1 file changed, 72 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 398c6f054a6e..ad39cd608011 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3438,48 +3438,86 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>   intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
>   intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
>  
> - /* 1.a got on intel_atomic_commit_tail() */
> + /*
> +  * 1. Enable Power Wells
> +  *
> +  * This was handled at the beginning of
> intel_atomic_commit_tail(),
> +  * before we called down into this function.
> +  */
>  
> - /* 2. */
> + /* 2. Enable Panel Power if PPS is required */
>   intel_edp_panel_on(intel_dp);
>  
>   /*
> -  * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
> -  * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
> -  * haswell_crtc_enable()->intel_enable_shared_dpll()
> +  * 3. For non-TBT Type-C ports, set FIA lane count
> +  * (DFLEXDPSP.DPX4TXLATC)
> +  *
> +  * This was done before tgl_ddi_pre_enable_dp by
> +  * haswell_crtc_enable()->intel_encoders_pre_pll_enable().
>*/
>  
> - /* 4.b */
> + /*
> +  * 4. Enable the port PLL.
> +  *
> +  * The PLL enabling itself was already done before this
> function by
> +  * haswell_crtc_enable()->intel_enable_shared_dpll().  We need
> only
> +  * configure the PLL to port mapping here.
> +  */
>   intel_ddi_clk_select(encoder, crtc_state);
>  
> - /* 5. */
> + /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO
> Power */
>   if (!intel_phy_is_tc(dev_priv, phy) ||
>   dig_port->tc_mode != TC_PORT_TBT_ALT)
>   intel_display_power_get(dev_priv,
>   dig_port->ddi_io_power_domain);
>  
> - /* 6. */
> + /* 6. Program DP_MODE */
>   icl_program_mg_dp_mode(dig_port, crtc_state);
>  
>   /*
> -  * 7.a - single stream or multi-stream master transcoder:
> Configure
> -  * Transcoder Clock Select. For additional MST streams this
> will be done
> -  * by intel_mst_pre_enable_dp() after programming VC Payload ID
> through
> -  * AUX.
> +  * 7. The rest of the below are substeps under the bspec's
> "Enable and
> +  * Train Display Port" step.  Note that steps that are specific
> to
> +  * MST will be handled by intel_mst_pre_enable_dp()
> before/after it
> +  * calls into this function.  Also intel_mst_pre_enable_dp()
> only calls
> +  * us when active_mst_links==0, so any steps designated for
> "single
> +  * stream or multi-stream master transcoder" can just be
> performed
> +  * unconditionally here.
> +  */
> +
> + /*
> +  * 7a. Configure Transcoder Clock Select to direct the Port
> clock to the
> +  * Transcoder.

Before push, please fix:
s/7a/7.a
s/7b/7.b
...

To keep consistent with the steps above

Other than that:

Reviewed-by: José Roberto de Souza 

>*/
>   intel_ddi_enable_pipe_clock(crtc_state);
>  
> - /* 7.b */
> + /*
> +  * 7b. Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select
> & MST
> +  * Transport Select
> +  */
>   intel_ddi_config_transcoder_func(crtc_state);
>  
> - /* 7.d */
> + /*
> +  * 7c. Configure & enable DP_TP_CTL with link training pattern
> 1
> +  * selected
> +  *
> +  * This will be handled by the intel_dp_start_link_train()
> farther
> +  * down this function.
> +  */
> +
> + /*
> +  * 7d. Type C with DP alternate or fixed/legacy/static
> connection -
> +  * Disable PHY clock gating per Type-C DDI Buffer page
> +  */
>   icl_phy_set_clock_gating(dig_port, false);
>  
> - /* 7.e */
> + /* 7e. Configure voltage swing and related IO settings */
>   tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
>   encoder->type);
>  
> - /* 7.f */
> + /*
> +  * 7f. Combo PHY: Configure PORT_CL_DW10 Static Power Down to
> power up
> +  * the used lanes of the DDI.
> +  */
>   if (intel_phy_is_combo(

Re: [Intel-gfx] [PATCH] drm/i915: Expand documentation for gen12 DP pre-enable sequence

[Lucas De Marchi]

On Thu, Nov 07, 2019 at 09:45:27AM -0800, Matt Roper wrote:

Rather than just specifying the bullet numbers from the bspec (e.g.,
"4.b") actually include the description of what the bspec wants us to
do.  Steps can be renumbered or moved so including the description will
help us match the code up to the spec.  Plus if we add support for new
platforms, some of the steps may be added/removed so more descriptive
comments will be useful for ensuring all of the bspec requirements are
met.

Cc: José Roberto de Souza 
Cc: Lucas De Marchi 
Signed-off-by: Matt Roper 



Reviewed-by: Lucas De Marchi 

Lucas De Marchi


---
drivers/gpu/drm/i915/display/intel_ddi.c | 92 ++--
1 file changed, 72 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 398c6f054a6e..ad39cd608011 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3438,48 +3438,86 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);

-   /* 1.a got on intel_atomic_commit_tail() */
+   /*
+* 1. Enable Power Wells
+*
+* This was handled at the beginning of intel_atomic_commit_tail(),
+* before we called down into this function.
+*/

-   /* 2. */
+   /* 2. Enable Panel Power if PPS is required */
intel_edp_panel_on(intel_dp);

/*
-* 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
-* haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
-* haswell_crtc_enable()->intel_enable_shared_dpll()
+* 3. For non-TBT Type-C ports, set FIA lane count
+* (DFLEXDPSP.DPX4TXLATC)
+*
+* This was done before tgl_ddi_pre_enable_dp by
+* haswell_crtc_enable()->intel_encoders_pre_pll_enable().
 */

-   /* 4.b */
+   /*
+* 4. Enable the port PLL.
+*
+* The PLL enabling itself was already done before this function by
+* haswell_crtc_enable()->intel_enable_shared_dpll().  We need only
+* configure the PLL to port mapping here.
+*/
intel_ddi_clk_select(encoder, crtc_state);

-   /* 5. */
+   /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
intel_display_power_get(dev_priv,
dig_port->ddi_io_power_domain);

-   /* 6. */
+   /* 6. Program DP_MODE */
icl_program_mg_dp_mode(dig_port, crtc_state);

/*
-* 7.a - single stream or multi-stream master transcoder: Configure
-* Transcoder Clock Select. For additional MST streams this will be done
-* by intel_mst_pre_enable_dp() after programming VC Payload ID through
-* AUX.
+* 7. The rest of the below are substeps under the bspec's "Enable and
+* Train Display Port" step.  Note that steps that are specific to
+* MST will be handled by intel_mst_pre_enable_dp() before/after it
+* calls into this function.  Also intel_mst_pre_enable_dp() only calls
+* us when active_mst_links==0, so any steps designated for "single
+* stream or multi-stream master transcoder" can just be performed
+* unconditionally here.
+*/
+
+   /*
+* 7a. Configure Transcoder Clock Select to direct the Port clock to the
+* Transcoder.
 */
intel_ddi_enable_pipe_clock(crtc_state);

-   /* 7.b */
+   /*
+* 7b. Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
+* Transport Select
+*/
intel_ddi_config_transcoder_func(crtc_state);

-   /* 7.d */
+   /*
+* 7c. Configure & enable DP_TP_CTL with link training pattern 1
+* selected
+*
+* This will be handled by the intel_dp_start_link_train() farther
+* down this function.
+*/
+
+   /*
+* 7d. Type C with DP alternate or fixed/legacy/static connection -
+* Disable PHY clock gating per Type-C DDI Buffer page
+*/
icl_phy_set_clock_gating(dig_port, false);

-   /* 7.e */
+   /* 7e. Configure voltage swing and related IO settings */
tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
encoder->type);

-   /* 7.f */
+   /*
+* 7f. Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
+* the used lanes of the DDI.
+*/
if (intel_phy_is_combo(dev_priv, phy)) {
bool lane_reversal =
dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
@@ -3489,7 +3527,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder 
*en

[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev10)

[Patchwork]

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev10)
URL   : https://patchwork.freedesktop.org/series/68028/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15178


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/index.html

Known issues


  Here are the changes found in Patchwork_15178 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_gem_contexts:
- fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] ([fdo# 111542])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html

  * igt@i915_selftest@live_hangcheck:
- fi-icl-y:   [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / 
[fdo#108569])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-y/igt@i915_selftest@live_hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-icl-y/igt@i915_selftest@live_hangcheck.html

  
 Possible fixes 

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][5] ([fdo#104108]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
 Warnings 

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][7] ([fdo#111407]) -> [FAIL][8] ([fdo#111045] / 
[fdo#111096])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (51 -> 45)
--

  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15178

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15178: 1fca0e7b861dfd3f3fe14940f5b29e9922c9d87d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1fca0e7b861d drm/i915: Restrict qgv points which don't have enough bandwidth.
a731ea6228dd drm/i915: Refactor intel_can_enable_sagv

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/index.html
___
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Switch obj->mm.lock lockdep annotations on its head

[Tang, CQ]

> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -22,6 +22,8 @@
>   *
>   */
> 
> +#include 
> +
>  #include "display/intel_frontbuffer.h"
>  #include "gt/intel_gt.h"
>  #include "i915_drv.h"
> @@ -52,6 +54,14 @@ void i915_gem_object_init(struct
> drm_i915_gem_object *obj,  {
>   __mutex_init(&obj->mm.lock, "obj->mm.lock", key);
> 
> + if (IS_ENABLED(CONFIG_LOCKDEP)) {
> + mutex_lock_nested(&obj->mm.lock,
> I915_MM_GET_PAGES);
> + fs_reclaim_acquire(GFP_KERNEL);
> + might_lock(&obj->mm.lock);
> + fs_reclaim_release(GFP_KERNEL);
> + mutex_unlock(&obj->mm.lock);
> + }
> +

I looked the upstream code in drm-tip,   I see other changes but not above.  Is 
this correct?

--CQ


>   spin_lock_init(&obj->vma.lock);
>   INIT_LIST_HEAD(&obj->vma.list);
> 
> @@ -186,7 +196,7 @@ static void __i915_gem_free_objects(struct
> drm_i915_private *i915,
>   GEM_BUG_ON(!list_empty(&obj->lut_list));
> 
>   atomic_set(&obj->mm.pages_pin_count, 0);
> - __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
> + __i915_gem_object_put_pages(obj);
>   GEM_BUG_ON(i915_gem_object_has_pages(obj));
>   bitmap_free(obj->bit_17);
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index 458cd51331f1..edaf7126a84d 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> @@ -319,11 +319,22 @@ i915_gem_object_unpin_pages(struct
> drm_i915_gem_object *obj)
> 
>  enum i915_mm_subclass { /* lockdep subclass for obj-
> >mm.lock/struct_mutex */
>   I915_MM_NORMAL = 0,
> - I915_MM_SHRINKER /* called "recursively" from direct-reclaim-
> esque */
> + /*
> +  * Only used by struct_mutex, when called "recursively" from
> +  * direct-reclaim-esque. Safe because there is only every one
> +  * struct_mutex in the entire system.
> +  */
> + I915_MM_SHRINKER = 1,
> + /*
> +  * Used for obj->mm.lock when allocating pages. Safe because the
> object
> +  * isn't yet on any LRU, and therefore the shrinker can't deadlock on
> +  * it. As soon as the object has pages, obj->mm.lock nests within
> +  * fs_reclaim.
> +  */
> + I915_MM_GET_PAGES = 1,
>  };
> 
> -int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> - enum i915_mm_subclass subclass);
> +int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
>  void i915_gem_object_truncate(struct drm_i915_gem_object *obj);  void
> i915_gem_object_writeback(struct drm_i915_gem_object *obj);
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 96008374a412..15f8297dc34e 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -162,7 +162,11 @@ struct drm_i915_gem_object {
>   atomic_t bind_count;
> 
>   struct {
> - struct mutex lock; /* protects the pages and their use */
> + /*
> +  * Protects the pages and their use. Do not use directly, but
> +  * instead go through the pin/unpin interfaces.
> +  */
> + struct mutex lock;
>   atomic_t pages_pin_count;
>   atomic_t shrink_pin;
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> index 29f4c2850745..f402c2c415c2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -106,7 +106,7 @@ int __i915_gem_object_get_pages(struct
> drm_i915_gem_object *obj)  {
>   int err;
> 
> - err = mutex_lock_interruptible(&obj->mm.lock);
> + err = mutex_lock_interruptible_nested(&obj->mm.lock,
> +I915_MM_GET_PAGES);
>   if (err)
>   return err;
> 
> @@ -190,8 +190,7 @@ __i915_gem_object_unset_pages(struct
> drm_i915_gem_object *obj)
>   return pages;
>  }
> 
> -int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
> - enum i915_mm_subclass subclass)
> +int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
>  {
>   struct sg_table *pages;
>   int err;
> @@ -202,7 +201,7 @@ int __i915_gem_object_put_pages(struct
> drm_i915_gem_object *obj,
>   GEM_BUG_ON(atomic_read(&obj->bind_count));
> 
>   /* May be called by shrinker from within get_pages() (on another bo)
> */
> - mutex_lock_nested(&obj->mm.lock, subclass);
> + mutex_lock(&obj->mm.lock);
>   if (unlikely(atomic_read(&obj->mm.pages_pin_count))) {
>   err = -EBUSY;
>   goto unlock;
> @@ -308,7 +307,7 @@ void *i915_gem_object_pin_map(struct
> drm_i915_gem_object *obj,
>   if (!i915_gem_object_type_has(obj, flags))
> 

Re: [Intel-gfx] [PATCH] drm/i915/gem: Safely acquire the ctx->vm when copying

[Niranjan Vishwanathapura]

On Thu, Nov 07, 2019 at 05:01:14PM +, Chris Wilson wrote:

Quoting Niranjan Vishwanathapura (2019-11-07 16:09:31)

On Wed, Nov 06, 2019 at 09:13:12AM +, Chris Wilson wrote:
>As we read the ctx->vm unlocked before cloning/exporting, we should
>validate our reference is correct before returning it. We already do for
>clone_vm() but were not so strict around get_ppgtt().
>
>Signed-off-by: Chris Wilson 
>---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 80 +++--
> 1 file changed, 43 insertions(+), 37 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>index de6e55af82cf..a06cc8e63281 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>@@ -995,6 +995,38 @@ static int context_barrier_task(struct i915_gem_context 
*ctx,
>   return err;
> }
>
>+static struct i915_address_space *
>+context_get_vm_rcu(struct i915_gem_context *ctx)
>+{
>+  do {
>+  struct i915_address_space *vm;
>+
>+  vm = rcu_dereference(ctx->vm);
>+  if (!kref_get_unless_zero(&vm->ref))
>+  continue;

But should we check for NULL vm?
I know the callers are ensuring ctx->vm will not be NULL, but just wondering.


We don't need to as the rule is that ctx->vm once set can never be
unset; and it can only be set during construction based on the HW
properties. The idea is that !!ctx->vm is an invariant indicating
whether or not we have full-ppgtt enabled. From a security perspective,
allowing a downgrade from full-ppgtt to a shared global gtt is a big no,
so I don't anticipating us allowing setting ctx->vm to NULL anytime in
the near future :)


OK, sounds right.




>+
>+  /*
>+   * This ppgtt may have be reallocated between
>+   * the read and the kref, and reassigned to a third
>+   * context. In order to avoid inadvertent sharing
>+   * of this ppgtt with that third context (and not
>+   * src), we have to confirm that we have the same
>+   * ppgtt after passing through the strong memory
>+   * barrier implied by a successful
>+   * kref_get_unless_zero().
>+   *
>+   * Once we have acquired the current ppgtt of src,
>+   * we no longer care if it is released from src, as
>+   * it cannot be reallocated elsewhere.
>+   */

Comment should be made generic? It is too specific to cloning case.


s/src/ctx/
-Chris

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev10)

[Patchwork]

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev10)
URL   : https://patchwork.freedesktop.org/series/68028/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0

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Re: [Intel-gfx] [PATCH V11 4/6] mdev: introduce virtio device and its device ops

[Kirti Wankhede]

On 11/7/2019 8:41 PM, Jason Wang wrote:

This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.

Reviewed-by: Cornelia Huck 
Signed-off-by: Jason Wang 


I'm not expert on virtio part, my ack is from mdev perspective.

Reviewed-by: Kirti Wankhede 

Thanks,
Kirti


---
  MAINTAINERS  |   1 +
  drivers/vfio/mdev/mdev_core.c|  21 +
  drivers/vfio/mdev/mdev_private.h |   2 +
  include/linux/mdev.h |   6 ++
  include/linux/mdev_virtio_ops.h  | 147 +++
  5 files changed, 177 insertions(+)
  create mode 100644 include/linux/mdev_virtio_ops.h

diff --git a/MAINTAINERS b/MAINTAINERS
index f661d13344d6..4997957443df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17248,6 +17248,7 @@ F:  include/linux/virtio*.h
  F:include/uapi/linux/virtio_*.h
  F:drivers/crypto/virtio/
  F:mm/balloon_compaction.c
+F: include/linux/mdev_virtio_ops.h
  
  VIRTIO BLOCK AND SCSI DRIVERS

  M:"Michael S. Tsirkin" 
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index 4e70f19ac145..c58253404ed5 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -78,6 +78,27 @@ const struct mdev_vfio_device_ops *mdev_get_vfio_ops(struct 
mdev_device *mdev)
  }
  EXPORT_SYMBOL(mdev_get_vfio_ops);
  
+/*

+ * Specify the virtio device ops for the mdev device, this
+ * must be called during create() callback for virtio mdev device.
+ */
+void mdev_set_virtio_ops(struct mdev_device *mdev,
+const struct mdev_virtio_device_ops *virtio_ops)
+{
+   mdev_set_class(mdev, MDEV_CLASS_ID_VIRTIO);
+   mdev->virtio_ops = virtio_ops;
+}
+EXPORT_SYMBOL(mdev_set_virtio_ops);
+
+/* Get the virtio device ops for the mdev device. */
+const struct mdev_virtio_device_ops *
+mdev_get_virtio_ops(struct mdev_device *mdev)
+{
+   WARN_ON(mdev->class_id != MDEV_CLASS_ID_VIRTIO);
+   return mdev->virtio_ops;
+}
+EXPORT_SYMBOL(mdev_get_virtio_ops);
+
  struct device *mdev_dev(struct mdev_device *mdev)
  {
return &mdev->dev;
diff --git a/drivers/vfio/mdev/mdev_private.h b/drivers/vfio/mdev/mdev_private.h
index 411227373625..2c74dd032409 100644
--- a/drivers/vfio/mdev/mdev_private.h
+++ b/drivers/vfio/mdev/mdev_private.h
@@ -11,6 +11,7 @@
  #define MDEV_PRIVATE_H
  
  #include 

+#include 
  
  int  mdev_bus_register(void);

  void mdev_bus_unregister(void);
@@ -38,6 +39,7 @@ struct mdev_device {
u16 class_id;
union {
const struct mdev_vfio_device_ops *vfio_ops;
+   const struct mdev_virtio_device_ops *virtio_ops;
};
  };
  
diff --git a/include/linux/mdev.h b/include/linux/mdev.h

index 9e37506d1987..f3d75a60c2b5 100644
--- a/include/linux/mdev.h
+++ b/include/linux/mdev.h
@@ -17,6 +17,7 @@
  
  struct mdev_device;

  struct mdev_vfio_device_ops;
+struct mdev_virtio_device_ops;
  
  /*

   * Called by the parent device driver to set the device which represents
@@ -112,6 +113,10 @@ void mdev_set_class(struct mdev_device *mdev, u16 id);
  void mdev_set_vfio_ops(struct mdev_device *mdev,
   const struct mdev_vfio_device_ops *vfio_ops);
  const struct mdev_vfio_device_ops *mdev_get_vfio_ops(struct mdev_device 
*mdev);
+void mdev_set_virtio_ops(struct mdev_device *mdev,
+const struct mdev_virtio_device_ops *virtio_ops);
+const struct mdev_virtio_device_ops *
+mdev_get_virtio_ops(struct mdev_device *mdev);
  
  extern struct bus_type mdev_bus_type;
  
@@ -127,6 +132,7 @@ struct mdev_device *mdev_from_dev(struct device *dev);
  
  enum {

MDEV_CLASS_ID_VFIO = 1,
+   MDEV_CLASS_ID_VIRTIO = 2,
/* New entries must be added here */
  };
  
diff --git a/include/linux/mdev_virtio_ops.h b/include/linux/mdev_virtio_ops.h

new file mode 100644
index ..8951331c6629
--- /dev/null
+++ b/include/linux/mdev_virtio_ops.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Virtio mediated device driver
+ *
+ * Copyright 2019, Red Hat Corp.
+ * Author: Jason Wang 
+ */
+#ifndef MDEV_VIRTIO_OPS_H
+#define MDEV_VIRTIO_OPS_H
+
+#include 
+#include 
+#include 
+
+#define VIRTIO_MDEV_DEVICE_API_STRING  "virtio-mdev"
+
+struct virtio_mdev_callback {
+   irqreturn_t (*callback)(void *data);
+   void *private;
+};
+
+/**
+ * struct mdev_virtio_device_ops - Structure to be registered for each
+ * mdev device to register the device for virtio/vhost drivers.
+ *
+ * The callbacks are mandatory unless explicitly mentioned.
+ *
+ * @set_vq_address:Set the address of virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @desc_area: address of desc area
+ * @driver_area: address of driver area
+ * @device_area: address of device area
+ *

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev10)

[Patchwork]

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev10)
URL   : https://patchwork.freedesktop.org/series/68028/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a731ea6228dd drm/i915: Refactor intel_can_enable_sagv
-:191: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#191: FILE: drivers/gpu/drm/i915/intel_pm.c:3835:
+   for_each_new_intel_crtc_in_state(state, crtc,
+new_crtc_state, i) {

-:271: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#271: FILE: drivers/gpu/drm/i915/intel_pm.c:3915:
+   bool state_sagv_masked = \

-:276: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#276: FILE: drivers/gpu/drm/i915/intel_pm.c:3920:
+   bool sagv_masked = \

-:311: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#311: FILE: drivers/gpu/drm/i915/intel_pm.c:4341:
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)

-:423: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#423: FILE: drivers/gpu/drm/i915/intel_pm.c:4991:
+   skl_compute_plane_wm(crtc_state, 0, latency,
+wm_params, &levels[0],

-:425: CHECK:BRACES: Unbalanced braces around else statement
#425: FILE: drivers/gpu/drm/i915/intel_pm.c:4993:
+   } else

-:427: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#427: FILE: drivers/gpu/drm/i915/intel_pm.c:4995:
+   memcpy(&plane_wm->sagv_wm0, &levels[0],
+   sizeof(struct skl_wm_level));

-:490: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#490: FILE: drivers/gpu/drm/i915/intel_pm.c:5681:
+   for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+   new_crtc_state, i) {

-:496: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#496: FILE: drivers/gpu/drm/i915/intel_pm.c:5687:
+   struct skl_plane_wm *plane_wm = \

-:519: WARNING:LINE_SPACING: Missing a blank line after declarations
#519: FILE: drivers/gpu/drm/i915/intel_pm.c:5710:
+   int pipe_bit = BIT(crtc->pipe);
+   state->crtc_sagv_mask |= pipe_bit;

total: 0 errors, 4 warnings, 6 checks, 454 lines checked
1fca0e7b861d drm/i915: Restrict qgv points which don't have enough bandwidth.
-:131: CHECK:LINE_SPACING: Please don't use multiple blank lines
#131: FILE: drivers/gpu/drm/i915/display/intel_bw.c:139:
+
+

-:237: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#237: FILE: drivers/gpu/drm/i915/display/intel_bw.c:484:
+   if (!intel_can_enable_sagv(state)) {
+

-:404: CHECK:BRACES: braces {} should be used on all arms of this statement
#404: FILE: drivers/gpu/drm/i915/display/intel_display.c:14963:
+   if (INTEL_GEN(dev_priv) < 11) {
[...]
+   } else
[...]

-:407: CHECK:BRACES: Unbalanced braces around else statement
#407: FILE: drivers/gpu/drm/i915/display/intel_display.c:14966:
+   } else

total: 0 errors, 0 warnings, 4 checks, 505 lines checked

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Gamma cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups
URL   : https://patchwork.freedesktop.org/series/69136/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15177


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_15177 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15177, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_15177:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live_execlists:
- fi-icl-dsi: [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-dsi/igt@i915_selftest@live_execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-icl-dsi/igt@i915_selftest@live_execlists.html

  
Known issues


  Here are the changes found in Patchwork_15177 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_gem_contexts:
- fi-bsw-nick:[PASS][3] -> [INCOMPLETE][4] ([fdo# 111542])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111736]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][7] ([fdo#111407]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][9] ([fdo#104108]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (51 -> 45)
--

  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15177

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15177: 4888c33ef45e557085500f6d3196da5c1ee23270 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4888c33ef45e drm/i915: Pass the crtc to the low level read_lut() funcs
631db3ed62b9 drm/i915: Fix readout of PIPEGCMAX
7cef77b47c3f drm/i915: Refactor LUT read functions
1d66b7bd3630 drm/i915: Clean up integer types in color code
1d633ad1816e drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
f7394645c856 drm/i915: s/blob_data/lut/
d5557fbd2bb6 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
0a500e1f5971 drm/i915: Clean up i9xx_load_luts_internal()
ce81f95570f1 drm/i915: Add i9xx_lut_8()
a30aa9a2a86a drm/i915: Polish CHV CGM CSC loading
1250c5426804 drm/i915: Polish CHV .load_luts() a bit
aab7b7b6ba2e drm: Inline drm_color_lut_extract()

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15177/index.html
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Re: [Intel-gfx] [PATCH V11 3/6] mdev: introduce device specific ops

[Kirti Wankhede]

On 11/7/2019 8:41 PM, Jason Wang wrote:

Currently, except for the create and remove, the rest of
mdev_parent_ops is designed for vfio-mdev driver only and may not help
for kernel mdev driver. With the help of class id, this patch
introduces device specific callbacks inside mdev_device
structure. This allows different set of callback to be used by
vfio-mdev and virtio-mdev.

Reviewed-by: Parav Pandit 
Signed-off-by: Jason Wang 



Reviewed-by: Kirti Wankhede 

Thanks,
Kirti


---
  .../driver-api/vfio-mediated-device.rst   | 35 +
  MAINTAINERS   |  1 +
  drivers/gpu/drm/i915/gvt/kvmgt.c  | 18 ---
  drivers/s390/cio/vfio_ccw_ops.c   | 18 ---
  drivers/s390/crypto/vfio_ap_ops.c | 14 +++--
  drivers/vfio/mdev/mdev_core.c | 24 -
  drivers/vfio/mdev/mdev_private.h  |  5 ++
  drivers/vfio/mdev/vfio_mdev.c | 37 ++---
  include/linux/mdev.h  | 43 ---
  include/linux/mdev_vfio_ops.h | 52 +++
  samples/vfio-mdev/mbochs.c| 20 ---
  samples/vfio-mdev/mdpy.c  | 20 ---
  samples/vfio-mdev/mtty.c  | 18 ---
  13 files changed, 206 insertions(+), 99 deletions(-)
  create mode 100644 include/linux/mdev_vfio_ops.h

diff --git a/Documentation/driver-api/vfio-mediated-device.rst 
b/Documentation/driver-api/vfio-mediated-device.rst
index 6709413bee29..04d56884c357 100644
--- a/Documentation/driver-api/vfio-mediated-device.rst
+++ b/Documentation/driver-api/vfio-mediated-device.rst
@@ -152,15 +152,6 @@ callbacks per mdev parent device, per mdev type, or any 
other categorization.
  Vendor drivers are expected to be fully asynchronous in this respect or
  provide their own internal resource protection.)
  
-The callbacks in the mdev_parent_ops structure are as follows:

-
-* open: open callback of mediated device
-* close: close callback of mediated device
-* ioctl: ioctl callback of mediated device
-* read : read emulation callback
-* write: write emulation callback
-* mmap: mmap emulation callback
-
  A driver should use the mdev_parent_ops structure in the function call to
  register itself with the mdev core driver::
  
@@ -172,10 +163,34 @@ that a driver should use to unregister itself with the mdev core driver::
  
  	extern void mdev_unregister_device(struct device *dev);
  
-It is also required to specify the class_id in create() callback through::

+As multiple types of mediated devices may be supported, class id needs
+to be specified in the create() callback. This could be done
+explicitly for the device that interacts with the mdev device directly
+through::
  
  	int mdev_set_class(struct mdev_device *mdev, u16 id);
  
+For the device that uses the mdev bus for its operation, the class

+should provide helper function to set class id and device specific
+ops. E.g for vfio-mdev devices, the function to be called is::
+
+   int mdev_set_vfio_ops(struct mdev_device *mdev,
+  const struct mdev_vfio_device_ops *vfio_ops);
+
+The class id (set by this function to MDEV_CLASS_ID_VFIO) is used to
+match a device with an mdev driver via its id table. The device
+specific callbacks (specified in *vfio_ops) are obtainable via
+mdev_get_vfio_ops() (for use by the mdev bus driver). A vfio-mdev
+device (class id MDEV_CLASS_ID_VFIO) uses the following
+device-specific ops:
+
+* open: open callback of vfio mediated device
+* close: close callback of vfio mediated device
+* ioctl: ioctl callback of vfio mediated device
+* read : read emulation callback
+* write: write emulation callback
+* mmap: mmap emulation callback
+
  Mediated Device Management Interface Through sysfs
  ==
  
diff --git a/MAINTAINERS b/MAINTAINERS

index cba1095547fd..f661d13344d6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17121,6 +17121,7 @@ S:  Maintained
  F:Documentation/driver-api/vfio-mediated-device.rst
  F:drivers/vfio/mdev/
  F:include/linux/mdev.h
+F: include/linux/mdev_vfio_ops.h
  F:samples/vfio-mdev/
  
  VFIO PLATFORM DRIVER

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 6420f0dbd31b..662f3a672372 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -42,6 +42,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  
  #include 

@@ -643,6 +644,8 @@ static void kvmgt_put_vfio_device(void *vgpu)
vfio_device_put(((struct intel_vgpu *)vgpu)->vdev.vfio_device);
  }
  
+static const struct mdev_vfio_device_ops intel_vfio_vgpu_dev_ops;

+
  static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
  {
struct intel_vgpu *vgpu = NULL;
@@ -678,7 +681,7 @@ static int intel_vgpu_create(struct kobject *kobj, struct 
mdev_device *mdev)
  

Re: [Intel-gfx] [PATCH V11 2/6] modpost: add support for mdev class id

[Kirti Wankhede]

On 11/7/2019 8:41 PM, Jason Wang wrote:

Add support to parse mdev class id table.

Reviewed-by: Parav Pandit 
Reviewed-by: Cornelia Huck 
Signed-off-by: Jason Wang 


Reviewed-by: Kirti Wankhede 

Thanks,
Kirti


---
  drivers/vfio/mdev/vfio_mdev.c |  2 ++
  scripts/mod/devicetable-offsets.c |  3 +++
  scripts/mod/file2alias.c  | 11 +++
  3 files changed, 16 insertions(+)

diff --git a/drivers/vfio/mdev/vfio_mdev.c b/drivers/vfio/mdev/vfio_mdev.c
index 38431e9ef7f5..a6641cd8b5a3 100644
--- a/drivers/vfio/mdev/vfio_mdev.c
+++ b/drivers/vfio/mdev/vfio_mdev.c
@@ -125,6 +125,8 @@ static const struct mdev_class_id vfio_id_table[] = {
{ 0 },
  };
  
+MODULE_DEVICE_TABLE(mdev, vfio_id_table);

+
  static struct mdev_driver vfio_mdev_driver = {
.name   = "vfio_mdev",
.probe  = vfio_mdev_probe,
diff --git a/scripts/mod/devicetable-offsets.c 
b/scripts/mod/devicetable-offsets.c
index 054405b90ba4..6cbb1062488a 100644
--- a/scripts/mod/devicetable-offsets.c
+++ b/scripts/mod/devicetable-offsets.c
@@ -231,5 +231,8 @@ int main(void)
DEVID(wmi_device_id);
DEVID_FIELD(wmi_device_id, guid_string);
  
+	DEVID(mdev_class_id);

+   DEVID_FIELD(mdev_class_id, id);
+
return 0;
  }
diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index c91eba751804..45f1c22f49be 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -1335,6 +1335,16 @@ static int do_wmi_entry(const char *filename, void 
*symval, char *alias)
return 1;
  }
  
+/* looks like: "mdev:cN" */

+static int do_mdev_entry(const char *filename, void *symval, char *alias)
+{
+   DEF_FIELD(symval, mdev_class_id, id);
+
+   sprintf(alias, "mdev:c%02X", id);
+   add_wildcard(alias);
+   return 1;
+}
+
  /* Does namelen bytes of name exactly match the symbol? */
  static bool sym_is(const char *name, unsigned namelen, const char *symbol)
  {
@@ -1407,6 +1417,7 @@ static const struct devtable devtable[] = {
{"typec", SIZE_typec_device_id, do_typec_entry},
{"tee", SIZE_tee_client_device_id, do_tee_entry},
{"wmi", SIZE_wmi_device_id, do_wmi_entry},
+   {"mdev", SIZE_mdev_class_id, do_mdev_entry},
  };
  
  /* Create MODULE_ALIAS() statements.



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Re: [Intel-gfx] [PATCH V11 1/6] mdev: class id support

[Kirti Wankhede]

On 11/7/2019 8:41 PM, Jason Wang wrote:

Mdev bus only supports vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
the first driver could be virtio-mdev. This means we need to add
device class id support in bus match method to pair the mdev device
and mdev driver correctly.

So this patch adds id_table to mdev_driver and class_id for mdev
device with the match method for mdev bus.

Reviewed-by: Parav Pandit 
Reviewed-by: Cornelia Huck 
Signed-off-by: Jason Wang 


Reviewed-by: Kirti Wankhede 

Thanks,
Kirti


---
  .../driver-api/vfio-mediated-device.rst   |  5 
  drivers/gpu/drm/i915/gvt/kvmgt.c  |  1 +
  drivers/s390/cio/vfio_ccw_ops.c   |  1 +
  drivers/s390/crypto/vfio_ap_ops.c |  1 +
  drivers/vfio/mdev/mdev_core.c | 17 +
  drivers/vfio/mdev/mdev_driver.c   | 25 +++
  drivers/vfio/mdev/mdev_private.h  |  1 +
  drivers/vfio/mdev/vfio_mdev.c |  6 +
  include/linux/mdev.h  |  8 ++
  include/linux/mod_devicetable.h   |  8 ++
  samples/vfio-mdev/mbochs.c|  1 +
  samples/vfio-mdev/mdpy.c  |  1 +
  samples/vfio-mdev/mtty.c  |  1 +
  13 files changed, 76 insertions(+)

diff --git a/Documentation/driver-api/vfio-mediated-device.rst 
b/Documentation/driver-api/vfio-mediated-device.rst
index 25eb7d5b834b..6709413bee29 100644
--- a/Documentation/driver-api/vfio-mediated-device.rst
+++ b/Documentation/driver-api/vfio-mediated-device.rst
@@ -102,12 +102,14 @@ structure to represent a mediated device's driver::
* @probe: called when new device created
* @remove: called when device removed
* @driver: device driver structure
+  * @id_table: the ids serviced by this driver
*/
   struct mdev_driver {
 const char *name;
 int  (*probe)  (struct device *dev);
 void (*remove) (struct device *dev);
 struct device_driverdriver;
+const struct mdev_class_id *id_table;
   };
  
  A mediated bus driver for mdev should use this structure in the function calls

@@ -170,6 +172,9 @@ that a driver should use to unregister itself with the mdev 
core driver::
  
  	extern void mdev_unregister_device(struct device *dev);
  
+It is also required to specify the class_id in create() callback through::

+
+   int mdev_set_class(struct mdev_device *mdev, u16 id);
  
  Mediated Device Management Interface Through sysfs

  ==
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 343d79c1cb7e..6420f0dbd31b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -678,6 +678,7 @@ static int intel_vgpu_create(struct kobject *kobj, struct 
mdev_device *mdev)
 dev_name(mdev_dev(mdev)));
ret = 0;
  
+	mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);

  out:
return ret;
  }
diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
index f0d71ab77c50..cf2c013ae32f 100644
--- a/drivers/s390/cio/vfio_ccw_ops.c
+++ b/drivers/s390/cio/vfio_ccw_ops.c
@@ -129,6 +129,7 @@ static int vfio_ccw_mdev_create(struct kobject *kobj, 
struct mdev_device *mdev)
   private->sch->schid.ssid,
   private->sch->schid.sch_no);
  
+	mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);

return 0;
  }
  
diff --git a/drivers/s390/crypto/vfio_ap_ops.c b/drivers/s390/crypto/vfio_ap_ops.c

index 5c0f53c6dde7..07c31070afeb 100644
--- a/drivers/s390/crypto/vfio_ap_ops.c
+++ b/drivers/s390/crypto/vfio_ap_ops.c
@@ -343,6 +343,7 @@ static int vfio_ap_mdev_create(struct kobject *kobj, struct 
mdev_device *mdev)
list_add(&matrix_mdev->node, &matrix_dev->mdev_list);
mutex_unlock(&matrix_dev->lock);
  
+	mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);

return 0;
  }
  
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c

index b558d4cfd082..7bfa2e46e829 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -45,6 +45,17 @@ void mdev_set_drvdata(struct mdev_device *mdev, void *data)
  }
  EXPORT_SYMBOL(mdev_set_drvdata);
  
+/*

+ * Specify the class for the mdev device, this must be called during
+ * create() callback.
+ */
+void mdev_set_class(struct mdev_device *mdev, u16 id)
+{
+   WARN_ON(mdev->class_id);
+   mdev->class_id = id;
+}
+EXPORT_SYMBOL(mdev_set_class);
+
  struct device *mdev_dev(struct mdev_device *mdev)
  {
return &mdev->dev;
@@ -324,6 +335,12 @@ int mdev_device_create(struct kobject *kobj,
if (ret)
goto ops_create_fail;
  
+	if (!mdev->class_id) {

+   ret = -EINVAL;
+   dev_warn(dev, "mdev vendor driver failed to specify device 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Gamma cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm: Inline drm_color_lut_extract()
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)
+./include/drm/drm_color_mgmt.h:48:28: warning: shift count is negative (-1)

Commit: drm/i915: Polish CHV .load_luts() a bit
Okay!

Commit: drm/i915: Polish CHV CGM CSC loading
Okay!

Commit: drm/i915: Add i9xx_lut_8()
Okay!

Commit: drm/i915: Clean up i9xx_load_luts_internal()
Okay!

Commit: drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
Okay!

Commit: drm/i915: s/blob_data/lut/
Okay!

Commit: drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
Okay!

Commit: drm/i915: Clean up integer types in color code
Okay!

Commit: drm/i915: Refactor LUT read functions
Okay!

Commit: drm/i915: Fix readout of PIPEGCMAX
Okay!

Commit: drm/i915: Pass the crtc to the low level read_lut() funcs
Okay!

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: Gamma cleanups
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
aab7b7b6ba2e drm: Inline drm_color_lut_extract()
1250c5426804 drm/i915: Polish CHV .load_luts() a bit
a30aa9a2a86a drm/i915: Polish CHV CGM CSC loading
ce81f95570f1 drm/i915: Add i9xx_lut_8()
0a500e1f5971 drm/i915: Clean up i9xx_load_luts_internal()
d5557fbd2bb6 drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+   blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+   blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:60: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#60: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+   blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 65 lines checked
f7394645c856 drm/i915: s/blob_data/lut/
-:39: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#39: FILE: drivers/gpu/drm/i915/display/intel_color.c:1679:
+   lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:42: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#42: FILE: drivers/gpu/drm/i915/display/intel_color.c:1681:
+   lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:45: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#45: FILE: drivers/gpu/drm/i915/display/intel_color.c:1683:
+   lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/display/intel_color.c:1730:
+   lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 I915_READ(PIPEGCMAX(pipe, 0)));

-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/display/intel_color.c:1732:
+   lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
   I915_READ(PIPEGCMAX(pipe, 1)));

-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/display/intel_color.c:1734:
+   lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
  I915_READ(PIPEGCMAX(pipe, 2)));

-:110: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#110: FILE: drivers/gpu/drm/i915/display/intel_color.c:1771:
+   lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:113: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#113: FILE: drivers/gpu/drm/i915/display/intel_color.c:1773:
+   lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:118: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#118: FILE: drivers/gpu/drm/i915/display/intel_color.c:1777:
+   lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:142: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#142: FILE: drivers/gpu/drm/i915/display/intel_color.c:1813:
+   lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:145: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#145: FILE: drivers/gpu/drm/i915/display/intel_color.c:1815:
+   lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:148: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#148: FILE: drivers/gpu/drm/i915/display/intel_color.c:1817:
+   lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:172: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#172: FILE: drivers/gpu/drm/i915/display/intel_color.c:1846:
+   lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:175: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#175: FILE: drivers/gpu/drm/i915/display/intel_color.c:1848:
+   lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:178: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#178: FILE: drivers/gpu/drm/i915/display/intel_color.c:1850:
+   lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:205: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#205: FILE: drivers/gpu/drm/i915/display/intel_color.c:1896:
+   lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:208: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#208: FILE: drivers/gpu/drm/i915/display/intel_color.c:1898:
+   lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:211: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#211: FILE: drivers/gpu/drm/i915/display/intel_color.c:1900:
+   lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 18 checks, 183 lines checked
1d633ad1816e drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
1d66b7bd3630 drm/i915: Clean up integer types in color code
7c

[Intel-gfx] ✓ Fi.CI.BAT: success for mdev based hardware virtio offloading support

[Patchwork]

== Series Details ==

Series: mdev based hardware virtio offloading support
URL   : https://patchwork.freedesktop.org/series/69135/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15176


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15176/index.html

Known issues


  Here are the changes found in Patchwork_15176 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_gem_contexts:
- fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] ([fdo# 111542])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15176/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2:  [PASS][3] -> [FAIL][4] ([fdo#103167])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15176/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111736]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15176/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][7] ([fdo#111407]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15176/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][9] ([fdo#104108]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15176/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (51 -> 45)
--

  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15176

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15176: 202515ad0a81fdea73f83fb083c14d4ef44c4684 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

202515ad0a81 docs: sample driver to demonstrate how to implement virtio-mdev 
framework
9f42a0ac8dab virtio: introduce a mdev based transport
1643d29b8cd6 mdev: introduce virtio device and its device ops
e94f948040f5 mdev: introduce device specific ops
58af09c8da00 modpost: add support for mdev class id
9507b5357d7b mdev: class id support

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15176/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mdev based hardware virtio offloading support

[Patchwork]

== Series Details ==

Series: mdev based hardware virtio offloading support
URL   : https://patchwork.freedesktop.org/series/69135/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9507b5357d7b mdev: class id support
58af09c8da00 modpost: add support for mdev class id
e94f948040f5 mdev: introduce device specific ops
-:500: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#500: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 618 lines checked
1643d29b8cd6 mdev: introduce virtio device and its device ops
-:108: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#108: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 219 lines checked
9f42a0ac8dab virtio: introduce a mdev based transport
-:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#53: 
new file mode 100644

-:113: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#113: FILE: drivers/virtio/virtio_mdev.c:56:
+static void virtio_mdev_get(struct virtio_device *vdev, unsigned offset,

-:114: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#114: FILE: drivers/virtio/virtio_mdev.c:57:
+   void *buf, unsigned len)

-:122: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#122: FILE: drivers/virtio/virtio_mdev.c:65:
+static void virtio_mdev_set(struct virtio_device *vdev, unsigned offset,

-:123: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#123: FILE: drivers/virtio/virtio_mdev.c:66:
+   const void *buf, unsigned len)

-:303: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#303: FILE: drivers/virtio/virtio_mdev.c:246:
+static int virtio_mdev_find_vqs(struct virtio_device *vdev, unsigned nvqs,

total: 0 errors, 6 warnings, 0 checks, 429 lines checked
202515ad0a81 docs: sample driver to demonstrate how to implement virtio-mdev 
framework
-:63: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#63: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 714 lines checked

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm: Add __drm_atomic_helper_crtc_state_reset() & co.

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm: Add 
__drm_atomic_helper_crtc_state_reset() & co.
URL   : https://patchwork.freedesktop.org/series/69129/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15175


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_15175 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15175, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15175/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_15175:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@reload-with-fault-injection:
- fi-bsw-kefka:   [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15175/fi-bsw-kefka/igt@i915_module_l...@reload-with-fault-injection.html

  
Known issues


  Here are the changes found in Patchwork_15175 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111736]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15175/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][5] ([fdo#111407]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15175/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][7] ([fdo#104108]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15175/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (51 -> 45)
--

  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15175

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15175: fc9cd4c16f83a4dfad81c650ca2be9a83caf115c @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

fc9cd4c16f83 drm/i915: Introduce intel_plane_state_reset()
f77f1d0feca7 drm/i915: Introduce intel_crtc_state_reset()
1af8c56f280e drm/i915: Introduce intel_crtc_{alloc, free}()
9e996834eca6 drm/i915: s/intel_crtc/crtc/ in intel_crtc_init()
b00efdb4f412 drm: Add __drm_atomic_helper_crtc_state_reset() & co.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15175/index.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable second dbuf slice for ICL and TGL

[Patchwork]

== Series Details ==

Series: drm/i915: Enable second dbuf slice for ICL and TGL
URL   : https://patchwork.freedesktop.org/series/69124/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15174


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_15174 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15174, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_15174:

### IGT changes ###

 Possible regressions 

  * igt@kms_busy@basic-flip-c:
- fi-icl-dsi: [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-dsi/igt@kms_b...@basic-flip-c.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/fi-icl-dsi/igt@kms_b...@basic-flip-c.html
- fi-icl-u4:  [PASS][3] -> [DMESG-WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-u4/igt@kms_b...@basic-flip-c.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/fi-icl-u4/igt@kms_b...@basic-flip-c.html
- fi-icl-u3:  [PASS][5] -> [DMESG-WARN][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-u3/igt@kms_b...@basic-flip-c.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/fi-icl-u3/igt@kms_b...@basic-flip-c.html
- fi-icl-guc: [PASS][7] -> [DMESG-WARN][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-guc/igt@kms_b...@basic-flip-c.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/fi-icl-guc/igt@kms_b...@basic-flip-c.html
- fi-icl-u2:  [PASS][9] -> [DMESG-WARN][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-u2/igt@kms_b...@basic-flip-c.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/fi-icl-u2/igt@kms_b...@basic-flip-c.html

  
Known issues


  Here are the changes found in Patchwork_15174 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111736]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@gem_exec_suspend@basic-s3:
- fi-cml-s:   [DMESG-WARN][13] ([fdo#111764]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/fi-cml-s/igt@gem_exec_susp...@basic-s3.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [FAIL][15] ([fdo#111407]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2:  [INCOMPLETE][17] ([fdo#104108]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15174/fi-skl-6700k2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
  [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764


Participating hosts (51 -> 44)
--

  Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-icl-y fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7288 -> Patchwork_15174

  CI-20190529: 20190529
  CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15174: 2fdfc3b51c5b0bcac8efab38bf28704298f6e9f7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2fdfc3b51c5b drm/i915: Enable second dbuf slice for ICL and TGL

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15

[Intel-gfx] [CI 3/5] drm/i915/selftests: Replace mock_file hackery with drm's true fake

[Chris Wilson]

As drm now exports a method to create an anonymous struct file around a
drm_device for internal use, make use of it to avoid our horrible hacks.

Danial suggested that the mock_file_put() wrapper was suitable for
drm-core, along with the mock_drm_getfile() [and that the vestigal
mock_drm_file() in this patch should perhaps be the drm interface
itself]. However, the eventual goal is to remove the mock_drm_file() and
use the struct file and fput() directly, in this patch we take a simple
transition in that direction.

Signed-off-by: Chris Wilson 
Reviewed-by: Matthew Auld 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/Kconfig.debug|  2 +
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  2 +-
 .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++---
 .../i915/gem/selftests/i915_gem_object_blt.c  |  4 +-
 drivers/gpu/drm/i915/gt/selftest_context.c|  4 +-
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |  8 +--
 .../gpu/drm/i915/gt/selftest_workarounds.c|  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem.c |  4 +-
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
 drivers/gpu/drm/i915/selftests/i915_request.c |  2 +-
 .../drm/i915/selftests/intel_memory_region.c  |  2 +-
 drivers/gpu/drm/i915/selftests/mock_drm.c | 49 +++
 drivers/gpu/drm/i915/selftests/mock_drm.h |  8 ++-
 14 files changed, 39 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
b/drivers/gpu/drm/i915/Kconfig.debug
index ef123eb29168..1140525da75a 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -37,6 +37,7 @@ config DRM_I915_DEBUG
select X86_MSR # used by igt/pm_rpm
select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
select DRM_DEBUG_MM if DRM=y
+   select DRM_EXPORT_FOR_TESTS if m
select DRM_DEBUG_SELFTEST
select DMABUF_SELFTESTS
select SW_SYNC # signaling validation framework (igt/syncobj*)
@@ -160,6 +161,7 @@ config DRM_I915_SELFTEST
bool "Enable selftests upon driver load"
depends on DRM_I915
default n
+   select DRM_EXPORT_FOR_TESTS if m
select FAULT_INJECTION
select PRIME_NUMBERS
help
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 5c9583349077..2310ed9b8f89 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1944,6 +1944,6 @@ int i915_gem_huge_page_live_selftests(struct 
drm_i915_private *i915)
err = i915_subtests(tests, ctx);
 
 out_file:
-   mock_file_free(i915, file);
+   mock_file_put(file);
return err;
 }
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 62fabc023a83..47890c92534c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -149,7 +149,7 @@ static int live_nop_switch(void *arg)
}
 
 out_file:
-   mock_file_free(i915, file);
+   mock_file_put(file);
return err;
 }
 
@@ -377,7 +377,7 @@ static int live_parallel_switch(void *arg)
}
kfree(data);
 out_file:
-   mock_file_free(i915, file);
+   mock_file_put(file);
return err;
 }
 
@@ -716,7 +716,7 @@ static int igt_ctx_exec(void *arg)
if (igt_live_test_end(&t))
err = -EIO;
 
-   mock_file_free(i915, file);
+   mock_file_put(file);
if (err)
return err;
 
@@ -854,7 +854,7 @@ static int igt_shared_ctx_exec(void *arg)
if (igt_live_test_end(&t))
err = -EIO;
 out_file:
-   mock_file_free(i915, file);
+   mock_file_put(file);
return err;
 }
 
@@ -1426,7 +1426,7 @@ static int igt_ctx_readonly(void *arg)
if (igt_live_test_end(&t))
err = -EIO;
 
-   mock_file_free(i915, file);
+   mock_file_put(file);
return err;
 }
 
@@ -1750,7 +1750,7 @@ static int igt_vm_isolation(void *arg)
 out_file:
if (igt_live_test_end(&t))
err = -EIO;
-   mock_file_free(i915, file);
+   mock_file_put(file);
return err;
 }
 
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index e8132aca0bb6..d9fdfddb7091 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -301,7 +301,7 @@ static int igt_fill_blt_thread(void *arg)
 
intel_context_put(ce);
 out_file:
-   mock_file_free(i915, file);
+   mock_file_put(file);
return err;
 }
 
@@ -432,7 +432,7 @@ static int igt_copy_blt_thread(void *arg)
 
intel_context_put(ce);
 out_file:
-   mock_file_fre

[Intel-gfx] [CI 5/5] drm/i915/selftests: Verify mmap_gtt revocation on unbinding

[Chris Wilson]

Whenever, we unbind (or change fence registers) on an object, we must
revoke any and all mmap_gtt using the previous bindings. Those user PTEs
point at the GGTT which know points into a new object, the wrong object.
Ergo, those PTEs must be cleared so that any user access provokes a new
page fault.

Signed-off-by: Chris Wilson 
Cc: Abdiel Janulgue 
Reviewed-by: Abdiel Janulgue 
---
 .../drm/i915/gem/selftests/i915_gem_mman.c| 110 ++
 1 file changed, 110 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index d5ae491a0367..19060fdc83f6 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -793,6 +793,115 @@ static int igt_mmap_gtt(void *arg)
return err;
 }
 
+static int check_present_pte(pte_t *pte, unsigned long addr, void *data)
+{
+   if (!pte_present(*pte) || pte_none(*pte)) {
+   pr_err("missing PTE:%lx\n",
+  (addr - (unsigned long)data) >> PAGE_SHIFT);
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static int check_absent_pte(pte_t *pte, unsigned long addr, void *data)
+{
+   if (pte_present(*pte) && !pte_none(*pte)) {
+   pr_err("present PTE:%lx; expected to be revoked\n",
+  (addr - (unsigned long)data) >> PAGE_SHIFT);
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static int check_present(unsigned long addr, unsigned long len)
+{
+   return apply_to_page_range(current->mm, addr, len,
+  check_present_pte, (void *)addr);
+}
+
+static int check_absent(unsigned long addr, unsigned long len)
+{
+   return apply_to_page_range(current->mm, addr, len,
+  check_absent_pte, (void *)addr);
+}
+
+static int prefault_range(u64 start, u64 len)
+{
+   const char __user *addr, *end;
+   char __maybe_unused c;
+
+   addr = u64_to_user_ptr(start);
+   end = addr + len;
+
+   for (; addr < end; addr += PAGE_SIZE) {
+   int err = __get_user(c, addr);
+   if (err)
+   return err;
+   }
+
+   return __get_user(c, end - 1);
+}
+
+static int igt_mmap_gtt_revoke(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct drm_i915_gem_object *obj;
+   unsigned long addr;
+   int err;
+
+   if (!i915_ggtt_has_aperture(&i915->ggtt))
+   return 0;
+
+   obj = i915_gem_object_create_internal(i915, SZ_4M);
+   if (IS_ERR(obj))
+   return PTR_ERR(obj);
+
+   err = create_mmap_offset(obj);
+   if (err)
+   goto out;
+
+   addr = igt_mmap_node(i915, &obj->base.vma_node,
+0, PROT_WRITE, MAP_SHARED);
+   if (IS_ERR_VALUE(addr)) {
+   err = addr;
+   goto out;
+   }
+
+   err = prefault_range(addr, obj->base.size);
+   if (err)
+   goto out_unmap;
+
+   GEM_BUG_ON(!atomic_read(&obj->bind_count));
+
+   err = check_present(addr, obj->base.size);
+   if (err)
+   goto out_unmap;
+
+   /*
+* After unbinding the object from the GGTT, its address may be reused
+* for other objects. Ergo we have to revoke the previous mmap PTE
+* access as it no longer points to the same object.
+*/
+   err = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
+   if (err) {
+   pr_err("Failed to unbind object!\n");
+   goto out_unmap;
+   }
+   GEM_BUG_ON(atomic_read(&obj->bind_count));
+
+   err = check_absent(addr, obj->base.size);
+   if (err)
+   goto out_unmap;
+
+out_unmap:
+   vm_munmap(addr, obj->base.size);
+out:
+   i915_gem_object_put(obj);
+   return err;
+}
+
 int i915_gem_mman_live_selftests(struct drm_i915_private *i915)
 {
static const struct i915_subtest tests[] = {
@@ -800,6 +909,7 @@ int i915_gem_mman_live_selftests(struct drm_i915_private 
*i915)
SUBTEST(igt_smoke_tiling),
SUBTEST(igt_mmap_offset_exhaustion),
SUBTEST(igt_mmap_gtt),
+   SUBTEST(igt_mmap_gtt_revoke),
};
 
return i915_subtests(tests, i915);
-- 
2.24.0

___
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[Intel-gfx] [CI 1/5] drm: Move EXPORT_SYMBOL_FOR_TESTS_ONLY under a separate Kconfig

[Chris Wilson]

Currently, we only export symbols for drm-selftests which are either
compiled as modules or into the main drm builtin. However, if we want to
export symbols from drm.ko for the drivers' selftests, we require a
means of controlling that export separately. So we add a new Kconfig to
determine whether or not the EXPORT_SYMBOL_FOR_TESTS_ONLY() takes
effect.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/Kconfig | 4 
 include/drm/drm_util.h  | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 617d9c3a86c3..d3560afe34d3 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -54,6 +54,9 @@ config DRM_DEBUG_MM
 
  If in doubt, say "N".
 
+config DRM_EXPORT_FOR_TESTS
+   bool
+
 config DRM_DEBUG_SELFTEST
tristate "kselftests for DRM"
depends on DRM
@@ -61,6 +64,7 @@ config DRM_DEBUG_SELFTEST
select PRIME_NUMBERS
select DRM_LIB_RANDOM
select DRM_KMS_HELPER
+   select DRM_EXPORT_FOR_TESTS if m
default n
help
  This option provides kernel modules that can be used to run
diff --git a/include/drm/drm_util.h b/include/drm/drm_util.h
index 07b8e9f04599..79952d8c4bba 100644
--- a/include/drm/drm_util.h
+++ b/include/drm/drm_util.h
@@ -41,7 +41,7 @@
  * Use EXPORT_SYMBOL_FOR_TESTS_ONLY() for functions that shall
  * only be visible for drmselftests.
  */
-#if defined(CONFIG_DRM_DEBUG_SELFTEST_MODULE)
+#if defined(CONFIG_DRM_EXPORT_FOR_TESTS)
 #define EXPORT_SYMBOL_FOR_TESTS_ONLY(x) EXPORT_SYMBOL(x)
 #else
 #define EXPORT_SYMBOL_FOR_TESTS_ONLY(x)
-- 
2.24.0

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[Intel-gfx] [CI 4/5] drm/i915/selftests: Wrap vm_mmap() around GEM objects

[Chris Wilson]

Provide a utility function to create a vma corresponding to an mmap() of
our device. And use it to exercise the equivalent of userspace
performing a GTT mmap of our objects.

Signed-off-by: Chris Wilson 
Cc: Abdiel Janulgue 
Reviewed-by: Abdiel Janulgue 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 .../drm/i915/gem/selftests/i915_gem_mman.c| 100 ++
 drivers/gpu/drm/i915/selftests/igt_mmap.c |  39 +++
 drivers/gpu/drm/i915/selftests/igt_mmap.h |  19 
 4 files changed, 159 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/selftests/igt_mmap.c
 create mode 100644 drivers/gpu/drm/i915/selftests/igt_mmap.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 90dcf09f52cc..e0fd10c0cfb8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -259,6 +259,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/i915_selftest.o \
selftests/igt_flush_test.o \
selftests/igt_live_test.o \
+   selftests/igt_mmap.o \
selftests/igt_reset.o \
selftests/igt_spinner.o
 
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 29b2077b73d2..d5ae491a0367 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -12,6 +12,7 @@
 #include "i915_selftest.h"
 #include "selftests/i915_random.h"
 #include "selftests/igt_flush_test.h"
+#include "selftests/igt_mmap.h"
 
 struct tile {
unsigned int width;
@@ -694,12 +695,111 @@ static int igt_mmap_offset_exhaustion(void *arg)
goto out;
 }
 
+#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
+static int igt_mmap_gtt(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct drm_i915_gem_object *obj;
+   struct vm_area_struct *area;
+   unsigned long addr;
+   void *vaddr;
+   int err, i;
+
+   if (!i915_ggtt_has_aperture(&i915->ggtt))
+   return 0;
+
+   obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+   if (IS_ERR(obj))
+   return PTR_ERR(obj);
+
+   vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+   if (IS_ERR(vaddr)) {
+   err = PTR_ERR(vaddr);
+   goto out;
+   }
+   memset(vaddr, POISON_INUSE, PAGE_SIZE);
+   i915_gem_object_flush_map(obj);
+   i915_gem_object_unpin_map(obj);
+
+   err = create_mmap_offset(obj);
+   if (err)
+   goto out;
+
+   addr = igt_mmap_node(i915, &obj->base.vma_node,
+0, PROT_WRITE, MAP_SHARED);
+   if (IS_ERR_VALUE(addr)) {
+   err = addr;
+   goto out;
+   }
+
+   pr_debug("igt_mmap(obj:gtt) @ %lx\n", addr);
+
+   area = find_vma(current->mm, addr);
+   if (!area) {
+   pr_err("Did not create a vm_area_struct for the mmap\n");
+   err = -EINVAL;
+   goto out_unmap;
+   }
+
+   if (area->vm_private_data != obj) {
+   pr_err("vm_area_struct did not point back to our object!\n");
+   err = -EINVAL;
+   goto out_unmap;
+   }
+
+   for (i = 0; i < PAGE_SIZE / sizeof(u32); i++) {
+   u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof*(ux)));
+   u32 x;
+
+   if (get_user(x, ux)) {
+   pr_err("Unable to read from GTT mmap, offset:%zd\n",
+  i * sizeof(x));
+   err = -EFAULT;
+   break;
+   }
+
+   if (x != expand32(POISON_INUSE)) {
+   pr_err("Read incorrect value from GTT mmap, offset:%zd, 
found:%x, expected:%x\n",
+  i * sizeof(x), x, expand32(POISON_INUSE));
+   err = -EINVAL;
+   break;
+   }
+
+   x = expand32(POISON_FREE);
+   if (put_user(x, ux)) {
+   pr_err("Unable to write to GTT mmap, offset:%zd\n",
+  i * sizeof(x));
+   err = -EFAULT;
+   break;
+   }
+   }
+
+out_unmap:
+   vm_munmap(addr, PAGE_SIZE);
+
+   vaddr = i915_gem_object_pin_map(obj, I915_MAP_FORCE_WC);
+   if (IS_ERR(vaddr)) {
+   err = PTR_ERR(vaddr);
+   goto out;
+   }
+   if (err == 0 && memchr_inv(vaddr, POISON_FREE, PAGE_SIZE)) {
+   pr_err("Write via GGTT mmap did not land in backing store\n");
+   err = -EINVAL;
+   }
+   i915_gem_object_unpin_map(obj);
+
+out:
+   i915_gem_object_put(obj);
+   return err;
+}
+
 int i915_gem_mman_live_selftests(struct drm_i915_private *i915)
 {
static const struct i915_subtest tests[] = {
SUBTEST(igt_partial_tiling),
SUBTEST(i

[Intel-gfx] [CI 2/5] drm: Expose a method for creating anonymous struct file around drm_minor

[Chris Wilson]

Sometimes we need to create a struct file to wrap a drm_device, as it
the user were to have opened /dev/dri/card0 but to do so anonymously
(i.e. for internal use). Provide a utility method to create a struct
file with the drm_device->driver.fops, that wrap the drm_device.

v2: Restrict usage to selftests

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_file.c | 42 ++
 include/drm/drm_file.h |  3 +++
 2 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c
index ea34bc991858..4d9385d1bf2d 100644
--- a/drivers/gpu/drm/drm_file.c
+++ b/drivers/gpu/drm/drm_file.c
@@ -31,7 +31,9 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -754,3 +756,43 @@ void drm_send_event(struct drm_device *dev, struct 
drm_pending_event *e)
spin_unlock_irqrestore(&dev->event_lock, irqflags);
 }
 EXPORT_SYMBOL(drm_send_event);
+
+/**
+ * mock_drm_getfile - Create a new struct file for the drm device
+ * @minor: drm minor to wrap (e.g. #drm_device.primary)
+ * @flags: file creation mode (O_RDWR etc)
+ *
+ * This create a new struct file that wraps a DRM file context around a
+ * DRM minor. This mimicks userspace opening e.g. /dev/dri/card0, but without
+ * invoking userspace. The struct file may be operated on using its f_op
+ * (the drm_device.driver.fops) to mimick userspace operations, or be supplied
+ * to userspace facing functions as an internal/anonymous client.
+ *
+ * RETURNS:
+ * Pointer to newly created struct file, ERR_PTR on failure.
+ */
+struct file *mock_drm_getfile(struct drm_minor *minor, unsigned int flags)
+{
+   struct drm_device *dev = minor->dev;
+   struct drm_file *priv;
+   struct file *file;
+
+   priv = drm_file_alloc(minor);
+   if (IS_ERR(priv))
+   return ERR_CAST(priv);
+
+   file = anon_inode_getfile("drm", dev->driver->fops, priv, flags);
+   if (IS_ERR(file)) {
+   drm_file_free(priv);
+   return file;
+   }
+
+   /* Everyone shares a single global address space */
+   file->f_mapping = dev->anon_inode->i_mapping;
+
+   drm_dev_get(dev);
+   priv->filp = file;
+
+   return file;
+}
+EXPORT_SYMBOL_FOR_TESTS_ONLY(mock_drm_getfile);
diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
index 67af60bb527a..8b099b347817 100644
--- a/include/drm/drm_file.h
+++ b/include/drm/drm_file.h
@@ -42,6 +42,7 @@ struct dma_fence;
 struct drm_file;
 struct drm_device;
 struct device;
+struct file;
 
 /*
  * FIXME: Not sure we want to have drm_minor here in the end, but to avoid
@@ -387,4 +388,6 @@ void drm_event_cancel_free(struct drm_device *dev,
 void drm_send_event_locked(struct drm_device *dev, struct drm_pending_event 
*e);
 void drm_send_event(struct drm_device *dev, struct drm_pending_event *e);
 
+struct file *mock_drm_getfile(struct drm_minor *minor, unsigned int flags);
+
 #endif /* _DRM_FILE_H_ */
-- 
2.24.0

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Re: [Intel-gfx] i915 HDCP 2.2 TX encryption on Teledyne test instrument

[Voldman, Mikhail]

Hi Ram,

Can you point me to the: "additional kernel patch for your product to set the 
desired state as default state of the property at the creation".

Mikhail Voldman
System Architect

Teledyne LeCroy, Protocol Solutions Group
2111 Big Timber Road
Elgin, IL  60123
Note new email address:  mikhail.vold...@teledyne.com
847-888-0450 x136

Send me a file securely


-Original Message-
From: Ramalingam C  
Sent: Tuesday, November 5, 2019 11:12 PM
To: Voldman, Mikhail 
Cc: Kurmi Suresh Kumar ; intel-gfx 

Subject: Re: i915 HDCP 2.2 TX encryption on Teledyne test instrument

---External Email---

Moving to #intel-gfx

Hi,

Glad that I could help you!

On 2019-11-05 at 21:56:28 +, Voldman, Mikhail wrote:
> Hello Ramalingam,
> 
> Thank you for quick response. 
> Your information is very helpful. 
> But can you elaborate:
> 
> In your product, If you want to enable the HDCP always based on the 
> sink capability, set the "Content protection" to DESIRED state along 
> with desired content type.  [MV] should I set DESIRED protection level as DRM 
> master?
This needs additional kernel patch for your product to set the desired state as 
default state of the property at the creation.
> 
> As these are properties, non DRM Masters can only read them. can set 
> them. [MV] do you mean: " non DRM Masters can only read them, but  can't set 
> them."
Yes.
> Can I use MEI interface to control HDCP?
Not needed if you set the default state as desired.
-Ram
> 
> Mikhail Voldman
> System Architect
> 
> Teledyne LeCroy, Protocol Solutions Group
> 2111 Big Timber Road
> Elgin, IL  60123
> Note new email address:  mikhail.vold...@teledyne.com
> 847-888-0450 x136
> 
> Send me a file securely
> 
> 
> -Original Message-
> From: Ramalingam C 
> Sent: Monday, November 4, 2019 10:44 PM
> To: Voldman, Mikhail 
> Cc: Kurmi Suresh Kumar 
> Subject: Re: i915 HDCP 2.2 TX encryption on Teledyne test instrument
> 
> ---External Email---
> 
> On 2019-11-04 at 20:42:49 +, Voldman, Mikhail wrote:
> > Hello Ramalingam,
> > 
> > We exchanged number of e-mails few months ago regarding Linux i915 HDCP 2.2 
> > encryption  support in the new Teledyne video test instrument.
> > Thanks for your help we were able to control HDCP 2.2 encryption as DRM 
> > masters.
> > 
> > Unfortunately our product requirement specified than we need to  enable 
> > HDCP 2.2 always if attached monitor capabilities shows HDCP 2.2 support.
> > Also i915 based TX required to execute HDCP 2.2 re-authentication if Sink 
> > HPD is detected.
> > 
> > Is current Intel i915 kernel driver implementation can support desired 
> > functionality? Do you have plans to support this?
> 
> "HDCP always" will never be an upstream solution. always userspace 
> driven.
> 
> In your product, If you want to enable the HDCP always based on the 
> sink capability, set the "Content protection" to DESIRED state along 
> with desired content type.
> 
> As these are properties, non DRM Masters can only read them. can set 
> them.
> 
> Hope you are unblocked. All the best!
> 
> -Ram
> > 
> > Are current i915 allow control HDCP encryption by NOT DRM master 
> > application?
> > 
> > Any suggestion or advice by Intel HDCP 2.2 experts will be really 
> > appreciated.
> > 
> > Best Regards,
> > 
> > Mikhail Voldman
> > System Architect
> > [cid:image001.gif@01D2D0A7.919320A0]
> > Teledyne LeCroy, Protocol Solutions Group
> > 2111 Big Timber Road
> > Elgin, IL  60123
> > Note new email address:  
> > mikhail.vold...@teledyne.com
> > 847-888-0450 x136
> > 
> > Send me a file 
> > securely > teledyne.com>
> > 
> 
> 
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[Intel-gfx] [PATCH] drm/i915: Expand documentation for gen12 DP pre-enable sequence

[Matt Roper]

Rather than just specifying the bullet numbers from the bspec (e.g.,
"4.b") actually include the description of what the bspec wants us to
do.  Steps can be renumbered or moved so including the description will
help us match the code up to the spec.  Plus if we add support for new
platforms, some of the steps may be added/removed so more descriptive
comments will be useful for ensuring all of the bspec requirements are
met.

Cc: José Roberto de Souza 
Cc: Lucas De Marchi 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 92 ++--
 1 file changed, 72 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 398c6f054a6e..ad39cd608011 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3438,48 +3438,86 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
 
-   /* 1.a got on intel_atomic_commit_tail() */
+   /*
+* 1. Enable Power Wells
+*
+* This was handled at the beginning of intel_atomic_commit_tail(),
+* before we called down into this function.
+*/
 
-   /* 2. */
+   /* 2. Enable Panel Power if PPS is required */
intel_edp_panel_on(intel_dp);
 
/*
-* 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
-* haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
-* haswell_crtc_enable()->intel_enable_shared_dpll()
+* 3. For non-TBT Type-C ports, set FIA lane count
+* (DFLEXDPSP.DPX4TXLATC)
+*
+* This was done before tgl_ddi_pre_enable_dp by
+* haswell_crtc_enable()->intel_encoders_pre_pll_enable().
 */
 
-   /* 4.b */
+   /*
+* 4. Enable the port PLL.
+*
+* The PLL enabling itself was already done before this function by
+* haswell_crtc_enable()->intel_enable_shared_dpll().  We need only
+* configure the PLL to port mapping here.
+*/
intel_ddi_clk_select(encoder, crtc_state);
 
-   /* 5. */
+   /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
intel_display_power_get(dev_priv,
dig_port->ddi_io_power_domain);
 
-   /* 6. */
+   /* 6. Program DP_MODE */
icl_program_mg_dp_mode(dig_port, crtc_state);
 
/*
-* 7.a - single stream or multi-stream master transcoder: Configure
-* Transcoder Clock Select. For additional MST streams this will be done
-* by intel_mst_pre_enable_dp() after programming VC Payload ID through
-* AUX.
+* 7. The rest of the below are substeps under the bspec's "Enable and
+* Train Display Port" step.  Note that steps that are specific to
+* MST will be handled by intel_mst_pre_enable_dp() before/after it
+* calls into this function.  Also intel_mst_pre_enable_dp() only calls
+* us when active_mst_links==0, so any steps designated for "single
+* stream or multi-stream master transcoder" can just be performed
+* unconditionally here.
+*/
+
+   /*
+* 7a. Configure Transcoder Clock Select to direct the Port clock to the
+* Transcoder.
 */
intel_ddi_enable_pipe_clock(crtc_state);
 
-   /* 7.b */
+   /*
+* 7b. Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
+* Transport Select
+*/
intel_ddi_config_transcoder_func(crtc_state);
 
-   /* 7.d */
+   /*
+* 7c. Configure & enable DP_TP_CTL with link training pattern 1
+* selected
+*
+* This will be handled by the intel_dp_start_link_train() farther
+* down this function.
+*/
+
+   /*
+* 7d. Type C with DP alternate or fixed/legacy/static connection -
+* Disable PHY clock gating per Type-C DDI Buffer page
+*/
icl_phy_set_clock_gating(dig_port, false);
 
-   /* 7.e */
+   /* 7e. Configure voltage swing and related IO settings */
tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
encoder->type);
 
-   /* 7.f */
+   /*
+* 7f. Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
+* the used lanes of the DDI.
+*/
if (intel_phy_is_combo(dev_priv, phy)) {
bool lane_reversal =
dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
@@ -3489,7 +3527,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder 
*encoder,
   lane_reversal);
}
 
-   /* 7.g */
+

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Enable second dbuf slice for ICL and TGL

[Patchwork]

== Series Details ==

Series: drm/i915: Enable second dbuf slice for ICL and TGL
URL   : https://patchwork.freedesktop.org/series/69124/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Enable second dbuf slice for ICL and TGL
+drivers/gpu/drm/i915/intel_pm.c:4253:1: warning: symbol 
'skl_pipe_downscale_amount' was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_pm.c:4274:1: warning: symbol 'icl_get_pipe_ratio' 
was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_pm.c:4371:30: warning: symbol 'icl_allowed_dbufs' 
was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_pm.c:4395:30: warning: symbol 'tgl_allowed_dbufs' 
was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_pm.c:4465:5: warning: symbol 
'i915_get_allowed_dbuf_mask' was not declared. Should it be static?

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable second dbuf slice for ICL and TGL

[Patchwork]

== Series Details ==

Series: drm/i915: Enable second dbuf slice for ICL and TGL
URL   : https://patchwork.freedesktop.org/series/69124/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2fdfc3b51c5b drm/i915: Enable second dbuf slice for ICL and TGL
-:221: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (8, 0)
#221: FILE: drivers/gpu/drm/i915/display/intel_display_power.h:311:
for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
[...]
+u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv);

-:467: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#467: FILE: drivers/gpu/drm/i915/intel_pm.c:3953:
+   u32 pipe_dbuf_slice_mask = \

-:469: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#469: FILE: drivers/gpu/drm/i915/intel_pm.c:3955:
+   i915_get_allowed_dbuf_mask(dev_priv,
+   pipe,

-:585: CHECK:LINE_SPACING: Please don't use multiple blank lines
#585: FILE: drivers/gpu/drm/i915/intel_pm.c:4303:
+
+

-:589: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#589: FILE: drivers/gpu/drm/i915/intel_pm.c:4307:
+   DRM_DEBUG_KMS("Pipe %d downscale amount %d.%d\n",
+  crtc->pipe, pipe_downscale.val >> 16,

-:608: CHECK:LINE_SPACING: Please don't use multiple blank lines
#608: FILE: drivers/gpu/drm/i915/intel_pm.c:4326:
+
+

-:609: CHECK:CAMELCASE: Avoid CamelCase: 
#609: FILE: drivers/gpu/drm/i915/intel_pm.c:4327:
+#define ICL_PIPE_A_DBUF_SLICES(DBuf1)  \

-:617: CHECK:CAMELCASE: Avoid CamelCase: 
#617: FILE: drivers/gpu/drm/i915/intel_pm.c:4335:
+#define ICL_PIPE_AB_DBUF_SLICES(DBuf1, DBuf2)   \

-:629: CHECK:CAMELCASE: Avoid CamelCase: 
#629: FILE: drivers/gpu/drm/i915/intel_pm.c:4347:
+#define ICL_PIPE_ABC_DBUF_SLICES(DBuf1, DBuf2, DBuf3)  \

-:639: CHECK:CAMELCASE: Avoid CamelCase: 
#639: FILE: drivers/gpu/drm/i915/intel_pm.c:4357:
+#define ICL_PIPE_ABCD_DBUF_SLICES(DBuf1, DBuf2, DBuf3, DBuf4)  \

-:748: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#748: FILE: drivers/gpu/drm/i915/intel_pm.c:4466:
+u32 i915_get_allowed_dbuf_mask(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,

total: 0 errors, 2 warnings, 9 checks, 680 lines checked

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Re: [Intel-gfx] [PATCH 01/12] drm: Inline drm_color_lut_extract()

[Daniel Vetter]

On Thu, Nov 07, 2019 at 05:17:14PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> This thing can get called several thousand times per LUT
> so seems like we want to inline it to:
> - avoid the function call overhead
> - allow constant folding
> 
> A quick synthetic test (w/o any hardware interaction) with
> a ridiculously large LUT size shows about 50% reduction in
> runtime on my HSW and BSW boxes. Slightly less with more
> reasonable LUT size but still easily measurable in tens
> of microseconds.
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/drm_color_mgmt.c | 24 
>  include/drm/drm_color_mgmt.h | 23 ++-

You forgot to add the include stanza in the kerneldoc .rst files, which
means this is now lost from the output. Please fix.
-Daniel

>  2 files changed, 22 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_color_mgmt.c 
> b/drivers/gpu/drm/drm_color_mgmt.c
> index 4ce5c6d8de99..19c5f635992a 100644
> --- a/drivers/gpu/drm/drm_color_mgmt.c
> +++ b/drivers/gpu/drm/drm_color_mgmt.c
> @@ -108,30 +108,6 @@
>   *   standard enum values supported by the DRM plane.
>   */
>  
> -/**
> - * drm_color_lut_extract - clamp and round LUT entries
> - * @user_input: input value
> - * @bit_precision: number of bits the hw LUT supports
> - *
> - * Extract a degamma/gamma LUT value provided by user (in the form of
> - * &drm_color_lut entries) and round it to the precision supported by the
> - * hardware.
> - */
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision)
> -{
> - uint32_t val = user_input;
> - uint32_t max = 0x >> (16 - bit_precision);
> -
> - /* Round only if we're not using full precision. */
> - if (bit_precision < 16) {
> - val += 1UL << (16 - bit_precision - 1);
> - val >>= 16 - bit_precision;
> - }
> -
> - return clamp_val(val, 0, max);
> -}
> -EXPORT_SYMBOL(drm_color_lut_extract);
> -
>  /**
>   * drm_crtc_enable_color_mgmt - enable color management properties
>   * @crtc: DRM CRTC
> diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
> index d1c662d92ab7..069b21d61871 100644
> --- a/include/drm/drm_color_mgmt.h
> +++ b/include/drm/drm_color_mgmt.h
> @@ -29,7 +29,28 @@
>  struct drm_crtc;
>  struct drm_plane;
>  
> -uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
> +/**
> + * drm_color_lut_extract - clamp and round LUT entries
> + * @user_input: input value
> + * @bit_precision: number of bits the hw LUT supports
> + *
> + * Extract a degamma/gamma LUT value provided by user (in the form of
> + * &drm_color_lut entries) and round it to the precision supported by the
> + * hardware.
> + */
> +static inline u32 drm_color_lut_extract(u32 user_input, int bit_precision)
> +{
> + u32 val = user_input;
> + u32 max = 0x >> (16 - bit_precision);
> +
> + /* Round only if we're not using full precision. */
> + if (bit_precision < 16) {
> + val += 1UL << (16 - bit_precision - 1);
> + val >>= 16 - bit_precision;
> + }
> +
> + return clamp_val(val, 0, max);
> +}
>  
>  void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
>   uint degamma_lut_size,
> -- 
> 2.23.0
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 1/5] drm: Add __drm_atomic_helper_crtc_state_reset() & co.

[Daniel Vetter]

On Thu, Nov 07, 2019 at 04:24:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Annoyingly __drm_atomic_helper_crtc_reset() does two
> totally separate things:
> a) reset the state to defaults values
> b) assign the crtc->state pointer
> 
> I just want a) without the b) so let's split out part
> a) into __drm_atomic_helper_crtc_state_reset(). And
> of course we'll do the same thing for planes and connectors.
> 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Daniel Vetter 

And I guess

Acked-by: Daniel Vetter 

for merging through drm-intel, I don't expect anyone to start using this
in the next few weeks.

Cheers, Daniel

> ---
>  drivers/gpu/drm/drm_atomic_state_helper.c | 70 ---
>  include/drm/drm_atomic_state_helper.h |  6 ++
>  2 files changed, 67 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c 
> b/drivers/gpu/drm/drm_atomic_state_helper.c
> index d0a937fb0c56..a972068d58cf 100644
> --- a/drivers/gpu/drm/drm_atomic_state_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_state_helper.c
> @@ -57,6 +57,22 @@
>   * for these functions.
>   */
>  
> +/**
> + * __drm_atomic_helper_crtc_state_reset - reset the CRTC state
> + * @crtc_state: atomic CRTC state, must not be NULL
> + * @crtc: CRTC object, must not be NULL
> + *
> + * Initializes the newly allocated @crtc_state with default
> + * values. This is useful for drivers that subclass the CRTC state.
> + */
> +void
> +__drm_atomic_helper_crtc_state_reset(struct drm_crtc_state *crtc_state,
> +  struct drm_crtc *crtc)
> +{
> + crtc_state->crtc = crtc;
> +}
> +EXPORT_SYMBOL(__drm_atomic_helper_crtc_state_reset);
> +
>  /**
>   * __drm_atomic_helper_crtc_reset - reset state on CRTC
>   * @crtc: drm CRTC
> @@ -74,7 +90,7 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
>  struct drm_crtc_state *crtc_state)
>  {
>   if (crtc_state)
> - crtc_state->crtc = crtc;
> + __drm_atomic_helper_crtc_state_reset(crtc_state, crtc);
>  
>   crtc->state = crtc_state;
>  }
> @@ -212,23 +228,43 @@ void drm_atomic_helper_crtc_destroy_state(struct 
> drm_crtc *crtc,
>  EXPORT_SYMBOL(drm_atomic_helper_crtc_destroy_state);
>  
>  /**
> - * __drm_atomic_helper_plane_reset - resets planes state to default values
> + * __drm_atomic_helper_plane_state_reset - resets plane state to default 
> values
> + * @plane_state: atomic plane state, must not be NULL
>   * @plane: plane object, must not be NULL
> - * @state: atomic plane state, must not be NULL
>   *
> - * Initializes plane state to default. This is useful for drivers that 
> subclass
> - * the plane state.
> + * Initializes the newly allocated @plane_state with default
> + * values. This is useful for drivers that subclass the CRTC state.
>   */
> -void __drm_atomic_helper_plane_reset(struct drm_plane *plane,
> -  struct drm_plane_state *state)
> +void __drm_atomic_helper_plane_state_reset(struct drm_plane_state *state,
> +struct drm_plane *plane)
>  {
>   state->plane = plane;
>   state->rotation = DRM_MODE_ROTATE_0;
>  
>   state->alpha = DRM_BLEND_ALPHA_OPAQUE;
>   state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;
> +}
> +EXPORT_SYMBOL(__drm_atomic_helper_plane_state_reset);
>  
> - plane->state = state;
> +/**
> + * __drm_atomic_helper_plane_reset - reset state on plane
> + * @plane: drm plane
> + * @plane_state: plane state to assign
> + *
> + * Initializes the newly allocated @plane_state and assigns it to
> + * the &drm_crtc->state pointer of @plane, usually required when
> + * initializing the drivers or when called from the &drm_plane_funcs.reset
> + * hook.
> + *
> + * This is useful for drivers that subclass the plane state.
> + */
> +void __drm_atomic_helper_plane_reset(struct drm_plane *plane,
> +  struct drm_plane_state *plane_state)
> +{
> + if (plane_state)
> + __drm_atomic_helper_plane_state_reset(plane_state, plane);
> +
> + plane->state = plane_state;
>  }
>  EXPORT_SYMBOL(__drm_atomic_helper_plane_reset);
>  
> @@ -335,6 +371,22 @@ void drm_atomic_helper_plane_destroy_state(struct 
> drm_plane *plane,
>  }
>  EXPORT_SYMBOL(drm_atomic_helper_plane_destroy_state);
>  
> +/**
> + * __drm_atomic_helper_connector_state_reset - reset the connector state
> + * @conn__state: atomic connector state, must not be NULL
> + * @connector: connectotr object, must not be NULL
> + *
> + * Initializes the newly allocated @conn_state with default
> + * values. This is useful for drivers that subclass the connector state.
> + */
> +void
> +__drm_atomic_helper_connector_state_reset(struct drm_connector_state 
> *conn_state,
> +   struct drm_connector *connector)
> +{
> + conn_state->connector = connector;
> +}
> +EXPORT_SYMBOL(__drm_atomic_helper_connector_state_reset);
> +
>  /

[Intel-gfx] [ANNOUNCEMENT] Documenting tests with igt_describe()

[Arkadiusz Hiler]

Hey all,

IGT tests are largely undocumented and a lot of them are quite enigmatic if you
haven't internalized the whole framework and are not familiar with naming
conventions that some people use.

To tackle this we require[0] documenting new tests with igt_describe()[1].

The idea is to provide a short description (one or two sentences) on
what the test is supposed to verify to give the reader enough of context
so they easily can tell what scenario the test is exercising.

This also makes reading the tests so much easier - sometimes it is
really hard and takes a long time to understand the main thought behind
a test just from the implementation details.

We don't want you to translate C into English, we want you to provide a bit of
that extra information that you would have put in the comments anyway.

See igt_describe() documentation[1] for guidelines on writing good descriptions.

[0]: 
https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19
[1]: 
https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe

Signed-off-by: Arkadiusz Hiler 
Signed-off-by: Petri Latvala 


## FAQ

Q: How is this being enforced?
A: If your patch introduces undocumented tests you will get an email with
   instruction how to proceed. This is considered as failing the CI checks.
   e.g.: 
https://lists.freedesktop.org/archives/igt-dev/2019-November/017266.html

Q: I am not sure my descriptions are good...
A: That what the review is for. Feel free to poke me or Petri on IRC in case you
   want some help with writing them.

Q: Why are you using igt_describe() and not doxygen/sphinx/gtk-doc/etc.
   comments?
A: We are documenting tests, not C functions. Those tools do not
   understand comments over magic control blocks used by the test
   harness to define tests/subtests. Additional benefit is that the
   documentation is available not only in the source code and the
   generated documentation but also on the command line by using
   --describe switch.

-- 
Cheers,
Arek

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Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/selftests: Replace mock_file hackery with drm's true fake

[Daniel Vetter]

On Thu, Nov 07, 2019 at 05:17:00PM +, Chris Wilson wrote:
> Quoting Daniel Vetter (2019-11-07 08:39:24)
> > On Wed, Nov 06, 2019 at 02:24:30PM +, Chris Wilson wrote:
> > > As drm now exports a method to create an anonymous struct file around a
> > > drm_device for internal use, make use of it to avoid our horrible hacks.
> > > 
> > > Signed-off-by: Chris Wilson 
> > > ---
> > >  drivers/gpu/drm/i915/Kconfig.debug|  2 +
> > >  .../gpu/drm/i915/gem/selftests/huge_pages.c   |  2 +-
> > >  .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++---
> > >  .../i915/gem/selftests/i915_gem_object_blt.c  |  4 +-
> > >  drivers/gpu/drm/i915/gt/selftest_context.c|  4 +-
> > >  drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |  8 +--
> > >  .../gpu/drm/i915/gt/selftest_workarounds.c|  2 +-
> > >  drivers/gpu/drm/i915/selftests/i915_gem.c |  4 +-
> > >  .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
> > >  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
> > >  drivers/gpu/drm/i915/selftests/i915_request.c |  2 +-
> > >  .../drm/i915/selftests/intel_memory_region.c  |  2 +-
> > >  drivers/gpu/drm/i915/selftests/mock_drm.c | 49 +++
> > >  drivers/gpu/drm/i915/selftests/mock_drm.h |  8 ++-
> > >  14 files changed, 39 insertions(+), 66 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
> > > b/drivers/gpu/drm/i915/Kconfig.debug
> > > index ef123eb29168..1140525da75a 100644
> > > --- a/drivers/gpu/drm/i915/Kconfig.debug
> > > +++ b/drivers/gpu/drm/i915/Kconfig.debug
> > > @@ -37,6 +37,7 @@ config DRM_I915_DEBUG
> > >   select X86_MSR # used by igt/pm_rpm
> > >   select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
> > >   select DRM_DEBUG_MM if DRM=y
> > > + select DRM_EXPORT_FOR_TESTS if m
> > >   select DRM_DEBUG_SELFTEST
> > >   select DMABUF_SELFTESTS
> > >   select SW_SYNC # signaling validation framework (igt/syncobj*)
> > > @@ -160,6 +161,7 @@ config DRM_I915_SELFTEST
> > >   bool "Enable selftests upon driver load"
> > >   depends on DRM_I915
> > >   default n
> > > + select DRM_EXPORT_FOR_TESTS if m
> > >   select FAULT_INJECTION
> > >   select PRIME_NUMBERS
> > >   help
> > > diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c 
> > > b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > > index 688c49a24f32..06dad7b0db82 100644
> > > --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > > +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > > @@ -1944,6 +1944,6 @@ int i915_gem_huge_page_live_selftests(struct 
> > > drm_i915_private *i915)
> > >   err = i915_subtests(tests, ctx);
> > >  
> > >  out_file:
> > > - mock_file_free(i915, file);
> > > + mock_file_put(file);
> > >   return err;
> > >  }
> > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 
> > > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > > index 62fabc023a83..47890c92534c 100644
> > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > > @@ -149,7 +149,7 @@ static int live_nop_switch(void *arg)
> > >   }
> > >  
> > >  out_file:
> > > - mock_file_free(i915, file);
> > > + mock_file_put(file);
> > >   return err;
> > >  }
> > >  
> > > @@ -377,7 +377,7 @@ static int live_parallel_switch(void *arg)
> > >   }
> > >   kfree(data);
> > >  out_file:
> > > - mock_file_free(i915, file);
> > > + mock_file_put(file);
> > >   return err;
> > >  }
> > >  
> > > @@ -716,7 +716,7 @@ static int igt_ctx_exec(void *arg)
> > >   if (igt_live_test_end(&t))
> > >   err = -EIO;
> > >  
> > > - mock_file_free(i915, file);
> > > + mock_file_put(file);
> > >   if (err)
> > >   return err;
> > >  
> > > @@ -854,7 +854,7 @@ static int igt_shared_ctx_exec(void *arg)
> > >   if (igt_live_test_end(&t))
> > >   err = -EIO;
> > >  out_file:
> > > - mock_file_free(i915, file);
> > > + mock_file_put(file);
> > >   return err;
> > >  }
> > >  
> > > @@ -1426,7 +1426,7 @@ static int igt_ctx_readonly(void *arg)
> > >   if (igt_live_test_end(&t))
> > >   err = -EIO;
> > >  
> > > - mock_file_free(i915, file);
> > > + mock_file_put(file);
> > >   return err;
> > >  }
> > >  
> > > @@ -1750,7 +1750,7 @@ static int igt_vm_isolation(void *arg)
> > >  out_file:
> > >   if (igt_live_test_end(&t))
> > >   err = -EIO;
> > > - mock_file_free(i915, file);
> > > + mock_file_put(file);
> > >   return err;
> > >  }
> > >  
> > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c 
> > > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> > > index e8132aca0bb6..d9fdfddb7091 100644
> > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> > > +++ b/drivers/gpu/d

Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/selftests: Replace mock_file hackery with drm's true fake

[Matthew Auld]

On Wed, 6 Nov 2019 at 14:24, Chris Wilson  wrote:
>
> As drm now exports a method to create an anonymous struct file around a
> drm_device for internal use, make use of it to avoid our horrible hacks.
>
> Signed-off-by: Chris Wilson 

As per your eventual plan, fwiw,
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/selftests: Replace mock_file hackery with drm's true fake

[Chris Wilson]

Quoting Daniel Vetter (2019-11-07 08:39:24)
> On Wed, Nov 06, 2019 at 02:24:30PM +, Chris Wilson wrote:
> > As drm now exports a method to create an anonymous struct file around a
> > drm_device for internal use, make use of it to avoid our horrible hacks.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/Kconfig.debug|  2 +
> >  .../gpu/drm/i915/gem/selftests/huge_pages.c   |  2 +-
> >  .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++---
> >  .../i915/gem/selftests/i915_gem_object_blt.c  |  4 +-
> >  drivers/gpu/drm/i915/gt/selftest_context.c|  4 +-
> >  drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |  8 +--
> >  .../gpu/drm/i915/gt/selftest_workarounds.c|  2 +-
> >  drivers/gpu/drm/i915/selftests/i915_gem.c |  4 +-
> >  .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
> >  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
> >  drivers/gpu/drm/i915/selftests/i915_request.c |  2 +-
> >  .../drm/i915/selftests/intel_memory_region.c  |  2 +-
> >  drivers/gpu/drm/i915/selftests/mock_drm.c | 49 +++
> >  drivers/gpu/drm/i915/selftests/mock_drm.h |  8 ++-
> >  14 files changed, 39 insertions(+), 66 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
> > b/drivers/gpu/drm/i915/Kconfig.debug
> > index ef123eb29168..1140525da75a 100644
> > --- a/drivers/gpu/drm/i915/Kconfig.debug
> > +++ b/drivers/gpu/drm/i915/Kconfig.debug
> > @@ -37,6 +37,7 @@ config DRM_I915_DEBUG
> >   select X86_MSR # used by igt/pm_rpm
> >   select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
> >   select DRM_DEBUG_MM if DRM=y
> > + select DRM_EXPORT_FOR_TESTS if m
> >   select DRM_DEBUG_SELFTEST
> >   select DMABUF_SELFTESTS
> >   select SW_SYNC # signaling validation framework (igt/syncobj*)
> > @@ -160,6 +161,7 @@ config DRM_I915_SELFTEST
> >   bool "Enable selftests upon driver load"
> >   depends on DRM_I915
> >   default n
> > + select DRM_EXPORT_FOR_TESTS if m
> >   select FAULT_INJECTION
> >   select PRIME_NUMBERS
> >   help
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c 
> > b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > index 688c49a24f32..06dad7b0db82 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > @@ -1944,6 +1944,6 @@ int i915_gem_huge_page_live_selftests(struct 
> > drm_i915_private *i915)
> >   err = i915_subtests(tests, ctx);
> >  
> >  out_file:
> > - mock_file_free(i915, file);
> > + mock_file_put(file);
> >   return err;
> >  }
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 
> > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > index 62fabc023a83..47890c92534c 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > @@ -149,7 +149,7 @@ static int live_nop_switch(void *arg)
> >   }
> >  
> >  out_file:
> > - mock_file_free(i915, file);
> > + mock_file_put(file);
> >   return err;
> >  }
> >  
> > @@ -377,7 +377,7 @@ static int live_parallel_switch(void *arg)
> >   }
> >   kfree(data);
> >  out_file:
> > - mock_file_free(i915, file);
> > + mock_file_put(file);
> >   return err;
> >  }
> >  
> > @@ -716,7 +716,7 @@ static int igt_ctx_exec(void *arg)
> >   if (igt_live_test_end(&t))
> >   err = -EIO;
> >  
> > - mock_file_free(i915, file);
> > + mock_file_put(file);
> >   if (err)
> >   return err;
> >  
> > @@ -854,7 +854,7 @@ static int igt_shared_ctx_exec(void *arg)
> >   if (igt_live_test_end(&t))
> >   err = -EIO;
> >  out_file:
> > - mock_file_free(i915, file);
> > + mock_file_put(file);
> >   return err;
> >  }
> >  
> > @@ -1426,7 +1426,7 @@ static int igt_ctx_readonly(void *arg)
> >   if (igt_live_test_end(&t))
> >   err = -EIO;
> >  
> > - mock_file_free(i915, file);
> > + mock_file_put(file);
> >   return err;
> >  }
> >  
> > @@ -1750,7 +1750,7 @@ static int igt_vm_isolation(void *arg)
> >  out_file:
> >   if (igt_live_test_end(&t))
> >   err = -EIO;
> > - mock_file_free(i915, file);
> > + mock_file_put(file);
> >   return err;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c 
> > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> > index e8132aca0bb6..d9fdfddb7091 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> > @@ -301,7 +301,7 @@ static int igt_fill_blt_thread(void *arg)
> >  
> >   intel_context_put(ce);
> >  out_file:
> > - mock_file_free(i915, file);
> > + mock_file_put(file);
> >   return err;
> >  }
> >  
> > @@ -432,7 +432,7 @@ static int igt

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Split a setting of MSA to MST and SST (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Split a setting of MSA to MST and SST (rev2)
URL   : https://patchwork.freedesktop.org/series/69092/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7286 -> Patchwork_15173


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_15173 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15173, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15173/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_15173:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live_execlists:
- fi-glk-dsi: [PASS][1] -> [TIMEOUT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7286/fi-glk-dsi/igt@i915_selftest@live_execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15173/fi-glk-dsi/igt@i915_selftest@live_execlists.html

  
Known issues


  Here are the changes found in Patchwork_15173 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live_gem_contexts:
- fi-bsw-kefka:   [PASS][3] -> [INCOMPLETE][4] ([fdo# 111542])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7286/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15173/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][5] -> [FAIL][6] ([fdo#111045] / [fdo#111096])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7286/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15173/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
 Possible fixes 

  * igt@gem_exec_create@basic:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111736]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7286/fi-tgl-u/igt@gem_exec_cre...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15173/fi-tgl-u/igt@gem_exec_cre...@basic.html

  * igt@kms_busy@basic-flip-a:
- fi-icl-u2:  [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7286/fi-icl-u2/igt@kms_b...@basic-flip-a.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15173/fi-icl-u2/igt@kms_b...@basic-flip-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736


Participating hosts (50 -> 45)
--

  Additional (1): fi-kbl-soraka 
  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-byt-clapper 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7286 -> Patchwork_15173

  CI-20190529: 20190529
  CI_DRM_7286: e14c445cbd00478ba6a25daa4461065ce1200856 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15173: 5c1183a2af692337682ff40e1d1781844006a650 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

5c1183a2af69 drm/i915: Split a setting of MSA to MST and SST

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15173/index.html
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Re: [Intel-gfx] [PATCH] drm/i915/gem: Safely acquire the ctx->vm when copying

[Chris Wilson]

Quoting Niranjan Vishwanathapura (2019-11-07 16:09:31)
> On Wed, Nov 06, 2019 at 09:13:12AM +, Chris Wilson wrote:
> >As we read the ctx->vm unlocked before cloning/exporting, we should
> >validate our reference is correct before returning it. We already do for
> >clone_vm() but were not so strict around get_ppgtt().
> >
> >Signed-off-by: Chris Wilson 
> >---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 80 +++--
> > 1 file changed, 43 insertions(+), 37 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
> >b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >index de6e55af82cf..a06cc8e63281 100644
> >--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >@@ -995,6 +995,38 @@ static int context_barrier_task(struct i915_gem_context 
> >*ctx,
> >   return err;
> > }
> >
> >+static struct i915_address_space *
> >+context_get_vm_rcu(struct i915_gem_context *ctx)
> >+{
> >+  do {
> >+  struct i915_address_space *vm;
> >+
> >+  vm = rcu_dereference(ctx->vm);
> >+  if (!kref_get_unless_zero(&vm->ref))
> >+  continue;
> 
> But should we check for NULL vm?
> I know the callers are ensuring ctx->vm will not be NULL, but just wondering.

We don't need to as the rule is that ctx->vm once set can never be
unset; and it can only be set during construction based on the HW
properties. The idea is that !!ctx->vm is an invariant indicating
whether or not we have full-ppgtt enabled. From a security perspective,
allowing a downgrade from full-ppgtt to a shared global gtt is a big no,
so I don't anticipating us allowing setting ctx->vm to NULL anytime in
the near future :)

> >+
> >+  /*
> >+   * This ppgtt may have be reallocated between
> >+   * the read and the kref, and reassigned to a third
> >+   * context. In order to avoid inadvertent sharing
> >+   * of this ppgtt with that third context (and not
> >+   * src), we have to confirm that we have the same
> >+   * ppgtt after passing through the strong memory
> >+   * barrier implied by a successful
> >+   * kref_get_unless_zero().
> >+   *
> >+   * Once we have acquired the current ppgtt of src,
> >+   * we no longer care if it is released from src, as
> >+   * it cannot be reallocated elsewhere.
> >+   */
> 
> Comment should be made generic? It is too specific to cloning case.

s/src/ctx/
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/gem: Safely acquire the ctx->vm when copying

[Niranjan Vishwanathapura]

On Wed, Nov 06, 2019 at 09:13:12AM +, Chris Wilson wrote:

As we read the ctx->vm unlocked before cloning/exporting, we should
validate our reference is correct before returning it. We already do for
clone_vm() but were not so strict around get_ppgtt().

Signed-off-by: Chris Wilson 
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 80 +++--
1 file changed, 43 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index de6e55af82cf..a06cc8e63281 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -995,6 +995,38 @@ static int context_barrier_task(struct i915_gem_context 
*ctx,
return err;
}

+static struct i915_address_space *
+context_get_vm_rcu(struct i915_gem_context *ctx)
+{
+   do {
+   struct i915_address_space *vm;
+
+   vm = rcu_dereference(ctx->vm);
+   if (!kref_get_unless_zero(&vm->ref))
+   continue;


But should we check for NULL vm?
I know the callers are ensuring ctx->vm will not be NULL, but just wondering.


+
+   /*
+* This ppgtt may have be reallocated between
+* the read and the kref, and reassigned to a third
+* context. In order to avoid inadvertent sharing
+* of this ppgtt with that third context (and not
+* src), we have to confirm that we have the same
+* ppgtt after passing through the strong memory
+* barrier implied by a successful
+* kref_get_unless_zero().
+*
+* Once we have acquired the current ppgtt of src,
+* we no longer care if it is released from src, as
+* it cannot be reallocated elsewhere.
+*/


Comment should be made generic? It is too specific to cloning case.

Other than that, patch looks good to me.
Reviewed-by: Niranjana Vishwanathapura 


+
+   if (vm == rcu_access_pointer(ctx->vm))
+   return rcu_pointer_handoff(vm);
+
+   i915_vm_put(vm);
+   } while (1);
+}
+
static int get_ppgtt(struct drm_i915_file_private *file_priv,
 struct i915_gem_context *ctx,
 struct drm_i915_gem_context_param *args)
@@ -1006,7 +1038,7 @@ static int get_ppgtt(struct drm_i915_file_private 
*file_priv,
return -ENODEV;

rcu_read_lock();
-   vm = i915_vm_get(ctx->vm);
+   vm = context_get_vm_rcu(ctx);
rcu_read_unlock();

ret = mutex_lock_interruptible(&file_priv->vm_idr_lock);
@@ -2035,47 +2067,21 @@ static int clone_vm(struct i915_gem_context *dst,
struct i915_address_space *vm;
int err = 0;

-   rcu_read_lock();
-   do {
-   vm = rcu_dereference(src->vm);
-   if (!vm)
-   break;
-
-   if (!kref_get_unless_zero(&vm->ref))
-   continue;
-
-   /*
-* This ppgtt may have be reallocated between
-* the read and the kref, and reassigned to a third
-* context. In order to avoid inadvertent sharing
-* of this ppgtt with that third context (and not
-* src), we have to confirm that we have the same
-* ppgtt after passing through the strong memory
-* barrier implied by a successful
-* kref_get_unless_zero().
-*
-* Once we have acquired the current ppgtt of src,
-* we no longer care if it is released from src, as
-* it cannot be reallocated elsewhere.
-*/
-
-   if (vm == rcu_access_pointer(src->vm))
-   break;
+   if (!rcu_access_pointer(src->vm))
+   return 0;

-   i915_vm_put(vm);
-   } while (1);
+   rcu_read_lock();
+   vm = context_get_vm_rcu(src);
rcu_read_unlock();

-   if (vm) {
-   if (!mutex_lock_interruptible(&dst->mutex)) {
-   __assign_ppgtt(dst, vm);
-   mutex_unlock(&dst->mutex);
-   } else {
-   err = -EINTR;
-   }
-   i915_vm_put(vm);
+   if (!mutex_lock_interruptible(&dst->mutex)) {
+   __assign_ppgtt(dst, vm);
+   mutex_unlock(&dst->mutex);
+   } else {
+   err = -EINTR;
}

+   i915_vm_put(vm);
return err;
}

--
2.24.0

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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/bios: store child devices in a list

[Ville Syrjälä]

On Thu, Nov 07, 2019 at 06:08:53PM +0200, Jani Nikula wrote:
> Using the array is getting clumsy. Make things a bit more dynamic.
> 
> Remove early returns on not having child devices when the end result
> after "iterating" the empty list would be the same.
> 
> v2:
> - stick to previous naming of child devices (Ville)
> - use kzalloc, handle failure
> - initialize list head earlier to keep intel_bios_driver_remove() safe
> 
> Cc: Ville Syrjala 
> Signed-off-by: Jani Nikula 
> 
> ---
> 
> The end goal: allow more meta information to be added to the new
> child_device struct, independent of DDI port info being used or not on
> the platform, and eventually migrate ddi_port_info to it as well,
> unifying the stuff across platforms.
> 
> Currently it's not easily possible to associate for example the DSC
> compression data to the child device for non-DDI platforms or for DSI
> outputs. This lets us add the compression data (pointer) to struct
> child_device.
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 123 ++
>  drivers/gpu/drm/i915/i915_drv.h   |   3 +-
>  2 files changed, 58 insertions(+), 68 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index c19b234bebe6..37b944397b75 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -58,6 +58,12 @@
>   * that.
>   */
>  
> +/* Wrapper for VBT child device config */
> +struct display_device_data {
> + struct child_device_config child;
> + struct list_head node;
> +};
> +
>  #define  SLAVE_ADDR1 0x70
>  #define  SLAVE_ADDR2 0x72
>  
> @@ -449,8 +455,9 @@ static void
>  parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
>  {
>   struct sdvo_device_mapping *mapping;
> + const struct display_device_data *devdata;
>   const struct child_device_config *child;
> - int i, count = 0;
> + int count = 0;
>  
>   /*
>* Only parse SDVO mappings on gens that could have SDVO. This isn't
> @@ -461,8 +468,8 @@ parse_sdvo_device_mapping(struct drm_i915_private 
> *dev_priv, u8 bdb_version)
>   return;
>   }
>  
> - for (i = 0, count = 0; i < dev_priv->vbt.child_dev_num; i++) {
> - child = dev_priv->vbt.child_dev + i;
> + list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
> + child = &devdata->child;
>  
>   if (child->slave_addr != SLAVE_ADDR1 &&
>   child->slave_addr != SLAVE_ADDR2) {
> @@ -1572,8 +1579,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *dev_priv,
>  
>  static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 
> bdb_version)
>  {
> - const struct child_device_config *child;
> - int i;
> + const struct display_device_data *devdata;
>  
>   if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
>   return;
> @@ -1581,11 +1587,8 @@ static void parse_ddi_ports(struct drm_i915_private 
> *dev_priv, u8 bdb_version)
>   if (bdb_version < 155)
>   return;
>  
> - for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
> - child = dev_priv->vbt.child_dev + i;
> -
> - parse_ddi_port(dev_priv, child, bdb_version);
> - }
> + list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node)
> + parse_ddi_port(dev_priv, &devdata->child, bdb_version);
>  }
>  
>  static void
> @@ -1593,8 +1596,9 @@ parse_general_definitions(struct drm_i915_private 
> *dev_priv,
> const struct bdb_header *bdb)
>  {
>   const struct bdb_general_definitions *defs;
> + struct display_device_data *devdata;
>   const struct child_device_config *child;
> - int i, child_device_num, count;
> + int i, child_device_num;
>   u8 expected_size;
>   u16 block_size;
>   int bus_pin;
> @@ -1650,26 +1654,7 @@ parse_general_definitions(struct drm_i915_private 
> *dev_priv,
>  
>   /* get the number of child device */
>   child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
> - count = 0;
> - /* get the number of child device that is present */
> - for (i = 0; i < child_device_num; i++) {
> - child = child_device_ptr(defs, i);
> - if (!child->device_type)
> - continue;
> - count++;
> - }
> - if (!count) {
> - DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
> - return;
> - }
> - dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL);
> - if (!dev_priv->vbt.child_dev) {
> - DRM_DEBUG_KMS("No memory space for child device\n");
> - return;
> - }
>  
> - dev_priv->vbt.child_dev_num = count;
> - count = 0;
>   for (i = 0; i < child_device_num; i++) {
>   child = child_device_ptr(defs, i);
>   if (!child->device_t

[Intel-gfx] [PATCH] drm/i915: Taint the kernel on dumping the GEM ftrace buffer

[Chris Wilson]

As the ftrace buffer is single shot, once dumped it will not update. As
such, it only provides information for the first bug and all subsequent
bugs are noise. The goal of CI is to have zero bugs, so taint the kernel
causing CI to reboot the machine; fix the bug and move on.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index f6f9675848b8..b321e4544f10 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -68,9 +68,10 @@ struct drm_i915_private;
pr_err(__VA_ARGS__);\
trace_printk(__VA_ARGS__);  \
 } while (0)
-#define GEM_TRACE_DUMP() ftrace_dump(DUMP_ALL)
+#define GEM_TRACE_DUMP() \
+   do { ftrace_dump(DUMP_ALL); set_taint_for_CI(TAIN_WARN); } while (0)
 #define GEM_TRACE_DUMP_ON(expr) \
-   do { if (expr) ftrace_dump(DUMP_ALL); } while (0)
+   do { if (expr) GEM_TRACE_DUMP(); } while (0)
 #else
 #define GEM_TRACE(...) do { } while (0)
 #define GEM_TRACE_ERR(...) do { } while (0)
-- 
2.24.0

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[Intel-gfx] [PATCH v2 2/2] drm/i915/bios: pass devdata to parse_ddi_port

[Jani Nikula]

Allow accessing the parent structure later on. Drop const for allowing
future modification as well.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 37b944397b75..2f3d51417964 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1425,9 +1425,10 @@ static enum port dvo_port_to_port(u8 dvo_port)
 }
 
 static void parse_ddi_port(struct drm_i915_private *dev_priv,
-  const struct child_device_config *child,
+  struct display_device_data *devdata,
   u8 bdb_version)
 {
+   const struct child_device_config *child = &devdata->child;
struct ddi_vbt_port_info *info;
bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
enum port port;
@@ -1579,7 +1580,7 @@ static void parse_ddi_port(struct drm_i915_private 
*dev_priv,
 
 static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
 {
-   const struct display_device_data *devdata;
+   struct display_device_data *devdata;
 
if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
return;
@@ -1588,7 +1589,7 @@ static void parse_ddi_ports(struct drm_i915_private 
*dev_priv, u8 bdb_version)
return;
 
list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node)
-   parse_ddi_port(dev_priv, &devdata->child, bdb_version);
+   parse_ddi_port(dev_priv, devdata, bdb_version);
 }
 
 static void
-- 
2.20.1

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[Intel-gfx] [PATCH v2 1/2] drm/i915/bios: store child devices in a list

[Jani Nikula]

Using the array is getting clumsy. Make things a bit more dynamic.

Remove early returns on not having child devices when the end result
after "iterating" the empty list would be the same.

v2:
- stick to previous naming of child devices (Ville)
- use kzalloc, handle failure
- initialize list head earlier to keep intel_bios_driver_remove() safe

Cc: Ville Syrjala 
Signed-off-by: Jani Nikula 

---

The end goal: allow more meta information to be added to the new
child_device struct, independent of DDI port info being used or not on
the platform, and eventually migrate ddi_port_info to it as well,
unifying the stuff across platforms.

Currently it's not easily possible to associate for example the DSC
compression data to the child device for non-DDI platforms or for DSI
outputs. This lets us add the compression data (pointer) to struct
child_device.
---
 drivers/gpu/drm/i915/display/intel_bios.c | 123 ++
 drivers/gpu/drm/i915/i915_drv.h   |   3 +-
 2 files changed, 58 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index c19b234bebe6..37b944397b75 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -58,6 +58,12 @@
  * that.
  */
 
+/* Wrapper for VBT child device config */
+struct display_device_data {
+   struct child_device_config child;
+   struct list_head node;
+};
+
 #defineSLAVE_ADDR1 0x70
 #defineSLAVE_ADDR2 0x72
 
@@ -449,8 +455,9 @@ static void
 parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
 {
struct sdvo_device_mapping *mapping;
+   const struct display_device_data *devdata;
const struct child_device_config *child;
-   int i, count = 0;
+   int count = 0;
 
/*
 * Only parse SDVO mappings on gens that could have SDVO. This isn't
@@ -461,8 +468,8 @@ parse_sdvo_device_mapping(struct drm_i915_private 
*dev_priv, u8 bdb_version)
return;
}
 
-   for (i = 0, count = 0; i < dev_priv->vbt.child_dev_num; i++) {
-   child = dev_priv->vbt.child_dev + i;
+   list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
+   child = &devdata->child;
 
if (child->slave_addr != SLAVE_ADDR1 &&
child->slave_addr != SLAVE_ADDR2) {
@@ -1572,8 +1579,7 @@ static void parse_ddi_port(struct drm_i915_private 
*dev_priv,
 
 static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
 {
-   const struct child_device_config *child;
-   int i;
+   const struct display_device_data *devdata;
 
if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
return;
@@ -1581,11 +1587,8 @@ static void parse_ddi_ports(struct drm_i915_private 
*dev_priv, u8 bdb_version)
if (bdb_version < 155)
return;
 
-   for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
-   child = dev_priv->vbt.child_dev + i;
-
-   parse_ddi_port(dev_priv, child, bdb_version);
-   }
+   list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node)
+   parse_ddi_port(dev_priv, &devdata->child, bdb_version);
 }
 
 static void
@@ -1593,8 +1596,9 @@ parse_general_definitions(struct drm_i915_private 
*dev_priv,
  const struct bdb_header *bdb)
 {
const struct bdb_general_definitions *defs;
+   struct display_device_data *devdata;
const struct child_device_config *child;
-   int i, child_device_num, count;
+   int i, child_device_num;
u8 expected_size;
u16 block_size;
int bus_pin;
@@ -1650,26 +1654,7 @@ parse_general_definitions(struct drm_i915_private 
*dev_priv,
 
/* get the number of child device */
child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
-   count = 0;
-   /* get the number of child device that is present */
-   for (i = 0; i < child_device_num; i++) {
-   child = child_device_ptr(defs, i);
-   if (!child->device_type)
-   continue;
-   count++;
-   }
-   if (!count) {
-   DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
-   return;
-   }
-   dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL);
-   if (!dev_priv->vbt.child_dev) {
-   DRM_DEBUG_KMS("No memory space for child device\n");
-   return;
-   }
 
-   dev_priv->vbt.child_dev_num = count;
-   count = 0;
for (i = 0; i < child_device_num; i++) {
child = child_device_ptr(defs, i);
if (!child->device_type)
@@ -1678,15 +1663,23 @@ parse_general_definitions(struct drm_i915_private 
*dev_priv,
DRM_DEBUG_KMS("Found VBT child device with type 0x%x\n",
  child->devic