[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Media decompression support
== Series Details == Series: drm/i915/tgl: Media decompression support URL : https://patchwork.freedesktop.org/series/71535/ State : success == Summary == CI Bug Log - changes from CI_DRM_7660_full -> Patchwork_15961_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_7660_full and Patchwork_15961_full: ### New Piglit tests (7) ### * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_float-position-double_dvec4_array2: - Statuses : 1 fail(s) - Exec time: [0.13] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat4x3_array3-position-double_dvec2: - Statuses : 1 fail(s) - Exec time: [0.14] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_int_array3-position-double_dmat3x2: - Statuses : 1 fail(s) - Exec time: [0.14] s * spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dvec4_array5-uint_uvec2: - Statuses : 1 fail(s) - Exec time: [0.16] s * spec@glsl-4.20@execution@vs_in@vs-input-double_dmat2_array5-uint_uint-position: - Statuses : 1 fail(s) - Exec time: [0.13] s * spec@glsl-4.20@execution@vs_in@vs-input-float_mat3_array3-double_dmat2-position: - Statuses : 1 fail(s) - Exec time: [0.13] s * spec@glsl-4.20@execution@vs_in@vs-input-int_ivec3-double_dmat3x2-position: - Statuses : 1 fail(s) - Exec time: [0.13] s Known issues Here are the changes found in Patchwork_15961_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +8 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb2/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_b...@busy-vcs1.html * igt@gem_busy@close-race: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([i915#435]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb5/igt@gem_b...@close-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb6/igt@gem_b...@close-race.html * igt@gem_ctx_isolation@vcs1-clean: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb4/igt@gem_ctx_isolat...@vcs1-clean.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb6/igt@gem_ctx_isolat...@vcs1-clean.html * igt@gem_eio@reset-stress: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#470]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb8/igt@gem_...@reset-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb5/igt@gem_...@reset-stress.html * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][9] -> [FAIL][10] ([i915#232]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-snb1/igt@gem_...@unwedge-stress.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-snb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#110854]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb1/igt@gem_exec_balan...@smoke.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_exec_gttfill@basic: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111593]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb2/igt@gem_exec_gttf...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb6/igt@gem_exec_gttf...@basic.html * igt@gem_exec_schedule@preempt-queue-blt: - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111677]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb2/igt@gem_exec_sched...@preempt-queue-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb8/igt@gem_exec_sched...@preempt-queue-blt.html * igt@gem_exec_schedule@preempt-queue-contexts-render: - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([fdo#111606] / [fdo#111677]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-tglb6/igt@gem_exec_sched...@preempt-queue-contexts-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/shard-tglb5/igt@gem_exec_sched...@preempt-queue-contexts-render.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#112146]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html [20]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Introduce remap_io_sg() to prefault discontiguous objects
== Series Details == Series: drm/i915: Introduce remap_io_sg() to prefault discontiguous objects URL : https://patchwork.freedesktop.org/series/71530/ State : success == Summary == CI Bug Log - changes from CI_DRM_7659_full -> Patchwork_15959_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15959_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@rcs0-mixed-process: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#679]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-skl6/igt@gem_ctx_persiste...@rcs0-mixed-process.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-skl5/igt@gem_ctx_persiste...@rcs0-mixed-process.html * igt@gem_ctx_persistence@vcs1-mixed: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-iclb2/igt@gem_ctx_persiste...@vcs1-mixed.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-iclb7/igt@gem_ctx_persiste...@vcs1-mixed.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-iclb2/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-iclb7/igt@gem_exec_balan...@smoke.html * igt@gem_exec_create@basic: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111736]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-tglb7/igt@gem_exec_cre...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-tglb6/igt@gem_exec_cre...@basic.html * igt@gem_exec_create@madvise: - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#435]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-tglb7/igt@gem_exec_cre...@madvise.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-tglb3/igt@gem_exec_cre...@madvise.html * igt@gem_exec_gttfill@basic: - shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([fdo#111593]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-tglb2/igt@gem_exec_gttf...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-tglb8/igt@gem_exec_gttf...@basic.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +14 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-iclb3/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1: - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111677]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-tglb1/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-tglb3/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd1.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#112146]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-iclb5/igt@gem_exec_sched...@preemptive-hang-bsd.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_schedule@smoketest-vebox: - shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#707]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-tglb1/igt@gem_exec_sched...@smoketest-vebox.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-tglb3/igt@gem_exec_sched...@smoketest-vebox.html * igt@gem_exec_suspend@basic-s4-devices: - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#460]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-tglb1/igt@gem_exec_susp...@basic-s4-devices.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-tglb6/igt@gem_exec_susp...@basic-s4-devices.html * igt@gem_sync@basic-all: - shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#470] / [i915#472]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-tglb2/igt@gem_s...@basic-all.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/shard-tglb6/igt@gem_s...@basic-all.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#454]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-iclb1/igt@i915_pm...@dc6-psr.html [26]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/gem: Extend mmap support for lmem
== Series Details == Series: series starting with [CI,1/3] drm/i915/gem: Extend mmap support for lmem URL : https://patchwork.freedesktop.org/series/71538/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7661 -> Patchwork_15963 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15963 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15963, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15963: ### IGT changes ### Possible regressions * igt@i915_selftest@live_gem_contexts: - fi-kbl-x1275: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html Known issues Here are the changes found in Patchwork_15963 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-8700k: [PASS][2] -> [INCOMPLETE][3] ([i915#505]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_evict: - fi-bwr-2160:[PASS][4] -> [FAIL][5] ([i915#878]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-bwr-2160/igt@i915_selftest@live_evict.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-bwr-2160/igt@i915_selftest@live_evict.html * igt@i915_selftest@live_execlists: - fi-kbl-soraka: [PASS][6] -> [DMESG-FAIL][7] ([i915#656]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-kbl-soraka/igt@i915_selftest@live_execlists.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-kbl-soraka/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [PASS][8] -> [DMESG-FAIL][9] ([i915#722]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_mman: - fi-bxt-dsi: [PASS][10] -> [DMESG-WARN][11] ([i915#889]) +23 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-bxt-dsi/igt@i915_selftest@live_mman.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-bxt-dsi/igt@i915_selftest@live_mman.html * igt@i915_selftest@live_reset: - fi-bxt-dsi: [PASS][12] -> [DMESG-FAIL][13] ([i915#889]) +7 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-bxt-dsi/igt@i915_selftest@live_reset.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-bxt-dsi/igt@i915_selftest@live_reset.html Possible fixes * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6700k2: [INCOMPLETE][14] ([i915#671]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][16] ([i915#563]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-hsw-4770/igt@i915_selftest@live_blt.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_workarounds: - fi-icl-dsi: [DMESG-FAIL][18] -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-icl-dsi/igt@i915_selftest@live_workarounds.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-icl-dsi/igt@i915_selftest@live_workarounds.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][20] ([i915#704]) -> [SKIP][21] ([fdo#109271]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15963/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][23] ([i915#62] / [i915#92]) +7 similar issues [22]:
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add Wa_1407352427:icl,ehl (rev4)
On Wed, Jan 01, 2020 at 02:00:22AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add Wa_1407352427:icl,ehl (rev4)
> URL : https://patchwork.freedesktop.org/series/71403/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7659_full -> Patchwork_15958_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
>
Applied to dinq. Thanks Lionel for the review.
Matt
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_15958_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@gem_exec_schedule@pi-common-bsd1}:
> - shard-tglb: [PASS][1] -> [INCOMPLETE][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-tglb1/igt@gem_exec_sched...@pi-common-bsd1.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/shard-tglb5/igt@gem_exec_sched...@pi-common-bsd1.html
>
>
>
> ### Piglit changes ###
>
> Possible regressions
>
> * spec@ext_framebuffer_multisample_blit_scaled@blit-scaled samples=8 with
> gl_texture_2d_multisample_array (NEW):
> - {pig-hsw-4770r}:NOTRUN -> [WARN][3]
>[3]: None
>
>
> New tests
> -
>
> New tests have been introduced between CI_DRM_7659_full and
> Patchwork_15958_full:
>
> ### New Piglit tests (47) ###
>
> * shaders@glsl-derivs-abs:
> - Statuses : 1 fail(s)
> - Exec time: [0.13] s
>
> * shaders@glsl-uniform-struct:
> - Statuses : 1 fail(s)
> - Exec time: [0.10] s
>
> * spec@!opengl 1.1@depthstencil-default_fb-blit samples=4:
> - Statuses : 1 fail(s)
> - Exec time: [0.11] s
>
> * spec@!opengl 1.1@depthstencil-default_fb-clear samples=8:
> - Statuses : 1 fail(s)
> - Exec time: [0.10] s
>
> * spec@!opengl 1.1@depthstencil-default_fb-readpixels-24_8 samples=8:
> - Statuses : 1 fail(s)
> - Exec time: [0.07] s
>
> * spec@!opengl 1.1@depthstencil-default_fb-readpixels-float-and-ushort
> samples=4:
> - Statuses : 1 fail(s)
> - Exec time: [0.12] s
>
> * spec@!opengl 1.1@depthstencil-default_fb-readpixels-float-and-ushort
> samples=8:
> - Statuses : 1 fail(s)
> - Exec time: [0.08] s
>
> * spec@!opengl 1.1@fragment-center:
> - Statuses : 1 fail(s)
> - Exec time: [0.08] s
>
> * spec@!opengl 1.1@gl-1.1-read-pixels-after-display-list:
> - Statuses : 1 fail(s)
> - Exec time: [0.13] s
>
> * spec@!opengl 1.1@gl-1.1-xor-copypixels:
> - Statuses : 1 fail(s)
> - Exec time: [0.09] s
>
> * spec@!opengl 1.1@infinite-spot-light:
> - Statuses : 1 fail(s)
> - Exec time: [0.10] s
>
> * spec@!opengl 1.1@line-aa-width:
> - Statuses : 1 fail(s)
> - Exec time: [0.09] s
>
> * spec@!opengl 1.1@texture-al:
> - Statuses : 1 fail(s)
> - Exec time: [0.07] s
>
> * spec@arb_arrays_of_arrays@execution@ubo@fs-nonconst:
> - Statuses : 1 fail(s)
> - Exec time: [0.10] s
>
> * spec@arb_depth_buffer_float@depthstencil-render-miplevels 1024 d=z32f_s8:
> - Statuses : 1 fail(s)
> - Exec time: [0.29] s
>
> * spec@arb_depth_buffer_float@fbo-clear-formats:
> - Statuses : 1 fail(s)
> - Exec time: [0.15] s
>
> * spec@arb_texture_multisample@large-float-texture-fp16:
> - Statuses : 1 fail(s)
> - Exec time: [0.30] s
>
> * spec@arb_texture_multisample@texelfetch@4-fs-isampler2dms:
> - Statuses : 1 fail(s)
> - Exec time: [0.07] s
>
> * spec@ext_framebuffer_multisample@blit-multiple-render-targets 2:
> - Statuses : 1 fail(s)
> - Exec time: [0.12] s
>
> * spec@ext_framebuffer_multisample_blit_scaled@blit-scaled samples=8 with
> gl_texture_2d_multisample_array:
> - Statuses : 1 warn(s)
> - Exec time: [0.17] s
>
> *
> spec@glsl-1.10@execution@built-in-functions@fs-op-selection-bool-bvec4-bvec4:
> - Statuses : 1 fail(s)
> - Exec time: [0.12] s
>
> * spec@glsl-1.30@execution@fs-texturelod-miplevels-biased:
> - Statuses : 1 fail(s)
> - Exec time: [0.10] s
>
> *
> spec@glsl-1.30@execution@interpolation@interpolation-flat-gl_backcolor-flat-vertex:
> - Statuses : 1 fail(s)
> - Exec time: [0.12] s
>
> *
> spec@glsl-1.30@execution@interpolation@interpolation-none-other-flat-distance:
> - Statuses : 1 fail(s)
> - Exec time: [0.12] s
>
> *
> spec@glsl-1.30@execution@interpolation@interpolation-noperspective-gl_backsecondarycolor-flat-distance:
> - Statuses : 1 fail(s)
> - Exec time: [0.10] s
>
> *
> spec@glsl-1.30@execution@interpolation@interpolation-smooth-gl_frontcolor-smooth-distance:
> - Statuses : 1 fail(s)
> - Exec time: [0.11] s
>
> *
> spec@glsl-1.50@execution@variable-indexing@vs-output-array-float-index-wr-before-gs:
> -
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/3] drm/i915/gem: Extend mmap support for lmem
== Series Details == Series: series starting with [CI,1/3] drm/i915/gem: Extend mmap support for lmem URL : https://patchwork.freedesktop.org/series/71538/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5b09b1115138 drm/i915/gem: Extend mmap support for lmem fcac03df03c3 drm/i915/selftests: Extend fault handler selftests to all memory regions -:158: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #158: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:834: +#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24)) total: 0 errors, 0 warnings, 1 checks, 403 lines checked 422c6c94fa80 drm/i915/gem: Single page objects are naturally contiguous ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/3] drm/i915/gem: Extend mmap support for lmem
From: Abdiel Janulgue
Local memory objects are similar to our usual scatterlist, but instead
of using the struct page stored therein, we need to use the
sg->dma_address.
Signed-off-by: Abdiel Janulgue
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 16 +++--
drivers/gpu/drm/i915/i915_drv.h | 6 ++---
drivers/gpu/drm/i915/i915_mm.c | 30 +++-
3 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 905527ce2999..4caf7d750c34 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -216,6 +216,7 @@ static vm_fault_t i915_error_to_vmf_fault(int err)
case -ENOSPC: /* shmemfs allocation failure */
case -ENOMEM: /* our allocation failure */
+ case -ENXIO:
return VM_FAULT_OOM;
case 0:
@@ -236,11 +237,10 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
struct vm_area_struct *area = vmf->vma;
struct i915_mmap_offset *mmo = area->vm_private_data;
struct drm_i915_gem_object *obj = mmo->obj;
+ bool use_dma =
+ !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_STRUCT_PAGE);
int err;
- if (unlikely(!i915_gem_object_has_struct_page(obj)))
- return VM_FAULT_SIGBUS;
-
/* Sanity check that we allow writing into this object */
if (unlikely(i915_gem_object_is_readonly(obj) &&
area->vm_flags & VM_WRITE))
@@ -251,9 +251,9 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
goto out;
/* PTEs are revoked in obj->ops->put_pages() */
- err = remap_io_sg_page(area,
- area->vm_start, area->vm_end - area->vm_start,
- obj->mm.pages->sgl);
+ err = remap_io_sg(area,
+ area->vm_start, area->vm_end - area->vm_start,
+ obj->mm.pages->sgl, use_dma);
if (area->vm_flags & VM_WRITE) {
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
@@ -552,7 +552,9 @@ __assign_mmap_offset(struct drm_file *file,
}
if (mmap_type != I915_MMAP_TYPE_GTT &&
- !i915_gem_object_has_struct_page(obj)) {
+ !i915_gem_object_type_has(obj,
+ I915_GEM_OBJECT_HAS_STRUCT_PAGE |
+ I915_GEM_OBJECT_HAS_IOMEM)) {
err = -ENODEV;
goto out;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c7e3020e766..ccd632fecf36 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2017,9 +2017,9 @@ int i915_reg_read_ioctl(struct drm_device *dev, void
*data,
int remap_io_mapping(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn, unsigned long size,
struct io_mapping *iomap);
-int remap_io_sg_page(struct vm_area_struct *vma,
-unsigned long addr, unsigned long size,
-struct scatterlist *sgl);
+int remap_io_sg(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long size,
+ struct scatterlist *sgl, bool use_dma);
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
index 2998689e6d42..7f1680b4125e 100644
--- a/drivers/gpu/drm/i915/i915_mm.c
+++ b/drivers/gpu/drm/i915/i915_mm.c
@@ -35,6 +35,7 @@ struct remap_pfn {
pgprot_t prot;
struct sgt_iter sgt;
+ bool dma;
};
static int remap_pfn(pte_t *pte, unsigned long addr, void *data)
@@ -48,12 +49,15 @@ static int remap_pfn(pte_t *pte, unsigned long addr, void
*data)
return 0;
}
-static inline unsigned long sgt_pfn(const struct sgt_iter *sgt)
+static inline unsigned long sgt_pfn(const struct sgt_iter *sgt, bool use_dma)
{
+ if (use_dma)
+ return (sgt->dma + sgt->curr) >> PAGE_SHIFT;
+
return sgt->pfn + (sgt->curr >> PAGE_SHIFT);
}
-static int remap_sg_page(pte_t *pte, unsigned long addr, void *data)
+static int remap_sg(pte_t *pte, unsigned long addr, void *data)
{
struct remap_pfn *r = data;
@@ -62,12 +66,12 @@ static int remap_sg_page(pte_t *pte, unsigned long addr,
void *data)
/* Special PTE are not associated with any struct page */
set_pte_at(r->mm, addr, pte,
- pte_mkspecial(pfn_pte(sgt_pfn(>sgt), r->prot)));
+ pte_mkspecial(pfn_pte(sgt_pfn(>sgt, r->dma), r->prot)));
r->pfn++; /* track insertions in case we need to unwind later */
r->sgt.curr += PAGE_SIZE;
if (r->sgt.curr >= r->sgt.max)
- r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), false);
+ r->sgt =
[Intel-gfx] [CI 2/3] drm/i915/selftests: Extend fault handler selftests to all memory regions
From: Abdiel Janulgue
Instead of testing individually our new fault handlers, iterate over all
memory regions and test all from one interface.
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
.../drm/i915/gem/selftests/i915_gem_mman.c| 297 --
1 file changed, 209 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index cbf796da64e3..35a5d51674bf 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -9,6 +9,7 @@
#include "gt/intel_engine_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
+#include "gem/i915_gem_region.h"
#include "huge_gem_object.h"
#include "i915_selftest.h"
#include "selftests/i915_random.h"
@@ -725,114 +726,222 @@ static int igt_mmap_offset_exhaustion(void *arg)
goto out;
}
-#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
-static int igt_mmap(void *arg, enum i915_mmap_type type)
+static int gtt_set(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *i915 = arg;
- struct drm_i915_gem_object *obj;
- struct i915_mmap_offset *mmo;
- struct vm_area_struct *area;
- unsigned long addr;
- void *vaddr;
- int err = 0, i;
+ struct i915_vma *vma;
+ void __iomem *map;
+ int err = 0;
- if (!i915_ggtt_has_aperture(>ggtt))
- return 0;
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
- obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ intel_gt_pm_get(vma->vm->gt);
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
+ goto out;
+ }
+
+ memset_io(map, POISON_INUSE, obj->base.size);
+ i915_vma_unpin_iomap(vma);
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
- if (IS_ERR(vaddr)) {
- err = PTR_ERR(vaddr);
+out:
+ intel_gt_pm_put(vma->vm->gt);
+ return err;
+}
+
+static int gtt_check(struct drm_i915_gem_object *obj)
+{
+ struct i915_vma *vma;
+ void __iomem *map;
+ int err = 0;
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ intel_gt_pm_get(vma->vm->gt);
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
goto out;
}
- memset(vaddr, POISON_INUSE, PAGE_SIZE);
+
+ if (memchr_inv((void __force *)map, POISON_FREE, obj->base.size)) {
+ pr_err("%s: Write via mmap did not land in backing store
(GTT)\n",
+ obj->mm.region->name);
+ err = -EINVAL;
+ }
+ i915_vma_unpin_iomap(vma);
+
+out:
+ intel_gt_pm_put(vma->vm->gt);
+ return err;
+}
+
+static int wc_set(struct drm_i915_gem_object *obj)
+{
+ void *vaddr;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ memset(vaddr, POISON_INUSE, obj->base.size);
i915_gem_object_flush_map(obj);
i915_gem_object_unpin_map(obj);
- mmo = mmap_offset_attach(obj, type, NULL);
- if (IS_ERR(mmo)) {
- err = PTR_ERR(mmo);
- goto out;
+ return 0;
+}
+
+static int wc_check(struct drm_i915_gem_object *obj)
+{
+ void *vaddr;
+ int err = 0;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ if (memchr_inv(vaddr, POISON_FREE, obj->base.size)) {
+ pr_err("%s: Write via mmap did not land in backing store
(WC)\n",
+ obj->mm.region->name);
+ err = -EINVAL;
}
+ i915_gem_object_unpin_map(obj);
+
+ return err;
+}
+
+static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
+{
+ if (type == I915_MMAP_TYPE_GTT &&
+ !i915_ggtt_has_aperture(_i915(obj->base.dev)->ggtt))
+ return false;
+
+ if (type != I915_MMAP_TYPE_GTT &&
+ !i915_gem_object_type_has(obj,
+ I915_GEM_OBJECT_HAS_STRUCT_PAGE |
+ I915_GEM_OBJECT_HAS_IOMEM))
+ return false;
+
+ return true;
+}
+
+#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
+static int __igt_mmap(struct drm_i915_private *i915,
+ struct drm_i915_gem_object *obj,
+ enum i915_mmap_type type)
+{
+ struct i915_mmap_offset *mmo;
+ struct
[Intel-gfx] [CI 3/3] drm/i915/gem: Single page objects are naturally contiguous
Small objects that only occupy a single page are naturally contiguous,
so mark them as such and allow them the special abilities that come with
it.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index d50adac12249..1515384d7e0e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -107,7 +107,10 @@ void i915_gem_object_init_memory_region(struct
drm_i915_gem_object *obj,
{
INIT_LIST_HEAD(>mm.blocks);
obj->mm.region = intel_memory_region_get(mem);
+
obj->flags |= flags;
+ if (obj->base.size <= mem->min_page_size)
+ obj->flags |= I915_BO_ALLOC_CONTIGUOUS;
mutex_lock(>objects.lock);
--
2.25.0.rc0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/gem: Extend mmap support for lmem
== Series Details == Series: series starting with [CI,1/2] drm/i915/gem: Extend mmap support for lmem URL : https://patchwork.freedesktop.org/series/71537/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7661 -> Patchwork_15962 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15962 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15962, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15962: ### IGT changes ### Possible regressions * igt@i915_selftest@live_mman: - fi-gdg-551: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-gdg-551/igt@i915_selftest@live_mman.html - fi-skl-lmem:[PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-skl-lmem/igt@i915_selftest@live_mman.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-skl-lmem/igt@i915_selftest@live_mman.html Known issues Here are the changes found in Patchwork_15962 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@hdmi-crc-fast: - fi-icl-u2: [PASS][4] -> [FAIL][5] ([fdo#109635]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html Possible fixes * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6700k2: [INCOMPLETE][6] ([i915#671]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-skl-6600u: [DMESG-WARN][8] ([i915#889]) -> [PASS][9] +23 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-skl-6600u/igt@i915_pm_...@module-reload.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-skl-6600u/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][10] ([i915#563]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-hsw-4770/igt@i915_selftest@live_blt.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gt_lrc: - fi-skl-6600u: [DMESG-FAIL][12] ([i915#889]) -> [PASS][13] +7 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html * igt@i915_selftest@live_workarounds: - fi-icl-dsi: [DMESG-FAIL][14] -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-icl-dsi/igt@i915_selftest@live_workarounds.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-icl-dsi/igt@i915_selftest@live_workarounds.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][16] ([fdo#111407]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][18] ([i915#704]) -> [SKIP][19] ([fdo#109271]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-kbl-guc/igt@i915_pm_...@basic-rte.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][21] ([i915#62] / [i915#92]) +7 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7661/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15962/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html * igt@kms_flip@basic-flip-vs-wf_vblank: - fi-kbl-x1275: [DMESG-WARN][22] ([i915#62] / [i915#92]) -> [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [22]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add Wa_1407352427:icl,ehl (rev4)
== Series Details ==
Series: drm/i915: Add Wa_1407352427:icl,ehl (rev4)
URL : https://patchwork.freedesktop.org/series/71403/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7659_full -> Patchwork_15958_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15958_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_schedule@pi-common-bsd1}:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/shard-tglb1/igt@gem_exec_sched...@pi-common-bsd1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/shard-tglb5/igt@gem_exec_sched...@pi-common-bsd1.html
### Piglit changes ###
Possible regressions
* spec@ext_framebuffer_multisample_blit_scaled@blit-scaled samples=8 with
gl_texture_2d_multisample_array (NEW):
- {pig-hsw-4770r}:NOTRUN -> [WARN][3]
[3]: None
New tests
-
New tests have been introduced between CI_DRM_7659_full and
Patchwork_15958_full:
### New Piglit tests (47) ###
* shaders@glsl-derivs-abs:
- Statuses : 1 fail(s)
- Exec time: [0.13] s
* shaders@glsl-uniform-struct:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@!opengl 1.1@depthstencil-default_fb-blit samples=4:
- Statuses : 1 fail(s)
- Exec time: [0.11] s
* spec@!opengl 1.1@depthstencil-default_fb-clear samples=8:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@!opengl 1.1@depthstencil-default_fb-readpixels-24_8 samples=8:
- Statuses : 1 fail(s)
- Exec time: [0.07] s
* spec@!opengl 1.1@depthstencil-default_fb-readpixels-float-and-ushort
samples=4:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* spec@!opengl 1.1@depthstencil-default_fb-readpixels-float-and-ushort
samples=8:
- Statuses : 1 fail(s)
- Exec time: [0.08] s
* spec@!opengl 1.1@fragment-center:
- Statuses : 1 fail(s)
- Exec time: [0.08] s
* spec@!opengl 1.1@gl-1.1-read-pixels-after-display-list:
- Statuses : 1 fail(s)
- Exec time: [0.13] s
* spec@!opengl 1.1@gl-1.1-xor-copypixels:
- Statuses : 1 fail(s)
- Exec time: [0.09] s
* spec@!opengl 1.1@infinite-spot-light:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@!opengl 1.1@line-aa-width:
- Statuses : 1 fail(s)
- Exec time: [0.09] s
* spec@!opengl 1.1@texture-al:
- Statuses : 1 fail(s)
- Exec time: [0.07] s
* spec@arb_arrays_of_arrays@execution@ubo@fs-nonconst:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
* spec@arb_depth_buffer_float@depthstencil-render-miplevels 1024 d=z32f_s8:
- Statuses : 1 fail(s)
- Exec time: [0.29] s
* spec@arb_depth_buffer_float@fbo-clear-formats:
- Statuses : 1 fail(s)
- Exec time: [0.15] s
* spec@arb_texture_multisample@large-float-texture-fp16:
- Statuses : 1 fail(s)
- Exec time: [0.30] s
* spec@arb_texture_multisample@texelfetch@4-fs-isampler2dms:
- Statuses : 1 fail(s)
- Exec time: [0.07] s
* spec@ext_framebuffer_multisample@blit-multiple-render-targets 2:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* spec@ext_framebuffer_multisample_blit_scaled@blit-scaled samples=8 with
gl_texture_2d_multisample_array:
- Statuses : 1 warn(s)
- Exec time: [0.17] s
*
spec@glsl-1.10@execution@built-in-functions@fs-op-selection-bool-bvec4-bvec4:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* spec@glsl-1.30@execution@fs-texturelod-miplevels-biased:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
*
spec@glsl-1.30@execution@interpolation@interpolation-flat-gl_backcolor-flat-vertex:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
*
spec@glsl-1.30@execution@interpolation@interpolation-none-other-flat-distance:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
*
spec@glsl-1.30@execution@interpolation@interpolation-noperspective-gl_backsecondarycolor-flat-distance:
- Statuses : 1 fail(s)
- Exec time: [0.10] s
*
spec@glsl-1.30@execution@interpolation@interpolation-smooth-gl_frontcolor-smooth-distance:
- Statuses : 1 fail(s)
- Exec time: [0.11] s
*
spec@glsl-1.50@execution@variable-indexing@vs-output-array-float-index-wr-before-gs:
- Statuses : 1 fail(s)
- Exec time: [0.22] s
* spec@glsl-4.00@execution@built-in-functions@fs-notequal-dvec4-dvec4:
- Statuses : 1 fail(s)
- Exec time: [0.14] s
* spec@glsl-4.00@execution@built-in-functions@gs-greaterthanequal-dvec4-dvec4:
- Statuses : 1 fail(s)
- Exec time: [0.09] s
*
spec@glsl-4.10@execution@vs_in@vs-input-position-int_ivec4_array3-double_double_array2:
- Statuses : 1 fail(s)
- Exec time: [0.17] s
*
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/gem: Extend mmap support for lmem
== Series Details == Series: series starting with [CI,1/2] drm/i915/gem: Extend mmap support for lmem URL : https://patchwork.freedesktop.org/series/71537/ State : warning == Summary == $ dim checkpatch origin/drm-tip c269d4536b3a drm/i915/gem: Extend mmap support for lmem 68ca521ddb6d drm/i915/selftests: Extend fault handler selftests to all memory regions -:157: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #157: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:832: +#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24)) total: 0 errors, 0 warnings, 1 checks, 356 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/2] drm/i915/gem: Extend mmap support for lmem
From: Abdiel Janulgue
Local memory objects are similar to our usual scatterlist, but instead
of using the struct page stored therein, we need to use the
sg->dma_address.
Signed-off-by: Abdiel Janulgue
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 16 +++--
drivers/gpu/drm/i915/i915_drv.h | 6 ++---
drivers/gpu/drm/i915/i915_mm.c | 30 +++-
3 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 905527ce2999..4caf7d750c34 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -216,6 +216,7 @@ static vm_fault_t i915_error_to_vmf_fault(int err)
case -ENOSPC: /* shmemfs allocation failure */
case -ENOMEM: /* our allocation failure */
+ case -ENXIO:
return VM_FAULT_OOM;
case 0:
@@ -236,11 +237,10 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
struct vm_area_struct *area = vmf->vma;
struct i915_mmap_offset *mmo = area->vm_private_data;
struct drm_i915_gem_object *obj = mmo->obj;
+ bool use_dma =
+ !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_STRUCT_PAGE);
int err;
- if (unlikely(!i915_gem_object_has_struct_page(obj)))
- return VM_FAULT_SIGBUS;
-
/* Sanity check that we allow writing into this object */
if (unlikely(i915_gem_object_is_readonly(obj) &&
area->vm_flags & VM_WRITE))
@@ -251,9 +251,9 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
goto out;
/* PTEs are revoked in obj->ops->put_pages() */
- err = remap_io_sg_page(area,
- area->vm_start, area->vm_end - area->vm_start,
- obj->mm.pages->sgl);
+ err = remap_io_sg(area,
+ area->vm_start, area->vm_end - area->vm_start,
+ obj->mm.pages->sgl, use_dma);
if (area->vm_flags & VM_WRITE) {
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
@@ -552,7 +552,9 @@ __assign_mmap_offset(struct drm_file *file,
}
if (mmap_type != I915_MMAP_TYPE_GTT &&
- !i915_gem_object_has_struct_page(obj)) {
+ !i915_gem_object_type_has(obj,
+ I915_GEM_OBJECT_HAS_STRUCT_PAGE |
+ I915_GEM_OBJECT_HAS_IOMEM)) {
err = -ENODEV;
goto out;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c7e3020e766..ccd632fecf36 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2017,9 +2017,9 @@ int i915_reg_read_ioctl(struct drm_device *dev, void
*data,
int remap_io_mapping(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn, unsigned long size,
struct io_mapping *iomap);
-int remap_io_sg_page(struct vm_area_struct *vma,
-unsigned long addr, unsigned long size,
-struct scatterlist *sgl);
+int remap_io_sg(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long size,
+ struct scatterlist *sgl, bool use_dma);
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
index 2998689e6d42..7f1680b4125e 100644
--- a/drivers/gpu/drm/i915/i915_mm.c
+++ b/drivers/gpu/drm/i915/i915_mm.c
@@ -35,6 +35,7 @@ struct remap_pfn {
pgprot_t prot;
struct sgt_iter sgt;
+ bool dma;
};
static int remap_pfn(pte_t *pte, unsigned long addr, void *data)
@@ -48,12 +49,15 @@ static int remap_pfn(pte_t *pte, unsigned long addr, void
*data)
return 0;
}
-static inline unsigned long sgt_pfn(const struct sgt_iter *sgt)
+static inline unsigned long sgt_pfn(const struct sgt_iter *sgt, bool use_dma)
{
+ if (use_dma)
+ return (sgt->dma + sgt->curr) >> PAGE_SHIFT;
+
return sgt->pfn + (sgt->curr >> PAGE_SHIFT);
}
-static int remap_sg_page(pte_t *pte, unsigned long addr, void *data)
+static int remap_sg(pte_t *pte, unsigned long addr, void *data)
{
struct remap_pfn *r = data;
@@ -62,12 +66,12 @@ static int remap_sg_page(pte_t *pte, unsigned long addr,
void *data)
/* Special PTE are not associated with any struct page */
set_pte_at(r->mm, addr, pte,
- pte_mkspecial(pfn_pte(sgt_pfn(>sgt), r->prot)));
+ pte_mkspecial(pfn_pte(sgt_pfn(>sgt, r->dma), r->prot)));
r->pfn++; /* track insertions in case we need to unwind later */
r->sgt.curr += PAGE_SIZE;
if (r->sgt.curr >= r->sgt.max)
- r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), false);
+ r->sgt =
[Intel-gfx] [CI 2/2] drm/i915/selftests: Extend fault handler selftests to all memory regions
From: Abdiel Janulgue
Instead of testing individually our new fault handlers, iterate over all
memory regions and test all from one interface.
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
Cc: Chris Wilson
Cc: Joonas Lahtinen
Reported-by: kbuild test robot
---
.../drm/i915/gem/selftests/i915_gem_mman.c| 265 --
1 file changed, 187 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index cbf796da64e3..659c6c4ec924 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -9,6 +9,7 @@
#include "gt/intel_engine_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
+#include "gem/i915_gem_region.h"
#include "huge_gem_object.h"
#include "i915_selftest.h"
#include "selftests/i915_random.h"
@@ -725,44 +726,135 @@ static int igt_mmap_offset_exhaustion(void *arg)
goto out;
}
-#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
-static int igt_mmap(void *arg, enum i915_mmap_type type)
+static int gtt_set(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *i915 = arg;
- struct drm_i915_gem_object *obj;
- struct i915_mmap_offset *mmo;
- struct vm_area_struct *area;
- unsigned long addr;
- void *vaddr;
- int err = 0, i;
+ struct i915_vma *vma;
+ void __iomem *map;
+ int err = 0;
- if (!i915_ggtt_has_aperture(>ggtt))
- return 0;
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
- obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ intel_gt_pm_get(vma->vm->gt);
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
+ goto out;
+ }
+
+ memset_io(map, POISON_INUSE, obj->base.size);
+ i915_vma_unpin_iomap(vma);
+
+out:
+ intel_gt_pm_put(vma->vm->gt);
+ return err;
+}
+
+static int gtt_check(struct drm_i915_gem_object *obj)
+{
+ struct i915_vma *vma;
+ void __iomem *map;
+ int err = 0;
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
- if (IS_ERR(vaddr)) {
- err = PTR_ERR(vaddr);
+ intel_gt_pm_get(vma->vm->gt);
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
goto out;
}
- memset(vaddr, POISON_INUSE, PAGE_SIZE);
+
+ if (memchr_inv((void __force *)map, POISON_FREE, obj->base.size)) {
+ pr_err("Write via mmap did not land in backing store\n");
+ err = -EINVAL;
+ }
+ i915_vma_unpin_iomap(vma);
+
+out:
+ intel_gt_pm_put(vma->vm->gt);
+ return err;
+}
+
+static int wc_set(struct drm_i915_gem_object *obj)
+{
+ void *vaddr;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ memset(vaddr, POISON_INUSE, obj->base.size);
i915_gem_object_flush_map(obj);
i915_gem_object_unpin_map(obj);
- mmo = mmap_offset_attach(obj, type, NULL);
- if (IS_ERR(mmo)) {
- err = PTR_ERR(mmo);
- goto out;
+ return 0;
+}
+
+static int wc_check(struct drm_i915_gem_object *obj)
+{
+ void *vaddr;
+ int err = 0;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ if (memchr_inv(vaddr, POISON_FREE, obj->base.size)) {
+ pr_err("Write via mmap did not land in backing store\n");
+ err = -EINVAL;
}
+ i915_gem_object_unpin_map(obj);
+
+ return err;
+}
+
+static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
+{
+ if (type == I915_MMAP_TYPE_GTT &&
+ !i915_ggtt_has_aperture(_i915(obj->base.dev)->ggtt))
+ return false;
+
+ if (type != I915_MMAP_TYPE_GTT &&
+ !i915_gem_object_type_has(obj,
+ I915_GEM_OBJECT_HAS_STRUCT_PAGE |
+ I915_GEM_OBJECT_HAS_IOMEM))
+ return false;
+
+ return true;
+}
+
+#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
+static int __igt_mmap(struct drm_i915_private *i915,
+ struct drm_i915_gem_object *obj,
+ enum i915_mmap_type type)
+{
+ struct i915_mmap_offset *mmo;
+ struct vm_area_struct *area;
+ unsigned long addr;
+ int err, i;
+
+ if
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Media decompression support
== Series Details == Series: drm/i915/tgl: Media decompression support URL : https://patchwork.freedesktop.org/series/71535/ State : success == Summary == CI Bug Log - changes from CI_DRM_7660 -> Patchwork_15961 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/index.html Known issues Here are the changes found in Patchwork_15961 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-8700k: [PASS][1] -> [INCOMPLETE][2] ([i915#505]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-6700k2: [PASS][3] -> [INCOMPLETE][4] ([i915#671]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_gem_contexts: - fi-byt-n2820: [PASS][5] -> [DMESG-FAIL][6] ([i915#722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][7] ([i915#816]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [FAIL][9] ([fdo#103375]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [FAIL][11] ([fdo#111550]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_pm_rpm@module-reload: - fi-skl-6600u: [DMESG-WARN][13] ([i915#889]) -> [PASS][14] +23 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-6600u/igt@i915_pm_...@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-6600u/igt@i915_pm_...@module-reload.html - fi-skl-lmem:[DMESG-WARN][15] ([i915#889]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-lmem/igt@i915_pm_...@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-lmem/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][17] ([i915#553] / [i915#725]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-hsw-4770r/igt@i915_selftest@live_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-hsw-4770r/igt@i915_selftest@live_blt.html - fi-hsw-4770:[DMESG-FAIL][19] ([i915#725]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-hsw-4770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][21] ([fdo#112406]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-kbl-soraka/igt@i915_selftest@live_gt_heartbeat.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-kbl-soraka/igt@i915_selftest@live_gt_heartbeat.html * igt@i915_selftest@live_gt_lrc: - fi-skl-6600u: [DMESG-FAIL][23] ([i915#889]) -> [PASS][24] +7 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html * igt@i915_selftest@live_sanitycheck: - fi-skl-lmem:[INCOMPLETE][25] -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-lmem/igt@i915_selftest@live_sanitycheck.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15961/fi-skl-lmem/igt@i915_selftest@live_sanitycheck.html Warnings
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Media decompression support
== Series Details == Series: drm/i915/tgl: Media decompression support URL : https://patchwork.freedesktop.org/series/71535/ State : warning == Summary == $ dim checkpatch origin/drm-tip 33c7be81f878 drm/i915: Add support for non-power-of-2 FB plane alignment fdf7e1ca3344 drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned cdc1c53c61f4 drm/i915: Add debug message for FB plane[0].offset!=0 error 877d8123db86 drm/i915: Make sure plane dims are correct for UV CCS planes 3224c01082d0 drm/framebuffer: Format modifier for Intel Gen-12 media compression e101ef87bf8a drm/fb: Extend format_info member arrays to handle four planes 046f9d49ca43 drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: compressed buffers. Unlike render decompression, plane 6 and plane 7 do not -:128: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment #128: FILE: drivers/gpu/drm/i915/display/intel_display.c:2685: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: total: 0 errors, 2 warnings, 0 checks, 458 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Restore coarse power gating
On Tue, Dec 31, 2019 at 12:27:08PM +, Chris Wilson wrote:
> The coarse power gating was disabled as part of commit 2248a28384fe
> ("drm/i915/gen8+: Add RC6 CTX corruption WA") as a prelude to recover
> from the context corruption; the power gating itself has no direct
> impact on the RC6 context corruption. However, that recovery scheme was
> never implemented due to difficult corner cases, and so we no longer need
> to keep the power gating disabled.
>
> Fixes: 2248a28384fe ("drm/i915/gen8+: Add RC6 CTX corruption WA")
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/846
> Signed-off-by: Chris Wilson
> Cc: Imre Deak
> Cc: Mika Kuoppala
> Cc: Eero Tamminen
> Cc: Jon Bloomfield
Yes, the original reason to disable CPG doesn't apply imo any more:
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b7f122dccdca..85b565e69ad4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1657,8 +1657,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
>
> /* WaRsDisableCoarsePowerGating:skl,cnl */
> -#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> - IS_GEN_RANGE(dev_priv, 9, 10)
> +#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)
> \
> + (IS_CANNONLAKE(dev_priv) || \
> + IS_SKL_GT3(dev_priv) ||\
> + IS_SKL_GT4(dev_priv))
> +
>
> #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
> #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
> --
> 2.25.0.rc0
>
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/gem: Extend mmap support for lmem
== Series Details == Series: series starting with [CI,1/2] drm/i915/gem: Extend mmap support for lmem URL : https://patchwork.freedesktop.org/series/71534/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7660 -> Patchwork_15960 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15960 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15960, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15960: ### IGT changes ### Possible regressions * igt@i915_selftest@live_mman: - fi-gdg-551: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-gdg-551/igt@i915_selftest@live_mman.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-gdg-551/igt@i915_selftest@live_mman.html - fi-whl-u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-whl-u/igt@i915_selftest@live_mman.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-whl-u/igt@i915_selftest@live_mman.html - fi-ilk-650: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-ilk-650/igt@i915_selftest@live_mman.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-ilk-650/igt@i915_selftest@live_mman.html - fi-bsw-n3050: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-bsw-n3050/igt@i915_selftest@live_mman.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-bsw-n3050/igt@i915_selftest@live_mman.html - fi-hsw-4770:[PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-hsw-4770/igt@i915_selftest@live_mman.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-hsw-4770/igt@i915_selftest@live_mman.html - fi-skl-guc: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-guc/igt@i915_selftest@live_mman.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-skl-guc/igt@i915_selftest@live_mman.html - fi-skl-6700k2: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-skl-6700k2/igt@i915_selftest@live_mman.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-skl-6700k2/igt@i915_selftest@live_mman.html - fi-snb-2520m: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-snb-2520m/igt@i915_selftest@live_mman.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-snb-2520m/igt@i915_selftest@live_mman.html - fi-cfl-8700k: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-cfl-8700k/igt@i915_selftest@live_mman.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-cfl-8700k/igt@i915_selftest@live_mman.html - fi-hsw-peppy: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-hsw-peppy/igt@i915_selftest@live_mman.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-hsw-peppy/igt@i915_selftest@live_mman.html - fi-kbl-7500u: NOTRUN -> [INCOMPLETE][21] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-kbl-7500u/igt@i915_selftest@live_mman.html - fi-kbl-guc: [PASS][22] -> [INCOMPLETE][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-kbl-guc/igt@i915_selftest@live_mman.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-kbl-guc/igt@i915_selftest@live_mman.html - fi-bsw-kefka: [PASS][24] -> [INCOMPLETE][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-bsw-kefka/igt@i915_selftest@live_mman.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-bsw-kefka/igt@i915_selftest@live_mman.html - fi-bwr-2160:[PASS][26] -> [INCOMPLETE][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7660/fi-bwr-2160/igt@i915_selftest@live_mman.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-bwr-2160/igt@i915_selftest@live_mman.html - fi-kbl-r: NOTRUN -> [INCOMPLETE][28] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15960/fi-kbl-r/igt@i915_selftest@live_mman.html - fi-bdw-5557u: [PASS][29] -> [INCOMPLETE][30] [29]:
Re: [Intel-gfx] [PATCH 3/3] drm/i915/dumb: return the allocated memory size
Quoting Ramalingam C (2019-12-30 13:23:51)
> On successful allocation, instead returning the requested size
> return the total size of allocated pages.
>
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/i915_gem.c | 13 +++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 7f39df3fab7f..5a53de797852 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -241,7 +241,9 @@ i915_gem_dumb_create(struct drm_file *file,
> {
> enum intel_memory_type mem_type = INTEL_MEMORY_SYSTEM;
> int cpp = DIV_ROUND_UP(args->bpp, 8);
> + struct intel_memory_region *mr;
> u32 format;
> + int ret;
>
> switch (cpp) {
> case 1:
> @@ -270,8 +272,15 @@ i915_gem_dumb_create(struct drm_file *file,
> if (HAS_LMEM(to_i915(dev)))
> mem_type = INTEL_MEMORY_LOCAL;
>
> - return i915_gem_create(file, to_i915(dev), mem_type,
> - >size, >handle);
> + ret = i915_gem_create(file, to_i915(dev), mem_type,
> + >size, >handle);
> + if (ret)
> + goto out;
> +
> + mr = intel_memory_region_by_type(to_i915(dev), mem_type);
> + args->size = ALIGN(args->size, mr->min_page_size);
How? How did we create an object that was not a multiple of the minimum
page size?
(Besides you should be using obj->mm.region here rather than assuming,
so more rearrangement if this is the right approach.)
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/gem: Extend mmap support for lmem
== Series Details == Series: series starting with [CI,1/2] drm/i915/gem: Extend mmap support for lmem URL : https://patchwork.freedesktop.org/series/71534/ State : warning == Summary == $ dim checkpatch origin/drm-tip e69fb2d55ec0 drm/i915/gem: Extend mmap support for lmem 16126f545232 drm/i915/selftests: Add selftest for memory region PF handling -:141: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #141: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:817: +#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24)) total: 0 errors, 0 warnings, 1 checks, 333 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/fb: Extend format_info member arrays to handle four planes
From: Dhinakaran Pandiyan
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä
Cc: Matt Roper
Cc: Mika Kahola
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Imre Deak
Reviewed-by: Mika Kahola
---
include/drm/drm_fourcc.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
* triplet @char_per_block, @block_w, @block_h for better
* describing the pixel format.
*/
- u8 cpp[3];
+ u8 cpp[4];
/**
* @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
* information from their drm_mode_config.get_format_info hook
* if they want the core to be validating the pitch.
*/
- u8 char_per_block[3];
+ u8 char_per_block[4];
};
/**
@@ -113,7 +113,7 @@ struct drm_format_info {
* Block width in pixels, this is intended to be accessed through
* drm_format_info_block_width()
*/
- u8 block_w[3];
+ u8 block_w[4];
/**
* @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
* Block height in pixels, this is intended to be accessed through
* drm_format_info_block_height()
*/
- u8 block_h[3];
+ u8 block_h[4];
/** @hsub: Horizontal chroma subsampling factor */
u8 hsub;
--
2.23.1
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[Intel-gfx] [PATCH 1/7] drm/i915: Add support for non-power-of-2 FB plane alignment
At least one framebuffer plane on TGL - the UV plane of YUV semiplanar
FBs - requires a non-power-of-2 alignment, so add support for this. This
new alignment restriction applies only to an offset within an FB, so the
GEM buffer itself containing the FB must still be power-of-2 aligned.
Add a check for this (in practice plane 0, since the plane 0 offset must
be 0).
v2:
- Fix WARN check for alignment=0.
v3:
- Return error for alignment programming bugs. (Chris)
Cc: Chris Wilson
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_display.c | 24 +---
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index da5266e76738..6e4152770c15 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2194,6 +2194,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
return ERR_PTR(-EINVAL);
alignment = intel_surf_alignment(fb, 0);
+ if (WARN_ON(alignment && !is_power_of_2(alignment)))
+ return ERR_PTR(-EINVAL);
/* Note that the w/a also requires 64 PTE of padding following the
* bo. We currently fill all unused PTE with the shadow page and so
@@ -2432,9 +2434,6 @@ static u32 intel_compute_aligned_offset(struct
drm_i915_private *dev_priv,
unsigned int cpp = fb->format->cpp[color_plane];
u32 offset, offset_aligned;
- if (alignment)
- alignment--;
-
if (!is_surface_linear(fb, color_plane)) {
unsigned int tile_size, tile_width, tile_height;
unsigned int tile_rows, tiles, pitch_tiles;
@@ -2456,17 +2455,24 @@ static u32 intel_compute_aligned_offset(struct
drm_i915_private *dev_priv,
*x %= tile_width;
offset = (tile_rows * pitch_tiles + tiles) * tile_size;
- offset_aligned = offset & ~alignment;
+
+ offset_aligned = offset;
+ if (alignment)
+ offset_aligned = rounddown(offset_aligned, alignment);
intel_adjust_tile_offset(x, y, tile_width, tile_height,
tile_size, pitch_tiles,
offset, offset_aligned);
} else {
offset = *y * pitch + *x * cpp;
- offset_aligned = offset & ~alignment;
-
- *y = (offset & alignment) / pitch;
- *x = ((offset & alignment) - *y * pitch) / cpp;
+ offset_aligned = offset;
+ if (alignment) {
+ offset_aligned = rounddown(offset_aligned, alignment);
+ *y = (offset % alignment) / pitch;
+ *x = ((offset % alignment) - *y * pitch) / cpp;
+ } else {
+ *y = *x = 0;
+ }
}
return offset_aligned;
@@ -3738,6 +3744,8 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
intel_add_fb_offsets(, , plane_state, 0);
offset = intel_plane_compute_aligned_offset(, , plane_state, 0);
alignment = intel_surf_alignment(fb, 0);
+ if (WARN_ON(alignment && !is_power_of_2(alignment)))
+ return -EINVAL;
/*
* AUX surface offset is specified as the distance from the
--
2.23.1
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[Intel-gfx] [PATCH 0/7] drm/i915/tgl: Media decompression support
This is the second part of [1] with media decompression enabled. I left the third part with render decompression/color clear functionality for later - once we have the IGT test for it in place. Cc: Dhinakaran Pandiyan Cc: Radhakrishna Sripada Cc: Ville Syrjala Cc: Nanley G Chery Cc: Mika Kahola Cc: Matt Roper Dhinakaran Pandiyan (3): drm/framebuffer: Format modifier for Intel Gen-12 media compression drm/fb: Extend format_info member arrays to handle four planes drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine Imre Deak (4): drm/i915: Add support for non-power-of-2 FB plane alignment drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned drm/i915: Add debug message for FB plane[0].offset!=0 error drm/i915: Make sure plane dims are correct for UV CCS planes drivers/gpu/drm/i915/display/intel_display.c | 246 ++ drivers/gpu/drm/i915/display/intel_display.h | 1 + .../drm/i915/display/intel_display_types.h| 6 +- drivers/gpu/drm/i915/display/intel_sprite.c | 55 +++- drivers/gpu/drm/i915/i915_reg.h | 1 + include/drm/drm_fourcc.h | 8 +- include/uapi/drm/drm_fourcc.h | 13 + 7 files changed, 262 insertions(+), 68 deletions(-) -- 2.23.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/7] drm/i915: Add debug message for FB plane[0].offset!=0 error
Print a debug message if the FB plane[0] offset is not 0 as expected, to
help understainding an add FB IOCTL fail.
Cc: Chris Wilson
Cc: Ville Syrjälä
Cc: Mika Kahola
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bbc9cf288067..2c2450d3469b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16912,8 +16912,11 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
}
/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
- if (mode_cmd->offsets[0] != 0)
+ if (mode_cmd->offsets[0] != 0) {
+ DRM_DEBUG_KMS("plane 0 offset (0x%08x) must be 0\n",
+ mode_cmd->offsets[0]);
goto err;
+ }
drm_helper_mode_fill_fb_struct(_priv->drm, fb, mode_cmd);
--
2.23.1
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[Intel-gfx] [PATCH 7/7] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine
From: Dhinakaran Pandiyan
Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
support media decompression.
v2: Fix checkpatch warnings on code style (Lucas)
From DK:
Separate modifier array for planes that cannot decompress media (Ville)
v3: Support planar formats
v4: Switch plane order
v5:
- Use format block descriptors to get CCS subsampling calculation right
everywhere.
- Extend the plane state normal view array to accommodate 4 color planes.
- Use helpers to convert between main and CCS planes.
v6: Add missing packed YUV formats to the MC format list. (Yang)
v7: Align UV planes to tile-row size.
Cc: Nanley G Chery
Cc: Ville Syrjälä
Cc: Matt Roper
Cc: Yang A Shi
Cc: Radhakrishna Sripada
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
Signed-off-by: Imre Deak
Reviewed-by: Radhakrishna Sripada (v6)
---
drivers/gpu/drm/i915/display/intel_display.c | 176 ++
drivers/gpu/drm/i915/display/intel_display.h | 1 +
.../drm/i915/display/intel_display_types.h| 6 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 55 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
5 files changed, 188 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d5128e900660..da4db5052579 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1945,7 +1945,9 @@ static bool is_ccs_plane(const struct drm_framebuffer
*fb, int plane)
static bool is_gen12_ccs_modifier(u64 modifier)
{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+ return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+
}
static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
@@ -1978,8 +1980,7 @@ static int ccs_to_main_plane(const struct drm_framebuffer
*fb, int ccs_plane)
}
/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
-static int
-intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
+int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
{
if (is_ccs_modifier(fb->modifier))
return main_to_ccs_plane(fb, main_plane);
@@ -2021,6 +2022,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
return 128;
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (is_ccs_plane(fb, color_plane))
return 64;
/* fall through */
@@ -2171,6 +2173,10 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (is_semiplanar_uv_plane(fb, color_plane))
+ return intel_tile_row_size(fb, color_plane);
+ /* Fall-through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
@@ -2574,6 +2580,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2625,6 +2632,30 @@ static const struct drm_format_info gen12_ccs_formats[]
= {
{ .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
.char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
.hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_YUYV, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_YVYU, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_UYVY, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_VYUY, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_NV12, .num_planes = 4,
+ .char_per_block = { 1, 2, 1, 1 },
[Intel-gfx] [PATCH 2/7] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned
Currently the GGTT offset of a UV plane in a semiplanar YUV FB is tile
size (4kB) aligned. I noticed, that enforcing only this alignment leads
oddly to random memory corruptions on TGL while scanning out Y-tiled
FBs. This issue can be easily reproduced with a UV plane offset that is
not aligned to the plane's tile row size.
Some experiments showed the correct alignment to be tile row size
indeed. This also makes sense, since the de-tiling fence created for the
object - with its own stride and so "left" and "right" edge - applies to
all the planes in the FB, so each tile row of all planes should be tile
row aligned.
In fact BSpec requires this alignment since SKL. On SKL we may enforce
this due to the AUX plane x,y coords check, but on ICL and TGL we don't.
For now enforce this only on TGL; I can follow up with any necessary
change for ICL after more tests.
BSpec requires a stricter alignment for linear UV planes too (kind of a
tile row alignment), but it's unclear whether that's really needed
(couldn't be explained with the de-tiling fence as above) and enforcing
that could break existing user space; so avoid that too for now until
more tests.
v2:
- Clarify the commit log wrt. the address space the alignment applies to.
(Chris)
Cc: Chris Wilson
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Acked-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_display.c | 36 ++--
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6e4152770c15..bbc9cf288067 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1995,6 +1995,13 @@ intel_format_info_is_yuv_semiplanar(const struct
drm_format_info *info,
info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
}
+static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
+ color_plane == 1;
+}
+
static unsigned int
intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
{
@@ -2069,6 +2076,16 @@ static void intel_tile_dims(const struct drm_framebuffer
*fb, int color_plane,
*tile_height = intel_tile_height(fb, color_plane);
}
+static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ unsigned int tile_width, tile_height;
+
+ intel_tile_dims(fb, color_plane, _width, _height);
+
+ return fb->pitches[color_plane] * tile_height;
+}
+
unsigned int
intel_fb_align_height(const struct drm_framebuffer *fb,
int color_plane, unsigned int height)
@@ -2143,7 +2160,8 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
struct drm_i915_private *dev_priv = to_i915(fb->dev);
/* AUX_DIST needs only 4K alignment */
- if (is_aux_plane(fb, color_plane))
+ if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
+ is_ccs_plane(fb, color_plane))
return 4096;
switch (fb->modifier) {
@@ -2158,6 +2176,10 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ is_semiplanar_uv_plane(fb, color_plane))
+ return intel_tile_row_size(fb, color_plane);
+ /* Fall-through */
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
default:
@@ -2505,9 +2527,17 @@ static int intel_fb_offset_to_xy(int *x, int *y,
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
unsigned int height;
+ u32 alignment;
+
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ is_semiplanar_uv_plane(fb, color_plane))
+ alignment = intel_tile_row_size(fb, color_plane);
+ else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
+ alignment = intel_tile_size(dev_priv);
+ else
+ alignment = 0;
- if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
- fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
+ if (alignment != 0 && fb->offsets[color_plane] % alignment) {
DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
fb->offsets[color_plane], color_plane);
return -EINVAL;
--
2.23.1
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[Intel-gfx] [PATCH 5/7] drm/framebuffer: Format modifier for Intel Gen-12 media compression
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
v2: Update code comment describing the color plane order for YUV
semiplanar formats.
Cc: Nanley G Chery
Cc: Matt Roper
Cc: Ville Syrjälä
Cc: Mika Kahola
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
Signed-off-by: Imre Deak
Reviewed-by: Mika Kahola
---
include/uapi/drm/drm_fourcc.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..8bc0b31597d8 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.23.1
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[Intel-gfx] [PATCH 4/7] drm/i915: Make sure plane dims are correct for UV CCS planes
As intel_fb_plane_get_subsampling() returns the subsampling factor wrt.
its main plane, for a CCS plane we need to apply both the main and the
CCS plane's subsampling factor on the FB's dimensions to get the CCS
plane's dimensions.
Cc: Dhinakaran Pandiyan
Cc: Mika Kahola
Cc: Radhakrishna Sripada
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2c2450d3469b..d5128e900660 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2913,11 +2913,15 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int
ccs_plane, int x, int y)
static void
intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int
color_plane)
{
+ int main_plane = is_ccs_plane(fb, color_plane) ?
+ccs_to_main_plane(fb, color_plane) : 0;
+ int main_hsub, main_vsub;
int hsub, vsub;
+ intel_fb_plane_get_subsampling(_hsub, _vsub, fb, main_plane);
intel_fb_plane_get_subsampling(, , fb, color_plane);
- *w = fb->width / hsub;
- *h = fb->height / vsub;
+ *w = fb->width / main_hsub / hsub;
+ *h = fb->height / main_vsub / vsub;
}
/*
--
2.23.1
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[Intel-gfx] [CI 2/2] drm/i915/selftests: Add selftest for memory region PF handling
From: Abdiel Janulgue
Instead of testing individually our new fault handlers, iterate over all
memory regions and test all from one interface.
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
Cc: Chris Wilson
Cc: Joonas Lahtinen
Reported-by: kbuild test robot
---
.../drm/i915/gem/selftests/i915_gem_mman.c| 246 --
1 file changed, 171 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index cbf796da64e3..a7ef35117aa2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -9,6 +9,7 @@
#include "gt/intel_engine_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
+#include "gem/i915_gem_region.h"
#include "huge_gem_object.h"
#include "i915_selftest.h"
#include "selftests/i915_random.h"
@@ -725,44 +726,121 @@ static int igt_mmap_offset_exhaustion(void *arg)
goto out;
}
-#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
-static int igt_mmap(void *arg, enum i915_mmap_type type)
+static int gtt_set(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *i915 = arg;
- struct drm_i915_gem_object *obj;
- struct i915_mmap_offset *mmo;
- struct vm_area_struct *area;
- unsigned long addr;
- void *vaddr;
- int err = 0, i;
+ struct i915_vma *vma;
+ void __iomem *map;
+ int err = 0;
- if (!i915_ggtt_has_aperture(>ggtt))
- return 0;
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
- obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ intel_gt_pm_get(vma->vm->gt);
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
+ goto out;
+ }
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
- if (IS_ERR(vaddr)) {
- err = PTR_ERR(vaddr);
+ memset_io(map, POISON_INUSE, PAGE_SIZE);
+ i915_vma_unpin_iomap(vma);
+
+out:
+ intel_gt_pm_put(vma->vm->gt);
+ return err;
+}
+
+static int gtt_check(struct drm_i915_gem_object *obj)
+{
+ struct i915_vma *vma;
+ void __iomem *map;
+ int err = 0;
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ intel_gt_pm_get(vma->vm->gt);
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
goto out;
}
+
+ if (memchr_inv((void __force *)map, POISON_FREE, PAGE_SIZE)) {
+ pr_err("Write via mmap did not land in backing store\n");
+ err = -EINVAL;
+ }
+ i915_vma_unpin_iomap(vma);
+
+out:
+ intel_gt_pm_put(vma->vm->gt);
+ return err;
+}
+
+static int wc_set(struct drm_i915_gem_object *obj)
+{
+ void *vaddr;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
memset(vaddr, POISON_INUSE, PAGE_SIZE);
i915_gem_object_flush_map(obj);
i915_gem_object_unpin_map(obj);
- mmo = mmap_offset_attach(obj, type, NULL);
- if (IS_ERR(mmo)) {
- err = PTR_ERR(mmo);
- goto out;
+ return 0;
+}
+
+static int wc_check(struct drm_i915_gem_object *obj)
+{
+ void *vaddr;
+ int err = 0;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ if (memchr_inv(vaddr, POISON_FREE, PAGE_SIZE)) {
+ pr_err("Write via mmap did not land in backing store\n");
+ err = -EINVAL;
}
+ i915_gem_object_unpin_map(obj);
+
+ return err;
+}
+
+#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
+static int __igt_mmap(struct drm_i915_private *i915,
+ struct drm_i915_gem_object *obj,
+ enum i915_mmap_type type)
+{
+ struct i915_mmap_offset *mmo;
+ struct vm_area_struct *area;
+ unsigned long addr;
+ int err, i;
+
+ if (!i915_ggtt_has_aperture(>ggtt) &&
+ type == I915_MMAP_TYPE_GTT)
+ return 0;
+
+ err = wc_set(obj);
+ if (err == -ENXIO)
+ err = gtt_set(obj);
+ if (err)
+ return err;
+
+ mmo = mmap_offset_attach(obj, type, NULL);
+ if (IS_ERR(mmo))
+ return PTR_ERR(mmo);
addr = igt_mmap_node(i915, >vma_node, 0, PROT_WRITE, MAP_SHARED);
- if (IS_ERR_VALUE(addr)) {
- err = addr;
- goto out;
- }
+ if (IS_ERR_VALUE(addr))
+
[Intel-gfx] [CI 1/2] drm/i915/gem: Extend mmap support for lmem
From: Abdiel Janulgue
Local memory objects are similar to our usual scatterlist, but instead
of using the struct page stored therein, we need to use the
sg->dma_address.
Signed-off-by: Abdiel Janulgue
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 16 +---
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
drivers/gpu/drm/i915/i915_mm.c | 23 ++-
3 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 905527ce2999..4caf7d750c34 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -216,6 +216,7 @@ static vm_fault_t i915_error_to_vmf_fault(int err)
case -ENOSPC: /* shmemfs allocation failure */
case -ENOMEM: /* our allocation failure */
+ case -ENXIO:
return VM_FAULT_OOM;
case 0:
@@ -236,11 +237,10 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
struct vm_area_struct *area = vmf->vma;
struct i915_mmap_offset *mmo = area->vm_private_data;
struct drm_i915_gem_object *obj = mmo->obj;
+ bool use_dma =
+ !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_STRUCT_PAGE);
int err;
- if (unlikely(!i915_gem_object_has_struct_page(obj)))
- return VM_FAULT_SIGBUS;
-
/* Sanity check that we allow writing into this object */
if (unlikely(i915_gem_object_is_readonly(obj) &&
area->vm_flags & VM_WRITE))
@@ -251,9 +251,9 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
goto out;
/* PTEs are revoked in obj->ops->put_pages() */
- err = remap_io_sg_page(area,
- area->vm_start, area->vm_end - area->vm_start,
- obj->mm.pages->sgl);
+ err = remap_io_sg(area,
+ area->vm_start, area->vm_end - area->vm_start,
+ obj->mm.pages->sgl, use_dma);
if (area->vm_flags & VM_WRITE) {
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
@@ -552,7 +552,9 @@ __assign_mmap_offset(struct drm_file *file,
}
if (mmap_type != I915_MMAP_TYPE_GTT &&
- !i915_gem_object_has_struct_page(obj)) {
+ !i915_gem_object_type_has(obj,
+ I915_GEM_OBJECT_HAS_STRUCT_PAGE |
+ I915_GEM_OBJECT_HAS_IOMEM)) {
err = -ENODEV;
goto out;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c2348272e211..5361a3a2a659 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2015,9 +2015,9 @@ int i915_reg_read_ioctl(struct drm_device *dev, void
*data,
int remap_io_mapping(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn, unsigned long size,
struct io_mapping *iomap);
-int remap_io_sg_page(struct vm_area_struct *vma,
-unsigned long addr, unsigned long size,
-struct scatterlist *sgl);
+int remap_io_sg(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long size,
+ struct scatterlist *sgl, bool use_dma);
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
index 2998689e6d42..cb891914ae21 100644
--- a/drivers/gpu/drm/i915/i915_mm.c
+++ b/drivers/gpu/drm/i915/i915_mm.c
@@ -35,6 +35,7 @@ struct remap_pfn {
pgprot_t prot;
struct sgt_iter sgt;
+ bool use_dma;
};
static int remap_pfn(pte_t *pte, unsigned long addr, void *data)
@@ -53,7 +54,7 @@ static inline unsigned long sgt_pfn(const struct sgt_iter
*sgt)
return sgt->pfn + (sgt->curr >> PAGE_SHIFT);
}
-static int remap_sg_page(pte_t *pte, unsigned long addr, void *data)
+static int remap_sg(pte_t *pte, unsigned long addr, void *data)
{
struct remap_pfn *r = data;
@@ -67,7 +68,7 @@ static int remap_sg_page(pte_t *pte, unsigned long addr, void
*data)
r->sgt.curr += PAGE_SIZE;
if (r->sgt.curr >= r->sgt.max)
- r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), false);
+ r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), r->use_dma);
return 0;
}
@@ -108,30 +109,34 @@ int remap_io_mapping(struct vm_area_struct *vma,
}
/**
- * remap_io_sg_page - remap an IO mapping to userspace
+ * remap_io_sg- remap an IO mapping to userspace
* @vma: user vma to map to
* @addr: target user address to start at
* @size: size of map area
* @sgl: Start sg entry
+ * @use_dma: Use stored dma address or pfn
*
* Note: this is only safe if the mm semaphore is held when called.
*/
-int remap_io_sg_page(struct vm_area_struct *vma,
-unsigned
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: save state of AUD_FREQ_CNTRL on all gen9+ platforms
== Series Details == Series: drm/i915: save state of AUD_FREQ_CNTRL on all gen9+ platforms URL : https://patchwork.freedesktop.org/series/71527/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657_full -> Patchwork_15955_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_7657_full and Patchwork_15955_full: ### New Piglit tests (39) ### * shaders@glsl-fs-ceil: - Statuses : 1 fail(s) - Exec time: [0.10] s * shaders@glsl-fs-discard-01: - Statuses : 1 fail(s) - Exec time: [0.11] s * shaders@glsl-fs-floor: - Statuses : 1 fail(s) - Exec time: [0.13] s * shaders@glsl-fs-if-texture2d-discard: - Statuses : 1 fail(s) - Exec time: [0.12] s * shaders@glsl-fs-log: - Statuses : 1 fail(s) - Exec time: [0.14] s * spec@!opengl 1.0@gl-1.0-no-op-paths: - Statuses : 1 fail(s) - Exec time: [0.16] s * spec@!opengl 1.1@depthstencil-default_fb-blit samples=2: - Statuses : 1 fail(s) - Exec time: [0.18] s * spec@!opengl 1.1@depthstencil-default_fb-clear samples=4: - Statuses : 1 fail(s) - Exec time: [0.13] s * spec@!opengl 1.1@depthstencil-default_fb-drawpixels-32f_24_8_rev: - Statuses : 1 fail(s) - Exec time: [0.08] s * spec@!opengl 1.1@depthstencil-default_fb-drawpixels-float-and-ushort: - Statuses : 1 fail(s) - Exec time: [0.09] s * spec@!opengl 1.1@depthstencil-default_fb-readpixels-32f_24_8_rev samples=4: - Statuses : 1 fail(s) - Exec time: [0.09] s * spec@!opengl 1.1@dlist-fdo3129-01: - Statuses : 1 fail(s) - Exec time: [0.13] s * spec@!opengl 3.2@layered-rendering@clear-color-all-types 3d single_level: - Statuses : 1 fail(s) - Exec time: [0.06] s * spec@amd_shader_trinary_minmax@execution@built-in-functions@fs-mid3-int-int-int: - Statuses : 1 fail(s) - Exec time: [0.16] s * spec@arb_copy_image@arb_copy_image-targets gl_texture_1d 32 1 1 gl_texture_rectangle 32 32 1 11 0 0 5 13 0 14 1 1: - Statuses : 1 fail(s) - Exec time: [0.15] s * spec@arb_framebuffer_object@framebuffer-blit-levels draw rgba: - Statuses : 1 fail(s) - Exec time: [0.11] s * spec@arb_gpu_shader_fp64@execution@built-in-functions@gs-greaterthan-dvec3-dvec3: - Statuses : 1 fail(s) - Exec time: [0.10] s * spec@arb_shader_image_load_store@restrict: - Statuses : 1 fail(s) - Exec time: [0.12] s * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 32 42 1 8 3: - Statuses : 1 fail(s) - Exec time: [0.10] s * spec@arb_texture_multisample@texelfetch@2-fs-usampler2dmsarray: - Statuses : 1 fail(s) - Exec time: [0.10] s * spec@arb_texture_multisample@texelfetch@4-fs-isampler2dms: - Statuses : 1 fail(s) - Exec time: [0.08] s * spec@arb_texture_query_levels@execution@vs-maxlevel: - Statuses : 1 fail(s) - Exec time: [0.09] s * spec@arb_texture_query_lod@execution@fs-texturequerylod-nearest-biased: - Statuses : 1 fail(s) - Exec time: [0.12] s * spec@arb_texture_rectangle@texwrap rect proj: - Statuses : 1 fail(s) - Exec time: [0.11] s * spec@ext_framebuffer_multisample@alpha-to-one-msaa-disabled 2: - Statuses : 1 fail(s) - Exec time: [0.24] s * spec@ext_framebuffer_multisample@interpolation 4 non-centroid-disabled: - Statuses : 1 fail(s) - Exec time: [0.12] s * spec@ext_framebuffer_object@fbo-cubemap: - Statuses : 1 fail(s) - Exec time: [0.12] s * spec@glsl-1.10@execution@vs-nested-return-sibling-if: - Statuses : 1 fail(s) - Exec time: [0.16] s * spec@glsl-1.30@execution@interpolation@interpolation-noperspective-gl_backsecondarycolor-smooth-none: - Statuses : 1 fail(s) - Exec time: [0.09] s * spec@glsl-1.30@execution@interpolation@interpolation-noperspective-other-flat-fixed: - Statuses : 1 fail(s) - Exec time: [0.15] s * spec@glsl-1.30@execution@interpolation@interpolation-smooth-gl_backsecondarycolor-flat-fixed: - Statuses : 1 fail(s) - Exec time: [0.11] s * spec@glsl-1.30@execution@tex-miplevel-selection textureprojgrad 2drectshadow: - Statuses : 1 fail(s) - Exec time: [0.08] s * spec@glsl-1.40@execution@texturesize@fs-texturesize-isampler1darray: - Statuses : 1 fail(s) - Exec time: [0.12] s * spec@glsl-4.00@execution@built-in-functions@fs-greaterthan-dvec4-dvec4: - Statuses : 1 fail(s) - Exec time: [0.11] s * spec@glsl-4.20@execution@vs_in@vs-input-position-byte_ivec2-double_dvec3: - Statuses : 1 fail(s) - Exec time: [0.17] s * spec@glsl-4.30@execution@built-in-functions@cs-lessthan-ivec4-ivec4: - Statuses : 1 fail(s) - Exec time: [0.13] s * spec@glsl-4.30@execution@built-in-functions@cs-op-eq-float-float-using-if: - Statuses : 1 fail(s) - Exec time: [0.15] s *
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Introduce remap_io_sg() to prefault discontiguous objects
== Series Details == Series: drm/i915: Introduce remap_io_sg() to prefault discontiguous objects URL : https://patchwork.freedesktop.org/series/71530/ State : success == Summary == CI Bug Log - changes from CI_DRM_7659 -> Patchwork_15959 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/index.html Known issues Here are the changes found in Patchwork_15959 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [TIMEOUT][2] ([i915#816]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[PASS][3] -> [DMESG-FAIL][4] ([i915#553] / [i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-hsw-4770/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#656]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-kbl-soraka/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/fi-kbl-soraka/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_objects: - fi-bwr-2160:[PASS][7] -> [FAIL][8] ([i915#878]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-bwr-2160/igt@i915_selftest@live_objects.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/fi-bwr-2160/igt@i915_selftest@live_objects.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111096] / [i915#323]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6700k2: [INCOMPLETE][11] ([i915#671]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html Warnings * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15959/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 [i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#878]: https://gitlab.freedesktop.org/drm/intel/issues/878 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 45) -- Additional (4): fi-skl-6770hq fi-skl-lmem fi-ivb-3770 fi-skl-6600u Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7659 -> Patchwork_15959 CI-20190529: 20190529 CI_DRM_7659: bc7f03590ed801bb911de587835ff9547ae63fbc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5356: 62146738c68abfa7497b023a049163932f5a9aa0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15959: 8917f528d0ded636f401a29e06a63bc174f71a8a @ git://anongit.freedesktop.org/gfx-ci/linux
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Limit audio CDCLK>=2*BCLK constraint back to GLK only (rev2)
== Series Details == Series: drm/i915: Limit audio CDCLK>=2*BCLK constraint back to GLK only (rev2) URL : https://patchwork.freedesktop.org/series/71525/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7657_full -> Patchwork_15954_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15954_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15954_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15954_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@preempt-queue-contexts-vebox: - shard-iclb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb4/igt@gem_exec_sched...@preempt-queue-contexts-vebox.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-iclb8/igt@gem_exec_sched...@preempt-queue-contexts-vebox.html Known issues Here are the changes found in Patchwork_15954_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-kbl6/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_persistence@vcs1-mixed-process: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@gem_ctx_persiste...@vcs1-mixed-process.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-iclb7/igt@gem_ctx_persiste...@vcs1-mixed-process.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_eio@kms: - shard-glk: [PASS][9] -> [INCOMPLETE][10] ([i915#58] / [k.org#198133]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-glk8/igt@gem_...@kms.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-glk3/igt@gem_...@kms.html - shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([i915#476]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb7/igt@gem_...@kms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-tglb2/igt@gem_...@kms.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#110854]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@gem_exec_balan...@smoke.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-iclb7/igt@gem_exec_balan...@smoke.html * igt@gem_exec_reloc@basic-active: - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#472]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb6/igt@gem_exec_re...@basic-active.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-tglb8/igt@gem_exec_re...@basic-active.html * igt@gem_exec_reloc@basic-gtt-read-active: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#109]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-skl5/igt@gem_exec_re...@basic-gtt-read-active.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-skl3/igt@gem_exec_re...@basic-gtt-read-active.html * igt@gem_exec_reuse@single: - shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#435]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb1/igt@gem_exec_re...@single.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-tglb6/igt@gem_exec_re...@single.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-vebox: - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([fdo#111606] / [fdo#111677]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb3/igt@gem_exec_sched...@preempt-queue-contexts-chain-vebox.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/shard-tglb8/igt@gem_exec_sched...@preempt-queue-contexts-chain-vebox.html * igt@gem_exec_schedule@preempt-queue-vebox: - shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([fdo#111677]) [23]:
[Intel-gfx] [CI] drm/i915: Introduce remap_io_sg() to prefault discontiguous objects
From: Abdiel Janulgue
Provide a way to set the PTE within apply_page_range for discontiguous
objects in addition to the existing method of just incrementing the pfn
for a page range.
Fixes: cc662126b413 ("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET")
Signed-off-by: Abdiel Janulgue
Cc: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 29
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_mm.c | 59
3 files changed, 72 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 879fff8adc48..b4adde2b8354 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -236,42 +236,33 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf)
struct vm_area_struct *area = vmf->vma;
struct i915_mmap_offset *mmo = area->vm_private_data;
struct drm_i915_gem_object *obj = mmo->obj;
- unsigned long i, size = area->vm_end - area->vm_start;
- bool write = area->vm_flags & VM_WRITE;
- vm_fault_t ret = VM_FAULT_SIGBUS;
int err;
if (!i915_gem_object_has_struct_page(obj))
- return ret;
+ return VM_FAULT_SIGBUS;
/* Sanity check that we allow writing into this object */
- if (i915_gem_object_is_readonly(obj) && write)
- return ret;
+ if (i915_gem_object_is_readonly(obj) && area->vm_flags & VM_WRITE)
+ return VM_FAULT_SIGBUS;
err = i915_gem_object_pin_pages(obj);
if (err)
- return i915_error_to_vmf_fault(err);
+ goto out;
/* PTEs are revoked in obj->ops->put_pages() */
- for (i = 0; i < size >> PAGE_SHIFT; i++) {
- struct page *page = i915_gem_object_get_page(obj, i);
-
- ret = vmf_insert_pfn(area,
-(unsigned long)area->vm_start + i *
PAGE_SIZE,
-page_to_pfn(page));
- if (ret != VM_FAULT_NOPAGE)
- break;
- }
+ err = remap_io_sg_page(area,
+ area->vm_start, area->vm_end - area->vm_start,
+ obj->mm.pages->sgl);
- if (write) {
+ if (area->vm_flags & VM_WRITE) {
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
- obj->cache_dirty = true; /* XXX flush after PAT update? */
obj->mm.dirty = true;
}
i915_gem_object_unpin_pages(obj);
- return ret;
+out:
+ return i915_error_to_vmf_fault(err);
}
static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7f122dccdca..c2348272e211 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2015,6 +2015,9 @@ int i915_reg_read_ioctl(struct drm_device *dev, void
*data,
int remap_io_mapping(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn, unsigned long size,
struct io_mapping *iomap);
+int remap_io_sg_page(struct vm_area_struct *vma,
+unsigned long addr, unsigned long size,
+struct scatterlist *sgl);
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
index 318562ce64c0..2998689e6d42 100644
--- a/drivers/gpu/drm/i915/i915_mm.c
+++ b/drivers/gpu/drm/i915/i915_mm.c
@@ -33,6 +33,8 @@ struct remap_pfn {
struct mm_struct *mm;
unsigned long pfn;
pgprot_t prot;
+
+ struct sgt_iter sgt;
};
static int remap_pfn(pte_t *pte, unsigned long addr, void *data)
@@ -46,6 +48,30 @@ static int remap_pfn(pte_t *pte, unsigned long addr, void
*data)
return 0;
}
+static inline unsigned long sgt_pfn(const struct sgt_iter *sgt)
+{
+ return sgt->pfn + (sgt->curr >> PAGE_SHIFT);
+}
+
+static int remap_sg_page(pte_t *pte, unsigned long addr, void *data)
+{
+ struct remap_pfn *r = data;
+
+ if (GEM_WARN_ON(!r->sgt.pfn))
+ return -EINVAL;
+
+ /* Special PTE are not associated with any struct page */
+ set_pte_at(r->mm, addr, pte,
+ pte_mkspecial(pfn_pte(sgt_pfn(>sgt), r->prot)));
+ r->pfn++; /* track insertions in case we need to unwind later */
+
+ r->sgt.curr += PAGE_SIZE;
+ if (r->sgt.curr >= r->sgt.max)
+ r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), false);
+
+ return 0;
+}
+
/**
* remap_io_mapping - remap an IO mapping to userspace
* @vma: user vma to map to
@@ -80,3 +106,36 @@ int remap_io_mapping(struct vm_area_struct *vma,
return 0;
}
+
+/**
+ * remap_io_sg_page - remap an IO mapping to userspace
+ * @vma: user vma to map to
+ *
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add Wa_1407352427:icl,ehl (rev4)
== Series Details == Series: drm/i915: Add Wa_1407352427:icl,ehl (rev4) URL : https://patchwork.freedesktop.org/series/71403/ State : success == Summary == CI Bug Log - changes from CI_DRM_7659 -> Patchwork_15958 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/index.html Known issues Here are the changes found in Patchwork_15958 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770:[PASS][1] -> [DMESG-FAIL][2] ([i915#553] / [i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-hsw-4770/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-kbl-soraka: [PASS][3] -> [DMESG-FAIL][4] ([i915#656]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-kbl-soraka/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-kbl-soraka/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-byt-n2820: [PASS][5] -> [DMESG-FAIL][6] ([i915#722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gt_heartbeat: - fi-kbl-guc: [PASS][7] -> [FAIL][8] ([i915#878]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-kbl-guc/igt@i915_selftest@live_gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-kbl-guc/igt@i915_selftest@live_gt_heartbeat.html * igt@i915_selftest@live_requests: - fi-whl-u: [PASS][9] -> [FAIL][10] ([i915#878]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-whl-u/igt@i915_selftest@live_requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-whl-u/igt@i915_selftest@live_requests.html Possible fixes * igt@i915_module_load@reload-with-fault-injection: - fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html - fi-cfl-8700k: [INCOMPLETE][13] ([i915#505]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html Warnings * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6700k2: [INCOMPLETE][15] ([i915#671]) -> [DMESG-WARN][16] ([i915#889]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [INCOMPLETE][18] ([i915#879]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-kbl-x1275/igt@i915_module_l...@reload-with-fault-injection.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-kbl-x1275/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][19] ([i915#770]) -> [DMESG-FAIL][20] ([i915#725]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-hsw-4770r/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15958/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7659/fi-kbl-x1275/igt@prime_v...@basic-fence-flip.html [24]:
[Intel-gfx] [PATCH v3] drm/i915: Add Wa_1407352427:icl,ehl
The workaround database now indicates we need to disable psdunit clock
gating as well.
v3:
- Rebase on top of other workarounds that have landed.
- Restrict cc:stable tag to 5.2+ since that's when ICL was first
officially supported.
Bspec: 32354
Bspec: 33450
Bspec: 33451
Suggested-by: Lionel Landwerlin
Cc: sta...@vger.kernel.org # v5.2+
Cc: Lionel Landwerlin
Cc: Lucas De Marchi
Cc: Matt Atwood
Signed-off-by: Matt Roper
Acked-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 030a3f3e69af..cf770793be54 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4183,6 +4183,7 @@ enum {
#define UNSLICE_UNIT_LEVEL_CLKGATE2_MMIO(0x94e4)
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
+#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
#define CGPSF_CLKGATE_DIS(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d3dd80db8813..148ac455dfa7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6607,6 +6607,9 @@ static void icl_init_clock_gating(struct drm_i915_private
*dev_priv)
intel_uncore_rmw(_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE,
0, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
+ /* Wa_1407352427:icl,ehl */
+ intel_uncore_rmw(_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
+0, PSDUNIT_CLKGATE_DIS);
}
static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.23.0
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Add Wa_1407352427:icl,ehl (rev3)
== Series Details == Series: drm/i915: Add Wa_1407352427:icl,ehl (rev3) URL : https://patchwork.freedesktop.org/series/71403/ State : failure == Summary == Applying: drm/i915: Add Wa_1407352427:icl,ehl Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_reg.h M drivers/gpu/drm/i915/intel_pm.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_pm.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_pm.c Auto-merging drivers/gpu/drm/i915/i915_reg.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Add Wa_1407352427:icl,ehl When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Assume future platforms will inherit TGL's SFC capability
On Tue, Dec 31, 2019 at 09:17:41AM -0800, Lucas De Marchi wrote:
> On Thu, Dec 26, 2019 at 03:05:41PM -0800, Matt Roper wrote:
> > On Thu, Dec 26, 2019 at 02:23:49PM -0800, Lucas De Marchi wrote:
> > > On Tue, Dec 24, 2019 at 03:15:21PM -0800, Matt Roper wrote:
> > > > Our usual i915 convention is to assume that future platforms will follow
> > > > the same behavior as the latest platform of today. The VDBOX/SFC
> > > > capabilities described here don't seem like something that should be
> > > > specific to TGL, so let's future-proof by making the test apply to all
> > > > gen12+ platforms.
> > > >
> > > > Cc: Lucas De Marchi
> > > > Signed-off-by: Matt Roper
> > > > ---
> > > > drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > > index 1acb5db77431..bb709a08bd3c 100644
> > > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > > @@ -1093,7 +1093,7 @@ void intel_device_info_init_mmio(struct
> > > > drm_i915_private *dev_priv)
> > > > * hooked up to an SFC (Scaler & Format Converter) unit.
> > > > * In TGL each VDBOX has access to an SFC.
> > > > */
> > > > - if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0)
> > > > + if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 ==
> > > > 0)
> > > > RUNTIME_INFO(dev_priv)->vdbox_sfc_access |=
> > > > BIT(i);
> > >
> > > but why are we even doing this instead of initiliazing them at compile
> > > time on the device_info? If it's fused off, then whatever is set in
> > > vdbox_sfc_access bit shouldn't matter... or if the code making use of
> > > this doesn't check for engine availability, then this part of the
> > > function could just disable the bit of whatever is fused off, regardless
> > > if it's ice lake, tiger lake or whatever.
> >
> > I'm not sure; it looks like among other things we send this bitmask
> > directly to the GuC, so I'm not really comfortable making the assumption
> > that all users of the mask will pay attention to whether the engine is
> > fused off or not, even if that turns out to be true for the i915 usage.
> >
> > I could switch this to being initialized statically and then modified
> > here if an engine is fused off. In that case should this move out of
> > RUNTIME_INFO() and back to INTEL_INFO()? Honestly I've never really
> > understood why we have those separated given that we still ignore the
> > const and modify INTEL_INFO at runtime in several places.
>
> hummn... true, there's this problem of not being able to initialize it
> statically in one place and possibly modify it later.
>
> We can't move it to INTEL_INFO. Anything that can be modified in runtime
> needs to be inside the runtime_info, not info. I think the goal with the
> separation was to make it explicit what are the fields that can be
> changed in runtime. We really can't change `info` since its static const
> that can be shared (think binding the driver to more than one device).
> It didn't matter much in the past since we were limited to 1.
That's what I thought...but it still seems we do in a handful of places
which is what I find confusing. I.e., there are several places we use
mkwrite_device_info(dev_priv) to cast away the const-ness of the
INTEL_INFO so that we can adjust things based on runtime conditions
(fuse values, VTd active, lack of stolen memory, etc.).
I had assumed mkwrite_device_info() was some kind of transitional thing
before the separation of INTEL_INFO and RUNTIME_INFO was complete, but
it seems like it's sticking around and actually growing in use?
>
> And I think the reason to have the runtime_info const and discard it here
> is because it should be in fact treated as const in all places except on
> initialization: we don't want accidental changes of that struct.
>
> So... I think there may be a better solution here, but I don't think
> it's important enough to block this: it's always better to be consistent
> to be able to refactor this when the needs arrive.
>
>
> Reviewed-by: Lucas De Marchi
Thanks for the review. Applied to dinq.
Matt
>
> Lucas De Marchi
>
> >
> >
> > Matt
> >
> > >
> > > Lucas De Marchi
> > >
> > >
> > > > }
> > > > DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n",
> > > > --
> > > > 2.23.0
> > > >
> > > > ___
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Assume future platforms will inherit TGL's SFC capability (rev2)
On Fri, Dec 27, 2019 at 01:52:12PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/tgl: Assume future platforms will inherit TGL's SFC > capability (rev2) > URL : https://patchwork.freedesktop.org/series/71371/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7637_full -> Patchwork_15927_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_15927_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_15927_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_15927_full: > > ### IGT changes ### > > Possible regressions > > * igt@gem_eio@reset-stress: > - shard-snb: [PASS][1] -> [DMESG-WARN][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7637/shard-snb2/igt@gem_...@reset-stress.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15927/shard-snb6/igt@gem_...@reset-stress.html Failure to reset GPU on SNB. Not caused by this patch, which will only change behavior on future platforms beyond TGL. > > * igt@kms_plane_lowres@pipe-c-tiling-x: > - shard-tglb: NOTRUN -> [FAIL][3] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15927/shard-tglb8/igt@kms_plane_low...@pipe-c-tiling-x.html CRC mismatch; not sure what would cause that, but this patch would not affect that test. Applied to dinq. Thanks Lucas for the review. Matt > > > Known issues > > > Here are the changes found in Patchwork_15927_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_ctx_isolation@rcs0-s3: > - shard-tglb: [PASS][4] -> [INCOMPLETE][5] ([i915#456]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7637/shard-tglb1/igt@gem_ctx_isolat...@rcs0-s3.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15927/shard-tglb7/igt@gem_ctx_isolat...@rcs0-s3.html > > * igt@gem_ctx_shared@q-smoketest-all: > - shard-tglb: [PASS][6] -> [INCOMPLETE][7] ([fdo#111735]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7637/shard-tglb1/igt@gem_ctx_sha...@q-smoketest-all.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15927/shard-tglb3/igt@gem_ctx_sha...@q-smoketest-all.html > > * igt@gem_eio@in-flight-suspend: > - shard-tglb: [PASS][8] -> [INCOMPLETE][9] ([i915#456] / > [i915#460] / [i915#534]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7637/shard-tglb2/igt@gem_...@in-flight-suspend.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15927/shard-tglb5/igt@gem_...@in-flight-suspend.html > > * igt@gem_exec_schedule@preempt-queue-contexts-bsd2: > - shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([fdo#111606] / > [fdo#111677]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7637/shard-tglb6/igt@gem_exec_sched...@preempt-queue-contexts-bsd2.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15927/shard-tglb6/igt@gem_exec_sched...@preempt-queue-contexts-bsd2.html > > * igt@gem_exec_suspend@basic-s3: > - shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +8 > similar issues >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7637/shard-kbl6/igt@gem_exec_susp...@basic-s3.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15927/shard-kbl7/igt@gem_exec_susp...@basic-s3.html > > * igt@i915_suspend@sysfs-reader: > - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +5 > similar issues >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7637/shard-apl3/igt@i915_susp...@sysfs-reader.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15927/shard-apl1/igt@i915_susp...@sysfs-reader.html > > * igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding: > - shard-skl: [PASS][16] -> [FAIL][17] ([i915#54]) +2 similar > issues >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7637/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15927/shard-skl1/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html > > * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled: > - shard-skl: [PASS][18] -> [FAIL][19] ([i915#52] / [i915#54]) >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7637/shard-skl1/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-untiled.html >[19]: >
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Assume future platforms will inherit TGL's SFC capability
On Thu, Dec 26, 2019 at 03:05:41PM -0800, Matt Roper wrote:
On Thu, Dec 26, 2019 at 02:23:49PM -0800, Lucas De Marchi wrote:
On Tue, Dec 24, 2019 at 03:15:21PM -0800, Matt Roper wrote:
> Our usual i915 convention is to assume that future platforms will follow
> the same behavior as the latest platform of today. The VDBOX/SFC
> capabilities described here don't seem like something that should be
> specific to TGL, so let's future-proof by making the test apply to all
> gen12+ platforms.
>
> Cc: Lucas De Marchi
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
> index 1acb5db77431..bb709a08bd3c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -1093,7 +1093,7 @@ void intel_device_info_init_mmio(struct
drm_i915_private *dev_priv)
> * hooked up to an SFC (Scaler & Format Converter) unit.
> * In TGL each VDBOX has access to an SFC.
> */
> - if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0)
> + if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0)
>RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
but why are we even doing this instead of initiliazing them at compile
time on the device_info? If it's fused off, then whatever is set in
vdbox_sfc_access bit shouldn't matter... or if the code making use of
this doesn't check for engine availability, then this part of the
function could just disable the bit of whatever is fused off, regardless
if it's ice lake, tiger lake or whatever.
I'm not sure; it looks like among other things we send this bitmask
directly to the GuC, so I'm not really comfortable making the assumption
that all users of the mask will pay attention to whether the engine is
fused off or not, even if that turns out to be true for the i915 usage.
I could switch this to being initialized statically and then modified
here if an engine is fused off. In that case should this move out of
RUNTIME_INFO() and back to INTEL_INFO()? Honestly I've never really
understood why we have those separated given that we still ignore the
const and modify INTEL_INFO at runtime in several places.
hummn... true, there's this problem of not being able to initialize it
statically in one place and possibly modify it later.
We can't move it to INTEL_INFO. Anything that can be modified in runtime
needs to be inside the runtime_info, not info. I think the goal with the
separation was to make it explicit what are the fields that can be
changed in runtime. We really can't change `info` since its static const
that can be shared (think binding the driver to more than one device).
It didn't matter much in the past since we were limited to 1.
And I think the reason to have the runtime_info const and discard it here
is because it should be in fact treated as const in all places except on
initialization: we don't want accidental changes of that struct.
So... I think there may be a better solution here, but I don't think
it's important enough to block this: it's always better to be consistent
to be able to refactor this when the needs arrive.
Reviewed-by: Lucas De Marchi
Lucas De Marchi
Matt
Lucas De Marchi
>}
>DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n",
> --
> 2.23.0
>
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VTT-OSGC Platform Enablement
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Re: [Intel-gfx] [PATCH] drm/i915: save state of AUD_FREQ_CNTRL on all gen9+ platforms
On Tue, Dec 31, 2019 at 04:47:18PM +0200, Kai Vehmanen wrote:
> On old platforms the default values of AUD_FREQ_CNTRL are
> typically used (as set by BIOS), so this has not been an issue,
> but future platforms will definitely need this. Extend the state
> save logic to cover all gen9+ platforms.
>
> Bspec: 49281
> Cc: Matt Roper
> Signed-off-by: Kai Vehmanen
Looks good to me.
Reviewed-by: Matt Roper
Given that the lack of this save/restore was causing noticeable problems
on ICL/TGL, do you know whether the same problems were also seen on
EHL/JSL? If so, we may want Cc: stable and Fixes: tags so that it gets
backported?
Matt
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 27710098d056..e6517c5d83ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -849,7 +849,7 @@ static unsigned long
> i915_audio_component_get_power(struct device *kdev)
> ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
>
> if (dev_priv->audio_power_refcount++ == 0) {
> - if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> I915_WRITE(AUD_FREQ_CNTRL, dev_priv->audio_freq_cntrl);
> DRM_DEBUG_KMS("restored AUD_FREQ_CNTRL to 0x%x\n",
> dev_priv->audio_freq_cntrl);
> @@ -1124,7 +1124,7 @@ static void i915_audio_component_init(struct
> drm_i915_private *dev_priv)
> return;
> }
>
> - if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> dev_priv->audio_freq_cntrl = I915_READ(AUD_FREQ_CNTRL);
> DRM_DEBUG_KMS("init value of AUD_FREQ_CNTRL of 0x%x\n",
> dev_priv->audio_freq_cntrl);
> --
> 2.17.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use common priotree lists for virtual engine
== Series Details == Series: drm/i915: Use common priotree lists for virtual engine URL : https://patchwork.freedesktop.org/series/71528/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7657 -> Patchwork_15956 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15956 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15956, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15956: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s3: - fi-byt-j1900: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-byt-j1900/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-byt-j1900/igt@gem_exec_susp...@basic-s3.html Known issues Here are the changes found in Patchwork_15956 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#103375]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#111550]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_module_load@reload-with-fault-injection: - fi-bxt-dsi: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-bxt-dsi/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-lmem:[PASS][9] -> [INCOMPLETE][10] ([i915#671]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-lmem/igt@i915_module_l...@reload-with-fault-injection.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-skl-lmem/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live_uncore: - fi-bwr-2160:[PASS][11] -> [FAIL][12] ([i915#878]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-bwr-2160/igt@i915_selftest@live_uncore.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-bwr-2160/igt@i915_selftest@live_uncore.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [INCOMPLETE][13] ([fdo#111736] / [i915#460]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [INCOMPLETE][15] ([i915#505] / [i915#671]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-skl-guc: [INCOMPLETE][17] ([i915#151]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-guc/igt@i915_pm_...@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-skl-guc/igt@i915_pm_...@module-reload.html * igt@kms_busy@basic-flip-pipe-a: - fi-icl-u2: [INCOMPLETE][19] ([i915#140]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html Warnings * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][21] ([i915#553] / [i915#725]) -> [DMESG-FAIL][22] ([i915#725]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-hsw-4770/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15956/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] /
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Use common priotree lists for virtual engine
== Series Details ==
Series: drm/i915: Use common priotree lists for virtual engine
URL : https://patchwork.freedesktop.org/series/71528/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
104676df08c6 drm/i915: Use common priotree lists for virtual engine
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
References: 422d7df4f090 ("drm/i915: Replace engine->timeline with a plain
list")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 422d7df4f090 ("drm/i915: Replace
engine->timeline with a plain list")'
#12:
References: 422d7df4f090 ("drm/i915: Replace engine->timeline with a plain
list")
total: 1 errors, 1 warnings, 0 checks, 16 lines checked
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[Intel-gfx] [PATCH] drm/i915: Use common priotree lists for virtual engine
Since commit 422d7df4f090 ("drm/i915: Replace engine->timeline with a
plain list"), we used the default embedded priotree slot for the virtual
engine request queue, which means we can also use the same solitary slot
with the scheduler, so long as we mark the priotree as forever being
that single slot (which we can do by permanently setting no_priotree).
References: 422d7df4f090 ("drm/i915: Replace engine->timeline with a plain
list")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/i915_scheduler.c | 3 +--
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b7c963cfad04..789b0261050d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4538,6 +4538,7 @@ intel_execlists_create_virtual(struct intel_engine_cs
**siblings,
INIT_LIST_HEAD(virtual_queue(ve));
ve->base.execlists.queue_priority_hint = INT_MIN;
+ ve->base.execlists.no_priolist = true;
tasklet_init(>base.execlists.tasklet,
virtual_submission_tasklet,
(unsigned long)ve);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index bf87c70bfdd9..ea03c1cf6250 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -338,8 +338,7 @@ static void __i915_schedule(struct i915_sched_node *node,
continue;
}
- if (!intel_engine_is_virtual(engine) &&
- !i915_request_is_active(node_to_request(node))) {
+ if (!i915_request_is_active(node_to_request(node))) {
if (!cache.priolist)
cache.priolist =
i915_sched_lookup_priolist(engine,
--
2.25.0.rc0
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Restore coarse power gating
== Series Details == Series: drm/i915/gt: Restore coarse power gating URL : https://patchwork.freedesktop.org/series/71520/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657_full -> Patchwork_15953_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15953_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@processes: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#570]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-apl4/igt@gem_ctx_persiste...@processes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-apl3/igt@gem_ctx_persiste...@processes.html * igt@gem_ctx_persistence@vcs1-queued: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@gem_ctx_persiste...@vcs1-queued.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-iclb3/igt@gem_ctx_persiste...@vcs1-queued.html * igt@gem_exec_parallel@fds: - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#470]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb7/igt@gem_exec_paral...@fds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-tglb9/igt@gem_exec_paral...@fds.html * igt@gem_exec_reloc@basic-active: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#472]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb6/igt@gem_exec_re...@basic-active.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-tglb3/igt@gem_exec_re...@basic-active.html * igt@gem_exec_reuse@single: - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#435]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb1/igt@gem_exec_re...@single.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-tglb6/igt@gem_exec_re...@single.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb8/igt@gem_exec_sched...@in-order-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-iclb1/igt@gem_exec_sched...@in-order-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +11 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-iclb7/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_persistent_relocs@forked-thrash-inactive: - shard-iclb: [PASS][15] -> [TIMEOUT][16] ([i915#530]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb5/igt@gem_persistent_rel...@forked-thrash-inactive.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-iclb6/igt@gem_persistent_rel...@forked-thrash-inactive.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#644]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-skl4/igt@gem_pp...@flink-and-close-vma-leak.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-skl9/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_render_copy_redux@interruptible: - shard-hsw: [PASS][19] -> [FAIL][20] ([i915#910]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-hsw6/igt@gem_render_copy_re...@interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-hsw2/igt@gem_render_copy_re...@interruptible.html * igt@gem_sync@basic-all: - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#470] / [i915#472]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb2/igt@gem_s...@basic-all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-tglb6/igt@gem_s...@basic-all.html * igt@i915_selftest@live_gt_timelines: - shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#455]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb8/igt@i915_selftest@live_gt_timelines.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/shard-tglb5/igt@i915_selftest@live_gt_timelines.html * igt@kms_color@pipe-b-ctm-red-to-blue: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#109]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-skl10/igt@kms_co...@pipe-b-ctm-red-to-blue.html [26]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: save state of AUD_FREQ_CNTRL on all gen9+ platforms
== Series Details == Series: drm/i915: save state of AUD_FREQ_CNTRL on all gen9+ platforms URL : https://patchwork.freedesktop.org/series/71527/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657 -> Patchwork_15955 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/index.html Known issues Here are the changes found in Patchwork_15955 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [TIMEOUT][2] ([i915#816]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-byt-j1900/igt@gem_close_r...@basic-threads.html - fi-byt-n2820: [PASS][3] -> [TIMEOUT][4] ([i915#816]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103375]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#111550]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_pm_rpm@module-reload: - fi-skl-lmem:[PASS][9] -> [DMESG-WARN][10] ([i915#592]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-lmem/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-skl-lmem/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][11] -> [DMESG-FAIL][12] ([i915#725]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-hsw-4770r/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][13] -> [FAIL][14] ([fdo#111407]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [INCOMPLETE][15] ([fdo#111736] / [i915#460]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6700k2: [INCOMPLETE][17] ([i915#671]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-skl-guc: [INCOMPLETE][19] ([i915#151]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-guc/igt@i915_pm_...@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-skl-guc/igt@i915_pm_...@module-reload.html * igt@kms_busy@basic-flip-pipe-a: - fi-icl-u2: [INCOMPLETE][21] ([i915#140]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html Warnings * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [INCOMPLETE][23] ([i915#505] / [i915#671]) -> [DMESG-WARN][24] ([i915#889]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15955/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +3 similar issues [25]:
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave and Daniel, 2 fixes, 1 of which is marked for stable. drm-misc-fixes-2019-12-31: -sun4i: Fix double-free in connector/encoder cleanup (Stefan) -malidp: Make vtable static (Ben) Cc: Ben Dooks Cc: Stefan Mavrodiev Cheers, Sean The following changes since commit d16f0f61400074dbc75797ca5ef5c3d50f6c0ddf: Merge tag 'drm-fixes-5.5-2019-12-12' of git://people.freedesktop.org/~agd5f/linux into drm-fixes (2019-12-13 14:50:01 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2019-12-31 for you to fetch changes up to ac2917b01992c098b8d4e6837115e3ca347fdd90: drm/arm/mali: make malidp_mw_connector_helper_funcs static (2019-12-20 15:23:51 +) -sun4i: Fix double-free in connector/encoder cleanup (Stefan) -malidp: Make vtable static (Ben) Cc: Ben Dooks Cc: Stefan Mavrodiev Ben Dooks (Codethink) (1): drm/arm/mali: make malidp_mw_connector_helper_funcs static Stefan Mavrodiev (1): drm/sun4i: hdmi: Remove duplicate cleanup calls drivers/gpu/drm/arm/malidp_mw.c| 2 +- drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: save state of AUD_FREQ_CNTRL on all gen9+ platforms
On old platforms the default values of AUD_FREQ_CNTRL are
typically used (as set by BIOS), so this has not been an issue,
but future platforms will definitely need this. Extend the state
save logic to cover all gen9+ platforms.
Bspec: 49281
Cc: Matt Roper
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 27710098d056..e6517c5d83ae 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -849,7 +849,7 @@ static unsigned long i915_audio_component_get_power(struct
device *kdev)
ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
if (dev_priv->audio_power_refcount++ == 0) {
- if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 9) {
I915_WRITE(AUD_FREQ_CNTRL, dev_priv->audio_freq_cntrl);
DRM_DEBUG_KMS("restored AUD_FREQ_CNTRL to 0x%x\n",
dev_priv->audio_freq_cntrl);
@@ -1124,7 +1124,7 @@ static void i915_audio_component_init(struct
drm_i915_private *dev_priv)
return;
}
- if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 9) {
dev_priv->audio_freq_cntrl = I915_READ(AUD_FREQ_CNTRL);
DRM_DEBUG_KMS("init value of AUD_FREQ_CNTRL of 0x%x\n",
dev_priv->audio_freq_cntrl);
--
2.17.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Limit audio CDCLK>=2*BCLK constraint back to GLK only (rev2)
== Series Details == Series: drm/i915: Limit audio CDCLK>=2*BCLK constraint back to GLK only (rev2) URL : https://patchwork.freedesktop.org/series/71525/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657 -> Patchwork_15954 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/index.html Known issues Here are the changes found in Patchwork_15954 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [PASS][1] -> [FAIL][2] ([fdo#103375]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#111550]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6770hq: [PASS][5] -> [INCOMPLETE][6] ([i915#671]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-6770hq/igt@i915_module_l...@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-skl-6770hq/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-skl-lmem:[PASS][7] -> [DMESG-WARN][8] ([i915#592]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-lmem/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-skl-lmem/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][9] -> [DMESG-FAIL][10] ([i915#725]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-hsw-4770r/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-hsw-4770r/igt@i915_selftest@live_blt.html - fi-bsw-n3050: [PASS][11] -> [DMESG-FAIL][12] ([i915#723]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-bsw-n3050/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-bsw-n3050/igt@i915_selftest@live_blt.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][13] -> [FAIL][14] ([fdo#109635] / [i915#217]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][15] -> [FAIL][16] ([fdo#111096] / [i915#323]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [INCOMPLETE][17] ([fdo#111736] / [i915#460]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@kms_busy@basic-flip-pipe-a: - fi-icl-u2: [INCOMPLETE][19] ([i915#140]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html Warnings * igt@i915_selftest@live_blt: - fi-ivb-3770:[DMESG-FAIL][21] ([i915#725]) -> [DMESG-FAIL][22] ([i915#770]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-ivb-3770/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15954/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92]) -> [DMESG-WARN][26] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Tweak flushes around ivb ppgtt
== Series Details == Series: drm/i915/gt: Tweak flushes around ivb ppgtt URL : https://patchwork.freedesktop.org/series/71519/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657_full -> Patchwork_15952_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15952_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-kbl4/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-kbl1/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_persistence@vcs1-mixed-process: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@gem_ctx_persiste...@vcs1-mixed-process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-iclb3/igt@gem_ctx_persiste...@vcs1-mixed-process.html * igt@gem_eio@kms: - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#476]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb7/igt@gem_...@kms.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-tglb2/igt@gem_...@kms.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@gem_exec_balan...@smoke.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@gem_exec_reuse@single: - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#435]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb1/igt@gem_exec_re...@single.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-tglb6/igt@gem_exec_re...@single.html * igt@gem_exec_schedule@fifo-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb1/igt@gem_exec_sched...@fifo-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-iclb8/igt@gem_exec_sched...@fifo-bsd1.html * igt@gem_exec_schedule@preempt-queue-contexts-bsd1: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111606] / [fdo#111677]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb1/igt@gem_exec_sched...@preempt-queue-contexts-bsd1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-tglb5/igt@gem_exec_sched...@preempt-queue-contexts-bsd1.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#112146]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb6/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-iclb2/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html * igt@gem_exec_schedule@smoketest-blt: - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([i915#470]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb8/igt@gem_exec_sched...@smoketest-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-tglb3/igt@gem_exec_sched...@smoketest-blt.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive: - shard-tglb: [PASS][19] -> [TIMEOUT][20] ([fdo#112126] / [i915#530]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb5/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrash-inactive.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-tglb7/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrash-inactive.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-apl: [PASS][21] -> [TIMEOUT][22] ([i915#530]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-apl1/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-apl8/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][23] -> [FAIL][24] ([i915#454]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@i915_pm...@dc6-dpms.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@i915_selftest@live_requests: - shard-tglb: [PASS][25] -> [INCOMPLETE][26] ([i915#472]) [25]:
[Intel-gfx] [PATCH v2] drm/i915: Limit audio CDCLK>=2*BCLK constraint back to GLK only
Revert changes done in commit f6ec9483091f ("drm/i915: extend audio
CDCLK>=2*BCLK constraint to more platforms"). Audio drivers
communicate with i915 over HDA bus multiple times during system
boot-up and each of these transactions result in matching
get_power/put_power calls to i915, and depending on the platform,
a modeset change causing visible flicker.
GLK is the only platform with minimum CDCLK significantly lower
than BCLK, and thus for GLK setting a higher CDCLK is mandatory.
For other platforms, minimum CDCLK is close but below 2*BCLK
(e.g. on ICL, CDCLK=176.4kHz with BCLK=96kHz). Spec-wise the constraint
should be set, but in practise no communication errors have been
reported and the downside if set is the flicker observed at boot-time.
Revert to old behaviour until better mechanism to manage
probe-time clocks is available.
The full CDCLK>=2*BCLK constraint is still enforced at pipe
enable time in intel_crtc_compute_min_cdclk().
Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/913
Signed-off-by: Kai Vehmanen
---
Notes:
v2: d'oh, change put_power() as well
drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 27710098d056..e406719a6716 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -856,7 +856,7 @@ static unsigned long i915_audio_component_get_power(struct
device *kdev)
}
/* Force CDCLK to 2*BCLK as long as we need audio powered. */
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, true);
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
@@ -875,7 +875,7 @@ static void i915_audio_component_put_power(struct device
*kdev,
/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
if (--dev_priv->audio_power_refcount == 0)
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, false);
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Limit audio CDCLK>=2*BCLK constraint back to GLK only
Revert changes done in commit f6ec9483091f ("drm/i915: extend audio
CDCLK>=2*BCLK constraint to more platforms"). Audio drivers
communicate with i915 over HDA bus multiple times during system
boot-up and each of these transactions result in matching
get_power/put_power calls to i915, and depending on the platform,
a modeset change causing visible flicker.
GLK is the only platform with minimum CDCLK significantly lower
than BCLK, and thus for GLK setting a higher CDCLK is mandatory.
For other platforms, minimum CDCLK is close but below 2*BCLK
(e.g. on ICL, CDCLK=176.4kHz with BCLK=96kHz). Spec-wise the constraint
should be set, but in practise no communication errors have been
reported and the downside if set is the flicker observed at boot-time.
Revert to old behaviour until better mechanism to manage
probe-time clocks is available.
The full CDCLK>=2*BCLK constraint is still enforced at pipe
enable time in intel_crtc_compute_min_cdclk().
Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/913
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 27710098d056..2c5f9b23f286 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -856,7 +856,7 @@ static unsigned long i915_audio_component_get_power(struct
device *kdev)
}
/* Force CDCLK to 2*BCLK as long as we need audio powered. */
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, true);
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Restore coarse power gating
== Series Details == Series: drm/i915/gt: Restore coarse power gating URL : https://patchwork.freedesktop.org/series/71520/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657 -> Patchwork_15953 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/index.html Known issues Here are the changes found in Patchwork_15953 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [TIMEOUT][2] ([i915#816]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#103375]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#111550]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-8700k: [PASS][7] -> [INCOMPLETE][8] ([i915#505]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-cfl-8700k/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-6600u: [PASS][9] -> [INCOMPLETE][10] ([i915#671] / [i915#69]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-6600u/igt@i915_module_l...@reload-with-fault-injection.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-skl-6600u/igt@i915_module_l...@reload-with-fault-injection.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][11] -> [FAIL][12] ([fdo#111096] / [i915#323]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-icl-dsi: [PASS][13] -> [DMESG-WARN][14] ([i915#109]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-dsi/igt@prime_self_import@basic-with_one_bo_two_files.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-icl-dsi/igt@prime_self_import@basic-with_one_bo_two_files.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [INCOMPLETE][15] ([fdo#111736] / [i915#460]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [INCOMPLETE][17] ([i915#505] / [i915#671]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-skl-guc: [INCOMPLETE][19] ([i915#151]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-guc/igt@i915_pm_...@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-skl-guc/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][21] ([i915#553] / [i915#725]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-hsw-4770/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_busy@basic-flip-pipe-a: - fi-icl-u2: [INCOMPLETE][23] ([i915#140]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15953/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html Warnings * igt@gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +4 similar issues [25]:
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/gt: Include a bunch more rcs image state
== Series Details == Series: series starting with [1/5] drm/i915/gt: Include a bunch more rcs image state URL : https://patchwork.freedesktop.org/series/71506/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657_full -> Patchwork_15951_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15951_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@vcs1-mixed-process: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@gem_ctx_persiste...@vcs1-mixed-process.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-iclb5/igt@gem_ctx_persiste...@vcs1-mixed-process.html * igt@gem_ctx_shared@q-smoketest-blt: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([fdo#111735]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb5/igt@gem_ctx_sha...@q-smoketest-blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-tglb4/igt@gem_ctx_sha...@q-smoketest-blt.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_parallel@contexts: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#470]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb1/igt@gem_exec_paral...@contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-tglb8/igt@gem_exec_paral...@contexts.html * igt@gem_exec_schedule@preempt-queue-blt: - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([fdo#111677]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb7/igt@gem_exec_sched...@preempt-queue-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-tglb8/igt@gem_exec_sched...@preempt-queue-blt.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +15 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-iclb8/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb5/igt@gem_exec_sched...@reorder-wide-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_exec_suspend@basic-s4-devices: - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#460]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb8/igt@gem_exec_susp...@basic-s4-devices.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-tglb9/igt@gem_exec_susp...@basic-s4-devices.html * igt@gem_exec_whisper@normal: - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([i915#435]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb5/igt@gem_exec_whis...@normal.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-tglb8/igt@gem_exec_whis...@normal.html * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive: - shard-apl: [PASS][19] -> [TIMEOUT][20] ([i915#530]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-apl3/igt@gem_persistent_rel...@forked-interruptible-thrash-inactive.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-apl6/igt@gem_persistent_rel...@forked-interruptible-thrash-inactive.html * igt@gem_sync@basic-all: - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#470] / [i915#472]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb2/igt@gem_s...@basic-all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-tglb6/igt@gem_s...@basic-all.html * igt@i915_selftest@live_requests: - shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#472]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb8/igt@i915_selftest@live_requests.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15951/shard-tglb2/igt@i915_selftest@live_requests.html * igt@kms_color@pipe-a-ctm-negative: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#109]) [25]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Restore coarse power gating
== Series Details == Series: drm/i915/gt: Restore coarse power gating URL : https://patchwork.freedesktop.org/series/71520/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0bd0e98f0db7 drm/i915/gt: Restore coarse power gating -:31: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #31: FILE: drivers/gpu/drm/i915/i915_drv.h:1660: +#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) ^I^I^I\$ -:31: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #31: FILE: drivers/gpu/drm/i915/i915_drv.h:1660: +#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ + (IS_CANNONLAKE(dev_priv) || \ +IS_SKL_GT3(dev_priv) ||\ +IS_SKL_GT4(dev_priv)) total: 0 errors, 1 warnings, 1 checks, 13 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Tweak flushes around ivb ppgtt
== Series Details == Series: drm/i915/gt: Tweak flushes around ivb ppgtt URL : https://patchwork.freedesktop.org/series/71519/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657 -> Patchwork_15952 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/index.html Known issues Here are the changes found in Patchwork_15952 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [TIMEOUT][2] ([i915#816]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s3: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#103375]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-icl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#111550]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-icl-u2/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_pm_rpm@module-reload: - fi-skl-lmem:[PASS][7] -> [DMESG-WARN][8] ([i915#592]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-lmem/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-skl-lmem/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_execlists: - fi-bwr-2160:[PASS][9] -> [FAIL][10] ([i915#878]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-bwr-2160/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-bwr-2160/igt@i915_selftest@live_execlists.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [INCOMPLETE][11] ([fdo#111736] / [i915#460]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload-with-fault-injection: - fi-cfl-guc: [INCOMPLETE][13] ([i915#505] / [i915#671]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-cfl-guc/igt@i915_module_l...@reload-with-fault-injection.html - fi-skl-6700k2: [INCOMPLETE][15] ([i915#671]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-skl-6700k2/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-skl-guc: [INCOMPLETE][17] ([i915#151]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-skl-guc/igt@i915_pm_...@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-skl-guc/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[DMESG-FAIL][19] ([i915#725]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-ivb-3770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_busy@basic-flip-pipe-a: - fi-icl-u2: [INCOMPLETE][21] ([i915#140]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-icl-u2/igt@kms_b...@basic-flip-pipe-a.html Warnings * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][23] ([i915#553] / [i915#725]) -> [DMESG-FAIL][24] ([i915#725]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/fi-hsw-4770/igt@i915_selftest@live_blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15952/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +5 similar issues [25]:
[Intel-gfx] [PATCH] drm/i915/gt: Restore coarse power gating
The coarse power gating was disabled as part of commit 2248a28384fe
("drm/i915/gen8+: Add RC6 CTX corruption WA") as a prelude to recover
from the context corruption; the power gating itself has no direct
impact on the RC6 context corruption. However, that recovery scheme was
never implemented due to difficult corner cases, and so we no longer need
to keep the power gating disabled.
Fixes: 2248a28384fe ("drm/i915/gen8+: Add RC6 CTX corruption WA")
Closes: https://gitlab.freedesktop.org/drm/intel/issues/846
Signed-off-by: Chris Wilson
Cc: Imre Deak
Cc: Mika Kuoppala
Cc: Eero Tamminen
Cc: Jon Bloomfield
---
drivers/gpu/drm/i915/i915_drv.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7f122dccdca..85b565e69ad4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1657,8 +1657,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
/* WaRsDisableCoarsePowerGating:skl,cnl */
-#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
- IS_GEN_RANGE(dev_priv, 9, 10)
+#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
+ (IS_CANNONLAKE(dev_priv) || \
+IS_SKL_GT3(dev_priv) ||\
+IS_SKL_GT4(dev_priv))
+
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
--
2.25.0.rc0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/gt: Tweak flushes around ivb ppgtt
A small tweak to flush then invalidate appears to improve the reliability of ppGTT switches on Ivybridge -- but does not improve hsw/vlv bcs reliability. Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 066c4eddf5d0..48dbe46edbff 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -1394,7 +1394,7 @@ static int load_pd_dir(struct i915_request *rq, intel_ring_advance(rq, cs); - return 0; + return rq->engine->emit_flush(rq, EMIT_FLUSH); } static inline int mi_set_context(struct i915_request *rq, u32 flags) @@ -1584,7 +1584,7 @@ static int switch_mm(struct i915_request *rq, struct i915_address_space *vm) if (ret) return ret; - return rq->engine->emit_flush(rq, EMIT_FLUSH); + return rq->engine->emit_flush(rq, EMIT_INVALIDATE); } static int switch_context(struct i915_request *rq) -- 2.25.0.rc0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 9/9] drm/i915/display: use port_info on intel_ddi_init
On Mon, 23 Dec 2019, Lucas De Marchi wrote:
> Now that we have tables for all platforms using ddi, keep the port_info
> around so we can use it for decisions like "what phy does it have?"
> instead of keep checking the platform/gen everywhere.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 36 ---
> drivers/gpu/drm/i915/display/intel_ddi.h | 8 -
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> .../drm/i915/display/intel_display_types.h| 3 ++
> 4 files changed, 35 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a1b7075ea6be..9d06a34f5f8e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4782,14 +4782,25 @@ intel_ddi_max_lanes(struct intel_digital_port
> *dig_port)
> return max_lanes;
> }
>
> -void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> +bool __pure intel_ddi_has_tc_phy(const struct intel_digital_port *dig_port)
Nitpick, I think __pure is premature optimization that may cause more
confusion than it benefits. Also, 'git grep __pure -- drivers | wc -l'.
BR,
Jani.
> {
> + return dig_port->port_info->phy_type == PHY_TYPE_TC;
> +}
> +
> +bool __pure intel_ddi_has_combo_phy(const struct intel_digital_port
> *dig_port)
> +{
> + return dig_port->port_info->phy_type == PHY_TYPE_COMBO;
> +}
> +
> +void intel_ddi_init(struct drm_i915_private *dev_priv,
> + const struct intel_ddi_port_info *port_info)
> +{
> + enum port port = port_info->port;
> struct ddi_vbt_port_info *vbt_port_info =
> _priv->vbt.ddi_port_info[port];
> struct intel_digital_port *intel_dig_port;
> struct intel_encoder *encoder;
> bool init_hdmi, init_dp, init_lspcon = false;
> - enum phy phy = intel_port_to_phy(dev_priv, port);
>
> init_hdmi = vbt_port_info->supports_dvi || vbt_port_info->supports_hdmi;
> init_dp = vbt_port_info->supports_dp;
> @@ -4803,12 +4814,12 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> init_dp = true;
> init_lspcon = true;
> init_hdmi = false;
> - DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
> + DRM_DEBUG_KMS("VBT says port %s has lspcon\n", port_info->name);
> }
>
> if (!init_dp && !init_hdmi) {
> - DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible,
> respect it\n",
> - port_name(port));
> + DRM_DEBUG_KMS("VBT says %s is not DVI/HDMI/DP compatible,
> respect it\n",
> + port_info->name);
> return;
> }
>
> @@ -4819,7 +4830,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> encoder = _dig_port->base;
>
> drm_encoder_init(_priv->drm, >base, _ddi_funcs,
> - DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
> + DRM_MODE_ENCODER_TMDS, port_info->name);
>
> encoder->hotplug = intel_ddi_hotplug;
> encoder->compute_output_type = intel_ddi_compute_output_type;
> @@ -4837,7 +4848,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
>
> encoder->type = INTEL_OUTPUT_DDI;
> encoder->power_domain = intel_port_to_power_domain(port);
> - encoder->port = port;
> + encoder->port = port_info->port;
> encoder->cloneable = 0;
> encoder->pipe_mask = ~0;
>
> @@ -4851,8 +4862,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
> intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
> intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
> + intel_dig_port->port_info = port_info;
>
> - if (intel_phy_is_tc(dev_priv, phy)) {
> + if (intel_ddi_has_tc_phy(intel_dig_port)) {
> bool is_legacy = !vbt_port_info->supports_typec_usb &&
>!vbt_port_info->supports_tbt;
>
> @@ -4883,15 +4895,15 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> if (init_lspcon) {
> if (lspcon_init(intel_dig_port))
> /* TODO: handle hdmi info frame part */
> - DRM_DEBUG_KMS("LSPCON init success on port %c\n",
> - port_name(port));
> + DRM_DEBUG_KMS("LSPCON init success on port %s\n",
> + port_info->name);
> else
> /*
>* LSPCON init faied, but DP init was success, so
>* lets try to drive as DP++ port.
>*/
> - DRM_ERROR("LSPCON init failed on
Re: [Intel-gfx] [PATCH 9/9] drm/i915/display: use port_info on intel_ddi_init
On Mon, 23 Dec 2019, Matt Roper wrote:
> On Mon, Dec 23, 2019 at 11:58:50AM -0800, Lucas De Marchi wrote:
>> Now that we have tables for all platforms using ddi, keep the port_info
>> around so we can use it for decisions like "what phy does it have?"
>> instead of keep checking the platform/gen everywhere.
>>
>> Signed-off-by: Lucas De Marchi
>> ---
>> drivers/gpu/drm/i915/display/intel_ddi.c | 36 ---
>> drivers/gpu/drm/i915/display/intel_ddi.h | 8 -
>> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>> .../drm/i915/display/intel_display_types.h| 3 ++
>> 4 files changed, 35 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index a1b7075ea6be..9d06a34f5f8e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -4782,14 +4782,25 @@ intel_ddi_max_lanes(struct intel_digital_port
>> *dig_port)
>> return max_lanes;
>> }
>>
>> -void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>> +bool __pure intel_ddi_has_tc_phy(const struct intel_digital_port *dig_port)
>> {
>> +return dig_port->port_info->phy_type == PHY_TYPE_TC;
>> +}
>> +
>> +bool __pure intel_ddi_has_combo_phy(const struct intel_digital_port
>> *dig_port)
>> +{
>> +return dig_port->port_info->phy_type == PHY_TYPE_COMBO;
>> +}
>> +
>> +void intel_ddi_init(struct drm_i915_private *dev_priv,
>> +const struct intel_ddi_port_info *port_info)
>> +{
>> +enum port port = port_info->port;
>> struct ddi_vbt_port_info *vbt_port_info =
>> _priv->vbt.ddi_port_info[port];
>> struct intel_digital_port *intel_dig_port;
>> struct intel_encoder *encoder;
>> bool init_hdmi, init_dp, init_lspcon = false;
>> -enum phy phy = intel_port_to_phy(dev_priv, port);
>>
>> init_hdmi = vbt_port_info->supports_dvi || vbt_port_info->supports_hdmi;
>> init_dp = vbt_port_info->supports_dp;
>> @@ -4803,12 +4814,12 @@ void intel_ddi_init(struct drm_i915_private
>> *dev_priv, enum port port)
>> init_dp = true;
>> init_lspcon = true;
>> init_hdmi = false;
>> -DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
>> +DRM_DEBUG_KMS("VBT says port %s has lspcon\n", port_info->name);
>> }
>>
>> if (!init_dp && !init_hdmi) {
>> -DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible,
>> respect it\n",
>> - port_name(port));
>> +DRM_DEBUG_KMS("VBT says %s is not DVI/HDMI/DP compatible,
>> respect it\n",
>> + port_info->name);
>> return;
>> }
>>
>> @@ -4819,7 +4830,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
>> enum port port)
>> encoder = _dig_port->base;
>>
>> drm_encoder_init(_priv->drm, >base, _ddi_funcs,
>> - DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
>> + DRM_MODE_ENCODER_TMDS, port_info->name);
>>
>> encoder->hotplug = intel_ddi_hotplug;
>> encoder->compute_output_type = intel_ddi_compute_output_type;
>> @@ -4837,7 +4848,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
>> enum port port)
>>
>> encoder->type = INTEL_OUTPUT_DDI;
>> encoder->power_domain = intel_port_to_power_domain(port);
>> -encoder->port = port;
>> +encoder->port = port_info->port;
>
> In theory, shouldn't we be able to drop encoder->port completely once
> we've converted everything over to the proper ddi/phy/vbt namespace?
>
> Overall I like the direction this series is going. The continued use of
> 'port' terminology, both in the driver and in the hardware specs has
> become increasingly confusing as things get chopped up and indexed
> differently. I think this will help clarify exactly what a platform is
> expecting and force people to think about which namespace is correct for
> the part of the hardware they're working with.
Indeed, this part I like.
I am less certain whether we need to change output setup to be driven by
the new port_info. Seems like we could keep the existing output setup
(with its wrinkles) while converting port towards a struct consisting of
port, phy and phy type. And make the latter table driven instead of the
current intel_port_to_*() and intel_phy_is_*(). I think that's good
stuff.
But I don't like all the wrinkles with port F and DSI and straps etc. in
the output setup changes in this series. And we'll still *also* depend
on VBT here. I am not sure if the output setup should in fact be driven
by the VBT instead of the ports (yeah, *gasp*!).
I guess the issue with output setup would be if there are collisions in
ports with different phys. Though that would require VBT parsing changes
for DDI too, as that currently ignores such cases (and we have that in
CHV DSI).
BR,
Jani.
>
>
>
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Stop programming DDI_BUF_TRANS_SELECT on recent platforms
== Series Details == Series: drm/i915: Stop programming DDI_BUF_TRANS_SELECT on recent platforms URL : https://patchwork.freedesktop.org/series/71503/ State : success == Summary == CI Bug Log - changes from CI_DRM_7657_full -> Patchwork_15950_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15950_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@vcs1-queued: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@gem_ctx_persiste...@vcs1-queued.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-iclb6/igt@gem_ctx_persiste...@vcs1-queued.html * igt@gem_ctx_persistence@vecs0-mixed-process: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#679]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-apl1/igt@gem_ctx_persiste...@vecs0-mixed-process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-apl6/igt@gem_ctx_persiste...@vecs0-mixed-process.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb2/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_create@forked: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#108838] / [i915#435]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb1/igt@gem_exec_cre...@forked.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-tglb1/igt@gem_exec_cre...@forked.html * igt@gem_exec_parallel@vcs0-fds: - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#470]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb1/igt@gem_exec_paral...@vcs0-fds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-tglb9/igt@gem_exec_paral...@vcs0-fds.html * igt@gem_exec_schedule@fifo-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +14 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb1/igt@gem_exec_sched...@fifo-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-iclb5/igt@gem_exec_sched...@fifo-bsd1.html * igt@gem_exec_schedule@preempt-queue-blt: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111677]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb7/igt@gem_exec_sched...@preempt-queue-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-tglb3/igt@gem_exec_sched...@preempt-queue-blt.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-vebox: - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111606] / [fdo#111677]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb3/igt@gem_exec_sched...@preempt-queue-contexts-chain-vebox.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-tglb6/igt@gem_exec_sched...@preempt-queue-contexts-chain-vebox.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#112146]) +5 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-iclb5/igt@gem_exec_sched...@reorder-wide-bsd.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_exec_whisper@normal: - shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#435]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb5/igt@gem_exec_whis...@normal.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-tglb3/igt@gem_exec_whis...@normal.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-apl: [PASS][21] -> [FAIL][22] ([i915#644]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-apl2/igt@gem_pp...@flink-and-close-vma-leak.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-apl2/igt@gem_pp...@flink-and-close-vma-leak.html - shard-skl: [PASS][23] -> [FAIL][24] ([i915#644]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-skl4/igt@gem_pp...@flink-and-close-vma-leak.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15950/shard-skl9/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_sync@basic-all: - shard-tglb: [PASS][25] -> [INCOMPLETE][26] ([i915#470] / [i915#472]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7657/shard-tglb2/igt@gem_s...@basic-all.html [26]:
Re: [Intel-gfx] [PATCH 8/9] drm/i915/display: refer to vbt info as vbt_port_info
On Mon, 23 Dec 2019, Lucas De Marchi wrote:
> Now that we maintain our static port info, rename the places that refer
> to the port_info from vbt to use the vbt prefix. This is just a
> preparation step for a following change in which we will use the
> port_info variable name.
Side note, I intend to get rid of dev_priv->vbt.ddi_port_info[]
entirely.
For output initialization time, you'd have to call some function in
intel_bios.c to get the info you want. Maybe at that point you'd get an
opaque pointer to struct display_device_data which you could use to
query the child device data. You'd stick that pointer to intel_encoder
(or intel_connector), and subsequent queries would be based on that,
instead of figuring out the port and indexing something in dev_priv.
In the mean time, the rename for now seems fine.
BR,
Jani.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1bdf63845472..a1b7075ea6be 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -902,7 +902,8 @@ icl_get_combo_buf_trans(struct drm_i915_private
> *dev_priv, int type, int rate,
>
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port
> port)
> {
> - struct ddi_vbt_port_info *port_info =
> _priv->vbt.ddi_port_info[port];
> + struct ddi_vbt_port_info *vbt_port_info =
> + _priv->vbt.ddi_port_info[port];
> int n_entries, level, default_entry;
> enum phy phy = intel_port_to_phy(dev_priv, port);
>
> @@ -943,8 +944,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
> *dev_priv, enum port por
> if (WARN_ON_ONCE(n_entries == 0))
> return 0;
>
> - if (port_info->hdmi_level_shift_set)
> - level = port_info->hdmi_level_shift;
> + if (vbt_port_info->hdmi_level_shift_set)
> + level = vbt_port_info->hdmi_level_shift;
> else
> level = default_entry;
>
> @@ -4783,15 +4784,15 @@ intel_ddi_max_lanes(struct intel_digital_port
> *dig_port)
>
> void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> {
> - struct ddi_vbt_port_info *port_info =
> + struct ddi_vbt_port_info *vbt_port_info =
> _priv->vbt.ddi_port_info[port];
> struct intel_digital_port *intel_dig_port;
> struct intel_encoder *encoder;
> bool init_hdmi, init_dp, init_lspcon = false;
> enum phy phy = intel_port_to_phy(dev_priv, port);
>
> - init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
> - init_dp = port_info->supports_dp;
> + init_hdmi = vbt_port_info->supports_dvi || vbt_port_info->supports_hdmi;
> + init_dp = vbt_port_info->supports_dp;
>
> if (intel_bios_is_lspcon_present(dev_priv, port)) {
> /*
> @@ -4852,8 +4853,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
>
> if (intel_phy_is_tc(dev_priv, phy)) {
> - bool is_legacy = !port_info->supports_typec_usb &&
> - !port_info->supports_tbt;
> + bool is_legacy = !vbt_port_info->supports_typec_usb &&
> + !vbt_port_info->supports_tbt;
>
> intel_tc_port_init(intel_dig_port, is_legacy);
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 7/9] drm/i915/display: add phy, vbt and ddi indexes
On Mon, 23 Dec 2019, Lucas De Marchi wrote:
> Identify 3 possible cases in which the index numbers can be different
> from the "port" and add them to the description-based ddi initialization
> table. This can be used in place of additional functions mapping from
> on to the other. Right now we already cover part of this by creating kind of
> virtual phy numbering, but that comes with downsides:
>
> a) there's not really a "phy numbering" in the spec, this is purely a
> software thing; hardware uses whatever they want thinking mapping from
> one to the other arbitrarily is easy in software.
>
> b) currently the mapping occurs on "leaf" functions, making the decision
> based on the platform.
>
> With this new table the approach will be: the port as defined by the
> enum port is purely a driver convention and won't be used anymore to
> define the register offset or register bits. For that we have the other
> 3 indexes, identified as being possibly different from the current usage
> of register bits: ddi, vbt and phy. The phy type is also added here,
> meant to replace the checks for combo vs tc (although the helper
> functions can remain so we may differentiate between, e.g. Dekel and MG
> phys).
I'm not sure how the vbt_idx is supposed to be used (because it's
actually not used anywhere here). I would like to reduce the amount of
VBT info spread around in the driver, so I'd really need to know more.
> While at it, also give names to the ports so they can be easily
> identified.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 54 +--
> drivers/gpu/drm/i915/display/intel_display.h | 7 +++
> .../drm/i915/display/intel_display_types.h| 5 ++
> 3 files changed, 39 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ad85cf75c815..219f180fa395 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16277,14 +16277,14 @@ static bool ddi_is_port_present(struct
> drm_i915_private *i915,
> static const struct intel_output tgl_output = {
> .dsi_init = icl_dsi_init,
> .ddi_ports = {
> - { .port = PORT_A },
> - { .port = PORT_B },
> - { .port = PORT_D },
> - { .port = PORT_E },
> - { .port = PORT_F },
> - { .port = PORT_G },
> - { .port = PORT_H },
> - { .port = PORT_I },
> + { .name = "DDI A", .port = PORT_A, .phy_type =
> PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0, },
> + { .name = "DDI B", .port = PORT_B, .phy_type =
> PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1, },
> + { .name = "DDI TC1", .port = PORT_D, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x3, .phy_idx = 0x0, .vbt_idx = 0x2, },
> + { .name = "DDI TC2", .port = PORT_E, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x4, .phy_idx = 0x1, .vbt_idx = 0x3, },
> + { .name = "DDI TC3", .port = PORT_F, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x5, .phy_idx = 0x2, .vbt_idx = 0x4, },
> + { .name = "DDI TC4", .port = PORT_G, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x6, .phy_idx = 0x3, .vbt_idx = 0x5, },
> + { .name = "DDI TC5", .port = PORT_H, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x7, .phy_idx = 0x4, .vbt_idx = 0x6, },
> + { .name = "DDI TC6", .port = PORT_I, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x8, .phy_idx = 0x5, .vbt_idx = 0x7, },
> { .port = PORT_NONE }
Makes you wonder if this sort of info should be linked from the
intel_device_info instead of adding new arrays. Not sure.
BR,
Jani.
> }
> };
> @@ -16293,12 +16293,12 @@ static const struct intel_output icl_output = {
> .dsi_init = icl_dsi_init,
> .is_port_present = icl_is_port_present,
> .ddi_ports = {
> - { .port = PORT_A },
> - { .port = PORT_B },
> - { .port = PORT_C },
> - { .port = PORT_D },
> - { .port = PORT_E },
> - { .port = PORT_F },
> + { .name = "DDI A", .port = PORT_A, .phy_type =
> PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0, },
> + { .name = "DDI B", .port = PORT_B, .phy_type =
> PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1, },
> + { .name = "DDI TC1", .port = PORT_C, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x2, .phy_idx = 0x0, .vbt_idx = 0x2, },
> + { .name = "DDI TC2", .port = PORT_D, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x3, .phy_idx = 0x1, .vbt_idx = 0x3, },
> + { .name = "DDI TC3", .port = PORT_E, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x4, .phy_idx = 0x2, .vbt_idx = 0x4, },
> + { .name = "DDI TC4", .port = PORT_F, .phy_type = PHY_TYPE_TC,
> .ddi_idx = 0x5, .phy_idx = 0x3,
Re: [Intel-gfx] [PATCH 6/9] drm/i915/display: description-based initialization for remaining ddi platforms
On Tue, 31 Dec 2019, Jani Nikula wrote:
> On Mon, 23 Dec 2019, Lucas De Marchi wrote:
>> Support remaining platforms under HAS_DDI() by providing a slightly more
>> complex is_port_present() hook. The downside is that now we call
>> I915_READ(SFUSE_STRAP) for each port being initialized, but that's only
>> on initialization: a few more mmio reads won't hurt.
>>
>> Alternatives would be to provide one hook per port, or to have a
>> "pre_init()" hook that takes care of the mmio read. However I think this
>> is simpler - we may need to adapt if future platforms don't follow the
>> same initialization "template".
>
> All of this really makes me wonder if we end up being *more* complicated
> overall by trying very hard to make this generic, when, in reality, it
> doesn't seem to be all that generic.
>
> As I said, two relatively low hanging improvements would be a) moving
> VBT specific hacks to intel_bios.c and b) adding port mask to
> intel_device_info. Those two alone would go a long way in simplifying
> intel_setup_outputs().
>
>>
>> Signed-off-by: Lucas De Marchi
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 72 +---
>> 1 file changed, 46 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 6b4d320ff92c..ad85cf75c815 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -16246,6 +16246,34 @@ static bool icl_is_port_present(struct
>> drm_i915_private *i915,
>> intel_bios_is_port_present(i915, PORT_F);
>> }
>>
>> +static bool ddi_is_port_present(struct drm_i915_private *i915,
>> +const struct intel_ddi_port_info *port_info)
>> +{
>> +/* keep I915_READ() happy */
>
> Display could get rid of I915_READ and I915_WRITE after
> https://patchwork.freedesktop.org/series/70298/ ...
>
> BR,
> Jani.
>
>> +struct drm_i915_private *dev_priv = i915;
>> +
>> +if (port_info->port == PORT_A)
>> +return I915_READ(DDI_BUF_CTL(PORT_A))
>> +& DDI_INIT_DISPLAY_DETECTED;
>> +
>> +if (port_info->port == PORT_E)
>> +return IS_GEN9_BC(dev_priv) &&
>> +intel_bios_is_port_present(i915, PORT_E);
>> +
>> +switch (port_info->port) {
>> +case PORT_B:
>> +return I915_READ(SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
>> +case PORT_C:
>> +return I915_READ(SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
>> +case PORT_D:
>> +return I915_READ(SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
>> +case PORT_F:
>> +return I915_READ(SFUSE_STRAP) & SFUSE_STRAP_DDIF_DETECTED;
>> +default:
>> +return false;
>> +}
>> +}
>> +
>> static const struct intel_output tgl_output = {
>> .dsi_init = icl_dsi_init,
>> .ddi_ports = {
>> @@ -16296,11 +16324,24 @@ static const struct intel_output gen9lp_output = {
>> },
>> };
>>
>> +static const struct intel_output ddi_output = {
>> +.is_port_present = ddi_is_port_present,
>> +.ddi_ports = {
>> +{ .port = PORT_A },
>> +{ .port = PORT_B },
>> +{ .port = PORT_C },
>> +{ .port = PORT_D },
>> +{ .port = PORT_E },
>> +{ .port = PORT_F },
>> +{ .port = PORT_NONE }
>> +}
>> +};
>> +
>> /*
>> * Use a description-based approach for platforms that can be supported
>> with a
>> * static table
>> */
>> -static void setup_ddi_outputs_desc(struct drm_i915_private *i915)
>> +static void setup_ddi_outputs(struct drm_i915_private *i915)
>> {
>> const struct intel_output *output;
>> const struct intel_ddi_port_info *port_info;
>> @@ -16313,6 +16354,8 @@ static void setup_ddi_outputs_desc(struct
>> drm_i915_private *i915)
>> output = _output;
>> else if (IS_GEN9_LP(i915))
>> output = _output;
>> +else
>> +output = _output;
>>
>> for (port_info = output->ddi_ports;
>> port_info->port != PORT_NONE; port_info++) {
>> @@ -16338,35 +16381,12 @@ static void intel_setup_outputs(struct
>> drm_i915_private *dev_priv)
>> return;
>>
>> if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
>> -setup_ddi_outputs_desc(dev_priv);
>> +setup_ddi_outputs(dev_priv);
>> } else if (HAS_DDI(dev_priv)) {
>> -int found;
>> -
>> if (intel_ddi_crt_present(dev_priv))
>> intel_crt_init(dev_priv);
PS. You still need stuff like this after the supposedly generic output
setup...
>>
>> -found = I915_READ(DDI_BUF_CTL(PORT_A)) &
>> DDI_INIT_DISPLAY_DETECTED;
>> -if (found)
>> -intel_ddi_init(dev_priv, PORT_A);
>> -
>> -/* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
>> - * register */
>> -
Re: [Intel-gfx] [PATCH 6/9] drm/i915/display: description-based initialization for remaining ddi platforms
On Mon, 23 Dec 2019, Lucas De Marchi wrote:
> Support remaining platforms under HAS_DDI() by providing a slightly more
> complex is_port_present() hook. The downside is that now we call
> I915_READ(SFUSE_STRAP) for each port being initialized, but that's only
> on initialization: a few more mmio reads won't hurt.
>
> Alternatives would be to provide one hook per port, or to have a
> "pre_init()" hook that takes care of the mmio read. However I think this
> is simpler - we may need to adapt if future platforms don't follow the
> same initialization "template".
All of this really makes me wonder if we end up being *more* complicated
overall by trying very hard to make this generic, when, in reality, it
doesn't seem to be all that generic.
As I said, two relatively low hanging improvements would be a) moving
VBT specific hacks to intel_bios.c and b) adding port mask to
intel_device_info. Those two alone would go a long way in simplifying
intel_setup_outputs().
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 72 +---
> 1 file changed, 46 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6b4d320ff92c..ad85cf75c815 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16246,6 +16246,34 @@ static bool icl_is_port_present(struct
> drm_i915_private *i915,
> intel_bios_is_port_present(i915, PORT_F);
> }
>
> +static bool ddi_is_port_present(struct drm_i915_private *i915,
> + const struct intel_ddi_port_info *port_info)
> +{
> + /* keep I915_READ() happy */
Display could get rid of I915_READ and I915_WRITE after
https://patchwork.freedesktop.org/series/70298/ ...
BR,
Jani.
> + struct drm_i915_private *dev_priv = i915;
> +
> + if (port_info->port == PORT_A)
> + return I915_READ(DDI_BUF_CTL(PORT_A))
> + & DDI_INIT_DISPLAY_DETECTED;
> +
> + if (port_info->port == PORT_E)
> + return IS_GEN9_BC(dev_priv) &&
> + intel_bios_is_port_present(i915, PORT_E);
> +
> + switch (port_info->port) {
> + case PORT_B:
> + return I915_READ(SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
> + case PORT_C:
> + return I915_READ(SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
> + case PORT_D:
> + return I915_READ(SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
> + case PORT_F:
> + return I915_READ(SFUSE_STRAP) & SFUSE_STRAP_DDIF_DETECTED;
> + default:
> + return false;
> + }
> +}
> +
> static const struct intel_output tgl_output = {
> .dsi_init = icl_dsi_init,
> .ddi_ports = {
> @@ -16296,11 +16324,24 @@ static const struct intel_output gen9lp_output = {
> },
> };
>
> +static const struct intel_output ddi_output = {
> + .is_port_present = ddi_is_port_present,
> + .ddi_ports = {
> + { .port = PORT_A },
> + { .port = PORT_B },
> + { .port = PORT_C },
> + { .port = PORT_D },
> + { .port = PORT_E },
> + { .port = PORT_F },
> + { .port = PORT_NONE }
> + }
> +};
> +
> /*
> * Use a description-based approach for platforms that can be supported with
> a
> * static table
> */
> -static void setup_ddi_outputs_desc(struct drm_i915_private *i915)
> +static void setup_ddi_outputs(struct drm_i915_private *i915)
> {
> const struct intel_output *output;
> const struct intel_ddi_port_info *port_info;
> @@ -16313,6 +16354,8 @@ static void setup_ddi_outputs_desc(struct
> drm_i915_private *i915)
> output = _output;
> else if (IS_GEN9_LP(i915))
> output = _output;
> + else
> + output = _output;
>
> for (port_info = output->ddi_ports;
>port_info->port != PORT_NONE; port_info++) {
> @@ -16338,35 +16381,12 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> return;
>
> if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> - setup_ddi_outputs_desc(dev_priv);
> + setup_ddi_outputs(dev_priv);
> } else if (HAS_DDI(dev_priv)) {
> - int found;
> -
> if (intel_ddi_crt_present(dev_priv))
> intel_crt_init(dev_priv);
>
> - found = I915_READ(DDI_BUF_CTL(PORT_A)) &
> DDI_INIT_DISPLAY_DETECTED;
> - if (found)
> - intel_ddi_init(dev_priv, PORT_A);
> -
> - /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
> - * register */
> - found = I915_READ(SFUSE_STRAP);
> -
> - if (found & SFUSE_STRAP_DDIB_DETECTED)
> - intel_ddi_init(dev_priv, PORT_B);
> - if (found & SFUSE_STRAP_DDIC_DETECTED)
> -
Re: [Intel-gfx] [PATCH 5/9] drm/i915/display: move icl to description-based ddi init
On Mon, 23 Dec 2019, Lucas De Marchi wrote:
> By adding a hook that determines if a port is present, we are able to
> support Ice Lake in the new description-based DDI initialization.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 61 ++--
> 1 file changed, 42 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b3fb1e03cb0b..6b4d320ff92c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16224,9 +16224,28 @@ static void intel_pps_init(struct drm_i915_private
> *dev_priv)
> struct intel_output {
> /* Initialize DSI if present */
> void (*dsi_init)(struct drm_i915_private *i915);
> +
> + /*
> + * Check if port is present before trying to initialize; if not provided
> + * it's assumed the port is present (or we can't check and fail
> + * gracefully
> + */
> + bool (*is_port_present)(struct drm_i915_private *i915,
> + const struct intel_ddi_port_info *port_info);
> +
> struct intel_ddi_port_info ddi_ports[];
> };
>
> +static bool icl_is_port_present(struct drm_i915_private *i915,
> + const struct intel_ddi_port_info *port_info)
> +{
> + if (port_info->port != PORT_F)
> + return true;
> +
> + return IS_ICL_WITH_PORT_F(i915) &&
> + intel_bios_is_port_present(i915, PORT_F);
> +}
> +
You know, all of that is here because there were some boards with broken
VBTs claiming there was a port F on hardware that didn't have port
F. And now we're turning it into infrastructure for all platforms. :(
I actually preferred it when it was a localized hack for ICL. (Though I
said at the time we should not add hacks for VBTs because this shit
won't get fixed if we keep accommodating it.)
If we still need the port F hack, I think I'd rather move it to
intel_bios.c and skip port F description in VBT for platformsm that
don't have it. So we can rely on VBT info elsewhere.
Note that intel_ddi_init() will still check for VBT.
> static const struct intel_output tgl_output = {
> .dsi_init = icl_dsi_init,
> .ddi_ports = {
> @@ -16242,6 +16261,20 @@ static const struct intel_output tgl_output = {
> }
> };
>
> +static const struct intel_output icl_output = {
> + .dsi_init = icl_dsi_init,
> + .is_port_present = icl_is_port_present,
> + .ddi_ports = {
> + { .port = PORT_A },
> + { .port = PORT_B },
> + { .port = PORT_C },
> + { .port = PORT_D },
> + { .port = PORT_E },
> + { .port = PORT_F },
> + { .port = PORT_NONE }
At this stage of the series it seems to me we could have a ports mask in
intel_device_info, and just loop over it using for_each_port_masked().
BR,
Jani.
> + }
> +};
> +
> static const struct intel_output ehl_output = {
> .dsi_init = icl_dsi_init,
> .ddi_ports = {
> @@ -16276,12 +16309,19 @@ static void setup_ddi_outputs_desc(struct
> drm_i915_private *i915)
> output = _output;
> else if (IS_ELKHARTLAKE(i915))
> output = _output;
> + else if (IS_GEN(i915, 11))
> + output = _output;
> else if (IS_GEN9_LP(i915))
> output = _output;
>
> for (port_info = output->ddi_ports;
> - port_info->port != PORT_NONE; port_info++)
> + port_info->port != PORT_NONE; port_info++) {
> + if (output->is_port_present &&
> + !output->is_port_present(i915, port_info))
> + continue;
> +
> intel_ddi_init(i915, port_info->port);
> + }
>
> if (output->dsi_init)
> output->dsi_init(i915);
> @@ -16297,25 +16337,8 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
> return;
>
> - if (INTEL_GEN(dev_priv) >= 12 || IS_ELKHARTLAKE(dev_priv) ||
> - IS_GEN9_LP(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> setup_ddi_outputs_desc(dev_priv);
> - } else if (IS_GEN(dev_priv, 11)) {
> - intel_ddi_init(dev_priv, PORT_A);
> - intel_ddi_init(dev_priv, PORT_B);
> - intel_ddi_init(dev_priv, PORT_C);
> - intel_ddi_init(dev_priv, PORT_D);
> - intel_ddi_init(dev_priv, PORT_E);
> - /*
> - * On some ICL SKUs port F is not present. No strap bits for
> - * this, so rely on VBT.
> - * Work around broken VBTs on SKUs known to have no port F.
> - */
> - if (IS_ICL_WITH_PORT_F(dev_priv) &&
> - intel_bios_is_port_present(dev_priv, PORT_F))
> -
Re: [Intel-gfx] [PATCH 4/9] drm/i915/display: start description-based ddi initialization
On Mon, 23 Dec 2019, Lucas De Marchi wrote:
> For the latest platforms we can share the logic to initialize the the
> ddi, so start moving the most trivial ones to a new setup_outputs_desc()
> function that will be responsible for initialization according to a
> static const table.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 96 +--
> .../drm/i915/display/intel_display_types.h| 4 +
> 2 files changed, 73 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 04819b0bd494..b3fb1e03cb0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16221,6 +16221,72 @@ static void intel_pps_init(struct drm_i915_private
> *dev_priv)
> intel_pps_unlock_regs_wa(dev_priv);
> }
>
> +struct intel_output {
> + /* Initialize DSI if present */
> + void (*dsi_init)(struct drm_i915_private *i915);
We'll need to be able to initialize DSI on multiple ports too. I've
already drafted a series to do so, maybe I've even sent it to the
list. Basically you'd pass the port to icl_dsi_init() too.
I don't want that development to get any more complicated than it
already is.
BR,
Jani.
> + struct intel_ddi_port_info ddi_ports[];
> +};
> +
> +static const struct intel_output tgl_output = {
> + .dsi_init = icl_dsi_init,
> + .ddi_ports = {
> + { .port = PORT_A },
> + { .port = PORT_B },
> + { .port = PORT_D },
> + { .port = PORT_E },
> + { .port = PORT_F },
> + { .port = PORT_G },
> + { .port = PORT_H },
> + { .port = PORT_I },
> + { .port = PORT_NONE }
> + }
> +};
> +
> +static const struct intel_output ehl_output = {
> + .dsi_init = icl_dsi_init,
> + .ddi_ports = {
> + { .port = PORT_A },
> + { .port = PORT_B },
> + { .port = PORT_C },
> + { .port = PORT_D },
> + { .port = PORT_NONE }
> + }
> +};
> +
> +static const struct intel_output gen9lp_output = {
> + .dsi_init = vlv_dsi_init,
> + .ddi_ports = {
> + { .port = PORT_A },
> + { .port = PORT_B },
> + { .port = PORT_C },
> + { .port = PORT_NONE }
> + },
> +};
> +
> +/*
> + * Use a description-based approach for platforms that can be supported with
> a
> + * static table
> + */
> +static void setup_ddi_outputs_desc(struct drm_i915_private *i915)
> +{
> + const struct intel_output *output;
> + const struct intel_ddi_port_info *port_info;
> +
> + if (INTEL_GEN(i915) >= 12)
> + output = _output;
> + else if (IS_ELKHARTLAKE(i915))
> + output = _output;
> + else if (IS_GEN9_LP(i915))
> + output = _output;
> +
> + for (port_info = output->ddi_ports;
> + port_info->port != PORT_NONE; port_info++)
> + intel_ddi_init(i915, port_info->port);
> +
> + if (output->dsi_init)
> + output->dsi_init(i915);
> +}
> +
> static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> {
> struct intel_encoder *encoder;
> @@ -16231,22 +16297,9 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
> return;
>
> - if (INTEL_GEN(dev_priv) >= 12) {
> - intel_ddi_init(dev_priv, PORT_A);
> - intel_ddi_init(dev_priv, PORT_B);
> - intel_ddi_init(dev_priv, PORT_D);
> - intel_ddi_init(dev_priv, PORT_E);
> - intel_ddi_init(dev_priv, PORT_F);
> - intel_ddi_init(dev_priv, PORT_G);
> - intel_ddi_init(dev_priv, PORT_H);
> - intel_ddi_init(dev_priv, PORT_I);
> - icl_dsi_init(dev_priv);
> - } else if (IS_ELKHARTLAKE(dev_priv)) {
> - intel_ddi_init(dev_priv, PORT_A);
> - intel_ddi_init(dev_priv, PORT_B);
> - intel_ddi_init(dev_priv, PORT_C);
> - intel_ddi_init(dev_priv, PORT_D);
> - icl_dsi_init(dev_priv);
> + if (INTEL_GEN(dev_priv) >= 12 || IS_ELKHARTLAKE(dev_priv) ||
> + IS_GEN9_LP(dev_priv)) {
> + setup_ddi_outputs_desc(dev_priv);
> } else if (IS_GEN(dev_priv, 11)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> @@ -16263,17 +16316,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_ddi_init(dev_priv, PORT_F);
>
> icl_dsi_init(dev_priv);
> - } else if (IS_GEN9_LP(dev_priv)) {
> - /*
> - * FIXME: Broxton doesn't support port detection via the
> - * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> - * detect the ports.
> -
