Re: [Intel-gfx] [PATCH 5/5] drm: Remove exports for drm_pci_alloc/drm_pci_free
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next
linus/master next-20200203]
[cannot apply to tegra-drm/drm/tegra/for-next drm/drm-next v5.5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-Remove-PageReserved-manipulation-from-drm_pci_alloc/20200203-201707
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 7.5.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.5.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/drm_dma.c: In function 'drm_legacy_dma_takedown':
>> drivers/gpu/drm/drm_dma.c:103:6: error: implicit declaration of function
>> 'drm_pci_free'; did you mean 'arm_dma_free'?
>> [-Werror=implicit-function-declaration]
drm_pci_free(dev, dma->bufs[i].seglist[j]);
^~~~
arm_dma_free
cc1: some warnings being treated as errors
vim +103 drivers/gpu/drm/drm_dma.c
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 72
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 73
/**
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 74
* Cleanup the DMA resources.
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 75 *
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 76
* \param dev DRM device.
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 77 *
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 78
* Free all pages associated with DMA buffers, the buffers and pages lists, and
59c51591a0ac75 drivers/char/drm/drm_dma.c Michael Opdenacker 2007-05-09 79
* finally the drm_device::dma structure itself.
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 80
*/
e2e99a8206bcce drivers/gpu/drm/drm_dma.c Daniel Vetter 2013-08-08 81
void drm_legacy_dma_takedown(struct drm_device *dev)
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 82 {
cdd55a294c13f8 drivers/char/drm/drm_dma.c Dave Airlie2007-07-11 83
struct drm_device_dma *dma = dev->dma;
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 84
int i, j;
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 85
e2e99a8206bcce drivers/gpu/drm/drm_dma.c Daniel Vetter 2013-08-08 86
if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA) ||
fa5386459f06dc drivers/gpu/drm/drm_dma.c Daniel Vetter 2016-08-03 87
!drm_core_check_feature(dev, DRIVER_LEGACY))
e2e99a8206bcce drivers/gpu/drm/drm_dma.c Daniel Vetter 2013-08-08 88
return;
e2e99a8206bcce drivers/gpu/drm/drm_dma.c Daniel Vetter 2013-08-08 89
b5e89ed53ed8d2 drivers/char/drm/drm_dma.c Dave Airlie2005-09-25 90
if (!dma)
b5e89ed53ed8d2 drivers/char/drm/drm_dma.c Dave Airlie2005-09-25 91
return;
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 92
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 93
/* Clear dma buffers */
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 94
for (i = 0; i <= DRM_MAX_ORDER; i++) {
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 95
if (dma->bufs[i].seg_count) {
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 96
DRM_DEBUG("order %d: buf_count = %d,"
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 97
" seg_count = %d\n",
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 98
i,
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 99
dma->bufs[i].buf_count,
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 100
dma->bufs[i].seg_count);
^1da177e4c3f41 drivers/char/drm/drm_dma.c Linus Torvalds 2005-04-16 101
for (j = 0; j < dma->bufs[i].seg_count; j++) {
^1da177e4c3f41 drivers/char/drm/drm_dma.c
Re: [Intel-gfx] [PATCH 3/5] drm/r128: Wean off drm_pci_alloc
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next
linus/master next-20200203]
[cannot apply to tegra-drm/drm/tegra/for-next drm/drm-next v5.5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-Remove-PageReserved-manipulation-from-drm_pci_alloc/20200203-201707
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-s2-20200204 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.2-10+deb8u1) 4.9.2
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All error/warnings (new ones prefixed by >>):
drivers/gpu/drm/r128/ati_pcigart.c: In function
'drm_ati_alloc_pcigart_table':
>> drivers/gpu/drm/r128/ati_pcigart.c:50:7: error: expected expression before
>> '^' token
^gart_info->bus_addr,
^
>> drivers/gpu/drm/r128/ati_pcigart.c:48:3: error: too few arguments to
>> function 'dma_alloc_coherent'
dma_alloc_coherent(&dev->pdev->dev,
^
In file included from include/linux/pci-dma-compat.h:8:0,
from include/linux/pci.h:2371,
from include/drm/drm_pci.h:35,
from drivers/gpu/drm/r128/ati_pcigart.c:37:
include/linux/dma-mapping.h:641:21: note: declared here
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
^
drivers/gpu/drm/r128/ati_pcigart.c: At top level:
>> drivers/gpu/drm/r128/ati_pcigart.c:101:2: error: expected identifier or '('
>> before 'return'
return 1;
^
>> drivers/gpu/drm/r128/ati_pcigart.c:102:1: error: expected identifier or '('
>> before '}' token
}
^
drivers/gpu/drm/r128/ati_pcigart.c: In function 'drm_ati_pcigart_init':
>> drivers/gpu/drm/r128/ati_pcigart.c:168:13: warning: assignment makes pointer
>> from integer without a cast
page_base = (u32) entry->busaddr[i];
^
>> drivers/gpu/drm/r128/ati_pcigart.c:176:21: error: invalid operands to binary
>> | (have 'u32 *' and 'int')
val = page_base | 0xc;
^
drivers/gpu/drm/r128/ati_pcigart.c:179:22: error: invalid operands to binary
>> (have 'u32 *' and 'int')
val = (page_base >> 8) | 0xc;
^
>> drivers/gpu/drm/r128/ati_pcigart.c:183:9: warning: assignment makes integer
>> from pointer without a cast
val = page_base;
^
>> drivers/gpu/drm/r128/ati_pcigart.c:188:12: warning: dereferencing 'void *'
>> pointer
address[gart_idx] = cpu_to_le32(val);
^
>> drivers/gpu/drm/r128/ati_pcigart.c:188:5: error: invalid use of void
>> expression
address[gart_idx] = cpu_to_le32(val);
^
drivers/gpu/drm/r128/ati_pcigart.c: In function 'drm_ati_pcigart_cleanup':
>> drivers/gpu/drm/r128/ati_pcigart.c:99:2: warning: control reaches end of
>> non-void function [-Wreturn-type]
}
^
vim +50 drivers/gpu/drm/r128/ati_pcigart.c
43
44 static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
45 struct drm_ati_pcigart_info
*gart_info)
46 {
47 gart_info->addr =
> 48 dma_alloc_coherent(&dev->pdev->dev,
49gart_info->table_size,
> 50^gart_info->bus_addr,
51GFP_KERNEL);
52 if (!gart_info->addr)
53 return -ENOMEM;
54
55 return 0;
56 }
57
58 static void drm_ati_free_pcigart_table(struct drm_device *dev,
59 struct drm_ati_pcigart_info
*gart_info)
60 {
61 dma_free_coherent(&dev->pdev->dev,
62gart_info->table_size,
63gart_info->addr,
64gart_info->bus_addr);
65 }
66
67 int drm_ati_pcigart_cleanup(struct drm_device *dev, struct
drm_ati_pcigart_info *gart_info)
68 {
69 struct drm_sg_mem *entry = dev->sg;
70 unsigned long pages;
71 int i;
72 int max_pages;
73
7
Re: [Intel-gfx] [PATCH 2/2] drm/i915/dgfx: Do not write in removed FBC fence registers
On Wed, 2020-01-29 at 13:42 +0200, Ville Syrjälä wrote:
> On Tue, Jan 28, 2020 at 03:52:41PM -0800, José Roberto de Souza
> wrote:
> > From: Radhakrishna Sripada
> >
> > dgfx platforms do not support CPU fence and FBC host tracking so
> > lets avoid write to removed registers.
> >
> > Cc: Rodrigo Vivi
> > Cc: Matt Roper
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: Radhakrishna Sripada > >
> > Signed-off-by: Lucas De Marchi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1f0d24a1dec1..12900b8ce28e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct
> > drm_i915_private *dev_priv)
> > break;
> > }
> >
> > - if (params->fence_id >= 0) {
> > + if (IS_DGFX(dev_priv)) {
> > + /*
> > +* dGFX GPUs don't have apperture or fences and only
> > rely on FBC
> > +* render nuke to track frontbuffer modifications
> > +*/
> > + } else if (params->fence_id >= 0) {
> > dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
> > intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
> >SNB_CPU_FENCE_ENABLE | params-
> > >fence_id);
>
> if (fence) {
> do stuff
> } else if (num_fences) {
> do other stuff
> }
Did not get what you want here.
It is covering all cases:
- DGFX that don't have the registers
- Setting the registers when fence_id >= 0
- Clearing the register when fences_id == -1
>
> > --
> > 2.25.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+
On Wed, 2020-01-29 at 13:58 +0200, Ville Syrjälä wrote:
> On Wed, Jan 29, 2020 at 01:44:49PM +0200, Ville Syrjälä wrote:
> > On Tue, Jan 28, 2020 at 03:52:40PM -0800, José Roberto de Souza
> > wrote:
> > > dGFX have local memory so it do not have aperture and do not
> > > support
> > > CPU fences but even for iGFX it have a small number of fences.
> > >
> > > As replacement for fences to track frontbuffer modifications by
> > > CPU
> > > we have a software tracking that is already in used by FBC and
> > > PSR.
> > > PSR don't support fences so it shows that this tracking is
> > > reliable.
> > >
> > > So lets make fences a nice-to-have to activate FBC for GEN9+(as
> > > we
> > > only have a good CI coverage for GEN9+), this will allow us to
> > > enable
> > > FBC for dGFXs and iGFXs even when there is no available fence.
> > >
> > > intel_fbc_hw_tracking_covers_screen() maybe can also have the
> > > same
> > > treatment as fences but BSpec is not clear if the size limitation
> > > is
> > > for hardware tracking or general use of FBC and I don't have a 5K
> > > display to test it, so keeping as is for safety.
> > >
> > > Cc: Daniel Vetter
> > > Cc: Dhinakaran Pandiyan
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/display/intel_fbc.c | 12
> > > 1 file changed, 8 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index 2a3f1333c8ff..1f0d24a1dec1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -717,11 +717,15 @@ static bool intel_fbc_can_activate(struct
> > > intel_crtc *crtc)
> > > return false;
> > > }
> > >
> > > - /* The use of a CPU fence is mandatory in order to detect
> > > writes
> > > - * by the CPU to the scanout and trigger updates to the FBC.
> > > + /* The use of a CPU fence is one of two ways to detect writes
> > > by the
> > > + * CPU to the scanout and trigger updates to the FBC.
> > > + *
> > > + * The other method is by software tracking(see
> > > + * intel_fbc_invalidate/flush()), it will manually notify FBC
> > > and nuke
> > > + * the current compressed buffer and recompress it.
> > >*
> > >* Note that is possible for a tiled surface to be unmappable
> > > (and
> > > - * so have no fence associated with it) due to aperture
> > > constaints
> > > + * so have no fence associated with it) due to aperture
> > > constraints
> > >* at the time of pinning.
> > >*
> > >* FIXME with 90/270 degree rotation we should use the fence on
> > > @@ -730,7 +734,7 @@ static bool intel_fbc_can_activate(struct
> > > intel_crtc *crtc)
> > >* For now this will effecively disable FBC with 90/270 degree
> > >* rotation.
> > >*/
> > > - if (cache->fence_id < 0) {
> > > + if (cache->fence_id < 0 && INTEL_GEN(dev_priv) < 9) {
> >
> > Not enough. We need to check that the tiling format is actually
> > supported.
>
> Actually not sure if all of them are or not. IIRC some docs just said
> X/Y tile is supported (and in some other place linear was also
> listed).
Did some testing with kms_frontbuffer_tracking and linear works at
least in GEN12 with fences complete disabled, will do some testing in
GEN9 and GEN11 too and with the other types of tiling.
Any tips to find this documents? It was relevant for GEN9+?
Only thing that BSpec says is that FBC is not supported in RGB 16bpp
with planes rotated by 90 or 270.
>
> > Also the tracking stuff is busted in intel ddx so need to get
> > https://patchwork.freedesktop.org/series/70636/ merged somehow.
Ouch, hopefully no one using Intel DDX have PSR panels otherwise we
would have bug reports.
Well maybe until that is figure out, the check above could be
INTEL_GEN(dev_priv) < 11, if I remember correctly ICL is the first
platform not supported by DDX.
> >
> > > fbc->no_fbc_reason = "framebuffer not tiled or fenced";
> > > return false;
> > > }
> > > --
> > > 2.25.0
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel
___
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[Intel-gfx] [PATCH 2/2] drm/i915/tgl: Program MBUS_ABOX{1, 2}_CTL during display init
On gen11 we only needed to program MBus credits into MBUS_ABOX_CTL
during display initialization, but on gen12 we're now supposed to
program the same values into MBUS_ABOX1_CTL and MBUS_ABOX2_CTL as well.
v2:
- Program registers with rmw to preserve contents of unrelated bits.
- Switch to the new display uncore helpers.
Bspec: 49213
Bspec: 50096
Cc: Stanislav Lisovskiy
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 529319c962e8..f638691cda6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4516,6 +4516,10 @@ static void icl_mbus_init(struct drm_i915_private
*dev_priv)
MBUS_ABOX_BW_CREDIT(1);
intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val);
+ intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val);
+ }
}
static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd431f6a011..d3df704ee099 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2865,6 +2865,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
#define MBUS_ABOX_CTL _MMIO(0x45038)
+#define MBUS_ABOX1_CTL _MMIO(0x45048)
+#define MBUS_ABOX2_CTL _MMIO(0x4504C)
#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
#define MBUS_ABOX_B_CREDIT_MASK(0xF << 16)
--
2.24.1
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[Intel-gfx] [PATCH 1/2] drm/i915: Program MBUS with rmw during initialization
It wasn't terribly clear from the bspec's wording, but after discussion
with the hardware folks, it turns out that we need to preserve the
pre-existing contents of the MBUS ABOX control register when
initializing a few specific bits.
Bspec: 49213
Bspec: 50096
Fixes: 4cb4585e5a7f ("drm/i915/icl: initialize MBus during display init")
Cc: Stanislav Lisovskiy
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 6d91e180db99..529319c962e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4504,14 +4504,18 @@ static void icl_dbuf_disable(struct drm_i915_private
*dev_priv)
static void icl_mbus_init(struct drm_i915_private *dev_priv)
{
- u32 val;
+ u32 mask, val;
+ mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
+ MBUS_ABOX_BT_CREDIT_POOL2_MASK |
+ MBUS_ABOX_B_CREDIT_MASK |
+ MBUS_ABOX_BW_CREDIT_MASK;
val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
- MBUS_ABOX_BT_CREDIT_POOL2(16) |
- MBUS_ABOX_B_CREDIT(1) |
- MBUS_ABOX_BW_CREDIT(1);
+ MBUS_ABOX_BT_CREDIT_POOL2(16) |
+ MBUS_ABOX_B_CREDIT(1) |
+ MBUS_ABOX_BW_CREDIT(1);
- intel_de_write(dev_priv, MBUS_ABOX_CTL, val);
+ intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val);
}
static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
--
2.24.1
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[Intel-gfx] [PATCH] drm/i915/ehl: Check VBT before updating the transcoder for pipe
Since the pipe->transcoder mapping is not expected to change unless
there is either eDP or DSI connectors present, check the VBT to confirm
their presence in addition to checking TRANS_DDI_FUNC_CTL(transcoder).
This additional check is needed on platforms like Elkhart Lake because
we cannot just rely on GOP/Firmware programmed values in
TRANS_DDI_FUNC_CTL(transcoder) before updating the transcoder mapping.
This patch is only relevant to EHL -- and a no-op on others --
because some of the PHYs are shared between the different DDIs and
we rely on the VBT to present the most accurate information to the
driver.
Cc: Matt Roper
Cc: José Roberto de Souza
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/i915/display/intel_display.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c0e5002ce64c..4b38f293bd88 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10805,6 +10805,18 @@ static void hsw_get_ddi_pll(struct drm_i915_private
*dev_priv, enum port port,
pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
}
+static bool ehl_vbt_edp_dsi_present(struct drm_i915_private *dev_priv,
+ enum transcoder transcoder)
+{
+ bool edp_present = intel_bios_is_port_present(dev_priv, PORT_A);
+ bool dsi_present = intel_bios_is_dsi_present(dev_priv, NULL);
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ return transcoder == TRANSCODER_EDP ? edp_present : dsi_present;
+
+ return true;
+}
+
static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config,
u64 *power_domain_mask,
@@ -10844,7 +10856,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc
*crtc,
tmp = intel_de_read(dev_priv,
TRANS_DDI_FUNC_CTL(panel_transcoder));
- if (!(tmp & TRANS_DDI_FUNC_ENABLE))
+ if (!(tmp & TRANS_DDI_FUNC_ENABLE) ||
+ !ehl_vbt_edp_dsi_present(dev_priv, panel_transcoder))
continue;
/*
--
2.21.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 07/10] drm/i915/guc: Apply new uC status tracking to GuC submission as well
To be able to differentiate the before and after of our commitment to
GuC submission, which will be used in follow-up patches to early set-up
the submission structures.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 12
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 17 +--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 9 ++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 14 -
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 29 +++
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 6
drivers/gpu/drm/i915/intel_gvt.c | 2 +-
8 files changed, 42 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index c4c1523da7a6..f96d1bdf4bf2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -207,7 +207,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
{
u32 flags = 0;
- if (!intel_guc_is_submission_supported(guc))
+ if (!intel_guc_submission_is_used(guc))
flags |= GUC_CTL_DISABLE_SCHEDULER;
return flags;
@@ -217,7 +217,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
{
u32 flags = 0;
- if (intel_guc_is_submission_supported(guc)) {
+ if (intel_guc_submission_is_used(guc)) {
u32 ctxnum, base;
base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
@@ -348,7 +348,7 @@ int intel_guc_init(struct intel_guc *guc)
if (ret)
goto err_ads;
- if (intel_guc_is_submission_supported(guc)) {
+ if (intel_guc_submission_is_used(guc)) {
/*
* This is stuff we need to have available at fw load time
* if we are planning to enable submission later
@@ -389,7 +389,7 @@ void intel_guc_fini(struct intel_guc *guc)
i915_ggtt_disable_guc(gt->ggtt);
- if (intel_guc_is_submission_supported(guc))
+ if (intel_guc_submission_is_used(guc))
intel_guc_submission_fini(guc);
intel_guc_ct_fini(&guc->ct);
@@ -544,7 +544,7 @@ int intel_guc_suspend(struct intel_guc *guc)
* If GuC communication is enabled but submission is not supported,
* we do not need to suspend the GuC.
*/
- if (!intel_guc_submission_is_enabled(guc))
+ if (!intel_guc_submission_is_used(guc) || !intel_guc_is_ready(guc))
return 0;
/*
@@ -609,7 +609,7 @@ int intel_guc_resume(struct intel_guc *guc)
* we do not need to resume the GuC but we do need to enable the
* GuC communication on resume (above).
*/
- if (!intel_guc_submission_is_enabled(guc))
+ if (!intel_guc_submission_is_used(guc) || !intel_guc_is_ready(guc))
return 0;
return intel_guc_send(guc, action, ARRAY_SIZE(action));
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index f6b33745ae0b..1aba4d2c15b3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -39,7 +39,7 @@ struct intel_guc {
void (*disable)(struct intel_guc *guc);
} interrupts;
- bool submission_supported;
+ bool submission_selected;
struct i915_vma *ads_vma;
struct __guc_ads_blob *ads_blob;
@@ -172,9 +172,20 @@ static inline int intel_guc_sanitize(struct intel_guc *guc)
return 0;
}
-static inline bool intel_guc_is_submission_supported(struct intel_guc *guc)
+static inline bool intel_guc_submission_is_supported(struct intel_guc *guc)
{
- return guc->submission_supported;
+ /* XXX: GuC submission is unavailable for now */
+ return false;
+}
+
+static inline bool intel_guc_submission_is_wanted(struct intel_guc *guc)
+{
+ return guc->submission_selected;
+}
+
+static inline bool intel_guc_submission_is_used(struct intel_guc *guc)
+{
+ return intel_guc_is_used(guc) && intel_guc_submission_is_wanted(guc);
}
static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9e42324fdecd..1beaa77f9bb6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -660,12 +660,9 @@ void intel_guc_submission_disable(struct intel_guc *guc)
guc_proc_desc_fini(guc);
}
-static bool __guc_submission_support(struct intel_guc *guc)
+static bool __guc_submission_selected(struct intel_guc *guc)
{
- /* XXX: GuC submission is unavailable for now */
- return false;
-
- if (!intel_guc_is_supported(guc))
+ if (!intel_guc_submission_is_supported(guc))
return false;
re
[Intel-gfx] [PATCH v2 04/10] drm/i915/uc: Update the FW status on injected fetch error
In a follow up patch we will rely on the fact that the status always moves away from "SELECTED" after the fetch is attempted to decide what to do with the GuC. v2: Split this change to its own patch (Michal) Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 8ee0a0c7f447..c9c094a73399 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -279,7 +279,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw) err = i915_inject_probe_error(i915, -ENXIO); if (err) - return err; + goto fail; __force_fw_fetch_failures(uc_fw, -EINVAL); __force_fw_fetch_failures(uc_fw, -ESTALE); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 09/10] drm/i915/uc: consolidate firmware cleanup
We are quite trigger happy in cleaning up the firmware blobs, as we do
so from several error/fini paths in GuC/HuC/uC code. We do have the
__uc_cleanup_firmwares cleanup function, which unwinds
__uc_fetch_firmwares and is already called both from the error path of
gem_init and from gem_driver_release, so let's stop cleaning up from
all the other paths.
The fact that we're not cleaning the firmware immediately means that
we can't consider firmware availability as an indication of
initialization success. A "READY_TO_LOAD" status has been added to
indicate that the initialization was successful, to be used to
selectively load HuC only if HuC init has completed (HuC init failure
is not considered a fatal error).
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 10 --
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 3 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 7 +--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 18 +++---
5 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 97b9c71a6fd4..2d05de570bdf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -333,7 +333,7 @@ int intel_guc_init(struct intel_guc *guc)
ret = intel_uc_fw_init(&guc->fw);
if (ret)
- goto err_fetch;
+ goto out;
ret = intel_guc_log_create(&guc->log);
if (ret)
@@ -364,6 +364,8 @@ int intel_guc_init(struct intel_guc *guc)
/* We need to notify the guc whenever we change the GGTT */
i915_ggtt_enable_guc(gt->ggtt);
+ intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_READY_TO_LOAD);
+
return 0;
err_ct:
@@ -374,8 +376,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_guc_log_destroy(&guc->log);
err_fw:
intel_uc_fw_fini(&guc->fw);
-err_fetch:
- intel_uc_fw_cleanup_fetch(&guc->fw);
+out:
i915_probe_error(gt->i915, "failed with %d\n", ret);
return ret;
}
@@ -397,9 +398,6 @@ void intel_guc_fini(struct intel_guc *guc)
intel_guc_ads_destroy(guc);
intel_guc_log_destroy(&guc->log);
intel_uc_fw_fini(&guc->fw);
- intel_uc_fw_cleanup_fetch(&guc->fw);
-
- intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_DISABLED);
}
/*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 5f448d0e360b..2e4f4a8e791e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -121,12 +121,13 @@ int intel_huc_init(struct intel_huc *huc)
if (err)
goto out_fini;
+ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_READY_TO_LOAD);
+
return 0;
out_fini:
intel_uc_fw_fini(&huc->fw);
out:
- intel_uc_fw_cleanup_fetch(&huc->fw);
i915_probe_error(i915, "failed with %d\n", err);
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index a119b7776973..4c55b1285cbc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -417,7 +417,7 @@ static int __uc_init_hw(struct intel_uc *uc)
GEM_BUG_ON(!intel_uc_supports_guc(uc));
GEM_BUG_ON(!intel_uc_wants_guc(uc));
- if (!intel_uc_fw_is_available(&guc->fw)) {
+ if (!intel_uc_fw_is_ready_to_load(&guc->fw)) {
ret = __uc_check_hw(uc) ||
intel_uc_fw_is_overridden(&guc->fw) ||
intel_uc_wants_guc_submission(uc) ?
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index c9c094a73399..3759569ec000 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -501,7 +501,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32
dst_offset, u32 dma_flags)
if (err)
return err;
- if (!intel_uc_fw_is_available(uc_fw))
+ if (!intel_uc_fw_is_ready_to_load(uc_fw))
return -ENOEXEC;
/* Call custom loader */
@@ -544,7 +544,10 @@ int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
void intel_uc_fw_fini(struct intel_uc_fw *uc_fw)
{
- intel_uc_fw_cleanup_fetch(uc_fw);
+ if (i915_gem_object_has_pinned_pages(uc_fw->obj))
+ i915_gem_object_unpin_pages(uc_fw->obj);
+
+ intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_AVAILABLE);
}
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
index 1f30543d0d2d..ba3c362aeca2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
@@ -29,8 +29,11 @@ struct intel_gt;
* || SELECTED
[Intel-gfx] [PATCH v2 05/10] drm/i915/uc: autogenerate uC checker functions
We want to map uC-level checks to GuC/HuC-level ones. The mapping from
the uC state to the GuC/HuC one follows the same pattern for all the
functions:
uc_xxx_guc() -> guc_is_yyy()
So we can easily use a macro to autogenerate the functions via macros by
passing in the 2 mapped states.
v2: Split this change to its own patch (Michal)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 30 ---
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 49c913524686..2ce993ceb60a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -40,15 +40,21 @@ void intel_uc_runtime_suspend(struct intel_uc *uc);
int intel_uc_resume(struct intel_uc *uc);
int intel_uc_runtime_resume(struct intel_uc *uc);
-static inline bool intel_uc_supports_guc(struct intel_uc *uc)
-{
- return intel_guc_is_supported(&uc->guc);
+#define __uc_state_checker(x, state, required) \
+static inline bool intel_uc_##state##_##x(struct intel_uc *uc) \
+{ \
+ return intel_##x##_is_##required(&uc->x); \
}
-static inline bool intel_uc_uses_guc(struct intel_uc *uc)
-{
- return intel_guc_is_enabled(&uc->guc);
-}
+#define uc_state_checkers(x) \
+__uc_state_checker(x, supports, supported) \
+__uc_state_checker(x, uses, enabled)
+
+uc_state_checkers(guc);
+uc_state_checkers(huc);
+
+#undef uc_state_checkers
+#undef __uc_state_checker
static inline bool intel_uc_supports_guc_submission(struct intel_uc *uc)
{
@@ -60,16 +66,6 @@ static inline bool intel_uc_uses_guc_submission(struct
intel_uc *uc)
return intel_guc_is_submission_supported(&uc->guc);
}
-static inline bool intel_uc_supports_huc(struct intel_uc *uc)
-{
- return intel_uc_supports_guc(uc);
-}
-
-static inline bool intel_uc_uses_huc(struct intel_uc *uc)
-{
- return intel_huc_is_enabled(&uc->huc);
-}
-
#define intel_uc_ops_function(_NAME, _OPS, _TYPE, _RET) \
static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
{ \
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 08/10] drm/i915/uc: Abort early on uc_init failure
Now that we can differentiate wants vs uses GuC/HuC, intel_uc_init is
restricted to running only if we have successfully fetched the required
blob(s) and are committed to using the microcontroller(s).
The only remaining thing that can go wrong in uc_init is the allocation
of GuC/HuC related objects; if we get such a failure better to bail out
immediately instead of wedging later, like we do for e.g.
intel_engines_init, since without objects we can't use the HW, including
not being able to attempt the firmware load.
While at it, remove the unneeded fw_cleanup call (this is handled
outside of gt_init) and add a probe failure injection point for testing.
Also, update the logs for uc_init failures to probe_failure() since
they will cause the driver load to fail.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
Reviewed-by: Fernando Pacheco
---
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 24 +---
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 4 ++--
5 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f1f1b306e0af..cd64f81a3e60 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -592,7 +592,9 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_engines;
- intel_uc_init(>->uc);
+ err = intel_uc_init(>->uc);
+ if (err)
+ goto err_engines;
err = intel_gt_resume(gt);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index f96d1bdf4bf2..97b9c71a6fd4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -376,7 +376,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_uc_fw_fini(&guc->fw);
err_fetch:
intel_uc_fw_cleanup_fetch(&guc->fw);
- DRM_DEV_DEBUG_DRIVER(gt->i915->drm.dev, "failed with %d\n", ret);
+ i915_probe_error(gt->i915, "failed with %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 32a069841c14..5f448d0e360b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -127,7 +127,7 @@ int intel_huc_init(struct intel_huc *huc)
intel_uc_fw_fini(&huc->fw);
out:
intel_uc_fw_cleanup_fetch(&huc->fw);
- DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "failed with %d\n", err);
+ i915_probe_error(i915, "failed with %d\n", err);
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 175fa6361ff2..a119b7776973 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -273,7 +273,7 @@ static void __uc_cleanup_firmwares(struct intel_uc *uc)
intel_uc_fw_cleanup_fetch(&uc->guc.fw);
}
-static void __uc_init(struct intel_uc *uc)
+static int __uc_init(struct intel_uc *uc)
{
struct intel_guc *guc = &uc->guc;
struct intel_huc *huc = &uc->huc;
@@ -282,19 +282,29 @@ static void __uc_init(struct intel_uc *uc)
GEM_BUG_ON(!intel_uc_wants_guc(uc));
if (!intel_uc_uses_guc(uc))
- return;
+ return 0;
+
+ if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
+ return -ENOMEM;
/* XXX: GuC submission is unavailable for now */
GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
ret = intel_guc_init(guc);
- if (ret) {
- intel_uc_fw_cleanup_fetch(&huc->fw);
- return;
+ if (ret)
+ return ret;
+
+ if (intel_uc_uses_huc(uc)) {
+ ret = intel_huc_init(huc);
+ if (ret)
+ goto out_guc;
}
- if (intel_uc_uses_huc(uc))
- intel_huc_init(huc);
+ return 0;
+
+out_guc:
+ intel_guc_fini(guc);
+ return ret;
}
static void __uc_fini(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 35ce8a6be88b..480965504679 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -16,7 +16,7 @@ struct intel_uc_ops {
int (*sanitize)(struct intel_uc *uc);
void (*init_fw)(struct intel_uc *uc);
void (*fini_fw)(struct intel_uc *uc);
- void (*init)(struct intel_uc *uc);
+ int (*init)(struct intel_uc *uc);
void (*fini)(struct intel_uc *uc);
int (*init_hw)(struct intel_uc *uc);
void (*fini_hw)(struct intel_uc *uc);
@@ -89,7 +89,7 @@ static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
intel_uc_ops_function(sanitize, sanitize, int, 0);
intel_uc_o
[Intel-gfx] [PATCH v2 02/10] drm/i915/guc: Kill USES_GUC macro
use intel_uc_uses_guc() directly instead, to be consistent in the way we
check what we want to do with the GuC.
v2: split guc_log_info changes to their own patch (Michal)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 15 +--
drivers/gpu/drm/i915/i915_drv.h | 1 -
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 7dae91e0d002..048240b19772 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -427,7 +427,7 @@ static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
u64 size;
int ret;
- if (!USES_GUC(ggtt->vm.i915))
+ if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
return 0;
GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7264c0ff766c..bfdcb657780b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1778,11 +1778,12 @@ static void i915_guc_log_info(struct seq_file *m,
struct intel_guc_log *log)
static int i915_guc_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_uc *uc = &dev_priv->gt.uc;
- if (!USES_GUC(dev_priv))
+ if (!intel_uc_uses_guc(uc))
return -ENODEV;
- i915_guc_log_info(m, &dev_priv->gt.uc.guc.log);
+ i915_guc_log_info(m, &uc->guc.log);
/* Add more as required ... */
@@ -1883,11 +1884,12 @@ static int i915_guc_log_dump(struct seq_file *m, void
*data)
static int i915_guc_log_level_get(void *data, u64 *val)
{
struct drm_i915_private *dev_priv = data;
+ struct intel_uc *uc = &dev_priv->gt.uc;
- if (!USES_GUC(dev_priv))
+ if (!intel_uc_uses_guc(uc))
return -ENODEV;
- *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log);
+ *val = intel_guc_log_get_level(&uc->guc.log);
return 0;
}
@@ -1895,11 +1897,12 @@ static int i915_guc_log_level_get(void *data, u64 *val)
static int i915_guc_log_level_set(void *data, u64 val)
{
struct drm_i915_private *dev_priv = data;
+ struct intel_uc *uc = &dev_priv->gt.uc;
- if (!USES_GUC(dev_priv))
+ if (!intel_uc_uses_guc(uc))
return -ENODEV;
- return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val);
+ return intel_guc_log_set_level(&uc->guc.log, val);
}
DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a71ff233cc55..a8e1ec7d571f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1701,7 +1701,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
/* Having GuC is not the same as using GuC */
-#define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc)
#define USES_GUC_SUBMISSION(dev_priv)
intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
#define HAS_POOLED_EU(dev_priv)(INTEL_INFO(dev_priv)->has_pooled_eu)
--
2.24.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 06/10] drm/i915/uc: Improve tracking of uC init status
To be able to setup GuC submission functions during engine init we need
to commit to using GuC as soon as possible.
Currently, the only thing that can stop us from using the
microcontrollers once we've fetched the blobs is a fundamental
error (e.g. OOM); given that if we hit such an error we can't really
fall-back to anything, we can "officialize" the FW fetching completion
as the moment at which we're committing to using GuC.
To better differentiate this case, the uses_guc check, which indicates
that GuC is supported and was selected in modparam, is renamed to
wants_guc and a new uses_guc is introduced to represent the case were
we're committed to using the GuC. Note that uses_guc does still not imply
that the blob is actually loaded on the HW (is_running is the check for
that). Also, since we need to have attempted the fetch for the result
of uses_guc to be meaningful, we need to make sure we've moved away
from INTEL_UC_FIRMWARE_SELECTED.
All the GuC changes have been mirrored on the HuC for coherency.
v2: split fetch return changes and new macros to their own patches,
support HuC only if GuC is wanted, improve "used" state
description (Michal)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
Reviewed-by: Fernando Pacheco #v1
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 8 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 8 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 23 --
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 24 ++-
5 files changed, 51 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 7ca9e5159f05..f6b33745ae0b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -143,11 +143,17 @@ static inline bool intel_guc_is_supported(struct
intel_guc *guc)
return intel_uc_fw_is_supported(&guc->fw);
}
-static inline bool intel_guc_is_enabled(struct intel_guc *guc)
+static inline bool intel_guc_is_wanted(struct intel_guc *guc)
{
return intel_uc_fw_is_enabled(&guc->fw);
}
+static inline bool intel_guc_is_used(struct intel_guc *guc)
+{
+ GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) ==
INTEL_UC_FIRMWARE_SELECTED);
+ return intel_uc_fw_is_available(&guc->fw);
+}
+
static inline bool intel_guc_is_fw_running(struct intel_guc *guc)
{
return intel_uc_fw_is_running(&guc->fw);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 644c059fe01d..a40b9cfc6c22 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -41,11 +41,17 @@ static inline bool intel_huc_is_supported(struct intel_huc
*huc)
return intel_uc_fw_is_supported(&huc->fw);
}
-static inline bool intel_huc_is_enabled(struct intel_huc *huc)
+static inline bool intel_huc_is_wanted(struct intel_huc *huc)
{
return intel_uc_fw_is_enabled(&huc->fw);
}
+static inline bool intel_huc_is_used(struct intel_huc *huc)
+{
+ GEM_BUG_ON(__intel_uc_fw_status(&huc->fw) ==
INTEL_UC_FIRMWARE_SELECTED);
+ return intel_uc_fw_is_available(&huc->fw);
+}
+
static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
{
return intel_uc_fw_is_running(&huc->fw);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index eee193bf2cc4..9cdf4cbe691c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -20,7 +20,7 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
struct drm_i915_private *i915 = gt->i915;
intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC,
- intel_uc_uses_guc(uc),
+ intel_uc_wants_guc(uc),
INTEL_INFO(i915)->platform, INTEL_REVID(i915));
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index affc4d6f9ead..654d7c0c757a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -48,17 +48,17 @@ static void __confirm_options(struct intel_uc *uc)
DRM_DEV_DEBUG_DRIVER(i915->drm.dev,
"enable_guc=%d (guc:%s submission:%s huc:%s)\n",
i915_modparams.enable_guc,
-yesno(intel_uc_uses_guc(uc)),
+yesno(intel_uc_wants_guc(uc)),
yesno(intel_uc_uses_guc_submission(uc)),
-yesno(intel_uc_uses_huc(uc)));
+yesno(intel_uc_wants_huc(uc)));
if (i915_modparams.enable_guc == -1)
return;
if (i915_modparams.enable_guc == 0) {
- GEM_BUG_
[Intel-gfx] [PATCH v2 01/10] drm/i915/debugfs: Pass guc_log struct to i915_guc_log_info
The log struct is the only thing the function needs (apart from
the seq_file), so we can pass just that instead of the whole dev_priv.
v2: Split this change to its own patch (Michal)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e75e8212f03b..7264c0ff766c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1753,10 +1753,8 @@ stringify_guc_log_type(enum guc_log_buffer_type type)
return "";
}
-static void i915_guc_log_info(struct seq_file *m,
- struct drm_i915_private *dev_priv)
+static void i915_guc_log_info(struct seq_file *m, struct intel_guc_log *log)
{
- struct intel_guc_log *log = &dev_priv->gt.uc.guc.log;
enum guc_log_buffer_type type;
if (!intel_guc_log_relay_created(log)) {
@@ -1784,7 +1782,7 @@ static int i915_guc_info(struct seq_file *m, void *data)
if (!USES_GUC(dev_priv))
return -ENODEV;
- i915_guc_log_info(m, dev_priv);
+ i915_guc_log_info(m, &dev_priv->gt.uc.guc.log);
/* Add more as required ... */
--
2.24.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 03/10] drm/i915/guc: Kill USES_GUC_SUBMISSION macro
use intel_uc_uses_guc_submission() directly instead, to be consistent in
the way we check what we want to do with the GuC.
v2: do not go through ctx->vm->gt, use i915->gt instead
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
Reviewed-by: Michal Wajdeczko #v1
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 12 ++--
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 3 ++-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
drivers/gpu/drm/i915/i915_drv.h | 3 ---
drivers/gpu/drm/i915/intel_gvt.c | 2 +-
8 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index fad62d768f08..19b0204c6770 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1442,7 +1442,7 @@ set_engines__load_balance(struct i915_user_extension
__user *base, void *data)
if (!HAS_EXECLISTS(i915))
return -ENODEV;
- if (USES_GUC_SUBMISSION(i915))
+ if (intel_uc_uses_guc_submission(&i915->gt.uc))
return -ENODEV; /* not implement yet */
if (get_user(idx, &ext->engine_index))
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 3e5e6c86e843..c3514ec7b8db 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1640,7 +1640,7 @@ static int igt_reset_engines_atomic(void *arg)
if (!intel_has_reset_engine(gt))
return 0;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
igt_global_reset_lock(gt);
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 79b9f7d092e4..0d18d30630fd 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1808,7 +1808,7 @@ static int live_suppress_self_preempt(void *arg)
if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
return 0;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0; /* presume black blox */
if (intel_vgpu_active(gt->i915))
@@ -3044,7 +3044,7 @@ static int live_virtual_engine(void *arg)
unsigned int class, inst;
int err;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
for_each_engine(engine, gt, id) {
@@ -3177,7 +3177,7 @@ static int live_virtual_mask(void *arg)
unsigned int class, inst;
int err;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
@@ -3319,7 +3319,7 @@ static int live_virtual_preserved(void *arg)
* are preserved.
*/
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
/* As we use CS_GPR we cannot run before they existed on all engines. */
@@ -3543,7 +3543,7 @@ static int live_virtual_bond(void *arg)
unsigned int class, inst;
int err;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
@@ -3704,7 +3704,7 @@ static int live_virtual_reset(void *arg)
* forgotten.
*/
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
if (!intel_has_reset_engine(gt))
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c
b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 6ad6aca315f6..35406ecdf0b2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -115,7 +115,7 @@ static int igt_atomic_engine_reset(void *arg)
if (!intel_has_reset_engine(gt))
return 0;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
intel_gt_pm_get(gt);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 685d1e04a5ff..5fe00ee6bd1b 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1246,7 +1246,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
ce->vm = i915_vm_get(&ppgtt->vm);
intel_context_set_single_submission(ce);
- if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */
+ /* Max ri
[Intel-gfx] [PATCH v2 00/10] Commit early to GuC
Main difference from v1 is that I've dropped the patch to start the re-org of guc submission setup (I plan to re-send that as part of [1], after Chris' intel_lrc.c split patches land) and added a patch to be less aggressive in cleaning up the firmware objects. Some chunks have also be split to their own patches, as requested by Michal, to better isolate the changes. [1] https://patchwork.freedesktop.org/series/72562/ Cc: Chris Wilson Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost Daniele Ceraolo Spurio (10): drm/i915/debugfs: Pass guc_log struct to i915_guc_log_info drm/i915/guc: Kill USES_GUC macro drm/i915/guc: Kill USES_GUC_SUBMISSION macro drm/i915/uc: Update the FW status on injected fetch error drm/i915/uc: autogenerate uC checker functions drm/i915/uc: Improve tracking of uC init status drm/i915/guc: Apply new uC status tracking to GuC submission as well drm/i915/uc: Abort early on uc_init failure drm/i915/uc: consolidate firmware cleanup HAX: drm/i915: default to enable_guc=2 drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c| 4 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +- drivers/gpu/drm/i915/gt/selftest_lrc.c| 12 ++-- drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 24 drivers/gpu/drm/i915/gt/uc/intel_guc.h| 25 ++-- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 9 +-- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 5 +- drivers/gpu/drm/i915/gt/uc/intel_huc.h| 8 ++- drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 61 +++ drivers/gpu/drm/i915/gt/uc/intel_uc.h | 61 +++ drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 9 ++- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 18 +- drivers/gpu/drm/i915/gvt/scheduler.c | 3 +- drivers/gpu/drm/i915/i915_debugfs.c | 25 drivers/gpu/drm/i915/i915_drv.h | 10 --- drivers/gpu/drm/i915/i915_params.h| 2 +- drivers/gpu/drm/i915/intel_gvt.c | 2 +- 21 files changed, 169 insertions(+), 119 deletions(-) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 10/10] HAX: drm/i915: default to enable_guc=2
To enable GuC and HuC loading on all gen9+ CI machines. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index cb16410c2ada..7f6b3cbcd74f 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -56,7 +56,7 @@ struct drm_printer; param(int, disable_power_well, -1, 0400) \ param(int, enable_ips, 1, 0600) \ param(int, invert_brightness, 0, 0600) \ - param(int, enable_guc, 0, 0400) \ + param(int, enable_guc, 2, 0400) \ param(int, guc_log_level, -1, 0400) \ param(char *, guc_firmware_path, NULL, 0400) \ param(char *, huc_firmware_path, NULL, 0400) \ -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.
It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A nameing rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 170
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 173 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index dd7e5588001e..d4ece0a824c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
intel_write_dp_sdp(encoder, crtc_state,
HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(vsc, 0, size);
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+ return -EINVAL;
+ vsc->sdp_type = sdp->sdp_header.HB1;
+
+ if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+ } else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) {
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+ } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+ vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
+ vsc->colorimetry = sdp->db[16] & 0xf;
+ vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+ switch (sdp->db[17] & 0x7) {
+ case 0x1:
+ vsc->bpc = 8;
+ break;
+ case 0x2:
+ vsc->bpc = 10;
+ break;
+ case 0x3:
+ vsc->bpc = 12;
+ break;
+ case 0x4:
+ vsc->bpc = 16;
+ break;
+ default:
+ MISSING_CASE(sdp->db[17] & 0x7);
+ return -EINVAL;
+ }
+
+ vsc->content_type = sdp->db[18] & 0x7;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe
*drm_infoframe,
+ const void *buffer, size_t size)
+{
+ int ret;
+
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+ return -EINVAL;
+
+ /*
+* Least Significant Eight Bits of (Data Byte Count – 1)
+* 1Dh (i.e., Data Byte Count = 30 bytes).
+*/
+ if (sdp->sdp_header.HB2 != 0x1D)
+ return -EINVAL;
+
+ /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+ if ((sdp->sdp_header.HB3 & 0x3) != 0)
+ return -EINVAL;
+
+ /* INFOFRAME SDP Version Number */
+ if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
+ return -EINVAL;
+
+ /* CTA Header Byte 2 (INFOFRAME Version Number) */
+ if (sdp->db[0] != 1)
+ return -EINVAL;
+
+ /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
+ if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
+HDMI_DRM_INFOFRAME_SIZE);
+
+ return ret;
+}
+
+static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+
[Intel-gfx] [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal crtc state dump. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c0e5002ce64c..239861bcedba 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) + intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(&pipe_config->hw.mode); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump
Dump out the DP VSC SDP in the normal crtc state dump
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Use drm core's DP VSC SDP logging function
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 593c63f51210..4f187fd330e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
}
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
static const char * const output_type_str[] = {
@@ -13036,6 +13046,9 @@ static void intel_dump_pipe_config(const struct
intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_VSC))
+ intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->hw.mode);
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP
Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 42
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a9eaf7a6bc15..64e4edefa998 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
&pipe_config->infoframes.drm);
intel_read_dp_sdp(encoder, pipe_config,
HDMI_PACKET_TYPE_GAMUT_METADATA);
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4f187fd330e8..02471c7aa6e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
return memcmp(a, b, sizeof(*a)) == 0;
}
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+const struct drm_dp_vsc_sdp *b)
+{
+ return memcmp(a, b, sizeof(*a)) == 0;
+}
+
static void
pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
bool fastset, const char *name,
@@ -13528,6 +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv,
}
}
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+ bool fastset, const char *name,
+ const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ if (fastset) {
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
+ DRM_DEBUG_KMS("expected:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+ DRM_DEBUG_KMS("found:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+ } else {
+ DRM_ERROR("mismatch in %s dp sdp\n", name);
+ DRM_ERROR("expected:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+ DRM_ERROR("found:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+ }
+}
+
static void __printf(4, 5)
pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
const char *name, const char *format, ...)
@@ -13729,6 +13760,16 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
if (current_config->name1 != pipe_config->name1) { \
pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -13902,6 +13943,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_INFOFRAME(spd);
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to pack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_pack() function.
And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A machanism and a naming rule of intel_dp_set_infoframes() function
references intel_encoder->set_infoframes() of intel_hdmi.c .
VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
Because PSR routine has its own routine of writing a VSC SDP, when the PSR
is enabled, intel_dp_set_infoframes() does not write a VSC SDP.
v3:
- Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
used for HDMI), when intel_dp_set_infoframes() function will be called.
- Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 194
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 197 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index b265b5c599f2..dd7e5588001e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
*crtc_state,
return false;
}
+static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
+struct dp_sdp *sdp, size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ /*
+* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+* VSC SDP Header Bytes
+*/
+ sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+ sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
+ sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+ sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+
+ /* VSC SDP Payload for DB16 through DB18 */
+ /* Pixel Encoding and Colorimetry Formats */
+ sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
+ sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+
+ switch (vsc->bpc) {
+ case 8:
+ sdp->db[17] = 0x1; /* DB17[3:0] */
+ break;
+ case 10:
+ sdp->db[17] = 0x2;
+ break;
+ case 12:
+ sdp->db[17] = 0x3;
+ break;
+ case 16:
+ sdp->db[17] = 0x4;
+ break;
+ default:
+ MISSING_CASE(vsc->bpc);
+ break;
+ }
+ /* Dynamic Range and Component Bit Depth */
+ if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
+ sdp->db[17] |= 0x80; /* DB17[7] */
+
+ /* Content Type */
+ sdp->db[18] = vsc->content_type & 0x7;
+
+ return length;
+}
+
+static ssize_t
+intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
*drm_infoframe,
+struct dp_sdp *sdp,
+size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+ const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
HDMI_DRM_INFOFRAME_SIZE;
+ unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+ ssize_t len;
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
+ if (len < 0) {
+ DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
infoframe\n");
+ return -ENOSPC;
+ }
+
+ if (len != infoframe_size) {
+ DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+ return -ENOSPC;
+ }
+
+ /*
+* Set up the infoframe sdp packet for HDR static metadata.
+* Prepare VSC Header for SU as per DP 1.4a spec,
+* Table 2-100 and Table 2-101
+*/
+
+ /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
+ sdp->sdp_header.HB0 = 0;
+ /*
+* Packet Type 80h + Non-audio INFOFRAME Type value
+* HDMI_INFOFRAME_TYPE_DRM: 0x87
+* - 80h + Non-audio INFOFRAME Type value
+* - InfoFrame Type: 0x07
+*[CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
+*/
+ sdp->sdp_header.HB1 = drm_infoframe->type;
+ /*
+* Least Significant Eight Bits of (Data Byte Count – 1)
+* info
[Intel-gfx] [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() to make sure not to send VSC SDP and HDR Metadata Infoframe SDP. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 69073a15edb8..8509cd33569e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, INTEL_OUTPUT_DP_MST); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state); + /* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump. HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata Infoframe SDP use the same member variable in infoframes of crtc state. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 239861bcedba..593c63f51210 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) + intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(&pipe_config->hw.mode); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 03/17] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
It stores computed dp hdr metadata infoframe sdp to infoframes.drm of
crtc state. It referenced intel_hdmi_compute_drm_infoframe().
While computing, we'll also fill out the inforames.enable bitmask
appropriately.
v2: Wrap a long line.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2bdc43c80e03..b265b5c599f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,27 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
&crtc_state->infoframes.vsc);
}
+static void
+intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
*crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ int ret;
+ struct hdmi_drm_infoframe *drm_infoframe =
&crtc_state->infoframes.drm.drm;
+
+ if (!conn_state->hdr_output_metadata)
+ return;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
+
+ if (ret) {
+ DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
+ return;
+ }
+
+ crtc_state->infoframes.enable |=
+ intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -2569,6 +2590,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+ intel_dp_compute_hdr_metadata_infoframe_sdp(pipe_config, conn_state);
return 0;
}
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
v2: Minor style fix
v3: Move logging functions to drm core [Jani N]
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/drm_dp_helper.c | 174
include/drm/drm_dp_helper.h | 3 +
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5a103e9b3c86..5e3aef8c32e0 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+static const char *dp_colorspace_get_name(enum dp_colorspace colorspace)
+{
+ if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+ return "Invalid";
+
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "RGB";
+ case DP_COLORSPACE_YUV444:
+ return "YUV444";
+ case DP_COLORSPACE_YUV422:
+ return "YUV422";
+ case DP_COLORSPACE_YUV420:
+ return "YUV420";
+ case DP_COLORSPACE_Y_ONLY:
+ return "Y_ONLY";
+ case DP_COLORSPACE_RAW:
+ return "RAW";
+ default:
+ return "Reserved";
+ }
+}
+
+static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
+ enum dp_colorimetry colorimetry)
+{
+ if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
+ return "Invalid";
+
+ switch (colorimetry) {
+ case DP_COLORIMETRY_DEFAULT:
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "sRGB";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "BT.601";
+ case DP_COLORSPACE_Y_ONLY:
+ return "DICOM PS3.14";
+ case DP_COLORSPACE_RAW:
+ return "Custom Color Profile";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "Wide Fixed";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "BT.709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "Wide Float";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "xvYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "OpRGB";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "xvYCC 709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "DCI-P3";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "sYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "Custom Profile";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "OpYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+ switch (colorspace) {
+ case DP_COLORSPACE_RGB:
+ return "BT.2020 RGB";
+ case DP_COLORSPACE_YUV444:
+ case DP_COLORSPACE_YUV422:
+ case DP_COLORSPACE_YUV420:
+ return "BT.2020 CYCC";
+ default:
+
[Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM infoframe
It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.
In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.
It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.
Signed-off-by: Gwan-gyeong Mun
---
drivers/video/hdmi.c | 58 +++-
include/linux/hdmi.h | 2 ++
2 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 9c82e2a0a411..9818836d82b7 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
hdmi_vendor_any_infoframe *frame,
}
/**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI DRM
infoframe
* @frame: HDMI DRM infoframe
* @buffer: source buffer
* @size: size of buffer
*
- * Unpacks the information contained in binary @buffer into a structured
+ * Unpacks the information data block contained in binary @buffer into a
structured
* @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
*
* Returns 0 on success or a negative error code on failure.
*/
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
-const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
{
const u8 *ptr = buffer;
const u8 *temp;
@@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
int ret;
int i;
- if (size < HDMI_INFOFRAME_SIZE(DRM))
- return -EINVAL;
-
- if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
- ptr[1] != 1 ||
- ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
- return -EINVAL;
-
- if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ if (size < HDMI_DRM_INFOFRAME_SIZE)
return -EINVAL;
ret = hdmi_drm_infoframe_init(frame);
if (ret)
return ret;
- ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
frame->eotf = ptr[0] & 0x7;
frame->metadata_type = ptr[1] & 0x7;
@@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
return 0;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the information contained in binary @buffer into a structured
+ * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
+ * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+const void *buffer, size_t size)
+{
+ const u8 *ptr = buffer;
+ int ret;
+
+ if (size < HDMI_INFOFRAME_SIZE(DRM))
+ return -EINVAL;
+
+ if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+ ptr[1] != 1 ||
+ ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
HDMI_INFOFRAME_HEADER_SIZE,
+size - HDMI_INFOFRAME_HEADER_SIZE);
+ return ret;
+}
/**
* hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9918a6c910c5..afb43efc03e0 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe
*frame, void *buffer,
ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
void *buffer, size_t size);
int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size);
enum hdmi_spd_sdi {
HDMI_S
[Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
Before applying it, routines of program SDP always calculated configs when
they called. And it removes unused functions.
v3: Rebased
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 226 ---
drivers/gpu/drm/i915/display/intel_dp.h | 6 -
3 files changed, 1 insertion(+), 234 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c96f629cddc3..374ab6a3757c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
- intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
- intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d4ece0a824c0..cffb77daec96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp vsc_sdp = {};
-
- /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
- vsc_sdp.sdp_header.HB0 = 0;
- vsc_sdp.sdp_header.HB1 = 0x7;
-
- /*
-* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-* Colorimetry Format indication.
-*/
- vsc_sdp.sdp_header.HB2 = 0x5;
-
- /*
-* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
-* Colorimetry Format indication (HB2 = 05h).
-*/
- vsc_sdp.sdp_header.HB3 = 0x13;
-
- /* DP 1.4a spec, Table 2-120 */
- switch (crtc_state->output_format) {
- case INTEL_OUTPUT_FORMAT_YCBCR444:
- vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
- break;
- case INTEL_OUTPUT_FORMAT_YCBCR420:
- vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
- break;
- case INTEL_OUTPUT_FORMAT_RGB:
- default:
- /* RGB: DB16[7:4] = 0h */
- break;
- }
-
- switch (conn_state->colorspace) {
- case DRM_MODE_COLORIMETRY_BT709_YCC:
- vsc_sdp.db[16] |= 0x1;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_601:
- vsc_sdp.db[16] |= 0x2;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_709:
- vsc_sdp.db[16] |= 0x3;
- break;
- case DRM_MODE_COLORIMETRY_SYCC_601:
- vsc_sdp.db[16] |= 0x4;
- break;
- case DRM_MODE_COLORIMETRY_OPYCC_601:
- vsc_sdp.db[16] |= 0x5;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_CYCC:
- case DRM_MODE_COLORIMETRY_BT2020_RGB:
- vsc_sdp.db[16] |= 0x6;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_YCC:
- vsc_sdp.db[16] |= 0x7;
- break;
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
- vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
- break;
- default:
- /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
- /* RGB->YCBCR color conversion uses the BT.709 color space. */
- if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
- break;
- }
-
- /*
-* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
-* the following Component Bit Depth values are defined:
-* 001b = 8bpc.
-* 010b = 10bpc.
-* 011b = 12bpc.
-* 100b = 16bpc.
-*/
- switch (crtc_state->pipe_bpp) {
- case 24: /* 8bpc */
- vsc_sdp.db[17] = 0x1;
- break;
- case 30: /* 10bpc */
- vsc_sdp.db[17] = 0x2;
- break;
- case 36: /* 12bpc */
- vsc_sdp.db[17] = 0x3;
- break;
- case 48: /* 16bpc */
- vsc_
[Intel-gfx] [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates
Call intel_dp_set_infoframes() function on pipe updates to make sure that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 64e4edefa998..69073a15edb8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, intel_ddi_set_dp_msa(crtc_state, conn_state); intel_psr_update(intel_dp, crtc_state); + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); intel_edp_drrs_enable(intel_dp, crtc_state); intel_panel_update_backlight(encoder, crtc_state, conn_state); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
Added state readout for DP HDR Metadata Infoframe SDP. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 374ab6a3757c..a9eaf7a6bc15 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, pipe_config->fec_enable); } + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); + break; case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ -4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); intel_dp_get_m_n(intel_crtc, pipe_config); + + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); break; default: break; @@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_infoframe(encoder, pipe_config, HDMI_INFOFRAME_TYPE_DRM, &pipe_config->infoframes.drm); + + intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); } static enum intel_output_type -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.
In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.
There are no changes to PSR mechanism.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 54 +++-
drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 22 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8509cd33569e..00b46c45f6a8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_dp_stop_link_train(intel_dp);
intel_edp_backlight_on(crtc_state, conn_state);
- intel_psr_enable(intel_dp, crtc_state);
+ intel_psr_enable(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
@@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
*encoder,
intel_ddi_set_dp_msa(crtc_state, conn_state);
- intel_psr_update(intel_dp, crtc_state);
+ intel_psr_update(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index e41ed962aa80..a4564607b6c5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
}
}
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct dp_sdp psr_vsc;
-
- if (dev_priv->psr.psr2_enabled) {
- /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- if (dev_priv->psr.colorimetry_support) {
- psr_vsc.sdp_header.HB2 = 0x5;
- psr_vsc.sdp_header.HB3 = 0x13;
- } else {
- psr_vsc.sdp_header.HB2 = 0x4;
- psr_vsc.sdp_header.HB3 = 0xe;
- }
- } else {
- /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
- memset(&psr_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x2;
- psr_vsc.sdp_header.HB3 = 0x8;
- }
-
- intel_dig_port->write_infoframe(&intel_dig_port->base,
- crtc_state,
- DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
-}
-
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -841,9 +808,12 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
{
struct intel_dp *intel_dp = dev_priv->psr.dp;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
u32 val;
WARN_ON(dev_priv->psr.enabled);
@@ -881,7 +851,9 @@ static void intel_psr_enable_locked(struct drm_i915_private
*dev_priv,
DRM_DEBUG_KMS("Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
- intel_psr_setup_vsc(intel_dp, crtc_state);
+ intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+&dev_priv->psr.vsc);
+ intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state
[Intel-gfx] [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 53 +
drivers/gpu/drm/i915/display/intel_dp.h | 8
2 files changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cffb77daec96..4d65ef36577f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
&crtc_state->infoframes.vsc);
}
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ vsc->sdp_type = DP_SDP_VSC;
+
+ if (dev_priv->psr.psr2_enabled) {
+ if (dev_priv->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [PSR2, +Colorimetry] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+vsc);
+ } else {
+ /*
+* [PSR2, -Colorimetry]
+* Prepare VSC Header for SU as per eDP 1.4 spec, Table
6-11
+* 3D stereo + PSR/PSR2 + Y-coordinate.
+*/
+ vsc->revision = 0x4;
+ vsc->length = 0xe;
+ }
+ } else {
+ /*
+* [PSR1]
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+* higher).
+*/
+ vsc->revision = 0x2;
+ vsc->length = 0x8;
+ }
+}
+
static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
*crtc_state,
const struct drm_connector_state
*conn_state)
@@ -4889,6 +4925,23 @@ static void intel_write_dp_sdp(struct intel_encoder
*encoder,
intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
}
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct dp_sdp sdp = {};
+ ssize_t len;
+
+ len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
+
+ if (WARN_ON(len < 0))
+ return;
+
+ intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+ &sdp, len);
+}
+
void intel_dp_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 6562bb8edeba..5074e52722c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -18,6 +18,7 @@ struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
@@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
--
2.
[Intel-gfx] [PATCH v3 01/17] drm: add DP 1.4 VSC SDP Payload related enums and a structure
It adds new enumeration definitions for VSC SDP Payload for Pixel
Encoding/Colorimetry Format.
And it adds a new drm data structure for DP VSC SDP.
enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
And enum dp_content_type corresponds "Content Type"
All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
v3: Add a new drm data structure for DP VSC SDP
Signed-off-by: Gwan-gyeong Mun
---
include/drm/drm_dp_helper.h | 57 +
1 file changed, 57 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 262faf9e5e94..c098727681fa 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1209,6 +1209,63 @@ struct dp_sdp {
#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
+/* Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18] */
+enum dp_colorspace {
+ DP_COLORSPACE_RGB = 0,
+ DP_COLORSPACE_YUV444 = 0x1,
+ DP_COLORSPACE_YUV422 = 0x2,
+ DP_COLORSPACE_YUV420 = 0x3,
+ DP_COLORSPACE_Y_ONLY = 0x4,
+ DP_COLORSPACE_RAW = 0x5,
+ DP_COLORSPACE_RESERVED = 0x6,
+};
+
+/**
+ * Based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through DB18]
+ * and a name of enum member followes DRM_MODE_COLORIMETRY definition.
+ */
+enum dp_colorimetry {
+ DP_COLORIMETRY_DEFAULT = 0, /* sRGB (IEC 61966-2-1) / ITU-R BT.601 */
+ DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
+ DP_COLORIMETRY_BT709_YCC = 0x1,
+ DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
+ DP_COLORIMETRY_XVYCC_601 = 0x2,
+ DP_COLORIMETRY_OPRGB = 0x3,
+ DP_COLORIMETRY_XVYCC_709 = 0x3,
+ DP_COLORIMETRY_DCI_P3_RGB = 0x4,
+ DP_COLORIMETRY_SYCC_601 = 0x4,
+ DP_COLORIMETRY_RGB_CUSTOM = 0x5,
+ DP_COLORIMETRY_OPYCC_601 = 0x5,
+ DP_COLORIMETRY_BT2020_RGB = 0x6,
+ DP_COLORIMETRY_BT2020_CYCC = 0x6,
+ DP_COLORIMETRY_BT2020_YCC = 0x7,
+};
+
+enum dp_dynamic_range {
+ DP_DYNAMIC_RANGE_VESA = 0,
+ DP_DYNAMIC_RANGE_CTA = 1,
+};
+
+enum dp_content_type {
+ DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
+ DP_CONTENT_TYPE_GRAPHICS = 0x01,
+ DP_CONTENT_TYPE_PHOTO = 0x02,
+ DP_CONTENT_TYPE_VIDEO = 0x03,
+ DP_CONTENT_TYPE_GAME = 0x04,
+};
+
+/* DRM DP VSC SDP as per DP 1.4 spec */
+struct drm_dp_vsc_sdp {
+ unsigned char sdp_type; /* Secondary-data Packet Type */
+ unsigned char revision; /* Revision Number */
+ unsigned char length; /* Number of Valid Data Bytes */
+ enum dp_colorspace colorspace;
+ enum dp_colorimetry colorimetry;
+ int bpc; /* bit per color */
+ enum dp_dynamic_range dynamic_range;
+ enum dp_content_type content_type;
+};
+
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
--
2.24.1
___
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[Intel-gfx] [PATCH v3 02/17] drm/i915/dp: Add compute routine for DP VSC SDP
In order to support state readout for DP VSC SDP, we need to have a
structure which holds DP VSC SDP payload data such as
"union hdmi_infoframe drm" which is used for DRM infoframe.
It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.
And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
While computing we'll also fill out the inforames.enable bitmask
appropriately.
The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Signed-off-by: Gwan-gyeong Mun
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 92 +++
2 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 33ba93863488..6633c1061670 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1021,6 +1021,7 @@ struct intel_crtc_state {
union hdmi_infoframe spd;
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
+ struct drm_dp_vsc_sdp vsc;
} infoframes;
/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..2bdc43c80e03 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2372,6 +2372,97 @@ static bool intel_dp_port_has_audio(struct
drm_i915_private *dev_priv,
return true;
}
+static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state
*crtc_state,
+const struct drm_connector_state
*conn_state,
+struct drm_dp_vsc_sdp *vsc)
+{
+ /*
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+* Colorimetry Format indication.
+*/
+ vsc->revision = 0x5;
+ vsc->length = 0x13;
+
+ /* DP 1.4a spec, Table 2-120 */
+ switch (crtc_state->output_format) {
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ vsc->colorspace = DP_COLORSPACE_YUV444;
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ vsc->colorspace = DP_COLORSPACE_YUV420;
+ break;
+ case INTEL_OUTPUT_FORMAT_RGB:
+ default:
+ vsc->colorspace = DP_COLORSPACE_RGB;
+ }
+
+ switch (conn_state->colorspace) {
+ case DRM_MODE_COLORIMETRY_BT709_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_709:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
+ break;
+ case DRM_MODE_COLORIMETRY_SYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_OPYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_RGB:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+ vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
+ break;
+ default:
+ /*
+* RGB->YCBCR color conversion uses the BT.709
+* color space.
+*/
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ else
+ vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
+ break;
+ }
+
+ vsc->bpc = crtc_state->pipe_bpp / 3;
+ /* all YCbCr are always limited range */
+ vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
+ vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
+}
+
+static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+struct intel_crtc_state *crtc_state,
+const struct drm_connector_state
*conn_state)
+{
+ struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
+
+ /* When PSR is enabled, VSC SDP is handled by PSR routine */
+ if (intel_psr_enabled(intel_dp))
+ return;
+
+ if (!intel_dp_needs_vsc_sdp(crtc_s
[Intel-gfx] [PATCH v3 00/17] In order to readout DP SDPs, refactors the handling of DP SDPs
In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes. It adds new compute routines for DP HDR Metadata Infoframe SDP and DP VSC SDP. And new writing routines of DP SDPs (Secondary Data Packet) that uses computed configs. New reading routines of DP SDPs are added for readout. It adds a logging function for DP VSC SDP. When receiving video it is very useful to be able to log DP VSC SDP. This greatly simplifies debugging. In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses a new psr vsc sdp compute routine. v2: Minor style fix v3: - Add a new drm data structure for DP VSC SDP - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp - Move logging functions to drm core [Jani N] And use drm core's DP VSC SDP logging function - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be used for HDMI), when intel_dp_set_infoframes() function will be called. Gwan-gyeong Mun (17): drm: add DP 1.4 VSC SDP Payload related enums and a structure drm/i915/dp: Add compute routine for DP VSC SDP drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet) video/hdmi: Add Unpack only function for DRM infoframe drm/i915/dp: Read out DP SDPs (Secondary Data Packet) drm: Add logging function for DP VSC SDP drm/i915: Include HDMI DRM infoframe in the crtc state dump drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump drm/i915: Include DP VSC SDP in the crtc state dump drm/i915: Program DP SDPs with computed configs drm/i915: Add state readout for DP HDR Metadata Infoframe SDP drm/i915: Add state readout for DP VSC SDP drm/i915: Program DP SDPs on pipe updates drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp() drm/i915/dp: Add compute routine for DP PSR VSC SDP drm/i915/psr: Use new DP VSC SDP compute routine on PSR drivers/gpu/drm/drm_dp_helper.c | 174 + drivers/gpu/drm/i915/display/intel_ddi.c | 19 +- drivers/gpu/drm/i915/display/intel_display.c | 61 ++ .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 607 +- drivers/gpu/drm/i915/display/intel_dp.h | 18 +- drivers/gpu/drm/i915/display/intel_psr.c | 54 +- drivers/gpu/drm/i915/display/intel_psr.h | 6 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/video/hdmi.c | 58 +- include/drm/drm_dp_helper.h | 60 ++ include/linux/hdmi.h | 2 + 12 files changed, 843 insertions(+), 218 deletions(-) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/18] drm/i915/dp: Add logging function for DP VSC SDP
On Sat, 2020-02-01 at 14:43 +0200, Jani Nikula wrote:
> On Fri, 31 Jan 2020, Gwan-gyeong Mun
> wrote:
> > When receiving video it is very useful to be able to log DP VSC
> > SDP.
> > This greatly simplifies debugging.
>
> Seems like a lot of the functions should really be in drm core.
>
> BR,
> Jani.
Hi,
Okay, I'll move these logging functions to drm core.
Br,
G.G.
>
> > Signed-off-by: Gwan-gyeong Mun
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 173
> >
> > drivers/gpu/drm/i915/display/intel_dp.h | 4 +
> > 2 files changed, 177 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 6756030692c8..e33488222ac5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5090,6 +5090,179 @@ void intel_read_dp_sdp(struct intel_encoder
> > *encoder,
> > }
> > }
> >
> > +static const char *dp_colorspace_get_name(enum dp_colorspace
> > colorspace)
> > +{
> > + if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> > + return "Invalid";
> > +
> > + switch (colorspace) {
> > + case DP_COLORSPACE_RGB:
> > + return "RGB";
> > + case DP_COLORSPACE_YUV444:
> > + return "YUV444";
> > + case DP_COLORSPACE_YUV422:
> > + return "YUV422";
> > + case DP_COLORSPACE_YUV420:
> > + return "YUV420";
> > + case DP_COLORSPACE_Y_ONLY:
> > + return "Y_ONLY";
> > + case DP_COLORSPACE_RAW:
> > + return "RAW";
> > + default:
> > + return "Reserved";
> > + }
> > +}
> > +
> > +static const char *dp_colorimetry_get_name(enum dp_colorspace
> > colorspace,
> > + enum dp_colorimetry
> > colorimetry)
> > +{
> > + if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> > + return "Invalid";
> > +
> > + switch (colorimetry) {
> > + case DP_COLORIMETRY_DEFAULT:
> > + switch (colorspace) {
> > + case DP_COLORSPACE_RGB:
> > + return "sRGB";
> > + case DP_COLORSPACE_YUV444:
> > + case DP_COLORSPACE_YUV422:
> > + case DP_COLORSPACE_YUV420:
> > + return "BT.601";
> > + case DP_COLORSPACE_Y_ONLY:
> > + return "DICOM PS3.14";
> > + case DP_COLORSPACE_RAW:
> > + return "Custom Color Profile";
> > + default:
> > + return "Reserved";
> > + }
> > + case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and
> > DP_COLORIMETRY_BT709_YCC */
> > + switch (colorspace) {
> > + case DP_COLORSPACE_RGB:
> > + return "Wide Fixed";
> > + case DP_COLORSPACE_YUV444:
> > + case DP_COLORSPACE_YUV422:
> > + case DP_COLORSPACE_YUV420:
> > + return "BT.709";
> > + default:
> > + return "Reserved";
> > + }
> > + case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and
> > DP_COLORIMETRY_XVYCC_601 */
> > + switch (colorspace) {
> > + case DP_COLORSPACE_RGB:
> > + return "Wide Float";
> > + case DP_COLORSPACE_YUV444:
> > + case DP_COLORSPACE_YUV422:
> > + case DP_COLORSPACE_YUV420:
> > + return "xvYCC 601";
> > + default:
> > + return "Reserved";
> > + }
> > + case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
> > + switch (colorspace) {
> > + case DP_COLORSPACE_RGB:
> > + return "OpRGB";
> > + case DP_COLORSPACE_YUV444:
> > + case DP_COLORSPACE_YUV422:
> > + case DP_COLORSPACE_YUV420:
> > + return "xvYCC 709";
> > + default:
> > + return "Reserved";
> > + }
> > + case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601
> > */
> > + switch (colorspace) {
> > + case DP_COLORSPACE_RGB:
> > + return "DCI-P3";
> > + case DP_COLORSPACE_YUV444:
> > + case DP_COLORSPACE_YUV422:
> > + case DP_COLORSPACE_YUV420:
> > + return "sYCC 601";
> > + default:
> > + return "Reserved";
> > + }
> > + case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601
> > */
> > + switch (colorspace) {
> > + case DP_COLORSPACE_RGB:
> > + return "Custom Profile";
> > + case DP_COLORSPACE_YUV444:
> > + case DP_COLORSPACE_YUV422:
> > + case DP_COLORSPACE_YUV420:
> > + return "OpYCC 601";
> > + default:
> > + return "Reserved";
> > + }
> > + case DP_COLORIMETRY_BT2020_RGB: /* and
> > DP_COLORIMETRY_BT2020_CYCC */
> > + switch (colorspace) {
> > + case DP_COLORS
[Intel-gfx] [PATCH v2] drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when clearing DDI select
TGL is suffering of timeouts and fifo underruns when disabling
transcoder in MST mode, this is fixed by set TRANS_DDI_MODE_SELECT to
0(HDMI mode) when clearing DDI select.
Although BSpec disable sequence don't require this step, it is a
harmless change and it is also done by Windows driver.
Anyhow HW team was notified about that but it can take some time to
documentation to be updated.
A case that always lead to those issues is:
- do a modeset enabling pipe A and pipe B in the same MST stream
leaving A as master
- disable pipe A, promote B as master doing a full modeset in A
- enable pipe A, changing the master transcoder back to A(doing a
full modeset in B)
- Pow: underruns and timeouts
The transcoders involved will only work again when complete disabled
and their power wells turned off causing a reset in their registers.
v2: Setting TRANS_DDI_MODE_SELECT to default when clearing DDI select
not anymore when disabling TRANS_DDI, both work but this one looks
more safe. (Ville comment)
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index aa066fb9eb00..45082e71262c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1988,10 +1988,12 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
val &= ~TRANS_DDI_FUNC_ENABLE;
if (INTEL_GEN(dev_priv) >= 12) {
- if (!intel_dp_mst_is_master_trans(crtc_state))
+ if (!intel_dp_mst_is_master_trans(crtc_state)) {
val &= ~TGL_TRANS_DDI_PORT_MASK;
+ val &= ~TRANS_DDI_MODE_SELECT_MASK;
+ }
} else {
- val &= ~TRANS_DDI_PORT_MASK;
+ val &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
}
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), val);
@@ -3729,6 +3731,7 @@ static void intel_ddi_post_disable_dp(struct
intel_encoder *encoder,
val = intel_de_read(dev_priv,
TRANS_DDI_FUNC_CTL(cpu_transcoder));
val &= ~TGL_TRANS_DDI_PORT_MASK;
+ val &= ~TRANS_DDI_MODE_SELECT_MASK;
intel_de_write(dev_priv,
TRANS_DDI_FUNC_CTL(cpu_transcoder),
val);
--
2.25.0
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_basic: Drop per-engine testing of *execbuf
On 03/02/20 13:45, Chris Wilson wrote:
The gtt/readonly tests are nothing to do with execution and engines;
they are strictly checking the copy-from-user of the ioctl arguments.
Drop the silly per-engine tests.
Signed-off-by: Chris Wilson
Cc: Antonio Argenziano
LGTM.
Reviewed-by: Antonio Argenziano
---
tests/i915/gem_exec_basic.c | 109 +--
tests/i915/gem_exec_params.c | 61
2 files changed, 76 insertions(+), 94 deletions(-)
diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index 70dce34b5..0d05819ce 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -36,84 +36,6 @@ static uint32_t batch_create(int fd)
return handle;
}
-static void batch_fini(int fd, uint32_t handle)
-{
- gem_sync(fd, handle); /* catch any GPU hang */
- gem_close(fd, handle);
-}
-
-static void noop(int fd, uint64_t flags)
-{
- struct drm_i915_gem_execbuffer2 execbuf;
- struct drm_i915_gem_exec_object2 exec;
-
- gem_require_ring(fd, flags);
-
- memset(&exec, 0, sizeof(exec));
-
- exec.handle = batch_create(fd);
-
- memset(&execbuf, 0, sizeof(execbuf));
- execbuf.buffers_ptr = to_user_pointer(&exec);
- execbuf.buffer_count = 1;
- execbuf.flags = flags;
- gem_execbuf(fd, &execbuf);
-
- batch_fini(fd, exec.handle);
-}
-
-static void readonly(int fd, uint64_t flags)
-{
- struct drm_i915_gem_execbuffer2 *execbuf;
- struct drm_i915_gem_exec_object2 exec;
-
- gem_require_ring(fd, flags);
-
- memset(&exec, 0, sizeof(exec));
- exec.handle = batch_create(fd);
-
- execbuf = mmap(NULL, 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
- igt_assert(execbuf != NULL);
-
- execbuf->buffers_ptr = to_user_pointer(&exec);
- execbuf->buffer_count = 1;
- execbuf->flags = flags;
- igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
-
- gem_execbuf(fd, execbuf);
-
- munmap(execbuf, 4096);
-
- batch_fini(fd, exec.handle);
-}
-
-static void gtt(int fd, uint64_t flags)
-{
- struct drm_i915_gem_execbuffer2 *execbuf;
- struct drm_i915_gem_exec_object2 *exec;
- uint32_t handle;
-
- gem_require_ring(fd, flags);
-
- handle = gem_create(fd, 4096);
-
- gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
- execbuf = gem_mmap__gtt(fd, handle, 4096, PROT_WRITE);
- exec = (struct drm_i915_gem_exec_object2 *)(execbuf + 1);
- gem_close(fd, handle);
-
- exec->handle = batch_create(fd);
-
- execbuf->buffers_ptr = to_user_pointer(exec);
- execbuf->buffer_count = 1;
- execbuf->flags = flags;
-
- gem_execbuf(fd, execbuf);
-
- batch_fini(fd, exec->handle);
- munmap(execbuf, 4096);
-}
-
igt_main
{
const struct intel_execution_engine2 *e;
@@ -121,30 +43,29 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
- igt_require_gem(fd);
-
+ /* igt_require_gem(fd); // test is mandatory */
igt_fork_hang_detector(fd);
}
igt_subtest_with_dynamic("basic") {
- __for_each_physical_engine(fd, e) {
- igt_dynamic_f("%s", e->name)
- noop(fd, e->flags);
- }
- }
+ struct drm_i915_gem_exec_object2 exec = {
+ .handle = batch_create(fd),
+ };
- igt_subtest_with_dynamic("readonly") {
__for_each_physical_engine(fd, e) {
- igt_dynamic_f("%s", e->name)
- readonly(fd, e->flags);
+ igt_dynamic_f("%s", e->name) {
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&exec),
+ .buffer_count = 1,
+ .flags = e->flags,
+ };
+
+ gem_execbuf(fd, &execbuf);
+ }
}
- }
- igt_subtest_with_dynamic("gtt") {
- __for_each_physical_engine(fd, e) {
- igt_dynamic_f("%s", e->name)
- gtt(fd, e->flags);
- }
+ gem_sync(fd, exec.handle); /* catch any GPU hang */
+ gem_close(fd, exec.handle);
}
igt_fixture {
diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index 9c3525698..094fa904c 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -206,6 +206,61 @@ static int has_secure_batches(const int fd)
return v > 0;
}
+static uint32_t batch_create(int fd)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_cr
Re: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_basic: Drop per-engine testing of *execbuf
On 03/02/20 14:18, Chris Wilson wrote:
Quoting Antonio Argenziano (2020-02-03 22:15:26)
On 03/02/20 13:45, Chris Wilson wrote:
@@ -121,30 +43,29 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
- igt_require_gem(fd);
-
+ /* igt_require_gem(fd); // test is mandatory */
What if that fd is bad? Assert?
fd can't be bad, that's taken care of by drm_open_driver(). If the
driver is unusable for execbuf, we want the test failure. It's a choice.
Not sure the right answer, both have advantages.
Fair enough.
+static void mmapped(int i915)
+{
+ struct drm_i915_gem_execbuffer2 *execbuf;
+ struct drm_i915_gem_exec_object2 *exec;
+ uint32_t handle;
gem_require_mappable_ggtt()?
No... I was dropping a hint in the name. How's the toolbox?
I'm afraid I'm not the right person to develop new stuff for IGT...
gem_require_mappable_ggtt() /* insert comment about extending the test
*/? :)
Antonio
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_basic: Drop per-engine testing of *execbuf
Quoting Antonio Argenziano (2020-02-03 22:15:26)
>
>
> On 03/02/20 13:45, Chris Wilson wrote:
> > @@ -121,30 +43,29 @@ igt_main
> >
> > igt_fixture {
> > fd = drm_open_driver(DRIVER_INTEL);
> > - igt_require_gem(fd);
> > -
> > + /* igt_require_gem(fd); // test is mandatory */
>
> What if that fd is bad? Assert?
fd can't be bad, that's taken care of by drm_open_driver(). If the
driver is unusable for execbuf, we want the test failure. It's a choice.
Not sure the right answer, both have advantages.
> > +static void mmapped(int i915)
> > +{
> > + struct drm_i915_gem_execbuffer2 *execbuf;
> > + struct drm_i915_gem_exec_object2 *exec;
> > + uint32_t handle;
>
> gem_require_mappable_ggtt()?
No... I was dropping a hint in the name. How's the toolbox?
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_basic: Drop per-engine testing of *execbuf
On 03/02/20 13:45, Chris Wilson wrote:
The gtt/readonly tests are nothing to do with execution and engines;
they are strictly checking the copy-from-user of the ioctl arguments.
Drop the silly per-engine tests.
Signed-off-by: Chris Wilson
Cc: Antonio Argenziano
---
tests/i915/gem_exec_basic.c | 109 +--
tests/i915/gem_exec_params.c | 61
2 files changed, 76 insertions(+), 94 deletions(-)
diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index 70dce34b5..0d05819ce 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -36,84 +36,6 @@ static uint32_t batch_create(int fd)
return handle;
}
-static void batch_fini(int fd, uint32_t handle)
-{
- gem_sync(fd, handle); /* catch any GPU hang */
- gem_close(fd, handle);
-}
-
-static void noop(int fd, uint64_t flags)
-{
- struct drm_i915_gem_execbuffer2 execbuf;
- struct drm_i915_gem_exec_object2 exec;
-
- gem_require_ring(fd, flags);
-
- memset(&exec, 0, sizeof(exec));
-
- exec.handle = batch_create(fd);
-
- memset(&execbuf, 0, sizeof(execbuf));
- execbuf.buffers_ptr = to_user_pointer(&exec);
- execbuf.buffer_count = 1;
- execbuf.flags = flags;
- gem_execbuf(fd, &execbuf);
-
- batch_fini(fd, exec.handle);
-}
-
-static void readonly(int fd, uint64_t flags)
-{
- struct drm_i915_gem_execbuffer2 *execbuf;
- struct drm_i915_gem_exec_object2 exec;
-
- gem_require_ring(fd, flags);
-
- memset(&exec, 0, sizeof(exec));
- exec.handle = batch_create(fd);
-
- execbuf = mmap(NULL, 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
- igt_assert(execbuf != NULL);
-
- execbuf->buffers_ptr = to_user_pointer(&exec);
- execbuf->buffer_count = 1;
- execbuf->flags = flags;
- igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
-
- gem_execbuf(fd, execbuf);
-
- munmap(execbuf, 4096);
-
- batch_fini(fd, exec.handle);
-}
-
-static void gtt(int fd, uint64_t flags)
-{
- struct drm_i915_gem_execbuffer2 *execbuf;
- struct drm_i915_gem_exec_object2 *exec;
- uint32_t handle;
-
- gem_require_ring(fd, flags);
-
- handle = gem_create(fd, 4096);
-
- gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
- execbuf = gem_mmap__gtt(fd, handle, 4096, PROT_WRITE);
- exec = (struct drm_i915_gem_exec_object2 *)(execbuf + 1);
- gem_close(fd, handle);
-
- exec->handle = batch_create(fd);
-
- execbuf->buffers_ptr = to_user_pointer(exec);
- execbuf->buffer_count = 1;
- execbuf->flags = flags;
-
- gem_execbuf(fd, execbuf);
-
- batch_fini(fd, exec->handle);
- munmap(execbuf, 4096);
-}
-
igt_main
{
const struct intel_execution_engine2 *e;
@@ -121,30 +43,29 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
- igt_require_gem(fd);
-
+ /* igt_require_gem(fd); // test is mandatory */
What if that fd is bad? Assert?
igt_fork_hang_detector(fd);
}
igt_subtest_with_dynamic("basic") {
- __for_each_physical_engine(fd, e) {
- igt_dynamic_f("%s", e->name)
- noop(fd, e->flags);
- }
- }
+ struct drm_i915_gem_exec_object2 exec = {
+ .handle = batch_create(fd),
+ };
- igt_subtest_with_dynamic("readonly") {
__for_each_physical_engine(fd, e) {
- igt_dynamic_f("%s", e->name)
- readonly(fd, e->flags);
+ igt_dynamic_f("%s", e->name) {
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&exec),
+ .buffer_count = 1,
+ .flags = e->flags,
+ };
+
+ gem_execbuf(fd, &execbuf);
+ }
}
- }
- igt_subtest_with_dynamic("gtt") {
- __for_each_physical_engine(fd, e) {
- igt_dynamic_f("%s", e->name)
- gtt(fd, e->flags);
- }
+ gem_sync(fd, exec.handle); /* catch any GPU hang */
+ gem_close(fd, exec.handle);
}
igt_fixture {
diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index 9c3525698..094fa904c 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -206,6 +206,61 @@ static int has_secure_batches(const int fd)
return v > 0;
}
+static uint32_t batch_create(int fd)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd,
Re: [Intel-gfx] [PATCH 5/5] drm: Remove exports for drm_pci_alloc/drm_pci_free
On Sun, Feb 2, 2020 at 12:16 PM Chris Wilson wrote:
>
> The drm_pci_alloc routines have been a thin wrapper around the core dma
> coherent routines. Remove the crutch of a wrapper and the exported
> symbols, marking it for only internal legacy use.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_bufs.c | 5 +++--
> drivers/gpu/drm/drm_legacy.h | 23 +++
> drivers/gpu/drm/drm_pci.c| 31 ++-
> include/drm/drm_pci.h| 18 --
> 4 files changed, 32 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
> index 19297e58b232..a33df3744f76 100644
> --- a/drivers/gpu/drm/drm_bufs.c
> +++ b/drivers/gpu/drm/drm_bufs.c
> @@ -675,7 +675,7 @@ static void drm_cleanup_buf_error(struct drm_device *dev,
> if (entry->seg_count) {
> for (i = 0; i < entry->seg_count; i++) {
> if (entry->seglist[i]) {
> - drm_pci_free(dev, entry->seglist[i]);
> + drm_legacy_pci_free(dev, entry->seglist[i]);
> }
> }
> kfree(entry->seglist);
> @@ -975,7 +975,8 @@ int drm_legacy_addbufs_pci(struct drm_device *dev,
>
> while (entry->buf_count < count) {
>
> - dmah = drm_pci_alloc(dev, PAGE_SIZE << page_order, 0x1000);
> + dmah = drm_legacy_pci_alloc(dev,
> + PAGE_SIZE << page_order, 0x1000);
>
> if (!dmah) {
> /* Set count correctly so we free the proper amount.
> */
> diff --git a/drivers/gpu/drm/drm_legacy.h b/drivers/gpu/drm/drm_legacy.h
> index 1be3ea320474..3853b45341c7 100644
> --- a/drivers/gpu/drm/drm_legacy.h
> +++ b/drivers/gpu/drm/drm_legacy.h
> @@ -36,6 +36,7 @@
>
> struct agp_memory;
> struct drm_device;
> +struct drm_dma_handle;
> struct drm_file;
> struct drm_buf_desc;
>
> @@ -211,4 +212,26 @@ void drm_master_legacy_init(struct drm_master *master);
> static inline void drm_master_legacy_init(struct drm_master *master) {}
> #endif
>
> +
> +#if IS_ENABLED(CONFIG_DRM_LEGACY) && IS_ENABLED(CONFIG_PCI)
> +
> +struct drm_dma_handle *
> +drm_legacy_pci_alloc(struct drm_device *dev, size_t size, size_t align);
> +void drm_legacy_pci_free(struct drm_device *dev, struct drm_dma_handle *
> dmah);
> +
> +#else
> +
> +static inline struct drm_dma_handle *
> +drm_legacy_pci_alloc(struct drm_device *dev, size_t size, size_t align)
> +{
> + return NULL;
> +}
> +
> +static inline void drm_legacy_pci_free(struct drm_device *dev,
> + struct drm_dma_handle *dmah)
> +{
> +}
> +
> +#endif
> +
> #endif /* __DRM_LEGACY_H__ */
> diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
> index c6bb98729a26..12239498538c 100644
> --- a/drivers/gpu/drm/drm_pci.c
> +++ b/drivers/gpu/drm/drm_pci.c
> @@ -36,19 +36,10 @@
> #include "drm_internal.h"
> #include "drm_legacy.h"
>
> -/**
> - * drm_pci_alloc - Allocate a PCI consistent memory block, for DMA.
> - * @dev: DRM device
> - * @size: size of block to allocate
> - * @align: alignment of block
> - *
> - * FIXME: This is a needless abstraction of the Linux dma-api and should be
> - * removed.
> - *
> - * Return: A handle to the allocated memory block on success or NULL on
> - * failure.
> - */
> -drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t
> align)
> +#if IS_ENABLED(CONFIG_DRM_LEGACY) && IS_ENABLED(CONFIG_PCI)
> +
> +drm_dma_handle_t *
> +drm_legacy_pci_alloc(struct drm_device * dev, size_t size, size_t align)
> {
> drm_dma_handle_t *dmah;
>
> @@ -76,24 +67,14 @@ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev,
> size_t size, size_t ali
> return dmah;
> }
>
> -EXPORT_SYMBOL(drm_pci_alloc);
> -
> -/**
> - * drm_pci_free - Free a PCI consistent memory block
> - * @dev: DRM device
> - * @dmah: handle to memory block
> - *
> - * FIXME: This is a needless abstraction of the Linux dma-api and should be
> - * removed.
> - */
> -void drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
> +void drm_legacy_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
> {
> dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr,
> dmah->busaddr);
> kfree(dmah);
> }
>
> -EXPORT_SYMBOL(drm_pci_free);
> +#endif
>
> static int drm_get_pci_domain(struct drm_device *dev)
> {
> diff --git a/include/drm/drm_pci.h b/include/drm/drm_pci.h
> index 9031e217b506..cade5b60b643 100644
> --- a/include/drm/drm_pci.h
> +++ b/include/drm/drm_pci.h
> @@ -34,34 +34,16 @@
>
> #include
>
> -struct drm_dma_handle;
> -struct drm_device;
> struct drm_driver;
> -struct drm_master;
>
> #ifdef CONFIG_PCI
>
> -struct drm_dma_handle *drm_pci_alloc(struct drm_device *dev, size_t size,
> -size_
Re: [Intel-gfx] [PATCH 3/5] drm/r128: Wean off drm_pci_alloc
On Sun, Feb 2, 2020 at 12:16 PM Chris Wilson wrote:
>
> drm_pci_alloc is a thin wrapper over dma_coherent_alloc. Ditch the
> wrapper and just use the dma routines directly.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/r128/ati_pcigart.c | 32 +++---
> drivers/gpu/drm/r128/ati_pcigart.h | 2 +-
> 2 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/r128/ati_pcigart.c
> b/drivers/gpu/drm/r128/ati_pcigart.c
> index 9b4072f97215..3d67afbbf0fc 100644
> --- a/drivers/gpu/drm/r128/ati_pcigart.c
> +++ b/drivers/gpu/drm/r128/ati_pcigart.c
> @@ -44,9 +44,12 @@
> static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
>struct drm_ati_pcigart_info *gart_info)
> {
> - gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
> - PAGE_SIZE);
> - if (gart_info->table_handle == NULL)
> + gart_info->addr =
> + dma_alloc_coherent(&dev->pdev->dev,
> + gart_info->table_size,
> + ^gart_info->bus_addr,
Stray ^ here. With that fixed:
Reviewed-by: Alex Deucher
> + GFP_KERNEL);
> + if (!gart_info->addr)
> return -ENOMEM;
>
> return 0;
> @@ -55,8 +58,10 @@ static int drm_ati_alloc_pcigart_table(struct drm_device
> *dev,
> static void drm_ati_free_pcigart_table(struct drm_device *dev,
>struct drm_ati_pcigart_info *gart_info)
> {
> - drm_pci_free(dev, gart_info->table_handle);
> - gart_info->table_handle = NULL;
> + dma_free_coherent(&dev->pdev->dev,
> + gart_info->table_size,
> + gart_info->addr,
> + gart_info->bus_addr);
> }
>
> int drm_ati_pcigart_cleanup(struct drm_device *dev, struct
> drm_ati_pcigart_info *gart_info)
> @@ -89,8 +94,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct
> drm_ati_pcigart_info
> gart_info->bus_addr = 0;
> }
>
> - if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
> - gart_info->table_handle) {
> + if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
> drm_ati_free_pcigart_table(dev, gart_info);
> }
>
> @@ -103,7 +107,7 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct
> drm_ati_pcigart_info *ga
> struct drm_sg_mem *entry = dev->sg;
> void *address = NULL;
> unsigned long pages;
> - u32 *pci_gart = NULL, page_base, gart_idx;
> + u32 *page_base, gart_idx;
> dma_addr_t bus_address = 0;
> int i, j, ret = -ENOMEM;
> int max_ati_pages, max_real_pages;
> @@ -128,18 +132,14 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct
> drm_ati_pcigart_info *ga
> DRM_ERROR("cannot allocate PCI GART page!\n");
> goto done;
> }
> -
> - pci_gart = gart_info->table_handle->vaddr;
> - address = gart_info->table_handle->vaddr;
> - bus_address = gart_info->table_handle->busaddr;
> } else {
> - address = gart_info->addr;
> - bus_address = gart_info->bus_addr;
> DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
> (unsigned long long)bus_address,
> (unsigned long)address);
> }
>
> + address = gart_info->addr;
> + bus_address = gart_info->bus_addr;
>
> max_ati_pages = (gart_info->table_size / sizeof(u32));
> max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
> @@ -147,7 +147,7 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct
> drm_ati_pcigart_info *ga
> ? entry->pages : max_real_pages;
>
> if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
> - memset(pci_gart, 0, max_ati_pages * sizeof(u32));
> + memset(address, 0, max_ati_pages * sizeof(u32));
> } else {
> memset_io((void __iomem *)map->handle, 0, max_ati_pages *
> sizeof(u32));
> }
> @@ -185,7 +185,7 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct
> drm_ati_pcigart_info *ga
> }
> if (gart_info->gart_table_location ==
> DRM_ATI_GART_MAIN) {
> - pci_gart[gart_idx] = cpu_to_le32(val);
> + address[gart_idx] = cpu_to_le32(val);
> } else {
> offset = gart_idx * sizeof(u32);
> writel(val, (void __iomem *)map->handle +
> offset);
> diff --git a/drivers/gpu/drm/r128/ati_pcigart.h
> b/drivers/gpu/drm/r128/ati_pcigart.h
> index a728a1364e66..62
Re: [Intel-gfx] [PATCH 2/5] drm: Remove the dma_alloc_coherent wrapper for internal usage
On Sun, Feb 2, 2020 at 12:16 PM Chris Wilson wrote:
>
> Internally for "consistent" maps, we create a temporary struct
> drm_dma_handle in order to user our own dma_alloc_coherent wrapper then
> destroy the temporary wrap. Simplify our logic by removing the temporary
> wrapper!
>
> Signed-off-by: Chris Wilson
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_bufs.c | 20 +---
> drivers/gpu/drm/drm_pci.c | 15 ++-
> drivers/gpu/drm/drm_vm.c | 10 --
> include/drm/drm_legacy.h | 6 --
> 4 files changed, 15 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
> index 8ce9d73fab4f..19297e58b232 100644
> --- a/drivers/gpu/drm/drm_bufs.c
> +++ b/drivers/gpu/drm/drm_bufs.c
> @@ -149,7 +149,6 @@ static int drm_addmap_core(struct drm_device *dev,
> resource_size_t offset,
> {
> struct drm_local_map *map;
> struct drm_map_list *list;
> - drm_dma_handle_t *dmah;
> unsigned long user_token;
> int ret;
>
> @@ -324,14 +323,14 @@ static int drm_addmap_core(struct drm_device *dev,
> resource_size_t offset,
> * As we're limiting the address to 2^32-1 (or less),
> * casting it down to 32 bits is no problem, but we
> * need to point to a 64bit variable first. */
> - dmah = drm_pci_alloc(dev, map->size, map->size);
> - if (!dmah) {
> + map->handle = dma_alloc_coherent(&dev->pdev->dev,
> +map->size,
> +&map->offset,
> +GFP_KERNEL);
> + if (!map->handle) {
> kfree(map);
> return -ENOMEM;
> }
> - map->handle = dmah->vaddr;
> - map->offset = (unsigned long)dmah->busaddr;
> - kfree(dmah);
> break;
> default:
> kfree(map);
> @@ -513,7 +512,6 @@ int drm_legacy_getmap_ioctl(struct drm_device *dev, void
> *data,
> int drm_legacy_rmmap_locked(struct drm_device *dev, struct drm_local_map
> *map)
> {
> struct drm_map_list *r_list = NULL, *list_t;
> - drm_dma_handle_t dmah;
> int found = 0;
> struct drm_master *master;
>
> @@ -554,10 +552,10 @@ int drm_legacy_rmmap_locked(struct drm_device *dev,
> struct drm_local_map *map)
> case _DRM_SCATTER_GATHER:
> break;
> case _DRM_CONSISTENT:
> - dmah.vaddr = map->handle;
> - dmah.busaddr = map->offset;
> - dmah.size = map->size;
> - __drm_legacy_pci_free(dev, &dmah);
> + dma_free_coherent(&dev->pdev->dev,
> + map->size,
> + map->handle,
> + map->offset);
> break;
> }
> kfree(map);
> diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
> index d16dac4325f9..c6bb98729a26 100644
> --- a/drivers/gpu/drm/drm_pci.c
> +++ b/drivers/gpu/drm/drm_pci.c
> @@ -78,18 +78,6 @@ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev,
> size_t size, size_t ali
>
> EXPORT_SYMBOL(drm_pci_alloc);
>
> -/*
> - * Free a PCI consistent memory block without freeing its descriptor.
> - *
> - * This function is for internal use in the Linux-specific DRM core code.
> - */
> -void __drm_legacy_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
> -{
> - if (dmah->vaddr)
> - dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr,
> - dmah->busaddr);
> -}
> -
> /**
> * drm_pci_free - Free a PCI consistent memory block
> * @dev: DRM device
> @@ -100,7 +88,8 @@ void __drm_legacy_pci_free(struct drm_device * dev,
> drm_dma_handle_t * dmah)
> */
> void drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
> {
> - __drm_legacy_pci_free(dev, dmah);
> + dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr,
> + dmah->busaddr);
> kfree(dmah);
> }
>
> diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
> index 52e87e4869a5..64619fe90046 100644
> --- a/drivers/gpu/drm/drm_vm.c
> +++ b/drivers/gpu/drm/drm_vm.c
> @@ -269,8 +269,6 @@ static void drm_vm_shm_close(struct vm_area_struct *vma)
> }
>
> if (!found_maps) {
> - drm_dma_handle_t dmah;
> -
> switch (map->type) {
> case _DRM_REGISTERS:
> case _DRM_FRAME_BUFFER:
> @@ -284,10 +282,10 @@ static void drm_vm_shm_close(struct vm_area_struct *vma)
> case _DRM_SCATTER_GATHER:
> break;
> case _DRM_CONSISTENT:
> -
Re: [Intel-gfx] [PATCH 1/5] drm: Remove PageReserved manipulation from drm_pci_alloc
On Sun, Feb 2, 2020 at 12:16 PM Chris Wilson wrote:
>
> drm_pci_alloc/drm_pci_free are very thin wrappers around the core dma
> facilities, and we have no special reason within the drm layer to behave
> differently. In particular, since
>
> commit de09d31dd38a50fdce106c15abd68432eebbd014
> Author: Kirill A. Shutemov
> Date: Fri Jan 15 16:51:42 2016 -0800
>
> page-flags: define PG_reserved behavior on compound pages
>
> As far as I can see there's no users of PG_reserved on compound pages.
> Let's use PF_NO_COMPOUND here.
>
> it has been illegal to combine GFP_COMP with SetPageReserved, so lets
> stop doing both and leave the dma layer to its own devices.
>
> Reported-by: Taketo Kabe
Needs an email address.
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/1027
Should be Bug: rather than Closes:
> Fixes: de09d31dd38a ("page-flags: define PG_reserved behavior on compound
> pages")
> Signed-off-by: Chris Wilson
> Cc: # v4.5+
With those fixed:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_pci.c | 23 ++-
> 1 file changed, 2 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
> index f2e43d341980..d16dac4325f9 100644
> --- a/drivers/gpu/drm/drm_pci.c
> +++ b/drivers/gpu/drm/drm_pci.c
> @@ -51,8 +51,6 @@
> drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t
> align)
> {
> drm_dma_handle_t *dmah;
> - unsigned long addr;
> - size_t sz;
>
> /* pci_alloc_consistent only guarantees alignment to the smallest
> * PAGE_SIZE order which is greater than or equal to the requested
> size.
> @@ -68,20 +66,13 @@ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev,
> size_t size, size_t ali
> dmah->size = size;
> dmah->vaddr = dma_alloc_coherent(&dev->pdev->dev, size,
> &dmah->busaddr,
> -GFP_KERNEL | __GFP_COMP);
> +GFP_KERNEL);
>
> if (dmah->vaddr == NULL) {
> kfree(dmah);
> return NULL;
> }
>
> - /* XXX - Is virt_to_page() legal for consistent mem? */
> - /* Reserve */
> - for (addr = (unsigned long)dmah->vaddr, sz = size;
> -sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
> - SetPageReserved(virt_to_page((void *)addr));
> - }
> -
> return dmah;
> }
>
> @@ -94,19 +85,9 @@ EXPORT_SYMBOL(drm_pci_alloc);
> */
> void __drm_legacy_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
> {
> - unsigned long addr;
> - size_t sz;
> -
> - if (dmah->vaddr) {
> - /* XXX - Is virt_to_page() legal for consistent mem? */
> - /* Unreserve */
> - for (addr = (unsigned long)dmah->vaddr, sz = dmah->size;
> -sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
> - ClearPageReserved(virt_to_page((void *)addr));
> - }
> + if (dmah->vaddr)
> dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr,
> dmah->busaddr);
> - }
> }
>
> /**
> --
> 2.25.0
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_basic: Drop per-engine testing of *execbuf
The gtt/readonly tests are nothing to do with execution and engines;
they are strictly checking the copy-from-user of the ioctl arguments.
Drop the silly per-engine tests.
Signed-off-by: Chris Wilson
Cc: Antonio Argenziano
---
tests/i915/gem_exec_basic.c | 109 +--
tests/i915/gem_exec_params.c | 61
2 files changed, 76 insertions(+), 94 deletions(-)
diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index 70dce34b5..0d05819ce 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -36,84 +36,6 @@ static uint32_t batch_create(int fd)
return handle;
}
-static void batch_fini(int fd, uint32_t handle)
-{
- gem_sync(fd, handle); /* catch any GPU hang */
- gem_close(fd, handle);
-}
-
-static void noop(int fd, uint64_t flags)
-{
- struct drm_i915_gem_execbuffer2 execbuf;
- struct drm_i915_gem_exec_object2 exec;
-
- gem_require_ring(fd, flags);
-
- memset(&exec, 0, sizeof(exec));
-
- exec.handle = batch_create(fd);
-
- memset(&execbuf, 0, sizeof(execbuf));
- execbuf.buffers_ptr = to_user_pointer(&exec);
- execbuf.buffer_count = 1;
- execbuf.flags = flags;
- gem_execbuf(fd, &execbuf);
-
- batch_fini(fd, exec.handle);
-}
-
-static void readonly(int fd, uint64_t flags)
-{
- struct drm_i915_gem_execbuffer2 *execbuf;
- struct drm_i915_gem_exec_object2 exec;
-
- gem_require_ring(fd, flags);
-
- memset(&exec, 0, sizeof(exec));
- exec.handle = batch_create(fd);
-
- execbuf = mmap(NULL, 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
- igt_assert(execbuf != NULL);
-
- execbuf->buffers_ptr = to_user_pointer(&exec);
- execbuf->buffer_count = 1;
- execbuf->flags = flags;
- igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
-
- gem_execbuf(fd, execbuf);
-
- munmap(execbuf, 4096);
-
- batch_fini(fd, exec.handle);
-}
-
-static void gtt(int fd, uint64_t flags)
-{
- struct drm_i915_gem_execbuffer2 *execbuf;
- struct drm_i915_gem_exec_object2 *exec;
- uint32_t handle;
-
- gem_require_ring(fd, flags);
-
- handle = gem_create(fd, 4096);
-
- gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
- execbuf = gem_mmap__gtt(fd, handle, 4096, PROT_WRITE);
- exec = (struct drm_i915_gem_exec_object2 *)(execbuf + 1);
- gem_close(fd, handle);
-
- exec->handle = batch_create(fd);
-
- execbuf->buffers_ptr = to_user_pointer(exec);
- execbuf->buffer_count = 1;
- execbuf->flags = flags;
-
- gem_execbuf(fd, execbuf);
-
- batch_fini(fd, exec->handle);
- munmap(execbuf, 4096);
-}
-
igt_main
{
const struct intel_execution_engine2 *e;
@@ -121,30 +43,29 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
- igt_require_gem(fd);
-
+ /* igt_require_gem(fd); // test is mandatory */
igt_fork_hang_detector(fd);
}
igt_subtest_with_dynamic("basic") {
- __for_each_physical_engine(fd, e) {
- igt_dynamic_f("%s", e->name)
- noop(fd, e->flags);
- }
- }
+ struct drm_i915_gem_exec_object2 exec = {
+ .handle = batch_create(fd),
+ };
- igt_subtest_with_dynamic("readonly") {
__for_each_physical_engine(fd, e) {
- igt_dynamic_f("%s", e->name)
- readonly(fd, e->flags);
+ igt_dynamic_f("%s", e->name) {
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&exec),
+ .buffer_count = 1,
+ .flags = e->flags,
+ };
+
+ gem_execbuf(fd, &execbuf);
+ }
}
- }
- igt_subtest_with_dynamic("gtt") {
- __for_each_physical_engine(fd, e) {
- igt_dynamic_f("%s", e->name)
- gtt(fd, e->flags);
- }
+ gem_sync(fd, exec.handle); /* catch any GPU hang */
+ gem_close(fd, exec.handle);
}
igt_fixture {
diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index 9c3525698..094fa904c 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -206,6 +206,61 @@ static int has_secure_batches(const int fd)
return v > 0;
}
+static uint32_t batch_create(int fd)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, 4096);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ ret
Re: [Intel-gfx] [PATCH V5] drm: Add support for DP 1.4 Compliance edid corruption test
Hi Jerry,
First of all, thanks for your patch. You can see some comments inline,
just simple things.
On 01/31, Jerry (Fangzhi) Zuo wrote:
> Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
> real CRC value of the last edid data block, and write it back.
> Current edid CRC calculates routine adds the last CRC byte,
> and check if non-zero.
>
> This behavior is not accurate; actually, we need to return
> the actual CRC value when corruption is detected.
> This commit changes this issue by returning the calculated CRC,
> and initiate the required sequence.
>
> Change since v5
> - Obtain real CRC value before dumping bad edid
>
> Change since v4
> - Fix for CI.CHECKPATCH
>
> Change since v3
> - Fix a minor typo.
>
> Change since v2
> - Rewrite checksum computation routine to avoid duplicated code.
> - Rename to avoid confusion.
>
> Change since v1
> - Have separate routine for returning real CRC.
>
> Signed-off-by: Jerry (Fangzhi) Zuo
> ---
> drivers/gpu/drm/drm_dp_helper.c | 35 +
> drivers/gpu/drm/drm_edid.c | 23 ++
> include/drm/drm_connector.h | 6 ++
> include/drm/drm_dp_helper.h | 3 +++
> 4 files changed, 63 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index f629fc5494a4..18b285fa1a42 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -351,6 +351,41 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
> }
> EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
>
> +/**
> + * drm_dp_send_real_edid_checksum() - send back real edid checksum value
> + * @aux: DisplayPort AUX channel
> + * @real_edid_checksum: real edid checksum for the last block
> + *
> + * Returns true on success
I think this should be:
Returns:
True on success...
> + */
> +bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
> +u8 real_edid_checksum)
Use tabs intead of space
> +{
> + u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
> +
> + drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, &auto_test_req, 1);
drm_dp_dpcd_read() documentation says:
[..]
Returns the number of bytes transferred on success, or a negative error
code on failure. [..][1]
How about catching the return value of drm_dp_dpcd_read() and handle it?
1. drivers/gpu/drm/drm_dp_helper.c
> + auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
> +
> + drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1);
Same
> + link_edid_read &= DP_TEST_LINK_EDID_READ;
> +
> + if (!auto_test_req || !link_edid_read) {
> + DRM_DEBUG_KMS("Source DUT does not support TEST_EDID_READ\n");
I'm not 100% sure, but I think that drm_dbg_kms() represents the new
approach for handling debug messages. Could you confirm that? If so,
could you update it?
> + return false;
> + }
> +
> + drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, &auto_test_req, 1);
> +
> + /* send back checksum for the last edid extension block data */
> + drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, &real_edid_checksum, 1);
Again, how about handling the return from drm_dp_dpcd_write?
> +
> + test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
> + drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1);
> +
> + return true;
> +}
> +EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
> +
> /**
> * drm_dp_downstream_max_clock() - extract branch device max
> * pixel rate for legacy VGA
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 99769d6c9f84..f064e75fb4c5 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -1590,11 +1590,22 @@ static int validate_displayid(u8 *displayid, int
> length, int idx);
> static int drm_edid_block_checksum(const u8 *raw_edid)
> {
> int i;
> - u8 csum = 0;
> - for (i = 0; i < EDID_LENGTH; i++)
> + u8 csum = 0, crc = 0;
> +
> + for (i = 0; i < EDID_LENGTH - 1; i++)
> csum += raw_edid[i];
>
> - return csum;
> + crc = 0x100 - csum;
> +
> + return crc;
> +}
> +
> +static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8
> real_checksum)
> +{
> + if (raw_edid[EDID_LENGTH - 1] != real_checksum)
> + return true;
> + else
> + return false;
> }
>
> static bool drm_edid_is_zero(const u8 *in_edid, int length)
> @@ -1652,7 +1663,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool
> print_bad_edid,
> }
>
> csum = drm_edid_block_checksum(raw_edid);
> - if (csum) {
> + if (drm_edid_block_checksum_diff(raw_edid, csum)) {
> if (edid_corrupt)
> *edid_corrupt = true;
>
> @@ -1793,6 +1804,10 @@ static void connector_bad_edid(struct drm_connector
> *connector,
> u8 *edid, int num_blocks)
> {
>
Re: [Intel-gfx] [PATCH v4 05/22] drm/amdgpu: Convert to CRTC VBLANK callbacks
On Thu, Jan 23, 2020 at 9:00 AM Thomas Zimmermann wrote:
>
> VBLANK callbacks in struct drm_driver are deprecated in favor of
> their equivalents in struct drm_crtc_funcs. Convert amdgpu over.
>
> v2:
> * don't wrap existing functions; change signature instead
>
> Signed-off-by: Thomas Zimmermann
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 21 +++
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 4
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 4
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 4
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +
> 10 files changed, 43 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index f42e8d467c12..2319fdfc42e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1191,9 +1191,9 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
> int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
> int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
> int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
> -u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
> -int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
> -void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
> +u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
> +int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
> +void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
> long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
> unsigned long arg);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index a1e769d4417d..ad9c9546a64f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -99,7 +99,7 @@ static void amdgpu_display_flip_work_func(struct
> work_struct *__work)
> & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
> (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
> (int)(work->target_vblank -
> - amdgpu_get_vblank_counter_kms(adev->ddev,
> amdgpu_crtc->crtc_id)) > 0) {
> + amdgpu_get_vblank_counter_kms(crtc)) > 0) {
> schedule_delayed_work(&work->flip_work,
> usecs_to_jiffies(1000));
> return;
> }
> @@ -219,7 +219,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc
> *crtc,
> if (!adev->enable_virtual_display)
> work->base = amdgpu_bo_gpu_offset(new_abo);
> work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
> - amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
> + amdgpu_get_vblank_counter_kms(crtc);
>
> /* we borrow the event spin lock for protecting flip_wrok */
> spin_lock_irqsave(&crtc->dev->event_lock, flags);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 955b78f1bba4..bc2fa428013f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1388,10 +1388,6 @@ static struct drm_driver kms_driver = {
> .postclose = amdgpu_driver_postclose_kms,
> .lastclose = amdgpu_driver_lastclose_kms,
> .unload = amdgpu_driver_unload_kms,
> - .get_vblank_counter = amdgpu_get_vblank_counter_kms,
> - .enable_vblank = amdgpu_enable_vblank_kms,
> - .disable_vblank = amdgpu_disable_vblank_kms,
> - .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
> .irq_handler = amdgpu_irq_handler,
> .ioctls = amdgpu_ioctls_kms,
> .gem_free_object_unlocked = amdgpu_gem_object_free,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 60591dbc2097..98c196de27a4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -1110,14 +1110,15 @@ void amdgpu_driver_postclose_kms(struct drm_device
> *dev,
> /**
> * amdgpu_get_vblank_counter_kms - get frame count
> *
> - * @dev: drm dev pointer
> - * @pipe: crtc to get the frame count from
> + * @crtc: crtc to get the frame count from
> *
> * Gets the frame count on the requested crtc (all asics).
> * Returns frame count on success, -EINVAL on failure.
> */
> -u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
> +u32 amdgpu_get_vblank_counter_kms(struct drm_c
Re: [Intel-gfx] [PATCH v4 04/22] drm/amdgpu: Convert to struct drm_crtc_helper_funcs.get_scanout_position()
On Thu, Jan 23, 2020 at 9:00 AM Thomas Zimmermann wrote:
>
> The callback struct drm_driver.get_scanout_position() is deprecated in
> favor of struct drm_crtc_helper_funcs.get_scanout_position(). Convert
> amdgpu over.
>
> Signed-off-by: Thomas Zimmermann
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 12
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 5 +
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 1 +
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
> 9 files changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 4e699071d144..a1e769d4417d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -914,3 +914,15 @@ int amdgpu_display_crtc_idx_to_irq_type(struct
> amdgpu_device *adev, int crtc)
> return AMDGPU_CRTC_IRQ_NONE;
> }
> }
> +
> +bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
> + bool in_vblank_irq, int *vpos,
> + int *hpos, ktime_t *stime, ktime_t *etime,
> + const struct drm_display_mode *mode)
> +{
> + struct drm_device *dev = crtc->dev;
> + unsigned int pipe = crtc->index;
> +
> + return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
> + stime, etime, mode);
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index a9c4edca70c9..955b78f1bba4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1377,16 +1377,6 @@ int amdgpu_file_to_fpriv(struct file *filp, struct
> amdgpu_fpriv **fpriv)
> return 0;
> }
>
> -static bool
> -amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
> -bool in_vblank_irq, int *vpos, int *hpos,
> -ktime_t *stime, ktime_t *etime,
> -const struct drm_display_mode *mode)
> -{
> - return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
> - stime, etime, mode);
> -}
> -
> static struct drm_driver kms_driver = {
> .driver_features =
> DRIVER_USE_AGP | DRIVER_ATOMIC |
> @@ -1402,7 +1392,6 @@ static struct drm_driver kms_driver = {
> .enable_vblank = amdgpu_enable_vblank_kms,
> .disable_vblank = amdgpu_disable_vblank_kms,
> .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
> - .get_scanout_position = amdgpu_get_crtc_scanout_position,
> .irq_handler = amdgpu_irq_handler,
> .ioctls = amdgpu_ioctls_kms,
> .gem_free_object_unlocked = amdgpu_gem_object_free,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> index eb9975f4decb..37ba07e2feb5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> @@ -612,6 +612,11 @@ void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
> struct drm_display_mode *adjusted_mode);
> int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int
> crtc);
>
> +bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
> + bool in_vblank_irq, int *vpos,
> + int *hpos, ktime_t *stime, ktime_t *etime,
> + const struct drm_display_mode *mode);
> +
> /* fbdev layer */
> int amdgpu_fbdev_init(struct amdgpu_device *adev);
> void amdgpu_fbdev_fini(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 40d2ac723dd6..bdc1e0f036d4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -2685,6 +2685,7 @@ static const struct drm_crtc_helper_funcs
> dce_v10_0_crtc_helper_funcs = {
> .prepare = dce_v10_0_crtc_prepare,
> .commit = dce_v10_0_crtc_commit,
> .disable = dce_v10_0_crtc_disable,
> + .get_scanout_position = amdgpu_crtc_get_scanout_position,
> };
>
> static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 898ef72d423c..0319da5f7bf9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -2793
Re: [Intel-gfx] [PATCH v4 10/22] drm/radeon: Convert to struct drm_crtc_helper_funcs.get_scanout_position()
On Thu, Jan 23, 2020 at 9:00 AM Thomas Zimmermann wrote:
>
> The callback struct drm_driver.get_scanout_position() is deprecated in
> favor of struct drm_crtc_helper_funcs.get_scanout_position(). Convert
> radeon over.
>
> v4:
> * 80-character line fixes
>
> Signed-off-by: Thomas Zimmermann
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/atombios_crtc.c | 1 +
> drivers/gpu/drm/radeon/radeon_display.c | 13 +
> drivers/gpu/drm/radeon/radeon_drv.c | 11 ---
> drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 3 ++-
> drivers/gpu/drm/radeon/radeon_mode.h| 6 ++
> 5 files changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
> b/drivers/gpu/drm/radeon/atombios_crtc.c
> index be583695427a..91811757104c 100644
> --- a/drivers/gpu/drm/radeon/atombios_crtc.c
> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
> @@ -2231,6 +2231,7 @@ static const struct drm_crtc_helper_funcs
> atombios_helper_funcs = {
> .prepare = atombios_crtc_prepare,
> .commit = atombios_crtc_commit,
> .disable = atombios_crtc_disable,
> + .get_scanout_position = radeon_get_crtc_scanout_position,
> };
>
> void radeon_atombios_init_crtc(struct drm_device *dev,
> diff --git a/drivers/gpu/drm/radeon/radeon_display.c
> b/drivers/gpu/drm/radeon/radeon_display.c
> index 856526cb2caf..2f641f3b39e7 100644
> --- a/drivers/gpu/drm/radeon/radeon_display.c
> +++ b/drivers/gpu/drm/radeon/radeon_display.c
> @@ -1978,3 +1978,16 @@ int radeon_get_crtc_scanoutpos(struct drm_device *dev,
> unsigned int pipe,
>
> return ret;
> }
> +
> +bool
> +radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
> +bool in_vblank_irq, int *vpos, int *hpos,
> +ktime_t *stime, ktime_t *etime,
> +const struct drm_display_mode *mode)
> +{
> + struct drm_device *dev = crtc->dev;
> + unsigned int pipe = crtc->index;
> +
> + return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
> + stime, etime, mode);
> +}
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
> b/drivers/gpu/drm/radeon/radeon_drv.c
> index fd74e2611185..1f597f166bff 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -563,16 +563,6 @@ static const struct file_operations
> radeon_driver_kms_fops = {
> #endif
> };
>
> -static bool
> -radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
> -bool in_vblank_irq, int *vpos, int *hpos,
> -ktime_t *stime, ktime_t *etime,
> -const struct drm_display_mode *mode)
> -{
> - return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
> - stime, etime, mode);
> -}
> -
> static struct drm_driver kms_driver = {
> .driver_features =
> DRIVER_USE_AGP | DRIVER_GEM | DRIVER_RENDER,
> @@ -585,7 +575,6 @@ static struct drm_driver kms_driver = {
> .enable_vblank = radeon_enable_vblank_kms,
> .disable_vblank = radeon_disable_vblank_kms,
> .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
> - .get_scanout_position = radeon_get_crtc_scanout_position,
> .irq_preinstall = radeon_driver_irq_preinstall_kms,
> .irq_postinstall = radeon_driver_irq_postinstall_kms,
> .irq_uninstall = radeon_driver_irq_uninstall_kms,
> diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
> b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
> index a1985a552794..8817fd033cd0 100644
> --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
> +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
> @@ -,7 +,8 @@ static const struct drm_crtc_helper_funcs
> legacy_helper_funcs = {
> .mode_set_base_atomic = radeon_crtc_set_base_atomic,
> .prepare = radeon_crtc_prepare,
> .commit = radeon_crtc_commit,
> - .disable = radeon_crtc_disable
> + .disable = radeon_crtc_disable,
> + .get_scanout_position = radeon_get_crtc_scanout_position,
> };
>
>
> diff --git a/drivers/gpu/drm/radeon/radeon_mode.h
> b/drivers/gpu/drm/radeon/radeon_mode.h
> index fd470d6bf3f4..3a61530c1398 100644
> --- a/drivers/gpu/drm/radeon/radeon_mode.h
> +++ b/drivers/gpu/drm/radeon/radeon_mode.h
> @@ -881,6 +881,12 @@ extern int radeon_get_crtc_scanoutpos(struct drm_device
> *dev, unsigned int pipe,
> ktime_t *stime, ktime_t *etime,
> const struct drm_display_mode *mode);
>
> +extern bool
> +radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
> +int *vpos, int *hpos,
> +ktime_t *stime, ktime_t *etime,
> +const struct
Re: [Intel-gfx] [PATCH 8/8] drm/edid: Dump bogus 18 byte descriptors
> -Original Message-
> From: Intel-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, January 28, 2020 4:09 AM
> To: Ville Syrjala
> Cc: Intel Graphics Development ; Maling list
> - DRI
> developers
> Subject: Re: [Intel-gfx] [PATCH 8/8] drm/edid: Dump bogus 18 byte descriptors
>
> On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > I'm curious if there are any bogus 18 byte descriptors around.
> > Let's dump them out if we encounter them.
> >
> > Not sure we'd actually want this, but at least I get to see if our CI
> > has anything that hits this :)
> >
> > Signed-off-by: Ville Syrjälä
>
> Acked-by: Alex Deucher
Looks good to me as well.
Reviewed-by: Uma Shankar
> > ---
> > drivers/gpu/drm/drm_edid.c | 22 +++---
> > 1 file changed, 19 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 8e76efe1654d..4d8303e56536 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -2202,6 +2202,12 @@ static bool is_display_descriptor(const u8 d[18], u8
> tag)
> > d[2] == 0x00 && d[3] == tag; }
> >
> > +static bool is_any_display_descriptor(const u8 d[18]) {
> > + return d[0] == 0x00 && d[1] == 0x00 &&
> > + d[2] == 0x00;
> > +}
> > +
> > static bool is_detailed_timing_descriptor(const u8 d[18]) {
> > return d[0] != 0x00 || d[1] != 0x00; @@ -2209,6 +2215,15 @@
> > static bool is_detailed_timing_descriptor(const u8 d[18])
> >
> > typedef void detailed_cb(const struct detailed_timing *timing, void
> > *closure);
> >
> > +static void do_detailed_block(const u8 d[18], detailed_cb *cb, void
> > +*closure) {
> > + if (!is_detailed_timing_descriptor(d) &&
> > + !is_any_display_descriptor(d))
> > + DRM_WARN("Unrecognized 18 byte descriptor: %*ph\n",
> > +18, d);
> > +
> > + cb((const struct detailed_timing *)d, closure); }
> > +
> > static void
> > cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void
> > *closure) { @@ -2221,7 +2236,7 @@ cea_for_each_detailed_block(const
> > u8 *ext, detailed_cb *cb, void *closure)
> >
> > n = (127 - d) / 18;
> > for (i = 0; i < n; i++)
> > - cb((const struct detailed_timing *)(det_base + 18 * i),
> > closure);
> > + do_detailed_block(det_base + 18 * i, cb, closure);
> > }
> >
> > static void
> > @@ -2234,7 +2249,7 @@ vtb_for_each_detailed_block(const u8 *ext, detailed_cb
> *cb, void *closure)
> > return; /* unknown version */
> >
> > for (i = 0; i < n; i++)
> > - cb((const struct detailed_timing *)(det_base + 18 * i),
> > closure);
> > + do_detailed_block(det_base + 18 * i, cb, closure);
> > }
> >
> > static void
> > @@ -2247,7 +2262,8 @@ drm_for_each_detailed_block(const u8 *raw_edid,
> detailed_cb *cb, void *closure)
> > return;
> >
> > for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
> > - cb(&(edid->detailed_timings[i]), closure);
> > + do_detailed_block((const u8 *)&edid->detailed_timings[i],
> > + cb, closure);
> >
> > for (i = 1; i <= raw_edid[0x7e]; i++) {
> > const u8 *ext = raw_edid + (i * EDID_LENGTH);
> > --
> > 2.24.1
> >
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/8] drm/edid: Constify lots of things
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjälä
> Sent: Tuesday, January 28, 2020 5:19 PM
> To: Alex Deucher
> Cc: Intel Graphics Development ; Maling list
> - DRI
> developers
> Subject: Re: [Intel-gfx] [PATCH 7/8] drm/edid: Constify lots of things
>
> On Mon, Jan 27, 2020 at 05:38:15PM -0500, Alex Deucher wrote:
> > On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
> > wrote:
> > >
> > > From: Ville Syrjälä
> > >
> > > Let's try to make a lot more stuff const in the edid parser.
> > >
> > > The "downside" is that we can no longer mangle the EDID in the
> > > middle of the parsing to apply quirks (drm_mode_detailed()).
> > > I don't really think mangling the blob itself is such a great idea
> > > anyway so I won't miss that part. But if we do want it back I guess
> > > we should do the mangling in one explicit place before we otherwise
> > > parse the EDID.
> > >
> > > Signed-off-by: Ville Syrjälä
> >
> > I generally agree, but are there any userspace expectations that they
> > will be getting a corrected EDID in some cases?
>
> Not sure. I think the the only thing we're fixing up is some DTDs so at least
> there's a
> better way for userspace to get the fixed information (getconnector ioctl). I
> guess
> Xorg is still parsing the EDID though, but it should have more or less the
> same quirks
> in its parser.
Theoretically, there may be a possibility of userspace getting out of sync in
case EDID exposed
to user is different to the quirked version getting used in kernel. I feel what
you said in commit
message looks good, where we can do the quirks at one place and share the same
to userspace.
Later just use that to proceed with parsing with constantifed edid in kernel.
Regards,
Uma Shankar
> >
> > Alex
> >
> > > ---
> > > drivers/gpu/drm/drm_connector.c | 4 +-
> > > drivers/gpu/drm/drm_edid.c | 303 ++--
> > > include/drm/drm_connector.h | 4 +-
> > > 3 files changed, 176 insertions(+), 135 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_connector.c
> > > b/drivers/gpu/drm/drm_connector.c index f632ca05960e..92a5cd6ff6b1
> > > 100644
> > > --- a/drivers/gpu/drm/drm_connector.c
> > > +++ b/drivers/gpu/drm/drm_connector.c
> > > @@ -2377,7 +2377,7 @@ EXPORT_SYMBOL(drm_mode_put_tile_group);
> > > * tile group or NULL if not found.
> > > */
> > > struct drm_tile_group *drm_mode_get_tile_group(struct drm_device *dev,
> > > - char topology[8])
> > > + const u8 topology[8])
> > > {
> > > struct drm_tile_group *tg;
> > > int id;
> > > @@ -2407,7 +2407,7 @@ EXPORT_SYMBOL(drm_mode_get_tile_group);
> > > * new tile group or NULL.
> > > */
> > > struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev,
> > > - char topology[8])
> > > + const u8
> > > + topology[8])
> > > {
> > > struct drm_tile_group *tg;
> > > int ret;
> > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > index fd9b724067a7..8e76efe1654d 100644
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -88,7 +88,7 @@
> > >
> > > struct detailed_mode_closure {
> > > struct drm_connector *connector;
> > > - struct edid *edid;
> > > + const struct edid *edid;
> > > bool preferred;
> > > u32 quirks;
> > > int modes;
> > > @@ -1584,8 +1584,8 @@ MODULE_PARM_DESC(edid_fixup,
> > > "Minimum number of valid EDID header bytes (0-8,
> > > default 6)");
> > >
> > > static void drm_get_displayid(struct drm_connector *connector,
> > > - struct edid *edid);
> > > -static int validate_displayid(u8 *displayid, int length, int idx);
> > > + const struct edid *edid); static int
> > > +validate_displayid(const u8 *displayid, int length, int idx);
> > >
> > > static int drm_edid_block_checksum(const u8 *raw_edid) { @@
> > > -2207,41 +2207,41 @@ static bool is_detailed_timing_descriptor(const u8
> > > d[18])
> > > return d[0] != 0x00 || d[1] != 0x00; }
> > >
> > > -typedef void detailed_cb(struct detailed_timing *timing, void
> > > *closure);
> > > +typedef void detailed_cb(const struct detailed_timing *timing, void
> > > +*closure);
> > >
> > > static void
> > > -cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void
> > > *closure)
> > > +cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void
> > > +*closure)
> > > {
> > > int i, n;
> > > u8 d = ext[0x02];
> > > - u8 *det_base = ext + d;
> > > + const u8 *det_base = ext + d;
> > >
> > > if (d < 4 || d > 127)
> > > return;
> > >
> > > n = (127 - d) / 18;
> > > for (i = 0; i < n; i++)
> > > - cb((struct de
[Intel-gfx] [PATCH] drm/i915/gt: Fix rc6 on Ivybridge
The current rc6 threshold is larger than the evaluation interval on Ivybridge; it never enters rc6. Remove the special casing so it behaves like the other gen6/gen7, and we see rc6 residencies before we manually park the system. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1114 Testcase: igt/i915_pm_rc6_residency/rc6-idle #ivb Signed-off-by: Chris Wilson Cc: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_rc6.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 01a99fdbb3c4..682f598f7042 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -226,10 +226,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6) set(uncore, GEN6_RC_SLEEP, 0); set(uncore, GEN6_RC1e_THRESHOLD, 1000); - if (IS_IVYBRIDGE(i915)) - set(uncore, GEN6_RC6_THRESHOLD, 125000); - else - set(uncore, GEN6_RC6_THRESHOLD, 5); + set(uncore, GEN6_RC6_THRESHOLD, 5); set(uncore, GEN6_RC6p_THRESHOLD, 15); set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */ -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/8] drm/edid: Add a FIXME about DispID CEA data block revision
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Saturday, January 25, 2020 1:32 AM
> To: dri-de...@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org; Andres Rodriguez
> Subject: [Intel-gfx] [PATCH 6/8] drm/edid: Add a FIXME about DispID CEA data
> block
> revision
>
> From: Ville Syrjälä
>
> I don't understand what the DispID CEA data block revision means. The spec
> doesn't
> say. I guess some DispID must have a value of >= 3 in there or else we
> generally
> wouldn't even parse the CEA data blocks. Or does all this code actually not do
> anything?
This signifies the CTA extension revision (byte 1 of the block). As per the
spec, seems like
Version 1 is legacy and 2 is deprecated. So version >=3 is checked here.
Refer section 7.3 of CTA-861-G
> Cc: Andres Rodriguez
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 0369a54e3d32..fd9b724067a7 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -3977,6 +3977,13 @@ cea_db_tag(const u8 *db) static int
> cea_revision(const
> u8 *cea) {
> + /*
> + * FIXME is this correct for the DispID variant?
> + * The DispID spec doesn't really specify whether
> + * this is the revision of the CEA extension or
> + * the DispID CEA data block. And the only value
> + * given as an example is 0.
> + */
> return cea[1];
> }
>
> --
> 2.24.1
>
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Re: [Intel-gfx] [PATCH 5/8] drm/edid: Document why we don't bounds check the DispID CEA block start/end
> -Original Message-
> From: dri-devel On Behalf Of Ville
> Syrjälä
> Sent: Tuesday, January 28, 2020 5:14 PM
> To: Alex Deucher
> Cc: Intel Graphics Development ; Andres
> Rodriguez
> ; Maling list - DRI developers de...@lists.freedesktop.org>
> Subject: Re: [PATCH 5/8] drm/edid: Document why we don't bounds check the
> DispID CEA block start/end
>
> On Mon, Jan 27, 2020 at 05:30:42PM -0500, Alex Deucher wrote:
> > On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
> > wrote:
> > >
> > > From: Ville Syrjälä
> > >
> > > After much head scratching I managed to convince myself that
> > > for_each_displayid_db() has already done the bounds checks for the
> > > DispID CEA data block. Which is why we don't need to repeat them in
> > > cea_db_offsets(). To avoid having to go through that pain again in
> > > the future add a comment which explains this fact.
> > >
> > > Cc: Andres Rodriguez
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/drm_edid.c | 4
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > index 3df5744026b0..0369a54e3d32 100644
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -4001,6 +4001,10 @@ cea_db_offsets(const u8 *cea, int *start, int *end)
> > > * no non-DTD data.
> > > */
> > > if (cea[0] == DATA_BLOCK_CTA) {
> > > + /*
> > > +* for_each_displayid_db() has already verified
> > > +* that these stay within expected bounds.
> > > +*/
> >
> > I think the preferred format is to have the start of the comment be on
> > the first line after the /* with that fixed:
>
> Nope.
Yes the style is correct here, comment is apt as well.
Reviewed-by: Uma Shankar
> > Acked-by: Alex Deucher
> >
> > > *start = 3;
> > > *end = *start + cea[2];
> > > } else if (cea[0] == CEA_EXT) {
> > > --
> > > 2.24.1
> > >
> > > ___
> > > dri-devel mailing list
> > > dri-de...@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH 4/8] drm/i915: Clear out spurious whitespace
> -Original Message-
> From: Intel-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, January 28, 2020 3:58 AM
> To: Ville Syrjala
> Cc: Intel Graphics Development ; Maling list
> - DRI
> developers
> Subject: Re: [Intel-gfx] [PATCH 4/8] drm/i915: Clear out spurious whitespace
>
> Title should be s/i915/edid/ , with that fixed:
> Reviewed-by: Alex Deucher
Yeah with the title fixed, this is
Reviewed-by: Uma Shankar
>
> On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > Nuke some whitespace that shouldn't be there.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/drm_edid.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index d6bce58b27ac..3df5744026b0 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -2842,7 +2842,7 @@ do_inferred_modes(struct detailed_timing *timing, void
> *c)
> > closure->modes += drm_dmt_modes_for_range(closure->connector,
> > closure->edid,
> > timing);
> > -
> > +
> > if (!version_greater(closure->edid, 1, 1))
> > return; /* GTF not defined yet */
> >
> > @@ -3084,7 +3084,7 @@ do_cvt_mode(struct detailed_timing *timing, void
> > *c)
> >
> > static int
> > add_cvt_modes(struct drm_connector *connector, struct edid *edid) -{
> > +{
> > struct detailed_mode_closure closure = {
> > .connector = connector,
> > .edid = edid,
> > @@ -4342,7 +4342,7 @@ void drm_edid_get_monitor_name(struct edid
> > *edid, char *name, int bufsize) {
> > int name_length;
> > char buf[13];
> > -
> > +
> > if (bufsize <= 0)
> > return;
> >
> > --
> > 2.24.1
> >
> > ___
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> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [Intel-gfx] [PATCH 3/8] drm/edid: Introduce is_detailed_timing_descritor()
> -Original Message-
> From: Intel-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, January 28, 2020 4:06 AM
> To: Ville Syrjala
> Cc: Allen Chen ; Intel Graphics Development g...@lists.freedesktop.org>; Maling list - DRI developers de...@lists.freedesktop.org>
> Subject: Re: [Intel-gfx] [PATCH 3/8] drm/edid: Introduce
> is_detailed_timing_descritor()
>
> On Fri, Jan 24, 2020 at 3:02 PM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > Let's introduce is_detailed_timing_descritor() as the opposite
> > counterpart of is_display_descriptor().
> >
> > Cc: Allen Chen
> > Signed-off-by: Ville Syrjälä
>
> Acked-by: Alex Deucher
Looks good.
Reviewed-by: Uma Shankar
> > ---
> > drivers/gpu/drm/drm_edid.c | 42
> > ++
> > 1 file changed, 24 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 96ae1fde4ce2..d6bce58b27ac 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -2202,6 +2202,11 @@ static bool is_display_descriptor(const u8 d[18], u8
> tag)
> > d[2] == 0x00 && d[3] == tag; }
> >
> > +static bool is_detailed_timing_descriptor(const u8 d[18]) {
> > + return d[0] != 0x00 || d[1] != 0x00; }
> > +
> > typedef void detailed_cb(struct detailed_timing *timing, void
> > *closure);
> >
> > static void
> > @@ -3101,27 +3106,28 @@ do_detailed_mode(struct detailed_timing *timing,
> void *c)
> > struct detailed_mode_closure *closure = c;
> > struct drm_display_mode *newmode;
> >
> > - if (timing->pixel_clock) {
> > - newmode = drm_mode_detailed(closure->connector->dev,
> > - closure->edid, timing,
> > - closure->quirks);
> > - if (!newmode)
> > - return;
> > + if (!is_detailed_timing_descriptor((const u8 *)timing))
> > + return;
> > +
> > + newmode = drm_mode_detailed(closure->connector->dev,
> > + closure->edid, timing,
> > + closure->quirks);
> > + if (!newmode)
> > + return;
> >
> > - if (closure->preferred)
> > - newmode->type |= DRM_MODE_TYPE_PREFERRED;
> > + if (closure->preferred)
> > + newmode->type |= DRM_MODE_TYPE_PREFERRED;
> >
> > - /*
> > -* Detailed modes are limited to 10kHz pixel clock
> > resolution,
> > -* so fix up anything that looks like CEA/HDMI mode, but
> > the clock
> > -* is just slightly off.
> > -*/
> > - fixup_detailed_cea_mode_clock(newmode);
> > + /*
> > +* Detailed modes are limited to 10kHz pixel clock resolution,
> > +* so fix up anything that looks like CEA/HDMI mode, but the clock
> > +* is just slightly off.
> > +*/
> > + fixup_detailed_cea_mode_clock(newmode);
> >
> > - drm_mode_probed_add(closure->connector, newmode);
> > - closure->modes++;
> > - closure->preferred = false;
> > - }
> > + drm_mode_probed_add(closure->connector, newmode);
> > + closure->modes++;
> > + closure->preferred = false;
> > }
> >
> > /*
> > --
> > 2.24.1
> >
> > ___
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> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [Intel-gfx] [PATCH 2/8] drm/edid: Don't accept any old garbage as a display descriptor
> -Original Message-
> From: Intel-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, January 28, 2020 4:06 AM
> To: Ville Syrjala
> Cc: Allen Chen ; Intel Graphics Development g...@lists.freedesktop.org>; Maling list - DRI developers de...@lists.freedesktop.org>
> Subject: Re: [Intel-gfx] [PATCH 2/8] drm/edid: Don't accept any old garbage
> as a
> display descriptor
>
> On Fri, Jan 24, 2020 at 3:02 PM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > Currently we assume any 18 byte descriptor to be a display descritor
> > if only the tag byte matches the expected value. But for detailed
> > timing descriptors that same byte is just the lower 8 bits of hblank,
> > and as such can match any display descriptor tag. To properly validate
> > that the 18 byte descriptor is in fact a display descriptor we must
> > also examine bytes 0-2 (just byte 1 should actually suffice but the
> > spec does say that bytes 0 and
> > 2 must also always be zero for display descriptors so we check those
> > too).
> >
> > Unlike Allen's original proposed patch to just fix is_rb() we roll
> > this out across the board to fix everything.
> >
> > Cc: Allen Chen
> > Signed-off-by: Ville Syrjälä
>
> Acked-by: Alex Deucher
Looks Good to me.
Reviewed-by: Uma Shankar
> > ---
> > drivers/gpu/drm/drm_edid.c | 65
> > --
> > 1 file changed, 41 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 1b6e544cf5c7..96ae1fde4ce2 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -2196,6 +2196,12 @@ struct drm_display_mode
> > *drm_mode_find_dmt(struct drm_device *dev, }
> > EXPORT_SYMBOL(drm_mode_find_dmt);
> >
> > +static bool is_display_descriptor(const u8 d[18], u8 tag) {
> > + return d[0] == 0x00 && d[1] == 0x00 &&
> > + d[2] == 0x00 && d[3] == tag; }
> > +
> > typedef void detailed_cb(struct detailed_timing *timing, void
> > *closure);
> >
> > static void
> > @@ -2257,9 +2263,12 @@ static void
> > is_rb(struct detailed_timing *t, void *data) {
> > u8 *r = (u8 *)t;
> > - if (r[3] == EDID_DETAIL_MONITOR_RANGE)
> > - if (r[15] & 0x10)
> > - *(bool *)data = true;
> > +
> > + if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
> > + return;
> > +
> > + if (r[15] & 0x10)
> > + *(bool *)data = true;
> > }
> >
> > /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly.
> > */ @@ -2279,7 +2288,11 @@ static void find_gtf2(struct
> > detailed_timing *t, void *data) {
> > u8 *r = (u8 *)t;
> > - if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
> > +
> > + if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
> > + return;
> > +
> > + if (r[10] == 0x02)
> > *(u8 **)data = r;
> > }
> >
> > @@ -2818,7 +2831,7 @@ do_inferred_modes(struct detailed_timing *timing, void
> *c)
> > struct detailed_non_pixel *data = &timing->data.other_data;
> > struct detailed_data_monitor_range *range = &data->data.range;
> >
> > - if (data->type != EDID_DETAIL_MONITOR_RANGE)
> > + if (!is_display_descriptor((const u8 *)timing,
> > + EDID_DETAIL_MONITOR_RANGE))
> > return;
> >
> > closure->modes += drm_dmt_modes_for_range(closure->connector,
> > @@ -2897,10 +2910,11 @@ static void
> > do_established_modes(struct detailed_timing *timing, void *c) {
> > struct detailed_mode_closure *closure = c;
> > - struct detailed_non_pixel *data = &timing->data.other_data;
> >
> > - if (data->type == EDID_DETAIL_EST_TIMINGS)
> > - closure->modes += drm_est3_modes(closure->connector,
> > timing);
> > + if (!is_display_descriptor((const u8 *)timing,
> > EDID_DETAIL_EST_TIMINGS))
> > + return;
> > +
> > + closure->modes += drm_est3_modes(closure->connector, timing);
> > }
> >
> > /**
> > @@ -2949,19 +2963,19 @@ do_standard_modes(struct detailed_timing *timing,
> void *c)
> > struct detailed_non_pixel *data = &timing->data.other_data;
> > struct drm_connector *connector = closure->connector;
> > struct edid *edid = closure->edid;
> > + int i;
> >
> > - if (data->type == EDID_DETAIL_STD_MODES) {
> > - int i;
> > - for (i = 0; i < 6; i++) {
> > - struct std_timing *std;
> > - struct drm_display_mode *newmode;
> > + if (!is_display_descriptor((const u8 *)timing,
> > EDID_DETAIL_STD_MODES))
> > + return;
> >
> > - std = &data->data.timings[i];
> > - newmode = drm_mode_std(connector, edid, std);
> > - if (newmode) {
> > - drm_mode_probed_add(connector, newmode);
> > -
Re: [Intel-gfx] [PATCH 1/8] drm/edid: Check the number of detailed timing descriptors in the CEA ext block
> -Original Message-
> From: dri-devel On Behalf Of Alex
> Deucher
> Sent: Tuesday, January 28, 2020 4:04 AM
> To: Ville Syrjala
> Cc: Allen Chen ; Intel Graphics Development g...@lists.freedesktop.org>; Maling list - DRI developers de...@lists.freedesktop.org>
> Subject: Re: [PATCH 1/8] drm/edid: Check the number of detailed timing
> descriptors
> in the CEA ext block
>
> On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > CEA-861 says :
> > "d = offset for the byte following the reserved data block.
> > If no data is provided in the reserved data block, then d=4.
> > If no DTDs are provided, then d=0."
> >
> > So let's not look for DTDs when d==0. In fact let's just make that
> > <4 since those values would just mean that he DTDs overlap the block
> > header. And let's also check that d isn't so big as to declare the
> > descriptors to live past the block end, although the code does already
> > survive that case as we'd just end up with a negative number of
> > descriptors and the loop would not do anything.
> >
> > Cc: Allen Chen
> > Signed-off-by: Ville Syrjälä
>
> Acked-by: Alex Deucher
Looks good to me as well.
Reviewed-by: Uma Shankar
> > ---
> > drivers/gpu/drm/drm_edid.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 99769d6c9f84..1b6e544cf5c7 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -2201,10 +2201,13 @@ typedef void detailed_cb(struct
> > detailed_timing *timing, void *closure); static void
> > cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
> > {
> > - int i, n = 0;
> > + int i, n;
> > u8 d = ext[0x02];
> > u8 *det_base = ext + d;
> >
> > + if (d < 4 || d > 127)
> > + return;
> > +
> > n = (127 - d) / 18;
> > for (i = 0; i < n; i++)
> > cb((struct detailed_timing *)(det_base + 18 * i),
> > closure);
> > --
> > 2.24.1
> >
> > ___
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[Intel-gfx] [PATCH] drm/i915/selftest: Ensure string fits within name[]
Shrink the strncpy bounds to ensure the NUL-terminator can fit within
the embedded array:
In file included from drivers/gpu/drm/i915/gem/i915_gem_context.c:2475:
drivers/gpu/drm/i915/gem/selftests/mock_context.c: In function ‘mock_context’:
drivers/gpu/drm/i915/gem/selftests/mock_context.c:40:3: error: ‘strncpy’
specified bound 24 equals destination size [-Werror=stringop-truncation]
40 | strncpy(ctx->name, name, sizeof(ctx->name));
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/selftests/mock_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c
b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
index 7bad8fed4238..81764289cf0d 100644
--- a/drivers/gpu/drm/i915/gem/selftests/mock_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
@@ -37,7 +37,7 @@ mock_context(struct drm_i915_private *i915,
if (name) {
struct i915_ppgtt *ppgtt;
- strncpy(ctx->name, name, sizeof(ctx->name));
+ strncpy(ctx->name, name, sizeof(ctx->name) - 1);
ppgtt = mock_ppgtt(i915, name);
if (!ppgtt)
--
2.25.0
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[Intel-gfx] [CI] drm/i915/selftests: Add a simple rollover test for the kernel context
Exercise the seqno wrap paths on the kernel context to provide a small
amount of sanity checking and ensure that they are visible to lockdep.
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 187
1 file changed, 187 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index e2d78cc22fb4..e59bf7e31d83 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -6,6 +6,8 @@
#include
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
#include "intel_gt.h"
#include "intel_gt_requests.h"
@@ -750,6 +752,189 @@ static int live_hwsp_wrap(void *arg)
return err;
}
+static void engine_heartbeat_disable(struct intel_engine_cs *engine,
+unsigned long *saved)
+{
+ *saved = engine->props.heartbeat_interval_ms;
+ engine->props.heartbeat_interval_ms = 0;
+
+ intel_engine_pm_get(engine);
+ intel_engine_park_heartbeat(engine);
+}
+
+static void engine_heartbeat_enable(struct intel_engine_cs *engine,
+ unsigned long saved)
+{
+ intel_engine_pm_put(engine);
+
+ engine->props.heartbeat_interval_ms = saved;
+}
+
+static int live_hwsp_rollover_kernel(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /*
+* Run the host for long enough, and even the kernel context will
+* see a seqno rollover.
+*/
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct intel_timeline *tl = ce->timeline;
+ struct i915_request *rq[3] = {};
+ unsigned long heartbeat;
+ int i;
+
+ engine_heartbeat_disable(engine, &heartbeat);
+ if (intel_gt_wait_for_idle(gt, HZ / 2)) {
+ err = -EIO;
+ goto out;
+ }
+
+ GEM_BUG_ON(i915_active_fence_isset(&tl->last_request));
+ tl->seqno = 0;
+ timeline_rollback(tl);
+ timeline_rollback(tl);
+ WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);
+
+ for (i = 0; i < ARRAY_SIZE(rq); i++) {
+ struct i915_request *this;
+
+ this = i915_request_create(ce);
+ if (IS_ERR(this)) {
+ err = PTR_ERR(this);
+ goto out;
+ }
+
+ pr_debug("%s: create fence.seqnp:%d\n",
+engine->name,
+lower_32_bits(this->fence.seqno));
+
+ GEM_BUG_ON(rcu_access_pointer(this->timeline) != tl);
+
+ rq[i] = i915_request_get(this);
+ i915_request_add(this);
+ }
+
+ /* We expected a wrap! */
+ GEM_BUG_ON(rq[2]->fence.seqno > rq[0]->fence.seqno);
+
+ if (i915_request_wait(rq[2], 0, HZ / 5) < 0) {
+ pr_err("Wait for timeline wrap timed out!\n");
+ err = -EIO;
+ goto out;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(rq); i++) {
+ if (!i915_request_completed(rq[i])) {
+ pr_err("Pre-wrap request not completed!\n");
+ err = -EINVAL;
+ goto out;
+ }
+ }
+
+out:
+ for (i = 0; i < ARRAY_SIZE(rq); i++)
+ i915_request_put(rq[i]);
+ engine_heartbeat_enable(engine, heartbeat);
+ if (err)
+ break;
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ return err;
+}
+
+static int live_hwsp_rollover_user(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /*
+* Simulate a long running user context, and force the seqno wrap
+* on the user's timeline.
+*/
+
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq[3] = {};
+ struct intel_timeline *tl;
+ struct intel_context *ce;
+ int i;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_alloc_state(ce);
+ if (err)
+ goto out;
+
+ tl = ce->timeline;
+ if (!tl->has_initial_breadcrumb
Re: [Intel-gfx] [PATCH 4/6] drm/i915/selftests: Add a simple rollover for the kernel context
Quoting Matthew Auld (2020-02-03 17:32:29)
> On 03/02/2020 09:41, Chris Wilson wrote:
> > + for (i = 0; i < ARRAY_SIZE(rq); i++) {
> > + rq[i] = i915_request_create(ce);
> > + if (IS_ERR(rq[i])) {
> > + err = PTR_ERR(rq[i]);
> > + goto out;
> > + }
> > +
...
> > +out:
> > + for (i = 0; i < ARRAY_SIZE(rq); i++)
> > + i915_request_put(rq[i]);
>
> !IS_ERR_OR_NULL()?
Oh drat, I let err into rq[]. I'll rework the assignment to avoid
putting the ERR_PTR here.
-Chris
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Re: [Intel-gfx] [RFC 1/2] drm/i915/tgl: WaEnablePreemptionGranularityControlByUMD
On Thu, Jan 30, 2020 at 11:31:07AM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Enable FtrPerCtxtPreemptionGranularityControl bit and whitelist
> GEN8_CS_CHICKEN1 so WaEnablePreemptionGranularityControlByUMD is
> implemented.
I may be misremembering, but wasn't this a "fake" workaround we added on
past platforms to avoid breaking compatibility with old pre-preemption
userspace? I.e., some userspace wasn't expecting fine-grained
preemption, so turning it on by default in the kernel would cause
breakage; we had to set the default to 'disabled' and then make
preemption-aware userspace opt back in.
Do we still need that for TGL? Wouldn't all userspace that exists for
this platform be aware of fine-grained preemption now (meaning we
wouldn't need to work around old, dumb userspace on this platform and
could just enable fine-grained preemption by default in the kernel)? Or
do we need this because there are there other workarounds that require
userspace to explicitly disable fine-grained preemption around specific
operations?
Matt
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Michał Winiarski
> Cc: Joonas Lahtinen
> Cc: piotr.zdunow...@intel.com
> Cc: michal.mro...@intel.com
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5a7db279f702..5d2a8cb70e16 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1254,6 +1254,9 @@ static void tgl_whitelist_build(struct intel_engine_cs
> *engine)
> whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> RING_FORCE_TO_NONPRIV_ACCESS_RD |
> RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> + /* WaEnablePreemptionGranularityControlByUMD:tgl */
> + whitelist_reg(w, GEN8_CS_CHICKEN1);
> break;
> default:
> break;
> @@ -1412,8 +1415,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> 0);
> }
>
> - if (IS_GEN_RANGE(i915, 9, 11)) {
> - /*
> FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
> + if (IS_GEN_RANGE(i915, 9, 12)) {
> + /*
> FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
> wa_masked_en(wal,
>GEN7_FF_SLICE_CS_CHICKEN1,
>GEN9_FFSC_PERCTX_PREEMPT_CTRL);
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 4/6] drm/i915/selftests: Add a simple rollover for the kernel context
On 03/02/2020 09:41, Chris Wilson wrote:
Exercise the seqno wrap paths on the kernel context to provide a small
amount of sanity checking and ensure that they are visible to lockdep.
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 177
1 file changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index e2d78cc22fb4..25edfd7a1544 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -6,6 +6,8 @@
#include
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
#include "intel_gt.h"
#include "intel_gt_requests.h"
@@ -750,6 +752,179 @@ static int live_hwsp_wrap(void *arg)
return err;
}
+static void engine_heartbeat_disable(struct intel_engine_cs *engine,
+unsigned long *saved)
+{
+ *saved = engine->props.heartbeat_interval_ms;
+ engine->props.heartbeat_interval_ms = 0;
+
+ intel_engine_pm_get(engine);
+ intel_engine_park_heartbeat(engine);
+}
+
+static void engine_heartbeat_enable(struct intel_engine_cs *engine,
+ unsigned long saved)
+{
+ intel_engine_pm_put(engine);
+
+ engine->props.heartbeat_interval_ms = saved;
+}
+
+static int live_hwsp_rollover_kernel(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /*
+* Run the host for long enough, and even the kernel context will
+* see a seqno rollover.
+*/
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct intel_timeline *tl = ce->timeline;
+ struct i915_request *rq[3] = {};
+ unsigned long heartbeat;
+ int i;
+
+ engine_heartbeat_disable(engine, &heartbeat);
+ if (intel_gt_wait_for_idle(gt, HZ / 2)) {
+ err = -EIO;
+ goto out;
+ }
+
+ GEM_BUG_ON(i915_active_fence_isset(&tl->last_request));
+ tl->seqno = 0;
+ timeline_rollback(tl);
+ timeline_rollback(tl);
+ WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);
+
+ for (i = 0; i < ARRAY_SIZE(rq); i++) {
+ rq[i] = i915_request_create(ce);
+ if (IS_ERR(rq[i])) {
+ err = PTR_ERR(rq[i]);
+ goto out;
+ }
+
+ pr_debug("%s: create fence.seqnp:%d\n",
+engine->name,
lower_32_bits(rq[i]->fence.seqno));
+ i915_request_get(rq[i]);
+ GEM_BUG_ON(rcu_access_pointer(rq[i]->timeline) != tl);
+ i915_request_add(rq[i]);
+ }
+
+ /* We expected a wrap! */
+ GEM_BUG_ON(rq[2]->fence.seqno > rq[0]->fence.seqno);
+
+ if (i915_request_wait(rq[2], 0, HZ / 5) < 0) {
+ pr_err("Wait for timeline wrap timed out!\n");
+ err = -EIO;
+ goto out;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(rq); i++) {
+ if (!i915_request_completed(rq[i])) {
+ pr_err("Pre-wrap request not completed!\n");
+ err = -EINVAL;
+ goto out;
+ }
+ }
+
+out:
+ for (i = 0; i < ARRAY_SIZE(rq); i++)
+ i915_request_put(rq[i]);
!IS_ERR_OR_NULL()?
Makes sense,
Reviewed-by: Matthew Auld
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Re: [Intel-gfx] [PATCH] drm/i915: Remove lite restore defines
Quoting Mika Kuoppala (2020-02-03 16:33:12) > We have switched from tail manipulation to forced context restore > to implement WaIdleLiteRestore. Remove the useless defines and comments. We still use the wa_tail as the first pass to avoid having to do WaIdleLiteRestore. And we do need to reset the ring after a suspend/resume because of the wa_tail. Hopefully, our selftest for the latter still detects such bugs... We just aren't using the macro any more. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Remove lite restore defines
We have switched from tail manipulation to forced context restore
to implement WaIdleLiteRestore. Remove the useless defines and comments.
References: f26a9e959a7b ("drm/i915/gt: Detect if we miss WaIdleLiteRestore")
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index c196fb90c59f..bc0835c3fb2c 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -176,8 +176,6 @@
/* Typical size of the average request (2 pipecontrols and a MI_BB) */
#define EXECLISTS_REQUEST_SIZE 64 /* bytes */
-#define WA_TAIL_DWORDS 2
-#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
struct virtual_engine {
struct intel_engine_cs base;
@@ -2927,22 +2925,6 @@ static void execlists_context_reset(struct intel_context
*ce)
CE_TRACE(ce, "reset\n");
GEM_BUG_ON(!intel_context_is_pinned(ce));
- /*
-* Because we emit WA_TAIL_DWORDS there may be a disparity
-* between our bookkeeping in ce->ring->head and ce->ring->tail and
-* that stored in context. As we only write new commands from
-* ce->ring->tail onwards, everything before that is junk. If the GPU
-* starts reading from its RING_HEAD from the context, it may try to
-* execute that junk and die.
-*
-* The contexts that are stilled pinned on resume belong to the
-* kernel, and are local to each engine. All other contexts will
-* have their head/tail sanitized upon pinning before use, so they
-* will never see garbage,
-*
-* So to avoid that we reset the context images upon resume. For
-* simplicity, we just zero everything out.
-*/
intel_ring_reset(ce->ring, ce->ring->emit);
/* Scrub away the garbage */
--
2.17.1
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for mipi dsi cmd mode (rev6)
== Series Details == Series: Add support for mipi dsi cmd mode (rev6) URL : https://patchwork.freedesktop.org/series/69290/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for mipi dsi cmd mode (rev6)
== Series Details ==
Series: Add support for mipi dsi cmd mode (rev6)
URL : https://patchwork.freedesktop.org/series/69290/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ea615cb735b1 drm/i915/dsi: Configure transcoder operation for command mode.
385e5a8e53ff drm/i915/dsi: Add vblank calculation for command mode
-:48: WARNING:LONG_LINE: line over 100 characters
#48: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:874:
+ line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) /
(1000 * intel_dsi->lane_count);
total: 0 errors, 1 warnings, 0 checks, 101 lines checked
772ce3c4e0f8 drm/i915/dsi: Add cmd mode flags in display mode private flags
-:30: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#30: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:645:
+#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
^
-:32: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#32: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:647:
+#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
^
-:34: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#34: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:649:
+#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
^
total: 0 errors, 0 warnings, 3 checks, 16 lines checked
1ef376297866 drm/i915/dsi: Add check for periodic command mode
b941069992a4 drm/i915/dsi: Use private flags to indicate TE in cmd mode
e067d4de5cf6 drm/i915/dsi: Configure TE interrupt for cmd mode
60e2f1c03550 drm/i915/dsi: Add TE handler for dsi cmd mode.
-:50: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'val !=
CMD_MODE_NO_GATE'
#50: FILE: drivers/gpu/drm/i915/i915_irq.c:2269:
+ if ((val != CMD_MODE_NO_GATE) && (val != CMD_MODE_TE_GATE)) {
-:50: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'val !=
CMD_MODE_TE_GATE'
#50: FILE: drivers/gpu/drm/i915/i915_irq.c:2269:
+ if ((val != CMD_MODE_NO_GATE) && (val != CMD_MODE_TE_GATE)) {
total: 0 errors, 0 warnings, 2 checks, 76 lines checked
e78b1c235dfc drm/i915/dsi: Initiate fame request in cmd mode
fbc38b833279 drm/i915/dsi: Clear the DSI IIR
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm: Add a detailed DP HDMI branch info on debugfs
== Series Details == Series: series starting with [1/2] drm: Add a detailed DP HDMI branch info on debugfs URL : https://patchwork.freedesktop.org/series/72914/ State : success == Summary == CI Bug Log - changes from CI_DRM_7859 -> Patchwork_16392 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/index.html Known issues Here are the changes found in Patchwork_16392 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][3] -> [DMESG-FAIL][4] ([fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-icl-y/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [PASS][5] -> [TIMEOUT][6] ([fdo#112271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-bdw-5557u/igt@i915_selftest@live_gtt.html * igt@i915_selftest@live_hangcheck: - fi-icl-dsi: [PASS][7] -> [INCOMPLETE][8] ([fdo#108569]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-gdg-551: [PASS][9] -> [INCOMPLETE][10] ([i915#172]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-gdg-551/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-gdg-551/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html Possible fixes * igt@i915_module_load@reload-no-display: - fi-icl-u2: [INCOMPLETE][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-icl-u2/igt@i915_module_l...@reload-no-display.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-icl-u2/igt@i915_module_l...@reload-no-display.html * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [FAIL][13] ([i915#178]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][15] ([i915#563]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-hsw-4770/igt@i915_selftest@live_blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-byt-n2820: [DMESG-FAIL][17] ([i915#1052]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [DMESG-FAIL][19] ([i915#623]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-edid-read: - fi-icl-u2: [FAIL][21] ([i915#217]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html Warnings * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][23] ([fdo#112271] / [i915#1084] / [i915#816]) -> [INCOMPLETE][24] ([i915#45]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@gem_exec_parallel@contexts: - fi-byt-n2820: [FAIL][25] ([i915#694]) -> [TIMEOUT][26] ([fdo#112271] / [i915#1084]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-byt-n2820/igt@gem_exec_paral...@contexts.html [26]: https://intel-gfx-
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsb: Enable lmem for dsb
== Series Details ==
Series: drm/i915/dsb: Enable lmem for dsb
URL : https://patchwork.freedesktop.org/series/72818/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7850_full -> Patchwork_16355_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_16355_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_persistence@legacy-bcs0-mixed-process}:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-skl10/igt@gem_ctx_persiste...@legacy-bcs0-mixed-process.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-skl6/igt@gem_ctx_persiste...@legacy-bcs0-mixed-process.html
Known issues
Here are the changes found in Patchwork_16355_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@vcs1-mixed-process:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +19 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-iclb4/igt@gem_ctx_persiste...@vcs1-mixed-process.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-iclb5/igt@gem_ctx_persiste...@vcs1-mixed-process.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-iclb2/igt@gem_exec_balan...@smoke.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-iclb5/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-iclb8/igt@gem_exec_sched...@pi-common-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-iclb4/igt@gem_exec_sched...@pi-common-bsd.html
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +26 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-iclb4/igt@gem_exec_sched...@preempt-contexts-bsd2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-iclb5/igt@gem_exec_sched...@preempt-contexts-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +7 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-iclb5/igt@gem_exec_sched...@preempt-other-chain-bsd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +5
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-kbl2/igt@gem_exec_susp...@basic-s3.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-kbl7/igt@gem_exec_susp...@basic-s3.html
* igt@gem_partial_pwrite_pread@write:
- shard-hsw: [PASS][15] -> [FAIL][16] ([i915#694]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-hsw1/igt@gem_partial_pwrite_pr...@write.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-hsw5/igt@gem_partial_pwrite_pr...@write.html
* igt@i915_pm_rps@min-max-config-loaded:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#370])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-iclb4/igt@i915_pm_...@min-max-config-loaded.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-iclb6/igt@i915_pm_...@min-max-config-loaded.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#300])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [PASS][21] -> [FAIL][22] ([IGT#5] / [i915#697])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-skl4/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16355/shard-skl1/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
* igt@kms_draw_crc@draw-method-xrgb-pwrite-xtiled:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#52] / [i915#54])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7850/shard-skl7/igt@kms_draw_...@draw-method-xrgb-pwrite-x
Re: [Intel-gfx] [PATCH 06/12] drm/i915/gt: Pull sseu context updates under gt
On Fri, 31 Jan 2020 at 10:46, Chris Wilson wrote: > > Lift the routines to emit a request to update the SSEU on the > intel_context out of i915_gem_context. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Stop using mutex while sending CTB messages (rev4)
== Series Details == Series: drm/i915/guc: Stop using mutex while sending CTB messages (rev4) URL : https://patchwork.freedesktop.org/series/72827/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7859 -> Patchwork_16391 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16391 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16391, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16391: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s3: - fi-skl-guc: [PASS][1] -> [DMESG-WARN][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-skl-guc/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-skl-guc/igt@gem_exec_susp...@basic-s3.html * igt@i915_pm_rpm@basic-rte: - fi-skl-guc: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-skl-guc/igt@i915_pm_...@basic-rte.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-skl-guc/igt@i915_pm_...@basic-rte.html Known issues Here are the changes found in Patchwork_16391 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-guc: [PASS][5] -> [SKIP][6] ([fdo#109271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-skl-guc/igt@i915_pm_...@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-skl-guc/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][7] -> [DMESG-FAIL][8] ([fdo#108569]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-icl-y/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-gdg-551: [PASS][9] -> [INCOMPLETE][10] ([i915#172]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-gdg-551/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-gdg-551/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][11] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_module_load@reload-no-display: - fi-icl-u2: [INCOMPLETE][13] -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-icl-u2/igt@i915_module_l...@reload-no-display.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-icl-u2/igt@i915_module_l...@reload-no-display.html * igt@i915_selftest@live_gem_contexts: - fi-byt-n2820: [DMESG-FAIL][15] ([i915#1052]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [DMESG-FAIL][17] ([i915#623]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-edid-read: - fi-icl-u2: [FAIL][19] ([i915#217]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html Warnings * igt@gem_exec_parallel@fds: - fi-byt-n2820: [TIMEOUT][21] ([fdo#112271] / [i915#1084]) -> [FAIL][22] ([i915#694]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/fi-byt-n2820/igt@gem_exec_paral...@fds.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16391/fi-byt-n2820/igt@gem_exec_paral...@fds.html - fi-byt-j1900: [INCOMPLETE][23] ([i915#45]) -> [FAIL][24] ([i915#694]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_785
[Intel-gfx] [PATCH 09/26] drm/i915: Reworkd DFP max bpc handling
From: Ville Syrjälä
Stash the downstream facing port max bpc away during
intel_dp_set_edid(). We'll soon need the EDID in there so
we can't figure this out so easily during .compute_config() anymore.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 5 +
drivers/gpu/drm/i915/display/intel_dp.c | 21 +--
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5774240c0996..dba0bb245a43 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1304,6 +1304,11 @@ struct intel_dp {
/* Display stream compression testing */
bool force_dsc_en;
+
+ /* Downstream facing port caps */
+ struct {
+ u8 max_bpc;
+ } dfp;
};
enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1786e6e8ffe3..5fab7ab97815 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1914,13 +1914,12 @@ static int intel_dp_compute_bpp(struct intel_dp
*intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_connector *intel_connector = intel_dp->attached_connector;
- int bpp, bpc;
+ int bpp;
bpp = pipe_config->pipe_bpp;
- bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd,
intel_dp->downstream_ports);
- if (bpc > 0)
- bpp = min(bpp, 3*bpc);
+ if (intel_dp->dfp.max_bpc)
+ bpp = min(bpp, 3 * intel_dp->dfp.max_bpc);
if (intel_dp_is_edp(intel_dp)) {
/* Get bpp from vbt only for panels that dont have bpp in edid
*/
@@ -5657,12 +5656,20 @@ intel_dp_get_edid(struct intel_dp *intel_dp)
static void
intel_dp_set_edid(struct intel_dp *intel_dp)
{
- struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct intel_connector *connector = intel_dp->attached_connector;
struct edid *edid;
intel_dp_unset_edid(intel_dp);
edid = intel_dp_get_edid(intel_dp);
- intel_connector->detect_edid = edid;
+ connector->detect_edid = edid;
+
+ intel_dp->dfp.max_bpc =
+ drm_dp_downstream_max_bpc(intel_dp->dpcd,
+ intel_dp->downstream_ports);
+
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] DFP max bpc %d\n",
+ connector->base.base.id, connector->base.name,
+ intel_dp->dfp.max_bpc);
if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
@@ -5683,6 +5690,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
intel_dp->has_hdmi_sink = false;
intel_dp->has_audio = false;
+
+ intel_dp->dfp.max_bpc = 0;
}
static int
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 21/26] drm/i915: DP->HDMI TMDS clock limits vs. deep color
From: Ville Syrjälä
Account for the TMDS clock limits declared by the DFP/DP++ dongle
when determining what color depth we're going to use.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 67 ---
drivers/gpu/drm/i915/display/intel_hdmi.c | 50 ++---
drivers/gpu/drm/i915/display/intel_hdmi.h | 2 +
3 files changed, 90 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 65202615c8f1..639a0c2e5a40 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1918,18 +1918,69 @@ static bool intel_dp_supports_dsc(struct intel_dp
*intel_dp,
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
-static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config)
+static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
+}
+
+static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
int bpc)
+{
+ int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
+
+ if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
+ clock /= 2;
+
+ return clock;
+}
+
+static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state, int bpc)
+{
+ int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
+
+ if (intel_dp->dfp.min_tmds_clock &&
+ tmds_clock < intel_dp->dfp.min_tmds_clock)
+ return false;
+
+ if (intel_dp->dfp.max_tmds_clock &&
+ tmds_clock > intel_dp->dfp.max_tmds_clock)
+ return false;
+
+ return true;
+}
+
+static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ int bpc)
+{
+ bool has_hdmi_sink = intel_dp->has_hdmi_sink;
+
+ return intel_hdmi_deep_color_possible(crtc_state, bpc, has_hdmi_sink) &&
+ intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
+}
+
+static int intel_dp_max_bpp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_connector *intel_connector = intel_dp->attached_connector;
- int bpp;
+ int bpp, bpc;
- bpp = pipe_config->pipe_bpp;
+ bpc = crtc_state->pipe_bpp / 3;
if (intel_dp->dfp.max_bpc)
- bpp = min(bpp, 3 * intel_dp->dfp.max_bpc);
+ bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
+ if (intel_dp->dfp.min_tmds_clock) {
+ for (; bpc >= 10; bpc -= 2) {
+ if (intel_dp_hdmi_deep_color_possible(intel_dp,
crtc_state, bpc))
+ break;
+ }
+ }
+
+ bpp = bpc * 3;
if (intel_dp_is_edp(intel_dp)) {
/* Get bpp from vbt only for panels that dont have bpp in edid
*/
if (intel_connector->base.display_info.bpc == 0 &&
@@ -2244,7 +2295,7 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
limits.min_bpp = intel_dp_min_bpp(pipe_config);
- limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
+ limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
if (intel_dp_is_edp(intel_dp)) {
/*
@@ -3579,10 +3630,10 @@ void intel_dp_configure_protocol_converter(struct
intel_dp *intel_dp)
{
u8 tmp;
- if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
+ if (!drm_dp_is_branch(intel_dp->dpcd))
return;
- if (!drm_dp_is_branch(intel_dp->dpcd))
+ if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
return;
tmp = intel_dp->has_hdmi_sink ?
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 31fec0050f8d..d6326a4a4a9a 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2218,35 +2218,18 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
return intel_mode_valid_max_plane_size(dev_priv, mode);
}
-static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
-int bpc)
+bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
+ int bpc, bool has_hdmi_sink)
{
- struct drm_i915_private *dev_priv =
-
[Intel-gfx] [PATCH 01/26] drm/i915: Nuke pre-production GLK HDMI w/a 1139
From: Ville Syrjälä w/a #1139 is only needed for pre-production GLK. Nuke it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_hdmi.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index ab13cf834cc4..9e409a819ff5 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2274,11 +2274,6 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, } } - /* Display WA #1139: glk */ - if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && - adjusted_mode->htotal > 5460) - return false; - /* Display Wa_1405510057:icl */ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && bpc == 10 && INTEL_GEN(dev_priv) >= 11 && -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/26] drm/i915: Configure DP 1.3+ protocol converted HDMI mode
From: Ville Syrjälä
DP 1.3 adds some extra control knobs for DP->HDMI protocol conversion.
Let's use that to configure the "HDMI mode" (ie. infoframes vs. not)
based on the capabilities of the sink.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 818bee4918fa..3d1393ff6435 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3551,6 +3551,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_configure_protocol_converter(intel_dp);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c0a638df97c5..d075450a0472 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3575,6 +3575,27 @@ static void intel_dp_enable_port(struct intel_dp
*intel_dp,
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
+void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp)
+{
+ u8 tmp;
+
+ if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
+ return;
+
+ if (!drm_dp_is_branch(intel_dp->dpcd))
+ return;
+
+ tmp = intel_dp->has_hdmi_sink ?
+ DP_HDMI_DVI_OUTPUT_CONFIG : 0;
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) <= 0)
+ DRM_DEBUG_KMS("Failed to set protocol converter HDMI mode to
%s\n",
+ enableddisabled(intel_dp->has_hdmi_sink));
+
+ /* TODO: configure YCbCr 4:2:2/4:2:0 conversion */
+}
+
static void intel_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
@@ -3611,6 +3632,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
}
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_configure_protocol_converter(intel_dp);
intel_dp_start_link_train(intel_dp);
intel_dp_stop_link_train(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..953197d46444 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -51,6 +51,7 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp,
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp);
void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state,
bool enable);
--
2.24.1
___
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[Intel-gfx] [PATCH 16/26] drm/i915: Deal with TMDS DFP clock limits
From: Ville Syrjälä
Use the new helpers to extract the TMDS clock limits from
the downstream facing port and check them in .mode_valid().
TODO: we should check these in .compute_config() too to eg.
determine if we can do deep color on the HDMI side or not
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 35 +--
2 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index f978b33ea757..117fc17dae44 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1307,6 +1307,7 @@ struct intel_dp {
/* Downstream facing port caps */
struct {
+ int min_tmds_clock, max_tmds_clock;
int max_dotclock;
u8 max_bpc;
} dfp;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a0b611e8b370..c0a638df97c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -585,14 +585,29 @@ static bool intel_dp_hdisplay_bad(struct drm_i915_private
*dev_priv,
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
+ const struct drm_display_mode *mode,
int target_clock)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
+ const struct drm_display_info *info = &connector->base.display_info;
+ int tmds_clock;
if (intel_dp->dfp.max_dotclock &&
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
+ /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
+ tmds_clock = target_clock;
+ if (drm_mode_is_420_only(info, mode))
+ tmds_clock /= 2;
+
+ if (intel_dp->dfp.min_tmds_clock &&
+ tmds_clock < intel_dp->dfp.min_tmds_clock)
+ return MODE_CLOCK_LOW;
+ if (intel_dp->dfp.max_tmds_clock &&
+ tmds_clock > intel_dp->dfp.max_tmds_clock)
+ return MODE_CLOCK_HIGH;
+
return MODE_OK;
}
@@ -669,7 +684,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
return MODE_H_ILLEGAL;
- status = intel_dp_mode_valid_downstream(intel_connector, target_clock);
+ status = intel_dp_mode_valid_downstream(intel_connector,
+ mode, target_clock);
if (status != MODE_OK)
return status;
@@ -5667,10 +5683,21 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
drm_dp_downstream_max_dotclock(intel_dp->dpcd,
intel_dp->downstream_ports);
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d\n",
+ intel_dp->dfp.min_tmds_clock =
+ drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
+intel_dp->downstream_ports,
+edid);
+ intel_dp->dfp.max_tmds_clock =
+ drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
+intel_dp->downstream_ports,
+edid);
+
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS
clock %d-%d\n",
connector->base.base.id, connector->base.name,
intel_dp->dfp.max_bpc,
- intel_dp->dfp.max_dotclock);
+ intel_dp->dfp.max_dotclock,
+ intel_dp->dfp.min_tmds_clock,
+ intel_dp->dfp.max_tmds_clock);
if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
@@ -5694,6 +5721,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
intel_dp->dfp.max_bpc = 0;
intel_dp->dfp.max_dotclock = 0;
+ intel_dp->dfp.min_tmds_clock = 0;
+ intel_dp->dfp.max_tmds_clock = 0;
}
static int
--
2.24.1
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[Intel-gfx] [PATCH 24/26] drm/i915: Decouple DP++ from the HDMI code
From: Ville Syrjälä
Decouple the DP dual mode adaptor stuff from the HDMI code so that
we can try to use it for DP branch downstream facing HDMI ports as
well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
.../drm/i915/display/intel_display_types.h| 12 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 94 ++-
drivers/gpu/drm/i915/display/intel_hdmi.h | 9 +-
4 files changed, 72 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3d1393ff6435..92c280905f31 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3598,7 +3598,8 @@ static void intel_ddi_pre_enable_hdmi(struct
intel_encoder *encoder,
int level = intel_ddi_hdmi_level(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_hdmi->dp_dual_mode, true);
intel_ddi_clk_select(encoder, crtc_state);
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
@@ -3778,7 +3779,8 @@ static void intel_ddi_post_disable_hdmi(struct
intel_encoder *encoder,
intel_ddi_clk_disable(encoder);
- intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_hdmi->dp_dual_mode, false);
}
static void icl_disable_transcoder_port_sync(const struct intel_crtc_state
*old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 00471791d772..0d135859e9d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -46,6 +46,7 @@
#include "i915_drv.h"
#include "intel_de.h"
+struct i2c_adapter;
struct drm_printer;
struct __intel_global_objs_state;
@@ -1150,15 +1151,18 @@ struct cxsr_latency {
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
+struct intel_dp_dual_mode {
+ struct i2c_adapter *adapter;
+ int max_tmds_clock;
+ enum drm_dp_dual_mode_type type;
+};
+
struct intel_hdmi {
i915_reg_t hdmi_reg;
int ddc_bus;
- struct {
- enum drm_dp_dual_mode_type type;
- int max_tmds_clock;
- } dp_dual_mode;
bool has_hdmi_sink;
bool has_audio;
+ struct intel_dp_dual_mode dp_dual_mode;
struct intel_connector *attached_connector;
struct cec_notifier *cec_notifier;
};
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 9e0316f6eb3f..ad8e974585b9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1249,20 +1249,19 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
&crtc_state->infoframes.drm);
}
-void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
+void intel_dp_dual_mode_set_tmds_output(struct intel_encoder *encoder,
+ struct intel_dp_dual_mode *dp_dual_mode,
+ bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
- struct i2c_adapter *adapter =
- intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
-
- if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
+ if (dp_dual_mode->type < DRM_DP_DUAL_MODE_TYPE2_DVI)
return;
- DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
+ DRM_DEBUG_KMS("[ENCODER:%d:%s] %s DP dual mode adaptor TMDS output\n",
+ encoder->base.base.id, encoder->base.name,
enable ? "Enabling" : "Disabling");
- drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
-adapter, enable);
+ drm_dp_dual_mode_set_tmds_output(dp_dual_mode->type,
+dp_dual_mode->adapter, enable);
}
static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
@@ -1750,7 +1749,8 @@ static void intel_hdmi_prepare(struct intel_encoder
*encoder,
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
u32 hdmi_val;
- intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_hdmi->dp_dual_mode, true);
hdmi_val = SDVO_ENCODING_HDMI;
if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
@@ -2064,7 +2064,8 @@ static void intel_disab
[Intel-gfx] [PATCH 19/26] drm/i915: Handle downstream facing ports w/o EDID
From: Ville Syrjälä
Use drm_dp_downstream_mode() to get a suitable mode for downstream
facing ports which don't have an EDID.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d075450a0472..65202615c8f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5893,7 +5893,7 @@ static int intel_dp_get_modes(struct drm_connector
*connector)
}
/* if eDP has no EDID, fall back to fixed mode */
- if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
+ if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
intel_connector->panel.fixed_mode) {
struct drm_display_mode *mode;
@@ -5905,6 +5905,19 @@ static int intel_dp_get_modes(struct drm_connector
*connector)
}
}
+ if (!edid) {
+ struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
+ struct drm_display_mode *mode;
+
+ mode = drm_dp_downstream_mode(connector->dev,
+ intel_dp->dpcd,
+ intel_dp->downstream_ports);
+ if (mode) {
+ drm_mode_probed_add(connector, mode);
+ return 1;
+ }
+ }
+
return 0;
}
--
2.24.1
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[Intel-gfx] [PATCH 26/26] drm/i915: Try to frob the TMDS buffer enable knob on DP++ dongles on DP DFPs
From: Ville Syrjälä
To save a bit of power let's try to power down the TMDS buffers on
DP++ dongles hooked to downstream facing DP++ ports.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++
drivers/gpu/drm/i915/display/intel_dp.c | 25
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 92c280905f31..5daa52909980 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3512,6 +3512,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder
*encoder,
else
WARN_ON(is_mst && port == PORT_A);
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_dp->dp_dual_mode, true);
+
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
crtc_state->lane_count, is_mst);
@@ -3757,6 +3760,9 @@ static void intel_ddi_post_disable_dp(struct
intel_encoder *encoder,
dig_port->ddi_io_power_domain);
intel_ddi_clk_disable(encoder);
+
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_dp->dp_dual_mode, false);
}
static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5143c1b0fd92..0452cc9423e6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3510,19 +3510,28 @@ static void g4x_post_disable_dp(struct intel_encoder
*encoder,
/* Only ilk+ has port A */
if (port == PORT_A)
ilk_edp_pll_off(intel_dp, old_crtc_state);
+
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_dp->dp_dual_mode, false);
}
static void vlv_post_disable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state
*old_conn_state)
{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
intel_dp_link_down(encoder, old_crtc_state);
+
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_dp->dp_dual_mode, false);
}
static void chv_post_disable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state
*old_conn_state)
{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
intel_dp_link_down(encoder, old_crtc_state);
@@ -3533,6 +3542,9 @@ static void chv_post_disable_dp(struct intel_encoder
*encoder,
chv_data_lane_soft_reset(encoder, old_crtc_state, true);
vlv_dpio_put(dev_priv);
+
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_dp->dp_dual_mode, false);
}
static void
@@ -3748,6 +3760,9 @@ static void g4x_pre_enable_dp(struct intel_encoder
*encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
enum port port = encoder->port;
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_dp->dp_dual_mode, true);
+
intel_dp_prepare(encoder, pipe_config);
/* Only ilk+ has port A */
@@ -3865,6 +3880,11 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_dp->dp_dual_mode, true);
+
vlv_phy_pre_encoder_enable(encoder, pipe_config);
intel_enable_dp(encoder, pipe_config, conn_state);
@@ -3883,6 +3903,11 @@ static void chv_pre_enable_dp(struct intel_encoder
*encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_dp_dual_mode_set_tmds_output(encoder,
+ &intel_dp->dp_dual_mode, true);
+
chv_phy_pre_encoder_enable(encoder, pipe_config);
intel_enable_dp(encoder, pipe_config, conn_state);
--
2.24.1
___
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[Intel-gfx] [PATCH 22/26] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling
From: Ville Syrjälä
Add helpers to determine whether the DFP supports
YCbCr 4:2:0 passthrough or YCbCr 4:4:4->4:2:0 conversion.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_helper.c | 44 +
include/drm/drm_dp_helper.h | 8 ++
2 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 507282dc79ac..66d176090d6a 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -615,6 +615,50 @@ int drm_dp_downstream_max_bpc(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
}
EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
+bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4])
+{
+ if (!drm_dp_is_branch(dpcd))
+ return false;
+
+ if (dpcd[DP_DPCD_REV] < 0x13)
+ return false;
+
+ switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+ case DP_DS_PORT_TYPE_DP:
+ return true;
+ case DP_DS_PORT_TYPE_HDMI:
+ if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+ return false;
+
+ return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
+ default:
+ return false;
+ }
+}
+EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
+
+bool drm_dp_downstream_444_to_420_conversion(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
+const u8 port_cap[4])
+{
+ if (!drm_dp_is_branch(dpcd))
+ return false;
+
+ if (dpcd[DP_DPCD_REV] < 0x13)
+ return false;
+
+ switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+ case DP_DS_PORT_TYPE_HDMI:
+ if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+ return false;
+
+ return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
+ default:
+ return false;
+ }
+}
+EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
+
/**
* drm_dp_downstream_mode() - return a mode for downstream facing port
* @dpcd: DisplayPort configuration data
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index be4a5ffe4252..9cef282064f3 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -406,6 +406,10 @@ struct drm_device;
# define DP_DS_DVI_HIGH_COLOR_DEPTH(1 << 2)
/* offset 3 for HDMI */
# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
+# define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
+# define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
+# define DP_DS_HDMI_YCBCR444_TO_422_CONV(1 << 3)
+# define DP_DS_HDMI_YCBCR444_TO_420_CONV(1 << 4)
#define DP_MAX_DOWNSTREAM_PORTS0x10
@@ -1500,6 +1504,10 @@ int drm_dp_downstream_min_tmds_clock(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4],
const struct edid *edid);
+bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4]);
+bool drm_dp_downstream_444_to_420_conversion(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
+const u8 port_cap[4]);
struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
const u8
dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]);
--
2.24.1
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[Intel-gfx] [PATCH 25/26] drm/i915: Try to probe DP++ dongles on DP++ downstream facing ports
From: Ville Syrjälä
In order to get accurate TMDS clocks limits for the DP++ ports we
can try to probe the DP dual mode adapter registers. Unfortunately
I've not yet seen a DP->DP++ branch device that would actually
forward these i2c accesses to the dual mode dongle downstream.
But we don't lose much by trying and maybe it'll work on some
branch devices, if not now then maybe in the future.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 41 +++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0d135859e9d4..5cd052f55662 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1316,6 +1316,7 @@ struct intel_dp {
u8 max_bpc;
bool ycbcr_444_to_420;
} dfp;
+ struct intel_dp_dual_mode dp_dual_mode;
};
enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3bf19d691fd5..5143c1b0fd92 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -608,6 +608,10 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
tmds_clock > intel_dp->dfp.max_tmds_clock)
return MODE_CLOCK_HIGH;
+ if (intel_dp->dp_dual_mode.max_tmds_clock &&
+ tmds_clock > intel_dp->dp_dual_mode.max_tmds_clock)
+ return MODE_CLOCK_HIGH;
+
return MODE_OK;
}
@@ -1762,6 +1766,8 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
aux_ch_name(dig_port->aux_ch),
port_name(encoder->port));
intel_dp->aux.transfer = intel_dp_aux_transfer;
+
+ intel_dp->dp_dual_mode.adapter = &intel_dp->aux.ddc;
}
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
@@ -1950,6 +1956,10 @@ static bool intel_dp_hdmi_tmds_clock_valid(struct
intel_dp *intel_dp,
tmds_clock > intel_dp->dfp.max_tmds_clock)
return false;
+ if (intel_dp->dp_dual_mode.max_tmds_clock &&
+ tmds_clock > intel_dp->dp_dual_mode.max_tmds_clock)
+ return false;
+
return true;
}
@@ -5850,6 +5860,35 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
intel_dp_update_dfp(intel_dp, edid);
intel_dp_update_420(intel_dp);
+ if (drm_dp_downstream_is_tmds(intel_dp->dpcd,
+ intel_dp->downstream_ports,
+ edid)) {
+ /*
+* Most branch devices don't seem to forward the
+* DP dual mode i2c accesses to the dongle, so even
+* when you have a type2 HDMI dongle with a high TMDS
+* clock limit we may not be able to detect it :(
+* To avoid users complaining about losing high
+* resolution modes let's not assume type1 DVI
+* dongle presence when the access fails. There
+* doesn't seem to be any way to read the CONFIG1
+* pin state from the branch device.
+*/
+ intel_dp_dual_mode_detect(connector, &intel_dp->dp_dual_mode,
false);
+
+ /*
+* We drive LSPCON DP dual mode adaptors in PCON mode
+* so we should just ignore the HDMI side of it.
+*/
+ if (intel_dp->dp_dual_mode.type == DRM_DP_DUAL_MODE_LSPCON) {
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Ignoring LSPCON DP
dual mode adaptor presence\n",
+ connector->base.base.id,
+ connector->base.name);
+
+ intel_dp_dual_mode_reset(&intel_dp->dp_dual_mode);
+ }
+ }
+
if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
intel_dp->has_audio = drm_detect_monitor_audio(edid);
@@ -5877,6 +5916,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
intel_dp->dfp.ycbcr_444_to_420 = false;
connector->base.ycbcr_420_allowed = false;
+
+ intel_dp_dual_mode_reset(&intel_dp->dp_dual_mode);
}
static int
--
2.24.1
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[Intel-gfx] [PATCH 18/26] drm/dp: Add drm_dp_downstream_mode()
From: Ville Syrjälä
The downstream facing port caps in the DPCD can give us a hint
as to what kind of display mode the sink can use if it doesn't
have an EDID. Use that information to pick a suitable mode.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_helper.c | 54 +
drivers/gpu/drm/drm_edid.c | 21 +
include/drm/drm_dp_helper.h | 12
include/drm/drm_edid.h | 4 +++
4 files changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 31ca550467ed..507282dc79ac 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -615,6 +615,60 @@ int drm_dp_downstream_max_bpc(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
}
EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
+/**
+ * drm_dp_downstream_mode() - return a mode for downstream facing port
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ *
+ * Provides a suitable mode for downstream facing ports without EDID.
+ *
+ * Returns a new drm_display_mode on success or NULL on failure
+ */
+struct drm_display_mode *
+drm_dp_downstream_mode(struct drm_device *dev,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4])
+
+{
+ u8 vic;
+
+ if (!drm_dp_is_branch(dpcd))
+ return NULL;
+
+ if (dpcd[DP_DPCD_REV] < 0x11)
+ return NULL;
+
+ switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+ case DP_DS_PORT_TYPE_NON_EDID:
+ switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
+ case DP_DS_NON_EDID_720x480i_60:
+ vic = 6;
+ break;
+ case DP_DS_NON_EDID_720x480i_50:
+ vic = 21;
+ break;
+ case DP_DS_NON_EDID_1920x1080i_60:
+ vic = 5;
+ break;
+ case DP_DS_NON_EDID_1920x1080i_50:
+ vic = 20;
+ break;
+ case DP_DS_NON_EDID_1280x720_60:
+ vic = 4;
+ break;
+ case DP_DS_NON_EDID_1280x720_50:
+ vic = 19;
+ break;
+ default:
+ return NULL;
+ }
+ return drm_display_mode_from_cea_vic(dev, vic);
+ default:
+ return NULL;
+ }
+}
+EXPORT_SYMBOL(drm_dp_downstream_mode);
+
/**
* drm_dp_downstream_id() - identify branch device
* @aux: DisplayPort AUX channel
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 99769d6c9f84..4894a00b0711 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3633,6 +3633,27 @@ drm_add_cmdb_modes(struct drm_connector *connector, u8
svd)
bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
}
+struct drm_display_mode *
+drm_display_mode_from_cea_vic(struct drm_device *dev,
+ u8 video_code)
+{
+ const struct drm_display_mode *cea_mode;
+ struct drm_display_mode *newmode;
+
+ cea_mode = cea_mode_for_vic(video_code);
+ if (!cea_mode)
+ return NULL;
+
+ newmode = drm_mode_duplicate(dev, cea_mode);
+ if (!newmode)
+ return NULL;
+
+ newmode->vrefresh = 0;
+
+ return newmode;
+}
+EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
+
static int
do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
{
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 89683a3a9af1..be4a5ffe4252 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -27,6 +27,8 @@
#include
#include
+struct drm_device;
+
/*
* Unless otherwise noted, all values are from the DP 1.1a spec. Note that
* DP and DPCD versions are independent. Differences from 1.0 are not noted,
@@ -384,6 +386,13 @@
# define DP_DS_PORT_TYPE_DP_DUALMODE5
# define DP_DS_PORT_TYPE_WIRELESS 6
# define DP_DS_PORT_HPD(1 << 3)
+# define DP_DS_NON_EDID_MASK (0xf << 4)
+# define DP_DS_NON_EDID_720x480i_60(1 << 4)
+# define DP_DS_NON_EDID_720x480i_50(2 << 4)
+# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
+# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
+# define DP_DS_NON_EDID_1280x720_60(5 << 4)
+# define DP_DS_NON_EDID_1280x720_50(7 << 4)
/* offset 1 for VGA is maximum megapixels per second / 8 */
/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
/* offset 2 for VGA/DVI/HDMI */
@@ -1491,6 +1500,9 @@ int drm_dp_downstream_min_tmds_clock(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4],
const struct edid *edid);
+struct drm_display_mode *drm_dp_do
[Intel-gfx] [PATCH 20/26] drm/i915: Extract intel_hdmi_has_audio()
From: Ville Syrjälä
Pull the "do we want to enable audio?" computation into a small helper
to make intel_hdmi_compute_config() less messy. Will make it easier to
add more checks for this later (eg. we should actually be checking
at the hblank is long enough for audio transmission).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 28 +++
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 5991a99c43a8..31fec0050f8d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2405,6 +2405,23 @@ static bool intel_hdmi_limited_color_range(const struct
intel_crtc_state *crtc_s
}
}
+static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+const struct drm_connector_state *conn_state)
+{
+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+ const struct intel_digital_connector_state *intel_conn_state =
+ to_intel_digital_connector_state(conn_state);
+
+ if (!crtc_state->has_hdmi_sink)
+ return false;
+
+ if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
+ return intel_hdmi->has_audio;
+ else
+ return intel_conn_state->force_audio == HDMI_AUDIO_ON;
+}
+
int intel_hdmi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -2414,8 +2431,6 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct drm_connector *connector = conn_state->connector;
struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
- struct intel_digital_connector_state *intel_conn_state =
- to_intel_digital_connector_state(conn_state);
int ret;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -2444,13 +2459,8 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
pipe_config->has_pch_encoder = true;
- if (pipe_config->has_hdmi_sink) {
- if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
- pipe_config->has_audio = intel_hdmi->has_audio;
- else
- pipe_config->has_audio =
- intel_conn_state->force_audio == HDMI_AUDIO_ON;
- }
+ pipe_config->has_audio =
+ intel_hdmi_has_audio(encoder, pipe_config, conn_state);
ret = intel_hdmi_compute_clock(encoder, pipe_config);
if (ret)
--
2.24.1
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[Intel-gfx] [PATCH 23/26] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters
From: Ville Syrjälä
For platforms that can't do native 4:2:0 outout we may still be
able to do it by getting the DP->HDMI protocol converter to
perform the 4:4:4->4:2:0 downsamling for us. In this case we
have to configure our hardware to output YCbCr 4:4:4, which we've
already hooked up so all we need to do is flip the switch.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 118 +++---
drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +-
drivers/gpu/drm/i915/display/intel_hdmi.h | 4 +-
4 files changed, 106 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 117fc17dae44..00471791d772 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1310,6 +1310,7 @@ struct intel_dp {
int min_tmds_clock, max_tmds_clock;
int max_dotclock;
u8 max_bpc;
+ bool ycbcr_444_to_420;
} dfp;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 639a0c2e5a40..3bf19d691fd5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1921,7 +1921,9 @@ static bool intel_dp_supports_dsc(struct intel_dp
*intel_dp,
static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
+ return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
+intel_dp->dfp.ycbcr_444_to_420);
}
static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
@@ -1955,9 +1957,10 @@ static bool intel_dp_hdmi_deep_color_possible(struct
intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state,
int bpc)
{
- bool has_hdmi_sink = intel_dp->has_hdmi_sink;
- return intel_hdmi_deep_color_possible(crtc_state, bpc, has_hdmi_sink) &&
+ return intel_hdmi_deep_color_possible(crtc_state, bpc,
+ intel_dp->has_hdmi_sink,
+ intel_dp_hdmi_ycbcr420(intel_dp,
crtc_state)) &&
intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
}
@@ -2368,11 +2371,17 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
int ret;
- if (!drm_mode_is_420_only(info, adjusted_mode) ||
- !intel_dp_get_colorimetry_status(intel_dp) ||
- !connector->ycbcr_420_allowed)
+ if (!connector->ycbcr_420_allowed)
return 0;
+ if (!drm_mode_is_420_only(info, adjusted_mode))
+ return 0;
+
+ if (intel_dp->dfp.ycbcr_444_to_420) {
+ crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
+ return 0;
+ }
+
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
/* YCBCR 420 output conversion needs a scaler */
@@ -3640,11 +3649,24 @@ void intel_dp_configure_protocol_converter(struct
intel_dp *intel_dp)
DP_HDMI_DVI_OUTPUT_CONFIG : 0;
if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) <= 0)
+ DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
DRM_DEBUG_KMS("Failed to set protocol converter HDMI mode to
%s\n",
enableddisabled(intel_dp->has_hdmi_sink));
- /* TODO: configure YCbCr 4:2:2/4:2:0 conversion */
+ tmp = intel_dp->dfp.ycbcr_444_to_420 ?
+ DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
+ DRM_DEBUG_KMS("Failed to set protocol converter YCbCr 4:2:0
conversion mode to %s\n",
+ enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
+
+ tmp = 0;
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0)
+ DRM_DEBUG_KMS("Failed to set protocol converter YCbCr 4:2:2
conversion mode to %s\n",
+ enableddisabled(false));
}
static void intel_enable_dp(struct intel_encoder *encoder,
@@ -5739,14 +5761,10 @@ intel_dp_get_edid(struct intel_dp *intel_dp)
}
static void
-intel_dp_set_edid(struct intel_dp *intel_dp)
+intel_dp_update_dfp(struct intel_dp *intel_dp,
+ const struct edid *edid)
{
struct intel_connector
[Intel-gfx] [PATCH 11/26] drm/dp: Pimp drm_dp_downstream_max_bpc()
From: Ville Syrjälä
Deal with more cases in drm_dp_downstream_max_bpc():
- DPCD 1.0 -> assume 8bpc for non-DP
- DPCD 1.1+ DP (or DP++ with DP sink) -> allow anything
- DPCD 1.1+ TMDS -> check the caps, assume 8bpc if the value is crap
- anything else -> assume 8bpc
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_helper.c | 65 -
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
include/drm/drm_dp_helper.h | 10 ++--
4 files changed, 52 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index bdb7ae3ce32e..7164b9d274e1 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -456,32 +456,44 @@ int drm_dp_downstream_max_clock(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
EXPORT_SYMBOL(drm_dp_downstream_max_clock);
/**
- * drm_dp_downstream_max_bpc() - extract branch device max
- * bits per component
- * @dpcd: DisplayPort configuration data
- * @port_cap: port capabilities
- *
- * Returns max bpc on success or 0 if max bpc not defined
- */
+ * drm_dp_downstream_max_bpc() - extract downstream facing port max
+ * bits per component
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: downstream facing port capabilities
+ * @edid: EDID
+ *
+ * Returns max bpc on success or 0 if max bpc not defined
+ */
int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
- const u8 port_cap[4])
+ const u8 port_cap[4],
+ const struct edid *edid)
{
- int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
- bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
- DP_DETAILED_CAP_INFO_AVAILABLE;
- int bpc;
-
- if (!detailed_cap_info)
+ if (!drm_dp_is_branch(dpcd))
return 0;
- switch (type) {
- case DP_DS_PORT_TYPE_VGA:
- case DP_DS_PORT_TYPE_DVI:
- case DP_DS_PORT_TYPE_HDMI:
+ if (dpcd[DP_DPCD_REV] < 0x11) {
+ switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DWN_STRM_PORT_TYPE_MASK) {
+ case DP_DWN_STRM_PORT_TYPE_DP:
+ return 0;
+ default:
+ return 8;
+ }
+ }
+
+ switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+ case DP_DS_PORT_TYPE_DP:
+ return 0;
case DP_DS_PORT_TYPE_DP_DUALMODE:
- bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
+ if (is_edid_digital_input_dp(edid))
+ return 0;
+ /* fall through */
+ case DP_DS_PORT_TYPE_HDMI:
+ case DP_DS_PORT_TYPE_DVI:
+ case DP_DS_PORT_TYPE_VGA:
+ if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+ return 8;
- switch (bpc) {
+ switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
case DP_DS_8BPC:
return 8;
case DP_DS_10BPC:
@@ -490,10 +502,12 @@ int drm_dp_downstream_max_bpc(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
return 12;
case DP_DS_16BPC:
return 16;
+ default:
+ return 8;
}
- /* fall through */
+ break;
default:
- return 0;
+ return 8;
}
}
EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
@@ -516,12 +530,15 @@ EXPORT_SYMBOL(drm_dp_downstream_id);
* @m: pointer for debugfs file
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
+ * @edid: EDID
* @aux: DisplayPort AUX channel
*
*/
void drm_dp_downstream_debug(struct seq_file *m,
const u8 dpcd[DP_RECEIVER_CAP_SIZE],
-const u8 port_cap[4], struct drm_dp_aux *aux)
+const u8 port_cap[4],
+const struct edid *edid,
+struct drm_dp_aux *aux)
{
bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DETAILED_CAP_INFO_AVAILABLE;
@@ -588,7 +605,7 @@ void drm_dp_downstream_debug(struct seq_file *m,
seq_printf(m, "\t\tMax TMDS clock: %d kHz\n",
clk);
}
- bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
+ bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
if (bpc > 0)
seq_printf(m, "\t\tMax bpc: %d\n", bpc);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5fab7ab97815..706750f9379e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5665,7 +5665,7 @@ i
[Intel-gfx] [PATCH 13/26] drm/i915: Reworkd DP DFP clock handling
From: Ville Syrjälä
Move the downstream facing port dotclock check into a new function
(intel_dp_mode_valid_downstream()) so that we have a nice future
place where we can collect other related checks.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 55 +--
2 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index dba0bb245a43..f978b33ea757 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1307,6 +1307,7 @@ struct intel_dp {
/* Downstream facing port caps */
struct {
+ int max_dotclock;
u8 max_bpc;
} dfp;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 22c5995e31a7..bbe5c72b5bb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -238,29 +238,6 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return max_link_clock * max_lanes;
}
-static int
-intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct intel_encoder *encoder = &intel_dig_port->base;
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- int max_dotclk = dev_priv->max_dotclk_freq;
- int ds_max_dotclk;
-
- int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
-
- if (type != DP_DS_PORT_TYPE_VGA)
- return max_dotclk;
-
- ds_max_dotclk = drm_dp_downstream_max_dotclock(intel_dp->dpcd,
-
intel_dp->downstream_ports);
-
- if (ds_max_dotclk != 0)
- max_dotclk = min(max_dotclk, ds_max_dotclk);
-
- return max_dotclk;
-}
-
static int cnl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -606,6 +583,19 @@ static bool intel_dp_hdisplay_bad(struct drm_i915_private
*dev_priv,
return hdisplay == 4096 && !HAS_DDI(dev_priv);
}
+static enum drm_mode_status
+intel_dp_mode_valid_downstream(struct intel_connector *connector,
+ int target_clock)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
+
+ if (intel_dp->dfp.max_dotclock &&
+ target_clock > intel_dp->dfp.max_dotclock)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -616,15 +606,14 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct drm_i915_private *dev_priv = to_i915(connector->dev);
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
- int max_dotclk;
+ int max_dotclk = dev_priv->max_dotclk_freq;
u16 dsc_max_output_bpp = 0;
u8 dsc_slice_count = 0;
+ enum drm_mode_status status;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
- max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
-
if (intel_dp_is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
return MODE_PANEL;
@@ -680,6 +669,10 @@ intel_dp_mode_valid(struct drm_connector *connector,
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
return MODE_H_ILLEGAL;
+ status = intel_dp_mode_valid_downstream(intel_connector, target_clock);
+ if (status != MODE_OK)
+ return status;
+
return intel_mode_valid_max_plane_size(dev_priv, mode);
}
@@ -5667,9 +5660,14 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
drm_dp_downstream_max_bpc(intel_dp->dpcd,
intel_dp->downstream_ports, edid);
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] DFP max bpc %d\n",
+ intel_dp->dfp.max_dotclock =
+ drm_dp_downstream_max_dotclock(intel_dp->dpcd,
+ intel_dp->downstream_ports);
+
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d\n",
connector->base.base.id, connector->base.name,
- intel_dp->dfp.max_bpc);
+ intel_dp->dfp.max_bpc,
+ intel_dp->dfp.max_dotclock);
if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
@@ -5692,6 +5690,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
intel_dp->has_audio = false;
intel_dp->dfp.max_bpc = 0;
+ intel_dp->dfp.max_dotclock
[Intel-gfx] [PATCH 15/26] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock()
From: Ville Syrjälä
Add helpers to get the TMDS clock limits for HDMI/DVI downstream
facing ports.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_helper.c | 116
include/drm/drm_dp_helper.h | 6 ++
2 files changed, 122 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 0ae6849744c2..31ca550467ed 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -450,6 +450,114 @@ int drm_dp_downstream_max_dotclock(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
}
EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
+/**
+ * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max
TMDS clock
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ * @edid: EDID
+ *
+ * Returns HDMI/DVI downstream facing port max TMDS clock in kHz on success,
+ * or 0 if max TMDS clock not defined
+ */
+int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+const u8 port_cap[4],
+const struct edid *edid)
+{
+ if (!drm_dp_is_branch(dpcd))
+ return 0;
+
+ if (dpcd[DP_DPCD_REV] < 0x11) {
+ switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DWN_STRM_PORT_TYPE_MASK) {
+ case DP_DWN_STRM_PORT_TYPE_TMDS:
+ return 165000;
+ default:
+ return 0;
+ }
+ }
+
+ switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+ case DP_DS_PORT_TYPE_DP_DUALMODE:
+ if (is_edid_digital_input_dp(edid))
+ return 0;
+ /*
+* It's left up to the driver to check the
+* DP dual mode adapter's max TMDS clock.
+*
+* Unfortunatley it looks like branch devices
+* may not fordward that the DP dual mode i2c
+* access so we just usually get i2c nak :(
+*/
+ /* fall through */
+ case DP_DS_PORT_TYPE_HDMI:
+/*
+ * We should perhaps assume 165 MHz when detailed cap
+ * info is not available. But looks like many typical
+ * branch devices fall into that category and so we'd
+ * probably end up with users complaining that they can't
+ * get high resolution modes with their favorite dongle.
+ *
+ * So let's limit to 300 MHz instead since DPCD 1.4
+ * HDMI 2.0 DFPs are required to have the detailed cap
+ * info. So it's more likely we're dealing with a HDMI 1.4
+ * compatible* device here.
+ */
+ if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+ return 30;
+ return port_cap[1] * 2500;
+ case DP_DS_PORT_TYPE_DVI:
+ if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+ return 165000;
+ /* FIXME what to do about DVI dual link? */
+ return port_cap[1] * 2500;
+ default:
+ return 0;
+ }
+}
+EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
+
+/**
+ * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min
TMDS clock
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ * @edid: EDID
+ *
+ * Returns HDMI/DVI downstream facing port min TMDS clock in kHz on success,
+ * or 0 if max TMDS clock not defined
+ */
+int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+const u8 port_cap[4],
+const struct edid *edid)
+{
+ if (!drm_dp_is_branch(dpcd))
+ return 0;
+
+ if (dpcd[DP_DPCD_REV] < 0x11) {
+ switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DWN_STRM_PORT_TYPE_MASK) {
+ case DP_DWN_STRM_PORT_TYPE_TMDS:
+ return 25000;
+ default:
+ return 0;
+ }
+ }
+
+ switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+ case DP_DS_PORT_TYPE_DP_DUALMODE:
+ if (is_edid_digital_input_dp(edid))
+ return 0;
+ /* fall through */
+ case DP_DS_PORT_TYPE_DVI:
+ case DP_DS_PORT_TYPE_HDMI:
+ /*
+* Unclear whether the protocol converter could
+* utilize pixel replication. Assume it won't.
+*/
+ return 25000;
+ default:
+ return 0;
+ }
+}
+EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
+
/**
* drm_dp_downstream_max_bpc() - extract downstream facing port max
* bits per component
@@ -595,6 +703,14 @@ void drm_dp_downstre
[Intel-gfx] [PATCH 14/26] drm/i915: Dump downstream facing port caps
From: Ville Syrjälä
It helps when the logs have a dump of the DFP capabilities.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index bbe5c72b5bb3..a0b611e8b370 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4528,6 +4528,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
DP_MAX_DOWNSTREAM_PORTS) < 0)
return false; /* downstream port status fetch failed */
+ DRM_DEBUG_KMS("DPCD DFP: %*ph\n",
(int)sizeof(intel_dp->downstream_ports),
+ intel_dp->downstream_ports);
+
return true;
}
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/26] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock()
From: Ville Syrjälä
We want to differentiate between the DFP dotclock and TMDS clock
limits. Let's convert the current thing to just give us the
dotclock limit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_helper.c | 42 ++---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +--
include/drm/drm_dp_helper.h | 4 +--
3 files changed, 20 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 7164b9d274e1..0ae6849744c2 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -423,37 +423,32 @@ bool drm_dp_downstream_is_tmds(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
/**
- * drm_dp_downstream_max_clock() - extract branch device max
- * pixel rate for legacy VGA
- * converter or max TMDS clock
- * rate for others
+ * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot
clock
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
*
- * Returns max clock in kHz on success or 0 if max clock not defined
+ * Returns downstream facing port max dot clock in kHz on success,
+ * or 0 if max clock not defined
*/
-int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
- const u8 port_cap[4])
+int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4])
{
- int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
- bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
- DP_DETAILED_CAP_INFO_AVAILABLE;
+ if (!drm_dp_is_branch(dpcd))
+ return 0;
- if (!detailed_cap_info)
+ if (dpcd[DP_DPCD_REV] < 0x11)
return 0;
- switch (type) {
+ switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
case DP_DS_PORT_TYPE_VGA:
- return port_cap[1] * 8 * 1000;
- case DP_DS_PORT_TYPE_DVI:
- case DP_DS_PORT_TYPE_HDMI:
- case DP_DS_PORT_TYPE_DP_DUALMODE:
- return port_cap[1] * 2500;
+ if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+ return 0;
+ return port_cap[1] * 8000;
default:
return 0;
}
}
-EXPORT_SYMBOL(drm_dp_downstream_max_clock);
+EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
/**
* drm_dp_downstream_max_bpc() - extract downstream facing port max
@@ -596,14 +591,9 @@ void drm_dp_downstream_debug(struct seq_file *m,
seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
if (detailed_cap_info) {
- clk = drm_dp_downstream_max_clock(dpcd, port_cap);
-
- if (clk > 0) {
- if (type == DP_DS_PORT_TYPE_VGA)
- seq_printf(m, "\t\tMax dot clock: %d kHz\n",
clk);
- else
- seq_printf(m, "\t\tMax TMDS clock: %d kHz\n",
clk);
- }
+ clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
+ if (clk > 0)
+ seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 706750f9379e..22c5995e31a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -252,8 +252,8 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
if (type != DP_DS_PORT_TYPE_VGA)
return max_dotclk;
- ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
- intel_dp->downstream_ports);
+ ds_max_dotclk = drm_dp_downstream_max_dotclock(intel_dp->dpcd,
+
intel_dp->downstream_ports);
if (ds_max_dotclk != 0)
max_dotclk = min(max_dotclk, ds_max_dotclk);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 62637acaefee..39c1faf7dede 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1480,8 +1480,8 @@ bool drm_dp_downstream_is_type(const u8
dpcd[DP_RECEIVER_CAP_SIZE],
bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4],
const struct edid *edid);
-int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
- const u8 port_cap[4]);
+int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4]);
int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
[Intel-gfx] [PATCH 06/26] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks
From: Ville Syrjälä
Non-HDMI sinks shouldn't be sent infoframes. Check for that when
using LSPCON.
FIXME: How do we turn off infoframes once enabled? Do we even
have to?
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 --
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c| 7 ++-
3 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index aa066fb9eb00..818bee4918fa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3658,18 +3658,16 @@ static void intel_ddi_pre_enable(struct intel_encoder
*encoder,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
} else {
- struct intel_lspcon *lspcon =
- enc_to_intel_lspcon(encoder);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
- if (lspcon->active) {
- struct intel_digital_port *dig_port =
- enc_to_dig_port(encoder);
+ /* FIXME precompute everything properly */
+ /* FIXME how do we turn infoframes off again? */
+ if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
dig_port->set_infoframes(encoder,
crtc_state->has_infoframe,
crtc_state, conn_state);
- }
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7c6133a9c51b..5774240c0996 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1207,6 +1207,7 @@ struct intel_dp {
u8 sink_count;
bool link_mst;
bool link_trained;
+ bool has_hdmi_sink;
bool has_audio;
bool reset_link_params;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..1786e6e8ffe3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5664,7 +5664,11 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
edid = intel_dp_get_edid(intel_dp);
intel_connector->detect_edid = edid;
- intel_dp->has_audio = drm_detect_monitor_audio(edid);
+ if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
+ intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
+ intel_dp->has_audio = drm_detect_monitor_audio(edid);
+ }
+
drm_dp_cec_set_edid(&intel_dp->aux, edid);
}
@@ -5677,6 +5681,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
kfree(intel_connector->detect_edid);
intel_connector->detect_edid = NULL;
+ intel_dp->has_hdmi_sink = false;
intel_dp->has_audio = false;
}
--
2.24.1
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[Intel-gfx] [PATCH 07/26] drm/dp: Define protocol converter DPCD registers
From: Ville Syrjälä DP 1.3 and 1.4 introduced some new registers for DP->HDMI protocol converters. Define those. Signed-off-by: Ville Syrjälä --- include/drm/drm_dp_helper.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 262faf9e5e94..faf05cda5043 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -974,6 +974,16 @@ #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 +#define DP_PROTOCOL_CONVERTER_CONTROL_00x3050 /* DP 1.3 */ +# define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */ +#define DP_PROTOCOL_CONVERTER_CONTROL_10x3051 /* DP 1.3 */ +# define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */ +# define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */ +# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */ +# define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */ +#define DP_PROTOCOL_CONVERTER_CONTROL_20x3052 /* DP 1.3 */ +# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */ + #define DP_AUX_HDCP_BKSV 0x68000 #define DP_AUX_HDCP_RI_PRIME 0x68005 #define DP_AUX_HDCP_AKSV 0x68007 -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/26] drm/dp: Add helpers to identify downstream facing port types
From: Ville Syrjälä
Add a few helpers to let us better identify which kind of DFP
we're dealing with.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_helper.c | 60 +
include/drm/drm_dp_helper.h | 5 +++
2 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f8cedbc3da5d..bdb7ae3ce32e 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -362,6 +362,66 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
}
EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
+static bool is_edid_digital_input_dp(const struct edid *edid)
+{
+ return edid && edid->revision >= 4 &&
+ edid->input & DRM_EDID_INPUT_DIGITAL &&
+ (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) ==
DRM_EDID_DIGITAL_TYPE_DP;
+}
+
+/**
+ * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ *
+ * Caveat: Only works with DPCD 1.1+ port caps.
+ *
+ * Returns whether the downstream facing port matches the type.
+ */
+bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4], u8 type)
+{
+ return drm_dp_is_branch(dpcd) &&
+ dpcd[DP_DPCD_REV] >= 0x11 &&
+ (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
+}
+EXPORT_SYMBOL(drm_dp_downstream_is_type);
+
+/**
+ * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
+ * @dpcd: DisplayPort configuration data
+ * @port_cap: port capabilities
+ * @edid: EDID
+ *
+ * Returns whether the downstream facing port is TMDS (HDMI/DVI).
+ */
+bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4],
+ const struct edid *edid)
+{
+ if (dpcd[DP_DPCD_REV] < 0x11) {
+ switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DWN_STRM_PORT_TYPE_MASK) {
+ case DP_DWN_STRM_PORT_TYPE_TMDS:
+ return true;
+ default:
+ return false;
+ }
+ }
+
+ switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
+ case DP_DS_PORT_TYPE_DP_DUALMODE:
+ if (is_edid_digital_input_dp(edid))
+ return false;
+ /* fall through */
+ case DP_DS_PORT_TYPE_DVI:
+ case DP_DS_PORT_TYPE_HDMI:
+ return true;
+ default:
+ return false;
+ }
+}
+EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
+
/**
* drm_dp_downstream_max_clock() - extract branch device max
* pixel rate for legacy VGA
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 2ffa47f875fa..958db298adc7 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1475,6 +1475,11 @@ static inline ssize_t drm_dp_dpcd_writeb(struct
drm_dp_aux *aux,
int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
u8 status[DP_LINK_STATUS_SIZE]);
+bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4], u8 type);
+bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+ const u8 port_cap[4],
+ const struct edid *edid);
int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]);
int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
--
2.24.1
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[Intel-gfx] [PATCH 04/26] drm/i915: Add glk to intel_detect_preproduction_hw()
From: Ville Syrjälä
Detect GLK pre-production steppings. Not 100% of A2 being pre-prod
since the spec is a bit of a mess but feels more or less correct.
Suggested-by: Chris Wilson
Acked-by: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4661c5f1f297..73d259d99554 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -438,6 +438,7 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
+ pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
if (pre) {
DRM_ERROR("This is a pre-production stepping. "
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a71ff233cc55..9df900f9307f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1562,6 +1562,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define GLK_REVID_A0 0x0
#define GLK_REVID_A1 0x1
+#define GLK_REVID_A2 0x2
+#define GLK_REVID_B0 0x3
#define IS_GLK_REVID(dev_priv, since, until) \
(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
--
2.24.1
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[Intel-gfx] [PATCH 02/26] drm/i915: Limit display Wa_1405510057 to gen11
From: Ville Syrjälä TGL+ supposedly do not need Wa_1405510057 so limit it to gen11 only. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_hdmi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 9e409a819ff5..5991a99c43a8 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2274,9 +2274,9 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, } } - /* Display Wa_1405510057:icl */ + /* Display Wa_1405510057:icl,ehl */ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && - bpc == 10 && INTEL_GEN(dev_priv) >= 11 && + bpc == 10 && IS_GEN(dev_priv, 11) && (adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start) % 8 == 2) return false; -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/26] drm/dp: Define more downstream facing port caps
From: Ville Syrjälä Our definitions for the DPCD DFP capabilities are lacking. Add the missing bits. Signed-off-by: Ville Syrjälä --- include/drm/drm_dp_helper.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index faf05cda5043..2ffa47f875fa 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -385,12 +385,18 @@ # define DP_DS_PORT_TYPE_WIRELESS 6 # define DP_DS_PORT_HPD(1 << 3) /* offset 1 for VGA is maximum megapixels per second / 8 */ -/* offset 2 */ +/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */ +/* offset 2 for VGA/DVI/HDMI */ # define DP_DS_MAX_BPC_MASK(3 << 0) # define DP_DS_8BPC0 # define DP_DS_10BPC 1 # define DP_DS_12BPC 2 # define DP_DS_16BPC 3 +/* offset 3 for DVI */ +# define DP_DS_DVI_DUAL_LINK (1 << 1) +# define DP_DS_DVI_HIGH_COLOR_DEPTH(1 << 2) +/* offset 3 for HDMI */ +# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0) #define DP_MAX_DOWNSTREAM_PORTS0x10 -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/26] drm/dp: Include the AUX CH name in the debug messages
From: Ville Syrjälä
To make it easier to figure out what caused a particular debug
message let's print out aux->name.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_helper.c | 44 +++--
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5a103e9b3c86..f8cedbc3da5d 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -257,7 +257,8 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8
request,
err = ret;
}
- DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err);
+ DRM_DEBUG_KMS("%s: Too many retries, giving up. First error: %d\n",
+ aux->name, err);
ret = err;
unlock:
@@ -678,10 +679,11 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg)
* Avoid spamming the kernel log with timeout errors.
*/
if (ret == -ETIMEDOUT)
- DRM_DEBUG_KMS_RATELIMITED("transaction timed
out\n");
+ DRM_DEBUG_KMS_RATELIMITED("%s: transaction
timed out\n",
+ aux->name);
else
- DRM_DEBUG_KMS("transaction failed: %d\n", ret);
-
+ DRM_DEBUG_KMS("%s: transaction failed: %d\n",
+ aux->name, ret);
return ret;
}
@@ -695,11 +697,12 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg)
break;
case DP_AUX_NATIVE_REPLY_NACK:
- DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n",
ret, msg->size);
+ DRM_DEBUG_KMS("%s: native nack (result=%d, size=%zu)\n",
+ aux->name, ret, msg->size);
return -EREMOTEIO;
case DP_AUX_NATIVE_REPLY_DEFER:
- DRM_DEBUG_KMS("native defer\n");
+ DRM_DEBUG_KMS("%s: native defer\n", aux->name);
/*
* We could check for I2C bit rate capabilities and if
* available adjust this interval. We could also be
@@ -713,7 +716,8 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
continue;
default:
- DRM_ERROR("invalid native reply %#04x\n", msg->reply);
+ DRM_ERROR("%s: invalid native reply %#04x\n",
+ aux->name, msg->reply);
return -EREMOTEIO;
}
@@ -728,13 +732,13 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg)
return ret;
case DP_AUX_I2C_REPLY_NACK:
- DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu)\n",
- ret, msg->size);
+ DRM_DEBUG_KMS("%s: I2C nack (result=%d, size=%zu)\n",
+ aux->name, ret, msg->size);
aux->i2c_nack_count++;
return -EREMOTEIO;
case DP_AUX_I2C_REPLY_DEFER:
- DRM_DEBUG_KMS("I2C defer\n");
+ DRM_DEBUG_KMS("%s: I2C defer\n", aux->name);
/* DP Compliance Test 4.2.2.5 Requirement:
* Must have at least 7 retries for I2C defers on the
* transaction to pass this test
@@ -748,12 +752,13 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg)
continue;
default:
- DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
+ DRM_ERROR("%s: invalid I2C reply %#04x\n",
+ aux->name, msg->reply);
return -EREMOTEIO;
}
}
- DRM_DEBUG_KMS("too many retries, giving up\n");
+ DRM_DEBUG_KMS("%s: Too many retries, giving up\n", aux->name);
return -EREMOTEIO;
}
@@ -782,8 +787,8 @@ static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *o
return err == 0 ? -EPROTO : err;
if (err < msg.size && err < ret) {
- DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes
got %d bytes\n",
- msg.size, err);
+ DRM_DEBUG_KMS("%s: Partial I2C reply: requested %zu
bytes got %d bytes\n",
+ aux->name, msg.size, err);
ret = err;
[Intel-gfx] [PATCH 03/26] drm/i915: Drop WaDDIIOTimeout:glk
From: Ville Syrjälä
WaDDIIOTimeout is only for A1 (pre-prod) glk steppings. Nuke it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a2d2407af2ed..cf373eb6c694 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -128,16 +128,6 @@ static void glk_init_clock_gating(struct drm_i915_private
*dev_priv)
*/
I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
PWM1_GATING_DIS | PWM2_GATING_DIS);
-
- /* WaDDIIOTimeout:glk */
- if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
- u32 val = I915_READ(CHICKEN_MISC_2);
- val &= ~(GLK_CL0_PWR_DOWN |
-GLK_CL1_PWR_DOWN |
-GLK_CL2_PWR_DOWN);
- I915_WRITE(CHICKEN_MISC_2, val);
- }
-
}
static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
--
2.24.1
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[Intel-gfx] [PATCH 00/26] drm/i915: Pimp DP DFP handling
From: Ville Syrjälä
Attempt to deal with DP downstream facing ports (DFP) more
thoroughly. This involves reading more of the port caps
and dealing with various clock/bpc limitations.
Also we try to hook up the DP dual mode dongles into the
mix (unfortunately I've not yet seen a DP++ DFP that would
pass the dual mode adapter register i2c accesses through).
And we try to enable YCbCr 444->420 conversion for HDMI DFPs
which could allow some 4k displays to actually use 4k on
pre-icl hardware (which doesn't have native 420 output),
assuming we don't run into some other hardware limits.
It's a bit on the large side but since it looks like other
people are poking around the same area I figured I'd post
the entire thing.
Entire series available here:
git://github.com/vsyrjala/linux.git dp_downstream_ports_5
Ville Syrjälä (26):
drm/i915: Nuke pre-production GLK HDMI w/a 1139
drm/i915: Limit display Wa_1405510057 to gen11
drm/i915: Drop WaDDIIOTimeout:glk
drm/i915: Add glk to intel_detect_preproduction_hw()
drm/dp: Include the AUX CH name in the debug messages
drm/i915/lspcon: Do not send infoframes to non-HDMI sinks
drm/dp: Define protocol converter DPCD registers
drm/dp: Define more downstream facing port caps
drm/i915: Reworkd DFP max bpc handling
drm/dp: Add helpers to identify downstream facing port types
drm/dp: Pimp drm_dp_downstream_max_bpc()
drm/dp: Redo drm_dp_downstream_max_clock() as
drm_dp_downstream_max_dotclock()
drm/i915: Reworkd DP DFP clock handling
drm/i915: Dump downstream facing port caps
drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock()
drm/i915: Deal with TMDS DFP clock limits
drm/i915: Configure DP 1.3+ protocol converted HDMI mode
drm/dp: Add drm_dp_downstream_mode()
drm/i915: Handle downstream facing ports w/o EDID
drm/i915: Extract intel_hdmi_has_audio()
drm/i915: DP->HDMI TMDS clock limits vs. deep color
drm/dp: Add helpers for DFP YCbCr 4:2:0 handling
drm/i915: Do YCbCr 444->420 conversion via DP protocol converters
drm/i915: Decouple DP++ from the HDMI code
drm/i915: Try to probe DP++ dongles on DP++ downstream facing ports
drm/i915: Try to frob the TMDS buffer enable knob on DP++ dongles on
DP DFPs
drivers/gpu/drm/drm_dp_helper.c | 409 +++---
drivers/gpu/drm/drm_edid.c| 21 +
drivers/gpu/drm/i915/display/intel_ddi.c | 23 +-
.../drm/i915/display/intel_display_types.h| 22 +-
drivers/gpu/drm/i915/display/intel_dp.c | 367 ++--
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 181
drivers/gpu/drm/i915/display/intel_hdmi.h | 11 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 10 -
include/drm/drm_dp_helper.h | 63 ++-
include/drm/drm_edid.h| 4 +
14 files changed, 904 insertions(+), 215 deletions(-)
--
2.24.1
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