[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Add mechanism to submit a
context WA on ring submission
URL : https://patchwork.freedesktop.org/series/74363/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c0358b495597 drm/i915: Add mechanism to submit a context WA on ring submission
-:262: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#262:
new file mode 100644
-:373: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#373: FILE: drivers/gpu/drm/i915/gt/selftest_ring_submission.c:107:
+ pr_err("pass[%d] wa_bb emitted for the kernel
context\n",
+ pass);
-:384: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#384: FILE: drivers/gpu/drm/i915/gt/selftest_ring_submission.c:118:
+ pr_err("pass[%d] wa_bb *NOT* emitted after the
kernel context\n",
+ pass);
-:395: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#395: FILE: drivers/gpu/drm/i915/gt/selftest_ring_submission.c:129:
+ pr_err("pass[%d] wa_bb *NOT* emitted for the
user context switch\n",
+ pass);
total: 0 errors, 1 warnings, 3 checks, 504 lines checked
1283df1a1750 drm/i915/gen7: Clear all EU/L3 residual contexts
-:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#46:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 585 lines checked
___
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[Intel-gfx] [PATCH 3/3] drm/i915/gem: Limit struct_mutex to eb_reserve
We only need to serialise the multiple pinning during the eb_reserve
phase. Ideally this would be using the vm->mutex as an outer lock, or
using a composite global mutex (ww_mutex), but at the moment we are
using struct_mutex for the group.
Fixes: 003d8b9143a6 ("drm/i915/gem: Only call eb_lookup_vma once during execbuf
ioctl")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 51 ---
drivers/gpu/drm/i915/i915_drv.h | 6 ---
2 files changed, 20 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 7bb27f382af7..faa5b5c99a9a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -610,7 +610,7 @@ static int eb_reserve(struct i915_execbuffer *eb)
struct list_head last;
struct eb_vma *ev;
unsigned int i, pass;
- int err;
+ int err = 0;
/*
* Attempt to pin all of the buffers into the GTT.
@@ -626,8 +626,10 @@ static int eb_reserve(struct i915_execbuffer *eb)
* room for the earlier objects *unless* we need to defragment.
*/
+ if (mutex_lock_interruptible(>i915->drm.struct_mutex))
+ return -EINTR;
+
pass = 0;
- err = 0;
do {
list_for_each_entry(ev, >unbound, bind_link) {
err = eb_reserve_vma(eb, ev, pin_flags);
@@ -635,7 +637,7 @@ static int eb_reserve(struct i915_execbuffer *eb)
break;
}
if (!(err == -ENOSPC || err == -EAGAIN))
- return err;
+ break;
/* Resort *all* the objects into priority order */
INIT_LIST_HEAD(>unbound);
@@ -666,7 +668,9 @@ static int eb_reserve(struct i915_execbuffer *eb)
list_splice_tail(, >unbound);
if (err == -EAGAIN) {
+ mutex_unlock(>i915->drm.struct_mutex);
flush_workqueue(eb->i915->mm.userptr_wq);
+ mutex_lock(>i915->drm.struct_mutex);
continue;
}
@@ -680,15 +684,20 @@ static int eb_reserve(struct i915_execbuffer *eb)
err = i915_gem_evict_vm(eb->context->vm);
mutex_unlock(>context->vm->mutex);
if (err)
- return err;
+ goto unlock;
break;
default:
- return -ENOSPC;
+ err = -ENOSPC;
+ goto unlock;
}
pin_flags = PIN_USER;
} while (1);
+
+unlock:
+ mutex_unlock(>i915->drm.struct_mutex);
+ return err;
}
static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
@@ -1631,7 +1640,6 @@ static int eb_prefault_relocations(const struct
i915_execbuffer *eb)
static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
{
- struct drm_device *dev = >i915->drm;
bool have_copy = false;
struct eb_vma *ev;
int err = 0;
@@ -1642,8 +1650,6 @@ static noinline int eb_relocate_slow(struct
i915_execbuffer *eb)
goto out;
}
- mutex_unlock(>struct_mutex);
-
/*
* We take 3 passes through the slowpatch.
*
@@ -1666,21 +1672,8 @@ static noinline int eb_relocate_slow(struct
i915_execbuffer *eb)
cond_resched();
err = 0;
}
- if (err) {
- mutex_lock(>struct_mutex);
- goto out;
- }
-
- /* A frequent cause for EAGAIN are currently unavailable client pages */
- flush_workqueue(eb->i915->mm.userptr_wq);
-
- err = i915_mutex_lock_interruptible(dev);
- if (err) {
- mutex_lock(>struct_mutex);
+ if (err)
goto out;
- }
-
- GEM_BUG_ON(!eb->batch);
list_for_each_entry(ev, >relocs, reloc_link) {
if (!have_copy) {
@@ -1738,9 +1731,11 @@ static int eb_relocate(struct i915_execbuffer *eb)
if (err)
return err;
- err = eb_reserve(eb);
- if (err)
- return err;
+ if (!list_empty(>unbound)) {
+ err = eb_reserve(eb);
+ if (err)
+ return err;
+ }
/* The objects are in their final locations, apply the relocations. */
if (eb->args->flags & __EXEC_HAS_RELOC) {
@@ -2690,10 +2685,6 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_context;
- err = i915_mutex_lock_interruptible(dev);
- if (err)
- goto err_engine;
-
err = eb_relocate();
if (err) {
/*
@@ -2837,8
[Intel-gfx] [PATCH 2/3] drm/i915: Always propagate the invocation to i915_schedule
We only call i915_schedule() when we know we have changed the priority
on a request and so require to propagate any change in priority to its
signalers (for PI). By unconditionally checking all of our signalers, we
avoid skipping changes made prior to construction of the request (as the
request may be waited upon before submission when used in parallel).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_scheduler.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index be770f2419b1..52f71e83e088 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -227,10 +227,10 @@ static void kick_submission(struct intel_engine_cs
*engine,
static void __i915_schedule(struct i915_sched_node *node,
const struct i915_sched_attr *attr)
{
+ const int prio = max(attr->priority, node->attr.priority);
struct intel_engine_cs *engine;
struct i915_dependency *dep, *p;
struct i915_dependency stack;
- const int prio = attr->priority;
struct sched_cache cache;
LIST_HEAD(dfs);
@@ -238,9 +238,6 @@ static void __i915_schedule(struct i915_sched_node *node,
lockdep_assert_held(_lock);
GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
- if (prio <= READ_ONCE(node->attr.priority))
- return;
-
if (node_signaled(node))
return;
--
2.25.1
___
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[Intel-gfx] [PATCH 1/3] drm/i915: Assert requests within a context are submitted in order
Check the flow of requests into the hardware to verify that are
submitted in order along their timeline.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4
drivers/gpu/drm/i915/i915_request.c | 4
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 16a023ac4604..13941d1c0a4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1622,6 +1622,7 @@ static bool can_merge_rq(const struct i915_request *prev,
if (!can_merge_ctx(prev->context, next->context))
return false;
+ GEM_BUG_ON(i915_seqno_passed(prev->fence.seqno, next->fence.seqno));
return true;
}
@@ -2142,6 +2143,9 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
GEM_BUG_ON(last &&
!can_merge_ctx(last->context,
rq->context));
+ GEM_BUG_ON(last &&
+ i915_seqno_passed(last->fence.seqno,
+rq->fence.seqno));
submit = true;
last = rq;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index ca5361eb1f0b..35147df79655 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -737,6 +737,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
RCU_INIT_POINTER(rq->timeline, tl);
RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
rq->hwsp_seqno = tl->hwsp_seqno;
+ GEM_BUG_ON(i915_request_completed(rq));
rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
@@ -1284,6 +1285,9 @@ __i915_request_add_to_timeline(struct i915_request *rq)
prev = to_request(__i915_active_fence_set(>last_request,
>fence));
if (prev && !i915_request_completed(prev)) {
+ GEM_BUG_ON(i915_seqno_passed(prev->fence.seqno,
+rq->fence.seqno));
+
if (is_power_of_2(prev->engine->mask | rq->engine->mask))
i915_sw_fence_await_sw_fence(>submit,
>submit,
--
2.25.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: allow setting generic data pointer
== Series Details == Series: drm/i915/gt: allow setting generic data pointer URL : https://patchwork.freedesktop.org/series/74360/ State : success == Summary == CI Bug Log - changes from CI_DRM_8074 -> Patchwork_16852 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16852/index.html Known issues Here are the changes found in Patchwork_16852 that come from known issues: ### IGT changes ### Issues hit * igt@kms_addfb_basic@bad-pitch-999: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([CI#94] / [i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-999.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16852/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-999.html Possible fixes * igt@prime_vgem@basic-gtt: - fi-tgl-y: [DMESG-WARN][3] ([CI#94] / [i915#402]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-tgl-y/igt@prime_v...@basic-gtt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16852/fi-tgl-y/igt@prime_v...@basic-gtt.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (50 -> 43) -- Additional (1): fi-kbl-7560u Missing(8): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-gdg-551 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8074 -> Patchwork_16852 CI-20190529: 20190529 CI_DRM_8074: 0dd63259839ca847514d749219635f311015 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16852: b5c27a068592cbdb2b4abf4e73ee5e305e3e227d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b5c27a068592 drm/i915/gt: allow setting generic data pointer == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16852/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gt: allow setting generic data pointer
== Series Details == Series: drm/i915/gt: allow setting generic data pointer URL : https://patchwork.freedesktop.org/series/74360/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/buddy: avoid double list_add
== Series Details == Series: series starting with [1/2] drm/i915/buddy: avoid double list_add URL : https://patchwork.freedesktop.org/series/74355/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8074 -> Patchwork_16850 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16850 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16850, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16850/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16850: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gem: - fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-bsw-kefka/igt@i915_selftest@l...@gem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16850/fi-bsw-kefka/igt@i915_selftest@l...@gem.html Warnings * igt@amdgpu/amd_prime@amd-to-i915: - fi-icl-y: [SKIP][3] ([fdo#109315]) -> [SKIP][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-icl-y/igt@amdgpu/amd_pr...@amd-to-i915.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16850/fi-icl-y/igt@amdgpu/amd_pr...@amd-to-i915.html Known issues Here are the changes found in Patchwork_16850 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-skl-6600u: [PASS][5] -> [INCOMPLETE][6] ([i915#69]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16850/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html * igt@gem_render_linear_blits@basic: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-tgl-y/igt@gem_render_linear_bl...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16850/fi-tgl-y/igt@gem_render_linear_bl...@basic.html * igt@i915_selftest@live@execlists: - fi-icl-y: [PASS][9] -> [INCOMPLETE][10] ([i915#140]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-icl-y/igt@i915_selftest@l...@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16850/fi-icl-y/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gem_contexts: - fi-cml-s: [PASS][11] -> [DMESG-FAIL][12] ([i915#877]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-cml-s/igt@i915_selftest@live@gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16850/fi-cml-s/igt@i915_selftest@live@gem_contexts.html Possible fixes * igt@prime_vgem@basic-gtt: - fi-tgl-y: [DMESG-WARN][13] ([CI#94] / [i915#402]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-tgl-y/igt@prime_v...@basic-gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16850/fi-tgl-y/igt@prime_v...@basic-gtt.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 Participating hosts (50 -> 43) -- Additional (1): fi-kbl-7560u Missing(8): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-ivb-3770 fi-skl-lmem fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8074 -> Patchwork_16850 CI-20190529: 20190529 CI_DRM_8074: 0dd63259839ca847514d749219635f311015 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16850: 362c612df08473f377fa496f1767bcaf4d186c58 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 362c612df084 drm/i915/selftests: try to rein in alloc_smoke e89ba2d291ff drm/i915/buddy: avoid double list_add == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16850/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: allow setting generic data pointer
== Series Details == Series: drm/i915/gt: allow setting generic data pointer URL : https://patchwork.freedesktop.org/series/74360/ State : warning == Summary == $ dim checkpatch origin/drm-tip b5c27a068592 drm/i915/gt: allow setting generic data pointer -:72: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_g' - possible side-effects? #72: FILE: drivers/gpu/drm/i915/gt/debugfs_gt.h:38: +#define intel_gt_debugfs_register_file(_g, _r, _f, _c) \ + __intel_gt_debugfs_register_files(_g, _r, _f, _c, _g) total: 0 errors, 0 warnings, 1 checks, 46 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for i915/gem_exec_params: add test_invalid_batch
== Series Details == Series: i915/gem_exec_params: add test_invalid_batch URL : https://patchwork.freedesktop.org/series/74356/ State : failure == Summary == Applying: i915/gem_exec_params: add test_invalid_batch error: sha1 information is lacking or useless (tests/i915/gem_exec_params.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 i915/gem_exec_params: add test_invalid_batch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/buddy: avoid double list_add
== Series Details == Series: series starting with [1/2] drm/i915/buddy: avoid double list_add URL : https://patchwork.freedesktop.org/series/74355/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/phys: unconditionally call release_memory_region
== Series Details == Series: drm/i915/phys: unconditionally call release_memory_region URL : https://patchwork.freedesktop.org/series/74354/ State : success == Summary == CI Bug Log - changes from CI_DRM_8074 -> Patchwork_16849 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16849/index.html Known issues Here are the changes found in Patchwork_16849 that come from known issues: ### IGT changes ### Issues hit * igt@kms_addfb_basic@bad-pitch-128: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([CI#94] / [i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16849/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html * igt@kms_flip@basic-flip-vs-wf_vblank: - fi-kbl-soraka: [PASS][3] -> [FAIL][4] ([i915#34]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-kbl-soraka/igt@kms_flip@basic-flip-vs-wf_vblank.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16849/fi-kbl-soraka/igt@kms_flip@basic-flip-vs-wf_vblank.html Possible fixes * igt@prime_vgem@basic-gtt: - fi-tgl-y: [DMESG-WARN][5] ([CI#94] / [i915#402]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-tgl-y/igt@prime_v...@basic-gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16849/fi-tgl-y/igt@prime_v...@basic-gtt.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (50 -> 43) -- Additional (1): fi-kbl-7560u Missing(8): fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8074 -> Patchwork_16849 CI-20190529: 20190529 CI_DRM_8074: 0dd63259839ca847514d749219635f311015 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16849: c2288814c4892b49c27aa4250ce0e6a483d04077 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c2288814c489 drm/i915/phys: unconditionally call release_memory_region == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16849/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/phys: unconditionally call release_memory_region
== Series Details == Series: drm/i915/phys: unconditionally call release_memory_region URL : https://patchwork.freedesktop.org/series/74354/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: be more solid in checking the alignment
== Series Details == Series: drm/i915: be more solid in checking the alignment URL : https://patchwork.freedesktop.org/series/74353/ State : success == Summary == CI Bug Log - changes from CI_DRM_8074 -> Patchwork_16848 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16848/index.html Known issues Here are the changes found in Patchwork_16848 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#109635] / [i915#262]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16848/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-edid-read: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#217]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16848/fi-icl-u2/igt@kms_chamel...@hdmi-edid-read.html * igt@prime_vgem@basic-read: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-tgl-y/igt@prime_v...@basic-read.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16848/fi-tgl-y/igt@prime_v...@basic-read.html Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [FAIL][7] ([CI#94]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16848/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#111096] / [i915#323]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16848/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-gtt: - fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8074/fi-tgl-y/igt@prime_v...@basic-gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16848/fi-tgl-y/igt@prime_v...@basic-gtt.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (50 -> 44) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8074 -> Patchwork_16848 CI-20190529: 20190529 CI_DRM_8074: 0dd63259839ca847514d749219635f311015 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16848: 1920f5de2ebe3c7e11b1df26dd65d45f11adbd6f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1920f5de2ebe drm/i915: be more solid in checking the alignment == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16848/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: be more solid in checking the alignment
== Series Details == Series: drm/i915: be more solid in checking the alignment URL : https://patchwork.freedesktop.org/series/74353/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: properly sanity check batch_start_offset (rev2)
== Series Details == Series: drm/i915: properly sanity check batch_start_offset (rev2) URL : https://patchwork.freedesktop.org/series/74287/ State : success == Summary == CI Bug Log - changes from CI_DRM_8073 -> Patchwork_16847 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16847/index.html Known issues Here are the changes found in Patchwork_16847 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gem_contexts: - fi-cfl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#943]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16847/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-tgl-y/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16847/fi-tgl-y/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16847/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@vgem_basic@create: - fi-tgl-y: [DMESG-WARN][7] ([CI#94] / [i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-tgl-y/igt@vgem_ba...@create.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16847/fi-tgl-y/igt@vgem_ba...@create.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#943]: https://gitlab.freedesktop.org/drm/intel/issues/943 Participating hosts (47 -> 41) -- Additional (4): fi-kbl-soraka fi-elk-e7500 fi-snb-2520m fi-skl-6600u Missing(10): fi-hsw-4200u fi-hsw-peppy fi-skl-6770hq fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-skl-lmem fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8073 -> Patchwork_16847 CI-20190529: 20190529 CI_DRM_8073: 04042aee59126471bb37cec526ccaf44b4e8d506 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16847: 5aaff43297e17fe8352c34908a197798c8d66949 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5aaff43297e1 drm/i915: properly sanity check batch_start_offset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16847/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: properly sanity check batch_start_offset (rev2)
== Series Details == Series: drm/i915: properly sanity check batch_start_offset (rev2) URL : https://patchwork.freedesktop.org/series/74287/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Add support for integrated privacy screens
Hi Jani,
Thank you for the comments. Please see my responses inline.
On Thu, Mar 5, 2020 at 2:02 AM Jani Nikula wrote:
>
> On Wed, 04 Mar 2020, Rajat Jain wrote:
> > Certain laptops now come with panels that have integrated privacy
> > screens on them. This patch adds support for such panels by adding
> > a privacy-screen property to the intel_connector for the panel, that
> > the userspace can then use to control and check the status.
> >
> > Identifying the presence of privacy screen, and controlling it, is done
> > via ACPI _DSM methods.
> >
> > Currently, this is done only for the Intel display ports. But in future,
> > this can be done for any other ports if the hardware becomes available
> > (e.g. external monitors supporting integrated privacy screens?).
>
> I think you should add the property at the drm core level in
> drm_connector.c, not in i915, to ensure we have the same property across
> drivers. Even if, for now, you leave the acpi implementation part in
> i915.
OK, will do. In order to do that I may need to introduce driver level
hooks that i915 driver can populate and drm core can call (or may be
some functions to add privacy screen property that drm core exports
and i915 driver will call).
>
> More comments inline.
>
> >
> > Signed-off-by: Rajat Jain
> > ---
> > v6: Always initialize prop in intel_attach_privacy_screen_property()
> > v5: fix a cosmetic checkpatch warning
> > v4: Fix a typo in intel_privacy_screen.h
> > v3: * Change license to GPL-2.0 OR MIT
> > * Move privacy screen enum from UAPI to intel_display_types.h
> > * Rename parameter name and some other minor changes.
> > v2: Formed by splitting the original patch into multiple patches.
> > - All code has been moved into i915 now.
> > - Privacy screen is a i915 property
> > - Have a local state variable to store the prvacy screen. Don't read
> > it from hardware.
> >
> > drivers/gpu/drm/i915/Makefile | 3 +-
> > drivers/gpu/drm/i915/display/intel_atomic.c | 13 +++-
> > .../gpu/drm/i915/display/intel_connector.c| 35 +
> > .../gpu/drm/i915/display/intel_connector.h| 1 +
> > .../drm/i915/display/intel_display_types.h| 18 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
> > .../drm/i915/display/intel_privacy_screen.c | 72 +++
> > .../drm/i915/display/intel_privacy_screen.h | 27 +++
> > 8 files changed, 171 insertions(+), 4 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/display/intel_privacy_screen.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_privacy_screen.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 991a8c537d123..825951b4cd006 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -208,7 +208,8 @@ i915-y += \
> > display/intel_vga.o
> > i915-$(CONFIG_ACPI) += \
> > display/intel_acpi.o \
> > - display/intel_opregion.o
> > + display/intel_opregion.o \
> > + display/intel_privacy_screen.o
> > i915-$(CONFIG_DRM_FBDEV_EMULATION) += \
> > display/intel_fbdev.o
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index d043057d2fa03..4ed537c87 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -40,6 +40,7 @@
> > #include "intel_global_state.h"
> > #include "intel_hdcp.h"
> > #include "intel_psr.h"
> > +#include "intel_privacy_screen.h"
> > #include "intel_sprite.h"
> >
> > /**
> > @@ -60,11 +61,14 @@ int intel_digital_connector_atomic_get_property(struct
> > drm_connector *connector,
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_digital_connector_state *intel_conn_state =
> > to_intel_digital_connector_state(state);
> > + struct intel_connector *intel_connector =
> > to_intel_connector(connector);
> >
> > if (property == dev_priv->force_audio_property)
> > *val = intel_conn_state->force_audio;
> > else if (property == dev_priv->broadcast_rgb_property)
> > *val = intel_conn_state->broadcast_rgb;
> > + else if (property == intel_connector->privacy_screen_property)
> > + *val = intel_conn_state->privacy_screen_status;
> > else {
> > drm_dbg_atomic(_priv->drm,
> > "Unknown property [PROP:%d:%s]\n",
> > @@ -93,15 +97,18 @@ int intel_digital_connector_atomic_set_property(struct
> > drm_connector *connector,
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_digital_connector_state *intel_conn_state =
> > to_intel_digital_connector_state(state);
> > + struct intel_connector *intel_connector =
> > to_intel_connector(connector);
> >
> > if (property == dev_priv->force_audio_property) {
> >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add support for HDCP 1.4 over MST connectors (rev5)
== Series Details == Series: drm/i915: Add support for HDCP 1.4 over MST connectors (rev5) URL : https://patchwork.freedesktop.org/series/70393/ State : success == Summary == CI Bug Log - changes from CI_DRM_8073 -> Patchwork_16845 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16845/index.html Known issues Here are the changes found in Patchwork_16845 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gem_contexts: - fi-cml-s: [PASS][1] -> [DMESG-FAIL][2] ([i915#877]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-cml-s/igt@i915_selftest@live@gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16845/fi-cml-s/igt@i915_selftest@live@gem_contexts.html - fi-cfl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#943]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16845/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([i915#217]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16845/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-gtt: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-tgl-y/igt@prime_v...@basic-gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16845/fi-tgl-y/igt@prime_v...@basic-gtt.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [DMESG-WARN][9] ([i915#44]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16845/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@vgem_basic@create: - fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-tgl-y/igt@vgem_ba...@create.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16845/fi-tgl-y/igt@vgem_ba...@create.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 [i915#943]: https://gitlab.freedesktop.org/drm/intel/issues/943 Participating hosts (47 -> 38) -- Additional (2): fi-kbl-soraka fi-elk-e7500 Missing(11): fi-bdw-5557u fi-hsw-4200u fi-skl-6770hq fi-bsw-cyan fi-ctg-p8600 fi-ivb-3770 fi-cfl-8109u fi-blb-e6850 fi-byt-clapper fi-bdw-samus fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8073 -> Patchwork_16845 CI-20190529: 20190529 CI_DRM_8073: 04042aee59126471bb37cec526ccaf44b4e8d506 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16845: 910e44eeaee67752558b7a4f86d81989a8602dd4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 910e44eeaee6 drm/i915: Add HDCP 1.4 support for MST connectors ed43091c9480 drm/i915: Print HDCP version info for all connectors bbf7c097884e drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message 76ae56e95efc drm/i915: Add connector to hdcp_shim->check_link() c10d2e023dd1 drm/i915: Plumb port through hdcp init e63dce8c2a3f drm/i915: Factor out HDCP shim functions from dp for use by dp_mst 7ea37f514e7b drm/i915: Use ddi_update_pipe in intel_dp_mst c9622c22eb06 drm/i915: Support DP MST in enc_to_dig_port() function 7d468b95ce7a drm/i915: Don't fully disable HDCP on a port if multiple pipes are using it a53b07c7917d drm/i915: Protect workers against disappearing connectors ef2cfbb9e130 drm/i915: Factor out hdcp->value assignments 5bdc5dc77094 drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signalling 16e8d618fa38 drm/i915: Intercept Aksv writes in the aux hooks 729375a1130b drm/i915: WARN if HDCP signalling is enabled upon disable c8f617e7591f drm/i915: Clear the repeater bit on HDCP disable f3d9bb7dc10f drm/i915: Fix sha_text population code == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16845/index.html ___ Intel-gfx mailing list
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Don't treat unslice registers as masked
== Series Details == Series: drm/i915/tgl: Don't treat unslice registers as masked URL : https://patchwork.freedesktop.org/series/74351/ State : failure == Summary == Applying: drm/i915/tgl: Don't treat unslice registers as masked error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gt/intel_workarounds.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/tgl: Don't treat unslice registers as masked When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Add support for HDCP 1.4 over MST connectors (rev5)
== Series Details == Series: drm/i915: Add support for HDCP 1.4 over MST connectors (rev5) URL : https://patchwork.freedesktop.org/series/70393/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for HDCP 1.4 over MST connectors (rev5)
== Series Details ==
Series: drm/i915: Add support for HDCP 1.4 over MST connectors (rev5)
URL : https://patchwork.freedesktop.org/series/70393/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f3d9bb7dc10f drm/i915: Fix sha_text population code
-:63: WARNING:LINE_SPACING: Missing a blank line after declarations
#63: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:343:
+ u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) *
8);
+ sha_text |= ksv[j] << off;
total: 0 errors, 1 warnings, 0 checks, 61 lines checked
c8f617e7591f drm/i915: Clear the repeater bit on HDCP disable
729375a1130b drm/i915: WARN if HDCP signalling is enabled upon disable
16e8d618fa38 drm/i915: Intercept Aksv writes in the aux hooks
5bdc5dc77094 drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP
signalling
ef2cfbb9e130 drm/i915: Factor out hdcp->value assignments
-:69: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#69: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:934:
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_ENABLED, true);
-:114: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#114: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:1802:
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_ENABLED,
-:126: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#126: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:1817:
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_ENABLED,
-:138: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#138: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:1837:
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_DESIRED, true);
total: 0 errors, 0 warnings, 4 checks, 138 lines checked
a53b07c7917d drm/i915: Protect workers against disappearing connectors
-:86: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#86: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:2198:
+ drm_WARN_ON(connector->base.dev,
+ connector->base.registration_state == DRM_CONNECTOR_REGISTERED);
total: 0 errors, 0 warnings, 1 checks, 71 lines checked
7d468b95ce7a drm/i915: Don't fully disable HDCP on a port if multiple pipes are
using it
c9622c22eb06 drm/i915: Support DP MST in enc_to_dig_port() function
7ea37f514e7b drm/i915: Use ddi_update_pipe in intel_dp_mst
e63dce8c2a3f drm/i915: Factor out HDCP shim functions from dp for use by dp_mst
-:660: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#660:
new file mode 100644
-:665: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for
'drivers/gpu/drm/i915/display/intel_dp_hdcp.c', please use '//' instead
#665: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:1:
+/* SPDX-License-Identifier: MIT */
-:665: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#665: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:1:
+/* SPDX-License-Identifier: MIT */
-:986: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#986: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:322:
+
+}
-:1065: WARNING:LINE_SPACING: Missing a blank line after declarations
#1065: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:401:
+ ssize_t ret;
+ ret = drm_dp_dpcd_read(_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
-:1128: WARNING:LINE_SPACING: Missing a blank line after declarations
#1128: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:464:
+ ssize_t ret;
+ ret = drm_dp_dpcd_read(_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
-:1143: WARNING:LINE_SPACING: Missing a blank line after declarations
#1143: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:479:
+ u8 bstatus;
+ ret = drm_dp_dpcd_read(_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
-:1163: WARNING:LINE_SPACING: Missing a blank line after declarations
#1163: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:499:
+ size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
+ ret = drm_dp_dpcd_read(_dig_port->dp.aux,
total: 0 errors, 7 warnings, 1 checks, 1224 lines checked
c10d2e023dd1 drm/i915: Plumb port through hdcp init
76ae56e95efc drm/i915: Add connector to hdcp_shim->check_link()
bbf7c097884e drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST
sideband message
-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:951:
+drm_dp_sideband_parse_query_stream_enc_status(
-:128: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#128: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:3221:
+int drm_dp_send_query_stream_enc_status(struct
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Make wa_1606700617 permanent (rev2)
== Series Details == Series: drm/i915/tgl: Make wa_1606700617 permanent (rev2) URL : https://patchwork.freedesktop.org/series/74240/ State : success == Summary == CI Bug Log - changes from CI_DRM_8073 -> Patchwork_16844 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16844/index.html Known issues Here are the changes found in Patchwork_16844 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#111096] / [i915#323]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16844/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@vgem_basic@setversion: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-tgl-y/igt@vgem_ba...@setversion.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16844/fi-tgl-y/igt@vgem_ba...@setversion.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [DMESG-WARN][5] ([i915#44]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16844/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@vgem_basic@create: - fi-tgl-y: [DMESG-WARN][7] ([CI#94] / [i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-tgl-y/igt@vgem_ba...@create.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16844/fi-tgl-y/igt@vgem_ba...@create.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44 Participating hosts (47 -> 42) -- Additional (3): fi-kbl-soraka fi-snb-2520m fi-skl-6600u Missing(8): fi-hsw-4200u fi-skl-6770hq fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-skl-lmem fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8073 -> Patchwork_16844 CI-20190529: 20190529 CI_DRM_8073: 04042aee59126471bb37cec526ccaf44b4e8d506 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16844: 2591b1a7af9885a30547116c8baddea7f6d5b537 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2591b1a7af98 drm/i915/tgl: Make wa_1606700617 permanent == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16844/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/tgl: Make wa_1606700617 permanent (rev2)
== Series Details == Series: drm/i915/tgl: Make wa_1606700617 permanent (rev2) URL : https://patchwork.freedesktop.org/series/74240/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (rev6)
== Series Details == Series: drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (rev6) URL : https://patchwork.freedesktop.org/series/72747/ State : success == Summary == CI Bug Log - changes from CI_DRM_8068_full -> Patchwork_16830_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16830_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +10 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb4/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-iclb6/igt@gem_b...@busy-vcs1.html * igt@gem_exec_schedule@implicit-both-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [i915#677]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb2/igt@gem_exec_sched...@implicit-both-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-iclb6/igt@gem_exec_sched...@implicit-both-bsd2.html * igt@gem_exec_schedule@pi-shared-iova-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#677]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb8/igt@gem_exec_sched...@pi-shared-iova-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-iclb1/igt@gem_exec_sched...@pi-shared-iova-bsd.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-apl8/igt@i915_susp...@sysfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-apl6/igt@i915_susp...@sysfs-reader.html * igt@kms_color@pipe-b-ctm-green-to-red: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#129]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl1/igt@kms_co...@pipe-b-ctm-green-to-red.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-skl8/igt@kms_co...@pipe-b-ctm-green-to-red.html * igt@kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#182]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl7/igt@kms_co...@pipe-c-ctm-0-25.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-skl10/igt@kms_co...@pipe-c-ctm-0-25.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-256x85-offscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-skl8/igt@kms_cursor_...@pipe-b-cursor-256x85-offscreen.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#72]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl9/igt@kms_...@bpc-switch-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-skl9/igt@kms_...@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-kbl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-kbl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16830/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +4 similar issues [25]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off
== Series Details == Series: drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off URL : https://patchwork.freedesktop.org/series/74346/ State : success == Summary == CI Bug Log - changes from CI_DRM_8073 -> Patchwork_16843 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16843/index.html Known issues Here are the changes found in Patchwork_16843 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@hdmi-crc-fast: - fi-icl-u2: [PASS][1] -> [FAIL][2] ([fdo#109635] / [i915#217]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16843/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#217]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16843/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-fence-flip: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16843/fi-tgl-y/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [DMESG-WARN][7] ([i915#44]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16843/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@vgem_basic@create: - fi-tgl-y: [DMESG-WARN][9] ([CI#94] / [i915#402]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8073/fi-tgl-y/igt@vgem_ba...@create.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16843/fi-tgl-y/igt@vgem_ba...@create.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44 Participating hosts (47 -> 43) -- Additional (4): fi-kbl-soraka fi-elk-e7500 fi-snb-2520m fi-skl-6600u Missing(8): fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-ctg-p8600 fi-cfl-8109u fi-blb-e6850 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8073 -> Patchwork_16843 CI-20190529: 20190529 CI_DRM_8073: 04042aee59126471bb37cec526ccaf44b4e8d506 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16843: 905f1e2e1bf43dbfa3442a1ff9a0b73bf31c1548 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 905f1e2e1bf4 drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16843/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off
== Series Details == Series: drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off URL : https://patchwork.freedesktop.org/series/74346/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/1] Revert "drm/i915/tgl: Add extra hdc flush workaround"
== Series Details == Series: series starting with [1/1] Revert "drm/i915/tgl: Add extra hdc flush workaround" URL : https://patchwork.freedesktop.org/series/74293/ State : success == Summary == CI Bug Log - changes from CI_DRM_8068_full -> Patchwork_16829_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16829_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +10 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb4/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-iclb8/igt@gem_b...@busy-vcs1.html * igt@gem_exec_schedule@implicit-both-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [i915#677]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb4/igt@gem_exec_sched...@implicit-both-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-iclb8/igt@gem_exec_sched...@implicit-both-bsd1.html * igt@gem_exec_schedule@pi-shared-iova-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#677]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb8/igt@gem_exec_sched...@pi-shared-iova-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-iclb2/igt@gem_exec_sched...@pi-shared-iova-bsd.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-kbl2/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-kbl3/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@mock@buddy: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#1310] / [i915#1360]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl2/igt@i915_selftest@m...@buddy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-skl9/igt@i915_selftest@m...@buddy.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-apl8/igt@i915_susp...@fence-restore-tiled2untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@i915_suspend@fence-restore-untiled: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#69]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl5/igt@i915_susp...@fence-restore-untiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-skl6/igt@i915_susp...@fence-restore-untiled.html * igt@kms_color@pipe-b-ctm-green-to-red: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#129]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl1/igt@kms_co...@pipe-b-ctm-green-to-red.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-skl8/igt@kms_co...@pipe-b-ctm-green-to-red.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-snb: [PASS][19] -> [DMESG-WARN][20] ([i915#42]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-snb5/igt@kms_cursor_...@pipe-a-cursor-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-snb6/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-256x85-offscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-skl8/igt@kms_cursor_...@pipe-b-cursor-256x85-offscreen.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][23] -> [FAIL][24] ([i915#72]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16829/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][25] ->
[Intel-gfx] [PATCH v4 1/2] drm/edid: Name the detailed monitor range flags
This patch adds defines for the detailed monitor
range flags as per the EDID specification.
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Harry Wentland
Cc: Clinton A Taylor
Cc: Kazlauskas Nicholas
Signed-off-by: Manasi Navare
---
include/drm/drm_edid.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index f0b03d401c27..f89c97623845 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -91,6 +91,11 @@ struct detailed_data_string {
u8 str[13];
} __attribute__((packed));
+#define EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00
+#define EDID_RANGE_LIMITS_ONLY_FLAG 0x01
+#define EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02
+#define EDID_CVT_SUPPORT_FLAG 0x04
+
struct detailed_data_monitor_range {
u8 min_vfreq;
u8 max_vfreq;
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/2] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
Adaptive Sync is a VESA feature so add a DRM core helper to parse
the EDID's detailed descritors to obtain the adaptive sync monitor range.
Store this info as part fo drm_display_info so it can be used
across all drivers.
This part of the code is stripped out of amdgpu's function
amdgpu_dm_update_freesync_caps() to make it generic and be used
across all DRM drivers
v4:
* Use is_display_descriptor() (Ville)
* Name the monitor range flags (Ville)
v3:
* Remove the edid parsing restriction for just DP (Nicholas)
* Use drm_for_each_detailed_block (Ville)
* Make the drm_get_adaptive_sync_range function static (Harry, Jani)
v2:
* Change vmin and vmax to use u8 (Ville)
* Dont store pixel clock since that is just a max dotclock
and not related to VRR mode (Manasi)
Cc: Ville Syrjälä
Cc: Harry Wentland
Cc: Clinton A Taylor
Cc: Kazlauskas Nicholas
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/drm_edid.c | 44 +
include/drm/drm_connector.h | 22 +++
2 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index ad41764a4ebe..61ed544d9535 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
}
}
+static
+void get_adaptive_sync_range(struct detailed_timing *timing,
+void *info_adaptive_sync)
+{
+ struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync;
+ const struct detailed_non_pixel *data = >data.other_data;
+ const struct detailed_data_monitor_range *range = >data.range;
+
+ if (!is_display_descriptor((const u8 *)timing,
EDID_DETAIL_MONITOR_RANGE))
+ return;
+
+ /*
+* Check for flag range limits only. If flag == 1 then
+* no additional timing information provided.
+* Default GTF, GTF Secondary curve and CVT are not
+* supported
+*/
+ if (range->flags != EDID_RANGE_LIMITS_ONLY_FLAG)
+ return;
+
+ adaptive_sync->min_vfreq = range->min_vfreq;
+ adaptive_sync->max_vfreq = range->max_vfreq;
+}
+
+static
+void drm_get_adaptive_sync_range(struct drm_connector *connector,
+const struct edid *edid)
+{
+ struct drm_display_info *info = >display_info;
+
+ if (!version_greater(edid, 1, 1))
+ return;
+
+ drm_for_each_detailed_block((u8 *)edid, get_adaptive_sync_range,
+ >adaptive_sync);
+
+ DRM_DEBUG_KMS("Adaptive Sync refresh rate range is %d Hz - %d Hz\n",
+ info->adaptive_sync.min_vfreq,
+ info->adaptive_sync.max_vfreq);
+}
+
/* A connector has no EDID information, so we've got no EDID to compute quirks
from. Reset
* all of the values which would have been set from EDID
*/
@@ -4960,6 +5001,7 @@ drm_reset_display_info(struct drm_connector *connector)
memset(>hdmi, 0, sizeof(info->hdmi));
info->non_desktop = 0;
+ memset(>adaptive_sync, 0, sizeof(info->adaptive_sync));
}
u32 drm_add_display_info(struct drm_connector *connector, const struct edid
*edid)
@@ -4975,6 +5017,8 @@ u32 drm_add_display_info(struct drm_connector *connector,
const struct edid *edi
info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
+ drm_get_adaptive_sync_range(connector, edid);
+
DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
if (edid->revision < 3)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 0df7a95ca5d9..2b22c0fa42c4 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -254,6 +254,23 @@ enum drm_panel_orientation {
DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
};
+/**
+ * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for
+ * _display_info
+ *
+ * This struct is used to store a Panel's Adaptive Sync capabilities
+ * as parsed from EDID's detailed monitor range descriptor block.
+ *
+ * @min_vfreq: This is the min supported refresh rate in Hz from
+ * EDID's detailed monitor range.
+ * @max_vfreq: This is the max supported refresh rate in Hz from
+ * EDID's detailed monitor range
+ */
+struct drm_adaptive_sync_info {
+ u8 min_vfreq;
+ u8 max_vfreq;
+};
+
/*
* This is a consolidated colorimetry list supported by HDMI and
* DP protocol standard. The respective connectors will register
@@ -473,6 +490,11 @@ struct drm_display_info {
* @non_desktop: Non desktop display (HMD).
*/
bool non_desktop;
+
+ /**
+* @adaptive_sync: Adaptive Sync capabilities of the DP/eDP sink
+*/
+ struct drm_adaptive_sync_info adaptive_sync;
};
int drm_display_info_set_bus_formats(struct drm_display_info *info,
--
2.19.1
___
Intel-gfx mailing list
Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+
On Thu, 2020-02-20 at 19:26 +0200, Ville Syrjälä wrote:
> On Tue, Feb 18, 2020 at 05:42:30PM -0800, José Roberto de Souza
> wrote:
> > dGFX have local memory so it do not have aperture and do not
> > support
> > CPU fences but even for iGFX it have a small number of fences.
> >
> > As replacement for fences to track frontbuffer modifications by CPU
> > we have a software tracking that is already in used by FBC and PSR.
> > PSR don't support fences so it shows that this tracking is
> > reliable.
> >
> > So lets make fences a nice-to-have to activate FBC for GEN9+, this
> > will allow us to enable FBC for dGFXs and iGFXs even when there is
> > no
> > available fence.
> >
> > We do not set fences to rotated planes but FBC only have
> > restrictions
> > against 16bpp, so adding it here.
> >
> > Also adding a new check for the tiling format, fences are only set
> > to X and Y tiled planes but again FBC don't have any restrictions
> > against tiling so adding linear as supported as well, other formats
> > should be added after tested but IGT only supports drawing in thse
> > 3 formats.
> >
> > intel_fbc_hw_tracking_covers_screen() maybe can also have the same
> > treatment as fences but BSpec is not clear if the size limitation
> > is
> > for hardware tracking or general use of FBC and I don't have a 5K
> > display to test it, so keeping as is for safety.
> >
> > v2:
> > - Added tiling and pixel format rotation checks
> > - Changed the GEN version not requiring fences to 11 from 9, DDX
> > needs some changes but it don't have support for GEN11+
> >
> > v3:
> > - Changed back to GEN9+
> > - Moved GEN test to inside of tiling_is_valid()
> >
> > Cc: Daniel Vetter
> > Cc: Dhinakaran Pandiyan
> > Cc: Ville Syrjälä
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 45
> >
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > 2 files changed, 39 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1d76e3646a25..a0d1d661a006 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -585,7 +585,7 @@ static bool stride_is_valid(struct
> > drm_i915_private *dev_priv,
> > }
> >
> > static bool pixel_format_is_valid(struct drm_i915_private
> > *dev_priv,
> > - u32 pixel_format)
> > + u32 pixel_format, unsigned int
> > rotation)
> > {
> > switch (pixel_format) {
> > case DRM_FORMAT_XRGB:
> > @@ -599,6 +599,9 @@ static bool pixel_format_is_valid(struct
> > drm_i915_private *dev_priv,
> > /* WaFbcOnly1to1Ratio:ctg */
> > if (IS_G4X(dev_priv))
> > return false;
> > + if ((rotation & (DRM_MODE_ROTATE_90 |
> > DRM_MODE_ROTATE_270)) &&
> > + INTEL_GEN(dev_priv) >= 9)
> > + return false;
>
> Would still would prefer a rotations_is_valid() or some such thing.
Like this?
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 5e35c894bdf9..692edd45b769 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -600,15 +600,21 @@ static bool pixel_format_is_valid(struct
drm_i915_private *dev_priv,
/* WaFbcOnly1to1Ratio:ctg */
if (IS_G4X(dev_priv))
return false;
- if ((rotation & (DRM_MODE_ROTATE_90 |
DRM_MODE_ROTATE_270)) &&
- INTEL_GEN(dev_priv) >= 9)
- return false;
return true;
default:
return false;
}
}
+static bool rotations_is_valid(struct drm_i915_private *dev_priv,
+ u32 pixel_format, unsigned int rotation)
+{
+ if (INTEL_GEN(dev_priv) >= 9 && pixel_format ==
DRM_FORMAT_RGB565 &&
+ rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270))
+ return false;
+ return true;
+}
+
/*
* For some reason, the hardware tracking starts looking at whatever
we
* programmed as the display plane base address register. It does not
look at
@@ -810,6 +816,12 @@ static bool intel_fbc_can_activate(struct
intel_crtc *crtc)
return false;
}
+ if (!rotations_is_valid(dev_priv, cache->fb.format->format,
+ cache->plane.rotation)) {
+ fbc->no_fbc_reason = "plane rotation is invalid";
+ return false;
+ }
+
if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE
&&
cache->fb.format->has_alpha) {
fbc->no_fbc_reason = "per-pixel alpha blending is
incompatible with FBC";
>
> > return true;
> > default:
> > return false;
> > @@ -639,6 +642,22 @@ static bool
> >
Re: [Intel-gfx] [PATCH] drm/i915/gt: allow setting generic data pointer
On 3/5/20 5:15 PM, Andi Shyti wrote:
Hi Daniele,
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index 75255aaacaed..9112a8585caf 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -26,15 +26,14 @@ void debugfs_gt_register(struct intel_gt *gt)
debugfs_gt_pm_register(gt, root);
}
-void debugfs_gt_register_files(struct intel_gt *gt,
- struct dentry *root,
- const struct debugfs_gt_file *files,
- unsigned long count)
+void __intel_gt_debugfs_register_files(struct intel_gt *gt, struct dentry
*root,
+ const struct debugfs_gt_file *files,
+ unsigned long count, void *data)
{
while (count--) {
if (!files->eval || files->eval(gt))
IMO the files->eval() function should also use the provided data instead of
intel_gt. This will also allow us to drop the intel_gt parameter in this
function, which in turn means we can use this function directly from all the
levels.
do you mean something like this:
- bool (*eval)(const struct intel_gt *gt);
+ bool (*eval)(void *data);
?
yes
I am missing the use case, though, what is it that cannot be
reached by the gt so that it needs to be more generic?
It's not a problem of reaching it from gt but the other way around, I
don't want the caller to have to retrieve a gt variable it don't needs
just to pass it to this function and then go back to the actual required
data from gt inside of the eval function. Anything you need for your
evaluation should be reachable from the struct used as data for the debugfs.
To make a concrete example, I want to avoid an unneeded guc_to_gt inside
intel_guc_debugfs_register that would also require a matched guc =
>uc.guc inside the eval function, passing guc (i.e. the data)
straight in the eval is cleaner IMO.
Daniele
Do you want to use it at i915 level?
Thanks for the review,
Andi
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: properly sanity check batch_start_offset
== Series Details == Series: drm/i915: properly sanity check batch_start_offset URL : https://patchwork.freedesktop.org/series/74287/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8068_full -> Patchwork_16826_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16826_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16826_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16826_full: ### IGT changes ### Possible regressions * igt@gem_ctx_persistence@close-replace-race: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-tglb6/igt@gem_ctx_persiste...@close-replace-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-tglb3/igt@gem_ctx_persiste...@close-replace-race.html * igt@runner@aborted: - shard-tglb: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-tglb3/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_16826_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +5 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-kbl4/igt@gem_ctx_isolat...@rcs0-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb2/igt@gem_exec_sched...@independent-bsd2.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_whisper@basic-queues-forked: - shard-glk: [PASS][8] -> [INCOMPLETE][9] ([i915#58] / [k.org#198133]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-glk7/igt@gem_exec_whis...@basic-queues-forked.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-glk1/igt@gem_exec_whis...@basic-queues-forked.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#180]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-apl4/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#454]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb8/igt@i915_pm...@dc6-dpms.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@i915_pm_rpm@gem-pread: - shard-iclb: [PASS][14] -> [INCOMPLETE][15] ([i915#189]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb4/igt@i915_pm_...@gem-pread.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-iclb2/igt@i915_pm_...@gem-pread.html * igt@i915_suspend@fence-restore-untiled: - shard-iclb: [PASS][16] -> [INCOMPLETE][17] ([i915#1185]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-iclb6/igt@i915_susp...@fence-restore-untiled.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-iclb3/igt@i915_susp...@fence-restore-untiled.html * igt@kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#182]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl7/igt@kms_co...@pipe-c-ctm-0-25.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-skl8/igt@kms_co...@pipe-c-ctm-0-25.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][20] -> [FAIL][21] ([i915#72]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16826/shard-glk2/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][22] -> [INCOMPLETE][23] ([i915#198]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8068/shard-skl9/igt@kms_...@bpc-switch-suspend.html [23]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gem: Limit struct_mutex to eb_reserve (rev2)
== Series Details == Series: drm/i915/gem: Limit struct_mutex to eb_reserve (rev2) URL : https://patchwork.freedesktop.org/series/74291/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8071 -> Patchwork_16842 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16842 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16842, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16842: ### IGT changes ### Possible regressions * igt@gem_exec_parallel@basic: - fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-icl-guc/igt@gem_exec_paral...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-icl-guc/igt@gem_exec_paral...@basic.html * igt@gem_exec_parallel@contexts: - fi-skl-guc: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-skl-guc/igt@gem_exec_paral...@contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-skl-guc/igt@gem_exec_paral...@contexts.html - fi-icl-dsi: [PASS][5] -> [TIMEOUT][6] +9 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-icl-dsi/igt@gem_exec_paral...@contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-icl-dsi/igt@gem_exec_paral...@contexts.html - fi-skl-6600u: [PASS][7] -> [TIMEOUT][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-skl-6600u/igt@gem_exec_paral...@contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-skl-6600u/igt@gem_exec_paral...@contexts.html - fi-cfl-8700k: [PASS][9] -> [TIMEOUT][10] +9 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-cfl-8700k/igt@gem_exec_paral...@contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-cfl-8700k/igt@gem_exec_paral...@contexts.html - fi-skl-lmem:NOTRUN -> [TIMEOUT][11] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-skl-lmem/igt@gem_exec_paral...@contexts.html - fi-skl-6700k2: [PASS][12] -> [TIMEOUT][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-skl-6700k2/igt@gem_exec_paral...@contexts.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-skl-6700k2/igt@gem_exec_paral...@contexts.html * igt@gem_exec_parallel@fds: - fi-cml-s: [PASS][14] -> [TIMEOUT][15] +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-cml-s/igt@gem_exec_paral...@fds.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-cml-s/igt@gem_exec_paral...@fds.html - fi-cfl-guc: [PASS][16] -> [TIMEOUT][17] +9 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-cfl-guc/igt@gem_exec_paral...@fds.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-cfl-guc/igt@gem_exec_paral...@fds.html * igt@gem_exec_store@basic-all: - fi-cfl-8109u: [PASS][18] -> [TIMEOUT][19] +10 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-cfl-8109u/igt@gem_exec_st...@basic-all.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-cfl-8109u/igt@gem_exec_st...@basic-all.html - fi-apl-guc: [PASS][20] -> [TIMEOUT][21] +8 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-apl-guc/igt@gem_exec_st...@basic-all.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-apl-guc/igt@gem_exec_st...@basic-all.html - fi-kbl-x1275: [PASS][22] -> [TIMEOUT][23] +9 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-kbl-x1275/igt@gem_exec_st...@basic-all.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-kbl-x1275/igt@gem_exec_st...@basic-all.html - fi-icl-y: [PASS][24] -> [TIMEOUT][25] +9 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-icl-y/igt@gem_exec_st...@basic-all.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-icl-y/igt@gem_exec_st...@basic-all.html * igt@gem_exec_suspend@basic: - fi-icl-u2: [PASS][26] -> [TIMEOUT][27] +9 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8071/fi-icl-u2/igt@gem_exec_susp...@basic.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16842/fi-icl-u2/igt@gem_exec_susp...@basic.html * igt@gem_exec_suspend@basic-s0:
Re: [Intel-gfx] [PATCH] drm/i915/gt: allow setting generic data pointer
Hi Daniele,
> > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
> > b/drivers/gpu/drm/i915/gt/debugfs_gt.c
> > index 75255aaacaed..9112a8585caf 100644
> > --- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
> > @@ -26,15 +26,14 @@ void debugfs_gt_register(struct intel_gt *gt)
> > debugfs_gt_pm_register(gt, root);
> > }
> > -void debugfs_gt_register_files(struct intel_gt *gt,
> > - struct dentry *root,
> > - const struct debugfs_gt_file *files,
> > - unsigned long count)
> > +void __intel_gt_debugfs_register_files(struct intel_gt *gt, struct dentry
> > *root,
> > + const struct debugfs_gt_file *files,
> > + unsigned long count, void *data)
> > {
> > while (count--) {
> > if (!files->eval || files->eval(gt))
>
> IMO the files->eval() function should also use the provided data instead of
> intel_gt. This will also allow us to drop the intel_gt parameter in this
> function, which in turn means we can use this function directly from all the
> levels.
do you mean something like this:
- bool (*eval)(const struct intel_gt *gt);
+ bool (*eval)(void *data);
?
I am missing the use case, though, what is it that cannot be
reached by the gt so that it needs to be more generic?
Do you want to use it at i915 level?
Thanks for the review,
Andi
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Limit struct_mutex to eb_reserve (rev2)
== Series Details == Series: drm/i915/gem: Limit struct_mutex to eb_reserve (rev2) URL : https://patchwork.freedesktop.org/series/74291/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: allow setting generic data pointer
On 3/5/20 3:59 PM, Andi Shyti wrote:
When registering debugfs files the intel gt debugfs library
forces a 'struct *gt' private data on the caller.
There might be different needs, therefore make it generic by
adding one more argument to the "debugfs_register_files()"
function which gets the generic void private data as argument.
Still keep it simple by defining a wrapper where struct *gt is
the chosen private data to be stored.
I take the chance to rename the functions by using "intel_gt_" as
prefix instead of "debugfs_".
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/debugfs_engines.c | 2 +-
drivers/gpu/drm/i915/gt/debugfs_gt.c | 9 -
drivers/gpu/drm/i915/gt/debugfs_gt.h | 10 ++
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 2 +-
4 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.c
b/drivers/gpu/drm/i915/gt/debugfs_engines.c
index 6a5e9ab20b94..3434df10d58c 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_engines.c
@@ -32,5 +32,5 @@ void debugfs_engines_register(struct intel_gt *gt, struct
dentry *root)
{ "engines", _fops },
};
- debugfs_gt_register_files(gt, root, files, ARRAY_SIZE(files));
+ intel_gt_debugfs_register_file(gt, root, files, ARRAY_SIZE(files));
}
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index 75255aaacaed..9112a8585caf 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -26,15 +26,14 @@ void debugfs_gt_register(struct intel_gt *gt)
debugfs_gt_pm_register(gt, root);
}
-void debugfs_gt_register_files(struct intel_gt *gt,
- struct dentry *root,
- const struct debugfs_gt_file *files,
- unsigned long count)
+void __intel_gt_debugfs_register_files(struct intel_gt *gt, struct dentry
*root,
+ const struct debugfs_gt_file *files,
+ unsigned long count, void *data)
{
while (count--) {
if (!files->eval || files->eval(gt))
IMO the files->eval() function should also use the provided data instead
of intel_gt. This will also allow us to drop the intel_gt parameter in
this function, which in turn means we can use this function directly
from all the levels.
Daniele
debugfs_create_file(files->name,
- 0444, root, gt,
+ 0444, root, data,
files->fops);
files++;
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.h
b/drivers/gpu/drm/i915/gt/debugfs_gt.h
index 4ea0f06cda8f..1c01d70a2a44 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.h
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.h
@@ -31,9 +31,11 @@ struct debugfs_gt_file {
bool (*eval)(const struct intel_gt *gt);
};
-void debugfs_gt_register_files(struct intel_gt *gt,
- struct dentry *root,
- const struct debugfs_gt_file *files,
- unsigned long count);
+void __intel_gt_debugfs_register_files(struct intel_gt *gt, struct dentry
*root,
+ const struct debugfs_gt_file *files,
+ unsigned long count, void *data);
+
+#define intel_gt_debugfs_register_file(_g, _r, _f, _c) \
+ __intel_gt_debugfs_register_files(_g, _r, _f, _c, _g)
#endif /* DEBUGFS_GT_H */
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 059c9e5c002e..a8d2391a207a 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -597,5 +597,5 @@ void debugfs_gt_pm_register(struct intel_gt *gt, struct
dentry *root)
{ "rps_boost", _boost_fops, rps_eval },
};
- debugfs_gt_register_files(gt, root, files, ARRAY_SIZE(files));
+ intel_gt_debugfs_register_file(gt, root, files, ARRAY_SIZE(files));
}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Deactive FBC in fastsets when disabled by parameter
On Wed, 2020-02-19 at 20:52 +0200, Ville Syrjälä wrote: > On Wed, Feb 19, 2020 at 06:37:27PM +, Souza, Jose wrote: > > On Wed, 2020-02-19 at 15:37 +0200, Ville Syrjälä wrote: > > > On Tue, Feb 18, 2020 at 05:42:28PM -0800, José Roberto de Souza > > > wrote: > > > > Most of the kms_frontbuffer_tracking tests disables the feature > > > > being > > > > tested, draw, get the CRC then enable the feature, draw again, > > > > get > > > > the > > > > CRC and check if it matches. > > > > Some times it is able to do that with a fastset, so > > > > intel_pre_plane_update() is executed but > > > > intel_fbc_can_flip_nuke() > > > > was > > > > not checking if FBC is now enabled in this CRTC leaving FBC > > > > active > > > > and > > > > causing the warning bellow in __intel_fbc_disable() > > > > > > > > [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-pri- > > > > indfb- > > > > multidraw > > > > Setting dangerous option enable_fbc - tainting kernel > > > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting > > > > PSR > > > > debug to f > > > > i915 :00:02.0: [drm:intel_psr_debug_set [i915]] Invalid > > > > debug > > > > mask f > > > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting > > > > PSR > > > > debug to 1 > > > > i915 :00:02.0: [drm:intel_atomic_check [i915]] > > > > [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of > > > > EDID > > > > bpp 24, requested bpp 36, max platform bpp 36 > > > > [drm:intel_dp_compute_config [i915]] DP link computation with > > > > max > > > > lane count 2 max rate 27 max bpp 24 pixel clock 138120KHz > > > > [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > > > > [drm:intel_dp_compute_config [i915]] DP lane count 2 clock > > > > 27 > > > > bpp 24 > > > > [drm:intel_dp_compute_config [i915]] DP link rate required > > > > 414360 > > > > available 54 > > > > i915 :00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: > > > > 24, > > > > pipe bpp: 24, dithering: 0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > [CRTC:91:pipe A] enable: yes [fastset] > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] active: > > > > yes, > > > > output_types: EDP (0x100), output format: RGB > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: > > > > lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, > > > > link_n: > > > > 524288, tu: 64 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] audio: > > > > 0, > > > > infoframes: 0, infoframes enabled: 0x0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > requested > > > > mode: > > > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 > > > > 138120 > > > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted > > > > mode: > > > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 > > > > 138120 > > > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > > > [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 > > > > 1968 > > > > 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] port > > > > clock: > > > > 27, pipe src size: 1920x1080, pixel rate 138120 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > linetime: > > > > 119, ips linetime: 0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > num_scalers: > > > > 2, scaler_users: 0x0, scaler_id: -1 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] pch > > > > pfit: > > > > pos: 0x, size: 0x, disabled, force thru: no > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, > > > > double wide: 0 > > > > [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: > > > > 0x1c001a5, > > > > cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: > > > > 0x0, > > > > mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, > > > > mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, > > > > mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > csc_mode: > > > > 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] MST > > > > master > > > > transcoder: > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > [PLANE:31:plane 1A] fb: [FB:262] 1920x1080 format = XR24 > > > > little- > > > > endian (0x34325258), visible: yes > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] rotatio > > > > n: 0x1, scaler: -1 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] src: > > > > 1920.00x1080.00+0.00+0.00 dst: 1920x1080+0+0 > > > > i915 :00:02.0: [drm:intel_psr_disable_locked [i915]] > > > > Disabling > >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Show the "switch priority hint" in dumps
== Series Details == Series: drm/i915/execlists: Show the "switch priority hint" in dumps URL : https://patchwork.freedesktop.org/series/74340/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16841 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16841/index.html Known issues Here are the changes found in Patchwork_16841 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#111096] / [i915#323]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16841/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-fence-flip: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16841/fi-tgl-y/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@kms_addfb_basic@addfb25-modifier-no-flag: - fi-tgl-y: [DMESG-WARN][5] ([CI#94] / [i915#402]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16841/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (49 -> 42) -- Additional (2): fi-kbl-soraka fi-kbl-7560u Missing(9): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-cfl-8109u fi-elk-e7500 fi-blb-e6850 fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8070 -> Patchwork_16841 CI-20190529: 20190529 CI_DRM_8070: d4e6f8b48e361f0cae9132f50f1778707b2546a2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16841: d0ef337b3a89247a8ed4b7bf2d77fe5a641e20d7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d0ef337b3a89 drm/i915/execlists: Show the "switch priority hint" in dumps == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16841/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts
From: Prathap Kumar Valsan
On gen7 and gen7.5 devices, there could be leftover data residuals in
EU/L3 from the retiring context. This patch introduces workaround to clear
that residual contexts, by submitting a batch buffer with dedicated HW
context to the GPU with ring allocation for each context switching.
This security mitigation changes does not triggers any performance
regression. Performance is on par with current drm-tips.
v2: Add igt generated header file for CB kernel assembled with Mesa tool
and addressed use of Kernel macro for ptr_align comment.
v3: Resolve Sparse warnings with newly generated, and imported CB
kernel.
v4: Include new igt generated CB kernel for gen7 and gen7.5. Also
add code formatting and compiler warnings changes (Chris Wilson)
Signed-off-by: Mika Kuoppala
Signed-off-by: Prathap Kumar Valsan
Signed-off-by: Akeem G Abodunrin
Cc: Chris Wilson
Cc: Balestrieri Francesco
Cc: Bloomfield Jon
Cc: Dutt Sudeep
Acked-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20200304130353.2448417-2-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/gen7_renderclear.c| 402 ++
drivers/gpu/drm/i915/gt/gen7_renderclear.h| 15 +
drivers/gpu/drm/i915/gt/hsw_clear_kernel.c| 61 +++
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 17 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 3 +-
drivers/gpu/drm/i915/gt/ivb_clear_kernel.c| 61 +++
7 files changed, 556 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/gen7_renderclear.c
create mode 100644 drivers/gpu/drm/i915/gt/gen7_renderclear.h
create mode 100644 drivers/gpu/drm/i915/gt/hsw_clear_kernel.c
create mode 100644 drivers/gpu/drm/i915/gt/ivb_clear_kernel.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 991a8c537d12..9f887a86e555 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -80,6 +80,7 @@ gt-y += \
gt/debugfs_gt.o \
gt/debugfs_gt_pm.o \
gt/gen6_ppgtt.o \
+ gt/gen7_renderclear.o \
gt/gen8_ppgtt.o \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
new file mode 100644
index ..de595b66a746
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -0,0 +1,402 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "gen7_renderclear.h"
+#include "i915_drv.h"
+#include "intel_gpu_commands.h"
+
+#define MAX_URB_ENTRIES 64
+#define STATE_SIZE (4 * 1024)
+#define GT3_INLINE_DATA_DELAYS 0x1E00
+#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
+
+struct cb_kernel {
+ const void *data;
+ u32 size;
+};
+
+#define CB_KERNEL(name) { .data = (name), .size = sizeof(name) }
+
+#include "ivb_clear_kernel.c"
+static const struct cb_kernel cb_kernel_ivb = CB_KERNEL(ivb_clear_kernel);
+
+#include "hsw_clear_kernel.c"
+static const struct cb_kernel cb_kernel_hsw = CB_KERNEL(hsw_clear_kernel);
+
+struct batch_chunk {
+ struct i915_vma *vma;
+ u32 offset;
+ u32 *start;
+ u32 *end;
+ u32 max_items;
+};
+
+struct batch_vals {
+ u32 max_primitives;
+ u32 max_urb_entries;
+ u32 cmd_size;
+ u32 state_size;
+ u32 state_start;
+ u32 batch_size;
+ u32 surface_height;
+ u32 surface_width;
+ u32 scratch_size;
+ u32 max_size;
+};
+
+static void
+batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
+{
+ if (IS_HASWELL(i915)) {
+ bv->max_primitives = 280;
+ bv->max_urb_entries = MAX_URB_ENTRIES;
+ bv->surface_height = 16 * 16;
+ bv->surface_width = 32 * 2 * 16;
+ } else {
+ bv->max_primitives = 128;
+ bv->max_urb_entries = MAX_URB_ENTRIES / 2;
+ bv->surface_height = 16 * 8;
+ bv->surface_width = 32 * 16;
+ }
+ bv->cmd_size = bv->max_primitives * 4096;
+ bv->state_size = STATE_SIZE;
+ bv->state_start = bv->cmd_size;
+ bv->batch_size = bv->cmd_size + bv->state_size;
+ bv->scratch_size = bv->surface_height * bv->surface_width;
+ bv->max_size = bv->batch_size + bv->scratch_size;
+}
+
+static void batch_init(struct batch_chunk *bc,
+ struct i915_vma *vma,
+ u32 *start, u32 offset, u32 max_bytes)
+{
+ bc->vma = vma;
+ bc->offset = offset;
+ bc->start = start + bc->offset / sizeof(*bc->start);
+ bc->end = bc->start;
+ bc->max_items = max_bytes / sizeof(*bc->start);
+}
+
+static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
+{
+ return (cs - bc->start) * sizeof(*bc->start) + bc->offset;
+}
+
+static u32 batch_addr(const struct batch_chunk *bc)
+{
+ return
[Intel-gfx] [CI 1/2] drm/i915: Add mechanism to submit a context WA on ring submission
From: Mika Kuoppala
This patch adds framework to submit an arbitrary batchbuffer on each
context switch to clear residual state for render engine on Gen7/7.5
devices.
The idea of always emitting the context and vm setup around each request
is primary to make reset recovery easy, and not require rewriting the
ringbuffer. As each request would set up its own context, leaving it to
the HW to notice and elide no-op context switches, we could restart the
ring at any point, and reorder the requests freely.
However, to avoid emitting clear_residuals() between consecutive requests
in the ringbuffer of the same context, we do want to track the current
context in the ring. In doing so, we need to be careful to only record a
context switch when we are sure the next request will be emitted.
This security mitigation change does not trigger any performance
regression. Performance is on par with current mainline/drm-tip.
v2: Update vm_alias params to point to correct address space "vm" due to
changes made in the patch "f21613797bae98773"
v3-v4: none
Signed-off-by: Mika Kuoppala
Signed-off-by: Prathap Kumar Valsan
Signed-off-by: Akeem G Abodunrin
Cc: Chris Wilson
Cc: Balestrieri Francesco
Cc: Bloomfield Jon
Cc: Dutt Sudeep
Reviewed-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20200304130353.2448417-1-ch...@chris-wilson.co.uk
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 138 -
.../drm/i915/gt/selftest_ring_submission.c| 290 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 425 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_ring_submission.c
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index ee241b7eaa3b..f0ce70861e93 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1356,7 +1356,9 @@ static int load_pd_dir(struct i915_request *rq,
return rq->engine->emit_flush(rq, EMIT_FLUSH);
}
-static inline int mi_set_context(struct i915_request *rq, u32 flags)
+static inline int mi_set_context(struct i915_request *rq,
+struct intel_context *ce,
+u32 flags)
{
struct drm_i915_private *i915 = rq->i915;
struct intel_engine_cs *engine = rq->engine;
@@ -1431,7 +1433,7 @@ static inline int mi_set_context(struct i915_request *rq,
u32 flags)
*cs++ = MI_NOOP;
*cs++ = MI_SET_CONTEXT;
- *cs++ = i915_ggtt_offset(rq->context->state) | flags;
+ *cs++ = i915_ggtt_offset(ce->state) | flags;
/*
* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
* WaMiSetContext_Hang:snb,ivb,vlv
@@ -1546,13 +1548,56 @@ static int switch_mm(struct i915_request *rq, struct
i915_address_space *vm)
return rq->engine->emit_flush(rq, EMIT_INVALIDATE);
}
+static int clear_residuals(struct i915_request *rq)
+{
+ struct intel_engine_cs *engine = rq->engine;
+ int ret;
+
+ ret = switch_mm(rq, vm_alias(engine->kernel_context->vm));
+ if (ret)
+ return ret;
+
+ if (engine->kernel_context->state) {
+ ret = mi_set_context(rq,
+engine->kernel_context,
+MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT);
+ if (ret)
+ return ret;
+ }
+
+ ret = engine->emit_bb_start(rq,
+ engine->wa_ctx.vma->node.start, 0,
+ 0);
+ if (ret)
+ return ret;
+
+ ret = engine->emit_flush(rq, EMIT_FLUSH);
+ if (ret)
+ return ret;
+
+ /* Always invalidate before the next switch_mm() */
+ return engine->emit_flush(rq, EMIT_INVALIDATE);
+}
+
static int switch_context(struct i915_request *rq)
{
+ struct intel_engine_cs *engine = rq->engine;
struct intel_context *ce = rq->context;
+ void **residuals = NULL;
int ret;
GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
+ if (engine->wa_ctx.vma && ce != engine->kernel_context) {
+ if (engine->wa_ctx.vma->private != ce) {
+ ret = clear_residuals(rq);
+ if (ret)
+ return ret;
+
+ residuals = >wa_ctx.vma->private;
+ }
+ }
+
ret = switch_mm(rq, vm_alias(ce->vm));
if (ret)
return ret;
@@ -1560,7 +1605,7 @@ static int switch_context(struct i915_request *rq)
if (ce->state) {
u32 flags;
- GEM_BUG_ON(rq->engine->id != RCS0);
+ GEM_BUG_ON(engine->id != RCS0);
/* For resource streamer on HSW+ and power context elsewhere */
BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN !=
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/execlists: Show the "switch priority hint" in dumps
== Series Details == Series: drm/i915/execlists: Show the "switch priority hint" in dumps URL : https://patchwork.freedesktop.org/series/74340/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: allow setting generic data pointer
When registering debugfs files the intel gt debugfs library
forces a 'struct *gt' private data on the caller.
There might be different needs, therefore make it generic by
adding one more argument to the "debugfs_register_files()"
function which gets the generic void private data as argument.
Still keep it simple by defining a wrapper where struct *gt is
the chosen private data to be stored.
I take the chance to rename the functions by using "intel_gt_" as
prefix instead of "debugfs_".
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/debugfs_engines.c | 2 +-
drivers/gpu/drm/i915/gt/debugfs_gt.c | 9 -
drivers/gpu/drm/i915/gt/debugfs_gt.h | 10 ++
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 2 +-
4 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.c
b/drivers/gpu/drm/i915/gt/debugfs_engines.c
index 6a5e9ab20b94..3434df10d58c 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_engines.c
@@ -32,5 +32,5 @@ void debugfs_engines_register(struct intel_gt *gt, struct
dentry *root)
{ "engines", _fops },
};
- debugfs_gt_register_files(gt, root, files, ARRAY_SIZE(files));
+ intel_gt_debugfs_register_file(gt, root, files, ARRAY_SIZE(files));
}
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index 75255aaacaed..9112a8585caf 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -26,15 +26,14 @@ void debugfs_gt_register(struct intel_gt *gt)
debugfs_gt_pm_register(gt, root);
}
-void debugfs_gt_register_files(struct intel_gt *gt,
- struct dentry *root,
- const struct debugfs_gt_file *files,
- unsigned long count)
+void __intel_gt_debugfs_register_files(struct intel_gt *gt, struct dentry
*root,
+ const struct debugfs_gt_file *files,
+ unsigned long count, void *data)
{
while (count--) {
if (!files->eval || files->eval(gt))
debugfs_create_file(files->name,
- 0444, root, gt,
+ 0444, root, data,
files->fops);
files++;
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.h
b/drivers/gpu/drm/i915/gt/debugfs_gt.h
index 4ea0f06cda8f..1c01d70a2a44 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.h
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.h
@@ -31,9 +31,11 @@ struct debugfs_gt_file {
bool (*eval)(const struct intel_gt *gt);
};
-void debugfs_gt_register_files(struct intel_gt *gt,
- struct dentry *root,
- const struct debugfs_gt_file *files,
- unsigned long count);
+void __intel_gt_debugfs_register_files(struct intel_gt *gt, struct dentry
*root,
+ const struct debugfs_gt_file *files,
+ unsigned long count, void *data);
+
+#define intel_gt_debugfs_register_file(_g, _r, _f, _c) \
+ __intel_gt_debugfs_register_files(_g, _r, _f, _c, _g)
#endif /* DEBUGFS_GT_H */
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 059c9e5c002e..a8d2391a207a 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -597,5 +597,5 @@ void debugfs_gt_pm_register(struct intel_gt *gt, struct
dentry *root)
{ "rps_boost", _boost_fops, rps_eval },
};
- debugfs_gt_register_files(gt, root, files, ARRAY_SIZE(files));
+ intel_gt_debugfs_register_file(gt, root, files, ARRAY_SIZE(files));
}
--
2.25.0
___
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Don't treat unslice registers as masked
On Thu, 2020-03-05 at 12:24 -0800, Matt Roper wrote:
> The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2
> registers
> that we update in a few engine workarounds are not masked registers
> (i.e., we don't have to write a mask bit in the top 16 bits when
> updating one of the lower 16 bits). As such, these workarounds
> should
> be applied via wa_write_or() rather than wa_masked_en()
Thanks Nick for spotting and Matt for fixing it, did not notice this
difference up to know.
Reviewed-by: José Roberto de Souza
>
> Reported-by: Nick Desaulniers
> Fixes: 50148a25f841 ("drm/i915/tgl: Move and restrict Wa_1408615072")
> Fixes: 3551ff928744 ("drm/i915/gen11: Moving WAs to
> rcs_engine_wa_init()")
> Cc: José Roberto de Souza
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 908a70914399..b4785212fb7d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1382,8 +1382,8 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> wa_masked_en(wal, GEN9_ROW_CHICKEN4,
> GEN12_DISABLE_TDL_PUSH);
>
> /* Wa_1408615072:tgl */
> - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> - VSUNIT_CLKGATE_DIS_TGL);
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> + VSUNIT_CLKGATE_DIS_TGL);
> }
>
> if (IS_TIGERLAKE(i915)) {
> @@ -1467,12 +1467,12 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
>* Wa_1408615072:icl,ehl (vsunit)
>* Wa_1407596294:icl,ehl (hsunit)
>*/
> - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> - VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> + VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
>
> /* Wa_1407352427:icl,ehl */
> - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> - PSDUNIT_CLKGATE_DIS);
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> + PSDUNIT_CLKGATE_DIS);
>
> /* Wa_1406680159:icl,ehl */
> wa_write_or(wal,
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Return early for await_start on same timeline
== Series Details == Series: drm/i915: Return early for await_start on same timeline URL : https://patchwork.freedesktop.org/series/74338/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16839 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/index.html Known issues Here are the changes found in Patchwork_16839 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [PASS][1] -> [FAIL][2] ([CI#94]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_getparams_basic@basic-eu-total: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@i915_getparams_ba...@basic-eu-total.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/fi-tgl-y/igt@i915_getparams_ba...@basic-eu-total.html * igt@i915_selftest@live@gem_contexts: - fi-cml-s: [PASS][5] -> [DMESG-FAIL][6] ([i915#877]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-cml-s/igt@i915_selftest@live@gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/fi-cml-s/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@late_gt_pm: - fi-tgl-y: [PASS][7] -> [INCOMPLETE][8] ([CI#94]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@i915_selftest@live@late_gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/fi-tgl-y/igt@i915_selftest@live@late_gt_pm.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [PASS][9] -> [FAIL][10] ([i915#217]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html - fi-kbl-7500u: [PASS][11] -> [FAIL][12] ([fdo#111407]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_flip@basic-flip-vs-dpms: - fi-skl-6770hq: [PASS][13] -> [SKIP][14] ([fdo#109271]) +24 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html Possible fixes * igt@kms_addfb_basic@addfb25-modifier-no-flag: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 Participating hosts (49 -> 46) -- Additional (2): fi-kbl-soraka fi-kbl-7560u Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8070 -> Patchwork_16839 CI-20190529: 20190529 CI_DRM_8070: d4e6f8b48e361f0cae9132f50f1778707b2546a2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16839: b6afdb6c7c6e1b12d5249074631e6615b81afce9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b6afdb6c7c6e drm/i915: Return early for await_start on same timeline == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16839/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: HDCP: fix Ri prime and R0 checks during auth (rev2)
== Series Details == Series: drm/i915: HDCP: fix Ri prime and R0 checks during auth (rev2) URL : https://patchwork.freedesktop.org/series/74271/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/6] drm/i915/uc: Move uC debugfs to its own folder under GT
On 3/5/20 10:02 AM, Andi Shyti wrote:
Hi Daniele,
On Thu, Feb 27, 2020 at 06:28:42PM -0800, Daniele Ceraolo Spurio wrote:
uC is a component of the GT, so it makes sense for the uC debugfs files
to be in the GT folder. A subfolder has been used to keep the same
structure we have for the code.
Can we please document the interface changes. I see there are
some differences between the original and the new interfaces.
What differences are you referring to? there aren't supposed to be any,
aside from the path change.
Have I seen it wrong or there are new files in this patch?
No, no new debugfs files, only the old ones moved across.
In any case, maybe we need to have the new structure.
+#define DEFINE_UC_DEBUGFS_ATTRIBUTE(__name)\
+ static int __name ## _open(struct inode *inode, struct file *file) \
+{ \
+ return single_open(file, __name ## _show, inode->i_private); \
+} \
+static const struct file_operations __name ## _fops = {
\
+ .owner = THIS_MODULE, \
+ .open = __name ## _open,\
+ .read = seq_read, \
+ .llseek = seq_lseek,\
+ .release = single_release, \
+}
Why do we need DEFINE_UC_DEBUGFS_ATTRIBUTE()?
DEFINE_GT_DEBUGFS_ATTRIBUTE() was meant to be common to all gt
debugfs. I there any reason we need a new one?
Just wanted to avoid including the other header just for this macro.
well that was supposed to be a library for all the gem/debugfs
files and avoid duplicated code, I don't see anything wrong with
including the file.
+struct debugfs_uc_file {
+ const char *name;
+ const struct file_operations *fops;
+};
+
+#define debugfs_uc_register_files(files__, root__, data__) \
+do { \
+ int i__ = 0; \
+ for (i__ = 0; i__ < ARRAY_SIZE(files__); i__++) { \
+ debugfs_create_file(files__[i__].name, \
+ 0444, root__, data__, \
+ files__[i__].fops); \
+ } \
+} while (0)
You want to define your own debugfs_uc_register_files() instead
of using debugfs_gt_register_files() because you want "data__"
to be void, right?
I think we can achieve that by adding a wrapper in debugfs_gt.c,
perhaps we can do something like:
void __debugfs_gt_register_files(struct intel_gt *gt,
struct dentry *root,
const struct debugfs_gt_file *files,
void *data,
unsigned long count)
{
..
}
and
#define debugfs_gt_register_files(...) __debugfs_gt_register_files(...)
#define debugfs_uc_register_files(...) __debugfs_gt_register_files(...)
so that we can keep everything in a library. What do you think.
LGTM. Mind if I rename to:
intel_gt_debugfs_register(...)
intel_uc_debugfs_register(...)
to avoid the debugfs_* prefix, as pointed out by Jani?
I have a patch for it, can you please hold a little, unless, of
course, yours is already ready.
Sure, I'll wait for your patch to land first.
Daniele
Obvously, the naming you propose makes sense.
Andi
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Return early for await_start on same timeline
== Series Details == Series: drm/i915: Return early for await_start on same timeline URL : https://patchwork.freedesktop.org/series/74338/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: drm_fb_helper cleanup. (rev3)
== Series Details ==
Series: drm: drm_fb_helper cleanup. (rev3)
URL : https://patchwork.freedesktop.org/series/74140/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16838
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16838/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_16838:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gem_contexts:
- {fi-ehl-1}: [PASS][1] -> [DMESG-FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-ehl-1/igt@i915_selftest@live@gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16838/fi-ehl-1/igt@i915_selftest@live@gem_contexts.html
Known issues
Here are the changes found in Patchwork_16838 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [PASS][3] -> [FAIL][4] ([CI#94])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16838/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live@gem_contexts:
- fi-cml-s: [PASS][5] -> [DMESG-FAIL][6] ([i915#877])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16838/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
* igt@kms_addfb_basic@addfb25-yf-tiled:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402])
+1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-yf-tiled.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16838/fi-tgl-y/igt@kms_addfb_ba...@addfb25-yf-tiled.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111407])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16838/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@kms_addfb_basic@addfb25-modifier-no-flag:
- fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12]
+1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16838/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
Participating hosts (49 -> 38)
--
Additional (2): fi-kbl-soraka fi-kbl-7560u
Missing(13): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq
fi-glk-dsi fi-bsw-cyan fi-bwr-2160 fi-snb-2520m fi-ctg-p8600 fi-skl-lmem
fi-bdw-samus fi-bsw-nick fi-skl-6600u
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8070 -> Patchwork_16838
CI-20190529: 20190529
CI_DRM_8070: d4e6f8b48e361f0cae9132f50f1778707b2546a2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16838: 20055c3f1cd148890751083536dfd917d1455535 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
20055c3f1cd1 drm/todo: Update drm_fb_helper tasks
e29c1841f9cb drm/fb-helper: Remove drm_fb_helper add, add_all and remove
connector functions
00e5d305068d drm: Remove drm_fb_helper add, add all and remove connector calls
7724cd065d42 drm/i915/display: Remove drm_fb_helper_{add, remove}_one_connector
calls
05220ebcdb90 drm/amdgpu: Remove drm_fb_helper_{add, remove}_one_connector calls
b335ca350b9c drm/radeon: remove radeon_fb_{add, remove}_connector functions
9a2c55206305 drm: Remove unused arg from drm_fb_helper_init
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16838/index.html
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm: drm_fb_helper cleanup. (rev3)
== Series Details == Series: drm: drm_fb_helper cleanup. (rev3) URL : https://patchwork.freedesktop.org/series/74140/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Add mechanism to submit a
context WA on ring submission
URL : https://patchwork.freedesktop.org/series/74331/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16837
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_16837 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16837, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16837/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_16837:
### IGT changes ###
Possible regressions
* {igt@i915_selftest@live@ring_submission} (NEW):
- fi-elk-e7500: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16837/fi-elk-e7500/igt@i915_selftest@live@ring_submission.html
* igt@runner@aborted:
- fi-byt-j1900: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16837/fi-byt-j1900/igt@run...@aborted.html
New tests
-
New tests have been introduced between CI_DRM_8070 and Patchwork_16837:
### New IGT tests (1) ###
* igt@i915_selftest@live@ring_submission:
- Statuses : 1 dmesg-fail(s) 1 incomplete(s) 34 pass(s)
- Exec time: [0.0, 5.62] s
Known issues
Here are the changes found in Patchwork_16837 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [PASS][3] -> [FAIL][4] ([CI#94])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16837/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live@gem_contexts:
- fi-cml-s: [PASS][5] -> [DMESG-FAIL][6] ([i915#877])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16837/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402])
+1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16837/fi-tgl-y/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch.html
Possible fixes
* igt@kms_addfb_basic@addfb25-modifier-no-flag:
- fi-tgl-y: [DMESG-WARN][9] ([CI#94] / [i915#402]) -> [PASS][10]
+1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16837/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
Participating hosts (49 -> 38)
--
Additional (1): fi-kbl-soraka
Missing(12): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy
fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-kbl-x1275 fi-cfl-8109u fi-blb-e6850
fi-bdw-samus fi-snb-2600
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8070 -> Patchwork_16837
CI-20190529: 20190529
CI_DRM_8070: d4e6f8b48e361f0cae9132f50f1778707b2546a2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16837: 0a707ecdc6219190569615d208836e6476dea373 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0a707ecdc621 drm/i915/gen7: Clear all EU/L3 residual contexts
e0fd0fe40b02 drm/i915: Add mechanism to submit a context WA on ring submission
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16837/index.html
___
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission
== Series Details == Series: series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission URL : https://patchwork.freedesktop.org/series/74331/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Don't treat unslice registers as masked
On Thu, Mar 5, 2020 at 12:25 PM Matt Roper wrote:
>
> The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 registers
> that we update in a few engine workarounds are not masked registers
> (i.e., we don't have to write a mask bit in the top 16 bits when
> updating one of the lower 16 bits). As such, these workarounds should
> be applied via wa_write_or() rather than wa_masked_en()
>
> Reported-by: Nick Desaulniers
> Fixes: 50148a25f841 ("drm/i915/tgl: Move and restrict Wa_1408615072")
> Fixes: 3551ff928744 ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()")
> Cc: José Roberto de Souza
> Signed-off-by: Matt Roper
I appreciate the fast turnaround time!
Tested-by: Nick Desaulniers
If the maintainer wouldn't mind adding the following tags to help us
track and show some love for our bots:
Link: https://github.com/ClangBuiltLinux/linux/issues/918
Reported-by: kernelci.org bot
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 908a70914399..b4785212fb7d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1382,8 +1382,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
>
> /* Wa_1408615072:tgl */
> - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> -VSUNIT_CLKGATE_DIS_TGL);
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> + VSUNIT_CLKGATE_DIS_TGL);
> }
>
> if (IS_TIGERLAKE(i915)) {
> @@ -1467,12 +1467,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> * Wa_1408615072:icl,ehl (vsunit)
> * Wa_1407596294:icl,ehl (hsunit)
> */
> - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> -VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> + VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
>
> /* Wa_1407352427:icl,ehl */
> - wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> -PSDUNIT_CLKGATE_DIS);
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> + PSDUNIT_CLKGATE_DIS);
>
> /* Wa_1406680159:icl,ehl */
> wa_write_or(wal,
> --
> 2.24.1
>
--
Thanks,
~Nick Desaulniers
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Add mechanism to submit a context WA on ring submission
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Add mechanism to submit a
context WA on ring submission
URL : https://patchwork.freedesktop.org/series/74331/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e0fd0fe40b02 drm/i915: Add mechanism to submit a context WA on ring submission
-:262: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#262:
new file mode 100644
-:373: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#373: FILE: drivers/gpu/drm/i915/gt/selftest_ring_submission.c:107:
+ pr_err("pass[%d] wa_bb emitted for the kernel
context\n",
+ pass);
-:384: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#384: FILE: drivers/gpu/drm/i915/gt/selftest_ring_submission.c:118:
+ pr_err("pass[%d] wa_bb *NOT* emitted after the
kernel context\n",
+ pass);
-:395: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#395: FILE: drivers/gpu/drm/i915/gt/selftest_ring_submission.c:129:
+ pr_err("pass[%d] wa_bb *NOT* emitted for the
user context switch\n",
+ pass);
total: 0 errors, 1 warnings, 3 checks, 501 lines checked
0a707ecdc621 drm/i915/gen7: Clear all EU/L3 residual contexts
-:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#46:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 585 lines checked
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Actually emit the await_start
== Series Details == Series: drm/i915: Actually emit the await_start URL : https://patchwork.freedesktop.org/series/74319/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16836 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16836/index.html Known issues Here are the changes found in Patchwork_16836 that come from known issues: ### IGT changes ### Issues hit * igt@gem_flink_basic@double-flink: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([CI#94] / [i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@gem_flink_ba...@double-flink.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16836/fi-tgl-y/igt@gem_flink_ba...@double-flink.html Possible fixes * igt@kms_addfb_basic@addfb25-modifier-no-flag: - fi-tgl-y: [DMESG-WARN][3] ([CI#94] / [i915#402]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16836/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (49 -> 45) -- Additional (2): fi-kbl-soraka fi-kbl-7560u Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8070 -> Patchwork_16836 CI-20190529: 20190529 CI_DRM_8070: d4e6f8b48e361f0cae9132f50f1778707b2546a2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16836: cb6ff8492eb0da08a771276bab3aa509076748c0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cb6ff8492eb0 drm/i915: Actually emit the await_start == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16836/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] i915/gem_exec_params: add test_invalid_batch
Sanity check that kernel rejects invalid batch_start_offset and
batch_len.
Signed-off-by: Matthew Auld
Cc: Mika Kuoppala
Cc: Chris Wilson
---
tests/i915/gem_exec_params.c | 47
1 file changed, 47 insertions(+)
diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index cf7ea306..45581738 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -268,6 +268,50 @@ static void mmapped(int i915)
gem_close(i915, buf);
}
+static uint32_t batch_create_size(int fd, uint32_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, , sizeof(bbe));
+
+ return handle;
+}
+
+static void __invalid_batch_start(int fd,
+ struct drm_i915_gem_execbuffer2 *execbuf,
+ uint32_t start_offset,
+ uint32_t batch_len)
+{
+ execbuf->batch_start_offset = start_offset;
+ execbuf->batch_len = batch_len;
+ igt_assert_eq(__gem_execbuf(fd, execbuf), -EINVAL);
+}
+
+static void test_invalid_batch_start(int fd)
+{
+ uint32_t size = 4096;
+ struct drm_i915_gem_exec_object2 exec = {
+ .handle = batch_create_size(fd, size),
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(),
+ .buffer_count = 1,
+ };
+
+ __invalid_batch_start(fd, , 0, -1);
+ __invalid_batch_start(fd, , -1, 0);
+ __invalid_batch_start(fd, , -1, -1);
+ __invalid_batch_start(fd, , -1U & ~0x7, 0);
+ __invalid_batch_start(fd, , 0, -1U & ~0x7);
+ __invalid_batch_start(fd, , size, 0);
+ __invalid_batch_start(fd, , size, size);
+
+ gem_sync(fd, exec.handle);
+ gem_close(fd, exec.handle);
+}
+
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 gem_exec[1];
uint32_t batch[2] = {MI_BATCH_BUFFER_END};
@@ -507,6 +551,9 @@ igt_main
igt_subtest("batch-first")
test_batch_first(fd);
+ igt_subtest("invalid-batch-start-offset")
+ test_invalid_batch_start(fd);
+
#define DIRT(name) \
igt_subtest(#name "-dirt") { \
execbuf.flags = 0; \
--
2.20.1
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Actually emit the await_start
== Series Details == Series: drm/i915: Actually emit the await_start URL : https://patchwork.freedesktop.org/series/74319/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/buddy: avoid double list_add
Be careful not to mark an already free node as free again. Signed-off-by: Matthew Auld Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_buddy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_buddy.c b/drivers/gpu/drm/i915/i915_buddy.c index 66883af64ca1..20babbdb297d 100644 --- a/drivers/gpu/drm/i915/i915_buddy.c +++ b/drivers/gpu/drm/i915/i915_buddy.c @@ -312,7 +312,8 @@ i915_buddy_alloc(struct i915_buddy_mm *mm, unsigned int order) return block; out_free: - __i915_buddy_free(mm, block); + if (i != order) + __i915_buddy_free(mm, block); return ERR_PTR(err); } -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/selftests: try to rein in alloc_smoke
Depending on RNG we might try to fill an 8G region for every possible
order, using the smallest possible chunk size of 4K, which seems to be
very slow. Try to remedy the situation by adding an overall timeout for
the test, while also selecting each order level in a random fashion.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1310
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_buddy.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_buddy.c
b/drivers/gpu/drm/i915/selftests/i915_buddy.c
index 1b856bae67b5..939a6caebb03 100644
--- a/drivers/gpu/drm/i915/selftests/i915_buddy.c
+++ b/drivers/gpu/drm/i915/selftests/i915_buddy.c
@@ -298,10 +298,12 @@ static void igt_mm_config(u64 *size, u64 *chunk_size)
static int igt_buddy_alloc_smoke(void *arg)
{
struct i915_buddy_mm mm;
- int max_order;
+ IGT_TIMEOUT(end_time);
+ I915_RND_STATE(prng);
u64 chunk_size;
u64 mm_size;
- int err;
+ int *order;
+ int err, i;
igt_mm_config(_size, _size);
@@ -313,10 +315,16 @@ static int igt_buddy_alloc_smoke(void *arg)
return err;
}
- for (max_order = mm.max_order; max_order >= 0; max_order--) {
+ order = i915_random_order(mm.max_order + 1, );
+ if (!order)
+ goto out_fini;
+
+ for (i = 0; i <= mm.max_order; ++i) {
struct i915_buddy_block *block;
- int order;
+ int max_order = order[i];
+ bool timeout = false;
LIST_HEAD(blocks);
+ int order;
u64 total;
err = igt_check_mm();
@@ -360,6 +368,11 @@ static int igt_buddy_alloc_smoke(void *arg)
}
total += i915_buddy_block_size(, block);
+
+ if (__igt_timeout(end_time, NULL)) {
+ timeout = true;
+ break;
+ }
} while (total < mm.size);
if (!err)
@@ -373,7 +386,7 @@ static int igt_buddy_alloc_smoke(void *arg)
pr_err("post-mm check failed\n");
}
- if (err)
+ if (err || timeout)
break;
cond_resched();
@@ -382,6 +395,8 @@ static int igt_buddy_alloc_smoke(void *arg)
if (err == -ENOMEM)
err = 0;
+ kfree(order);
+out_fini:
i915_buddy_fini();
return err;
--
2.20.1
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[Intel-gfx] [PATCH] drm/i915/phys: unconditionally call release_memory_region
From: Abdiel Janulgue
The release method will undo what we did at creation, and so we
shouldn't care if we have pages or not. Fixes a small leak in the
mock_phys selftest.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index b07bb40edd5a..698e22420dc5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -194,10 +194,11 @@ int i915_gem_object_attach_phys(struct
drm_i915_gem_object *obj, int align)
/* Perma-pin (until release) the physical set of pages */
__i915_gem_object_pin_pages(obj);
- if (!IS_ERR_OR_NULL(pages)) {
+ if (!IS_ERR_OR_NULL(pages))
i915_gem_shmem_ops.put_pages(obj, pages);
- i915_gem_object_release_memory_region(obj);
- }
+
+ i915_gem_object_release_memory_region(obj);
+
mutex_unlock(>mm.lock);
return 0;
--
2.20.1
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[Intel-gfx] [PATCH] drm/i915: be more solid in checking the alignment
The alignment is u64, and yet is_power_of_2() assumes unsigned long,
which might give different results between 32b and 64b kernel.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 ++-
drivers/gpu/drm/i915/i915_utils.h | 5 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 7bb27f382af7..b62576f34a1d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -430,7 +430,8 @@ eb_validate_vma(struct i915_execbuffer *eb,
if (unlikely(entry->flags & eb->invalid_flags))
return -EINVAL;
- if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))
+ if (unlikely(entry->alignment &&
+!is_power_of_2_u64(entry->alignment)))
return -EINVAL;
/*
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index cae0ae520398..024a9e224ff3 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -236,6 +236,11 @@ static inline u64 ptr_to_u64(const void *ptr)
__idx; \
})
+static inline bool is_power_of_2_u64(u64 n)
+{
+ return (n != 0 && ((n & (n - 1)) == 0));
+}
+
static inline void __list_del_many(struct list_head *head,
struct list_head *first)
{
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve the start alignment of bonded pairs
== Series Details == Series: drm/i915: Improve the start alignment of bonded pairs URL : https://patchwork.freedesktop.org/series/74315/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16835 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16835/index.html Known issues Here are the changes found in Patchwork_16835 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [PASS][1] -> [FAIL][2] ([CI#94]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16835/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111096] / [i915#323]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16835/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_vgem@basic-busy-default: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@prime_v...@basic-busy-default.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16835/fi-tgl-y/igt@prime_v...@basic-busy-default.html Possible fixes * igt@kms_addfb_basic@addfb25-modifier-no-flag: - fi-tgl-y: [DMESG-WARN][7] ([CI#94] / [i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16835/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (49 -> 35) -- Missing(14): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-skl-6770hq fi-glk-dsi fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-gdg-551 fi-bsw-kefka fi-blb-e6850 fi-bsw-nick fi-bdw-samus fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8070 -> Patchwork_16835 CI-20190529: 20190529 CI_DRM_8070: d4e6f8b48e361f0cae9132f50f1778707b2546a2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16835: 8a1189eb3710e14e381d51497f6d5a13bdc0a66d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8a1189eb3710 drm/i915: Improve the start alignment of bonded pairs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16835/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Enable timeslice on partial virtual engine dequeue
== Series Details == Series: drm/i915/execlists: Enable timeslice on partial virtual engine dequeue URL : https://patchwork.freedesktop.org/series/74304/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16833 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16833/index.html Known issues Here are the changes found in Patchwork_16833 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [PASS][1] -> [FAIL][2] ([CI#94]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16833/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live@gem_contexts: - fi-skl-lmem:[PASS][3] -> [INCOMPLETE][4] ([i915#424]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16833/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html * igt@prime_self_import@basic-llseek-size: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16833/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html Possible fixes * igt@kms_addfb_basic@addfb25-modifier-no-flag: - fi-tgl-y: [DMESG-WARN][7] ([CI#94] / [i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16833/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 Participating hosts (49 -> 42) -- Additional (2): fi-kbl-soraka fi-kbl-7560u Missing(9): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bwr-2160 fi-ilk-650 fi-ctg-p8600 fi-cfl-8109u fi-bdw-samus fi-skl-6600u Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8070 -> Patchwork_16833 CI-20190529: 20190529 CI_DRM_8070: d4e6f8b48e361f0cae9132f50f1778707b2546a2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16833: 4fce90bf1b0a9a7eb1476ba2c22eec45354ff88c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4fce90bf1b0a drm/i915/execlists: Enable timeslice on partial virtual engine dequeue == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16833/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: properly sanity check batch_start_offset
Check the edge case where batch_start_offset sits exactly on the batch
size.
v2: add new range_overflows variant to capture the special case where
the size is permitted to be zero, like with batch_len.
Testcase: igt/gem_exec_params/invalid-batch-start-offset
Fixes: 0b5372727be3 ("drm/i915/cmdparser: Use cached vmappings")
Signed-off-by: Matthew Auld
Cc: Mika Kuoppala
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 +++---
drivers/gpu/drm/i915/i915_utils.h | 12
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 7bb27f382af7..43c05034ddb0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2714,9 +2714,9 @@ i915_gem_do_execbuffer(struct drm_device *dev,
goto err_vma;
}
- if (range_overflows_t(u64,
- eb.batch_start_offset, eb.batch_len,
- eb.batch->vma->size)) {
+ if (range_overflows_end_t(u64,
+ eb.batch_start_offset, eb.batch_len,
+ eb.batch->vma->size)) {
drm_dbg(>drm, "Attempting to use out-of-bounds batch\n");
err = -EINVAL;
goto err_vma;
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index cae0ae520398..4cb74564e2dd 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -108,6 +108,18 @@ bool i915_error_injected(void);
#define range_overflows_t(type, start, size, max) \
range_overflows((type)(start), (type)(size), (type)(max))
+#define range_overflows_end(start, size, max) ({ \
+ typeof(start) start__ = (start); \
+ typeof(size) size__ = (size); \
+ typeof(max) max__ = (max); \
+ (void)(__ == __); \
+ (void)(__ == __); \
+ start__ >= max__ || size__ > max__ - start__; \
+})
+
+#define range_overflows_end_t(type, start, size, max) \
+ range_overflows_end((type)(start), (type)(size), (type)(max))
+
/* Note we don't consider signbits :| */
#define overflows_type(x, T) \
(sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
--
2.20.1
___
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[Intel-gfx] [PATCH] drm/i915/tgl: Don't treat unslice registers as masked
The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 registers
that we update in a few engine workarounds are not masked registers
(i.e., we don't have to write a mask bit in the top 16 bits when
updating one of the lower 16 bits). As such, these workarounds should
be applied via wa_write_or() rather than wa_masked_en()
Reported-by: Nick Desaulniers
Fixes: 50148a25f841 ("drm/i915/tgl: Move and restrict Wa_1408615072")
Fixes: 3551ff928744 ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()")
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 908a70914399..b4785212fb7d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1382,8 +1382,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
/* Wa_1408615072:tgl */
- wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
-VSUNIT_CLKGATE_DIS_TGL);
+ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
+ VSUNIT_CLKGATE_DIS_TGL);
}
if (IS_TIGERLAKE(i915)) {
@@ -1467,12 +1467,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
* Wa_1408615072:icl,ehl (vsunit)
* Wa_1407596294:icl,ehl (hsunit)
*/
- wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
-VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
+ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
+ VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
/* Wa_1407352427:icl,ehl */
- wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
-PSDUNIT_CLKGATE_DIS);
+ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
+ PSDUNIT_CLKGATE_DIS);
/* Wa_1406680159:icl,ehl */
wa_write_or(wal,
--
2.24.1
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Improve the start alignment of bonded pairs
== Series Details == Series: drm/i915: Improve the start alignment of bonded pairs URL : https://patchwork.freedesktop.org/series/74315/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 14/16] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message
From: Sean Paul
Used to query whether an MST stream is encrypted or not.
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-s...@poorly.run
#v4
Changes in v4:
-Added to the set
Changes in v5:
-None
---
drivers/gpu/drm/drm_dp_mst_topology.c | 117 ++
include/drm/drm_dp_helper.h | 3 +
include/drm/drm_dp_mst_helper.h | 44 ++
3 files changed, 164 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 6c62ad8f44142..5bba5aac86f31 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include
@@ -418,6 +419,22 @@ drm_dp_encode_sideband_req(const struct
drm_dp_sideband_msg_req_body *req,
memcpy([idx], req->u.i2c_write.bytes,
req->u.i2c_write.num_bytes);
idx += req->u.i2c_write.num_bytes;
break;
+ case DP_QUERY_STREAM_ENC_STATUS: {
+ const struct drm_dp_query_stream_enc_status *msg;
+
+ msg = >u.enc_status;
+ buf[idx] = msg->stream_id;
+ idx++;
+ memcpy([idx], msg->client_id, sizeof(msg->client_id));
+ idx += sizeof(msg->client_id);
+ buf[idx] = 0;
+ buf[idx] |= msg->stream_event & GENMASK(1, 0);
+ buf[idx] |= msg->valid_stream_event ? BIT(2) : 0;
+ buf[idx] |= (msg->stream_behavior & GENMASK(1, 0)) << 3;
+ buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0;
+ idx++;
+ }
+ break;
}
raw->cur_len = idx;
}
@@ -930,6 +947,34 @@ static bool
drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms
return true;
}
+static bool
+drm_dp_sideband_parse_query_stream_enc_status(
+ struct drm_dp_sideband_msg_rx *raw,
+ struct drm_dp_sideband_msg_reply_body *repmsg)
+{
+ struct drm_dp_query_stream_enc_status_ack_reply *reply;
+
+ reply = >u.enc_status;
+
+ reply->stream_id = raw->msg[3];
+
+ reply->reply_signed = raw->msg[2] & BIT(0);
+
+ reply->hdcp_1x_device_present = raw->msg[2] & BIT(3);
+ reply->hdcp_2x_device_present = raw->msg[2] & BIT(4);
+
+ reply->query_capable_device_present = raw->msg[2] & BIT(5);
+ reply->legacy_device_present = raw->msg[2] & BIT(6);
+ reply->unauthorizable_device_present = raw->msg[2] & BIT(7);
+
+ reply->auth_completed = !!(raw->msg[1] & BIT(3));
+ reply->encryption_enabled = !!(raw->msg[1] & BIT(4));
+ reply->repeater_present = !!(raw->msg[1] & BIT(5));
+ reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6;
+
+ return true;
+}
+
static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw,
struct drm_dp_sideband_msg_reply_body
*msg)
{
@@ -964,6 +1009,8 @@ static bool drm_dp_sideband_parse_reply(struct
drm_dp_sideband_msg_rx *raw,
return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg);
case DP_CLEAR_PAYLOAD_ID_TABLE:
return true; /* since there's nothing to parse */
+ case DP_QUERY_STREAM_ENC_STATUS:
+ return drm_dp_sideband_parse_query_stream_enc_status(raw, msg);
default:
DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type,
drm_dp_mst_req_type_str(msg->req_type));
@@ -1115,6 +1162,25 @@ static void build_power_updown_phy(struct
drm_dp_sideband_msg_tx *msg,
msg->path_msg = true;
}
+static int
+build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8 stream_id,
+ u8 *q_id)
+{
+ struct drm_dp_sideband_msg_req_body req;
+
+ req.req_type = DP_QUERY_STREAM_ENC_STATUS;
+ req.u.enc_status.stream_id = stream_id;
+ memcpy(req.u.enc_status.client_id, q_id,
+ sizeof(req.u.enc_status.client_id));
+ req.u.enc_status.stream_event = 0;
+ req.u.enc_status.valid_stream_event = false;
+ req.u.enc_status.stream_behavior = 0;
+ req.u.enc_status.valid_stream_behavior = false;
+
+ drm_dp_encode_sideband_req(, msg);
+ return 0;
+}
+
static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_vcpi *vcpi)
{
@@ -3151,6 +3217,57 @@ int drm_dp_send_power_updown_phy(struct
drm_dp_mst_topology_mgr *mgr,
}
EXPORT_SYMBOL(drm_dp_send_power_updown_phy);
+int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_query_stream_enc_status_ack_reply *status)
+{
+ struct drm_dp_sideband_msg_tx *txmsg;
+ u8 nonce[7];
+ int len, ret;
+
+
[Intel-gfx] [PATCH v5 12/16] drm/i915: Plumb port through hdcp init
From: Sean Paul
This patch plumbs port through hdcp init instead of relying on
intel_attached_encoder() to return a non-NULL encoder which won't work
for MST connectors.
Cc: Ville Syrjälä
Signed-off-by: Sean Paul
Changes in v5:
-Added to the set
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c| 11 ++-
drivers/gpu/drm/i915/display/intel_hdcp.h| 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
4 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index f41fe9e9d6f89..abcb53975e0d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -601,7 +601,8 @@ int intel_dp_init_hdcp(struct intel_digital_port
*intel_dig_port,
return 0;
if (!intel_dp_is_edp(intel_dp))
- return intel_hdcp_init(intel_connector, _dp_hdcp_shim);
+ return intel_hdcp_init(intel_connector, port,
+ _dp_hdcp_shim);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 0ee29f88bab2d..fc3ce7586084c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1959,6 +1959,7 @@ enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder
cpu_transcoder)
}
static inline int initialize_hdcp_port_data(struct intel_connector *connector,
+ enum port port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -1966,8 +1967,7 @@ static inline int initialize_hdcp_port_data(struct
intel_connector *connector,
struct hdcp_port_data *data = >port_data;
if (INTEL_GEN(dev_priv) < 12)
- data->fw_ddi =
-
intel_get_mei_fw_ddi_index(intel_attached_encoder(connector)->port);
+ data->fw_ddi = intel_get_mei_fw_ddi_index(port);
else
/*
* As per ME FW API expectation, for GEN 12+, fw_ddi is filled
@@ -2034,14 +2034,14 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector,
+static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = >hdcp;
int ret;
- ret = initialize_hdcp_port_data(connector, shim);
+ ret = initialize_hdcp_port_data(connector, port, shim);
if (ret) {
drm_dbg_kms(>drm, "Mei hdcp data init failed\n");
return;
@@ -2051,6 +2051,7 @@ static void intel_hdcp2_init(struct intel_connector
*connector,
}
int intel_hdcp_init(struct intel_connector *connector,
+ enum port port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -2061,7 +2062,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return -EINVAL;
if (is_hdcp2_supported(dev_priv))
- intel_hdcp2_init(connector, shim);
+ intel_hdcp2_init(connector, port, shim);
ret =
drm_connector_attach_content_protection_property(>base,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 7c12ad609b1fe..713dc20853745 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -21,7 +21,7 @@ enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
-int intel_hdcp_init(struct intel_connector *connector,
+int intel_hdcp_init(struct intel_connector *connector, enum port port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
enum transcoder cpu_transcoder, u8 content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 29149b59f9e40..8b32c3c986bca 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3189,7 +3189,7 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
intel_hdmi->attached_connector = intel_connector;
if (is_hdcp_supported(dev_priv, port)) {
- int ret = intel_hdcp_init(intel_connector,
+ int ret = intel_hdcp_init(intel_connector, port,
[Intel-gfx] [PATCH v5 16/16] drm/i915: Add HDCP 1.4 support for MST connectors
From: Sean Paul
Now that all the groundwork has been laid, we can turn on HDCP 1.4 over
MST. Everything except for toggling the HDCP signalling and HDCP 2.2
support is the same as the DP case, so we'll re-use those callbacks
Cc: Juston Li
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-12-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-13-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-13-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-15-s...@poorly.run
#v4
Changes in v2:
-Toggle HDCP from encoder disable/enable
-Don't disable HDCP on MST connector destroy, leave that for encoder
disable, just ensure the check_work routine isn't running any longer
Changes in v3:
-Place the shim in the new intel_dp_hdcp.c file (Ville)
Changes in v4:
-Actually use the mst shim for mst connections (Juston)
-Use QUERY_STREAM_ENC_STATUS MST message to verify channel is encrypted
Changes in v5:
-Add sleep on disable signalling to match hdmi delay
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 105 ++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++
2 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 549f02f622b45..69b5412736467 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -7,10 +7,12 @@
*/
#include
+#include
#include
#include
#include "intel_display_types.h"
+#include "intel_ddi.h"
#include "intel_dp.h"
#include "intel_hdcp.h"
@@ -589,6 +591,104 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
.protocol = HDCP_PROTOCOL_DP,
};
+static int
+intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
+ enum transcoder cpu_transcoder,
+ bool enable)
+{
+ int ret;
+
+ if (!enable)
+ usleep_range(6, 60); /* Bspec says >= 6us */
+
+ ret = intel_ddi_toggle_hdcp_signalling(_dig_port->base,
+ cpu_transcoder, enable);
+ if (ret)
+ DRM_DEBUG_KMS("%s HDCP signalling failed (%d)\n",
+ enable ? "Enable" : "Disable", ret);
+ return ret;
+}
+
+static
+int intel_dp_mst_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
+void *buf, size_t size)
+{
+ return -EOPNOTSUPP;
+}
+
+static
+int intel_dp_mst_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
+ u8 msg_id, void *buf, size_t size)
+{
+ return -EOPNOTSUPP;
+}
+
+static int
+intel_dp_mst_hdcp2_config_stream_type(struct intel_digital_port
*intel_dig_port,
+ bool is_repeater, u8 content_type)
+{
+ return -EOPNOTSUPP;
+}
+
+static
+int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
+{
+ return -EOPNOTSUPP;
+}
+
+static
+int intel_dp_mst_hdcp2_capable(struct intel_digital_port *intel_dig_port,
+ bool *capable)
+{
+ *capable = false;
+ return 0;
+}
+
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *connector)
+{
+ struct intel_dp *intel_dp = _dig_port->dp;
+ struct drm_dp_query_stream_enc_status_ack_reply reply;
+ int ret;
+
+ if (!intel_dp_hdcp_check_link(intel_dig_port, connector))
+ return false;
+
+ ret = drm_dp_send_query_stream_enc_status(_dp->mst_mgr,
+ connector->port, );
+ if (ret) {
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] failed QSES ret=%d\n",
+ connector->base.base.id, connector->base.name,
+ ret);
+ return false;
+ }
+
+ return reply.auth_completed && reply.encryption_enabled;
+}
+
+static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
+ .write_an_aksv = intel_dp_hdcp_write_an_aksv,
+ .read_bksv = intel_dp_hdcp_read_bksv,
+ .read_bstatus = intel_dp_hdcp_read_bstatus,
+ .repeater_present = intel_dp_hdcp_repeater_present,
+ .read_ri_prime = intel_dp_hdcp_read_ri_prime,
+ .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
+ .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
+ .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
+ .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
+ .check_link = intel_dp_mst_hdcp_check_link,
+ .hdcp_capable = intel_dp_hdcp_capable,
+
+ .write_2_2_msg = intel_dp_mst_hdcp2_write_msg,
+ .read_2_2_msg = intel_dp_mst_hdcp2_read_msg,
+
[Intel-gfx] [PATCH v5 13/16] drm/i915: Add connector to hdcp_shim->check_link()
From: Sean Paul
Currently we derive the connector from digital port in check_link(). For
MST, this isn't sufficient since the digital port passed into the
function can have multiple connectors downstream. This patch adds
connector to the check_link() arguments so we have it when we need it.
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-13-s...@poorly.run
# v4
Changes in v4:
-Added to the set
Changes in v5:
-None
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 ++---
4 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3cac51955f250..9cc43dcbb518f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -312,7 +312,8 @@ struct intel_hdcp_shim {
bool enable);
/* Ensures the link is still protected */
- bool (*check_link)(struct intel_digital_port *intel_dig_port);
+ bool (*check_link)(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *connector);
/* Detects panel's hdcp capability. This is optional for HDMI. */
int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index abcb53975e0d5..549f02f622b45 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -538,7 +538,8 @@ int intel_dp_hdcp_toggle_signalling(struct
intel_digital_port *intel_dig_port,
}
static
-bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
+bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *connector)
{
ssize_t ret;
u8 bstatus;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index fc3ce7586084c..e0418ad202d1f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -956,7 +956,7 @@ static int intel_hdcp_check_link(struct intel_connector
*connector)
goto out;
}
- if (hdcp->shim->check_link(intel_dig_port)) {
+ if (hdcp->shim->check_link(intel_dig_port, connector)) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
intel_hdcp_update_value(connector,
DRM_MODE_CONTENT_PROTECTION_ENABLED, true);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 8b32c3c986bca..288525a9fdf7c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1522,11 +1522,10 @@ int intel_hdmi_hdcp_toggle_signalling(struct
intel_digital_port *intel_dig_port,
}
static
-bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
+bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
- struct intel_connector *connector =
- intel_dig_port->hdmi.attached_connector;
enum port port = intel_dig_port->base.port;
enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
int ret;
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] [PATCH v5 03/16] drm/i915: WARN if HDCP signalling is enabled upon disable
From: Sean Paul
HDCP signalling should not be left on, WARN if it is
Cc: Ville Syrjälä
Cc: Daniel Vetter
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-4-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-4-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-4-s...@poorly.run
#v4
Changes in v2:
-Added to the set in lieu of just clearing the bit
Changes in v3:
-None
Changes in v4:
-None
Changes in v5:
-Change WARN_ON to drm_WARN_ON
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 73d0f4648c06a..4aff5717e9428 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1593,6 +1593,8 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
val = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
val &= ~TRANS_DDI_FUNC_ENABLE;
+ drm_WARN_ON(crtc->base.dev, val & TRANS_DDI_HDCP_SIGNALLING);
+
if (INTEL_GEN(dev_priv) >= 12) {
if (!intel_dp_mst_is_master_trans(crtc_state)) {
val &= ~(TGL_TRANS_DDI_PORT_MASK |
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] [PATCH v5 06/16] drm/i915: Factor out hdcp->value assignments
From: Sean Paul
This is a bit of housecleaning for a future patch. Instead of sprinkling
hdcp->value assignments and prop_work scheduling everywhere, introduce a
function to do it for us.
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-7-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-7-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-7-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-7-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-Rebased on top of drm_* logging changes
Changes in v5:
-Change WARN_ON to drm_WARN_ON
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 67 ---
1 file changed, 46 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index d61bfea3fd28f..dfa792ee90ecd 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -880,6 +880,21 @@ struct intel_connector *intel_hdcp_to_connector(struct
intel_hdcp *hdcp)
return container_of(hdcp, struct intel_connector, hdcp);
}
+static void intel_hdcp_update_value(struct intel_connector *connector,
+ u64 value, bool update_property)
+{
+ struct intel_hdcp *hdcp = >hdcp;
+
+ drm_WARN_ON(connector->base.dev, !mutex_is_locked(>mutex));
+
+ if (hdcp->value == value)
+ return;
+
+ hdcp->value = value;
+ if (update_property)
+ schedule_work(>prop_work);
+}
+
/* Implements Part 3 of the HDCP authorization procedure */
static int intel_hdcp_check_link(struct intel_connector *connector)
{
@@ -907,15 +922,16 @@ static int intel_hdcp_check_link(struct intel_connector
*connector)
connector->base.name, connector->base.base.id,
intel_de_read(dev_priv, HDCP_STATUS(dev_priv,
cpu_transcoder, port)));
ret = -ENXIO;
- hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
- schedule_work(>prop_work);
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_DESIRED,
+ true);
goto out;
}
if (hdcp->shim->check_link(intel_dig_port)) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
- hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
- schedule_work(>prop_work);
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_ENABLED, true);
}
goto out;
}
@@ -927,16 +943,18 @@ static int intel_hdcp_check_link(struct intel_connector
*connector)
ret = _intel_hdcp_disable(connector);
if (ret) {
drm_err(_priv->drm, "Failed to disable hdcp (%d)\n", ret);
- hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
- schedule_work(>prop_work);
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_DESIRED,
+ true);
goto out;
}
ret = _intel_hdcp_enable(connector);
if (ret) {
drm_err(_priv->drm, "Failed to enable hdcp (%d)\n", ret);
- hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
- schedule_work(>prop_work);
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_DESIRED,
+ true);
goto out;
}
@@ -1771,16 +1789,18 @@ static int intel_hdcp2_check_link(struct
intel_connector *connector)
"HDCP2.2 link stopped the encryption, %x\n",
intel_de_read(dev_priv, HDCP2_STATUS(dev_priv,
cpu_transcoder, port)));
ret = -ENXIO;
- hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
- schedule_work(>prop_work);
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_DESIRED,
+ true);
goto out;
}
ret = hdcp->shim->check_2_2_link(intel_dig_port);
if (ret == HDCP_LINK_PROTECTED) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
- hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
- schedule_work(>prop_work);
+ intel_hdcp_update_value(connector,
+ DRM_MODE_CONTENT_PROTECTION_ENABLED,
+
[Intel-gfx] [PATCH v5 07/16] drm/i915: Protect workers against disappearing connectors
From: Sean Paul
This patch adds some protection against connectors being destroyed
before the HDCP workers are finished.
For check_work, we do a synchronous cancel after the connector is
unregistered which will ensure that it is finished before destruction.
In the case of prop_work, we can't do a synchronous wait since it needs
to take connection_mutex which could cause deadlock. Instead, we'll take
a reference on the connector when scheduling prop_work and give it up
once we're done.
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-8-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-8-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-8-s...@poorly.run
#v4
Changes in v2:
-Added to the set
Changes in v3:
-Change the WARN_ON condition in intel_hdcp_cleanup to allow for
initializing connectors as well
Changes in v4:
-None
Changes in v5:
-Change WARN_ON to drm_WARN_ON
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 44 ---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index dfa792ee90ecd..9523ab6c65e0d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -891,8 +891,10 @@ static void intel_hdcp_update_value(struct intel_connector
*connector,
return;
hdcp->value = value;
- if (update_property)
+ if (update_property) {
+ drm_connector_get(>base);
schedule_work(>prop_work);
+ }
}
/* Implements Part 3 of the HDCP authorization procedure */
@@ -984,6 +986,8 @@ static void intel_hdcp_prop_work(struct work_struct *work)
mutex_unlock(>mutex);
drm_modeset_unlock(_priv->drm.mode_config.connection_mutex);
+
+ drm_connector_put(>base);
}
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
@@ -1862,6 +1866,9 @@ static void intel_hdcp_check_work(struct work_struct
*work)
check_work);
struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
+ if (drm_connector_is_unregistered(>base))
+ return;
+
if (!intel_hdcp2_check_link(connector))
schedule_delayed_work(>check_work,
DRM_HDCP2_CHECK_PERIOD_MS);
@@ -2178,12 +2185,39 @@ void intel_hdcp_component_fini(struct drm_i915_private
*dev_priv)
void intel_hdcp_cleanup(struct intel_connector *connector)
{
- if (!connector->hdcp.shim)
+ struct intel_hdcp *hdcp = >hdcp;
+
+ if (!hdcp->shim)
return;
- mutex_lock(>hdcp.mutex);
- kfree(connector->hdcp.port_data.streams);
- mutex_unlock(>hdcp.mutex);
+ /*
+* If the connector is registered, it's possible userspace could kick
+* off another HDCP enable, which would re-spawn the workers.
+*/
+ drm_WARN_ON(connector->base.dev,
+ connector->base.registration_state == DRM_CONNECTOR_REGISTERED);
+
+ /*
+* Now that the connector is not registered, check_work won't be run,
+* but cancel any outstanding instances of it
+*/
+ cancel_delayed_work_sync(>check_work);
+
+ /*
+* We don't cancel prop_work in the same way as check_work since it
+* requires connection_mutex which could be held while calling this
+* function. Instead, we rely on the connector references grabbed before
+* scheduling prop_work to ensure the connector is alive when prop_work
+* is run. So if we're in the destroy path (which is where this
+* function should be called), we're "guaranteed" that prop_work is not
+* active (tl;dr This Should Never Happen).
+*/
+ drm_WARN_ON(connector->base.dev, work_pending(>prop_work));
+
+ mutex_lock(>mutex);
+ kfree(hdcp->port_data.streams);
+ hdcp->shim = NULL;
+ mutex_unlock(>mutex);
}
void intel_hdcp_atomic_check(struct drm_connector *connector,
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] [PATCH v5 11/16] drm/i915: Factor out HDCP shim functions from dp for use by dp_mst
From: Sean Paul
These functions are all the same for dp and dp_mst, so move them into a
dedicated file for both sst and mst to use.
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-11-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-12-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-12-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-12-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-Created intel_dp_hdcp.c for the shared functions to live (Ville)
Changes in v4:
-Rebased on new drm logging change
Changes in v5:
-None
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 585 +-
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 607 +++
4 files changed, 615 insertions(+), 581 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_hdcp.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 991a8c537d123..cb4a7f137c0d9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -225,6 +225,7 @@ i915-y += \
display/intel_ddi.o \
display/intel_dp.o \
display/intel_dp_aux_backlight.o \
+ display/intel_dp_hdcp.o \
display/intel_dp_link_training.o \
display/intel_dp_mst.o \
display/intel_dsi.o \
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4a38012a1fb03..306e4ccac5bb4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5958,580 +5958,6 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
edp_panel_vdd_off_sync(intel_dp);
}
-static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
-{
- long ret;
-
-#define C (hdcp->cp_irq_count_cached != atomic_read(>cp_irq_count))
- ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
- msecs_to_jiffies(timeout));
-
- if (!ret)
- DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
-}
-
-static
-int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
- u8 *an)
-{
- u8 aksv[DRM_HDCP_KSV_LEN] = {};
- ssize_t dpcd_ret;
-
- dpcd_ret = drm_dp_dpcd_write(_dig_port->dp.aux, DP_AUX_HDCP_AN,
-an, DRM_HDCP_AN_LEN);
- if (dpcd_ret != DRM_HDCP_AN_LEN) {
- DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
- dpcd_ret);
- return dpcd_ret >= 0 ? -EIO : dpcd_ret;
- }
-
- /*
-* Since Aksv is Oh-So-Secret, we can't access it in software. So we
-* send an empty buffer of the correct length through the DP helpers. On
-* the other side, in the transfer hook, we'll generate a flag based on
-* the destination address which will tickle the hardware to output the
-* Aksv on our behalf after the header is sent.
-*/
- dpcd_ret = drm_dp_dpcd_write(_dig_port->dp.aux, DP_AUX_HDCP_AKSV,
-aksv, DRM_HDCP_KSV_LEN);
- if (dpcd_ret != DRM_HDCP_KSV_LEN) {
- DRM_DEBUG_KMS("Failed to write Aksv over DP/AUX (%zd)\n",
- dpcd_ret);
- return dpcd_ret >= 0 ? -EIO : dpcd_ret;
- }
- return 0;
-}
-
-static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
- u8 *bksv)
-{
- ssize_t ret;
- ret = drm_dp_dpcd_read(_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
- DRM_HDCP_KSV_LEN);
- if (ret != DRM_HDCP_KSV_LEN) {
- DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
- return ret >= 0 ? -EIO : ret;
- }
- return 0;
-}
-
-static int intel_dp_hdcp_read_bstatus(struct intel_digital_port
*intel_dig_port,
- u8 *bstatus)
-{
- ssize_t ret;
- /*
-* For some reason the HDMI and DP HDCP specs call this register
-* definition by different names. In the HDMI spec, it's called BSTATUS,
-* but in DP it's called BINFO.
-*/
- ret = drm_dp_dpcd_read(_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
- bstatus, DRM_HDCP_BSTATUS_LEN);
- if (ret != DRM_HDCP_BSTATUS_LEN) {
- DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
- return ret >= 0 ? -EIO : ret;
- }
- return 0;
-}
-
-static
-int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
-u8 *bcaps)
-{
-
[Intel-gfx] [PATCH v5 05/16] drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signalling
From: Sean Paul
Instead of using intel_dig_port's encoder pipe to determine which
transcoder to toggle signalling on, use the cpu_transcoder field already
stored in intel_hdmi.
This is particularly important for MST.
Suggested-by: Ville Syrjälä
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-6-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-6-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-6-s...@poorly.run
#v4
Changes in v2:
-Added to the set
Changes in v3:
-s/hdcp/hdmi/ in commit msg (Ram)
Changes in v4:
-Rebased on intel_de_(read|write) change
Changes in v5:
-Update hdcp->cpu_transcoder in intel_hdcp_enable so it works with pipe != 0
---
drivers/gpu/drm/i915/display/intel_ddi.c | 13 +++--
drivers/gpu/drm/i915/display/intel_ddi.h | 2 ++
.../gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/display/intel_hdcp.c| 16 +---
drivers/gpu/drm/i915/display/intel_hdmi.c| 16 +++-
6 files changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4aff5717e9428..d27f74c8f55d0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1614,12 +1614,12 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
}
int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
+enum transcoder cpu_transcoder,
bool enable)
{
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
intel_wakeref_t wakeref;
- enum pipe pipe = 0;
int ret = 0;
u32 tmp;
@@ -1628,19 +1628,12 @@ int intel_ddi_toggle_hdcp_signalling(struct
intel_encoder *intel_encoder,
if (drm_WARN_ON(dev, !wakeref))
return -ENXIO;
- if (drm_WARN_ON(dev,
- !intel_encoder->get_hw_state(intel_encoder, ))) {
- ret = -EIO;
- goto out;
- }
-
- tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe));
+ tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (enable)
tmp |= TRANS_DDI_HDCP_SIGNALLING;
else
tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
- intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp);
-out:
+ intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
b/drivers/gpu/drm/i915/display/intel_ddi.h
index 55fd72b901fe4..cd1342a557e4f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -16,6 +16,7 @@ struct intel_crtc_state;
struct intel_dp;
struct intel_dpll_hw_state;
struct intel_encoder;
+enum transcoder;
void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -43,6 +44,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
u8 voltage_swing);
int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
+enum transcoder cpu_transcoder,
bool enable);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5e00e611f077f..bd577f143469c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -308,6 +308,7 @@ struct intel_hdcp_shim {
/* Enables HDCP signalling on the port */
int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
+enum transcoder cpu_transcoder,
bool enable);
/* Ensures the link is still protected */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1f80a1244abbb..b2e92ecd1e0ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6138,6 +6138,7 @@ int intel_dp_hdcp_read_v_prime_part(struct
intel_digital_port *intel_dig_port,
static
int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
+ enum transcoder cpu_transcoder,
[Intel-gfx] [PATCH v5 08/16] drm/i915: Don't fully disable HDCP on a port if multiple pipes are using it
From: Sean Paul
This patch is required for HDCP over MST. If a port is being used for
multiple HDCP streams, we don't want to fully disable HDCP on a port if
one of them is disabled. Instead, we just disable the HDCP signalling on
that particular pipe and exit early. The last pipe to disable HDCP will
also bring down HDCP on the port.
In order to achieve this, we need to keep a refcount in intel_digital_port
and protect it using a new hdcp_mutex.
Cc: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-8-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-9-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-9-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-9-s...@poorly.run
#v4
Changes in v2:
-Move the toggle_signalling call into _intel_hdcp_disable so it's called from
check_work
Changes in v3:
-None
Changes in v4:
-None
Changes in v5:
-Change WARN_ON to drm_WARN_ON
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++
.../drm/i915/display/intel_display_types.h| 5 ++
drivers/gpu/drm/i915/display/intel_dp.c | 2 +
drivers/gpu/drm/i915/display/intel_hdcp.c | 53 +++
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +
5 files changed, 56 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index d27f74c8f55d0..48910a2ce 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4452,6 +4452,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
drm_encoder_init(_priv->drm, >base, _ddi_funcs,
DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
+ mutex_init(_dig_port->hdcp_mutex);
+ intel_dig_port->num_hdcp_streams = 0;
+
encoder->hotplug = intel_ddi_hotplug;
encoder->compute_output_type = intel_ddi_compute_output_type;
encoder->compute_config = intel_ddi_compute_config;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index bd577f143469c..04161993e2038 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1388,6 +1388,11 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
+ /* protects num_hdcp_streams reference count */
+ struct mutex hdcp_mutex;
+ /* the number of pipes using HDCP signalling out of this port */
+ unsigned int num_hdcp_streams;
+
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index b2e92ecd1e0ff..4a38012a1fb03 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7800,6 +7800,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder = _dig_port->base;
encoder = _encoder->base;
+ mutex_init(_dig_port->hdcp_mutex);
+
if (drm_encoder_init(_priv->drm, _encoder->base,
_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
"DP %c", port_name(port)))
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 9523ab6c65e0d..0ee29f88bab2d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -803,6 +803,19 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
drm_dbg_kms(_priv->drm, "[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
+ /*
+* If there are other connectors on this port using HDCP, don't disable
+* it. Instead, toggle the HDCP signalling off on that particular
+* connector/pipe and exit.
+*/
+ if (intel_dig_port->num_hdcp_streams > 0) {
+ ret = hdcp->shim->toggle_signalling(intel_dig_port,
+ cpu_transcoder, false);
+ if (ret)
+ DRM_ERROR("Failed to disable HDCP signalling\n");
+ return ret;
+ }
+
hdcp->hdcp_encrypted = false;
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
if (intel_de_wait_for_clear(dev_priv,
@@ -883,6 +896,8 @@ struct intel_connector *intel_hdcp_to_connector(struct
intel_hdcp *hdcp)
static void intel_hdcp_update_value(struct intel_connector *connector,
u64 value, bool update_property)
{
+ struct drm_device *dev =
[Intel-gfx] [PATCH v5 10/16] drm/i915: Use ddi_update_pipe in intel_dp_mst
From: Sean Paul
In order to act upon content_protection property changes, we'll need to
implement the .update_pipe() hook. We can re-use intel_ddi_update_pipe
for this
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-10-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-11-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-11-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-11-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-None
Changes in v5:
-None
---
drivers/gpu/drm/i915/display/intel_ddi.c| 9 +
drivers/gpu/drm/i915/display/intel_dp.h | 4
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 48910a2ce..149937da20586 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3695,12 +3695,13 @@ static void intel_ddi_update_pipe_dp(struct
intel_encoder *encoder,
intel_panel_update_backlight(encoder, crtc_state, conn_state);
}
-static void intel_ddi_update_pipe(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+void intel_ddi_update_pipe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
- if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+ !intel_encoder_is_mst(encoder))
intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
intel_hdcp_update_pipe(encoder, crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 0c7be8ed1423a..ae4a1517632bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -123,4 +123,8 @@ static inline unsigned int intel_dp_unused_lane_mask(int
lane_count)
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
+void intel_ddi_update_pipe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
+
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 39f5de9a8c7ce..af658c76125c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -787,6 +787,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port
*intel_dig_port, enum
intel_encoder->compute_config = intel_dp_mst_compute_config;
intel_encoder->disable = intel_mst_disable_dp;
intel_encoder->post_disable = intel_mst_post_disable_dp;
+ intel_encoder->update_pipe = intel_ddi_update_pipe;
intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
intel_encoder->pre_enable = intel_mst_pre_enable_dp;
intel_encoder->enable = intel_mst_enable_dp;
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] [PATCH v5 15/16] drm/i915: Print HDCP version info for all connectors
From: Sean Paul
De-duplicate the HDCP version code for each connector and print it for
all connectors.
Cc: Juston Li
Cc: Ramalingam C
Reviewed-by: Juston Li
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20200227185714.171466-1-s...@poorly.run
#v4
Changes in v4:
- Added to the set
Changes in v5:
-Print "No connector support" for hdcp sink capability as well (Ram)
---
.../drm/i915/display/intel_display_debugfs.c | 21 ---
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 1e6eb7f2f72db..25f03da30ed49 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -597,6 +597,11 @@ static void intel_hdcp_info(struct seq_file *m,
{
bool hdcp_cap, hdcp2_cap;
+ if (!intel_connector->hdcp.shim) {
+ seq_puts(m, "No Connector Support");
+ goto out;
+ }
+
hdcp_cap = intel_hdcp_capable(intel_connector);
hdcp2_cap = intel_hdcp2_capable(intel_connector);
@@ -608,6 +613,7 @@ static void intel_hdcp_info(struct seq_file *m,
if (!hdcp_cap && !hdcp2_cap)
seq_puts(m, "None");
+out:
seq_puts(m, "\n");
}
@@ -624,10 +630,6 @@ static void intel_dp_info(struct seq_file *m,
drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
_dp->aux);
- if (intel_connector->hdcp.shim) {
- seq_puts(m, "\tHDCP version: ");
- intel_hdcp_info(m, intel_connector);
- }
}
static void intel_dp_mst_info(struct seq_file *m,
@@ -651,10 +653,6 @@ static void intel_hdmi_info(struct seq_file *m,
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder);
seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
- if (intel_connector->hdcp.shim) {
- seq_puts(m, "\tHDCP version: ");
- intel_hdcp_info(m, intel_connector);
- }
}
static void intel_lvds_info(struct seq_file *m,
@@ -710,6 +708,9 @@ static void intel_connector_info(struct seq_file *m,
break;
}
+ seq_puts(m, "\tHDCP version: ");
+ intel_hdcp_info(m, intel_connector);
+
seq_printf(m, "\tmodes:\n");
list_for_each_entry(mode, >modes, head)
intel_seq_print_mode(m, 2, mode);
@@ -1975,10 +1976,6 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
if (connector->status != connector_status_connected)
return -ENODEV;
- /* HDCP is supported by connector */
- if (!intel_connector->hdcp.shim)
- return -EINVAL;
-
seq_printf(m, "%s:%d HDCP version: ", connector->name,
connector->base.id);
intel_hdcp_info(m, intel_connector);
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] [PATCH v5 00/16] drm/i915: Add support for HDCP 1.4 over MST connectors
From: Sean Paul Hello friends, Another version of HDCP over MST rebased on -tip (pls stop refactoring stuff!). I've also added a couple of fixes to fix bugs found when I did some testing I on a non-CrOS laptop. PTAL, Sean Sean Paul (16): drm/i915: Fix sha_text population code drm/i915: Clear the repeater bit on HDCP disable drm/i915: WARN if HDCP signalling is enabled upon disable drm/i915: Intercept Aksv writes in the aux hooks drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signalling drm/i915: Factor out hdcp->value assignments drm/i915: Protect workers against disappearing connectors drm/i915: Don't fully disable HDCP on a port if multiple pipes are using it drm/i915: Support DP MST in enc_to_dig_port() function drm/i915: Use ddi_update_pipe in intel_dp_mst drm/i915: Factor out HDCP shim functions from dp for use by dp_mst drm/i915: Plumb port through hdcp init drm/i915: Add connector to hdcp_shim->check_link() drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message drm/i915: Print HDCP version info for all connectors drm/i915: Add HDCP 1.4 support for MST connectors drivers/gpu/drm/drm_dp_mst_topology.c | 117 +++ drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 27 +- drivers/gpu/drm/i915/display/intel_ddi.h | 2 + .../drm/i915/display/intel_display_debugfs.c | 21 +- .../drm/i915/display/intel_display_types.h| 30 +- drivers/gpu/drm/i915/display/intel_dp.c | 624 +-- drivers/gpu/drm/i915/display/intel_dp.h | 7 + drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 712 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 + drivers/gpu/drm/i915/display/intel_hdcp.c | 217 -- drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +- include/drm/drm_dp_helper.h | 3 + include/drm/drm_dp_mst_helper.h | 44 ++ include/drm/drm_hdcp.h| 3 + 16 files changed, 1155 insertions(+), 695 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dp_hdcp.c -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 09/16] drm/i915: Support DP MST in enc_to_dig_port() function
From: Sean Paul
Although DP_MST fake encoders are not subclassed from digital ports,
they are associated with them. Support these encoders.
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-9-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-10-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-10-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-10-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-None
Changes in v5:
-None
---
.../drm/i915/display/intel_display_types.h| 21 ---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 04161993e2038..3cac51955f250 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1502,6 +1502,18 @@ static inline bool intel_encoder_is_dig_port(struct
intel_encoder *encoder)
}
}
+static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
+{
+ return encoder->type == INTEL_OUTPUT_DP_MST;
+}
+
+static inline struct intel_dp_mst_encoder *
+enc_to_mst(struct intel_encoder *encoder)
+{
+ return container_of(>base, struct intel_dp_mst_encoder,
+ base.base);
+}
+
static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder *encoder)
{
@@ -1510,6 +1522,8 @@ enc_to_dig_port(struct intel_encoder *encoder)
if (intel_encoder_is_dig_port(intel_encoder))
return container_of(>base, struct intel_digital_port,
base.base);
+ else if (intel_encoder_is_mst(intel_encoder))
+ return enc_to_mst(encoder)->primary;
else
return NULL;
}
@@ -1520,13 +1534,6 @@ intel_attached_dig_port(struct intel_connector
*connector)
return enc_to_dig_port(intel_attached_encoder(connector));
}
-static inline struct intel_dp_mst_encoder *
-enc_to_mst(struct intel_encoder *encoder)
-{
- return container_of(>base, struct intel_dp_mst_encoder,
- base.base);
-}
-
static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
{
return _to_dig_port(encoder)->dp;
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] [PATCH v5 02/16] drm/i915: Clear the repeater bit on HDCP disable
From: Sean Paul
On HDCP disable, clear the repeater bit. This ensures if we connect a
non-repeater sink after a repeater, the bit is in the state we expect.
Fixes: ee5e5e7a5e0f (drm/i915: Add HDCP framework + base implementation)
Cc: Chris Wilson
Cc: Ramalingam C
Cc: Daniel Vetter
Cc: Sean Paul
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: intel-gfx@lists.freedesktop.org
Cc: # v4.17+
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-3-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-3-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-3-s...@poorly.run
#v4
Changes in v2:
-Added to the set
Changes in v3:
-None
I had previously agreed that clearing the rep_ctl bits on enable would
also be a good idea. However when I committed that idea to code, it
didn't look right. So let's rely on enables and disables being paired
and everything outside of that will be considered a bug
Changes in v4:
-s/I915_(READ|WRITE)/intel_de_(read|write)/
Changes in v5:
-None
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index defa8654e7ac5..553f5ff617a15 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -797,6 +797,7 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
struct intel_hdcp *hdcp = >hdcp;
enum port port = intel_dig_port->base.port;
enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ u32 repeater_ctl;
int ret;
drm_dbg_kms(_priv->drm, "[%s:%d] HDCP is being disabled...\n",
@@ -812,6 +813,11 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
return -ETIMEDOUT;
}
+ repeater_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder,
+ port);
+ intel_de_write(dev_priv, HDCP_REP_CTL,
+ intel_de_read(dev_priv, HDCP_REP_CTL) & ~repeater_ctl);
+
ret = hdcp->shim->toggle_signalling(intel_dig_port, false);
if (ret) {
drm_err(_priv->drm, "Failed to disable HDCP signalling\n");
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] [PATCH v5 01/16] drm/i915: Fix sha_text population code
From: Sean Paul
This patch fixes a few bugs:
1- We weren't taking into account sha_leftovers when adding multiple
ksvs to sha_text. As such, we were or'ing the end of ksv[j - 1] with
the beginning of ksv[j]
2- In the sha_leftovers == 2 and sha_leftovers == 3 case, bstatus was
being placed on the wrong half of sha_text, overlapping the leftover
ksv value
3- In the sha_leftovers == 2 case, we need to manually terminate the
byte stream with 0x80 since the hardware doesn't have enough room to
add it after writing M0
The upside is that all of the HDCP supported HDMI repeaters I could
find on Amazon just strip HDCP anyways, so it turns out to be _really_
hard to hit any of these cases without an MST hub, which is not (yet)
supported. Oh, and the sha_leftovers == 1 case works perfectly!
Fixes: ee5e5e7a5e0f (drm/i915: Add HDCP framework + base implementation)
Cc: Chris Wilson
Cc: Ramalingam C
Cc: Daniel Vetter
Cc: Sean Paul
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: intel-gfx@lists.freedesktop.org
Cc: # v4.17+
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-2-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-2-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-2-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-2-s...@poorly.run
#v4
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-Rebased on intel_de_write changes
Changes in v5:
-None
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 26 +--
include/drm/drm_hdcp.h| 3 +++
2 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index ee0f27ea2810d..defa8654e7ac5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -338,8 +338,10 @@ int intel_hdcp_validate_v_prime(struct intel_connector
*connector,
/* Fill up the empty slots in sha_text and write it out */
sha_empty = sizeof(sha_text) - sha_leftovers;
- for (j = 0; j < sha_empty; j++)
- sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8);
+ for (j = 0; j < sha_empty; j++) {
+ u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) *
8);
+ sha_text |= ksv[j] << off;
+ }
ret = intel_write_sha_text(dev_priv, sha_text);
if (ret < 0)
@@ -437,7 +439,7 @@ int intel_hdcp_validate_v_prime(struct intel_connector
*connector,
/* Write 32 bits of text */
intel_de_write(dev_priv, HDCP_REP_CTL,
rep_ctl | HDCP_SHA1_TEXT_32);
- sha_text |= bstatus[0] << 24 | bstatus[1] << 16;
+ sha_text |= bstatus[0] << 8 | bstatus[1];
ret = intel_write_sha_text(dev_priv, sha_text);
if (ret < 0)
return ret;
@@ -452,17 +454,29 @@ int intel_hdcp_validate_v_prime(struct intel_connector
*connector,
return ret;
sha_idx += sizeof(sha_text);
}
+
+ /*
+* Terminate the SHA-1 stream by hand. For the other leftover
+* cases this is appended by the hardware.
+*/
+ intel_de_write(dev_priv, HDCP_REP_CTL,
+ rep_ctl | HDCP_SHA1_TEXT_32);
+ sha_text = DRM_HDCP_SHA1_TERMINATOR << 24;
+ ret = intel_write_sha_text(dev_priv, sha_text);
+ if (ret < 0)
+ return ret;
+ sha_idx += sizeof(sha_text);
} else if (sha_leftovers == 3) {
- /* Write 32 bits of text */
+ /* Write 32 bits of text (filled from LSB) */
intel_de_write(dev_priv, HDCP_REP_CTL,
rep_ctl | HDCP_SHA1_TEXT_32);
- sha_text |= bstatus[0] << 24;
+ sha_text |= bstatus[0];
ret = intel_write_sha_text(dev_priv, sha_text);
if (ret < 0)
return ret;
sha_idx += sizeof(sha_text);
- /* Write 8 bits of text, 24 bits of M0 */
+ /* Write 8 bits of text (filled from LSB), 24 bits of M0 */
intel_de_write(dev_priv, HDCP_REP_CTL,
rep_ctl | HDCP_SHA1_TEXT_8);
ret = intel_write_sha_text(dev_priv, bstatus[1]);
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index c6bab4986a658..fe58dbb46962a 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -29,6 +29,9 @@
/* Slave address for the HDCP registers in the
[Intel-gfx] [PATCH v5 04/16] drm/i915: Intercept Aksv writes in the aux hooks
From: Sean Paul
Instead of hand rolling the transfer ourselves in the hdcp hook, inspect
aux messages and add the aksv flag in the aux transfer hook.
IIRC, this was the original implementation and folks wanted this hack to
be isolated to the hdcp code, which makes sense.
However in testing an LG monitor on my desk, I noticed it was passing
back a DEFER reply. This wasn't handled in our hand-rolled code and HDCP
auth was failing as a result. Instead of copy/pasting all of the retry
logic and delays from drm dp helpers, let's just use the helpers and hide
the aksv select as best as we can.
Reviewed-by: Ville Syrjälä
Reviewed-by: Ramalingam C
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-3-s...@poorly.run
#v1
Link:
https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-5-s...@poorly.run
#v2
Link:
https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-5-s...@poorly.run
#v3
Link:
https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-5-s...@poorly.run
#v4
Changes in v2:
-Remove 'generate' in intel_dp_aux_generate_xfer_flags, make arg const (Ville)
-Bundle Aksv if statement together (Ville)
-Rename 'txbuf' to 'aksv' (Ville)
Changes in v3:
-None
Changes in v4:
-None
Changes in v5:
-None
---
drivers/gpu/drm/i915/display/intel_dp.c | 62 -
1 file changed, 29 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0a417cd2af2bc..1f80a1244abbb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1534,12 +1534,27 @@ intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
txbuf[3] = msg->size - 1;
}
+static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
+{
+ /*
+* If we're trying to send the HDCP Aksv, we need to set a the Aksv
+* select bit to inform the hardware to send the Aksv after our header
+* since we can't access that data from software.
+*/
+ if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
+ msg->address == DP_AUX_HDCP_AKSV)
+ return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
+
+ return 0;
+}
+
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
{
struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
u8 txbuf[20], rxbuf[20];
size_t txsize, rxsize;
+ u32 flags = intel_dp_aux_xfer_flags(msg);
int ret;
intel_dp_aux_header(txbuf, msg);
@@ -1560,7 +1575,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
- rxbuf, rxsize, 0);
+ rxbuf, rxsize, flags);
if (ret > 0) {
msg->reply = rxbuf[0] >> 4;
@@ -1583,7 +1598,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
return -E2BIG;
ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
- rxbuf, rxsize, 0);
+ rxbuf, rxsize, flags);
if (ret > 0) {
msg->reply = rxbuf[0] >> 4;
/*
@@ -5959,17 +5974,9 @@ static
int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
u8 *an)
{
- struct intel_dp *intel_dp =
enc_to_intel_dp(to_intel_encoder(_dig_port->base.base));
- static const struct drm_dp_aux_msg msg = {
- .request = DP_AUX_NATIVE_WRITE,
- .address = DP_AUX_HDCP_AKSV,
- .size = DRM_HDCP_KSV_LEN,
- };
- u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
+ u8 aksv[DRM_HDCP_KSV_LEN] = {};
ssize_t dpcd_ret;
- int ret;
- /* Output An first, that's easy */
dpcd_ret = drm_dp_dpcd_write(_dig_port->dp.aux, DP_AUX_HDCP_AN,
an, DRM_HDCP_AN_LEN);
if (dpcd_ret != DRM_HDCP_AN_LEN) {
@@ -5979,29 +5986,18 @@ int intel_dp_hdcp_write_an_aksv(struct
intel_digital_port *intel_dig_port,
}
/*
-* Since Aksv is Oh-So-Secret, we can't access it in software. So in
-* order to get it on the wire, we need to create the AUX header as if
-* we were writing the data, and then tickle the hardware to output the
-* data once the header is sent out.
+* Since Aksv is Oh-So-Secret, we can't access it in software. So we
+* send an empty buffer of the correct length through the DP helpers. On
+* the other side, in the transfer hook, we'll generate a flag based on
+* the destination address
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev2)
== Series Details == Series: drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev2) URL : https://patchwork.freedesktop.org/series/74100/ State : failure == Summary == Applying: drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (v2) Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_dp_helper.c M drivers/gpu/drm/i915/display/intel_dp.c M include/drm/drm_dp_helper.h Falling back to patching base and 3-way merge... Auto-merging include/drm/drm_dp_helper.h CONFLICT (content): Merge conflict in include/drm/drm_dp_helper.h Auto-merging drivers/gpu/drm/i915/display/intel_dp.c Auto-merging drivers/gpu/drm/drm_dp_helper.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (v2) When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/execlists: Enable timeslice on partial virtual engine dequeue
== Series Details == Series: drm/i915/execlists: Enable timeslice on partial virtual engine dequeue URL : https://patchwork.freedesktop.org/series/74304/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable to dev
== Series Details == Series: series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable to dev URL : https://patchwork.freedesktop.org/series/74299/ State : success == Summary == CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16832 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16832/index.html Known issues Here are the changes found in Patchwork_16832 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [PASS][1] -> [FAIL][2] ([CI#94]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16832/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@kms_addfb_basic@addfb25-bad-modifier: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-bad-modifier.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16832/fi-tgl-y/igt@kms_addfb_ba...@addfb25-bad-modifier.html Possible fixes * igt@kms_addfb_basic@addfb25-modifier-no-flag: - fi-tgl-y: [DMESG-WARN][5] ([CI#94] / [i915#402]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16832/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (49 -> 40) -- Additional (1): fi-kbl-soraka Missing(10): fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-blb-e6850 fi-kbl-r fi-bdw-samus fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8070 -> Patchwork_16832 CI-20190529: 20190529 CI_DRM_8070: d4e6f8b48e361f0cae9132f50f1778707b2546a2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5495: 22df72de8affcec22d9f354bb6148d77f60cc580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16832: 54d76ab89c1c5512cdcb4a1dcc37dcd5d0e62f99 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 54d76ab89c1c drm/i915: Add support for integrated privacy screens 0dfdbf299bc6 drm/i915: Lookup and attach ACPI device node for connectors e83f0d80506c intel_acpi: Rename drm_dev local variable to dev == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16832/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable to dev
== Series Details == Series: series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable to dev URL : https://patchwork.freedesktop.org/series/74299/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/1] Revert "drm/i915/tgl: Add extra hdc flush workaround"
== Series Details == Series: series starting with [1/1] Revert "drm/i915/tgl: Add extra hdc flush workaround" URL : https://patchwork.freedesktop.org/series/74277/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8066_full -> Patchwork_16823_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16823_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16823_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16823_full: ### IGT changes ### Possible regressions * igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl7/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-skl6/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd1.html Known issues Here are the changes found in Patchwork_16823_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +11 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_b...@busy-vcs1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-iclb8/igt@gem_b...@busy-vcs1.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#679]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl7/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-skl6/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_exec_balan...@smoke.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@implicit-read-write-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb8/igt@gem_exec_sched...@implicit-read-write-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-iclb4/igt@gem_exec_sched...@implicit-read-write-bsd.html * igt@gem_exec_schedule@implicit-write-read-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276] / [i915#677]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_exec_sched...@implicit-write-read-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-iclb8/igt@gem_exec_sched...@implicit-write-read-bsd1.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +16 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_exec_sched...@promotion-bsd1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-iclb6/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#112146]) +6 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb7/igt@gem_exec_sched...@wide-bsd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-iclb2/igt@gem_exec_sched...@wide-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#644]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-kbl3/igt@gem_pp...@flink-and-close-vma-leak.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-kbl2/igt@gem_pp...@flink-and-close-vma-leak.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16823/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-256x85-offscreen.html [22]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable to dev
== Series Details ==
Series: series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable
to dev
URL : https://patchwork.freedesktop.org/series/74299/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e83f0d80506c intel_acpi: Rename drm_dev local variable to dev
0dfdbf299bc6 drm/i915: Lookup and attach ACPI device node for connectors
-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_acpi.c:265:
+ conn_dev = acpi_find_child_device(
total: 0 errors, 0 warnings, 1 checks, 70 lines checked
54d76ab89c1c drm/i915: Add support for integrated privacy screens
-:205: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#205:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 248 lines checked
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable to dev
== Series Details ==
Series: series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable
to dev
URL : https://patchwork.freedesktop.org/series/74298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8070 -> Patchwork_16831
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_16831:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_16831 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [PASS][3] -> [FAIL][4] ([CI#94])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_module_load@reload:
- fi-skl-6770hq: [PASS][5] -> [DMESG-WARN][6] ([i915#92]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-skl-6770hq/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-skl-6770hq/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770:[PASS][7] -> [SKIP][8] ([fdo#109271]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-hsw-4770/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@gem_contexts:
- fi-skl-lmem:[PASS][9] -> [INCOMPLETE][10] ([i915#424])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][11] -> [FAIL][12] ([i915#217])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-skl-6770hq: [PASS][13] -> [SKIP][14] ([fdo#109271]) +5 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-skl-6770hq: [PASS][15] -> [DMESG-WARN][16] ([i915#106])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][17] -> [DMESG-WARN][18] ([CI#94] / [i915#402])
+1 similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
Possible fixes
* igt@kms_addfb_basic@addfb25-modifier-no-flag:
- fi-tgl-y: [DMESG-WARN][19] ([CI#94] / [i915#402]) -> [PASS][20]
+1 similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html
Warnings
* igt@runner@aborted:
- fi-kbl-8809g: [FAIL][21] ([i915#1209]) -> [FAIL][22] ([i915#192] /
[i915#193] / [i915#194])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8070/fi-kbl-8809g/igt@run...@aborted.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16831/fi-kbl-8809g/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS,
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable to dev
== Series Details == Series: series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable to dev URL : https://patchwork.freedesktop.org/series/74298/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable to dev
== Series Details ==
Series: series starting with [v6,1/3] intel_acpi: Rename drm_dev local variable
to dev
URL : https://patchwork.freedesktop.org/series/74298/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c20368a27477 intel_acpi: Rename drm_dev local variable to dev
f4a4471b5c37 drm/i915: Lookup and attach ACPI device node for connectors
-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_acpi.c:265:
+ conn_dev = acpi_find_child_device(
total: 0 errors, 0 warnings, 1 checks, 70 lines checked
f9f7e4554cff drm/i915: Add support for integrated privacy screens
-:205: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#205:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 248 lines checked
___
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[Intel-gfx] [PATCH] drm/i915/tgl: Make wa_1606700617 permanent
This workaround is to disable FF DOP Clock gating. The fix
in B0 was backed out due to timing reasons and decided to
be made permanent.
Bspec: 52890
Signed-off-by: Swathi Dhanavanthri
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cb7d85c42f13..a9d1975b5245 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1337,11 +1337,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
struct drm_i915_private *i915 = engine->i915;
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
- /* Wa_1606700617:tgl */
- wa_masked_en(wal,
-GEN9_CS_DEBUG_MODE1,
-FF_DOP_CLOCK_GATE_DISABLE);
-
/*
* Wa_1607138336:tgl
* Wa_1607063988:tgl
@@ -1393,6 +1388,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
/* Wa_1409804808:tgl */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
+
+ /* Wa_1606700617:tgl */
+ wa_masked_en(wal,
+GEN9_CS_DEBUG_MODE1,
+FF_DOP_CLOCK_GATE_DISABLE);
}
if (IS_GEN(i915, 11)) {
--
2.20.1
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Re: [Intel-gfx] [PATCH 5/6] drm/i915/uc: Move uC debugfs to its own folder under GT
Hi Daniele,
> > On Thu, Feb 27, 2020 at 06:28:42PM -0800, Daniele Ceraolo Spurio wrote:
> > > uC is a component of the GT, so it makes sense for the uC debugfs files
> > > to be in the GT folder. A subfolder has been used to keep the same
> > > structure we have for the code.
> >
> > Can we please document the interface changes. I see there are
> > some differences between the original and the new interfaces.
> >
>
> What differences are you referring to? there aren't supposed to be any,
> aside from the path change.
Have I seen it wrong or there are new files in this patch?
In any case, maybe we need to have the new structure.
> > > +#define DEFINE_UC_DEBUGFS_ATTRIBUTE(__name)
> > > \
> > > + static int __name ## _open(struct inode *inode, struct file *file) \
> > > +{
> > > \
> > > + return single_open(file, __name ## _show, inode->i_private);\
> > > +}
> > > \
> > > +static const struct file_operations __name ## _fops = {
> > > \
> > > + .owner = THIS_MODULE, \
> > > + .open = __name ## _open,\
> > > + .read = seq_read, \
> > > + .llseek = seq_lseek,\
> > > + .release = single_release, \
> > > +}
> >
> > Why do we need DEFINE_UC_DEBUGFS_ATTRIBUTE()?
> >
> > DEFINE_GT_DEBUGFS_ATTRIBUTE() was meant to be common to all gt
> > debugfs. I there any reason we need a new one?
> >
>
> Just wanted to avoid including the other header just for this macro.
well that was supposed to be a library for all the gem/debugfs
files and avoid duplicated code, I don't see anything wrong with
including the file.
> > > +struct debugfs_uc_file {
> > > + const char *name;
> > > + const struct file_operations *fops;
> > > +};
> > > +
> > > +#define debugfs_uc_register_files(files__, root__, data__) \
> > > +do { \
> > > + int i__ = 0; \
> > > + for (i__ = 0; i__ < ARRAY_SIZE(files__); i__++) { \
> > > + debugfs_create_file(files__[i__].name, \
> > > + 0444, root__, data__, \
> > > + files__[i__].fops); \
> > > + } \
> > > +} while (0)
> >
> > You want to define your own debugfs_uc_register_files() instead
> > of using debugfs_gt_register_files() because you want "data__"
> > to be void, right?
> >
> > I think we can achieve that by adding a wrapper in debugfs_gt.c,
> > perhaps we can do something like:
> >
> > void __debugfs_gt_register_files(struct intel_gt *gt,
> > struct dentry *root,
> > const struct debugfs_gt_file *files,
> > void *data,
> > unsigned long count)
> > {
> >..
> > }
> >
> > and
> >
> > #define debugfs_gt_register_files(...) __debugfs_gt_register_files(...)
> > #define debugfs_uc_register_files(...) __debugfs_gt_register_files(...)
> >
> > so that we can keep everything in a library. What do you think.
> >
>
> LGTM. Mind if I rename to:
>
> intel_gt_debugfs_register(...)
> intel_uc_debugfs_register(...)
>
> to avoid the debugfs_* prefix, as pointed out by Jani?
I have a patch for it, can you please hold a little, unless, of
course, yours is already ready.
Obvously, the naming you propose makes sense.
Andi
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Adding YUV444 packed format support for skl+ (rev4)
On Sat, 29 Feb 2020 09:11:20 + Patchwork wrote: > == Series Details == > > Series: Adding YUV444 packed format support for skl+ (rev4) > URL : https://patchwork.freedesktop.org/series/73020/ > State : failure I'm a bit confused by this. The build changes listed at the bottom indicate that this did use a modified IGT tree with the test patch (per the cover-letter test-with tag) but the errors below look exactly like what I'd expect if testing with a non-modified IGT tree. In fact the line number where the error occurs matches with an non-modified tree and not the modified tree. Did I do something wrong with the cover letter? Do I just re-run? Should I resubmit the series? Bob > > == Summary == > > CI Bug Log - changes from CI_DRM_8023_full -> Patchwork_16744_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_16744_full absolutely > need to be verified manually. > > If you think the reported changes have nothing to do with the > changes introduced in Patchwork_16744_full, please notify your bug > team to allow them to document this new failure mode, which will > reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_16744_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_plane@pixel-format-pipe-a-planes: > - shard-iclb: [PASS][1] -> [FAIL][2] +13 similar issues >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb1/igt@kms_pl...@pixel-format-pipe-a-planes.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-iclb3/igt@kms_pl...@pixel-format-pipe-a-planes.html > > * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: > - shard-kbl: NOTRUN -> [FAIL][3] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-kbl6/igt@kms_pl...@pixel-format-pipe-a-planes-source-clamping.html > > * igt@kms_plane@pixel-format-pipe-b-planes: > - shard-skl: [PASS][4] -> [FAIL][5] +12 similar issues >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl3/igt@kms_pl...@pixel-format-pipe-b-planes.html > [5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-skl1/igt@kms_pl...@pixel-format-pipe-b-planes.html > - shard-kbl: [PASS][6] -> [FAIL][7] +12 similar issues >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-kbl4/igt@kms_pl...@pixel-format-pipe-b-planes.html > [7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-kbl6/igt@kms_pl...@pixel-format-pipe-b-planes.html > > * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: > - shard-tglb: [PASS][8] -> [FAIL][9] +19 similar issues >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-tglb8/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html > [9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-tglb3/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html > > * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: > - shard-glk: [PASS][10] -> [FAIL][11] +13 similar issues >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-glk9/igt@kms_plane_scal...@pipe-a-scaler-with-clipping-clamping.html > [11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-glk5/igt@kms_plane_scal...@pipe-a-scaler-with-clipping-clamping.html > > * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format: > - shard-apl: [PASS][12] -> [FAIL][13] +13 similar issues >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-apl3/igt@kms_plane_scal...@pipe-b-scaler-with-pixel-format.html > [13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-apl1/igt@kms_plane_scal...@pipe-b-scaler-with-pixel-format.html > > * igt@kms_plane_scaling@pipe-c-scaler-with-clipping-clamping: > - shard-iclb: NOTRUN -> [FAIL][14] >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-iclb3/igt@kms_plane_scal...@pipe-c-scaler-with-clipping-clamping.html > > > Known issues > > > Here are the changes found in Patchwork_16744_full that come from > known issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_schedule@pi-common-bsd: > - shard-iclb: [PASS][15] -> [SKIP][16] ([i915#677]) +2 > similar issues [15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb5/igt@gem_exec_sched...@pi-common-bsd.html > [16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-iclb4/igt@gem_exec_sched...@pi-common-bsd.html > > * igt@gem_exec_schedule@preempt-other-chain-bsd: > - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#112146]) +6 > similar issues [17]: >
[Intel-gfx] [PATCH i-g-t] tests/gem_exec_gttfill: MMAP_OFFSET related refresh
The test already tried to use a working mapping by first trying legacy
WC, then GTT. Use gem_mmap__device_coherent() helper instead of
approaching its implementation locally.
Signed-off-by: Janusz Krzysztofik
---
tests/i915/gem_exec_gttfill.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/tests/i915/gem_exec_gttfill.c b/tests/i915/gem_exec_gttfill.c
index f810dafd1..27277df48 100644
--- a/tests/i915/gem_exec_gttfill.c
+++ b/tests/i915/gem_exec_gttfill.c
@@ -155,15 +155,10 @@ static void fillgtt(int fd, unsigned ring, int timeout)
igt_assert(batches);
for (unsigned i = 0; i < count; i++) {
batches[i].handle = gem_create(fd, BATCH_SIZE);
- batches[i].ptr =
- __gem_mmap__wc(fd, batches[i].handle,
- 0, BATCH_SIZE, PROT_WRITE);
- if (!batches[i].ptr) {
- batches[i].ptr =
- __gem_mmap__gtt(fd, batches[i].handle,
- BATCH_SIZE, PROT_WRITE);
- }
- igt_require(batches[i].ptr);
+ batches[i].ptr = gem_mmap__device_coherent(fd,
+ batches[i].handle, 0,
+ BATCH_SIZE,
+ PROT_WRITE);
}
/* Flush all memory before we start the timer */
--
2.21.1
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[Intel-gfx] [PATCH] drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off
From: Ville Syrjälä
We only consider crtc_state->enable when initially calculating plane
visibility. Later on we try to override the plane's state to invisible
if the crtc is in DPMS off state (crtc_state->active==false).
Unfortunately the code doing that only updates the plane_state.visible
flag and the crtc_state.active_planes bimask, but forgets to update
some of the other plane bitmasks stored in the crtc_state. Namely
crtc_state.nv12_planes is left set up based on the original visibility
check which makes icl_check_nv12_planes() pick a slave plane for the
flagged plane in the bitmask. Later on we hit the watermark code
which sees a plane with a slave assigned and it then makes the
logical assumption that the master plane must itself be visible.
Since the master's plane_state.visible flag was already cleared
we get a WARN.
Fix the problem by clearing all the plane bitmasks for DPMS off.
This is more or less the wrong approach and instead we should
calculate all the plane related state purely based crtc_state->enable
(to guarantee that the subsequent DPMS on can't fail). However in
the past we definitely had some roadblocks to making that happen.
Not sure how many are left these days, but let's stick to the current
approach since it's a much simpler fix to the immediate problem
(the WARN).
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 21 +--
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 ++
drivers/gpu/drm/i915/display/intel_display.c | 8 ++-
3 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 457b258683d3..25dfeb3197aa 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -264,6 +264,20 @@ void intel_plane_copy_uapi_to_hw_state(struct
intel_plane_state *plane_state,
plane_state->hw.color_range = from_plane_state->uapi.color_range;
}
+void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+
+ crtc_state->active_planes &= ~BIT(plane->id);
+ crtc_state->nv12_planes &= ~BIT(plane->id);
+ crtc_state->c8_planes &= ~BIT(plane->id);
+ crtc_state->data_rate[plane->id] = 0;
+ crtc_state->min_cdclk[plane->id] = 0;
+
+ plane_state->uapi.visible = false;
+}
+
int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state
*old_plane_state,
@@ -273,12 +287,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
const struct drm_framebuffer *fb = new_plane_state->hw.fb;
int ret;
- new_crtc_state->active_planes &= ~BIT(plane->id);
- new_crtc_state->nv12_planes &= ~BIT(plane->id);
- new_crtc_state->c8_planes &= ~BIT(plane->id);
- new_crtc_state->data_rate[plane->id] = 0;
- new_crtc_state->min_cdclk[plane->id] = 0;
- new_plane_state->uapi.visible = false;
+ intel_plane_set_invisible(new_crtc_state, new_plane_state);
if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index a6bbf42bae1f..59dd1fbb02ea 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -52,5 +52,7 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
struct intel_plane *plane,
bool *need_cdclk_calc);
+void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state);
#endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8f23c4d51c33..3ff9d9102cd2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12376,12 +12376,8 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
* per-plane wm computation to the .check_plane() hook, and
* only combine the results from all planes in the current place?
*/
- if (!is_crtc_enabled) {
- plane_state->uapi.visible = visible = false;
- crtc_state->active_planes &= ~BIT(plane->id);
- crtc_state->data_rate[plane->id] = 0;
- crtc_state->min_cdclk[plane->id] = 0;
- }
+
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Cancel banned contexts after GT reset
== Series Details == Series: drm/i915/gt: Cancel banned contexts after GT reset URL : https://patchwork.freedesktop.org/series/74276/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8066_full -> Patchwork_16822_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16822_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16822_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16822_full: ### IGT changes ### Possible regressions * igt@i915_pm_dc@dc5-dpms: - shard-iclb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb1/igt@i915_pm...@dc5-dpms.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-iclb3/igt@i915_pm...@dc5-dpms.html * igt@i915_selftest@live@gtt: - shard-skl: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl1/igt@i915_selftest@l...@gtt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-skl1/igt@i915_selftest@l...@gtt.html Known issues Here are the changes found in Patchwork_16822_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-apl4/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_exec_schedule@implicit-read-write-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb1/igt@gem_exec_sched...@implicit-read-write-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-iclb3/igt@gem_exec_sched...@implicit-read-write-bsd1.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb8/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-iclb2/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@preempt-contexts-bsd2: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +14 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb1/igt@gem_exec_sched...@preempt-contexts-bsd2.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-iclb3/igt@gem_exec_sched...@preempt-contexts-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb6/igt@gem_exec_sched...@preemptive-hang-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@kms_addfb_basic@unused-modifier: - shard-skl: [PASS][15] -> [SKIP][16] ([fdo#109271]) +26 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl1/igt@kms_addfb_ba...@unused-modifier.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-skl1/igt@kms_addfb_ba...@unused-modifier.html * igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-alpha-transparent.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-alpha-transparent.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-glk2/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16822/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#69]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl10/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [22]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: WaDisableGPGPUMidThreadPreemption
== Series Details == Series: drm/i915/tgl: WaDisableGPGPUMidThreadPreemption URL : https://patchwork.freedesktop.org/series/74274/ State : success == Summary == CI Bug Log - changes from CI_DRM_8066_full -> Patchwork_16821_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16821_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +10 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-iclb5/igt@gem_b...@busy-vcs1.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox: - shard-skl: [PASS][3] -> [FAIL][4] ([i915#679]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl7/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@vebox.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-skl1/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@vebox.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@implicit-write-read-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_exec_sched...@implicit-write-read-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-iclb5/igt@gem_exec_sched...@implicit-write-read-bsd1.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb8/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-iclb4/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +17 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_exec_sched...@promotion-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-iclb3/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb7/igt@gem_exec_sched...@wide-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-iclb1/igt@gem_exec_sched...@wide-bsd.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +6 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-apl3/igt@i915_susp...@sysfs-reader.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-apl8/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-256x85-offscreen.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-256x85-offscreen.html * igt@kms_flip@dpms-off-confusion: - shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103665]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-kbl4/igt@kms_f...@dpms-off-confusion.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-kbl6/igt@kms_f...@dpms-off-confusion.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#221]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl10/igt@kms_f...@flip-vs-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-skl10/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip_tiling@flip-to-x-tiled: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#167]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl6/igt@kms_flip_til...@flip-to-x-tiled.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16821/shard-skl5/igt@kms_flip_til...@flip-to-x-tiled.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#69]) +1 similar issue [25]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/edp: Ignore short pulse when panel powered off
== Series Details == Series: drm/i915/edp: Ignore short pulse when panel powered off URL : https://patchwork.freedesktop.org/series/74265/ State : success == Summary == CI Bug Log - changes from CI_DRM_8066_full -> Patchwork_16817_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16817_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-iclb6/igt@gem_b...@busy-vcs1.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112146]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb3/igt@gem_exec_as...@concurrent-writes-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@implicit-read-write-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb8/igt@gem_exec_sched...@implicit-read-write-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-iclb4/igt@gem_exec_sched...@implicit-read-write-bsd.html * igt@gem_exec_schedule@implicit-write-read-bsd1: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276] / [i915#677]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_exec_sched...@implicit-write-read-bsd1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-iclb6/igt@gem_exec_sched...@implicit-write-read-bsd1.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-iclb2/igt@gem_exec_sched...@promotion-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-iclb3/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-apl4/igt@gem_workarou...@suspend-resume.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-apl4/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_rpm@system-suspend-modeset: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#151] / [i915#69]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl5/igt@i915_pm_...@system-suspend-modeset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-skl5/igt@i915_pm_...@system-suspend-modeset.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-kbl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-kbl1/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-256x85-offscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-256x85-offscreen.html * igt@kms_flip@dpms-off-confusion: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103665]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-kbl4/igt@kms_f...@dpms-off-confusion.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-kbl1/igt@kms_f...@dpms-off-confusion.html - shard-apl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103927]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8066/shard-apl2/igt@kms_f...@dpms-off-confusion.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16817/shard-apl2/igt@kms_f...@dpms-off-confusion.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][25] -> [FAIL][26] ([i915#79]) [25]:
Re: [Intel-gfx] [PATCH] drm/i915/gem: Limit struct_mutex to eb_reserve
Chris Wilson writes:
> We only need to serialise the multiple pinning during the eb_reserve
> phase. Ideally this would be using the vm->mutex as an outer lock, or
> using a composite global mutex (ww_mutex), but at the moment we are
> using struct_mutex for the group.
>
> Fixes: 003d8b9143a6 ("drm/i915/gem: Only call eb_lookup_vma once during
> execbuf ioctl")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 51 ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ---
> 2 files changed, 20 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 7bb27f382af7..faa5b5c99a9a 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -610,7 +610,7 @@ static int eb_reserve(struct i915_execbuffer *eb)
> struct list_head last;
> struct eb_vma *ev;
> unsigned int i, pass;
> - int err;
> + int err = 0;
>
> /*
>* Attempt to pin all of the buffers into the GTT.
> @@ -626,8 +626,10 @@ static int eb_reserve(struct i915_execbuffer *eb)
>* room for the earlier objects *unless* we need to defragment.
>*/
>
> + if (mutex_lock_interruptible(>i915->drm.struct_mutex))
> + return -EINTR;
> +
> pass = 0;
> - err = 0;
> do {
> list_for_each_entry(ev, >unbound, bind_link) {
> err = eb_reserve_vma(eb, ev, pin_flags);
> @@ -635,7 +637,7 @@ static int eb_reserve(struct i915_execbuffer *eb)
> break;
> }
> if (!(err == -ENOSPC || err == -EAGAIN))
> - return err;
> + break;
>
> /* Resort *all* the objects into priority order */
> INIT_LIST_HEAD(>unbound);
> @@ -666,7 +668,9 @@ static int eb_reserve(struct i915_execbuffer *eb)
> list_splice_tail(, >unbound);
>
> if (err == -EAGAIN) {
> + mutex_unlock(>i915->drm.struct_mutex);
> flush_workqueue(eb->i915->mm.userptr_wq);
> + mutex_lock(>i915->drm.struct_mutex);
General curiousity of what mechanism prevents the possible jail of -EAGAIN
looping?
For the fix tho,
Reviewed-by: Mika Kuoppala
> continue;
> }
>
> @@ -680,15 +684,20 @@ static int eb_reserve(struct i915_execbuffer *eb)
> err = i915_gem_evict_vm(eb->context->vm);
> mutex_unlock(>context->vm->mutex);
> if (err)
> - return err;
> + goto unlock;
> break;
>
> default:
> - return -ENOSPC;
> + err = -ENOSPC;
> + goto unlock;
> }
>
> pin_flags = PIN_USER;
> } while (1);
> +
> +unlock:
> + mutex_unlock(>i915->drm.struct_mutex);
> + return err;
> }
>
> static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
> @@ -1631,7 +1640,6 @@ static int eb_prefault_relocations(const struct
> i915_execbuffer *eb)
>
> static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
> {
> - struct drm_device *dev = >i915->drm;
> bool have_copy = false;
> struct eb_vma *ev;
> int err = 0;
> @@ -1642,8 +1650,6 @@ static noinline int eb_relocate_slow(struct
> i915_execbuffer *eb)
> goto out;
> }
>
> - mutex_unlock(>struct_mutex);
> -
> /*
>* We take 3 passes through the slowpatch.
>*
> @@ -1666,21 +1672,8 @@ static noinline int eb_relocate_slow(struct
> i915_execbuffer *eb)
> cond_resched();
> err = 0;
> }
> - if (err) {
> - mutex_lock(>struct_mutex);
> - goto out;
> - }
> -
> - /* A frequent cause for EAGAIN are currently unavailable client pages */
> - flush_workqueue(eb->i915->mm.userptr_wq);
> -
> - err = i915_mutex_lock_interruptible(dev);
> - if (err) {
> - mutex_lock(>struct_mutex);
> + if (err)
> goto out;
> - }
> -
> - GEM_BUG_ON(!eb->batch);
>
> list_for_each_entry(ev, >relocs, reloc_link) {
> if (!have_copy) {
> @@ -1738,9 +1731,11 @@ static int eb_relocate(struct i915_execbuffer *eb)
> if (err)
> return err;
>
> - err = eb_reserve(eb);
> - if (err)
> - return err;
> + if (!list_empty(>unbound)) {
> + err = eb_reserve(eb);
> + if (err)
> + return err;
> + }
>
> /* The objects are in their final locations, apply the relocations. */
> if (eb->args->flags & __EXEC_HAS_RELOC) {
> @@ -2690,10 +2685,6 @@
