[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable HDR on Gen9 devices with lspcon hdr capability

2020-03-26 Thread Patchwork
== Series Details ==

Series: Enable HDR on Gen9 devices with lspcon hdr capability
URL   : https://patchwork.freedesktop.org/series/75148/
State : failure

== Summary ==

Applying: drm/i915/display: Add HDR Capability detection for LSPCON
Applying: drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
Applying: drm/i915/display: Attach HDR property for capable Gen9 devices
Applying: drm/i915/display: Set HDR Infoframe for HDR capable LSPCON devices
Applying: drm/i915/display: Enable BT2020 for HDR on LSPCON devices
Applying: drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON
Applying: drm:i915:display: add checks for Gen9 devices with hdr capability
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/display/intel_hdmi.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0007 drm:i915:display: add checks for Gen9 devices with hdr 
capability
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] [PATCH 1/7] drm/i915/display: Add HDR Capability detection for LSPCON

2020-03-26 Thread Vipin Anand
From: Uma Shankar 

LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES
DPCD register. LSPCON implementations capable of supporting
HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch
reads the same, detects the HDR capability and adds this to
intel_lspcon struct.

Signed-off-by: Uma Shankar 
---
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_lspcon.c   | 32 +++
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 888ea8a170d1..2f281da6d253 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1333,6 +1333,7 @@ struct intel_lspcon {
bool active;
enum drm_lspcon_mode mode;
enum lspcon_vendor vendor;
+   bool hdr_supported;
 };
 
 struct intel_digital_port {
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c 
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d807c5648c87..2e41ae483a23 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -35,6 +35,8 @@
 #define LSPCON_VENDOR_PARADE_OUI 0x001CF8
 #define LSPCON_VENDOR_MCA_OUI 0x0060AD
 
+#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
+
 /* AUX addresses to write MCA AVI IF */
 #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF
@@ -104,6 +106,31 @@ static bool lspcon_detect_vendor(struct intel_lspcon 
*lspcon)
return true;
 }
 
+static bool lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
+{
+   struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+   u8 hdr_caps;
+   int ret;
+
+   /* Enable HDR for MCA based LSPCON devices */
+   if (lspcon->vendor == LSPCON_VENDOR_MCA)
+   ret = drm_dp_dpcd_read(>aux, DPCD_MCA_LSPCON_HDR_STATUS,
+  _caps, 1);
+   else
+   return false;
+
+   if (ret < 0) {
+   DRM_DEBUG_KMS("hdr capability detection failed\n");
+   lspcon->hdr_supported = false;
+   return false;
+   } else if (hdr_caps & 0x1) {
+   DRM_DEBUG_KMS("lspcon capable of HDR\n");
+   lspcon->hdr_supported = true;
+   }
+
+   return true;
+}
+
 static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon 
*lspcon)
 {
enum drm_lspcon_mode current_mode;
@@ -581,6 +608,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
return false;
}
 
+   if (!lspcon_detect_hdr_capability(lspcon)) {
+   DRM_ERROR("LSPCON hdr detection failed\n");
+   return false;
+   }
+
connector->ycbcr_420_allowed = true;
lspcon->active = true;
DRM_DEBUG_KMS("Success: LSPCON init\n");
-- 
2.26.0

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[Intel-gfx] [PATCH 7/7] drm:i915:display: add checks for Gen9 devices with hdr capability

2020-03-26 Thread Vipin Anand
this patch adds hdr capabilities checks for Gen9 devices with
lspcon support.

Signed-off-by: Vipin Anand 
---
 drivers/gpu/drm/i915/display/intel_hdmi.c   | 17 +
 drivers/gpu/drm/i915/display/intel_lspcon.c |  9 +++--
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 9ae2f88cc925..70d0d76ed606 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -833,9 +833,12 @@ intel_hdmi_compute_drm_infoframe(struct intel_encoder 
*encoder,
 {
struct hdmi_drm_infoframe *frame = _state->infoframes.drm.drm;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
int ret;
 
-   if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
+   if (!(INTEL_GEN(dev_priv) >= 10 ||
+ (((INTEL_GEN(dev_priv) >= 9)) &&
+ intel_dig_port->lspcon.active)))
return true;
 
if (!crtc_state->has_infoframe)
@@ -2102,9 +2105,12 @@ static int intel_hdmi_source_max_tmds_clock(struct 
intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
const struct ddi_vbt_port_info *info =
_priv->vbt.ddi_port_info[encoder->port];
+   struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
int max_tmds_clock;
 
-   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+   if (INTEL_GEN(dev_priv) >= 10 ||
+   (((INTEL_GEN(dev_priv) >= 9)) &&
+intel_dig_port->lspcon.active))
max_tmds_clock = 594000;
else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
max_tmds_clock = 30;
@@ -2423,6 +2429,7 @@ int intel_hdmi_compute_config(struct intel_encoder 
*encoder,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
+   struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
int ret;
 
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -2469,7 +2476,8 @@ int intel_hdmi_compute_config(struct intel_encoder 
*encoder,
pipe_config->lane_count = 4;
 
if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
-  IS_GEMINILAKE(dev_priv))) {
+  (((INTEL_GEN(dev_priv) >= 9)) &&
+   intel_dig_port->lspcon.active))) {
if (scdc->scrambling.low_rates)
pipe_config->hdmi_scrambling = true;
 
@@ -3171,7 +3179,8 @@ void intel_hdmi_init_connector(struct intel_digital_port 
*intel_dig_port,
connector->doublescan_allowed = 0;
connector->stereo_allowed = 1;
 
-   if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+   if (INTEL_GEN(dev_priv) >= 10 ||
+   (((INTEL_GEN(dev_priv) >= 9)) && intel_dig_port->lspcon.active))
connector->ycbcr_420_allowed = true;
 
intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c 
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 5cede4f07f22..be074acd74f3 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -116,6 +116,8 @@ static bool lspcon_detect_hdr_capability(struct 
intel_lspcon *lspcon)
if (lspcon->vendor == LSPCON_VENDOR_MCA)
ret = drm_dp_dpcd_read(>aux, DPCD_MCA_LSPCON_HDR_STATUS,
   _caps, 1);
+   else if (lspcon->vendor == LSPCON_VENDOR_PARADE)
+   return true;
else
return false;
 
@@ -474,7 +476,8 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
 * Todo: Add support for Parade later
 */
if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
-   lspcon->vendor != LSPCON_VENDOR_MCA)
+   (lspcon->vendor != LSPCON_VENDOR_MCA ||
+lspcon->vendor != LSPCON_VENDOR_PARADE))
return;
 
if (lspcon->vendor == LSPCON_VENDOR_MCA) {
@@ -646,7 +649,9 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
return false;
}
 
-   if (lspcon->vendor == LSPCON_VENDOR_MCA && lspcon->hdr_supported)
+   if ((lspcon->vendor == LSPCON_VENDOR_MCA ||
+lspcon->vendor == LSPCON_VENDOR_PARADE) &&
+lspcon->hdr_supported)
drm_object_attach_property(>base,
   
connector->dev->mode_config.hdr_output_metadata_property,
   0);
-- 
2.26.0


[Intel-gfx] [PATCH 2/7] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon

2020-03-26 Thread Vipin Anand
From: Uma Shankar 

Gen9 hardware supports HDMI2.0 through LSPCON chips.
Extending HDR support for MCA LSPCON based GEN9 devices.

SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering Infoframe (DRM packets) and send it to HDR capable
HDMI sink devices.

v2: Re-used hsw infoframe write implementation for HDR metadata
for LSPCON as per Ville's suggestion.

Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/i915/display/intel_hdmi.c   | 10 ++
 drivers/gpu/drm/i915/display/intel_lspcon.c | 35 +++--
 drivers/gpu/drm/i915/display/intel_lspcon.h |  5 ++-
 3 files changed, 39 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 93ac0f296852..9ae2f88cc925 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -577,6 +577,16 @@ static u32 hsw_infoframes_enabled(struct intel_encoder 
*encoder,
return val & mask;
 }
 
+void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
+   const struct intel_crtc_state *crtc_state,
+   unsigned int type,
+   const void *frame, ssize_t len)
+{
+   DRM_DEBUG_KMS("Update HDR metadata for lspcon\n");
+   /* It uses the legacy hsw implementation for the same */
+   hsw_write_infoframe(encoder, crtc_state, type, frame, len);
+}
+
 static const u8 infoframe_type_to_idx[] = {
HDMI_PACKET_TYPE_GENERAL_CONTROL,
HDMI_PACKET_TYPE_GAMUT_METADATA,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c 
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 2e41ae483a23..c5ddabf903d6 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -460,27 +460,42 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
 {
-   bool ret;
+   bool ret = true;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
 
/* LSPCON only needs AVI IF */
-   if (type != HDMI_INFOFRAME_TYPE_AVI)
+   if (!(type == HDMI_INFOFRAME_TYPE_AVI ||
+ type == HDMI_PACKET_TYPE_GAMUT_METADATA))
return;
 
-   if (lspcon->vendor == LSPCON_VENDOR_MCA)
-   ret = _lspcon_write_avi_infoframe_mca(_dp->aux,
- frame, len);
-   else
-   ret = _lspcon_write_avi_infoframe_parade(_dp->aux,
-frame, len);
+   /*
+* Supporting HDR on MCA LSPCON
+* Todo: Add support for Parade later
+*/
+   if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
+   lspcon->vendor != LSPCON_VENDOR_MCA)
+   return;
+
+   if (lspcon->vendor == LSPCON_VENDOR_MCA) {
+   if (type == HDMI_INFOFRAME_TYPE_AVI)
+   ret = _lspcon_write_avi_infoframe_mca(_dp->aux,
+ frame, len);
+   else if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
+   lspcon_drm_write_infoframe(encoder, crtc_state,
+  
HDMI_PACKET_TYPE_GAMUT_METADATA,
+  frame, VIDEO_DIP_DATA_SIZE);
+   } else {
+   ret = _lspcon_write_avi_infoframe_parade(_dp->aux, frame,
+len);
+   }
 
if (!ret) {
-   DRM_ERROR("Failed to write AVI infoframes\n");
+   DRM_ERROR("Failed to write infoframes\n");
return;
}
 
-   DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
+   DRM_DEBUG_DRIVER("Infoframes updated successfully\n");
 }
 
 void lspcon_read_infoframe(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h 
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 37cfddf8a9c5..b2051f236223 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -34,5 +34,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
  const struct intel_crtc_state *pipe_config);
 void lspcon_ycbcr420_config(struct drm_connector *connector,
struct intel_crtc_state *crtc_state);
-
+void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
+   const struct intel_crtc_state *crtc_state,
+   unsigned int type,
+   const void *frame, ssize_t len);
 #endif /* __INTEL_LSPCON_H__ */
-- 
2.26.0

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[Intel-gfx] [PATCH 4/7] drm/i915/display: Set HDR Infoframe for HDR capable LSPCON devices

2020-03-26 Thread Vipin Anand
From: Uma Shankar 

Send Dynamic Range and Mastering Infoframe (DRM for HDR metadata)
as SDP packet to LSPCON following the DP spec. LSPCON receives the
same and sends it to HDMI sink.

v2: Suppressed some warnings. No functional change.

Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/drm_atomic_state_helper.c   | 1 +
 drivers/gpu/drm/drm_atomic_uapi.c   | 1 +
 drivers/gpu/drm/i915/display/intel_lspcon.h | 1 +
 include/drm/drm_connector.h | 1 +
 4 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c 
b/drivers/gpu/drm/drm_atomic_state_helper.c
index 7cf3cf936547..7cf98c06f424 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -468,6 +468,7 @@ __drm_atomic_helper_connector_duplicate_state(struct 
drm_connector *connector,
 
if (state->hdr_output_metadata)
drm_property_blob_get(state->hdr_output_metadata);
+   state->hdr_metadata_changed = false;
 
/* Don't copy over a writeback job, they are used only once */
state->writeback_job = NULL;
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
b/drivers/gpu/drm/drm_atomic_uapi.c
index a1e5e262bae2..4c520e0b9872 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -734,6 +734,7 @@ static int drm_atomic_connector_set_property(struct 
drm_connector *connector,
val,
sizeof(struct hdr_output_metadata), -1,
);
+   state->hdr_metadata_changed |= replaced;
return ret;
} else if (property == config->aspect_ratio_property) {
state->picture_aspect_ratio = val;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h 
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index b2051f236223..bc34124f532e 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -38,4 +38,5 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
const void *frame, ssize_t len);
+
 #endif /* __INTEL_LSPCON_H__ */
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 221910948b37..28df268aa1a7 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -661,6 +661,7 @@ struct drm_connector_state {
 * DRM blob property for HDR output metadata
 */
struct drm_property_blob *hdr_output_metadata;
+   u8 hdr_metadata_changed : 1;
 };
 
 /**
-- 
2.26.0

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[Intel-gfx] [PATCH 0/7] Enable HDR on Gen9 devices with lspcon hdr capability

2020-03-26 Thread Vipin Anand
Initial patch series submitted https://patchwork.freedesktop.org/series/68081/
this patch series add hdr support  for GLK platform, I have added patch to
add checks for all Gen9 platforms with lspcon hdr capability.

Uma Shankar (6):
  drm/i915/display: Add HDR Capability detection for LSPCON
  drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
  drm/i915/display: Attach HDR property for capable Gen9 devices
  drm/i915/display: Set HDR Infoframe for HDR capable LSPCON devices
  drm/i915/display: Enable BT2020 for HDR on LSPCON devices
  drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON

Vipin Anand (1):
  drm:i915:display: add checks for Gen9 devices with hdr capability

 drivers/gpu/drm/drm_atomic_state_helper.c |  1 +
 drivers/gpu/drm/drm_atomic_uapi.c |  1 +
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 16 
 drivers/gpu/drm/i915/display/intel_hdmi.c | 27 +-
 drivers/gpu/drm/i915/display/intel_lspcon.c   | 95 +--
 drivers/gpu/drm/i915/display/intel_lspcon.h   |  4 +
 include/drm/drm_connector.h   |  1 +
 8 files changed, 132 insertions(+), 14 deletions(-)

-- 
2.26.0

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[Intel-gfx] [PATCH 6/7] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON

2020-03-26 Thread Vipin Anand
From: Uma Shankar 

Blanking needs to be reduced to incorporate DP and HDMI timing/link
bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
This will cause mode to blank out. Reduced Htotal by shortening the
back porch and front porch within permissible limits.

v2: This is marked as Not for merge and the responsibilty to program
these custom timings will be on userspace. This patch is just for
reference purposes. This is based on Ville's recommendation.

Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index c7424e2a04a3..3ab1fadb2ea3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -616,9 +616,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
 {
struct intel_dp *intel_dp = 
intel_attached_dp(to_intel_connector(connector));
struct intel_connector *intel_connector = to_intel_connector(connector);
+   struct intel_encoder *intel_encoder = 
intel_attached_encoder(intel_connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_i915_private *dev_priv = to_i915(connector->dev);
int target_clock = mode->clock;
+   struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder);
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk;
u16 dsc_max_output_bpp = 0;
@@ -638,6 +640,20 @@ intel_dp_mode_valid(struct drm_connector *connector,
 
target_clock = fixed_mode->clock;
}
+   /*
+* Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
+* limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
+* while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
+* cause mode to blank out. Reduced Htotal by shortening the back porch
+* and front porch within permissible limits.
+*/
+   if (lspcon->active && lspcon->hdr_supported &&
+   mode->clock > 57) {
+   mode->clock = 57;
+   mode->htotal -= 180;
+   mode->hsync_start -= 72;
+   mode->hsync_end -= 72;
+   }
 
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
-- 
2.26.0

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[Intel-gfx] [PATCH 5/7] drm/i915/display: Enable BT2020 for HDR on LSPCON devices

2020-03-26 Thread Vipin Anand
From: Uma Shankar 

Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
data for HDR using AVI infoframe. LSPCON firmware expects this and though
SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
which transfers the same to HDMI sink.

Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c 
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 4d8027493f2c..5cede4f07f22 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -506,6 +506,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder,
/* FIXME implement this */
 }
 
+/* HDMI HDR Colorspace Spec Definitions */
+#define NORMAL_COLORIMETRY_MASK0x3
+#define EXTENDED_COLORIMETRY_MASK  0x7
+#define HDMI_COLORIMETRY_BT2020_YCC((3 << 0) | (6 << 2) | (0 << 5))
+
 void lspcon_set_infoframes(struct intel_encoder *encoder,
   bool enable,
   const struct intel_crtc_state *crtc_state,
@@ -550,6 +555,19 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
   HDMI_QUANTIZATION_RANGE_LIMITED :
   HDMI_QUANTIZATION_RANGE_FULL);
 
+   /*
+* Set BT2020 colorspace if driving HDR data
+* ToDo: Make this generic and expose all colorspaces for lspcon
+*/
+   if (lspcon->active && conn_state->hdr_metadata_changed) {
+   frame.avi.colorimetry =
+   HDMI_COLORIMETRY_BT2020_YCC &
+   NORMAL_COLORIMETRY_MASK;
+   frame.avi.extended_colorimetry =
+   (HDMI_COLORIMETRY_BT2020_YCC >> 2) &
+EXTENDED_COLORIMETRY_MASK;
+   }
+
ret = hdmi_infoframe_pack(, buf, sizeof(buf));
if (ret < 0) {
DRM_ERROR("Failed to pack AVI IF\n");
-- 
2.26.0

___
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[Intel-gfx] [PATCH 3/7] drm/i915/display: Attach HDR property for capable Gen9 devices

2020-03-26 Thread Vipin Anand
From: Uma Shankar 

Attach HDR property for Gen9 devices with MCA LSPCON
chips.

Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c 
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index c5ddabf903d6..4d8027493f2c 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -628,6 +628,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
return false;
}
 
+   if (lspcon->vendor == LSPCON_VENDOR_MCA && lspcon->hdr_supported)
+   drm_object_attach_property(>base,
+  
connector->dev->mode_config.hdr_output_metadata_property,
+  0);
+
connector->ycbcr_420_allowed = true;
lspcon->active = true;
DRM_DEBUG_KMS("Success: LSPCON init\n");
-- 
2.26.0

___
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Re: [Intel-gfx] [PATCH] drm/i915/perf: Do not clear pollin for small user read buffers

2020-03-26 Thread Dixit, Ashutosh
On Thu, 26 Mar 2020 02:09:34 -0700, Lionel Landwerlin wrote:
>
> On 26/03/2020 06:43, Ashutosh Dixit wrote:
> > It is wrong to block the user thread in the next poll when OA data is
> > already available which could not fit in the user buffer provided in
> > the previous read. In several cases the exact user buffer size is not
> > known. Blocking user space in poll can lead to data loss when the
> > buffer size used is smaller than the available data.
> >
> > This change fixes this issue and allows user space to read all OA data
> > even when using a buffer size smaller than the available data using
> > multiple non-blocking reads rather than staying blocked in poll till
> > the next timer interrupt.
> >
> > v2: Fix ret value for blocking reads (Umesh)
> >
> > Cc: Umesh Nerlige Ramappa 
> > Cc: Lionel Landwerlin 
> > Signed-off-by: Ashutosh Dixit 
> > ---
> >   drivers/gpu/drm/i915/i915_perf.c | 63 ++--
> >   1 file changed, 12 insertions(+), 51 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c 
> > b/drivers/gpu/drm/i915/i915_perf.c
> > index 3222f6cd8255..e2d083efba6d 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -2957,49 +2957,6 @@ void i915_oa_init_reg_state(const struct 
> > intel_context *ce,
> > gen8_update_reg_state_unlocked(ce, stream);
> >   }
> >   -/**
> > - * i915_perf_read_locked - _perf_stream_ops->read with error 
> > normalisation
> > - * @stream: An i915 perf stream
> > - * @file: An i915 perf stream file
> > - * @buf: destination buffer given by userspace
> > - * @count: the number of bytes userspace wants to read
> > - * @ppos: (inout) file seek position (unused)
> > - *
> > - * Besides wrapping _perf_stream_ops->read this provides a common 
> > place to
> > - * ensure that if we've successfully copied any data then reporting that 
> > takes
> > - * precedence over any internal error status, so the data isn't lost.
> > - *
> > - * For example ret will be -ENOSPC whenever there is more buffered data 
> > than
> > - * can be copied to userspace, but that's only interesting if we weren't 
> > able
> > - * to copy some data because it implies the userspace buffer is too small 
> > to
> > - * receive a single record (and we never split records).
> > - *
> > - * Another case with ret == -EFAULT is more of a grey area since it would 
> > seem
> > - * like bad form for userspace to ask us to overrun its buffer, but the 
> > user
> > - * knows best:
> > - *
> > - *   http://yarchive.net/comp/linux/partial_reads_writes.html
> > - *
> > - * Returns: The number of bytes copied or a negative error code on failure.
> > - */
> > -static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream,
> > -struct file *file,
> > -char __user *buf,
> > -size_t count,
> > -loff_t *ppos)
> > -{
> > -   /* Note we keep the offset (aka bytes read) separate from any
> > -* error status so that the final check for whether we return
> > -* the bytes read with a higher precedence than any error (see
> > -* comment below) doesn't need to be handled/duplicated in
> > -* stream->ops->read() implementations.
> > -*/
> > -   size_t offset = 0;
> > -   int ret = stream->ops->read(stream, buf, count, );
> > -
> > -   return offset ?: (ret ?: -EAGAIN);
> > -}
> > -
> >   /**
> >* i915_perf_read - handles read() FOP for i915 perf stream FDs
> >* @file: An i915 perf stream file
> > @@ -3025,6 +2982,8 @@ static ssize_t i915_perf_read(struct file *file,
> >   {
> > struct i915_perf_stream *stream = file->private_data;
> > struct i915_perf *perf = stream->perf;
> > +   size_t offset = 0;
> > +   int __ret;
> > ssize_t ret;
> > /* To ensure it's handled consistently we simply treat all 
> > reads of
> > a
> > @@ -3048,16 +3007,19 @@ static ssize_t i915_perf_read(struct file *file,
> > return ret;
> > mutex_lock(>lock);
> > -   ret = i915_perf_read_locked(stream, file,
> > -   buf, count, ppos);
> > +   __ret = stream->ops->read(stream, buf, count, );
> > +   ret = offset ?: (__ret ?: -EAGAIN);
> > mutex_unlock(>lock);
> > } while (ret == -EAGAIN);
> > } else {
> > mutex_lock(>lock);
> > -   ret = i915_perf_read_locked(stream, file, buf, count, ppos);
> > +   __ret = stream->ops->read(stream, buf, count, );
> > +   ret = offset ?: (__ret ?: -EAGAIN);
> > mutex_unlock(>lock);
> > }
> >   + /* Possible values for __ret are 0, -EFAULT, -ENOSPC, -EAGAIN,
> > ... */
> > +
> > /* We allow the poll checking to sometimes report false positive EPOLLIN
> >  * events where we might actually report EAGAIN on 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Make Wa_14010229206 permanent

2020-03-26 Thread Patchwork
== Series Details ==

Series: drm/i915/tgl: Make Wa_14010229206 permanent
URL   : https://patchwork.freedesktop.org/series/75139/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8197 -> Patchwork_17107


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/index.html

Known issues


  Here are the changes found in Patchwork_17107 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@execlists:
- fi-skl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#656])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-skl-guc/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/fi-skl-guc/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gem_contexts:
- fi-cml-s:   [PASS][3] -> [DMESG-FAIL][4] ([i915#877])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/fi-cml-s/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@hangcheck:
- fi-icl-y:   [PASS][5] -> [INCOMPLETE][6] ([fdo#108569])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-icl-y/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/fi-icl-y/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
  [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877


Participating hosts (44 -> 39)
--

  Additional (2): fi-kbl-r fi-kbl-7500u 
  Missing(7): fi-hsw-4200u fi-byt-squawks fi-icl-guc fi-bwr-2160 
fi-bsw-cyan fi-byt-n2820 fi-bdw-samus 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8197 -> Patchwork_17107

  CI-20190529: 20190529
  CI_DRM_8197: 198bab1da198b9d6d5c36d52704dd4abab6e81a8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17107: 1ecd505ffa0483c39d25bd333b360ecea7eda96e @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1ecd505ffa04 drm/i915/tgl: Make Wa_14010229206 permanent

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/index.html
___
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Re: [Intel-gfx] [PATCH] drm/i915/perf: Do not clear pollin for small user read buffers

2020-03-26 Thread Dixit, Ashutosh
On Thu, 26 Mar 2020 11:02:46 -0700, Umesh Nerlige Ramappa wrote:
> On Wed, Mar 25, 2020 at 06:52:52PM -0700, Dixit, Ashutosh wrote:
> > On Wed, 25 Mar 2020 17:32:35 -0700, Umesh Nerlige Ramappa wrote:
> >>
> >> On Wed, Mar 25, 2020 at 11:20:19AM -0700, Ashutosh Dixit wrote:
> >> >
> >> > +/* Possible values for __ret are 0, -EFAULT, -ENOSPC, -EAGAIN, 
> >> > ... */
> >>
> >> __ret may never be EAGAIN either (comment^). I don't see EAGAIN in the read
> >> path.
> >
> > It's here:
> >
> > gen8_append_oa_reports()
> > {
> >
> >/*
> > * An invalid tail pointer here means we're still waiting for the 
> > poll
> > * hrtimer callback to give us a pointer
> > */
> >if (tail == INVALID_TAIL_PTR)
> >return -EAGAIN;
> > }
>
> Oh, you are right, EAGAIN is returned here. I was looking for it with the
> poll period patch series applied and these references are removed in that
> series.

No, you are right, since that series is likely to be merged first, it is
better to remove it from this patch.
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context

2020-03-26 Thread Patchwork
== Series Details ==

Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on 
ELSP[1] promotion to idle context
URL   : https://patchwork.freedesktop.org/series/75138/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8197 -> Patchwork_17106


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/index.html

Known issues


  Here are the changes found in Patchwork_17106 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@execlists:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-apl-guc/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-apl-guc/igt@i915_selftest@l...@execlists.html
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#140])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
- fi-cml-s:   [PASS][5] -> [INCOMPLETE][6] ([i915#283])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cml-s/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-cml-s/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2:  [PASS][7] -> [FAIL][8] ([i915#262])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html

  
 Possible fixes 

  * igt@i915_selftest@live@late_gt_pm:
- fi-bwr-2160:[INCOMPLETE][9] -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
  [i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647
  [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656


Participating hosts (44 -> 41)
--

  Additional (2): fi-kbl-r fi-kbl-7500u 
  Missing(5): fi-hsw-4770r fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-bdw-samus 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8197 -> Patchwork_17106

  CI-20190529: 20190529
  CI_DRM_8197: 198bab1da198b9d6d5c36d52704dd4abab6e81a8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17106: 185b85c7368afa95d0c352b09e7ac161ae19e2bc @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

185b85c7368a drm/i915/execlists: Explicitly reset both reg and context runtime
d6626ef65d6d drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle 
context

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/index.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context

2020-03-26 Thread Patchwork
== Series Details ==

Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on 
ELSP[1] promotion to idle context
URL   : https://patchwork.freedesktop.org/series/75137/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8197 -> Patchwork_17105


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_17105 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17105, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_17105:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@execlists:
- fi-skl-guc: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-skl-guc/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-skl-guc/igt@i915_selftest@l...@execlists.html
- fi-cfl-guc: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cfl-guc/igt@i915_selftest@l...@execlists.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-cfl-guc/igt@i915_selftest@l...@execlists.html

  
Known issues


  Here are the changes found in Patchwork_17105 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@execlists:
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-apl-guc/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-apl-guc/igt@i915_selftest@l...@execlists.html
- fi-icl-dsi: [PASS][7] -> [INCOMPLETE][8] ([i915#140])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
- fi-cml-u2:  [PASS][9] -> [INCOMPLETE][10] ([i915#283])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cml-u2/igt@i915_selftest@l...@execlists.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-cml-u2/igt@i915_selftest@l...@execlists.html

  
 Possible fixes 

  * igt@i915_selftest@live@late_gt_pm:
- fi-bwr-2160:[INCOMPLETE][11] -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
  [i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647


Participating hosts (44 -> 35)
--

  Additional (2): fi-kbl-r fi-kbl-7500u 
  Missing(11): fi-hsw-4770r fi-bxt-dsi fi-bdw-samus fi-bsw-n3050 
fi-byt-j1900 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-kbl-7560u 
fi-skl-6600u 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8197 -> Patchwork_17105

  CI-20190529: 20190529
  CI_DRM_8197: 198bab1da198b9d6d5c36d52704dd4abab6e81a8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17105: ad443fa00c35a13b98b4452da2be652582c3f1d5 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ad443fa00c35 drm/i915/execlists: Explicitly reset both reg and context runtime
5868edb0b7b7 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle 
context

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context

2020-03-26 Thread Patchwork
== Series Details ==

Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on 
ELSP[1] promotion to idle context
URL   : https://patchwork.freedesktop.org/series/75138/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d6626ef65d6d drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle 
context
-:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#29: 
  process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, 
ctl:, mode:0200}

total: 0 errors, 1 warnings, 0 checks, 126 lines checked
185b85c7368a drm/i915/execlists: Explicitly reset both reg and context runtime

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[Intel-gfx] [PATCH] drm/i915/tgl: Make Wa_14010229206 permanent

2020-03-26 Thread Swathi Dhanavanthri
This workaround now applies to all steppings, not just A0.
Wa_1409085225 is a temporary A0-only W/A however it is
identical to Wa_14010229206 and hence the combined workaround
is made permanent.
Bspec: 52890

Signed-off-by: Swathi Dhanavanthri 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e96cc7fa0936..c3c42cf614a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1380,12 +1380,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
-   /*
-* Wa_1409085225:tgl
-* Wa_14010229206:tgl
-*/
-   wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
-
/* Wa_1408615072:tgl */
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
VSUNIT_CLKGATE_DIS_TGL);
@@ -1403,6 +1397,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
wa_masked_en(wal,
 GEN9_CS_DEBUG_MODE1,
 FF_DOP_CLOCK_GATE_DISABLE);
+   /*
+* Wa_1409085225:tgl
+* Wa_14010229206:tgl
+*/
+   wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
}
 
if (IS_GEN(i915, 11)) {
-- 
2.20.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context

2020-03-26 Thread Patchwork
== Series Details ==

Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on 
ELSP[1] promotion to idle context
URL   : https://patchwork.freedesktop.org/series/75137/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5868edb0b7b7 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle 
context
-:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#29: 
  process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, 
ctl:, mode:0200}

total: 0 errors, 1 warnings, 0 checks, 116 lines checked
ad443fa00c35 drm/i915/execlists: Explicitly reset both reg and context runtime

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[Intel-gfx] [PATCH 2/2] drm/i915/execlists: Explicitly reset both reg and context runtime

2020-03-26 Thread Chris Wilson
Upon a GPU reset, we copy the default context image over top of the
guilty image. This will rollback the CTX_TIMESTAMP register to before
our value of ce->runtime.last. Reset both back to 0 so that we do not
encounter an underflow on the next schedule out after resume.

This should not be a huge issue in practice, as hangs should be rare in
correct code.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4edda15eba26..47cec545a069 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -238,6 +238,17 @@ __execlists_update_reg_state(const struct intel_context 
*ce,
 const struct intel_engine_cs *engine,
 u32 head);
 
+static u32 intel_context_get_runtime(const struct intel_context *ce)
+{
+   /*
+* We can use either ppHWSP[16] which is recorded before the context
+* switch (and so excludes the cost of context switches) or use the
+* value from the context image itself, which is saved/restored earlier
+* and so includes the cost of the save.
+*/
+   return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
+}
+
 static void mark_eio(struct i915_request *rq)
 {
if (i915_request_completed(rq))
@@ -1154,6 +1165,7 @@ static void restore_default_state(struct intel_context 
*ce,
   engine->context_size - PAGE_SIZE);
 
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+   ce->runtime.last = intel_context_get_runtime(ce);
 }
 
 static void reset_active(struct i915_request *rq,
@@ -1195,17 +1207,6 @@ static void reset_active(struct i915_request *rq,
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
 }
 
-static u32 intel_context_get_runtime(const struct intel_context *ce)
-{
-   /*
-* We can use either ppHWSP[16] which is recorded before the context
-* switch (and so excludes the cost of context switches) or use the
-* value from the context image itself, which is saved/restored earlier
-* and so includes the cost of the save.
-*/
-   return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
-}
-
 static void st_update_runtime_underflow(struct intel_context *ce, s32 dt)
 {
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
@@ -4581,6 +4582,7 @@ static void init_common_reg_state(u32 * const regs,
regs[CTX_CONTEXT_CONTROL] = ctl;
 
regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
+   regs[CTX_TIMESTAMP] = 0;
 }
 
 static void init_wa_bb_reg_state(u32 * const regs,
-- 
2.20.1

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[Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context

2020-03-26 Thread Chris Wilson
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).

  process_csb: vecs0: cs-irq head=0, tail=1
  process_csb: vecs0: csb[1]: status=0x0882:0x0020
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
  trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
  process_csb: vecs0: cs-irq head=1, tail=2
  process_csb: vecs0: csb[2]: status=0x0814:0x0040
  trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
  process_csb: vecs0: cs-irq head=2, tail=5
  process_csb: vecs0: csb[3]: status=0x0812:0x0020
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
  process_csb: vecs0: csb[4]: status=0x0814:0x0060
  trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
  process_csb: vecs0: csb[5]: status=0x0818:0x0020
  trace_ports: vecs0: completed { 8c0:32, 0:0 }
  process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, 
ctl:, mode:0200}
  process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, 
hwsp:30},
  process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
  process_csb: GEM_BUG_ON("context completed before request")

Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 72 ++---
 1 file changed, 36 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..4edda15eba26 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request 
**ports, int count)
memset_p((void **)ports, NULL, count);
 }
 
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
 {
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 execlists->queue_priority_hint);
record_preemption(execlists);
 
-   /*
-* Don't let the RING_HEAD advance past the breadcrumb
-* as we unwind (and until we resubmit) so that we do
-* not accidentally tell it to go backwards.
-*/
-   ring_set_paused(engine, 1);
-
/*
 * Note that we have not stopped the GPU at this point,
 * so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 last->sched.attr.priority,
 execlists->queue_priority_hint);
 
-   ring_set_paused(engine, 1);
defer_active(engine);
 
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * of timeslices, our queue might be.
 */
start_timeslice(engine);
-   return;
+   return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
}
 
if (last && !can_merge_rq(last, rq)) {
+   /* leave this for another sibling */
spin_unlock(>base.active.lock);
start_timeslice(engine);
-   return; /* leave this for another sibling */
+   return false;
}
 
ENGINE_TRACE(engine,
@@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * interrupt for secondary ports).
 */
execlists->queue_priority_hint = queue_prio(execlists);
+   if (!submit)
+   return false;
 
-   if (submit) {
-   *port = execlists_schedule_in(last, port - execlists->pending);
-   execlists->switch_priority_hint =
-   

[Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context

2020-03-26 Thread Chris Wilson
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).

  process_csb: vecs0: cs-irq head=0, tail=1
  process_csb: vecs0: csb[1]: status=0x0882:0x0020
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
  trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
  process_csb: vecs0: cs-irq head=1, tail=2
  process_csb: vecs0: csb[2]: status=0x0814:0x0040
  trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
  process_csb: vecs0: cs-irq head=2, tail=5
  process_csb: vecs0: csb[3]: status=0x0812:0x0020
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
  process_csb: vecs0: csb[4]: status=0x0814:0x0060
  trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
  process_csb: vecs0: csb[5]: status=0x0818:0x0020
  trace_ports: vecs0: completed { 8c0:32, 0:0 }
  process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, 
ctl:, mode:0200}
  process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, 
hwsp:30},
  process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
  process_csb: GEM_BUG_ON("context completed before request")

Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 68 ++---
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..132816235d8a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request 
**ports, int count)
memset_p((void **)ports, NULL, count);
 }
 
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
 {
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 execlists->queue_priority_hint);
record_preemption(execlists);
 
-   /*
-* Don't let the RING_HEAD advance past the breadcrumb
-* as we unwind (and until we resubmit) so that we do
-* not accidentally tell it to go backwards.
-*/
-   ring_set_paused(engine, 1);
-
/*
 * Note that we have not stopped the GPU at this point,
 * so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 last->sched.attr.priority,
 execlists->queue_priority_hint);
 
-   ring_set_paused(engine, 1);
defer_active(engine);
 
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * of timeslices, our queue might be.
 */
start_timeslice(engine);
-   return;
+   return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
}
 
if (last && !can_merge_rq(last, rq)) {
+   /* leave this for another sibling */
spin_unlock(>base.active.lock);
start_timeslice(engine);
-   return; /* leave this for another sibling */
+   return false;
}
 
ENGINE_TRACE(engine,
@@ -2193,32 +2186,30 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * interrupt for secondary ports).
 */
execlists->queue_priority_hint = queue_prio(execlists);
+   if (!submit)
+   return false;
 
-   if (submit) {
-   *port = execlists_schedule_in(last, port - execlists->pending);
-   execlists->switch_priority_hint =
-   

[Intel-gfx] [PATCH 2/2] drm/i915/execlists: Explicitly reset both reg and context runtime

2020-03-26 Thread Chris Wilson
Upon a GPU reset, we copy the default context image over top of the
guilty image. This will rollback the CTX_TIMESTAMP register to before
our value of ce->runtime.last. Reset both back to 0 so that we do not
encounter an underflow on the next schedule out after resume.

This should not be a huge issue in practice, as hangs should be rare in
correct code.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 132816235d8a..987dbdf2542e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -238,6 +238,17 @@ __execlists_update_reg_state(const struct intel_context 
*ce,
 const struct intel_engine_cs *engine,
 u32 head);
 
+static u32 intel_context_get_runtime(const struct intel_context *ce)
+{
+   /*
+* We can use either ppHWSP[16] which is recorded before the context
+* switch (and so excludes the cost of context switches) or use the
+* value from the context image itself, which is saved/restored earlier
+* and so includes the cost of the save.
+*/
+   return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
+}
+
 static void mark_eio(struct i915_request *rq)
 {
if (i915_request_completed(rq))
@@ -1154,6 +1165,7 @@ static void restore_default_state(struct intel_context 
*ce,
   engine->context_size - PAGE_SIZE);
 
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+   ce->runtime.last = intel_context_get_runtime(ce);
 }
 
 static void reset_active(struct i915_request *rq,
@@ -1195,17 +1207,6 @@ static void reset_active(struct i915_request *rq,
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
 }
 
-static u32 intel_context_get_runtime(const struct intel_context *ce)
-{
-   /*
-* We can use either ppHWSP[16] which is recorded before the context
-* switch (and so excludes the cost of context switches) or use the
-* value from the context image itself, which is saved/restored earlier
-* and so includes the cost of the save.
-*/
-   return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
-}
-
 static void st_update_runtime_underflow(struct intel_context *ce, s32 dt)
 {
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
@@ -4581,6 +4582,7 @@ static void init_common_reg_state(u32 * const regs,
regs[CTX_CONTEXT_CONTROL] = ctl;
 
regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
+   regs[CTX_TIMESTAMP] = 0;
 }
 
 static void init_wa_bb_reg_state(u32 * const regs,
-- 
2.20.1

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Re: [Intel-gfx] [PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma

2020-03-26 Thread Jani Nikula
On Thu, 26 Mar 2020, Nathan Chancellor  wrote:
> This is the only warning on an x86_64 defconfig build. Apologies if we
> are being too persistent or nagging but we need guidance from the i915
> maintainers on which solution they would prefer so it can be picked up.
> I understand you all are busy and I appreciate the work you all do but
> I do not want this to fall between the cracks because it is annoying to
> constantly see this warning.

Apologies for the delay. As I replied first thing in this thread, this
works for me. Thanks for the patch, pushed to drm-intel-next-queued.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev2)

2020-03-26 Thread Patchwork
== Series Details ==

Series: drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle 
context (rev2)
URL   : https://patchwork.freedesktop.org/series/75130/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17104


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/index.html

Known issues


  Here are the changes found in Patchwork_17104 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@execlists:
- fi-cml-s:   [PASS][1] -> [INCOMPLETE][2] ([i915#283])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cml-s/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-cml-s/igt@i915_selftest@l...@execlists.html
- fi-icl-y:   [PASS][3] -> [INCOMPLETE][4] ([i915#140])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-y/igt@i915_selftest@l...@execlists.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-icl-y/igt@i915_selftest@l...@execlists.html
- fi-bxt-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-icl-u2:  [INCOMPLETE][7] ([fdo#108569]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html

  
 Warnings 

  * igt@i915_selftest@live@execlists:
- fi-icl-dsi: [DMESG-FAIL][9] ([fdo#108569]) -> [INCOMPLETE][10] 
([i915#140])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-icl-dsi/igt@i915_selftest@l...@execlists.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
  [i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647


Participating hosts (49 -> 38)
--

  Missing(11): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-ivb-3770 fi-kbl-7560u fi-byt-clapper fi-bsw-nick fi-bdw-samus 
fi-snb-2600 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8195 -> Patchwork_17104

  CI-20190529: 20190529
  CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17104: f75f1d1d76f832a0e3d9d64dd675ceb56040582c @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f75f1d1d76f8 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle 
context

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev2)

2020-03-26 Thread Patchwork
== Series Details ==

Series: drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle 
context (rev2)
URL   : https://patchwork.freedesktop.org/series/75130/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f75f1d1d76f8 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle 
context
-:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#29: 
  process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, 
ctl:, mode:0200}

total: 0 errors, 1 warnings, 0 checks, 125 lines checked

___
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[Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev3)

2020-03-26 Thread Patchwork
== Series Details ==

Series: SAGV support for Gen12+ (rev3)
URL   : https://patchwork.freedesktop.org/series/75129/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17103


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/index.html

Known issues


  Here are the changes found in Patchwork_17103 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-apl-guc/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/fi-apl-guc/igt@i915_selftest@l...@hangcheck.html

  
 Possible fixes 

  * igt@i915_selftest@live@execlists:
- fi-icl-dsi: [DMESG-FAIL][3] ([fdo#108569]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/fi-icl-dsi/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- fi-icl-u2:  [INCOMPLETE][5] ([fdo#108569]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569


Participating hosts (49 -> 37)
--

  Missing(12): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u fi-hsw-peppy 
fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-bsw-kefka fi-kbl-7560u 
fi-byt-clapper fi-skl-6600u 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8195 -> Patchwork_17103

  CI-20190529: 20190529
  CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17103: 17b1ab4ef65f19f4159f1dcf8939b989d1cf83b9 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

17b1ab4ef65f drm/i915: Enable SAGV support for Gen12
9ab9d139acd7 drm/i915: Restrict qgv points which don't have enough bandwidth.
7ddef9fc5a42 drm/i915: Rename bw_state to new_bw_state
5ac95b3960a7 drm/i915: Added required new PCode commands
37f392cf14b8 drm/i915: Add proper SAGV support for TGL+
345239c1e284 drm/i915: Extract gen specific functions from intel_can_enable_sagv
9cd6396bdbd9 drm/i915: Add intel_atomic_get_bw_*_state helpers
b76321aa6824 drm/i915: Introduce skl_plane_wm_level accessor.
930754956920 drm/i915: Eliminate magic numbers "0" and "1" from color plane
ad8810ff373a drm/i915: Start passing latency as parameter

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev3)

2020-03-26 Thread Patchwork
== Series Details ==

Series: SAGV support for Gen12+ (rev3)
URL   : https://patchwork.freedesktop.org/series/75129/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ad8810ff373a drm/i915: Start passing latency as parameter
930754956920 drm/i915: Eliminate magic numbers "0" and "1" from color plane
-:118: WARNING:LONG_LINE: line over 100 characters
#118: FILE: drivers/gpu/drm/i915/intel_pm.c:4541:
+   rate = skl_plane_relative_data_rate(crtc_state, 
plane_state, COLOR_PLANE_UV);

total: 0 errors, 1 warnings, 0 checks, 163 lines checked
b76321aa6824 drm/i915: Introduce skl_plane_wm_level accessor.
9cd6396bdbd9 drm/i915: Add intel_atomic_get_bw_*_state helpers
345239c1e284 drm/i915: Extract gen specific functions from intel_can_enable_sagv
37f392cf14b8 drm/i915: Add proper SAGV support for TGL+
-:234: WARNING:BRACES: braces {} are not necessary for single statement blocks
#234: FILE: drivers/gpu/drm/i915/display/intel_display.c:15662:
+   if (bw_state && state->modeset && 
intel_can_enable_sagv(bw_state)) {
+   intel_enable_sagv(dev_priv);
+   }

-:341: WARNING:BRACES: braces {} are not necessary for any arm of this statement
#341: FILE: drivers/gpu/drm/i915/intel_pm.c:3874:
+   if (INTEL_GEN(dev_priv) >= 12) {
[...]
+   } else if (INTEL_GEN(dev_priv) >= 11) {
[...]
+   } else {
[...]

total: 0 errors, 2 warnings, 0 checks, 480 lines checked
5ac95b3960a7 drm/i915: Added required new PCode commands
7ddef9fc5a42 drm/i915: Rename bw_state to new_bw_state
9ab9d139acd7 drm/i915: Restrict qgv points which don't have enough bandwidth.
17b1ab4ef65f drm/i915: Enable SAGV support for Gen12

___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Re-org uC debugfs files and move them under GT (rev3)

2020-03-26 Thread Patchwork
== Series Details ==

Series: Re-org uC debugfs files and move them under GT (rev3)
URL   : https://patchwork.freedesktop.org/series/74051/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17102


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17102/index.html

Known issues


  Here are the changes found in Patchwork_17102 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@i915_selftest@live@execlists:
- fi-icl-dsi: [DMESG-FAIL][1] ([fdo#108569]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17102/fi-icl-dsi/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- fi-icl-u2:  [INCOMPLETE][3] ([fdo#108569]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17102/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569


Participating hosts (49 -> 38)
--

  Missing(11): fi-ilk-m540 fi-kbl-7560u fi-hsw-4200u fi-skl-guc 
fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-blb-e6850 fi-byt-clapper 
fi-bdw-samus fi-snb-2600 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8195 -> Patchwork_17102

  CI-20190529: 20190529
  CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17102: 209216ba5e1f65dfed02f205abefae348e040176 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

209216ba5e1f drm/i915/uc: do not free err log on uc_fini
33c4bb916643 drm/i915/uc: Move uC debugfs to its own folder under GT
ada6ea1bdc35 drm/i915/debugfs: move uC printers and update debugfs file names
6d5324446d31 drm/i915/huc: make "support huc" reflect HW capabilities
72a498f33e07 drm/i915/guc: drop stage_pool debugfs
e19786b07259 drm/i915/gt: allow setting generic data pointer

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17102/index.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Check timeout before flush and cond checks

2020-03-26 Thread Patchwork
== Series Details ==

Series: drm/i915/selftests: Check timeout before flush and cond checks
URL   : https://patchwork.freedesktop.org/series/75126/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17100


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_17100 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17100, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_17100:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@execlists:
- fi-skl-lmem:[PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
- fi-skl-guc: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-guc/igt@i915_selftest@l...@execlists.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-skl-guc/igt@i915_selftest@l...@execlists.html
- fi-cfl-guc: [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cfl-guc/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-cfl-guc/igt@i915_selftest@l...@execlists.html
- fi-bdw-5557u:   [PASS][7] -> [INCOMPLETE][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-bdw-5557u/igt@i915_selftest@l...@execlists.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-bdw-5557u/igt@i915_selftest@l...@execlists.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@execlists:
- {fi-ehl-1}: [PASS][9] -> [INCOMPLETE][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-ehl-1/igt@i915_selftest@l...@execlists.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-ehl-1/igt@i915_selftest@l...@execlists.html

  
Known issues


  Here are the changes found in Patchwork_17100 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@execlists:
- fi-kbl-r:   [PASS][11] -> [INCOMPLETE][12] ([fdo#112175] / 
[fdo#112259])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-r/igt@i915_selftest@l...@execlists.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-kbl-r/igt@i915_selftest@l...@execlists.html
- fi-apl-guc: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927] / 
[fdo#112175])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-apl-guc/igt@i915_selftest@l...@execlists.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-apl-guc/igt@i915_selftest@l...@execlists.html
- fi-kbl-x1275:   [PASS][15] -> [INCOMPLETE][16] ([fdo#112259])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
- fi-skl-6600u:   [PASS][17] -> [INCOMPLETE][18] ([i915#1260])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-6600u/igt@i915_selftest@l...@execlists.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-skl-6600u/igt@i915_selftest@l...@execlists.html
- fi-cml-s:   [PASS][19] -> [INCOMPLETE][20] ([i915#283])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cml-s/igt@i915_selftest@l...@execlists.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-cml-s/igt@i915_selftest@l...@execlists.html
- fi-skl-6700k2:  [PASS][21] -> [INCOMPLETE][22] ([fdo#112175])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html
- fi-icl-y:   [PASS][23] -> [INCOMPLETE][24] ([i915#140])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-y/igt@i915_selftest@l...@execlists.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-icl-y/igt@i915_selftest@l...@execlists.html
- fi-bxt-dsi: [PASS][25] -> [INCOMPLETE][26] ([fdo#103927])
   [25]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Re-org uC debugfs files and move them under GT (rev3)

2020-03-26 Thread Patchwork
== Series Details ==

Series: Re-org uC debugfs files and move them under GT (rev3)
URL   : https://patchwork.freedesktop.org/series/74051/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e19786b07259 drm/i915/gt: allow setting generic data pointer
72a498f33e07 drm/i915/guc: drop stage_pool debugfs
6d5324446d31 drm/i915/huc: make "support huc" reflect HW capabilities
ada6ea1bdc35 drm/i915/debugfs: move uC printers and update debugfs file names
33c4bb916643 drm/i915/uc: Move uC debugfs to its own folder under GT
-:97: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#97: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 516 lines checked
209216ba5e1f drm/i915/uc: do not free err log on uc_fini

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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/execlists: Explicitly reset both reg and context runtime

2020-03-26 Thread Patchwork
== Series Details ==

Series: drm/i915/execlists: Explicitly reset both reg and context runtime
URL   : https://patchwork.freedesktop.org/series/75127/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/gt/intel_lrc.o
drivers/gpu/drm/i915/gt/intel_lrc.c: In function ‘restore_default_state’:
drivers/gpu/drm/i915/gt/intel_lrc.c:1157:21: error: implicit declaration of 
function ‘intel_context_get_runtime’; did you mean 
‘intel_context_get_avg_runtime_ns’? [-Werror=implicit-function-declaration]
  ce->runtime.last = intel_context_get_runtime(ce);
 ^
 intel_context_get_avg_runtime_ns
drivers/gpu/drm/i915/gt/intel_lrc.c: At top level:
drivers/gpu/drm/i915/gt/intel_lrc.c:1199:12: error: conflicting types for 
‘intel_context_get_runtime’
 static u32 intel_context_get_runtime(const struct intel_context *ce)
^
drivers/gpu/drm/i915/gt/intel_lrc.c:1157:21: note: previous implicit 
declaration of ‘intel_context_get_runtime’ was here
  ce->runtime.last = intel_context_get_runtime(ce);
 ^
cc1: all warnings being treated as errors
scripts/Makefile.build:267: recipe for target 
'drivers/gpu/drm/i915/gt/intel_lrc.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_lrc.o] Error 1
scripts/Makefile.build:505: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:505: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:505: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1683: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf

2020-03-26 Thread Patchwork
== Series Details ==

Series: series starting with [01/12] drm/i915/selftests: Add request throughput 
measurement to perf
URL   : https://patchwork.freedesktop.org/series/75124/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17099


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_17099 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17099, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_17099:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@execlists:
- fi-skl-lmem:[PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
- fi-skl-guc: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-guc/igt@i915_selftest@l...@execlists.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-skl-guc/igt@i915_selftest@l...@execlists.html
- fi-cfl-guc: [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cfl-guc/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-cfl-guc/igt@i915_selftest@l...@execlists.html

  
New tests
-

  New tests have been introduced between CI_DRM_8195 and Patchwork_17099:

### New IGT tests (2) ###

  * igt@dmabuf@all@dma_fence_chain:
- Statuses : 18 pass(s)
- Exec time: [7.35, 29.18] s

  * igt@dmabuf@all@dma_fence_proxy:
- Statuses : 18 pass(s)
- Exec time: [0.03, 0.07] s

  

Known issues


  Here are the changes found in Patchwork_17099 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@execlists:
- fi-apl-guc: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927] / 
[fdo#112175])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-apl-guc/igt@i915_selftest@l...@execlists.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-apl-guc/igt@i915_selftest@l...@execlists.html
- fi-kbl-x1275:   [PASS][9] -> [INCOMPLETE][10] ([fdo#112259])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
- fi-cml-s:   [PASS][11] -> [INCOMPLETE][12] ([i915#283])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cml-s/igt@i915_selftest@l...@execlists.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-cml-s/igt@i915_selftest@l...@execlists.html
- fi-skl-6700k2:  [PASS][13] -> [INCOMPLETE][14] ([fdo#112175])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html
- fi-cml-u2:  [PASS][15] -> [INCOMPLETE][16] ([fdo#112175] / 
[i915#283])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cml-u2/igt@i915_selftest@l...@execlists.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-cml-u2/igt@i915_selftest@l...@execlists.html
- fi-kbl-guc: [PASS][17] -> [INCOMPLETE][18] ([CI#80] / 
[fdo#112175] / [fdo#112259])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-guc/igt@i915_selftest@l...@execlists.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-kbl-guc/igt@i915_selftest@l...@execlists.html
- fi-kbl-7500u:   [PASS][19] -> [INCOMPLETE][20] ([fdo#112175] / 
[fdo#112259])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-7500u/igt@i915_selftest@l...@execlists.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-kbl-7500u/igt@i915_selftest@l...@execlists.html
- fi-kbl-8809g:   [PASS][21] -> [INCOMPLETE][22] ([CI#80] / 
[fdo#112175] / [fdo#112259])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-8809g/igt@i915_selftest@l...@execlists.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-kbl-8809g/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@requests:
- fi-icl-guc: [PASS][23] -> [INCOMPLETE][24] ([fdo#109644] / 
[fdo#110464])
   [23]: 

Re: [Intel-gfx] [PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma

2020-03-26 Thread Nathan Chancellor
On Mon, Mar 16, 2020 at 02:41:23PM -0700, Nick Desaulniers wrote:
> On Fri, Feb 14, 2020 at 7:36 AM Michel Dänzer  wrote:
> >
> > On 2020-02-14 12:49 p.m., Jani Nikula wrote:
> > > On Fri, 14 Feb 2020, Chris Wilson  wrote:
> > >> Quoting Jani Nikula (2020-02-14 06:36:15)
> > >>> On Thu, 13 Feb 2020, Nathan Chancellor  wrote:
> >  A recent commit in clang added -Wtautological-compare to -Wall, which 
> >  is
> >  enabled for i915 after -Wtautological-compare is disabled for the rest
> >  of the kernel so we see the following warning on x86_64:
> > 
> >   ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1433:22: warning:
> >   result of comparison of constant 576460752303423487 with expression of
> >   type 'unsigned int' is always false
> >   [-Wtautological-constant-out-of-range-compare]
> >   if (unlikely(remain > N_RELOC(ULONG_MAX)))
> >  ^
> >   ../include/linux/compiler.h:78:42: note: expanded from macro 
> >  'unlikely'
> >   # define unlikely(x)__builtin_expect(!!(x), 0)
> >  ^
> >   1 warning generated.
> > 
> >  It is not wrong in the case where ULONG_MAX > UINT_MAX but it does not
> >  account for the case where this file is built for 32-bit x86, where
> >  ULONG_MAX == UINT_MAX and this check is still relevant.
> > 
> >  Cast remain to unsigned long, which keeps the generated code the same
> >  (verified with clang-11 on x86_64 and GCC 9.2.0 on x86 and x86_64) and
> >  the warning is silenced so we can catch more potential issues in the
> >  future.
> > 
> >  Link: https://github.com/ClangBuiltLinux/linux/issues/778
> >  Suggested-by: Michel Dänzer 
> >  Signed-off-by: Nathan Chancellor 
> > >>>
> > >>> Works for me as a workaround,
> > >>
> > >> But the whole point was that the compiler could see that it was
> > >> impossible and not emit the code. Doesn't this break that?
> > >
> > > It seems that goal and the warning are fundamentally incompatible.
> >
> > Not really:
> >
> > if (sizeof(remain) >= sizeof(unsigned long) &&
> > unlikely(remain > N_RELOC(ULONG_MAX)))
> >  return -EINVAL;
> >
> > In contrast to the cast, this doesn't generate any machine code on 64-bit:
> >
> > https://godbolt.org/z/GmUE4S
> >
> > but still generates the same code on 32-bit:
> >
> > https://godbolt.org/z/hAoz8L
> 
> Exactly.
> 
> This check is only a tautology when `sizeof(long) == sizeof(int)` (ie.
> ILP32 platforms, like 32b x86), notice how BOTH GCC AND Clang generate
> exactly the same code: https://godbolt.org/z/6ShrDM
> 
> Both compilers eliminate the check when `-m32` is not set, and
> generate the exact same check otherwise.  How about:
> ```
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index d3f4f28e9468..25b9d3f3ad57 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1415,8 +1415,10 @@ static int eb_relocate_vma(struct
> i915_execbuffer *eb, struct eb_vma *ev)
> 
> urelocs = u64_to_user_ptr(entry->relocs_ptr);
> remain = entry->relocation_count;
> +#ifndef CONFIG_64BIT
> if (unlikely(remain > N_RELOC(ULONG_MAX)))
> return -EINVAL;
> +#endif
> 
> /*
>  * We must check that the entire relocation array is safe
> ```
> 
> We now have 4 proposed solutions:
> 1. 
> https://lore.kernel.org/lkml/20191123195321.41305-1-natechancel...@gmail.com/
> 2. 
> https://lore.kernel.org/lkml/20200211050808.29463-1-natechancel...@gmail.com/
> 3. 
> https://lore.kernel.org/lkml/20200214054706.33870-1-natechancel...@gmail.com/
> 4. my diff above
> Let's please come to a resolution on this.

This is the only warning on an x86_64 defconfig build. Apologies if we
are being too persistent or nagging but we need guidance from the i915
maintainers on which solution they would prefer so it can be picked up.
I understand you all are busy and I appreciate the work you all do but
I do not want this to fall between the cracks because it is annoying to
constantly see this warning.

Cheers,
Nathan
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx


[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf

2020-03-26 Thread Patchwork
== Series Details ==

Series: series starting with [01/12] drm/i915/selftests: Add request throughput 
measurement to perf
URL   : https://patchwork.freedesktop.org/series/75124/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1d8f9dafbff4 drm/i915/selftests: Add request throughput measurement to perf
-:96: WARNING:LINE_SPACING: Missing a blank line after declarations
#96: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1525:
+   struct perf_series *ps = arg;
+   IGT_TIMEOUT(end_time);

-:130: WARNING:LINE_SPACING: Missing a blank line after declarations
#130: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1559:
+   struct i915_request *prev = NULL;
+   IGT_TIMEOUT(end_time);

-:165: WARNING:LINE_SPACING: Missing a blank line after declarations
#165: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1594:
+   struct perf_series *ps = arg;
+   IGT_TIMEOUT(end_time);

-:188: WARNING:LINE_SPACING: Missing a blank line after declarations
#188: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1617:
+   struct drm_i915_private *i915 = arg;
+   static int (* const func[])(void *arg) = {

-:196: WARNING:LINE_SPACING: Missing a blank line after declarations
#196: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1625:
+   struct intel_engine_cs *engine;
+   int (* const *fn)(void *arg);

-:325: WARNING:LINE_SPACING: Missing a blank line after declarations
#325: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1754:
+   struct intel_context *ce;
+   IGT_TIMEOUT(end_time);

-:393: WARNING:LINE_SPACING: Missing a blank line after declarations
#393: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1822:
+   struct intel_context *ce;
+   IGT_TIMEOUT(end_time);

-:462: WARNING:LINE_SPACING: Missing a blank line after declarations
#462: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1891:
+   struct intel_context *ce;
+   IGT_TIMEOUT(end_time);

-:518: WARNING:LINE_SPACING: Missing a blank line after declarations
#518: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1947:
+   struct drm_i915_private *i915 = arg;
+   static int (* const func[])(void *arg) = {

-:526: WARNING:LINE_SPACING: Missing a blank line after declarations
#526: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1955:
+   struct intel_engine_cs *engine;
+   int (* const *fn)(void *arg);

-:571: WARNING:YIELD: Using yield() is generally wrong. See yield() kernel-doc 
(sched/core.c)
#571: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:2000:
+   yield(); /* start all threads before we kthread_stop() */

total: 0 errors, 11 warnings, 0 checks, 611 lines checked
b7ab7a745aca drm/i915: Wrap i915_active in a simple kreffed struct
20bb84d17d20 drm/i915/perf: Schedule oa_config after modifying the contexts
c63b2aff058b dma-buf: Prettify typecasts for dma-fence-chain
e25810547705 dma-buf: Report signaled links inside dma-fence-chain
cb7a78a6b34e dma-buf: Exercise dma-fence-chain under selftests
-:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#33: 
new file mode 100644

-:61: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#61: FILE: drivers/dma-buf/st-dma-fence-chain.c:24:
+   spinlock_t lock;

-:235: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to 
using 'find_seqno', this function's name, in a string
#235: FILE: drivers/dma-buf/st-dma-fence-chain.c:198:
+   pr_err("Reported %d for find_seqno(0)!\n", err);

-:244: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to 
using 'find_seqno', this function's name, in a string
#244: FILE: drivers/dma-buf/st-dma-fence-chain.c:207:
+   pr_err("Reported %d for find_seqno(%d:%d)!\n",

-:249: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to 
using 'find_seqno', this function's name, in a string
#249: FILE: drivers/dma-buf/st-dma-fence-chain.c:212:
+   pr_err("Incorrect fence reported by 
find_seqno(%d:%d)\n",

-:272: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to 
using 'find_seqno', this function's name, in a string
#272: FILE: drivers/dma-buf/st-dma-fence-chain.c:235:
+   pr_err("Error not reported for future fence: 
find_seqno(%d:%d)!\n",

-:286: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to 
using 'find_seqno', this function's name, in a string
#286: FILE: drivers/dma-buf/st-dma-fence-chain.c:249:
+   pr_err("Incorrect fence reported by 
find_seqno(%d:%d)\n",

-:737: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to 
using 'dma_fence_chain', this function's name, in a string
#737: FILE: drivers/dma-buf/st-dma-fence-chain.c:700:
+   pr_info("sizeof(dma_fence_chain)=%zu\n",

total: 0 errors, 7 warnings, 1 checks, 725 lines checked
864706ced80d dma-buf: Proxy fence, an unsignaled fence placeholder

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning (rev2)

2020-03-26 Thread Patchwork
== Series Details ==

Series: drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning (rev2)
URL   : https://patchwork.freedesktop.org/series/75078/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17098


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/index.html

Known issues


  Here are the changes found in Patchwork_17098 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#108569])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html

  
 Possible fixes 

  * igt@i915_selftest@live@execlists:
- fi-icl-dsi: [DMESG-FAIL][3] ([fdo#108569]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/fi-icl-dsi/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- fi-icl-u2:  [INCOMPLETE][5] ([fdo#108569]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569


Participating hosts (49 -> 37)
--

  Missing(12): fi-ilk-m540 fi-bdw-samus fi-bdw-5557u fi-bsw-n3050 
fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u 
fi-byt-clapper fi-skl-6600u fi-snb-2600 


Build changes
-

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8195 -> Patchwork_17098

  CI-20190529: 20190529
  CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17098: 39b95b621dfcda82ef1437a6dfc7bd30df89e73d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

39b95b621dfc drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/index.html
___
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[Intel-gfx] [PATCH] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context

2020-03-26 Thread Chris Wilson
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).

  process_csb: vecs0: cs-irq head=0, tail=1
  process_csb: vecs0: csb[1]: status=0x0882:0x0020
  trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
  process_csb: vecs0: cs-irq head=1, tail=2
  process_csb: vecs0: csb[2]: status=0x0814:0x0040
  trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
  process_csb: vecs0: cs-irq head=2, tail=5
  process_csb: vecs0: csb[3]: status=0x0812:0x0020
  trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
  trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
  process_csb: vecs0: csb[4]: status=0x0814:0x0060
  trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
  process_csb: vecs0: csb[5]: status=0x0818:0x0020
  trace_ports: vecs0: completed { 8c0:32, 0:0 }
  process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, 
ctl:, mode:0200}
  process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, 
hwsp:30},
  process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
  process_csb: process_csb:2449 GEM_BUG_ON("context completed before request")

Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 71 ++---
 1 file changed, 35 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..9e24ff7451a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request 
**ports, int count)
memset_p((void **)ports, NULL, count);
 }
 
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
 {
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 execlists->queue_priority_hint);
record_preemption(execlists);
 
-   /*
-* Don't let the RING_HEAD advance past the breadcrumb
-* as we unwind (and until we resubmit) so that we do
-* not accidentally tell it to go backwards.
-*/
-   ring_set_paused(engine, 1);
-
/*
 * Note that we have not stopped the GPU at this point,
 * so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 last->sched.attr.priority,
 execlists->queue_priority_hint);
 
-   ring_set_paused(engine, 1);
defer_active(engine);
 
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * of timeslices, our queue might be.
 */
start_timeslice(engine);
-   return;
+   return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
}
 
if (last && !can_merge_rq(last, rq)) {
+   /* leave this for another sibling */
spin_unlock(>base.active.lock);
start_timeslice(engine);
-   return; /* leave this for another sibling */
+   return false;
}
 
ENGINE_TRACE(engine,
@@ -2193,32 +2186,30 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * interrupt for secondary ports).
 */
execlists->queue_priority_hint = queue_prio(execlists);
+   if (!submit)
+   return false;
 
-   if (submit) {
-   *port = execlists_schedule_in(last, port - execlists->pending);
-   execlists->switch_priority_hint =
-

[Intel-gfx] [PATCH] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context

2020-03-26 Thread Chris Wilson
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).

Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 71 ++---
 1 file changed, 35 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..9e24ff7451a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request 
**ports, int count)
memset_p((void **)ports, NULL, count);
 }
 
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
 {
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 execlists->queue_priority_hint);
record_preemption(execlists);
 
-   /*
-* Don't let the RING_HEAD advance past the breadcrumb
-* as we unwind (and until we resubmit) so that we do
-* not accidentally tell it to go backwards.
-*/
-   ring_set_paused(engine, 1);
-
/*
 * Note that we have not stopped the GPU at this point,
 * so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 last->sched.attr.priority,
 execlists->queue_priority_hint);
 
-   ring_set_paused(engine, 1);
defer_active(engine);
 
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * of timeslices, our queue might be.
 */
start_timeslice(engine);
-   return;
+   return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
}
 
if (last && !can_merge_rq(last, rq)) {
+   /* leave this for another sibling */
spin_unlock(>base.active.lock);
start_timeslice(engine);
-   return; /* leave this for another sibling */
+   return false;
}
 
ENGINE_TRACE(engine,
@@ -2193,32 +2186,30 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * interrupt for secondary ports).
 */
execlists->queue_priority_hint = queue_prio(execlists);
+   if (!submit)
+   return false;
 
-   if (submit) {
-   *port = execlists_schedule_in(last, port - execlists->pending);
-   execlists->switch_priority_hint =
-   switch_prio(engine, *execlists->pending);
+   *port = execlists_schedule_in(last, port - execlists->pending);
+   execlists->switch_priority_hint =
+   switch_prio(engine, *execlists->pending);
 
-   /*
-* Skip if we ended up with exactly the same set of requests,
-* e.g. trying to timeslice a pair of ordered contexts
-*/
-   if (!memcmp(active, execlists->pending,
-   (port - execlists->pending + 1) * sizeof(*port))) {
-   do
-   execlists_schedule_out(fetch_and_zero(port));
-   while (port-- != execlists->pending);
-
-   goto skip_submit;
-   }
-   clear_ports(port + 1, last_port - port);
+   /*
+* Skip if we ended up with exactly the same set of requests,
+* e.g. trying to timeslice a pair of ordered contexts
+*/
+   if (!memcmp(active, execlists->pending,
+   (port - execlists->pending + 1) * sizeof(*port))) {
+   do
+   

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning (rev2)

2020-03-26 Thread Patchwork
== Series Details ==

Series: drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning (rev2)
URL   : https://patchwork.freedesktop.org/series/75078/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
39b95b621dfc drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning
-:41: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 17 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for i915 lpsp support for lpsp igt (rev5)

2020-03-26 Thread Patchwork
== Series Details ==

Series: i915 lpsp support for lpsp igt (rev5)
URL   : https://patchwork.freedesktop.org/series/74648/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17097


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_17097:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@debugfs_test@read_all_entries:
- {fi-ehl-1}: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-ehl-1/igt@debugfs_test@read_all_entries.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-ehl-1/igt@debugfs_test@read_all_entries.html

  * igt@runner@aborted:
- {fi-ehl-1}: NOTRUN -> [FAIL][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-ehl-1/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_17097 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-8809g:   [PASS][4] -> [SKIP][5] ([fdo#109271])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-8809g/igt@i915_pm_...@module-reload.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-kbl-8809g/igt@i915_pm_...@module-reload.html

  
 Possible fixes 

  * igt@i915_selftest@live@execlists:
- fi-icl-dsi: [DMESG-FAIL][6] ([fdo#108569]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-icl-dsi/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- fi-icl-u2:  [INCOMPLETE][8] ([fdo#108569]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271


Participating hosts (49 -> 38)
--

  Missing(11): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-kbl-7500u fi-ctg-p8600 fi-gdg-551 fi-skl-lmem fi-kbl-7560u fi-byt-clapper 
fi-bdw-samus 


Build changes
-

  * CI: CI-20190529 -> None
  * IGT: IGT_5539 -> IGTPW_4358
  * Linux: CI_DRM_8195 -> Patchwork_17097

  CI-20190529: 20190529
  CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4358: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4358/index.html
  IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17097: df3af2bc5b98bdca45f071d60a5931f9d2af49eb @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

df3af2bc5b98 drm/i915: Add connector dbgfs for all connectors
79871fceb2e0 drm/i915: Add i915_lpsp_info debugfs
ff6b22d263e3 drm/i915: Power well id for ICL PG3

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/index.html
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[Intel-gfx] [PATCH v20 06/10] drm/i915: Add proper SAGV support for TGL+

2020-03-26 Thread Stanislav Lisovskiy
Let's refactor the whole SAGV logic, moving
the main calculations from intel_can_enable_sagv
to intel_compute_sagv_mask, which also handles
this in a unified way calling gen specific
functions to evaluate if SAGV is allowed for
each crtc. If crtc sagv mask have been changed
we serialize access and modify global state.

intel_can_enable_sagv now uses bw_state which
stores all information related to SAGV and
is now a trivial helper.

v2:
- Rework watermark calculation algorithm to
  attempt to calculate Level 0 watermark
  with added sagv block time latency and
  check if it fits in DBuf in order to
  determine if SAGV can be enabled already
  at this stage, just as BSpec 49325 states.
  if that fails rollback to usual Level 0
  latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)

v3: Rebased the patch

v4: - Added back interlaced check for Gen12 and
  added separate function for TGL SAGV check
  (thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
  to a separate function from skl_compute_wm

v5: - Added SAGV global state to dev_priv, because
  we need to track all pipes, not only those
  in atomic state. Each pipe has now correspondent
  bit mask reflecting, whether it can tolerate
  SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
  usage check.

v6: - Fixed rebase conflicts

v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
  calls when copying level 0 water marks for enabled SAGV, to
  fix this now simply using that field right away, without copying,
  for that introduced a new wm_level accessor which decides which
  wm_level to return based on SAGV state.

v8: - Protect crtc_sagv_mask same way as we do for other global state
  changes: i.e check if changes are needed, then grab all crtc locks
  to serialize the changes(Ville Syrjälä)
- Add crtc_sagv_mask caching in order to avoid needless recalculations
  (Matthew Roper)
- Put back Gen12 SAGV switch in order to get it enabled in separate
  patch(Matthew Roper)
- Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
- Check if there are no active pipes in intel_can_enable_sagv
  instead of platform specific functions(Matthew Roper), same
  for intel_has_sagv check.

v9  - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
- crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
- Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
- Extracted skl_plane_wm_level function and passing latency to
  separate patches(Ville Syrjälä)
- Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
  (Ville Syrjälä)
- Now using simple assignment for sagv_wm0 as it contains only
  pod types and no pointers(Ville Syrjälä)
- Fixed intel_can_enable_sagv not to do double duty, now it only
  check SAGV bits by ANDing those between local and global state.
  The SAGV masks are now computed after watermarks are available,
  in order to be able to figure out if ddb ranges are fitting nicely.
  (Ville Syrjälä)
- Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
  when using skl_plane_wm_level accessor, as we had previously for
  Gen11+ color plane and regular wm levels, so probably both
  has to be recalculated with additional SAGV block time for Level 0.

v10: - Starting to use new global state for storing pipe_sagv_mask

v11: - Fixed rebase conflict with recent drm-tip
 - Check if we really need to recalculate SAGV mask, otherwise
   bail out without making any changes.
 - Use cached SAGV result, instead of recalculating it everytime,
   if bw_state hasn't changed.

v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
   if we don't recalculated watermarks, bw_state is not recalculated,
   thus leading to SAGV state not recalculated by the commit state,
   which is still calling intel_can_enable_sagv function. Fix that
   by just analyzing the current global bw_state object - because
   we simply have no other objects related to that.

v13: - Rebased, fixed warnings regarding long lines
 - Changed function call sites from intel_atomic_bw* to
   intel_wb_* as was suggested.(Jani Nikula)
 - Taken ddb_state_changed and bw_state_changed into use.

v14: - total_affected_planes is no longer needed to check for ddb changes,
   just as active_pipe_changes.

v15: - Fixed stupid mistake with uninitialized crtc in
   skl_compute_sagv_mask.

v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
   flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
 - Added return value to intel_compute_sagv_mask which call
   intel_atomic_serialize_global_state in order to properly
   propagate EDEADLCK 

[Intel-gfx] [PATCH v20 09/10] drm/i915: Restrict qgv points which don't have enough bandwidth.

2020-03-26 Thread Stanislav Lisovskiy
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.

Currently we are just comparing against all of
those and take minimum(worst case).

v2: Fixed wrong PCode reply mask, removed hardcoded
values.

v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.

v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
  masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
  as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
  can't be enabled(BSpec)

v5:
- Add new mailbox reply codes, which seems to happen during boot
  time for TGL and indicate that QGV setting is not yet available.

v6:
- Increase number of supported QGV points to be in sync with BSpec.

v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)

v8: - Don't report an error if we can't restrict qgv points, as SAGV
  can be disabled by BIOS, which is completely legal. So don't
  make CI panic. Instead if we detect that there is only 1 QGV
  point accessible just analyze if we can fit the required bandwidth
  requirements, but no need in restricting.

v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
  simultaneously.

v10: - Fix CDCLK corruption, because of global state getting serialized
   without modeset, which caused copying of non-calculated cdclk
   to be copied to dev_priv(thanks to Ville for the hint).

v11: - Remove unneeded headers and spaces(Matthew Roper)
 - Remove unneeded intel_qgv_info qi struct from bw check and zero
   out the needed one(Matthew Roper)
 - Changed QGV error message to have more clear meaning(Matthew Roper)
 - Use state->modeset_set instead of any_ms(Matthew Roper)
 - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
 - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
 - Moved unrelated changes to other patch(using latency as parameter
   for plane wm calculation, moved to SAGV refactoring patch)

v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
 - Remove unnecessary mask being zero check when unmasking
   qgv points as this is completely legal(Matt Roper)
 - Check if we are setting the same mask as already being set
   in hardware to prevent error from PCode.
 - Fix error message when restricting/unrestricting qgv points
   to "mask/unmask" which sounds more accurate(Matt Roper)
 - Move sagv status setting to icl_get_bw_info from atomic check
   as this should be calculated only once.(Matt Roper)
 - Edited comments for the case when we can't enable SAGV and
   use only 1 QGV point with highest bandwidth to be more
   understandable.(Matt Roper)

v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
 - Changed comment for zero new_mask in qgv points masking function
   to better reflect reality(Ville Syrjälä)
 - Simplified bit mask operation in qgv points masking function
   (Ville Syrjälä)
 - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
   however this still can't be under modeset condition(Ville Syrjälä)
 - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
   (Ville Syrjälä)
 - Extracted PCode changes to separate patch.(Ville Syrjälä)
 - Now treat num_planes 0 same as 1 to avoid confusion and
   returning max_bw as 0, which would prevent choosing QGV
   point having max bandwidth in case if SAGV is not allowed,
   as per BSpec(Ville Syrjälä)
 - Do the actual qgv_points_mask swap in the same place as
   all other global state parts like cdclk are swapped.
   In the next patch, this all will be moved to bw state as
   global state, once new global state patch series from Ville
   lands

v14: - Now using global state to serialize access to qgv points
 - Added global state locking back, otherwise we seem to read
   bw state in a wrong way.

v15: - Added TODO comment for near atomic global state locking in
   bw code.

v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
   with Jani Nikula.
 - Take bw_state_changed flag into use.

v17: - Moved qgv point related manipulations next to SAGV code, as
   those are semantically related(Ville Syrjälä)
 - Renamed those into intel_sagv_(pre)|(post)_plane_update
   (Ville Syrjälä)

v18: - Move sagv related calls from commit tail into
   intel_sagv_(pre)|(post)_plane_update(Ville 

[Intel-gfx] [PATCH v20 10/10] drm/i915: Enable SAGV support for Gen12

2020-03-26 Thread Stanislav Lisovskiy
Flip the switch and enable SAGV support
for Gen12 also.

Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/i915/intel_pm.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e4d64b626f8..4c278493559a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct 
drm_i915_private *dev_priv)
 bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-   /* HACK! */
-   if (IS_GEN(dev_priv, 12))
-   return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v20 08/10] drm/i915: Rename bw_state to new_bw_state

2020-03-26 Thread Stanislav Lisovskiy
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.

Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index a8b2038db4d2..d16771dd2b10 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -418,7 +418,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
-   struct intel_bw_state *bw_state = NULL;
+   struct intel_bw_state *new_bw_state = NULL;
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
@@ -447,29 +447,29 @@ int intel_bw_atomic_check(struct intel_atomic_state 
*state)
old_active_planes == new_active_planes)
continue;
 
-   bw_state  = intel_atomic_get_bw_state(state);
-   if (IS_ERR(bw_state))
-   return PTR_ERR(bw_state);
+   new_bw_state  = intel_atomic_get_bw_state(state);
+   if (IS_ERR(new_bw_state))
+   return PTR_ERR(new_bw_state);
 
-   bw_state->data_rate[crtc->pipe] = new_data_rate;
-   bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+   new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+   new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
 
drm_dbg_kms(_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
-   bw_state->data_rate[crtc->pipe],
-   bw_state->num_active_planes[crtc->pipe]);
+   new_bw_state->data_rate[crtc->pipe],
+   new_bw_state->num_active_planes[crtc->pipe]);
}
 
-   if (!bw_state)
+   if (!new_bw_state)
return 0;
 
-   ret = intel_atomic_lock_global_state(_state->base);
+   ret = intel_atomic_lock_global_state(_bw_state->base);
if (ret)
return ret;
 
-   data_rate = intel_bw_data_rate(dev_priv, bw_state);
-   num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+   data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+   num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
 
max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
 
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v20 00/10] SAGV support for Gen12+

2020-03-26 Thread Stanislav Lisovskiy
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.

v17: Had to rebase the whole series.

v19: Added some new patches in between, rebased

v20: Added new patches and rebased the series

Stanislav Lisovskiy (10):
  drm/i915: Start passing latency as parameter
  drm/i915: Eliminate magic numbers "0" and "1" from color plane
  drm/i915: Introduce skl_plane_wm_level accessor.
  drm/i915: Add intel_atomic_get_bw_*_state helpers
  drm/i915: Extract gen specific functions from intel_can_enable_sagv
  drm/i915: Add proper SAGV support for TGL+
  drm/i915: Added required new PCode commands
  drm/i915: Rename bw_state to new_bw_state
  drm/i915: Restrict qgv points which don't have enough bandwidth.
  drm/i915: Enable SAGV support for Gen12

 drivers/gpu/drm/i915/display/intel_bw.c   | 200 +--
 drivers/gpu/drm/i915/display/intel_bw.h   |  24 +
 drivers/gpu/drm/i915/display/intel_display.c  |  29 +-
 .../drm/i915/display/intel_display_types.h|  12 +
 drivers/gpu/drm/i915/i915_reg.h   |   4 +
 drivers/gpu/drm/i915/intel_pm.c   | 555 +++---
 drivers/gpu/drm/i915/intel_pm.h   |   6 +-
 drivers/gpu/drm/i915/intel_sideband.c |   2 +
 8 files changed, 690 insertions(+), 142 deletions(-)

-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v20 02/10] drm/i915: Eliminate magic numbers "0" and "1" from color plane

2020-03-26 Thread Stanislav Lisovskiy
According to many computer science sources - magic values
in code _are_ _bad_. For many reasons: the reason is that "0"
or "1" or whatever magic values confuses and doesn't give any
info why this parameter is this value and what it's meaning
is.
I renamed "0" to COLOR_PLANE_Y and "1" to COLOR_PLANE_UV,
because we in fact already use this naming in many other places
and function names, when dealing with color planes.

Signed-off-by: Stanislav Lisovskiy 
---
 .../drm/i915/display/intel_display_types.h|  5 +++
 drivers/gpu/drm/i915/intel_pm.c   | 40 +--
 2 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 176ab5f1e867..523e0444b373 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -682,6 +682,11 @@ struct skl_plane_wm {
bool is_planar;
 };
 
+enum color_plane {
+   COLOR_PLANE_Y,
+   COLOR_PLANE_UV
+};
+
 struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b632b6bb9c3e..9e9a4612d842 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4013,7 +4013,7 @@ static int skl_compute_wm_params(const struct 
intel_crtc_state *crtc_state,
 int width, const struct drm_format_info 
*format,
 u64 modifier, unsigned int rotation,
 u32 plane_pixel_rate, struct skl_wm_params *wp,
-int color_plane);
+enum color_plane);
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 int level,
 unsigned int latency,
@@ -4035,7 +4035,7 @@ skl_cursor_allocation(const struct intel_crtc_state 
*crtc_state,
drm_format_info(DRM_FORMAT_ARGB),
DRM_FORMAT_MOD_LINEAR,
DRM_MODE_ROTATE_0,
-   crtc_state->pixel_rate, , 0);
+   crtc_state->pixel_rate, , COLOR_PLANE_Y);
drm_WARN_ON(_priv->drm, ret);
 
for (level = 0; level <= max_level; level++) {
@@ -4431,7 +4431,7 @@ static u8 skl_compute_dbuf_slices(const struct 
intel_crtc_state *crtc_state,
 static u64
 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 const struct intel_plane_state *plane_state,
-int color_plane)
+enum color_plane color_plane)
 {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -4446,7 +4446,7 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *crtc_state,
if (plane->id == PLANE_CURSOR)
return 0;
 
-   if (color_plane == 1 &&
+   if (color_plane == COLOR_PLANE_UV &&
!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 0;
 
@@ -4459,7 +4459,7 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *crtc_state,
height = drm_rect_height(_state->uapi.src) >> 16;
 
/* UV plane does 1/2 pixel sub-sampling */
-   if (color_plane == 1) {
+   if (color_plane == COLOR_PLANE_UV) {
width /= 2;
height /= 2;
}
@@ -4489,12 +4489,12 @@ skl_get_total_relative_data_rate(struct 
intel_crtc_state *crtc_state,
u64 rate;
 
/* packed/y */
-   rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
+   rate = skl_plane_relative_data_rate(crtc_state, plane_state, 
COLOR_PLANE_Y);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
 
/* uv-plane */
-   rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
+   rate = skl_plane_relative_data_rate(crtc_state, plane_state, 
COLOR_PLANE_UV);
uv_plane_data_rate[plane_id] = rate;
total_data_rate += rate;
}
@@ -4516,7 +4516,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state 
*crtc_state,
u64 rate;
 
if (!plane_state->planar_linked_plane) {
-   rate = skl_plane_relative_data_rate(crtc_state, 
plane_state, 0);
+   rate = skl_plane_relative_data_rate(crtc_state, 
plane_state, COLOR_PLANE_Y);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
} else {
@@ -4533,12 +4533,12 @@ icl_get_total_relative_data_rate(struct 
intel_crtc_state *crtc_state,
 

[Intel-gfx] [PATCH v20 06/10] drm/i915: Add proper SAGV support for TGL+

2020-03-26 Thread Stanislav Lisovskiy
Let's refactor the whole SAGV logic, moving
the main calculations from intel_can_enable_sagv
to intel_compute_sagv_mask, which also handles
this in a unified way calling gen specific
functions to evaluate if SAGV is allowed for
each crtc. If crtc sagv mask have been changed
we serialize access and modify global state.

intel_can_enable_sagv now uses bw_state which
stores all information related to SAGV and
is now a trivial helper.

v2:
- Rework watermark calculation algorithm to
  attempt to calculate Level 0 watermark
  with added sagv block time latency and
  check if it fits in DBuf in order to
  determine if SAGV can be enabled already
  at this stage, just as BSpec 49325 states.
  if that fails rollback to usual Level 0
  latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)

v3: Rebased the patch

v4: - Added back interlaced check for Gen12 and
  added separate function for TGL SAGV check
  (thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
  to a separate function from skl_compute_wm

v5: - Added SAGV global state to dev_priv, because
  we need to track all pipes, not only those
  in atomic state. Each pipe has now correspondent
  bit mask reflecting, whether it can tolerate
  SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
  usage check.

v6: - Fixed rebase conflicts

v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
  calls when copying level 0 water marks for enabled SAGV, to
  fix this now simply using that field right away, without copying,
  for that introduced a new wm_level accessor which decides which
  wm_level to return based on SAGV state.

v8: - Protect crtc_sagv_mask same way as we do for other global state
  changes: i.e check if changes are needed, then grab all crtc locks
  to serialize the changes(Ville Syrjälä)
- Add crtc_sagv_mask caching in order to avoid needless recalculations
  (Matthew Roper)
- Put back Gen12 SAGV switch in order to get it enabled in separate
  patch(Matthew Roper)
- Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
- Check if there are no active pipes in intel_can_enable_sagv
  instead of platform specific functions(Matthew Roper), same
  for intel_has_sagv check.

v9  - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
- crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
- Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
- Extracted skl_plane_wm_level function and passing latency to
  separate patches(Ville Syrjälä)
- Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
  (Ville Syrjälä)
- Now using simple assignment for sagv_wm0 as it contains only
  pod types and no pointers(Ville Syrjälä)
- Fixed intel_can_enable_sagv not to do double duty, now it only
  check SAGV bits by ANDing those between local and global state.
  The SAGV masks are now computed after watermarks are available,
  in order to be able to figure out if ddb ranges are fitting nicely.
  (Ville Syrjälä)
- Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
  when using skl_plane_wm_level accessor, as we had previously for
  Gen11+ color plane and regular wm levels, so probably both
  has to be recalculated with additional SAGV block time for Level 0.

v10: - Starting to use new global state for storing pipe_sagv_mask

v11: - Fixed rebase conflict with recent drm-tip
 - Check if we really need to recalculate SAGV mask, otherwise
   bail out without making any changes.
 - Use cached SAGV result, instead of recalculating it everytime,
   if bw_state hasn't changed.

v12: - Removed WARN from intel_can_enable_sagv, in some of the commits
   if we don't recalculated watermarks, bw_state is not recalculated,
   thus leading to SAGV state not recalculated by the commit state,
   which is still calling intel_can_enable_sagv function. Fix that
   by just analyzing the current global bw_state object - because
   we simply have no other objects related to that.

v13: - Rebased, fixed warnings regarding long lines
 - Changed function call sites from intel_atomic_bw* to
   intel_wb_* as was suggested.(Jani Nikula)
 - Taken ddb_state_changed and bw_state_changed into use.

v14: - total_affected_planes is no longer needed to check for ddb changes,
   just as active_pipe_changes.

v15: - Fixed stupid mistake with uninitialized crtc in
   skl_compute_sagv_mask.

v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted
   flag to indicate SAGV readiness for the pipe(Ville Syrjälä)
 - Added return value to intel_compute_sagv_mask which call
   intel_atomic_serialize_global_state in order to properly
   propagate EDEADLCK 

[Intel-gfx] [PATCH v20 07/10] drm/i915: Added required new PCode commands

2020-03-26 Thread Stanislav Lisovskiy
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.

v2: - Extracted those changes into separate patch
  (Ville Syrjälä)

Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/i915/i915_reg.h   | 4 
 drivers/gpu/drm/i915/intel_sideband.c | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c53fe918be6..1a61db746c7e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8994,6 +8994,7 @@ enum {
 #define GEN7_PCODE_ILLEGAL_DATA0x3
 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
 #define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED   0x11
 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
 #define   GEN6_PCODE_WRITE_RC6VIDS 0x4
 #define   GEN6_PCODE_READ_RC6VIDS  0x5
@@ -9015,6 +9016,7 @@ enum {
 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO   0xd
 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO  (0x0 << 8)
 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)(((point) << 
16) | (0x1 << 8))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG  0xe
 #define   GEN6_PCODE_READ_D_COMP   0x10
 #define   GEN6_PCODE_WRITE_D_COMP  0x11
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ  0x17
@@ -9027,6 +9029,8 @@ enum {
 #define GEN9_SAGV_IS_DISABLED  0x1
 #define GEN9_SAGV_ENABLE   0x3
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
+#define GEN11_PCODE_POINTS_RESTRICTED  0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
 #define GEN6_PCODE_DATA_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT   8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
b/drivers/gpu/drm/i915/intel_sideband.c
index 1447e7516cb7..1e7dd6b6f103 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -370,6 +370,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+   case GEN11_PCODE_REJECTED:
+   return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v20 01/10] drm/i915: Start passing latency as parameter

2020-03-26 Thread Stanislav Lisovskiy
We need to start passing memory latency as a
parameter when calculating plane wm levels,
as latency can get changed in different
circumstances(for example with or without SAGV).
So we need to be more flexible on that matter.

v2: Changed latency type from u32 to unsigned int(Ville Syrjälä)

Reviewed-by: Ville Syrjälä 
Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/i915/intel_pm.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8375054ba27d..b632b6bb9c3e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct 
intel_crtc_state *crtc_state,
 int color_plane);
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 int level,
+unsigned int latency,
 const struct skl_wm_params *wp,
 const struct skl_wm_level *result_prev,
 struct skl_wm_level *result /* out */);
@@ -4038,7 +4039,9 @@ skl_cursor_allocation(const struct intel_crtc_state 
*crtc_state,
drm_WARN_ON(_priv->drm, ret);
 
for (level = 0; level <= max_level; level++) {
-   skl_compute_plane_wm(crtc_state, level, , , );
+   unsigned int latency = dev_priv->wm.skl_latency[level];
+
+   skl_compute_plane_wm(crtc_state, level, latency, , , );
if (wm.min_ddb_alloc == U16_MAX)
break;
 
@@ -4972,12 +4975,12 @@ static bool skl_wm_has_lines(struct drm_i915_private 
*dev_priv, int level)
 
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 int level,
+unsigned int latency,
 const struct skl_wm_params *wp,
 const struct skl_wm_level *result_prev,
 struct skl_wm_level *result /* out */)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-   u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5106,9 +5109,10 @@ skl_compute_wm_levels(const struct intel_crtc_state 
*crtc_state,
 
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = [level];
+   unsigned int latency = dev_priv->wm.skl_latency[level];
 
-   skl_compute_plane_wm(crtc_state, level, wm_params,
-result_prev, result);
+   skl_compute_plane_wm(crtc_state, level, latency,
+wm_params, result_prev, result);
 
result_prev = result;
}
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v20 03/10] drm/i915: Introduce skl_plane_wm_level accessor.

2020-03-26 Thread Stanislav Lisovskiy
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.

So this accessor will give additional flexibility
to do that.

Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.

v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
  (Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
  skl_plane_wm_level

v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
- Changed colorplane id type from boolean to int as index
  (Ville Syrjälä)
- Moved crtc_state param so that it is first now
  (Ville Syrjälä)
- Moved wm_level declaration to tigher scope in
  skl_write_plane_wm(Ville Syrjälä)

v4: - Started to use enum values for color plane
- Do sizeof for a type what we are memset'ing
- Zero out wm_uv as well(Ville Syrjälä)

Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/i915/intel_pm.c | 85 ++---
 1 file changed, 67 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9e9a4612d842..f8d62d1977ac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4547,6 +4547,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state 
*crtc_state,
return total_data_rate;
 }
 
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+  enum plane_id plane_id,
+  int level,
+  enum color_plane color_plane)
+{
+   const struct skl_plane_wm *wm =
+   _state->wm.skl.optimal.planes[plane_id];
+
+   return color_plane == COLOR_PLANE_Y ? >wm[level] : 
>uv_wm[level];
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 {
@@ -4606,22 +4618,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state 
*crtc_state)
 */
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
+
for_each_plane_id_on_crtc(crtc, plane_id) {
-   const struct skl_plane_wm *wm =
-   _state->wm.skl.optimal.planes[plane_id];
+   const struct skl_wm_level *wm_level;
+   const struct skl_wm_level *wm_uv_level;
+
+   wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, COLOR_PLANE_Y);
+   wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+level, COLOR_PLANE_UV);
 
if (plane_id == PLANE_CURSOR) {
-   if (wm->wm[level].min_ddb_alloc > 
total[PLANE_CURSOR]) {
+   if (wm_level->min_ddb_alloc > 
total[PLANE_CURSOR]) {
drm_WARN_ON(_priv->drm,
-   wm->wm[level].min_ddb_alloc 
!= U16_MAX);
+   wm_level->min_ddb_alloc != 
U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
 
-   blocks += wm->wm[level].min_ddb_alloc;
-   blocks += wm->uv_wm[level].min_ddb_alloc;
+   blocks += wm_level->min_ddb_alloc;
+   blocks += wm_uv_level->min_ddb_alloc;
}
 
if (blocks <= alloc_size) {
@@ -4644,11 +4662,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state 
*crtc_state)
 * proportional to its relative data rate.
 */
for_each_plane_id_on_crtc(crtc, plane_id) {
-   const struct skl_plane_wm *wm =
-   _state->wm.skl.optimal.planes[plane_id];
+   const struct skl_wm_level *wm_level;
+   const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
 
+   wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, COLOR_PLANE_Y);
+   wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+level, COLOR_PLANE_UV);
+
if (plane_id == PLANE_CURSOR)
continue;
 
@@ -4663,7 +4686,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
  DIV64_U64_ROUND_UP(alloc_size * rate,
 total_data_rate));
-   total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+   

[Intel-gfx] [PATCH v20 09/10] drm/i915: Restrict qgv points which don't have enough bandwidth.

2020-03-26 Thread Stanislav Lisovskiy
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.

Currently we are just comparing against all of
those and take minimum(worst case).

v2: Fixed wrong PCode reply mask, removed hardcoded
values.

v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.

v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
  masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
  as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
  can't be enabled(BSpec)

v5:
- Add new mailbox reply codes, which seems to happen during boot
  time for TGL and indicate that QGV setting is not yet available.

v6:
- Increase number of supported QGV points to be in sync with BSpec.

v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)

v8: - Don't report an error if we can't restrict qgv points, as SAGV
  can be disabled by BIOS, which is completely legal. So don't
  make CI panic. Instead if we detect that there is only 1 QGV
  point accessible just analyze if we can fit the required bandwidth
  requirements, but no need in restricting.

v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
  simultaneously.

v10: - Fix CDCLK corruption, because of global state getting serialized
   without modeset, which caused copying of non-calculated cdclk
   to be copied to dev_priv(thanks to Ville for the hint).

v11: - Remove unneeded headers and spaces(Matthew Roper)
 - Remove unneeded intel_qgv_info qi struct from bw check and zero
   out the needed one(Matthew Roper)
 - Changed QGV error message to have more clear meaning(Matthew Roper)
 - Use state->modeset_set instead of any_ms(Matthew Roper)
 - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
 - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
 - Moved unrelated changes to other patch(using latency as parameter
   for plane wm calculation, moved to SAGV refactoring patch)

v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
 - Remove unnecessary mask being zero check when unmasking
   qgv points as this is completely legal(Matt Roper)
 - Check if we are setting the same mask as already being set
   in hardware to prevent error from PCode.
 - Fix error message when restricting/unrestricting qgv points
   to "mask/unmask" which sounds more accurate(Matt Roper)
 - Move sagv status setting to icl_get_bw_info from atomic check
   as this should be calculated only once.(Matt Roper)
 - Edited comments for the case when we can't enable SAGV and
   use only 1 QGV point with highest bandwidth to be more
   understandable.(Matt Roper)

v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
 - Changed comment for zero new_mask in qgv points masking function
   to better reflect reality(Ville Syrjälä)
 - Simplified bit mask operation in qgv points masking function
   (Ville Syrjälä)
 - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
   however this still can't be under modeset condition(Ville Syrjälä)
 - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
   (Ville Syrjälä)
 - Extracted PCode changes to separate patch.(Ville Syrjälä)
 - Now treat num_planes 0 same as 1 to avoid confusion and
   returning max_bw as 0, which would prevent choosing QGV
   point having max bandwidth in case if SAGV is not allowed,
   as per BSpec(Ville Syrjälä)
 - Do the actual qgv_points_mask swap in the same place as
   all other global state parts like cdclk are swapped.
   In the next patch, this all will be moved to bw state as
   global state, once new global state patch series from Ville
   lands

v14: - Now using global state to serialize access to qgv points
 - Added global state locking back, otherwise we seem to read
   bw state in a wrong way.

v15: - Added TODO comment for near atomic global state locking in
   bw code.

v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
   with Jani Nikula.
 - Take bw_state_changed flag into use.

v17: - Moved qgv point related manipulations next to SAGV code, as
   those are semantically related(Ville Syrjälä)
 - Renamed those into intel_sagv_(pre)|(post)_plane_update
   (Ville Syrjälä)

v18: - Move sagv related calls from commit tail into
   intel_sagv_(pre)|(post)_plane_update(Ville 

[Intel-gfx] [PATCH v20 04/10] drm/i915: Add intel_atomic_get_bw_*_state helpers

2020-03-26 Thread Stanislav Lisovskiy
Add correspondent helpers to be able to get old/new bandwidth
global state object.

v2: - Fixed typo in function call
v3: - Changed new functions naming to use convention proposed
  by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
v4: - Change function naming back to intel_atomic* pattern,
  was decided to rename in a separate patch series.

Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 29 -
 drivers/gpu/drm/i915/display/intel_bw.h |  9 
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index 58b264bc318d..a8b2038db4d2 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -374,7 +374,34 @@ static unsigned int intel_bw_data_rate(struct 
drm_i915_private *dev_priv,
return data_rate;
 }
 
-static struct intel_bw_state *
+struct intel_bw_state *
+intel_atomic_get_bw_old_state(struct intel_atomic_state *state)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   struct intel_global_state *bw_state;
+
+   bw_state = intel_atomic_get_old_global_obj_state(state, 
_priv->bw_obj);
+   if (IS_ERR(bw_state))
+   return ERR_CAST(bw_state);
+
+   return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_atomic_get_bw_new_state(struct intel_atomic_state *state)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+   struct intel_global_state *bw_state;
+
+   bw_state = intel_atomic_get_new_global_obj_state(state, 
_priv->bw_obj);
+
+   if (IS_ERR(bw_state))
+   return ERR_CAST(bw_state);
+
+   return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
 intel_atomic_get_bw_state(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h 
b/drivers/gpu/drm/i915/display/intel_bw.h
index a8aa7624c5aa..fe6579c952f5 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,15 @@ struct intel_bw_state {
 
 #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
 
+struct intel_bw_state *
+intel_atomic_get_bw_old_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_bw_new_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_bw_state(struct intel_atomic_state *state);
+
 void intel_bw_init_hw(struct drm_i915_private *dev_priv);
 int intel_bw_init(struct drm_i915_private *dev_priv);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
-- 
2.24.1.485.gad05a3d8e5

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[Intel-gfx] [PATCH v20 05/10] drm/i915: Extract gen specific functions from intel_can_enable_sagv

2020-03-26 Thread Stanislav Lisovskiy
Addressing one of the comments, recommending to extract platform
specific code from intel_can_enable_sagv as a preparation, before
we are going to add support for tgl+.

Current code in intel_can_enable_sagv is valid only for skl,
so this patch adds also proper support for icl, subsequent
patches will add support for tgl+, combined with other required
changes.

Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/i915/intel_pm.c | 89 ++---
 1 file changed, 61 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f8d62d1977ac..64193b098175 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3757,41 +3757,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
 }
 
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool icl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
 {
-   struct drm_device *dev = state->base.dev;
+   struct drm_device *dev = crtc_state->uapi.crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
struct intel_plane *plane;
-   struct intel_crtc_state *crtc_state;
-   enum pipe pipe;
+   struct intel_plane_state *plane_state;
int level, latency;
 
-   if (!intel_has_sagv(dev_priv))
-   return false;
+   crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
-   /*
-* If there are no active CRTCs, no additional checks need be performed
-*/
-   if (hweight8(state->active_pipes) == 0)
-   return true;
-
-   /*
-* SKL+ workaround: bspec recommends we disable SAGV when we have
-* more then one pipe enabled
-*/
-   if (hweight8(state->active_pipes) > 1)
-   return false;
-
-   /* Since we're now guaranteed to only have one active CRTC... */
-   pipe = ffs(state->active_pipes) - 1;
-   crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
-   crtc_state = to_intel_crtc_state(crtc->base.state);
-
-   if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+   if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+   DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+ pipe_name(crtc->pipe));
return false;
+   }
 
-   for_each_intel_plane_on_crtc(dev, crtc, plane) {
+   intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, 
crtc_state) {
struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane->id];
 
@@ -3807,7 +3790,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
latency = dev_priv->wm.skl_latency[level];
 
if (skl_needs_memory_bw_wa(dev_priv) &&
-   plane->base.state->fb->modifier ==
+   plane_state->uapi.fb->modifier ==
I915_FORMAT_MOD_X_TILED)
latency += 15;
 
@@ -3816,8 +3799,58 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
 * incur memory latencies higher than sagv_block_time_us we
 * can't enable SAGV.
 */
-   if (latency < dev_priv->sagv_block_time_us)
+   if (latency < dev_priv->sagv_block_time_us) {
+   DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV 
for pipe %c\n",
+ latency, dev_priv->sagv_block_time_us, 
pipe_name(crtc->pipe));
return false;
+   }
+   }
+
+   return true;
+}
+
+static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
+{
+   struct intel_atomic_state *state = 
to_intel_atomic_state(crtc_state->uapi.state);
+
+   /*
+* It has been recommended that for Gen 9 we switch SAGV off when
+* multiple pipes are used.
+*/
+   if (hweight8(state->active_pipes) > 1)
+   return false;
+
+   /*
+* Besides active pipe limitation, rest of checks pretty much match ICL
+* so no need to duplicate code
+*/
+   return icl_can_enable_sagv_on_pipe(crtc_state);
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+   struct drm_device *dev = state->base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct intel_crtc *crtc;
+   struct intel_crtc_state *crtc_state;
+   int i;
+
+   if (!intel_has_sagv(dev_priv))
+   return false;
+
+   /*
+* If there are no active CRTCs, no additional checks need be performed
+*/
+   if (hweight8(state->active_pipes) == 0)
+   return true;
+
+   for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+   if (INTEL_GEN(dev_priv) <= 9) {
+   if 

[Intel-gfx] [PATCH v3 4/6] drm/i915/debugfs: move uC printers and update debugfs file names

2020-03-26 Thread Daniele Ceraolo Spurio
Move the printers to the respective files for clarity. The
guc_load_status debugfs has been squashed in the guc_info one, has
having separate ones wasn't very useful. The HuC debugfs has been
renamed huc_info to match.

v2: keep printing HUC_STATUS2 (Tony), avoid const->non-const
container_of (Jani)

Suggested-by: Michal Wajdeczko 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: John Harrison 
Cc: Matthew Brost 
Cc: Tony Ye 
Cc: Jani Nikula 
Reviewed-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c |  44 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c |  92 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h |   4 +
 drivers/gpu/drm/i915/gt/uc/intel_huc.c |  29 +
 drivers/gpu/drm/i915/gt/uc/intel_huc.h |   2 +
 drivers/gpu/drm/i915/i915_debugfs.c| 131 +++--
 7 files changed, 189 insertions(+), 115 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 827d75073879..861657897c0f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -723,3 +723,47 @@ int intel_guc_allocate_and_map_vma(struct intel_guc *guc, 
u32 size,
 
return 0;
 }
+
+/**
+ * intel_guc_load_status - dump information about GuC load status
+ * @guc: the GuC
+ * @p: the _printer
+ *
+ * Pretty printer for GuC load status.
+ */
+void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p)
+{
+   struct intel_gt *gt = guc_to_gt(guc);
+   struct intel_uncore *uncore = gt->uncore;
+   intel_wakeref_t wakeref;
+
+   if (!intel_guc_is_supported(guc)) {
+   drm_printf(p, "GuC not supported\n");
+   return;
+   }
+
+   if (!intel_guc_is_wanted(guc)) {
+   drm_printf(p, "GuC disabled\n");
+   return;
+   }
+
+   intel_uc_fw_dump(>fw, p);
+
+   with_intel_runtime_pm(uncore->rpm, wakeref) {
+   u32 status = intel_uncore_read(uncore, GUC_STATUS);
+   u32 i;
+
+   drm_printf(p, "\nGuC status 0x%08x:\n", status);
+   drm_printf(p, "\tBootrom status = 0x%x\n",
+  (status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
+   drm_printf(p, "\tuKernel status = 0x%x\n",
+  (status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
+   drm_printf(p, "\tMIA Core status = 0x%x\n",
+  (status & GS_MIA_MASK) >> GS_MIA_SHIFT);
+   drm_puts(p, "\nScratch registers:\n");
+   for (i = 0; i < 16; i++) {
+   drm_printf(p, "\t%2d: \t0x%x\n",
+  i, intel_uncore_read(uncore, 
SOFT_SCRATCH(i)));
+   }
+   }
+}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 4594ccbeaa34..a5d7a86be4cf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -190,4 +190,6 @@ static inline void intel_guc_disable_msg(struct intel_guc 
*guc, u32 mask)
 int intel_guc_reset_engine(struct intel_guc *guc,
   struct intel_engine_cs *engine);
 
+void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
+
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index caed0d57e704..8cdd6dc3df58 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -672,3 +672,95 @@ void intel_guc_log_handle_flush_event(struct intel_guc_log 
*log)
 {
queue_work(system_highpri_wq, >relay.flush_work);
 }
+
+static const char *
+stringify_guc_log_type(enum guc_log_buffer_type type)
+{
+   switch (type) {
+   case GUC_ISR_LOG_BUFFER:
+   return "ISR";
+   case GUC_DPC_LOG_BUFFER:
+   return "DPC";
+   case GUC_CRASH_DUMP_LOG_BUFFER:
+   return "CRASH";
+   default:
+   MISSING_CASE(type);
+   }
+
+   return "";
+}
+
+/**
+ * intel_guc_log_info - dump information about GuC log relay
+ * @guc: the GuC
+ * @p: the _printer
+ *
+ * Pretty printer for GuC log info
+ */
+void intel_guc_log_info(struct intel_guc_log *log, struct drm_printer *p)
+{
+   enum guc_log_buffer_type type;
+
+   if (!intel_guc_log_relay_created(log)) {
+   drm_puts(p, "GuC log relay not created\n");
+   return;
+   }
+
+   drm_puts(p, "GuC logging stats:\n");
+
+   drm_printf(p, "\tRelay full count: %u\n", log->relay.full_count);
+
+   for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
+   drm_printf(p, "\t%s:\tflush count %10u, overflow count %10u\n",
+  stringify_guc_log_type(type),
+  log->stats[type].flush,
+  

[Intel-gfx] [PATCH v3 6/6] drm/i915/uc: do not free err log on uc_fini

2020-03-26 Thread Daniele Ceraolo Spurio
We need to keep the GuC error logs around to debug the load failure,
so we can't clean them in the error unwind, which includes uc_fini().
Moving the cleanup to driver remove ensures that the logs stick around
long enough for us to dump them.

v2: reword commit msg (John)

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Reviewed-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/intel_gt.c| 3 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 +++--
 drivers/gpu/drm/i915/gt/uc/intel_uc.h | 1 +
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index d09f7596cb98..1c99cc72305a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -635,8 +635,7 @@ void intel_gt_driver_remove(struct intel_gt *gt)
 {
__intel_gt_disable(gt);
 
-   intel_uc_fini_hw(>uc);
-   intel_uc_fini(>uc);
+   intel_uc_driver_remove(>uc);
 
intel_engines_release(gt);
 }
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index a4cbe06e06bd..b11e564ef22e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -131,6 +131,13 @@ static void __uc_free_load_err_log(struct intel_uc *uc)
i915_gem_object_put(log);
 }
 
+void intel_uc_driver_remove(struct intel_uc *uc)
+{
+   intel_uc_fini_hw(uc);
+   intel_uc_fini(uc);
+   __uc_free_load_err_log(uc);
+}
+
 static inline bool guc_communication_enabled(struct intel_guc *guc)
 {
return intel_guc_ct_enabled(>ct);
@@ -311,8 +318,6 @@ static void __uc_fini(struct intel_uc *uc)
 {
intel_huc_fini(>huc);
intel_guc_fini(>guc);
-
-   __uc_free_load_err_log(uc);
 }
 
 static int __uc_sanitize(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 5ae7b50b7dc1..9c954c589edf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -34,6 +34,7 @@ struct intel_uc {
 
 void intel_uc_init_early(struct intel_uc *uc);
 void intel_uc_driver_late_release(struct intel_uc *uc);
+void intel_uc_driver_remove(struct intel_uc *uc);
 void intel_uc_init_mmio(struct intel_uc *uc);
 void intel_uc_reset_prepare(struct intel_uc *uc);
 void intel_uc_suspend(struct intel_uc *uc);
-- 
2.24.1

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[Intel-gfx] [PATCH v3 1/6] drm/i915/gt: allow setting generic data pointer

2020-03-26 Thread Daniele Ceraolo Spurio
From: Andi Shyti 

When registering debugfs files the intel gt debugfs library
forces a 'struct *gt' private data on the caller.

To be open to different usages make the new
"intel_gt_debugfs_register_files()"[*] function more generic by
converting the 'struct *gt' pointer to a 'void *' type.

I take the chance to rename the functions by using "intel_gt_" as
prefix instead of "debugfs_", so that "debugfs_gt_register_files()"
becomes "intel_gt_debugfs_register_files()".

Signed-off-by: Andi Shyti 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/debugfs_engines.c |  2 +-
 drivers/gpu/drm/i915/gt/debugfs_gt.c  | 11 +--
 drivers/gpu/drm/i915/gt/debugfs_gt.h  |  9 -
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c   | 14 +-
 4 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.c 
b/drivers/gpu/drm/i915/gt/debugfs_engines.c
index 6a5e9ab20b94..5e3725e62241 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_engines.c
@@ -32,5 +32,5 @@ void debugfs_engines_register(struct intel_gt *gt, struct 
dentry *root)
{ "engines", _fops },
};
 
-   debugfs_gt_register_files(gt, root, files, ARRAY_SIZE(files));
+   intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
 }
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c 
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index 75255aaacaed..de73b63d6ba7 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -26,15 +26,14 @@ void debugfs_gt_register(struct intel_gt *gt)
debugfs_gt_pm_register(gt, root);
 }
 
-void debugfs_gt_register_files(struct intel_gt *gt,
-  struct dentry *root,
-  const struct debugfs_gt_file *files,
-  unsigned long count)
+void intel_gt_debugfs_register_files(struct dentry *root,
+const struct debugfs_gt_file *files,
+unsigned long count, void *data)
 {
while (count--) {
-   if (!files->eval || files->eval(gt))
+   if (!files->eval || files->eval(data))
debugfs_create_file(files->name,
-   0444, root, gt,
+   0444, root, data,
files->fops);
 
files++;
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.h 
b/drivers/gpu/drm/i915/gt/debugfs_gt.h
index 4ea0f06cda8f..f77540f727e9 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.h
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.h
@@ -28,12 +28,11 @@ void debugfs_gt_register(struct intel_gt *gt);
 struct debugfs_gt_file {
const char *name;
const struct file_operations *fops;
-   bool (*eval)(const struct intel_gt *gt);
+   bool (*eval)(void *data);
 };
 
-void debugfs_gt_register_files(struct intel_gt *gt,
-  struct dentry *root,
-  const struct debugfs_gt_file *files,
-  unsigned long count);
+void intel_gt_debugfs_register_files(struct dentry *root,
+const struct debugfs_gt_file *files,
+unsigned long count, void *data);
 
 #endif /* DEBUGFS_GT_H */
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c 
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 059c9e5c002e..dc024944873a 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -506,9 +506,11 @@ static int llc_show(struct seq_file *m, void *data)
return 0;
 }
 
-static bool llc_eval(const struct intel_gt *gt)
+static bool llc_eval(void *data)
 {
-   return HAS_LLC(gt->i915);
+   struct intel_gt *gt = data;
+
+   return gt && HAS_LLC(gt->i915);
 }
 
 DEFINE_GT_DEBUGFS_ATTRIBUTE(llc);
@@ -580,9 +582,11 @@ static int rps_boost_show(struct seq_file *m, void *data)
return 0;
 }
 
-static bool rps_eval(const struct intel_gt *gt)
+static bool rps_eval(void *data)
 {
-   return HAS_RPS(gt->i915);
+   struct intel_gt *gt = data;
+
+   return gt && HAS_RPS(gt->i915);
 }
 
 DEFINE_GT_DEBUGFS_ATTRIBUTE(rps_boost);
@@ -597,5 +601,5 @@ void debugfs_gt_pm_register(struct intel_gt *gt, struct 
dentry *root)
{ "rps_boost", _boost_fops, rps_eval },
};
 
-   debugfs_gt_register_files(gt, root, files, ARRAY_SIZE(files));
+   intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
 }
-- 
2.24.1

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[Intel-gfx] [PATCH v3 5/6] drm/i915/uc: Move uC debugfs to its own folder under GT

2020-03-26 Thread Daniele Ceraolo Spurio
uC is a component of the GT, so it makes sense for the uC debugfs files
to be in the GT folder. A subfolder has been used to keep the same
structure we have for the code.

v2: use intel_* prefix (Jani), rebase on new gt_debugfs_register_files,
fix permissions for writable debugfs files.

v3: Rename files (Michal), remove blank line (Jani), fix sparse warns.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Andi Shyti 
Cc: Michal Wajdeczko 
Cc: John Harrison 
Cc: Matthew Brost 
Cc: Tony Ye 
Cc: Jani Nikula 
Reviewed-by: Andi Shyti  #v2
---
 drivers/gpu/drm/i915/Makefile |   4 +
 drivers/gpu/drm/i915/gt/debugfs_gt.c  |   6 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|   5 +
 .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c|  42 ++
 .../gpu/drm/i915/gt/uc/intel_guc_debugfs.h|  14 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c|   5 -
 .../drm/i915/gt/uc/intel_guc_log_debugfs.c| 124 
 .../drm/i915/gt/uc/intel_guc_log_debugfs.h|  15 ++
 .../gpu/drm/i915/gt/uc/intel_huc_debugfs.c|  36 +
 .../gpu/drm/i915/gt/uc/intel_huc_debugfs.h|  14 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c |  30 
 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h |  14 ++
 drivers/gpu/drm/i915/i915_debugfs.c   | 137 --
 13 files changed, 303 insertions(+), 143 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 99cd3d25f816..2fce8b0040f3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -167,14 +167,18 @@ i915-y += \
 
 # general-purpose microcontroller (GuC) support
 i915-y += gt/uc/intel_uc.o \
+ gt/uc/intel_uc_debugfs.o \
  gt/uc/intel_uc_fw.o \
  gt/uc/intel_guc.o \
  gt/uc/intel_guc_ads.o \
  gt/uc/intel_guc_ct.o \
+ gt/uc/intel_guc_debugfs.o \
  gt/uc/intel_guc_fw.o \
  gt/uc/intel_guc_log.o \
+ gt/uc/intel_guc_log_debugfs.o \
  gt/uc/intel_guc_submission.o \
  gt/uc/intel_huc.o \
+ gt/uc/intel_huc_debugfs.o \
  gt/uc/intel_huc_fw.o
 
 # modesetting core code
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c 
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index de73b63d6ba7..1de5fbaa1cf9 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -9,6 +9,7 @@
 #include "debugfs_engines.h"
 #include "debugfs_gt.h"
 #include "debugfs_gt_pm.h"
+#include "uc/intel_uc_debugfs.h"
 #include "i915_drv.h"
 
 void debugfs_gt_register(struct intel_gt *gt)
@@ -24,6 +25,8 @@ void debugfs_gt_register(struct intel_gt *gt)
 
debugfs_engines_register(gt, root);
debugfs_gt_pm_register(gt, root);
+
+   intel_uc_debugfs_register(>uc, root);
 }
 
 void intel_gt_debugfs_register_files(struct dentry *root,
@@ -31,9 +34,10 @@ void intel_gt_debugfs_register_files(struct dentry *root,
 unsigned long count, void *data)
 {
while (count--) {
+   umode_t mode = files->fops->write ? 0644 : 0444;
if (!files->eval || files->eval(data))
debugfs_create_file(files->name,
-   0444, root, data,
+   mode, root, data,
files->fops);
 
files++;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index a5d7a86be4cf..e84ab67b317d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -74,6 +74,11 @@ struct intel_guc {
struct mutex send_mutex;
 };
 
+static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
+{
+   return container_of(log, struct intel_guc, log);
+}
+
 static
 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
 {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
new file mode 100644
index ..fe7cb7b29a1e
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include 
+
+#include "gt/debugfs_gt.h"
+#include "intel_guc.h"
+#include "intel_guc_debugfs.h"
+#include "intel_guc_log_debugfs.h"
+
+static int guc_info_show(struct seq_file *m, void *data)
+{
+   

[Intel-gfx] [PATCH v3 0/6] Re-org uC debugfs files and move them under GT

2020-03-26 Thread Daniele Ceraolo Spurio
Minor changes applied to patch 5, which is the only one missing a
review.

As multiple people have noted, intel_gt_debugfs_register_files is
now generic enough to be pulled out of gt/. Andi has patches for that
and will follow up after this series is merged.

Cc: Andi Shyti 
Cc: Michal Wajdeczko 
Cc: John Harrison 
Cc: Matthew Brost 

Andi Shyti (1):
  drm/i915/gt: allow setting generic data pointer

Daniele Ceraolo Spurio (5):
  drm/i915/guc: drop stage_pool debugfs
  drm/i915/huc: make "support huc" reflect HW capabilities
  drm/i915/debugfs: move uC printers and update debugfs file names
  drm/i915/uc: Move uC debugfs to its own folder under GT
  drm/i915/uc: do not free err log on uc_fini

 drivers/gpu/drm/i915/Makefile |   4 +
 drivers/gpu/drm/i915/gt/debugfs_engines.c |   2 +-
 drivers/gpu/drm/i915/gt/debugfs_gt.c  |  15 +-
 drivers/gpu/drm/i915/gt/debugfs_gt.h  |   9 +-
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c   |  14 +-
 drivers/gpu/drm/i915/gt/intel_gt.c|   3 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  46 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|   7 +
 .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c|  42 +++
 .../gpu/drm/i915/gt/uc/intel_guc_debugfs.h|  14 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  14 -
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h |   1 -
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c|  97 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h|   4 +
 .../drm/i915/gt/uc/intel_guc_log_debugfs.c| 124 
 .../drm/i915/gt/uc/intel_guc_log_debugfs.h|  15 +
 drivers/gpu/drm/i915/gt/uc/intel_huc.c|  31 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc.h|   2 +
 .../gpu/drm/i915/gt/uc/intel_huc_debugfs.c|  36 +++
 .../gpu/drm/i915/gt/uc/intel_huc_debugfs.h|  14 +
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  17 --
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h |   1 -
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |   9 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.h |   1 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c |  30 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h |  14 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  25 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |   3 +-
 drivers/gpu/drm/i915/i915_debugfs.c   | 289 --
 29 files changed, 523 insertions(+), 360 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h

-- 
2.24.1

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[Intel-gfx] [PATCH v3 3/6] drm/i915/huc: make "support huc" reflect HW capabilities

2020-03-26 Thread Daniele Ceraolo Spurio
We currently initialize HuC support based on GuC being enabled in
modparam; this means that huc_is_supported() can return false on HW that
does have a HuC when enable_guc=0. The rationale for this behavior is
that HuC requires GuC for authentication and therefore is not supported
by itself. However, we do not allow defining HuC fw wthout GuC fw and
selecting HuC in modparam implicitly selects GuC as well, so we can't
actually hit a scenario where HuC is selected alone. Therefore, we can
flip the support check to reflect the HW capabilities and fw
availability, which is more intuitive and will make it cleaner to log
HuC the difference between not supported in HW and not selected.

Removing the difference between GuC and HuC also allows us to simplify
the init_early, since we don't need to differentiate the support based
on the type of uC.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: John Harrison 
Cc: Matthew Brost 
Reviewed-by: Andi Shyti 
Reviewed-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 14 -
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h |  1 -
 drivers/gpu/drm/i915/gt/uc/intel_huc.c|  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 17 ---
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h |  1 -
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 25 +++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  3 +--
 8 files changed, 20 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 819f09ef51fc..827d75073879 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -169,7 +169,7 @@ void intel_guc_init_early(struct intel_guc *guc)
 {
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 
-   intel_guc_fw_init_early(guc);
+   intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_GUC);
intel_guc_ct_init_early(>ct);
intel_guc_log_init_early(>log);
intel_guc_submission_init_early(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 3a1c47d600ea..d4a87f4c9421 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -13,20 +13,6 @@
 #include "intel_guc_fw.h"
 #include "i915_drv.h"
 
-/**
- * intel_guc_fw_init_early() - initializes GuC firmware struct
- * @guc: intel_guc struct
- *
- * On platforms with GuC selects firmware for uploading
- */
-void intel_guc_fw_init_early(struct intel_guc *guc)
-{
-   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
-   intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_GUC, HAS_GT_UC(i915),
-  INTEL_INFO(i915)->platform, INTEL_REVID(i915));
-}
-
 static void guc_prepare_xfer(struct intel_uncore *uncore)
 {
u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
index b5ab639d7259..0b4d2a9c9435 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
@@ -8,7 +8,6 @@
 
 struct intel_guc;
 
-void intel_guc_fw_init_early(struct intel_guc *guc);
 int intel_guc_fw_upload(struct intel_guc *guc);
 
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index a74b65694512..d73dc21686e7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -41,7 +41,7 @@ void intel_huc_init_early(struct intel_huc *huc)
 {
struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
 
-   intel_huc_fw_init_early(huc);
+   intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_HUC);
 
if (INTEL_GEN(i915) >= 11) {
huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 9cdf4cbe691c..e5ef509c70e8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -7,23 +7,6 @@
 #include "intel_huc_fw.h"
 #include "i915_drv.h"
 
-/**
- * intel_huc_fw_init_early() - initializes HuC firmware struct
- * @huc: intel_huc struct
- *
- * On platforms with HuC selects firmware for uploading
- */
-void intel_huc_fw_init_early(struct intel_huc *huc)
-{
-   struct intel_gt *gt = huc_to_gt(huc);
-   struct intel_uc *uc = >uc;
-   struct drm_i915_private *i915 = gt->i915;
-
-   intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_HUC,
-  intel_uc_wants_guc(uc),
-  INTEL_INFO(i915)->platform, INTEL_REVID(i915));
-}
-
 /**
  * intel_huc_fw_upload() - load HuC uCode to device
  * @huc: intel_huc structure
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h 
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
index b791269ce923..12f264ee3e0b 100644
--- 

[Intel-gfx] [PATCH v3 2/6] drm/i915/guc: drop stage_pool debugfs

2020-03-26 Thread Daniele Ceraolo Spurio
The pool will be private to GuC in the new submission scheme, so we
won't be able to print it and we can just drop the current legacy code.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: John Harrison 
Cc: Matthew Brost 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 53 -
 1 file changed, 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 25bf997e2dd1..ef875cec3524 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1356,58 +1356,6 @@ static int i915_guc_info(struct seq_file *m, void *data)
return 0;
 }
 
-static int i915_guc_stage_pool(struct seq_file *m, void *data)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct intel_uc *uc = _priv->gt.uc;
-   struct guc_stage_desc *desc = uc->guc.stage_desc_pool_vaddr;
-   int index;
-
-   if (!intel_uc_uses_guc_submission(uc))
-   return -ENODEV;
-
-   for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
-   struct intel_engine_cs *engine;
-
-   if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
-   continue;
-
-   seq_printf(m, "GuC stage descriptor %u:\n", index);
-   seq_printf(m, "\tIndex: %u\n", desc->stage_id);
-   seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
-   seq_printf(m, "\tPriority: %d\n", desc->priority);
-   seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
-   seq_printf(m, "\tEngines used: 0x%x\n",
-  desc->engines_used);
-   seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 
0x%x\n",
-  desc->db_trigger_phy,
-  desc->db_trigger_cpu,
-  desc->db_trigger_uk);
-   seq_printf(m, "\tProcess descriptor: 0x%x\n",
-  desc->process_desc);
-   seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
-  desc->wq_addr, desc->wq_size);
-   seq_putc(m, '\n');
-
-   for_each_uabi_engine(engine, dev_priv) {
-   u32 guc_engine_id = engine->guc_id;
-   struct guc_execlist_context *lrc =
-   >lrc[guc_engine_id];
-
-   seq_printf(m, "\t%s LRC:\n", engine->name);
-   seq_printf(m, "\t\tContext desc: 0x%x\n",
-  lrc->context_desc);
-   seq_printf(m, "\t\tContext id: 0x%x\n", 
lrc->context_id);
-   seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
-   seq_printf(m, "\t\tRing begin: 0x%x\n", 
lrc->ring_begin);
-   seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
-   seq_putc(m, '\n');
-   }
-   }
-
-   return 0;
-}
-
 static int i915_guc_log_dump(struct seq_file *m, void *data)
 {
struct drm_info_node *node = m->private;
@@ -2143,7 +2091,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
-   {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
{"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_ring_freq_table", i915_ring_freq_table, 0},
-- 
2.24.1

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[Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime

2020-03-26 Thread Chris Wilson
Upon a GPU reset, we copy the default context image over top of the
guilty image. This will rollback the CTX_TIMESTAMP register to before
our value of ce->runtime.last. Reset both back to 0 so that we do not
encounter an underflow on the next schedule out after resume.

This should not be a huge issue in practice, as hangs should be rare in
correct code.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..b458f8e17cf5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1154,6 +1154,7 @@ static void restore_default_state(struct intel_context 
*ce,
   engine->context_size - PAGE_SIZE);
 
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+   ce->runtime.last = intel_context_get_runtime(ce);
 }
 
 static void reset_active(struct i915_request *rq,
@@ -4581,6 +4582,7 @@ static void init_common_reg_state(u32 * const regs,
regs[CTX_CONTEXT_CONTROL] = ctl;
 
regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
+   regs[CTX_TIMESTAMP] = 0;
 }
 
 static void init_wa_bb_reg_state(u32 * const regs,
-- 
2.20.1

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Re: [Intel-gfx] [PATCH] drm/i915/perf: Do not clear pollin for small user read buffers

2020-03-26 Thread Umesh Nerlige Ramappa

On Wed, Mar 25, 2020 at 06:52:52PM -0700, Dixit, Ashutosh wrote:

On Wed, 25 Mar 2020 17:32:35 -0700, Umesh Nerlige Ramappa wrote:


On Wed, Mar 25, 2020 at 11:20:19AM -0700, Ashutosh Dixit wrote:
> It is wrong to block the user thread in the next poll when OA data is
> already available which could not fit in the user buffer provided in
> the previous read. In several cases the exact user buffer size is not
> known. Blocking user space in poll can lead to data loss when the
> buffer size used is smaller than the available data.
>
> This change fixes this issue and allows user space to read all OA data
> even when using a buffer size smaller than the available data using
> multiple non-blocking reads rather than staying blocked in poll till
> the next timer interrupt.
>
> Cc: Umesh Nerlige Ramappa 
> Cc: Lionel Landwerlin 
> Signed-off-by: Ashutosh Dixit 
> ---
> drivers/gpu/drm/i915/i915_perf.c | 62 ++--
> 1 file changed, 11 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c 
b/drivers/gpu/drm/i915/i915_perf.c
> index 3222f6cd8255..c1a47c030941 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2957,49 +2957,6 @@ void i915_oa_init_reg_state(const struct intel_context 
*ce,
>gen8_update_reg_state_unlocked(ce, stream);
> }
>
> -/**
> - * i915_perf_read_locked - _perf_stream_ops->read with error 
normalisation
> - * @stream: An i915 perf stream
> - * @file: An i915 perf stream file
> - * @buf: destination buffer given by userspace
> - * @count: the number of bytes userspace wants to read
> - * @ppos: (inout) file seek position (unused)
> - *
> - * Besides wrapping _perf_stream_ops->read this provides a common place 
to
> - * ensure that if we've successfully copied any data then reporting that 
takes
> - * precedence over any internal error status, so the data isn't lost.
> - *
> - * For example ret will be -ENOSPC whenever there is more buffered data than
> - * can be copied to userspace, but that's only interesting if we weren't able
> - * to copy some data because it implies the userspace buffer is too small to
> - * receive a single record (and we never split records).
> - *
> - * Another case with ret == -EFAULT is more of a grey area since it would 
seem
> - * like bad form for userspace to ask us to overrun its buffer, but the user
> - * knows best:
> - *
> - *   http://yarchive.net/comp/linux/partial_reads_writes.html
> - *
> - * Returns: The number of bytes copied or a negative error code on failure.
> - */
> -static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream,
> -   struct file *file,
> -   char __user *buf,
> -   size_t count,
> -   loff_t *ppos)
> -{
> -  /* Note we keep the offset (aka bytes read) separate from any
> -   * error status so that the final check for whether we return
> -   * the bytes read with a higher precedence than any error (see
> -   * comment below) doesn't need to be handled/duplicated in
> -   * stream->ops->read() implementations.
> -   */
> -  size_t offset = 0;
> -  int ret = stream->ops->read(stream, buf, count, );
> -
> -  return offset ?: (ret ?: -EAGAIN);
> -}
> -
> /**
>  * i915_perf_read - handles read() FOP for i915 perf stream FDs
>  * @file: An i915 perf stream file
> @@ -3025,6 +2982,8 @@ static ssize_t i915_perf_read(struct file *file,
> {
>struct i915_perf_stream *stream = file->private_data;
>struct i915_perf *perf = stream->perf;
> +  size_t offset = 0;
> +  int __ret;
>ssize_t ret;
>
>/* To ensure it's handled consistently we simply treat all reads of a
> @@ -3048,16 +3007,18 @@ static ssize_t i915_perf_read(struct file *file,
>return ret;
>
>mutex_lock(>lock);
> -  ret = i915_perf_read_locked(stream, file,
> -  buf, count, ppos);
> +  __ret = stream->ops->read(stream, buf, count, );
>mutex_unlock(>lock);
>} while (ret == -EAGAIN);

ret will never be EAGAIN here in the while. EAGAIN was returned by the
deleted function in this patch if offset and ret are both 0.


Good catch, I was so focussed on the non-blocking case that I missed the
blocking case.


Although I don't see how that would be true.


As you say above, the old function i915_perf_read_locked() was doing this:

return offset ?: (__ret ?: -EAGAIN);

So -EAGAIN is returned from i915_perf_read_locked() when there is no data
to read but otherwise there is no other error. Since this is blocking read
we cannot return -EAGAIN to user space (since there is no data to read), we
must go back and block again. That is the purpose of the while loop. I
broke this logic in this patch and will need to fix this.



>} else {
>mutex_lock(>lock);
> -  ret = 

Re: [Intel-gfx] [PATCH] drm/i915/display: Fix mode private_flags comparison at atomic_check

2020-03-26 Thread Shankar, Uma


> -Original Message-
> From: Ville Syrjälä 
> Sent: Thursday, March 26, 2020 9:47 PM
> To: Shankar, Uma 
> Cc: intel-gfx@lists.freedesktop.org; Maarten Lankhorst
> ; Kai Vehmanen
> ; Souza; Souza, Jose ;
> Khor, Swee Aun 
> Subject: Re: [PATCH] drm/i915/display: Fix mode private_flags comparison at
> atomic_check
> 
> On Thu, Mar 26, 2020 at 01:19:28PM +0530, Uma Shankar wrote:
> > This patch fixes the private_flags of mode to be checked and compared
> > against uapi.mode and not from hw.mode. This helps properly trigger
> > modeset at boot if desired by driver.
> >
> > It helps resolve audio_codec initialization issues if display is
> > connected at boot. Initial discussion on this issue has happened on
> > below thread:
> > https://patchwork.freedesktop.org/series/74828/
> >
> > Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1363
> >
> > Cc: Ville Syrjä 
> > Cc: Maarten Lankhorst 
> > Cc: Kai Vehmanen 
> > Cc: Souza, Jose 
> > Suggested-by: Ville Syrjä 
> 
> No one by that name here.

Copied this from an existing reference, not sure how some characters
got messed up ☹

> > Signed-off-by: Uma Shankar 
> > Signed-off-by: SweeAun Khor 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index fe55c7c713f1..e630429af2c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device 
> > *dev,
> > /* Catch I915_MODE_FLAG_INHERITED */
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > -   if (new_crtc_state->hw.mode.private_flags !=
> > -   old_crtc_state->hw.mode.private_flags)
> > +   if (new_crtc_state->uapi.mode.private_flags !=
> > +   old_crtc_state->uapi.mode.private_flags)
> > new_crtc_state->uapi.mode_changed = true;
> > }
> >
> > --
> > 2.22.0
> 
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/21] Revert "drm/i915/gem: Drop relocation slowpath"

2020-03-26 Thread Patchwork
== Series Details ==

Series: series starting with [01/21] Revert "drm/i915/gem: Drop relocation 
slowpath"
URL   : https://patchwork.freedesktop.org/series/75115/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8194 -> Patchwork_17096


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_17096 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17096, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_17096:

### IGT changes ###

 Possible regressions 

  * igt@gem_close_race@basic-process:
- fi-ivb-3770:[PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-ivb-3770/igt@gem_close_r...@basic-process.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-ivb-3770/igt@gem_close_r...@basic-process.html
- fi-hsw-4770:[PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-hsw-4770/igt@gem_close_r...@basic-process.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-hsw-4770/igt@gem_close_r...@basic-process.html
- fi-hsw-4770r:   [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-hsw-4770r/igt@gem_close_r...@basic-process.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-hsw-4770r/igt@gem_close_r...@basic-process.html

  * igt@gem_exec_fence@basic-await@rcs0:
- fi-blb-e6850:   [PASS][7] -> [DMESG-WARN][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-blb-e6850/igt@gem_exec_fence@basic-aw...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-blb-e6850/igt@gem_exec_fence@basic-aw...@rcs0.html
- fi-elk-e7500:   [PASS][9] -> [DMESG-WARN][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@rcs0.html
- fi-pnv-d510:[PASS][11] -> [DMESG-WARN][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-pnv-d510/igt@gem_exec_fence@basic-aw...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-pnv-d510/igt@gem_exec_fence@basic-aw...@rcs0.html
- fi-ilk-650: [PASS][13] -> [DMESG-WARN][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-ilk-650/igt@gem_exec_fence@basic-aw...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-ilk-650/igt@gem_exec_fence@basic-aw...@rcs0.html

  * igt@gem_exec_fence@basic-await@vcs0:
- fi-ilk-650: [PASS][15] -> [INCOMPLETE][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-ilk-650/igt@gem_exec_fence@basic-aw...@vcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-ilk-650/igt@gem_exec_fence@basic-aw...@vcs0.html

  * igt@gem_render_tiled_blits@basic:
- fi-gdg-551: [PASS][17] -> [DMESG-WARN][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-gdg-551/igt@gem_render_tiled_bl...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-gdg-551/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_selftest@live@gem_contexts:
- fi-skl-lmem:[PASS][19] -> [DMESG-WARN][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gem_contexts:
- {fi-kbl-7560u}: NOTRUN -> [DMESG-WARN][21]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-kbl-7560u/igt@i915_selftest@live@gem_contexts.html

  
Known issues


  Here are the changes found in Patchwork_17096 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-await@vcs0:
- fi-elk-e7500:   [PASS][22] -> [INCOMPLETE][23] ([i915#66])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@vcs0.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@vcs0.html

  * igt@i915_selftest@live@execlists:
- fi-icl-y:   [PASS][24] -> [DMESG-FAIL][25] ([fdo#108569])
   [24]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/21] Revert "drm/i915/gem: Drop relocation slowpath"

2020-03-26 Thread Patchwork
== Series Details ==

Series: series starting with [01/21] Revert "drm/i915/gem: Drop relocation 
slowpath"
URL   : https://patchwork.freedesktop.org/series/75115/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d083289b34df Revert "drm/i915/gem: Drop relocation slowpath"
-:78: WARNING:LINE_SPACING: Missing a blank line after declarations
#78: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1579:
+   int err = __get_user(c, addr);
+   if (err)

total: 0 errors, 1 warnings, 0 checks, 257 lines checked
936cc0098d93 drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2.
-:506: WARNING:LONG_LINE: line over 100 characters
#506: FILE: drivers/gpu/drm/i915/i915_gem.c:1338:
+   while ((obj = list_first_entry_or_null(>obj_list, struct 
drm_i915_gem_object, obj_link))) {

total: 0 errors, 1 warnings, 0 checks, 481 lines checked
74e05c05e4b8 drm/i915: Remove locking from i915_gem_object_prepare_read/write
41b0db48a24c drm/i915: Parse command buffer earlier in eb_relocate(slow)
4f72eac68d80 drm/i915: Use per object locking in execbuf, v6.
bfe136b956c4 drm/i915: Use ww locking in intel_renderstate.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#10: 
Convert to using ww-waiting, and make sure we always pin intel_context_state,

total: 0 errors, 1 warnings, 0 checks, 202 lines checked
0200da0a1df9 drm/i915: Add ww context handling to context_barrier_task
-:19: WARNING:LONG_LINE: line over 100 characters
#19: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:1100:
+   int (*pin)(struct intel_context *ce, struct 
i915_gem_ww_ctx *ww, void *data),

total: 0 errors, 1 warnings, 0 checks, 146 lines checked
6d83bbf7ff96 drm/i915: Nuke arguments to eb_pin_engine
757c8e3383b2 drm/i915: Pin engine before pinning all objects, v3.
9f9b3ccbfee0 drm/i915: Rework intel_context pinning to do everything outside of 
pin_mutex
-:125: CHECK:LINE_SPACING: Please don't use multiple blank lines
#125: FILE: drivers/gpu/drm/i915/gt/intel_context.c:176:
+
+

-:340: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#340: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:3045:
+   *vaddr = i915_gem_object_pin_map(ce->state->obj,
+   
i915_coherent_map_type(ce->engine->i915) |

total: 0 errors, 0 warnings, 2 checks, 445 lines checked
cfef16270648 drm/i915: Make sure execbuffer always passes ww state to 
i915_vma_pin.
-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:573:
+   err = i915_vma_pin_ww(vma, >ww,
   entry->pad_to_size, entry->alignment,

-:188: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#188: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2197:
+* hsw should have this fixed, but bdw mucks it up again. */

total: 0 errors, 1 warnings, 1 checks, 812 lines checked
85863b6646f5 drm/i915: Convert i915_gem_object/client_blt.c to use ww locking 
as well, v2.
cb74e29ea87a drm/i915: Kill last user of intel_context_create_request outside 
of selftests
f90980b43cf5 drm/i915: Convert i915_perf to ww locking as well
26070db64fbd drm/i915: Dirty hack to fix selftests locking inversion
b03c1aeda1ed drm/i915/selftests: Fix locking inversion in lrc selftest.
75eb93acc311 drm/i915: Use ww pinning for intel_context_create_request()
5f66150eaf57 drm/i915: Move i915_vma_lock in the selftests to avoid lock 
inversion, v2.
e91160d4fd13 drm/i915: Add ww locking to vm_fault_gtt
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 91 lines checked
1e09059f0103 drm/i915: Add ww locking to pin_to_display_plane
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 129 lines checked
1551e4c71efc drm/i915: Ensure we hold the pin mutex
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 37 lines checked

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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm:i915:display: add checks for Gen9 devices with hdr capability

2020-03-26 Thread Patchwork
== Series Details ==

Series: drm:i915:display: add checks for Gen9 devices with hdr capability
URL   : https://patchwork.freedesktop.org/series/75114/
State : failure

== Summary ==

Applying: drm:i915:display: add checks for Gen9 devices with hdr capability
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/display/intel_hdmi.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0001 drm:i915:display: add checks for Gen9 devices with hdr 
capability
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [Intel-gfx] [PATCH] drivers/gpu/drm/i915/selftests/i915_buddy.c: Fix bug

2020-03-26 Thread Matthew Auld
On Wed, 25 Mar 2020 at 21:23, George Spelvin  wrote:
>
> igt_mm_config() calls ilog2() on the (pseudo)random 21-bit number
> s>>12.  Once in 2 million seeds, this is zero and ilog2 summons
> the nasal demons.
>
> There was an attempt to handle this case with a max(), but that's
> too late; ms could already be something bizarre.
>
> Given that the low 12 bits of s and ms are always zero, it's a lot
> simpler just to divide them by 4096, then everything fits into 32
> bits, and we can easily generate a random number 1 <= s <= 0x1f.
>
> Signed-off-by: George Spelvin 
> Fixes: 14d1b9a6247c
> Cc: Matthew Auld 
> Cc: Jani Nikula 
> Cc: Joonas Lahtinen 
> Cc: Rodrigo Vivi 
> Cc: intel-gfx@lists.freedesktop.org
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH v5 14/16] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message

2020-03-26 Thread Lyude Paul
On Thu, 2020-03-05 at 15:12 -0500, Sean Paul wrote:
> From: Sean Paul 
> 
> Used to query whether an MST stream is encrypted or not.
> 
> Signed-off-by: Sean Paul 
> 
> Link: 
> https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-s...@poorly.run
> #v4
> 
> Changes in v4:
> -Added to the set
> Changes in v5:
> -None
> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 117 ++
>  include/drm/drm_dp_helper.h   |   3 +
>  include/drm/drm_dp_mst_helper.h   |  44 ++
>  3 files changed, 164 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 6c62ad8f44142..5bba5aac86f31 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -25,6 +25,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  
> @@ -418,6 +419,22 @@ drm_dp_encode_sideband_req(const struct
> drm_dp_sideband_msg_req_body *req,
>   memcpy([idx], req->u.i2c_write.bytes, req-
> >u.i2c_write.num_bytes);
>   idx += req->u.i2c_write.num_bytes;
>   break;
> + case DP_QUERY_STREAM_ENC_STATUS: {
> + const struct drm_dp_query_stream_enc_status *msg;
> +
> + msg = >u.enc_status;
> + buf[idx] = msg->stream_id;
> + idx++;
> + memcpy([idx], msg->client_id, sizeof(msg->client_id));
> + idx += sizeof(msg->client_id);
> + buf[idx] = 0;
> + buf[idx] |= msg->stream_event & GENMASK(1, 0);
> + buf[idx] |= msg->valid_stream_event ? BIT(2) : 0;
> + buf[idx] |= (msg->stream_behavior & GENMASK(1, 0)) << 3;
> + buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0;
> + idx++;
> + }
> + break;
>   }
>   raw->cur_len = idx;
>  }
> @@ -930,6 +947,34 @@ static bool
> drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms
>   return true;
>  }
>  
> +static bool
> +drm_dp_sideband_parse_query_stream_enc_status(
> + struct drm_dp_sideband_msg_rx *raw,
> + struct drm_dp_sideband_msg_reply_body *repmsg)
> +{
> + struct drm_dp_query_stream_enc_status_ack_reply *reply;
> +
> + reply = >u.enc_status;
> +
> + reply->stream_id = raw->msg[3];
> +
> + reply->reply_signed = raw->msg[2] & BIT(0);
> +
> + reply->hdcp_1x_device_present = raw->msg[2] & BIT(3);
> + reply->hdcp_2x_device_present = raw->msg[2] & BIT(4);
> +
> + reply->query_capable_device_present = raw->msg[2] & BIT(5);
> + reply->legacy_device_present = raw->msg[2] & BIT(6);
> + reply->unauthorizable_device_present = raw->msg[2] & BIT(7);
> +
> + reply->auth_completed = !!(raw->msg[1] & BIT(3));
> + reply->encryption_enabled = !!(raw->msg[1] & BIT(4));
> + reply->repeater_present = !!(raw->msg[1] & BIT(5));
> + reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6;
> +
> + return true;
> +}

I don't mind terribly either way, but since you're already using the
BIT/GENMASK() macros have you considered GET_BITFIELD()?

> +
>  static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw,
>   struct drm_dp_sideband_msg_reply_body
> *msg)
>  {
> @@ -964,6 +1009,8 @@ static bool drm_dp_sideband_parse_reply(struct
> drm_dp_sideband_msg_rx *raw,
>   return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg);
>   case DP_CLEAR_PAYLOAD_ID_TABLE:
>   return true; /* since there's nothing to parse */
> + case DP_QUERY_STREAM_ENC_STATUS:
> + return drm_dp_sideband_parse_query_stream_enc_status(raw,
> msg);
>   default:
>   DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type,
> drm_dp_mst_req_type_str(msg->req_type));
> @@ -1115,6 +1162,25 @@ static void build_power_updown_phy(struct
> drm_dp_sideband_msg_tx *msg,
>   msg->path_msg = true;
>  }
>  
> +static int
> +build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8
> stream_id,
> +   u8 *q_id)
> +{
> + struct drm_dp_sideband_msg_req_body req;
> +
> + req.req_type = DP_QUERY_STREAM_ENC_STATUS;
> + req.u.enc_status.stream_id = stream_id;
> + memcpy(req.u.enc_status.client_id, q_id,
> +sizeof(req.u.enc_status.client_id));
> + req.u.enc_status.stream_event = 0;
> + req.u.enc_status.valid_stream_event = false;
> + req.u.enc_status.stream_behavior = 0;
> + req.u.enc_status.valid_stream_behavior = false;
> +
> + drm_dp_encode_sideband_req(, msg);
> + return 0;
> +}
> +
>  static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr
> *mgr,
>   struct drm_dp_vcpi *vcpi)
>  {
> @@ -3151,6 +3217,57 @@ int drm_dp_send_power_updown_phy(struct
> drm_dp_mst_topology_mgr *mgr,
>  }
>  

[Intel-gfx] [PATCH] drm/i915/selftests: Check timeout before flush and cond checks

2020-03-26 Thread Chris Wilson
Allow a bit of leniency for the CPU scheduler to be distracted while we
flush the tasklet and so ensure that we always check the status of the
request once more before timing out.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/selftest_lrc.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c 
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 6f06ba750a0a..b8c8355b1095 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -74,20 +74,19 @@ static int wait_for_submit(struct intel_engine_cs *engine,
 {
timeout += jiffies;
do {
-   cond_resched();
-   intel_engine_flush_submission(engine);
+   bool done = time_after(jiffies, timeout);
 
-   if (READ_ONCE(engine->execlists.pending[0]))
-   continue;
+   intel_engine_flush_submission(engine);
 
if (i915_request_is_active(rq))
return 0;
 
if (i915_request_started(rq)) /* that was quick! */
return 0;
-   } while (time_before(jiffies, timeout));
 
-   return -ETIME;
+   if (done)
+   return -ETIME;
+   } while (1);
 }
 
 static int wait_for_reset(struct intel_engine_cs *engine,
-- 
2.20.1

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Re: [Intel-gfx] [PATCH] drm/i915/display: Fix mode private_flags comparison at atomic_check

2020-03-26 Thread Ville Syrjälä
On Thu, Mar 26, 2020 at 01:19:28PM +0530, Uma Shankar wrote:
> This patch fixes the private_flags of mode to be checked and
> compared against uapi.mode and not from hw.mode. This helps
> properly trigger modeset at boot if desired by driver.
> 
> It helps resolve audio_codec initialization issues if display
> is connected at boot. Initial discussion on this issue has happened
> on below thread:
> https://patchwork.freedesktop.org/series/74828/
> 
> Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1363
> 
> Cc: Ville Syrjä 
> Cc: Maarten Lankhorst 
> Cc: Kai Vehmanen 
> Cc: Souza, Jose 
> Suggested-by: Ville Syrjä 

No one by that name here.

> Signed-off-by: Uma Shankar 
> Signed-off-by: SweeAun Khor 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index fe55c7c713f1..e630429af2c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device *dev,
>   /* Catch I915_MODE_FLAG_INHERITED */
>   for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>   new_crtc_state, i) {
> - if (new_crtc_state->hw.mode.private_flags !=
> - old_crtc_state->hw.mode.private_flags)
> + if (new_crtc_state->uapi.mode.private_flags !=
> + old_crtc_state->uapi.mode.private_flags)
>   new_crtc_state->uapi.mode_changed = true;
>   }
>  
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Enable scaling filter for plane and CRTC

2020-03-26 Thread Ville Syrjälä
On Thu, Mar 26, 2020 at 08:45:59PM +0530, Bharadiya,Pankaj wrote:
> On Tue, Mar 24, 2020 at 06:46:10PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 24, 2020 at 03:32:09PM +, Laxminarayan Bharadiya, Pankaj 
> > wrote:
> > > 
> > > 
> > > > -Original Message-
> > > > From: Ville Syrjälä 
> > > > Sent: 23 March 2020 20:18
> > > > To: Laxminarayan Bharadiya, Pankaj
> > > > 
> > > > Cc: Lattannavar, Sameer ;
> > > > jani.nik...@linux.intel.com; dan...@ffwll.ch; 
> > > > intel-gfx@lists.freedesktop.org;
> > > > dri-de...@lists.freedesktop.org; dani...@collabora.com; Joonas Lahtinen
> > > > ; Vivi, Rodrigo 
> > > > ;
> > > > David Airlie ; Chris Wilson 
> > > > ;
> > > > Maarten Lankhorst ; Souza, Jose
> > > > ; Deak, Imre ; Shankar, Uma
> > > > 
> > > > Subject: Re: [PATCH v2 5/5] drm/i915: Enable scaling filter for plane 
> > > > and CRTC
> > > > 
> > > > On Thu, Mar 19, 2020 at 03:51:03PM +0530, Pankaj Bharadiya wrote:
> > > > > GEN >= 10 hardware supports the programmable scaler filter.
> > > > >
> > > > > Attach scaling filter property for CRTC and plane for GEN >= 10
> > > > > hardwares and program scaler filter based on the selected filter type.
> > > > >
> > > > > changes since v1:
> > > > > * None
> > > > > Changes since RFC:
> > > > > * Enable properties for GEN >= 10 platforms (Ville)
> > > > > * Do not round off the crtc co-ordinate (Danial Stone, Ville)
> > > > > * Add new functions to handle scaling filter setup (Ville)
> > > > > * Remove coefficient set 0 hardcoding.
> > > > >
> > > > > Signed-off-by: Shashank Sharma 
> > > > > Signed-off-by: Ankit Nautiyal 
> > > > > Signed-off-by: Pankaj Bharadiya
> > > > > 
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_display.c | 32
> > > > > ++--  drivers/gpu/drm/i915/display/intel_sprite.c  |
> > > > > 31 ++-
> > > > >  2 files changed, 60 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 791dd908aa89..4b3387ee332e 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -6309,6 +6309,25 @@ void
> > > > skl_scaler_setup_nearest_neighbor_filter(struct drm_i915_private 
> > > > *dev_priv,
> > > > >   }
> > > > >  }
> > > > >
> > > > > +static u32
> > > > > +skl_scaler_crtc_setup_filter(struct drm_i915_private *dev_priv, enum 
> > > > > pipe
> > > > pipe,
> > > > > +   int id, int set, enum drm_crtc_scaling_filter 
> > > > > filter) {
> > > > > + u32 scaler_filter_ctl = PS_FILTER_MEDIUM;
> > > > > +
> > > > > + if (filter == DRM_CRTC_SCALING_FILTER_NEAREST_NEIGHBOR) {
> > > > > + skl_scaler_setup_nearest_neighbor_filter(dev_priv, 
> > > > > pipe, id,
> > > > > +  set);
> > > > > + scaler_filter_ctl = PS_FILTER_PROGRAMMED |
> > > > > + PS_UV_VERT_FILTER_SELECT(set) |
> > > > > + PS_UV_HORZ_FILTER_SELECT(set) |
> > > > > + PS_Y_VERT_FILTER_SELECT(set) |
> > > > > + PS_Y_HORZ_FILTER_SELECT(set);
> > > > > +
> > > > > + }
> > > > > + return scaler_filter_ctl;
> > > > 
> > > > This function does too many things.
> > > 
> > > I was thinking to have a common function which configures the filter and 
> > > also
> > > provides the register bits (ps_ctrl) to select a desired filter so that 
> > > we need
> > > not have extra condition to figure out filter select register bits where 
> > > this
> > > function is being called.
> > > How about renaming this function to some better name like  
> > > skl_scaler_set_and_get_filter_select() or something else? 
> > > Or shall I breakdown this function into multiple functions?
> > 
> > I'd just inline the PS_CTRL stuff into the current function.
> 
> I am yet to verify this, but would like to get your early comments.
> How about something like this? -
> 
> +inline u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int 
> set)
> +{
> +   u32 filter_select = PS_FILTER_MEDIUM;

Pointless variable. 

if (whatever)
return A;
else
return B;

> +
> +   if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
> +   filter_select = PS_FILTER_PROGRAMMED |
> +   PS_UV_VERT_FILTER_SELECT(set) |
> +   PS_UV_HORZ_FILTER_SELECT(set) |
> +   PS_Y_VERT_FILTER_SELECT(set) |
> +   PS_Y_HORZ_FILTER_SELECT(set);
> +   }
> +
> +   return filter_select;
> +}
> +
> +void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe 
> pipe,
> +int id, int set, enum drm_scaling_filter filter)
> +{
> +   switch(filter) {
> +   case DRM_SCALING_FILTER_DEFAULT:
> +   break;
> +

Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Enable scaling filter for plane and CRTC

2020-03-26 Thread Bharadiya,Pankaj
On Tue, Mar 24, 2020 at 06:46:10PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 24, 2020 at 03:32:09PM +, Laxminarayan Bharadiya, Pankaj 
> wrote:
> > 
> > 
> > > -Original Message-
> > > From: Ville Syrjälä 
> > > Sent: 23 March 2020 20:18
> > > To: Laxminarayan Bharadiya, Pankaj
> > > 
> > > Cc: Lattannavar, Sameer ;
> > > jani.nik...@linux.intel.com; dan...@ffwll.ch; 
> > > intel-gfx@lists.freedesktop.org;
> > > dri-de...@lists.freedesktop.org; dani...@collabora.com; Joonas Lahtinen
> > > ; Vivi, Rodrigo ;
> > > David Airlie ; Chris Wilson ;
> > > Maarten Lankhorst ; Souza, Jose
> > > ; Deak, Imre ; Shankar, Uma
> > > 
> > > Subject: Re: [PATCH v2 5/5] drm/i915: Enable scaling filter for plane and 
> > > CRTC
> > > 
> > > On Thu, Mar 19, 2020 at 03:51:03PM +0530, Pankaj Bharadiya wrote:
> > > > GEN >= 10 hardware supports the programmable scaler filter.
> > > >
> > > > Attach scaling filter property for CRTC and plane for GEN >= 10
> > > > hardwares and program scaler filter based on the selected filter type.
> > > >
> > > > changes since v1:
> > > > * None
> > > > Changes since RFC:
> > > > * Enable properties for GEN >= 10 platforms (Ville)
> > > > * Do not round off the crtc co-ordinate (Danial Stone, Ville)
> > > > * Add new functions to handle scaling filter setup (Ville)
> > > > * Remove coefficient set 0 hardcoding.
> > > >
> > > > Signed-off-by: Shashank Sharma 
> > > > Signed-off-by: Ankit Nautiyal 
> > > > Signed-off-by: Pankaj Bharadiya
> > > > 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display.c | 32
> > > > ++--  drivers/gpu/drm/i915/display/intel_sprite.c  |
> > > > 31 ++-
> > > >  2 files changed, 60 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 791dd908aa89..4b3387ee332e 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -6309,6 +6309,25 @@ void
> > > skl_scaler_setup_nearest_neighbor_filter(struct drm_i915_private 
> > > *dev_priv,
> > > > }
> > > >  }
> > > >
> > > > +static u32
> > > > +skl_scaler_crtc_setup_filter(struct drm_i915_private *dev_priv, enum 
> > > > pipe
> > > pipe,
> > > > + int id, int set, enum drm_crtc_scaling_filter 
> > > > filter) {
> > > > +   u32 scaler_filter_ctl = PS_FILTER_MEDIUM;
> > > > +
> > > > +   if (filter == DRM_CRTC_SCALING_FILTER_NEAREST_NEIGHBOR) {
> > > > +   skl_scaler_setup_nearest_neighbor_filter(dev_priv, 
> > > > pipe, id,
> > > > +set);
> > > > +   scaler_filter_ctl = PS_FILTER_PROGRAMMED |
> > > > +   PS_UV_VERT_FILTER_SELECT(set) |
> > > > +   PS_UV_HORZ_FILTER_SELECT(set) |
> > > > +   PS_Y_VERT_FILTER_SELECT(set) |
> > > > +   PS_Y_HORZ_FILTER_SELECT(set);
> > > > +
> > > > +   }
> > > > +   return scaler_filter_ctl;
> > > 
> > > This function does too many things.
> > 
> > I was thinking to have a common function which configures the filter and 
> > also
> > provides the register bits (ps_ctrl) to select a desired filter so that we 
> > need
> > not have extra condition to figure out filter select register bits where 
> > this
> > function is being called.
> > How about renaming this function to some better name like  
> > skl_scaler_set_and_get_filter_select() or something else? 
> > Or shall I breakdown this function into multiple functions?
> 
> I'd just inline the PS_CTRL stuff into the current function.

I am yet to verify this, but would like to get your early comments.
How about something like this? -

+inline u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int 
set)
+{
+   u32 filter_select = PS_FILTER_MEDIUM;
+
+   if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
+   filter_select = PS_FILTER_PROGRAMMED |
+   PS_UV_VERT_FILTER_SELECT(set) |
+   PS_UV_HORZ_FILTER_SELECT(set) |
+   PS_Y_VERT_FILTER_SELECT(set) |
+   PS_Y_HORZ_FILTER_SELECT(set);
+   }
+
+   return filter_select;
+}
+
+void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
+int id, int set, enum drm_scaling_filter filter)
+{
+   switch(filter) {
+   case DRM_SCALING_FILTER_DEFAULT:
+   break;
+   case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
+   cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
+   break;
+   default:
+   default:
+   MISSING_CASE(filter);
+   }
+}
+
 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

Re: [Intel-gfx] [PATCH 00/51] drm_device managed resources, v5

2020-03-26 Thread Daniel Vetter
On Mon, Mar 23, 2020 at 03:48:59PM +0100, Daniel Vetter wrote:
> Hi all,
> 
> Another round, another set of polish all over. intel-gfx-ci was happy last
> time around (after I fixed a fumble), so really just review and comments
> needed now. There's still a few patches at the beginning holding the
> entire thing up and preventing merging of the driver patches which have
> acks/r-b already.
> 
> Thanks, Daniel

Ok got them all, applied them all. Thanks a lot to everyone for providing
review, feedback and testing on these.

Thanks, Daniel

> 
> Daniel Vetter (51):
>   mm/sl[uo]b: export __kmalloc_track(_node)_caller
>   drm/i915: Don't clear drvdata in ->release
>   drm: add managed resources tied to drm_device
>   drm: Set final_kfree in drm_dev_alloc
>   drm/mipi_dbi: Use drmm_add_final_kfree in all drivers
>   drm/udl: Use drmm_add_final_kfree
>   drm/qxl: Use drmm_add_final_kfree
>   drm/i915: Use drmm_add_final_kfree
>   drm/cirrus: Use drmm_add_final_kfree
>   drm/v3d: Use drmm_add_final_kfree
>   drm/tidss: Use drmm_add_final_kfree
>   drm/mcde: Use drmm_add_final_kfree
>   drm/vgem: Use drmm_add_final_kfree
>   drm/vkms: Use drmm_add_final_kfree
>   drm/repaper: Use drmm_add_final_kfree
>   drm/ingenic: Use drmm_add_final_kfree
>   drm/gm12u320: Use drmm_add_final_kfree
>   drm/: Use drmm_add_final_kfree
>   drm: Cleanups after drmm_add_final_kfree rollout
>   drm: Handle dev->unique with drmm_
>   drm: Use drmm_ for drm_dev_init cleanup
>   drm: manage drm_minor cleanup with drmm_
>   drm: Manage drm_gem_init with drmm_
>   drm: Manage drm_vblank_cleanup with drmm_
>   drm: Garbage collect drm_dev_fini
>   drm: Manage drm_mode_config_init with drmm_
>   drm/bochs: Remove leftover drm_atomic_helper_shutdown
>   drm/bochs: Drop explicit drm_mode_config_cleanup
>   drm/cirrus: Drop explicit drm_mode_config_cleanup call
>   drm/cirrus: Fully embrace devm_
>   drm/ingenic: Drop explicit drm_mode_config_cleanup call
>   drm/mcde: Drop explicit drm_mode_config_cleanup call
>   drm/mcde: More devm_drm_dev_init
>   drm/meson: Drop explicit drm_mode_config_cleanup call
>   drm/pl111: Drop explicit drm_mode_config_cleanup call
>   drm/rcar-du: Drop explicit drm_mode_config_cleanup call
>   drm/rockchip: Drop explicit drm_mode_config_cleanup call
>   drm/stm: Drop explicit drm_mode_config_cleanup call
>   drm/shmob: Drop explicit drm_mode_config_cleanup call
>   drm/mtk: Drop explicit drm_mode_config_cleanup call
>   drm/tidss: Drop explicit drm_mode_config_cleanup call
>   drm/gm12u320: More drmm_
>   drm/gm12u320: Use devm_drm_dev_init
>   drm/gm12u320: Use helpers for shutdown/suspend/resume
>   drm/gm12u320: Simplify upload work
>   drm/repaper: Drop explicit drm_mode_config_cleanup call
>   drm/mipi-dbi: Move drm_mode_config_init into mipi library
>   drm/mipi-dbi: Drop explicit drm_mode_config_cleanup call
>   drm/udl: Drop explicit drm_mode_config_cleanup call
>   drm/udl: drop drm_driver.release hook
>   drm: Add docs for managed resources
> 
>  Documentation/gpu/drm-internals.rst   |  12 +
>  Documentation/gpu/drm-kms.rst |   2 +-
>  drivers/gpu/drm/Makefile  |   3 +-
>  .../gpu/drm/arm/display/komeda/komeda_kms.c   |   2 +
>  drivers/gpu/drm/armada/armada_drv.c   |   2 +
>  drivers/gpu/drm/bochs/bochs.h |   1 -
>  drivers/gpu/drm/bochs/bochs_drv.c |   6 +-
>  drivers/gpu/drm/bochs/bochs_kms.c |  15 +-
>  drivers/gpu/drm/cirrus/cirrus.c   |  74 ++---
>  drivers/gpu/drm/drm_drv.c | 215 ++
>  drivers/gpu/drm/drm_gem.c |  21 +-
>  drivers/gpu/drm/drm_internal.h|   5 +-
>  drivers/gpu/drm/drm_managed.c | 276 ++
>  drivers/gpu/drm/drm_mipi_dbi.c|  24 +-
>  drivers/gpu/drm/drm_mode_config.c |  23 +-
>  drivers/gpu/drm/drm_vblank.c  |  31 +-
>  drivers/gpu/drm/i915/i915_drv.c   |  22 +-
>  drivers/gpu/drm/i915/i915_drv.h   |   3 +
>  .../gpu/drm/i915/selftests/mock_gem_device.c  |  32 +-
>  drivers/gpu/drm/ingenic/ingenic-drm.c |  17 +-
>  drivers/gpu/drm/mcde/mcde_drv.c   |  35 +--
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c|   9 +-
>  drivers/gpu/drm/meson/meson_drv.c |   5 +-
>  drivers/gpu/drm/pl111/pl111_drv.c |  12 +-
>  drivers/gpu/drm/qxl/qxl_drv.c |   2 -
>  drivers/gpu/drm/qxl/qxl_kms.c |   2 +
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c |   1 -
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c |   4 +-
>  drivers/gpu/drm/rockchip/rockchip_drm_drv.c   |  14 +-
>  drivers/gpu/drm/shmobile/shmob_drm_drv.c  |   2 -
>  drivers/gpu/drm/shmobile/shmob_drm_kms.c  |   6 +-
>  drivers/gpu/drm/stm/drv.c |  10 +-
>  drivers/gpu/drm/tidss/tidss_drv.c |  10 +-
>  drivers/gpu/drm/tidss/tidss_kms.c |  19 +-
>  

[Intel-gfx] [PATCH 04/12] dma-buf: Prettify typecasts for dma-fence-chain

2020-03-26 Thread Chris Wilson
Inside dma-fence-chain, we use a cmpxchg on an RCU-protected pointer. To
avoid the sparse warning for using the RCU pointer directly, we have to
cast away the __rcu annotation. However, we don't need to use void*
everywhere and can stick to the dma_fence*.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/dma-buf/dma-fence-chain.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/dma-buf/dma-fence-chain.c 
b/drivers/dma-buf/dma-fence-chain.c
index 44a741677d25..3d123502ff12 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -62,7 +62,8 @@ struct dma_fence *dma_fence_chain_walk(struct dma_fence 
*fence)
replacement = NULL;
}
 
-   tmp = cmpxchg((void **)>prev, (void *)prev, (void 
*)replacement);
+   tmp = cmpxchg((struct dma_fence __force **)>prev,
+ prev, replacement);
if (tmp == prev)
dma_fence_put(tmp);
else
-- 
2.20.1

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[Intel-gfx] [PATCH 08/12] drm/syncobj: Allow use of dma-fence-proxy

2020-03-26 Thread Chris Wilson
Allow the callers to supply a dma-fence-proxy for asynchronous waiting on
future fences.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/drm_syncobj.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 42d46414f767..e141db0e1eb6 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -184,6 +184,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -324,14 +325,9 @@ void drm_syncobj_replace_fence(struct drm_syncobj *syncobj,
struct dma_fence *old_fence;
struct syncobj_wait_entry *cur, *tmp;
 
-   if (fence)
-   dma_fence_get(fence);
-
spin_lock(>lock);
 
-   old_fence = rcu_dereference_protected(syncobj->fence,
- lockdep_is_held(>lock));
-   rcu_assign_pointer(syncobj->fence, fence);
+   old_fence = dma_fence_replace_proxy(>fence, fence);
 
if (fence != old_fence) {
list_for_each_entry_safe(cur, tmp, >cb_list, node)
-- 
2.20.1

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[Intel-gfx] [PATCH 03/12] drm/i915/perf: Schedule oa_config after modifying the contexts

2020-03-26 Thread Chris Wilson
We wish that the scheduler emit the context modification commands prior
to enabling the oa_config, for which we must explicitly inform it of the
ordering constraints. This is especially important as we now wait for
the final oa_config setup to be completed and as this wait may be on a
distinct context to the state modifications, we need that command packet
to be always last in the queue.

We borrow the i915_active for its ability to track multiple timelines
and the last dma_fence on each; a flexible dma_resv. Keeping track of
each dma_fence is important for us so that we can efficiently schedule
the requests and reprioritise as required.

Reported-by: Lionel Landwerlin 
Signed-off-by: Chris Wilson 
Cc: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/display/intel_overlay.c  |   8 +-
 drivers/gpu/drm/i915/gt/intel_context_param.c |   2 +-
 drivers/gpu/drm/i915/i915_active.c|   6 +-
 drivers/gpu/drm/i915/i915_active.h|   2 +-
 drivers/gpu/drm/i915/i915_perf.c  | 154 +++---
 drivers/gpu/drm/i915/i915_perf_types.h|   5 +-
 drivers/gpu/drm/i915/i915_vma.h   |   2 +-
 drivers/gpu/drm/i915/selftests/i915_active.c  |   4 +-
 8 files changed, 115 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c 
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 6e1d66323223..f1c948b4f6d4 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -272,7 +272,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
 
i915_request_add(rq);
 
-   return i915_active_wait(>last_flip);
+   return i915_active_wait(>last_flip, TASK_INTERRUPTIBLE);
 }
 
 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
@@ -429,14 +429,14 @@ static int intel_overlay_off(struct intel_overlay 
*overlay)
intel_overlay_flip_prepare(overlay, NULL);
i915_request_add(rq);
 
-   return i915_active_wait(>last_flip);
+   return i915_active_wait(>last_flip, TASK_INTERRUPTIBLE);
 }
 
 /* recover from an interruption due to a signal
  * We have to be careful not to repeat work forever an make forward progess. */
 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 {
-   return i915_active_wait(>last_flip);
+   return i915_active_wait(>last_flip, TASK_INTERRUPTIBLE);
 }
 
 /* Wait for pending overlay flip and release old frame.
@@ -477,7 +477,7 @@ static int intel_overlay_release_old_vid(struct 
intel_overlay *overlay)
 
i915_request_add(rq);
 
-   return i915_active_wait(>last_flip);
+   return i915_active_wait(>last_flip, TASK_INTERRUPTIBLE);
 }
 
 void intel_overlay_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_param.c 
b/drivers/gpu/drm/i915/gt/intel_context_param.c
index 65dcd090245d..903cce8c23c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_param.c
+++ b/drivers/gpu/drm/i915/gt/intel_context_param.c
@@ -15,7 +15,7 @@ int intel_context_set_ring_size(struct intel_context *ce, 
long sz)
if (intel_context_lock_pinned(ce))
return -EINTR;
 
-   err = i915_active_wait(>active);
+   err = i915_active_wait(>active, TASK_INTERRUPTIBLE);
if (err < 0)
goto unlock;
 
diff --git a/drivers/gpu/drm/i915/i915_active.c 
b/drivers/gpu/drm/i915/i915_active.c
index 2df49d2d114e..b746c24d65d5 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -496,7 +496,7 @@ static int flush_lazy_signals(struct i915_active *ref)
return err;
 }
 
-int i915_active_wait(struct i915_active *ref)
+int i915_active_wait(struct i915_active *ref, int state)
 {
int err;
 
@@ -511,7 +511,9 @@ int i915_active_wait(struct i915_active *ref)
if (err)
return err;
 
-   if (wait_var_event_interruptible(ref, i915_active_is_idle(ref)))
+   if (!i915_active_is_idle(ref) &&
+   ___wait_var_event(ref, i915_active_is_idle(ref),
+ state, 0, 0, schedule()))
return -EINTR;
 
flush_work(>work);
diff --git a/drivers/gpu/drm/i915/i915_active.h 
b/drivers/gpu/drm/i915/i915_active.h
index bffbcf7751a7..224b95a95fcd 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -181,7 +181,7 @@ static inline bool i915_active_has_exclusive(struct 
i915_active *ref)
return rcu_access_pointer(ref->excl.fence);
 }
 
-int i915_active_wait(struct i915_active *ref);
+int i915_active_wait(struct i915_active *ref, int state);
 
 int i915_sw_fence_await_active(struct i915_sw_fence *fence,
   struct i915_active *ref,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 3222f6cd8255..2aaaeb42977f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1961,10 +1961,11 @@ get_oa_vma(struct 

[Intel-gfx] [PATCH 12/12] drm/i915/gt: Declare when we enabled timeslicing

2020-03-26 Thread Chris Wilson
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING

v2: Only declare timeslicing if we can safely preempt userspace.

Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson 
Cc: Kenneth Graunke 
---
 drivers/gpu/drm/i915/gt/intel_engine.h  | 3 ++-
 drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +
 include/uapi/drm/i915_drm.h | 1 +
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h 
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b469de0dd9b6..424672ee7874 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -339,7 +339,8 @@ intel_engine_has_timeslices(const struct intel_engine_cs 
*engine)
if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
return false;
 
-   return intel_engine_has_semaphores(engine);
+   return (intel_engine_has_semaphores(engine) &&
+   intel_engine_has_preemption(engine));
 }
 
 #endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 848decee9066..b84fdd722781 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -121,6 +121,11 @@ static void set_scheduler_caps(struct drm_i915_private 
*i915)
else
disabled |= BIT(map[i].sched);
}
+
+   if (intel_engine_has_timeslices(engine))
+   enabled |= I915_SCHEDULER_CAP_TIMESLICING;
+   else
+   disabled |= I915_SCHEDULER_CAP_TIMESLICING;
}
 
i915->caps.scheduler = enabled & ~disabled;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 26b17f7772c0..ca5f026ca9ea 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -523,6 +523,7 @@ typedef struct drm_i915_irq_wait {
 #define   I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
 #define   I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
 #define   I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+#define   I915_SCHEDULER_CAP_TIMESLICING   (1ul << 5)
 
 #define I915_PARAM_HUC_STATUS   42
 
-- 
2.20.1

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[Intel-gfx] [PATCH 09/12] drm/i915/gem: Teach execbuf how to wait on future syncobj

2020-03-26 Thread Chris Wilson
If a syncobj has not yet been assigned, treat it as a future fence and
install and wait upon a dma-fence-proxy. The proxy will be replace by
the real fence later, and that fence will be responsible for signaling
our waiter.

Signed-off-by: Chris Wilson 
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21 +--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index c643eec4dca0..759b4102e03b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -2298,8 +2299,24 @@ await_fence_array(struct i915_execbuffer *eb,
continue;
 
fence = drm_syncobj_fence_get(syncobj);
-   if (!fence)
-   return -EINVAL;
+   if (!fence) {
+   struct dma_fence *old;
+
+   fence = dma_fence_create_proxy();
+   if (!fence)
+   return -ENOMEM;
+
+   spin_lock(>lock);
+   old = rcu_dereference_protected(syncobj->fence, true);
+   if (unlikely(old)) {
+   dma_fence_put(fence);
+   fence = dma_fence_get(old);
+   } else {
+   rcu_assign_pointer(syncobj->fence,
+  dma_fence_get(fence));
+   }
+   spin_unlock(>lock);
+   }
 
err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
-- 
2.20.1

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[Intel-gfx] [PATCH 07/12] dma-buf: Proxy fence, an unsignaled fence placeholder

2020-03-26 Thread Chris Wilson
Often we need to create a fence for a future event that has not yet been
associated with a fence. We can store a proxy fence, a placeholder, in
the timeline and replace it later when the real fence is known. Any
listeners that attach to the proxy fence will automatically be signaled
when the real fence completes, and any future listeners will instead be
attach directly to the real fence avoiding any indirection overhead.

Signed-off-by: Chris Wilson 
Cc: Lionel Landwerlin 
---
 drivers/dma-buf/Makefile |  13 +-
 drivers/dma-buf/dma-fence-private.h  |  20 +
 drivers/dma-buf/dma-fence-proxy.c| 189 +
 drivers/dma-buf/dma-fence.c  |   4 +-
 drivers/dma-buf/selftests.h  |   1 +
 drivers/dma-buf/st-dma-fence-proxy.c | 581 +++
 include/linux/dma-fence-proxy.h  |  20 +
 7 files changed, 824 insertions(+), 4 deletions(-)
 create mode 100644 drivers/dma-buf/dma-fence-private.h
 create mode 100644 drivers/dma-buf/dma-fence-proxy.c
 create mode 100644 drivers/dma-buf/st-dma-fence-proxy.c
 create mode 100644 include/linux/dma-fence-proxy.h

diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 995e05f609ff..afaf6dadd9a3 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -1,6 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
-dma-resv.o seqno-fence.o
+obj-y := \
+   dma-buf.o \
+   dma-fence.o \
+   dma-fence-array.o \
+   dma-fence-chain.o \
+   dma-fence-proxy.o \
+   dma-resv.o \
+   seqno-fence.o
 obj-$(CONFIG_DMABUF_HEAPS) += dma-heap.o
 obj-$(CONFIG_DMABUF_HEAPS) += heaps/
 obj-$(CONFIG_SYNC_FILE)+= sync_file.o
@@ -10,6 +16,7 @@ obj-$(CONFIG_UDMABUF) += udmabuf.o
 dmabuf_selftests-y := \
selftest.o \
st-dma-fence.o \
-   st-dma-fence-chain.o
+   st-dma-fence-chain.o \
+   st-dma-fence-proxy.o
 
 obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o
diff --git a/drivers/dma-buf/dma-fence-private.h 
b/drivers/dma-buf/dma-fence-private.h
new file mode 100644
index ..6924d28af0fa
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-private.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Fence mechanism for dma-buf and to allow for asynchronous dma access
+ *
+ * Copyright (C) 2012 Canonical Ltd
+ * Copyright (C) 2012 Texas Instruments
+ *
+ * Authors:
+ * Rob Clark 
+ * Maarten Lankhorst 
+ */
+
+#ifndef DMA_FENCE_PRIVATE_H
+#define DMA_FENCE_PRIAVTE_H
+
+struct dma_fence;
+
+bool __dma_fence_enable_signaling(struct dma_fence *fence);
+
+#endif /* DMA_FENCE_PRIAVTE_H */
diff --git a/drivers/dma-buf/dma-fence-proxy.c 
b/drivers/dma-buf/dma-fence-proxy.c
new file mode 100644
index ..6dce543d0757
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-proxy.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dma-fence-proxy: placeholder unsignaled fence
+ *
+ * Copyright (C) 2017-2019 Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "dma-fence-private.h"
+
+struct dma_fence_proxy {
+   struct dma_fence base;
+   spinlock_t lock;
+
+   struct dma_fence *real;
+   struct dma_fence_cb cb;
+   struct irq_work work;
+};
+
+static const char *proxy_get_driver_name(struct dma_fence *fence)
+{
+   struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+   struct dma_fence *real = READ_ONCE(p->real);
+
+   return real ? real->ops->get_driver_name(real) : "proxy";
+}
+
+static const char *proxy_get_timeline_name(struct dma_fence *fence)
+{
+   struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+   struct dma_fence *real = READ_ONCE(p->real);
+
+   return real ? real->ops->get_timeline_name(real) : "unset";
+}
+
+static void proxy_irq_work(struct irq_work *work)
+{
+   struct dma_fence_proxy *p = container_of(work, typeof(*p), work);
+
+   dma_fence_signal(>base);
+   dma_fence_put(>base);
+}
+
+static void proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb)
+{
+   struct dma_fence_proxy *p = container_of(cb, typeof(*p), cb);
+
+   if (real->error)
+   dma_fence_set_error(>base, real->error);
+
+   /* Lower the height of the proxy chain -> single stack frame */
+   irq_work_queue(>work);
+}
+
+static bool proxy_enable_signaling(struct dma_fence *fence)
+{
+   struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+   struct dma_fence *real = READ_ONCE(p->real);
+   bool ret = true;
+
+   if (real) {
+   spin_lock_nested(real->lock, SINGLE_DEPTH_NESTING);
+   ret = __dma_fence_enable_signaling(real);
+   spin_unlock(real->lock);
+   }
+
+   return ret;
+}
+
+static void proxy_release(struct dma_fence *fence)
+{
+   struct dma_fence_proxy *p = container_of(fence, typeof(*p), 

[Intel-gfx] [PATCH 10/12] drm/i915/gem: Allow combining submit-fences with syncobj

2020-03-26 Thread Chris Wilson
Fixes: a88b6e4cbafd ("drm/i915: Allow specification of parallel execbuf")
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +++---
 include/uapi/drm/i915_drm.h|  7 ---
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 759b4102e03b..48c4928ea8ec 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2263,7 +2263,7 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args,
BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
 
-   fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
+   fences[n] = ptr_pack_bits(syncobj, fence.flags, 3);
}
 
return fences;
@@ -2294,7 +2294,7 @@ await_fence_array(struct i915_execbuffer *eb,
struct dma_fence *fence;
unsigned int flags;
 
-   syncobj = ptr_unpack_bits(fences[n], , 2);
+   syncobj = ptr_unpack_bits(fences[n], , 3);
if (!(flags & I915_EXEC_FENCE_WAIT))
continue;
 
@@ -2318,7 +2318,11 @@ await_fence_array(struct i915_execbuffer *eb,
spin_unlock(>lock);
}
 
-   err = i915_request_await_dma_fence(eb->request, fence);
+   if (flags & I915_EXEC_FENCE_WAIT_SUBMIT)
+   err = i915_request_await_execution(eb->request, fence,
+  
eb->engine->bond_execute);
+   else
+   err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
if (err < 0)
return err;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index db649d03ab52..26b17f7772c0 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1040,9 +1040,10 @@ struct drm_i915_gem_exec_fence {
 */
__u32 handle;
 
-#define I915_EXEC_FENCE_WAIT(1<<0)
-#define I915_EXEC_FENCE_SIGNAL  (1<<1)
-#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
+#define I915_EXEC_FENCE_WAIT(1u << 0)
+#define I915_EXEC_FENCE_SIGNAL  (1u << 1)
+#define I915_EXEC_FENCE_WAIT_SUBMIT (1u << 2)
+#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_WAIT_SUBMIT << 1))
__u32 flags;
 };
 
-- 
2.20.1

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[Intel-gfx] [PATCH 01/12] drm/i915/selftests: Add request throughput measurement to perf

2020-03-26 Thread Chris Wilson
Under ideal circumstances, the driver should be able to keep the GPU
fully saturated with work. Measure how close to ideal we get under the
harshest of conditions with no user payload.

v2: Also measure throughput using only one thread.

Signed-off-by: Chris Wilson 
---
 .../drm/i915/selftests/i915_perf_selftests.h  |   1 +
 drivers/gpu/drm/i915/selftests/i915_request.c | 590 +-
 2 files changed, 590 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h 
b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index 3bf7f53e9924..d8da142985eb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -16,5 +16,6 @@
  * Tests are executed in order by igt/i915_selftest
  */
 selftest(engine_cs, intel_engine_cs_perf_selftests)
+selftest(request, i915_request_perf_selftests)
 selftest(blt, i915_gem_object_blt_perf_selftests)
 selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c 
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 1dab0360f76a..3cf0599cec4b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -23,6 +23,7 @@
  */
 
 #include 
+#include 
 
 #include "gem/i915_gem_pm.h"
 #include "gem/selftests/mock_context.h"
@@ -1239,7 +1240,7 @@ static int live_parallel_engines(void *arg)
struct igt_live_test t;
unsigned int idx;
 
-   snprintf(name, sizeof(name), "%ps", fn);
+   snprintf(name, sizeof(name), "%ps", *fn);
err = igt_live_test_begin(, i915, __func__, name);
if (err)
break;
@@ -1476,3 +1477,590 @@ int i915_request_live_selftests(struct drm_i915_private 
*i915)
 
return i915_subtests(tests, i915);
 }
+
+static int switch_to_kernel_sync(struct intel_context *ce, int err)
+{
+   struct i915_request *rq;
+   struct dma_fence *fence;
+
+   rq = intel_engine_create_kernel_request(ce->engine);
+   if (IS_ERR(rq))
+   return PTR_ERR(rq);
+
+   fence = i915_active_fence_get(>timeline->last_request);
+   if (fence) {
+   i915_request_await_dma_fence(rq, fence);
+   dma_fence_put(fence);
+   }
+
+   rq = i915_request_get(rq);
+   i915_request_add(rq);
+   if (i915_request_wait(rq, 0, HZ / 2) < 0 && !err)
+   err = -ETIME;
+   i915_request_put(rq);
+
+   while (!err && !intel_engine_is_idle(ce->engine))
+   intel_engine_flush_submission(ce->engine);
+
+   return err;
+}
+
+struct perf_stats {
+   struct intel_engine_cs *engine;
+   unsigned long count;
+   ktime_t time;
+   ktime_t busy;
+   u64 runtime;
+};
+
+struct perf_series {
+   struct drm_i915_private *i915;
+   unsigned int nengines;
+   struct intel_context *ce[];
+};
+
+static int s_sync0(void *arg)
+{
+   struct perf_series *ps = arg;
+   IGT_TIMEOUT(end_time);
+   unsigned int idx = 0;
+   int err = 0;
+
+   GEM_BUG_ON(!ps->nengines);
+   do {
+   struct i915_request *rq;
+
+   rq = i915_request_create(ps->ce[idx]);
+   if (IS_ERR(rq)) {
+   err = PTR_ERR(rq);
+   break;
+   }
+
+   i915_request_get(rq);
+   i915_request_add(rq);
+
+   if (i915_request_wait(rq, 0, HZ / 5) < 0)
+   err = -ETIME;
+   i915_request_put(rq);
+   if (err)
+   break;
+
+   if (++idx == ps->nengines)
+   idx = 0;
+   } while (!__igt_timeout(end_time, NULL));
+
+   return err;
+}
+
+static int s_sync1(void *arg)
+{
+   struct perf_series *ps = arg;
+   struct i915_request *prev = NULL;
+   IGT_TIMEOUT(end_time);
+   unsigned int idx = 0;
+   int err = 0;
+
+   GEM_BUG_ON(!ps->nengines);
+   do {
+   struct i915_request *rq;
+
+   rq = i915_request_create(ps->ce[idx]);
+   if (IS_ERR(rq)) {
+   err = PTR_ERR(rq);
+   break;
+   }
+
+   i915_request_get(rq);
+   i915_request_add(rq);
+
+   if (prev && i915_request_wait(prev, 0, HZ / 5) < 0)
+   err = -ETIME;
+   i915_request_put(prev);
+   prev = rq;
+   if (err)
+   break;
+
+   if (++idx == ps->nengines)
+   idx = 0;
+   } while (!__igt_timeout(end_time, NULL));
+   i915_request_put(prev);
+
+   return err;
+}
+
+static int s_many(void *arg)
+{
+   struct perf_series *ps = arg;
+   IGT_TIMEOUT(end_time);
+   unsigned int idx = 0;
+
+   GEM_BUG_ON(!ps->nengines);
+   do {
+   

[Intel-gfx] [PATCH 05/12] dma-buf: Report signaled links inside dma-fence-chain

2020-03-26 Thread Chris Wilson
Whenever we walk along the dma-fence-chain, we prune signaled links to
keep the chain nice and tidy. This leads to situations where we can
prune a link and report the earlier fence as the target seqno --
violating our own consistency checks that the seqno is not more advanced
than the last element in a dma-fence-chain.

Report a NULL fence and success if the seqno has already been signaled.

Signed-off-by: Chris Wilson 
---
 drivers/dma-buf/dma-fence-chain.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/dma-buf/dma-fence-chain.c 
b/drivers/dma-buf/dma-fence-chain.c
index 3d123502ff12..c435bbba851c 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -99,6 +99,12 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence, 
uint64_t seqno)
return -EINVAL;
 
dma_fence_chain_for_each(*pfence, >base) {
+   if ((*pfence)->seqno < seqno) { /* already signaled */
+   dma_fence_put(*pfence);
+   *pfence = NULL;
+   break;
+   }
+
if ((*pfence)->context != chain->base.context ||
to_dma_fence_chain(*pfence)->prev_seqno < seqno)
break;
@@ -222,6 +228,7 @@ EXPORT_SYMBOL(dma_fence_chain_ops);
  * @chain: the chain node to initialize
  * @prev: the previous fence
  * @fence: the current fence
+ * @seqno: the sequence number (syncpt) of the fence within the chain
  *
  * Initialize a new chain node and either start a new chain or add the node to
  * the existing chain of the previous fence.
-- 
2.20.1

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[Intel-gfx] [PATCH 11/12] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore

2020-03-26 Thread Chris Wilson
If we find ourselves waiting on a MI_SEMAPHORE_WAIT, either within the
user batch or in our own preamble, the engine raises a
GT_WAIT_ON_SEMAPHORE interrupt. We can unmask that interrupt and so
respond to a semaphore wait by yielding the timeslice, if we have
another context to yield to!

The only real complication is that the interrupt is only generated for
the start of the semaphore wait, and is asynchronous to our
process_csb() -- that is, we may not have registered the timeslice before
we see the interrupt. To ensure we don't miss a potential semaphore
blocking forward progress (e.g. selftests/live_timeslice_preempt) we mark
the interrupt and apply it to the next timeslice regardless of whether it
was active at the time.

v2: We use semaphores in preempt-to-busy, within the timeslicing
implementation itself! Ergo, when we do insert a preemption due to an
expired timeslice, the new context may start with the missed semaphore
flagged by the retired context and be yielded, ad infinitum. To avoid
this, read the context id at the time of the semaphore interrupt and
only yield if that context is still active.

Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Kenneth Graunke 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c|  6 +++
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  9 +
 drivers/gpu/drm/i915/gt/intel_gt_irq.c   | 13 ++-
 drivers/gpu/drm/i915/gt/intel_lrc.c  | 40 +---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 5 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dff0bbe9e1a6..6ac8d0022deb 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1291,6 +1291,12 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
 
if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
+   if (HAS_EXECLISTS(dev_priv)) {
+   drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
+  ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
+   drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
+  ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
+   }
drm_printf(m, "\tRING_START: 0x%08x\n",
   ENGINE_READ(engine, RING_START));
drm_printf(m, "\tRING_HEAD:  0x%08x\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..ac283ab5d89c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -156,6 +156,15 @@ struct intel_engine_execlists {
 */
struct i915_priolist default_priolist;
 
+   /**
+* @yield: CCID at the time of the last semaphore-wait interrupt.
+*
+* Instead of leaving a semaphore busy-spinning on an engine, we would
+* like to switch to another ready context, i.e. yielding the semaphore
+* timeslice.
+*/
+   u32 yield;
+
/**
 * @error_interrupt: CS Master EIR
 *
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c 
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f0e7fd95165a..875bd0392ffc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -39,6 +39,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
}
}
 
+   if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+   WRITE_ONCE(engine->execlists.yield,
+  ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
+   if (del_timer(>execlists.timer))
+   tasklet = true;
+   }
+
if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
tasklet = true;
 
@@ -228,7 +235,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
-   GT_CONTEXT_SWITCH_INTERRUPT;
+   GT_CONTEXT_SWITCH_INTERRUPT |
+   GT_WAIT_SEMAPHORE_INTERRUPT;
struct intel_uncore *uncore = gt->uncore;
const u32 dmask = irqs << 16 | irqs;
const u32 smask = irqs << 16;
@@ -366,7 +374,8 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
-   GT_CONTEXT_SWITCH_INTERRUPT;
+   GT_CONTEXT_SWITCH_INTERRUPT |
+   GT_WAIT_SEMAPHORE_INTERRUPT;
const u32 gt_interrupts[] = {
irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 

[Intel-gfx] [PATCH 06/12] dma-buf: Exercise dma-fence-chain under selftests

2020-03-26 Thread Chris Wilson
A few very simple testcases to exercise the dma-fence-chain API.

Signed-off-by: Chris Wilson 
---
 drivers/dma-buf/Makefile |   3 +-
 drivers/dma-buf/selftests.h  |   1 +
 drivers/dma-buf/st-dma-fence-chain.c | 713 +++
 3 files changed, 716 insertions(+), 1 deletion(-)
 create mode 100644 drivers/dma-buf/st-dma-fence-chain.c

diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 9c190026bfab..995e05f609ff 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_UDMABUF)   += udmabuf.o
 
 dmabuf_selftests-y := \
selftest.o \
-   st-dma-fence.o
+   st-dma-fence.o \
+   st-dma-fence-chain.o
 
 obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o
diff --git a/drivers/dma-buf/selftests.h b/drivers/dma-buf/selftests.h
index 5320386f02e5..55918ef9adab 100644
--- a/drivers/dma-buf/selftests.h
+++ b/drivers/dma-buf/selftests.h
@@ -11,3 +11,4 @@
  */
 selftest(sanitycheck, __sanitycheck__) /* keep first (igt selfcheck) */
 selftest(dma_fence, dma_fence)
+selftest(dma_fence_chain, dma_fence_chain)
diff --git a/drivers/dma-buf/st-dma-fence-chain.c 
b/drivers/dma-buf/st-dma-fence-chain.c
new file mode 100644
index ..bd08ba67b03b
--- /dev/null
+++ b/drivers/dma-buf/st-dma-fence-chain.c
@@ -0,0 +1,713 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "selftest.h"
+
+static struct kmem_cache *slab_fences;
+
+static inline struct mock_fence {
+   struct dma_fence base;
+   spinlock_t lock;
+} *to_mock_fence(struct dma_fence *f) {
+   return container_of(f, struct mock_fence, base);
+}
+
+static const char *mock_name(struct dma_fence *f)
+{
+   return "mock";
+}
+
+static void mock_fence_release(struct dma_fence *f)
+{
+   kmem_cache_free(slab_fences, to_mock_fence(f));
+}
+
+static const struct dma_fence_ops mock_ops = {
+   .get_driver_name = mock_name,
+   .get_timeline_name = mock_name,
+   .release = mock_fence_release,
+};
+
+static struct dma_fence *mock_fence(void)
+{
+   struct mock_fence *f;
+
+   f = kmem_cache_alloc(slab_fences, GFP_KERNEL);
+   if (!f)
+   return NULL;
+
+   spin_lock_init(>lock);
+   dma_fence_init(>base, _ops, >lock, 0, 0);
+
+   return >base;
+}
+
+static inline struct mock_chain {
+   struct dma_fence_chain base;
+} *to_mock_chain(struct dma_fence *f) {
+   return container_of(f, struct mock_chain, base.base);
+}
+
+static struct dma_fence *mock_chain(struct dma_fence *prev,
+   struct dma_fence *fence,
+   u64 seqno)
+{
+   struct mock_chain *f;
+
+   f = kmalloc(sizeof(*f), GFP_KERNEL);
+   if (!f)
+   return NULL;
+
+   dma_fence_chain_init(>base,
+dma_fence_get(prev),
+dma_fence_get(fence),
+seqno);
+
+   return >base.base;
+}
+
+static int sanitycheck(void *arg)
+{
+   struct dma_fence *f, *chain;
+   int err = 0;
+
+   f = mock_fence();
+   if (!f)
+   return -ENOMEM;
+
+   chain = mock_chain(NULL, f, 1);
+   if (!chain)
+   err = -ENOMEM;
+
+   dma_fence_signal(f);
+   dma_fence_put(f);
+
+   dma_fence_put(chain);
+
+   return err;
+}
+
+struct fence_chains {
+   unsigned int chain_length;
+   struct dma_fence **fences;
+   struct dma_fence **chains;
+
+   struct dma_fence *tail;
+};
+
+static uint64_t seqno_inc(unsigned int i)
+{
+   return i + 1;
+}
+
+static int fence_chains_init(struct fence_chains *fc, unsigned int count,
+uint64_t (*seqno_fn)(unsigned int))
+{
+   unsigned int i;
+   int err = 0;
+
+   fc->chains = kvmalloc_array(count, sizeof(*fc->chains),
+   GFP_KERNEL | __GFP_ZERO);
+   if (!fc->chains)
+   return -ENOMEM;
+
+   fc->fences = kvmalloc_array(count, sizeof(*fc->fences),
+   GFP_KERNEL | __GFP_ZERO);
+   if (!fc->fences) {
+   err = -ENOMEM;
+   goto err_chains;
+   }
+
+   fc->tail = NULL;
+   for (i = 0; i < count; i++) {
+   fc->fences[i] = mock_fence();
+   if (!fc->fences[i]) {
+   err = -ENOMEM;
+   goto unwind;
+   }
+
+   fc->chains[i] = mock_chain(fc->tail,
+  fc->fences[i],
+  seqno_fn(i));
+   if (!fc->chains[i]) {
+   err = -ENOMEM;
+   goto unwind;
+   }
+
+   fc->tail = fc->chains[i];
+   }
+
+   

[Intel-gfx] [PATCH 02/12] drm/i915: Wrap i915_active in a simple kreffed struct

2020-03-26 Thread Chris Wilson
For conveniences of callers that just want to use an i915_active to
track a wide array of concurrent timelines, wrap the base i915_active
struct inside a kref. This i915_active will self-destruct after use.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_active.c | 53 ++
 drivers/gpu/drm/i915/i915_active.h |  4 +++
 2 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_active.c 
b/drivers/gpu/drm/i915/i915_active.c
index a0d31f7bfb42..2df49d2d114e 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -937,6 +937,59 @@ void i915_active_noop(struct dma_fence *fence, struct 
dma_fence_cb *cb)
active_fence_cb(fence, cb);
 }
 
+struct auto_active {
+   struct i915_active base;
+   struct kref ref;
+};
+
+struct i915_active *i915_active_get(struct i915_active *ref)
+{
+   struct auto_active *aa = container_of(ref, typeof(*aa), base);
+
+   kref_get(>ref);
+   return >base;
+}
+
+static void auto_release(struct kref *ref)
+{
+   struct auto_active *aa = container_of(ref, typeof(*aa), ref);
+
+   i915_active_fini(>base);
+   kfree(aa);
+}
+
+void i915_active_put(struct i915_active *ref)
+{
+   struct auto_active *aa = container_of(ref, typeof(*aa), base);
+
+   kref_put(>ref, auto_release);
+}
+
+static int auto_active(struct i915_active *ref)
+{
+   i915_active_get(ref);
+   return 0;
+}
+
+static void auto_retire(struct i915_active *ref)
+{
+   i915_active_put(ref);
+}
+
+struct i915_active *i915_active_create(void)
+{
+   struct auto_active *aa;
+
+   aa = kmalloc(sizeof(*aa), GFP_KERNEL);
+   if (!aa)
+   return NULL;
+
+   kref_init(>ref);
+   i915_active_init(>base, auto_active, auto_retire);
+
+   return >base;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/i915_active.c"
 #endif
diff --git a/drivers/gpu/drm/i915/i915_active.h 
b/drivers/gpu/drm/i915/i915_active.h
index b3282ae7913c..bffbcf7751a7 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -221,4 +221,8 @@ void i915_request_add_active_barriers(struct i915_request 
*rq);
 void i915_active_print(struct i915_active *ref, struct drm_printer *m);
 void i915_active_unlock_wait(struct i915_active *ref);
 
+struct i915_active *i915_active_create(void);
+struct i915_active *i915_active_get(struct i915_active *ref);
+void i915_active_put(struct i915_active *ref);
+
 #endif /* _I915_ACTIVE_H_ */
-- 
2.20.1

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[Intel-gfx] [PATCH] drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning

2020-03-26 Thread Chris Wilson
Userptr causes lockdep to complain when we are using the aliasing-ppgtt
(and ggtt, but for that it is rightfully so to complain about) in that
when we revoke the userptr we take a mutex which we also use to revoke
the mmaps. However, we only revoke mmaps for GGTT bindings and we never
allow userptr to create a GGTT binding so the warning should be false
and is simply caused by our conflation of the aliasing-ppgtt with the
ggtt. So lets try treating the binding into the aliasing-ppgtt as a
separate lockclass from the ggtt. The downside is that we are
deliberately suppressing lockdep;s ability to warn us of cycles.

Closes: https://gitlab.freedesktop.org/drm/intel/issues/478
---
 drivers/gpu/drm/i915/i915_vma.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 191577a98390..9f4a31cd54ac 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -914,7 +914,8 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 
alignment, u64 flags)
wakeref = intel_runtime_pm_get(>vm->i915->runtime_pm);
 
/* No more allocations allowed once we hold vm->mutex */
-   err = mutex_lock_interruptible(>vm->mutex);
+   err = mutex_lock_interruptible_nested(>vm->mutex,
+ !(flags & PIN_GLOBAL));
if (err)
goto err_fence;
 
@@ -1320,7 +1321,7 @@ int i915_vma_unbind(struct i915_vma *vma)
if (err)
goto out_rpm;
 
-   err = mutex_lock_interruptible(>mutex);
+   err = mutex_lock_interruptible_nested(>vm->mutex, !wakeref);
if (err)
goto out_rpm;
 
-- 
2.20.1

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Re: [Intel-gfx] [v3] drm/i915/display: Fix mode private_flags comparison at atomic_check

2020-03-26 Thread Shankar, Uma


> -Original Message-
> From: Shankar, Uma 
> Sent: Thursday, March 26, 2020 6:21 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Ville Syrjä
> ; Maarten Lankhorst
> ; Kai Vehmanen
> ; Souza; Souza, Jose ;
> Khor, Swee Aun 
> Subject: [v3] drm/i915/display: Fix mode private_flags comparison at 
> atomic_check
> 
> This patch fixes the private_flags of mode to be checked and compared against
> uapi.mode and not from hw.mode. This helps properly trigger modeset at boot if
> desired by driver.
> 
> It helps resolve audio_codec initialization issues if display is connected at 
> boot.
> Initial discussion on this issue has happened on below thread:
> https://patchwork.freedesktop.org/series/74828/
> 
> v2: No functional change. Fixed the Closes tag and added Maarten's RB.
> 
> v3: Added Fixes tag.

Pushed the change to dinq.

Thanks again Ville and Maarten for all your valuable feedback, suggestions
and reviews.

Regards,
Uma Shankar

> Cc: Ville Syrjä 
> Cc: Maarten Lankhorst 
> Cc: Kai Vehmanen 
> Cc: Souza, Jose 
> Fixes: 58d124ea2739 ("drm/i915: Complete crtc hw/uapi split, v6.")
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/1363
> Suggested-by: Ville Syrjä 
> Signed-off-by: Uma Shankar 
> Signed-off-by: SweeAun Khor 
> Reviewed-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index fe55c7c713f1..e630429af2c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device *dev,
>   /* Catch I915_MODE_FLAG_INHERITED */
>   for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>   new_crtc_state, i) {
> - if (new_crtc_state->hw.mode.private_flags !=
> - old_crtc_state->hw.mode.private_flags)
> + if (new_crtc_state->uapi.mode.private_flags !=
> + old_crtc_state->uapi.mode.private_flags)
>   new_crtc_state->uapi.mode_changed = true;
>   }
> 
> --
> 2.22.0

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[Intel-gfx] [PULL] drm-misc-fixes

2020-03-26 Thread Maarten Lankhorst
drm-misc-fixes-2020-03-26:
drm-misc-fixes for v5.6:
- SG fixes for prime, radeon and amdgpu.
The following changes since commit b216a8e7908cd750550c0480cf7d2b3a37f06954:

  drm/lease: fix WARNING in idr_destroy (2020-03-18 14:42:18 +0100)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2020-03-26

for you to fetch changes up to 47f7826c520ecd92ffbffe59ecaa2fe61e42ec70:

  drm/radeon: fix scatter-gather mapping with user pages (2020-03-25 12:10:55 
-0400)


drm-misc-fixes for v5.6:
- SG fixes for prime, radeon and amdgpu.


Shane Francis (3):
  drm/prime: use dma length macro when mapping sg
  drm/amdgpu: fix scatter-gather mapping with user pages
  drm/radeon: fix scatter-gather mapping with user pages

 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
 drivers/gpu/drm/drm_prime.c | 2 +-
 drivers/gpu/drm/radeon/radeon_ttm.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)
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[Intel-gfx] [PATCH v3 2/3] drm/i915: Add i915_lpsp_info debugfs

2020-03-26 Thread Anshuman Gupta
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_info, it exposes whether an output is
capable of driving lpsp and exposes lpsp enablement info.

v2:
- CI fixup.
v3:
- register i915_lpsp_info only for supported connector. [Jani]
- use intel_display_power_well_is_enabled() instead of looking
  inside power_well count. [Jani]
- fixes the lpsp capable conditional logic. [Jani]
- combined the lpsp capable and enable info. [Jani]

Signed-off-by: Anshuman Gupta 
---
 .../drm/i915/display/intel_display_debugfs.c  | 121 ++
 .../drm/i915/display/intel_display_power.h|   2 +
 2 files changed, 123 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 424f4e52f783..8a5f5804140e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -9,6 +9,7 @@
 #include "i915_debugfs.h"
 #include "intel_csr.h"
 #include "intel_display_debugfs.h"
+#include "intel_display_power.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_fbc.h"
@@ -611,6 +612,98 @@ static void intel_hdcp_info(struct seq_file *m,
seq_puts(m, "\n");
 }
 
+#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP capable\n") : seq_puts(m, 
"LPSP incapable\n"))
+#define LPSP_ENABLE(COND) (COND ? seq_puts(m, "LPSP enabled\n") : seq_puts(m, 
"LPSP disabled\n"))
+
+/* LVDS also an embedded panel but we are not interested in it */
+static bool intel_have_embedded_panel(struct drm_connector *connector)
+{
+   return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
+   connector->connector_type == DRM_MODE_CONNECTOR_eDP;
+}
+
+static bool intel_have_gen9_lpsp_panel(struct drm_connector *connector)
+{
+   return intel_have_embedded_panel(connector) ||
+   connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort;
+}
+
+static bool intel_have_lpsp_supported_panel(struct drm_connector *connector)
+{
+   return intel_have_gen9_lpsp_panel(connector) ||
+   connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
+   connector->connector_type == DRM_MODE_CONNECTOR_HDMIB;
+}
+
+static bool
+intel_lpsp_power_well_enabled(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id)
+{
+   intel_wakeref_t wakeref;
+   bool is_enabled;
+
+   wakeref = intel_runtime_pm_get(_priv->runtime_pm);
+   is_enabled = intel_display_power_well_is_enabled(dev_priv,
+power_well_id);
+   intel_runtime_pm_put(_priv->runtime_pm, wakeref);
+
+   return is_enabled;
+}
+
+static void
+intel_lpsp_gen12_helper(struct seq_file *m, struct drm_connector *connector)
+{
+   struct intel_encoder *encoder =
+   intel_attached_encoder(to_intel_connector(connector));
+   struct drm_i915_private *dev_priv = to_i915(connector->dev);
+   bool lpsp_capable = false;
+
+   if (IS_TIGERLAKE(dev_priv))
+   lpsp_capable = encoder->port <= PORT_C ? true : false;
+
+   LPSP_CAPABLE(lpsp_capable);
+   LPSP_ENABLE(!intel_lpsp_power_well_enabled(dev_priv, ICL_DISP_PW_3));
+}
+
+static void
+intel_lpsp_gen11_helper(struct seq_file *m, struct drm_connector *connector)
+{
+   struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+   LPSP_CAPABLE(intel_have_embedded_panel(connector));
+   LPSP_ENABLE(!intel_lpsp_power_well_enabled(dev_priv, ICL_DISP_PW_3));
+}
+
+static void
+intel_lpsp_gen9_helper(struct seq_file *m, struct drm_connector *connector)
+{
+   struct intel_encoder *encoder =
+   intel_attached_encoder(to_intel_connector(connector));
+   struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+   LPSP_CAPABLE(encoder->port == PORT_A &&
+intel_have_gen9_lpsp_panel(connector));
+   LPSP_ENABLE(!intel_lpsp_power_well_enabled(dev_priv, SKL_DISP_PW_2));
+}
+
+static void
+intel_lpsp_legacy_gen_helper(struct seq_file *m,
+struct drm_connector *connector)
+{
+   struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+   /*
+* Apart from HASWELL/BROADWELL other legacy platform doesn't
+* support lpsp.
+*/
+   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+   LPSP_CAPABLE(connector->connector_type == 
DRM_MODE_CONNECTOR_eDP);
+   LPSP_ENABLE(!intel_lpsp_power_well_enabled(dev_priv, 
HSW_DISP_PW_GLOBAL));
+   } else {
+   seq_puts(m, "LPSP not supported\n");
+   }
+}
+
 static void intel_dp_info(struct seq_file *m,
  struct intel_connector *intel_connector)
 {
@@ -1987,6 +2080,30 @@ static int i915_hdcp_sink_capability_show(struct 
seq_file *m, void *data)
 }
 

[Intel-gfx] [PATCH v3 3/3] drm/i915: Add connector dbgfs for all connectors

2020-03-26 Thread Anshuman Gupta
Add connector debugfs attributes for each intel
connector which is getting register.

v2:
- adding connector debugfs for each connector in
  intel_connector_register() to fix CI failure for legacy connectors.

Reviewed-by: Jani Nikula 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/display/intel_connector.c | 3 +++
 drivers/gpu/drm/i915/display/intel_dp.c| 3 ---
 drivers/gpu/drm/i915/display/intel_hdmi.c  | 3 ---
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
b/drivers/gpu/drm/i915/display/intel_connector.c
index 98ec2ea86c7c..406e96785c76 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -33,6 +33,7 @@
 
 #include "i915_drv.h"
 #include "intel_connector.h"
+#include "intel_display_debugfs.h"
 #include "intel_display_types.h"
 #include "intel_hdcp.h"
 
@@ -123,6 +124,8 @@ int intel_connector_register(struct drm_connector 
*connector)
goto err_backlight;
}
 
+   intel_connector_debugfs_add(connector);
+
return 0;
 
 err_backlight:
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7f1a4e55cda1..c4352d013c29 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -48,7 +48,6 @@
 #include "intel_audio.h"
 #include "intel_connector.h"
 #include "intel_ddi.h"
-#include "intel_display_debugfs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
@@ -6204,8 +6203,6 @@ intel_dp_connector_register(struct drm_connector 
*connector)
if (ret)
return ret;
 
-   intel_connector_debugfs_add(connector);
-
DRM_DEBUG_KMS("registering %s bus for %s\n",
  intel_dp->aux.name, connector->kdev->kobj.name);
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0076abc63851..1f28153babbf 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -44,7 +44,6 @@
 #include "intel_audio.h"
 #include "intel_connector.h"
 #include "intel_ddi.h"
-#include "intel_display_debugfs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dpio_phy.h"
@@ -2860,8 +2859,6 @@ intel_hdmi_connector_register(struct drm_connector 
*connector)
if (ret)
return ret;
 
-   intel_connector_debugfs_add(connector);
-
intel_hdmi_create_i2c_symlink(connector);
 
return ret;
-- 
2.25.2

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[Intel-gfx] [PATCH v3 1/3] drm/i915: Power well id for ICL PG3

2020-03-26 Thread Anshuman Gupta
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.

Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_display_power.h | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 433e5a81dd4d..3672c00be94a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -943,7 +943,7 @@ static void assert_can_enable_dc5(struct drm_i915_private 
*dev_priv)
 
/* Power wells at this level and above must be disabled for DC5 entry */
if (INTEL_GEN(dev_priv) >= 12)
-   high_pg = TGL_DISP_PW_3;
+   high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
 
@@ -3571,7 +3571,7 @@ static const struct i915_power_well_desc 
icl_power_wells[] = {
.name = "power well 3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = _power_well_ops,
-   .id = DISP_PW_ID_NONE,
+   .id = ICL_DISP_PW_3,
{
.hsw.regs = _power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -3949,7 +3949,7 @@ static const struct i915_power_well_desc 
tgl_power_wells[] = {
.name = "power well 3",
.domains = TGL_PW_3_POWER_DOMAINS,
.ops = _power_well_ops,
-   .id = TGL_DISP_PW_3,
+   .id = ICL_DISP_PW_3,
{
.hsw.regs = _power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h 
b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..56cbae6327b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,7 +100,7 @@ enum i915_power_well_id {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
-   TGL_DISP_PW_3,
+   ICL_DISP_PW_3,
SKL_DISP_DC_OFF,
 };
 
-- 
2.25.2

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[Intel-gfx] [PATCH v3 0/3] i915 lpsp support for lpsp igt

2020-03-26 Thread Anshuman Gupta
This series adds i915_lpsp_info connector debugfs.
v3 has fixed some review comments on patch (2/3)
and added RB tag on patch (3/3).

Test-with: 20200326131929.23072-1-anshuman.gu...@intel.com

Anshuman Gupta (3):
  drm/i915: Power well id for ICL PG3
  drm/i915: Add i915_lpsp_info debugfs
  drm/i915: Add connector dbgfs for all connectors

 .../gpu/drm/i915/display/intel_connector.c|   3 +
 .../drm/i915/display/intel_display_debugfs.c  | 121 ++
 .../drm/i915/display/intel_display_power.c|   6 +-
 .../drm/i915/display/intel_display_power.h|   4 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |   3 -
 drivers/gpu/drm/i915/display/intel_hdmi.c |   3 -
 6 files changed, 130 insertions(+), 10 deletions(-)

-- 
2.25.2

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Re: [Intel-gfx] [PATCH 01/51] mm/sl[uo]b: export __kmalloc_track(_node)_caller

2020-03-26 Thread Daniel Vetter
On Mon, Mar 23, 2020 at 03:49:00PM +0100, Daniel Vetter wrote:
> slab does this already, and I want to use this in a memory allocation
> tracker in drm for stuff that's tied to the lifetime of a drm_device,
> not the underlying struct device. Kinda like devres, but for drm.
> 
> Acked-by: Andrew Morton 
> Signed-off-by: Daniel Vetter 
> Cc: Christoph Lameter 
> Cc: Pekka Enberg 
> Cc: David Rientjes 
> Cc: Joonsoo Kim 
> Cc: Andrew Morton 
> Cc: linux...@kvack.org
> --
> I plan to merge this through drm-misc-next (with Andrew's ack) once
> the remainder of the drm series is in shape.

Ok I pulled this in now, but it's going to miss the 5.7 merge window, so
queued for 5.8. Should show up in linux-next right after -rc1.
-Daniel

> -Daniel
> ---
>  mm/slob.c | 2 ++
>  mm/slub.c | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/mm/slob.c b/mm/slob.c
> index fa53e9f73893..ac2aecfbc7a8 100644
> --- a/mm/slob.c
> +++ b/mm/slob.c
> @@ -524,6 +524,7 @@ void *__kmalloc_track_caller(size_t size, gfp_t gfp, 
> unsigned long caller)
>  {
>   return __do_kmalloc_node(size, gfp, NUMA_NO_NODE, caller);
>  }
> +EXPORT_SYMBOL(__kmalloc_track_caller);
>  
>  #ifdef CONFIG_NUMA
>  void *__kmalloc_node_track_caller(size_t size, gfp_t gfp,
> @@ -531,6 +532,7 @@ void *__kmalloc_node_track_caller(size_t size, gfp_t gfp,
>  {
>   return __do_kmalloc_node(size, gfp, node, caller);
>  }
> +EXPORT_SYMBOL(__kmalloc_node_track_caller);
>  #endif
>  
>  void kfree(const void *block)
> diff --git a/mm/slub.c b/mm/slub.c
> index 2988dae3f692..a937de5182cc 100644
> --- a/mm/slub.c
> +++ b/mm/slub.c
> @@ -4377,6 +4377,7 @@ void *__kmalloc_track_caller(size_t size, gfp_t 
> gfpflags, unsigned long caller)
>  
>   return ret;
>  }
> +EXPORT_SYMBOL(__kmalloc_track_caller);
>  
>  #ifdef CONFIG_NUMA
>  void *__kmalloc_node_track_caller(size_t size, gfp_t gfpflags,
> @@ -4407,6 +4408,7 @@ void *__kmalloc_node_track_caller(size_t size, gfp_t 
> gfpflags,
>  
>   return ret;
>  }
> +EXPORT_SYMBOL(__kmalloc_node_track_caller);
>  #endif
>  
>  #ifdef CONFIG_SYSFS
> -- 
> 2.25.1
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 08/51] drm/i915: Use drmm_add_final_kfree

2020-03-26 Thread Daniel Vetter
On Thu, Mar 26, 2020 at 2:11 PM Jani Nikula  wrote:
>
> On Mon, 23 Mar 2020, Daniel Vetter  wrote:
> > With this we can drop the final kfree from the release function.
> >
> > The mock device in the selftests needed it's pci_device split
> > up from the drm_device. In the future we could simplify this again
> > by allocating the pci_device as a managed allocation too.
> >
> > v2: I overlooked that i915_driver_destroy is also called in the
> > unwind code of the error path. There we need a drm_dev_put.
> > Similar for the mock object.
> >
> > Now the problem with that is that the drm_driver->release callbacks
> > for both the real driver and the mock one assume everything has been
> > set up. Hence going through that path for a partially set up driver
> > will result in issues. Quickest fix is to disable the ->release() hook
> > until the driver is fully initialized, and keep the onion unwinding.
> > Long term would be cleanest to move everything over to drmm_ release
> > actions, but that's a lot of work for a big driver like i915. Plus
> > more core work needed first anyway.
> >
> > v3: Fix i915_drm pointer wrangling in mock_gem_device. Also switch
> > over to start using drm_dev_put() to clean up even on the error path.
> > Aside I think the current error path is leaking the allocation.
> >
> > v4: more fixes for intel-gfx-ci, some if it damage from v3 :-/
> >
> > Signed-off-by: Daniel Vetter 
> > Cc: Jani Nikula 
> > Cc: Joonas Lahtinen 
> > Cc: Rodrigo Vivi 
> > Cc: Chris Wilson 
> > Cc: Tvrtko Ursulin 
> > Cc: Matthew Auld 
> > Cc: Andi Shyti 
> > Cc: Mika Kuoppala 
> > Cc: Daniele Ceraolo Spurio 
> > Cc: Daniel Vetter 
> > Cc: Abdiel Janulgue 
> > Cc: intel-gfx@lists.freedesktop.org
>
> Okay, I didn't find any holes in this, and while I wish I had more
> confidence I checked all the corner cases, this is
>
> Reviewed-by: Jani Nikula 
>
> A couple of notes below, don't have to do anything about them. (Maybe
> better *not* to do anything about them, to move this forward. ;)
>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c   | 10 ++-
> >  drivers/gpu/drm/i915/i915_drv.h   |  3 ++
> >  .../gpu/drm/i915/selftests/mock_gem_device.c  | 30 ++-
> >  3 files changed, 35 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 4792051e9e2e..481313536b5a 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -43,6 +43,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >
> >  #include "display/intel_acpi.h"
> > @@ -890,6 +891,8 @@ i915_driver_create(struct pci_dev *pdev, const struct 
> > pci_device_id *ent)
> >   return ERR_PTR(err);
> >   }
> >
> > + drmm_add_final_kfree(>drm, i915);
> > +
> >   i915->drm.pdev = pdev;
> >   pci_set_drvdata(pdev, i915);
> >
> > @@ -908,7 +911,6 @@ static void i915_driver_destroy(struct drm_i915_private 
> > *i915)
> >   struct pci_dev *pdev = i915->drm.pdev;
> >
> >   drm_dev_fini(>drm);
> > - kfree(i915);
> >  }
> >
> >  /**
> > @@ -992,6 +994,8 @@ int i915_driver_probe(struct pci_dev *pdev, const 
> > struct pci_device_id *ent)
> >
> >   i915_welcome_messages(i915);
> >
> > + i915->do_release = true;
> > +
>
> This whole ->do_release thing is obviously a bummer. I did wonder if we
> could set driver->release to NULL initially, and set it to the proper
> thing here. It would make drm_dev_put() handle drm_dev_fini() internally
> too.
>
> Less obvious? I don't know.

Yeah it's not pretty, but I figured I'll go with obvious ugly than too
clever for my own ugly. The trouble is that i915 is the only big
driver bothers to correctly unwind everything in ->release, hence it's
the one driver that really suffers through the valley of ugly here.
All the others are more or less just terminally broken wrt lifetimes,
so only get better. Or so simple (like the drivers I already fully
clean up with this series) that I can get through the valley of ugly
in one small series of 50 patches for all of them.

> >   return 0;
> >
> >  out_cleanup_irq:
> > @@ -1012,6 +1016,7 @@ int i915_driver_probe(struct pci_dev *pdev, const 
> > struct pci_device_id *ent)
> >  out_fini:
> >   i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
> >   i915_driver_destroy(i915);
> > + drm_dev_put(>drm);
>
> Also wondered about throwing i915_driver_destroy away, and inlining the
> drm_dev_fini()...
>
> >   return ret;
> >  }
> >
> > @@ -1051,6 +1056,9 @@ static void i915_driver_release(struct drm_device 
> > *dev)
> >   struct drm_i915_private *dev_priv = to_i915(dev);
> >   struct intel_runtime_pm *rpm = _priv->runtime_pm;
> >
> > + if (!dev_priv->do_release)
>
> ...or, calling drm_dev_fini() in this branch, avoiding the need to call
> it elsewhere.
>
> *shrug*
>
> All of it can be done afterwards, if deemed useful.

drm_dev_fini() 

Re: [Intel-gfx] [PATCH] drm/i915/display: Return early after MISSING_CSAE for write_dp_sdp

2020-03-26 Thread Jani Nikula
On Wed, 25 Mar 2020, Chris Wilson  wrote:
> Avoid using the uninitialised len along the impossible error path to
> shut the compiler up:
>
> drivers/gpu/drm/i915/display/intel_dp.c:4928 intel_write_dp_sdp() error: 
> uninitialized symbol 'len'.

Why am I not seeing this? GCC 8.3.0

Reviewed-by: Jani Nikula 

Tpyo in the subject.

>
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7f1a4e55cda1..c33a39065704 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4922,7 +4922,7 @@ static void intel_write_dp_sdp(struct intel_encoder 
> *encoder,
>   break;
>   default:
>   MISSING_CASE(type);
> - break;
> + return;
>   }
>  
>   if (drm_WARN_ON(_priv->drm, len < 0))

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Re: [Intel-gfx] [PATCH 02/51] drm/i915: Don't clear drvdata in ->release

2020-03-26 Thread Jani Nikula
On Wed, 25 Mar 2020, Jani Nikula  wrote:
> On Mon, 23 Mar 2020, Daniel Vetter  wrote:
>> For two reasons:
>>
>> - The driver core clears this already for us after we're unloaded in
>>   __device_release_driver().
>>
>> - It's way too late, the drm_device ->release callback might massively
>>   outlive the underlying physical device, since a drm_device can't be
>
> *can be*?
>
>>   kept alive by open drm_file or well really anything else userspace
>>   is still hanging onto. So if we clear this ourselves, we should
>>   clear it in the pci ->remove callback, not in the drm_device
>>   ->relase callback.
>
> ->release
>
> Reviewed-by: Jani Nikula 

Oops,

drivers/gpu/drm/i915/i915_drv.c: In function ‘i915_driver_destroy’:
drivers/gpu/drm/i915/i915_drv.c:911:18: error: unused variable ‘pdev’ 
[-Werror=unused-variable]
  struct pci_dev *pdev = i915->drm.pdev;
  ^~~~



>
>>
>> Looking at git history this was fixed in the driver core with
>>
>> commit 0998d0631001288a5974afc0b2a5f568bcdecb4d
>> Author: Hans de Goede 
>> Date:   Wed May 23 00:09:34 2012 +0200
>>
>> device-core: Ensure drvdata = NULL when no driver is bound
>>
>> v2: Cite the core fix in the commit message (Chris).
>>
>> Cc: Greg Kroah-Hartman 
>> Cc: Chris Wilson 
>> Signed-off-by: Daniel Vetter 
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c | 3 ---
>>  1 file changed, 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 48ba37e35bea..4792051e9e2e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -909,9 +909,6 @@ static void i915_driver_destroy(struct drm_i915_private 
>> *i915)
>>  
>>  drm_dev_fini(>drm);
>>  kfree(i915);
>> -
>> -/* And make sure we never chase our dangling pointer from pci_dev */
>> -pci_set_drvdata(pdev, NULL);
>>  }
>>  
>>  /**

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Re: [Intel-gfx] [PATCH 08/51] drm/i915: Use drmm_add_final_kfree

2020-03-26 Thread Jani Nikula
On Mon, 23 Mar 2020, Daniel Vetter  wrote:
> With this we can drop the final kfree from the release function.
>
> The mock device in the selftests needed it's pci_device split
> up from the drm_device. In the future we could simplify this again
> by allocating the pci_device as a managed allocation too.
>
> v2: I overlooked that i915_driver_destroy is also called in the
> unwind code of the error path. There we need a drm_dev_put.
> Similar for the mock object.
>
> Now the problem with that is that the drm_driver->release callbacks
> for both the real driver and the mock one assume everything has been
> set up. Hence going through that path for a partially set up driver
> will result in issues. Quickest fix is to disable the ->release() hook
> until the driver is fully initialized, and keep the onion unwinding.
> Long term would be cleanest to move everything over to drmm_ release
> actions, but that's a lot of work for a big driver like i915. Plus
> more core work needed first anyway.
>
> v3: Fix i915_drm pointer wrangling in mock_gem_device. Also switch
> over to start using drm_dev_put() to clean up even on the error path.
> Aside I think the current error path is leaking the allocation.
>
> v4: more fixes for intel-gfx-ci, some if it damage from v3 :-/
>
> Signed-off-by: Daniel Vetter 
> Cc: Jani Nikula 
> Cc: Joonas Lahtinen 
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Cc: Tvrtko Ursulin 
> Cc: Matthew Auld 
> Cc: Andi Shyti 
> Cc: Mika Kuoppala 
> Cc: Daniele Ceraolo Spurio 
> Cc: Daniel Vetter 
> Cc: Abdiel Janulgue 
> Cc: intel-gfx@lists.freedesktop.org

Okay, I didn't find any holes in this, and while I wish I had more
confidence I checked all the corner cases, this is

Reviewed-by: Jani Nikula 

A couple of notes below, don't have to do anything about them. (Maybe
better *not* to do anything about them, to move this forward. ;)

> ---
>  drivers/gpu/drm/i915/i915_drv.c   | 10 ++-
>  drivers/gpu/drm/i915/i915_drv.h   |  3 ++
>  .../gpu/drm/i915/selftests/mock_gem_device.c  | 30 ++-
>  3 files changed, 35 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4792051e9e2e..481313536b5a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -43,6 +43,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  #include "display/intel_acpi.h"
> @@ -890,6 +891,8 @@ i915_driver_create(struct pci_dev *pdev, const struct 
> pci_device_id *ent)
>   return ERR_PTR(err);
>   }
>  
> + drmm_add_final_kfree(>drm, i915);
> +
>   i915->drm.pdev = pdev;
>   pci_set_drvdata(pdev, i915);
>  
> @@ -908,7 +911,6 @@ static void i915_driver_destroy(struct drm_i915_private 
> *i915)
>   struct pci_dev *pdev = i915->drm.pdev;
>  
>   drm_dev_fini(>drm);
> - kfree(i915);
>  }
>  
>  /**
> @@ -992,6 +994,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct 
> pci_device_id *ent)
>  
>   i915_welcome_messages(i915);
>  
> + i915->do_release = true;
> +

This whole ->do_release thing is obviously a bummer. I did wonder if we
could set driver->release to NULL initially, and set it to the proper
thing here. It would make drm_dev_put() handle drm_dev_fini() internally
too.

Less obvious? I don't know.

>   return 0;
>  
>  out_cleanup_irq:
> @@ -1012,6 +1016,7 @@ int i915_driver_probe(struct pci_dev *pdev, const 
> struct pci_device_id *ent)
>  out_fini:
>   i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
>   i915_driver_destroy(i915);
> + drm_dev_put(>drm);

Also wondered about throwing i915_driver_destroy away, and inlining the
drm_dev_fini()...

>   return ret;
>  }
>  
> @@ -1051,6 +1056,9 @@ static void i915_driver_release(struct drm_device *dev)
>   struct drm_i915_private *dev_priv = to_i915(dev);
>   struct intel_runtime_pm *rpm = _priv->runtime_pm;
>  
> + if (!dev_priv->do_release)

...or, calling drm_dev_fini() in this branch, avoiding the need to call
it elsewhere.

*shrug*

All of it can be done afterwards, if deemed useful.

> + return;
> +
>   disable_rpm_wakeref_asserts(rpm);
>  
>   i915_gem_driver_release(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a7ea1d855359..7ae652723ed7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -821,6 +821,9 @@ struct i915_selftest_stash {
>  struct drm_i915_private {
>   struct drm_device drm;
>  
> + /* FIXME: Device release actions should all be moved to drmm_ */
> + bool do_release;
> +
>   const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
>   struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
>   struct intel_driver_caps caps;
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c 
> 

Re: [Intel-gfx] [PATCH v2 00/16] x86, crypto: remove always-defined CONFIG_AS_* and cosolidate Kconfig/Makefiles

2020-03-26 Thread Jason A. Donenfeld
Very little has changed from last time, and this whole series still
looks good to me. I think I already ack'd most packages, but in case
it helps:

Reviewed-by: Jason A. Donenfeld 

Since this touches a lot of stuff, it might be best to get it in as
early as possible during the merge window, as I imagine new code being
added is going to want to be touching those makefiles too.
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[Intel-gfx] [PATCH v2 00/16] x86, crypto: remove always-defined CONFIG_AS_* and cosolidate Kconfig/Makefiles

2020-03-26 Thread Masahiro Yamada
This series of cleanups was prompted by Linus:
https://lkml.org/lkml/2020/3/12/726

First, this series drop always-on CONFIG_AS_* options.
Some of those options were introduced in old days.
For example, the check for CONFIG_AS_CFI dates back to 2006.

We raise the minimal tool versions from time to time.
Currently, we require binutils 2.21
(and we even plan to bump it to 2.23).

After cleaning away the old checks,
as-instr calls are moved to Kconfig from Makefiles,
then more Kconfig / Makefile code is cleaned up.

I folded all relevanet patches into this series,
as suggested by Jason A. Donenfeld.

The update for v2 is quite small.
I just swapped the patch order of patch 8 and 11
instead of moving comments around files,
which was addressed by Nick Desaulniers.


Borislav Petkov (1):
  Documentation/changes: Raise minimum supported binutils version to
2.23

Jason A. Donenfeld (4):
  x86: probe assembler capabilities via kconfig instead of makefile
  crypto: x86 - rework configuration based on Kconfig
  crypto: curve25519 - do not pollute dispatcher based on assembler
  x86: update AS_* macros to binutils >=2.23, supporting ADX and AVX2

Masahiro Yamada (11):
  lib/raid6/test: fix build on distros whose /bin/sh is not bash
  x86: remove unneeded defined(__ASSEMBLY__) check from asm/dwarf2.h
  x86: remove always-defined CONFIG_AS_CFI
  x86: remove unneeded (CONFIG_AS_)CFI_SIGNAL_FRAME
  x86: remove always-defined CONFIG_AS_CFI_SECTIONS
  x86: remove always-defined CONFIG_AS_SSSE3
  x86: remove always-defined CONFIG_AS_AVX
  x86: replace arch macros from compiler with CONFIG_X86_{32,64}
  drm/i915: remove always-defined CONFIG_AS_MOVNTDQA
  x86: add comments about the binutils version to support code in
as-instr
  crypto: x86 - clean up poly1305-x86_64-cryptogams.S by 'make clean'

 Documentation/process/changes.rst |   4 +-
 arch/x86/Kconfig  |   2 +
 arch/x86/Kconfig.assembler|  17 ++
 arch/x86/Makefile |  22 ---
 arch/x86/crypto/Makefile  | 162 +++---
 arch/x86/crypto/aesni-intel_avx-x86_64.S  |   6 -
 arch/x86/crypto/aesni-intel_glue.c|  21 +--
 arch/x86/crypto/blake2s-core.S|   2 -
 arch/x86/crypto/chacha_glue.c |   6 +-
 arch/x86/crypto/poly1305-x86_64-cryptogams.pl |  16 --
 arch/x86/crypto/poly1305_glue.c   |  11 +-
 arch/x86/crypto/sha1_ssse3_asm.S  |   4 -
 arch/x86/crypto/sha1_ssse3_glue.c |  13 --
 arch/x86/crypto/sha256-avx-asm.S  |   3 -
 arch/x86/crypto/sha256-avx2-asm.S |   3 -
 arch/x86/crypto/sha256_ssse3_glue.c   |  12 --
 arch/x86/crypto/sha512-avx-asm.S  |   2 -
 arch/x86/crypto/sha512-avx2-asm.S |   3 -
 arch/x86/crypto/sha512_ssse3_glue.c   |  10 --
 arch/x86/include/asm/dwarf2.h |  44 -
 arch/x86/include/asm/xor_avx.h|   9 -
 drivers/gpu/drm/i915/Makefile |   3 -
 drivers/gpu/drm/i915/i915_memcpy.c|   5 -
 include/crypto/curve25519.h   |   6 +-
 kernel/signal.c   |   2 +-
 lib/raid6/algos.c |  12 +-
 lib/raid6/avx2.c  |   4 -
 lib/raid6/recov_avx2.c|   6 -
 lib/raid6/recov_ssse3.c   |   6 -
 lib/raid6/test/Makefile   |   9 +-
 30 files changed, 101 insertions(+), 324 deletions(-)
 create mode 100644 arch/x86/Kconfig.assembler

-- 
2.17.1

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[Intel-gfx] [PATCH v2 09/16] drm/i915: remove always-defined CONFIG_AS_MOVNTDQA

2020-03-26 Thread Masahiro Yamada
CONFIG_AS_MOVNTDQA was introduced by commit 0b1de5d58e19 ("drm/i915:
Use SSE4.1 movntdqa to accelerate reads from WC memory").

We raise the minimal supported binutils version from time to time.
The last bump was commit 1fb12b35e5ff ("kbuild: Raise the minimum
required binutils version to 2.21").

I confirmed the code in $(call as-instr,...) can be assembled by the
binutils 2.21 assembler and also by LLVM integrated assembler.

Remove CONFIG_AS_MOVNTDQA, which is always defined.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Nick Desaulniers 
---

Changes in v2: None

 drivers/gpu/drm/i915/Makefile  | 3 ---
 drivers/gpu/drm/i915/i915_memcpy.c | 5 -
 2 files changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a1f2411aa21b..e559e53fc634 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -28,9 +28,6 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
 CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
 CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
 
-subdir-ccflags-y += \
-   $(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
-
 subdir-ccflags-y += -I$(srctree)/$(src)
 
 # Please keep these build lists sorted!
diff --git a/drivers/gpu/drm/i915/i915_memcpy.c 
b/drivers/gpu/drm/i915/i915_memcpy.c
index fdd550405fd3..7b3b83bd5ab8 100644
--- a/drivers/gpu/drm/i915/i915_memcpy.c
+++ b/drivers/gpu/drm/i915/i915_memcpy.c
@@ -35,7 +35,6 @@
 
 static DEFINE_STATIC_KEY_FALSE(has_movntdqa);
 
-#ifdef CONFIG_AS_MOVNTDQA
 static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len)
 {
kernel_fpu_begin();
@@ -93,10 +92,6 @@ static void __memcpy_ntdqu(void *dst, const void *src, 
unsigned long len)
 
kernel_fpu_end();
 }
-#else
-static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len) {}
-static void __memcpy_ntdqu(void *dst, const void *src, unsigned long len) {}
-#endif
 
 /**
  * i915_memcpy_from_wc: perform an accelerated *aligned* read from WC
-- 
2.17.1

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Re: [Intel-gfx] [v2] drm/i915/display: Fix mode private_flags comparison at atomic_check

2020-03-26 Thread Shankar, Uma


> -Original Message-
> From: Maarten Lankhorst 
> Sent: Thursday, March 26, 2020 5:38 PM
> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjä ; Kai Vehmanen
> ; Souza, Jose ; Khor, Swee
> Aun 
> Subject: Re: [v2] drm/i915/display: Fix mode private_flags comparison at
> atomic_check
> 
> Op 26-03-2020 om 13:24 schreef Uma Shankar:
> > This patch fixes the private_flags of mode to be checked and compared
> > against uapi.mode and not from hw.mode. This helps properly trigger
> > modeset at boot if desired by driver.
> >
> > It helps resolve audio_codec initialization issues if display is
> > connected at boot. Initial discussion on this issue has happened on
> > below thread:
> > https://patchwork.freedesktop.org/series/74828/
> >
> > v2: No functional change. Fixed the Closes tag and added Maarten's RB.
> >
> > Cc: Ville Syrjä 
> > Cc: Maarten Lankhorst 
> > Cc: Kai Vehmanen 
> > Cc: Souza, Jose 
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1363
> > Suggested-by: Ville Syrjä 
> > Signed-off-by: Uma Shankar 
> > Signed-off-by: SweeAun Khor 
> > Reviewed-by: Maarten Lankhorst 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index fe55c7c713f1..e630429af2c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device 
> > *dev,
> > /* Catch I915_MODE_FLAG_INHERITED */
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > -   if (new_crtc_state->hw.mode.private_flags !=
> > -   old_crtc_state->hw.mode.private_flags)
> > +   if (new_crtc_state->uapi.mode.private_flags !=
> > +   old_crtc_state->uapi.mode.private_flags)
> > new_crtc_state->uapi.mode_changed = true;
> > }
> >
> 
> Still missing the fixes tags!

My Bad, updated.


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[Intel-gfx] [v3] drm/i915/display: Fix mode private_flags comparison at atomic_check

2020-03-26 Thread Uma Shankar
This patch fixes the private_flags of mode to be checked and
compared against uapi.mode and not from hw.mode. This helps
properly trigger modeset at boot if desired by driver.

It helps resolve audio_codec initialization issues if display
is connected at boot. Initial discussion on this issue has happened
on below thread:
https://patchwork.freedesktop.org/series/74828/

v2: No functional change. Fixed the Closes tag and added
Maarten's RB.

v3: Added Fixes tag.

Cc: Ville Syrjä 
Cc: Maarten Lankhorst 
Cc: Kai Vehmanen 
Cc: Souza, Jose 
Fixes: 58d124ea2739 ("drm/i915: Complete crtc hw/uapi split, v6.")
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1363
Suggested-by: Ville Syrjä 
Signed-off-by: Uma Shankar 
Signed-off-by: SweeAun Khor 
Reviewed-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index fe55c7c713f1..e630429af2c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device *dev,
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
-   if (new_crtc_state->hw.mode.private_flags !=
-   old_crtc_state->hw.mode.private_flags)
+   if (new_crtc_state->uapi.mode.private_flags !=
+   old_crtc_state->uapi.mode.private_flags)
new_crtc_state->uapi.mode_changed = true;
}
 
-- 
2.22.0

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