Re: [Intel-gfx] [PULL] gvt-next-fixes
On 2020.03.31 09:26:44 -0700, Rodrigo Vivi wrote: > On Tue, Mar 31, 2020 at 03:00:25PM +0800, Zhenyu Wang wrote: > > > > Hi, > > > > Here's more queued gvt fixes for 5.7. Please see details below. > > > > Thanks > > -- > > The following changes since commit a61ac1e75105a077ec1efd6923ae3c619f862304: > > > > drm/i915/gvt: Wean gvt off using dev_priv (2020-03-06 10:08:10 +0800) > > > > are available in the Git repository at: > > > > https://github.com/intel/gvt-linux.git tags/gvt-next-fixes-2020-03-31 > > > > for you to fetch changes up to eb0ff8074e0baecba2cd0c7813f6cfa99bafc430: > > > > drm/i915/gvt: Fix klocwork issues about data size (2020-03-27 15:37:58 > > +0800) > > pulled, thanks I forgot to mention one thing for 5.7. We've fixed to change guest mem r/w from KVM to use new VFIO dma r/w instead in this series: https://patchwork.freedesktop.org/series/72038/ As this depends on VFIO tree and looks VFIO pull for 5.7 is not settled down yet, we'd need to backmerge and send pull against vfio merge for 5.7. thanks > > > > > > > gvt-next-fixes-2020-03-31 > > > > - Fix non-privilege access warning (Tina) > > - Fix display port type (Tina) > > - BDW cmd parser missed SWTESS_BASE_ADDRESS (Yan) > > - Bypass length check of LRI (Yan) > > - Fix one klocwork warning (Tina) > > > > > > Tina Zhang (3): > > drm/i915/gvt: Add some regs to force-to-nonpriv whitelist > > drm/i915/gvt: Fix display port type issue > > drm/i915/gvt: Fix klocwork issues about data size > > > > Yan Zhao (2): > > drm/i915/gvt: add support to command SWTESS_BASE_ADDRESS > > drm/i915/gvt: do not check len & max_len for lri > > > > drivers/gpu/drm/i915/gvt/cmd_parser.c | 16 > > drivers/gpu/drm/i915/gvt/display.c| 6 +++--- > > drivers/gpu/drm/i915/gvt/handlers.c | 8 ++-- > > drivers/gpu/drm/i915/gvt/scheduler.c | 4 ++-- > > 4 files changed, 15 insertions(+), 19 deletions(-) > > > > -- > > Open Source Technology Center, Intel ltd. > > > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 > > > ___ > intel-gvt-dev mailing list > intel-gvt-...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Do not clear pollin for small user read buffers (rev7)
== Series Details == Series: drm/i915/perf: Do not clear pollin for small user read buffers (rev7) URL : https://patchwork.freedesktop.org/series/75085/ State : success == Summary == CI Bug Log - changes from CI_DRM_8242 -> Patchwork_17191 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17191/index.html Changes --- No changes found Participating hosts (47 -> 37) -- Missing(10): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bwr-2160 fi-gdg-551 fi-cfl-8109u fi-kbl-7560u fi-bdw-samus fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8242 -> Patchwork_17191 CI-20190529: 20190529 CI_DRM_8242: 07d20020ec328dc9858680651366425afa51cd59 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5560: 213062c7dcf0cbc8069cbb5f91acbc494def33fd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17191: 474c470267ad8965e4f82037aa367c5c025e88b2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 474c470267ad drm/i915/perf: Do not clear pollin for small user read buffers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17191/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/6] drm/i915/tc/icl: Implement TC cold sequences
Hi Imre
I guess I did all the requested changes but trybot got some
warnings that I will need more time to understand and fix it.
If you have time please check if is this way that you are asking:
https://github.com/zehortigoza/linux/tree/tccold-v3
Trybot warnings:
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_5784/bat-all.html
Thanks
On Thu, 2020-04-02 at 04:02 +0300, Imre Deak wrote:
> On Thu, Apr 02, 2020 at 01:35:30AM +0300, Souza, Jose wrote:
> > On Wed, 2020-04-01 at 15:43 +0300, Imre Deak wrote:
> > > On Tue, Mar 31, 2020 at 05:41:19PM -0700, José Roberto de Souza
> > > wrote:
> > > > This is required for legacy/static TC ports as IOM is not aware
> > > > of
> > > > the connection and will not trigger the TC cold exit.
> > > >
> > > > Just request PCODE to exit TCCOLD is not enough as it could
> > > > enter
> > > > again be driver makes use of the port, to prevent it BSpec
> > > > states
> > > > that
> > > > aux powerwell should be held.
> > > >
> > > > So here embedding the TC cold exit sequence into ICL aux
> > > > enable,
> > > > it will enable aux, request tc cold exit and depending in the
> > > > TC
> > > > live
> > > > state continue with the regular aux enable sequence.
> > > >
> > > > And then turning on aux power well during tc lock and turning
> > > > off
> > > > during unlock both depending into the TC port refcount.
> > > >
> > > > BSpec: 21750
> > > > Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1296
> > > > Cc: Imre Deak
> > > > Cc: Cooper Chiou
> > > > Cc: Kai-Heng Feng
> > > > Signed-off-by: José Roberto de Souza
> > > > ---
> > > >
> > > > Will run some tests in the office with TBT dockstation to check
> > > > if
> > > > it will be a issue keep both aux enabled. Otherwise more
> > > > changes
> > > > will
> > > > be required here.
> > > >
> > > > .../drm/i915/display/intel_display_power.c| 12 -
> > > > .../drm/i915/display/intel_display_types.h| 1 +
> > > > drivers/gpu/drm/i915/display/intel_tc.c | 47
> > > > ++-
> > > > drivers/gpu/drm/i915/display/intel_tc.h | 2 +
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > 5 files changed, 59 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > index dbd61517ba63..1ccd57d645c7 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > @@ -592,9 +592,17 @@ icl_tc_phy_aux_power_well_enable(struct
> > > > drm_i915_private *dev_priv,
> > > >
> > > > _hsw_power_well_enable(dev_priv, power_well);
> > > >
> > > > - /* TODO ICL TC cold handling */
> > > > + if (INTEL_GEN(dev_priv) == 11)
> > >
> > > Should be if (ICL && dig_port->tc_legacy_port)
> >
> > Makes sence.
> > Oh so we could use it on __intel_tc_port_lock() too and
> > don't do this stuff for non legacy ports. Until we get a report of
> > a
> > system with a wrong VBT :P
>
> Yes, it's a loss of the vendor shipping a corrupt VBT. But we'll
> print
> an error and fix up the flag.
>
> > > > + intel_tc_icl_tc_cold_exit(dev_priv);
> > > >
> > > > - _hsw_power_well_continue_enable(dev_priv, power_well);
> > > > + /*
> > > > +* To avoid power well enable timeouts when
> > > > disconnected or in
> > > > TBT mode
> > > > +* when doing the TC cold exit sequence for GEN11
> > > > +*/
> > > > + if (INTEL_GEN(dev_priv) != 11 ||
> > > > + (intel_tc_port_live_status_mask(dig_port) &
> > > > +(TC_PORT_LEGACY | TC_PORT_DP_ALT)))
> > > > + _hsw_power_well_continue_enable(dev_priv,
> > > > power_well);
> > >
> > > Why can't we call this unconditionally?
> >
> > Because we are requesting aux power of regular TC ports as part of
> > tc
> > cold exit sequence, if the port is disconnected it will timeout in
> > hsw_wait_for_power_well_enable().
> >
> > Anyways it is wrong as it is not
> > taking care of TBT ports, so changing to: if (INTEL_GEN(dev_priv)
> > != 11
> > > > !dig_port->tc_legacy_port || intel_tc_port_live_status_mask())
>
> What I thought is that the legacy AUX power request will ack after
> the
> PCODE request completes, regardless of whether the sink is connected
> or
> not. If that is not the case then let's just suppress the timeout for
> legacy AUX power wells the same way we do that for TBT AUX. I don't
> like
> to make the above call conditional on the live status flag, as that
> can
> change at any moment. So in either case let's make the above call
> unconditional.
>
> > > >
> > > > if (INTEL_GEN(dev_priv) >= 12 && !power_well->desc-
> > > > > hsw.is_tc_tbt) {
>
> Could you check your email client, so that it doesn't wrap lines?
>
> > > > enum tc_port tc_port;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >
[Intel-gfx] [PATCH] drm/i915/perf: Do not clear pollin for small user read buffers
It is wrong to block the user thread in the next poll when OA data is
already available which could not fit in the user buffer provided in
the previous read. In several cases the exact user buffer size is not
known. Blocking user space in poll can lead to data loss when the
buffer size used is smaller than the available data.
This change fixes this issue and allows user space to read all OA data
even when using a buffer size smaller than the available data using
multiple non-blocking reads rather than staying blocked in poll till
the next timer interrupt.
v2: Fix ret value for blocking reads (Umesh)
v3: Mistake during patch send (Ashutosh)
v4: Remove -EAGAIN from comment (Umesh)
v5: Improve condition for clearing pollin and return (Lionel)
v6: Improve blocking read loop and other cleanups (Lionel)
v7: Added Cc stable
Cc: Umesh Nerlige Ramappa
Cc:
Reviewed-by: Lionel Landwerlin
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 61 ++--
1 file changed, 11 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 28e3d76fa2e6..2f78b147bb2d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2963,49 +2963,6 @@ void i915_oa_init_reg_state(const struct intel_context
*ce,
gen8_update_reg_state_unlocked(ce, stream);
}
-/**
- * i915_perf_read_locked - _perf_stream_ops->read with error normalisation
- * @stream: An i915 perf stream
- * @file: An i915 perf stream file
- * @buf: destination buffer given by userspace
- * @count: the number of bytes userspace wants to read
- * @ppos: (inout) file seek position (unused)
- *
- * Besides wrapping _perf_stream_ops->read this provides a common place to
- * ensure that if we've successfully copied any data then reporting that takes
- * precedence over any internal error status, so the data isn't lost.
- *
- * For example ret will be -ENOSPC whenever there is more buffered data than
- * can be copied to userspace, but that's only interesting if we weren't able
- * to copy some data because it implies the userspace buffer is too small to
- * receive a single record (and we never split records).
- *
- * Another case with ret == -EFAULT is more of a grey area since it would seem
- * like bad form for userspace to ask us to overrun its buffer, but the user
- * knows best:
- *
- * http://yarchive.net/comp/linux/partial_reads_writes.html
- *
- * Returns: The number of bytes copied or a negative error code on failure.
- */
-static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream,
-struct file *file,
-char __user *buf,
-size_t count,
-loff_t *ppos)
-{
- /* Note we keep the offset (aka bytes read) separate from any
-* error status so that the final check for whether we return
-* the bytes read with a higher precedence than any error (see
-* comment below) doesn't need to be handled/duplicated in
-* stream->ops->read() implementations.
-*/
- size_t offset = 0;
- int ret = stream->ops->read(stream, buf, count, );
-
- return offset ?: (ret ?: -EAGAIN);
-}
-
/**
* i915_perf_read - handles read() FOP for i915 perf stream FDs
* @file: An i915 perf stream file
@@ -3031,7 +2988,8 @@ static ssize_t i915_perf_read(struct file *file,
{
struct i915_perf_stream *stream = file->private_data;
struct i915_perf *perf = stream->perf;
- ssize_t ret;
+ size_t offset = 0;
+ int ret;
/* To ensure it's handled consistently we simply treat all reads of a
* disabled stream as an error. In particular it might otherwise lead
@@ -3054,13 +3012,12 @@ static ssize_t i915_perf_read(struct file *file,
return ret;
mutex_lock(>lock);
- ret = i915_perf_read_locked(stream, file,
- buf, count, ppos);
+ ret = stream->ops->read(stream, buf, count, );
mutex_unlock(>lock);
- } while (ret == -EAGAIN);
+ } while (!offset && !ret);
} else {
mutex_lock(>lock);
- ret = i915_perf_read_locked(stream, file, buf, count, ppos);
+ ret = stream->ops->read(stream, buf, count, );
mutex_unlock(>lock);
}
@@ -3071,11 +3028,15 @@ static ssize_t i915_perf_read(struct file *file,
* and read() returning -EAGAIN. Clearing the oa.pollin state here
* effectively ensures we back off until the next hrtimer callback
* before reporting another EPOLLIN event.
+* The exception to this is if ops->read() returned -ENOSPC which means
+* that more OA data is available than could fit in the
Re: [Intel-gfx] [PATCH 13/13] drm/i915: Move the port sync DP_TP_CTL stuff to the encoder hook
On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Move the final DP_TP_CTL frobbing of port sync to the master
> encoder's enable hook. Now neatly out of sight from the high level
> modeset code.
>
> And thus we've eliminated all the special casing of port sync
> in the high level modeset code.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 37
> drivers/gpu/drm/i915/display/intel_display.c | 99
>
> 2 files changed, 53 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 98475c81f1da..856c56f84833 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3547,6 +3547,41 @@ void intel_ddi_fdi_post_disable(struct
> intel_atomic_state *state,
> intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
> }
>
> +static void trans_port_sync_stop_link_train(struct
> intel_atomic_state *state,
> + struct intel_encoder
> *encoder,
> + const struct
> intel_crtc_state *crtc_state)
> +{
> + const struct drm_connector_state *conn_state;
> + struct drm_connector *conn;
> + int i;
> +
> + if (!crtc_state->sync_mode_slaves_mask)
> + return;
> +
> + for_each_new_connector_in_state(>base, conn, conn_state,
> i) {
> + struct intel_encoder *slave_encoder =
> + to_intel_encoder(conn_state->best_encoder);
> + struct intel_crtc *slave_crtc =
> to_intel_crtc(conn_state->crtc);
> + const struct intel_crtc_state *slave_crtc_state;
> +
> + if (!slave_crtc)
> + continue;
> +
> + slave_crtc_state =
> + intel_atomic_get_new_crtc_state(state,
> slave_crtc);
> +
> + if (slave_crtc_state->master_transcoder !=
> + crtc_state->cpu_transcoder)
> + continue;
> +
> + intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder)
> );
> + }
> +
> + usleep_range(200, 400);
> +
> + intel_dp_stop_link_train(enc_to_intel_dp(encoder));
> +}
> +
> static void intel_enable_ddi_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state
> *crtc_state,
> @@ -3567,6 +3602,8 @@ static void intel_enable_ddi_dp(struct
> intel_atomic_state *state,
>
> if (crtc_state->has_audio)
> intel_audio_codec_enable(encoder, crtc_state,
> conn_state);
> +
> + trans_port_sync_stop_link_train(state, encoder, crtc_state);
> }
>
> static i915_reg_t
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 84e59f6ab8e4..cdae7a680e4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -544,19 +544,25 @@ needs_modeset(const struct intel_crtc_state
> *state)
> return drm_atomic_crtc_needs_modeset(>uapi);
> }
>
> -bool
> -is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
> -{
> - return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
> - crtc_state->sync_mode_slaves_mask);
> -}
> -
> static bool
> is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
> {
> return crtc_state->master_transcoder != INVALID_TRANSCODER;
> }
>
> +static bool
> +is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
> +{
> + return crtc_state->sync_mode_slaves_mask != 0;
> +}
> +
> +bool
> +is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
> +{
> + return is_trans_port_sync_master(crtc_state) ||
> + is_trans_port_sync_slave(crtc_state);
> +}
> +
> /*
> * Platform specific helpers to calculate the port PLL loopback-
> (clock.m),
> * and post-divider (clock.p) values, pre- (clock.vco) and post-
> divided fast
> @@ -15104,63 +15110,6 @@ static void
> intel_commit_modeset_enables(struct intel_atomic_state *state)
> }
> }
>
> -static void intel_set_dp_tp_ctl_normal(struct intel_atomic_state
> *state,
> -struct intel_crtc *crtc)
> -{
> - struct drm_connector *uninitialized_var(conn);
> - struct drm_connector_state *conn_state;
> - struct intel_dp *intel_dp;
> - int i;
> -
> - for_each_new_connector_in_state(>base, conn, conn_state,
> i) {
> - if (conn_state->crtc == >base)
> - break;
> - }
> - intel_dp = intel_attached_dp(to_intel_connector(conn));
> - intel_dp_stop_link_train(intel_dp);
> -}
> -
> -static void intel_update_trans_port_sync_crtcs(struct
> intel_atomic_state *state,
> -struct
Re: [Intel-gfx] [PATCH 11/13] drm/i915: Do pipe updates after enables for everyone
On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently only port sync pipes do the sequence such that
> we first do the modeset part for every pipe and then do
> the plane/etc. updates. Let's follow that apporach for
> all pipes in skl+ so that we can properly integrate the
> port sync into the normal modeset flow.
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 44 ++--
>
> 1 file changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 33f38c8a5da4..3926ac8f1f10 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15152,17 +15152,6 @@ static void
> intel_update_trans_port_sync_crtcs(struct intel_atomic_state *state,
>
> usleep_range(200, 400);
> intel_set_dp_tp_ctl_normal(state, crtc);
> -
> - for_each_new_intel_crtc_in_state(state, slave_crtc,
> - new_slave_crtc_state, i) {
> - if (new_slave_crtc_state->master_transcoder !=
> - new_crtc_state->cpu_transcoder)
> - continue;
> -
> - intel_update_crtc(state, slave_crtc);
> - }
> -
> - intel_update_crtc(state, crtc);
> }
>
> static void icl_dbuf_slice_pre_update(struct intel_atomic_state
> *state)
> @@ -15251,6 +15240,8 @@ static void skl_commit_modeset_enables(struct
> intel_atomic_state *state)
> }
> }
>
> + update_pipes = modeset_pipes;
> +
> /*
>* Enable all pipes that needs a modeset and do not depends on
> other
>* pipes
> @@ -15266,10 +15257,6 @@ static void
> skl_commit_modeset_enables(struct intel_atomic_state *state)
> is_trans_port_sync_slave(new_crtc_state))
> continue;
>
> - drm_WARN_ON(_priv->drm,
> skl_ddb_allocation_overlaps(_crtc_state->wm.skl.ddb,
> -
> entries, I915_MAX_PIPES, pipe));
> -
> - entries[pipe] = new_crtc_state->wm.skl.ddb;
> modeset_pipes &= ~BIT(pipe);
>
> if (is_trans_port_sync_mode(new_crtc_state)) {
> @@ -15287,14 +15274,13 @@ static void
> skl_commit_modeset_enables(struct intel_atomic_state *state)
> }
> } else {
> intel_enable_crtc(state, crtc);
> - intel_update_crtc(state, crtc);
> }
> }
>
> /*
> - * Finally enable all pipes that needs a modeset and depends on
> - * other pipes, right now it is only MST slaves as both port
> sync slave
> - * and master are enabled together
> + * Then we enable all remaining pipes that depend on other
> + * pipes, right now it is only MST slaves as both port sync
> + * slave and master are enabled together
>*/
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state,
> i) {
> enum pipe pipe = crtc->pipe;
> @@ -15302,18 +15288,32 @@ static void
> skl_commit_modeset_enables(struct intel_atomic_state *state)
> if ((modeset_pipes & BIT(pipe)) == 0)
> continue;
>
> + modeset_pipes &= ~BIT(pipe);
> +
> + intel_enable_crtc(state, crtc);
> + }
> +
> + /*
> + * Finally we do the plane updates/etc. for all pipes that got
> enabled.
> + */
> + for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
> + new_crtc_state, i) {
> + enum pipe pipe = crtc->pipe;
> +
> + if ((update_pipes & BIT(pipe)) == 0)
> + continue;
> +
> drm_WARN_ON(_priv->drm,
> skl_ddb_allocation_overlaps(_crtc_state->wm.skl.ddb,
>
> entries, I915_MAX_PIPES, pipe));
>
> entries[pipe] = new_crtc_state->wm.skl.ddb;
> - modeset_pipes &= ~BIT(pipe);
> + update_pipes &= ~BIT(pipe);
>
> - intel_enable_crtc(state, crtc);
> intel_update_crtc(state, crtc);
> }
>
> drm_WARN_ON(_priv->drm, modeset_pipes);
> -
> + drm_WARN_ON(_priv->drm, update_pipes);
> }
>
> static void intel_atomic_helper_free_state(struct drm_i915_private
> *dev_priv)
___
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Re: [Intel-gfx] [PATCH 10/13] drm/i915: Fix port sync code to work with >2 pipes
On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Don't assume there is just one port sync slave. We might have
> several.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 98 ++--
>
> 1 file changed, 49 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b56a5a49418f..33f38c8a5da4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15009,18 +15009,6 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
> intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> }
>
> -static struct intel_crtc *intel_get_slave_crtc(const struct
> intel_crtc_state *new_crtc_state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(new_crtc_state-
> >uapi.crtc->dev);
> - enum transcoder slave_transcoder;
> -
> - drm_WARN_ON(_priv->drm,
> - !is_power_of_2(new_crtc_state-
> >sync_mode_slaves_mask));
> -
> - slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) -
> 1;
> - return intel_get_crtc_for_pipe(dev_priv,
> -(enum pipe)slave_transcoder);
> -}
>
> static void intel_old_crtc_state_disables(struct intel_atomic_state
> *state,
> struct intel_crtc_state
> *old_crtc_state,
> @@ -15109,8 +15097,8 @@ static void
> intel_commit_modeset_enables(struct intel_atomic_state *state)
> }
> }
>
> -static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
> -struct intel_atomic_state
> *state)
> +static void intel_set_dp_tp_ctl_normal(struct intel_atomic_state
> *state,
> +struct intel_crtc *crtc)
> {
> struct drm_connector *uninitialized_var(conn);
> struct drm_connector_state *conn_state;
> @@ -15125,45 +15113,55 @@ static void
> intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
> intel_dp_stop_link_train(intel_dp);
> }
>
> -static void intel_update_trans_port_sync_crtcs(struct intel_crtc
> *crtc,
> -struct
> intel_atomic_state *state,
> -struct intel_crtc_state
> *old_crtc_state,
> -struct intel_crtc_state
> *new_crtc_state)
> +static void intel_update_trans_port_sync_crtcs(struct
> intel_atomic_state *state,
> +struct intel_crtc *crtc)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - struct intel_crtc *slave_crtc =
> intel_get_slave_crtc(new_crtc_state);
> - struct intel_crtc_state *new_slave_crtc_state =
> - intel_atomic_get_new_crtc_state(state, slave_crtc);
> - struct intel_crtc_state *old_slave_crtc_state =
> - intel_atomic_get_old_crtc_state(state, slave_crtc);
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_crtc_state *new_slave_crtc_state;
> + const struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc *slave_crtc;
> + int i;
>
> - drm_WARN_ON(>drm, !slave_crtc || !new_slave_crtc_state ||
> - !old_slave_crtc_state);
> + for_each_new_intel_crtc_in_state(state, slave_crtc,
> + new_slave_crtc_state, i) {
> + if (new_slave_crtc_state->master_transcoder !=
> + new_crtc_state->cpu_transcoder)
Missing new_crtc_state initialization.
With that:
Reviewed-by: José Roberto de Souza
> + continue;
> +
> + drm_dbg_kms(>drm,
> + "Updating transcoder port sync slave
> [CRTC:%d:%s]\n",
> + slave_crtc->base.base.id, slave_crtc-
> >base.name);
> +
> + intel_enable_crtc(state, slave_crtc);
> + }
>
> drm_dbg_kms(>drm,
> - "Updating Transcoder Port Sync Master CRTC = %d %s
> and Slave CRTC %d %s\n",
> - crtc->base.base.id, crtc->base.name,
> - slave_crtc->base.base.id, slave_crtc->base.name);
> + "Updating transcoder port sync master
> [CRTC:%d:%s]\n",
> + crtc->base.base.id, crtc->base.name);
>
> - /* Enable seq for slave with with DP_TP_CTL left Idle until the
> - * master is ready
> - */
> - intel_enable_crtc(state, slave_crtc);
> -
> - /* Enable seq for master with with DP_TP_CTL left Idle */
> intel_enable_crtc(state, crtc);
>
> - /* Set Slave's DP_TP_CTL to Normal */
> - intel_set_dp_tp_ctl_normal(slave_crtc,
> -state);
> + for_each_new_intel_crtc_in_state(state, slave_crtc,
> + new_slave_crtc_state, i) {
> + if
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Make Wa_14010229206 permanent
On Thu, Mar 26, 2020 at 04:49:55PM -0700, Swathi Dhanavanthri wrote:
> This workaround now applies to all steppings, not just A0.
> Wa_1409085225 is a temporary A0-only W/A however it is
> identical to Wa_14010229206 and hence the combined workaround
> is made permanent.
> Bspec: 52890
>
> Signed-off-by: Swathi Dhanavanthri
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e96cc7fa0936..c3c42cf614a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1380,12 +1380,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> GEN7_FF_THREAD_MODE,
> GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
>
> - /*
> - * Wa_1409085225:tgl
> - * Wa_14010229206:tgl
> - */
> - wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
> -
> /* Wa_1408615072:tgl */
> wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> VSUNIT_CLKGATE_DIS_TGL);
> @@ -1403,6 +1397,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> wa_masked_en(wal,
>GEN9_CS_DEBUG_MODE1,
>FF_DOP_CLOCK_GATE_DISABLE);
There should be a blank line here, but I can add that while applying.
Reviewed-by: Matt Roper
Looks like CI results are back and clean now, so applied to dinq.
Thanks for the patch.
Matt
> + /*
> + * Wa_1409085225:tgl
> + * Wa_14010229206:tgl
> + */
> + wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
> }
>
> if (IS_GEN(i915, 11)) {
> --
> 2.20.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Check for has-reset before testing hostile contexts (rev2)
== Series Details == Series: drm/i915/selftests: Check for has-reset before testing hostile contexts (rev2) URL : https://patchwork.freedesktop.org/series/74915/ State : failure == Summary == Applying: drm/i915/selftests: Check for has-reset before testing hostile contexts Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/selftest_lrc.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] 5.6-rc7: Xorg hangs, too
Quoting Pavel Machek (2020-04-02 22:35:07)
> [258096.980089] 3 locks held by kswapd0/1034:
> [258096.980096] #0: 85851c80 (fs_reclaim){}, at:
> __fs_reclaim_acquire+0x0/0x30
> [258096.980114] #1: 85850b40 (shrinker_rwsem){}, at:
> shrink_slab.constprop.79+0x38/0x270
> [258096.980130] #2: 888197278b90 (>mutex){}, at:
> i915_vma_unbind+0x90/0xe0
> [258096.980177] 3 locks held by Xorg/3123:
> [258096.980183] #0: 8881972700c8 (>struct_mutex){}, at:
> i915_gem_do_execbuffer+0x690/0x1ef0
> [258096.980200] #1: 88819576e950 (>mutex){}, at:
> eb_lookup_vmas+0x7d/0xd10
> [258096.980215] #2: 888197278b90 (>mutex){}, at:
> i915_vma_pin+0xb4/0x750
That's the pair that's causing the trouble.
-Chris
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[Intel-gfx] 5.6-rc6: Xorg hangs
Hi! Hardware is thinkpad x220. I had this crash few days ago. And today I have similar-looking one, with slightly newer kernel. (Will post as a follow-up). Any idea what can be wrong? Pavel [171953.828956] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [171953.965936] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [172269.832635] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [172269.964645] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [172585.837116] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [172585.973091] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [172901.836180] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [172901.909705] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [173216.838138] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [173216.998141] iwlwifi :03:00.0: Radio type=0x0-0x0-0x3 [173394.002295] INFO: task Xorg:3074 blocked for more than 120 seconds. [173394.002326] Not tainted 5.6.0-rc6+ #83 [173394.002348] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [173394.002370] XorgD0 3074 3067 0x00404000 [173394.002397] Call Trace: [173394.002430] __schedule+0x350/0x6b0 [173394.002445] schedule+0x3b/0xf0 [173394.002457] schedule_preempt_disabled+0x13/0x20 [173394.002468] __mutex_lock+0x3e0/0x8a0 [173394.002480] ? i915_vma_pin+0xb4/0x750 [173394.002492] mutex_lock_nested+0x16/0x20 [173394.002503] ? mutex_lock_nested+0x16/0x20 [173394.002511] i915_vma_pin+0xb4/0x750 [173394.002526] eb_lookup_vmas+0x1c2/0xd10 [173394.002539] i915_gem_do_execbuffer+0x6a7/0x1ef0 [173394.002556] ? __lock_acquire.isra.33+0x297/0x550 [173394.002566] ? find_held_lock+0x35/0xa0 [173394.002579] ? kvmalloc_node+0x67/0x70 [173394.002593] ? i915_gem_execbuffer_ioctl+0x270/0x270 [173394.002604] i915_gem_execbuffer2_ioctl+0x1bc/0x390 [173394.002616] ? i915_gem_execbuffer_ioctl+0x270/0x270 [173394.002628] drm_ioctl_kernel+0xab/0xf0 [173394.002639] drm_ioctl+0x205/0x3e0 [173394.002650] ? i915_gem_execbuffer_ioctl+0x270/0x270 [173394.002665] ? __fget_files+0x9d/0xd0 [173394.002677] ksys_ioctl+0x73/0xb0 [173394.002688] __x64_sys_ioctl+0x15/0x20 [173394.002698] do_syscall_64+0x48/0x110 [173394.002709] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [173394.002720] RIP: 0033:0x7f207a42b427 [173394.002737] Code: Bad RIP value. [173394.002749] RSP: 002b:7ffc7ed2af88 EFLAGS: 0246 ORIG_RAX: 0010 [173394.002764] RAX: ffda RBX: 56121c1436d0 RCX: 7f207a42b427 [173394.002776] RDX: 7ffc7ed2afd0 RSI: 40406469 RDI: 000e [173394.002788] RBP: 7ffc7ed2afd0 R08: 56121c1810a0 R09: 7ffc7edd1090 [173394.002801] R10: 7ffc7ed2b070 R11: 0246 R12: 40406469 [173394.002813] R13: 000e R14: R15: [173394.002833] INFO: task InputThread:3377 blocked for more than 120 seconds. [173394.002845] Not tainted 5.6.0-rc6+ #83 [173394.002857] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [173394.002869] InputThread D0 3377 3067 0x0040 [173394.002886] Call Trace: [173394.002903] __schedule+0x350/0x6b0 [173394.002920] schedule+0x3b/0xf0 [173394.002935] schedule_preempt_disabled+0x13/0x20 [173394.002951] __mutex_lock+0x3e0/0x8a0 [173394.002971] ? i915_gem_object_bump_inactive_ggtt+0x3f/0x210 [173394.002984] mutex_lock_nested+0x16/0x20 [173394.002995] ? mutex_lock_nested+0x16/0x20 [173394.003006] i915_gem_object_bump_inactive_ggtt+0x3f/0x210 [173394.003018] i915_gem_object_unpin_from_display_plane+0x23/0x60 [173394.003033] intel_unpin_fb_vma+0x40/0xb0 [173394.003045] intel_legacy_cursor_update+0x2ae/0x320 [173394.003058] __setplane_atomic+0xce/0x110 [173394.003069] drm_mode_cursor_universal+0x13d/0x260 [173394.003082] drm_mode_cursor_common+0xd5/0x240 [173394.003093] ? drm_mode_setplane+0x1b0/0x1b0 [173394.003103] drm_mode_cursor_ioctl+0x45/0x60 [173394.003113] drm_ioctl_kernel+0xab/0xf0 [173394.003124] drm_ioctl+0x205/0x3e0 [173394.003133] ? drm_mode_setplane+0x1b0/0x1b0 [173394.003146] ? __fget_files+0x9d/0xd0 [173394.003158] ksys_ioctl+0x73/0xb0 [173394.003169] __x64_sys_ioctl+0x15/0x20 [173394.003178] do_syscall_64+0x48/0x110 [173394.003187] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [173394.003196] RIP: 0033:0x7f207a42b427 [173394.003208] Code: Bad RIP value. [173394.003216] RSP: 002b:7f2076b142d8 EFLAGS: 0246 ORIG_RAX: 0010 [173394.003225] RAX: ffda RBX: 56121c190180 RCX: 7f207a42b427 [173394.003233] RDX: 7f2076b14310 RSI: c01c64a3 RDI: 000e [173394.003241] RBP: 7f2076b14310 R08: 0001 R09: 0001 [173394.003249] R10: 0780 R11: 0246 R12: c01c64a3 [173394.003256] R13: 000e R14: 043b R15: 01e7
[Intel-gfx] [PULL] drm-intel-next-fixes
Hi Dave and Daniel, Here goes drm-intel-next-fixes-2020-04-02: Only gvt fixes on this round: - Fix non-privilege access warning (Tina) - Fix display port type (Tina) - BDW cmd parser missed SWTESS_BASE_ADDRESS (Yan) - Bypass length check of LRI (Yan) - Fix one klocwork warning (Tina) Thanks, Rodrigo. The following changes since commit 2bdd4c28baff29163808677a70942de2b45f17dc: drm/i915/display: Fix mode private_flags comparison at atomic_check (2020-03-26 10:21:30 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2020-04-02 for you to fetch changes up to 17d0c1062a0c60e17c96538adf4a84c208930d9d: Merge tag 'gvt-next-fixes-2020-03-31' of https://github.com/intel/gvt-linux into drm-intel-next-fixes (2020-03-31 09:25:15 -0700) Only gvt fixes on this round: - Fix non-privilege access warning (Tina) - Fix display port type (Tina) - BDW cmd parser missed SWTESS_BASE_ADDRESS (Yan) - Bypass length check of LRI (Yan) - Fix one klocwork warning (Tina) Rodrigo Vivi (1): Merge tag 'gvt-next-fixes-2020-03-31' of https://github.com/intel/gvt-linux into drm-intel-next-fixes Tina Zhang (3): drm/i915/gvt: Add some regs to force-to-nonpriv whitelist drm/i915/gvt: Fix display port type issue drm/i915/gvt: Fix klocwork issues about data size Yan Zhao (2): drm/i915/gvt: add support to command SWTESS_BASE_ADDRESS drm/i915/gvt: do not check len & max_len for lri drivers/gpu/drm/i915/gvt/cmd_parser.c | 16 drivers/gpu/drm/i915/gvt/display.c| 6 +++--- drivers/gpu/drm/i915/gvt/handlers.c | 8 ++-- drivers/gpu/drm/i915/gvt/scheduler.c | 4 ++-- 4 files changed, 15 insertions(+), 19 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/selftests: Check for has-reset before testing hostile contexts
In order to kill off a hostile context, we need to be able to reset the
GPU. So check that is supported prior to beginning the test.
Reported-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index f3ba58842120..985d4041d929 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -2046,6 +2046,9 @@ static int __cancel_hostile(struct live_preempt_cancel
*arg)
if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
return 0;
+ if (!intel_has_reset_engine(arg->engine->gt))
+ return 0;
+
GEM_TRACE("%s(%s)\n", __func__, arg->engine->name);
rq = spinner_create_request(>a.spin,
arg->a.ctx, arg->engine,
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915/gem: Utilize rcu iteration of context engines
Chris Wilson writes:
> Now that we can peek at GEM->engines[] and obtain a reference to them
> using RCU, do so for instances where we can safely iterate the
> potentially old copy of the engines. For setting, we can do this when we
> know the engine properties are copied over before swapping, so we know
> the new engines already have the global property and we update the old
> before they are discarded. For reading, we only need to be safe; as we
> do so on behalf of the user, their races are their own problem.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 +++--
> 1 file changed, 31 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 50e7580f9337..2b6dd08de6f1 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -757,21 +757,46 @@ __create_context(struct drm_i915_private *i915)
> return ERR_PTR(err);
> }
>
> +static inline struct i915_gem_engines *
> +__context_engines_await(const struct i915_gem_context *ctx)
> +{
> + struct i915_gem_engines *engines;
> +
> + rcu_read_lock();
> + do {
> + engines = rcu_dereference(ctx->engines);
> + GEM_BUG_ON(!engines);
> +
> + if (unlikely(!i915_sw_fence_await(>fence)))
> + continue;
> +
> + if (likely(engines == rcu_access_pointer(ctx->engines)))
> + break;
> +
> + i915_sw_fence_complete(>fence);
> + } while (1);
> + rcu_read_unlock();
> +
> + return engines;
> +}
> +
> static int
> context_apply_all(struct i915_gem_context *ctx,
> int (*fn)(struct intel_context *ce, void *data),
> void *data)
> {
> struct i915_gem_engines_iter it;
> + struct i915_gem_engines *e;
> struct intel_context *ce;
> int err = 0;
>
> - for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> + e = __context_engines_await(ctx);
> + for_each_gem_engine(ce, e, it) {
> err = fn(ce, data);
> if (err)
> break;
> }
> - i915_gem_context_unlock_engines(ctx);
> + i915_sw_fence_complete(>fence);
>
> return err;
> }
> @@ -786,11 +811,13 @@ static int __apply_ppgtt(struct intel_context *ce, void
> *vm)
> static struct i915_address_space *
> __set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm)
> {
> - struct i915_address_space *old = i915_gem_context_vm(ctx);
> + struct i915_address_space *old;
>
> + old = rcu_replace_pointer(ctx->vm,
> + i915_vm_open(vm),
> + lockdep_is_held(>mutex));
> GEM_BUG_ON(old && i915_vm_is_4lvl(vm) != i915_vm_is_4lvl(old));
>
> - rcu_assign_pointer(ctx->vm, i915_vm_open(vm));
> context_apply_all(ctx, __apply_ppgtt, vm);
>
> return old;
> @@ -1069,30 +1096,6 @@ static void cb_retire(struct i915_active *base)
> kfree(cb);
> }
>
> -static inline struct i915_gem_engines *
> -__context_engines_await(const struct i915_gem_context *ctx)
> -{
> - struct i915_gem_engines *engines;
> -
> - rcu_read_lock();
> - do {
> - engines = rcu_dereference(ctx->engines);
> - if (unlikely(!engines))
> - break;
> -
> - if (unlikely(!i915_sw_fence_await(>fence)))
> - continue;
> -
> - if (likely(engines == rcu_access_pointer(ctx->engines)))
> - break;
> -
> - i915_sw_fence_complete(>fence);
> - } while (1);
> - rcu_read_unlock();
> -
> - return engines;
> -}
> -
> I915_SELFTEST_DECLARE(static intel_engine_mask_t
> context_barrier_inject_fault);
> static int context_barrier_task(struct i915_gem_context *ctx,
> intel_engine_mask_t engines,
> --
> 2.20.1
>
> ___
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Peek at the next submission for error interrupts
Quoting Mika Kuoppala (2020-04-02 21:16:52) > Chris Wilson writes: > > > If we receive the error interrupt before the CS interrupt, we may find > > ourselves without an active request to reset, skipping the GPU reset. > > All because the attempt to reset was too early. > > > > With the tracing, we will see the the out of sync situations > so > > Reviewed-by: Mika Kuoppala I think that's the main benefit and it makes sense to have this patch by itself so that we can get a bit more info perhaps next time. Then if it keeps on failing, that might justify trying the second patch. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/execlists: Record the active CCID from before reset
Chris Wilson writes:
> If we cannot trust the reset will flush out the CS event queue such that
> process_csb() reports an accurate view of HW, we will need to search the
> active and pending contexts to determine which was actually running at
> the time we issued the reset.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 80cdde712842..4804587442e7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -166,6 +166,11 @@ struct intel_engine_execlists {
>*/
> u32 error_interrupt;
>
> + /**
> + * @reset_ccid: Active CCID [EXECLISTS_STATUS_HI] at the time of reset
> + */
> + u32 reset_ccid;
> +
> /**
>* @no_priolist: priority lists disabled
>*/
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index f028114714cd..55bf3cdf3b38 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3724,6 +3724,8 @@ static void execlists_reset_prepare(struct
> intel_engine_cs *engine)
>*/
> ring_set_paused(engine, 1);
> intel_engine_stop_cs(engine);
> +
> + engine->execlists.reset_ccid = active_ccid(engine);
> }
>
> static void reset_csb_pointers(struct intel_engine_cs *engine)
> @@ -3798,7 +3800,7 @@ static void __execlists_reset(struct intel_engine_cs
> *engine, bool stalled)
>* its request, it was still running at the time of the
>* reset and will have been clobbered.
>*/
> - rq = execlists_active(execlists);
> + rq = active_context(engine, engine->execlists.reset_ccid);
> if (!rq)
> goto unwind;
>
> --
> 2.20.1
>
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/execlists: Peek at the next submission for error interrupts
Chris Wilson writes:
> If we receive the error interrupt before the CS interrupt, we may find
> ourselves without an active request to reset, skipping the GPU reset.
> All because the attempt to reset was too early.
>
With the tracing, we will see the the out of sync situations
so
Reviewed-by: Mika Kuoppala
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 41 -
> 1 file changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 3479cda37fdc..f028114714cd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2804,6 +2804,45 @@ static struct execlists_capture *capture_regs(struct
> intel_engine_cs *engine)
> return NULL;
> }
>
> +static struct i915_request *
> +active_context(struct intel_engine_cs *engine, u32 ccid)
> +{
> + const struct intel_engine_execlists * const el = >execlists;
> + struct i915_request * const *port, *rq;
> +
> + /*
> + * Use the most recent result from process_csb(), but just in case
> + * we trigger an error (via interrupt) before the first CS event has
> + * been written, peek at the next submission.
> + */
> +
> + for (port = el->active; (rq = *port); port++) {
> + if (upper_32_bits(rq->context->lrc_desc) == ccid) {
> + ENGINE_TRACE(engine,
> + "ccid found at active:%zd\n",
> + port - el->active);
> + return rq;
> + }
> + }
> +
> + for (port = el->pending; (rq = *port); port++) {
> + if (upper_32_bits(rq->context->lrc_desc) == ccid) {
> + ENGINE_TRACE(engine,
> + "ccid found at pending:%zd\n",
> + port - el->pending);
> + return rq;
> + }
> + }
> +
> + ENGINE_TRACE(engine, "ccid:%x not found\n", ccid);
> + return NULL;
> +}
> +
> +static u32 active_ccid(struct intel_engine_cs *engine)
> +{
> + return ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI);
> +}
> +
> static bool execlists_capture(struct intel_engine_cs *engine)
> {
> struct execlists_capture *cap;
> @@ -2821,7 +2860,7 @@ static bool execlists_capture(struct intel_engine_cs
> *engine)
> return true;
>
> spin_lock_irq(>active.lock);
> - cap->rq = execlists_active(>execlists);
> + cap->rq = active_context(engine, active_ccid(engine));
> if (cap->rq) {
> cap->rq = active_request(cap->rq->context->timeline, cap->rq);
> cap->rq = i915_request_get_rcu(cap->rq);
> --
> 2.20.1
>
> ___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Keep a per-engine request pools (rev2)
== Series Details == Series: drm/i915: Keep a per-engine request pools (rev2) URL : https://patchwork.freedesktop.org/series/75427/ State : success == Summary == CI Bug Log - changes from CI_DRM_8238 -> Patchwork_17189 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17189/index.html Changes --- No changes found Participating hosts (50 -> 39) -- Missing(11): fi-ilk-m540 fi-tgl-u fi-tgl-dsi fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8238 -> Patchwork_17189 CI-20190529: 20190529 CI_DRM_8238: 840f70602a47208a2f1e444ba276f412f10e38df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5558: 3b55a816300d80bc5e0b995cd41ee8c8649a1ea2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17189: 14acbca51678ae918b24e847596b290f7b15a608 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 14acbca51678 drm/i915: Keep a per-engine request pools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17189/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: move remaining debugfs interfaces into gt (rev3)
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev3)
URL : https://patchwork.freedesktop.org/series/75333/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8238 -> Patchwork_17188
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17188/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17188:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_wait@busy@all}:
- fi-gdg-551: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-gdg-551/igt@gem_wait@b...@all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17188/fi-gdg-551/igt@gem_wait@b...@all.html
Known issues
Here are the changes found in Patchwork_17188 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#656])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17188/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1531]: https://gitlab.freedesktop.org/drm/intel/issues/1531
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (50 -> 37)
--
Missing(13): fi-kbl-soraka fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-snb-2520m fi-ivb-3770
fi-kbl-7560u fi-byt-clapper fi-skl-6600u
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8238 -> Patchwork_17188
CI-20190529: 20190529
CI_DRM_8238: 840f70602a47208a2f1e444ba276f412f10e38df @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5558: 3b55a816300d80bc5e0b995cd41ee8c8649a1ea2 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17188: db515ae2c79c34e64b3c0909064d21358cbf1170 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
db515ae2c79c drm/i915/gt: move remaining debugfs interfaces into gt
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17188/index.html
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Re: [Intel-gfx] [PATCH] drm/i915/uc: Cleanup kerneldoc warnings
Chris Wilson writes: > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:205: warning: Excess function > parameter 'supported' description in 'intel_uc_fw_init_early' > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:205: warning: Excess function > parameter 'platform' description in 'intel_uc_fw_init_early' > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:205: warning: Excess function > parameter 'rev' description in 'intel_uc_fw_init_early' > > drivers/gpu/drm/i915/gt/uc/intel_guc_log.c:696: warning: Function parameter > or member 'log' not described in 'intel_guc_log_info' > drivers/gpu/drm/i915/gt/uc/intel_guc_log.c:696: warning: Excess function > parameter 'guc' description in 'intel_guc_log_info' > > Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 2 +- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 --- > 2 files changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c > b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c > index 5b11a6d8e27f..fb10f3597ea5 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c > @@ -687,7 +687,7 @@ stringify_guc_log_type(enum guc_log_buffer_type type) > > /** > * intel_guc_log_info - dump information about GuC log relay > - * @guc: the GuC > + * @log: the GuC log > * @p: the _printer > * > * Pretty printer for GuC log info > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > index fa893dd1823c..1f5d25f15340 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > @@ -193,9 +193,6 @@ static void __uc_fw_user_override(struct intel_uc_fw > *uc_fw) > * intel_uc_fw_init_early - initialize the uC object and select the firmware > * @uc_fw: uC firmware > * @type: type of uC > - * @supported: is uC support possible > - * @platform: platform identifier > - * @rev: hardware revision > * > * Initialize the state of our uC object and relevant tracking and select the > * firmware to fetch and load. > -- > 2.20.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Keep a per-engine request pools
Add a tiny per-engine request mempool so that we should always have a
request available for powermanagement allocations from tricky
contexts. This reserve is expected to be only used for kernel
contexts when barriers must be emitted [almost] without fail.
The main consumer for this reserved request is expected to be engine-pm,
for which we know that there will always be at least the previous pm
request that we can reuse under mempressure (so there should always be
a spare request for engine_park()).
This is an alternative to using a comparatively bulky mempool, which
requires custom handling for both our reserved allocation requirement
and to protect our TYPESAFE_BY_RCU slab cache.
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 7 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +++
drivers/gpu/drm/i915/i915_request.c | 27
drivers/gpu/drm/i915/i915_request.h | 2 ++
4 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 843cb6f2f696..5f45c8274203 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -431,7 +431,14 @@ void intel_engines_free(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
+ /* Free the requests! dma-resv keeps fences around for an eternity */
+ rcu_barrier();
+
for_each_engine(engine, gt, id) {
+ if (engine->request_pool)
+ kmem_cache_free(i915_request_slab_cache(),
+ engine->request_pool);
+
kfree(engine);
gt->engine[id] = NULL;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..de8e6edcf999 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -308,6 +308,9 @@ struct intel_engine_cs {
struct list_head hold; /* ready requests, but on hold */
} active;
+ /* keep a request in reserve for a [pm] barrier under oom */
+ struct i915_request *request_pool;
+
struct llist_head barrier_tasks;
struct intel_context *kernel_context; /* pinned */
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 3388c5b610c5..22635bbabf06 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -101,6 +101,11 @@ static signed long i915_fence_wait(struct dma_fence *fence,
timeout);
}
+struct kmem_cache *i915_request_slab_cache(void)
+{
+ return global.slab_requests;
+}
+
static void i915_fence_release(struct dma_fence *fence)
{
struct i915_request *rq = to_request(fence);
@@ -115,6 +120,10 @@ static void i915_fence_release(struct dma_fence *fence)
i915_sw_fence_fini(>submit);
i915_sw_fence_fini(>semaphore);
+ /* Keep one request on each engine for reserved use under mempressure */
+ if (!cmpxchg(>engine->request_pool, NULL, rq))
+ return;
+
kmem_cache_free(global.slab_requests, rq);
}
@@ -629,14 +638,22 @@ static void retire_requests(struct intel_timeline *tl)
}
static noinline struct i915_request *
-request_alloc_slow(struct intel_timeline *tl, gfp_t gfp)
+request_alloc_slow(struct intel_timeline *tl,
+ struct i915_request **rsvd,
+ gfp_t gfp)
{
struct i915_request *rq;
- if (list_empty(>requests))
- goto out;
+ /* If we cannot wait, dip into our reserves */
+ if (!gfpflags_allow_blocking(gfp)) {
+ rq = xchg(rsvd, NULL);
+ if (!rq) /* Use the normal failure path for one final WARN */
+ goto out;
- if (!gfpflags_allow_blocking(gfp))
+ return rq;
+ }
+
+ if (list_empty(>requests))
goto out;
/* Move our oldest request to the slab-cache (if not in use!) */
@@ -721,7 +738,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
rq = kmem_cache_alloc(global.slab_requests,
gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
if (unlikely(!rq)) {
- rq = request_alloc_slow(tl, gfp);
+ rq = request_alloc_slow(tl, >engine->request_pool, gfp);
if (!rq) {
ret = -ENOMEM;
goto err_unreserve;
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 3c552bfea67a..d8ce908e1346 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -300,6 +300,8 @@ static inline bool dma_fence_is_i915(const struct dma_fence
[Intel-gfx] [PATCH] drm/i915: Keep a per-engine request pools
Add a tiny per-engine request mempool so that we should always have a
request available for powermanagement allocations from tricky
contexts. This reserve is expected to be only used for kernel
contexts when barriers must be emitted [almost] without fail.
This is an alternative to using a comparatively bulky mempool, which
requires custom handling for both our reserved allocation requirement
and to protect our TYPESAFE_BY_RCU slab cache.
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 7 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +++
drivers/gpu/drm/i915/i915_request.c | 27
drivers/gpu/drm/i915/i915_request.h | 2 ++
4 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 843cb6f2f696..5f45c8274203 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -431,7 +431,14 @@ void intel_engines_free(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
+ /* Free the requests! dma-resv keeps fences around for an eternity */
+ rcu_barrier();
+
for_each_engine(engine, gt, id) {
+ if (engine->request_pool)
+ kmem_cache_free(i915_request_slab_cache(),
+ engine->request_pool);
+
kfree(engine);
gt->engine[id] = NULL;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..de8e6edcf999 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -308,6 +308,9 @@ struct intel_engine_cs {
struct list_head hold; /* ready requests, but on hold */
} active;
+ /* keep a request in reserve for a [pm] barrier under oom */
+ struct i915_request *request_pool;
+
struct llist_head barrier_tasks;
struct intel_context *kernel_context; /* pinned */
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 3388c5b610c5..22635bbabf06 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -101,6 +101,11 @@ static signed long i915_fence_wait(struct dma_fence *fence,
timeout);
}
+struct kmem_cache *i915_request_slab_cache(void)
+{
+ return global.slab_requests;
+}
+
static void i915_fence_release(struct dma_fence *fence)
{
struct i915_request *rq = to_request(fence);
@@ -115,6 +120,10 @@ static void i915_fence_release(struct dma_fence *fence)
i915_sw_fence_fini(>submit);
i915_sw_fence_fini(>semaphore);
+ /* Keep one request on each engine for reserved use under mempressure */
+ if (!cmpxchg(>engine->request_pool, NULL, rq))
+ return;
+
kmem_cache_free(global.slab_requests, rq);
}
@@ -629,14 +638,22 @@ static void retire_requests(struct intel_timeline *tl)
}
static noinline struct i915_request *
-request_alloc_slow(struct intel_timeline *tl, gfp_t gfp)
+request_alloc_slow(struct intel_timeline *tl,
+ struct i915_request **rsvd,
+ gfp_t gfp)
{
struct i915_request *rq;
- if (list_empty(>requests))
- goto out;
+ /* If we cannot wait, dip into our reserves */
+ if (!gfpflags_allow_blocking(gfp)) {
+ rq = xchg(rsvd, NULL);
+ if (!rq) /* Use the normal failure path for one final WARN */
+ goto out;
- if (!gfpflags_allow_blocking(gfp))
+ return rq;
+ }
+
+ if (list_empty(>requests))
goto out;
/* Move our oldest request to the slab-cache (if not in use!) */
@@ -721,7 +738,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
rq = kmem_cache_alloc(global.slab_requests,
gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
if (unlikely(!rq)) {
- rq = request_alloc_slow(tl, gfp);
+ rq = request_alloc_slow(tl, >engine->request_pool, gfp);
if (!rq) {
ret = -ENOMEM;
goto err_unreserve;
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 3c552bfea67a..d8ce908e1346 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -300,6 +300,8 @@ static inline bool dma_fence_is_i915(const struct dma_fence
*fence)
return fence->ops == _fence_ops;
}
+struct kmem_cache *i915_request_slab_cache(void);
+
struct i915_request * __must_check
__i915_request_create(struct intel_context *ce, gfp_t gfp);
struct i915_request * __must_check
--
2.20.1
[Intel-gfx] [PATCH v5] drm/i915/gt: move remaining debugfs interfaces into gt
From: Andi Shyti
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
i915_rcs_topology
i915_sseu_status
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
gt
|
+-- forcewake_user
|
+-- interrupt_info
|
+-- reset
|
+-- rcs_topology
|
+-- sseu_status
Signed-off-by: Andi Shyti
Reviewed-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
Hi,
this patch is the first of a series that aims to refactor the
debugfs structure in the i915. Some changes will affect the
debugfs framework as well.
It has gone through a series of offline reviews mainly from
Tvrtko. Even though it hasn't been done publicly, I took the
freedom to add Tvrtko's review.
Thanks Tvrtko and Chris for the review,
Andi
Changelog
=
v5:
- renamed from debugfs_gt_sseu.[ch] to debugfs_sseu.[ch]
- moved i915_rcs_topology from i915_debugfs.c to
gt/debugfs_sseu.c
- added Tvrtko's and Chris r-b.
v4:
- interrupt and sseu debugfs interface are moved to their own
"debugfs_gt_irq" and "debugfs_gt_sseu" files
- reset functions are renamed to reset_show/store
v3:
- better arrangement of what should stay in i915_debugfs and
what needs to be moved under gt/
- more use of the local "uncore" and "i915" variables to improve
readability
v2:
- dropped changes on "drop_caches", they were indeed irrelevant
- improved interrupt info function
drivers/gpu/drm/i915/Makefile| 2 +
drivers/gpu/drm/i915/gt/debugfs_gt.c | 50 ++-
drivers/gpu/drm/i915/gt/debugfs_gt_irq.c | 162 ++
drivers/gpu/drm/i915/gt/debugfs_gt_irq.h | 15 +
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 32 ++
drivers/gpu/drm/i915/gt/debugfs_sseu.c | 294 +
drivers/gpu/drm/i915/gt/debugfs_sseu.h | 16 +
drivers/gpu/drm/i915/i915_debugfs.c | 384 +--
8 files changed, 571 insertions(+), 384 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_irq.c
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_irq.h
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_sseu.c
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_sseu.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2fce8b0040f3..51929d6648e2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,6 +79,8 @@ gt-y += \
gt/debugfs_engines.o \
gt/debugfs_gt.o \
gt/debugfs_gt_pm.o \
+ gt/debugfs_gt_irq.o \
+ gt/debugfs_sseu.o \
gt/gen6_ppgtt.o \
gt/gen7_renderclear.o \
gt/gen8_ppgtt.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index 1de5fbaa1cf9..507fe5dcb360 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -8,9 +8,53 @@
#include "debugfs_engines.h"
#include "debugfs_gt.h"
+#include "debugfs_gt_irq.h"
#include "debugfs_gt_pm.h"
-#include "uc/intel_uc_debugfs.h"
+#include "debugfs_sseu.h"
#include "i915_drv.h"
+#include "intel_gt_pm.h"
+#include "intel_gt_requests.h"
+#include "uc/intel_uc_debugfs.h"
+
+static int reset_show(void *data, u64 *val)
+{
+ struct intel_gt *gt = data;
+ int ret = intel_gt_terminally_wedged(gt);
+
+ switch (ret) {
+ case -EIO:
+ *val = 1;
+ return 0;
+ case 0:
+ *val = 0;
+ return 0;
+ default:
+ return ret;
+ }
+}
+
+static int reset_store(void *data, u64 val)
+{
+ struct intel_gt *gt = data;
+
+ /* Flush any previous reset before applying for a new one */
+ wait_event(gt->reset.queue,
+ !test_bit(I915_RESET_BACKOFF, >reset.flags));
+
+ intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
+ "Manually reset engine mask to %llx", val);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
+
+static void __debugfs_gt_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct debugfs_gt_file files[] = {
+ { "reset", _fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
void debugfs_gt_register(struct intel_gt *gt)
{
@@ -23,8 +67,12 @@ void debugfs_gt_register(struct intel_gt *gt)
if (IS_ERR(root))
return;
+ __debugfs_gt_register(gt, root);
+
debugfs_engines_register(gt, root);
debugfs_gt_pm_register(gt, root);
+ debugfs_gt_register_sseu(gt, root);
+ debugfs_gt_register_irq(gt, root);
intel_uc_debugfs_register(>uc, root);
}
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_irq.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.c
new file mode 100644
index ..8aaf76dfc573
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ *
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev3)
== Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev3) URL : https://patchwork.freedesktop.org/series/75333/ State : warning == Summary == $ dim checkpatch origin/drm-tip db515ae2c79c drm/i915/gt: move remaining debugfs interfaces into gt -:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #119: new file mode 100644 -:443: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #443: FILE: drivers/gpu/drm/i915/gt/debugfs_sseu.c:74: + eu_reg[2 * s + 1] = intel_uncore_read(uncore, + GEN10_SS23_EU_PGCTL_ACK(s)); -:493: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #493: FILE: drivers/gpu/drm/i915/gt/debugfs_sseu.c:124: + eu_reg[2*s] = intel_uncore_read(uncore, ^ -:495: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #495: FILE: drivers/gpu/drm/i915/gt/debugfs_sseu.c:126: + eu_reg[2*s + 1] = intel_uncore_read(uncore, ^ -:533: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #533: FILE: drivers/gpu/drm/i915/gt/debugfs_sseu.c:164: + eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & ^ -:533: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #533: FILE: drivers/gpu/drm/i915/gt/debugfs_sseu.c:164: + eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & ^ -:534: CHECK:SPACING: spaces preferred around that '%' (ctx:VxV) #534: FILE: drivers/gpu/drm/i915/gt/debugfs_sseu.c:165: + eu_mask[ss%2]); ^ total: 0 errors, 1 warnings, 6 checks, 1062 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use per-engine request pools (rev8)
== Series Details == Series: drm/i915: Use per-engine request pools (rev8) URL : https://patchwork.freedesktop.org/series/75415/ State : success == Summary == CI Bug Log - changes from CI_DRM_8238 -> Patchwork_17187 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17187/index.html Known issues Here are the changes found in Patchwork_17187 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-pci-d3-state: - fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([i915#189]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-icl-dsi/igt@i915_pm_...@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17187/fi-icl-dsi/igt@i915_pm_...@basic-pci-d3-state.html [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 Participating hosts (50 -> 35) -- Missing(15): fi-ilk-m540 fi-bdw-5557u fi-bsw-n3050 fi-byt-j1900 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-gdg-551 fi-icl-y fi-skl-lmem fi-kbl-7560u fi-byt-clapper fi-bdw-samus fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8238 -> Patchwork_17187 CI-20190529: 20190529 CI_DRM_8238: 840f70602a47208a2f1e444ba276f412f10e38df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5558: 3b55a816300d80bc5e0b995cd41ee8c8649a1ea2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17187: 148b3f6831c2f10608b2ea796adbfb08f452371e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 148b3f6831c2 drm/i915: Use per-engine request pools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17187/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915/gt: move remaining debugfs interfaces into gt
Quoting Andi Shyti (2020-04-02 18:44:17)
> static const struct drm_info_list i915_debugfs_list[] = {
> {"i915_capabilities", i915_capabilities, 0},
> {"i915_gem_objects", i915_gem_object_info, 0},
> @@ -1862,10 +1484,8 @@ static const struct drm_info_list i915_debugfs_list[]
> = {
> {"i915_llc", i915_llc, 0},
> {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
> {"i915_engine_info", i915_engine_info, 0},
> - {"i915_rcs_topology", i915_rcs_topology, 0},
> {"i915_shrinker_info", i915_shrinker_info, 0},
> {"i915_wa_registers", i915_wa_registers, 0},
> - {"i915_sseu_status", i915_sseu_status, 0},
> {"i915_rps_boost_info", i915_rps_boost_info, 0},
Future passes:
i915_gem_fence_regs
i915_frequency_info [or subsume]
i915_ring_freq_table
i915_swizzle_info
i915_llc
i915_wa_registers?
i915_rps_boost_info
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Re: [Intel-gfx] [PATCH v20 09/10] drm/i915: Restrict qgv points which don't have enough bandwidth.
On Thu, Mar 26, 2020 at 08:36:57PM +0200, Stanislav Lisovskiy wrote: > According to BSpec 53998, we should try to > restrict qgv points, which can't provide > enough bandwidth for desired display configuration. > > Currently we are just comparing against all of > those and take minimum(worst case). > > v2: Fixed wrong PCode reply mask, removed hardcoded > values. > > v3: Forbid simultaneous legacy SAGV PCode requests and > restricting qgv points. Put the actual restriction > to commit function, added serialization(thanks to Ville) > to prevent commit being applied out of order in case of > nonblocking and/or nomodeset commits. > > v4: > - Minor code refactoring, fixed few typos(thanks to James Ausmus) > - Change the naming of qgv point > masking/unmasking functions(James Ausmus). > - Simplify the masking/unmasking operation itself, > as we don't need to mask only single point per request(James Ausmus) > - Reject and stick to highest bandwidth point if SAGV > can't be enabled(BSpec) > > v5: > - Add new mailbox reply codes, which seems to happen during boot > time for TGL and indicate that QGV setting is not yet available. > > v6: > - Increase number of supported QGV points to be in sync with BSpec. > > v7: - Rebased and resolved conflict to fix build failure. > - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus) > > v8: - Don't report an error if we can't restrict qgv points, as SAGV > can be disabled by BIOS, which is completely legal. So don't > make CI panic. Instead if we detect that there is only 1 QGV > point accessible just analyze if we can fit the required bandwidth > requirements, but no need in restricting. > > v9: - Fix wrong QGV transition if we have 0 planes and no SAGV > simultaneously. > > v10: - Fix CDCLK corruption, because of global state getting serialized >without modeset, which caused copying of non-calculated cdclk >to be copied to dev_priv(thanks to Ville for the hint). > > v11: - Remove unneeded headers and spaces(Matthew Roper) > - Remove unneeded intel_qgv_info qi struct from bw check and zero >out the needed one(Matthew Roper) > - Changed QGV error message to have more clear meaning(Matthew Roper) > - Use state->modeset_set instead of any_ms(Matthew Roper) > - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used > - Keep using crtc_state->hw.active instead of .enable(Matthew Roper) > - Moved unrelated changes to other patch(using latency as parameter >for plane wm calculation, moved to SAGV refactoring patch) > > v12: - Fix rebase conflict with own temporary SAGV/QGV fix. > - Remove unnecessary mask being zero check when unmasking >qgv points as this is completely legal(Matt Roper) > - Check if we are setting the same mask as already being set >in hardware to prevent error from PCode. > - Fix error message when restricting/unrestricting qgv points >to "mask/unmask" which sounds more accurate(Matt Roper) > - Move sagv status setting to icl_get_bw_info from atomic check >as this should be calculated only once.(Matt Roper) > - Edited comments for the case when we can't enable SAGV and >use only 1 QGV point with highest bandwidth to be more >understandable.(Matt Roper) > > v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä) > - Changed comment for zero new_mask in qgv points masking function >to better reflect reality(Ville Syrjälä) > - Simplified bit mask operation in qgv points masking function >(Ville Syrjälä) > - Moved intel_qgv_points_mask closer to gen11 SAGV disabling, >however this still can't be under modeset condition(Ville Syrjälä) > - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask >(Ville Syrjälä) > - Extracted PCode changes to separate patch.(Ville Syrjälä) > - Now treat num_planes 0 same as 1 to avoid confusion and >returning max_bw as 0, which would prevent choosing QGV >point having max bandwidth in case if SAGV is not allowed, >as per BSpec(Ville Syrjälä) > - Do the actual qgv_points_mask swap in the same place as >all other global state parts like cdclk are swapped. >In the next patch, this all will be moved to bw state as >global state, once new global state patch series from Ville >lands > > v14: - Now using global state to serialize access to qgv points > - Added global state locking back, otherwise we seem to read >bw state in a wrong way. > > v15: - Added TODO comment for near atomic global state locking in >bw code. > > v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed >with Jani Nikula. > - Take bw_state_changed flag into use. > > v17: - Moved qgv point related
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use per-engine request pools (rev7)
== Series Details == Series: drm/i915: Use per-engine request pools (rev7) URL : https://patchwork.freedesktop.org/series/75415/ State : success == Summary == CI Bug Log - changes from CI_DRM_8238 -> Patchwork_17186 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17186/index.html Changes --- No changes found Participating hosts (50 -> 38) -- Missing(12): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-gdg-551 fi-ivb-3770 fi-bsw-kefka fi-blb-e6850 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8238 -> Patchwork_17186 CI-20190529: 20190529 CI_DRM_8238: 840f70602a47208a2f1e444ba276f412f10e38df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5558: 3b55a816300d80bc5e0b995cd41ee8c8649a1ea2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17186: 547b54d56387e36ca228f75199a116e9f838115c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 547b54d56387 drm/i915: Use per-engine request pools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17186/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v20 08/10] drm/i915: Rename bw_state to new_bw_state
On Thu, Mar 26, 2020 at 08:10:03PM +0200, Stanislav Lisovskiy wrote:
> That is a preparation patch before next one where we
> introduce old_bw_state and a bunch of other changes
> as well.
> In a review comment it was suggested to split out
> at least that renaming into a separate patch, what
> is done here.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index a8b2038db4d2..d16771dd2b10 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -418,7 +418,7 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> - struct intel_bw_state *bw_state = NULL;
> + struct intel_bw_state *new_bw_state = NULL;
> unsigned int data_rate, max_data_rate;
> unsigned int num_active_planes;
> struct intel_crtc *crtc;
> @@ -447,29 +447,29 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> old_active_planes == new_active_planes)
> continue;
>
> - bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> + new_bw_state = intel_atomic_get_bw_state(state);
^
Pls remove the spurious space while at it.
Reviewed-by: Ville Syrjälä
> + if (IS_ERR(new_bw_state))
> + return PTR_ERR(new_bw_state);
>
> - bw_state->data_rate[crtc->pipe] = new_data_rate;
> - bw_state->num_active_planes[crtc->pipe] = new_active_planes;
> + new_bw_state->data_rate[crtc->pipe] = new_data_rate;
> + new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
>
> drm_dbg_kms(_priv->drm,
> "pipe %c data rate %u num active planes %u\n",
> pipe_name(crtc->pipe),
> - bw_state->data_rate[crtc->pipe],
> - bw_state->num_active_planes[crtc->pipe]);
> + new_bw_state->data_rate[crtc->pipe],
> + new_bw_state->num_active_planes[crtc->pipe]);
> }
>
> - if (!bw_state)
> + if (!new_bw_state)
> return 0;
>
> - ret = intel_atomic_lock_global_state(_state->base);
> + ret = intel_atomic_lock_global_state(_bw_state->base);
> if (ret)
> return ret;
>
> - data_rate = intel_bw_data_rate(dev_priv, bw_state);
> - num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
> + data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
> + num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
>
> max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
>
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v20 07/10] drm/i915: Added required new PCode commands
On Thu, Mar 26, 2020 at 08:10:02PM +0200, Stanislav Lisovskiy wrote:
> We need a new PCode request commands and reply codes
> to be added as a prepartion patch for QGV points
> restricting for new SAGV support.
>
> v2: - Extracted those changes into separate patch
> (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4
> drivers/gpu/drm/i915/intel_sideband.c | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c53fe918be6..1a61db746c7e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8994,6 +8994,7 @@ enum {
> #define GEN7_PCODE_ILLEGAL_DATA 0x3
> #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
> #define GEN11_PCODE_LOCKED 0x6
> +#define GEN11_PCODE_REJECTED 0x11
> #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> #define GEN6_PCODE_READ_RC6VIDS0x5
> @@ -9015,6 +9016,7 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO(0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) <<
> 16) | (0x1 << 8))
> +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG0xe
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP0x11
> #define HSW_PCODE_DE_WRITE_FREQ_REQ0x17
> @@ -9027,6 +9029,8 @@ enum {
> #define GEN9_SAGV_IS_DISABLED0x1
> #define GEN9_SAGV_ENABLE 0x3
> #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> +#define GEN11_PCODE_POINTS_RESTRICTED0x0
> +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
What are these? The indentation makes me thingk they are new commands,
but the placement totally disagrees with that.
> #define GEN6_PCODE_DATA _MMIO(0x138128)
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> b/drivers/gpu/drm/i915/intel_sideband.c
> index 1447e7516cb7..1e7dd6b6f103 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -370,6 +370,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
> return -ENXIO;
> case GEN11_PCODE_LOCKED:
> return -EBUSY;
> + case GEN11_PCODE_REJECTED:
> + return -EACCES;
> case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> return -EOVERFLOW;
> default:
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v20 06/10] drm/i915: Add proper SAGV support for TGL+
On Thu, Mar 26, 2020 at 08:39:59PM +0200, Stanislav Lisovskiy wrote: > Let's refactor the whole SAGV logic, moving > the main calculations from intel_can_enable_sagv > to intel_compute_sagv_mask, which also handles > this in a unified way calling gen specific > functions to evaluate if SAGV is allowed for > each crtc. If crtc sagv mask have been changed > we serialize access and modify global state. > > intel_can_enable_sagv now uses bw_state which > stores all information related to SAGV and > is now a trivial helper. > > v2: > - Rework watermark calculation algorithm to > attempt to calculate Level 0 watermark > with added sagv block time latency and > check if it fits in DBuf in order to > determine if SAGV can be enabled already > at this stage, just as BSpec 49325 states. > if that fails rollback to usual Level 0 > latency and disable SAGV. > - Remove unneeded tabs(James Ausmus) > > v3: Rebased the patch > > v4: - Added back interlaced check for Gen12 and > added separate function for TGL SAGV check > (thanks to James Ausmus for spotting) > - Removed unneeded gen check > - Extracted Gen12 SAGV decision making code > to a separate function from skl_compute_wm > > v5: - Added SAGV global state to dev_priv, because > we need to track all pipes, not only those > in atomic state. Each pipe has now correspondent > bit mask reflecting, whether it can tolerate > SAGV or not(thanks to Ville Syrjala for suggestions). > - Now using active flag instead of enable in crc > usage check. > > v6: - Fixed rebase conflicts > > v7: - kms_cursor_legacy seems to get broken because of multiple memcpy > calls when copying level 0 water marks for enabled SAGV, to > fix this now simply using that field right away, without copying, > for that introduced a new wm_level accessor which decides which > wm_level to return based on SAGV state. > > v8: - Protect crtc_sagv_mask same way as we do for other global state > changes: i.e check if changes are needed, then grab all crtc locks > to serialize the changes(Ville Syrjälä) > - Add crtc_sagv_mask caching in order to avoid needless recalculations > (Matthew Roper) > - Put back Gen12 SAGV switch in order to get it enabled in separate > patch(Matthew Roper) > - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper) > - Check if there are no active pipes in intel_can_enable_sagv > instead of platform specific functions(Matthew Roper), same > for intel_has_sagv check. > > v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä) > - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä) > - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask > - Extracted skl_plane_wm_level function and passing latency to > separate patches(Ville Syrjälä) > - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm > (Ville Syrjälä) > - Now using simple assignment for sagv_wm0 as it contains only > pod types and no pointers(Ville Syrjälä) > - Fixed intel_can_enable_sagv not to do double duty, now it only > check SAGV bits by ANDing those between local and global state. > The SAGV masks are now computed after watermarks are available, > in order to be able to figure out if ddb ranges are fitting nicely. > (Ville Syrjälä) > - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic > when using skl_plane_wm_level accessor, as we had previously for > Gen11+ color plane and regular wm levels, so probably both > has to be recalculated with additional SAGV block time for Level 0. > > v10: - Starting to use new global state for storing pipe_sagv_mask > > v11: - Fixed rebase conflict with recent drm-tip > - Check if we really need to recalculate SAGV mask, otherwise >bail out without making any changes. > - Use cached SAGV result, instead of recalculating it everytime, >if bw_state hasn't changed. > > v12: - Removed WARN from intel_can_enable_sagv, in some of the commits >if we don't recalculated watermarks, bw_state is not recalculated, >thus leading to SAGV state not recalculated by the commit state, >which is still calling intel_can_enable_sagv function. Fix that >by just analyzing the current global bw_state object - because >we simply have no other objects related to that. > > v13: - Rebased, fixed warnings regarding long lines > - Changed function call sites from intel_atomic_bw* to >intel_wb_* as was suggested.(Jani Nikula) > - Taken ddb_state_changed and bw_state_changed into use. > > v14: - total_affected_planes is no longer needed to check for ddb changes, >just as active_pipe_changes. > > v15: - Fixed stupid mistake with uninitialized crtc in >skl_compute_sagv_mask. > > v16: -
[Intel-gfx] [PATCH] drm/i915: Use per-engine request pools
Add a per-engine request mempool so that we should always have a couple
of requests available for powermanagement allocations from tricky
contexts. These reserves are expected to be only used for kernel
contexts when barriers must be emitted [almost] without fail.
When using the mempool, requests are first allocated from the global
slab cache (utilising all the per-cpu lockless freelists and caches) and
only if that is empty and cannot be filled under the gfp_t do we
fallback to using the per-engine cache of recently freed requests. For
our use cases, this will never be empty for long as there will always be
at least the previous powermanagent request to reuse.
The downside is that this is quite a bulky addition and abstraction to
use, but it will ensure that we never fail to park the engine due to
oom.
An alternative to using the mempool would be to opencode a single
reserved slot (with xchg for the management in emergency alloc and
free), so long as we are confident in our design that we only need the
single reserve request.
v2: Only use the mempool for nonblocking allocations which are not
expected to fail.
v3: mempool harbours a grudge against slab caches that denies the use of
constructors and falls foul of TYPESAFE_BY_RCU rules. Use custom
alloc/free callbacks so that it neither hits a VM_BUG_ON nor poisons the
RCU'ed element.
v4: Beware the eternal references in dma-resv keeping the requests alive.
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Tvrtko Ursulin
Reviewed-by: Janusz Krzysztofik #v2
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 37
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++
drivers/gpu/drm/i915/gt/mock_engine.c| 5 +++
drivers/gpu/drm/i915/i915_request.c | 20 +++
drivers/gpu/drm/i915/i915_request.h | 2 ++
7 files changed, 69 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b469de0dd9b6..23747996a1ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -324,6 +324,9 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+int intel_engine_init_request_pool(struct intel_engine_cs *engine);
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine);
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 843cb6f2f696..5ade585c29e8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -431,7 +431,13 @@ void intel_engines_free(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
+ /* Free the requests! dma-resv keeps fences around for an eternity */
+ rcu_barrier();
+
for_each_engine(engine, gt, id) {
+ /* Must be kept until after all requests are freed! */
+ intel_engine_fini_request_pool(engine);
+
kfree(engine);
gt->engine[id] = NULL;
}
@@ -602,6 +608,30 @@ static int init_status_page(struct intel_engine_cs *engine)
return ret;
}
+static void *__mempool_alloc_slab(gfp_t gfp, void *data)
+{
+ return kmem_cache_alloc(data, gfp);
+}
+
+static void __mempool_free_slab(void *element, void *data)
+{
+ kmem_cache_free(data, element);
+}
+
+int intel_engine_init_request_pool(struct intel_engine_cs *engine)
+{
+ /* NB mempool_init_slab() does not handle TYPESAFE_BY_RCU */
+ return mempool_init(>request_pool,
+ INTEL_ENGINE_REQUEST_POOL_RESERVED,
+ __mempool_alloc_slab, __mempool_free_slab,
+ i915_request_slab_cache());
+}
+
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine)
+{
+ mempool_exit(>request_pool);
+}
+
static int engine_setup_common(struct intel_engine_cs *engine)
{
int err;
@@ -612,6 +642,9 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
if (err)
return err;
+ if (intel_engine_init_request_pool(engine))
+ goto err_status_page;
+
intel_engine_init_active(engine, ENGINE_PHYSICAL);
intel_engine_init_breadcrumbs(engine);
intel_engine_init_execlists(engine);
@@ -630,6 +663,10 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
intel_engine_init_ctx_wa(engine);
return 0;
+
+err_status_page:
+ cleanup_status_page(engine);
+ return -ENOMEM;
}
struct measure_breadcrumb {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index
[Intel-gfx] [PATCH] drm/i915: Use per-engine request pools
Add a per-engine request mempool so that we should always have a couple
of requests available for powermanagement allocations from tricky
contexts. These reserves are expected to be only used for kernel
contexts when barriers must be emitted [almost] without fail.
When using the mempool, requests are first allocated from the global
slab cache (utilising all the per-cpu lockless freelists and caches) and
only if that is empty and cannot be filled under the gfp_t do we
fallback to using the per-engine cache of recently freed requests. For
our use cases, this will never be empty for long as there will always be
at least the previous powermanagent request to reuse.
The downside is that this is quite a bulky addition and abstraction to
use, but it will ensure that we never fail to park the engine due to
oom.
v2: Only use the mempool for nonblocking allocations which are not
expected to fail.
v3: mempool harbours a grudge against slab caches that denies the use of
constructors and falls foul of TYPESAFE_BY_RCU rules. Use custom
alloc/free callbacks so that it neither hits a VM_BUG_ON nor poisons the
RCU'ed element.
v4: Beware the eternal references in dma-resv keeping the requests alive.
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Tvrtko Ursulin
Reviewed-by: Janusz Krzysztofik #v2
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 38
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++
drivers/gpu/drm/i915/gt/mock_engine.c| 5 +++
drivers/gpu/drm/i915/i915_request.c | 20 +++
drivers/gpu/drm/i915/i915_request.h | 2 ++
7 files changed, 70 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b469de0dd9b6..23747996a1ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -324,6 +324,9 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+int intel_engine_init_request_pool(struct intel_engine_cs *engine);
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine);
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 843cb6f2f696..e0db65807f2a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -431,7 +431,14 @@ void intel_engines_free(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
+ /* Free the requests! dma-resv keeps fences around for an eternity */
+ i915_gem_drain_freed_objects(gt->i915);
+ rcu_barrier();
+
for_each_engine(engine, gt, id) {
+ /* Must be kept until after all requests are freed! */
+ intel_engine_fini_request_pool(engine);
+
kfree(engine);
gt->engine[id] = NULL;
}
@@ -602,6 +609,30 @@ static int init_status_page(struct intel_engine_cs *engine)
return ret;
}
+static void *__mempool_alloc_slab(gfp_t gfp, void *data)
+{
+ return kmem_cache_alloc(data, gfp);
+}
+
+static void __mempool_free_slab(void *element, void *data)
+{
+ kmem_cache_free(data, element);
+}
+
+int intel_engine_init_request_pool(struct intel_engine_cs *engine)
+{
+ /* NB mempool_init_slab() does not handle TYPESAFE_BY_RCU */
+ return mempool_init(>request_pool,
+ INTEL_ENGINE_REQUEST_POOL_RESERVED,
+ __mempool_alloc_slab, __mempool_free_slab,
+ i915_request_slab_cache());
+}
+
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine)
+{
+ mempool_exit(>request_pool);
+}
+
static int engine_setup_common(struct intel_engine_cs *engine)
{
int err;
@@ -612,6 +643,9 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
if (err)
return err;
+ if (intel_engine_init_request_pool(engine))
+ goto err_status_page;
+
intel_engine_init_active(engine, ENGINE_PHYSICAL);
intel_engine_init_breadcrumbs(engine);
intel_engine_init_execlists(engine);
@@ -630,6 +664,10 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
intel_engine_init_ctx_wa(engine);
return 0;
+
+err_status_page:
+ cleanup_status_page(engine);
+ return -ENOMEM;
}
struct measure_breadcrumb {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..0db03215127b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -13,6 +13,7 @@
#include
#include
#include
[Intel-gfx] [PATCH] drm/i915: Use per-engine request pools
Add a per-engine request mempool so that we should always have a couple
of requests available for powermanagement allocations from tricky
contexts. These reserves are expected to be only used for kernel
contexts when barriers must be emitted [almost] without fail.
When using the mempool, requests are first allocated from the global
slab cache (utilising all the per-cpu lockless freelists and caches) and
only if that is empty and cannot be filled under the gfp_t do we
fallback to using the per-engine cache of recently freed requests. For
our use cases, this will never be empty for long as there will always be
at least the previous powermanagent request to reuse.
The downside is that this is quite a bulky addition and abstraction to
use, but it will ensure that we never fail to park the engine due to
oom.
v2: Only use the mempool for nonblocking allocations which are not
expected to fail.
v3: mempool harbours a grudge against slab caches that denies the use of
constructors and falls foul of TYPESAFE_BY_RCU rules. Use custom
alloc/free callbacks so that it neither hits a VM_BUG_ON nor poisons the
RCU'ed element.
v4: Beware the eternal references in dma-resv keeping the requests alive.
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Tvrtko Ursulin
Reviewed-by: Janusz Krzysztofik #v2
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 38
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++
drivers/gpu/drm/i915/gt/mock_engine.c| 5 +++
drivers/gpu/drm/i915/i915_request.c | 20 +++
drivers/gpu/drm/i915/i915_request.h | 2 ++
7 files changed, 70 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b469de0dd9b6..23747996a1ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -324,6 +324,9 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+int intel_engine_init_request_pool(struct intel_engine_cs *engine);
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine);
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 843cb6f2f696..301fb33b4cf5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -431,7 +431,14 @@ void intel_engines_free(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
+ /* Free the requests! dma-resv keeps fences around for an eternity */
+ i915_gem_drain_freed_objects(engine->i915);
+ rcu_barrier();
+
for_each_engine(engine, gt, id) {
+ /* Must be kept until after all requests are freed! */
+ intel_engine_fini_request_pool(engine);
+
kfree(engine);
gt->engine[id] = NULL;
}
@@ -602,6 +609,30 @@ static int init_status_page(struct intel_engine_cs *engine)
return ret;
}
+static void *__mempool_alloc_slab(gfp_t gfp, void *data)
+{
+ return kmem_cache_alloc(data, gfp);
+}
+
+static void __mempool_free_slab(void *element, void *data)
+{
+ kmem_cache_free(data, element);
+}
+
+int intel_engine_init_request_pool(struct intel_engine_cs *engine)
+{
+ /* NB mempool_init_slab() does not handle TYPESAFE_BY_RCU */
+ return mempool_init(>request_pool,
+ INTEL_ENGINE_REQUEST_POOL_RESERVED,
+ __mempool_alloc_slab, __mempool_free_slab,
+ i915_request_slab_cache());
+}
+
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine)
+{
+ mempool_exit(>request_pool);
+}
+
static int engine_setup_common(struct intel_engine_cs *engine)
{
int err;
@@ -612,6 +643,9 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
if (err)
return err;
+ if (intel_engine_init_request_pool(engine))
+ goto err_status_page;
+
intel_engine_init_active(engine, ENGINE_PHYSICAL);
intel_engine_init_breadcrumbs(engine);
intel_engine_init_execlists(engine);
@@ -630,6 +664,10 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
intel_engine_init_ctx_wa(engine);
return 0;
+
+err_status_page:
+ cleanup_status_page(engine);
+ return -ENOMEM;
}
struct measure_breadcrumb {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..0db03215127b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -13,6 +13,7 @@
#include
#include
#include
Re: [Intel-gfx] [PATCH v20 04/10] drm/i915: Add intel_atomic_get_bw_*_state helpers
On Thu, Apr 02, 2020 at 07:20:59PM +0300, Ville Syrjälä wrote:
> On Thu, Mar 26, 2020 at 08:09:59PM +0200, Stanislav Lisovskiy wrote:
> > Add correspondent helpers to be able to get old/new bandwidth
> > global state object.
> >
> > v2: - Fixed typo in function call
> > v3: - Changed new functions naming to use convention proposed
> > by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
> > v4: - Change function naming back to intel_atomic* pattern,
> > was decided to rename in a separate patch series.
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 29 -
> > drivers/gpu/drm/i915/display/intel_bw.h | 9
> > 2 files changed, 37 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 58b264bc318d..a8b2038db4d2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -374,7 +374,34 @@ static unsigned int intel_bw_data_rate(struct
> > drm_i915_private *dev_priv,
> > return data_rate;
> > }
> >
> > -static struct intel_bw_state *
> > +struct intel_bw_state *
> > +intel_atomic_get_bw_old_state(struct intel_atomic_state *state)
Also these names aren't consistent wrt. existing practices.
Should be intel_atomic_get_{new,old}_bw_state()
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_global_state *bw_state;
> > +
> > + bw_state = intel_atomic_get_old_global_obj_state(state,
> > _priv->bw_obj);
> > + if (IS_ERR(bw_state))
> > + return ERR_CAST(bw_state);
>
> These can't return an error.
>
> > +
> > + return to_intel_bw_state(bw_state);
> > +}
> > +
> > +struct intel_bw_state *
> > +intel_atomic_get_bw_new_state(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_global_state *bw_state;
> > +
> > + bw_state = intel_atomic_get_new_global_obj_state(state,
> > _priv->bw_obj);
> > +
> > + if (IS_ERR(bw_state))
> > + return ERR_CAST(bw_state);
> > +
> > + return to_intel_bw_state(bw_state);
> > +}
> > +
> > +struct intel_bw_state *
> > intel_atomic_get_bw_state(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > b/drivers/gpu/drm/i915/display/intel_bw.h
> > index a8aa7624c5aa..fe6579c952f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -24,6 +24,15 @@ struct intel_bw_state {
> >
> > #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
> >
> > +struct intel_bw_state *
> > +intel_atomic_get_bw_old_state(struct intel_atomic_state *state);
> > +
> > +struct intel_bw_state *
> > +intel_atomic_get_bw_new_state(struct intel_atomic_state *state);
> > +
> > +struct intel_bw_state *
> > +intel_atomic_get_bw_state(struct intel_atomic_state *state);
> > +
> > void intel_bw_init_hw(struct drm_i915_private *dev_priv);
> > int intel_bw_init(struct drm_i915_private *dev_priv);
> > int intel_bw_atomic_check(struct intel_atomic_state *state);
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH v20 05/10] drm/i915: Extract gen specific functions from intel_can_enable_sagv
On Thu, Mar 26, 2020 at 08:10:00PM +0200, Stanislav Lisovskiy wrote:
> Addressing one of the comments, recommending to extract platform
> specific code from intel_can_enable_sagv as a preparation, before
> we are going to add support for tgl+.
>
> Current code in intel_can_enable_sagv is valid only for skl,
> so this patch adds also proper support for icl, subsequent
> patches will add support for tgl+, combined with other required
> changes.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/intel_pm.c | 89 ++---
> 1 file changed, 61 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f8d62d1977ac..64193b098175 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3757,41 +3757,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +static bool icl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
icl_crtc_can_enable_sagv()/etc. would be more consistent with existing
practices. crtc_state can be const.
> {
> - struct drm_device *dev = state->base.dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
IMO just remove this 'dev' variable.
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *crtc;
> struct intel_plane *plane;
> - struct intel_crtc_state *crtc_state;
> - enum pipe pipe;
> + struct intel_plane_state *plane_state;
const
> int level, latency;
>
> - if (!intel_has_sagv(dev_priv))
> - return false;
> + crtc = to_intel_crtc(crtc_state->uapi.crtc);
Initialize when declaring.
>
> - /*
> - * If there are no active CRTCs, no additional checks need be performed
> - */
> - if (hweight8(state->active_pipes) == 0)
> - return true;
> -
> - /*
> - * SKL+ workaround: bspec recommends we disable SAGV when we have
> - * more then one pipe enabled
> - */
> - if (hweight8(state->active_pipes) > 1)
> - return false;
> -
> - /* Since we're now guaranteed to only have one active CRTC... */
> - pipe = ffs(state->active_pipes) - 1;
> - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> - crtc_state = to_intel_crtc_state(crtc->base.state);
We seem to be missing a hw.active check.
> -
> - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> + DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
> + pipe_name(crtc->pipe));
> return false;
> + }
>
> - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
> crtc_state) {
> struct skl_plane_wm *wm =
> _state->wm.skl.optimal.planes[plane->id];
>
> @@ -3807,7 +3790,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
> latency = dev_priv->wm.skl_latency[level];
>
> if (skl_needs_memory_bw_wa(dev_priv) &&
> - plane->base.state->fb->modifier ==
> + plane_state->uapi.fb->modifier ==
> I915_FORMAT_MOD_X_TILED)
> latency += 15;
>
> @@ -3816,8 +3799,58 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
>* incur memory latencies higher than sagv_block_time_us we
>* can't enable SAGV.
>*/
> - if (latency < dev_priv->sagv_block_time_us)
> + if (latency < dev_priv->sagv_block_time_us) {
> + DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV
> for pipe %c\n",
> + latency, dev_priv->sagv_block_time_us,
> pipe_name(crtc->pipe));
> return false;
How much noise will these debugs generate?
> + }
> + }
> +
> + return true;
> +}
> +
> +static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_atomic_state *state =
> to_intel_atomic_state(crtc_state->uapi.state);
> +
> + /*
> + * It has been recommended that for Gen 9 we switch SAGV off when
> + * multiple pipes are used.
> + */
> + if (hweight8(state->active_pipes) > 1)
> + return false;
> +
> + /*
> + * Besides active pipe limitation, rest of checks pretty much match ICL
> + * so no need to duplicate code
> + */
> + return icl_can_enable_sagv_on_pipe(crtc_state);
> +}
> +
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
Pls don't add needless 'dev' variables.
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc;
> +
Re: [Intel-gfx] [PATCH v20 02/10] drm/i915: Eliminate magic numbers "0" and "1" from color plane
On Thu, Apr 02, 2020 at 07:28:43PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 02, 2020 at 07:17:52PM +0300, Ville Syrjälä wrote:
> > On Thu, Mar 26, 2020 at 08:09:57PM +0200, Stanislav Lisovskiy wrote:
> > > According to many computer science sources - magic values
> > > in code _are_ _bad_. For many reasons: the reason is that "0"
> > > or "1" or whatever magic values confuses and doesn't give any
> > > info why this parameter is this value and what it's meaning
> > > is.
> > > I renamed "0" to COLOR_PLANE_Y and "1" to COLOR_PLANE_UV,
> > > because we in fact already use this naming in many other places
> > > and function names, when dealing with color planes.
> >
> > And now it's incosistent with all the rest of the codebase :(
>
> ]I think functions like func(0,1,2) is more than ugly.
>
> I can find dozens of sources from credible people stating why it's
> wrong.
>
> If the existing code base is inspiring people to do it that way
> - then it's wrong.
>
> And I honestly don't even know what is more stupid here:
> passing magic numbers into functions, making it look non-obvious
> or arguing about that. Kind of competition.
>
> I think we have also enum values passed into functions in our
> code and that seems fine(may be because that code wasn't written by me?).
>
> For instance you do use PIPE_A, PIPE_B instead of 0,1,2 right?
color_plane is just an index into the fb metadata. It's not a specific
named thing as such. Again, if we want to introduce some new convention
for this stuff we should do it across the whole driver (and probably
also drm core) otherewise you're just introducing inconsistencies
between different parts of the codebase. Different conventions between
different parts just increases the load on the poor brain when you have
to convert between thenm to figure out what's going on.
>
> Or sure I can find another examples.
>
>
> >
> > >
> > > Signed-off-by: Stanislav Lisovskiy
> > > ---
> > > .../drm/i915/display/intel_display_types.h| 5 +++
> > > drivers/gpu/drm/i915/intel_pm.c | 40 +--
> > > 2 files changed, 25 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 176ab5f1e867..523e0444b373 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -682,6 +682,11 @@ struct skl_plane_wm {
> > > bool is_planar;
> > > };
> > >
> > > +enum color_plane {
> > > + COLOR_PLANE_Y,
> > > + COLOR_PLANE_UV
> > > +};
> > > +
> > > struct skl_pipe_wm {
> > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > };
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index b632b6bb9c3e..9e9a4612d842 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4013,7 +4013,7 @@ static int skl_compute_wm_params(const struct
> > > intel_crtc_state *crtc_state,
> > >int width, const struct drm_format_info
> > > *format,
> > >u64 modifier, unsigned int rotation,
> > >u32 plane_pixel_rate, struct skl_wm_params *wp,
> > > - int color_plane);
> > > + enum color_plane);
> > > static void skl_compute_plane_wm(const struct intel_crtc_state
> > > *crtc_state,
> > >int level,
> > >unsigned int latency,
> > > @@ -4035,7 +4035,7 @@ skl_cursor_allocation(const struct intel_crtc_state
> > > *crtc_state,
> > > drm_format_info(DRM_FORMAT_ARGB),
> > > DRM_FORMAT_MOD_LINEAR,
> > > DRM_MODE_ROTATE_0,
> > > - crtc_state->pixel_rate, , 0);
> > > + crtc_state->pixel_rate, , COLOR_PLANE_Y);
> > > drm_WARN_ON(_priv->drm, ret);
> > >
> > > for (level = 0; level <= max_level; level++) {
> > > @@ -4431,7 +4431,7 @@ static u8 skl_compute_dbuf_slices(const struct
> > > intel_crtc_state *crtc_state,
> > > static u64
> > > skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
> > >const struct intel_plane_state *plane_state,
> > > - int color_plane)
> > > + enum color_plane color_plane)
> > > {
> > > struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > @@ -4446,7 +4446,7 @@ skl_plane_relative_data_rate(const struct
> > > intel_crtc_state *crtc_state,
> > > if (plane->id == PLANE_CURSOR)
> > > return 0;
> > >
> > > - if (color_plane == 1 &&
> > > + if (color_plane == COLOR_PLANE_UV &&
> > > !intel_format_info_is_yuv_semiplanar(fb->format,
Re: [Intel-gfx] [PATCH v3 2/3] drm/i915: Add i915_lpsp_info debugfs
On 2020-04-02 at 20:59:21 +0530, Manna, Animesh wrote:
>
> On 02-04-2020 18:15, Anshuman Gupta wrote:
> >On 2020-04-01 at 21:23:28 +0530, Manna, Animesh wrote:
> >thanks animesh for review!
> >>On 31-03-2020 17:07, Anshuman Gupta wrote:
> >>>New i915_pm_lpsp igt solution approach relies on connector specific
> >>>debugfs attribute i915_lpsp_info, it exposes whether an output is
> >>>capable of driving lpsp and exposes lpsp enablement info.
> >>>
> >>>v2:
> >>>- CI fixup.
> >>>v3:
> >>>- register i915_lpsp_info only for supported connector. [Jani]
> >>>- use intel_display_power_well_is_enabled() instead of looking
> >>> inside power_well count. [Jani]
> >>>- fixes the lpsp capable conditional logic. [Jani]
> >>>- combined the lpsp capable and enable info. [Jani]
> >>>
> >>>Signed-off-by: Anshuman Gupta
> >>>---
> >>> .../drm/i915/display/intel_display_debugfs.c | 124 ++
> >>> .../drm/i915/display/intel_display_power.h| 2 +
> >>> 2 files changed, 126 insertions(+)
> >>>
> >>>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >>>b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >>>index 424f4e52f783..b185c4617468 100644
> >>>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >>>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >>>@@ -9,6 +9,7 @@
> >>> #include "i915_debugfs.h"
> >>> #include "intel_csr.h"
> >>> #include "intel_display_debugfs.h"
> >>>+#include "intel_display_power.h"
> >>> #include "intel_display_types.h"
> >>> #include "intel_dp.h"
> >>> #include "intel_fbc.h"
> >>>@@ -611,6 +612,98 @@ static void intel_hdcp_info(struct seq_file *m,
> >>> seq_puts(m, "\n");
> >>> }
> >>>+#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP capable\n") :
> >>>seq_puts(m, "LPSP incapable\n"))
> >>>+#define LPSP_ENABLE(COND) (COND ? seq_puts(m, "LPSP enabled\n") :
> >>>seq_puts(m, "LPSP disabled\n"))
> >>>+
> >>>+/* LVDS also an embedded panel but we are not interested in it */
> >>>+static bool intel_have_embedded_panel(struct drm_connector *connector)
> >>>+{
> >>>+ return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> >>>+ connector->connector_type == DRM_MODE_CONNECTOR_eDP;
> >>>+}
> >>>+
> >>>+static bool intel_have_gen9_lpsp_panel(struct drm_connector *connector)
> >>>+{
> >>>+ return intel_have_embedded_panel(connector) ||
> >>>+ connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort;
> >>>+}
> >>>+
> >>>+static bool intel_have_lpsp_supported_panel(struct drm_connector
> >>>*connector)
> >>>+{
> >>>+ return intel_have_gen9_lpsp_panel(connector) ||
> >>>+ connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> >>>+ connector->connector_type == DRM_MODE_CONNECTOR_HDMIB;
> >>>+}
> >>This function will pass for every platform for almost all
> >>(EDP/MIPI/DP/HDMI) connector type even if not supported ...rt?
> >Above function will only used to add i915_lpsp_info for DP/MIPI/DP/HDMI
> >connecotr,
> >It can nuke it with condition below condition.
> > return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> > connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
> > connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> > connector->connector_type == DRM_MODE_CONNECTOR_HDMIB;
> >So in order to avoid such big condition i had prefred the above function,
> >please suggest a better readable way.
> >use condition as such, function name change or using a macro.
> >>Apart from that I did not understand the purpose of above functions.
> >My thought process was to break longer conditional if chunk in static
> >function,
> >please suggest if u are in favour of nuke these functions, or if u want to
> >suggest
> >a better name.
> >>Can we have a single function to check the connector is supported lpsp or
> >>not.
> >>
> >>static bool is_lpsp_supported(struct drm_connector *connector)
> >>
> >>In function definition we can check for platform first, then check
> >>connector_type and return true/false.
> >i915_lpsp_info_show is first checking the gen and then platform, after
> >checking
> >platform it needs to check DDI port and connector based upon platform lpsp
> >block diagram
> >in order to evaluate lpsp capablity, followed by power well check to
> >evlauate lpsp
> >enabled.
> >if i understand you are suggesting to break above two parts,
> >is_lpsp_supported()
> >is_lpsp_capable()
> >but by breaking above we would require to check gen and platfrom twice
> >which can be avoided by combining above.
>
> No, as I mentioned below, both looks to me same, better to have one function.
>
> if (is_lpsp_supported())
> then add debugfs-entry.
>
> Inside is_lpsp_supported() check everything related to connector. And in
> i915_lpsp_info_show() function check only power-well status and print lpsp is
> enabled or disabled
>
Lets say we have a function to check lpsp
Re: [Intel-gfx] [PATCH v20 02/10] drm/i915: Eliminate magic numbers "0" and "1" from color plane
On Thu, Apr 02, 2020 at 07:17:52PM +0300, Ville Syrjälä wrote:
> On Thu, Mar 26, 2020 at 08:09:57PM +0200, Stanislav Lisovskiy wrote:
> > According to many computer science sources - magic values
> > in code _are_ _bad_. For many reasons: the reason is that "0"
> > or "1" or whatever magic values confuses and doesn't give any
> > info why this parameter is this value and what it's meaning
> > is.
> > I renamed "0" to COLOR_PLANE_Y and "1" to COLOR_PLANE_UV,
> > because we in fact already use this naming in many other places
> > and function names, when dealing with color planes.
>
> And now it's incosistent with all the rest of the codebase :(
]I think functions like func(0,1,2) is more than ugly.
I can find dozens of sources from credible people stating why it's
wrong.
If the existing code base is inspiring people to do it that way
- then it's wrong.
And I honestly don't even know what is more stupid here:
passing magic numbers into functions, making it look non-obvious
or arguing about that. Kind of competition.
I think we have also enum values passed into functions in our
code and that seems fine(may be because that code wasn't written by me?).
For instance you do use PIPE_A, PIPE_B instead of 0,1,2 right?
Or sure I can find another examples.
>
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > .../drm/i915/display/intel_display_types.h| 5 +++
> > drivers/gpu/drm/i915/intel_pm.c | 40 +--
> > 2 files changed, 25 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 176ab5f1e867..523e0444b373 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -682,6 +682,11 @@ struct skl_plane_wm {
> > bool is_planar;
> > };
> >
> > +enum color_plane {
> > + COLOR_PLANE_Y,
> > + COLOR_PLANE_UV
> > +};
> > +
> > struct skl_pipe_wm {
> > struct skl_plane_wm planes[I915_MAX_PLANES];
> > };
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index b632b6bb9c3e..9e9a4612d842 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4013,7 +4013,7 @@ static int skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> > int width, const struct drm_format_info
> > *format,
> > u64 modifier, unsigned int rotation,
> > u32 plane_pixel_rate, struct skl_wm_params *wp,
> > -int color_plane);
> > +enum color_plane);
> > static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > int level,
> > unsigned int latency,
> > @@ -4035,7 +4035,7 @@ skl_cursor_allocation(const struct intel_crtc_state
> > *crtc_state,
> > drm_format_info(DRM_FORMAT_ARGB),
> > DRM_FORMAT_MOD_LINEAR,
> > DRM_MODE_ROTATE_0,
> > - crtc_state->pixel_rate, , 0);
> > + crtc_state->pixel_rate, , COLOR_PLANE_Y);
> > drm_WARN_ON(_priv->drm, ret);
> >
> > for (level = 0; level <= max_level; level++) {
> > @@ -4431,7 +4431,7 @@ static u8 skl_compute_dbuf_slices(const struct
> > intel_crtc_state *crtc_state,
> > static u64
> > skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state *plane_state,
> > -int color_plane)
> > +enum color_plane color_plane)
> > {
> > struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > @@ -4446,7 +4446,7 @@ skl_plane_relative_data_rate(const struct
> > intel_crtc_state *crtc_state,
> > if (plane->id == PLANE_CURSOR)
> > return 0;
> >
> > - if (color_plane == 1 &&
> > + if (color_plane == COLOR_PLANE_UV &&
> > !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> > return 0;
> >
> > @@ -4459,7 +4459,7 @@ skl_plane_relative_data_rate(const struct
> > intel_crtc_state *crtc_state,
> > height = drm_rect_height(_state->uapi.src) >> 16;
> >
> > /* UV plane does 1/2 pixel sub-sampling */
> > - if (color_plane == 1) {
> > + if (color_plane == COLOR_PLANE_UV) {
> > width /= 2;
> > height /= 2;
> > }
> > @@ -4489,12 +4489,12 @@ skl_get_total_relative_data_rate(struct
> > intel_crtc_state *crtc_state,
> > u64 rate;
> >
> > /* packed/y */
> > - rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> > + rate =
Re: [Intel-gfx] [PATCH v20 04/10] drm/i915: Add intel_atomic_get_bw_*_state helpers
On Thu, Mar 26, 2020 at 08:09:59PM +0200, Stanislav Lisovskiy wrote:
> Add correspondent helpers to be able to get old/new bandwidth
> global state object.
>
> v2: - Fixed typo in function call
> v3: - Changed new functions naming to use convention proposed
> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
> v4: - Change function naming back to intel_atomic* pattern,
> was decided to rename in a separate patch series.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 29 -
> drivers/gpu/drm/i915/display/intel_bw.h | 9
> 2 files changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 58b264bc318d..a8b2038db4d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -374,7 +374,34 @@ static unsigned int intel_bw_data_rate(struct
> drm_i915_private *dev_priv,
> return data_rate;
> }
>
> -static struct intel_bw_state *
> +struct intel_bw_state *
> +intel_atomic_get_bw_old_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *bw_state;
> +
> + bw_state = intel_atomic_get_old_global_obj_state(state,
> _priv->bw_obj);
> + if (IS_ERR(bw_state))
> + return ERR_CAST(bw_state);
These can't return an error.
> +
> + return to_intel_bw_state(bw_state);
> +}
> +
> +struct intel_bw_state *
> +intel_atomic_get_bw_new_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *bw_state;
> +
> + bw_state = intel_atomic_get_new_global_obj_state(state,
> _priv->bw_obj);
> +
> + if (IS_ERR(bw_state))
> + return ERR_CAST(bw_state);
> +
> + return to_intel_bw_state(bw_state);
> +}
> +
> +struct intel_bw_state *
> intel_atomic_get_bw_state(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index a8aa7624c5aa..fe6579c952f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -24,6 +24,15 @@ struct intel_bw_state {
>
> #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
>
> +struct intel_bw_state *
> +intel_atomic_get_bw_old_state(struct intel_atomic_state *state);
> +
> +struct intel_bw_state *
> +intel_atomic_get_bw_new_state(struct intel_atomic_state *state);
> +
> +struct intel_bw_state *
> +intel_atomic_get_bw_state(struct intel_atomic_state *state);
> +
> void intel_bw_init_hw(struct drm_i915_private *dev_priv);
> int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use per-engine request pools (rev5)
== Series Details ==
Series: drm/i915: Use per-engine request pools (rev5)
URL : https://patchwork.freedesktop.org/series/75415/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8238 -> Patchwork_17185
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17185 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17185, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17185:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gem_contexts:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-icl-dsi/igt@i915_selftest@live@gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-icl-dsi/igt@i915_selftest@live@gem_contexts.html
- fi-snb-2520m: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-snb-2520m/igt@i915_selftest@live@gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-snb-2520m/igt@i915_selftest@live@gem_contexts.html
- fi-hsw-peppy: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-hsw-peppy/igt@i915_selftest@live@gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-hsw-peppy/igt@i915_selftest@live@gem_contexts.html
- fi-icl-u2: [PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-icl-u2/igt@i915_selftest@live@gem_contexts.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-icl-u2/igt@i915_selftest@live@gem_contexts.html
- fi-icl-y: [PASS][9] -> [INCOMPLETE][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-icl-y/igt@i915_selftest@live@gem_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-icl-y/igt@i915_selftest@live@gem_contexts.html
- fi-ivb-3770:[PASS][11] -> [INCOMPLETE][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-ivb-3770/igt@i915_selftest@live@gem_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-ivb-3770/igt@i915_selftest@live@gem_contexts.html
- fi-ilk-650: [PASS][13] -> [INCOMPLETE][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-ilk-650/igt@i915_selftest@live@gem_contexts.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-ilk-650/igt@i915_selftest@live@gem_contexts.html
- fi-hsw-4770:[PASS][15] -> [INCOMPLETE][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-hsw-4770/igt@i915_selftest@live@gem_contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-hsw-4770/igt@i915_selftest@live@gem_contexts.html
- fi-icl-guc: [PASS][17] -> [INCOMPLETE][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-icl-guc/igt@i915_selftest@live@gem_contexts.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-icl-guc/igt@i915_selftest@live@gem_contexts.html
- fi-bdw-5557u: [PASS][19] -> [INCOMPLETE][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gem_contexts:
- {fi-ehl-1}: [PASS][21] -> [INCOMPLETE][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-ehl-1/igt@i915_selftest@live@gem_contexts.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-ehl-1/igt@i915_selftest@live@gem_contexts.html
Known issues
Here are the changes found in Patchwork_17185 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gem_contexts:
- fi-skl-6600u: [PASS][23] -> [INCOMPLETE][24] ([i915#1591])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17185/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html
- fi-bsw-kefka: [PASS][25] -> [INCOMPLETE][26] ([i915#392])
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html
Re: [Intel-gfx] [PATCH v20 02/10] drm/i915: Eliminate magic numbers "0" and "1" from color plane
On Thu, Mar 26, 2020 at 08:09:57PM +0200, Stanislav Lisovskiy wrote:
> According to many computer science sources - magic values
> in code _are_ _bad_. For many reasons: the reason is that "0"
> or "1" or whatever magic values confuses and doesn't give any
> info why this parameter is this value and what it's meaning
> is.
> I renamed "0" to COLOR_PLANE_Y and "1" to COLOR_PLANE_UV,
> because we in fact already use this naming in many other places
> and function names, when dealing with color planes.
And now it's incosistent with all the rest of the codebase :(
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> .../drm/i915/display/intel_display_types.h| 5 +++
> drivers/gpu/drm/i915/intel_pm.c | 40 +--
> 2 files changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 176ab5f1e867..523e0444b373 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -682,6 +682,11 @@ struct skl_plane_wm {
> bool is_planar;
> };
>
> +enum color_plane {
> + COLOR_PLANE_Y,
> + COLOR_PLANE_UV
> +};
> +
> struct skl_pipe_wm {
> struct skl_plane_wm planes[I915_MAX_PLANES];
> };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b632b6bb9c3e..9e9a4612d842 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4013,7 +4013,7 @@ static int skl_compute_wm_params(const struct
> intel_crtc_state *crtc_state,
>int width, const struct drm_format_info
> *format,
>u64 modifier, unsigned int rotation,
>u32 plane_pixel_rate, struct skl_wm_params *wp,
> - int color_plane);
> + enum color_plane);
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>int level,
>unsigned int latency,
> @@ -4035,7 +4035,7 @@ skl_cursor_allocation(const struct intel_crtc_state
> *crtc_state,
> drm_format_info(DRM_FORMAT_ARGB),
> DRM_FORMAT_MOD_LINEAR,
> DRM_MODE_ROTATE_0,
> - crtc_state->pixel_rate, , 0);
> + crtc_state->pixel_rate, , COLOR_PLANE_Y);
> drm_WARN_ON(_priv->drm, ret);
>
> for (level = 0; level <= max_level; level++) {
> @@ -4431,7 +4431,7 @@ static u8 skl_compute_dbuf_slices(const struct
> intel_crtc_state *crtc_state,
> static u64
> skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>const struct intel_plane_state *plane_state,
> - int color_plane)
> + enum color_plane color_plane)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> @@ -4446,7 +4446,7 @@ skl_plane_relative_data_rate(const struct
> intel_crtc_state *crtc_state,
> if (plane->id == PLANE_CURSOR)
> return 0;
>
> - if (color_plane == 1 &&
> + if (color_plane == COLOR_PLANE_UV &&
> !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> return 0;
>
> @@ -4459,7 +4459,7 @@ skl_plane_relative_data_rate(const struct
> intel_crtc_state *crtc_state,
> height = drm_rect_height(_state->uapi.src) >> 16;
>
> /* UV plane does 1/2 pixel sub-sampling */
> - if (color_plane == 1) {
> + if (color_plane == COLOR_PLANE_UV) {
> width /= 2;
> height /= 2;
> }
> @@ -4489,12 +4489,12 @@ skl_get_total_relative_data_rate(struct
> intel_crtc_state *crtc_state,
> u64 rate;
>
> /* packed/y */
> - rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> + rate = skl_plane_relative_data_rate(crtc_state, plane_state,
> COLOR_PLANE_Y);
> plane_data_rate[plane_id] = rate;
> total_data_rate += rate;
>
> /* uv-plane */
> - rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> + rate = skl_plane_relative_data_rate(crtc_state, plane_state,
> COLOR_PLANE_UV);
> uv_plane_data_rate[plane_id] = rate;
> total_data_rate += rate;
> }
> @@ -4516,7 +4516,7 @@ icl_get_total_relative_data_rate(struct
> intel_crtc_state *crtc_state,
> u64 rate;
>
> if (!plane_state->planar_linked_plane) {
> - rate = skl_plane_relative_data_rate(crtc_state,
> plane_state, 0);
> + rate = skl_plane_relative_data_rate(crtc_state,
>
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/perf_pmu: Exercise mixing perf reads into i915 mmaps
On 02/04/2020 15:07, Chris Wilson wrote:
Quoting Chris Wilson (2020-04-02 15:00:57)
Feed a fresh i915 mmap into a read(perf_fd) to teach lockdep about the
potential lock chains should we take a pagefault into our vm_fault
handlers from within perf.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 259670f4b..1d6681d80 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1827,6 +1827,35 @@ accuracy(int gem_fd, const struct
intel_execution_engine2 *e,
assert_within(100.0 * busy_r, 100.0 * expected, 2);
}
+static void *create_mmap(int gem_fd, const struct mmap_offset *t, int sz)
+{
+ uint32_t handle;
+ void *ptr;
+
+ handle = gem_create(gem_fd, sz);
+ ptr = __gem_mmap_offset(gem_fd, handle, 0, sz, PROT_WRITE, t->type);
+ gem_close(gem_fd, handle);
+
+ return ptr;
+}
+
+static void
+faulting_read(int gem_fd, const struct mmap_offset *t)
+{
+ void *ptr;
+ int fd;
+
+ ptr = create_mmap(gem_fd, t, 4096);
+ igt_require(ptr != NULL);
+
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(0, 0));
+ igt_require(fd != -1);
+ igt_assert_eq(read(fd, ptr, 4096), 2 * sizeof(uint64_t));
+ close(fd);
+
+ munmap(ptr, 4096);
+}
+
#define test_each_engine(T, i915, e) \
igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
igt_dynamic_f("%s", e->name)
@@ -1860,6 +1889,16 @@ igt_main
igt_subtest("invalid-init")
invalid_init(fd);
+ igt_subtest_with_dynamic("faulting-read") {
+ for_each_mmap_offset_type(fd, t) {
+ if (!gem_has_mmap_offset_type(fd, t))
+ continue;
Redundant, for_each_mmap_offset_type() includes the skip.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/23] perf/core: Only copy-to-user after completely unlocking all locks, v2.
== Series Details ==
Series: series starting with [01/23] perf/core: Only copy-to-user after
completely unlocking all locks, v2.
URL : https://patchwork.freedesktop.org/series/75423/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8238 -> Patchwork_17184
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17184 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17184, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17184:
### IGT changes ###
Possible regressions
* igt@gem_close_race@basic-process:
- fi-ivb-3770:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-ivb-3770/igt@gem_close_r...@basic-process.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-ivb-3770/igt@gem_close_r...@basic-process.html
- fi-hsw-4770:[PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-hsw-4770/igt@gem_close_r...@basic-process.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-hsw-4770/igt@gem_close_r...@basic-process.html
- fi-hsw-peppy: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-hsw-peppy/igt@gem_close_r...@basic-process.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-hsw-peppy/igt@gem_close_r...@basic-process.html
* igt@gem_exec_fence@basic-await@rcs0:
- fi-elk-e7500: [PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@rcs0.html
- fi-pnv-d510:[PASS][9] -> [DMESG-WARN][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-pnv-d510/igt@gem_exec_fence@basic-aw...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-pnv-d510/igt@gem_exec_fence@basic-aw...@rcs0.html
* igt@gem_render_tiled_blits@basic:
- fi-gdg-551: [PASS][11] -> [DMESG-WARN][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-gdg-551/igt@gem_render_tiled_bl...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-gdg-551/igt@gem_render_tiled_bl...@basic.html
* igt@i915_selftest@live@gem_contexts:
- fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-cfl-8109u/igt@i915_selftest@live@gem_contexts.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-cfl-8109u/igt@i915_selftest@live@gem_contexts.html
- fi-skl-lmem:[PASS][15] -> [DMESG-WARN][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][17]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-pnv-d510/igt@run...@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][18]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-cfl-8109u/igt@run...@aborted.html
- fi-elk-e7500: NOTRUN -> [FAIL][19]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-elk-e7500/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gem_contexts:
- {fi-kbl-7560u}: [PASS][20] -> [DMESG-WARN][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-kbl-7560u/igt@i915_selftest@live@gem_contexts.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-kbl-7560u/igt@i915_selftest@live@gem_contexts.html
Known issues
Here are the changes found in Patchwork_17184 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-process:
- fi-byt-j1900: [PASS][22] -> [INCOMPLETE][23] ([i915#45])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-byt-j1900/igt@gem_close_r...@basic-process.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17184/fi-byt-j1900/igt@gem_close_r...@basic-process.html
- fi-byt-n2820: [PASS][24] -> [INCOMPLETE][25] ([i915#45])
[24]:
[Intel-gfx] [PATCH] drm/i915: Use per-engine request pools
Add a per-engine request mempool so that we should always have a couple
of requests available for powermanagement allocations from tricky
contexts. These reserves are expected to be only used for kernel
contexts when barriers must be emitted [almost] without fail.
When using the mempool, requests are first allocated from the global
slab cache (utilising all the per-cpu lockless freelists and caches) and
only if that is empty and cannot be filled under the gfp_t do we
fallback to using the per-engine cache of recently freed requests. For
our use cases, this will never be empty for long as there will always be
at least the previous powermanagent request to reuse.
The downside is that this is quite a bulky addition and abstraction to
use, but it will ensure that we never fail to park the engine due to
oom.
v2: Only use the mempool for nonblocking allocations which are not
expected to fail.
v3: mempool harbours a grudge against slab caches that denies the use of
constructors and falls foul of TYPESAFE_BY_RCU rules. Use custom
alloc/free callbacks so that it neither hits a VM_BUG_ON nor poisons the
RCU'ed element.
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Tvrtko Ursulin
Reviewed-by: Janusz Krzysztofik #v2
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 +++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 26
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
drivers/gpu/drm/i915/gt/mock_engine.c| 2 ++
drivers/gpu/drm/i915/i915_request.c | 20 +--
drivers/gpu/drm/i915/i915_request.h | 2 ++
7 files changed, 53 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b469de0dd9b6..c1159bd17989 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -324,6 +324,9 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+void intel_engine_init_request_pool(struct intel_engine_cs *engine);
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine);
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 843cb6f2f696..fbaf3fc6366f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -602,6 +602,30 @@ static int init_status_page(struct intel_engine_cs *engine)
return ret;
}
+static void *__mempool_alloc_slab(gfp_t gfp, void *data)
+{
+ return kmem_cache_alloc(data, gfp);
+}
+
+static void __mempool_free_slab(void *element, void *data)
+{
+ kmem_cache_free(data, element);
+}
+
+void intel_engine_init_request_pool(struct intel_engine_cs *engine)
+{
+ /* NB mempool_init_slab() does not handle TYPESAFE_BY_RCU */
+ mempool_init(>request_pool,
+INTEL_ENGINE_REQUEST_POOL_RESERVED,
+__mempool_alloc_slab, __mempool_free_slab,
+i915_request_slab_cache());
+}
+
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine)
+{
+ mempool_exit(>request_pool);
+}
+
static int engine_setup_common(struct intel_engine_cs *engine)
{
int err;
@@ -617,6 +641,7 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
intel_engine_init_execlists(engine);
intel_engine_init_cmd_parser(engine);
intel_engine_init__pm(engine);
+ intel_engine_init_request_pool(engine);
intel_engine_init_retire(engine);
intel_engine_pool_init(>pool);
@@ -817,6 +842,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
cleanup_status_page(engine);
intel_engine_fini_retire(engine);
+ intel_engine_fini_request_pool(engine);
intel_engine_pool_fini(>pool);
intel_engine_fini_breadcrumbs(engine);
intel_engine_cleanup_cmd_parser(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..0db03215127b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -308,6 +309,9 @@ struct intel_engine_cs {
struct list_head hold; /* ready requests, but on hold */
} active;
+ mempool_t request_pool; /* keep some in reserve for powermanagement */
+#define INTEL_ENGINE_REQUEST_POOL_RESERVED 2
+
struct llist_head barrier_tasks;
struct intel_context *kernel_context; /* pinned */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3479cda37fdc..afc9107e5d04 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++
Re: [Intel-gfx] [PATCH v3 2/3] drm/i915: Add i915_lpsp_info debugfs
On 02-04-2020 18:15, Anshuman Gupta wrote:
On 2020-04-01 at 21:23:28 +0530, Manna, Animesh wrote:
thanks animesh for review!
On 31-03-2020 17:07, Anshuman Gupta wrote:
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_info, it exposes whether an output is
capable of driving lpsp and exposes lpsp enablement info.
v2:
- CI fixup.
v3:
- register i915_lpsp_info only for supported connector. [Jani]
- use intel_display_power_well_is_enabled() instead of looking
inside power_well count. [Jani]
- fixes the lpsp capable conditional logic. [Jani]
- combined the lpsp capable and enable info. [Jani]
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 124 ++
.../drm/i915/display/intel_display_power.h| 2 +
2 files changed, 126 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 424f4e52f783..b185c4617468 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -9,6 +9,7 @@
#include "i915_debugfs.h"
#include "intel_csr.h"
#include "intel_display_debugfs.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_fbc.h"
@@ -611,6 +612,98 @@ static void intel_hdcp_info(struct seq_file *m,
seq_puts(m, "\n");
}
+#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP capable\n") : seq_puts(m,
"LPSP incapable\n"))
+#define LPSP_ENABLE(COND) (COND ? seq_puts(m, "LPSP enabled\n") : seq_puts(m, "LPSP
disabled\n"))
+
+/* LVDS also an embedded panel but we are not interested in it */
+static bool intel_have_embedded_panel(struct drm_connector *connector)
+{
+ return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP;
+}
+
+static bool intel_have_gen9_lpsp_panel(struct drm_connector *connector)
+{
+ return intel_have_embedded_panel(connector) ||
+ connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort;
+}
+
+static bool intel_have_lpsp_supported_panel(struct drm_connector *connector)
+{
+ return intel_have_gen9_lpsp_panel(connector) ||
+ connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
+ connector->connector_type == DRM_MODE_CONNECTOR_HDMIB;
+}
This function will pass for every platform for almost all (EDP/MIPI/DP/HDMI)
connector type even if not supported ...rt?
Above function will only used to add i915_lpsp_info for DP/MIPI/DP/HDMI
connecotr,
It can nuke it with condition below condition.
return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB;
So in order to avoid such big condition i had prefred the above function,
please suggest a better readable way.
use condition as such, function name change or using a macro.
Apart from that I did not understand the purpose of above functions.
My thought process was to break longer conditional if chunk in static function,
please suggest if u are in favour of nuke these functions, or if u want to
suggest
a better name.
Can we have a single function to check the connector is supported lpsp or not.
static bool is_lpsp_supported(struct drm_connector *connector)
In function definition we can check for platform first, then check
connector_type and return true/false.
i915_lpsp_info_show is first checking the gen and then platform, after checking
platform it needs to check DDI port and connector based upon platform lpsp
block diagram
in order to evaluate lpsp capablity, followed by power well check to evlauate
lpsp
enabled.
if i understand you are suggesting to break above two parts,
is_lpsp_supported()
is_lpsp_capable()
but by breaking above we would require to check gen and platfrom twice
which can be avoided by combining above.
No, as I mentioned below, both looks to me same, better to have one function.
if (is_lpsp_supported())
then add debugfs-entry.
Inside is_lpsp_supported() check everything related to connector. And in
i915_lpsp_info_show() function check only power-well status and print lpsp is
enabled or disabled
My understanding first i-g-t will check the lpsp capability of a connector then
check the lpsp status to compare with our expectation ... right?
BTW, LPSP is related to single pipe with minimum power-well usage. No direct
relation with port/connector. For headless configuration we can have lpsp mode
enabled. How you will handle that?
Regards,
Animesh
please correct me if i am wrong.
Thanks ,
Anshuman Gupta.
+
+static bool
+intel_lpsp_power_well_enabled(struct drm_i915_private *dev_priv,
+
[Intel-gfx] [CI] drm/i915: Use per-engine request pools
Add a per-engine request mempool so that we should always have a couple
of requests available for powermanagement allocations from tricky
contexts. These reserves are expected to be only used for kernel
contexts when barriers must be emitted [almost] without fail.
When using the mempool, requests are first allocated from the global
slab cache (utilising all the per-cpu lockless freelists and caches) and
only if that is empty and cannot be filled under the gfp_t do we
fallback to using the per-engine cache of recently freed requests. For
our use cases, this will never be empty for long as there will always be
at least the previous powermanagent request to reuse.
The downside is that this is quite a bulky addition and abstraction to
use, but it will ensure that we never fail to park the engine due to
oom.
v2: Only use the mempool for nonblocking allocations which are not
expected to fail.
v3: mempool harbours a grudge against slab caches that denies the use of
constructors and falls foul of TYPESAFE_BY_RCU rules. Use custom
alloc/free callbacks so that it neither hits a VM_BUG_ON nor poisons the
RCU'ed element.
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Tvrtko Ursulin
Reviewed-by: Janusz Krzysztofik #v2
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 +++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 26
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
drivers/gpu/drm/i915/i915_request.c | 20 +--
drivers/gpu/drm/i915/i915_request.h | 2 ++
6 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b469de0dd9b6..c1159bd17989 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -324,6 +324,9 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+void intel_engine_init_request_pool(struct intel_engine_cs *engine);
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine);
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 843cb6f2f696..fbaf3fc6366f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -602,6 +602,30 @@ static int init_status_page(struct intel_engine_cs *engine)
return ret;
}
+static void *__mempool_alloc_slab(gfp_t gfp, void *data)
+{
+ return kmem_cache_alloc(data, gfp);
+}
+
+static void __mempool_free_slab(void *element, void *data)
+{
+ kmem_cache_free(data, element);
+}
+
+void intel_engine_init_request_pool(struct intel_engine_cs *engine)
+{
+ /* NB mempool_init_slab() does not handle TYPESAFE_BY_RCU */
+ mempool_init(>request_pool,
+INTEL_ENGINE_REQUEST_POOL_RESERVED,
+__mempool_alloc_slab, __mempool_free_slab,
+i915_request_slab_cache());
+}
+
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine)
+{
+ mempool_exit(>request_pool);
+}
+
static int engine_setup_common(struct intel_engine_cs *engine)
{
int err;
@@ -617,6 +641,7 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
intel_engine_init_execlists(engine);
intel_engine_init_cmd_parser(engine);
intel_engine_init__pm(engine);
+ intel_engine_init_request_pool(engine);
intel_engine_init_retire(engine);
intel_engine_pool_init(>pool);
@@ -817,6 +842,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
cleanup_status_page(engine);
intel_engine_fini_retire(engine);
+ intel_engine_fini_request_pool(engine);
intel_engine_pool_fini(>pool);
intel_engine_fini_breadcrumbs(engine);
intel_engine_cleanup_cmd_parser(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..0db03215127b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -308,6 +309,9 @@ struct intel_engine_cs {
struct list_head hold; /* ready requests, but on hold */
} active;
+ mempool_t request_pool; /* keep some in reserve for powermanagement */
+#define INTEL_ENGINE_REQUEST_POOL_RESERVED 2
+
struct llist_head barrier_tasks;
struct intel_context *kernel_context; /* pinned */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3479cda37fdc..afc9107e5d04 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4892,6 +4892,8
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/23] perf/core: Only copy-to-user after completely unlocking all locks, v2.
== Series Details ==
Series: series starting with [01/23] perf/core: Only copy-to-user after
completely unlocking all locks, v2.
URL : https://patchwork.freedesktop.org/series/75423/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e9bb8bda08c5 perf/core: Only copy-to-user after completely unlocking all locks,
v2.
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#17:
<4> [604.892540] 8264a558 (rcu_state.barrier_mutex){+.+.}, at:
rcu_barrier+0x23/0x190
-:200: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#200: FILE: kernel/events/core.c:5008:
+__perf_read(struct perf_event *event, char __user *buf,
+ size_t count, u64 **values)
total: 0 errors, 1 warnings, 1 checks, 129 lines checked
4c5bce10a92a Revert "drm/i915/gem: Drop relocation slowpath"
-:78: WARNING:LINE_SPACING: Missing a blank line after declarations
#78: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1618:
+ int err = __get_user(c, addr);
+ if (err)
total: 0 errors, 1 warnings, 0 checks, 257 lines checked
b3cea5caa585 drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2.
-:506: WARNING:LONG_LINE: line over 100 characters
#506: FILE: drivers/gpu/drm/i915/i915_gem.c:1341:
+ while ((obj = list_first_entry_or_null(>obj_list, struct
drm_i915_gem_object, obj_link))) {
total: 0 errors, 1 warnings, 0 checks, 481 lines checked
1c6bad3a7182 drm/i915: Remove locking from i915_gem_object_prepare_read/write
4b4b9e26fc97 drm/i915: Parse command buffer earlier in eb_relocate(slow)
617a1d088295 Revert "drm/i915/gem: Split eb_vma into its own allocation"
9b03f80f6396 drm/i915: Use per object locking in execbuf, v7.
3e2a63f8be33 drm/i915: Use ww locking in intel_renderstate.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
Convert to using ww-waiting, and make sure we always pin intel_context_state,
total: 0 errors, 1 warnings, 0 checks, 202 lines checked
968378aa2d04 drm/i915: Add ww context handling to context_barrier_task
-:19: WARNING:LONG_LINE: line over 100 characters
#19: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:1100:
+ int (*pin)(struct intel_context *ce, struct
i915_gem_ww_ctx *ww, void *data),
total: 0 errors, 1 warnings, 0 checks, 146 lines checked
6242b98866e5 drm/i915: Nuke arguments to eb_pin_engine
351148011a0d drm/i915: Pin engine before pinning all objects, v3.
2fa57bd2a12c drm/i915: Rework intel_context pinning to do everything outside of
pin_mutex
-:125: CHECK:LINE_SPACING: Please don't use multiple blank lines
#125: FILE: drivers/gpu/drm/i915/gt/intel_context.c:176:
+
+
-:340: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#340: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:3113:
+ *vaddr = i915_gem_object_pin_map(ce->state->obj,
+
i915_coherent_map_type(ce->engine->i915) |
total: 0 errors, 0 warnings, 2 checks, 445 lines checked
a0ef4b3627ad drm/i915: Make sure execbuffer always passes ww state to
i915_vma_pin.
-:95: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#95: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:592:
+ err = i915_vma_pin_ww(vma, >ww,
entry->pad_to_size, entry->alignment,
-:203: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#203: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2212:
+* hsw should have this fixed, but bdw mucks it up again. */
total: 0 errors, 1 warnings, 1 checks, 827 lines checked
16e33183c09e drm/i915: Convert i915_gem_object/client_blt.c to use ww locking
as well, v2.
484cb9a63457 drm/i915: Kill last user of intel_context_create_request outside
of selftests
d4b9ea0aee60 drm/i915: Convert i915_perf to ww locking as well
b9f86d313299 drm/i915: Dirty hack to fix selftests locking inversion
3a14330db1de drm/i915/selftests: Fix locking inversion in lrc selftest.
aea30143d0f3 drm/i915: Use ww pinning for intel_context_create_request()
d666c06d8891 drm/i915: Move i915_vma_lock in the selftests to avoid lock
inversion, v2.
6cdda6ab9f59 drm/i915: Add ww locking to vm_fault_gtt
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 91 lines checked
43b44cc265fa drm/i915: Add ww locking to pin_to_display_plane
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 129 lines checked
b49bed048016 drm/i915: Ensure we hold the pin mutex
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 37 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
[Intel-gfx] ✓ Fi.CI.BAT: success for perf/core: Only copy-to-user after completely unlocking all locks, v2.
== Series Details == Series: perf/core: Only copy-to-user after completely unlocking all locks, v2. URL : https://patchwork.freedesktop.org/series/75422/ State : success == Summary == CI Bug Log - changes from CI_DRM_8238 -> Patchwork_17183 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17183/index.html Known issues Here are the changes found in Patchwork_17183 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-edid-read: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([i915#976]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8238/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17183/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [i915#976]: https://gitlab.freedesktop.org/drm/intel/issues/976 Participating hosts (50 -> 43) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8238 -> Patchwork_17183 CI-20190529: 20190529 CI_DRM_8238: 840f70602a47208a2f1e444ba276f412f10e38df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5558: 3b55a816300d80bc5e0b995cd41ee8c8649a1ea2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17183: edcfb0ee5b6fc0c7934fd91de8f0f520c8b58941 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == edcfb0ee5b6f perf/core: Only copy-to-user after completely unlocking all locks, v2. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17183/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for perf/core: Only copy-to-user after completely unlocking all locks, v2.
== Series Details ==
Series: perf/core: Only copy-to-user after completely unlocking all locks, v2.
URL : https://patchwork.freedesktop.org/series/75422/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
edcfb0ee5b6f perf/core: Only copy-to-user after completely unlocking all locks,
v2.
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#17:
<4> [604.892540] 8264a558 (rcu_state.barrier_mutex){+.+.}, at:
rcu_barrier+0x23/0x190
-:200: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#200: FILE: kernel/events/core.c:5008:
+__perf_read(struct perf_event *event, char __user *buf,
+ size_t count, u64 **values)
total: 0 errors, 1 warnings, 1 checks, 129 lines checked
___
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Re: [Intel-gfx] kernel 5.6: baytrail hdmi audio not working
On Thu, Apr 02, 2020 at 04:52:03PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 01, 2020 at 06:53:17PM -0400, Giacomo Comes wrote:
> > Hi,
> > on my Intel Compute Stick STCK1 (baytrail hdmi audio)
> > sound is not working with the kernel 5.6
> >
> > I have bisected the kernel and I found the commit that introduced the issue:
> >
> > commit 58d124ea2739e1440ddd743d46c470fe724aca9a
> > Author: Maarten Lankhorst
> > Date: Thu Oct 31 12:26:04 2019 +0100
> >
> > drm/i915: Complete crtc hw/uapi split, v6.
> >
> > Now that we separated everything into uapi and hw, it's
> > time to make the split definitive. Remove the union and
> > make a copy of the hw state on modeset and fastset.
> >
> > Color blobs are copied in crtc atomic_check(), right
> > before color management is checked.
> >
> > If more information is required please let me know.
>
> Should hopefully be fixed with
> commit 2bdd4c28baff ("drm/i915/display: Fix mode private_flags
> comparison at atomic_check")
>
> Stable folks, please pick that up for 5.6.x stable releases.
I can confirm that the commit indeed solves the problem I have.
It should go in the stable 5.6.x release ASAP.
Thanks.
Giacomo
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[Intel-gfx] [PATCH 02/23] Revert "drm/i915/gem: Drop relocation slowpath"
This reverts commit 7dc8f1143778 ("drm/i915/gem: Drop relocation
slowpath"). We need the slowpath relocation for taking ww-mutex
inside the page fault handler, and we will take this mutex when
pinning all objects.
Cc: Chris Wilson
Cc: Matthew Auld
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 239 +-
1 file changed, 235 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 9d11bad74e9a..b896bd527d5c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1521,7 +1521,9 @@ static int eb_relocate_vma(struct i915_execbuffer *eb,
struct eb_vma *ev)
* we would try to acquire the struct mutex again. Obviously
* this is bad and so lockdep complains vehemently.
*/
- copied = __copy_from_user(r, urelocs, count * sizeof(r[0]));
+ pagefault_disable();
+ copied = __copy_from_user_inatomic(r, urelocs, count *
sizeof(r[0]));
+ pagefault_enable();
if (unlikely(copied)) {
remain = -EFAULT;
goto out;
@@ -1569,6 +1571,236 @@ static int eb_relocate_vma(struct i915_execbuffer *eb,
struct eb_vma *ev)
return remain;
}
+static int
+eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
+{
+ const struct drm_i915_gem_exec_object2 *entry = ev->exec;
+ struct drm_i915_gem_relocation_entry *relocs =
+ u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < entry->relocation_count; i++) {
+ u64 offset = eb_relocate_entry(eb, ev, [i]);
+
+ if ((s64)offset < 0) {
+ err = (int)offset;
+ goto err;
+ }
+ }
+ err = 0;
+err:
+ reloc_cache_reset(>reloc_cache);
+ return err;
+}
+
+static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
+{
+ const char __user *addr, *end;
+ unsigned long size;
+ char __maybe_unused c;
+
+ size = entry->relocation_count;
+ if (size == 0)
+ return 0;
+
+ if (size > N_RELOC(ULONG_MAX))
+ return -EINVAL;
+
+ addr = u64_to_user_ptr(entry->relocs_ptr);
+ size *= sizeof(struct drm_i915_gem_relocation_entry);
+ if (!access_ok(addr, size))
+ return -EFAULT;
+
+ end = addr + size;
+ for (; addr < end; addr += PAGE_SIZE) {
+ int err = __get_user(c, addr);
+ if (err)
+ return err;
+ }
+ return __get_user(c, end - 1);
+}
+
+static int eb_copy_relocations(const struct i915_execbuffer *eb)
+{
+ struct drm_i915_gem_relocation_entry *relocs;
+ const unsigned int count = eb->buffer_count;
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < count; i++) {
+ const unsigned int nreloc = eb->exec[i].relocation_count;
+ struct drm_i915_gem_relocation_entry __user *urelocs;
+ unsigned long size;
+ unsigned long copied;
+
+ if (nreloc == 0)
+ continue;
+
+ err = check_relocations(>exec[i]);
+ if (err)
+ goto err;
+
+ urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
+ size = nreloc * sizeof(*relocs);
+
+ relocs = kvmalloc_array(size, 1, GFP_KERNEL);
+ if (!relocs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ /* copy_from_user is limited to < 4GiB */
+ copied = 0;
+ do {
+ unsigned int len =
+ min_t(u64, BIT_ULL(31), size - copied);
+
+ if (__copy_from_user((char *)relocs + copied,
+(char __user *)urelocs + copied,
+len))
+ goto end;
+
+ copied += len;
+ } while (copied < size);
+
+ /*
+* As we do not update the known relocation offsets after
+* relocating (due to the complexities in lock handling),
+* we need to mark them as invalid now so that we force the
+* relocation processing next time. Just in case the target
+* object is evicted and then rebound into its old
+* presumed_offset before the next execbuffer - if that
+* happened we would make the mistake of assuming that the
+* relocations were valid.
+*/
+ if (!user_access_begin(urelocs,
[Intel-gfx] [PATCH 19/23] drm/i915: Use ww pinning for intel_context_create_request()
We want to get rid of intel_context_pin(), convert
intel_context_create_request() first. :)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_context.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 5c7acddf9651..f70135685552 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -450,15 +450,25 @@ int intel_context_prepare_remote_request(struct
intel_context *ce,
struct i915_request *intel_context_create_request(struct intel_context *ce)
{
+ struct i915_gem_ww_ctx ww;
struct i915_request *rq;
int err;
- err = intel_context_pin(ce);
- if (unlikely(err))
- return ERR_PTR(err);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = intel_context_pin_ww(ce, );
+ if (!err) {
+ rq = i915_request_create(ce);
+ intel_context_unpin(ce);
+ } else if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ } else {
+ rq = ERR_PTR(err);
+ }
- rq = i915_request_create(ce);
- intel_context_unpin(ce);
+ i915_gem_ww_ctx_fini();
if (IS_ERR(rq))
return rq;
--
2.25.1
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[Intel-gfx] [PATCH 08/23] drm/i915: Use ww locking in intel_renderstate.
We want to start using ww locking in intel_context_pin, for this
we need to lock multiple objects, and the single i915_gem_object_lock
is not enough.
Convert to using ww-waiting, and make sure we always pin intel_context_state,
even if we don't have a renderstate object.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_gt.c | 21 +++---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 71 ++---
drivers/gpu/drm/i915/gt/intel_renderstate.h | 9 ++-
3 files changed, 65 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 6eae4c791007..c11e89472ad8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -406,21 +406,20 @@ static int __engines_record_defaults(struct intel_gt *gt)
/* We must be able to switch to something! */
GEM_BUG_ON(!engine->kernel_context);
- err = intel_renderstate_init(, engine);
- if (err)
- goto out;
-
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
err = PTR_ERR(ce);
goto out;
}
- rq = intel_context_create_request(ce);
+ err = intel_renderstate_init(, ce);
+ if (err)
+ goto err;
+
+ rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- intel_context_put(ce);
- goto out;
+ goto err_fini;
}
err = intel_engine_emit_ctx_wa(rq);
@@ -434,9 +433,13 @@ static int __engines_record_defaults(struct intel_gt *gt)
err_rq:
requests[id] = i915_request_get(rq);
i915_request_add(rq);
- intel_renderstate_fini();
- if (err)
+err_fini:
+ intel_renderstate_fini(, ce);
+err:
+ if (err) {
+ intel_context_put(ce);
goto out;
+ }
}
/* Flush the default context image to memory, and enable powersaving. */
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c
b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index ca533d98d14d..c65554c431f8 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -27,6 +27,7 @@
#include "i915_drv.h"
#include "intel_renderstate.h"
+#include "gt/intel_context.h"
#include "intel_ring.h"
static const struct intel_renderstate_rodata *
@@ -74,10 +75,9 @@ static int render_state_setup(struct intel_renderstate *so,
u32 *d;
int ret;
- i915_gem_object_lock(so->vma->obj, NULL);
ret = i915_gem_object_prepare_write(so->vma->obj, _clflush);
if (ret)
- goto out_unlock;
+ return ret;
d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0));
@@ -158,8 +158,6 @@ static int render_state_setup(struct intel_renderstate *so,
ret = 0;
out:
i915_gem_object_finish_access(so->vma->obj);
-out_unlock:
- i915_gem_object_unlock(so->vma->obj);
return ret;
err:
@@ -171,33 +169,47 @@ static int render_state_setup(struct intel_renderstate
*so,
#undef OUT_BATCH
int intel_renderstate_init(struct intel_renderstate *so,
- struct intel_engine_cs *engine)
+ struct intel_context *ce)
{
- struct drm_i915_gem_object *obj;
+ struct intel_engine_cs *engine = ce->engine;
+ struct drm_i915_gem_object *obj = NULL;
int err;
memset(so, 0, sizeof(*so));
so->rodata = render_state_get_rodata(engine);
- if (!so->rodata)
- return 0;
+ if (so->rodata) {
+ if (so->rodata->batch_items * 4 > PAGE_SIZE)
+ return -EINVAL;
+
+ obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ so->vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
+ if (IS_ERR(so->vma)) {
+ err = PTR_ERR(so->vma);
+ goto err_obj;
+ }
+ }
- if (so->rodata->batch_items * 4 > PAGE_SIZE)
- return -EINVAL;
+ i915_gem_ww_ctx_init(>ww, true);
+retry:
+ err = intel_context_pin(ce);
+ if (err)
+ goto err_fini;
- obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ /* return early if there's nothing to setup */
+ if (!err && !so->rodata)
+ return 0;
- so->vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
- if (IS_ERR(so->vma)) {
-
[Intel-gfx] [PATCH 22/23] drm/i915: Add ww locking to pin_to_display_plane
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 65 --
drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 +
2 files changed, 49 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 1a3dd77a35b9..4be148392acc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -37,6 +37,12 @@ void i915_gem_object_flush_if_display(struct
drm_i915_gem_object *obj)
i915_gem_object_unlock(obj);
}
+void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj)
+{
+ if (i915_gem_object_is_framebuffer(obj))
+ __i915_gem_object_flush_for_display(obj);
+}
+
/**
* Moves a single object to the WC read, and possibly write domain.
* @obj: object to act on
@@ -197,18 +203,12 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
if (ret)
return ret;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
-
/* Always invalidate stale cachelines */
if (obj->cache_level != cache_level) {
i915_gem_object_set_cache_coherency(obj, cache_level);
obj->cache_dirty = true;
}
- i915_gem_object_unlock(obj);
-
/* The cache-level will be applied when each vma is rebound. */
return i915_gem_object_unbind(obj,
I915_GEM_OBJECT_UNBIND_ACTIVE |
@@ -255,6 +255,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void
*data,
struct drm_i915_gem_caching *args = data;
struct drm_i915_gem_object *obj;
enum i915_cache_level level;
+ struct i915_gem_ww_ctx ww;
int ret = 0;
switch (args->caching) {
@@ -293,7 +294,18 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev,
void *data,
goto out;
}
- ret = i915_gem_object_set_cache_level(obj, level);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ ret = i915_gem_object_lock(obj, );
+ if (!ret)
+ ret = i915_gem_object_set_cache_level(obj, level);
+
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff();
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
out:
i915_gem_object_put(obj);
@@ -313,6 +325,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
unsigned int flags)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct i915_gem_ww_ctx ww;
struct i915_vma *vma;
int ret;
@@ -320,6 +333,11 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj))
return ERR_PTR(-EINVAL);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ ret = i915_gem_object_lock(obj, );
+ if (ret)
+ goto err;
/*
* The display engine is not coherent with the LLC cache on gen6. As
* a result, we make sure that the pinning that is about to occur is
@@ -334,7 +352,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
HAS_WT(i915) ?
I915_CACHE_WT : I915_CACHE_NONE);
if (ret)
- return ERR_PTR(ret);
+ goto err;
/*
* As the user may map the buffer once pinned in the display plane
@@ -347,18 +365,31 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
vma = ERR_PTR(-ENOSPC);
if ((flags & PIN_MAPPABLE) == 0 &&
(!view || view->type == I915_GGTT_VIEW_NORMAL))
- vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
- flags |
- PIN_MAPPABLE |
- PIN_NONBLOCK);
- if (IS_ERR(vma))
- vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
- if (IS_ERR(vma))
- return vma;
+ vma = i915_gem_object_ggtt_pin_ww(obj, , view, 0, alignment,
+ flags | PIN_MAPPABLE |
+ PIN_NONBLOCK);
+ if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK))
+ vma = i915_gem_object_ggtt_pin_ww(obj, , view, 0,
+ alignment, flags);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto err;
+ }
vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
- i915_gem_object_flush_if_display(obj);
+ i915_gem_object_flush_if_display_locked(obj);
+
+err:
+
[Intel-gfx] [PATCH 11/23] drm/i915: Pin engine before pinning all objects, v3.
We want to lock all gem objects, including the engine context objects,
rework the throttling to ensure that we can do this. Now we only throttle
once, but can take eb_pin_engine while acquiring objects. This means we
will have to drop the lock to wait. If we don't have to throttle we can
still take the fastpath, if not we will take the slowpath and wait for
the throttle request while unlocked.
The engine has to be pinned as first step, otherwise gpu relocations
won't work.
Changes since v1:
- Only need to get a throttled request in the fastpath, no need for
a global flag any more.
- Always free the waited request correctly.
Changes since v2:
- Use intel_engine_pm_get()/put() to keeep engine pool alive during
EDEADLK handling.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 174 --
1 file changed, 118 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 7fef5a85ecde..ed111af8f264 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -16,6 +16,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pool.h"
+#include "gt/intel_engine_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_ring.h"
@@ -55,7 +56,8 @@ enum {
#define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN |
__EXEC_OBJECT_HAS_FENCE)
#define __EXEC_HAS_RELOC BIT(31)
-#define __EXEC_INTERNAL_FLAGS (~0u << 31)
+#define __EXEC_ENGINE_PINNED BIT(30)
+#define __EXEC_INTERNAL_FLAGS (~0u << 30)
#define UPDATE PIN_OFFSET_FIXED
#define BATCH_OFFSET_BIAS (256*1024)
@@ -288,6 +290,9 @@ struct i915_execbuffer {
};
static int eb_parse(struct i915_execbuffer *eb);
+static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb,
+ bool throttle);
+static void eb_unpin_engine(struct i915_execbuffer *eb);
static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
{
@@ -914,7 +919,7 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long
handle)
}
}
-static void eb_release_vmas(const struct i915_execbuffer *eb, bool final)
+static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
{
const unsigned int count = eb->buffer_count;
unsigned int i;
@@ -931,6 +936,8 @@ static void eb_release_vmas(const struct i915_execbuffer
*eb, bool final)
if (final)
i915_vma_put(vma);
}
+
+ eb_unpin_engine(eb);
}
static void eb_destroy(const struct i915_execbuffer *eb)
@@ -1729,7 +1736,8 @@ static int eb_prefault_relocations(const struct
i915_execbuffer *eb)
return 0;
}
-static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb)
+static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb,
+ struct i915_request *rq)
{
bool have_copy = false;
struct eb_vma *ev;
@@ -1745,6 +1753,21 @@ static noinline int eb_relocate_parse_slow(struct
i915_execbuffer *eb)
eb_release_vmas(eb, false);
i915_gem_ww_ctx_fini(>ww);
+ if (rq) {
+ /* nonblocking is always false */
+ if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT) < 0) {
+ i915_request_put(rq);
+ rq = NULL;
+
+ err = -EINTR;
+ goto err_relock;
+ }
+
+ i915_request_put(rq);
+ rq = NULL;
+ }
+
/*
* We take 3 passes through the slowpatch.
*
@@ -1768,14 +1791,25 @@ static noinline int eb_relocate_parse_slow(struct
i915_execbuffer *eb)
err = 0;
}
- flush_workqueue(eb->i915->mm.userptr_wq);
+ if (!err)
+ flush_workqueue(eb->i915->mm.userptr_wq);
+err_relock:
i915_gem_ww_ctx_init(>ww, true);
if (err)
goto out;
/* reacquire the objects */
repeat_validate:
+ rq = eb_pin_engine(eb, false);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err;
+ }
+
+ /* We didn't throttle, should be NULL */
+ GEM_WARN_ON(rq);
+
err = eb_validate_vmas(eb);
if (err)
goto err;
@@ -1839,14 +1873,47 @@ static noinline int eb_relocate_parse_slow(struct
i915_execbuffer *eb)
}
}
+ if (rq)
+ i915_request_put(rq);
+
return err;
}
static int eb_relocate_parse(struct i915_execbuffer *eb)
{
int err;
+ struct i915_request *rq = NULL;
+ bool throttle = true;
retry:
+ rq = eb_pin_engine(eb, throttle);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+
[Intel-gfx] [PATCH 18/23] drm/i915/selftests: Fix locking inversion in lrc selftest.
This function does not use intel_context_create_request, so it has
to use the same locking order as normal code. This is required to
shut up lockdep in selftests.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index f3ba58842120..2a78a993c009 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4299,6 +4299,7 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
{
struct intel_context *ce;
struct i915_request *rq;
+ struct i915_gem_ww_ctx ww;
enum {
RING_START_IDX = 0,
RING_TAIL_IDX,
@@ -4313,7 +4314,11 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
if (IS_ERR(ce))
return PTR_ERR(ce);
- err = intel_context_pin(ce);
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_gem_object_lock(scratch->obj, );
+ if (!err)
+ err = intel_context_pin_ww(ce, );
if (err)
goto err_put;
@@ -4342,11 +4347,9 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
*cs++ = 0;
- i915_vma_lock(scratch);
err = i915_request_await_object(rq, scratch->obj, true);
if (!err)
err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(scratch);
i915_request_get(rq);
i915_request_add(rq);
@@ -4383,6 +4386,12 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
err_unpin:
intel_context_unpin(ce);
err_put:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
intel_context_put(ce);
return err;
}
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/23] Revert "drm/i915/gem: Split eb_vma into its own allocation"
This reverts commit 0f1dd02295f35dcdcbaafcbcbbec0753884ab974.
This conflicts with the ww mutex handling, which needs to drop
the references after gpu submission anyway, because otherwise we
may risk unlocking a BO after first freeing it.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 131 --
1 file changed, 58 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 1e9e89603e91..5e093488dd48 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -40,11 +40,6 @@ struct eb_vma {
u32 handle;
};
-struct eb_vma_array {
- struct kref kref;
- struct eb_vma vma[];
-};
-
enum {
FORCE_CPU_RELOC = 1,
FORCE_GTT_RELOC,
@@ -57,6 +52,7 @@ enum {
#define __EXEC_OBJECT_NEEDS_MAPBIT(29)
#define __EXEC_OBJECT_NEEDS_BIAS BIT(28)
#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */
+#define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN |
__EXEC_OBJECT_HAS_FENCE)
#define __EXEC_HAS_RELOC BIT(31)
#define __EXEC_INTERNAL_FLAGS (~0u << 31)
@@ -287,7 +283,6 @@ struct i915_execbuffer {
*/
int lut_size;
struct hlist_head *buckets; /** ht for relocation handles */
- struct eb_vma_array *array;
};
static int eb_parse(struct i915_execbuffer *eb);
@@ -299,62 +294,8 @@ static inline bool eb_use_cmdparser(const struct
i915_execbuffer *eb)
eb->args->batch_len);
}
-static struct eb_vma_array *eb_vma_array_create(unsigned int count)
-{
- struct eb_vma_array *arr;
-
- arr = kvmalloc(struct_size(arr, vma, count), GFP_KERNEL | __GFP_NOWARN);
- if (!arr)
- return NULL;
-
- kref_init(>kref);
- arr->vma[0].vma = NULL;
-
- return arr;
-}
-
-static inline void eb_unreserve_vma(struct eb_vma *ev)
-{
- struct i915_vma *vma = ev->vma;
-
- if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
- __i915_vma_unpin_fence(vma);
-
- if (ev->flags & __EXEC_OBJECT_HAS_PIN)
- __i915_vma_unpin(vma);
-
- ev->flags &= ~(__EXEC_OBJECT_HAS_PIN |
- __EXEC_OBJECT_HAS_FENCE);
-}
-
-static void eb_vma_array_destroy(struct kref *kref)
-{
- struct eb_vma_array *arr = container_of(kref, typeof(*arr), kref);
- struct eb_vma *ev = arr->vma;
-
- while (ev->vma) {
- eb_unreserve_vma(ev);
- i915_vma_put(ev->vma);
- ev++;
- }
-
- kvfree(arr);
-}
-
-static void eb_vma_array_put(struct eb_vma_array *arr)
-{
- kref_put(>kref, eb_vma_array_destroy);
-}
-
static int eb_create(struct i915_execbuffer *eb)
{
- /* Allocate an extra slot for use by the command parser + sentinel */
- eb->array = eb_vma_array_create(eb->buffer_count + 2);
- if (!eb->array)
- return -ENOMEM;
-
- eb->vma = eb->array->vma;
-
if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
unsigned int size = 1 + ilog2(eb->buffer_count);
@@ -388,10 +329,8 @@ static int eb_create(struct i915_execbuffer *eb)
break;
} while (--size);
- if (unlikely(!size)) {
- eb_vma_array_put(eb->array);
+ if (unlikely(!size))
return -ENOMEM;
- }
eb->lut_size = size;
} else {
@@ -502,6 +441,26 @@ eb_pin_vma(struct i915_execbuffer *eb,
return !eb_vma_misplaced(entry, vma, ev->flags);
}
+static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
+{
+ GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
+
+ if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
+ __i915_vma_unpin_fence(vma);
+
+ __i915_vma_unpin(vma);
+}
+
+static inline void
+eb_unreserve_vma(struct eb_vma *ev)
+{
+ if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
+ return;
+
+ __eb_unreserve_vma(ev->vma, ev->flags);
+ ev->flags &= ~__EXEC_OBJECT_RESERVED;
+}
+
static int
eb_validate_vma(struct i915_execbuffer *eb,
struct drm_i915_gem_exec_object2 *entry,
@@ -944,13 +903,31 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned
long handle)
}
}
+static void eb_release_vmas(const struct i915_execbuffer *eb)
+{
+ const unsigned int count = eb->buffer_count;
+ unsigned int i;
+
+ for (i = 0; i < count; i++) {
+ struct eb_vma *ev = >vma[i];
+ struct i915_vma *vma = ev->vma;
+
+ if (!vma)
+ break;
+
+ eb->vma[i].vma = NULL;
+
+ if (ev->flags & __EXEC_OBJECT_HAS_PIN)
+ __eb_unreserve_vma(vma, ev->flags);
+
+ i915_vma_put(vma);
+ }
+}
+
static void
[Intel-gfx] [PATCH 07/23] drm/i915: Use per object locking in execbuf, v7.
Now that we changed execbuf submission slightly to allow us to do all
pinning in one place, we can now simply add ww versions on top of
struct_mutex. All we have to do is a separate path for -EDEADLK
handling, which needs to unpin all gem bo's before dropping the lock,
then starting over.
This finally allows us to do parallel submission, but because not
all of the pinning code uses the ww ctx yet, we cannot completely
drop struct_mutex yet.
Changes since v1:
- Keep struct_mutex for now. :(
Changes since v2:
- Make sure we always lock the ww context in slowpath.
Changes since v3:
- Don't call __eb_unreserve_vma in eb_move_to_gpu now; this can be
done on normal unlock path.
- Unconditionally release vmas and context.
Changes since v4:
- Rebased on top of struct_mutex reduction.
Changes since v5:
- Remove training wheels.
Changes since v6:
- Fix accidentally broken -ENOSPC handling.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 273 ++
1 file changed, 148 insertions(+), 125 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 5e093488dd48..dd3aff4ac3fb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -249,6 +249,8 @@ struct i915_execbuffer {
/** list of vma that have execobj.relocation_count */
struct list_head relocs;
+ struct i915_gem_ww_ctx ww;
+
/**
* Track the most recently used object for relocations, as we
* frequently have to perform multiple relocations within the same
@@ -441,24 +443,18 @@ eb_pin_vma(struct i915_execbuffer *eb,
return !eb_vma_misplaced(entry, vma, ev->flags);
}
-static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
-{
- GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
-
- if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
- __i915_vma_unpin_fence(vma);
-
- __i915_vma_unpin(vma);
-}
-
static inline void
eb_unreserve_vma(struct eb_vma *ev)
{
if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
return;
- __eb_unreserve_vma(ev->vma, ev->flags);
ev->flags &= ~__EXEC_OBJECT_RESERVED;
+
+ if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
+ __i915_vma_unpin_fence(ev->vma);
+
+ __i915_vma_unpin(ev->vma);
}
static int
@@ -552,16 +548,6 @@ eb_add_vma(struct i915_execbuffer *eb,
eb->batch = ev;
}
-
- if (eb_pin_vma(eb, entry, ev)) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
- eb->args->flags |= __EXEC_HAS_RELOC;
- }
- } else {
- eb_unreserve_vma(ev);
- list_add_tail(>bind_link, >unbound);
- }
}
static inline int use_cpu_reloc(const struct reloc_cache *cache,
@@ -646,10 +632,6 @@ static int eb_reserve(struct i915_execbuffer *eb)
* This avoid unnecessary unbinding of later objects in order to make
* room for the earlier objects *unless* we need to defragment.
*/
-
- if (mutex_lock_interruptible(>i915->drm.struct_mutex))
- return -EINTR;
-
pass = 0;
do {
list_for_each_entry(ev, >unbound, bind_link) {
@@ -657,8 +639,8 @@ static int eb_reserve(struct i915_execbuffer *eb)
if (err)
break;
}
- if (!(err == -ENOSPC || err == -EAGAIN))
- break;
+ if (err != -ENOSPC)
+ return err;
/* Resort *all* the objects into priority order */
INIT_LIST_HEAD(>unbound);
@@ -688,13 +670,6 @@ static int eb_reserve(struct i915_execbuffer *eb)
}
list_splice_tail(, >unbound);
- if (err == -EAGAIN) {
- mutex_unlock(>i915->drm.struct_mutex);
- flush_workqueue(eb->i915->mm.userptr_wq);
- mutex_lock(>i915->drm.struct_mutex);
- continue;
- }
-
switch (pass++) {
case 0:
break;
@@ -705,20 +680,15 @@ static int eb_reserve(struct i915_execbuffer *eb)
err = i915_gem_evict_vm(eb->context->vm);
mutex_unlock(>context->vm->mutex);
if (err)
- goto unlock;
+ return err;
break;
default:
- err = -ENOSPC;
- goto unlock;
+ return -ENOSPC;
}
pin_flags = PIN_USER;
} while (1);
-
-unlock:
- mutex_unlock(>i915->drm.struct_mutex);
- return
[Intel-gfx] [PATCH 14/23] drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2.
This is the last part outside of selftests that still don't use the
correct lock ordering of timeline->mutex vs resv_lock.
With gem fixed, there are a few places that still get locking wrong:
- gvt/scheduler.c
- i915_perf.c
- Most if not all selftests.
Changes since v1:
- Add intel_engine_pm_get/put() calls to fix use-after-free when using
intel_engine_get_pool().
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 80 +++--
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 156 +++---
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 3 +
3 files changed, 165 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 5d94a77f9bdd..10df576e785f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -157,6 +157,7 @@ static void clear_pages_worker(struct work_struct *work)
struct clear_pages_work *w = container_of(work, typeof(*w), work);
struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
struct i915_vma *vma = w->sleeve->vma;
+ struct i915_gem_ww_ctx ww;
struct i915_request *rq;
struct i915_vma *batch;
int err = w->dma.error;
@@ -172,17 +173,20 @@ static void clear_pages_worker(struct work_struct *work)
obj->read_domains = I915_GEM_GPU_DOMAINS;
obj->write_domain = 0;
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
- if (unlikely(err))
+ i915_gem_ww_ctx_init(, false);
+ intel_engine_pm_get(w->ce->engine);
+retry:
+ err = intel_context_pin_ww(w->ce, );
+ if (err)
goto out_signal;
- batch = intel_emit_vma_fill_blt(w->ce, vma, w->value);
+ batch = intel_emit_vma_fill_blt(w->ce, vma, , w->value);
if (IS_ERR(batch)) {
err = PTR_ERR(batch);
- goto out_unpin;
+ goto out_ctx;
}
- rq = intel_context_create_request(w->ce);
+ rq = i915_request_create(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_batch;
@@ -224,9 +228,19 @@ static void clear_pages_worker(struct work_struct *work)
i915_request_add(rq);
out_batch:
intel_emit_vma_release(w->ce, batch);
-out_unpin:
- i915_vma_unpin(vma);
+out_ctx:
+ intel_context_unpin(w->ce);
out_signal:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+
+ i915_vma_unpin(w->sleeve->vma);
+ intel_engine_pm_put(w->ce->engine);
+
if (unlikely(err)) {
dma_fence_set_error(>dma, err);
dma_fence_signal(>dma);
@@ -234,6 +248,45 @@ static void clear_pages_worker(struct work_struct *work)
}
}
+static int pin_wait_clear_pages_work(struct clear_pages_work *w,
+struct intel_context *ce)
+{
+ struct i915_vma *vma = w->sleeve->vma;
+ struct i915_gem_ww_ctx ww;
+ int err;
+
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_gem_object_lock(vma->obj, );
+ if (err)
+ goto out;
+
+ err = i915_vma_pin_ww(vma, , 0, 0, PIN_USER);
+ if (unlikely(err))
+ goto out;
+
+ err = i915_sw_fence_await_reservation(>wait,
+ vma->obj->base.resv, NULL,
+ true, I915_FENCE_TIMEOUT,
+ I915_FENCE_GFP);
+ if (err)
+ goto err_unpin_vma;
+
+ dma_resv_add_excl_fence(vma->obj->base.resv, >dma);
+
+err_unpin_vma:
+ if (err)
+ i915_vma_unpin(vma);
+out:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+ return err;
+}
+
static int __i915_sw_fence_call
clear_pages_work_notify(struct i915_sw_fence *fence,
enum i915_sw_fence_notify state)
@@ -287,18 +340,9 @@ int i915_gem_schedule_fill_pages_blt(struct
drm_i915_gem_object *obj,
dma_fence_init(>dma, _pages_work_ops, _lock, 0, 0);
i915_sw_fence_init(>wait, clear_pages_work_notify);
- i915_gem_object_lock(obj, NULL);
- err = i915_sw_fence_await_reservation(>wait,
- obj->base.resv, NULL,
- true, I915_FENCE_TIMEOUT,
- I915_FENCE_GFP);
- if (err < 0) {
+ err = pin_wait_clear_pages_work(work, ce);
+ if (err < 0)
dma_fence_set_error(>dma, err);
- } else {
- dma_resv_add_excl_fence(obj->base.resv, >dma);
- err = 0;
- }
-
[Intel-gfx] [PATCH 23/23] drm/i915: Ensure we hold the pin mutex
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 9 -
drivers/gpu/drm/i915/i915_vma.h | 1 +
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c
b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index c39d73142950..df42ba06711a 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -207,7 +207,7 @@ int intel_renderstate_init(struct intel_renderstate *so,
if (err)
goto err_context;
- err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ err = i915_vma_pin_ww(so->vma, >ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
if (err)
goto err_context;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index a74f9605f334..030fafa763b0 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -868,6 +868,8 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
#ifdef CONFIG_PROVE_LOCKING
if (debug_locks && lockdep_is_held(>vm->i915->drm.struct_mutex))
WARN_ON(!ww);
+ if (debug_locks && ww && vma->resv)
+ assert_vma_held(vma);
#endif
BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND);
@@ -1008,8 +1010,13 @@ int i915_ggtt_pin(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
+ WARN_ON(!ww && vma->resv && dma_resv_held(vma->resv));
+
do {
- err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL);
+ if (ww)
+ err = i915_vma_pin_ww(vma, ww, 0, align, flags |
PIN_GLOBAL);
+ else
+ err = i915_vma_pin(vma, 0, align, flags | PIN_GLOBAL);
if (err != -ENOSPC) {
if (!err) {
err = i915_vma_wait_for_bind(vma);
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 2e3779a8a437..d937ce950481 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -242,6 +242,7 @@ i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
static inline int __must_check
i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
+ WARN_ON_ONCE(vma->resv && dma_resv_held(vma->resv));
return i915_vma_pin_ww(vma, NULL, size, alignment, flags);
}
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/23] drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2.
Make sure vma_lock is not used as inner lock when kernel context is used,
and add ww handling where appropriate.
Signed-off-by: Maarten Lankhorst
---
.../i915/gem/selftests/i915_gem_coherency.c | 26 ++--
.../drm/i915/gem/selftests/i915_gem_mman.c| 41 ++-
drivers/gpu/drm/i915/selftests/i915_request.c | 18 +---
3 files changed, 57 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 99f8466a108a..d93b7d9ad174 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -199,25 +199,25 @@ static int gpu_set(struct context *ctx, unsigned long
offset, u32 v)
i915_gem_object_lock(ctx->obj, NULL);
err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);
- i915_gem_object_unlock(ctx->obj);
if (err)
- return err;
+ goto out_unlock;
vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0);
- if (IS_ERR(vma))
- return PTR_ERR(vma);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_unlock;
+ }
rq = intel_engine_create_kernel_request(ctx->engine);
if (IS_ERR(rq)) {
- i915_vma_unpin(vma);
- return PTR_ERR(rq);
+ err = PTR_ERR(rq);
+ goto out_unpin;
}
cs = intel_ring_begin(rq, 4);
if (IS_ERR(cs)) {
- i915_request_add(rq);
- i915_vma_unpin(vma);
- return PTR_ERR(cs);
+ err = PTR_ERR(cs);
+ goto out_rq;
}
if (INTEL_GEN(ctx->engine->i915) >= 8) {
@@ -238,14 +238,16 @@ static int gpu_set(struct context *ctx, unsigned long
offset, u32 v)
}
intel_ring_advance(rq, cs);
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, true);
if (err == 0)
err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
- i915_vma_unpin(vma);
+out_rq:
i915_request_add(rq);
+out_unpin:
+ i915_vma_unpin(vma);
+out_unlock:
+ i915_gem_object_unlock(ctx->obj);
return err;
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index eec58da734bd..c8b9343cc88c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -528,31 +528,42 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
for_each_uabi_engine(engine, i915) {
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
int err;
vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
if (IS_ERR(vma))
return PTR_ERR(vma);
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_gem_object_lock(obj, );
+ if (!err)
+ err = i915_vma_pin_ww(vma, , 0, 0, PIN_USER);
if (err)
- return err;
+ goto err;
rq = intel_engine_create_kernel_request(engine);
if (IS_ERR(rq)) {
- i915_vma_unpin(vma);
- return PTR_ERR(rq);
+ err = PTR_ERR(rq);
+ goto err_unpin;
}
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, true);
if (err == 0)
err = i915_vma_move_to_active(vma, rq,
EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
i915_request_add(rq);
+err_unpin:
i915_vma_unpin(vma);
+err:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
if (err)
return err;
}
@@ -1000,6 +1011,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
for_each_uabi_engine(engine, i915) {
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
vma = i915_vma_instance(obj, engine->kernel_context->vm, NULL);
if (IS_ERR(vma)) {
@@ -1007,9 +1019,13 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
goto out_unmap;
}
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ i915_gem_ww_ctx_init(, false);
[Intel-gfx] [PATCH 16/23] drm/i915: Convert i915_perf to ww locking as well
We have the ordering of timeline->mutex vs resv_lock wrong,
convert the i915_pin_vma and intel_context_pin as well to
future-proof this.
We may need to do future changes to do this more transaction-like,
and only get down to a single i915_gem_ww_ctx, but for now this
should work.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_perf.c | 57 +++-
1 file changed, 42 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 28e3d76fa2e6..b4de6a3469bc 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1195,24 +1195,39 @@ static struct intel_context *oa_pin_context(struct
i915_perf_stream *stream)
struct i915_gem_engines_iter it;
struct i915_gem_context *ctx = stream->ctx;
struct intel_context *ce;
- int err;
+ struct i915_gem_ww_ctx ww;
+ int err = -ENODEV;
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
if (ce->engine != stream->engine) /* first match! */
continue;
- /*
-* As the ID is the gtt offset of the context's vma we
-* pin the vma to ensure the ID remains fixed.
-*/
- err = intel_context_pin(ce);
- if (err == 0) {
- stream->pinned_ctx = ce;
- break;
- }
+ err = 0;
+ break;
}
i915_gem_context_unlock_engines(ctx);
+ if (err)
+ return ERR_PTR(err);
+
+ i915_gem_ww_ctx_init(, true);
+retry:
+ /*
+* As the ID is the gtt offset of the context's vma we
+* pin the vma to ensure the ID remains fixed.
+*/
+ err = intel_context_pin_ww(ce, );
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+
+ if (err)
+ return ERR_PTR(err);
+
+ stream->pinned_ctx = ce;
return stream->pinned_ctx;
}
@@ -1927,15 +1942,22 @@ emit_oa_config(struct i915_perf_stream *stream,
{
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
int err;
vma = get_oa_vma(stream, oa_config);
if (IS_ERR(vma))
return PTR_ERR(vma);
- err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = i915_gem_object_lock(vma->obj, );
+ if (err)
+ goto err;
+
+ err = i915_vma_pin_ww(vma, , 0, 0, PIN_GLOBAL | PIN_HIGH);
if (err)
- goto err_vma_put;
+ goto err;
intel_engine_pm_get(ce->engine);
rq = i915_request_create(ce);
@@ -1957,11 +1979,9 @@ emit_oa_config(struct i915_perf_stream *stream,
goto err_add_request;
}
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, 0);
if (!err)
err = i915_vma_move_to_active(vma, rq, 0);
- i915_vma_unlock(vma);
if (err)
goto err_add_request;
@@ -1975,7 +1995,14 @@ emit_oa_config(struct i915_perf_stream *stream,
i915_request_add(rq);
err_vma_unpin:
i915_vma_unpin(vma);
-err_vma_put:
+err:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+
+ i915_gem_ww_ctx_fini();
i915_vma_put(vma);
return err;
}
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/23] drm/i915: Nuke arguments to eb_pin_engine
Those arguments are already set as eb.file and eb.args, so kill off
the extra arguments. This will allow us to move eb_pin_engine() to
after we reserved all BO's.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index dd3aff4ac3fb..7fef5a85ecde 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2428,11 +2428,10 @@ static void eb_unpin_engine(struct i915_execbuffer *eb)
}
static unsigned int
-eb_select_legacy_ring(struct i915_execbuffer *eb,
- struct drm_file *file,
- struct drm_i915_gem_execbuffer2 *args)
+eb_select_legacy_ring(struct i915_execbuffer *eb)
{
struct drm_i915_private *i915 = eb->i915;
+ struct drm_i915_gem_execbuffer2 *args = eb->args;
unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
if (user_ring_id != I915_EXEC_BSD &&
@@ -2447,7 +2446,7 @@ eb_select_legacy_ring(struct i915_execbuffer *eb,
unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
- bsd_idx = gen8_dispatch_bsd_engine(i915, file);
+ bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file);
} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
bsd_idx <= I915_EXEC_BSD_RING2) {
bsd_idx >>= I915_EXEC_BSD_SHIFT;
@@ -2472,18 +2471,16 @@ eb_select_legacy_ring(struct i915_execbuffer *eb,
}
static int
-eb_pin_engine(struct i915_execbuffer *eb,
- struct drm_file *file,
- struct drm_i915_gem_execbuffer2 *args)
+eb_pin_engine(struct i915_execbuffer *eb)
{
struct intel_context *ce;
unsigned int idx;
int err;
if (i915_gem_context_user_engines(eb->gem_context))
- idx = args->flags & I915_EXEC_RING_MASK;
+ idx = eb->args->flags & I915_EXEC_RING_MASK;
else
- idx = eb_select_legacy_ring(eb, file, args);
+ idx = eb_select_legacy_ring(eb);
ce = i915_gem_context_get_engine(eb->gem_context, idx);
if (IS_ERR(ce))
@@ -2781,7 +2778,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_destroy;
- err = eb_pin_engine(, file, args);
+ err = eb_pin_engine();
if (unlikely(err))
goto err_context;
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 21/23] drm/i915: Add ww locking to vm_fault_gtt
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 51 +++-
1 file changed, 33 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index b39c24dae64e..e35e8d0b6938 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -283,37 +283,46 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
struct intel_runtime_pm *rpm = >runtime_pm;
struct i915_ggtt *ggtt = >ggtt;
bool write = area->vm_flags & VM_WRITE;
+ struct i915_gem_ww_ctx ww;
intel_wakeref_t wakeref;
struct i915_vma *vma;
pgoff_t page_offset;
int srcu;
int ret;
- /* Sanity check that we allow writing into this object */
- if (i915_gem_object_is_readonly(obj) && write)
- return VM_FAULT_SIGBUS;
-
/* We don't use vmf->pgoff since that has the fake offset */
page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
trace_i915_gem_object_fault(obj, page_offset, true, write);
- ret = i915_gem_object_pin_pages(obj);
+ wakeref = intel_runtime_pm_get(rpm);
+
+ i915_gem_ww_ctx_init(, true);
+retry:
+ ret = i915_gem_object_lock(obj, );
if (ret)
- goto err;
+ goto err_rpm;
- wakeref = intel_runtime_pm_get(rpm);
+ /* Sanity check that we allow writing into this object */
+ if (i915_gem_object_is_readonly(obj) && write) {
+ ret = -EFAULT;
+ goto err_rpm;
+ }
- ret = intel_gt_reset_trylock(ggtt->vm.gt, );
+ ret = i915_gem_object_pin_pages(obj);
if (ret)
goto err_rpm;
+ ret = intel_gt_reset_trylock(ggtt->vm.gt, );
+ if (ret)
+ goto err_pages;
+
/* Now pin it into the GTT as needed */
- vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
- PIN_MAPPABLE |
- PIN_NONBLOCK /* NOWARN */ |
- PIN_NOEVICT);
- if (IS_ERR(vma)) {
+ vma = i915_gem_object_ggtt_pin_ww(obj, , NULL, 0, 0,
+ PIN_MAPPABLE |
+ PIN_NONBLOCK /* NOWARN */ |
+ PIN_NOEVICT);
+ if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) {
/* Use a partial view if it is bigger than available space */
struct i915_ggtt_view view =
compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
@@ -328,11 +337,11 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
* all hope that the hardware is able to track future writes.
*/
- vma = i915_gem_object_ggtt_pin(obj, , 0, 0, flags);
- if (IS_ERR(vma)) {
+ vma = i915_gem_object_ggtt_pin_ww(obj, , , 0, 0, flags);
+ if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) {
flags = PIN_MAPPABLE;
view.type = I915_GGTT_VIEW_PARTIAL;
- vma = i915_gem_object_ggtt_pin(obj, , 0, 0, flags);
+ vma = i915_gem_object_ggtt_pin_ww(obj, , , 0,
0, flags);
}
/* The entire mappable GGTT is pinned? Unexpected! */
@@ -389,10 +398,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
__i915_vma_unpin(vma);
err_reset:
intel_gt_reset_unlock(ggtt->vm.gt, srcu);
+err_pages:
+ i915_gem_object_unpin_pages(obj);
err_rpm:
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff();
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
intel_runtime_pm_put(rpm, wakeref);
- i915_gem_object_unpin_pages(obj);
-err:
return i915_error_to_vmf_fault(ret);
}
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/23] drm/i915: Kill last user of intel_context_create_request outside of selftests
Instead of using intel_context_create_request(), use intel_context_pin()
and i915_create_request directly.
Now all those calls are gone outside of selftests. :)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 ++---
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e96cc7fa0936..d866f5903554 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1744,6 +1744,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
const struct i915_wa *wa;
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
unsigned int i;
u32 *results;
int err;
@@ -1756,29 +1757,34 @@ static int engine_wa_list_verify(struct intel_context
*ce,
return PTR_ERR(vma);
intel_engine_pm_get(ce->engine);
- rq = intel_context_create_request(ce);
- intel_engine_pm_put(ce->engine);
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_gem_object_lock(vma->obj, );
+ if (err == 0)
+ err = intel_context_pin_ww(ce, );
+ if (err)
+ goto err_pm;
+
+ rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- goto err_vma;
+ goto err_unpin;
}
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, true);
if (err == 0)
err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
- if (err) {
- i915_request_add(rq);
- goto err_vma;
- }
-
- err = wa_list_srm(rq, wal, vma);
- if (err)
- goto err_vma;
+ if (err == 0)
+ err = wa_list_srm(rq, wal, vma);
i915_request_get(rq);
+ if (err)
+ i915_request_set_error_once(rq, err);
i915_request_add(rq);
+
+ if (err)
+ goto err_rq;
+
if (i915_request_wait(rq, 0, HZ / 5) < 0) {
err = -ETIME;
goto err_rq;
@@ -1803,7 +1809,16 @@ static int engine_wa_list_verify(struct intel_context
*ce,
err_rq:
i915_request_put(rq);
-err_vma:
+err_unpin:
+ intel_context_unpin(ce);
+err_pm:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+ intel_engine_pm_put(ce->engine);
i915_vma_unpin(vma);
i915_vma_put(vma);
return err;
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/23] drm/i915: Dirty hack to fix selftests locking inversion
Some i915 selftests still use i915_vma_lock() as inner lock, and intel_context_create_request() intel_timeline->mutex as outer lock. Fortunately for selftests this is not an issue, they should be fixed but we can move ahead and cleanify lockdep now. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_context.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 113d0bda1bcf..5c7acddf9651 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -460,6 +460,18 @@ struct i915_request *intel_context_create_request(struct intel_context *ce) rq = i915_request_create(ce); intel_context_unpin(ce); + if (IS_ERR(rq)) + return rq; + + /* +* timeline->mutex should be the inner lock, but is used as outer lock. +* Hack around this to shut up lockdep in selftests.. +*/ + lockdep_unpin_lock(>timeline->mutex, rq->cookie); + mutex_release(>timeline->mutex.dep_map, _RET_IP_); + mutex_acquire(>timeline->mutex.dep_map, SINGLE_DEPTH_NESTING, 0, _RET_IP_); + rq->cookie = lockdep_pin_lock(>timeline->mutex); + return rq; } -- 2.25.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/23] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2.
i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory
eviction. We don't use it yet, but lets start adding the definition
first.
To use it, we have to pass a non-NULL ww to gem_object_lock, and don't
unlock directly. It is done in i915_gem_ww_ctx_fini.
Changes since v1:
- Change ww_ctx and obj order in locking functions (Jonas Lahtinen)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 10 ++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 38 +++---
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../i915/gem/selftests/i915_gem_coherency.c | 10 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 4 +-
.../drm/i915/gem/selftests/i915_gem_phys.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 52 +--
drivers/gpu/drm/i915/i915_gem.h | 11
drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++
drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +-
.../drm/i915/selftests/intel_memory_region.c | 2 +-
26 files changed, 175 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e09a11b1e509..2e2e5ce82dc2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2303,7 +2303,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
{
- i915_gem_object_lock(vma->obj);
+ i915_gem_object_lock(vma->obj, NULL);
if (flags & PLANE_HAS_FENCE)
i915_vma_unpin_fence(vma);
i915_gem_object_unpin_from_display_plane(vma);
@@ -17047,7 +17047,7 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
if (!intel_fb->frontbuffer)
return -ENOMEM;
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
tiling = i915_gem_object_get_tiling(obj);
stride = i915_gem_object_get_stride(obj);
i915_gem_object_unlock(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 0598e5382a1d..5d94a77f9bdd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -287,7 +287,7 @@ int i915_gem_schedule_fill_pages_blt(struct
drm_i915_gem_object *obj,
dma_fence_init(>dma, _pages_work_ops, _lock, 0, 0);
i915_sw_fence_init(>wait, clear_pages_work_notify);
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
err = i915_sw_fence_await_reservation(>wait,
obj->base.resv, NULL,
true, I915_FENCE_TIMEOUT,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 50e7580f9337..ac2b88ca00ce 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx)
continue;
rcu_read_unlock();
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
list_for_each_entry(lut, >lut_list, obj_link) {
if (lut->ctx != ctx)
continue;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 7db5a793739d..cfadccfc2990 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf
*dma_buf, enum dma_data_dire
if (err)
return err;
- err = i915_gem_object_lock_interruptible(obj);
+ err = i915_gem_object_lock_interruptible(obj, NULL);
if (err)
goto out;
@@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf,
enum dma_data_direct
if (err)
return err;
-
[Intel-gfx] [PATCH 01/23] perf/core: Only copy-to-user after completely unlocking all locks, v2.
We inadvertently create a dependency on mmap_sem with a whole chain.
This breaks any user who wants to take a lock and call rcu_barrier(),
while also taking that lock inside mmap_sem:
<4> [604.892532] ==
<4> [604.892534] WARNING: possible circular locking dependency detected
<4> [604.892536] 5.6.0-rc7-CI-Patchwork_17096+ #1 Tainted: G U
<4> [604.892537] --
<4> [604.892538] kms_frontbuffer/2595 is trying to acquire lock:
<4> [604.892540] 8264a558 (rcu_state.barrier_mutex){+.+.}, at:
rcu_barrier+0x23/0x190
<4> [604.892547]
but task is already holding lock:
<4> [604.892547] 888484716050 (reservation_ww_class_mutex){+.+.}, at:
i915_gem_object_pin_to_display_plane+0x89/0x270 [i915]
<4> [604.892592]
which lock already depends on the new lock.
<4> [604.892593]
the existing dependency chain (in reverse order) is:
<4> [604.892594]
-> #6 (reservation_ww_class_mutex){+.+.}:
<4> [604.892597]__ww_mutex_lock.constprop.15+0xc3/0x1090
<4> [604.892598]ww_mutex_lock+0x39/0x70
<4> [604.892600]dma_resv_lockdep+0x10e/0x1f5
<4> [604.892602]do_one_initcall+0x58/0x300
<4> [604.892604]kernel_init_freeable+0x17b/0x1dc
<4> [604.892605]kernel_init+0x5/0x100
<4> [604.892606]ret_from_fork+0x24/0x50
<4> [604.892607]
-> #5 (reservation_ww_class_acquire){+.+.}:
<4> [604.892609]dma_resv_lockdep+0xec/0x1f5
<4> [604.892610]do_one_initcall+0x58/0x300
<4> [604.892610]kernel_init_freeable+0x17b/0x1dc
<4> [604.892611]kernel_init+0x5/0x100
<4> [604.892612]ret_from_fork+0x24/0x50
<4> [604.892613]
-> #4 (>mmap_sem#2){}:
<4> [604.892615]__might_fault+0x63/0x90
<4> [604.892617]_copy_to_user+0x1e/0x80
<4> [604.892619]perf_read+0x200/0x2b0
<4> [604.892621]vfs_read+0x96/0x160
<4> [604.892622]ksys_read+0x9f/0xe0
<4> [604.892623]do_syscall_64+0x4f/0x220
<4> [604.892624]entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4> [604.892625]
-> #3 (_mutex){+.+.}:
<4> [604.892626]__mutex_lock+0x9a/0x9c0
<4> [604.892627]perf_event_init_cpu+0xa4/0x140
<4> [604.892629]perf_event_init+0x19d/0x1cd
<4> [604.892630]start_kernel+0x362/0x4e4
<4> [604.892631]secondary_startup_64+0xa4/0xb0
<4> [604.892631]
-> #2 (pmus_lock){+.+.}:
<4> [604.892633]__mutex_lock+0x9a/0x9c0
<4> [604.892633]perf_event_init_cpu+0x6b/0x140
<4> [604.892635]cpuhp_invoke_callback+0x9b/0x9d0
<4> [604.892636]_cpu_up+0xa2/0x140
<4> [604.892637]do_cpu_up+0x61/0xa0
<4> [604.892639]smp_init+0x57/0x96
<4> [604.892639]kernel_init_freeable+0x87/0x1dc
<4> [604.892640]kernel_init+0x5/0x100
<4> [604.892642]ret_from_fork+0x24/0x50
<4> [604.892642]
-> #1 (cpu_hotplug_lock.rw_sem){}:
<4> [604.892643]cpus_read_lock+0x34/0xd0
<4> [604.892644]rcu_barrier+0xaa/0x190
<4> [604.892645]kernel_init+0x21/0x100
<4> [604.892647]ret_from_fork+0x24/0x50
<4> [604.892647]
-> #0 (rcu_state.barrier_mutex){+.+.}:
<4> [604.892649]__lock_acquire+0x1328/0x15d0
<4> [604.892650]lock_acquire+0xa7/0x1c0
<4> [604.892651]__mutex_lock+0x9a/0x9c0
<4> [604.892652]rcu_barrier+0x23/0x190
<4> [604.892680]i915_gem_object_unbind+0x29d/0x3f0 [i915]
<4> [604.892707]i915_gem_object_pin_to_display_plane+0x141/0x270 [i915]
<4> [604.892737]intel_pin_and_fence_fb_obj+0xec/0x1f0 [i915]
<4> [604.892767]intel_plane_pin_fb+0x3f/0xd0 [i915]
<4> [604.892797]intel_prepare_plane_fb+0x13b/0x5c0 [i915]
<4> [604.892798]drm_atomic_helper_prepare_planes+0x85/0x110
<4> [604.892827]intel_atomic_commit+0xda/0x390 [i915]
<4> [604.892828]drm_atomic_helper_set_config+0x57/0xa0
<4> [604.892830]drm_mode_setcrtc+0x1c4/0x720
<4> [604.892830]drm_ioctl_kernel+0xb0/0xf0
<4> [604.892831]drm_ioctl+0x2e1/0x390
<4> [604.892833]ksys_ioctl+0x7b/0x90
<4> [604.892835]__x64_sys_ioctl+0x11/0x20
<4> [604.892835]do_syscall_64+0x4f/0x220
<4> [604.892836]entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4> [604.892837]
Changes since v1:
- Use (*values)[n++] in perf_read_one().
Signed-off-by: Maarten Lankhorst
---
kernel/events/core.c | 59 +++-
1 file changed, 31 insertions(+), 28 deletions(-)
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 085d9263d595..cf2e19f8130b 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -4926,20 +4926,20 @@ static int __perf_read_group_add(struct perf_event
*leader,
}
static int perf_read_group(struct perf_event *event,
- u64 read_format, char __user *buf)
+ u64 read_format, char __user *buf,
+ u64 **values)
{
struct perf_event
[Intel-gfx] [PATCH 05/23] drm/i915: Parse command buffer earlier in eb_relocate(slow)
We want to introduce backoff logic, but we need to lock the
pool object as well for command parsing. Because of this, we
will need backoff logic for the engine pool obj, move the batch
validation up slightly to eb_lookup_vmas, and the actual command
parsing in a separate function which can get called from execbuf
relocation fast and slowpath.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 68 ++-
1 file changed, 37 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 55066dc0e1fe..1e9e89603e91 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -290,6 +290,8 @@ struct i915_execbuffer {
struct eb_vma_array *array;
};
+static int eb_parse(struct i915_execbuffer *eb);
+
static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
{
return intel_engine_requires_cmd_parser(eb->engine) ||
@@ -873,6 +875,7 @@ static struct i915_vma *eb_lookup_vma(struct
i915_execbuffer *eb, u32 handle)
static int eb_lookup_vmas(struct i915_execbuffer *eb)
{
+ struct drm_i915_private *i915 = eb->i915;
unsigned int batch = eb_batch_index(eb);
unsigned int i;
int err = 0;
@@ -886,18 +889,37 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
vma = eb_lookup_vma(eb, eb->exec[i].handle);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
- break;
+ goto err;
}
err = eb_validate_vma(eb, >exec[i], vma);
if (unlikely(err)) {
i915_vma_put(vma);
- break;
+ goto err;
}
eb_add_vma(eb, i, batch, vma);
}
+ if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) {
+ drm_dbg(>drm,
+ "Attempting to use self-modifying batch buffer\n");
+ return -EINVAL;
+ }
+
+ if (range_overflows_t(u64,
+ eb->batch_start_offset, eb->batch_len,
+ eb->batch->vma->size)) {
+ drm_dbg(>drm, "Attempting to use out-of-bounds batch\n");
+ return -EINVAL;
+ }
+
+ if (eb->batch_len == 0)
+ eb->batch_len = eb->batch->vma->size - eb->batch_start_offset;
+
+ return 0;
+
+err:
eb->vma[i].vma = NULL;
return err;
}
@@ -1727,7 +1749,7 @@ static int eb_prefault_relocations(const struct
i915_execbuffer *eb)
return 0;
}
-static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
+static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb)
{
bool have_copy = false;
struct eb_vma *ev;
@@ -1778,6 +1800,11 @@ static noinline int eb_relocate_slow(struct
i915_execbuffer *eb)
}
}
+ /* as last step, parse the command buffer */
+ err = eb_parse(eb);
+ if (err)
+ goto err;
+
/*
* Leave the user relocations as are, this is the painfully slow path,
* and we want to avoid the complication of dropping the lock whilst
@@ -1810,7 +1837,7 @@ static noinline int eb_relocate_slow(struct
i915_execbuffer *eb)
return err;
}
-static int eb_relocate(struct i915_execbuffer *eb)
+static int eb_relocate_parse(struct i915_execbuffer *eb)
{
int err;
@@ -1830,11 +1857,11 @@ static int eb_relocate(struct i915_execbuffer *eb)
list_for_each_entry(ev, >relocs, reloc_link) {
if (eb_relocate_vma(eb, ev))
- return eb_relocate_slow(eb);
+ return eb_relocate_parse_slow(eb);
}
}
- return 0;
+ return eb_parse(eb);
}
static int eb_move_to_gpu(struct i915_execbuffer *eb)
@@ -2765,7 +2792,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_context;
- err = eb_relocate();
+ err = eb_relocate_parse();
if (err) {
/*
* If the user expects the execobject.offset and
@@ -2778,33 +2805,10 @@ i915_gem_do_execbuffer(struct drm_device *dev,
goto err_vma;
}
- if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) {
- drm_dbg(>drm,
- "Attempting to use self-modifying batch buffer\n");
- err = -EINVAL;
- goto err_vma;
- }
-
- if (range_overflows_t(u64,
- eb.batch_start_offset, eb.batch_len,
- eb.batch->vma->size)) {
- drm_dbg(>drm, "Attempting to use out-of-bounds batch\n");
- err = -EINVAL;
- goto err_vma;
- }
-
-
[Intel-gfx] [PATCH 04/23] drm/i915: Remove locking from i915_gem_object_prepare_read/write
Execbuffer submission will perform its own WW locking, and we
cannot rely on the implicit lock there.
This also makes it clear that the GVT code will get a lockdep splat when
multiple batchbuffer shadows need to be performed in the same instance,
fix that up.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 20 ++-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 13 ++--
drivers/gpu/drm/i915/gem/i915_gem_object.h| 1 -
.../gpu/drm/i915/gem/selftests/huge_pages.c | 5 -
.../i915/gem/selftests/i915_gem_coherency.c | 14 +
.../drm/i915/gem/selftests/i915_gem_context.c | 12 ---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 5 -
drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 -
drivers/gpu/drm/i915/i915_gem.c | 20 +--
9 files changed, 70 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 066310564b1a..1a3dd77a35b9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -581,19 +581,17 @@ int i915_gem_object_prepare_read(struct
drm_i915_gem_object *obj,
if (!i915_gem_object_has_struct_page(obj))
return -ENODEV;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
+ assert_object_held(obj);
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE,
MAX_SCHEDULE_TIMEOUT);
if (ret)
- goto err_unlock;
+ return ret;
ret = i915_gem_object_pin_pages(obj);
if (ret)
- goto err_unlock;
+ return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
!static_cpu_has(X86_FEATURE_CLFLUSH)) {
@@ -621,8 +619,6 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object
*obj,
err_unpin:
i915_gem_object_unpin_pages(obj);
-err_unlock:
- i915_gem_object_unlock(obj);
return ret;
}
@@ -635,20 +631,18 @@ int i915_gem_object_prepare_write(struct
drm_i915_gem_object *obj,
if (!i915_gem_object_has_struct_page(obj))
return -ENODEV;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
+ assert_object_held(obj);
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE |
I915_WAIT_ALL,
MAX_SCHEDULE_TIMEOUT);
if (ret)
- goto err_unlock;
+ return ret;
ret = i915_gem_object_pin_pages(obj);
if (ret)
- goto err_unlock;
+ return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
!static_cpu_has(X86_FEATURE_CLFLUSH)) {
@@ -685,7 +679,5 @@ int i915_gem_object_prepare_write(struct
drm_i915_gem_object *obj,
err_unpin:
i915_gem_object_unpin_pages(obj);
-err_unlock:
- i915_gem_object_unlock(obj);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 7cc5f9c1cea3..55066dc0e1fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1001,11 +1001,14 @@ static void reloc_cache_reset(struct reloc_cache *cache)
vaddr = unmask_page(cache->vaddr);
if (cache->vaddr & KMAP) {
+ struct drm_i915_gem_object *obj =
+ (struct drm_i915_gem_object *)cache->node.mm;
if (cache->vaddr & CLFLUSH_AFTER)
mb();
kunmap_atomic(vaddr);
- i915_gem_object_finish_access((struct drm_i915_gem_object
*)cache->node.mm);
+ i915_gem_object_finish_access(obj);
+ i915_gem_object_unlock(obj);
} else {
struct i915_ggtt *ggtt = cache_to_ggtt(cache);
@@ -1040,10 +1043,16 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,
unsigned int flushes;
int err;
- err = i915_gem_object_prepare_write(obj, );
+ err = i915_gem_object_lock_interruptible(obj, NULL);
if (err)
return ERR_PTR(err);
+ err = i915_gem_object_prepare_write(obj, );
+ if (err) {
+ i915_gem_object_unlock(obj);
+ return ERR_PTR(err);
+ }
+
BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 5103067269b0..11b8e2735071 100644
[Intel-gfx] [PATCH 13/23] drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin.
As a preparation step for full object locking and wait/wound handling
during pin and object mapping, ensure that we always pass the ww context
in i915_gem_execbuffer.c to i915_vma_pin, use lockdep to ensure this
happens.
This also requires changing the order of eb_parse slightly, to ensure
we pass ww at a point where we could still handle -EDEADLK safely.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 136 ++
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 4 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 4 +-
drivers/gpu/drm/i915/gt/intel_context.c | 65 +
drivers/gpu/drm/i915/gt/intel_context.h | 13 ++
drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ring.c | 10 +-
drivers/gpu/drm/i915/gt/intel_ring.h | 3 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 15 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 12 +-
drivers/gpu/drm/i915/gt/intel_timeline.h | 3 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 13 +-
drivers/gpu/drm/i915/i915_gem.c | 11 +-
drivers/gpu/drm/i915/i915_vma.c | 13 +-
drivers/gpu/drm/i915/i915_vma.h | 13 +-
24 files changed, 213 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2e2e5ce82dc2..a429e90956f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3441,7 +3441,7 @@ initial_plane_vma(struct drm_i915_private *i915,
if (IS_ERR(vma))
goto err_obj;
- if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
+ if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
goto err_obj;
if (i915_gem_object_is_tiled(obj) &&
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 062848951095..f5b01e70eb61 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1145,7 +1145,7 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
i915_gem_ww_ctx_init(, true);
retry:
- err = intel_context_pin(ce);
+ err = intel_context_pin_ww(ce, );
if (err)
goto err;
@@ -1238,7 +1238,7 @@ static int pin_ppgtt_update(struct intel_context *ce,
struct i915_gem_ww_ctx *ww
if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915))
/* ppGTT is not part of the legacy context image */
- return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm));
+ return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm), ww);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ed111af8f264..d7bf96e9986a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -421,16 +421,17 @@ eb_pin_vma(struct i915_execbuffer *eb,
pin_flags |= PIN_GLOBAL;
/* Attempt to reuse the current location if available */
- if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) {
+ /* TODO: Add -EDEADLK handling here */
+ if (unlikely(i915_vma_pin_ww(vma, >ww, 0, 0, pin_flags))) {
if (entry->flags & EXEC_OBJECT_PINNED)
return false;
/* Failing that pick any _free_ space if suitable */
- if (unlikely(i915_vma_pin(vma,
- entry->pad_to_size,
- entry->alignment,
- eb_pin_flags(entry, ev->flags) |
- PIN_USER | PIN_NOEVICT)))
+ if (unlikely(i915_vma_pin_ww(vma, >ww,
+entry->pad_to_size,
+entry->alignment,
+eb_pin_flags(entry, ev->flags) |
+PIN_USER | PIN_NOEVICT)))
return false;
}
@@ -572,7 +573,7 @@ static inline int use_cpu_reloc(const struct reloc_cache
*cache,
obj->cache_level != I915_CACHE_NONE);
}
-static int eb_reserve_vma(const struct
[Intel-gfx] [PATCH 12/23] drm/i915: Rework intel_context pinning to do everything outside of pin_mutex
Instead of doing everything inside of pin_mutex, we move all pinning
outside. Because i915_active has its own reference counting and
pinning is also having the same issues vs mutexes, we make sure
everything is pinned first, so the pinning in i915_active only needs
to bump refcounts. This allows us to take pin refcounts correctly
all the time.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_context.c | 233 +++---
drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 34 ++-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 1 -
.../gpu/drm/i915/gt/intel_ring_submission.c | 13 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 13 +-
6 files changed, 191 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index e4aece20bc80..bc0ed268ccb8 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -93,79 +93,6 @@ static void intel_context_active_release(struct
intel_context *ce)
i915_active_release(>active);
}
-int __intel_context_do_pin(struct intel_context *ce)
-{
- int err;
-
- if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, >flags))) {
- err = intel_context_alloc_state(ce);
- if (err)
- return err;
- }
-
- err = i915_active_acquire(>active);
- if (err)
- return err;
-
- if (mutex_lock_interruptible(>pin_mutex)) {
- err = -EINTR;
- goto out_release;
- }
-
- if (unlikely(intel_context_is_closed(ce))) {
- err = -ENOENT;
- goto out_unlock;
- }
-
- if (likely(!atomic_add_unless(>pin_count, 1, 0))) {
- err = intel_context_active_acquire(ce);
- if (unlikely(err))
- goto out_unlock;
-
- err = ce->ops->pin(ce);
- if (unlikely(err))
- goto err_active;
-
- CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n",
-i915_ggtt_offset(ce->ring->vma),
-ce->ring->head, ce->ring->tail);
-
- smp_mb__before_atomic(); /* flush pin before it is visible */
- atomic_inc(>pin_count);
- }
-
- GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */
- GEM_BUG_ON(i915_active_is_idle(>active));
- goto out_unlock;
-
-err_active:
- intel_context_active_release(ce);
-out_unlock:
- mutex_unlock(>pin_mutex);
-out_release:
- i915_active_release(>active);
- return err;
-}
-
-void intel_context_unpin(struct intel_context *ce)
-{
- if (!atomic_dec_and_test(>pin_count))
- return;
-
- CE_TRACE(ce, "unpin\n");
- ce->ops->unpin(ce);
-
- /*
-* Once released, we may asynchronously drop the active reference.
-* As that may be the only reference keeping the context alive,
-* take an extra now so that it is not freed before we finish
-* dereferencing it.
-*/
- intel_context_get(ce);
- intel_context_active_release(ce);
- intel_context_put(ce);
-}
-
static int __context_pin_state(struct i915_vma *vma)
{
unsigned int bias = i915_ggtt_pin_bias(vma) | PIN_OFFSET_BIAS;
@@ -225,6 +152,138 @@ static void __ring_retire(struct intel_ring *ring)
i915_active_release(>vma->active);
}
+static int intel_context_pre_pin(struct intel_context *ce)
+{
+ int err;
+
+ CE_TRACE(ce, "active\n");
+
+ err = __ring_active(ce->ring);
+ if (err)
+ return err;
+
+ err = intel_timeline_pin(ce->timeline);
+ if (err)
+ goto err_ring;
+
+ if (!ce->state)
+ return 0;
+
+ err = __context_pin_state(ce->state);
+ if (err)
+ goto err_timeline;
+
+
+ return 0;
+
+err_timeline:
+ intel_timeline_unpin(ce->timeline);
+err_ring:
+ __ring_retire(ce->ring);
+ return err;
+}
+
+static void intel_context_post_unpin(struct intel_context *ce)
+{
+ if (ce->state)
+ __context_unpin_state(ce->state);
+
+ intel_timeline_unpin(ce->timeline);
+ __ring_retire(ce->ring);
+}
+
+int __intel_context_do_pin(struct intel_context *ce)
+{
+ bool handoff = false;
+ void *vaddr;
+ int err = 0;
+
+ if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, >flags))) {
+ err = intel_context_alloc_state(ce);
+ if (err)
+ return err;
+ }
+
+ /*
+* We always pin the context/ring/timeline here, to ensure a pin
+* refcount for __intel_context_active(), which prevent a lock
+* inversion of ce->pin_mutex vs dma_resv_lock().
+*/
+ err = intel_context_pre_pin(ce);
+ if (err)
+ return
[Intel-gfx] [PATCH 09/23] drm/i915: Add ww context handling to context_barrier_task
This is required if we want to pass a ww context in intel_context_pin
and gen6_ppgtt_pin().
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 55 ++-
.../drm/i915/gem/selftests/i915_gem_context.c | 22 +++-
2 files changed, 48 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ac2b88ca00ce..062848951095 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1097,6 +1097,7 @@ I915_SELFTEST_DECLARE(static intel_engine_mask_t
context_barrier_inject_fault);
static int context_barrier_task(struct i915_gem_context *ctx,
intel_engine_mask_t engines,
bool (*skip)(struct intel_context *ce, void
*data),
+ int (*pin)(struct intel_context *ce, struct
i915_gem_ww_ctx *ww, void *data),
int (*emit)(struct i915_request *rq, void
*data),
void (*task)(void *data),
void *data)
@@ -1104,6 +1105,7 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
struct context_barrier_task *cb;
struct i915_gem_engines_iter it;
struct i915_gem_engines *e;
+ struct i915_gem_ww_ctx ww;
struct intel_context *ce;
int err = 0;
@@ -1141,10 +1143,21 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
if (skip && skip(ce, data))
continue;
- rq = intel_context_create_request(ce);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = intel_context_pin(ce);
+ if (err)
+ goto err;
+
+ if (pin)
+ err = pin(ce, , data);
+ if (err)
+ goto err_unpin;
+
+ rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- break;
+ goto err_unpin;
}
err = 0;
@@ -1154,6 +1167,16 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
err = i915_active_add_request(>base, rq);
i915_request_add(rq);
+err_unpin:
+ intel_context_unpin(ce);
+err:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+
if (err)
break;
}
@@ -1209,6 +1232,17 @@ static void set_ppgtt_barrier(void *data)
i915_vm_close(old);
}
+static int pin_ppgtt_update(struct intel_context *ce, struct i915_gem_ww_ctx
*ww, void *data)
+{
+ struct i915_address_space *vm = ce->vm;
+
+ if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915))
+ /* ppGTT is not part of the legacy context image */
+ return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm));
+
+ return 0;
+}
+
static int emit_ppgtt_update(struct i915_request *rq, void *data)
{
struct i915_address_space *vm = rq->context->vm;
@@ -1265,20 +1299,10 @@ static int emit_ppgtt_update(struct i915_request *rq,
void *data)
static bool skip_ppgtt_update(struct intel_context *ce, void *data)
{
- if (!test_bit(CONTEXT_ALLOC_BIT, >flags))
- return true;
-
if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
- return false;
-
- if (!atomic_read(>pin_count))
- return true;
-
- /* ppGTT is not part of the legacy context image */
- if (gen6_ppgtt_pin(i915_vm_to_ppgtt(ce->vm)))
- return true;
-
- return false;
+ return !ce->state;
+ else
+ return !atomic_read(>pin_count);
}
static int set_ppgtt(struct drm_i915_file_private *file_priv,
@@ -1329,6 +1353,7 @@ static int set_ppgtt(struct drm_i915_file_private
*file_priv,
*/
err = context_barrier_task(ctx, ALL_ENGINES,
skip_ppgtt_update,
+ pin_ppgtt_update,
emit_ppgtt_update,
set_ppgtt_barrier,
old);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 42edbd0f3c14..78356031ec61 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1903,8 +1903,8 @@ static int mock_context_barrier(void *arg)
return -ENOMEM;
counter = 0;
- err = context_barrier_task(ctx, 0,
- NULL, NULL,
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Utilize rcu iteration of context engines (rev3)
== Series Details == Series: drm/i915/gem: Utilize rcu iteration of context engines (rev3) URL : https://patchwork.freedesktop.org/series/75270/ State : success == Summary == CI Bug Log - changes from CI_DRM_8238 -> Patchwork_17181 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17181/index.html Changes --- No changes found Participating hosts (50 -> 43) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8238 -> Patchwork_17181 CI-20190529: 20190529 CI_DRM_8238: 840f70602a47208a2f1e444ba276f412f10e38df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5558: 3b55a816300d80bc5e0b995cd41ee8c8649a1ea2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17181: 92fc6f8ff1aacb1926e17b399dfa898b17997e36 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 92fc6f8ff1aa drm/i915/gem: Utilize rcu iteration of context engines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17181/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] perf/core: Only copy-to-user after completely unlocking all locks, v2.
We inadvertently create a dependency on mmap_sem with a whole chain.
This breaks any user who wants to take a lock and call rcu_barrier(),
while also taking that lock inside mmap_sem:
<4> [604.892532] ==
<4> [604.892534] WARNING: possible circular locking dependency detected
<4> [604.892536] 5.6.0-rc7-CI-Patchwork_17096+ #1 Tainted: G U
<4> [604.892537] --
<4> [604.892538] kms_frontbuffer/2595 is trying to acquire lock:
<4> [604.892540] 8264a558 (rcu_state.barrier_mutex){+.+.}, at:
rcu_barrier+0x23/0x190
<4> [604.892547]
but task is already holding lock:
<4> [604.892547] 888484716050 (reservation_ww_class_mutex){+.+.}, at:
i915_gem_object_pin_to_display_plane+0x89/0x270 [i915]
<4> [604.892592]
which lock already depends on the new lock.
<4> [604.892593]
the existing dependency chain (in reverse order) is:
<4> [604.892594]
-> #6 (reservation_ww_class_mutex){+.+.}:
<4> [604.892597]__ww_mutex_lock.constprop.15+0xc3/0x1090
<4> [604.892598]ww_mutex_lock+0x39/0x70
<4> [604.892600]dma_resv_lockdep+0x10e/0x1f5
<4> [604.892602]do_one_initcall+0x58/0x300
<4> [604.892604]kernel_init_freeable+0x17b/0x1dc
<4> [604.892605]kernel_init+0x5/0x100
<4> [604.892606]ret_from_fork+0x24/0x50
<4> [604.892607]
-> #5 (reservation_ww_class_acquire){+.+.}:
<4> [604.892609]dma_resv_lockdep+0xec/0x1f5
<4> [604.892610]do_one_initcall+0x58/0x300
<4> [604.892610]kernel_init_freeable+0x17b/0x1dc
<4> [604.892611]kernel_init+0x5/0x100
<4> [604.892612]ret_from_fork+0x24/0x50
<4> [604.892613]
-> #4 (>mmap_sem#2){}:
<4> [604.892615]__might_fault+0x63/0x90
<4> [604.892617]_copy_to_user+0x1e/0x80
<4> [604.892619]perf_read+0x200/0x2b0
<4> [604.892621]vfs_read+0x96/0x160
<4> [604.892622]ksys_read+0x9f/0xe0
<4> [604.892623]do_syscall_64+0x4f/0x220
<4> [604.892624]entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4> [604.892625]
-> #3 (_mutex){+.+.}:
<4> [604.892626]__mutex_lock+0x9a/0x9c0
<4> [604.892627]perf_event_init_cpu+0xa4/0x140
<4> [604.892629]perf_event_init+0x19d/0x1cd
<4> [604.892630]start_kernel+0x362/0x4e4
<4> [604.892631]secondary_startup_64+0xa4/0xb0
<4> [604.892631]
-> #2 (pmus_lock){+.+.}:
<4> [604.892633]__mutex_lock+0x9a/0x9c0
<4> [604.892633]perf_event_init_cpu+0x6b/0x140
<4> [604.892635]cpuhp_invoke_callback+0x9b/0x9d0
<4> [604.892636]_cpu_up+0xa2/0x140
<4> [604.892637]do_cpu_up+0x61/0xa0
<4> [604.892639]smp_init+0x57/0x96
<4> [604.892639]kernel_init_freeable+0x87/0x1dc
<4> [604.892640]kernel_init+0x5/0x100
<4> [604.892642]ret_from_fork+0x24/0x50
<4> [604.892642]
-> #1 (cpu_hotplug_lock.rw_sem){}:
<4> [604.892643]cpus_read_lock+0x34/0xd0
<4> [604.892644]rcu_barrier+0xaa/0x190
<4> [604.892645]kernel_init+0x21/0x100
<4> [604.892647]ret_from_fork+0x24/0x50
<4> [604.892647]
-> #0 (rcu_state.barrier_mutex){+.+.}:
<4> [604.892649]__lock_acquire+0x1328/0x15d0
<4> [604.892650]lock_acquire+0xa7/0x1c0
<4> [604.892651]__mutex_lock+0x9a/0x9c0
<4> [604.892652]rcu_barrier+0x23/0x190
<4> [604.892680]i915_gem_object_unbind+0x29d/0x3f0 [i915]
<4> [604.892707]i915_gem_object_pin_to_display_plane+0x141/0x270 [i915]
<4> [604.892737]intel_pin_and_fence_fb_obj+0xec/0x1f0 [i915]
<4> [604.892767]intel_plane_pin_fb+0x3f/0xd0 [i915]
<4> [604.892797]intel_prepare_plane_fb+0x13b/0x5c0 [i915]
<4> [604.892798]drm_atomic_helper_prepare_planes+0x85/0x110
<4> [604.892827]intel_atomic_commit+0xda/0x390 [i915]
<4> [604.892828]drm_atomic_helper_set_config+0x57/0xa0
<4> [604.892830]drm_mode_setcrtc+0x1c4/0x720
<4> [604.892830]drm_ioctl_kernel+0xb0/0xf0
<4> [604.892831]drm_ioctl+0x2e1/0x390
<4> [604.892833]ksys_ioctl+0x7b/0x90
<4> [604.892835]__x64_sys_ioctl+0x11/0x20
<4> [604.892835]do_syscall_64+0x4f/0x220
<4> [604.892836]entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4> [604.892837]
Changes since v1:
- Use (*values)[n++] in perf_read_one().
Signed-off-by: Maarten Lankhorst
---
kernel/events/core.c | 59 +++-
1 file changed, 31 insertions(+), 28 deletions(-)
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 085d9263d595..cf2e19f8130b 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -4926,20 +4926,20 @@ static int __perf_read_group_add(struct perf_event
*leader,
}
static int perf_read_group(struct perf_event *event,
- u64 read_format, char __user *buf)
+ u64 read_format, char __user *buf,
+ u64 **values)
{
struct perf_event
Re: [Intel-gfx] [PATCH i-g-t] i915/perf_pmu: Exercise mixing perf reads into i915 mmaps
Quoting Chris Wilson (2020-04-02 15:00:57)
> Feed a fresh i915 mmap into a read(perf_fd) to teach lockdep about the
> potential lock chains should we take a pagefault into our vm_fault
> handlers from within perf.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> tests/perf_pmu.c | 39 +++
> 1 file changed, 39 insertions(+)
>
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 259670f4b..1d6681d80 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -1827,6 +1827,35 @@ accuracy(int gem_fd, const struct
> intel_execution_engine2 *e,
> assert_within(100.0 * busy_r, 100.0 * expected, 2);
> }
>
> +static void *create_mmap(int gem_fd, const struct mmap_offset *t, int sz)
> +{
> + uint32_t handle;
> + void *ptr;
> +
> + handle = gem_create(gem_fd, sz);
> + ptr = __gem_mmap_offset(gem_fd, handle, 0, sz, PROT_WRITE, t->type);
> + gem_close(gem_fd, handle);
> +
> + return ptr;
> +}
> +
> +static void
> +faulting_read(int gem_fd, const struct mmap_offset *t)
> +{
> + void *ptr;
> + int fd;
> +
> + ptr = create_mmap(gem_fd, t, 4096);
> + igt_require(ptr != NULL);
> +
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(0, 0));
> + igt_require(fd != -1);
> + igt_assert_eq(read(fd, ptr, 4096), 2 * sizeof(uint64_t));
> + close(fd);
> +
> + munmap(ptr, 4096);
> +}
> +
> #define test_each_engine(T, i915, e) \
> igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
> igt_dynamic_f("%s", e->name)
> @@ -1860,6 +1889,16 @@ igt_main
> igt_subtest("invalid-init")
> invalid_init(fd);
>
> + igt_subtest_with_dynamic("faulting-read") {
> + for_each_mmap_offset_type(fd, t) {
> + if (!gem_has_mmap_offset_type(fd, t))
> + continue;
Redundant, for_each_mmap_offset_type() includes the skip.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/perf_pmu: Exercise mixing perf reads into i915 mmaps
Feed a fresh i915 mmap into a read(perf_fd) to teach lockdep about the
potential lock chains should we take a pagefault into our vm_fault
handlers from within perf.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 259670f4b..1d6681d80 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1827,6 +1827,35 @@ accuracy(int gem_fd, const struct
intel_execution_engine2 *e,
assert_within(100.0 * busy_r, 100.0 * expected, 2);
}
+static void *create_mmap(int gem_fd, const struct mmap_offset *t, int sz)
+{
+ uint32_t handle;
+ void *ptr;
+
+ handle = gem_create(gem_fd, sz);
+ ptr = __gem_mmap_offset(gem_fd, handle, 0, sz, PROT_WRITE, t->type);
+ gem_close(gem_fd, handle);
+
+ return ptr;
+}
+
+static void
+faulting_read(int gem_fd, const struct mmap_offset *t)
+{
+ void *ptr;
+ int fd;
+
+ ptr = create_mmap(gem_fd, t, 4096);
+ igt_require(ptr != NULL);
+
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(0, 0));
+ igt_require(fd != -1);
+ igt_assert_eq(read(fd, ptr, 4096), 2 * sizeof(uint64_t));
+ close(fd);
+
+ munmap(ptr, 4096);
+}
+
#define test_each_engine(T, i915, e) \
igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
igt_dynamic_f("%s", e->name)
@@ -1860,6 +1889,16 @@ igt_main
igt_subtest("invalid-init")
invalid_init(fd);
+ igt_subtest_with_dynamic("faulting-read") {
+ for_each_mmap_offset_type(fd, t) {
+ if (!gem_has_mmap_offset_type(fd, t))
+ continue;
+
+ igt_dynamic_f("%s", t->name)
+ faulting_read(fd, t);
+ }
+ }
+
/**
* Test that a single engine metric can be initialized or it
* is correctly rejected.
--
2.26.0
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Re: [Intel-gfx] [PATCH v2] drm/i915: Use per-engine request pools
On Thu, 2020-04-02 at 13:16 +0100, Chris Wilson wrote:
> Add a per-engine request mempool so that we should always have a couple
> of requests available for powermanagement allocations from tricky
> contexts. These reserves are expected to be only used for kernel
> contexts when barriers must be emitted [almost] without fail.
>
> When using the mempool, requests are first allocated from the global
> slab cache (utilising all the per-cpu lockless freelists and caches) and
> only if that is empty and cannot be filled under the gfp_t do we
> fallback to using the per-engine cache of recently freed requests. For
> our use cases, this will never be empty for long as there will always be
> at least the previous powermanagent request to reuse.
>
> The downside is that this is quite a bulky addition and abstraction to
> use, but it will ensure that we never fail to park the engine due to
> oom.
>
> v2: Only use the mempool for nonblocking allocations which are not
> expected to fail.
LGTM. Thanks for addressing the issue.
Reviewed-by: Janusz Krzysztofik
Thanks,
Janusz
>
> Signed-off-by: Chris Wilson
> Cc: Janusz Krzysztofik
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 ++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 4
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> drivers/gpu/drm/i915/i915_request.c | 20 +---
> drivers/gpu/drm/i915/i915_request.h | 2 ++
> 6 files changed, 39 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index b469de0dd9b6..c1159bd17989 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -324,6 +324,9 @@ void intel_engine_init_active(struct intel_engine_cs
> *engine,
> #define ENGINE_MOCK 1
> #define ENGINE_VIRTUAL 2
>
> +void intel_engine_init_request_pool(struct intel_engine_cs *engine);
> +void intel_engine_fini_request_pool(struct intel_engine_cs *engine);
> +
> static inline bool
> intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 843cb6f2f696..16bbd9174937 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -602,6 +602,18 @@ static int init_status_page(struct intel_engine_cs
> *engine)
> return ret;
> }
>
> +void intel_engine_init_request_pool(struct intel_engine_cs *engine)
> +{
> + mempool_init_slab_pool(>request_pool,
> +INTEL_ENGINE_REQUEST_POOL_RESERVED,
> +i915_request_slab_cache());
> +}
> +
> +void intel_engine_fini_request_pool(struct intel_engine_cs *engine)
> +{
> + mempool_exit(>request_pool);
> +}
> +
> static int engine_setup_common(struct intel_engine_cs *engine)
> {
> int err;
> @@ -617,6 +629,7 @@ static int engine_setup_common(struct intel_engine_cs
> *engine)
> intel_engine_init_execlists(engine);
> intel_engine_init_cmd_parser(engine);
> intel_engine_init__pm(engine);
> + intel_engine_init_request_pool(engine);
> intel_engine_init_retire(engine);
>
> intel_engine_pool_init(>pool);
> @@ -817,6 +830,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
> *engine)
> cleanup_status_page(engine);
>
> intel_engine_fini_retire(engine);
> + intel_engine_fini_request_pool(engine);
> intel_engine_pool_fini(>pool);
> intel_engine_fini_breadcrumbs(engine);
> intel_engine_cleanup_cmd_parser(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 80cdde712842..0db03215127b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -13,6 +13,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -308,6 +309,9 @@ struct intel_engine_cs {
> struct list_head hold; /* ready requests, but on hold */
> } active;
>
> + mempool_t request_pool; /* keep some in reserve for powermanagement */
> +#define INTEL_ENGINE_REQUEST_POOL_RESERVED 2
> +
> struct llist_head barrier_tasks;
>
> struct intel_context *kernel_context; /* pinned */
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 3479cda37fdc..afc9107e5d04 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -4892,6 +4892,8 @@ static void virtual_context_destroy(struct kref *kref)
> __execlists_context_fini(>context);
> intel_context_fini(>context);
>
> + intel_engine_fini_request_pool(>base);
> +
> kfree(ve->bonds);
>
Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Parametrize PFIT_PIPE
On Wed, Apr 01, 2020 at 03:48:26PM -0700, Manasi Navare wrote:
> On Wed, Feb 12, 2020 at 07:43:51PM +0200, Jani Nikula wrote:
> > On Wed, 12 Feb 2020, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Make the PFIT_PIPE stuff less ugly via parametrization.
> > >
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/display/intel_panel.c | 3 +--
> > > drivers/gpu/drm/i915/i915_reg.h| 1 +
> > > 2 files changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
> > > b/drivers/gpu/drm/i915/display/intel_panel.c
> > > index cba2f1c2557f..8b0730f4c442 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_panel.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> > > @@ -434,8 +434,7 @@ void intel_gmch_panel_fitting(struct intel_crtc
> > > *intel_crtc,
> > > /* 965+ wants fuzzy fitting */
> > > /* FIXME: handle multiple panels by failing gracefully */
> > > if (INTEL_GEN(dev_priv) >= 4)
> > > - pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
> > > - PFIT_FILTER_FUZZY);
> > > + pfit_control |= PFIT_PIPE(intel_crtc->pipe) | PFIT_FILTER_FUZZY;
> > >
> > > out:
> > > if ((pfit_control & PFIT_ENABLE) == 0) {
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index b09c1d6dc0aa..faf8945a51b0 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4928,6 +4928,7 @@ enum {
> > > #define PFIT_ENABLE(1 << 31)
> > > #define PFIT_PIPE_MASK (3 << 29)
> > > #define PFIT_PIPE_SHIFT29
> > > +#define PFIT_PIPE(pipe)((pipe) << 29)
> >
> > This is fine, but might have as well defined this in terms of
> > REG_FIELD_PREP. I especially like it for parametrized stuff because it
> > ensures we don't flood the value outside the field.
> >
> > Reviewed-by: Jani Nikula
>
> Was just reviewing this series and noticed that Jani had suggested using
> REG_FIELD_PREP stuff here, are you going to change that Ville?
IIRC I already pushed this.
>
> Looks good otherwise
>
> Manasi
> >
> > > #define VERT_INTERP_DISABLE(0 << 10)
> > > #define VERT_INTERP_BILINEAR (1 << 10)
> > > #define VERT_INTERP_MASK (3 << 10)
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions
On Wed, Apr 01, 2020 at 04:53:23PM -0700, Manasi Navare wrote:
> On Wed, Feb 12, 2020 at 06:17:34PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Most of the pfit functions are of the form:
> >
> > func()
> > {
> > if (pfit_enabled) {
> > ...
> > }
> > }
> >
> > Flip the pfit_enabled check around to flatten the functions.
> >
> > And while we're touching all this let's do the usual
> > s/pipe_config/crtc_state/ replacement.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 233 +--
> > 1 file changed, 115 insertions(+), 118 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index becc6322b7dc..796e27c4aece 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6233,42 +6233,42 @@ static void skl_pfit_enable(const struct
> > intel_crtc_state *crtc_state)
> > enum pipe pipe = crtc->pipe;
> > const struct intel_crtc_scaler_state *scaler_state =
> > _state->scaler_state;
> > + u16 uv_rgb_hphase, uv_rgb_vphase;
> > + int pfit_w, pfit_h, hscale, vscale;
> > + unsigned long irqflags;
> > + int id;
> >
> > - if (crtc_state->pch_pfit.enabled) {
> > - u16 uv_rgb_hphase, uv_rgb_vphase;
> > - int pfit_w, pfit_h, hscale, vscale;
> > - unsigned long irqflags;
> > - int id;
> > + if (!crtc_state->pch_pfit.enabled)
> > + return;
> >
> > - if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> > - return;
> > + if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> > + return;
> >
> > - pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
> > - pfit_h = crtc_state->pch_pfit.size & 0x;
> > + pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
> > + pfit_h = crtc_state->pch_pfit.size & 0x;
> >
> > - hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
> > - vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
> > + hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
> > + vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
> >
> > - uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
> > - uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> > + uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
> > + uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> >
> > - id = scaler_state->scaler_id;
> > + id = scaler_state->scaler_id;
> >
> > - spin_lock_irqsave(_priv->uncore.lock, irqflags);
> > + spin_lock_irqsave(_priv->uncore.lock, irqflags);
> >
> > - intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN
> > |
> > - PS_FILTER_MEDIUM |
> > scaler_state->scalers[id].mode);
> > - intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
> > - PS_Y_PHASE(0) |
> > PS_UV_RGB_PHASE(uv_rgb_vphase));
> > - intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> > - PS_Y_PHASE(0) |
> > PS_UV_RGB_PHASE(uv_rgb_hphase));
> > - intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> > - crtc_state->pch_pfit.pos);
> > - intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> > - crtc_state->pch_pfit.size);
> > + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
> > + PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
> > + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
> > + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
> > + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> > + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> > + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> > + crtc_state->pch_pfit.pos);
> > + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> > + crtc_state->pch_pfit.size);
> >
> > - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> > - }
> > + spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> > }
> >
> > static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> > @@ -6277,22 +6277,23 @@ static void ilk_pfit_enable(const struct
> > intel_crtc_state *crtc_state)
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > - if (crtc_state->pch_pfit.enabled) {
> > - /* Force use of hard-coded filter coefficients
> > -* as some pre-programmed values are broken,
> > -* e.g. x201.
> > -*/
> > - if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
> > - intel_de_write(dev_priv, PF_CTL(pipe),
> > -
Re: [Intel-gfx] kernel 5.6: baytrail hdmi audio not working
On Wed, Apr 01, 2020 at 06:53:17PM -0400, Giacomo Comes wrote:
> Hi,
> on my Intel Compute Stick STCK1 (baytrail hdmi audio)
> sound is not working with the kernel 5.6
>
> I have bisected the kernel and I found the commit that introduced the issue:
>
> commit 58d124ea2739e1440ddd743d46c470fe724aca9a
> Author: Maarten Lankhorst
> Date: Thu Oct 31 12:26:04 2019 +0100
>
> drm/i915: Complete crtc hw/uapi split, v6.
>
> Now that we separated everything into uapi and hw, it's
> time to make the split definitive. Remove the union and
> make a copy of the hw state on modeset and fastset.
>
> Color blobs are copied in crtc atomic_check(), right
> before color management is checked.
>
> If more information is required please let me know.
Should hopefully be fixed with
commit 2bdd4c28baff ("drm/i915/display: Fix mode private_flags
comparison at atomic_check")
Stable folks, please pick that up for 5.6.x stable releases.
--
Ville Syrjälä
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Re: [Intel-gfx] [PATCH v3 2/3] drm/i915: Add i915_lpsp_info debugfs
On 2020-04-01 at 21:23:28 +0530, Manna, Animesh wrote:
thanks animesh for review!
>
> On 31-03-2020 17:07, Anshuman Gupta wrote:
> >New i915_pm_lpsp igt solution approach relies on connector specific
> >debugfs attribute i915_lpsp_info, it exposes whether an output is
> >capable of driving lpsp and exposes lpsp enablement info.
> >
> >v2:
> >- CI fixup.
> >v3:
> >- register i915_lpsp_info only for supported connector. [Jani]
> >- use intel_display_power_well_is_enabled() instead of looking
> > inside power_well count. [Jani]
> >- fixes the lpsp capable conditional logic. [Jani]
> >- combined the lpsp capable and enable info. [Jani]
> >
> >Signed-off-by: Anshuman Gupta
> >---
> > .../drm/i915/display/intel_display_debugfs.c | 124 ++
> > .../drm/i915/display/intel_display_power.h| 2 +
> > 2 files changed, 126 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >index 424f4e52f783..b185c4617468 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >@@ -9,6 +9,7 @@
> > #include "i915_debugfs.h"
> > #include "intel_csr.h"
> > #include "intel_display_debugfs.h"
> >+#include "intel_display_power.h"
> > #include "intel_display_types.h"
> > #include "intel_dp.h"
> > #include "intel_fbc.h"
> >@@ -611,6 +612,98 @@ static void intel_hdcp_info(struct seq_file *m,
> > seq_puts(m, "\n");
> > }
> >+#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP capable\n") :
> >seq_puts(m, "LPSP incapable\n"))
> >+#define LPSP_ENABLE(COND) (COND ? seq_puts(m, "LPSP enabled\n") :
> >seq_puts(m, "LPSP disabled\n"))
> >+
> >+/* LVDS also an embedded panel but we are not interested in it */
> >+static bool intel_have_embedded_panel(struct drm_connector *connector)
> >+{
> >+return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> >+connector->connector_type == DRM_MODE_CONNECTOR_eDP;
> >+}
> >+
> >+static bool intel_have_gen9_lpsp_panel(struct drm_connector *connector)
> >+{
> >+return intel_have_embedded_panel(connector) ||
> >+connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort;
> >+}
> >+
> >+static bool intel_have_lpsp_supported_panel(struct drm_connector *connector)
> >+{
> >+return intel_have_gen9_lpsp_panel(connector) ||
> >+connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> >+connector->connector_type == DRM_MODE_CONNECTOR_HDMIB;
> >+}
>
> This function will pass for every platform for almost all (EDP/MIPI/DP/HDMI)
> connector type even if not supported ...rt?
Above function will only used to add i915_lpsp_info for DP/MIPI/DP/HDMI
connecotr,
It can nuke it with condition below condition.
return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB;
So in order to avoid such big condition i had prefred the above function,
please suggest a better readable way.
use condition as such, function name change or using a macro.
> Apart from that I did not understand the purpose of above functions.
My thought process was to break longer conditional if chunk in static function,
please suggest if u are in favour of nuke these functions, or if u want to
suggest
a better name.
> Can we have a single function to check the connector is supported lpsp or not.
>
> static bool is_lpsp_supported(struct drm_connector *connector)
>
> In function definition we can check for platform first, then check
> connector_type and return true/false.
i915_lpsp_info_show is first checking the gen and then platform, after checking
platform it needs to check DDI port and connector based upon platform lpsp
block diagram
in order to evaluate lpsp capablity, followed by power well check to evlauate
lpsp
enabled.
if i understand you are suggesting to break above two parts,
is_lpsp_supported()
is_lpsp_capable()
but by breaking above we would require to check gen and platfrom twice
which can be avoided by combining above.
please correct me if i am wrong.
Thanks ,
Anshuman Gupta.
>
> >+
> >+static bool
> >+intel_lpsp_power_well_enabled(struct drm_i915_private *dev_priv,
> >+ enum i915_power_well_id power_well_id)
> >+{
> >+intel_wakeref_t wakeref;
> >+bool is_enabled;
> >+
> >+wakeref = intel_runtime_pm_get(_priv->runtime_pm);
> >+is_enabled = intel_display_power_well_is_enabled(dev_priv,
> >+ power_well_id);
> >+intel_runtime_pm_put(_priv->runtime_pm, wakeref);
> >+
> >+return is_enabled;
> >+}
> >+
> >+static void
> >+intel_lpsp_gen12_helper(struct seq_file *m, struct drm_connector *connector)
> >+{
>
[Intel-gfx] [drm-tip:drm-tip 9/10] include/net/ax25.h:125:2: error: redefinition of enumerator 'AX25_PROTO_DAMA_MASTER'
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: cade363a69762c57ffb58f91b47670df7ca520bf
commit: f0b7c5c4d7beea0cd83b2f8659faf9fd406137e6 [9/10] Merge remote-tracking
branch 'drm-intel/topic/core-for-CI' into drm-tip
config: x86_64-allyesconfig (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project
e6a39f00e8d0cd3684df54fb03d288efe2969202)
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout f0b7c5c4d7beea0cd83b2f8659faf9fd406137e6
# save the attached .config to linux build tree
COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
In file included from net/ax25/ax25_addr.c:16:
>> include/net/ax25.h:125:2: error: redefinition of enumerator
>> 'AX25_PROTO_DAMA_MASTER'
AX25_PROTO_MAX = __AX25_PROTO_MAX -1
^
include/net/ax25.h:121:24: note: expanded from macro 'AX25_PROTO_MAX'
#define AX25_PROTO_MAX AX25_PROTO_DAMA_MASTER
^
include/net/ax25.h:120:2: note: previous definition is here
AX25_PROTO_DAMA_MASTER,
^
1 error generated.
vim +/AX25_PROTO_DAMA_MASTER +125 include/net/ax25.h
^1da177e4c3f41 Linus Torvalds 2005-04-16 113
^1da177e4c3f41 Linus Torvalds 2005-04-16 114 enum {
^1da177e4c3f41 Linus Torvalds 2005-04-16 115 AX25_PROTO_STD_SIMPLEX,
^1da177e4c3f41 Linus Torvalds 2005-04-16 116 AX25_PROTO_STD_DUPLEX,
c7c694d196a39a Ralf Baechle 2006-03-19 117 #ifdef CONFIG_AX25_DAMA_SLAVE
^1da177e4c3f41 Linus Torvalds 2005-04-16 118 AX25_PROTO_DAMA_SLAVE,
c7c694d196a39a Ralf Baechle 2006-03-19 119 #ifdef CONFIG_AX25_DAMA_MASTER
c7c694d196a39a Ralf Baechle 2006-03-19 120 AX25_PROTO_DAMA_MASTER,
c7c694d196a39a Ralf Baechle 2006-03-19 121 #define AX25_PROTO_MAX
AX25_PROTO_DAMA_MASTER
c7c694d196a39a Ralf Baechle 2006-03-19 122 #endif
c7c694d196a39a Ralf Baechle 2006-03-19 123 #endif
c7c694d196a39a Ralf Baechle 2006-03-19 124 __AX25_PROTO_MAX,
c7c694d196a39a Ralf Baechle 2006-03-19 @125 AX25_PROTO_MAX =
__AX25_PROTO_MAX -1
^1da177e4c3f41 Linus Torvalds 2005-04-16 126 };
^1da177e4c3f41 Linus Torvalds 2005-04-16 127
:: The code at line 125 was first introduced by commit
:: c7c694d196a39af6e644e24279953d04f30362db [AX.25]: Fix potencial memory
hole.
:: TO: Ralf Baechle DL5RB
:: CC: David S. Miller
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gem: Utilize rcu iteration of context engines
Now that we can peek at GEM->engines[] and obtain a reference to them
using RCU, do so for instances where we can safely iterate the
potentially old copy of the engines. For setting, we can do this when we
know the engine properties are copied over before swapping, so we know
the new engines already have the global property and we update the old
before they are discarded. For reading, we only need to be safe; as we
do so on behalf of the user, their races are their own problem.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 +++--
1 file changed, 31 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 50e7580f9337..2b6dd08de6f1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -757,21 +757,46 @@ __create_context(struct drm_i915_private *i915)
return ERR_PTR(err);
}
+static inline struct i915_gem_engines *
+__context_engines_await(const struct i915_gem_context *ctx)
+{
+ struct i915_gem_engines *engines;
+
+ rcu_read_lock();
+ do {
+ engines = rcu_dereference(ctx->engines);
+ GEM_BUG_ON(!engines);
+
+ if (unlikely(!i915_sw_fence_await(>fence)))
+ continue;
+
+ if (likely(engines == rcu_access_pointer(ctx->engines)))
+ break;
+
+ i915_sw_fence_complete(>fence);
+ } while (1);
+ rcu_read_unlock();
+
+ return engines;
+}
+
static int
context_apply_all(struct i915_gem_context *ctx,
int (*fn)(struct intel_context *ce, void *data),
void *data)
{
struct i915_gem_engines_iter it;
+ struct i915_gem_engines *e;
struct intel_context *ce;
int err = 0;
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ e = __context_engines_await(ctx);
+ for_each_gem_engine(ce, e, it) {
err = fn(ce, data);
if (err)
break;
}
- i915_gem_context_unlock_engines(ctx);
+ i915_sw_fence_complete(>fence);
return err;
}
@@ -786,11 +811,13 @@ static int __apply_ppgtt(struct intel_context *ce, void
*vm)
static struct i915_address_space *
__set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm)
{
- struct i915_address_space *old = i915_gem_context_vm(ctx);
+ struct i915_address_space *old;
+ old = rcu_replace_pointer(ctx->vm,
+ i915_vm_open(vm),
+ lockdep_is_held(>mutex));
GEM_BUG_ON(old && i915_vm_is_4lvl(vm) != i915_vm_is_4lvl(old));
- rcu_assign_pointer(ctx->vm, i915_vm_open(vm));
context_apply_all(ctx, __apply_ppgtt, vm);
return old;
@@ -1069,30 +1096,6 @@ static void cb_retire(struct i915_active *base)
kfree(cb);
}
-static inline struct i915_gem_engines *
-__context_engines_await(const struct i915_gem_context *ctx)
-{
- struct i915_gem_engines *engines;
-
- rcu_read_lock();
- do {
- engines = rcu_dereference(ctx->engines);
- if (unlikely(!engines))
- break;
-
- if (unlikely(!i915_sw_fence_await(>fence)))
- continue;
-
- if (likely(engines == rcu_access_pointer(ctx->engines)))
- break;
-
- i915_sw_fence_complete(>fence);
- } while (1);
- rcu_read_unlock();
-
- return engines;
-}
-
I915_SELFTEST_DECLARE(static intel_engine_mask_t context_barrier_inject_fault);
static int context_barrier_task(struct i915_gem_context *ctx,
intel_engine_mask_t engines,
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/17] drm/i915/audio: use struct drm_device based logging
== Series Details == Series: series starting with [01/17] drm/i915/audio: use struct drm_device based logging URL : https://patchwork.freedesktop.org/series/75414/ State : success == Summary == CI Bug Log - changes from CI_DRM_8237 -> Patchwork_17179 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17179/index.html Known issues Here are the changes found in Patchwork_17179 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([i915#656]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8237/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17179/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html Possible fixes * igt@i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][3] ([i915#289]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8237/fi-icl-u2/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17179/fi-icl-u2/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][5] ([i915#62]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8237/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17179/fi-kbl-x1275/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-n3050: [INCOMPLETE][7] ([i915#1382]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8237/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17179/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html * igt@i915_selftest@live@requests: - fi-icl-u2: [INCOMPLETE][9] ([i915#1505] / [i915#1581]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8237/fi-icl-u2/igt@i915_selftest@l...@requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17179/fi-icl-u2/igt@i915_selftest@l...@requests.html * igt@kms_force_connector_basic@force-connector-state: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12] +9 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8237/fi-kbl-x1275/igt@kms_force_connector_ba...@force-connector-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17179/fi-kbl-x1275/igt@kms_force_connector_ba...@force-connector-state.html * igt@kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [PASS][14] +21 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8237/fi-kbl-x1275/igt@kms_force_connector_ba...@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17179/fi-kbl-x1275/igt@kms_force_connector_ba...@force-edid.html [i915#1382]: https://gitlab.freedesktop.org/drm/intel/issues/1382 [i915#1505]: https://gitlab.freedesktop.org/drm/intel/issues/1505 [i915#1581]: https://gitlab.freedesktop.org/drm/intel/issues/1581 [i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (42 -> 45) -- Additional (6): fi-skl-guc fi-snb-2520m fi-kbl-7500u fi-ivb-3770 fi-skl-6600u fi-snb-2600 Missing(3): fi-byt-squawks fi-bsw-cyan fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8237 -> Patchwork_17179 CI-20190529: 20190529 CI_DRM_8237: a9a502feaca70cf6ae0259977095244a0a33c138 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5558: 3b55a816300d80bc5e0b995cd41ee8c8649a1ea2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17179: a2696b2a35a3236787b5ad5eda97670bad71a7de @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a2696b2a35a3 drm/i915/uc: prefer struct drm_device based logging 8488b70421b5 drm/i915/gt: prefer struct drm_device based logging e8205d33d8cb drm/i915/stolen: prefer struct drm_device based logging 4177202ed569 drm/i915/uncore: prefer struct drm_device based logging a6b82b4321ac drm/i915/dram: prefer struct drm_device based logging 75a3dc9d0164 drm/i915/pmu: prefer struct drm_device based logging b6bdc53eb65d drm/i915/error: prefer struct drm_device based logging 16ebe7bc1db8 drm/i915/uc: prefer struct drm_device based logging d94202a534f7 drm/i915/switcheroo: use struct drm_device based logging
[Intel-gfx] [PATCH v2] drm/i915: Use per-engine request pools
Add a per-engine request mempool so that we should always have a couple
of requests available for powermanagement allocations from tricky
contexts. These reserves are expected to be only used for kernel
contexts when barriers must be emitted [almost] without fail.
When using the mempool, requests are first allocated from the global
slab cache (utilising all the per-cpu lockless freelists and caches) and
only if that is empty and cannot be filled under the gfp_t do we
fallback to using the per-engine cache of recently freed requests. For
our use cases, this will never be empty for long as there will always be
at least the previous powermanagent request to reuse.
The downside is that this is quite a bulky addition and abstraction to
use, but it will ensure that we never fail to park the engine due to
oom.
v2: Only use the mempool for nonblocking allocations which are not
expected to fail.
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 +++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
drivers/gpu/drm/i915/i915_request.c | 20 +---
drivers/gpu/drm/i915/i915_request.h | 2 ++
6 files changed, 39 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b469de0dd9b6..c1159bd17989 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -324,6 +324,9 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+void intel_engine_init_request_pool(struct intel_engine_cs *engine);
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine);
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 843cb6f2f696..16bbd9174937 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -602,6 +602,18 @@ static int init_status_page(struct intel_engine_cs *engine)
return ret;
}
+void intel_engine_init_request_pool(struct intel_engine_cs *engine)
+{
+ mempool_init_slab_pool(>request_pool,
+ INTEL_ENGINE_REQUEST_POOL_RESERVED,
+ i915_request_slab_cache());
+}
+
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine)
+{
+ mempool_exit(>request_pool);
+}
+
static int engine_setup_common(struct intel_engine_cs *engine)
{
int err;
@@ -617,6 +629,7 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
intel_engine_init_execlists(engine);
intel_engine_init_cmd_parser(engine);
intel_engine_init__pm(engine);
+ intel_engine_init_request_pool(engine);
intel_engine_init_retire(engine);
intel_engine_pool_init(>pool);
@@ -817,6 +830,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
cleanup_status_page(engine);
intel_engine_fini_retire(engine);
+ intel_engine_fini_request_pool(engine);
intel_engine_pool_fini(>pool);
intel_engine_fini_breadcrumbs(engine);
intel_engine_cleanup_cmd_parser(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..0db03215127b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -308,6 +309,9 @@ struct intel_engine_cs {
struct list_head hold; /* ready requests, but on hold */
} active;
+ mempool_t request_pool; /* keep some in reserve for powermanagement */
+#define INTEL_ENGINE_REQUEST_POOL_RESERVED 2
+
struct llist_head barrier_tasks;
struct intel_context *kernel_context; /* pinned */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3479cda37fdc..afc9107e5d04 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4892,6 +4892,8 @@ static void virtual_context_destroy(struct kref *kref)
__execlists_context_fini(>context);
intel_context_fini(>context);
+ intel_engine_fini_request_pool(>base);
+
kfree(ve->bonds);
kfree(ve);
}
@@ -5203,6 +5205,7 @@ intel_execlists_create_virtual(struct intel_engine_cs
**siblings,
intel_engine_init_active(>base, ENGINE_VIRTUAL);
intel_engine_init_breadcrumbs(>base);
intel_engine_init_execlists(>base);
+ intel_engine_init_request_pool(>base);
ve->base.cops = _context_ops;
Re: [Intel-gfx] [PATCH] drm/i915: Use per-engine request pools
Quoting Chris Wilson (2020-04-02 12:59:08) > Add a per-engine request mempool so that we should always have a couple > of requests available for powermanagement allocations from tricky > contexts. These reserves are expected to be only used for kernel > contexts when barriers must be emitted [almost] without fail. > > When using the mempool, requests are first allocated from the global > slab cache (utilising all the per-cpu lockless freelists and caches) and > only if that is empty and cannot be filled under the gfp_t do we > fallback to using the per-engine cache of recently freed requests. For > our use cases, this will never be empty for long as there will always be > at least the previous powermanagent request to reuse. > > The downside is that this is quite a bulky addition and abstraction to > use, but it will ensure that we never fail to park the engine due to > oom. Strictly speaking, mempool_alloc() does not have the semantics I ascribe it. Which is annoying. mempool_alloc() will always dip into the reserves if a NORETRY alloc fails, and so we should ourselves reserve dipping into the mempool if we can. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Use per-engine request pools
Add a per-engine request mempool so that we should always have a couple
of requests available for powermanagement allocations from tricky
contexts. These reserves are expected to be only used for kernel
contexts when barriers must be emitted [almost] without fail.
When using the mempool, requests are first allocated from the global
slab cache (utilising all the per-cpu lockless freelists and caches) and
only if that is empty and cannot be filled under the gfp_t do we
fallback to using the per-engine cache of recently freed requests. For
our use cases, this will never be empty for long as there will always be
at least the previous powermanagent request to reuse.
The downside is that this is quite a bulky addition and abstraction to
use, but it will ensure that we never fail to park the engine due to
oom.
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 +++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
drivers/gpu/drm/i915/i915_request.c | 22
drivers/gpu/drm/i915/i915_request.h | 2 ++
6 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b469de0dd9b6..c1159bd17989 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -324,6 +324,9 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+void intel_engine_init_request_pool(struct intel_engine_cs *engine);
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine);
+
static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 843cb6f2f696..6a5bb6e7b126 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -602,6 +602,18 @@ static int init_status_page(struct intel_engine_cs *engine)
return ret;
}
+void intel_engine_init_request_pool(struct intel_engine_cs *engine)
+{
+ mempool_init_slab_pool(>request_pool,
+ INTEL_ENGINE_REQUEST_POOL_RESERVED,
+ i915_request_slab_cache());
+}
+
+void intel_engine_fini_request_pool(struct intel_engine_cs *engine)
+{
+ mempool_exit(>request_pool);
+}
+
static int engine_setup_common(struct intel_engine_cs *engine)
{
int err;
@@ -618,6 +630,7 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
intel_engine_init_cmd_parser(engine);
intel_engine_init__pm(engine);
intel_engine_init_retire(engine);
+ intel_engine_init_request_pool(engine);
intel_engine_pool_init(>pool);
@@ -816,6 +829,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
cleanup_status_page(engine);
+ intel_engine_fini_request_pool(engine);
intel_engine_fini_retire(engine);
intel_engine_pool_fini(>pool);
intel_engine_fini_breadcrumbs(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..0db03215127b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -308,6 +309,9 @@ struct intel_engine_cs {
struct list_head hold; /* ready requests, but on hold */
} active;
+ mempool_t request_pool; /* keep some in reserve for powermanagement */
+#define INTEL_ENGINE_REQUEST_POOL_RESERVED 2
+
struct llist_head barrier_tasks;
struct intel_context *kernel_context; /* pinned */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3479cda37fdc..afc9107e5d04 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4892,6 +4892,8 @@ static void virtual_context_destroy(struct kref *kref)
__execlists_context_fini(>context);
intel_context_fini(>context);
+ intel_engine_fini_request_pool(>base);
+
kfree(ve->bonds);
kfree(ve);
}
@@ -5203,6 +5205,7 @@ intel_execlists_create_virtual(struct intel_engine_cs
**siblings,
intel_engine_init_active(>base, ENGINE_VIRTUAL);
intel_engine_init_breadcrumbs(>base);
intel_engine_init_execlists(>base);
+ intel_engine_init_request_pool(>base);
ve->base.cops = _context_ops;
ve->base.request_alloc = execlists_request_alloc;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 3388c5b610c5..a912ce8b9437 100644
---
[Intel-gfx] [PATCH 15/17] drm/i915/stolen: prefer struct drm_device based logging
Prefer struct drm_device based logging over struct device based logging.
No functional changes.
Cc: Wambui Karuga
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 5557dfa83a7b..dc250278bd2c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -381,14 +381,14 @@ static int i915_gem_init_stolen(struct drm_i915_private
*i915)
mutex_init(>mm.stolen_lock);
if (intel_vgpu_active(i915)) {
- dev_notice(i915->drm.dev,
+ drm_notice(>drm,
"%s, disabling use of stolen memory\n",
"iGVT-g active");
return 0;
}
if (intel_vtd_active() && INTEL_GEN(i915) < 8) {
- dev_notice(i915->drm.dev,
+ drm_notice(>drm,
"%s, disabling use of stolen memory\n",
"DMAR active");
return 0;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/17] drm/i915/uc: prefer struct drm_device based logging
Prefer struct drm_device based logging over struct device based logging.
No functional changes.
Cc: Wambui Karuga
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 14 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 18 +-
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 4681cdd24da4..f518fe05c6f9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -63,25 +63,25 @@ static void __confirm_options(struct intel_uc *uc)
}
if (!intel_uc_supports_guc(uc))
- dev_info(i915->drm.dev,
+ drm_info(>drm,
"Incompatible option enable_guc=%d - %s\n",
i915_modparams.enable_guc, "GuC is not supported!");
if (i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC &&
!intel_uc_supports_huc(uc))
- dev_info(i915->drm.dev,
+ drm_info(>drm,
"Incompatible option enable_guc=%d - %s\n",
i915_modparams.enable_guc, "HuC is not supported!");
if (i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION &&
!intel_uc_supports_guc_submission(uc))
- dev_info(i915->drm.dev,
+ drm_info(>drm,
"Incompatible option enable_guc=%d - %s\n",
i915_modparams.enable_guc, "GuC submission is N/A");
if (i915_modparams.enable_guc & ~(ENABLE_GUC_SUBMISSION |
ENABLE_GUC_LOAD_HUC))
- dev_info(i915->drm.dev,
+ drm_info(>drm,
"Incompatible option enable_guc=%d - %s\n",
i915_modparams.enable_guc, "undocumented flag");
}
@@ -480,14 +480,14 @@ static int __uc_init_hw(struct intel_uc *uc)
if (intel_uc_uses_guc_submission(uc))
intel_guc_submission_enable(guc);
- dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n",
+ drm_info(>drm, "%s firmware %s version %u.%u %s:%s\n",
intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path,
guc->fw.major_ver_found, guc->fw.minor_ver_found,
"submission",
enableddisabled(intel_uc_uses_guc_submission(uc)));
if (intel_uc_uses_huc(uc)) {
- dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n",
+ drm_info(>drm, "%s firmware %s version %u.%u %s:%s\n",
intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
huc->fw.path,
huc->fw.major_ver_found, huc->fw.minor_ver_found,
@@ -508,7 +508,7 @@ static int __uc_init_hw(struct intel_uc *uc)
__uc_sanitize(uc);
if (!ret) {
- dev_notice(i915->drm.dev, "GuC is uninitialized\n");
+ drm_notice(>drm, "GuC is uninitialized\n");
/* We want to run without GuC submission */
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 129db476f69e..572e34f28f0e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -299,7 +299,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
/* Check the size of the blob before examining buffer contents */
if (unlikely(fw->size < sizeof(struct uc_css_header))) {
- dev_warn(dev, "%s firmware %s: invalid size: %zu < %zu\n",
+ drm_warn(>drm, "%s firmware %s: invalid size: %zu <
%zu\n",
intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
fw->size, sizeof(struct uc_css_header));
err = -ENODATA;
@@ -312,7 +312,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw -
css->exponent_size_dw) * sizeof(u32);
if (unlikely(size != sizeof(struct uc_css_header))) {
- dev_warn(dev,
+ drm_warn(>drm,
"%s firmware %s: unexpected header size: %zu != %zu\n",
intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
fw->size, sizeof(struct uc_css_header));
@@ -325,7 +325,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
/* now RSA */
if (unlikely(css->key_size_dw != UOS_RSA_SCRATCH_COUNT)) {
- dev_warn(dev, "%s firmware %s: unexpected key size: %u != %u\n",
+ drm_warn(>drm, "%s firmware %s: unexpected key size: %u
!= %u\n",
intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
css->key_size_dw, UOS_RSA_SCRATCH_COUNT);
err = -EPROTO;
@@ -336,7 +336,7 @@ int
[Intel-gfx] [PATCH 16/17] drm/i915/gt: prefer struct drm_device based logging
Prefer struct drm_device based logging over struct device based logging.
No functional changes.
Cc: Wambui Karuga
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_rc6.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_reset.c | 14 +++---
5 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index ae07bcd7c226..eebd1190506f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1080,7 +1080,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.vma_ops.clear_pages = clear_pages;
if (unlikely(ggtt->do_idle_maps))
- dev_notice(i915->drm.dev,
+ drm_notice(>drm,
"Applying Ironlake quirks for intel_iommu\n");
return 0;
@@ -1145,7 +1145,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
return ret;
if (intel_vtd_active())
- dev_info(i915->drm.dev, "VT-d active for gfx access\n");
+ drm_info(>drm, "VT-d active for gfx access\n");
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 2e40400d1ecd..3e8a56c7d818 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -204,7 +204,7 @@ int intel_gt_resume(struct intel_gt *gt)
/* Only when the HW is re-initialised, can we replay the requests */
err = intel_gt_init_hw(gt);
if (err) {
- dev_err(gt->i915->drm.dev,
+ drm_err(>i915->drm,
"Failed to initialize GPU, declaring it wedged!\n");
goto err_wedged;
}
@@ -220,7 +220,7 @@ int intel_gt_resume(struct intel_gt *gt)
intel_engine_pm_put(engine);
if (err) {
- dev_err(gt->i915->drm.dev,
+ drm_err(>i915->drm,
"Failed to restart %s (%d)\n",
engine->name, err);
goto err_wedged;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3479cda37fdc..21164bc691c7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3062,7 +3062,7 @@ check_redzone(const void *vaddr, const struct
intel_engine_cs *engine)
vaddr += engine->context_size;
if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE))
- dev_err_once(engine->i915->drm.dev,
+ drm_err_once(>i915->drm,
"%s context redzone overwritten!\n",
engine->name);
}
@@ -3558,7 +3558,7 @@ static void enable_error_interrupt(struct intel_engine_cs
*engine)
status = ENGINE_READ(engine, RING_ESR);
if (unlikely(status)) {
- dev_err(engine->i915->drm.dev,
+ drm_err(>i915->drm,
"engine '%s' resumed still in error: %08x\n",
engine->name, status);
__intel_gt_reset(engine->gt, engine->mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 09d3e5a45397..1c1923ec8be7 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -468,7 +468,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
return false;
if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) {
- dev_notice(i915->drm.dev,
+ drm_notice(>drm,
"RC6 and powersaving disabled by BIOS\n");
return false;
}
@@ -500,7 +500,7 @@ static bool pctx_corrupted(struct intel_rc6 *rc6)
if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO))
return false;
- dev_notice(i915->drm.dev,
+ drm_notice(>drm,
"RC6 context corruption, disabling runtime power
management\n");
return true;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 003f26b42998..39070b514e65 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -109,7 +109,7 @@ static bool mark_guilty(struct i915_request *rq)
goto out;
}
- dev_notice(ctx->i915->drm.dev,
+ drm_notice(>i915->drm,
"%s context reset due to GPU hang\n",
ctx->name);
@@ -1031,7 +1031,7 @@ void intel_gt_reset(struct intel_gt *gt,
goto unlock;
if (reason)
- dev_notice(gt->i915->drm.dev,
+ drm_notice(>i915->drm,
"Resetting chip for
[Intel-gfx] [PATCH 13/17] drm/i915/dram: prefer struct drm_device based logging
Prefer struct drm_device based logging over struct device based logging. No functional changes. Cc: Wambui Karuga Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dram.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 6b922efb1d7c..8aa12cad93ce 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -495,6 +495,5 @@ void intel_dram_edram_detect(struct drm_i915_private *i915) else i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap); - dev_info(i915->drm.dev, -"Found %uMB of eDRAM\n", i915->edram_size_mb); + drm_info(>drm, "Found %uMB of eDRAM\n", i915->edram_size_mb); } -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/17] drm/i915/pmu: prefer struct drm_device based logging
Prefer struct drm_device based logging over struct device based logging.
No functional changes.
Cc: Wambui Karuga
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_pmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 2c062534eac1..230e9256ab30 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1115,7 +1115,7 @@ void i915_pmu_register(struct drm_i915_private *i915)
int ret = -ENOMEM;
if (INTEL_GEN(i915) <= 2) {
- dev_info(i915->drm.dev, "PMU not supported for this GPU.");
+ drm_info(>drm, "PMU not supported for this GPU.");
return;
}
@@ -1178,7 +1178,7 @@ void i915_pmu_register(struct drm_i915_private *i915)
if (!is_igp(i915))
kfree(pmu->name);
err:
- dev_notice(i915->drm.dev, "Failed to register PMU!\n");
+ drm_notice(>drm, "Failed to register PMU!\n");
}
void i915_pmu_unregister(struct drm_i915_private *i915)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/17] drm/i915/uncore: prefer struct drm_device based logging
Prefer struct drm_device based logging over struct device based logging. No functional changes. Cc: Wambui Karuga Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 013312e9b55c..fa86b7ab2d99 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -665,7 +665,7 @@ void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) mmio_debug_resume(uncore->debug); if (check_for_unclaimed_mmio(uncore)) - dev_info(uncore->i915->drm.dev, + drm_info(>i915->drm, "Invalid mmio detected during user access\n"); spin_unlock(>debug->lock); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/17] drm/i915/state: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Cc: Wambui Karuga
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_global_state.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c
b/drivers/gpu/drm/i915/display/intel_global_state.c
index a0cc894c3868..6f72feb14f3e 100644
--- a/drivers/gpu/drm/i915/display/intel_global_state.c
+++ b/drivers/gpu/drm/i915/display/intel_global_state.c
@@ -71,6 +71,7 @@ struct intel_global_state *
intel_atomic_get_global_obj_state(struct intel_atomic_state *state,
struct intel_global_obj *obj)
{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
int index, num_objs, i;
size_t size;
struct __intel_global_objs_state *arr;
@@ -106,8 +107,8 @@ intel_atomic_get_global_obj_state(struct intel_atomic_state
*state,
state->num_global_objs = num_objs;
- DRM_DEBUG_ATOMIC("Added new global object %p state %p to %p\n",
-obj, obj_state, state);
+ drm_dbg_atomic(>drm, "Added new global object %p state %p to
%p\n",
+ obj, obj_state, state);
return obj_state;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/17] drm/i915/error: prefer struct drm_device based logging
Prefer struct drm_device based logging over struct device based logging. No functional changes. Cc: Wambui Karuga Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 2a4cd0ba5464..424ad975a360 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1858,7 +1858,7 @@ void i915_error_state_store(struct i915_gpu_coredump *error) return; i915 = error->i915; - dev_info(i915->drm.dev, "%s\n", error_msg(error)); + drm_info(>drm, "%s\n", error_msg(error)); if (error->simulated || cmpxchg(>gpu_error.first_error, NULL, error)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/17] drm/i915/uc: prefer struct drm_device based logging
Prefer struct drm_device based logging over struct device based logging.
No functional changes.
Cc: Wambui Karuga
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 12 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 10 +-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index b11e564ef22e..4681cdd24da4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -45,12 +45,12 @@ static void __confirm_options(struct intel_uc *uc)
{
struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
- DRM_DEV_DEBUG_DRIVER(i915->drm.dev,
-"enable_guc=%d (guc:%s submission:%s huc:%s)\n",
-i915_modparams.enable_guc,
-yesno(intel_uc_wants_guc(uc)),
-yesno(intel_uc_wants_guc_submission(uc)),
-yesno(intel_uc_wants_huc(uc)));
+ drm_dbg(>drm,
+ "enable_guc=%d (guc:%s submission:%s huc:%s)\n",
+ i915_modparams.enable_guc,
+ yesno(intel_uc_wants_guc(uc)),
+ yesno(intel_uc_wants_guc_submission(uc)),
+ yesno(intel_uc_wants_huc(uc)));
if (i915_modparams.enable_guc == -1)
return;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index fa893dd1823c..129db476f69e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -32,11 +32,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
enum intel_uc_fw_status status)
{
uc_fw->__status = status;
- DRM_DEV_DEBUG_DRIVER(__uc_fw_to_gt(uc_fw)->i915->drm.dev,
-"%s firmware -> %s\n",
-intel_uc_fw_type_repr(uc_fw->type),
-status == INTEL_UC_FIRMWARE_SELECTED ?
-uc_fw->path : intel_uc_fw_status_repr(status));
+ drm_dbg(&__uc_fw_to_gt(uc_fw)->i915->drm,
+ "%s firmware -> %s\n",
+ intel_uc_fw_type_repr(uc_fw->type),
+ status == INTEL_UC_FIRMWARE_SELECTED ?
+ uc_fw->path : intel_uc_fw_status_repr(status));
}
#endif
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/17] drm/i915/switcheroo: use struct drm_device based logging
Convert all the pr_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Cc: Wambui Karuga
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_switcheroo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_switcheroo.c
b/drivers/gpu/drm/i915/i915_switcheroo.c
index ed69b5d4a375..b3a24eac21f1 100644
--- a/drivers/gpu/drm/i915/i915_switcheroo.c
+++ b/drivers/gpu/drm/i915/i915_switcheroo.c
@@ -20,14 +20,14 @@ static void i915_switcheroo_set_state(struct pci_dev *pdev,
}
if (state == VGA_SWITCHEROO_ON) {
- pr_info("switched on\n");
+ drm_info(>drm, "switched on\n");
i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
/* i915 resume handler doesn't set to D0 */
pci_set_power_state(pdev, PCI_D0);
i915_resume_switcheroo(i915);
i915->drm.switch_power_state = DRM_SWITCH_POWER_ON;
} else {
- pr_info("switched off\n");
+ drm_info(>drm, "switched off\n");
i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING;
i915_suspend_switcheroo(i915, pmm);
i915->drm.switch_power_state = DRM_SWITCH_POWER_OFF;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/17] drm/i915/crt: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Cc: Wambui Karuga
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 78f9b6cde810..e80debe44d71 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -594,7 +594,8 @@ static struct edid *intel_crt_get_edid(struct drm_connector
*connector,
edid = drm_get_edid(connector, i2c);
if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
- DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO
bit-banging\n");
+ drm_dbg_kms(connector->dev,
+ "CRT GMBUS EDID read failed, retry using GPIO
bit-banging\n");
intel_gmbus_force_bit(i2c, true);
edid = drm_get_edid(connector, i2c);
intel_gmbus_force_bit(i2c, false);
--
2.20.1
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