Re: [Intel-gfx] [PATCH 2/2] drm/i915: remove gvt/Makefile
On 2020.04.10 00:58:16 +0300, Jani Nikula wrote: > On Fri, 10 Apr 2020, Masahiro Yamada wrote: > > Including subdirectory Makefile from the driver main Makefile does not > > buy us much because this is not real isolation. > > The isolation it does buy us is that gvt/ subdirectory is developed and > maintained on a separate mailing list and separate git repo. I think at > some point there were plans to make it an actual module too. > > So while you could quip about Conway's law here, I think it might be > better to keep this as it is. > > Zhenyu, Zhi, what do you think? Yeah, I have the same feeling, maybe we can add some comment in gvt Makefile to state that point. Thanks > > > > Having a single Makefile at the top of the module is clearer, and > > it is what this driver almost does. > > > > Move all gvt objects to the i915 main Makefile. > > > > Signed-off-by: Masahiro Yamada > > --- > > > > drivers/gpu/drm/i915/Makefile | 28 > > drivers/gpu/drm/i915/gvt/Makefile | 8 > > 2 files changed, 24 insertions(+), 12 deletions(-) > > delete mode 100644 drivers/gpu/drm/i915/gvt/Makefile > > > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > > index 6cd1f6253814..74e965882a98 100644 > > --- a/drivers/gpu/drm/i915/Makefile > > +++ b/drivers/gpu/drm/i915/Makefile > > @@ -275,10 +275,30 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \ > > # virtual gpu code > > i915-y += i915_vgpu.o > > > > -ifeq ($(CONFIG_DRM_I915_GVT),y) > > -i915-y += intel_gvt.o > > -include $(src)/gvt/Makefile > > -endif > > +i915-$(CONFIG_DRM_I915_GVT) += \ > > + intel_gvt.o \ > > + gvt/gvt.o \ > > + gvt/aperture_gm.o \ > > + gvt/handlers.o \ > > + gvt/vgpu.o \ > > + gvt/trace_points.o \ > > + gvt/firmware.o \ > > + gvt/interrupt.o \ > > + gvt/gtt.o \ > > + gvt/cfg_space.o \ > > + gvt/opregion.o \ > > + gvt/mmio.o \ > > + gvt/display.o \ > > + gvt/edid.o \ > > + gvt/execlist.o \ > > + gvt/scheduler.o \ > > + gvt/sched_policy.o \ > > + gvt/mmio_context.o \ > > + gvt/cmd_parser.o \ > > + gvt/debugfs.o \ > > + gvt/fb_decoder.o \ > > + gvt/dmabuf.o \ > > + gvt/page_track.o > > > > obj-$(CONFIG_DRM_I915) += i915.o > > obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o > > diff --git a/drivers/gpu/drm/i915/gvt/Makefile > > b/drivers/gpu/drm/i915/gvt/Makefile > > deleted file mode 100644 > > index 4d70f4689479.. > > --- a/drivers/gpu/drm/i915/gvt/Makefile > > +++ /dev/null > > @@ -1,8 +0,0 @@ > > -# SPDX-License-Identifier: GPL-2.0 > > -GVT_DIR := gvt > > -GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o > > firmware.o \ > > - interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \ > > - execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o > > debugfs.o \ > > - fb_decoder.o dmabuf.o page_track.o > > - > > -i915-y += $(addprefix $(GVT_DIR)/, > > $(GVT_SOURCE)) > > -- > Jani Nikula, Intel Open Source Graphics Center -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for i915 lpsp support for lpsp igt (rev7)
== Series Details == Series: i915 lpsp support for lpsp igt (rev7) URL : https://patchwork.freedesktop.org/series/74648/ State : success == Summary == CI Bug Log - changes from CI_DRM_8281_full -> Patchwork_17264_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_17264_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17264_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17264_full: ### IGT changes ### Warnings * igt@i915_pm_lpsp@screens-disabled: - shard-snb: [SKIP][1] ([fdo#109271]) -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-snb4/igt@i915_pm_l...@screens-disabled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/shard-snb4/igt@i915_pm_l...@screens-disabled.html New tests - New tests have been introduced between CI_DRM_8281_full and Patchwork_17264_full: ### New IGT tests (7) ### * igt@gem_exec_store@pages: - Statuses : - Exec time: [None] s * igt@i915_pm_lpsp@kms-lpsp: - Statuses : - Exec time: [None] s * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp-1: - Statuses : 2 skip(s) - Exec time: [0.0] s * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-edp-1: - Statuses : 3 pass(s) - Exec time: [0.10, 0.45] s * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a-1: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a-2: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga-1: - Statuses : 1 skip(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_17264_full that come from known issues: ### IGT changes ### Issues hit * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#716]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-glk8/igt@gen9_exec_pa...@allowed-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/shard-glk5/igt@gen9_exec_pa...@allowed-all.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-snb: [PASS][5] -> [FAIL][6] ([i915#1066]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-snb6/igt@i915_pm_rc6_reside...@rc6-idle.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/shard-snb2/igt@i915_pm_rc6_reside...@rc6-idle.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-offscreen: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#54] / [i915#93] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-kbl7/igt@kms_cursor_...@pipe-a-cursor-64x64-offscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-64x64-offscreen.html - shard-apl: [PASS][9] -> [FAIL][10] ([i915#54] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-64x64-offscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-64x64-offscreen.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109349]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/shard-iclb5/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-glk9/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/shard-glk3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#34]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl2/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/shard-skl2/igt@kms_f...@plain-flip-fb-recreate-interruptible.html * igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible: - shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([i915#1297]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-kbl4/igt@kms_f...@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/shard-kbl7/igt@kms_f...@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/23] perf/core: Only copy-to-user after completely unlocking all locks, v3.
== Series Details == Series: series starting with [01/23] perf/core: Only copy-to-user after completely unlocking all locks, v3. URL : https://patchwork.freedesktop.org/series/75668/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8275_full -> Patchwork_17253_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17253_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17253_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17253_full: ### IGT changes ### Possible regressions * igt@gem_close@many-handles-one-vma: - shard-tglb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8275/shard-tglb6/igt@gem_cl...@many-handles-one-vma.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-tglb5/igt@gem_cl...@many-handles-one-vma.html - shard-snb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8275/shard-snb5/igt@gem_cl...@many-handles-one-vma.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-snb2/igt@gem_cl...@many-handles-one-vma.html - shard-iclb: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8275/shard-iclb3/igt@gem_cl...@many-handles-one-vma.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-iclb1/igt@gem_cl...@many-handles-one-vma.html * igt@gem_ctx_persistence@smoketest: - shard-skl: [PASS][7] -> [INCOMPLETE][8] +12 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8275/shard-skl5/igt@gem_ctx_persiste...@smoketest.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-skl8/igt@gem_ctx_persiste...@smoketest.html * igt@kms_big_fb@linear-8bpp-rotate-180: - shard-apl: [PASS][9] -> [INCOMPLETE][10] +15 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8275/shard-apl3/igt@kms_big...@linear-8bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-apl8/igt@kms_big...@linear-8bpp-rotate-180.html * igt@kms_big_fb@y-tiled-16bpp-rotate-270: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] +11 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8275/shard-iclb4/igt@kms_big...@y-tiled-16bpp-rotate-270.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-iclb6/igt@kms_big...@y-tiled-16bpp-rotate-270.html * igt@kms_big_fb@y-tiled-64bpp-rotate-180: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] +13 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8275/shard-tglb3/igt@kms_big...@y-tiled-64bpp-rotate-180.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-tglb5/igt@kms_big...@y-tiled-64bpp-rotate-180.html * igt@kms_big_fb@y-tiled-8bpp-rotate-0: - shard-kbl: [PASS][15] -> [INCOMPLETE][16] +14 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8275/shard-kbl2/igt@kms_big...@y-tiled-8bpp-rotate-0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-kbl1/igt@kms_big...@y-tiled-8bpp-rotate-0.html * igt@runner@aborted: - shard-iclb: NOTRUN -> ([FAIL][17], [FAIL][18]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-iclb7/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-iclb7/igt@run...@aborted.html - shard-tglb: NOTRUN -> ([FAIL][19], [FAIL][20]) ([i915#1389]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-tglb7/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-tglb8/igt@run...@aborted.html Warnings * igt@runner@aborted: - shard-kbl: [FAIL][21] ([i915#1423] / [i915#92]) -> ([FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26]) ([i915#1389] / [i915#1402] / [i915#1423] / [i915#92]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8275/shard-kbl6/igt@run...@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-kbl1/igt@run...@aborted.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-kbl2/igt@run...@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-kbl4/igt@run...@aborted.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-kbl7/igt@run...@aborted.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17253/shard-kbl4/igt@run...@aborted.html Suppressed
Re: [Intel-gfx] [PATCH 2/2] drm/i915: remove gvt/Makefile
On Fri, 10 Apr 2020, Masahiro Yamada wrote: > Including subdirectory Makefile from the driver main Makefile does not > buy us much because this is not real isolation. The isolation it does buy us is that gvt/ subdirectory is developed and maintained on a separate mailing list and separate git repo. I think at some point there were plans to make it an actual module too. So while you could quip about Conway's law here, I think it might be better to keep this as it is. Zhenyu, Zhi, what do you think? BR, Jani. > > Having a single Makefile at the top of the module is clearer, and > it is what this driver almost does. > > Move all gvt objects to the i915 main Makefile. > > Signed-off-by: Masahiro Yamada > --- > > drivers/gpu/drm/i915/Makefile | 28 > drivers/gpu/drm/i915/gvt/Makefile | 8 > 2 files changed, 24 insertions(+), 12 deletions(-) > delete mode 100644 drivers/gpu/drm/i915/gvt/Makefile > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 6cd1f6253814..74e965882a98 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -275,10 +275,30 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \ > # virtual gpu code > i915-y += i915_vgpu.o > > -ifeq ($(CONFIG_DRM_I915_GVT),y) > -i915-y += intel_gvt.o > -include $(src)/gvt/Makefile > -endif > +i915-$(CONFIG_DRM_I915_GVT) += \ > + intel_gvt.o \ > + gvt/gvt.o \ > + gvt/aperture_gm.o \ > + gvt/handlers.o \ > + gvt/vgpu.o \ > + gvt/trace_points.o \ > + gvt/firmware.o \ > + gvt/interrupt.o \ > + gvt/gtt.o \ > + gvt/cfg_space.o \ > + gvt/opregion.o \ > + gvt/mmio.o \ > + gvt/display.o \ > + gvt/edid.o \ > + gvt/execlist.o \ > + gvt/scheduler.o \ > + gvt/sched_policy.o \ > + gvt/mmio_context.o \ > + gvt/cmd_parser.o \ > + gvt/debugfs.o \ > + gvt/fb_decoder.o \ > + gvt/dmabuf.o \ > + gvt/page_track.o > > obj-$(CONFIG_DRM_I915) += i915.o > obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o > diff --git a/drivers/gpu/drm/i915/gvt/Makefile > b/drivers/gpu/drm/i915/gvt/Makefile > deleted file mode 100644 > index 4d70f4689479.. > --- a/drivers/gpu/drm/i915/gvt/Makefile > +++ /dev/null > @@ -1,8 +0,0 @@ > -# SPDX-License-Identifier: GPL-2.0 > -GVT_DIR := gvt > -GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o > firmware.o \ > - interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \ > - execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o > debugfs.o \ > - fb_decoder.o dmabuf.o page_track.o > - > -i915-y += $(addprefix $(GVT_DIR)/, > $(GVT_SOURCE)) -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 15/17] drm/gma500: Stop using mode->private_flags
Hi Ville.
> > > > > index 264d7ad004b4..9e88a37f55e9 100644
> > > > > --- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > > +++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > > @@ -132,6 +132,8 @@ struct psb_intel_sdvo {
> > > > > /* DDC bus used by this SDVO encoder */
> > > > > uint8_t ddc_bus;
> > > > >
> > > > > + u8 pixel_multiplier;
> > > > > +
> > > >
> > > > There is really no good reason to use an u8 here.
> > >
> > > Wastes less space.
> >
> > When there is a good reason - use the size limited variants.
> > But in this use case there is no reason to space optimize it.
>
> IMO when it's stuffed into a structure there's no reason not to
> optimize it. At some point it all starts to add up.
>
> At least i915 suffers a lot from bloated structures (dev_priv
> and atomic state structs being the prime examples) where we
> could probably shave dozens if not hundreds of bytes if
> everything just used the smallest type possible. In fact
> this series does shave dozens of bytes from the crtc state
> alone.
There is a difference between a structure used many times -
And a structure used once or only a few times.
If everyone started to optimize the types used, then we
would end up with code that is hard to maintain.
The point here is that we have a structure allocated maybe
once and a field assinged from a int - which using integer promotion
is then stuffed into an u8. If we one day start to be clever and
use values above 255 we need to find all the places where a
u8 was used to optimize size of some random struct.
If this was a struct instantiated many times and used all over
the story was another - but thats not the case here.
Here the principle of least suprises hold - do not change the type.
I try to explain the rationale behind the argument to use int.
Feel free to disagree.
>
> >
> > When in the slightly pedantic mode, using u8 is not consistent.
> > ddc_bus defined above usese uint8_t.
>
> u8 & co. are preferred in kernel code. Checkpatch even complains when
> you use the stdint types. The uint8_t here is some old leftovers.
Mixing coding practice makes code less readable, no matter
the output of checkpatch.
The right fix would be to update gma500 to migrate away from the
stdint types. But that would be a sepearte patch for another day.
My orginal feedback on the patch has not changed.
Feel free to move forward with the patch without my r-b.
Sam
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] i915/i915_pm_rc6_residency: Show where the time is spent
Hi Chris, On Wed, Apr 08, 2020 at 01:59:46PM +0100, Chris Wilson wrote: > Sometimes the bg_load only wakes up once or twice in 3s. That's > just unbelievable, so include some measurements to see how long the > load spends in submission & waiting. > > Signed-off-by: Chris Wilson Reviewed-by: Andi Shyti Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 15/17] drm/gma500: Stop using mode->private_flags
On Thu, Apr 09, 2020 at 10:49:52PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 07, 2020 at 09:35:37PM +0200, Sam Ravnborg wrote:
> > On Tue, Apr 07, 2020 at 10:08:00PM +0300, Ville Syrjälä wrote:
> > > On Tue, Apr 07, 2020 at 08:56:53PM +0200, Sam Ravnborg wrote:
> > > > Hi Ville.
> > > >
> > > > On Fri, Apr 03, 2020 at 11:40:06PM +0300, Ville Syrjala wrote:
> > > > > From: Ville Syrjälä
> > > > >
> > > > > gma500 only uses mode->private_flags to convey the sdvo pixel
> > > > > multiplier from the encoder .mode_fixup() hook to the encoder
> > > > > .mode_set() hook. Those always seems get called as a pair so
> > > > > let's just stuff the pixel multiplier into the encoder itself
> > > > > as there are no state objects we could use in this non-atomic
> > > > > driver.
> > > > >
> > > > > Paves the way for nuking mode->private_flag.
> > > > Nice little clean-up. One comment below.
> > > >
> > > > Sam
> > > > >
> > > > > Cc: Patrik Jakobsson
> > > > > CC: Sam Ravnborg
> > > > > Cc: Daniel Vetter
> > > > > Cc: Emil Velikov
> > > > > Signed-off-by: Ville Syrjälä
> > > > > ---
> > > > > drivers/gpu/drm/gma500/psb_intel_drv.h | 19 ---
> > > > > drivers/gpu/drm/gma500/psb_intel_sdvo.c | 11 ++-
> > > > > 2 files changed, 6 insertions(+), 24 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h
> > > > > b/drivers/gpu/drm/gma500/psb_intel_drv.h
> > > > > index fb601983cef0..3dd5718c3e31 100644
> > > > > --- a/drivers/gpu/drm/gma500/psb_intel_drv.h
> > > > > +++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
> > > > > @@ -56,25 +56,6 @@
> > > > > #define INTEL_OUTPUT_DISPLAYPORT 9
> > > > > #define INTEL_OUTPUT_EDP 10
> > > > >
> > > > > -#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
> > > > > -#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf <<
> > > > > INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
> > > > > -
> > > > > -static inline void
> > > > > -psb_intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
> > > > > - int multiplier)
> > > > > -{
> > > > > - mode->clock *= multiplier;
> > > > > - mode->private_flags |= multiplier;
> > > > > -}
> > > > > -
> > > > > -static inline int
> > > > > -psb_intel_mode_get_pixel_multiplier(const struct drm_display_mode
> > > > > *mode)
> > > > > -{
> > > > > - return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK)
> > > > > ->> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
> > > > > -}
> > > > > -
> > > > > -
> > > > > /*
> > > > > * Hold information useally put on the device driver privates here,
> > > > > * since it needs to be shared across multiple of devices drivers
> > > > > privates.
> > > > > diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > > b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > > index 264d7ad004b4..9e88a37f55e9 100644
> > > > > --- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > > +++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > > @@ -132,6 +132,8 @@ struct psb_intel_sdvo {
> > > > > /* DDC bus used by this SDVO encoder */
> > > > > uint8_t ddc_bus;
> > > > >
> > > > > + u8 pixel_multiplier;
> > > > > +
> > > >
> > > > There is really no good reason to use an u8 here.
> > >
> > > Wastes less space.
> >
> > When there is a good reason - use the size limited variants.
> > But in this use case there is no reason to space optimize it.
>
> IMO when it's stuffed into a structure there's no reason not to
> optimize it. At some point it all starts to add up.
>
> At least i915 suffers a lot from bloated structures (dev_priv
> and atomic state structs being the prime examples) where we
> could probably shave dozens if not hundreds of bytes if
> everything just used the smallest type possible. In fact
> this series does shave dozens of bytes from the crtc state
> alone.
Make that hundreds of bytes actually. I think we have three or more
copies of drm_display_mode embedded in there and this series shrinks
each one by 80 bytes (iirc).
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 15/17] drm/gma500: Stop using mode->private_flags
On Tue, Apr 07, 2020 at 09:35:37PM +0200, Sam Ravnborg wrote:
> On Tue, Apr 07, 2020 at 10:08:00PM +0300, Ville Syrjälä wrote:
> > On Tue, Apr 07, 2020 at 08:56:53PM +0200, Sam Ravnborg wrote:
> > > Hi Ville.
> > >
> > > On Fri, Apr 03, 2020 at 11:40:06PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> > > > gma500 only uses mode->private_flags to convey the sdvo pixel
> > > > multiplier from the encoder .mode_fixup() hook to the encoder
> > > > .mode_set() hook. Those always seems get called as a pair so
> > > > let's just stuff the pixel multiplier into the encoder itself
> > > > as there are no state objects we could use in this non-atomic
> > > > driver.
> > > >
> > > > Paves the way for nuking mode->private_flag.
> > > Nice little clean-up. One comment below.
> > >
> > > Sam
> > > >
> > > > Cc: Patrik Jakobsson
> > > > CC: Sam Ravnborg
> > > > Cc: Daniel Vetter
> > > > Cc: Emil Velikov
> > > > Signed-off-by: Ville Syrjälä
> > > > ---
> > > > drivers/gpu/drm/gma500/psb_intel_drv.h | 19 ---
> > > > drivers/gpu/drm/gma500/psb_intel_sdvo.c | 11 ++-
> > > > 2 files changed, 6 insertions(+), 24 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h
> > > > b/drivers/gpu/drm/gma500/psb_intel_drv.h
> > > > index fb601983cef0..3dd5718c3e31 100644
> > > > --- a/drivers/gpu/drm/gma500/psb_intel_drv.h
> > > > +++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
> > > > @@ -56,25 +56,6 @@
> > > > #define INTEL_OUTPUT_DISPLAYPORT 9
> > > > #define INTEL_OUTPUT_EDP 10
> > > >
> > > > -#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
> > > > -#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf <<
> > > > INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
> > > > -
> > > > -static inline void
> > > > -psb_intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
> > > > - int multiplier)
> > > > -{
> > > > - mode->clock *= multiplier;
> > > > - mode->private_flags |= multiplier;
> > > > -}
> > > > -
> > > > -static inline int
> > > > -psb_intel_mode_get_pixel_multiplier(const struct drm_display_mode
> > > > *mode)
> > > > -{
> > > > - return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK)
> > > > - >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
> > > > -}
> > > > -
> > > > -
> > > > /*
> > > > * Hold information useally put on the device driver privates here,
> > > > * since it needs to be shared across multiple of devices drivers
> > > > privates.
> > > > diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > index 264d7ad004b4..9e88a37f55e9 100644
> > > > --- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > +++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
> > > > @@ -132,6 +132,8 @@ struct psb_intel_sdvo {
> > > > /* DDC bus used by this SDVO encoder */
> > > > uint8_t ddc_bus;
> > > >
> > > > + u8 pixel_multiplier;
> > > > +
> > >
> > > There is really no good reason to use an u8 here.
> >
> > Wastes less space.
>
> When there is a good reason - use the size limited variants.
> But in this use case there is no reason to space optimize it.
IMO when it's stuffed into a structure there's no reason not to
optimize it. At some point it all starts to add up.
At least i915 suffers a lot from bloated structures (dev_priv
and atomic state structs being the prime examples) where we
could probably shave dozens if not hundreds of bytes if
everything just used the smallest type possible. In fact
this series does shave dozens of bytes from the crtc state
alone.
>
> When in the slightly pedantic mode, using u8 is not consistent.
> ddc_bus defined above usese uint8_t.
u8 & co. are preferred in kernel code. Checkpatch even complains when
you use the stdint types. The uint8_t here is some old leftovers.
>
> Sam
> >
> > > psb_intel_sdvo_get_pixel_multiplier() return an int, so use an int here
> > > too.
> > >
> > > With this fixed:
> > > Reviewed-by: Sam Ravnborg
> > >
> > > > /* Input timings for adjusted_mode */
> > > > struct psb_intel_sdvo_dtd input_dtd;
> > > >
> > > > @@ -958,7 +960,6 @@ static bool psb_intel_sdvo_mode_fixup(struct
> > > > drm_encoder *encoder,
> > > > struct drm_display_mode
> > > > *adjusted_mode)
> > > > {
> > > > struct psb_intel_sdvo *psb_intel_sdvo =
> > > > to_psb_intel_sdvo(encoder);
> > > > - int multiplier;
> > > >
> > > > /* We need to construct preferred input timings based on our
> > > > * output timings. To do that, we have to set the output
> > > > @@ -985,8 +986,9 @@ static bool psb_intel_sdvo_mode_fixup(struct
> > > > drm_encoder *encoder,
> > > > /* Make the CRTC code factor in the SDVO pixel multiplier. The
> > > > * SDVO device will factor out the multiplier during mode_set.
> > > > */
> > > > - multiplier =
Re: [Intel-gfx] [PATCH] drm/i915: remove redundant assignment to variable err
Quoting Colin King (2020-04-09 14:31:07)
> From: Colin Ian King
>
> The variable err is being initialized with a value that is never read
> and it is being updated later with a new value. The initialization is
> redundant and can be removed.
>
> Addresses-Coverity: ("Unused value")
> Signed-off-by: Colin Ian King
Could be useful... No, let's not look at that function again.
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RESEND PATCH] drm/i915: do AUD_FREQ_CNTRL state save on all gen9+ platforms
On Thu, Apr 09, 2020 at 05:14:01PM +0300, Kai Vehmanen wrote: > Hey, > > On Mon, 30 Mar 2020, Kai Vehmanen wrote: > > > Replace the TGL/ICL specific platform checks with a more generic check > > using INTEL_GEN(). Fixes bug with broken audio after S3 resume on JSL > > platforms. > > I would be (gently) beaten with a stick on alsa-devel for sending this > type of content free ping, but I still dare to seek your input on what is > the proper way to get attention to a patch that are seemingly forever > stuck on the review sideline. And what is this? https://patchwork.freedesktop.org/patch/347148/?series=71527=1 > > I've sent this on 13.3., resend on 30.3.. Should I just keep on sending > resends and let the system work (this is the alsa-devel practise), or > should I start to contact potential reviewers with more direct asks? Just ping on original patch or ping someone on irc. Resending the same patch over and over does no good. At least my brain just ignores anything that looks like it's just a resend w/o any clear justification. > > Tests seem to all pass and this is pretty important for anyone using JSL > platforms (you lose HDMI/DP audio after first S3 suspend otherwise): > https://patchwork.freedesktop.org/series/74664/ > > Br, Kai -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev14)
== Series Details == Series: SAGV support for Gen12+ (rev14) URL : https://patchwork.freedesktop.org/series/75129/ State : success == Summary == CI Bug Log - changes from CI_DRM_8285 -> Patchwork_17271 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17271/index.html Known issues Here are the changes found in Patchwork_17271 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([i915#262]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8285/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17271/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_module_load@reload: - fi-skl-6770hq: [DMESG-WARN][3] ([i915#203]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8285/fi-skl-6770hq/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17271/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [SKIP][5] ([fdo#109271]) -> [PASS][6] +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8285/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17271/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-skl-6770hq: [DMESG-WARN][7] ([i915#106]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8285/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17271/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][9] ([i915#62] / [i915#95]) -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8285/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17271/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106 [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 47) -- Additional (1): fi-cml-u2 Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8285 -> Patchwork_17271 CI-20190529: 20190529 CI_DRM_8285: 12fc367c2557ea74051378b2baadc6116add10ba @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5586: 29fad328e6a1b105c8d688cafe19b1b5c19ad0c8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17271: e967954f905e7e51449b415b65d478a0eb934a99 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e967954f905e drm/i915: Enable SAGV support for Gen12 9a18dd734b17 drm/i915: Restrict qgv points which don't have enough bandwidth. 8324f5130045 drm/i915: Rename bw_state to new_bw_state 49c46f4edf34 drm/i915: Added required new PCode commands fd7ee6e3d868 drm/i915: Add TGL+ SAGV support 7c3a86821437 drm/i915: Separate icl and skl SAGV checking 7b65af3b3c25 drm/i915: Use bw state for per crtc SAGV evaluation f573a32afca5 drm/i915: Add pre/post plane updates for SAGV 926c0a7aaf2a drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv 00989296f52d drm/i915: Add intel_atomic_get_bw_*_state helpers 28f3e791c62a drm/i915: Introduce skl_plane_wm_level accessor. 39684149a1cb drm/i915: Eliminate magic numbers "0" and "1" from color plane db3bb77d347e drm/i915: Start passing latency as parameter == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17271/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for SAGV support for Gen12+ (rev14)
== Series Details == Series: SAGV support for Gen12+ (rev14) URL : https://patchwork.freedesktop.org/series/75129/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: Start passing latency as parameter Okay! Commit: drm/i915: Eliminate magic numbers "0" and "1" from color plane Okay! Commit: drm/i915: Introduce skl_plane_wm_level accessor. Okay! Commit: drm/i915: Add intel_atomic_get_bw_*_state helpers Okay! Commit: drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv Okay! Commit: drm/i915: Add pre/post plane updates for SAGV Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915: Add Plane color encoding support for YCBCR_BT2020
On Wed, Apr 08, 2020 at 07:52:27PM +0530, Kishore Kadiyala wrote:
> Currently the plane property doesn't have support for YCBCR_BT2020,
> which enables the corresponding color conversion mode on plane CSC.
> Enabling the plane property for the planes for GLK & ICL+ platforms.
>
> V2: Enabling support for YCBCT_BT2020 for HDR planes on
> platforms GLK & ICL
>
> V3: Refined the condition check to handle GLK & ICL+ HDR planes
> Also added BT2020 handling in glk_plane_color_ctl.
>
> V4: Combine If-else into single If
>
> V5: Drop the checking for HDR planes and enable YCBCR_BT2020
> for platforms GLK & ICL+.
>
> Cc: Ville Syrjala
> Cc: Uma Shankar
> Cc: Jani Nikula
> Signed-off-by: Kishore Kadiyala
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 +---
> drivers/gpu/drm/i915/display/intel_sprite.c | 9 +++--
> 2 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 70ec301fe6e3..f2dfa61a49fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4808,11 +4808,17 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
> *crtc_state,
> plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>
> if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
> - if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
> + switch (plane_state->hw.color_encoding) {
> + case DRM_COLOR_YCBCR_BT709:
> plane_color_ctl |=
> PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> - else
> + break;
> + case DRM_COLOR_YCBCR_BT2020:
> + plane_color_ctl |=
> + PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
> + break;
> + default:
> plane_color_ctl |=
> PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
IIRC the spec has been fixed in the meantime, so as a followup can
you rename this to YUV601_TO_RGB601?
> -
> + }
> if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> plane_color_ctl |=
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> } else if (fb->format->is_yuv) {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index deda351719db..0072525046a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -3031,6 +3031,7 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
> struct intel_plane *plane;
> enum drm_plane_type plane_type;
> unsigned int supported_rotations;
> + unsigned int supported_csc;
> const u64 *modifiers;
> const u32 *formats;
> int num_formats;
> @@ -3105,9 +3106,13 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
> DRM_MODE_ROTATE_0,
> supported_rotations);
>
> + supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
> +
> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
> +
> drm_plane_create_color_properties(>base,
> - BIT(DRM_COLOR_YCBCR_BT601) |
> - BIT(DRM_COLOR_YCBCR_BT709),
> + supported_csc,
> BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
> BIT(DRM_COLOR_YCBCR_FULL_RANGE),
> DRM_COLOR_YCBCR_BT709,
> --
> 2.17.1
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev14)
== Series Details ==
Series: SAGV support for Gen12+ (rev14)
URL : https://patchwork.freedesktop.org/series/75129/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
db3bb77d347e drm/i915: Start passing latency as parameter
39684149a1cb drm/i915: Eliminate magic numbers "0" and "1" from color plane
28f3e791c62a drm/i915: Introduce skl_plane_wm_level accessor.
00989296f52d drm/i915: Add intel_atomic_get_bw_*_state helpers
926c0a7aaf2a drm/i915: Prepare to extract gen specific functions from
intel_can_enable_sagv
-:84: CHECK:LINE_SPACING: Please don't use multiple blank lines
#84: FILE: drivers/gpu/drm/i915/intel_pm.c:3809:
+
total: 0 errors, 0 warnings, 1 checks, 93 lines checked
f573a32afca5 drm/i915: Add pre/post plane updates for SAGV
7b65af3b3c25 drm/i915: Use bw state for per crtc SAGV evaluation
-:111: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#111: FILE: drivers/gpu/drm/i915/intel_pm.c:3861:
+new_crtc_state, i) {
+
total: 0 errors, 0 warnings, 1 checks, 137 lines checked
7c3a86821437 drm/i915: Separate icl and skl SAGV checking
fd7ee6e3d868 drm/i915: Add TGL+ SAGV support
-:217: CHECK:LINE_SPACING: Please don't use multiple blank lines
#217: FILE: drivers/gpu/drm/i915/intel_pm.c:5356:
+
+
-:247: WARNING:LONG_LINE: line over 100 characters
#247: FILE: drivers/gpu/drm/i915/intel_pm.c:5848:
+ plane->base.base.id, plane->base.name,
old_wm->sagv_wm0.plane_res_l,
-:273: WARNING:LONG_LINE: line over 100 characters
#273: FILE: drivers/gpu/drm/i915/intel_pm.c:5889:
+ plane->base.base.id, plane->base.name,
old_wm->sagv_wm0.min_ddb_alloc,
total: 0 errors, 2 warnings, 1 checks, 247 lines checked
49c46f4edf34 drm/i915: Added required new PCode commands
8324f5130045 drm/i915: Rename bw_state to new_bw_state
9a18dd734b17 drm/i915: Restrict qgv points which don't have enough bandwidth.
e967954f905e drm/i915: Enable SAGV support for Gen12
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: remove unneeded ccflags-y from gvt/Makefile
== Series Details == Series: series starting with [1/2] drm/i915: remove unneeded ccflags-y from gvt/Makefile URL : https://patchwork.freedesktop.org/series/75756/ State : success == Summary == CI Bug Log - changes from CI_DRM_8284 -> Patchwork_17270 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17270/index.html Known issues Here are the changes found in Patchwork_17270 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#1662]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8284/fi-tgl-y/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17270/fi-tgl-y/igt@i915_selftest@l...@execlists.html * igt@kms_flip@basic-flip-vs-dpms: - fi-skl-6770hq: [PASS][3] -> [SKIP][4] ([fdo#109271]) +24 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8284/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17270/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-icl-dsi: [INCOMPLETE][5] ([i915#189]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8284/fi-icl-dsi/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17270/fi-icl-dsi/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1662]: https://gitlab.freedesktop.org/drm/intel/issues/1662 [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 Participating hosts (53 -> 47) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8284 -> Patchwork_17270 CI-20190529: 20190529 CI_DRM_8284: 307cf5040adae84648708ec34c64402dddff0171 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5586: 29fad328e6a1b105c8d688cafe19b1b5c19ad0c8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17270: 923a4c82674832bcc9150df1cc4b5f67024fb273 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 923a4c826748 drm/i915: remove gvt/Makefile b7e9f445aafa drm/i915: remove unneeded ccflags-y from gvt/Makefile == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17270/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: drop guc parameter from guc_ggtt_offset
On 4/9/20 7:03 AM, Michal Wajdeczko wrote:
On 09.04.2020 02:56, Daniele Ceraolo Spurio wrote:
We stopped using the parameter in commit dd18cedfa36f
("drm/i915/guc: Move the pin bias value from GuC to GGTT"),
so we can safely remove it.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Brost
Cc: Michal Wajdeczko
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 6 +++---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 +---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 5 ++---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 3 +--
6 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 861657897c0f..5134d544bf4c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -220,7 +220,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
if (intel_guc_submission_is_used(guc)) {
u32 ctxnum, base;
- base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
+ base = intel_guc_ggtt_offset(guc->stage_desc_pool);
ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
base >>= PAGE_SHIFT;
@@ -232,7 +232,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
{
- u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
+ u32 offset = intel_guc_ggtt_offset(guc->log.vma) >> PAGE_SHIFT;
u32 flags;
#if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
@@ -273,7 +273,7 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
static u32 guc_ctl_ads_flags(struct intel_guc *guc)
{
- u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
+ u32 ads = intel_guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
u32 flags = ads << GUC_ADS_ADDR_SHIFT;
return flags;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index e84ab67b317d..366191204a7d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -103,7 +103,6 @@ static inline void intel_guc_to_host_event_handler(struct
intel_guc *guc)
/**
* intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
- * @guc: intel_guc structure.
* @vma: i915 graphics virtual memory area.
*
* GuC does not allow any gfx GGTT address that falls into range
@@ -114,8 +113,7 @@ static inline void intel_guc_to_host_event_handler(struct
intel_guc *guc)
*
* Return: GGTT offset of the @vma.
*/
-static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
- struct i915_vma *vma)
+static inline u32 intel_guc_ggtt_offset(struct i915_vma *vma)
leaving this function with 'intel_guc' prefix without param guc would
break our naming schema, maybe we should rename it to:
static inline u32 i915_ggtt_offset_guc(struct i915_vma *vma)
I'm not convinced this is a good idea, the guc code still owns this
function, so IMO it should still be called intel_guc_* to make that
clear. We do have plenty of examples where the prefix and the param
don't match, e.g. i915_ggtt_pin_bias just below accepts a vma and not
the GGTT structure. With this I don't want to say that we should not try
to match the prefix and param as much as possible, just that we should
avoid enforcing that rule too strictly.
as code inside init_ggtt() already understands guc specifics ...
{
u32 offset = i915_ggtt_offset(vma);
btw, we have here (not shown) in diff:
GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
that I would move to i915_ggtt_offset() as it quite generic
Not all objects are pinned using the bias so can't do that.
and replace it with something more GuC specific, like:
GEM_BUG_ON(offset < intel_wopcm_guc_size(wopcm))
I have a patch later in the series to move the wopcm under uc, so
getting it from the vma would be troublesome (vma->vm->gt.uc). Since we
use this for HuC as well maybe we can change to:
intel_uc_ggtt_offset(struct intel_uc *uc, struct i915_vma *vma)
{
GEM_BUG_ON(offset < intel_uc_wopcm_guc_size(uc));
...
}
but not sure if passing in the uc just to get to the wopcm is overkill
when we have the bias value easily accessible via i915_ggtt_pin_bias.
Thoughts?
Daniele
Michal
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 101728006ae9..9237d798f7f4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -107,7 +107,7 @@ static void __guc_ads_init(struct intel_guc *guc)
blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
Re: [Intel-gfx] [PATCH v21 05/10] drm/i915: Extract gen specific functions from intel_can_enable_sagv
On Wed, Apr 08, 2020 at 07:18:11PM +0300, Lisovskiy, Stanislav wrote:
> On Wed, Apr 08, 2020 at 06:54:09PM +0300, Lisovskiy, Stanislav wrote:
> > On Wed, Apr 08, 2020 at 05:55:02PM +0300, Ville Syrjälä wrote:
> > > On Wed, Apr 08, 2020 at 10:58:04AM +0300, Lisovskiy, Stanislav wrote:
> > > > On Tue, Apr 07, 2020 at 10:01:28PM +0300, Ville Syrjälä wrote:
> > > > > On Fri, Apr 03, 2020 at 09:20:03AM +0300, Stanislav Lisovskiy wrote:
> > > > > > Addressing one of the comments, recommending to extract platform
> > > > > > specific code from intel_can_enable_sagv as a preparation, before
> > > > > > we are going to add support for tgl+.
> > > > > >
> > > > > > Current code in intel_can_enable_sagv is valid only for skl,
> > > > > > so this patch adds also proper support for icl, subsequent
> > > > > > patches will add support for tgl+, combined with other required
> > > > > > changes.
> > > > > >
> > > > > > v2: - Renamed icl_can_enable_sagv into
> > > > > > icl_crtc_can_enable_sagv(Ville)
> > > > > > - Removed dev variables(Ville)
> > > > > > - Constified crtc/plane_state in icl_crtc_can_enable_sagv
> > > > > > function(Ville)
> > > > > > - Added hw.active check(Ville)
> > > > > > - Refactored if ladder(Ville)
> > > > > >
> > > > > > Signed-off-by: Stanislav Lisovskiy
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/intel_pm.c | 84
> > > > > > +
> > > > > > 1 file changed, 55 insertions(+), 29 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index f8d62d1977ac..27d4d626cb34 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -3757,42 +3757,25 @@ intel_disable_sagv(struct drm_i915_private
> > > > > > *dev_priv)
> > > > > > return 0;
> > > > > > }
> > > > > >
> > > > > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > > > > +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state
> > > > > > *crtc_state)
> > > > > > {
> > > > > > - struct drm_device *dev = state->base.dev;
> > > > > > - struct drm_i915_private *dev_priv = to_i915(dev);
> > > > > > - struct intel_crtc *crtc;
> > > > > > + struct drm_i915_private *dev_priv =
> > > > > > to_i915(crtc_state->uapi.crtc->dev);
> > > > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > > > struct intel_plane *plane;
> > > > > > - struct intel_crtc_state *crtc_state;
> > > > > > - enum pipe pipe;
> > > > > > + const struct intel_plane_state *plane_state;
> > > > > > int level, latency;
> > > > > >
> > > > > > - if (!intel_has_sagv(dev_priv))
> > > > > > + if (crtc_state->hw.adjusted_mode.flags &
> > > > > > DRM_MODE_FLAG_INTERLACE) {
> > > > > > + DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe
> > > > > > %c\n",
> > > > > > + pipe_name(crtc->pipe));
> > > > > > return false;
> > > > > > + }
> > > > > >
> > > > > > - /*
> > > > > > -* If there are no active CRTCs, no additional checks need be
> > > > > > performed
> > > > > > -*/
> > > > > > - if (hweight8(state->active_pipes) == 0)
> > > > > > + if (!crtc_state->hw.active)
> > > > >
> > > > > Should really be checked before anything else. Doesn't matter too much
> > > > > anymore since I made us clear the crtc state always, but still a bit
> > > > > inconsistent to look at other stuff in the state before we even know
> > > > > if
> > > > > the crtc is even enabled.
> > > > >
> > > > > > return true;
> > > > > >
> > > > > > - /*
> > > > > > -* SKL+ workaround: bspec recommends we disable SAGV when we
> > > > > > have
> > > > > > -* more then one pipe enabled
> > > > > > -*/
> > > > > > - if (hweight8(state->active_pipes) > 1)
> > > > > > - return false;
> > > > > > -
> > > > > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > > > > - pipe = ffs(state->active_pipes) - 1;
> > > > > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > > > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > > > > -
> > > > > > - if (crtc_state->hw.adjusted_mode.flags &
> > > > > > DRM_MODE_FLAG_INTERLACE)
> > > > > > - return false;
> > > > > > -
> > > > > > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > > > > - struct skl_plane_wm *wm =
> > > > > > + intel_atomic_crtc_state_for_each_plane_state(plane,
> > > > > > plane_state, crtc_state) {
> > > > > > + const struct skl_plane_wm *wm =
> > > > > > _state->wm.skl.optimal.planes[plane->id];
> > > > > >
> > > > > > /* Skip this plane if it's not enabled */
> > > > > > @@ -3807,7 +3790,7 @@ bool intel_can_enable_sagv(struct
> > > > > > intel_atomic_state *state)
> > > > > > latency = dev_priv->wm.skl_latency[level];
> > > >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: remove unneeded ccflags-y from gvt/Makefile
== Series Details == Series: series starting with [1/2] drm/i915: remove unneeded ccflags-y from gvt/Makefile URL : https://patchwork.freedesktop.org/series/75756/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: remove unneeded ccflags-y from gvt/Makefile +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2280:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2281:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/i915_perf.c:1427:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1481:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/linux/compiler.h:199:9: warning: context imbalance in 'engines_sample' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context
[Intel-gfx] [PATCH v22 11/13] drm/i915: Rename bw_state to new_bw_state
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.
v2: Removed spurious space
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 96f86cfa91d4..f793297ef946 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -418,7 +418,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
- struct intel_bw_state *bw_state = NULL;
+ struct intel_bw_state *new_bw_state = NULL;
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
@@ -447,29 +447,29 @@ int intel_bw_atomic_check(struct intel_atomic_state
*state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- bw_state->data_rate[crtc->pipe] = new_data_rate;
- bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+ new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+ new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
drm_dbg_kms(_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
- bw_state->data_rate[crtc->pipe],
- bw_state->num_active_planes[crtc->pipe]);
+ new_bw_state->data_rate[crtc->pipe],
+ new_bw_state->num_active_planes[crtc->pipe]);
}
- if (!bw_state)
+ if (!new_bw_state)
return 0;
- ret = intel_atomic_lock_global_state(_state->base);
+ ret = intel_atomic_lock_global_state(_bw_state->base);
if (ret)
return ret;
- data_rate = intel_bw_data_rate(dev_priv, bw_state);
- num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
--
2.24.1.485.gad05a3d8e5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v22 12/13] drm/i915: Restrict qgv points which don't have enough bandwidth.
According to BSpec 53998, we should try to restrict qgv points, which can't provide enough bandwidth for desired display configuration. Currently we are just comparing against all of those and take minimum(worst case). v2: Fixed wrong PCode reply mask, removed hardcoded values. v3: Forbid simultaneous legacy SAGV PCode requests and restricting qgv points. Put the actual restriction to commit function, added serialization(thanks to Ville) to prevent commit being applied out of order in case of nonblocking and/or nomodeset commits. v4: - Minor code refactoring, fixed few typos(thanks to James Ausmus) - Change the naming of qgv point masking/unmasking functions(James Ausmus). - Simplify the masking/unmasking operation itself, as we don't need to mask only single point per request(James Ausmus) - Reject and stick to highest bandwidth point if SAGV can't be enabled(BSpec) v5: - Add new mailbox reply codes, which seems to happen during boot time for TGL and indicate that QGV setting is not yet available. v6: - Increase number of supported QGV points to be in sync with BSpec. v7: - Rebased and resolved conflict to fix build failure. - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus) v8: - Don't report an error if we can't restrict qgv points, as SAGV can be disabled by BIOS, which is completely legal. So don't make CI panic. Instead if we detect that there is only 1 QGV point accessible just analyze if we can fit the required bandwidth requirements, but no need in restricting. v9: - Fix wrong QGV transition if we have 0 planes and no SAGV simultaneously. v10: - Fix CDCLK corruption, because of global state getting serialized without modeset, which caused copying of non-calculated cdclk to be copied to dev_priv(thanks to Ville for the hint). v11: - Remove unneeded headers and spaces(Matthew Roper) - Remove unneeded intel_qgv_info qi struct from bw check and zero out the needed one(Matthew Roper) - Changed QGV error message to have more clear meaning(Matthew Roper) - Use state->modeset_set instead of any_ms(Matthew Roper) - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used - Keep using crtc_state->hw.active instead of .enable(Matthew Roper) - Moved unrelated changes to other patch(using latency as parameter for plane wm calculation, moved to SAGV refactoring patch) v12: - Fix rebase conflict with own temporary SAGV/QGV fix. - Remove unnecessary mask being zero check when unmasking qgv points as this is completely legal(Matt Roper) - Check if we are setting the same mask as already being set in hardware to prevent error from PCode. - Fix error message when restricting/unrestricting qgv points to "mask/unmask" which sounds more accurate(Matt Roper) - Move sagv status setting to icl_get_bw_info from atomic check as this should be calculated only once.(Matt Roper) - Edited comments for the case when we can't enable SAGV and use only 1 QGV point with highest bandwidth to be more understandable.(Matt Roper) v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä) - Changed comment for zero new_mask in qgv points masking function to better reflect reality(Ville Syrjälä) - Simplified bit mask operation in qgv points masking function (Ville Syrjälä) - Moved intel_qgv_points_mask closer to gen11 SAGV disabling, however this still can't be under modeset condition(Ville Syrjälä) - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask (Ville Syrjälä) - Extracted PCode changes to separate patch.(Ville Syrjälä) - Now treat num_planes 0 same as 1 to avoid confusion and returning max_bw as 0, which would prevent choosing QGV point having max bandwidth in case if SAGV is not allowed, as per BSpec(Ville Syrjälä) - Do the actual qgv_points_mask swap in the same place as all other global state parts like cdclk are swapped. In the next patch, this all will be moved to bw state as global state, once new global state patch series from Ville lands v14: - Now using global state to serialize access to qgv points - Added global state locking back, otherwise we seem to read bw state in a wrong way. v15: - Added TODO comment for near atomic global state locking in bw code. v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed with Jani Nikula. - Take bw_state_changed flag into use. v17: - Moved qgv point related manipulations next to SAGV code, as those are semantically related(Ville Syrjälä) - Renamed those into intel_sagv_(pre)|(post)_plane_update (Ville Syrjälä) v18: - Move sagv related calls from commit tail into intel_sagv_(pre)|(post)_plane_update(Ville
[Intel-gfx] [PATCH v22 13/13] drm/i915: Enable SAGV support for Gen12
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 238793243fd9..56e1b208bead 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct
drm_i915_private *dev_priv)
bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
--
2.24.1.485.gad05a3d8e5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: remove unneeded ccflags-y from gvt/Makefile
== Series Details == Series: series starting with [1/2] drm/i915: remove unneeded ccflags-y from gvt/Makefile URL : https://patchwork.freedesktop.org/series/75756/ State : warning == Summary == $ dim checkpatch origin/drm-tip b7e9f445aafa drm/i915: remove unneeded ccflags-y from gvt/Makefile -:42: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #42: FILE: drivers/gpu/drm/i915/gvt/trace.h:380: +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/gvt ^ -:42: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #42: FILE: drivers/gpu/drm/i915/gvt/trace.h:380: +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/gvt ^ -:42: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #42: FILE: drivers/gpu/drm/i915/gvt/trace.h:380: +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/gvt ^ -:42: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #42: FILE: drivers/gpu/drm/i915/gvt/trace.h:380: +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/gvt ^ -:42: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #42: FILE: drivers/gpu/drm/i915/gvt/trace.h:380: +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/gvt ^ -:42: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #42: FILE: drivers/gpu/drm/i915/gvt/trace.h:380: +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/gvt ^ total: 0 errors, 0 warnings, 6 checks, 13 lines checked 923a4c826748 drm/i915: remove gvt/Makefile -:56: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #56: deleted file mode 100644 total: 0 errors, 1 warnings, 0 checks, 34 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v22 07/13] drm/i915: Use bw state for per crtc SAGV evaluation
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
Signed-off-by: Stanislav Lisovskiy
Cc: Ville Syrjälä
Cc: James Ausmus
---
drivers/gpu/drm/i915/display/intel_bw.h | 6 +++
drivers/gpu/drm/i915/intel_pm.c | 63 +++--
drivers/gpu/drm/i915/intel_pm.h | 4 +-
3 files changed, 58 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index ac004d6f4276..d6df91058223 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,12 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+* Contains a bit mask, used to determine, whether correspondent
+* pipe allows SAGV or not.
+*/
+ u8 pipe_sagv_reject;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1df288396d8..41305abad179 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct
drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3779,6 +3780,7 @@ void intel_sagv_post_plane_update(struct
intel_atomic_state *state)
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane;
@@ -3788,6 +3790,13 @@ static bool intel_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state
if (!crtc_state->hw.active)
return true;
+ /*
+* SKL+ workaround: bspec recommends we disable SAGV when we have
+* more then one pipe enabled
+*/
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
pipe_name(crtc->pipe));
@@ -3827,29 +3836,51 @@ static bool intel_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
+{
+ return bw_state->pipe_sagv_reject == 0;
+}
+
+static int intel_compute_sagv_mask(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
struct intel_crtc *crtc;
const struct intel_crtc_state *crtc_state;
enum pipe pipe;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_bw_state *new_bw_state = NULL;
+ const struct intel_bw_state *old_bw_state = NULL;
+ int i;
if (!intel_has_sagv(dev_priv))
- return false;
+ return 0;
- /*
-* SKL+ workaround: bspec recommends we disable SAGV when we have
-* more then one pipe enabled
-*/
- if (hweight8(state->active_pipes) > 1)
- return false;
+ for_each_new_intel_crtc_in_state(state, crtc,
+new_crtc_state, i) {
+
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ if (intel_crtc_can_enable_sagv(new_crtc_state))
+ new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
+ }
+
+ if (!old_bw_state)
+ return 0;
- return intel_crtc_can_enable_sagv(crtc_state);
+ if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
+ ret = intel_atomic_serialize_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
/*
@@
[Intel-gfx] [PATCH v22 09/13] drm/i915: Add TGL+ SAGV support
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/intel_pm.c | 127 +-
3 files changed, 129 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ac7f600c84ca..a591e35d9ac4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13932,7 +13932,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(_plane_wm->wm[level],
- _plane_wm->wm[level]))
+ _plane_wm->wm[level]) ||
+ (level == 0 &&
skl_wm_level_equals(_plane_wm->wm[level],
+
_plane_wm->sagv_wm0)))
continue;
drm_err(_priv->drm,
@@ -13987,7 +13989,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(_plane_wm->wm[level],
- _plane_wm->wm[level]))
+ _plane_wm->wm[level]) ||
+ (level == 0 &&
skl_wm_level_equals(_plane_wm->wm[level],
+
_plane_wm->sagv_wm0)))
continue;
drm_err(_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b437182c630a..37e13c98ac10 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -688,6 +688,8 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
@@ -698,6 +700,7 @@ enum color_plane {
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
+ bool can_sagv;
};
enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 026d48209cc9..dcc312670a94 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3875,6 +3875,9 @@ static bool icl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
return intel_crtc_can_enable_sagv(crtc_state);
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
return bw_state->pipe_sagv_reject == 0;
@@ -3885,7 +3888,7 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
@@ -3903,7 +3906,9 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 12)
+ can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
else
can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
@@ -3917,6 +3922,24 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
if (!old_bw_state)
return 0;
+ for_each_new_intel_crtc_in_state(state, crtc,
+new_crtc_state, i) {
+ struct skl_pipe_wm *pipe_wm = _crtc_state->wm.skl.optimal;
+
+ /*
+* Due to drm limitation at commit state, when
+* changes are written the whole atomic state is
+* zeroed away => which prevents from using it,
+* so just sticking it into pipe wm state for
+* keeping it simple - anyway this is related to wm.
+* Proper way in ideal universe would be of course not
+* to lose parent
[Intel-gfx] [PATCH v22 10/13] drm/i915: Added required new PCode commands
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
v3: - Moved new PCode masks to another place from
PCode commands(Ville)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_sideband.c | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b39b9abf8a4..a3cdb22826d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9085,6 +9085,7 @@ enum {
#define GEN7_PCODE_ILLEGAL_DATA0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -9106,6 +9107,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)(((point) <<
16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -9134,6 +9136,9 @@ enum {
#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
#define GEN8_LSLICESTAT_MASK 0x7
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
+
#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
#define CHV_SS_PG_ENABLE (1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 1447e7516cb7..1e7dd6b6f103 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -370,6 +370,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
--
2.24.1.485.gad05a3d8e5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v22 08/13] drm/i915: Separate icl and skl SAGV checking
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 71 ++---
1 file changed, 57 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 41305abad179..026d48209cc9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3761,8 +3761,23 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state = NULL;
- if (!intel_can_enable_sagv(state)) {
+ /*
+* Just return if we can't control SAGV or don't have it.
+* This is different from situation when we have SAGV but just can't
+* afford it due to DBuf limitation - in case if SAGV is completely
+* disabled in a BIOS, we are not even allowed to send a PCode request,
+* as it will throw an error. So have to check it here.
+*/
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (!intel_can_enable_sagv(new_bw_state)) {
intel_disable_sagv(dev_priv);
return;
}
@@ -3771,8 +3786,23 @@ void intel_sagv_pre_plane_update(struct
intel_atomic_state *state)
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state = NULL;
- if (intel_can_enable_sagv(state)) {
+ /*
+* Just return if we can't control SAGV or don't have it.
+* This is different from situation when we have SAGV but just can't
+* afford it due to DBuf limitation - in case if SAGV is completely
+* disabled in a BIOS, we are not even allowed to send a PCode request,
+* as it will throw an error. So have to check it here.
+*/
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (intel_can_enable_sagv(new_bw_state)) {
intel_enable_sagv(dev_priv);
return;
}
@@ -3780,7 +3810,6 @@ void intel_sagv_post_plane_update(struct
intel_atomic_state *state)
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
- struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane;
@@ -3790,13 +3819,6 @@ static bool intel_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state
if (!crtc_state->hw.active)
return true;
- /*
-* SKL+ workaround: bspec recommends we disable SAGV when we have
-* more then one pipe enabled
-*/
- if (hweight8(state->active_pipes) > 1)
- return false;
-
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
pipe_name(crtc->pipe));
@@ -3835,6 +3857,23 @@ static bool intel_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state
return true;
}
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
+ /*
+* SKL+ workaround: bspec recommends we disable SAGV when we have
+* more then one pipe enabled
+*/
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
+static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
@@ -3846,9 +3885,7 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *crtc_state;
- enum pipe pipe;
- struct intel_crtc_state *new_crtc_state;
+ const struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
@@ -3858,6 +3895,7 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
[Intel-gfx] [PATCH v22 06/13] drm/i915: Add pre/post plane updates for SAGV
Lets have a unified way to handle SAGV changes,
espoecially considering the upcoming Gen12 changes.
Current "standard" way of doing this in commit_tail
is pre/post plane updates, when everything which
has to be forbidden and not supported in new config
has to be restricted before update and relaxed after
plane update.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 13 -
drivers/gpu/drm/i915/intel_pm.c | 20
drivers/gpu/drm/i915/intel_pm.h | 2 ++
3 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 70ec301fe6e3..ac7f600c84ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15349,12 +15349,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_set_cdclk_pre_plane_update(state);
- /*
-* SKL workaround: bspec recommends we disable the SAGV when we
-* have more then one pipe enabled
-*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ intel_sagv_pre_plane_update(state);
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -15451,11 +15446,11 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_check_cpu_fifo_underruns(dev_priv);
intel_check_pch_fifo_underruns(dev_priv);
- if (state->modeset)
+ if (state->modeset) {
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ intel_sagv_post_plane_update(state);
+ }
drm_atomic_helper_commit_hw_done(>base);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 41af69ad3edc..d1df288396d8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3757,6 +3757,26 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ if (!intel_can_enable_sagv(state)) {
+ intel_disable_sagv(dev_priv);
+ return;
+ }
+}
+
+void intel_sagv_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ if (intel_can_enable_sagv(state)) {
+ intel_enable_sagv(dev_priv);
+ return;
+ }
+}
+
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..9a6036ab0f90 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct intel_atomic_state *state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
const struct skl_wm_level *l2);
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
--
2.24.1.485.gad05a3d8e5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v22 02/13] drm/i915: Eliminate magic numbers "0" and "1" from color plane
According to many computer science sources - magic values
in code _are_ _bad_. For many reasons: the reason is that "0"
or "1" or whatever magic values confuses and doesn't give any
info why this parameter is this value and what it's meaning
is.
I renamed "0" to COLOR_PLANE_Y and "1" to COLOR_PLANE_UV,
because we in fact already use this naming in many other places
and function names, when dealing with color planes.
v2: Removed long line to make checkpatch happy.
Signed-off-by: Stanislav Lisovskiy
---
.../drm/i915/display/intel_display_types.h| 5 +++
drivers/gpu/drm/i915/intel_pm.c | 42 ++-
2 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ba8c08145c88..b437182c630a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -691,6 +691,11 @@ struct skl_plane_wm {
bool is_planar;
};
+enum color_plane {
+ COLOR_PLANE_Y,
+ COLOR_PLANE_UV
+};
+
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b632b6bb9c3e..176a28d71822 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4013,7 +4013,7 @@ static int skl_compute_wm_params(const struct
intel_crtc_state *crtc_state,
int width, const struct drm_format_info
*format,
u64 modifier, unsigned int rotation,
u32 plane_pixel_rate, struct skl_wm_params *wp,
-int color_plane);
+enum color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
unsigned int latency,
@@ -4035,7 +4035,7 @@ skl_cursor_allocation(const struct intel_crtc_state
*crtc_state,
drm_format_info(DRM_FORMAT_ARGB),
DRM_FORMAT_MOD_LINEAR,
DRM_MODE_ROTATE_0,
- crtc_state->pixel_rate, , 0);
+ crtc_state->pixel_rate, , COLOR_PLANE_Y);
drm_WARN_ON(_priv->drm, ret);
for (level = 0; level <= max_level; level++) {
@@ -4431,7 +4431,7 @@ static u8 skl_compute_dbuf_slices(const struct
intel_crtc_state *crtc_state,
static u64
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
-int color_plane)
+enum color_plane color_plane)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -4446,7 +4446,7 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *crtc_state,
if (plane->id == PLANE_CURSOR)
return 0;
- if (color_plane == 1 &&
+ if (color_plane == COLOR_PLANE_UV &&
!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 0;
@@ -4459,7 +4459,7 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *crtc_state,
height = drm_rect_height(_state->uapi.src) >> 16;
/* UV plane does 1/2 pixel sub-sampling */
- if (color_plane == 1) {
+ if (color_plane == COLOR_PLANE_UV) {
width /= 2;
height /= 2;
}
@@ -4489,12 +4489,12 @@ skl_get_total_relative_data_rate(struct
intel_crtc_state *crtc_state,
u64 rate;
/* packed/y */
- rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
+ rate = skl_plane_relative_data_rate(crtc_state, plane_state,
COLOR_PLANE_Y);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
/* uv-plane */
- rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
+ rate = skl_plane_relative_data_rate(crtc_state, plane_state,
COLOR_PLANE_UV);
uv_plane_data_rate[plane_id] = rate;
total_data_rate += rate;
}
@@ -4516,7 +4516,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state
*crtc_state,
u64 rate;
if (!plane_state->planar_linked_plane) {
- rate = skl_plane_relative_data_rate(crtc_state,
plane_state, 0);
+ rate = skl_plane_relative_data_rate(crtc_state,
plane_state, COLOR_PLANE_Y);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
} else {
@@ -4533,12 +4533,14 @@
[Intel-gfx] [PATCH v22 05/13] drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv
Addressing one of the comments, recommending to extract platform
specific code from intel_can_enable_sagv as a preparation, before
we are going to add support for tgl+.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 67 +++--
1 file changed, 38 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 15ad6a73e0bd..41af69ad3edc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3757,42 +3757,25 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
- struct drm_device *dev = state->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane;
- struct intel_crtc_state *crtc_state;
- enum pipe pipe;
+ const struct intel_plane_state *plane_state;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
-
- /*
-* If there are no active CRTCs, no additional checks need be performed
-*/
- if (hweight8(state->active_pipes) == 0)
+ if (!crtc_state->hw.active)
return true;
- /*
-* SKL+ workaround: bspec recommends we disable SAGV when we have
-* more then one pipe enabled
-*/
- if (hweight8(state->active_pipes) > 1)
- return false;
-
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
-
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+ pipe_name(crtc->pipe));
return false;
+ }
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
- struct skl_plane_wm *wm =
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
crtc_state) {
+ const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane->id];
/* Skip this plane if it's not enabled */
@@ -3807,7 +3790,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
latency = dev_priv->wm.skl_latency[level];
if (skl_needs_memory_bw_wa(dev_priv) &&
- plane->base.state->fb->modifier ==
+ plane_state->uapi.fb->modifier ==
I915_FORMAT_MOD_X_TILED)
latency += 15;
@@ -3823,6 +3806,32 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
return true;
}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ const struct intel_crtc_state *crtc_state;
+ enum pipe pipe;
+
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
+ /*
+* SKL+ workaround: bspec recommends we disable SAGV when we have
+* more then one pipe enabled
+*/
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ /* Since we're now guaranteed to only have one active CRTC... */
+ pipe = ffs(state->active_pipes) - 1;
+ crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
/*
* Calculate initial DBuf slice offset, based on slice size
* and mask(i.e if slice size is 1024 and second slice is enabled
--
2.24.1.485.gad05a3d8e5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v22 04/13] drm/i915: Add intel_atomic_get_bw_*_state helpers
Add correspondent helpers to be able to get old/new bandwidth
global state object.
v2: - Fixed typo in function call
v3: - Changed new functions naming to use convention proposed
by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
v4: - Change function naming back to intel_atomic* pattern,
was decided to rename in a separate patch series.
v5: - Fix function naming to match existing practices(Ville)
v6: - Removed spurious whitespace
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 28 -
drivers/gpu/drm/i915/display/intel_bw.h | 9
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 88f367eb28ea..96f86cfa91d4 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -375,7 +375,33 @@ static unsigned int intel_bw_data_rate(struct
drm_i915_private *dev_priv,
return data_rate;
}
-static struct intel_bw_state *
+struct intel_bw_state *
+intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_old_global_obj_state(state,
_priv->bw_obj);
+ if (!bw_state)
+ return NULL;
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_new_global_obj_state(state,
_priv->bw_obj);
+ if (!bw_state)
+ return NULL;
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
intel_atomic_get_bw_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index a8aa7624c5aa..ac004d6f4276 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,15 @@ struct intel_bw_state {
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
+struct intel_bw_state *
+intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_bw_state(struct intel_atomic_state *state);
+
void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
--
2.24.1.485.gad05a3d8e5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v22 01/13] drm/i915: Start passing latency as parameter
We need to start passing memory latency as a
parameter when calculating plane wm levels,
as latency can get changed in different
circumstances(for example with or without SAGV).
So we need to be more flexible on that matter.
v2: Changed latency type from u32 to unsigned int(Ville Syrjälä)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8375054ba27d..b632b6bb9c3e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct
intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+unsigned int latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -4038,7 +4039,9 @@ skl_cursor_allocation(const struct intel_crtc_state
*crtc_state,
drm_WARN_ON(_priv->drm, ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, , , );
+ unsigned int latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, , , );
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4972,12 +4975,12 @@ static bool skl_wm_has_lines(struct drm_i915_private
*dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+unsigned int latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5106,9 +5109,10 @@ skl_compute_wm_levels(const struct intel_crtc_state
*crtc_state,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = [level];
+ unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
-result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+wm_params, result_prev, result);
result_prev = result;
}
--
2.24.1.485.gad05a3d8e5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v22 03/13] drm/i915: Introduce skl_plane_wm_level accessor.
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.
v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
(Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
skl_plane_wm_level
v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
- Changed colorplane id type from boolean to int as index
(Ville Syrjälä)
- Moved crtc_state param so that it is first now
(Ville Syrjälä)
- Moved wm_level declaration to tigher scope in
skl_write_plane_wm(Ville Syrjälä)
v4: - Started to use enum values for color plane
- Do sizeof for a type what we are memset'ing
- Zero out wm_uv as well(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 85 ++---
1 file changed, 67 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 176a28d71822..15ad6a73e0bd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4549,6 +4549,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state
*crtc_state,
return total_data_rate;
}
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
+ int level,
+ enum color_plane color_plane)
+{
+ const struct skl_plane_wm *wm =
+ _state->wm.skl.optimal.planes[plane_id];
+
+ return color_plane == COLOR_PLANE_Y ? >wm[level] :
>uv_wm[level];
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -4608,22 +4620,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
*crtc_state)
*/
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
+
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- _state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, COLOR_PLANE_Y);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+level, COLOR_PLANE_UV);
if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc >
total[PLANE_CURSOR]) {
+ if (wm_level->min_ddb_alloc >
total[PLANE_CURSOR]) {
drm_WARN_ON(_priv->drm,
- wm->wm[level].min_ddb_alloc
!= U16_MAX);
+ wm_level->min_ddb_alloc !=
U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
- blocks += wm->wm[level].min_ddb_alloc;
- blocks += wm->uv_wm[level].min_ddb_alloc;
+ blocks += wm_level->min_ddb_alloc;
+ blocks += wm_uv_level->min_ddb_alloc;
}
if (blocks <= alloc_size) {
@@ -4646,11 +4664,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
*crtc_state)
* proportional to its relative data rate.
*/
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- _state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, COLOR_PLANE_Y);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+level, COLOR_PLANE_UV);
+
if (plane_id == PLANE_CURSOR)
continue;
@@ -4665,7 +4688,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+
[Intel-gfx] [PATCH v22 00/13] SAGV support for Gen12+
For Gen11+ platforms BSpec suggests disabling specific QGV points separately, depending on bandwidth limitations and current display configuration. Thus it required adding a new PCode request for disabling QGV points and some refactoring of already existing SAGV code. Also had to refactor intel_can_enable_sagv function, as current seems to be outdated and using skl specific workarounds, also not following BSpec for Gen11+. Stanislav Lisovskiy (13): drm/i915: Start passing latency as parameter drm/i915: Eliminate magic numbers "0" and "1" from color plane drm/i915: Introduce skl_plane_wm_level accessor. drm/i915: Add intel_atomic_get_bw_*_state helpers drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv drm/i915: Add pre/post plane updates for SAGV drm/i915: Use bw state for per crtc SAGV evaluation drm/i915: Separate icl and skl SAGV checking drm/i915: Add TGL+ SAGV support drm/i915: Added required new PCode commands drm/i915: Rename bw_state to new_bw_state drm/i915: Restrict qgv points which don't have enough bandwidth. drm/i915: Enable SAGV support for Gen12 drivers/gpu/drm/i915/display/intel_bw.c | 191 +-- drivers/gpu/drm/i915/display/intel_bw.h | 24 + drivers/gpu/drm/i915/display/intel_display.c | 21 +- .../drm/i915/display/intel_display_types.h| 11 + drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_pm.c | 476 +++--- drivers/gpu/drm/i915/intel_pm.h | 8 +- drivers/gpu/drm/i915/intel_sideband.c | 2 + 8 files changed, 604 insertions(+), 134 deletions(-) -- 2.24.1.485.gad05a3d8e5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: remove redundant assignment to variable err
== Series Details == Series: drm/i915: remove redundant assignment to variable err URL : https://patchwork.freedesktop.org/series/75747/ State : success == Summary == CI Bug Log - changes from CI_DRM_8284 -> Patchwork_17269 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17269/index.html Known issues Here are the changes found in Patchwork_17269 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-skl-6770hq: [PASS][1] -> [DMESG-WARN][2] ([i915#203]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8284/fi-skl-6770hq/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17269/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][3] -> [FAIL][4] ([i915#579]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8284/fi-kbl-guc/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17269/fi-kbl-guc/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@hangcheck: - fi-bwr-2160:[PASS][5] -> [INCOMPLETE][6] ([i915#489]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8284/fi-bwr-2160/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17269/fi-bwr-2160/igt@i915_selftest@l...@hangcheck.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [PASS][7] -> [SKIP][8] ([fdo#109271]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8284/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17269/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-skl-6770hq: [PASS][9] -> [DMESG-WARN][10] ([i915#106]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8284/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17269/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-icl-dsi: [INCOMPLETE][11] ([i915#189]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8284/fi-icl-dsi/igt@i915_pm_...@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17269/fi-icl-dsi/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106 [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 Participating hosts (53 -> 46) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8284 -> Patchwork_17269 CI-20190529: 20190529 CI_DRM_8284: 307cf5040adae84648708ec34c64402dddff0171 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5586: 29fad328e6a1b105c8d688cafe19b1b5c19ad0c8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17269: 5fec0934d1a0f6e59d55b7cb2d591d19b0314711 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5fec0934d1a0 drm/i915: remove redundant assignment to variable err == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17269/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: remove gvt/Makefile
Including subdirectory Makefile from the driver main Makefile does not buy us much because this is not real isolation. Having a single Makefile at the top of the module is clearer, and it is what this driver almost does. Move all gvt objects to the i915 main Makefile. Signed-off-by: Masahiro Yamada --- drivers/gpu/drm/i915/Makefile | 28 drivers/gpu/drm/i915/gvt/Makefile | 8 2 files changed, 24 insertions(+), 12 deletions(-) delete mode 100644 drivers/gpu/drm/i915/gvt/Makefile diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 6cd1f6253814..74e965882a98 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -275,10 +275,30 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \ # virtual gpu code i915-y += i915_vgpu.o -ifeq ($(CONFIG_DRM_I915_GVT),y) -i915-y += intel_gvt.o -include $(src)/gvt/Makefile -endif +i915-$(CONFIG_DRM_I915_GVT) += \ + intel_gvt.o \ + gvt/gvt.o \ + gvt/aperture_gm.o \ + gvt/handlers.o \ + gvt/vgpu.o \ + gvt/trace_points.o \ + gvt/firmware.o \ + gvt/interrupt.o \ + gvt/gtt.o \ + gvt/cfg_space.o \ + gvt/opregion.o \ + gvt/mmio.o \ + gvt/display.o \ + gvt/edid.o \ + gvt/execlist.o \ + gvt/scheduler.o \ + gvt/sched_policy.o \ + gvt/mmio_context.o \ + gvt/cmd_parser.o \ + gvt/debugfs.o \ + gvt/fb_decoder.o \ + gvt/dmabuf.o \ + gvt/page_track.o obj-$(CONFIG_DRM_I915) += i915.o obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile deleted file mode 100644 index 4d70f4689479.. --- a/drivers/gpu/drm/i915/gvt/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -GVT_DIR := gvt -GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \ - interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \ - execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o debugfs.o \ - fb_decoder.o dmabuf.o page_track.o - -i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE)) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: remove unneeded ccflags-y from gvt/Makefile
When CONFIG_DRM_I915_GVT=y, the same include path is added twice. drivers/gpu/drm/i915/Makefile specifies: subdir-ccflags-y += -I$(srctree)/$(src) drivers/gpu/drm/i915/gvt/Makefile adds the second '-I $(srctree)/$(src)', which is redundant. The include path '-I $(srctree)/$(src)/$(GVT_DIR)/' is added to allow include/trace/define_trace.h to find the gvt/trace.h By setting the correct relative path to TRACE_INCLUDE_PATH, this -I is also unneeded. Signed-off-by: Masahiro Yamada --- drivers/gpu/drm/i915/gvt/Makefile | 1 - drivers/gpu/drm/i915/gvt/trace.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile index ea8324abc784..4d70f4689479 100644 --- a/drivers/gpu/drm/i915/gvt/Makefile +++ b/drivers/gpu/drm/i915/gvt/Makefile @@ -5,5 +5,4 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \ execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o debugfs.o \ fb_decoder.o dmabuf.o page_track.o -ccflags-y += -I $(srctree)/$(src) -I $(srctree)/$(src)/$(GVT_DIR)/ i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE)) diff --git a/drivers/gpu/drm/i915/gvt/trace.h b/drivers/gpu/drm/i915/gvt/trace.h index 6d787750d279..d63b7eef6179 100644 --- a/drivers/gpu/drm/i915/gvt/trace.h +++ b/drivers/gpu/drm/i915/gvt/trace.h @@ -377,7 +377,7 @@ TRACE_EVENT(render_mmio, /* This part must be out of protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915/gvt #undef TRACE_INCLUDE_FILE #define TRACE_INCLUDE_FILE trace #include -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for uC code cleanups
== Series Details == Series: uC code cleanups URL : https://patchwork.freedesktop.org/series/75719/ State : success == Summary == CI Bug Log - changes from CI_DRM_8281_full -> Patchwork_17262_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8281_full and Patchwork_17262_full: ### New IGT tests (2) ### * igt@gem_exec_store@cachelines: - Statuses : - Exec time: [None] s * igt@gem_exec_store@pages: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_17262_full that come from known issues: ### IGT changes ### Issues hit * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#716]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-glk8/igt@gen9_exec_pa...@allowed-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-glk2/igt@gen9_exec_pa...@allowed-all.html - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#716]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-kbl7/igt@gen9_exec_pa...@allowed-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-kbl1/igt@gen9_exec_pa...@allowed-all.html * igt@i915_module_load@reload-with-fault-injection: - shard-skl: [PASS][5] -> [TIMEOUT][6] ([i915#1418]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl1/igt@i915_module_l...@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-skl4/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_selftest@live@requests: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#1531] / [i915#1658]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-tglb2/igt@i915_selftest@l...@requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-tglb2/igt@i915_selftest@l...@requests.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#54] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-apl1/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-apl1/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109349]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-iclb4/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl1/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-skl4/igt@kms_f...@flip-vs-expired-vblank.html - shard-apl: [PASS][15] -> [FAIL][16] ([i915#79]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-apl8/igt@kms_f...@flip-vs-expired-vblank.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-apl8/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#46]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-skl1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl4/igt@kms_...@bpc-switch-dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-skl6/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-iclb2/igt@kms_psr@psr2_cursor_render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17262/shard-iclb1/igt@kms_psr@psr2_cursor_render.html Possible fixes * igt@gem_ctx_persistence@engines-mixed-process@vcs0: -
Re: [Intel-gfx] [RESEND PATCH] drm/i915: do AUD_FREQ_CNTRL state save on all gen9+ platforms
Hey, On Mon, 30 Mar 2020, Kai Vehmanen wrote: > Replace the TGL/ICL specific platform checks with a more generic check > using INTEL_GEN(). Fixes bug with broken audio after S3 resume on JSL > platforms. I would be (gently) beaten with a stick on alsa-devel for sending this type of content free ping, but I still dare to seek your input on what is the proper way to get attention to a patch that are seemingly forever stuck on the review sideline. I've sent this on 13.3., resend on 30.3.. Should I just keep on sending resends and let the system work (this is the alsa-devel practise), or should I start to contact potential reviewers with more direct asks? Tests seem to all pass and this is pretty important for anyone using JSL platforms (you lose HDMI/DP audio after first S3 suspend otherwise): https://patchwork.freedesktop.org/series/74664/ Br, Kai ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915/guc: drop guc parameter from guc_ggtt_offset
On 09.04.2020 02:56, Daniele Ceraolo Spurio wrote:
> We stopped using the parameter in commit dd18cedfa36f
> ("drm/i915/guc: Move the pin bias value from GuC to GGTT"),
> so we can safely remove it.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Matthew Brost
> Cc: Michal Wajdeczko
> Cc: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 6 +++---
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 +---
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 5 ++---
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_huc.c| 3 +--
> 6 files changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 861657897c0f..5134d544bf4c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -220,7 +220,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
> if (intel_guc_submission_is_used(guc)) {
> u32 ctxnum, base;
>
> - base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
> + base = intel_guc_ggtt_offset(guc->stage_desc_pool);
> ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
>
> base >>= PAGE_SHIFT;
> @@ -232,7 +232,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
>
> static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
> {
> - u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
> + u32 offset = intel_guc_ggtt_offset(guc->log.vma) >> PAGE_SHIFT;
> u32 flags;
>
> #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
> @@ -273,7 +273,7 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
>
> static u32 guc_ctl_ads_flags(struct intel_guc *guc)
> {
> - u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
> + u32 ads = intel_guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
> u32 flags = ads << GUC_ADS_ADDR_SHIFT;
>
> return flags;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index e84ab67b317d..366191204a7d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -103,7 +103,6 @@ static inline void intel_guc_to_host_event_handler(struct
> intel_guc *guc)
>
> /**
> * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
> - * @guc: intel_guc structure.
> * @vma: i915 graphics virtual memory area.
> *
> * GuC does not allow any gfx GGTT address that falls into range
> @@ -114,8 +113,7 @@ static inline void intel_guc_to_host_event_handler(struct
> intel_guc *guc)
> *
> * Return: GGTT offset of the @vma.
> */
> -static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
> - struct i915_vma *vma)
> +static inline u32 intel_guc_ggtt_offset(struct i915_vma *vma)
leaving this function with 'intel_guc' prefix without param guc would
break our naming schema, maybe we should rename it to:
static inline u32 i915_ggtt_offset_guc(struct i915_vma *vma)
as code inside init_ggtt() already understands guc specifics ...
> {
> u32 offset = i915_ggtt_offset(vma);
btw, we have here (not shown) in diff:
GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
that I would move to i915_ggtt_offset() as it quite generic
and replace it with something more GuC specific, like:
GEM_BUG_ON(offset < intel_wopcm_guc_size(wopcm))
Michal
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 101728006ae9..9237d798f7f4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -107,7 +107,7 @@ static void __guc_ads_init(struct intel_guc *guc)
> blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
> blob->system_info.vdbox_sfc_support_mask =
> RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
>
> - base = intel_guc_ggtt_offset(guc, guc->ads_vma);
> + base = intel_guc_ggtt_offset(guc->ads_vma);
>
> /* Clients info */
> guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index 11742fca0e9e..aad5ac54c1ba 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -187,7 +187,7 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
> return err;
> }
>
> - CT_DEBUG(ct, "vma base=%#x\n", intel_guc_ggtt_offset(guc, ct->vma));
> + CT_DEBUG(ct, "vma base=%#x\n", intel_guc_ggtt_offset(ct->vma));
>
> /* store pointers to desc and cmds */
> for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
> @@ -220,7 +220,6 @@ void intel_guc_ct_fini(struct
[Intel-gfx] ✓ Fi.CI.BAT: success for HAX timer: Describe the delayed_work for a freed timer (rev2)
== Series Details == Series: HAX timer: Describe the delayed_work for a freed timer (rev2) URL : https://patchwork.freedesktop.org/series/75740/ State : success == Summary == CI Bug Log - changes from CI_DRM_8283 -> Patchwork_17268 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17268/index.html Changes --- No changes found Participating hosts (52 -> 45) -- Additional (1): fi-skl-6770hq Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-tgl-y fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8283 -> Patchwork_17268 CI-20190529: 20190529 CI_DRM_8283: a6f4f55d343fea03e11e754b1094dda8cf2538ac @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5585: 13c0be2fe8669fef08c0d1c44b147c43d1f53d2b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17268: 05d26e5da5b73691ad6f673c43511085ba18fbeb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 05d26e5da5b7 HAX timer: Describe the delayed_work for a freed timer == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17268/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-next-fixes
Hi Dave, Daniel, Here's this week round of drm-misc-next-fixes Maxime drm-misc-next-fixes-2020-04-09: A few DMA-related fixes, an OOB fix for virtio and a probe-related fix for analogix_dp The following changes since commit 0e7e6198af28c1573267aba1be33dd0b7fb35691: Merge branch 'ttm-transhuge' of git://people.freedesktop.org/~thomash/linux into drm-next (2020-04-03 09:07:49 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2020-04-09 for you to fetch changes up to 152cce0006abf7e17dfb7dc94896b044bda4e588: drm/bridge: analogix_dp: Split bind() into probe() and real bind() (2020-04-09 10:29:35 +0200) A few DMA-related fixes, an OOB fix for virtio and a probe-related fix for analogix_dp Chris Wilson (1): drm/legacy: Fix type for drm_local_map.offset Jiri Slaby (1): drm/virtio: fix OOB in virtio_gpu_object_create Marek Szyprowski (2): drm/prime: fix extracting of the DMA addresses from a scatterlist drm/bridge: analogix_dp: Split bind() into probe() and real bind() Maxime Ripard (1): Merge drm/drm-next into drm-misc-next-fixes .../bindings/display/panel/panel-dpi.yaml | 10 -- .../bindings/display/ti/ti,am65x-dss.yaml | 4 +-- .../bindings/display/ti/ti,j721e-dss.yaml | 4 +-- .../devicetree/bindings/display/ti/ti,k2g-dss.yaml | 4 +-- drivers/dma-buf/Kconfig| 11 --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 33 --- drivers/gpu/drm/drm_mm.c | 8 + drivers/gpu/drm/drm_prime.c| 37 +++--- drivers/gpu/drm/exynos/exynos_dp.c | 29 ++--- drivers/gpu/drm/panel/panel-simple.c | 11 --- drivers/gpu/drm/rockchip/analogix_dp-rockchip.c| 36 +++-- drivers/gpu/drm/vboxvideo/vbox_drv.c | 4 +++ drivers/gpu/drm/vc4/vc4_hdmi.c | 20 +--- drivers/gpu/drm/virtio/virtgpu_object.c| 14 drivers/gpu/drm/xen/xen_drm_front.c| 2 +- drivers/video/fbdev/core/fbcon.c | 3 ++ include/drm/bridge/analogix_dp.h | 5 +-- include/drm/drm_legacy.h | 2 +- 18 files changed, 132 insertions(+), 105 deletions(-) signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v12 01/11] drm/i915: Use 64-bit division macro
Since the PWM framework is switching struct pwm_state.duty_cycle's datatype to u64, prepare for this transition by using DIV_ROUND_UP_ULL to handle a 64-bit dividend. Cc: Jani Nikula Cc: Joonas Lahtinen Cc: David Airlie Cc: Daniel Vetter Cc: Chris Wilson Cc: "Ville Syrjälä" Cc: intel-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Guru Das Srinagesh Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_panel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 7b3ec6eb..b45eabf 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -1877,7 +1877,7 @@ static int pwm_setup_backlight(struct intel_connector *connector, panel->backlight.min = 0; /* 0% */ panel->backlight.max = 100; /* 100% */ - panel->backlight.level = DIV_ROUND_UP( + panel->backlight.level = DIV_ROUND_UP_ULL( pwm_get_duty_cycle(panel->backlight.pwm) * 100, CRC_PMIC_PWM_PERIOD_NS); panel->backlight.enabled = panel->backlight.level != 0; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v3 2/2] tests/gem_userptr_blits: Refresh other still MMAP_GTT dependent subtests
Extend initial check for support of MMAP_GTT mapping to userptr with
equivalent checks for each MMAP_OFFSET mapping type supported by i915
driver. Based on that, extend coverage of process-exit-gtt* subtests
over non-GTT mapping types. In case of dmabuf-* subtests, use first
supported mapping type if there are any.
v2: Clear 'map' before reuse (Zbigniew).
v3: Kill out-of-context errno check (Chris).
Signed-off-by: Janusz Krzysztofik
Reviewed-by: Zbigniew Kempczyński
Cc: Chris Wilson
---
tests/i915/gem_userptr_blits.c | 111 -
1 file changed, 81 insertions(+), 30 deletions(-)
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index 975cd9dab..17f4d10f0 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -73,18 +73,31 @@
static uint32_t userptr_flags = LOCAL_I915_USERPTR_UNSYNCHRONIZED;
-static bool can_gtt_mmap;
+static bool *can_mmap;
#define WIDTH 512
#define HEIGHT 512
static uint32_t linear[WIDTH*HEIGHT];
-static bool has_gtt_mmap(int i915)
+static bool has_mmap(int i915, const struct mmap_offset *t)
{
- void *ptr, *map = NULL;
+ void *ptr, *map;
uint32_t handle;
+ handle = gem_create(i915, PAGE_SIZE);
+ map = __gem_mmap_offset(i915, handle, 0, PAGE_SIZE, PROT_WRITE,
+ t->type);
+ gem_close(i915, handle);
+ if (map) {
+ munmap(map, PAGE_SIZE);
+ } else {
+ igt_debug("no HW / kernel support for mmap-offset(%s)\n",
+ t->name);
+ return false;
+ }
+ map = NULL;
+
igt_assert(posix_memalign(, PAGE_SIZE, PAGE_SIZE) == 0);
if (__gem_userptr(i915, ptr, 4096, 0,
@@ -92,9 +105,12 @@ static bool has_gtt_mmap(int i915)
goto out_ptr;
igt_assert(handle != 0);
- map = __gem_mmap__gtt(i915, handle, 4096, PROT_WRITE);
+ map = __gem_mmap_offset(i915, handle, 0, 4096, PROT_WRITE, t->type);
if (map)
munmap(map, 4096);
+ else
+ igt_debug("mmap-offset(%s) banned, lockdep loop prevention\n",
+ t->name);
gem_close(i915, handle);
out_ptr:
@@ -642,20 +658,25 @@ static int test_invalid_mapping(int fd, const struct
mmap_offset *t)
return 0;
}
-#define PE_GTT_MAP 0x1
-#define PE_BUSY 0x2
-static void test_process_exit(int fd, int flags)
+#define PE_BUSY 0x1
+static void test_process_exit(int fd, const struct mmap_offset *mmo, int flags)
{
- if (flags & PE_GTT_MAP)
- igt_require(can_gtt_mmap);
+ if (mmo)
+ igt_require_f(can_mmap[mmo->type],
+ "HW & kernel support for LLC and mmap-offset(%s)
over userptr\n",
+ mmo->name);
igt_fork(child, 1) {
uint32_t handle;
handle = create_userptr_bo(fd, sizeof(linear));
- if (flags & PE_GTT_MAP) {
- uint32_t *ptr = __gem_mmap__gtt(fd, handle,
sizeof(linear), PROT_READ | PROT_WRITE);
+ if (mmo) {
+ uint32_t *ptr;
+
+ ptr = __gem_mmap_offset(fd, handle, 0, sizeof(linear),
+ PROT_READ | PROT_WRITE,
+ mmo->type);
if (ptr)
*ptr = 0;
}
@@ -933,13 +954,14 @@ static void (* volatile orig_sigbus)(int sig, siginfo_t
*info, void *param);
static volatile unsigned long sigbus_start;
static volatile long sigbus_cnt = -1;
-static void *umap(int fd, uint32_t handle)
+static void *umap(int fd, uint32_t handle, const struct mmap_offset *mmo)
{
void *ptr;
- if (can_gtt_mmap) {
- ptr = gem_mmap__gtt(fd, handle, sizeof(linear),
- PROT_READ | PROT_WRITE);
+ if (mmo) {
+ ptr = __gem_mmap_offset(fd, handle, 0, sizeof(linear),
+ PROT_READ | PROT_WRITE, mmo->type);
+ igt_assert(ptr);
} else {
uint32_t tmp = gem_create(fd, sizeof(linear));
igt_assert_eq(copy(fd, tmp, handle), 0);
@@ -951,16 +973,17 @@ static void *umap(int fd, uint32_t handle)
}
static void
-check_bo(int fd1, uint32_t handle1, int is_userptr, int fd2, uint32_t handle2)
+check_bo(int fd1, uint32_t handle1, int is_userptr, int fd2, uint32_t handle2,
+const struct mmap_offset *mmo)
{
unsigned char *ptr1, *ptr2;
unsigned long size = sizeof(linear);
- ptr2 = umap(fd2, handle2);
+ ptr2 = umap(fd2, handle2, mmo);
if (is_userptr)
ptr1 = is_userptr > 0 ? get_handle_ptr(handle1) : ptr2;
else
- ptr1 = umap(fd1, handle1);
+ ptr1 = umap(fd1, handle1, mmo);
[Intel-gfx] [PATCH i-g-t v3 0/2] tests/gem_userptr_blits: Refresh still MMAP_GTT dependent subtests
Refresh subtests which are still using pre-v4 MMAP_GTT API. v2: Patch 2/2: clear 'map' before reuse (Zbigniew). v3: Patch 2/2: kill out-of-context errno check (Chris). Janusz Krzysztofik (2): tests/gem_userptr_blits: Refresh readonly-mmap-unsync exercise tests/gem_userptr_blits: Refresh other still MMAP_GTT dependent subtests tests/i915/gem_userptr_blits.c | 132 - 1 file changed, 97 insertions(+), 35 deletions(-) -- 2.21.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/2] tests/gem_userptr_blits: Refresh readonly-mmap-unsync exercise
Upgrade the subtest to use MMAP_GTT API v4 (aka MMAP_OFFSET),
dynamically examine each mapping type supported by i915 driver.
Signed-off-by: Janusz Krzysztofik
Reviewed-by: Zbigniew Kempczyński
---
tests/i915/gem_userptr_blits.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index beced298a..975cd9dab 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -1277,7 +1277,7 @@ static void sigjmp_handler(int sig)
siglongjmp(sigjmp, sig);
}
-static void test_readonly_mmap(int i915)
+static void test_readonly_mmap(int i915, const struct mmap_offset *t)
{
char *original, *result;
uint32_t handle;
@@ -1294,6 +1294,14 @@ static void test_readonly_mmap(int i915)
* on the GPU as well.
*/
+ handle = gem_create(i915, PAGE_SIZE);
+ ptr = __gem_mmap_offset(i915, handle, 0, PAGE_SIZE,
+ PROT_READ | PROT_WRITE, t->type);
+ gem_close(i915, handle);
+ igt_require_f(ptr, "HW & kernel support for mmap-offset(%s)\n",
+ t->name);
+ munmap(ptr, PAGE_SIZE);
+
igt_require(igt_setup_clflush());
sz = 16 << 12;
@@ -1307,11 +1315,11 @@ static void test_readonly_mmap(int i915)
igt_clflush_range(pages, sz);
original = g_compute_checksum_for_data(G_CHECKSUM_SHA1, pages, sz);
- ptr = __gem_mmap__gtt(i915, handle, sz, PROT_WRITE);
+ ptr = __gem_mmap_offset(i915, handle, 0, sz, PROT_WRITE, t->type);
igt_assert(ptr == NULL);
/* Optional kernel support for GTT mmaps of userptr */
- ptr = __gem_mmap__gtt(i915, handle, sz, PROT_READ);
+ ptr = __gem_mmap_offset(i915, handle, 0, sz, PROT_READ, t->type);
gem_close(i915, handle);
if (ptr) { /* Check that a write into the GTT readonly map fails */
@@ -2110,8 +2118,11 @@ igt_main_args("c:", NULL, help_str, opt_handler, NULL)
igt_subtest("readonly-unsync")
test_readonly(fd);
- igt_subtest("readonly-mmap-unsync")
- test_readonly_mmap(fd);
+ igt_describe("Examine mmap-offset mapping to read-only
userptr");
+ igt_subtest_with_dynamic("readonly-mmap-unsync")
+ for_each_mmap_offset_type(fd, t)
+ igt_dynamic(t->name)
+ test_readonly_mmap(fd, t);
igt_subtest("readonly-pwrite-unsync")
test_readonly_pwrite(fd);
--
2.21.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/10] dma-buf: Report signaled links inside dma-fence-chain
Quoting Lionel Landwerlin (2020-04-09 12:16:48)
> On 09/04/2020 13:52, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2020-04-08 21:00:59)
> >> On 03/04/2020 12:12, Chris Wilson wrote:
> >>> Whenever we walk along the dma-fence-chain, we prune signaled links to
> >>> keep the chain nice and tidy. This leads to situations where we can
> >>> prune a link and report the earlier fence as the target seqno --
> >>> violating our own consistency checks that the seqno is not more advanced
> >>> than the last element in a dma-fence-chain.
> >>>
> >>> Report a NULL fence and success if the seqno has already been signaled.
> >>>
> >>> Signed-off-by: Chris Wilson
> >>> ---
> >>>drivers/dma-buf/dma-fence-chain.c | 7 +++
> >>>1 file changed, 7 insertions(+)
> >>>
> >>> diff --git a/drivers/dma-buf/dma-fence-chain.c
> >>> b/drivers/dma-buf/dma-fence-chain.c
> >>> index 3d123502ff12..c435bbba851c 100644
> >>> --- a/drivers/dma-buf/dma-fence-chain.c
> >>> +++ b/drivers/dma-buf/dma-fence-chain.c
> >>> @@ -99,6 +99,12 @@ int dma_fence_chain_find_seqno(struct dma_fence
> >>> **pfence, uint64_t seqno)
> >>>return -EINVAL;
> >>>
> >>>dma_fence_chain_for_each(*pfence, >base) {
> >>> + if ((*pfence)->seqno < seqno) { /* already signaled */
> >>> + dma_fence_put(*pfence);
> >>> + *pfence = NULL;
> >>> + break;
> >>> + }
> >>> +
> >>
> >> Wouldn't this condition been fulfilled in the previous check? :
> >>
> >>
> >> chain = to_dma_fence_chain(*pfence);
> >> if (!chain || chain->base.seqno < seqno)
> >> return -EINVAL;
> > The problem is in the chain iteration. It assumes that an unordered set
> > of fences is in the order of the user's seqno. There are no restrictions
> > placed on the chain, so we must apply the ordering from the timeline seqno
> > directly.
> > -Chris
>
>
> I don't really understand that. chain->seqno should be ordered because
> chain->prev_seqno <= chain->seqno.
>
> Do you have an example where this is not the case?
See the failing test case.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: remove redundant assignment to variable err
From: Colin Ian King
The variable err is being initialized with a value that is never read
and it is being updated later with a new value. The initialization is
redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
index 2b6db6f799de..faa5b6d91795 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
@@ -14,7 +14,7 @@ static int igt_gem_object(void *arg)
{
struct drm_i915_private *i915 = arg;
struct drm_i915_gem_object *obj;
- int err = -ENOMEM;
+ int err;
/* Basic test to ensure we can create an object */
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HAX timer: Describe the delayed_work for a freed timer (rev2)
== Series Details == Series: HAX timer: Describe the delayed_work for a freed timer (rev2) URL : https://patchwork.freedesktop.org/series/75740/ State : warning == Summary == $ dim checkpatch origin/drm-tip 05d26e5da5b7 HAX timer: Describe the delayed_work for a freed timer -:8: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #8: <3> [310.437368] ODEBUG: free active (active state 0) object type: timer_list hint: delayed_work_timer_fn+0x0/0x10 -:27: WARNING:LINE_SPACING: Missing a blank line after declarations #27: FILE: kernel/time/timer.c:609: + struct delayed_work *work = from_timer(work, timer, timer); + return work->work.func; total: 0 errors, 2 warnings, 0 checks, 15 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/guc: re-enable ARAT expired interrupt when using GuC
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: re-enable ARAT expired
interrupt when using GuC
URL : https://patchwork.freedesktop.org/series/75715/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8281_full -> Patchwork_17261_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17261_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_heartbeat_interval@mixed@bcs0}:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl4/igt@sysfs_heartbeat_interval@mi...@bcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-skl8/igt@sysfs_heartbeat_interval@mi...@bcs0.html
New tests
-
New tests have been introduced between CI_DRM_8281_full and
Patchwork_17261_full:
### New IGT tests (2) ###
* igt@gem_exec_store@cachelines:
- Statuses :
- Exec time: [None] s
* igt@gem_exec_store@pages:
- Statuses :
- Exec time: [None] s
Known issues
Here are the changes found in Patchwork_17261_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@legacy-engines-mixed-process@blt:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#1528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-apl2/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-apl1/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html
* igt@gem_exec_whisper@basic-queues-priority:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#1318])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl9/igt@gem_exec_whis...@basic-queues-priority.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-skl8/igt@gem_exec_whis...@basic-queues-priority.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#716])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-glk8/igt@gen9_exec_pa...@allowed-all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-glk4/igt@gen9_exec_pa...@allowed-all.html
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#716])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-kbl7/igt@gen9_exec_pa...@allowed-all.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-kbl1/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-skl: [PASS][11] -> [TIMEOUT][12] ([i915#1418])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl1/igt@i915_module_l...@reload-with-fault-injection.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-skl1/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#54] / [i915#95])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-apl1/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-apl7/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109349])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-iclb3/igt@kms_dp_...@basic-dsc-enable-edp.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-apl: [PASS][17] -> [FAIL][18] ([i915#79])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-apl2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-apl1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#34])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl3/igt@kms_f...@plain-flip-fb-recreate.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17261/shard-skl2/igt@kms_f...@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#49])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-pwrite.html
[22]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] dma-buf: Prettify typecasts for dma-fence-chain
== Series Details == Series: series starting with [1/3] dma-buf: Prettify typecasts for dma-fence-chain URL : https://patchwork.freedesktop.org/series/75743/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8283 -> Patchwork_17267 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17267 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17267, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17267/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17267: ### IGT changes ### Possible regressions * igt@i915_selftest@live@execlists: - fi-icl-y: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8283/fi-icl-y/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17267/fi-icl-y/igt@i915_selftest@l...@execlists.html New tests - New tests have been introduced between CI_DRM_8283 and Patchwork_17267: ### New IGT tests (1) ### * igt@dmabuf@all@dma_fence_chain: - Statuses : 43 pass(s) - Exec time: [7.47, 31.83] s Known issues Here are the changes found in Patchwork_17267 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@requests: - fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#1531] / [i915#1581]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8283/fi-icl-dsi/igt@i915_selftest@l...@requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17267/fi-icl-dsi/igt@i915_selftest@l...@requests.html [i915#1531]: https://gitlab.freedesktop.org/drm/intel/issues/1531 [i915#1581]: https://gitlab.freedesktop.org/drm/intel/issues/1581 Participating hosts (52 -> 46) -- Additional (1): fi-skl-6770hq Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8283 -> Patchwork_17267 CI-20190529: 20190529 CI_DRM_8283: a6f4f55d343fea03e11e754b1094dda8cf2538ac @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5585: 13c0be2fe8669fef08c0d1c44b147c43d1f53d2b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17267: 9118ea143e62d62cfa3d9e4a254b40dddcec845b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9118ea143e62 dma-buf: Exercise dma-fence-chain under selftests 38f765418273 dma-buf: Report signaled links inside dma-fence-chain 5fe27cc9dd40 dma-buf: Prettify typecasts for dma-fence-chain == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17267/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v13] tests: Add a test for device hot unplug
From: Janusz Krzysztofik There is a test which verifies unloading of i915 driver module but no test exists that checks how a driver behaves when it gets unbound from a device or when the device gets unplugged. Implement such test using sysfs interface. Two minimalistic subtests - "unbind-rebind" and "unplug-rescan" - perform the named operations on a DRM device which is believed to be not in use. Another pair of subtests named "hotunbind-lateclose" and hotunplug-lateclose" do the same on a DRM device while keeping its file descriptor open and close it thereafter. v2: Run a subprocess with dummy_load instead of external command (Antonio). v3: Run dummy_load from the test process directly (Antonio). v4: Run dummy_load from inside subtests (Antonio). v5: Try to restore the device to a working state after each subtest (Petri, Daniel). v6: Run workload inside an igt helper subprocess so resources consumed by the workload are cleaned up automatically on workload subprocess crash, without affecting test results, - move the igt helper with workload back from subtests to initial fixture so workload crash also does not affect test results, - other cleanups suggested by Katarzyna and Chris. v7: No changes. v8: Move workload functions back from fixture to subtests, - register different actions and different workloads in respective tables and iterate over those tables while enumerating subtests, - introduce new subtest flavors by simply omitting module unload step, - instead of simply requesting bus rescan or not, introduce action specific device recovery helpers, required specifically with those new subtests not touching the module, - split workload functions in two parts, one spawning the workload, the other waiting for its completion, - for the new subtests not requiring module unload, run workload functions directly from the test process and use new workload completion wait functions in place of subprocess completion wait, - take more control over logging, longjumps and exit codes in workload subprocesses, - add some debug messages for easy progress watching, - move function API descriptions on top of respective typedefs. v9: All changes after Daniel's comments - thanks! - flatten the code, don't try to create a midlayer (Daniel), - provide minimal subtests that even don't keep device open (Daniel), - don't use driver unbind in more advanced subtests (Daniel), - provide subtests with different level of resources allocated during device unplug (Daniel), - provide subtests which check driver behavior after device hot unplug (Daniel). v10 Rename variables and function arguments to something that indicates they're file descriptors (Daniel), - introduce a data structure that contains various file descriptors and a helper function to set them all (Daniel), - fix strange indentation (Daniel), - limit scope to first three subtests as the initial set of tests to merge (Daniel). v11 Fix typos in some comments, - use SPDX license identifier, - include a per-patch changelog in the commit message (Daniel). v12 We don't use SPDX license identifiers nor GPL-2.0 in IGT (Petri), - avoid chipset, make sure we reopen the same device (Chris), - rename subtest "drm_open-hotunplug" to "hotunplug-lateclose", - add subtest "hotunbind-lateclose" (less affected by IOMMU issues), - move some redundant code to helpers, - reorder some helpers, - reword some messages and comments, - clean up headers. v13 Add test / subtest descriptions (patchwork). Signed-off-by: Janusz Krzysztofik Cc: Antonio Argenziano Cc: Petri Latvala Cc: Daniel Vetter Cc: Katarzyna Dec Acked-by: Chris Wilson --- tests/Makefile.sources | 1 + tests/core_hotunplug.c | 282 + tests/meson.build | 1 + 3 files changed, 284 insertions(+) create mode 100644 tests/core_hotunplug.c diff --git a/tests/Makefile.sources b/tests/Makefile.sources index 4e44c98c2..32cbbf4f9 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -18,6 +18,7 @@ TESTS_progs = \ core_getclient \ core_getstats \ core_getversion \ + core_hotunplug \ core_setmaster \ core_setmaster_vs_auth \ debugfs_test \ diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c new file mode 100644 index 0..6705e0199 --- /dev/null +++ b/tests/core_hotunplug.c @@ -0,0 +1,282 @@ +/* + * Copyright © 2019 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v5,1/4] drm/i915/perf: break OA config buffer object in 2
== Series Details == Series: series starting with [v5,1/4] drm/i915/perf: break OA config buffer object in 2 URL : https://patchwork.freedesktop.org/series/75741/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8283 -> Patchwork_17266 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17266 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17266, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17266/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17266: ### IGT changes ### Possible regressions * igt@i915_selftest@live@perf: - fi-hsw-4770:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8283/fi-hsw-4770/igt@i915_selftest@l...@perf.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17266/fi-hsw-4770/igt@i915_selftest@l...@perf.html - fi-hsw-peppy: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8283/fi-hsw-peppy/igt@i915_selftest@l...@perf.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17266/fi-hsw-peppy/igt@i915_selftest@l...@perf.html * igt@kms_flip@basic-flip-vs-modeset: - fi-skl-lmem:[PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8283/fi-skl-lmem/igt@kms_f...@basic-flip-vs-modeset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17266/fi-skl-lmem/igt@kms_f...@basic-flip-vs-modeset.html Known issues Here are the changes found in Patchwork_17266 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@hangcheck: - fi-icl-y: [PASS][7] -> [INCOMPLETE][8] ([i915#1580]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8283/fi-icl-y/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17266/fi-icl-y/igt@i915_selftest@l...@hangcheck.html [i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580 Participating hosts (52 -> 46) -- Additional (1): fi-skl-6770hq Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8283 -> Patchwork_17266 CI-20190529: 20190529 CI_DRM_8283: a6f4f55d343fea03e11e754b1094dda8cf2538ac @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5585: 13c0be2fe8669fef08c0d1c44b147c43d1f53d2b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17266: 83a8d4534edeb24530274e72d90fc293c9439e13 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 83a8d4534ede drm/i915/perf: enable filtering on multiple contexts 8a7d87df6de1 drm/i915/perf: prepare driver to receive multiple ctx handles ef7148882b7e drm/i915/perf: stop using the kernel context 579ee6f9f229 drm/i915/perf: break OA config buffer object in 2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17266/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] dma-buf: Prettify typecasts for dma-fence-chain
== Series Details ==
Series: series starting with [1/3] dma-buf: Prettify typecasts for
dma-fence-chain
URL : https://patchwork.freedesktop.org/series/75743/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5fe27cc9dd40 dma-buf: Prettify typecasts for dma-fence-chain
38f765418273 dma-buf: Report signaled links inside dma-fence-chain
9118ea143e62 dma-buf: Exercise dma-fence-chain under selftests
-:34: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#34:
new file mode 100644
-:62: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#62: FILE: drivers/dma-buf/st-dma-fence-chain.c:24:
+ spinlock_t lock;
-:236: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#236: FILE: drivers/dma-buf/st-dma-fence-chain.c:198:
+ pr_err("Reported %d for find_seqno(0)!\n", err);
-:245: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#245: FILE: drivers/dma-buf/st-dma-fence-chain.c:207:
+ pr_err("Reported %d for find_seqno(%d:%d)!\n",
-:250: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#250: FILE: drivers/dma-buf/st-dma-fence-chain.c:212:
+ pr_err("Incorrect fence reported by
find_seqno(%d:%d)\n",
-:273: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#273: FILE: drivers/dma-buf/st-dma-fence-chain.c:235:
+ pr_err("Error not reported for future fence:
find_seqno(%d:%d)!\n",
-:287: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#287: FILE: drivers/dma-buf/st-dma-fence-chain.c:249:
+ pr_err("Incorrect fence reported by
find_seqno(%d:%d)\n",
-:738: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'dma_fence_chain', this function's name, in a string
#738: FILE: drivers/dma-buf/st-dma-fence-chain.c:700:
+ pr_info("sizeof(dma_fence_chain)=%zu\n",
total: 0 errors, 7 warnings, 1 checks, 725 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] HAX timer: Describe the delayed_work for a freed timer
Improve upon the
<3> [310.437368] ODEBUG: free active (active state 0) object type: timer_list
hint: delayed_work_timer_fn+0x0/0x10
by describing what delayed_work was queued instead.
Signed-off-by: Chris Wilson
---
kernel/time/timer.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/kernel/time/timer.c b/kernel/time/timer.c
index 4820823515e9..262eea5abb86 100644
--- a/kernel/time/timer.c
+++ b/kernel/time/timer.c
@@ -602,7 +602,14 @@ static struct debug_obj_descr timer_debug_descr;
static void *timer_debug_hint(void *addr)
{
- return ((struct timer_list *) addr)->function;
+ struct timer_list *timer = addr;
+
+ if (timer->function == delayed_work_timer_fn) {
+ struct delayed_work *work = from_timer(work, timer, timer);
+ return work->work.func;
+ }
+
+ return timer->function;
}
static bool timer_is_static_object(void *addr)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for HAX timer: Describe the delayed_work for a freed timer
== Series Details ==
Series: HAX timer: Describe the delayed_work for a freed timer
URL : https://patchwork.freedesktop.org/series/75740/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC kernel/time/timer.o
kernel/time/timer.c: In function ‘timer_debug_hint’:
kernel/time/timer.c:607:10: warning: dereferencing ‘void *’ pointer
if (addr->function == delayed_work_timer_fn) {
^~
kernel/time/timer.c:607:10: error: request for member ‘function’ in something
not a structure or union
scripts/Makefile.build:267: recipe for target 'kernel/time/timer.o' failed
make[2]: *** [kernel/time/timer.o] Error 1
scripts/Makefile.build:505: recipe for target 'kernel/time' failed
make[1]: *** [kernel/time] Error 2
Makefile:1683: recipe for target 'kernel' failed
make: *** [kernel] Error 2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/10] dma-buf: Report signaled links inside dma-fence-chain
On 09/04/2020 13:52, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-08 21:00:59)
On 03/04/2020 12:12, Chris Wilson wrote:
Whenever we walk along the dma-fence-chain, we prune signaled links to
keep the chain nice and tidy. This leads to situations where we can
prune a link and report the earlier fence as the target seqno --
violating our own consistency checks that the seqno is not more advanced
than the last element in a dma-fence-chain.
Report a NULL fence and success if the seqno has already been signaled.
Signed-off-by: Chris Wilson
---
drivers/dma-buf/dma-fence-chain.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-chain.c
b/drivers/dma-buf/dma-fence-chain.c
index 3d123502ff12..c435bbba851c 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -99,6 +99,12 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence,
uint64_t seqno)
return -EINVAL;
dma_fence_chain_for_each(*pfence, >base) {
+ if ((*pfence)->seqno < seqno) { /* already signaled */
+ dma_fence_put(*pfence);
+ *pfence = NULL;
+ break;
+ }
+
Wouldn't this condition been fulfilled in the previous check? :
chain = to_dma_fence_chain(*pfence);
if (!chain || chain->base.seqno < seqno)
return -EINVAL;
The problem is in the chain iteration. It assumes that an unordered set
of fences is in the order of the user's seqno. There are no restrictions
placed on the chain, so we must apply the ordering from the timeline seqno
directly.
-Chris
I don't really understand that. chain->seqno should be ordered because
chain->prev_seqno <= chain->seqno.
Do you have an example where this is not the case?
-Lionel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] dma-buf: Report signaled links inside dma-fence-chain
Whenever we walk along the dma-fence-chain, we prune signaled links to
keep the chain nice and tidy. This leads to situations where we can
prune a link and report the earlier fence as the target seqno --
violating our own consistency checks that the seqno is not more advanced
than the last element in a dma-fence-chain.
Report a NULL fence and success if the seqno has already been signaled.
Signed-off-by: Chris Wilson
Tested-by: Venkata Sandeep Dhanalakota
Reviewed-by: Venkata Sandeep Dhanalakota
---
drivers/dma-buf/dma-fence-chain.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-chain.c
b/drivers/dma-buf/dma-fence-chain.c
index 3d123502ff12..c435bbba851c 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -99,6 +99,12 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence,
uint64_t seqno)
return -EINVAL;
dma_fence_chain_for_each(*pfence, >base) {
+ if ((*pfence)->seqno < seqno) { /* already signaled */
+ dma_fence_put(*pfence);
+ *pfence = NULL;
+ break;
+ }
+
if ((*pfence)->context != chain->base.context ||
to_dma_fence_chain(*pfence)->prev_seqno < seqno)
break;
@@ -222,6 +228,7 @@ EXPORT_SYMBOL(dma_fence_chain_ops);
* @chain: the chain node to initialize
* @prev: the previous fence
* @fence: the current fence
+ * @seqno: the sequence number (syncpt) of the fence within the chain
*
* Initialize a new chain node and either start a new chain or add the node to
* the existing chain of the previous fence.
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] dma-buf: Exercise dma-fence-chain under selftests
A few very simple testcases to exercise the dma-fence-chain API.
Signed-off-by: Chris Wilson
Reviewed-by: Venkata Sandeep Dhanalakota
---
drivers/dma-buf/Makefile | 3 +-
drivers/dma-buf/selftests.h | 1 +
drivers/dma-buf/st-dma-fence-chain.c | 713 +++
3 files changed, 716 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma-buf/st-dma-fence-chain.c
diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 9c190026bfab..995e05f609ff 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_UDMABUF) += udmabuf.o
dmabuf_selftests-y := \
selftest.o \
- st-dma-fence.o
+ st-dma-fence.o \
+ st-dma-fence-chain.o
obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o
diff --git a/drivers/dma-buf/selftests.h b/drivers/dma-buf/selftests.h
index 5320386f02e5..55918ef9adab 100644
--- a/drivers/dma-buf/selftests.h
+++ b/drivers/dma-buf/selftests.h
@@ -11,3 +11,4 @@
*/
selftest(sanitycheck, __sanitycheck__) /* keep first (igt selfcheck) */
selftest(dma_fence, dma_fence)
+selftest(dma_fence_chain, dma_fence_chain)
diff --git a/drivers/dma-buf/st-dma-fence-chain.c
b/drivers/dma-buf/st-dma-fence-chain.c
new file mode 100644
index ..bd08ba67b03b
--- /dev/null
+++ b/drivers/dma-buf/st-dma-fence-chain.c
@@ -0,0 +1,713 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "selftest.h"
+
+static struct kmem_cache *slab_fences;
+
+static inline struct mock_fence {
+ struct dma_fence base;
+ spinlock_t lock;
+} *to_mock_fence(struct dma_fence *f) {
+ return container_of(f, struct mock_fence, base);
+}
+
+static const char *mock_name(struct dma_fence *f)
+{
+ return "mock";
+}
+
+static void mock_fence_release(struct dma_fence *f)
+{
+ kmem_cache_free(slab_fences, to_mock_fence(f));
+}
+
+static const struct dma_fence_ops mock_ops = {
+ .get_driver_name = mock_name,
+ .get_timeline_name = mock_name,
+ .release = mock_fence_release,
+};
+
+static struct dma_fence *mock_fence(void)
+{
+ struct mock_fence *f;
+
+ f = kmem_cache_alloc(slab_fences, GFP_KERNEL);
+ if (!f)
+ return NULL;
+
+ spin_lock_init(>lock);
+ dma_fence_init(>base, _ops, >lock, 0, 0);
+
+ return >base;
+}
+
+static inline struct mock_chain {
+ struct dma_fence_chain base;
+} *to_mock_chain(struct dma_fence *f) {
+ return container_of(f, struct mock_chain, base.base);
+}
+
+static struct dma_fence *mock_chain(struct dma_fence *prev,
+ struct dma_fence *fence,
+ u64 seqno)
+{
+ struct mock_chain *f;
+
+ f = kmalloc(sizeof(*f), GFP_KERNEL);
+ if (!f)
+ return NULL;
+
+ dma_fence_chain_init(>base,
+dma_fence_get(prev),
+dma_fence_get(fence),
+seqno);
+
+ return >base.base;
+}
+
+static int sanitycheck(void *arg)
+{
+ struct dma_fence *f, *chain;
+ int err = 0;
+
+ f = mock_fence();
+ if (!f)
+ return -ENOMEM;
+
+ chain = mock_chain(NULL, f, 1);
+ if (!chain)
+ err = -ENOMEM;
+
+ dma_fence_signal(f);
+ dma_fence_put(f);
+
+ dma_fence_put(chain);
+
+ return err;
+}
+
+struct fence_chains {
+ unsigned int chain_length;
+ struct dma_fence **fences;
+ struct dma_fence **chains;
+
+ struct dma_fence *tail;
+};
+
+static uint64_t seqno_inc(unsigned int i)
+{
+ return i + 1;
+}
+
+static int fence_chains_init(struct fence_chains *fc, unsigned int count,
+uint64_t (*seqno_fn)(unsigned int))
+{
+ unsigned int i;
+ int err = 0;
+
+ fc->chains = kvmalloc_array(count, sizeof(*fc->chains),
+ GFP_KERNEL | __GFP_ZERO);
+ if (!fc->chains)
+ return -ENOMEM;
+
+ fc->fences = kvmalloc_array(count, sizeof(*fc->fences),
+ GFP_KERNEL | __GFP_ZERO);
+ if (!fc->fences) {
+ err = -ENOMEM;
+ goto err_chains;
+ }
+
+ fc->tail = NULL;
+ for (i = 0; i < count; i++) {
+ fc->fences[i] = mock_fence();
+ if (!fc->fences[i]) {
+ err = -ENOMEM;
+ goto unwind;
+ }
+
+ fc->chains[i] = mock_chain(fc->tail,
+ fc->fences[i],
+ seqno_fn(i));
+ if (!fc->chains[i]) {
+ err = -ENOMEM;
+ goto unwind;
+ }
+
+ fc->tail =
[Intel-gfx] [PATCH 1/3] dma-buf: Prettify typecasts for dma-fence-chain
Inside dma-fence-chain, we use a cmpxchg on an RCU-protected pointer. To avoid the sparse warning for using the RCU pointer directly, we have to cast away the __rcu annotation. However, we don't need to use void* everywhere and can stick to the dma_fence*. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/dma-buf/dma-fence-chain.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c index 44a741677d25..3d123502ff12 100644 --- a/drivers/dma-buf/dma-fence-chain.c +++ b/drivers/dma-buf/dma-fence-chain.c @@ -62,7 +62,8 @@ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence) replacement = NULL; } - tmp = cmpxchg((void **)>prev, (void *)prev, (void *)replacement); + tmp = cmpxchg((struct dma_fence __force **)>prev, + prev, replacement); if (tmp == prev) dma_fence_put(tmp); else -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/10] dma-buf: Report signaled links inside dma-fence-chain
Quoting Lionel Landwerlin (2020-04-08 21:00:59)
> On 03/04/2020 12:12, Chris Wilson wrote:
> > Whenever we walk along the dma-fence-chain, we prune signaled links to
> > keep the chain nice and tidy. This leads to situations where we can
> > prune a link and report the earlier fence as the target seqno --
> > violating our own consistency checks that the seqno is not more advanced
> > than the last element in a dma-fence-chain.
> >
> > Report a NULL fence and success if the seqno has already been signaled.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/dma-buf/dma-fence-chain.c | 7 +++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/dma-buf/dma-fence-chain.c
> > b/drivers/dma-buf/dma-fence-chain.c
> > index 3d123502ff12..c435bbba851c 100644
> > --- a/drivers/dma-buf/dma-fence-chain.c
> > +++ b/drivers/dma-buf/dma-fence-chain.c
> > @@ -99,6 +99,12 @@ int dma_fence_chain_find_seqno(struct dma_fence
> > **pfence, uint64_t seqno)
> > return -EINVAL;
> >
> > dma_fence_chain_for_each(*pfence, >base) {
> > + if ((*pfence)->seqno < seqno) { /* already signaled */
> > + dma_fence_put(*pfence);
> > + *pfence = NULL;
> > + break;
> > + }
> > +
>
>
> Wouldn't this condition been fulfilled in the previous check? :
>
>
> chain = to_dma_fence_chain(*pfence);
> if (!chain || chain->base.seqno < seqno)
> return -EINVAL;
The problem is in the chain iteration. It assumes that an unordered set
of fences is in the order of the user's seqno. There are no restrictions
placed on the chain, so we must apply the ordering from the timeline seqno
directly.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 1/4] drm/i915/perf: break OA config buffer object in 2
We want to enable performance monitoring on multiple contexts to cover
the Iris use case of using 2 GEM contexts (3D & compute).
So start by breaking the OA configuration BO which contains global &
per context register writes.
NOA muxes & OA configurations are global, while FLEXEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 176 ---
1 file changed, 116 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5cde3e4e7be6..d2183fd701a3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -372,6 +372,7 @@ struct i915_oa_config_bo {
struct i915_oa_config *oa_config;
struct i915_vma *vma;
+ u32 per_context_offset;
};
static struct ctl_table_header *sysctl_header;
@@ -1826,37 +1827,43 @@ static struct i915_oa_config_bo *
alloc_oa_config_buffer(struct i915_perf_stream *stream,
struct i915_oa_config *oa_config)
{
- struct drm_i915_gem_object *obj;
struct i915_oa_config_bo *oa_bo;
+ struct drm_i915_gem_object *obj;
size_t config_length = 0;
- u32 *cs;
+ u32 *cs_start, *cs;
int err;
oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
if (!oa_bo)
return ERR_PTR(-ENOMEM);
+ /*
+* Global configuration requires a jump into the NOA wait BO for it to
+* apply.
+*/
config_length += num_lri_dwords(oa_config->mux_regs_len);
config_length += num_lri_dwords(oa_config->b_counter_regs_len);
- config_length += num_lri_dwords(oa_config->flex_regs_len);
config_length += 3; /* MI_BATCH_BUFFER_START */
+
+ config_length += num_lri_dwords(oa_config->flex_regs_len);
+ config_length += 1 /* MI_BATCH_BUFFER_END */;
+
config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
- obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
+ obj = i915_gem_object_create_shmem(stream->perf->i915,
+ config_length);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
goto err_free;
}
- cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
- if (IS_ERR(cs)) {
- err = PTR_ERR(cs);
- goto err_oa_bo;
+ cs_start = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs_start)) {
+ err = PTR_ERR(cs_start);
+ goto err_bo;
}
- cs = write_cs_mi_lri(cs,
-oa_config->mux_regs,
-oa_config->mux_regs_len);
+ cs = cs_start;
cs = write_cs_mi_lri(cs,
oa_config->b_counter_regs,
oa_config->b_counter_regs_len);
@@ -1871,6 +1878,14 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
*cs++ = i915_ggtt_offset(stream->noa_wait);
*cs++ = 0;
+ oa_bo->per_context_offset = 4 * (cs - cs_start);
+
+ cs = write_cs_mi_lri(cs,
+oa_config->mux_regs,
+oa_config->mux_regs_len);
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
i915_gem_object_flush_map(obj);
i915_gem_object_unpin_map(obj);
@@ -1879,7 +1894,7 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
NULL);
if (IS_ERR(oa_bo->vma)) {
err = PTR_ERR(oa_bo->vma);
- goto err_oa_bo;
+ goto err_bo;
}
oa_bo->oa_config = i915_oa_config_get(oa_config);
@@ -1887,15 +1902,15 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
return oa_bo;
-err_oa_bo:
+err_bo:
i915_gem_object_put(obj);
err_free:
kfree(oa_bo);
return ERR_PTR(err);
}
-static struct i915_vma *
-get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
+static struct i915_oa_config_bo *
+get_oa_bo(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
{
struct i915_oa_config_bo *oa_bo;
@@ -1908,34 +1923,31 @@ get_oa_vma(struct i915_perf_stream *stream, struct
i915_oa_config *oa_config)
memcmp(oa_bo->oa_config->uuid,
oa_config->uuid,
sizeof(oa_config->uuid)) == 0)
- goto out;
+ return oa_bo;
}
- oa_bo = alloc_oa_config_buffer(stream, oa_config);
- if (IS_ERR(oa_bo))
- return ERR_CAST(oa_bo);
-
-out:
- return i915_vma_get(oa_bo->vma);
+ return alloc_oa_config_buffer(stream, oa_config);
}
static int
emit_oa_config(struct i915_perf_stream *stream,
struct i915_oa_config *oa_config,
struct
[Intel-gfx] [PATCH v5 4/4] drm/i915/perf: enable filtering on multiple contexts
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58 ++--
include/uapi/drm/i915_drm.h | 21
2 files changed, 76 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 543d29cd5c14..546bea945ddd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3687,7 +3687,8 @@ static int read_properties_unlocked(struct i915_perf
*perf,
struct perf_open_properties *props)
{
u64 __user *uprop = uprops;
- u32 i;
+ u32 __user *uctx_handles = NULL;
+ u32 i, n_uctx_handles = 0;
int err;
memset(props, 0, sizeof(struct perf_open_properties));
@@ -3738,7 +3739,7 @@ static int read_properties_unlocked(struct i915_perf
*perf,
switch ((enum drm_i915_perf_property_id)id) {
case DRM_I915_PERF_PROP_CTX_HANDLE:
- if (props->n_ctx_handles > 0) {
+ if (props->n_ctx_handles > 0 || n_uctx_handles > 0) {
DRM_DEBUG("Context handle specified multiple
times\n");
err = -EINVAL;
goto error;
@@ -3852,6 +3853,38 @@ static int read_properties_unlocked(struct i915_perf
*perf,
}
props->poll_oa_period = value;
break;
+ case DRM_I915_PERF_PROP_CTX_HANDLE_ARRAY:
+ /* HSW can only filter in HW and only on a single
+* context.
+*/
+ if (IS_HASWELL(perf->i915)) {
+ DRM_DEBUG("Multi context filter not supported
on HSW\n");
+ err = -ENODEV;
+ goto error;
+ }
+ uctx_handles = u64_to_user_ptr(value);
+ break;
+ case DRM_I915_PERF_PROP_CTX_HANDLE_ARRAY_LENGTH:
+ if (IS_HASWELL(perf->i915)) {
+ DRM_DEBUG("Multi context filter not supported
on HSW\n");
+ err = -ENODEV;
+ goto error;
+ }
+ if (props->n_ctx_handles > 0 || n_uctx_handles > 0) {
+ DRM_DEBUG("Context handle specified multiple
times\n");
+ err = -EINVAL;
+ goto error;
+ }
+ props->ctx_handles =
+ kmalloc_array(value,
+ sizeof(*props->ctx_handles),
+ GFP_KERNEL);
+ if (!props->ctx_handles) {
+ err = -ENOMEM;
+ goto error;
+ }
+ n_uctx_handles = value;
+ break;
case DRM_I915_PERF_PROP_MAX:
MISSING_CASE(id);
err = -EINVAL;
@@ -3861,6 +3894,21 @@ static int read_properties_unlocked(struct i915_perf
*perf,
uprop += 2;
}
+ if (n_uctx_handles > 0 && props->n_ctx_handles > 0) {
+ DRM_DEBUG("Context handle specified multiple times\n");
+ err = -EINVAL;
+ goto error;
+ }
+
+ for (i = 0; i < n_uctx_handles; i++) {
+ err = get_user(props->ctx_handles[i], uctx_handles);
+ if (err)
+ goto error;
+
+ uctx_handles++;
+ props->n_ctx_handles++;
+ }
+
return 0;
error:
@@ -4644,8 +4692,12 @@ int i915_perf_ioctl_version(void)
*
* 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
*interval for the hrtimer used to check for OA data.
+*
+* 6: Add DRM_I915_PERF_PROP_CTX_HANDLE_ARRAY &
+*DRM_I915_PERF_PROP_CTX_HANDLE_ARRAY_LENGTH to allow an
+*application monitor/pin multiple contexts.
*/
- return 5;
+ return 6;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 14b67cd6b54b..f80e7932d728 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1993,6 +1993,27 @@ enum drm_i915_perf_property_id {
*/
DRM_I915_PERF_PROP_POLL_OA_PERIOD,
+ /**
+* Specifies an array of u32 GEM context handles to filter reports
+* with.
+
[Intel-gfx] [PATCH v5 3/4] drm/i915/perf: prepare driver to receive multiple ctx handles
Make all the internal necessary changes before we flip the switch.
v2: Use an unlimited number of intel contexts (Chris)
v3: Handle GEM context with multiple RCS0 logical contexts (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 556 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 37 +-
2 files changed, 359 insertions(+), 234 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index db526e0c160a..543d29cd5c14 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -192,6 +192,7 @@
*/
#include
+#include
#include
#include
@@ -329,7 +330,8 @@ static const struct i915_oa_format
gen12_oa_formats[I915_OA_FORMAT_MAX] = {
* @single_context: Whether a single or all gpu contexts should be monitored
* @hold_preemption: Whether the preemption is disabled for the filtered
* context
- * @ctx_handle: A gem ctx handle for use with @single_context
+ * @n_ctx_handles: Length of @ctx_handles
+ * @ctx_handles: An array of gem context handles
* @metrics_set: An ID for an OA unit metric set advertised via sysfs
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
@@ -349,9 +351,10 @@ static const struct i915_oa_format
gen12_oa_formats[I915_OA_FORMAT_MAX] = {
struct perf_open_properties {
u32 sample_flags;
- u64 single_context:1;
u64 hold_preemption:1;
- u64 ctx_handle;
+
+ u32 n_ctx_handles;
+ u32 *ctx_handles;
/* OA sampling state */
int metrics_set;
@@ -625,6 +628,23 @@ static int append_oa_sample(struct i915_perf_stream
*stream,
return 0;
}
+static int ctx_id_equal(const void *key, const void *elem)
+{
+ const struct i915_perf_context_detail *details = elem;
+
+ return ((int)details->id) - *((int *)key);
+}
+
+static inline bool ctx_id_match(struct i915_perf_stream *stream,
+ u32 masked_ctx_id)
+{
+ return bsearch(_ctx_id,
+ stream->pinned_ctxs,
+ stream->n_pinned_ctxs,
+ sizeof(*stream->pinned_ctxs),
+ ctx_id_equal) != NULL;
+}
+
/**
* Copies all buffered OA reports into userspace read() buffer.
* @stream: An i915-perf stream opened for OA metrics
@@ -736,7 +756,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
continue;
}
- ctx_id = report32[2] & stream->specific_ctx_id_mask;
+ ctx_id = report32[2] & stream->ctx_id_mask;
/*
* Squash whatever is in the CTX_ID field if it's marked as
@@ -781,26 +801,32 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* switches since it's not-uncommon for periodic samples to
* identify a switch before any 'context switch' report.
*/
- if (!stream->perf->exclusive_stream->ctx ||
- stream->specific_ctx_id == ctx_id ||
- stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
- reason & OAREPORT_REASON_CTX_SWITCH) {
-
- /*
-* While filtering for a single context we avoid
-* leaking the IDs of other contexts.
-*/
- if (stream->perf->exclusive_stream->ctx &&
- stream->specific_ctx_id != ctx_id) {
- report32[2] = INVALID_CTX_ID;
- }
-
+ if (!stream->perf->exclusive_stream->n_ctxs) {
ret = append_oa_sample(stream, buf, count, offset,
report);
if (ret)
break;
+ } else {
+ bool ctx_match = ctx_id != INVALID_CTX_ID &&
+ ctx_id_match(stream, ctx_id);
+
+ if (ctx_match ||
+ stream->oa_buffer.last_ctx_match ||
+ reason & OAREPORT_REASON_CTX_SWITCH) {
+ /*
+* While filtering for a single context we avoid
+* leaking the IDs of other contexts.
+*/
+ if (!ctx_match)
+ report32[2] = INVALID_CTX_ID;
+
+ ret = append_oa_sample(stream, buf, count,
offset,
+ report);
+ if (ret)
+ break;
+ }
- stream->oa_buffer.last_ctx_id = ctx_id;
+
[Intel-gfx] [PATCH v5 2/4] drm/i915/perf: stop using the kernel context
Chris doesn't like that.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 152 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 10 +-
2 files changed, 104 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d2183fd701a3..db526e0c160a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1350,9 +1350,31 @@ free_noa_wait(struct i915_perf_stream *stream)
i915_vma_unpin_and_release(>noa_wait, 0);
}
+static int i915_perf_stream_sync(struct i915_perf_stream *stream,
+bool enable)
+{
+ struct i915_active *active;
+ int err = 0;
+
+ active = i915_active_create();
+ if (!active)
+ return -ENOMEM;
+
+ if (enable)
+ err = stream->perf->ops.enable_metric_set(stream, active);
+ else
+ stream->perf->ops.disable_metric_set(stream, active);
+ if (err == 0)
+ __i915_active_wait(active, TASK_UNINTERRUPTIBLE);
+
+ i915_active_put(active);
+ return err;
+}
+
static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
{
struct i915_perf *perf = stream->perf;
+ int err;
BUG_ON(stream != perf->exclusive_stream);
@@ -1363,7 +1385,14 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
* See i915_oa_init_reg_state() and lrc_configure_all_contexts()
*/
WRITE_ONCE(perf->exclusive_stream, NULL);
- perf->ops.disable_metric_set(stream);
+ err = i915_perf_stream_sync(stream, false /* enable */);
+ if (err) {
+ drm_err(>i915->drm,
+ "Error while disabling OA stream\n");
+ }
+
+ intel_context_unpin(stream->config_context);
+ intel_context_put(stream->config_context);
free_oa_buffer(stream);
@@ -1993,11 +2022,6 @@ emit_oa_config(struct i915_perf_stream *stream,
return err;
}
-static struct intel_context *oa_context(struct i915_perf_stream *stream)
-{
- return stream->pinned_ctx ?: stream->engine->kernel_context;
-}
-
static int
hsw_enable_metric_set(struct i915_perf_stream *stream,
struct i915_active *active)
@@ -2021,19 +2045,20 @@ hsw_enable_metric_set(struct i915_perf_stream *stream,
0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
err = emit_oa_config(stream, stream->oa_config,
-oa_context(stream),
+stream->config_context,
active,
false /* global */);
if (err)
return err;
return emit_oa_config(stream, stream->oa_config,
- oa_context(stream),
+ stream->config_context,
active,
true /* global */);
}
-static void hsw_disable_metric_set(struct i915_perf_stream *stream)
+static void hsw_disable_metric_set(struct i915_perf_stream *stream,
+ struct i915_active *active)
{
struct intel_uncore *uncore = stream->uncore;
@@ -2158,13 +2183,14 @@ gen8_load_flex(struct i915_request *rq,
return 0;
}
-static int gen8_modify_context(struct intel_context *ce,
+static int gen8_modify_context(struct i915_perf_stream *stream,
+ struct intel_context *ce,
const struct flex *flex, unsigned int count)
{
struct i915_request *rq;
int err;
- rq = intel_engine_create_kernel_request(ce->engine);
+ rq = intel_context_create_request(stream->config_context);
if (IS_ERR(rq))
return PTR_ERR(rq);
@@ -2206,7 +2232,8 @@ gen8_modify_self(struct intel_context *ce,
return err;
}
-static int gen8_configure_context(struct i915_gem_context *ctx,
+static int gen8_configure_context(struct i915_perf_stream *stream,
+ struct i915_gem_context *ctx,
struct flex *flex, unsigned int count)
{
struct i915_gem_engines_iter it;
@@ -2224,7 +2251,7 @@ static int gen8_configure_context(struct i915_gem_context
*ctx,
continue;
flex->value = intel_sseu_make_rpcs(ctx->i915, >sseu);
- err = gen8_modify_context(ce, flex, count);
+ err = gen8_modify_context(stream, ce, flex, count);
intel_context_unpin(ce);
if (err)
@@ -2274,7 +2301,7 @@ static int gen12_configure_oar_context(struct
i915_perf_stream *stream,
if (err)
return err;
- err = gen8_modify_context(ce, regs_context, ARRAY_SIZE(regs_context));
+ err = gen8_modify_context(stream, ce, regs_context,
ARRAY_SIZE(regs_context));
intel_context_unlock_pinned(ce);
[Intel-gfx] [PATCH] HAX timer: Describe the delayed_work for a freed timer
Improve upon the
<3> [310.437368] ODEBUG: free active (active state 0) object type: timer_list
hint: delayed_work_timer_fn+0x0/0x10
by describing what delayed_work was queued instead.
Signed-off-by: Chris Wilson
---
kernel/time/timer.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/kernel/time/timer.c b/kernel/time/timer.c
index 4820823515e9..f637a815d91c 100644
--- a/kernel/time/timer.c
+++ b/kernel/time/timer.c
@@ -602,7 +602,14 @@ static struct debug_obj_descr timer_debug_descr;
static void *timer_debug_hint(void *addr)
{
- return ((struct timer_list *) addr)->function;
+ struct timer_list *timer = addr;
+
+ if (addr->function == delayed_work_timer_fn) {
+ struct delayed_work *work = from_timer(work, timer, timer);
+ return work->work.func;
+ }
+
+ return timer->function;
}
static bool timer_is_static_object(void *addr)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for i915 lpsp support for lpsp igt (rev7)
== Series Details ==
Series: i915 lpsp support for lpsp igt (rev7)
URL : https://patchwork.freedesktop.org/series/74648/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8281 -> Patchwork_17264
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17264:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@debugfs_test@read_all_entries:
- {fi-ehl-1}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/fi-ehl-1/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/fi-ehl-1/igt@debugfs_test@read_all_entries.html
* igt@runner@aborted:
- {fi-ehl-1}: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/fi-ehl-1/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_17264 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [INCOMPLETE][4] ([i915#189]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8281/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/fi-icl-dsi/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189
Participating hosts (51 -> 46)
--
Additional (2): fi-skl-6770hq fi-kbl-7560u
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-kbl-8809g fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* IGT: IGT_5581 -> IGTPW_4438
* Linux: CI_DRM_8281 -> Patchwork_17264
CI-20190529: 20190529
CI_DRM_8281: 4d6c69198d6840226f92f2c4645e2c8260ca3e83 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4438: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4438/index.html
IGT_5581: ab0620e555119ec55f12ba9ab9e6e9246d407648 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17264: 314d3d56f22db613bee1306e86f1a3bf2a41edee @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
314d3d56f22d drm/i915: Add i915_lpsp_status debugfs attribute
a7c4df3f9562 drm/i915: Add connector dbgfs for all connectors
9a892f85809b drm/i915: Add i915_lpsp_capability debugfs
9485fcfc0011 drm/i915: Power well id for ICL PG3
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17264/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 0/4] i915 lpsp support for lpsp igt
v4 has fixed the review comment provided by animesh. Test-with: 20200409053951.26929-2-anshuman.gu...@intel.com Anshuman Gupta (4): drm/i915: Power well id for ICL PG3 drm/i915: Add i915_lpsp_capability debugfs drm/i915: Add connector dbgfs for all connectors drm/i915: Add i915_lpsp_status debugfs attribute .../gpu/drm/i915/display/intel_connector.c| 3 + .../drm/i915/display/intel_display_debugfs.c | 109 ++ .../drm/i915/display/intel_display_power.c| 6 +- .../drm/i915/display/intel_display_power.h| 4 +- drivers/gpu/drm/i915/display/intel_dp.c | 3 - drivers/gpu/drm/i915/display/intel_hdmi.c | 3 - 6 files changed, 118 insertions(+), 10 deletions(-) -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/4] drm/i915: Add i915_lpsp_capability debugfs
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_capability, it exposes whether an output is
capable of driving lpsp.
v2:
- CI fixup.
v3:
- register i915_lpsp_info only for supported connector. [Jani]
- use intel_display_power_well_is_enabled() instead of looking
inside power_well count. [Jani]
- fixes the lpsp capable conditional logic. [Jani]
- combined the lpsp capable and enable info. [Jani]
v4:
- Separate out connector based debugfs i915_lpsp_capability
lpsp enable status would be exposes by different entry. [Animesh]
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 63 +++
1 file changed, 63 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index bdeea2e02642..402b89daff62 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -611,6 +611,28 @@ static void intel_hdcp_info(struct seq_file *m,
seq_puts(m, "\n");
}
+#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
+ seq_puts(m, "LPSP: incapable\n"))
+
+static bool intel_have_edp_dsi_panel(struct drm_connector *connector)
+{
+ return connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP;
+}
+
+static bool intel_have_dp_edp_dsi_panel(struct drm_connector *connector)
+{
+ return intel_have_edp_dsi_panel(connector) ||
+ connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort;
+}
+
+static bool intel_have_hdmi_dp_edp_dsi_panel(struct drm_connector *connector)
+{
+ return intel_have_dp_edp_dsi_panel(connector) ||
+ connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
+ connector->connector_type == DRM_MODE_CONNECTOR_HDMIB;
+}
+
static void intel_dp_info(struct seq_file *m,
struct intel_connector *intel_connector)
{
@@ -1991,6 +2013,42 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_lpsp_capability_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_encoder *encoder =
+ intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *i915 = to_i915(connector->dev);
+
+ if (connector->status != connector_status_connected)
+ return -ENODEV;
+
+ switch (INTEL_GEN(i915)) {
+ case 12:
+ /*
+* Actually TGL can drive LPSP on port till DDI_C
+* but there is no physical connected DDI_C on TGL sku's,
+* even driver is not initilizing DDI_C port for gen12.
+*/
+ LPSP_CAPABLE(encoder->port <= PORT_B);
+ break;
+ case 11:
+ LPSP_CAPABLE(intel_have_edp_dsi_panel(connector));
+ break;
+ case 10:
+ case 9:
+ LPSP_CAPABLE(encoder->port == PORT_A &&
+intel_have_dp_edp_dsi_panel(connector));
+ break;
+ default:
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ LPSP_CAPABLE(connector->connector_type ==
DRM_MODE_CONNECTOR_eDP);
+ }
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
+
static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
{
struct drm_connector *connector = m->private;
@@ -2134,5 +2192,10 @@ int intel_connector_debugfs_add(struct drm_connector
*connector)
debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root,
connector, _dsc_fec_support_fops);
+ /* Legacy panels doesn't lpsp on any platform */
+ if (intel_have_hdmi_dp_edp_dsi_panel(connector))
+ debugfs_create_file("i915_lpsp_capability", 0444, root,
+ connector, _lpsp_capability_fops);
+
return 0;
}
--
2.26.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 3/4] drm/i915: Add connector dbgfs for all connectors
Add connector debugfs attributes for each intel connector which is getting register. v2: - adding connector debugfs for each connector in intel_connector_register() to fix CI failure for legacy connectors. Reviewed-by: Jani Nikula Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_connector.c | 3 +++ drivers/gpu/drm/i915/display/intel_dp.c| 3 --- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c index 98ec2ea86c7c..406e96785c76 100644 --- a/drivers/gpu/drm/i915/display/intel_connector.c +++ b/drivers/gpu/drm/i915/display/intel_connector.c @@ -33,6 +33,7 @@ #include "i915_drv.h" #include "intel_connector.h" +#include "intel_display_debugfs.h" #include "intel_display_types.h" #include "intel_hdcp.h" @@ -123,6 +124,8 @@ int intel_connector_register(struct drm_connector *connector) goto err_backlight; } + intel_connector_debugfs_add(connector); + return 0; err_backlight: diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 85cfd7210ad8..2cea1c0dcaa8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -48,7 +48,6 @@ #include "intel_audio.h" #include "intel_connector.h" #include "intel_ddi.h" -#include "intel_display_debugfs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" @@ -6451,8 +6450,6 @@ intel_dp_connector_register(struct drm_connector *connector) if (ret) return ret; - intel_connector_debugfs_add(connector); - drm_dbg_kms(>drm, "registering %s bus for %s\n", intel_dp->aux.name, connector->kdev->kobj.name); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 011d83c2a1e3..0ca8bf62cb8e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -44,7 +44,6 @@ #include "intel_audio.h" #include "intel_connector.h" #include "intel_ddi.h" -#include "intel_display_debugfs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dpio_phy.h" @@ -2877,8 +2876,6 @@ intel_hdmi_connector_register(struct drm_connector *connector) if (ret) return ret; - intel_connector_debugfs_add(connector); - intel_hdmi_create_i2c_symlink(connector); return ret; -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 4/4] drm/i915: Add i915_lpsp_status debugfs attribute
It requires a separate debugfs attribute to expose lpsp
status to user space, as there may be display less configuration
without any valid connected output, those configuration will not be
able to test lpsp status, if lpsp status exposed from a connector
based debugfs attribute.
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 46 +++
.../drm/i915/display/intel_display_power.h| 2 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 402b89daff62..9a5b7f1cbe07 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -9,6 +9,7 @@
#include "i915_debugfs.h"
#include "intel_csr.h"
#include "intel_display_debugfs.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_fbc.h"
@@ -613,6 +614,8 @@ static void intel_hdcp_info(struct seq_file *m,
#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
+#define LPSP_STATUS(COND) (COND ? seq_puts(m, "LPSP: enabled\n") : \
+ seq_puts(m, "LPSP: disabled\n"))
static bool intel_have_edp_dsi_panel(struct drm_connector *connector)
{
@@ -1165,6 +1168,48 @@ static int i915_drrs_status(struct seq_file *m, void
*unused)
return 0;
}
+static bool
+intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
+ enum i915_power_well_id power_well_id)
+{
+ intel_wakeref_t wakeref;
+ bool is_enabled;
+
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+ is_enabled = intel_display_power_well_is_enabled(i915,
+power_well_id);
+ intel_runtime_pm_put(>runtime_pm, wakeref);
+
+ return is_enabled;
+}
+
+static int i915_lpsp_status(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+
+ switch (INTEL_GEN(i915)) {
+ case 12:
+ case 11:
+ LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
ICL_DISP_PW_3));
+ break;
+ case 10:
+ case 9:
+ LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
SKL_DISP_PW_2));
+ break;
+ default:
+ /*
+* Apart from HASWELL/BROADWELL other legacy platform doesn't
+* support lpsp.
+*/
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
HSW_DISP_PW_GLOBAL));
+ else
+ seq_puts(m, "LPSP: not supported\n");
+ }
+
+ return 0;
+}
+
static int i915_dp_mst_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -1932,6 +1977,7 @@ static const struct drm_info_list
intel_display_debugfs_list[] = {
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_ddb_info", i915_ddb_info, 0},
{"i915_drrs_status", i915_drrs_status, 0},
+ {"i915_lpsp_status", i915_lpsp_status, 0},
};
static const struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 56cbae6327b7..14c5ad20287f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -266,6 +266,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain);
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
+bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
+enum i915_power_well_id power_well_id);
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
--
2.26.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 1/4] drm/i915: Power well id for ICL PG3
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_power.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 433e5a81dd4d..3672c00be94a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -943,7 +943,7 @@ static void assert_can_enable_dc5(struct drm_i915_private
*dev_priv)
/* Power wells at this level and above must be disabled for DC5 entry */
if (INTEL_GEN(dev_priv) >= 12)
- high_pg = TGL_DISP_PW_3;
+ high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -3571,7 +3571,7 @@ static const struct i915_power_well_desc
icl_power_wells[] = {
.name = "power well 3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = _power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = ICL_DISP_PW_3,
{
.hsw.regs = _power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -3949,7 +3949,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
.name = "power well 3",
.domains = TGL_PW_3_POWER_DOMAINS,
.ops = _power_well_ops,
- .id = TGL_DISP_PW_3,
+ .id = ICL_DISP_PW_3,
{
.hsw.regs = _power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..56cbae6327b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,7 +100,7 @@ enum i915_power_well_id {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
- TGL_DISP_PW_3,
+ ICL_DISP_PW_3,
SKL_DISP_DC_OFF,
};
--
2.26.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Introduce drm scaling filter property (rev6)
== Series Details == Series: Introduce drm scaling filter property (rev6) URL : https://patchwork.freedesktop.org/series/73883/ State : success == Summary == CI Bug Log - changes from CI_DRM_8278_full -> Patchwork_17256_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17256_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_whisper@basic-forked: - shard-snb: [PASS][1] -> [INCOMPLETE][2] ([i915#82]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-snb1/igt@gem_exec_whis...@basic-forked.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-snb6/igt@gem_exec_whis...@basic-forked.html * igt@gem_workarounds@suspend-resume-context: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#69]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-skl5/igt@gem_workarou...@suspend-resume-context.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-skl8/igt@gem_workarou...@suspend-resume-context.html * igt@gen9_exec_parse@allowed-all: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#716]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-kbl6/igt@gen9_exec_pa...@allowed-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-kbl7/igt@gen9_exec_pa...@allowed-all.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#716]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-skl9/igt@gen9_exec_pa...@allowed-single.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-skl6/igt@gen9_exec_pa...@allowed-single.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109349]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-iclb4/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#79]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-glk8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-glk3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-kbl2/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-kbl4/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180] / [i915#93] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-kbl3/igt@kms_frontbuffer_track...@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-kbl4/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#49]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-skl4/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-pwrite.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-skl6/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8278/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17256/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html Possible fixes
Re: [Intel-gfx] [PATCH i-g-t] intel-ci: Drop gem_exec_suspend@basic-S4-device from BAT
On 2020-04-08 17:19, Chris Wilson wrote: > S4-devices is a debug only path, and while it can prove informative as > to the nature of suspend issues, being a debug only path it is not so > relevant towards the driver health. Relegate it to the shards and idle > runs, so we can shave 20s off BAT. > > gem_exec_suspend@basic itself is just a test suspend, a sanitycheck to > ensure the test is functional, for manual debugging of the tests. > > Signed-off-by: Chris Wilson > Cc: Martin Peres > Cc: Petri Latvala Acked-by: Martin Peres > --- > tests/intel-ci/fast-feedback.testlist | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/tests/intel-ci/fast-feedback.testlist > b/tests/intel-ci/fast-feedback.testlist > index 620d5f3a7..2ccad4386 100644 > --- a/tests/intel-ci/fast-feedback.testlist > +++ b/tests/intel-ci/fast-feedback.testlist > @@ -23,10 +23,8 @@ igt@gem_exec_fence@nb-await > igt@gem_exec_gttfill@basic > igt@gem_exec_parallel@engines > igt@gem_exec_store@basic > -igt@gem_exec_suspend@basic > igt@gem_exec_suspend@basic-s0 > igt@gem_exec_suspend@basic-s3 > -igt@gem_exec_suspend@basic-s4-devices > igt@gem_flink_basic@bad-flink > igt@gem_flink_basic@bad-open > igt@gem_flink_basic@basic > pEpkey.asc Description: pEpkey.asc ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
