[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Move the batch buffer pool from the engine to the gt (rev2)
== Series Details ==
Series: drm/i915/gt: Move the batch buffer pool from the engine to the gt (rev2)
URL : https://patchwork.freedesktop.org/series/75979/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8307_full -> Patchwork_17322_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17322_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_schedule@pi-shared-iova@bcs0}:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-skl2/igt@gem_exec_schedule@pi-shared-i...@bcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-skl5/igt@gem_exec_schedule@pi-shared-i...@bcs0.html
* {igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2}:
- shard-glk: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vbl...@ab-hdmi-a1-hdmi-a2.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vbl...@ab-hdmi-a1-hdmi-a2.html
Known issues
Here are the changes found in Patchwork_17322_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-apl3/igt@i915_susp...@sysfs-reader.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-apl6/igt@i915_susp...@sysfs-reader.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +3 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-kbl1/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109349])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-iclb4/igt@kms_dp_...@basic-dsc-enable-edp.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [i915#265])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-skl4/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +3 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#31])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-skl8/igt@kms_setm...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-skl8/igt@kms_setm...@basic.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#69])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-skl6/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-skl9/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html
Possible fixes
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][19] ([i915#454]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-iclb4/igt@i915_pm...@dc6-dpms.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-iclb3/igt@i915_pm...@dc6-dpms.html
* igt@kms_color@pipe-a-degamma:
- shard-skl: [FAIL][21] ([fdo#108145] / [i915#71]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-skl8/igt@kms_co...@pipe-a-degamma.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17322/shard-skl9/igt@kms_co...@pipe-a-degamma.html
* igt@kms_color@pipe-a-gamma:
- shard-tglb: [FAIL][23] ([i915#1149]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8307/shard-tglb5/igt@kms_co...@pipe-a-gamma.html
[24]:
Re: [Intel-gfx] improve use_mm / unuse_mm v2
On Thu, Apr 16, 2020 at 07:31:55AM +0200, Christoph Hellwig wrote: > this series improves the use_mm / unuse_mm interface by better > documenting the assumptions, and my taking the set_fs manipulations > spread over the callers into the core API. I appreciate all the work you're doing here. Do you have plans to introduce a better-named API than set_fs() / get_fs()? Also, having set_fs() return the previous value of 'fs' would simplify a lot of the callers. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: TBT AUX should use TC power well ops
On Wed, Apr 15, 2020 at 04:58:58PM -0700, Souza, Jose wrote:
> On Wed, 2020-04-15 at 16:34 -0700, Matt Roper wrote:
> > As on ICL, we want to use the Type-C aux handlers for the TBT aux
> > wells
> > to ensure the DP_AUX_CH_CTL_TBT_IO flag is set properly.
>
> Reviewed-by: José Roberto de Souza
Thanks. CI came back clean, so I went ahead and pushed patch #1 of the
series.
Matt
>
> >
> > Fixes: 656409bbaf87 ("drm/i915/tgl: Add power well support")
> > Cc: José Roberto de Souza
> > Cc: Imre Deak
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++--
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 6cc0e23ca566..03bdde19c8c9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -4147,7 +4147,7 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > {
> > .name = "AUX D TBT1",
> > .domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
> > - .ops = _power_well_ops,
> > + .ops = _tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > .hsw.regs = _aux_power_well_regs,
> > @@ -4158,7 +4158,7 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > {
> > .name = "AUX E TBT2",
> > .domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
> > - .ops = _power_well_ops,
> > + .ops = _tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > .hsw.regs = _aux_power_well_regs,
> > @@ -4169,7 +4169,7 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > {
> > .name = "AUX F TBT3",
> > .domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
> > - .ops = _power_well_ops,
> > + .ops = _tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > .hsw.regs = _aux_power_well_regs,
> > @@ -4180,7 +4180,7 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > {
> > .name = "AUX G TBT4",
> > .domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
> > - .ops = _power_well_ops,
> > + .ops = _tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > .hsw.regs = _aux_power_well_regs,
> > @@ -4191,7 +4191,7 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > {
> > .name = "AUX H TBT5",
> > .domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
> > - .ops = _power_well_ops,
> > + .ops = _tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > .hsw.regs = _aux_power_well_regs,
> > @@ -4202,7 +4202,7 @@ static const struct i915_power_well_desc
> > tgl_power_wells[] = {
> > {
> > .name = "AUX I TBT6",
> > .domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
> > - .ops = _power_well_ops,
> > + .ops = _tc_phy_aux_power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > .hsw.regs = _aux_power_well_regs,
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
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[Intel-gfx] [drm-intel:topic/core-for-CI 2/20] kernel/locking/lockdep.c:2744:49: sparse: sparse: cast truncates bits from constant value (a0000 becomes 0)
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI
head: d0435a9b45070b945578c093dcd363b6b73a502c
commit: cbc1ad45be43de36150fd98dae644fc89a69a5a0 [2/20] lockdep: Up
MAX_LOCKDEP_CHAINS
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-191-gc51a0382-dirty
git checkout cbc1ad45be43de36150fd98dae644fc89a69a5a0
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot
sparse warnings: (new ones prefixed by >>)
>> kernel/locking/lockdep.c:2744:49: sparse: sparse: cast truncates bits from
>> constant value (a becomes 0)
>> kernel/locking/lockdep.c:2744:49: sparse: sparse: cast truncates bits from
>> constant value (a becomes 0)
vim +2744 kernel/locking/lockdep.c
810507fe6fd5ff Waiman Long 2020-02-06 2736
810507fe6fd5ff Waiman Long 2020-02-06 2737 static inline void
init_chain_block(int offset, int next, int bucket, int size)
810507fe6fd5ff Waiman Long 2020-02-06 2738 {
810507fe6fd5ff Waiman Long 2020-02-06 2739 chain_hlocks[offset] = (next >>
16) | CHAIN_BLK_FLAG;
810507fe6fd5ff Waiman Long 2020-02-06 2740 chain_hlocks[offset + 1] =
(u16)next;
810507fe6fd5ff Waiman Long 2020-02-06 2741
810507fe6fd5ff Waiman Long 2020-02-06 2742 if (size && !bucket) {
810507fe6fd5ff Waiman Long 2020-02-06 2743 chain_hlocks[offset +
2] = size >> 16;
810507fe6fd5ff Waiman Long 2020-02-06 @2744 chain_hlocks[offset +
3] = (u16)size;
810507fe6fd5ff Waiman Long 2020-02-06 2745 }
810507fe6fd5ff Waiman Long 2020-02-06 2746 }
810507fe6fd5ff Waiman Long 2020-02-06 2747
:: The code at line 2744 was first introduced by commit
:: 810507fe6fd5ff3de429121adff49523fabb643a locking/lockdep: Reuse freed
chain_hlocks entries
:: TO: Waiman Long
:: CC: Ingo Molnar
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt
== Series Details == Series: series starting with [CI,1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt URL : https://patchwork.freedesktop.org/series/76055/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17338 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17338 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17338, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17338/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17338: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_pm: - fi-kbl-r: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-kbl-r/igt@i915_selftest@live@gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17338/fi-kbl-r/igt@i915_selftest@live@gt_pm.html - fi-skl-guc: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-skl-guc/igt@i915_selftest@live@gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17338/fi-skl-guc/igt@i915_selftest@live@gt_pm.html - fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17338/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html Known issues Here are the changes found in Patchwork_17338 that come from known issues: ### IGT changes ### Warnings * igt@amdgpu/amd_prime@i915-to-amd: - fi-bwr-2160:[FAIL][7] ([i915#489]) -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17338/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (51 -> 45) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8311 -> Patchwork_17338 CI-20190529: 20190529 CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17338: 9bf31402e7bd605cb63ecbcc6c12ea4d7900edb2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9bf31402e7bd drm/i915/selftests: Check power consumption at min/max frequencies 19f5c73e9693 drm/i915/selftests: Move gpu energy measurement into its own little lib 14195cf9296d drm/i915/gt: Use the RPM config register to determine clk frequencies 6727bb3359e8 drm/i915/gt: Trace RPS events 840a974dda70 drm/i915/selftests: Delay spinner before waiting for an interrupt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17338/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt
== Series Details == Series: series starting with [CI,1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt URL : https://patchwork.freedesktop.org/series/76055/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt
== Series Details == Series: series starting with [CI,1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt URL : https://patchwork.freedesktop.org/series/76055/ State : warning == Summary == $ dim checkpatch origin/drm-tip 840a974dda70 drm/i915/selftests: Delay spinner before waiting for an interrupt 6727bb3359e8 drm/i915/gt: Trace RPS events 14195cf9296d drm/i915/gt: Use the RPM config register to determine clk frequencies -:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #78: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 352 lines checked 19f5c73e9693 drm/i915/selftests: Move gpu energy measurement into its own little lib -:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #79: new file mode 100644 -:109: CHECK:LINE_SPACING: Please don't use multiple blank lines #109: FILE: drivers/gpu/drm/i915/selftests/librapl.c:26: + + total: 0 errors, 1 warnings, 1 checks, 93 lines checked 9bf31402e7bd drm/i915/selftests: Check power consumption at min/max frequencies ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/5] drm/i915/gt: Trace RPS events
Add tracek to the RPS events (interrupts, worker, enabling, threshold
selection, frequency setting), so that if we have to debug reticent HW
we have some traces to start from.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 47 ++---
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 4dcfae16a7ce..42275e25ea1b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -82,6 +82,8 @@ static void rps_enable_interrupts(struct intel_rps *rps)
GEN6_PM_RP_DOWN_THRESHOLD |
GEN6_PM_RP_DOWN_TIMEOUT);
WRITE_ONCE(rps->pm_events, events);
+ GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",
+events, rps_pm_mask(rps, rps->last_freq));
spin_lock_irq(>irq_lock);
gen6_gt_pm_enable_irq(gt, rps->pm_events);
@@ -140,6 +142,7 @@ static void rps_disable_interrupts(struct intel_rps *rps)
cancel_work_sync(>work);
rps_reset_interrupts(rps);
+ GT_TRACE(gt, "interrupts:off\n");
}
static const struct cparams {
@@ -581,6 +584,10 @@ static void rps_set_power(struct intel_rps *rps, int
new_power)
if (IS_VALLEYVIEW(i915))
goto skip_hw_write;
+ GT_TRACE(rps_to_gt(rps),
+"changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n",
+new_power, threshold_up, ei_up, threshold_down, ei_down);
+
set(uncore, GEN6_RP_UP_EI, GT_INTERVAL_FROM_US(i915, ei_up));
set(uncore, GEN6_RP_UP_THRESHOLD,
GT_INTERVAL_FROM_US(i915, ei_up * threshold_up / 100));
@@ -645,6 +652,8 @@ static void gen6_rps_set_thresholds(struct intel_rps *rps,
u8 val)
void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive)
{
+ GT_TRACE(rps_to_gt(rps), "mark interactive: %s\n", yesno(interactive));
+
mutex_lock(>power.mutex);
if (interactive) {
if (!rps->power.interactive++ && READ_ONCE(rps->active))
@@ -672,6 +681,9 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
GEN6_AGGRESSIVE_TURBO);
set(uncore, GEN6_RPNSWREQ, swreq);
+ GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d, swreq:%x\n",
+val, intel_gpu_freq(rps, val), swreq);
+
return 0;
}
@@ -684,6 +696,9 @@ static int vlv_rps_set(struct intel_rps *rps, u8 val)
err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val);
vlv_punit_put(i915);
+ GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n",
+val, intel_gpu_freq(rps, val));
+
return err;
}
@@ -717,6 +732,8 @@ void intel_rps_unpark(struct intel_rps *rps)
if (!rps->enabled)
return;
+ GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq);
+
/*
* Use the user's desired frequency as a guide, but for better
* performance, jump directly to RPe as our starting frequency.
@@ -784,6 +801,8 @@ void intel_rps_park(struct intel_rps *rps)
*/
rps->cur_freq =
max_t(int, round_down(rps->cur_freq - 1, 2), rps->min_freq);
+
+ GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq);
}
void intel_rps_boost(struct i915_request *rq)
@@ -800,6 +819,9 @@ void intel_rps_boost(struct i915_request *rq)
!dma_fence_is_signaled_locked(>fence)) {
set_bit(I915_FENCE_FLAG_BOOST, >fence.flags);
+ GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n",
+rq->fence.context, rq->fence.seqno);
+
if (!atomic_fetch_inc(>num_waiters) &&
READ_ONCE(rps->cur_freq) < rps->boost_freq)
schedule_work(>work);
@@ -895,6 +917,7 @@ static void gen6_rps_init(struct intel_rps *rps)
static bool rps_reset(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
+
/* force a reset */
rps->power.mode = -1;
rps->last_freq = -1;
@@ -1215,11 +1238,17 @@ void intel_rps_enable(struct intel_rps *rps)
if (!rps->enabled)
return;
- drm_WARN_ON(>drm, rps->max_freq < rps->min_freq);
- drm_WARN_ON(>drm, rps->idle_freq > rps->max_freq);
+ GT_TRACE(rps_to_gt(rps),
+"min:%x, max:%x, freq:[%d, %d]\n",
+rps->min_freq, rps->max_freq,
+intel_gpu_freq(rps, rps->min_freq),
+intel_gpu_freq(rps, rps->max_freq));
+
+ GEM_BUG_ON(rps->max_freq < rps->min_freq);
+ GEM_BUG_ON(rps->idle_freq > rps->max_freq);
- drm_WARN_ON(>drm, rps->efficient_freq < rps->min_freq);
- drm_WARN_ON(>drm, rps->efficient_freq > rps->max_freq);
+ GEM_BUG_ON(rps->efficient_freq < rps->min_freq);
+ GEM_BUG_ON(rps->efficient_freq > rps->max_freq);
}
static void gen6_rps_disable(struct
[Intel-gfx] [CI 5/5] drm/i915/selftests: Check power consumption at min/max frequencies
A basic premise of RPS is that at lower frequencies, not only do we run
slower, but we save power compared to higher frequencies. For example,
when idle, we set the minimum frequency just in case there is some
residual current. Since the power curve should be a physical
relationship, if we find no power saving it's likely that we've broken
our frequency handling, so test!
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 138 +++
drivers/gpu/drm/i915/gt/selftest_rps.h | 1 +
3 files changed, 140 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index c50bb502fe03..0141c334f2ac 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -54,6 +54,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
SUBTEST(live_rps_interrupt),
+ SUBTEST(live_rps_power),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 83cc4d1fc5de..26c2eb219e66 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -3,6 +3,8 @@
* Copyright © 2020 Intel Corporation
*/
+#include
+
#include "intel_engine_pm.h"
#include "intel_gt_clock_utils.h"
#include "intel_gt_pm.h"
@@ -10,6 +12,7 @@
#include "selftest_rps.h"
#include "selftests/igt_flush_test.h"
#include "selftests/igt_spinner.h"
+#include "selftests/librapl.h"
static void dummy_rps_work(struct work_struct *wrk)
{
@@ -228,3 +231,138 @@ int live_rps_interrupt(void *arg)
return err;
}
+
+static u64 __measure_power(int duration_ms)
+{
+ u64 dE, dt;
+
+ dt = ktime_get();
+ dE = librapl_energy_uJ();
+ usleep_range(1000 * duration_ms, 2000 * duration_ms);
+ dE = librapl_energy_uJ() - dE;
+ dt = ktime_get() - dt;
+
+ return div64_u64(1000 * 1000 * dE, dt);
+}
+
+static int cmp_u64(const void *A, const void *B)
+{
+ const u64 *a = A, *b = B;
+
+ if (a < b)
+ return -1;
+ else if (a > b)
+ return 1;
+ else
+ return 0;
+}
+
+static u64 measure_power_at(struct intel_rps *rps, int freq)
+{
+ u64 x[5];
+ int i;
+
+ mutex_lock(>lock);
+ GEM_BUG_ON(!rps->active);
+ intel_rps_set(rps, freq);
+ mutex_unlock(>lock);
+
+ msleep(20); /* more than enough time to stabilise! */
+
+ i = read_cagf(rps);
+ if (i != freq)
+ pr_notice("Running at %x [%uMHz], not target %x [%uMHz]\n",
+ i, intel_gpu_freq(rps, i),
+ freq, intel_gpu_freq(rps, freq));
+
+ for (i = 0; i < 5; i++)
+ x[i] = __measure_power(5);
+
+ /* A simple triangle filter for better result stability */
+ sort(x, 5, sizeof(*x), cmp_u64, NULL);
+ return div_u64(x[1] + 2 * x[2] + x[3], 4);
+}
+
+int live_rps_power(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_rps *rps = >rps;
+ void (*saved_work)(struct work_struct *wrk);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ int err = 0;
+
+ /*
+* Our fundamental assumption is that running at lower frequency
+* actually saves power. Let's see if our RAPL measurement support
+* that theory.
+*/
+
+ if (!rps->enabled || rps->max_freq <= rps->min_freq)
+ return 0;
+
+ if (!librapl_energy_uJ())
+ return 0;
+
+ if (igt_spinner_init(, gt))
+ return -ENOMEM;
+
+ intel_gt_pm_wait_for_idle(gt);
+ saved_work = rps->work.func;
+ rps->work.func = dummy_rps_work;
+
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq;
+ u64 min, max;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ rq = igt_spinner_create_request(,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ intel_gt_set_wedged(engine->gt);
+ err = -EIO;
+ break;
+ }
+
+ max = measure_power_at(rps, rps->max_freq);
+
[Intel-gfx] [CI 3/5] drm/i915/gt: Use the RPM config register to determine clk frequencies
For many configuration details within RC6 and RPS we are programming
intervals for the internal clocks. From gen11, these clocks are
configuration via the RPM_CONFIG and so for convenience, we would like
to convert to/from more natural units (ns).
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Cc: Mika Kuoppala
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 27 ---
.../gpu/drm/i915/gt/intel_gt_clock_utils.c| 78 +++
.../gpu/drm/i915/gt/intel_gt_clock_utils.h| 21 +
drivers/gpu/drm/i915/gt/intel_rps.c | 40 ++
drivers/gpu/drm/i915/gt/selftest_rps.c| 7 +-
drivers/gpu/drm/i915/i915_debugfs.c | 34 +---
drivers/gpu/drm/i915/i915_reg.h | 25 --
8 files changed, 167 insertions(+), 66 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44c506b7e117..8f6fb9360fbe 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -91,6 +91,7 @@ gt-y += \
gt/intel_ggtt.o \
gt/intel_ggtt_fencing.o \
gt/intel_gt.o \
+ gt/intel_gt_clock_utils.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index aab30d908072..d4e3b4c0c48f 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -10,6 +10,7 @@
#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt.h"
+#include "intel_gt_clock_utils.h"
#include "intel_llc.h"
#include "intel_rc6.h"
#include "intel_rps.h"
@@ -394,21 +395,23 @@ static int frequency_show(struct seq_file *m, void
*unused)
seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
seq_printf(m, "CAGF: %dMHz\n", cagf);
- seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
- rpupei, GT_PM_INTERVAL_TO_US(i915, rpupei));
- seq_printf(m, "RP CUR UP: %d (%dus)\n",
- rpcurup, GT_PM_INTERVAL_TO_US(i915, rpcurup));
- seq_printf(m, "RP PREV UP: %d (%dus)\n",
- rpprevup, GT_PM_INTERVAL_TO_US(i915, rpprevup));
+ seq_printf(m, "RP CUR UP EI: %d (%dns)\n",
+ rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
+ seq_printf(m, "RP CUR UP: %d (%dns)\n",
+ rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
+ seq_printf(m, "RP PREV UP: %d (%dns)\n",
+ rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
seq_printf(m, "Up threshold: %d%%\n",
rps->power.up_threshold);
- seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
- rpdownei, GT_PM_INTERVAL_TO_US(i915, rpdownei));
- seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
- rpcurdown, GT_PM_INTERVAL_TO_US(i915, rpcurdown));
- seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
- rpprevdown, GT_PM_INTERVAL_TO_US(i915, rpprevdown));
+ seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n",
+ rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
+ seq_printf(m, "RP CUR DOWN: %d (%dns)\n",
+ rpcurdown,
+ intel_gt_pm_interval_to_ns(gt, rpcurdown));
+ seq_printf(m, "RP PREV DOWN: %d (%dns)\n",
+ rpprevdown,
+ intel_gt_pm_interval_to_ns(gt, rpprevdown));
seq_printf(m, "Down threshold: %d%%\n",
rps->power.down_threshold);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
new file mode 100644
index ..e63e400ee1c5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt.h"
+#include "intel_gt_clock_utils.h"
+
+#define MHZ_19_2 1920 /* 19.2MHz, 52.083ns */
+#define MHZ_24 2400 /* 24MHz, 83.333ns */
+#define MHZ_25 2500 /* 25MHz, 80ns */
+
+u32 intel_gt_clock_frequency(struct intel_gt *gt)
+{
+ if (INTEL_GEN(gt->i915) >= 11) {
+ u32 config;
+
+ config = intel_uncore_read(gt->uncore, RPM_CONFIG0);
+ config &= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
+ config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+
+ switch (config) {
+ case 0: return
[Intel-gfx] [CI 1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt
It seems that although (perhaps because of the memory stall?) the
spinner has signaled that it has started, it still takes some time to
spin up to 100% utilisation of the HW. Since the test depends on the
full utilisation of the HW to trigger the RPS interrupt, wait a little
bit and flush the interrupt status to be sure that the event we see if
from the spinner.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_rps.c | 28 +++---
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 26aadc2ae3be..199d608aa763 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -14,6 +14,20 @@ static void dummy_rps_work(struct work_struct *wrk)
{
}
+static void sleep_for_ei(struct intel_rps *rps, int timeout_us)
+{
+ /* Flush any previous EI */
+ usleep_range(timeout_us, 2 * timeout_us);
+
+ /* Reset the interrupt status */
+ rps_disable_interrupts(rps);
+ GEM_BUG_ON(rps->pm_iir);
+ rps_enable_interrupts(rps);
+
+ /* And then wait for the timeout, for real this time */
+ usleep_range(2 * timeout_us, 3 * timeout_us);
+}
+
static int __rps_up_interrupt(struct intel_rps *rps,
struct intel_engine_cs *engine,
struct igt_spinner *spin)
@@ -28,7 +42,6 @@ static int __rps_up_interrupt(struct intel_rps *rps,
intel_gt_pm_wait_for_idle(engine->gt);
GEM_BUG_ON(rps->active);
- rps->pm_iir = 0;
rps->cur_freq = rps->min_freq;
rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP);
@@ -71,7 +84,7 @@ static int __rps_up_interrupt(struct intel_rps *rps,
timeout = intel_uncore_read(uncore, GEN6_RP_UP_EI);
timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
- usleep_range(2 * timeout, 3 * timeout);
+ sleep_for_ei(rps, timeout);
GEM_BUG_ON(i915_request_completed(rq));
igt_spinner_end(spin);
@@ -122,16 +135,7 @@ static int __rps_down_interrupt(struct intel_rps *rps,
timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
- /* Flush any previous EI */
- usleep_range(timeout, 2 * timeout);
-
- /* Reset the interrupt status */
- rps_disable_interrupts(rps);
- GEM_BUG_ON(rps->pm_iir);
- rps_enable_interrupts(rps);
-
- /* And then wait for the timeout, for real this time */
- usleep_range(2 * timeout, 3 * timeout);
+ sleep_for_ei(rps, timeout);
if (rps->cur_freq != rps->max_freq) {
pr_err("%s: Frequency unexpectedly changed [down], now %d!\n",
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/5] drm/i915/selftests: Move gpu energy measurement into its own little lib
Move the handy utility to measure the GPU energy consumption using RAPL
msr into a common lib so that it can be reused easily.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 3 ++-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 25 +--
drivers/gpu/drm/i915/selftests/librapl.c | 26
drivers/gpu/drm/i915/selftests/librapl.h | 13
4 files changed, 46 insertions(+), 21 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/librapl.c
create mode 100644 drivers/gpu/drm/i915/selftests/librapl.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8f6fb9360fbe..ce24a4ee9591 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/igt_live_test.o \
selftests/igt_mmap.o \
selftests/igt_reset.o \
- selftests/igt_spinner.o
+ selftests/igt_spinner.o \
+ selftests/librapl.o
# virtual gpu code
i915-y += i915_vgpu.o
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 08c3dbd41b12..2dc460624bbc 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -11,22 +11,7 @@
#include "selftest_rc6.h"
#include "selftests/i915_random.h"
-
-static u64 energy_uJ(struct intel_rc6 *rc6)
-{
- unsigned long long power;
- u32 units;
-
- if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, ))
- return 0;
-
- units = (power & 0x1f00) >> 8;
-
- if (rdmsrl_safe(MSR_PP1_ENERGY_STATUS, ))
- return 0;
-
- return (100 * power) >> units; /* convert to uJ */
-}
+#include "selftests/librapl.h"
static u64 rc6_residency(struct intel_rc6 *rc6)
{
@@ -74,9 +59,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
dt = ktime_get();
- rc0_power = energy_uJ(rc6);
+ rc0_power = librapl_energy_uJ();
msleep(250);
- rc0_power = energy_uJ(rc6) - rc0_power;
+ rc0_power = librapl_energy_uJ() - rc0_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if ((res[1] - res[0]) >> 10) {
@@ -99,9 +84,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
intel_uncore_forcewake_flush(rc6_to_uncore(rc6), FORCEWAKE_ALL);
dt = ktime_get();
- rc6_power = energy_uJ(rc6);
+ rc6_power = librapl_energy_uJ();
msleep(100);
- rc6_power = energy_uJ(rc6) - rc6_power;
+ rc6_power = librapl_energy_uJ() - rc6_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if (res[1] == res[0]) {
diff --git a/drivers/gpu/drm/i915/selftests/librapl.c
b/drivers/gpu/drm/i915/selftests/librapl.c
new file mode 100644
index ..5e21e55fae91
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/librapl.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include
+
+#include "librapl.h"
+
+u64 librapl_energy_uJ(void)
+{
+ unsigned long long power;
+ u32 units;
+
+ if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, ))
+ return 0;
+
+ units = (power & 0x1f00) >> 8;
+
+ if (rdmsrl_safe(MSR_PP1_ENERGY_STATUS, ))
+ return 0;
+
+ return (100 * power) >> units; /* convert to uJ */
+}
+
+
diff --git a/drivers/gpu/drm/i915/selftests/librapl.h
b/drivers/gpu/drm/i915/selftests/librapl.h
new file mode 100644
index ..887f3e91dd05
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/librapl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef SELFTEST_LIBRAPL_H
+#define SELFTEST_LIBRAPL_H
+
+#include
+
+u64 librapl_energy_uJ(void);
+
+#endif /* SELFTEST_LIBRAPL_H */
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format support for skl+ (V15)
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, April 16, 2020 2:10 AM
> To: Paauwe, Bob J ; intel-gfx g...@lists.freedesktop.org>
> Cc: Daniel Vetter
> Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format
> support for skl+ (V15)
>
> On Wed, 08 Apr 2020, Jani Nikula wrote:
> > On Tue, 07 Apr 2020, Bob Paauwe wrote:
> >> From: Stanislav Lisovskiy
> >>
> >> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
> >>
> >> v2: Edited commit message, removed redundant whitespaces.
> >>
> >> v3: Fixed fallthrough logic for the format switch cases.
> >>
> >> v4: Yet again fixed fallthrough logic, to reuse code from other case
> >> labels.
> >>
> >> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> >>
> >> v6: Removed unneeded initializer for new XYUV format.
> >>
> >> v7: Added scaling support for DRM_FORMAT_XYUV
> >>
> >> v8: Edited commit message to be more clear about skl+, renamed
> >> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this
> format
> >> doesn't support per-pixel alpha. Fixed minor code issues.
> >>
> >> v9: Moved DRM format check to proper place in intel_framebuffer_init.
> >>
> >> v10: Added missing XYUV format to sprite planes for skl+.
> >>
> >> v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
> >>
> >> v12: Fixed rebase conflicts
> >>
> >> V13: Rebased.
> >> Added format to ICL format lists.
> >>
> >> V14: Added format to TGL format lists.
> >> Rebased.
> >>
> >> V15: Added format to glk_planar_formats[] and icl_sdr_y_plane_formats[]
> (Ville)
> >> Placed XYUV before XXVYU2101010 to be more consistent (Ville)
> >
> > Okay, so we like to add the changelog of the patch itself to the commit
> > message, but this is ridiculous wrt the patch and the commit
> > message. Whoever ends up applying it, please just nuke the changelog. I
> > don't want that in the logs.
>
> This turned out to be me. Pushed with the commit message cleaned up.
>
> BR,
> Jani.
Thanks Jani! What about the corresponding IGT patch? Did that get pushed too
so that this won't break CI?
https://patchwork.freedesktop.org/series/70516/
Bob
>
>
> >
> > BR,
> > Jani.
> >
> >
> >>
> >> v12:
> >> Reviewed-by: Ville Syrjälä
> >> Reviewed-by: Matt Roper
> >>
> >> Signed-off-by: Stanislav Lisovskiy
> >> Signed-off-by: Bob Paauwe
> >> ---
> >> drivers/gpu/drm/i915/display/intel_display.c | 5 +
> >> drivers/gpu/drm/i915/display/intel_sprite.c | 8
> >> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> >> 3 files changed, 14 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 70ec301fe6e3..3654262570b2 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -3342,6 +3342,8 @@ int skl_format_to_fourcc(int format, bool
> rgb_order, bool alpha)
> >>return DRM_FORMAT_RGB565;
> >>case PLANE_CTL_FORMAT_NV12:
> >>return DRM_FORMAT_NV12;
> >> + case PLANE_CTL_FORMAT_XYUV:
> >> + return DRM_FORMAT_XYUV;
> >>case PLANE_CTL_FORMAT_P010:
> >>return DRM_FORMAT_P010;
> >>case PLANE_CTL_FORMAT_P012:
> >> @@ -4586,6 +4588,8 @@ static u32 skl_plane_ctl_format(u32
> pixel_format)
> >>case DRM_FORMAT_XRGB16161616F:
> >>case DRM_FORMAT_ARGB16161616F:
> >>return PLANE_CTL_FORMAT_XRGB_16161616F;
> >> + case DRM_FORMAT_XYUV:
> >> + return PLANE_CTL_FORMAT_XYUV;
> >>case DRM_FORMAT_YUYV:
> >>return PLANE_CTL_FORMAT_YUV422 |
> PLANE_CTL_YUV422_YUYV;
> >>case DRM_FORMAT_YVYU:
> >> @@ -6175,6 +6179,7 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> >>case DRM_FORMAT_UYVY:
> >>case DRM_FORMAT_VYUY:
> >>case DRM_FORMAT_NV12:
> >> + case DRM_FORMAT_XYUV:
> >>case DRM_FORMAT_P010:
> >>case DRM_FORMAT_P012:
> >>case DRM_FORMAT_P016:
> >> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> >> index deda351719db..1a4377c988f5 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> >> @@ -2503,6 +2503,7 @@ static const u32 skl_plane_formats[] = {
> >>DRM_FORMAT_YVYU,
> >>DRM_FORMAT_UYVY,
> >>DRM_FORMAT_VYUY,
> >> + DRM_FORMAT_XYUV,
> >> };
> >>
> >> static const u32 skl_planar_formats[] = {
> >> @@ -2521,6 +2522,7 @@ static const u32 skl_planar_formats[] = {
> >>DRM_FORMAT_UYVY,
> >>DRM_FORMAT_VYUY,
> >>DRM_FORMAT_NV12,
> >> + DRM_FORMAT_XYUV,
> >> };
> >>
> >> static const u32 glk_planar_formats[] = {
> >> @@ -2539,6 +2541,7 @@ static const u32 glk_planar_formats[] = {
> >>DRM_FORMAT_UYVY,
> >>DRM_FORMAT_VYUY,
> >>DRM_FORMAT_NV12,
> >> + DRM_FORMAT_XYUV,
> >>DRM_FORMAT_P010,
> >>
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/tgl: TBT AUX should use TC power well ops
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: TBT AUX should use TC power
well ops
URL : https://patchwork.freedesktop.org/series/75998/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8305_full -> Patchwork_17319_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17319_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_flip@plain-flip-ts-check@a-edp1}:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-skl1/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-skl3/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html
Known issues
Here are the changes found in Patchwork_17319_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +4 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-kbl6/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-kbl2/igt@gem_exec_susp...@basic-s3.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#54] / [i915#95])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-128x42-sliding.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-128x42-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#300])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-suspend.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109441]) +1 similar
issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-iclb4/igt@kms_psr@psr2_primary_blt.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-apl8/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-apl2/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html
Possible fixes
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][13] ([i915#454]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-iclb1/igt@i915_pm...@dc6-dpms.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-iclb1/igt@i915_pm...@dc6-dpms.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-snb: [SKIP][15] ([fdo#109271]) -> [PASS][16] +3 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-snb6/igt@kms_atomic_transit...@plane-all-modeset-transition-fencing.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-snb1/igt@kms_atomic_transit...@plane-all-modeset-transition-fencing.html
* igt@kms_color@pipe-a-degamma:
- shard-skl: [FAIL][17] ([fdo#108145] / [i915#71]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-skl10/igt@kms_co...@pipe-a-degamma.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-skl5/igt@kms_co...@pipe-a-degamma.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen:
- shard-apl: [FAIL][19] ([i915#54] / [i915#95]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-apl8/igt@kms_cursor_...@pipe-a-cursor-64x21-onscreen.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-64x21-onscreen.html
* igt@kms_cursor_legacy@pipe-b-torture-bo:
- shard-snb: [DMESG-WARN][21] ([i915#128]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/shard-snb2/igt@kms_cursor_leg...@pipe-b-torture-bo.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/shard-snb5/igt@kms_cursor_leg...@pipe-b-torture-bo.html
* {igt@kms_flip@flip-vs-suspend-interruptible@a-dp1}:
- shard-kbl: [INCOMPLETE][23] ([i915#155]) -> [PASS][24]
[23]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt
== Series Details == Series: series starting with [1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt URL : https://patchwork.freedesktop.org/series/76052/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17337 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17337 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17337, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17337/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17337: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17337/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html Known issues Here are the changes found in Patchwork_17337 that come from known issues: ### IGT changes ### Warnings * igt@amdgpu/amd_prime@i915-to-amd: - fi-bwr-2160:[FAIL][3] ([i915#489]) -> [SKIP][4] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17337/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (51 -> 45) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8311 -> Patchwork_17337 CI-20190529: 20190529 CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17337: c4c6f9c67674135fedfdc3ad7158b43188c39aa0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c4c6f9c67674 drm/i915/selftests: Check power consumption at min/max frequencies 11358b42813e drm/i915/selftests: Move gpu energy measurement into its own little lib ee138671a7e5 drm/i915/gt: Use the RPM config register to determine clk frequencies 25ad39d54c1a drm/i915/gt: Trace RPS events 0a7f8f2b844b drm/i915/selftests: Delay spinner before waiting for an interrupt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17337/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt
== Series Details == Series: series starting with [1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt URL : https://patchwork.freedesktop.org/series/76052/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt
== Series Details == Series: series starting with [1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt URL : https://patchwork.freedesktop.org/series/76052/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0a7f8f2b844b drm/i915/selftests: Delay spinner before waiting for an interrupt 25ad39d54c1a drm/i915/gt: Trace RPS events ee138671a7e5 drm/i915/gt: Use the RPM config register to determine clk frequencies -:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #78: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 352 lines checked 11358b42813e drm/i915/selftests: Move gpu energy measurement into its own little lib -:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #79: new file mode 100644 -:109: CHECK:LINE_SPACING: Please don't use multiple blank lines #109: FILE: drivers/gpu/drm/i915/selftests/librapl.c:26: + + total: 0 errors, 1 warnings, 1 checks, 93 lines checked c4c6f9c67674 drm/i915/selftests: Check power consumption at min/max frequencies ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915/selftests: Check power consumption at min/max frequencies
A basic premise of RPS is that at lower frequencies, not only do we run
slower, but we save power compared to higher frequencies. For example,
when idle, we set the minimum frequency just in case there is some
residual current. Since the power curve should be a physical
relationship, if we find no power saving it's likely that we've broken
our frequency handling, so test!
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 132 +++
drivers/gpu/drm/i915/gt/selftest_rps.h | 1 +
3 files changed, 134 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index c50bb502fe03..0141c334f2ac 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -54,6 +54,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
SUBTEST(live_rps_interrupt),
+ SUBTEST(live_rps_power),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 83cc4d1fc5de..0484af708b27 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -3,6 +3,8 @@
* Copyright © 2020 Intel Corporation
*/
+#include
+
#include "intel_engine_pm.h"
#include "intel_gt_clock_utils.h"
#include "intel_gt_pm.h"
@@ -10,6 +12,7 @@
#include "selftest_rps.h"
#include "selftests/igt_flush_test.h"
#include "selftests/igt_spinner.h"
+#include "selftests/librapl.h"
static void dummy_rps_work(struct work_struct *wrk)
{
@@ -228,3 +231,132 @@ int live_rps_interrupt(void *arg)
return err;
}
+
+static u64 __measure_power(int duration_ms)
+{
+ u64 dE, dt;
+
+ dt = ktime_get();
+ dE = librapl_energy_uJ();
+ usleep_range(1000 * duration_ms, 2000 * duration_ms);
+ dE = librapl_energy_uJ() - dE;
+ dt = ktime_get() - dt;
+
+ return div64_u64(1000 * 1000 * dE, dt);
+}
+
+static int cmp_u64(const void *A, const void *B)
+{
+ const u64 *a = A, *b = B;
+
+ if (a < b)
+ return -1;
+ else if (a > b)
+ return 1;
+ else
+ return 0;
+}
+
+static u64 measure_power_at(struct intel_rps *rps, int freq)
+{
+ u64 x[5];
+ int i;
+
+ mutex_lock(>lock);
+ GEM_BUG_ON(!rps->active);
+ intel_rps_set(rps, freq);
+ mutex_unlock(>lock);
+
+ msleep(20); /* more than enough time to stabilise! */
+
+ for (i = 0; i < 5; i++)
+ x[i] = __measure_power(5);
+
+ /* A simple triangle filter for better result stability */
+ sort(x, 5, sizeof(*x), cmp_u64, NULL);
+ return div_u64(x[1] + 2 * x[2] + x[3], 4);
+}
+
+int live_rps_power(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_rps *rps = >rps;
+ void (*saved_work)(struct work_struct *wrk);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ int err = 0;
+
+ /*
+* Our fundamental assumption is that running at lower frequency
+* actually saves power. Let's see if our RAPL measurement support
+* that theory.
+*/
+
+ if (!rps->enabled || rps->max_freq <= rps->min_freq)
+ return 0;
+
+ if (!librapl_energy_uJ())
+ return 0;
+
+ if (igt_spinner_init(, gt))
+ return -ENOMEM;
+
+ intel_gt_pm_wait_for_idle(gt);
+ saved_work = rps->work.func;
+ rps->work.func = dummy_rps_work;
+
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq;
+ u64 min, max;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ rq = igt_spinner_create_request(,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ intel_gt_set_wedged(engine->gt);
+ err = -EIO;
+ break;
+ }
+
+ max = measure_power_at(rps, rps->max_freq);
+ min = measure_power_at(rps, rps->min_freq);
+
+ igt_spinner_end();
+
+ pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n",
+ engine->name,
+ min,
[Intel-gfx] [PATCH 3/5] drm/i915/gt: Use the RPM config register to determine clk frequencies
For many configuration details within RC6 and RPS we are programming
intervals for the internal clocks. From gen11, these clocks are
configuration via the RPM_CONFIG and so for convenience, we would like
to convert to/from more natural units (ns).
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Cc: Mika Kuoppala
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 27 ---
.../gpu/drm/i915/gt/intel_gt_clock_utils.c| 78 +++
.../gpu/drm/i915/gt/intel_gt_clock_utils.h| 21 +
drivers/gpu/drm/i915/gt/intel_rps.c | 40 ++
drivers/gpu/drm/i915/gt/selftest_rps.c| 7 +-
drivers/gpu/drm/i915/i915_debugfs.c | 34 +---
drivers/gpu/drm/i915/i915_reg.h | 25 --
8 files changed, 167 insertions(+), 66 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44c506b7e117..8f6fb9360fbe 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -91,6 +91,7 @@ gt-y += \
gt/intel_ggtt.o \
gt/intel_ggtt_fencing.o \
gt/intel_gt.o \
+ gt/intel_gt_clock_utils.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index aab30d908072..d4e3b4c0c48f 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -10,6 +10,7 @@
#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt.h"
+#include "intel_gt_clock_utils.h"
#include "intel_llc.h"
#include "intel_rc6.h"
#include "intel_rps.h"
@@ -394,21 +395,23 @@ static int frequency_show(struct seq_file *m, void
*unused)
seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
seq_printf(m, "CAGF: %dMHz\n", cagf);
- seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
- rpupei, GT_PM_INTERVAL_TO_US(i915, rpupei));
- seq_printf(m, "RP CUR UP: %d (%dus)\n",
- rpcurup, GT_PM_INTERVAL_TO_US(i915, rpcurup));
- seq_printf(m, "RP PREV UP: %d (%dus)\n",
- rpprevup, GT_PM_INTERVAL_TO_US(i915, rpprevup));
+ seq_printf(m, "RP CUR UP EI: %d (%dns)\n",
+ rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
+ seq_printf(m, "RP CUR UP: %d (%dns)\n",
+ rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
+ seq_printf(m, "RP PREV UP: %d (%dns)\n",
+ rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
seq_printf(m, "Up threshold: %d%%\n",
rps->power.up_threshold);
- seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
- rpdownei, GT_PM_INTERVAL_TO_US(i915, rpdownei));
- seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
- rpcurdown, GT_PM_INTERVAL_TO_US(i915, rpcurdown));
- seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
- rpprevdown, GT_PM_INTERVAL_TO_US(i915, rpprevdown));
+ seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n",
+ rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
+ seq_printf(m, "RP CUR DOWN: %d (%dns)\n",
+ rpcurdown,
+ intel_gt_pm_interval_to_ns(gt, rpcurdown));
+ seq_printf(m, "RP PREV DOWN: %d (%dns)\n",
+ rpprevdown,
+ intel_gt_pm_interval_to_ns(gt, rpprevdown));
seq_printf(m, "Down threshold: %d%%\n",
rps->power.down_threshold);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
new file mode 100644
index ..e63e400ee1c5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt.h"
+#include "intel_gt_clock_utils.h"
+
+#define MHZ_19_2 1920 /* 19.2MHz, 52.083ns */
+#define MHZ_24 2400 /* 24MHz, 83.333ns */
+#define MHZ_25 2500 /* 25MHz, 80ns */
+
+u32 intel_gt_clock_frequency(struct intel_gt *gt)
+{
+ if (INTEL_GEN(gt->i915) >= 11) {
+ u32 config;
+
+ config = intel_uncore_read(gt->uncore, RPM_CONFIG0);
+ config &= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
+ config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+
+ switch (config) {
+ case 0: return
[Intel-gfx] [PATCH 1/5] drm/i915/selftests: Delay spinner before waiting for an interrupt
It seems that although (perhaps because of the memory stall?) the
spinner has signaled that it has started, it still takes some time to
spin up to 100% utilisation of the HW. Since the test depends on the
full utilisation of the HW to trigger the RPS interrupt, wait a little
bit and flush the interrupt status to be sure that the event we see if
from the spinner.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_rps.c | 28 +++---
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 26aadc2ae3be..199d608aa763 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -14,6 +14,20 @@ static void dummy_rps_work(struct work_struct *wrk)
{
}
+static void sleep_for_ei(struct intel_rps *rps, int timeout_us)
+{
+ /* Flush any previous EI */
+ usleep_range(timeout_us, 2 * timeout_us);
+
+ /* Reset the interrupt status */
+ rps_disable_interrupts(rps);
+ GEM_BUG_ON(rps->pm_iir);
+ rps_enable_interrupts(rps);
+
+ /* And then wait for the timeout, for real this time */
+ usleep_range(2 * timeout_us, 3 * timeout_us);
+}
+
static int __rps_up_interrupt(struct intel_rps *rps,
struct intel_engine_cs *engine,
struct igt_spinner *spin)
@@ -28,7 +42,6 @@ static int __rps_up_interrupt(struct intel_rps *rps,
intel_gt_pm_wait_for_idle(engine->gt);
GEM_BUG_ON(rps->active);
- rps->pm_iir = 0;
rps->cur_freq = rps->min_freq;
rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP);
@@ -71,7 +84,7 @@ static int __rps_up_interrupt(struct intel_rps *rps,
timeout = intel_uncore_read(uncore, GEN6_RP_UP_EI);
timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
- usleep_range(2 * timeout, 3 * timeout);
+ sleep_for_ei(rps, timeout);
GEM_BUG_ON(i915_request_completed(rq));
igt_spinner_end(spin);
@@ -122,16 +135,7 @@ static int __rps_down_interrupt(struct intel_rps *rps,
timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
- /* Flush any previous EI */
- usleep_range(timeout, 2 * timeout);
-
- /* Reset the interrupt status */
- rps_disable_interrupts(rps);
- GEM_BUG_ON(rps->pm_iir);
- rps_enable_interrupts(rps);
-
- /* And then wait for the timeout, for real this time */
- usleep_range(2 * timeout, 3 * timeout);
+ sleep_for_ei(rps, timeout);
if (rps->cur_freq != rps->max_freq) {
pr_err("%s: Frequency unexpectedly changed [down], now %d!\n",
--
2.20.1
___
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[Intel-gfx] [PATCH 4/5] drm/i915/selftests: Move gpu energy measurement into its own little lib
Move the handy utility to measure the GPU energy consumption using RAPL
msr into a common lib so that it can be reused easily.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 3 ++-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 25 +--
drivers/gpu/drm/i915/selftests/librapl.c | 26
drivers/gpu/drm/i915/selftests/librapl.h | 13
4 files changed, 46 insertions(+), 21 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/librapl.c
create mode 100644 drivers/gpu/drm/i915/selftests/librapl.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8f6fb9360fbe..ce24a4ee9591 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/igt_live_test.o \
selftests/igt_mmap.o \
selftests/igt_reset.o \
- selftests/igt_spinner.o
+ selftests/igt_spinner.o \
+ selftests/librapl.o
# virtual gpu code
i915-y += i915_vgpu.o
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 08c3dbd41b12..2dc460624bbc 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -11,22 +11,7 @@
#include "selftest_rc6.h"
#include "selftests/i915_random.h"
-
-static u64 energy_uJ(struct intel_rc6 *rc6)
-{
- unsigned long long power;
- u32 units;
-
- if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, ))
- return 0;
-
- units = (power & 0x1f00) >> 8;
-
- if (rdmsrl_safe(MSR_PP1_ENERGY_STATUS, ))
- return 0;
-
- return (100 * power) >> units; /* convert to uJ */
-}
+#include "selftests/librapl.h"
static u64 rc6_residency(struct intel_rc6 *rc6)
{
@@ -74,9 +59,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
dt = ktime_get();
- rc0_power = energy_uJ(rc6);
+ rc0_power = librapl_energy_uJ();
msleep(250);
- rc0_power = energy_uJ(rc6) - rc0_power;
+ rc0_power = librapl_energy_uJ() - rc0_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if ((res[1] - res[0]) >> 10) {
@@ -99,9 +84,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
intel_uncore_forcewake_flush(rc6_to_uncore(rc6), FORCEWAKE_ALL);
dt = ktime_get();
- rc6_power = energy_uJ(rc6);
+ rc6_power = librapl_energy_uJ();
msleep(100);
- rc6_power = energy_uJ(rc6) - rc6_power;
+ rc6_power = librapl_energy_uJ() - rc6_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if (res[1] == res[0]) {
diff --git a/drivers/gpu/drm/i915/selftests/librapl.c
b/drivers/gpu/drm/i915/selftests/librapl.c
new file mode 100644
index ..5e21e55fae91
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/librapl.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include
+
+#include "librapl.h"
+
+u64 librapl_energy_uJ(void)
+{
+ unsigned long long power;
+ u32 units;
+
+ if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, ))
+ return 0;
+
+ units = (power & 0x1f00) >> 8;
+
+ if (rdmsrl_safe(MSR_PP1_ENERGY_STATUS, ))
+ return 0;
+
+ return (100 * power) >> units; /* convert to uJ */
+}
+
+
diff --git a/drivers/gpu/drm/i915/selftests/librapl.h
b/drivers/gpu/drm/i915/selftests/librapl.h
new file mode 100644
index ..887f3e91dd05
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/librapl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef SELFTEST_LIBRAPL_H
+#define SELFTEST_LIBRAPL_H
+
+#include
+
+u64 librapl_energy_uJ(void);
+
+#endif /* SELFTEST_LIBRAPL_H */
--
2.20.1
___
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[Intel-gfx] [PATCH 2/5] drm/i915/gt: Trace RPS events
Add tracek to the RPS events (interrupts, worker, enabling, threshold
selection, frequency setting), so that if we have to debug reticent HW
we have some traces to start from.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 47 ++---
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 4dcfae16a7ce..42275e25ea1b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -82,6 +82,8 @@ static void rps_enable_interrupts(struct intel_rps *rps)
GEN6_PM_RP_DOWN_THRESHOLD |
GEN6_PM_RP_DOWN_TIMEOUT);
WRITE_ONCE(rps->pm_events, events);
+ GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",
+events, rps_pm_mask(rps, rps->last_freq));
spin_lock_irq(>irq_lock);
gen6_gt_pm_enable_irq(gt, rps->pm_events);
@@ -140,6 +142,7 @@ static void rps_disable_interrupts(struct intel_rps *rps)
cancel_work_sync(>work);
rps_reset_interrupts(rps);
+ GT_TRACE(gt, "interrupts:off\n");
}
static const struct cparams {
@@ -581,6 +584,10 @@ static void rps_set_power(struct intel_rps *rps, int
new_power)
if (IS_VALLEYVIEW(i915))
goto skip_hw_write;
+ GT_TRACE(rps_to_gt(rps),
+"changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n",
+new_power, threshold_up, ei_up, threshold_down, ei_down);
+
set(uncore, GEN6_RP_UP_EI, GT_INTERVAL_FROM_US(i915, ei_up));
set(uncore, GEN6_RP_UP_THRESHOLD,
GT_INTERVAL_FROM_US(i915, ei_up * threshold_up / 100));
@@ -645,6 +652,8 @@ static void gen6_rps_set_thresholds(struct intel_rps *rps,
u8 val)
void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive)
{
+ GT_TRACE(rps_to_gt(rps), "mark interactive: %s\n", yesno(interactive));
+
mutex_lock(>power.mutex);
if (interactive) {
if (!rps->power.interactive++ && READ_ONCE(rps->active))
@@ -672,6 +681,9 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
GEN6_AGGRESSIVE_TURBO);
set(uncore, GEN6_RPNSWREQ, swreq);
+ GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d, swreq:%x\n",
+val, intel_gpu_freq(rps, val), swreq);
+
return 0;
}
@@ -684,6 +696,9 @@ static int vlv_rps_set(struct intel_rps *rps, u8 val)
err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val);
vlv_punit_put(i915);
+ GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n",
+val, intel_gpu_freq(rps, val));
+
return err;
}
@@ -717,6 +732,8 @@ void intel_rps_unpark(struct intel_rps *rps)
if (!rps->enabled)
return;
+ GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq);
+
/*
* Use the user's desired frequency as a guide, but for better
* performance, jump directly to RPe as our starting frequency.
@@ -784,6 +801,8 @@ void intel_rps_park(struct intel_rps *rps)
*/
rps->cur_freq =
max_t(int, round_down(rps->cur_freq - 1, 2), rps->min_freq);
+
+ GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq);
}
void intel_rps_boost(struct i915_request *rq)
@@ -800,6 +819,9 @@ void intel_rps_boost(struct i915_request *rq)
!dma_fence_is_signaled_locked(>fence)) {
set_bit(I915_FENCE_FLAG_BOOST, >fence.flags);
+ GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n",
+rq->fence.context, rq->fence.seqno);
+
if (!atomic_fetch_inc(>num_waiters) &&
READ_ONCE(rps->cur_freq) < rps->boost_freq)
schedule_work(>work);
@@ -895,6 +917,7 @@ static void gen6_rps_init(struct intel_rps *rps)
static bool rps_reset(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
+
/* force a reset */
rps->power.mode = -1;
rps->last_freq = -1;
@@ -1215,11 +1238,17 @@ void intel_rps_enable(struct intel_rps *rps)
if (!rps->enabled)
return;
- drm_WARN_ON(>drm, rps->max_freq < rps->min_freq);
- drm_WARN_ON(>drm, rps->idle_freq > rps->max_freq);
+ GT_TRACE(rps_to_gt(rps),
+"min:%x, max:%x, freq:[%d, %d]\n",
+rps->min_freq, rps->max_freq,
+intel_gpu_freq(rps, rps->min_freq),
+intel_gpu_freq(rps, rps->max_freq));
+
+ GEM_BUG_ON(rps->max_freq < rps->min_freq);
+ GEM_BUG_ON(rps->idle_freq > rps->max_freq);
- drm_WARN_ON(>drm, rps->efficient_freq < rps->min_freq);
- drm_WARN_ON(>drm, rps->efficient_freq > rps->max_freq);
+ GEM_BUG_ON(rps->efficient_freq < rps->min_freq);
+ GEM_BUG_ON(rps->efficient_freq > rps->max_freq);
}
static void gen6_rps_disable(struct
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Delay spinner before waiting for an interrupt
== Series Details == Series: drm/i915/selftests: Delay spinner before waiting for an interrupt URL : https://patchwork.freedesktop.org/series/76049/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17336 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17336 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17336, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17336/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17336: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_pm: - fi-icl-dsi: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-icl-dsi/igt@i915_selftest@live@gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17336/fi-icl-dsi/igt@i915_selftest@live@gt_pm.html Known issues Here are the changes found in Patchwork_17336 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_lrc: - fi-bwr-2160:[PASS][3] -> [INCOMPLETE][4] ([i915#489]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@i915_selftest@live@gt_lrc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17336/fi-bwr-2160/igt@i915_selftest@live@gt_lrc.html [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (51 -> 45) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8311 -> Patchwork_17336 CI-20190529: 20190529 CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17336: d722040ae4012aacab0abd580d631b410ffee6f7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d722040ae401 drm/i915/selftests: Delay spinner before waiting for an interrupt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17336/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/selftests: Delay spinner before waiting for an interrupt
== Series Details == Series: drm/i915/selftests: Delay spinner before waiting for an interrupt URL : https://patchwork.freedesktop.org/series/76049/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Check power consumption at min/max frequencies
Hi Chris,
> +static u64 __measure_power(int duration_ms)
> +{
> + u64 nrg, dt;
> +
> + dt = -ktime_get();
> + nrg = -st_energy_uJ();
> + msleep(5);
usleep_range?
Reviewed-by: Andi Shyti
Thanks,
Andi
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Wa_14011059788 (rev2)
== Series Details ==
Series: drm/i915/tgl: Wa_14011059788 (rev2)
URL : https://patchwork.freedesktop.org/series/75990/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8304_full -> Patchwork_17318_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17318_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17318_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17318_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_persistence@smoketest:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-tglb7/igt@gem_ctx_persiste...@smoketest.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-tglb2/igt@gem_ctx_persiste...@smoketest.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2}:
- shard-glk: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-glk9/igt@kms_flip@flip-vs-expired-vbl...@c-hdmi-a2.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-glk7/igt@kms_flip@flip-vs-expired-vbl...@c-hdmi-a2.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-edp1}:
- shard-skl: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-skl6/igt@kms_flip@flip-vs-suspend-interrupti...@c-edp1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-skl9/igt@kms_flip@flip-vs-suspend-interrupti...@c-edp1.html
Known issues
Here are the changes found in Patchwork_17318_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#69]) +1 similar
issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-skl9/igt@gem_...@in-flight-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-skl8/igt@gem_...@in-flight-suspend.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +1 similar
issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-kbl1/igt@gem_soft...@noreloc-s3.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-kbl2/igt@gem_soft...@noreloc-s3.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#54])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-glk7/igt@kms_cursor_...@pipe-b-cursor-128x128-offscreen.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-glk5/igt@kms_cursor_...@pipe-b-cursor-128x128-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-apl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-apl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-hsw: [PASS][15] -> [SKIP][16] ([fdo#109271])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-hsw1/igt@kms_cursor_leg...@2x-cursor-vs-flip-atomic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-hsw7/igt@kms_cursor_leg...@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@all-pipes-torture-bo:
- shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([i915#128])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-hsw4/igt@kms_cursor_leg...@all-pipes-torture-bo.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-hsw6/igt@kms_cursor_leg...@all-pipes-torture-bo.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [PASS][19] -> [FAIL][20] ([IGT#5])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-skl1/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/shard-skl4/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#173])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/shard-iclb5/igt@kms_psr@no_drrs.html
[22]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add missing deinitialization cases of load failure (rev2)
== Series Details == Series: drm/i915: Add missing deinitialization cases of load failure (rev2) URL : https://patchwork.freedesktop.org/series/75987/ State : success == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17335 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17335/index.html Known issues Here are the changes found in Patchwork_17335 that come from known issues: ### IGT changes ### Warnings * igt@amdgpu/amd_prime@i915-to-amd: - fi-bwr-2160:[FAIL][1] ([i915#489]) -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17335/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (51 -> 45) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8311 -> Patchwork_17335 CI-20190529: 20190529 CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17335: a685f486207f33975db8675f8155bc88cd8180ce @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a685f486207f drm/i915: Add missing deinitialization cases of load failure == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17335/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Use the RPM config register to determine clk frequencies
Hi Chris, On Thu, Apr 16, 2020 at 09:33:52PM +0100, Chris Wilson wrote: > Quoting Andi Shyti (2020-04-16 21:31:10) > > Hi Chris, > > > > > For many configuration details within RC6 and RPS we are programming > > > intervals for the internal clocks. From gen11, these clocks are > > > configuration via the RPM_CONFIG and so for convenience, we would like > > > to convert to/from more natural units (ns). > > > > > > Signed-off-by: Chris Wilson > > > Cc: Andi Shyti > > > Cc: Mika Kuoppala > > > --- > > > drivers/gpu/drm/i915/Makefile | 1 + > > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 27 + > > > drivers/gpu/drm/i915/gt/intel_gt_clk.c | 76 + > > > drivers/gpu/drm/i915/gt/intel_gt_clk.h | 21 +++ > > > drivers/gpu/drm/i915/gt/intel_rps.c | 37 +++- > > > drivers/gpu/drm/i915/gt/selftest_rps.c | 6 +- > > > drivers/gpu/drm/i915/i915_debugfs.c | 34 +++ > > > drivers/gpu/drm/i915/i915_reg.h | 25 > > > 8 files changed, 161 insertions(+), 66 deletions(-) > > > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.c > > > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.h > > > > I like the patch, it's a nice refactoring but the file name is > > misleading. When I see a *clk.[ch] file I think of a clock device > > rather than a set of utilities for frequency and interval > > conversion. > > > > Can we call the file intel_gt_timing.[ch] or clk_utils.[ch]? > > clk_utils.c > > It started off with the idea of just doing the clock probing, but the > utility routines were more practical. Reviewed-by: Andi Shyti Thank you, Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Use the RPM config register to determine clk frequencies
Quoting Andi Shyti (2020-04-16 21:31:10) > Hi Chris, > > > For many configuration details within RC6 and RPS we are programming > > intervals for the internal clocks. From gen11, these clocks are > > configuration via the RPM_CONFIG and so for convenience, we would like > > to convert to/from more natural units (ns). > > > > Signed-off-by: Chris Wilson > > Cc: Andi Shyti > > Cc: Mika Kuoppala > > --- > > drivers/gpu/drm/i915/Makefile | 1 + > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 27 + > > drivers/gpu/drm/i915/gt/intel_gt_clk.c | 76 + > > drivers/gpu/drm/i915/gt/intel_gt_clk.h | 21 +++ > > drivers/gpu/drm/i915/gt/intel_rps.c | 37 +++- > > drivers/gpu/drm/i915/gt/selftest_rps.c | 6 +- > > drivers/gpu/drm/i915/i915_debugfs.c | 34 +++ > > drivers/gpu/drm/i915/i915_reg.h | 25 > > 8 files changed, 161 insertions(+), 66 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.c > > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.h > > I like the patch, it's a nice refactoring but the file name is > misleading. When I see a *clk.[ch] file I think of a clock device > rather than a set of utilities for frequency and interval > conversion. > > Can we call the file intel_gt_timing.[ch] or clk_utils.[ch]? clk_utils.c It started off with the idea of just doing the clock probing, but the utility routines were more practical. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Use the RPM config register to determine clk frequencies
Hi Chris, > For many configuration details within RC6 and RPS we are programming > intervals for the internal clocks. From gen11, these clocks are > configuration via the RPM_CONFIG and so for convenience, we would like > to convert to/from more natural units (ns). > > Signed-off-by: Chris Wilson > Cc: Andi Shyti > Cc: Mika Kuoppala > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 27 + > drivers/gpu/drm/i915/gt/intel_gt_clk.c | 76 + > drivers/gpu/drm/i915/gt/intel_gt_clk.h | 21 +++ > drivers/gpu/drm/i915/gt/intel_rps.c | 37 +++- > drivers/gpu/drm/i915/gt/selftest_rps.c | 6 +- > drivers/gpu/drm/i915/i915_debugfs.c | 34 +++ > drivers/gpu/drm/i915/i915_reg.h | 25 > 8 files changed, 161 insertions(+), 66 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.c > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.h I like the patch, it's a nice refactoring but the file name is misleading. When I see a *clk.[ch] file I think of a clock device rather than a set of utilities for frequency and interval conversion. Can we call the file intel_gt_timing.[ch] or clk_utils.[ch]? Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Add missing deinitialization cases of load failure (rev2)
== Series Details == Series: drm/i915: Add missing deinitialization cases of load failure (rev2) URL : https://patchwork.freedesktop.org/series/75987/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add missing deinitialization cases of load failure (rev2)
== Series Details == Series: drm/i915: Add missing deinitialization cases of load failure (rev2) URL : https://patchwork.freedesktop.org/series/75987/ State : warning == Summary == $ dim checkpatch origin/drm-tip a685f486207f drm/i915: Add missing deinitialization cases of load failure -:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #17: [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context workarounds on rcs'0 total: 0 errors, 1 warnings, 0 checks, 73 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/selftests: Move gpu energy measurement into its own little lib
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Move gpu energy measurement into its own little lib URL : https://patchwork.freedesktop.org/series/76044/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17334 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17334 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17334, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17334: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_pm: - fi-bsw-n3050: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html - fi-bsw-nick:[PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html - fi-byt-n2820: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-byt-n2820/igt@i915_selftest@live@gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/fi-byt-n2820/igt@i915_selftest@live@gt_pm.html - fi-bsw-kefka: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html - fi-kbl-soraka: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html - fi-byt-j1900: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-byt-j1900/igt@i915_selftest@live@gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/fi-byt-j1900/igt@i915_selftest@live@gt_pm.html Known issues Here are the changes found in Patchwork_17334 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@late_gt_pm: - fi-bsw-kefka: [PASS][13] -> [INCOMPLETE][14] ([i915#1382]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bsw-kefka/igt@i915_selftest@live@late_gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/fi-bsw-kefka/igt@i915_selftest@live@late_gt_pm.html Warnings * igt@amdgpu/amd_prime@i915-to-amd: - fi-bwr-2160:[FAIL][15] ([i915#489]) -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1382]: https://gitlab.freedesktop.org/drm/intel/issues/1382 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (51 -> 44) -- Missing(7): fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8311 -> Patchwork_17334 CI-20190529: 20190529 CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17334: 05b16cdfef39c7101e890d23a9af07105c9210ba @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 05b16cdfef39 drm/i915/selftests: Check power consumption at min/max frequencies 04da6c2d287e drm/i915/selftests: Move gpu energy measurement into its own little lib == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17334/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Delay spinner before waiting for an interrupt
It seems that although (perhaps because of the memory stall?) the
spinner has signaled that it has started, it still takes some time to
spin up to 100% utilisation of the HW. Since the test depends on the
full utilisation of the HW to trigger the RPS interrupt, wait a little
bit and flush the interrupt status to be sure that the event we see if
from the spinner.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_rps.c | 28 +++---
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 26aadc2ae3be..199d608aa763 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -14,6 +14,20 @@ static void dummy_rps_work(struct work_struct *wrk)
{
}
+static void sleep_for_ei(struct intel_rps *rps, int timeout_us)
+{
+ /* Flush any previous EI */
+ usleep_range(timeout_us, 2 * timeout_us);
+
+ /* Reset the interrupt status */
+ rps_disable_interrupts(rps);
+ GEM_BUG_ON(rps->pm_iir);
+ rps_enable_interrupts(rps);
+
+ /* And then wait for the timeout, for real this time */
+ usleep_range(2 * timeout_us, 3 * timeout_us);
+}
+
static int __rps_up_interrupt(struct intel_rps *rps,
struct intel_engine_cs *engine,
struct igt_spinner *spin)
@@ -28,7 +42,6 @@ static int __rps_up_interrupt(struct intel_rps *rps,
intel_gt_pm_wait_for_idle(engine->gt);
GEM_BUG_ON(rps->active);
- rps->pm_iir = 0;
rps->cur_freq = rps->min_freq;
rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP);
@@ -71,7 +84,7 @@ static int __rps_up_interrupt(struct intel_rps *rps,
timeout = intel_uncore_read(uncore, GEN6_RP_UP_EI);
timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
- usleep_range(2 * timeout, 3 * timeout);
+ sleep_for_ei(rps, timeout);
GEM_BUG_ON(i915_request_completed(rq));
igt_spinner_end(spin);
@@ -122,16 +135,7 @@ static int __rps_down_interrupt(struct intel_rps *rps,
timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
- /* Flush any previous EI */
- usleep_range(timeout, 2 * timeout);
-
- /* Reset the interrupt status */
- rps_disable_interrupts(rps);
- GEM_BUG_ON(rps->pm_iir);
- rps_enable_interrupts(rps);
-
- /* And then wait for the timeout, for real this time */
- usleep_range(2 * timeout, 3 * timeout);
+ sleep_for_ei(rps, timeout);
if (rps->cur_freq != rps->max_freq) {
pr_err("%s: Frequency unexpectedly changed [down], now %d!\n",
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/selftests: Move gpu energy measurement into its own little lib
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Move gpu energy measurement into its own little lib URL : https://patchwork.freedesktop.org/series/76044/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Move gpu energy measurement into its own little lib
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Move gpu energy measurement into its own little lib URL : https://patchwork.freedesktop.org/series/76044/ State : warning == Summary == $ dim checkpatch origin/drm-tip 04da6c2d287e drm/i915/selftests: Move gpu energy measurement into its own little lib -:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #79: new file mode 100644 -:109: CHECK:LINE_SPACING: Please don't use multiple blank lines #109: FILE: drivers/gpu/drm/i915/selftests/librapl.c:26: + + total: 0 errors, 1 warnings, 1 checks, 93 lines checked 05b16cdfef39 drm/i915/selftests: Check power consumption at min/max frequencies -:61: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst #61: FILE: drivers/gpu/drm/i915/gt/selftest_rps.c:234: + msleep(5); total: 0 errors, 1 warnings, 0 checks, 157 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Document locking guidelines
Acked-by: Dave Airlie On Tue, 5 Nov 2019 at 21:06, Joonas Lahtinen wrote: > > Dave, ping for Acked-by here so we can merge? You already gave an > early ack in IRC while travelling. > > Regards, Joonas > > Quoting Joonas Lahtinen (2019-08-30 13:50:53) > > To ensure cross-driver locking compatibility, document the expected > > guidelines for implementing the GEM locking in i915. Note that this > > is a description of how things should end up after being reworked, > > and does not reflect the current state of things. > > > > Signed-off-by: Joonas Lahtinen > > Signed-off-by: Daniel Vetter > > Signed-off-by: Chris Wilson > > Cc: Dave Airlie > > Cc: Matthew Auld > > Cc: Abdiel Janulgue > > Cc: CQ Tang > > --- > > Documentation/gpu/i915.rst | 45 ++ > > 1 file changed, 45 insertions(+) > > > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > > index e249ea7b0ec7..63a72d10f2c7 100644 > > --- a/Documentation/gpu/i915.rst > > +++ b/Documentation/gpu/i915.rst > > @@ -320,6 +320,51 @@ for execution also include a list of all locations > > within buffers that > > refer to GPU-addresses so that the kernel can edit the buffer correctly. > > This process is dubbed relocation. > > > > +Locking Guidelines > > +-- > > + > > +**NOTE:** This is a description of how the locking should be after > > +refactoring is done. Does not necessarily reflect what the locking > > +looks like while WIP. > > + > > +#. All locking rules and interface contracts with cross-driver interfaces > > + (dma-buf, dma_fence) need to be followed. > > + > > +#. No struct_mutex anywhere in the code > > + > > +#. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx > > + is to be hoisted at highest level and passed down within i915_gem_ctx > > + in the call chain > > + > > +#. While holding lru/memory manager (buddy, drm_mm, whatever) locks > > + system memory allocations are not allowed > > + > > + * Enforce this by priming lockdep (with fs_reclaim). If we > > + allocate memory while holding these looks we get a rehash > > + of the shrinker vs. struct_mutex saga, and that would be > > + real bad. > > + > > +#. Do not nest different lru/memory manager locks within each other. > > + Take them in turn to update memory allocations, relying on the object’s > > + dma_resv ww_mutex to serialize against other operations. > > + > > +#. The suggestion for lru/memory managers locks is that they are small > > + enough to be spinlocks. > > + > > +#. All features need to come with exhaustive kernel selftests and/or > > + IGT tests when appropriate > > + > > +#. All LMEM uAPI paths need to be fully restartable (_interruptible() > > + for all locks/waits/sleeps) > > + > > + * Error handling validation through signal injection. > > + Still the best strategy we have for validating GEM uAPI > > + corner cases. > > + Must be excessively used in the IGT, and we need to check > > + that we really have full path coverage of all error cases. > > + > > + * -EDEADLK handling with ww_mutex > > + > > GEM BO Management Implementation Details > > > > > > -- > > 2.20.1 > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Add request throughput measurement to perf (rev3)
== Series Details == Series: drm/i915/selftests: Add request throughput measurement to perf (rev3) URL : https://patchwork.freedesktop.org/series/73930/ State : success == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17333 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17333/index.html Known issues Here are the changes found in Patchwork_17333 that come from known issues: ### IGT changes ### Warnings * igt@amdgpu/amd_prime@i915-to-amd: - fi-bwr-2160:[FAIL][1] ([i915#489]) -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17333/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (51 -> 45) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8311 -> Patchwork_17333 CI-20190529: 20190529 CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17333: a685a79c5061a4efa3544cc89007601d80f554f9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a685a79c5061 drm/i915/selftests: Add request throughput measurement to perf == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17333/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Add missing deinitialization cases of load failure
On Wed, 2020-04-15 at 20:36 +0100, Chris Wilson wrote: > Quoting José Roberto de Souza (2020-04-15 20:14:08) > > + i915_reset_error_state(i915); > > If you are bored, we should move this to unregister as that is the > last > point at which it can be accessed from userspace. Hopefully I > remember > next time we are rearranging this sequence. What if some error happen up to i915_gem_driver_remove()? We would leak a i915_gpu_coredump. Looks to me that i915_reset_error_state() should be called after i915_gem_driver_remove(). > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/selftests: Add request throughput measurement to perf (rev3)
== Series Details == Series: drm/i915/selftests: Add request throughput measurement to perf (rev3) URL : https://patchwork.freedesktop.org/series/73930/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915: Add missing deinitialization cases of load failure
The intel_display_power_put_async() used in TC cold sequences made easy to hit the missing deinitialization of driver in case of load failure as seen in the stack trace bellow. intel_modeset_driver_remove_noirq() had to be removed from i915_driver_modeset_remove_noirq() as those are different initialialition steps with IRQ and GEM initialization in between then. [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context workarounds on rcs'0 [drm:__i915_inject_probe_error [i915]] Injecting failure -19 at checkpoint 36 [__uc_init:294] [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:275:DDI A] VDD off [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x PP_CONTROL: 0x0060 [drm:intel_power_well_disable [i915]] disabling AUX A general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: G U 5.6.0-CI-Patchwork_17226+ #1 Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 Workqueue: events_unbound intel_display_power_put_async_work [i915] RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 RSP: 0018:c961fdb0 EFLAGS: 00010206 RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d RDX: 8001 RSI: RDI: RBP: 888479be R08: 88849a180920 R09: R10: R11: R12: a0414480 R13: 2000 R14: 888479beb320 R15: 2000 FS: () GS:88849ff8() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 5634fa8ed670 CR3: 05610004 CR4: 00760ee0 PKRU: 5554 Call Trace: release_async_put_domains+0x9b/0x110 [i915] intel_display_power_put_async_work+0x91/0xf0 [i915] process_one_work+0x260/0x600 ? worker_thread+0xc9/0x380 worker_thread+0x37/0x380 ? process_one_work+0x600/0x600 kthread+0x119/0x130 ? kthread_park+0x80/0x80 ret_from_fork+0x24/0x50 Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul cdc_ether usbnet mii snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec snd_hwdep snd_hda_core e1000e ptp mei_me snd_pcm pps_core mei intel_lpss_pci prime_numbers [last unloaded: i915] ---[ end trace b402d1b4060f8b97 ]--- BUG: sleeping function called from invalid context at kernel/sched/completion.c:99 in_atomic(): 0, irqs_disabled(): 0, non_block: 0, pid: 1142, name: kworker/u16:20 INFO: lockdep is turned off. Preemption disabled at: [<>] 0x0 CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: G UD 5.6.0-CI-Patchwork_17226+ #1 Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 Workqueue: events_unbound intel_display_power_put_async_work [i915] Call Trace: dump_stack+0x71/0x9b ___might_sleep+0x178/0x260 wait_for_completion+0x37/0x1a0 virt_efi_query_variable_info+0x161/0x1b0 efi_query_variable_store+0xb3/0x1a0 ? efivar_entry_set_safe+0x19c/0x220 efivar_entry_set_safe+0x19c/0x220 ? efi_pstore_write+0x10b/0x150 ? efi_pstore_write+0xa0/0x150 efi_pstore_write+0x10b/0x150 pstore_dump+0x123/0x340 kmsg_dump+0x87/0x1b0 oops_end+0x3e/0x90 do_general_protection+0x1c3/0x2f0 general_protection+0x2d/0x40 RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 RSP: 0018:c961fdb0 EFLAGS: 00010206 RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d RDX: 8001 RSI: RDI: RBP: 888479be R08: 88849a180920 R09: R10: R11: R12: a0414480 R13: 2000 R14: 888479beb320 R15: 2000 release_async_put_domains+0x9b/0x110 [i915] intel_display_power_put_async_work+0x91/0xf0 [i915] process_one_work+0x260/0x600 ? worker_thread+0xc9/0x380 worker_thread+0x37/0x380 ? process_one_work+0x600/0x600 kthread+0x119/0x130 ? kthread_park+0x80/0x80 ret_from_fork+0x24/0x50 [ cut here ] WARNING: CPU: 3 PID: 1142 at kernel/rcu/tree_plugin.h:293 rcu_note_context_switch+0x87/0x650 Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul cdc_ether usbnet mii snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec snd_hwdep
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add request throughput measurement to perf (rev3)
== Series Details ==
Series: drm/i915/selftests: Add request throughput measurement to perf (rev3)
URL : https://patchwork.freedesktop.org/series/73930/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a685a79c5061 drm/i915/selftests: Add request throughput measurement to perf
-:96: WARNING:LINE_SPACING: Missing a blank line after declarations
#96: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1525:
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
-:130: WARNING:LINE_SPACING: Missing a blank line after declarations
#130: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1559:
+ struct i915_request *prev = NULL;
+ IGT_TIMEOUT(end_time);
-:165: WARNING:LINE_SPACING: Missing a blank line after declarations
#165: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1594:
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
-:188: WARNING:LINE_SPACING: Missing a blank line after declarations
#188: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1617:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:196: WARNING:LINE_SPACING: Missing a blank line after declarations
#196: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1625:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:325: WARNING:LINE_SPACING: Missing a blank line after declarations
#325: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1754:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:393: WARNING:LINE_SPACING: Missing a blank line after declarations
#393: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1822:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:462: WARNING:LINE_SPACING: Missing a blank line after declarations
#462: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1891:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:518: WARNING:LINE_SPACING: Missing a blank line after declarations
#518: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1947:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:526: WARNING:LINE_SPACING: Missing a blank line after declarations
#526: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1955:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:571: WARNING:YIELD: Using yield() is generally wrong. See yield() kernel-doc
(sched/core.c)
#571: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:2000:
+ yield(); /* start all threads before we kthread_stop() */
total: 0 errors, 11 warnings, 0 checks, 611 lines checked
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Re: [Intel-gfx] [PATCH v5 8/8] drm/i915/tc: Do not warn when aux power well of static TC ports timeout
On Tue, Apr 14, 2020 at 12:49:56PM -0700, José Roberto de Souza wrote:
> This is a expected timeout of static TC ports not conneceted, so
> not throwing warnings that would taint CI.
>
> v3:
> - moved checks to tc_phy_aux_timeout_expected()
>
> v4:
> - moved and add comments to tc_phy_aux_timeout_expected()
>
> v5:
> - only checking tc_legacy_port for TC ports
>
> Signed-off-by: José Roberto de Souza
Looks ok:
Reviewed-by: Imre Deak
> ---
> .../drm/i915/display/intel_display_power.c| 59 +--
> 1 file changed, 42 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index e28756cee68a..40e1713fcdbf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -20,6 +20,8 @@
> #include "intel_tc.h"
> #include "intel_vga.h"
>
> +static const struct i915_power_well_ops icl_tc_phy_aux_power_well_ops;
> +
> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
>enum i915_power_well_id power_well_id);
>
> @@ -284,6 +286,21 @@ static void hsw_power_well_pre_disable(struct
> drm_i915_private *dev_priv,
> gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
> }
>
> +#define ICL_AUX_PW_TO_CH(pw_idx) \
> + ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> +
> +#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
> + ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> +
> +static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + int pw_idx = power_well->desc->hsw.idx;
> +
> + return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> + ICL_AUX_PW_TO_CH(pw_idx);
> +}
> +
> static struct intel_digital_port *
> aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> enum aux_ch aux_ch)
> @@ -311,6 +328,28 @@ aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> return dig_port;
> }
>
> +static bool tc_phy_aux_timeout_expected(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + /* An AUX timeout is expected if the TBT DP tunnel is down. */
> + if (power_well->desc->hsw.is_tc_tbt)
> + return true;
> +
> + /*
> + * An AUX timeout is expected because we enable TC legacy port aux
> + * to hold port out of TC cold
> + */
> + if (INTEL_GEN(dev_priv) == 11 &&
> + power_well->desc->ops == _tc_phy_aux_power_well_ops) {
> + enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> + struct intel_digital_port *dig_port =
> aux_ch_to_digital_port(dev_priv, aux_ch);
> +
> + return dig_port->tc_legacy_port;
> + }
> +
> + return false;
> +}
> +
> static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> @@ -323,8 +362,9 @@ static void hsw_wait_for_power_well_enable(struct
> drm_i915_private *dev_priv,
> drm_dbg_kms(_priv->drm, "%s power well enable timeout\n",
> power_well->desc->name);
>
> - /* An AUX timeout is expected if the TBT DP tunnel is down. */
> - drm_WARN_ON(_priv->drm, !power_well->desc->hsw.is_tc_tbt);
> + drm_WARN_ON(_priv->drm,
> + !tc_phy_aux_timeout_expected(dev_priv, power_well));
> +
> }
> }
>
> @@ -520,21 +560,6 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
>
> -#define ICL_AUX_PW_TO_CH(pw_idx) \
> - ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> -
> -#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
> - ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> -
> -static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - int pw_idx = power_well->desc->hsw.idx;
> -
> - return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> - ICL_AUX_PW_TO_CH(pw_idx);
> -}
> -
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
>
> static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
> --
> 2.26.0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Move gpu energy measurement into its own little lib
Move the handy utility to measure the GPU energy consumption using RAPL
msr into a common lib so that it can be reused easily.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 3 ++-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 25 +--
drivers/gpu/drm/i915/selftests/librapl.c | 26
drivers/gpu/drm/i915/selftests/librapl.h | 13
4 files changed, 46 insertions(+), 21 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/librapl.c
create mode 100644 drivers/gpu/drm/i915/selftests/librapl.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index fa8d78e40dad..dc80a1d4dc9b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/igt_live_test.o \
selftests/igt_mmap.o \
selftests/igt_reset.o \
- selftests/igt_spinner.o
+ selftests/igt_spinner.o \
+ selftests/librapl.o
# virtual gpu code
i915-y += i915_vgpu.o
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 08c3dbd41b12..5d59589d8a54 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -11,22 +11,7 @@
#include "selftest_rc6.h"
#include "selftests/i915_random.h"
-
-static u64 energy_uJ(struct intel_rc6 *rc6)
-{
- unsigned long long power;
- u32 units;
-
- if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, ))
- return 0;
-
- units = (power & 0x1f00) >> 8;
-
- if (rdmsrl_safe(MSR_PP1_ENERGY_STATUS, ))
- return 0;
-
- return (100 * power) >> units; /* convert to uJ */
-}
+#include "selftests/librapl.h"
static u64 rc6_residency(struct intel_rc6 *rc6)
{
@@ -74,9 +59,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
dt = ktime_get();
- rc0_power = energy_uJ(rc6);
+ rc0_power = st_energy_uJ();
msleep(250);
- rc0_power = energy_uJ(rc6) - rc0_power;
+ rc0_power = st_energy_uJ() - rc0_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if ((res[1] - res[0]) >> 10) {
@@ -99,9 +84,9 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
intel_uncore_forcewake_flush(rc6_to_uncore(rc6), FORCEWAKE_ALL);
dt = ktime_get();
- rc6_power = energy_uJ(rc6);
+ rc6_power = st_energy_uJ();
msleep(100);
- rc6_power = energy_uJ(rc6) - rc6_power;
+ rc6_power = st_energy_uJ() - rc6_power;
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if (res[1] == res[0]) {
diff --git a/drivers/gpu/drm/i915/selftests/librapl.c
b/drivers/gpu/drm/i915/selftests/librapl.c
new file mode 100644
index ..2a0c9aae8591
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/librapl.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include
+
+#include "librapl.h"
+
+u64 st_energy_uJ(void)
+{
+ unsigned long long power;
+ u32 units;
+
+ if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, ))
+ return 0;
+
+ units = (power & 0x1f00) >> 8;
+
+ if (rdmsrl_safe(MSR_PP1_ENERGY_STATUS, ))
+ return 0;
+
+ return (100 * power) >> units; /* convert to uJ */
+}
+
+
diff --git a/drivers/gpu/drm/i915/selftests/librapl.h
b/drivers/gpu/drm/i915/selftests/librapl.h
new file mode 100644
index ..e0d6334b4367
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/librapl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef SELFTEST_LIBRAPL_H
+#define SELFTEST_LIBRAPL_H
+
+#include
+
+u64 st_energy_uJ(void);
+
+#endif /* SELFTEST_LIBRAPL_H */
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Check power consumption at min/max frequencies
A basic premise of RPS is that at lower frequencies, not only do we run
slower, but we save power compared to higher frequencies. For example,
when idle, we set the minimum frequency just in case there is some
residual current. Since the power curve should be a physical
relationship, if we find no power saving it's likely that we've broken
our frequency handling, so test!
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 129 +++
drivers/gpu/drm/i915/gt/selftest_rps.h | 1 +
3 files changed, 131 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index c50bb502fe03..0141c334f2ac 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -54,6 +54,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
SUBTEST(live_rps_interrupt),
+ SUBTEST(live_rps_power),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 5ad5bee6bdba..3c783f9a04d5 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -3,6 +3,8 @@
* Copyright © 2020 Intel Corporation
*/
+#include
+
#include "intel_engine_pm.h"
#include "intel_gt_clk.h"
#include "intel_gt_pm.h"
@@ -10,6 +12,7 @@
#include "selftest_rps.h"
#include "selftests/igt_flush_test.h"
#include "selftests/igt_spinner.h"
+#include "selftests/librapl.h"
static void dummy_rps_work(struct work_struct *wrk)
{
@@ -224,3 +227,129 @@ int live_rps_interrupt(void *arg)
return err;
}
+
+static u64 __measure_power(int duration_ms)
+{
+ u64 nrg, dt;
+
+ dt = -ktime_get();
+ nrg = -st_energy_uJ();
+ msleep(5);
+ nrg += st_energy_uJ();
+ dt += ktime_get();
+
+ return div64_u64(1000 * 1000 * nrg, dt);
+}
+
+static int cmp_u64(const void *A, const void *B)
+{
+ const u64 *a = A, *b = B;
+
+ if (a < b)
+ return -1;
+ else if (a > b)
+ return 1;
+ else
+ return 0;
+}
+
+static u64 measure_power_at(struct intel_rps *rps, int freq)
+{
+ u64 x[5];
+ int i;
+
+ mutex_lock(>lock);
+ GEM_BUG_ON(!rps->active);
+ intel_rps_set(rps, freq);
+ mutex_unlock(>lock);
+
+ msleep(20); /* more than enough time to stabilise! */
+
+ for (i = 0; i < 5; i++)
+ x[i] = __measure_power(5);
+
+ /* A simple triangle filter for better result stability */
+ sort(x, 5, sizeof(*x), cmp_u64, NULL);
+ return div_u64(x[1] + 2 * x[2] + x[3], 4);
+}
+
+int live_rps_power(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_rps *rps = >rps;
+ void (*saved_work)(struct work_struct *wrk);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ int err = 0;
+
+ /*
+* Our fundamental assumption is that running at lower frequency
+* actually saves power. Let's see if our RAPL measurement support
+* that theory.
+*/
+
+ if (!rps->enabled || rps->max_freq <= rps->min_freq)
+ return 0;
+
+ if (igt_spinner_init(, gt))
+ return -ENOMEM;
+
+ intel_gt_pm_wait_for_idle(gt);
+ saved_work = rps->work.func;
+ rps->work.func = dummy_rps_work;
+
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq;
+ u64 min, max;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ rq = igt_spinner_create_request(,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ intel_gt_set_wedged(engine->gt);
+ err = -EIO;
+ break;
+ }
+
+ max = measure_power_at(rps, rps->max_freq);
+ min = measure_power_at(rps, rps->min_freq);
+
+ igt_spinner_end();
+
+ pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n",
+ engine->name,
+ min, intel_gpu_freq(rps, rps->min_freq),
+ max, intel_gpu_freq(rps, rps->max_freq));
+ if (min >= max) {
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Fix page flip ioctl format check
== Series Details == Series: drm: Fix page flip ioctl format check URL : https://patchwork.freedesktop.org/series/76040/ State : success == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17331 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17331/index.html Known issues Here are the changes found in Patchwork_17331 that come from known issues: ### IGT changes ### Warnings * igt@amdgpu/amd_prime@i915-to-amd: - fi-bwr-2160:[FAIL][1] -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17331/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17331/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 45) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8311 -> Patchwork_17331 CI-20190529: 20190529 CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17331: a4e87db6ffcae3e28a42d5072f14a1a1ce5733df @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a4e87db6ffca drm: Fix page flip ioctl format check == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17331/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/gt: Trace RPS events (rev3)
== Series Details == Series: series starting with [1/2] drm/i915/gt: Trace RPS events (rev3) URL : https://patchwork.freedesktop.org/series/76036/ State : failure == Summary == Applying: drm/i915/gt: Trace RPS events Applying: drm/i915/gt: Use the RPM config register to determine clk frequencies error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gt/intel_rps.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0002 drm/i915/gt: Use the RPM config register to determine clk frequencies When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/amdgpu: utilize subconnector property for DP through atombios
On Thu, 16 Apr 2020, Alex Deucher wrote:
> On Wed, Apr 15, 2020 at 6:05 AM Jani Nikula wrote:
>>
>>
>> Alex, Harry, Christian, can you please eyeball this series and see if it
>> makes sense for you?
>>
>
> Patches 4, 5 are:
> Acked-by: Alex Deucher
> Feel free to take them through whichever tree you want.
Thanks a bunch! I'll let you know.
BR,
Jani.
>
> Alex
>
>
>> Thanks,
>> Jani.
>>
>>
>> On Tue, 07 Apr 2020, Jeevan B wrote:
>> > From: Oleg Vasilev
>> >
>> > Since DP-specific information is stored in driver's structures, every
>> > driver needs to implement subconnector property by itself.
>> >
>> > v2: rebase
>> >
>> > Cc: Alex Deucher
>> > Cc: Christian König
>> > Cc: David (ChunMing) Zhou
>> > Cc: amd-...@lists.freedesktop.org
>> > Signed-off-by: Jeevan B
>> > Signed-off-by: Oleg Vasilev
>> > Reviewed-by: Emil Velikov
>> > Link:
>> > https://patchwork.freedesktop.org/patch/msgid/20190829114854.1539-6-oleg.vasi...@intel.com
>> > ---
>> > drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 10 ++
>> > drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 +
>> > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 18 +-
>> > 3 files changed, 28 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
>> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
>> > index f355d9a..71aade0 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
>> > @@ -26,6 +26,7 @@
>> >
>> > #include
>> > #include
>> > +#include
>> > #include
>> > #include
>> > #include "amdgpu.h"
>> > @@ -1405,6 +1406,10 @@ amdgpu_connector_dp_detect(struct drm_connector
>> > *connector, bool force)
>> > pm_runtime_put_autosuspend(connector->dev->dev);
>> > }
>> >
>> > + drm_dp_set_subconnector_property(_connector->base,
>> > + ret,
>> > + amdgpu_dig_connector->dpcd,
>> > +
>> > amdgpu_dig_connector->downstream_ports);
>> > return ret;
>> > }
>> >
>> > @@ -1951,6 +1956,11 @@ amdgpu_connector_add(struct amdgpu_device *adev,
>> > if (has_aux)
>> > amdgpu_atombios_dp_aux_init(amdgpu_connector);
>> >
>> > + if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
>> > + connector_type == DRM_MODE_CONNECTOR_eDP) {
>> > +
>> > drm_mode_add_dp_subconnector_property(_connector->base);
>> > + }
>> > +
>> > return;
>> >
>> > failed:
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
>> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
>> > index 37ba07e..04a430e 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
>> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
>> > @@ -469,6 +469,7 @@ struct amdgpu_encoder {
>> > struct amdgpu_connector_atom_dig {
>> > /* displayport */
>> > u8 dpcd[DP_RECEIVER_CAP_SIZE];
>> > + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>> > u8 dp_sink_type;
>> > int dp_clock;
>> > int dp_lane_count;
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
>> > b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
>> > index 9b74cfd..900b272 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
>> > @@ -328,6 +328,22 @@ static void amdgpu_atombios_dp_probe_oui(struct
>> > amdgpu_connector *amdgpu_connect
>> > buf[0], buf[1], buf[2]);
>> > }
>> >
>> > +static void amdgpu_atombios_dp_ds_ports(struct amdgpu_connector
>> > *amdgpu_connector)
>> > +{
>> > + struct amdgpu_connector_atom_dig *dig_connector =
>> > amdgpu_connector->con_priv;
>> > + int ret;
>> > +
>> > + if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) {
>> > + ret = drm_dp_dpcd_read(_connector->ddc_bus->aux,
>> > +DP_DOWNSTREAM_PORT_0,
>> > +dig_connector->downstream_ports,
>> > +DP_MAX_DOWNSTREAM_PORTS);
>> > + if (ret)
>> > + memset(dig_connector->downstream_ports, 0,
>> > +DP_MAX_DOWNSTREAM_PORTS);
>> > + }
>> > +}
>> > +
>> > int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
>> > {
>> > struct amdgpu_connector_atom_dig *dig_connector =
>> > amdgpu_connector->con_priv;
>> > @@ -343,7 +359,7 @@ int amdgpu_atombios_dp_get_dpcd(struct
>> > amdgpu_connector *amdgpu_connector)
>> > dig_connector->dpcd);
>> >
>> > amdgpu_atombios_dp_probe_oui(amdgpu_connector);
>> > -
>> > + amdgpu_atombios_dp_ds_ports(amdgpu_connector);
>> > return 0;
>> > }
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
>> ___
>> dri-devel mailing list
>>
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm: Fix page flip ioctl format check
== Series Details == Series: drm: Fix page flip ioctl format check URL : https://patchwork.freedesktop.org/series/76040/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Update forcewake firmware ranges (rev2)
== Series Details ==
Series: drm/i915/icl: Update forcewake firmware ranges (rev2)
URL : https://patchwork.freedesktop.org/series/75864/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17330
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17330/index.html
Known issues
Here are the changes found in Patchwork_17330 that come from known issues:
### IGT changes ###
Warnings
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-bwr-2160:[FAIL][1] -> [SKIP][2] ([fdo#109271])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17330/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1662]: https://gitlab.freedesktop.org/drm/intel/issues/1662
Participating hosts (51 -> 46)
--
Additional (1): fi-kbl-7560u
Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8311 -> Patchwork_17330
CI-20190529: 20190529
CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17330: 18313c3077bd75c8d5161996c82849081f8d8214 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
18313c3077bd drm/i915/icl: Update forcewake firmware ranges
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17330/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Add request throughput measurement to perf
Under ideal circumstances, the driver should be able to keep the GPU
fully saturated with work. Measure how close to ideal we get under the
harshest of conditions with no user payload.
v2: Also measure throughput using only one thread.
Signed-off-by: Chris Wilson
---
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_request.c | 590 +-
2 files changed, 590 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index 3bf7f53e9924..d8da142985eb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -16,5 +16,6 @@
* Tests are executed in order by igt/i915_selftest
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
+selftest(request, i915_request_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 1dab0360f76a..750ced92141b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include "gem/i915_gem_pm.h"
#include "gem/selftests/mock_context.h"
@@ -1239,7 +1240,7 @@ static int live_parallel_engines(void *arg)
struct igt_live_test t;
unsigned int idx;
- snprintf(name, sizeof(name), "%ps", fn);
+ snprintf(name, sizeof(name), "%ps", *fn);
err = igt_live_test_begin(, i915, __func__, name);
if (err)
break;
@@ -1476,3 +1477,590 @@ int i915_request_live_selftests(struct drm_i915_private
*i915)
return i915_subtests(tests, i915);
}
+
+static int switch_to_kernel_sync(struct intel_context *ce, int err)
+{
+ struct i915_request *rq;
+ struct dma_fence *fence;
+
+ rq = intel_engine_create_kernel_request(ce->engine);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ fence = i915_active_fence_get(>timeline->last_request);
+ if (fence) {
+ i915_request_await_dma_fence(rq, fence);
+ dma_fence_put(fence);
+ }
+
+ rq = i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 2) < 0 && !err)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ while (!err && !intel_engine_is_idle(ce->engine))
+ intel_engine_flush_submission(ce->engine);
+
+ return err;
+}
+
+struct perf_stats {
+ struct intel_engine_cs *engine;
+ unsigned long count;
+ ktime_t time;
+ ktime_t busy;
+ u64 runtime;
+};
+
+struct perf_series {
+ struct drm_i915_private *i915;
+ unsigned int nengines;
+ struct intel_context *ce[];
+};
+
+static int s_sync0(void *arg)
+{
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
+ unsigned int idx = 0;
+ int err = 0;
+
+ GEM_BUG_ON(!ps->nengines);
+ do {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ps->ce[idx]);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ if (++idx == ps->nengines)
+ idx = 0;
+ } while (!__igt_timeout(end_time, NULL));
+
+ return err;
+}
+
+static int s_sync1(void *arg)
+{
+ struct perf_series *ps = arg;
+ struct i915_request *prev = NULL;
+ IGT_TIMEOUT(end_time);
+ unsigned int idx = 0;
+ int err = 0;
+
+ GEM_BUG_ON(!ps->nengines);
+ do {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ps->ce[idx]);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (prev && i915_request_wait(prev, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(prev);
+ prev = rq;
+ if (err)
+ break;
+
+ if (++idx == ps->nengines)
+ idx = 0;
+ } while (!__igt_timeout(end_time, NULL));
+ i915_request_put(prev);
+
+ return err;
+}
+
+static int s_many(void *arg)
+{
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
+ unsigned int idx = 0;
+
+ GEM_BUG_ON(!ps->nengines);
+ do {
+
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/icl: Update forcewake firmware ranges (rev2)
== Series Details == Series: drm/i915/icl: Update forcewake firmware ranges (rev2) URL : https://patchwork.freedesktop.org/series/75864/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/gt: Use the RPM config register to determine clk frequencies
For many configuration details within RC6 and RPS we are programming
intervals for the internal clocks. From gen11, these clocks are
configuration via the RPM_CONFIG and so for convenience, we would like
to convert to/from more natural units (ns).
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 27 +
drivers/gpu/drm/i915/gt/intel_gt_clk.c | 78 +
drivers/gpu/drm/i915/gt/intel_gt_clk.h | 21 +++
drivers/gpu/drm/i915/gt/intel_rps.c | 37 +++-
drivers/gpu/drm/i915/gt/selftest_rps.c | 7 ++-
drivers/gpu/drm/i915/i915_debugfs.c | 34 +++
drivers/gpu/drm/i915/i915_reg.h | 25
8 files changed, 164 insertions(+), 66 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44c506b7e117..fa8d78e40dad 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -91,6 +91,7 @@ gt-y += \
gt/intel_ggtt.o \
gt/intel_ggtt_fencing.o \
gt/intel_gt.o \
+ gt/intel_gt_clk.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index aab30d908072..cd466472599f 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -10,6 +10,7 @@
#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt.h"
+#include "intel_gt_clk.h"
#include "intel_llc.h"
#include "intel_rc6.h"
#include "intel_rps.h"
@@ -394,21 +395,23 @@ static int frequency_show(struct seq_file *m, void
*unused)
seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
seq_printf(m, "CAGF: %dMHz\n", cagf);
- seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
- rpupei, GT_PM_INTERVAL_TO_US(i915, rpupei));
- seq_printf(m, "RP CUR UP: %d (%dus)\n",
- rpcurup, GT_PM_INTERVAL_TO_US(i915, rpcurup));
- seq_printf(m, "RP PREV UP: %d (%dus)\n",
- rpprevup, GT_PM_INTERVAL_TO_US(i915, rpprevup));
+ seq_printf(m, "RP CUR UP EI: %d (%dns)\n",
+ rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
+ seq_printf(m, "RP CUR UP: %d (%dns)\n",
+ rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
+ seq_printf(m, "RP PREV UP: %d (%dns)\n",
+ rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
seq_printf(m, "Up threshold: %d%%\n",
rps->power.up_threshold);
- seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
- rpdownei, GT_PM_INTERVAL_TO_US(i915, rpdownei));
- seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
- rpcurdown, GT_PM_INTERVAL_TO_US(i915, rpcurdown));
- seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
- rpprevdown, GT_PM_INTERVAL_TO_US(i915, rpprevdown));
+ seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n",
+ rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
+ seq_printf(m, "RP CUR DOWN: %d (%dns)\n",
+ rpcurdown,
+ intel_gt_pm_interval_to_ns(gt, rpcurdown));
+ seq_printf(m, "RP PREV DOWN: %d (%dns)\n",
+ rpprevdown,
+ intel_gt_pm_interval_to_ns(gt, rpprevdown));
seq_printf(m, "Down threshold: %d%%\n",
rps->power.down_threshold);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clk.c
b/drivers/gpu/drm/i915/gt/intel_gt_clk.c
new file mode 100644
index ..7cc3145a63ed
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clk.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt.h"
+#include "intel_gt_clk.h"
+
+#define MHZ_19_2 1920 /* 19.2MHz, 52.083ns */
+#define MHZ_24 2400 /* 24MHz, 83.333ns */
+#define MHZ_25 2500 /* 25MHz, 80ns */
+
+u32 intel_gt_clk_frequency(struct intel_gt *gt)
+{
+ if (INTEL_GEN(gt->i915) >= 11) {
+ u32 config;
+
+ config = intel_uncore_read(gt->uncore, RPM_CONFIG0);
+ config &= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
+ config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+
+ switch (config) {
+ case 0: return MHZ_24;
+ case 1:
+ case 2: return MHZ_19_2;
+ default:
+ case 3:
Re: [Intel-gfx] [PATCH] drm: Fix page flip ioctl format check
On Thu, Apr 16, 2020 at 08:08:14PM +0300, Laurent Pinchart wrote:
> Hi Ville,
>
> Thank you for the patch.
>
> On Thu, Apr 16, 2020 at 08:04:20PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Revert back to comparing fb->format->format instead fb->format for the
> > page flip ioctl. This check was originally only here to disallow pixel
> > format changes, but when we changed it to do the pointer comparison
> > we potentially started to reject some (but definitely not all) modifier
> > changes as well. In fact the current behaviour depends on whether the
> > driver overrides the format info for a specific format+modifier combo.
> > Eg. on i915 this now rejects compression vs. no compression changes but
> > does not reject any other tiling changes. That's just inconsistent
> > nonsense.
> >
> > The main reason we have to go back to the old behaviour is to fix page
> > flipping with Xorg. At some point Xorg got its atomic rights taken away
> > and since then we can't page flip between compressed and non-compressed
> > fbs on i915. Currently we get no page flipping for any games pretty much
> > since Mesa likes to use compressed buffers. Not sure how compositors are
> > working around this (don't use one myself). I guess they must be doing
> > something to get non-compressed buffers instead. Either that or
> > somehow no one noticed the tearing from the blit fallback.
> >
> > Looking back at the original discussion on this change we pretty much
> > just did it in the name of skipping a few extra pointer dereferences.
> > However, I've decided not to revert the whole thing in case someone
> > has since started to depend on these changes. None of the other checks
> > are relevant for i915 anyways.
>
> Do display controller usually support changing modifiers for page flips
> ? I understand from the information about that i915 does, but is that
> usual ? Could there be drivers that really on this check to reject
> modifier changes, and that aren't prepared to handle them if they are
> not rejected by the core ? I'm not opposed to this change, but I'd like
> to carefully consider the fallout.
After a bit of grepping I can't actually see any other driver providing
a .get_format_info() hook. So looks like there is no change in behaviour
for any other driver. Based on that we could even do a full revert, but
meh.
>
> > Cc: sta...@vger.kernel.org
> > Cc: Laurent Pinchart
> > Fixes: dbd4d5761e1f ("drm: Replace 'format->format' comparisons to just
> > 'format' comparisons")
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/drm_plane.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> > index d6ad60ab0d38..f2ca5315f23b 100644
> > --- a/drivers/gpu/drm/drm_plane.c
> > +++ b/drivers/gpu/drm/drm_plane.c
> > @@ -1153,7 +1153,7 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
> > if (ret)
> > goto out;
> >
> > - if (old_fb->format != fb->format) {
> > + if (old_fb->format->format != fb->format->format) {
> > DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer
> > format.\n");
> > ret = -EINVAL;
> > goto out;
>
> --
> Regards,
>
> Laurent Pinchart
--
Ville Syrjälä
Intel
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Add missing deinitialization cases of load failure
On Thu, Apr 16, 2020 at 08:20:23PM +0300, Souza, Jose wrote: > On Thu, 2020-04-16 at 20:06 +0300, Imre Deak wrote: > > On Thu, Apr 16, 2020 at 08:03:39PM +0300, Souza, Jose wrote: > > > On Thu, 2020-04-16 at 19:42 +0300, Imre Deak wrote: > > > > On Wed, Apr 15, 2020 at 12:14:08PM -0700, José Roberto de Souza > > > > wrote: > > > > > The intel_display_power_put_async() used in TC cold sequences > > > > > made > > > > > easy to hit the missing deinitialization of driver in case of > > > > > load > > > > > failure as seen in the stack trace bellow. > > > > > > > > > > intel_modeset_driver_remove_noirq() had to be removed from > > > > > i915_driver_modeset_remove_noirq() as those are different > > > > > initialialition steps with IRQ and GEM initialization in > > > > > between > > > > > then. > > > > > > > > > > [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context > > > > > workarounds on rcs'0 > > > > > [drm:__i915_inject_probe_error [i915]] Injecting failure -19 at > > > > > checkpoint 36 [__uc_init:294] > > > > > [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind > > > > > [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:275:DDI A] > > > > > VDD > > > > > off > > > > > [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x > > > > > PP_CONTROL: 0x0060 > > > > > [drm:intel_power_well_disable [i915]] disabling AUX A > > > > > general protection fault, probably for non-canonical address > > > > > 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI > > > > > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: > > > > > G U5.6.0-CI-Patchwork_17226+ #1 > > > > > Hardware name: Intel Corporation Tiger Lake Client > > > > > Platform/TigerLake U DDR4 SODIMM RVP, BIOS > > > > > TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > > > > > Workqueue: events_unbound intel_display_power_put_async_work > > > > > [i915] > > > > > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > > > > > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 > > > > > 41 > > > > > a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b > > > > > 03 > > > > > <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 > > > > > 08 75 > > > > > RSP: 0018:c961fdb0 EFLAGS: 00010206 > > > > > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: > > > > > 003d > > > > > RDX: 8001 RSI: RDI: > > > > > > > > > > RBP: 888479be R08: 88849a180920 R09: > > > > > > > > > > R10: R11: R12: > > > > > a0414480 > > > > > R13: 2000 R14: 888479beb320 R15: > > > > > 2000 > > > > > FS: () GS:88849ff8() > > > > > knlGS: > > > > > CS: 0010 DS: ES: CR0: 80050033 > > > > > CR2: 5634fa8ed670 CR3: 05610004 CR4: > > > > > 00760ee0 > > > > > PKRU: 5554 > > > > > Call Trace: > > > > > release_async_put_domains+0x9b/0x110 [i915] > > > > > intel_display_power_put_async_work+0x91/0xf0 [i915] > > > > > process_one_work+0x260/0x600 > > > > > ? worker_thread+0xc9/0x380 > > > > > worker_thread+0x37/0x380 > > > > > ? process_one_work+0x600/0x600 > > > > > kthread+0x119/0x130 > > > > > ? kthread_park+0x80/0x80 > > > > > ret_from_fork+0x24/0x50 > > > > > Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp > > > > > x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul > > > > > cdc_ether usbnet mii snd_intel_dspcfg ghash_clmulni_intel > > > > > snd_hda_codec snd_hwdep snd_hda_core e1000e ptp mei_me snd_pcm > > > > > pps_core mei intel_lpss_pci prime_numbers [last unloaded: i915] > > > > > ---[ end trace b402d1b4060f8b97 ]--- > > > > > BUG: sleeping function called from invalid context at > > > > > kernel/sched/completion.c:99 > > > > > in_atomic(): 0, irqs_disabled(): 0, non_block: 0, pid: 1142, > > > > > name: > > > > > kworker/u16:20 > > > > > INFO: lockdep is turned off. > > > > > Preemption disabled at: > > > > > [<>] 0x0 > > > > > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: > > > > > G UD 5.6.0-CI-Patchwork_17226+ #1 > > > > > Hardware name: Intel Corporation Tiger Lake Client > > > > > Platform/TigerLake U DDR4 SODIMM RVP, BIOS > > > > > TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > > > > > Workqueue: events_unbound intel_display_power_put_async_work > > > > > [i915] > > > > > Call Trace: > > > > > dump_stack+0x71/0x9b > > > > > ___might_sleep+0x178/0x260 > > > > > wait_for_completion+0x37/0x1a0 > > > > > virt_efi_query_variable_info+0x161/0x1b0 > > > > > efi_query_variable_store+0xb3/0x1a0 > > > > > ? efivar_entry_set_safe+0x19c/0x220 > > > > > efivar_entry_set_safe+0x19c/0x220 > > > > > ? efi_pstore_write+0x10b/0x150 > > > > > ? efi_pstore_write+0xa0/0x150 > > > > > efi_pstore_write+0x10b/0x150 > > > > > pstore_dump+0x123/0x340 > > > > > kmsg_dump+0x87/0x1b0 > > > > > oops_end+0x3e/0x90 > > > >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dpcd_bl: Unbreak enable_dpcd_backlight modparam (rev2)
== Series Details == Series: drm/i915/dpcd_bl: Unbreak enable_dpcd_backlight modparam (rev2) URL : https://patchwork.freedesktop.org/series/75895/ State : success == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17329 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17329/index.html Known issues Here are the changes found in Patchwork_17329 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-rte: - fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([i915#189]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-icl-dsi/igt@i915_pm_...@basic-rte.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17329/fi-icl-dsi/igt@i915_pm_...@basic-rte.html Warnings * igt@amdgpu/amd_prime@i915-to-amd: - fi-bwr-2160:[FAIL][3] -> [SKIP][4] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17329/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 Participating hosts (51 -> 44) -- Missing(7): fi-cml-u2 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8311 -> Patchwork_17329 CI-20190529: 20190529 CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17329: a1ba2089b4b0c79638998e158760ef763399d89f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a1ba2089b4b0 drm/i915/dpcd_bl: Unbreak enable_dpcd_backlight modparam == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17329/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Add missing deinitialization cases of load failure
On Thu, 2020-04-16 at 20:06 +0300, Imre Deak wrote: > On Thu, Apr 16, 2020 at 08:03:39PM +0300, Souza, Jose wrote: > > On Thu, 2020-04-16 at 19:42 +0300, Imre Deak wrote: > > > On Wed, Apr 15, 2020 at 12:14:08PM -0700, José Roberto de Souza > > > wrote: > > > > The intel_display_power_put_async() used in TC cold sequences > > > > made > > > > easy to hit the missing deinitialization of driver in case of > > > > load > > > > failure as seen in the stack trace bellow. > > > > > > > > intel_modeset_driver_remove_noirq() had to be removed from > > > > i915_driver_modeset_remove_noirq() as those are different > > > > initialialition steps with IRQ and GEM initialization in > > > > between > > > > then. > > > > > > > > [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context > > > > workarounds on rcs'0 > > > > [drm:__i915_inject_probe_error [i915]] Injecting failure -19 at > > > > checkpoint 36 [__uc_init:294] > > > > [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind > > > > [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:275:DDI A] > > > > VDD > > > > off > > > > [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x > > > > PP_CONTROL: 0x0060 > > > > [drm:intel_power_well_disable [i915]] disabling AUX A > > > > general protection fault, probably for non-canonical address > > > > 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI > > > > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: > > > > G U5.6.0-CI-Patchwork_17226+ #1 > > > > Hardware name: Intel Corporation Tiger Lake Client > > > > Platform/TigerLake U DDR4 SODIMM RVP, BIOS > > > > TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > > > > Workqueue: events_unbound intel_display_power_put_async_work > > > > [i915] > > > > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > > > > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 > > > > 41 > > > > a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b > > > > 03 > > > > <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 > > > > 08 75 > > > > RSP: 0018:c961fdb0 EFLAGS: 00010206 > > > > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: > > > > 003d > > > > RDX: 8001 RSI: RDI: > > > > > > > > RBP: 888479be R08: 88849a180920 R09: > > > > > > > > R10: R11: R12: > > > > a0414480 > > > > R13: 2000 R14: 888479beb320 R15: > > > > 2000 > > > > FS: () GS:88849ff8() > > > > knlGS: > > > > CS: 0010 DS: ES: CR0: 80050033 > > > > CR2: 5634fa8ed670 CR3: 05610004 CR4: > > > > 00760ee0 > > > > PKRU: 5554 > > > > Call Trace: > > > > release_async_put_domains+0x9b/0x110 [i915] > > > > intel_display_power_put_async_work+0x91/0xf0 [i915] > > > > process_one_work+0x260/0x600 > > > > ? worker_thread+0xc9/0x380 > > > > worker_thread+0x37/0x380 > > > > ? process_one_work+0x600/0x600 > > > > kthread+0x119/0x130 > > > > ? kthread_park+0x80/0x80 > > > > ret_from_fork+0x24/0x50 > > > > Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp > > > > x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul > > > > cdc_ether usbnet mii snd_intel_dspcfg ghash_clmulni_intel > > > > snd_hda_codec snd_hwdep snd_hda_core e1000e ptp mei_me snd_pcm > > > > pps_core mei intel_lpss_pci prime_numbers [last unloaded: i915] > > > > ---[ end trace b402d1b4060f8b97 ]--- > > > > BUG: sleeping function called from invalid context at > > > > kernel/sched/completion.c:99 > > > > in_atomic(): 0, irqs_disabled(): 0, non_block: 0, pid: 1142, > > > > name: > > > > kworker/u16:20 > > > > INFO: lockdep is turned off. > > > > Preemption disabled at: > > > > [<>] 0x0 > > > > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: > > > > G UD 5.6.0-CI-Patchwork_17226+ #1 > > > > Hardware name: Intel Corporation Tiger Lake Client > > > > Platform/TigerLake U DDR4 SODIMM RVP, BIOS > > > > TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > > > > Workqueue: events_unbound intel_display_power_put_async_work > > > > [i915] > > > > Call Trace: > > > > dump_stack+0x71/0x9b > > > > ___might_sleep+0x178/0x260 > > > > wait_for_completion+0x37/0x1a0 > > > > virt_efi_query_variable_info+0x161/0x1b0 > > > > efi_query_variable_store+0xb3/0x1a0 > > > > ? efivar_entry_set_safe+0x19c/0x220 > > > > efivar_entry_set_safe+0x19c/0x220 > > > > ? efi_pstore_write+0x10b/0x150 > > > > ? efi_pstore_write+0xa0/0x150 > > > > efi_pstore_write+0x10b/0x150 > > > > pstore_dump+0x123/0x340 > > > > kmsg_dump+0x87/0x1b0 > > > > oops_end+0x3e/0x90 > > > > do_general_protection+0x1c3/0x2f0 > > > > general_protection+0x2d/0x40 > > > > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > > > > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 > > > > 41 > > > > a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dpcd_bl: Unbreak enable_dpcd_backlight modparam (rev2)
== Series Details == Series: drm/i915/dpcd_bl: Unbreak enable_dpcd_backlight modparam (rev2) URL : https://patchwork.freedesktop.org/series/75895/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Fix page flip ioctl format check
Hi Ville,
Thank you for the patch.
On Thu, Apr 16, 2020 at 08:04:20PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Revert back to comparing fb->format->format instead fb->format for the
> page flip ioctl. This check was originally only here to disallow pixel
> format changes, but when we changed it to do the pointer comparison
> we potentially started to reject some (but definitely not all) modifier
> changes as well. In fact the current behaviour depends on whether the
> driver overrides the format info for a specific format+modifier combo.
> Eg. on i915 this now rejects compression vs. no compression changes but
> does not reject any other tiling changes. That's just inconsistent
> nonsense.
>
> The main reason we have to go back to the old behaviour is to fix page
> flipping with Xorg. At some point Xorg got its atomic rights taken away
> and since then we can't page flip between compressed and non-compressed
> fbs on i915. Currently we get no page flipping for any games pretty much
> since Mesa likes to use compressed buffers. Not sure how compositors are
> working around this (don't use one myself). I guess they must be doing
> something to get non-compressed buffers instead. Either that or
> somehow no one noticed the tearing from the blit fallback.
>
> Looking back at the original discussion on this change we pretty much
> just did it in the name of skipping a few extra pointer dereferences.
> However, I've decided not to revert the whole thing in case someone
> has since started to depend on these changes. None of the other checks
> are relevant for i915 anyways.
Do display controller usually support changing modifiers for page flips
? I understand from the information about that i915 does, but is that
usual ? Could there be drivers that really on this check to reject
modifier changes, and that aren't prepared to handle them if they are
not rejected by the core ? I'm not opposed to this change, but I'd like
to carefully consider the fallout.
> Cc: sta...@vger.kernel.org
> Cc: Laurent Pinchart
> Fixes: dbd4d5761e1f ("drm: Replace 'format->format' comparisons to just
> 'format' comparisons")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_plane.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> index d6ad60ab0d38..f2ca5315f23b 100644
> --- a/drivers/gpu/drm/drm_plane.c
> +++ b/drivers/gpu/drm/drm_plane.c
> @@ -1153,7 +1153,7 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
> if (ret)
> goto out;
>
> - if (old_fb->format != fb->format) {
> + if (old_fb->format->format != fb->format->format) {
> DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer
> format.\n");
> ret = -EINVAL;
> goto out;
--
Regards,
Laurent Pinchart
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Re: [Intel-gfx] [PATCH v2] drm/i915: Add missing deinitialization cases of load failure
On Thu, Apr 16, 2020 at 08:03:39PM +0300, Souza, Jose wrote: > On Thu, 2020-04-16 at 19:42 +0300, Imre Deak wrote: > > On Wed, Apr 15, 2020 at 12:14:08PM -0700, José Roberto de Souza > > wrote: > > > The intel_display_power_put_async() used in TC cold sequences made > > > easy to hit the missing deinitialization of driver in case of load > > > failure as seen in the stack trace bellow. > > > > > > intel_modeset_driver_remove_noirq() had to be removed from > > > i915_driver_modeset_remove_noirq() as those are different > > > initialialition steps with IRQ and GEM initialization in between > > > then. > > > > > > [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context > > > workarounds on rcs'0 > > > [drm:__i915_inject_probe_error [i915]] Injecting failure -19 at > > > checkpoint 36 [__uc_init:294] > > > [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind > > > [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:275:DDI A] VDD > > > off > > > [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x > > > PP_CONTROL: 0x0060 > > > [drm:intel_power_well_disable [i915]] disabling AUX A > > > general protection fault, probably for non-canonical address > > > 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI > > > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: > > > G U5.6.0-CI-Patchwork_17226+ #1 > > > Hardware name: Intel Corporation Tiger Lake Client > > > Platform/TigerLake U DDR4 SODIMM RVP, BIOS > > > TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > > > Workqueue: events_unbound intel_display_power_put_async_work [i915] > > > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > > > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 > > > a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 > > > <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 > > > RSP: 0018:c961fdb0 EFLAGS: 00010206 > > > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d > > > RDX: 8001 RSI: RDI: > > > RBP: 888479be R08: 88849a180920 R09: > > > R10: R11: R12: a0414480 > > > R13: 2000 R14: 888479beb320 R15: 2000 > > > FS: () GS:88849ff8() > > > knlGS: > > > CS: 0010 DS: ES: CR0: 80050033 > > > CR2: 5634fa8ed670 CR3: 05610004 CR4: 00760ee0 > > > PKRU: 5554 > > > Call Trace: > > > release_async_put_domains+0x9b/0x110 [i915] > > > intel_display_power_put_async_work+0x91/0xf0 [i915] > > > process_one_work+0x260/0x600 > > > ? worker_thread+0xc9/0x380 > > > worker_thread+0x37/0x380 > > > ? process_one_work+0x600/0x600 > > > kthread+0x119/0x130 > > > ? kthread_park+0x80/0x80 > > > ret_from_fork+0x24/0x50 > > > Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp > > > x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul > > > cdc_ether usbnet mii snd_intel_dspcfg ghash_clmulni_intel > > > snd_hda_codec snd_hwdep snd_hda_core e1000e ptp mei_me snd_pcm > > > pps_core mei intel_lpss_pci prime_numbers [last unloaded: i915] > > > ---[ end trace b402d1b4060f8b97 ]--- > > > BUG: sleeping function called from invalid context at > > > kernel/sched/completion.c:99 > > > in_atomic(): 0, irqs_disabled(): 0, non_block: 0, pid: 1142, name: > > > kworker/u16:20 > > > INFO: lockdep is turned off. > > > Preemption disabled at: > > > [<>] 0x0 > > > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: > > > G UD 5.6.0-CI-Patchwork_17226+ #1 > > > Hardware name: Intel Corporation Tiger Lake Client > > > Platform/TigerLake U DDR4 SODIMM RVP, BIOS > > > TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > > > Workqueue: events_unbound intel_display_power_put_async_work [i915] > > > Call Trace: > > > dump_stack+0x71/0x9b > > > ___might_sleep+0x178/0x260 > > > wait_for_completion+0x37/0x1a0 > > > virt_efi_query_variable_info+0x161/0x1b0 > > > efi_query_variable_store+0xb3/0x1a0 > > > ? efivar_entry_set_safe+0x19c/0x220 > > > efivar_entry_set_safe+0x19c/0x220 > > > ? efi_pstore_write+0x10b/0x150 > > > ? efi_pstore_write+0xa0/0x150 > > > efi_pstore_write+0x10b/0x150 > > > pstore_dump+0x123/0x340 > > > kmsg_dump+0x87/0x1b0 > > > oops_end+0x3e/0x90 > > > do_general_protection+0x1c3/0x2f0 > > > general_protection+0x2d/0x40 > > > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > > > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 > > > a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 > > > <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 > > > RSP: 0018:c961fdb0 EFLAGS: 00010206 > > > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d > > > RDX: 8001 RSI: RDI: > > > RBP: 888479be R08: 88849a180920 R09: > > > R10:
[Intel-gfx] [PATCH] drm: Fix page flip ioctl format check
From: Ville Syrjälä
Revert back to comparing fb->format->format instead fb->format for the
page flip ioctl. This check was originally only here to disallow pixel
format changes, but when we changed it to do the pointer comparison
we potentially started to reject some (but definitely not all) modifier
changes as well. In fact the current behaviour depends on whether the
driver overrides the format info for a specific format+modifier combo.
Eg. on i915 this now rejects compression vs. no compression changes but
does not reject any other tiling changes. That's just inconsistent
nonsense.
The main reason we have to go back to the old behaviour is to fix page
flipping with Xorg. At some point Xorg got its atomic rights taken away
and since then we can't page flip between compressed and non-compressed
fbs on i915. Currently we get no page flipping for any games pretty much
since Mesa likes to use compressed buffers. Not sure how compositors are
working around this (don't use one myself). I guess they must be doing
something to get non-compressed buffers instead. Either that or
somehow no one noticed the tearing from the blit fallback.
Looking back at the original discussion on this change we pretty much
just did it in the name of skipping a few extra pointer dereferences.
However, I've decided not to revert the whole thing in case someone
has since started to depend on these changes. None of the other checks
are relevant for i915 anyways.
Cc: sta...@vger.kernel.org
Cc: Laurent Pinchart
Fixes: dbd4d5761e1f ("drm: Replace 'format->format' comparisons to just
'format' comparisons")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_plane.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index d6ad60ab0d38..f2ca5315f23b 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -1153,7 +1153,7 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
if (ret)
goto out;
- if (old_fb->format != fb->format) {
+ if (old_fb->format->format != fb->format->format) {
DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer
format.\n");
ret = -EINVAL;
goto out;
--
2.24.1
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Re: [Intel-gfx] [PATCH v2] drm/i915: Add missing deinitialization cases of load failure
On Thu, 2020-04-16 at 19:42 +0300, Imre Deak wrote: > On Wed, Apr 15, 2020 at 12:14:08PM -0700, José Roberto de Souza > wrote: > > The intel_display_power_put_async() used in TC cold sequences made > > easy to hit the missing deinitialization of driver in case of load > > failure as seen in the stack trace bellow. > > > > intel_modeset_driver_remove_noirq() had to be removed from > > i915_driver_modeset_remove_noirq() as those are different > > initialialition steps with IRQ and GEM initialization in between > > then. > > > > [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context > > workarounds on rcs'0 > > [drm:__i915_inject_probe_error [i915]] Injecting failure -19 at > > checkpoint 36 [__uc_init:294] > > [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind > > [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:275:DDI A] VDD > > off > > [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x > > PP_CONTROL: 0x0060 > > [drm:intel_power_well_disable [i915]] disabling AUX A > > general protection fault, probably for non-canonical address > > 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI > > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: > > G U5.6.0-CI-Patchwork_17226+ #1 > > Hardware name: Intel Corporation Tiger Lake Client > > Platform/TigerLake U DDR4 SODIMM RVP, BIOS > > TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > > Workqueue: events_unbound intel_display_power_put_async_work [i915] > > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 > > a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 > > <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 > > RSP: 0018:c961fdb0 EFLAGS: 00010206 > > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d > > RDX: 8001 RSI: RDI: > > RBP: 888479be R08: 88849a180920 R09: > > R10: R11: R12: a0414480 > > R13: 2000 R14: 888479beb320 R15: 2000 > > FS: () GS:88849ff8() > > knlGS: > > CS: 0010 DS: ES: CR0: 80050033 > > CR2: 5634fa8ed670 CR3: 05610004 CR4: 00760ee0 > > PKRU: 5554 > > Call Trace: > > release_async_put_domains+0x9b/0x110 [i915] > > intel_display_power_put_async_work+0x91/0xf0 [i915] > > process_one_work+0x260/0x600 > > ? worker_thread+0xc9/0x380 > > worker_thread+0x37/0x380 > > ? process_one_work+0x600/0x600 > > kthread+0x119/0x130 > > ? kthread_park+0x80/0x80 > > ret_from_fork+0x24/0x50 > > Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp > > x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul > > cdc_ether usbnet mii snd_intel_dspcfg ghash_clmulni_intel > > snd_hda_codec snd_hwdep snd_hda_core e1000e ptp mei_me snd_pcm > > pps_core mei intel_lpss_pci prime_numbers [last unloaded: i915] > > ---[ end trace b402d1b4060f8b97 ]--- > > BUG: sleeping function called from invalid context at > > kernel/sched/completion.c:99 > > in_atomic(): 0, irqs_disabled(): 0, non_block: 0, pid: 1142, name: > > kworker/u16:20 > > INFO: lockdep is turned off. > > Preemption disabled at: > > [<>] 0x0 > > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: > > G UD 5.6.0-CI-Patchwork_17226+ #1 > > Hardware name: Intel Corporation Tiger Lake Client > > Platform/TigerLake U DDR4 SODIMM RVP, BIOS > > TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > > Workqueue: events_unbound intel_display_power_put_async_work [i915] > > Call Trace: > > dump_stack+0x71/0x9b > > ___might_sleep+0x178/0x260 > > wait_for_completion+0x37/0x1a0 > > virt_efi_query_variable_info+0x161/0x1b0 > > efi_query_variable_store+0xb3/0x1a0 > > ? efivar_entry_set_safe+0x19c/0x220 > > efivar_entry_set_safe+0x19c/0x220 > > ? efi_pstore_write+0x10b/0x150 > > ? efi_pstore_write+0xa0/0x150 > > efi_pstore_write+0x10b/0x150 > > pstore_dump+0x123/0x340 > > kmsg_dump+0x87/0x1b0 > > oops_end+0x3e/0x90 > > do_general_protection+0x1c3/0x2f0 > > general_protection+0x2d/0x40 > > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 > > a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 > > <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 > > RSP: 0018:c961fdb0 EFLAGS: 00010206 > > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d > > RDX: 8001 RSI: RDI: > > RBP: 888479be R08: 88849a180920 R09: > > R10: R11: R12: a0414480 > > R13: 2000 R14: 888479beb320 R15: 2000 > > release_async_put_domains+0x9b/0x110 [i915] > > intel_display_power_put_async_work+0x91/0xf0 [i915] > >
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/gt: Trace RPS events (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/gt: Trace RPS events (rev2) URL : https://patchwork.freedesktop.org/series/76036/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17328 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17328 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17328, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17328: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_pm: - fi-cml-s: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-cml-s/igt@i915_selftest@live@gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-cml-s/igt@i915_selftest@live@gt_pm.html - fi-icl-y: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-icl-y/igt@i915_selftest@live@gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-icl-y/igt@i915_selftest@live@gt_pm.html - fi-skl-6700k2: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-skl-6700k2/igt@i915_selftest@live@gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-skl-6700k2/igt@i915_selftest@live@gt_pm.html - fi-bsw-n3050: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html - fi-icl-dsi: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-icl-dsi/igt@i915_selftest@live@gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-icl-dsi/igt@i915_selftest@live@gt_pm.html - fi-skl-6600u: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-skl-6600u/igt@i915_selftest@live@gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-skl-6600u/igt@i915_selftest@live@gt_pm.html - fi-cfl-8109u: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html - fi-bsw-nick:[PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html - fi-hsw-peppy: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-hsw-peppy/igt@i915_selftest@live@gt_pm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-hsw-peppy/igt@i915_selftest@live@gt_pm.html - fi-skl-lmem:[PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-skl-lmem/igt@i915_selftest@live@gt_pm.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-skl-lmem/igt@i915_selftest@live@gt_pm.html - fi-apl-guc: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-apl-guc/igt@i915_selftest@live@gt_pm.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-apl-guc/igt@i915_selftest@live@gt_pm.html - fi-kbl-r: [PASS][23] -> [DMESG-FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-kbl-r/igt@i915_selftest@live@gt_pm.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-kbl-r/igt@i915_selftest@live@gt_pm.html - fi-bdw-5557u: [PASS][25] -> [DMESG-FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bdw-5557u/igt@i915_selftest@live@gt_pm.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-bdw-5557u/igt@i915_selftest@live@gt_pm.html - fi-skl-6770hq: [PASS][27] -> [DMESG-FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-skl-6770hq/igt@i915_selftest@live@gt_pm.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17328/fi-skl-6770hq/igt@i915_selftest@live@gt_pm.html - fi-snb-2600:[PASS][29] -> [DMESG-FAIL][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-snb-2600/igt@i915_selftest@live@gt_pm.html
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/gt: Trace RPS events (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/gt: Trace RPS events (rev2) URL : https://patchwork.freedesktop.org/series/76036/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/icl: Update forcewake firmware ranges
Some workarounds are not sticking across suspend resume cycles. The
forcewake ranges table has been updated and would reflect the hardware
appropriately.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222
v2: Simplify the table and use 0 for some unused ranges(Matt)
Cc: Matt Roper
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_uncore.c | 31 -
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index fa86b7ab2d99..078f5b2eb8a4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1092,8 +1092,7 @@ static const struct intel_forcewake_range
__gen9_fw_ranges[] = {
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen11_fw_ranges[] = {
- GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
- GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
@@ -1103,27 +1102,31 @@ static const struct intel_forcewake_range
__gen11_fw_ranges[] = {
GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8800, 0x8bff, 0),
GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
- GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
- GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x9560, 0x95ff, 0),
+ GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER),
- GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x24800, 0x3, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x24000, 0x2407f, 0),
+ GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x25000, 0x3, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x4, 0x1b, 0),
GEN_FW_RANGE(0x1c, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
- GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
- GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
- GEN_FW_RANGE(0x1cc000, 0x1c, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
+ GEN_FW_RANGE(0x1c8000, 0x1c, FORCEWAKE_MEDIA_VEBOX0),
GEN_FW_RANGE(0x1d, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
- GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
- GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
+ GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
};
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
--
2.20.1
___
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Re: [Intel-gfx] [PATCH v2] drm/i915: Add missing deinitialization cases of load failure
On Wed, Apr 15, 2020 at 12:14:08PM -0700, José Roberto de Souza wrote: > The intel_display_power_put_async() used in TC cold sequences made > easy to hit the missing deinitialization of driver in case of load > failure as seen in the stack trace bellow. > > intel_modeset_driver_remove_noirq() had to be removed from > i915_driver_modeset_remove_noirq() as those are different > initialialition steps with IRQ and GEM initialization in between then. > > [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context workarounds on > rcs'0 > [drm:__i915_inject_probe_error [i915]] Injecting failure -19 at checkpoint 36 > [__uc_init:294] > [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind > [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:275:DDI A] VDD off > [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x PP_CONTROL: > 0x0060 > [drm:intel_power_well_disable [i915]] disabling AUX A > general protection fault, probably for non-canonical address > 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: G U > 5.6.0-CI-Patchwork_17226+ #1 > Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 > SODIMM RVP, BIOS TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > Workqueue: events_unbound intel_display_power_put_async_work [i915] > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 a0 49 d3 e5 > eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 <4c> 85 68 10 74 ea 8b > 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 > RSP: 0018:c961fdb0 EFLAGS: 00010206 > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d > RDX: 8001 RSI: RDI: > RBP: 888479be R08: 88849a180920 R09: > R10: R11: R12: a0414480 > R13: 2000 R14: 888479beb320 R15: 2000 > FS: () GS:88849ff8() knlGS: > CS: 0010 DS: ES: CR0: 80050033 > CR2: 5634fa8ed670 CR3: 05610004 CR4: 00760ee0 > PKRU: 5554 > Call Trace: > release_async_put_domains+0x9b/0x110 [i915] > intel_display_power_put_async_work+0x91/0xf0 [i915] > process_one_work+0x260/0x600 > ? worker_thread+0xc9/0x380 > worker_thread+0x37/0x380 > ? process_one_work+0x600/0x600 > kthread+0x119/0x130 > ? kthread_park+0x80/0x80 > ret_from_fork+0x24/0x50 > Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp > x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul cdc_ether usbnet > mii snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec snd_hwdep snd_hda_core > e1000e ptp mei_me snd_pcm pps_core mei intel_lpss_pci prime_numbers [last > unloaded: i915] > ---[ end trace b402d1b4060f8b97 ]--- > BUG: sleeping function called from invalid context at > kernel/sched/completion.c:99 > in_atomic(): 0, irqs_disabled(): 0, non_block: 0, pid: 1142, name: > kworker/u16:20 > INFO: lockdep is turned off. > Preemption disabled at: > [<>] 0x0 > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: G UD > 5.6.0-CI-Patchwork_17226+ #1 > Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 > SODIMM RVP, BIOS TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > Workqueue: events_unbound intel_display_power_put_async_work [i915] > Call Trace: > dump_stack+0x71/0x9b > ___might_sleep+0x178/0x260 > wait_for_completion+0x37/0x1a0 > virt_efi_query_variable_info+0x161/0x1b0 > efi_query_variable_store+0xb3/0x1a0 > ? efivar_entry_set_safe+0x19c/0x220 > efivar_entry_set_safe+0x19c/0x220 > ? efi_pstore_write+0x10b/0x150 > ? efi_pstore_write+0xa0/0x150 > efi_pstore_write+0x10b/0x150 > pstore_dump+0x123/0x340 > kmsg_dump+0x87/0x1b0 > oops_end+0x3e/0x90 > do_general_protection+0x1c3/0x2f0 > general_protection+0x2d/0x40 > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 a0 49 d3 e5 > eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 <4c> 85 68 10 74 ea 8b > 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 > RSP: 0018:c961fdb0 EFLAGS: 00010206 > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d > RDX: 8001 RSI: RDI: > RBP: 888479be R08: 88849a180920 R09: > R10: R11: R12: a0414480 > R13: 2000 R14: 888479beb320 R15: 2000 > release_async_put_domains+0x9b/0x110 [i915] > intel_display_power_put_async_work+0x91/0xf0 [i915] > process_one_work+0x260/0x600 > ? worker_thread+0xc9/0x380 > worker_thread+0x37/0x380 > ? process_one_work+0x600/0x600 > kthread+0x119/0x130 > ? kthread_park+0x80/0x80 > ret_from_fork+0x24/0x50 > [ cut here ] > WARNING: CPU: 3 PID: 1142
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Trace RPS events (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/gt: Trace RPS events (rev2) URL : https://patchwork.freedesktop.org/series/76036/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8557361fae6d drm/i915/gt: Trace RPS events 7a6ae457560a drm/i915/gt: Use the RPM config register to determine clk frequencies -:77: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #77: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 347 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/gt: Trace RPS events
== Series Details == Series: series starting with [1/2] drm/i915/gt: Trace RPS events URL : https://patchwork.freedesktop.org/series/76036/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17327 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17327 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17327, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17327: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_pm: - fi-cml-s: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-cml-s/igt@i915_selftest@live@gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-cml-s/igt@i915_selftest@live@gt_pm.html - fi-icl-y: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-icl-y/igt@i915_selftest@live@gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-icl-y/igt@i915_selftest@live@gt_pm.html - fi-skl-6700k2: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-skl-6700k2/igt@i915_selftest@live@gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-skl-6700k2/igt@i915_selftest@live@gt_pm.html - fi-bsw-n3050: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html - fi-icl-dsi: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-icl-dsi/igt@i915_selftest@live@gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-icl-dsi/igt@i915_selftest@live@gt_pm.html - fi-skl-6600u: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-skl-6600u/igt@i915_selftest@live@gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-skl-6600u/igt@i915_selftest@live@gt_pm.html - fi-cfl-8109u: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html - fi-bsw-nick:[PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html - fi-hsw-peppy: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-hsw-peppy/igt@i915_selftest@live@gt_pm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-hsw-peppy/igt@i915_selftest@live@gt_pm.html - fi-skl-lmem:[PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-skl-lmem/igt@i915_selftest@live@gt_pm.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-skl-lmem/igt@i915_selftest@live@gt_pm.html - fi-apl-guc: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-apl-guc/igt@i915_selftest@live@gt_pm.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-apl-guc/igt@i915_selftest@live@gt_pm.html - fi-kbl-r: [PASS][23] -> [DMESG-FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-kbl-r/igt@i915_selftest@live@gt_pm.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-kbl-r/igt@i915_selftest@live@gt_pm.html - fi-bdw-5557u: [PASS][25] -> [DMESG-FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bdw-5557u/igt@i915_selftest@live@gt_pm.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-bdw-5557u/igt@i915_selftest@live@gt_pm.html - fi-skl-6770hq: [PASS][27] -> [DMESG-FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-skl-6770hq/igt@i915_selftest@live@gt_pm.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17327/fi-skl-6770hq/igt@i915_selftest@live@gt_pm.html - fi-snb-2600:[PASS][29] -> [DMESG-FAIL][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-snb-2600/igt@i915_selftest@live@gt_pm.html [30]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/gt: Trace RPS events
== Series Details == Series: series starting with [1/2] drm/i915/gt: Trace RPS events URL : https://patchwork.freedesktop.org/series/76036/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/display: Load DP_TP_CTL/STATUS offset before use it
On Wed, 2020-04-15 at 20:56 -0700, Matt Roper wrote:
> On Tue, Apr 14, 2020 at 04:04:40PM -0700, José Roberto de Souza
> wrote:
> > Right now dp.regs.dp_tp_ctl/status are only set during the encoder
> > pre_enable() hook, what is causing all reads and writes to those
> > registers to go to offset 0x0 before pre_enable() is executed.
> >
> > So if i915 takes the BIOS state and don't do a modeset any
> > following
> > link retraing will fail.
> >
> > In the case that i915 needs to do a modeset, the DDI disable
> > sequence
> > will write to a wrong register not disabling DP 'Transport Enable'
> > in
> > DP_TP_CTL, making a HDMI modeset in the same port/transcoder to
> > not light up the monitor.
>
> So to clarify I understand the problematic sequence properly:
> * i915 inherits already-enabled display from BIOS; pre_enable is
> never
>called
> * we do a modeset, so we have to disable the display and then try to
> re-enable
> - intel_disable_ddi_buf() writes to offset 0 rather than the
> proper
>register offset when attempting to reprogram DP_TP_CTL and
>disable DP
> - when we re-enable, the old, still-active DP settings in
> hardware
>cause problems and the display doesn't light up
>
> A couple clarifying questions:
> - It seems like we should have seen unclaimed register warnings from
>the bogus writes to offset 0 during disable. Any idea why those
>didn't show up?
Offset 0x0 is valid BSpec: 29316
> - In the commit message you mention that it's the DP Transport
> Enable
>that's the culprit here, which breaks future attempts to light up
>HDMI. I assume this means that we're also switching which pipe
>we're driving the port with, not just doing any
> modeset? Otherwise
>DP would stay DP, HDMI would stay HDMI, and we wouldn't see this
>problem with DP being active on an HDMI monitor (although we'd
> still
>be writing to an invalid register offset during our first DP
> disable
>which might cause other problems). Might be worth adding a
> mention
>of the pipe change to the commit message to clarify.
Got this state in a system were BIOS is lighing up DP in pipe B when
HDMI is also connected and leaving pipe A off, no idea why BIOS decided
this.
But when i915 takes over we do the modeset to light up HDMI and
reorder the pipes.
>
> The changes here look correct to me; we'll ensure the DP registers
> have
> proper offsets before we do our first modeset, and then the rest of
> the
> runtime behavior thereafter should be unchanged. So
>
> Reviewed-by: Matt Roper
>
>
> > So here for GENs older than 12, that have those registers fixed at
> > port offset range it is loading at encoder/port init while for
> > GEN12
> > it will keep setting it at encoder pre_enable() and during HW state
> > readout.
> >
> > Fixes: df6e205b ("drm/i915/tgl: move DP_TP_* to transcoder")
> > Cc: Matt Roper
> > Cc: Lucas De Marchi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++---
> > drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
> > 2 files changed, 13 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index be6c61bcbc9c..1aab93a94f40 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3252,9 +3252,6 @@ static void hsw_ddi_pre_enable_dp(struct
> > intel_atomic_state *state,
> > intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> > crtc_state->lane_count, is_mst);
> >
> > - intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
> > - intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
> > -
> > intel_edp_panel_on(intel_dp);
> >
> > intel_ddi_clk_select(encoder, crtc_state);
> > @@ -4061,12 +4058,18 @@ void intel_ddi_get_config(struct
> > intel_encoder *encoder,
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config-
> > >uapi.crtc);
> > enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > u32 temp, flags = 0;
> >
> > /* XXX: DSI transcoder paranoia */
> > if (drm_WARN_ON(_priv->drm,
> > transcoder_is_dsi(cpu_transcoder)))
> > return;
> >
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > + intel_dp->regs.dp_tp_ctl =
> > TGL_DP_TP_CTL(cpu_transcoder);
> > + intel_dp->regs.dp_tp_status =
> > TGL_DP_TP_STATUS(cpu_transcoder);
> > + }
> > +
> > intel_dsc_get_config(encoder, pipe_config);
> >
> > temp = intel_de_read(dev_priv,
> > TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > @@ -4396,6 +4399,7 @@ static const struct drm_encoder_funcs
> > intel_ddi_funcs = {
> > static struct intel_connector *
> > intel_ddi_init_dp_connector(struct intel_digital_port
> >
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add missing deinitialization cases of load failure
== Series Details ==
Series: drm/i915: Add missing deinitialization cases of load failure
URL : https://patchwork.freedesktop.org/series/75987/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8302_full -> Patchwork_17316_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17316_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_wait@write-busy@rcs0}:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-glk9/igt@gem_wait@write-b...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-glk4/igt@gem_wait@write-b...@rcs0.html
Known issues
Here are the changes found in Patchwork_17316_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
- shard-skl: [PASS][3] -> [FAIL][4] ([i915#177] / [i915#52] /
[i915#54])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-skl9/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-skl9/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [PASS][5] -> [SKIP][6] ([i915#668]) +7 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-tglb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-tglb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#648] / [i915#69])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-skl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-skl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109642] / [fdo#111068])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-iclb2/igt@kms_psr2...@frontbuffer.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-iclb5/igt@kms_psr2...@frontbuffer.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) +2 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-iclb2/igt@kms_psr@psr2_suspend.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-iclb8/igt@kms_psr@psr2_suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#69])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-skl4/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-skl6/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-apl7/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-apl4/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html
Possible fixes
* {igt@gem_ctx_isolation@preservation-s3@vcs0}:
- shard-kbl: [DMESG-WARN][17] ([i915#180]) -> [PASS][18] +3
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-kbl2/igt@gem_ctx_isolation@preservation...@vcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-kbl: [INCOMPLETE][19] ([i915#1423]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-kbl3/igt@i915_module_l...@reload-with-fault-injection.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-kbl7/igt@i915_module_l...@reload-with-fault-injection.html
- shard-apl: [INCOMPLETE][21] ([i915#1423]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-apl6/igt@i915_module_l...@reload-with-fault-injection.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/shard-apl4/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-dpms:
-
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/gt: Trace RPS events
== Series Details == Series: series starting with [1/2] drm/i915/gt: Trace RPS events URL : https://patchwork.freedesktop.org/series/76036/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2aaa5fffbe7c drm/i915/gt: Trace RPS events 1e6b7b0ed0e3 drm/i915/gt: Use the RPM config register to determine clk frequencies -:77: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #77: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 346 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/gt: Use the RPM config register to determine clk frequencies
For many configuration details within RC6 and RPS we are programming
intervals for the internal clocks. From gen11, these clocks are
configuration via the RPM_CONFIG and so for convenience, we would like
to convert to/from more natural units (ns).
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 27 +
drivers/gpu/drm/i915/gt/intel_gt_clk.c | 76 +
drivers/gpu/drm/i915/gt/intel_gt_clk.h | 21 +++
drivers/gpu/drm/i915/gt/intel_rps.c | 37 +++-
drivers/gpu/drm/i915/gt/selftest_rps.c | 7 ++-
drivers/gpu/drm/i915/i915_debugfs.c | 34 +++
drivers/gpu/drm/i915/i915_reg.h | 25
8 files changed, 162 insertions(+), 66 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44c506b7e117..fa8d78e40dad 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -91,6 +91,7 @@ gt-y += \
gt/intel_ggtt.o \
gt/intel_ggtt_fencing.o \
gt/intel_gt.o \
+ gt/intel_gt_clk.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index aab30d908072..cd466472599f 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -10,6 +10,7 @@
#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt.h"
+#include "intel_gt_clk.h"
#include "intel_llc.h"
#include "intel_rc6.h"
#include "intel_rps.h"
@@ -394,21 +395,23 @@ static int frequency_show(struct seq_file *m, void
*unused)
seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
seq_printf(m, "CAGF: %dMHz\n", cagf);
- seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
- rpupei, GT_PM_INTERVAL_TO_US(i915, rpupei));
- seq_printf(m, "RP CUR UP: %d (%dus)\n",
- rpcurup, GT_PM_INTERVAL_TO_US(i915, rpcurup));
- seq_printf(m, "RP PREV UP: %d (%dus)\n",
- rpprevup, GT_PM_INTERVAL_TO_US(i915, rpprevup));
+ seq_printf(m, "RP CUR UP EI: %d (%dns)\n",
+ rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
+ seq_printf(m, "RP CUR UP: %d (%dns)\n",
+ rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
+ seq_printf(m, "RP PREV UP: %d (%dns)\n",
+ rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
seq_printf(m, "Up threshold: %d%%\n",
rps->power.up_threshold);
- seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
- rpdownei, GT_PM_INTERVAL_TO_US(i915, rpdownei));
- seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
- rpcurdown, GT_PM_INTERVAL_TO_US(i915, rpcurdown));
- seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
- rpprevdown, GT_PM_INTERVAL_TO_US(i915, rpprevdown));
+ seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n",
+ rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
+ seq_printf(m, "RP CUR DOWN: %d (%dns)\n",
+ rpcurdown,
+ intel_gt_pm_interval_to_ns(gt, rpcurdown));
+ seq_printf(m, "RP PREV DOWN: %d (%dns)\n",
+ rpprevdown,
+ intel_gt_pm_interval_to_ns(gt, rpprevdown));
seq_printf(m, "Down threshold: %d%%\n",
rps->power.down_threshold);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clk.c
b/drivers/gpu/drm/i915/gt/intel_gt_clk.c
new file mode 100644
index ..eb5c54ce4377
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clk.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt.h"
+#include "intel_gt_clk.h"
+
+#define MHZ_19_2 1920 /* 19.2MHz, 52.083ns */
+#define MHZ_24 2400 /* 24MHz, 83.333ns */
+#define MHZ_25 2500 /* 25MHz, 80ns */
+
+u32 intel_gt_clk_frequency(struct intel_gt *gt)
+{
+ if (INTEL_GEN(gt->i915) >= 11) {
+ u32 config;
+
+ config = intel_uncore_read(gt->uncore, RPM_CONFIG0);
+ config &= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
+ config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+
+ switch (config) {
+ case 0: return MHZ_24;
+ case 1:
+ case 2: return MHZ_19_2;
+ default:
+ case 3:
[Intel-gfx] [PATCH 1/2] drm/i915/gt: Trace RPS events
Add tracek to the RPS events (interrupts, worker, enabling, threshold
selection, frequency setting), so that if we have to debug reticent HW
we have some traces to start from.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 47 ++---
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 4dcfae16a7ce..42275e25ea1b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -82,6 +82,8 @@ static void rps_enable_interrupts(struct intel_rps *rps)
GEN6_PM_RP_DOWN_THRESHOLD |
GEN6_PM_RP_DOWN_TIMEOUT);
WRITE_ONCE(rps->pm_events, events);
+ GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",
+events, rps_pm_mask(rps, rps->last_freq));
spin_lock_irq(>irq_lock);
gen6_gt_pm_enable_irq(gt, rps->pm_events);
@@ -140,6 +142,7 @@ static void rps_disable_interrupts(struct intel_rps *rps)
cancel_work_sync(>work);
rps_reset_interrupts(rps);
+ GT_TRACE(gt, "interrupts:off\n");
}
static const struct cparams {
@@ -581,6 +584,10 @@ static void rps_set_power(struct intel_rps *rps, int
new_power)
if (IS_VALLEYVIEW(i915))
goto skip_hw_write;
+ GT_TRACE(rps_to_gt(rps),
+"changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n",
+new_power, threshold_up, ei_up, threshold_down, ei_down);
+
set(uncore, GEN6_RP_UP_EI, GT_INTERVAL_FROM_US(i915, ei_up));
set(uncore, GEN6_RP_UP_THRESHOLD,
GT_INTERVAL_FROM_US(i915, ei_up * threshold_up / 100));
@@ -645,6 +652,8 @@ static void gen6_rps_set_thresholds(struct intel_rps *rps,
u8 val)
void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive)
{
+ GT_TRACE(rps_to_gt(rps), "mark interactive: %s\n", yesno(interactive));
+
mutex_lock(>power.mutex);
if (interactive) {
if (!rps->power.interactive++ && READ_ONCE(rps->active))
@@ -672,6 +681,9 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
GEN6_AGGRESSIVE_TURBO);
set(uncore, GEN6_RPNSWREQ, swreq);
+ GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d, swreq:%x\n",
+val, intel_gpu_freq(rps, val), swreq);
+
return 0;
}
@@ -684,6 +696,9 @@ static int vlv_rps_set(struct intel_rps *rps, u8 val)
err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val);
vlv_punit_put(i915);
+ GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n",
+val, intel_gpu_freq(rps, val));
+
return err;
}
@@ -717,6 +732,8 @@ void intel_rps_unpark(struct intel_rps *rps)
if (!rps->enabled)
return;
+ GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq);
+
/*
* Use the user's desired frequency as a guide, but for better
* performance, jump directly to RPe as our starting frequency.
@@ -784,6 +801,8 @@ void intel_rps_park(struct intel_rps *rps)
*/
rps->cur_freq =
max_t(int, round_down(rps->cur_freq - 1, 2), rps->min_freq);
+
+ GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq);
}
void intel_rps_boost(struct i915_request *rq)
@@ -800,6 +819,9 @@ void intel_rps_boost(struct i915_request *rq)
!dma_fence_is_signaled_locked(>fence)) {
set_bit(I915_FENCE_FLAG_BOOST, >fence.flags);
+ GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n",
+rq->fence.context, rq->fence.seqno);
+
if (!atomic_fetch_inc(>num_waiters) &&
READ_ONCE(rps->cur_freq) < rps->boost_freq)
schedule_work(>work);
@@ -895,6 +917,7 @@ static void gen6_rps_init(struct intel_rps *rps)
static bool rps_reset(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
+
/* force a reset */
rps->power.mode = -1;
rps->last_freq = -1;
@@ -1215,11 +1238,17 @@ void intel_rps_enable(struct intel_rps *rps)
if (!rps->enabled)
return;
- drm_WARN_ON(>drm, rps->max_freq < rps->min_freq);
- drm_WARN_ON(>drm, rps->idle_freq > rps->max_freq);
+ GT_TRACE(rps_to_gt(rps),
+"min:%x, max:%x, freq:[%d, %d]\n",
+rps->min_freq, rps->max_freq,
+intel_gpu_freq(rps, rps->min_freq),
+intel_gpu_freq(rps, rps->max_freq));
+
+ GEM_BUG_ON(rps->max_freq < rps->min_freq);
+ GEM_BUG_ON(rps->idle_freq > rps->max_freq);
- drm_WARN_ON(>drm, rps->efficient_freq < rps->min_freq);
- drm_WARN_ON(>drm, rps->efficient_freq > rps->max_freq);
+ GEM_BUG_ON(rps->efficient_freq < rps->min_freq);
+ GEM_BUG_ON(rps->efficient_freq > rps->max_freq);
}
static void gen6_rps_disable(struct
[Intel-gfx] [PATCH 2/2] drm/i915/gt: Use the RPM config register to determine clk frequencies
For many configuration details within RC6 and RPS we are programming
intervals for the internal clocks. From gen11, these clocks are
configuration via the RPM_CONFIG and so for convenience, we would like
to convert to/from more natural units (ns).
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 27 +
drivers/gpu/drm/i915/gt/intel_gt_clk.c | 76 +
drivers/gpu/drm/i915/gt/intel_gt_clk.h | 21 +++
drivers/gpu/drm/i915/gt/intel_rps.c | 37 +++-
drivers/gpu/drm/i915/gt/selftest_rps.c | 6 +-
drivers/gpu/drm/i915/i915_debugfs.c | 34 +++
drivers/gpu/drm/i915/i915_reg.h | 25
8 files changed, 161 insertions(+), 66 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_clk.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44c506b7e117..fa8d78e40dad 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -91,6 +91,7 @@ gt-y += \
gt/intel_ggtt.o \
gt/intel_ggtt_fencing.o \
gt/intel_gt.o \
+ gt/intel_gt_clk.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index aab30d908072..cd466472599f 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -10,6 +10,7 @@
#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt.h"
+#include "intel_gt_clk.h"
#include "intel_llc.h"
#include "intel_rc6.h"
#include "intel_rps.h"
@@ -394,21 +395,23 @@ static int frequency_show(struct seq_file *m, void
*unused)
seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
seq_printf(m, "CAGF: %dMHz\n", cagf);
- seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
- rpupei, GT_PM_INTERVAL_TO_US(i915, rpupei));
- seq_printf(m, "RP CUR UP: %d (%dus)\n",
- rpcurup, GT_PM_INTERVAL_TO_US(i915, rpcurup));
- seq_printf(m, "RP PREV UP: %d (%dus)\n",
- rpprevup, GT_PM_INTERVAL_TO_US(i915, rpprevup));
+ seq_printf(m, "RP CUR UP EI: %d (%dns)\n",
+ rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
+ seq_printf(m, "RP CUR UP: %d (%dns)\n",
+ rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
+ seq_printf(m, "RP PREV UP: %d (%dns)\n",
+ rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
seq_printf(m, "Up threshold: %d%%\n",
rps->power.up_threshold);
- seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
- rpdownei, GT_PM_INTERVAL_TO_US(i915, rpdownei));
- seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
- rpcurdown, GT_PM_INTERVAL_TO_US(i915, rpcurdown));
- seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
- rpprevdown, GT_PM_INTERVAL_TO_US(i915, rpprevdown));
+ seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n",
+ rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
+ seq_printf(m, "RP CUR DOWN: %d (%dns)\n",
+ rpcurdown,
+ intel_gt_pm_interval_to_ns(gt, rpcurdown));
+ seq_printf(m, "RP PREV DOWN: %d (%dns)\n",
+ rpprevdown,
+ intel_gt_pm_interval_to_ns(gt, rpprevdown));
seq_printf(m, "Down threshold: %d%%\n",
rps->power.down_threshold);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clk.c
b/drivers/gpu/drm/i915/gt/intel_gt_clk.c
new file mode 100644
index ..eb5c54ce4377
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clk.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt.h"
+#include "intel_gt_clk.h"
+
+#define MHZ_19_2 1920 /* 19.2MHz, 52.083ns */
+#define MHZ_24 2400 /* 24MHz, 83.333ns */
+#define MHZ_25 2500 /* 25MHz, 80ns */
+
+u32 intel_gt_clk_frequency(struct intel_gt *gt)
+{
+ if (INTEL_GEN(gt->i915) >= 11) {
+ u32 config;
+
+ config = intel_uncore_read(gt->uncore, RPM_CONFIG0);
+ config &= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
+ config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+
+ switch (config) {
+ case 0: return MHZ_24;
+ case 1:
+ case 2: return MHZ_19_2;
+ default:
+ case 3: return
[Intel-gfx] ✓ Fi.CI.IGT: success for i915 lpsp support for lpsp igt (rev9)
== Series Details == Series: i915 lpsp support for lpsp igt (rev9) URL : https://patchwork.freedesktop.org/series/74648/ State : success == Summary == CI Bug Log - changes from CI_DRM_8302_full -> Patchwork_17315_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_17315_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17315_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17315_full: ### IGT changes ### Warnings * igt@i915_pm_lpsp@screens-disabled: - shard-snb: [SKIP][1] ([fdo#109271]) -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-snb6/igt@i915_pm_l...@screens-disabled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-snb4/igt@i915_pm_l...@screens-disabled.html New tests - New tests have been introduced between CI_DRM_8302_full and Patchwork_17315_full: ### New IGT tests (7) ### * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp-1: - Statuses : 2 skip(s) - Exec time: [0.0] s * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-edp-1: - Statuses : 3 pass(s) - Exec time: [0.10, 0.45] s * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a-1: - Statuses : 2 skip(s) - Exec time: [0.0] s * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a-2: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga-1: - Statuses : 2 skip(s) - Exec time: [0.0] s * igt@kms_flip@dpms-off-confusion-interruptible@d-edp1: - Statuses : 1 pass(s) - Exec time: [8.70] s * igt@kms_flip@dpms-vs-vblank-race-interruptible@d-edp1: - Statuses : 1 pass(s) - Exec time: [3.65] s Known issues Here are the changes found in Patchwork_17315_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@kms: - shard-glk: [PASS][3] -> [TIMEOUT][4] ([i915#1383]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-glk8/igt@gem_...@kms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-glk8/igt@gem_...@kms.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([i915#61]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-hsw1/igt@gem_exec_whis...@basic-contexts-forked-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-hsw7/igt@gem_exec_whis...@basic-contexts-forked-all.html * igt@gen9_exec_parse@allowed-all: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#716]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-apl2/igt@gen9_exec_pa...@allowed-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-apl3/igt@gen9_exec_pa...@allowed-all.html * igt@i915_pm_dc@dc6-psr: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#454]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-skl1/igt@i915_pm...@dc6-psr.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-skl3/igt@i915_pm...@dc6-psr.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-snb: [PASS][11] -> [FAIL][12] ([i915#1066]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-snb5/igt@i915_pm_rc6_reside...@rc6-idle.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-snb6/igt@i915_pm_rc6_reside...@rc6-idle.html * igt@i915_pm_rpm@gem-idle: - shard-iclb: [PASS][13] -> [SKIP][14] ([i915#579]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-iclb1/igt@i915_pm_...@gem-idle.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-iclb4/igt@i915_pm_...@gem-idle.html - shard-glk: [PASS][15] -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-glk7/igt@i915_pm_...@gem-idle.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-glk5/igt@i915_pm_...@gem-idle.html - shard-tglb: [PASS][17] -> [SKIP][18] ([i915#579]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-tglb6/igt@i915_pm_...@gem-idle.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-tglb8/igt@i915_pm_...@gem-idle.html - shard-skl: [PASS][19] -> [SKIP][20] ([fdo#109271]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-skl6/igt@i915_pm_...@gem-idle.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/shard-skl7/igt@i915_pm_...@gem-idle.html - shard-hsw: [PASS][21] -> [SKIP][22] ([fdo#109271])
Re: [Intel-gfx] [PATCH v7 i-g-t 3/4] lib: Add function to hash a framebuffer
Hi, On Thu, Apr 16, 2020 at 08:49:42AM -0400, Rodrigo Siqueira wrote: > First of all, thank you a lot for your review and for testing this > patchset. I'm going to prepare a new version trying to address all > issues highlight by you, Petri, and Simon (I'm already working in a new > version). That would be awesome, thanks :) > Just a note, I run this test on top of VKMS in a virtual machine (x86). Yeah, that's what I assumed. Cc me when the new version will be ready, I'll give it a shot on an arm32 board. Maxime signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS interrupt generation
== Series Details == Series: series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS interrupt generation URL : https://patchwork.freedesktop.org/series/75983/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8302_full -> Patchwork_17314_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17314_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17314_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17314_full: ### IGT changes ### Possible regressions * igt@gem_ppgtt@blt-vs-render-ctx0: - shard-apl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-apl3/igt@gem_pp...@blt-vs-render-ctx0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-apl1/igt@gem_pp...@blt-vs-render-ctx0.html Known issues Here are the changes found in Patchwork_17314_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-kbl1/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-kbl4/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@gt_pm: - shard-tglb: [PASS][5] -> [DMESG-FAIL][6] ([i915#1725]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-tglb8/igt@i915_selftest@live@gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-tglb7/igt@i915_selftest@live@gt_pm.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#54] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-64x21-onscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-apl8/igt@kms_cursor_...@pipe-a-cursor-64x21-onscreen.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][9] -> [FAIL][10] ([IGT#5] / [i915#697]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-skl9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-skl5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [PASS][11] -> [FAIL][12] ([IGT#5]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-skl10/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-skl3/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#1188]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-skl3/igt@kms_...@bpc-switch.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-skl8/igt@kms_...@bpc-switch.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#198]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-skl4/igt@kms_...@bpc-switch-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-skl7/igt@kms_...@bpc-switch-suspend.html * igt@kms_lease@page_flip_implicit_plane: - shard-snb: [PASS][17] -> [SKIP][18] ([fdo#109271]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-snb1/igt@kms_lease@page_flip_implicit_plane.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-snb2/igt@kms_lease@page_flip_implicit_plane.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-apl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/shard-iclb2/igt@kms_psr2...@frontbuffer.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/shard-iclb1/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_suspend: - shard-iclb:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Enable application triggered OA reports (rev2)
== Series Details == Series: drm/i915/perf: Enable application triggered OA reports (rev2) URL : https://patchwork.freedesktop.org/series/75310/ State : success == Summary == CI Bug Log - changes from CI_DRM_8311 -> Patchwork_17326 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17326/index.html Known issues Here are the changes found in Patchwork_17326 that come from known issues: ### IGT changes ### Warnings * igt@amdgpu/amd_prime@i915-to-amd: - fi-bwr-2160:[FAIL][1] -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8311/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17326/fi-bwr-2160/igt@amdgpu/amd_pr...@i915-to-amd.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (51 -> 46) -- Additional (1): fi-kbl-7560u Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8311 -> Patchwork_17326 CI-20190529: 20190529 CI_DRM_8311: 19367bb5e65eaf0719597b3ff244fd1c2ea12bda @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17326: f12265d9a10d03229237d68fd7d47de82b05de6b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f12265d9a10d drm/i915/perf: Enable application triggered OA reports == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17326/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/perf: Enable application triggered OA reports (rev2)
== Series Details == Series: drm/i915/perf: Enable application triggered OA reports (rev2) URL : https://patchwork.freedesktop.org/series/75310/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/amdgpu: utilize subconnector property for DP through atombios
On Wed, Apr 15, 2020 at 6:05 AM Jani Nikula wrote:
>
>
> Alex, Harry, Christian, can you please eyeball this series and see if it
> makes sense for you?
>
Patches 4, 5 are:
Acked-by: Alex Deucher
Feel free to take them through whichever tree you want.
Alex
> Thanks,
> Jani.
>
>
> On Tue, 07 Apr 2020, Jeevan B wrote:
> > From: Oleg Vasilev
> >
> > Since DP-specific information is stored in driver's structures, every
> > driver needs to implement subconnector property by itself.
> >
> > v2: rebase
> >
> > Cc: Alex Deucher
> > Cc: Christian König
> > Cc: David (ChunMing) Zhou
> > Cc: amd-...@lists.freedesktop.org
> > Signed-off-by: Jeevan B
> > Signed-off-by: Oleg Vasilev
> > Reviewed-by: Emil Velikov
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20190829114854.1539-6-oleg.vasi...@intel.com
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 10 ++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 +
> > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 18 +-
> > 3 files changed, 28 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > index f355d9a..71aade0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > @@ -26,6 +26,7 @@
> >
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include "amdgpu.h"
> > @@ -1405,6 +1406,10 @@ amdgpu_connector_dp_detect(struct drm_connector
> > *connector, bool force)
> > pm_runtime_put_autosuspend(connector->dev->dev);
> > }
> >
> > + drm_dp_set_subconnector_property(_connector->base,
> > + ret,
> > + amdgpu_dig_connector->dpcd,
> > +
> > amdgpu_dig_connector->downstream_ports);
> > return ret;
> > }
> >
> > @@ -1951,6 +1956,11 @@ amdgpu_connector_add(struct amdgpu_device *adev,
> > if (has_aux)
> > amdgpu_atombios_dp_aux_init(amdgpu_connector);
> >
> > + if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > + connector_type == DRM_MODE_CONNECTOR_eDP) {
> > +
> > drm_mode_add_dp_subconnector_property(_connector->base);
> > + }
> > +
> > return;
> >
> > failed:
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> > index 37ba07e..04a430e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> > @@ -469,6 +469,7 @@ struct amdgpu_encoder {
> > struct amdgpu_connector_atom_dig {
> > /* displayport */
> > u8 dpcd[DP_RECEIVER_CAP_SIZE];
> > + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> > u8 dp_sink_type;
> > int dp_clock;
> > int dp_lane_count;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > index 9b74cfd..900b272 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > @@ -328,6 +328,22 @@ static void amdgpu_atombios_dp_probe_oui(struct
> > amdgpu_connector *amdgpu_connect
> > buf[0], buf[1], buf[2]);
> > }
> >
> > +static void amdgpu_atombios_dp_ds_ports(struct amdgpu_connector
> > *amdgpu_connector)
> > +{
> > + struct amdgpu_connector_atom_dig *dig_connector =
> > amdgpu_connector->con_priv;
> > + int ret;
> > +
> > + if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) {
> > + ret = drm_dp_dpcd_read(_connector->ddc_bus->aux,
> > +DP_DOWNSTREAM_PORT_0,
> > +dig_connector->downstream_ports,
> > +DP_MAX_DOWNSTREAM_PORTS);
> > + if (ret)
> > + memset(dig_connector->downstream_ports, 0,
> > +DP_MAX_DOWNSTREAM_PORTS);
> > + }
> > +}
> > +
> > int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
> > {
> > struct amdgpu_connector_atom_dig *dig_connector =
> > amdgpu_connector->con_priv;
> > @@ -343,7 +359,7 @@ int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector
> > *amdgpu_connector)
> > dig_connector->dpcd);
> >
> > amdgpu_atombios_dp_probe_oui(amdgpu_connector);
> > -
> > + amdgpu_atombios_dp_ds_ports(amdgpu_connector);
> > return 0;
> > }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: Enable application triggered OA reports (rev2)
== Series Details == Series: drm/i915/perf: Enable application triggered OA reports (rev2) URL : https://patchwork.freedesktop.org/series/75310/ State : warning == Summary == $ dim checkpatch origin/drm-tip f12265d9a10d drm/i915/perf: Enable application triggered OA reports -:26: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #26: v2: Add OA trigger registers to the pardon list for isolated whitelist (Chris) total: 0 errors, 1 warnings, 0 checks, 100 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Scrub execlists state on resume
== Series Details == Series: drm/i915/gt: Scrub execlists state on resume URL : https://patchwork.freedesktop.org/series/76026/ State : success == Summary == CI Bug Log - changes from CI_DRM_8310 -> Patchwork_17325 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17325/index.html Known issues Here are the changes found in Patchwork_17325 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-edid-read: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([i915#976]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8310/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17325/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html Possible fixes * igt@i915_selftest@live@gt_timelines: - fi-bwr-2160:[INCOMPLETE][3] ([i915#489]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8310/fi-bwr-2160/igt@i915_selftest@live@gt_timelines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17325/fi-bwr-2160/igt@i915_selftest@live@gt_timelines.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [SKIP][5] ([fdo#109271]) -> [PASS][6] +20 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8310/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17325/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 [i915#976]: https://gitlab.freedesktop.org/drm/intel/issues/976 Participating hosts (52 -> 45) -- Missing(7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8310 -> Patchwork_17325 CI-20190529: 20190529 CI_DRM_8310: 75646ce570b1e34dad7096169905e29cf755845c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17325: c0cf9d36c70f79573de1f4aac954d39d1143fc76 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c0cf9d36c70f drm/i915/gt: Scrub execlists state on resume == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17325/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 i-g-t 3/4] lib: Add function to hash a framebuffer
Hi Maxime,
First of all, thank you a lot for your review and for testing this
patchset. I'm going to prepare a new version trying to address all
issues highlight by you, Petri, and Simon (I'm already working in a new
version).
Just a note, I run this test on top of VKMS in a virtual machine (x86).
Best Regards
On 04/15, Maxime Ripard wrote:
> Hi Rodrigo,
>
> I gave your (and Brian's) patches on a RPi, and there's a couple of
> things that need to be fixed.
>
> On Mon, Oct 21, 2019 at 10:00:00PM -0300, Brian Starkey wrote:
> > To use writeback buffers as a CRC source, we need to be able to hash
> > them. Implement a simple FVA-1a hashing routine for this purpose.
> >
> > Doing a bytewise hash on the framebuffer directly can be very slow if
> > the memory is noncached. By making a copy of each line in the FB first
> > (which can take advantage of word-access speedup), we can do the hash
> > on a cached copy, which is much faster (10x speedup on my platform).
> >
> > V6: Simon Sir
> > - Replace #define by plain uint32_t variables
> > - Return -EINVAL in case fb->num_planes != 1
> > - Directly assign the mmap result to ptr
> > - No need to copy the whole stride, just copy fb->width * cpp since
> > we're only going to read that
> >
> > v5: use igt_memcpy_from_wc() instead of plain memcpy, as suggested by
> > Chris Wilson
> >
> > Signed-off-by: Brian Starkey
> > [rebased and updated to the most recent API]
> > Signed-off-by: Liviu Dudau
> > [rebased and updated the patch to address feedback]
> > Signed-off-by: Rodrigo Siqueira
> > Reviewed-by: Simon Ser
> > ---
> > lib/igt_fb.c | 68
> > lib/igt_fb.h | 2 ++
> > 2 files changed, 70 insertions(+)
> >
> > diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> > index 6b674c1b..64d52634 100644
> > --- a/lib/igt_fb.c
> > +++ b/lib/igt_fb.c
> > @@ -3491,6 +3491,74 @@ bool igt_fb_supported_format(uint32_t drm_format)
> > return false;
> > }
> >
> > +/*
> > + * This implements the FNV-1a hashing algorithm instead of CRC, for
> > + * simplicity
> > + * http://www.isthe.com/chongo/tech/comp/fnv/index.html
> > + *
> > + * hash = offset_basis
> > + * for each octet_of_data to be hashed
> > + * hash = hash xor octet_of_data
> > + * hash = hash * FNV_prime
> > + * return hash
> > + *
> > + * 32 bit offset_basis = 2166136261
> > + * 32 bit FNV_prime = 224 + 28 + 0x93 = 16777619
> > + */
> > +int igt_fb_get_crc(struct igt_fb *fb, igt_crc_t *crc)
> > +{
> > + uint32_t FNV1a_OFFSET_BIAS = 2166136261;
> > + uint32_t FNV1a_PRIME = 16777619;
> > + uint32_t hash;
> > + void *map;
> > + char *ptr, *line = NULL;
> > + int x, y, cpp = igt_drm_format_to_bpp(fb->drm_format) / 8;
> > + uint32_t stride = calc_plane_stride(fb, 0);
> > +
> > + if (fb->num_planes != 1)
> > + return -EINVAL;
> > +
> > + if (fb->is_dumb)
> > + ptr = kmstest_dumb_map_buffer(fb->fd, fb->gem_handle, fb->size,
> > + PROT_READ);
> > + else
> > + ptr = gem_mmap__gtt(fb->fd, fb->gem_handle, fb->size,
> > + PROT_READ);
>
> You should be using igt_fb_map_buffer here
>
> > + /*
> > +* Framebuffers are often uncached, which can make byte-wise accesses
> > +* very slow. We copy each line of the FB into a local buffer to speed
> > +* up the hashing.
> > +*/
> > + line = malloc(stride);
> > + if (!line) {
> > + munmap(map, fb->size);
> > + return -ENOMEM;
> > + }
> > +
> > + hash = FNV1a_OFFSET_BIAS;
> > +
> > + for (y = 0; y < fb->height; y++, ptr += stride) {
> > +
> > + igt_memcpy_from_wc(line, ptr, fb->width * cpp);
> > +
> > + for (x = 0; x < fb->width * cpp; x++) {
> > + hash ^= line[x];
> > + hash *= FNV1a_PRIME;
> > + }
> > + }
> > +
> > + crc->n_words = 1;
> > + crc->crc[0] = hash;
> > +
> > + free(line);
> > + munmap(map, fb->size);
>
> And this will lead to a segfault here, since map has not been
> initialized. I'm assuming the intention is to have map be the returned
> value of mmap, and ptr to be initialized to that same value, and use
> that as your current line pointer later on (the error path from the
> malloc has the same issue).
>
> Maxime
--
Rodrigo Siqueira
https://siqueira.tech
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gt: Scrub execlists state on resume
== Series Details == Series: drm/i915/gt: Scrub execlists state on resume URL : https://patchwork.freedesktop.org/series/76026/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] topic/phy-compliance
Quoting Jani Nikula (2020-04-15 10:48:15) > On Wed, 15 Apr 2020, Daniel Vetter wrote: > > On Wed, Apr 15, 2020 at 8:40 AM Jani Nikula > > wrote: > >> > >> On Wed, 08 Apr 2020, Maarten Lankhorst > >> wrote: > >> > Hey, > >> > > >> > Here's a pull request to pull in the DP PHY Compliance series. > >> > It's based on top of drm/drm-next, and contains all patches for core, > >> > amd and i915. :) > >> > >> Ping, I don't see this merged in any tree yet. > > > > Generally topic pull requests get pulled into all relevant trees, > > which would be drm-misc, drm-intel and drm-amd here. All of the > > optional ofc if you do instead maintainer-acks for merging through > > another tree. > > > > Since I wasn't involved in this no idea who requested the topic tree > > instead of acks, and the pull isn't addressed to specific people who > > should pull it in (I generally add that to avoid confusion like this > > here), but this aint something that drm.git needs to pull. Just stuff > > it into one of the trees as usual. Also just noticed that amd > > maintainers arent even cc'ed, adding Alex. You guys pls figure this > > out :-) > > It seemed like drm-misc and drm-intel would be out-of-sync for too long > before we'd get all of them eventually (back)merged together, so I > leaned towards the topic branch. Of course, the point starts to be moot > if it has already taken more than a week to merge this anywhere... > > And I'm pinging about merging the topic pull to drm-misc and drm-intel; > I'm currently not covering drm-intel. Pulled to drm-intel-next-queued now. Regards, Joonas > > BR, > Jani. > > > > > > -Daniel > > > >> > >> BR, > >> Jani. > >> > >> > >> > > >> > Cheers, > >> > Maarten > >> > > >> > topic/phy-compliance-2020-04-08: > >> > Topic pull request for topic/phy-compliance: > >> > - Standardize DP_PHY_TEST_PATTERN name. > >> > - Add support for setting/getting test pattern from sink. > >> > - Implement DP PHY compliance to i915. > >> > The following changes since commit > >> > 12ab316ced2c5f32ced0e6300a054db644b5444a: > >> > > >> > Merge tag 'amd-drm-next-5.7-2020-04-01' of > >> > git://people.freedesktop.org/~agd5f/linux into drm-next (2020-04-08 > >> > 09:34:27 +1000) > >> > > >> > are available in the Git repository at: > >> > > >> > git://anongit.freedesktop.org/drm/drm-misc > >> > tags/topic/phy-compliance-2020-04-08 > >> > > >> > for you to fetch changes up to 8cdf727119289db3a98835662eb28e1c5ad835f1: > >> > > >> > drm/i915/dp: Program vswing, pre-emphasis, test-pattern (2020-04-08 > >> > 14:41:09 +0200) > >> > > >> > > >> > Topic pull request for topic/phy-compliance: > >> > - Standardize DP_PHY_TEST_PATTERN name. > >> > - Add support for setting/getting test pattern from sink. > >> > - Implement DP PHY compliance to i915. > >> > > >> > > >> > Animesh Manna (7): > >> > drm/amd/display: Align macro name as per DP spec > >> > drm/dp: get/set phy compliance pattern > >> > drm/i915/dp: Made intel_dp_adjust_train() non-static > >> > drm/i915/dp: Preparation for DP phy compliance auto test > >> > drm/i915/dp: Add debugfs entry for DP phy compliance > >> > drm/i915/dp: Register definition for DP compliance register > >> > drm/i915/dp: Program vswing, pre-emphasis, test-pattern > >> > > >> > drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- > >> > drivers/gpu/drm/drm_dp_helper.c| 94 +++ > >> > .../gpu/drm/i915/display/intel_display_debugfs.c | 12 +- > >> > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > >> > drivers/gpu/drm/i915/display/intel_dp.c| 171 > >> > + > >> > drivers/gpu/drm/i915/display/intel_dp.h| 1 + > >> > .../gpu/drm/i915/display/intel_dp_link_training.c | 9 +- > >> > .../gpu/drm/i915/display/intel_dp_link_training.h | 4 + > >> > drivers/gpu/drm/i915/i915_reg.h| 18 +++ > >> > include/drm/drm_dp_helper.h| 33 +++- > >> > 10 files changed, 337 insertions(+), 8 deletions(-) > >> > >> -- > >> Jani Nikula, Intel Open Source Graphics Center > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for SAGV support for Gen12+ (rev21)
== Series Details == Series: SAGV support for Gen12+ (rev21) URL : https://patchwork.freedesktop.org/series/75129/ State : success == Summary == CI Bug Log - changes from CI_DRM_8301_full -> Patchwork_17312_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17312_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_draw_crc@draw-method-rgb565-render-untiled: - shard-glk: [PASS][1] -> [FAIL][2] ([i915#52] / [i915#54]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-glk9/igt@kms_draw_...@draw-method-rgb565-render-untiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-glk2/igt@kms_draw_...@draw-method-rgb565-render-untiled.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#79]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-glk9/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#34]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-glk8/igt@kms_f...@2x-plain-flip-fb-recreate-interruptible.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-glk7/igt@kms_f...@2x-plain-flip-fb-recreate-interruptible.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#1188]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-skl4/igt@kms_...@bpc-switch-dpms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-skl5/igt@kms_...@bpc-switch-dpms.html Possible fixes * igt@i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][9] ([i915#454]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-iclb2/igt@i915_pm...@dc6-psr.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-iclb1/igt@i915_pm...@dc6-psr.html * igt@i915_selftest@live@requests: - shard-tglb: [INCOMPLETE][11] ([i915#1531]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-tglb1/igt@i915_selftest@l...@requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-tglb8/igt@i915_selftest@l...@requests.html * igt@i915_suspend@debugfs-reader: - shard-skl: [INCOMPLETE][13] ([i915#69]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-skl6/igt@i915_susp...@debugfs-reader.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-skl8/igt@i915_susp...@debugfs-reader.html * igt@i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][15] ([i915#180]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-apl4/igt@i915_susp...@sysfs-reader.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-apl3/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][17] ([i915#180]) -> [PASS][18] +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-kbl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy: - shard-glk: [FAIL][19] ([i915#1566]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-crc-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-crc-legacy.html * igt@kms_flip@2x-plain-flip-fb-recreate: - shard-glk: [FAIL][21] ([i915#34]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-glk8/igt@kms_f...@2x-plain-flip-fb-recreate.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-glk2/igt@kms_f...@2x-plain-flip-fb-recreate.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [FAIL][23] ([i915#79]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/shard-skl2/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][25] ([i915#1188]) -> [PASS][26] +1 similar issue [25]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Enable DP Display Audio WA (rev6)
== Series Details ==
Series: drm/i915/display: Enable DP Display Audio WA (rev6)
URL : https://patchwork.freedesktop.org/series/75582/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8309 -> Patchwork_17324
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17324/index.html
Known issues
Here are the changes found in Patchwork_17324 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][1] -> [DMESG-WARN][2] ([i915#203]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8309/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17324/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-skl-6770hq: [PASS][3] -> [SKIP][4] ([fdo#109271]) +5 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8309/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17324/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-skl-6770hq: [PASS][5] -> [DMESG-WARN][6] ([i915#106])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8309/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17324/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
Possible fixes
* {igt@kms_flip@basic-flip-vs-wf_vblank@b-dvi-d1}:
- fi-bwr-2160:[FAIL][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8309/fi-bwr-2160/igt@kms_flip@basic-flip-vs-wf_vbl...@b-dvi-d1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17324/fi-bwr-2160/igt@kms_flip@basic-flip-vs-wf_vbl...@b-dvi-d1.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][9] ([fdo#109271]) -> [FAIL][10] ([i915#62])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8309/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17324/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106
[i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Participating hosts (52 -> 46)
--
Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8309 -> Patchwork_17324
CI-20190529: 20190529
CI_DRM_8309: 7532b3183c849056c824828bafb4ab0b525e586e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5593: 1c658f5e46598ae93345177d4981ef54704daec6 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17324: 824059d46f5a1c38b53c179306d3872f6647df06 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
824059d46f5a drm/i915/display: Enable DP Display Audio WA
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17324/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/perf: Enable application triggered OA reports
Gen12 brought an important redesign of the OA unit, splitting it in 2
with a per context part (OAR) and a global part (OAG).
OAR deals with per context counters and implements the
MI_REPORT_PERF_COUNT command.
OAG deals with global counters and the OA buffer.
Unfortunately some of the counters available in OAG are not available
in OAR, for instance counters that would report global caches
utilization.
Since applications making use of this want to access those additional
OAG counters we can enable them to generate a report from their
command buffer into the OA buffer. This is somewhat equivalent to
having them doing their own MI_REPORT_PERF_COUNT. The application then
parse the OA buffer as they were doing previously, only looking for a
begin/end OA report with the appropriate reason field in the OA buffer
instead of using MI_REPORT_PERF_COUNT generated reports for begin/end.
v2: Add OA trigger registers to the pardon list for isolated whitelist (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Umesh Nerlige Ramappa (v1)
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c| 18 ++
drivers/gpu/drm/i915/gt/selftest_workarounds.c | 9 +
drivers/gpu/drm/i915/i915_perf.c | 10 +++---
drivers/gpu/drm/i915/i915_reg.h| 2 ++
4 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5b1a03d2fd25..c3a3e7b9d522 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1127,6 +1127,10 @@ static void gen9_whitelist_build(struct i915_wa_list *w)
/* WaSendPushConstantsFromMMIO:skl,bxt */
whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+ /* Allow userspace trigger OA report generation in OA buffer. */
+ whitelist_reg(w, OAREPORTTRIG2);
+ whitelist_reg(w, OAREPORTTRIG6);
}
static void skl_whitelist_build(struct intel_engine_cs *engine)
@@ -1208,6 +1212,10 @@ static void cnl_whitelist_build(struct intel_engine_cs
*engine)
/* WaEnablePreemptionGranularityControlByUMD:cnl */
whitelist_reg(w, GEN8_CS_CHICKEN1);
+
+ /* Allow userspace trigger OA report generation in OA buffer. */
+ whitelist_reg(w, OAREPORTTRIG2);
+ whitelist_reg(w, OAREPORTTRIG6);
}
static void icl_whitelist_build(struct intel_engine_cs *engine)
@@ -1237,6 +1245,12 @@ static void icl_whitelist_build(struct intel_engine_cs
*engine)
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
RING_FORCE_TO_NONPRIV_ACCESS_RD |
RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ /*
+* Allow userspace trigger OA report generation in OA buffer.
+*/
+ whitelist_reg(w, OAREPORTTRIG2);
+ whitelist_reg(w, OAREPORTTRIG6);
break;
case VIDEO_DECODE_CLASS:
@@ -1281,6 +1295,10 @@ static void tgl_whitelist_build(struct intel_engine_cs
*engine)
/* Wa_1806527549:tgl */
whitelist_reg(w, HIZ_CHICKEN);
+
+ /* Allow userspace trigger OA report generation in OA buffer. */
+ whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
+ whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
break;
default:
break;
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 5ed323254ee1..0c05ebf5f55a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -915,6 +915,15 @@ static bool pardon_reg(struct drm_i915_private *i915,
i915_reg_t reg)
static const struct regmask pardon[] = {
{ GEN9_CTX_PREEMPT_REG, INTEL_GEN_MASK(9, 9) },
{ GEN8_L3SQCREG4, INTEL_GEN_MASK(9, 9) },
+
+ /*
+* These registers are global ones. They are used to trigger
+* OA reports into the global OA buffer.
+*/
+ { OAREPORTTRIG2, INTEL_GEN_MASK(7, 11) },
+ { OAREPORTTRIG6, INTEL_GEN_MASK(7, 11) },
+ { GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },
};
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5cde3e4e7be6..19bdbda94cfd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1450,7 +1450,8 @@ static void gen8_init_oa_buffer(struct i915_perf_stream
*stream)
* bit."
*/
intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset |
- OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
+
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Enable DP Display Audio WA (rev6)
== Series Details == Series: drm/i915/display: Enable DP Display Audio WA (rev6) URL : https://patchwork.freedesktop.org/series/75582/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Move the batch buffer pool from the engine to the gt
== Series Details == Series: drm/i915/gt: Move the batch buffer pool from the engine to the gt URL : https://patchwork.freedesktop.org/series/75979/ State : success == Summary == CI Bug Log - changes from CI_DRM_8301_full -> Patchwork_17310_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17310_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-apl8/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@vebox.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-apl3/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@vebox.html * igt@i915_selftest@live@requests: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([i915#1531] / [i915#1581]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-iclb6/igt@i915_selftest@l...@requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-iclb2/igt@i915_selftest@l...@requests.html * igt@i915_suspend@forcewake: - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#58] / [k.org#198133]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-glk9/igt@i915_susp...@forcewake.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-glk4/igt@i915_susp...@forcewake.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-apl6/igt@kms_cursor_...@pipe-a-cursor-128x128-onscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-apl2/igt@kms_cursor_...@pipe-a-cursor-128x128-onscreen.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-apl6/igt@kms_cursor_...@pipe-b-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-apl8/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_draw_crc@draw-method-rgb565-render-untiled: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#52] / [i915#54]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-glk9/igt@kms_draw_...@draw-method-rgb565-render-untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-glk4/igt@kms_draw_...@draw-method-rgb565-render-untiled.html * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#34]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-glk8/igt@kms_f...@2x-plain-flip-fb-recreate-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-glk2/igt@kms_f...@2x-plain-flip-fb-recreate-interruptible.html * igt@kms_flip@plain-flip-fb-recreate: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#34]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-skl5/igt@kms_f...@plain-flip-fb-recreate.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-skl1/igt@kms_f...@plain-flip-fb-recreate.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-skl4/igt@kms_...@bpc-switch-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-skl9/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-iclb2/igt@kms_psr@psr2_basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-iclb1/igt@kms_psr@psr2_basic.html Possible fixes * igt@i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][23] ([i915#454]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/shard-iclb2/igt@i915_pm...@dc6-psr.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/shard-iclb3/igt@i915_pm...@dc6-psr.html * igt@i915_suspend@debugfs-reader: - shard-skl: [INCOMPLETE][25] ([i915#69]) -> [PASS][26] [25]:
[Intel-gfx] [PATCH] drm/i915/gt: Scrub execlists state on resume
Before we resume, we reset the HW so we restart from a known good state.
However, as a part of the reset process, we drain our pending CS event
queue -- and if we are resuming that does not correspond to internal
state. On setup, we are scrubbing the CS pointers, but alas only on
setup.
Apply the sanitization not just to setup, but to all resumes.
Reported-by: Venkata Ramana Nayana
Signed-off-by: Chris Wilson
Cc: Venkata Ramana Nayana
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 4 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 72 +++-
3 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index f3c9d302ecf8..ebe20de7eb70 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -411,6 +411,7 @@ struct intel_engine_cs {
void(*irq_enable)(struct intel_engine_cs *engine);
void(*irq_disable)(struct intel_engine_cs *engine);
+ void(*sanitize)(struct intel_engine_cs *engine);
int (*resume)(struct intel_engine_cs *engine);
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 3e8a56c7d818..6bdb74892a1e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -147,6 +147,10 @@ static void gt_sanitize(struct intel_gt *gt, bool force)
if (intel_gt_is_wedged(gt))
intel_gt_unset_wedged(gt);
+ for_each_engine(engine, gt, id)
+ if (engine->sanitize)
+ engine->sanitize(engine);
+
intel_uc_sanitize(>uc);
for_each_engine(engine, gt, id)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6fbad5e2343f..34f67eb9bfa1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3615,6 +3615,43 @@ static int intel_init_workaround_bb(struct
intel_engine_cs *engine)
return ret;
}
+static void reset_csb_pointers(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlists * const execlists = >execlists;
+ const unsigned int reset_value = execlists->csb_size - 1;
+
+ ring_set_paused(engine, 0);
+
+ /*
+* After a reset, the HW starts writing into CSB entry [0]. We
+* therefore have to set our HEAD pointer back one entry so that
+* the *first* entry we check is entry 0. To complicate this further,
+* as we don't wait for the first interrupt after reset, we have to
+* fake the HW write to point back to the last entry so that our
+* inline comparison of our cached head position against the last HW
+* write works even before the first interrupt.
+*/
+ execlists->csb_head = reset_value;
+ WRITE_ONCE(*execlists->csb_write, reset_value);
+ wmb(); /* Make sure this is visible to HW (paranoia?) */
+
+ /*
+* Sometimes Icelake forgets to reset its pointers on a GPU reset.
+* Bludgeon them with a mmio update to be sure.
+*/
+ ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
+reset_value << 8 | reset_value);
+ ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);
+
+ invalidate_csb_entries(>csb_status[0],
+ >csb_status[reset_value]);
+}
+
+static void execlists_sanitize(struct intel_engine_cs *engine)
+{
+ reset_csb_pointers(engine);
+}
+
static void enable_error_interrupt(struct intel_engine_cs *engine)
{
u32 status;
@@ -3754,38 +3791,6 @@ static void execlists_reset_prepare(struct
intel_engine_cs *engine)
intel_engine_stop_cs(engine);
}
-static void reset_csb_pointers(struct intel_engine_cs *engine)
-{
- struct intel_engine_execlists * const execlists = >execlists;
- const unsigned int reset_value = execlists->csb_size - 1;
-
- ring_set_paused(engine, 0);
-
- /*
-* After a reset, the HW starts writing into CSB entry [0]. We
-* therefore have to set our HEAD pointer back one entry so that
-* the *first* entry we check is entry 0. To complicate this further,
-* as we don't wait for the first interrupt after reset, we have to
-* fake the HW write to point back to the last entry so that our
-* inline comparison of our cached head position against the last HW
-* write works even before the first interrupt.
-*/
- execlists->csb_head = reset_value;
- WRITE_ONCE(*execlists->csb_write, reset_value);
- wmb(); /* Make sure this is visible to HW (paranoia?) */
-
- /*
-* Sometimes Icelake forgets to reset its pointers on a GPU reset.
-*
[Intel-gfx] [v6] drm/i915/display: Enable DP Display Audio WA
For certain DP VDSC bpp settings, hblank asserts before hblank_early,
leading to a bad audio state. Driver need to program "hblank early
enable" and "samples per line" parameters in AUDIO_CONFIG_BE
register.
This is Display Audio WA #1406928334 for 4k+VDSC usecase
applicable on DP encoders. Implemented the same.
v2: Fixed build failures on 32bit machine.
v3: Dropped u64, added helpers for sample room calculation,
other general comments as per Jani Nikula's feedback.
Also fixed connector type check (spotted by Anshuman)
v4: Addressed Jani Nikula and Kai's review comments.
v5: Addressed Anshuman's review comment and used crtc_* variable
to get timings.
v6: Dropped a redundant initialization.
Reviewed-by: Anshuman Gupta
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_audio.c | 146 +
drivers/gpu/drm/i915/i915_reg.h| 16 +++
2 files changed, 162 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 57b80971ae78..dc311bb227f1 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -514,6 +514,148 @@ static void hsw_audio_codec_disable(struct intel_encoder
*encoder,
mutex_unlock(_priv->av_mutex);
}
+/* Add a factor to take care of rounding and truncations */
+#define ROUNDING_FACTOR 1
+
+static unsigned int get_hblank_early_enable_config(struct intel_encoder
*encoder,
+ const struct
intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ unsigned int link_clks_available, link_clks_required;
+ unsigned int tu_data, tu_line, link_clks_active;
+ unsigned int hblank_rise, hblank_early_prog;
+ unsigned int h_active, h_total, hblank_delta, pixel_clk, v_total;
+ unsigned int fec_coeff, refresh_rate, cdclk, vdsc_bpp;
+
+ h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
+ h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
+ v_total = crtc_state->hw.adjusted_mode.crtc_vtotal;
+ pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
+ refresh_rate = crtc_state->hw.adjusted_mode.vrefresh;
+ vdsc_bpp = crtc_state->dsc.compressed_bpp;
+ cdclk = i915->cdclk.hw.cdclk;
+ /* fec= 0.972261, using rounding multiplier of 100 */
+ fec_coeff = 972261;
+
+ drm_dbg_kms(>drm, "h_active = %u link_clk = %u :"
+ "lanes = %u vdsc_bpp = %u cdclk = %u\n",
+ h_active, crtc_state->port_clock, crtc_state->lane_count,
+ vdsc_bpp, cdclk);
+
+ link_clks_available = h_total - h_active) *
+ ((crtc_state->port_clock * ROUNDING_FACTOR) /
+ pixel_clk)) / ROUNDING_FACTOR) - 28);
+
+ link_clks_required = DIV_ROUND_UP(192000, (refresh_rate *
+ v_total)) * ((48 /
+ crtc_state->lane_count) + 2);
+
+ if (link_clks_available > link_clks_required)
+ hblank_delta = 32;
+ else
+ hblank_delta = DIV_ROUND_UP(5 * ROUNDING_FACTOR) /
+ crtc_state->port_clock) + ((5 *
+ ROUNDING_FACTOR) /
+ cdclk)) * pixel_clk),
+ ROUNDING_FACTOR);
+
+ tu_data = (pixel_clk * vdsc_bpp * 8) / ((crtc_state->port_clock *
+ crtc_state->lane_count * fec_coeff) / 100);
+ tu_line = (((h_active * crtc_state->port_clock * fec_coeff) /
+ 100) / (64 * pixel_clk));
+ link_clks_active = (tu_line - 1) * 64 + tu_data;
+
+ hblank_rise = ((link_clks_active + 6 * DIV_ROUND_UP(link_clks_active,
+ 250) + 4) * ((pixel_clk * ROUNDING_FACTOR) /
+ crtc_state->port_clock)) / ROUNDING_FACTOR;
+
+ hblank_early_prog = h_active - hblank_rise + hblank_delta;
+
+ return hblank_early_prog;
+}
+
+static unsigned int get_sample_room_req_config(const struct intel_crtc_state
*crtc_state)
+{
+ unsigned int h_active, h_total, pixel_clk;
+ unsigned int samples_room;
+
+ h_active = crtc_state->hw.adjusted_mode.hdisplay;
+ h_total = crtc_state->hw.adjusted_mode.htotal;
+ pixel_clk = crtc_state->hw.adjusted_mode.clock;
+
+ samples_room = h_total - h_active) * ((crtc_state->port_clock *
+ ROUNDING_FACTOR) / pixel_clk)) /
+ ROUNDING_FACTOR) - 12) / ((48 /
+ crtc_state->lane_count) + 2);
+
+ return samples_room;
+}
+
+static void enable_audio_dsc_wa(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private
Re: [Intel-gfx] [v5] drm/i915/display: Enable DP Display Audio WA
> -Original Message- > From: Jani Nikula > Sent: Thursday, April 16, 2020 3:43 PM > To: Gupta, Anshuman ; Shankar, Uma > > Cc: intel-gfx@lists.freedesktop.org; Vehmanen, Kai > Subject: Re: [v5] drm/i915/display: Enable DP Display Audio WA > > On Thu, 16 Apr 2020, Anshuman Gupta wrote: > > IMHO with control flow this function above initilization is not > > required. > > u may remove this initilization if u agree, while pushing the patch. > > I don't recommend anyone changing anything even remotely functional while > pushing. I'm fine with doing comment and whitepace changes, and as a rule > nothing > else. Yes, sure will push the next version dropping the initialization. Regards, Uma Shankar > BR, > Jani. > > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v5] drm/i915/display: Enable DP Display Audio WA
On Thu, 16 Apr 2020, Anshuman Gupta wrote: > IMHO with control flow this function above initilization is not > required. > u may remove this initilization if u agree, while pushing the patch. I don't recommend anyone changing anything even remotely functional while pushing. I'm fine with doing comment and whitepace changes, and as a rule nothing else. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v5] drm/i915/display: Enable DP Display Audio WA
On 2020-04-16 at 13:17:21 +0530, Uma Shankar wrote:
> For certain DP VDSC bpp settings, hblank asserts before hblank_early,
> leading to a bad audio state. Driver need to program "hblank early
> enable" and "samples per line" parameters in AUDIO_CONFIG_BE
> register.
>
> This is Display Audio WA #1406928334 for 4k+VDSC usecase
> applicable on DP encoders. Implemented the same.
>
> v2: Fixed build failures on 32bit machine.
>
> v3: Dropped u64, added helpers for sample room calculation,
> other general comments as per Jani Nikula's feedback.
> Also fixed connector type check (spotted by Anshuman)
>
> v4: Addressed Jani Nikula and Kai's review comments.
>
> v5: Addressed Anshuman's review comment and used crtc_* variable
> to get timings.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 147 +
> drivers/gpu/drm/i915/i915_reg.h| 16 +++
> 2 files changed, 163 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 57b80971ae78..ca678da1152f 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -514,6 +514,149 @@ static void hsw_audio_codec_disable(struct
> intel_encoder *encoder,
> mutex_unlock(_priv->av_mutex);
> }
>
> +/* Add a factor to take care of rounding and truncations */
> +#define ROUNDING_FACTOR 1
> +
> +static unsigned int get_hblank_early_enable_config(struct intel_encoder
> *encoder,
> +const struct
> intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + unsigned int link_clks_available, link_clks_required;
> + unsigned int tu_data, tu_line, link_clks_active;
> + unsigned int hblank_rise, hblank_early_prog;
> + unsigned int h_active, h_total, hblank_delta, pixel_clk, v_total;
> + unsigned int fec_coeff, refresh_rate, cdclk, vdsc_bpp;
> +
> + h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> + h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
> + v_total = crtc_state->hw.adjusted_mode.crtc_vtotal;
> + hblank_rise = crtc_state->hw.adjusted_mode.crtc_hsync_start;
IMHO with control flow this function above initilization is not
required.
u may remove this initilization if u agree, while pushing the patch.
Reviewed-by: Anshuman Gupta
> + pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> + refresh_rate = crtc_state->hw.adjusted_mode.vrefresh;
> + vdsc_bpp = crtc_state->dsc.compressed_bpp;
> + cdclk = i915->cdclk.hw.cdclk;
> + /* fec= 0.972261, using rounding multiplier of 100 */
> + fec_coeff = 972261;
> +
> + drm_dbg_kms(>drm, "h_active = %u link_clk = %u :"
> + "lanes = %u vdsc_bpp = %u cdclk = %u\n",
> + h_active, crtc_state->port_clock, crtc_state->lane_count,
> + vdsc_bpp, cdclk);
> +
> + link_clks_available = h_total - h_active) *
> +((crtc_state->port_clock * ROUNDING_FACTOR) /
> + pixel_clk)) / ROUNDING_FACTOR) - 28);
> +
> + link_clks_required = DIV_ROUND_UP(192000, (refresh_rate *
> + v_total)) * ((48 /
> + crtc_state->lane_count) + 2);
> +
> + if (link_clks_available > link_clks_required)
> + hblank_delta = 32;
> + else
> + hblank_delta = DIV_ROUND_UP(5 * ROUNDING_FACTOR) /
> + crtc_state->port_clock) + ((5 *
> + ROUNDING_FACTOR) /
> + cdclk)) * pixel_clk),
> + ROUNDING_FACTOR);
> +
> + tu_data = (pixel_clk * vdsc_bpp * 8) / ((crtc_state->port_clock *
> +crtc_state->lane_count * fec_coeff) / 100);
> + tu_line = (((h_active * crtc_state->port_clock * fec_coeff) /
> +100) / (64 * pixel_clk));
> + link_clks_active = (tu_line - 1) * 64 + tu_data;
> +
> + hblank_rise = ((link_clks_active + 6 * DIV_ROUND_UP(link_clks_active,
> + 250) + 4) * ((pixel_clk * ROUNDING_FACTOR) /
> + crtc_state->port_clock)) / ROUNDING_FACTOR;
> +
> + hblank_early_prog = h_active - hblank_rise + hblank_delta;
> +
> + return hblank_early_prog;
> +}
> +
> +static unsigned int get_sample_room_req_config(const struct intel_crtc_state
> *crtc_state)
> +{
> + unsigned int h_active, h_total, pixel_clk;
> + unsigned int samples_room;
> +
> + h_active = crtc_state->hw.adjusted_mode.hdisplay;
> + h_total = crtc_state->hw.adjusted_mode.htotal;
> + pixel_clk = crtc_state->hw.adjusted_mode.clock;
> +
> + samples_room = h_total - h_active) * ((crtc_state->port_clock *
> +
Re: [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
On 16-04-2020 15:19, Maarten Lankhorst wrote:
Hey,
Seems we're lacking error handling still when get fails?
Hi Maarten,
Error handling is taken care by dsb-framework, if _prepare() is failed then
dsb->cmd_buf will be null and during dsb-write() mmio-write will be used to
program registers.
As we have mmio fallback so do not want to fail the commit. Added a
code-comment in intel_atomic_prepare_commit(). Maybe if needed I can elaborate
a bit more. Please let me know your view on this.
Regards,
Animesh
~Maarten
Op 13-04-2020 om 08:34 schreef Animesh Manna:
Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
function which also includes pinning and map in cpu domain.
No change is dsb write/commit functions.
Now dsb get/put function is refactored and currently used only for
reference counting. Below dsb api added to do respective job
mentioned below.
intel_dsb_prepare - Allocate, pin and map the buffer.
intel_dsb_cleanup - Unpin and release the gem object.
RFC: Initial patch for design review.
v2: included _init() part in _prepare(). [Daniel, Ville]
v3: dsb_cleanup called after cleanup_planes. [Daniel]
v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten]
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c| 19 +-
drivers/gpu/drm/i915/display/intel_display.c | 47 -
.../drm/i915/display/intel_display_types.h| 6 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 169 --
drivers/gpu/drm/i915/display/intel_dsb.h | 6 +-
5 files changed, 170 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 98ece9cd7cdd..fb2caee90734 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -717,7 +717,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
@@ -900,7 +900,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
enum pipe pipe = crtc->pipe;
/* FIXME LUT entries are 16 bit only, so we can prog 0x max */
@@ -916,7 +916,7 @@ icl_program_gamma_superfine_segment(const struct
intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
const struct drm_color_lut *lut = blob->data;
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
enum pipe pipe = crtc->pipe;
int i;
@@ -949,7 +949,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
const struct drm_color_lut *lut = blob->data;
const struct drm_color_lut *entry;
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
enum pipe pipe = crtc->pipe;
int i;
@@ -1003,7 +1003,16 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
{
const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_dsb *dsb = intel_dsb_get(crtc);
+ struct intel_dsb *dsb = intel_dsb_get(crtc->config);
+
+ /*
+* TODO: Currently dsb buffer filling is done in load_lut() which
+* can be done much earlier, like initial stage of atomic_commit().
+* As currently replacing the mmio-write with dsb-write so the same
+* load_lut() api is used for dsb buffer creation which may not
+* fit in initial stage. Need to create a separate interface and
+* a different path in color framework while dealing with dsb.
+*/
if (crtc_state->hw.degamma_lut)
glk_load_degamma_lut(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 70ec301fe6e3..42c4d6c7f334 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14844,8 +14844,28 @@ static int intel_atomic_check(struct drm_device *dev,
static int intel_atomic_prepare_commit(struct
Re: [Intel-gfx] [PATCH v2] drm/i915: HDCP: fix Ri prime check done during link check
On Sun, 29 Mar 2020, Ramalingam C wrote:
> On 2020-03-28 at 11:41:00 +0100, Oliver Barta wrote:
>> From: Oliver Barta
>>
>> The check was always succeeding even in case of a mismatch due to the
>> HDCP_STATUS_ENC bit being set. Make sure both bits are actually set.
>>
> Looks good to me:
>
> Reviewed-by: Ramalingam C
Pushed to dinq, thanks for the patch and review.
Fixed the checkpatch indentation warning while at it.
BR,
Jani.
>> Signed-off-by: Oliver Barta
>> Fixes: 2320175feb74 ("drm/i915: Implement HDCP for HDMI")
>> ---
>> [v2] rebased on top of latest changes
>>
>> drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> index 0076abc63851..51a69f330588 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> @@ -1561,7 +1561,8 @@ bool intel_hdmi_hdcp_check_link(struct
>> intel_digital_port *intel_dig_port)
>> intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
>>
>> /* Wait for Ri prime match */
>> -if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
>> port)) &
>> +if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
>> + port)) & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
>> (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
>> drm_err(>drm,
>> "Ri' mismatch detected, link check failed (%x)\n",
>> --
>> 2.20.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
Hey,
Seems we're lacking error handling still when get fails?
~Maarten
Op 13-04-2020 om 08:34 schreef Animesh Manna:
> Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
> function which also includes pinning and map in cpu domain.
>
> No change is dsb write/commit functions.
>
> Now dsb get/put function is refactored and currently used only for
> reference counting. Below dsb api added to do respective job
> mentioned below.
>
> intel_dsb_prepare - Allocate, pin and map the buffer.
> intel_dsb_cleanup - Unpin and release the gem object.
>
> RFC: Initial patch for design review.
> v2: included _init() part in _prepare(). [Daniel, Ville]
> v3: dsb_cleanup called after cleanup_planes. [Daniel]
> v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten]
>
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Cc: Daniel Vetter
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_color.c| 19 +-
> drivers/gpu/drm/i915/display/intel_display.c | 47 -
> .../drm/i915/display/intel_display_types.h| 6 +-
> drivers/gpu/drm/i915/display/intel_dsb.c | 169 --
> drivers/gpu/drm/i915/display/intel_dsb.h | 6 +-
> 5 files changed, 170 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 98ece9cd7cdd..fb2caee90734 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -717,7 +717,7 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> enum pipe pipe = crtc->pipe;
>
> /* Program the max register to clamp values > 1.0. */
> @@ -900,7 +900,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> const struct drm_color_lut *color)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> enum pipe pipe = crtc->pipe;
>
> /* FIXME LUT entries are 16 bit only, so we can prog 0x max */
> @@ -916,7 +916,7 @@ icl_program_gamma_superfine_segment(const struct
> intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> const struct drm_color_lut *lut = blob->data;
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> enum pipe pipe = crtc->pipe;
> int i;
>
> @@ -949,7 +949,7 @@ icl_program_gamma_multi_segment(const struct
> intel_crtc_state *crtc_state)
> const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> const struct drm_color_lut *lut = blob->data;
> const struct drm_color_lut *entry;
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> enum pipe pipe = crtc->pipe;
> int i;
>
> @@ -1003,7 +1003,16 @@ static void icl_load_luts(const struct
> intel_crtc_state *crtc_state)
> {
> const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_dsb *dsb = intel_dsb_get(crtc);
> + struct intel_dsb *dsb = intel_dsb_get(crtc->config);
> +
> + /*
> + * TODO: Currently dsb buffer filling is done in load_lut() which
> + * can be done much earlier, like initial stage of atomic_commit().
> + * As currently replacing the mmio-write with dsb-write so the same
> + * load_lut() api is used for dsb buffer creation which may not
> + * fit in initial stage. Need to create a separate interface and
> + * a different path in color framework while dealing with dsb.
> + */
>
> if (crtc_state->hw.degamma_lut)
> glk_load_degamma_lut(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 70ec301fe6e3..42c4d6c7f334 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14844,8 +14844,28 @@ static int intel_atomic_check(struct drm_device *dev,
>
> static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
> {
> - return drm_atomic_helper_prepare_planes(state->base.dev,
> - >base);
> + struct intel_crtc_state *crtc_state;
> + struct intel_crtc *crtc;
> + int i, ret;
> +
> + ret = drm_atomic_helper_prepare_planes(state->base.dev, >base);
> + if (ret < 0)
> +
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format support for skl+ (V15)
On Wed, 08 Apr 2020, Jani Nikula wrote:
> On Tue, 07 Apr 2020, Bob Paauwe wrote:
>> From: Stanislav Lisovskiy
>>
>> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
>> specification.
>>
>> v2: Edited commit message, removed redundant whitespaces.
>>
>> v3: Fixed fallthrough logic for the format switch cases.
>>
>> v4: Yet again fixed fallthrough logic, to reuse code from other case
>> labels.
>>
>> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
>>
>> v6: Removed unneeded initializer for new XYUV format.
>>
>> v7: Added scaling support for DRM_FORMAT_XYUV
>>
>> v8: Edited commit message to be more clear about skl+, renamed
>> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
>> doesn't support per-pixel alpha. Fixed minor code issues.
>>
>> v9: Moved DRM format check to proper place in intel_framebuffer_init.
>>
>> v10: Added missing XYUV format to sprite planes for skl+.
>>
>> v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
>>
>> v12: Fixed rebase conflicts
>>
>> V13: Rebased.
>> Added format to ICL format lists.
>>
>> V14: Added format to TGL format lists.
>> Rebased.
>>
>> V15: Added format to glk_planar_formats[] and icl_sdr_y_plane_formats[]
>> (Ville)
>> Placed XYUV before XXVYU2101010 to be more consistent (Ville)
>
> Okay, so we like to add the changelog of the patch itself to the commit
> message, but this is ridiculous wrt the patch and the commit
> message. Whoever ends up applying it, please just nuke the changelog. I
> don't want that in the logs.
This turned out to be me. Pushed with the commit message cleaned up.
BR,
Jani.
>
> BR,
> Jani.
>
>
>>
>> v12:
>> Reviewed-by: Ville Syrjälä
>> Reviewed-by: Matt Roper
>>
>> Signed-off-by: Stanislav Lisovskiy
>> Signed-off-by: Bob Paauwe
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 5 +
>> drivers/gpu/drm/i915/display/intel_sprite.c | 8
>> drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> 3 files changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 70ec301fe6e3..3654262570b2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -3342,6 +3342,8 @@ int skl_format_to_fourcc(int format, bool rgb_order,
>> bool alpha)
>> return DRM_FORMAT_RGB565;
>> case PLANE_CTL_FORMAT_NV12:
>> return DRM_FORMAT_NV12;
>> +case PLANE_CTL_FORMAT_XYUV:
>> +return DRM_FORMAT_XYUV;
>> case PLANE_CTL_FORMAT_P010:
>> return DRM_FORMAT_P010;
>> case PLANE_CTL_FORMAT_P012:
>> @@ -4586,6 +4588,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
>> case DRM_FORMAT_XRGB16161616F:
>> case DRM_FORMAT_ARGB16161616F:
>> return PLANE_CTL_FORMAT_XRGB_16161616F;
>> +case DRM_FORMAT_XYUV:
>> +return PLANE_CTL_FORMAT_XYUV;
>> case DRM_FORMAT_YUYV:
>> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
>> case DRM_FORMAT_YVYU:
>> @@ -6175,6 +6179,7 @@ static int skl_update_scaler_plane(struct
>> intel_crtc_state *crtc_state,
>> case DRM_FORMAT_UYVY:
>> case DRM_FORMAT_VYUY:
>> case DRM_FORMAT_NV12:
>> +case DRM_FORMAT_XYUV:
>> case DRM_FORMAT_P010:
>> case DRM_FORMAT_P012:
>> case DRM_FORMAT_P016:
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>> b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index deda351719db..1a4377c988f5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -2503,6 +2503,7 @@ static const u32 skl_plane_formats[] = {
>> DRM_FORMAT_YVYU,
>> DRM_FORMAT_UYVY,
>> DRM_FORMAT_VYUY,
>> +DRM_FORMAT_XYUV,
>> };
>>
>> static const u32 skl_planar_formats[] = {
>> @@ -2521,6 +2522,7 @@ static const u32 skl_planar_formats[] = {
>> DRM_FORMAT_UYVY,
>> DRM_FORMAT_VYUY,
>> DRM_FORMAT_NV12,
>> +DRM_FORMAT_XYUV,
>> };
>>
>> static const u32 glk_planar_formats[] = {
>> @@ -2539,6 +2541,7 @@ static const u32 glk_planar_formats[] = {
>> DRM_FORMAT_UYVY,
>> DRM_FORMAT_VYUY,
>> DRM_FORMAT_NV12,
>> +DRM_FORMAT_XYUV,
>> DRM_FORMAT_P010,
>> DRM_FORMAT_P012,
>> DRM_FORMAT_P016,
>> @@ -2562,6 +2565,7 @@ static const u32 icl_sdr_y_plane_formats[] = {
>> DRM_FORMAT_Y210,
>> DRM_FORMAT_Y212,
>> DRM_FORMAT_Y216,
>> +DRM_FORMAT_XYUV,
>> DRM_FORMAT_XVYU2101010,
>> DRM_FORMAT_XVYU12_16161616,
>> DRM_FORMAT_XVYU16161616,
>> @@ -2589,6 +2593,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
>> DRM_FORMAT_Y210,
>> DRM_FORMAT_Y212,
>> DRM_FORMAT_Y216,
>> +DRM_FORMAT_XYUV,
>> DRM_FORMAT_XVYU2101010,
>> DRM_FORMAT_XVYU12_16161616,
>> DRM_FORMAT_XVYU16161616,
>> @@ -2620,6
