[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mst: filter out the display mode exceed sink's capability (rev3)
== Series Details ==
Series: drm/i915/mst: filter out the display mode exceed sink's capability
(rev3)
URL : https://patchwork.freedesktop.org/series/76095/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8498_full -> Patchwork_17706_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17706_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_preempt_timeout@timeout@vecs0}:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-glk1/igt@sysfs_preempt_timeout@time...@vecs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-glk9/igt@sysfs_preempt_timeout@time...@vecs0.html
Known issues
Here are the changes found in Patchwork_17706_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#300])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-skl10/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-kbl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_flip_tiling@flip-changes-tiling:
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#95])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl8/igt@kms_flip_til...@flip-changes-tiling.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-apl2/igt@kms_flip_til...@flip-changes-tiling.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#1188])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl5/igt@kms_...@bpc-switch-suspend.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-skl10/igt@kms_...@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265])
+1 similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-iclb3/igt@kms_psr@psr2_sprite_render.html
Possible fixes
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [DMESG-WARN][17] ([i915#1436] / [i915#716]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl1/igt@gen9_exec_pa...@allowed-all.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-apl7/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_selftest@live@execlists:
- shard-skl: [INCOMPLETE][19] ([i915#1795] / [i915#1874]) ->
[PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl2/igt@i915_selftest@l...@execlists.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-skl8/igt@i915_selftest@l...@execlists.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][21] ([i915#180]) -> [PASS][22] +3
similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/shard-kbl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1}:
- shard-glk: [FAIL][23]
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC
== Series Details == Series: drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC URL : https://patchwork.freedesktop.org/series/77382/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498_full -> Patchwork_17705_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17705_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html * igt@kms_cursor_legacy@flip-vs-cursor-varying-size: - shard-skl: [PASS][3] -> [FAIL][4] ([IGT#5] / [i915#697]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl2/igt@kms_cursor_leg...@flip-vs-cursor-varying-size.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-skl4/igt@kms_cursor_leg...@flip-vs-cursor-varying-size.html * igt@kms_cursor_legacy@pipe-c-torture-move: - shard-iclb: [PASS][5] -> [DMESG-WARN][6] ([i915#128]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb6/igt@kms_cursor_leg...@pipe-c-torture-move.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-iclb2/igt@kms_cursor_leg...@pipe-c-torture-move.html * igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-untiled: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#177] / [i915#52] / [i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl5/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-skl8/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-untiled.html * igt@kms_flip_tiling@flip-changes-tiling: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl8/igt@kms_flip_til...@flip-changes-tiling.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-apl7/igt@kms_flip_til...@flip-changes-tiling.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#1188]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl5/igt@kms_...@bpc-switch-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-skl7/igt@kms_...@bpc-switch-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-iclb4/igt@kms_psr@psr2_sprite_render.html Possible fixes * igt@gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][19] ([i915#1436] / [i915#716]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl1/igt@gen9_exec_pa...@allowed-all.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-apl4/igt@gen9_exec_pa...@allowed-all.html * igt@i915_selftest@live@execlists: - shard-skl: [INCOMPLETE][21] ([i915#1795] / [i915#1874]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl2/igt@i915_selftest@l...@execlists.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/shard-skl4/igt@i915_selftest@l...@execlists.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][23] ([i915#180]) -> [PASS][24] +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html [24]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mst: filter out the display mode exceed sink's capability (rev3)
== Series Details == Series: drm/i915/mst: filter out the display mode exceed sink's capability (rev3) URL : https://patchwork.freedesktop.org/series/76095/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498 -> Patchwork_17706 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/index.html Known issues Here are the changes found in Patchwork_17706 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([i915#262]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (52 -> 44) -- Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8498 -> Patchwork_17706 CI-20190529: 20190529 CI_DRM_8498: 1493c649ae92207a758afa50a639275bd6c80e2e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17706: 8c7c02df8f7602265c2cc0fa5dc96d7c84b3cf5e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8c7c02df8f76 drm/i915/mst: filter out the display mode exceed sink's capability == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17706/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/mst: filter out the display mode exceed sink's capability
So far, max dot clock rate for MST mode rely on physcial
bandwidth limitation. It would caused compatibility issue
if source display resolution exceed MST hub output ability.
For example, source DUT had DP 1.2 output capability.
And MST docking just support HDMI 1.4 spec. When a HDMI 2.0
monitor connected. Source would retrieve EDID from external
and get max resolution 4k@60fps. DP 1.2 can support 4K@60fps
because it did not surpass DP physical bandwidth limitation.
Do modeset to 4k@60fps, source output display data but MST
docking can't output HDMI properly due to this resolution
already over HDMI 1.4 spec.
Refer to commit ("drm/dp_mst: Use full_pbn
instead of available_pbn for bandwidth checks").
Source driver should refer to full_pbn to evaluate sink
output capability. And filter out the resolution surpass
sink output limitation.
v2: Using mgr->base.lock to protect full_pbn.
v3: Add ctx lock.
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Cooper Chiou
Cc: Lyude Paul
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 30 -
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 74559379384a..6b6f7eef5b68 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -611,6 +611,32 @@ static int intel_dp_mst_get_modes(struct drm_connector
*connector)
return intel_dp_mst_get_ddc_modes(connector);
}
+static bool
+intel_dp_mst_mode_clock_exceed_pbn_bandwidth(struct drm_connector *connector,
int clock, int bpp)
+{
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct intel_dp *intel_dp = intel_connector->mst_port;
+ struct drm_dp_mst_topology_mgr *mgr = _dp->mst_mgr;
+ struct drm_dp_mst_port *port = (to_intel_connector(connector))->port;
+ struct drm_modeset_acquire_ctx ctx;
+ bool ret = false;
+
+ if (!mgr)
+ return ret;
+
+ drm_modeset_acquire_init(, 0);
+
+ drm_modeset_lock(>base.lock, );
+ if (port->full_pbn)
+ ret = (drm_dp_calc_pbn_mode(clock, bpp, false) >
port->full_pbn);
+ drm_modeset_unlock(>base.lock);
+
+ drm_modeset_drop_locks();
+ drm_modeset_acquire_fini();
+
+ return ret;
+}
+
static enum drm_mode_status
intel_dp_mst_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -633,7 +659,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(mode->clock, 18);
- /* TODO - validate mode against available PBN for link */
+ if (intel_dp_mst_mode_clock_exceed_pbn_bandwidth(connector,
mode->clock, 24))
+ return MODE_CLOCK_HIGH;
+
if (mode->clock < 1)
return MODE_CLOCK_LOW;
--
2.17.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages()
== Series Details == Series: mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages() URL : https://patchwork.freedesktop.org/series/77381/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8498_full -> Patchwork_17704_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17704_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17704_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17704_full: ### IGT changes ### Possible regressions * igt@gem_userptr_blits@dmabuf-unsync: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] +7 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-tglb7/igt@gem_userptr_bl...@dmabuf-unsync.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-tglb1/igt@gem_userptr_bl...@dmabuf-unsync.html - shard-glk: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-glk8/igt@gem_userptr_bl...@dmabuf-unsync.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-glk8/igt@gem_userptr_bl...@dmabuf-unsync.html - shard-iclb: [PASS][5] -> [DMESG-WARN][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb6/igt@gem_userptr_bl...@dmabuf-unsync.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-iclb8/igt@gem_userptr_bl...@dmabuf-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup@gtt: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-...@gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-iclb3/igt@gem_userptr_blits@map-fixed-invalidate-busy-...@gtt.html * igt@gem_userptr_blits@map-fixed-invalidate-gup@gtt: - shard-kbl: [PASS][9] -> [INCOMPLETE][10] +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl1/igt@gem_userptr_blits@map-fixed-invalidate-...@gtt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-kbl4/igt@gem_userptr_blits@map-fixed-invalidate-...@gtt.html - shard-apl: [PASS][11] -> [INCOMPLETE][12] +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl1/igt@gem_userptr_blits@map-fixed-invalidate-...@gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-apl7/igt@gem_userptr_blits@map-fixed-invalidate-...@gtt.html * igt@gem_userptr_blits@stress-purge: - shard-skl: [PASS][13] -> [INCOMPLETE][14] +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl10/igt@gem_userptr_bl...@stress-purge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-skl10/igt@gem_userptr_bl...@stress-purge.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl6/igt@gem_userptr_bl...@sync-unmap-after-close.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-kbl2/igt@gem_userptr_bl...@sync-unmap-after-close.html - shard-apl: [PASS][17] -> [DMESG-WARN][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl4/igt@gem_userptr_bl...@sync-unmap-after-close.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-apl2/igt@gem_userptr_bl...@sync-unmap-after-close.html * igt@gem_userptr_blits@unsync-unmap-after-close: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-tglb6/igt@gem_userptr_bl...@unsync-unmap-after-close.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-tglb1/igt@gem_userptr_bl...@unsync-unmap-after-close.html * igt@gem_userptr_blits@userfault: - shard-snb: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-snb4/igt@gem_userptr_bl...@userfault.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-snb1/igt@gem_userptr_bl...@userfault.html - shard-skl: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl2/igt@gem_userptr_bl...@userfault.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/shard-skl6/igt@gem_userptr_bl...@userfault.html * igt@runner@aborted: -
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: move trace_i915_reg_rw() to a separate file
== Series Details == Series: series starting with [1/2] drm/i915: move trace_i915_reg_rw() to a separate file URL : https://patchwork.freedesktop.org/series/77378/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498_full -> Patchwork_17703_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17703_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_cursor_crc@pipe-b-cursor-128x128-random: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#54]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl8/igt@kms_cursor_...@pipe-b-cursor-128x128-random.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-128x128-random.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-apl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@pipe-c-torture-bo: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#128]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-tglb1/igt@kms_cursor_leg...@pipe-c-torture-bo.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-tglb7/igt@kms_cursor_leg...@pipe-c-torture-bo.html * igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-untiled: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#177] / [i915#52] / [i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl5/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-skl1/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-untiled.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#69]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl8/igt@kms_fbcon_...@psr-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-skl1/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip_tiling@flip-changes-tiling: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl8/igt@kms_flip_til...@flip-changes-tiling.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-apl1/igt@kms_flip_til...@flip-changes-tiling.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl3/igt@kms_frontbuffer_track...@fbc-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-apl6/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl7/igt@kms_...@bpc-switch-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-skl5/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-iclb3/igt@kms_psr@psr2_sprite_render.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl3/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-kbl2/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html Possible fixes * igt@gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][23] ([i915#1436] / [i915#716]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl1/igt@gen9_exec_pa...@allowed-all.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/shard-apl6/igt@gen9_exec_pa...@allowed-all.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC
== Series Details == Series: drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC URL : https://patchwork.freedesktop.org/series/77382/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498 -> Patchwork_17705 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/index.html Known issues Here are the changes found in Patchwork_17705 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] ([i915#1250] / [i915#1436]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-bsw-nick/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/fi-bsw-nick/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@execlists: - fi-cfl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#656]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-cfl-guc/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/fi-cfl-guc/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@requests: - fi-bwr-2160:[PASS][5] -> [INCOMPLETE][6] ([i915#1457] / [i915#489]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-bwr-2160/igt@i915_selftest@l...@requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/fi-bwr-2160/igt@i915_selftest@l...@requests.html [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1457]: https://gitlab.freedesktop.org/drm/intel/issues/1457 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (52 -> 45) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8498 -> Patchwork_17705 CI-20190529: 20190529 CI_DRM_8498: 1493c649ae92207a758afa50a639275bd6c80e2e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17705: 42cda1a46a6627b6ddc1ae0da45bed100c1f59ea @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 42cda1a46a66 drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17705/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Don't set queue-priority hint when supressing the reschedule
== Series Details ==
Series: series starting with [1/4] drm/i915: Don't set queue-priority hint when
supressing the reschedule
URL : https://patchwork.freedesktop.org/series/77377/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8498_full -> Patchwork_17702_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17702_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl4/igt@kms_cursor_...@pipe-b-cursor-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-kbl2/igt@kms_cursor_...@pipe-b-cursor-suspend.html
* igt@kms_flip_tiling@flip-changes-tiling:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#95])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl8/igt@kms_flip_til...@flip-changes-tiling.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-apl2/igt@kms_flip_til...@flip-changes-tiling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#118] / [i915#95])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-glk6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-move.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-glk1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180] / [i915#93]
/ [i915#95])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl7/igt@kms_frontbuffer_track...@fbc-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-kbl3/igt@kms_frontbuffer_track...@fbc-suspend.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#1188])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl5/igt@kms_...@bpc-switch-suspend.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-skl4/igt@kms_...@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265])
+2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-iclb3/igt@kms_psr@psr2_sprite_render.html
Possible fixes
* igt@i915_selftest@live@execlists:
- shard-skl: [INCOMPLETE][17] ([i915#1795] / [i915#1874]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl2/igt@i915_selftest@l...@execlists.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-skl8/igt@i915_selftest@l...@execlists.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][19] ([i915#180]) -> [PASS][20] +4
similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-kbl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1}:
- shard-glk: [FAIL][21] ([i915#79]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1}:
- shard-skl: [FAIL][23] ([i915#79]) -> [PASS][24]
[23]:
[Intel-gfx] ✓ Fi.CI.BAT: success for mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages()
== Series Details == Series: mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages() URL : https://patchwork.freedesktop.org/series/77381/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498 -> Patchwork_17704 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/index.html Known issues Here are the changes found in Patchwork_17704 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-cfl-8700k: [PASS][1] -> [INCOMPLETE][2] ([i915#656]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [PASS][3] -> [FAIL][4] ([i915#262]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (52 -> 45) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8498 -> Patchwork_17704 CI-20190529: 20190529 CI_DRM_8498: 1493c649ae92207a758afa50a639275bd6c80e2e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17704: ace503a8f42c4de5395983002282f6d0302543bc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ace503a8f42c drm/i915: convert get_user_pages() --> pin_user_pages() d8a6c141995a mm/gup: introduce pin_user_pages_fast_only() 4bab9b886ef9 mm/gup: refactor and de-duplicate gup_fast() code 5dd288837ad8 mm/gup: move __get_user_pages_fast() down a few lines in gup.c == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17704/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC
This is a permanent w/a for JSL/EHL.This is to be applied to the
PCH types on JSL/EHL ie JSP/MCC
Bspec: 52888
Signed-off-by: Swathi Dhanavanthri
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4dc601dffc08..1974369cebb8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2902,8 +2902,8 @@ static void gen11_display_irq_reset(struct
drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:icl */
- if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) {
+ /* Wa_14010685332:icl,jsl,ehl */
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP || PCH_JSP || PCH_MCC) {
intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Resolve device hotunplug issues
== Series Details ==
Series: drm/i915: Resolve device hotunplug issues
URL : https://patchwork.freedesktop.org/series/77372/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8498_full -> Patchwork_17701_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17701_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@all-pipes-torture-bo:
- shard-snb: [PASS][3] -> [DMESG-WARN][4] ([i915#128])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-snb5/igt@kms_cursor_leg...@all-pipes-torture-bo.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-snb4/igt@kms_cursor_leg...@all-pipes-torture-bo.html
* igt@kms_flip_tiling@flip-changes-tiling:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#95])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl8/igt@kms_flip_til...@flip-changes-tiling.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-apl8/igt@kms_flip_til...@flip-changes-tiling.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#1188]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl7/igt@kms_...@bpc-switch-dpms.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-skl7/igt@kms_...@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#69])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-skl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265])
+1 similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-iclb4/igt@kms_psr@psr2_sprite_render.html
Possible fixes
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [DMESG-WARN][17] ([i915#1436] / [i915#716]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl1/igt@gen9_exec_pa...@allowed-all.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-apl3/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_selftest@live@execlists:
- shard-skl: [INCOMPLETE][19] ([i915#1795] / [i915#1874]) ->
[PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl2/igt@i915_selftest@l...@execlists.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-skl5/igt@i915_selftest@l...@execlists.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][21] ([i915#180]) -> [PASS][22] +4
similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][23] ([fdo#109349]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb5/igt@kms_dp_...@basic-dsc-enable-edp.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1}:
-
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages()
== Series Details == Series: mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages() URL : https://patchwork.freedesktop.org/series/77381/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47:expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47:got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages()
== Series Details == Series: mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages() URL : https://patchwork.freedesktop.org/series/77381/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5dd288837ad8 mm/gup: move __get_user_pages_fast() down a few lines in gup.c -:111: CHECK:SPACING: No space is necessary after a cast #111: FILE: mm/gup.c:2764: + len = (unsigned long) nr_pages << PAGE_SHIFT; total: 0 errors, 0 warnings, 1 checks, 124 lines checked 4bab9b886ef9 mm/gup: refactor and de-duplicate gup_fast() code d8a6c141995a mm/gup: introduce pin_user_pages_fast_only() ace503a8f42c drm/i915: convert get_user_pages() --> pin_user_pages() ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: move trace_i915_reg_rw() to a separate file
== Series Details == Series: series starting with [1/2] drm/i915: move trace_i915_reg_rw() to a separate file URL : https://patchwork.freedesktop.org/series/77378/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498 -> Patchwork_17703 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/index.html Known issues Here are the changes found in Patchwork_17703 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-skl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#151]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-skl-guc/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/fi-skl-guc/igt@i915_pm_...@module-reload.html [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 Participating hosts (52 -> 44) -- Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8498 -> Patchwork_17703 CI-20190529: 20190529 CI_DRM_8498: 1493c649ae92207a758afa50a639275bd6c80e2e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17703: 7f37c24c1d4bef1f645fce042cfff357a2130fe3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7f37c24c1d4b drm/i915: trace intel_uncore_*_fw() caee6db994c4 drm/i915: move trace_i915_reg_rw() to a separate file == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17703/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: move trace_i915_reg_rw() to a separate file
== Series Details ==
Series: series starting with [1/2] drm/i915: move trace_i915_reg_rw() to a
separate file
URL : https://patchwork.freedesktop.org/series/77378/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
caee6db994c4 drm/i915: move trace_i915_reg_rw() to a separate file
-:66: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#66:
new file mode 100644
-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/i915_trace_reg_rw.h:15:
+TRACE_EVENT_CONDITION(i915_reg_rw,
+ TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace),
-:91: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#91: FILE: drivers/gpu/drm/i915/i915_trace_reg_rw.h:21:
+ TP_STRUCT__entry(
-:98: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#98: FILE: drivers/gpu/drm/i915/i915_trace_reg_rw.h:28:
+ TP_fast_assign(
-:106: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#106: FILE: drivers/gpu/drm/i915/i915_trace_reg_rw.h:36:
+ TP_printk("%s reg=0x%x, len=%d, val=(0x%x, 0x%x)",
+ __entry->write ? "write" : "read",
total: 0 errors, 1 warnings, 4 checks, 84 lines checked
7f37c24c1d4b drm/i915: trace intel_uncore_*_fw()
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[Intel-gfx] [PATCH 2/4] mm/gup: refactor and de-duplicate gup_fast() code
There were two nearly identical sets of code for gup_fast()
style of walking the page tables with interrupts disabled.
This has lead to the usual maintenance problems that arise from
having duplicated code.
There is already a core internal routine in gup.c for gup_fast(),
so just enhance it very slightly: allow skipping the fall-back
to "slow" (regular) get_user_pages(), via the new FOLL_FAST_ONLY
flag. Then, just call internal_get_user_pages_fast() from
__get_user_pages_fast(), and adjust the API to match pre-existing
API behavior.
There is a change in behavior from this refactoring: the nested
form of interrupt disabling is used in all gup_fast() variants
now. That's because there is only one place that interrupt disabling
for page walking is done, and so the safer form is required. This
should, if anything, eliminate possible (rare) bugs, because the
non-nested form of enabling interrupts was fragile at best.
Signed-off-by: John Hubbard
---
include/linux/mm.h | 1 +
mm/gup.c | 60 ++
2 files changed, 29 insertions(+), 32 deletions(-)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index a5594ac9ebe3..84b601cab699 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -2782,6 +2782,7 @@ struct page *follow_page(struct vm_area_struct *vma,
unsigned long address,
#define FOLL_LONGTERM 0x1 /* mapping lifetime is indefinite: see below */
#define FOLL_SPLIT_PMD 0x2 /* split huge pmd before returning */
#define FOLL_PIN 0x4 /* pages must be released via unpin_user_page */
+#define FOLL_FAST_ONLY 0x8 /* gup_fast: prevent fall-back to slow gup */
/*
* FOLL_PIN and FOLL_LONGTERM may be used in various combinations with each
diff --git a/mm/gup.c b/mm/gup.c
index 4502846d57f9..bb3e2c4288c3 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -2694,6 +2694,7 @@ static int internal_get_user_pages_fast(unsigned long
start, int nr_pages,
struct page **pages)
{
unsigned long addr, len, end;
+ unsigned long flags;
int nr_pinned = 0, ret = 0;
if (WARN_ON_ONCE(gup_flags & ~(FOLL_WRITE | FOLL_LONGTERM |
@@ -2710,15 +2711,26 @@ static int internal_get_user_pages_fast(unsigned long
start, int nr_pages,
if (unlikely(!access_ok((void __user *)start, len)))
return -EFAULT;
+ /*
+* Disable interrupts. The nested form is used, in order to allow full,
+* general purpose use of this routine.
+*
+* With interrupts disabled, we block page table pages from being
+* freed from under us. See struct mmu_table_batch comments in
+* include/asm-generic/tlb.h for more details.
+*
+* We do not adopt an rcu_read_lock(.) here as we also want to
+* block IPIs that come from THPs splitting.
+*/
if (IS_ENABLED(CONFIG_HAVE_FAST_GUP) &&
gup_fast_permitted(start, end)) {
- local_irq_disable();
+ local_irq_save(flags);
gup_pgd_range(addr, end, gup_flags, pages, _pinned);
- local_irq_enable();
+ local_irq_restore(flags);
ret = nr_pinned;
}
- if (nr_pinned < nr_pages) {
+ if (nr_pinned < nr_pages && !(gup_flags & FOLL_FAST_ONLY)) {
/* Try to get the remaining pages with get_user_pages */
start += nr_pinned << PAGE_SHIFT;
pages += nr_pinned;
@@ -2750,45 +2762,29 @@ static int internal_get_user_pages_fast(unsigned long
start, int nr_pages,
int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
struct page **pages)
{
- unsigned long len, end;
- unsigned long flags;
- int nr_pinned = 0;
+ int nr_pinned;
/*
* Internally (within mm/gup.c), gup fast variants must set FOLL_GET,
* because gup fast is always a "pin with a +1 page refcount" request.
+*
+* FOLL_FAST_ONLY is required in order to match the API description of
+* this routine: no fall back to regular ("slow") GUP.
*/
- unsigned int gup_flags = FOLL_GET;
+ unsigned int gup_flags = FOLL_GET | FOLL_FAST_ONLY;
if (write)
gup_flags |= FOLL_WRITE;
- start = untagged_addr(start) & PAGE_MASK;
- len = (unsigned long) nr_pages << PAGE_SHIFT;
- end = start + len;
-
- if (end <= start)
- return 0;
- if (unlikely(!access_ok((void __user *)start, len)))
- return 0;
-
+ nr_pinned = internal_get_user_pages_fast(start, nr_pages, gup_flags,
+pages);
/*
-* Disable interrupts. We use the nested form as we can already have
-* interrupts disabled by get_futex_key.
-*
-* With interrupts disabled, we block page table pages from being
-* freed from under
[Intel-gfx] [PATCH 3/4] mm/gup: introduce pin_user_pages_fast_only()
This is the FOLL_PIN equivalent of __get_user_pages_fast(),
except with a more descriptive name, and gup_flags instead of
a boolean "write" in the argument list.
Signed-off-by: John Hubbard
---
include/linux/mm.h | 2 ++
mm/gup.c | 36
2 files changed, 38 insertions(+)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 84b601cab699..98be7289d7e9 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1820,6 +1820,8 @@ extern int mprotect_fixup(struct vm_area_struct *vma,
*/
int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
struct page **pages);
+int pin_user_pages_fast_only(unsigned long start, int nr_pages,
+unsigned int gup_flags, struct page **pages);
/*
* per-process(per-mm_struct) statistics.
*/
diff --git a/mm/gup.c b/mm/gup.c
index bb3e2c4288c3..4413f0f94b68 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -2858,6 +2858,42 @@ int pin_user_pages_fast(unsigned long start, int
nr_pages,
}
EXPORT_SYMBOL_GPL(pin_user_pages_fast);
+/*
+ * This is the FOLL_PIN equivalent of __get_user_pages_fast(). Behavior is the
+ * same, except that this one sets FOLL_PIN instead of FOLL_GET.
+ *
+ * The API rules are the same, too: no negative values may be returned.
+ */
+int pin_user_pages_fast_only(unsigned long start, int nr_pages,
+unsigned int gup_flags, struct page **pages)
+{
+ int nr_pinned;
+
+ /*
+* FOLL_GET and FOLL_PIN are mutually exclusive. Note that the API
+* rules require returning 0, rather than -errno:
+*/
+ if (WARN_ON_ONCE(gup_flags & FOLL_GET))
+ return 0;
+ /*
+* FOLL_FAST_ONLY is required in order to match the API description of
+* this routine: no fall back to regular ("slow") GUP.
+*/
+ gup_flags |= (FOLL_PIN | FOLL_FAST_ONLY);
+ nr_pinned = internal_get_user_pages_fast(start, nr_pages, gup_flags,
+pages);
+ /*
+* This routine is not allowed to return negative values. However,
+* internal_get_user_pages_fast() *can* return -errno. Therefore,
+* correct for that here:
+*/
+ if (nr_pinned < 0)
+ nr_pinned = 0;
+
+ return nr_pinned;
+}
+EXPORT_SYMBOL_GPL(pin_user_pages_fast_only);
+
/**
* pin_user_pages_remote() - pin pages of a remote process (task != current)
*
--
2.26.2
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[Intel-gfx] [PATCH 4/4] drm/i915: convert get_user_pages() --> pin_user_pages()
This code was using get_user_pages*(), in a "Case 2" scenario
(DMA/RDMA), using the categorization from [1]. That means that it's
time to convert the get_user_pages*() + put_page() calls to
pin_user_pages*() + unpin_user_pages() calls.
There is some helpful background in [2]: basically, this is a small
part of fixing a long-standing disconnect between pinning pages, and
file systems' use of those pages.
[1] Documentation/core-api/pin_user_pages.rst
[2] "Explicit pinning of user-space pages":
https://lwn.net/Articles/807108/
Signed-off-by: John Hubbard
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 22 -
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 7ffd7afeb7a5..b55ac7563189 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -471,7 +471,7 @@ __i915_gem_userptr_get_pages_worker(struct work_struct
*_work)
down_read(>mmap_sem);
locked = 1;
}
- ret = get_user_pages_remote
+ ret = pin_user_pages_remote
(work->task, mm,
obj->userptr.ptr + pinned * PAGE_SIZE,
npages - pinned,
@@ -507,7 +507,7 @@ __i915_gem_userptr_get_pages_worker(struct work_struct
*_work)
}
mutex_unlock(>mm.lock);
- release_pages(pvec, pinned);
+ unpin_user_pages(pvec, pinned);
kvfree(pvec);
i915_gem_object_put(obj);
@@ -564,6 +564,7 @@ static int i915_gem_userptr_get_pages(struct
drm_i915_gem_object *obj)
struct sg_table *pages;
bool active;
int pinned;
+ unsigned int gup_flags = 0;
/* If userspace should engineer that these pages are replaced in
* the vma between us binding this page into the GTT and completion
@@ -598,11 +599,14 @@ static int i915_gem_userptr_get_pages(struct
drm_i915_gem_object *obj)
GFP_KERNEL |
__GFP_NORETRY |
__GFP_NOWARN);
- if (pvec) /* defer to worker if malloc fails */
- pinned = __get_user_pages_fast(obj->userptr.ptr,
- num_pages,
-
!i915_gem_object_is_readonly(obj),
- pvec);
+ /* defer to worker if malloc fails */
+ if (pvec) {
+ if (!i915_gem_object_is_readonly(obj))
+ gup_flags |= FOLL_WRITE;
+ pinned = pin_user_pages_fast_only(obj->userptr.ptr,
+ num_pages, gup_flags,
+ pvec);
+ }
}
active = false;
@@ -620,7 +624,7 @@ static int i915_gem_userptr_get_pages(struct
drm_i915_gem_object *obj)
__i915_gem_userptr_set_active(obj, true);
if (IS_ERR(pages))
- release_pages(pvec, pinned);
+ unpin_user_pages(pvec, pinned);
kvfree(pvec);
return PTR_ERR_OR_ZERO(pages);
@@ -675,7 +679,7 @@ i915_gem_userptr_put_pages(struct drm_i915_gem_object *obj,
}
mark_page_accessed(page);
- put_page(page);
+ unpin_user_page(page);
}
obj->mm.dirty = false;
--
2.26.2
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[Intel-gfx] [PATCH 1/4] mm/gup: move __get_user_pages_fast() down a few lines in gup.c
This is in order to avoid a forward declaration of
internal_get_user_pages_fast(), in the next patch.
This is code movement only--all generated code should
be identical.
Signed-off-by: John Hubbard
---
mm/gup.c | 112 +++
1 file changed, 56 insertions(+), 56 deletions(-)
diff --git a/mm/gup.c b/mm/gup.c
index 50cd9323efff..4502846d57f9 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -2666,62 +2666,6 @@ static bool gup_fast_permitted(unsigned long start,
unsigned long end)
}
#endif
-/*
- * Like get_user_pages_fast() except it's IRQ-safe in that it won't fall back
to
- * the regular GUP.
- * Note a difference with get_user_pages_fast: this always returns the
- * number of pages pinned, 0 if no pages were pinned.
- *
- * If the architecture does not support this function, simply return with no
- * pages pinned.
- */
-int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
- struct page **pages)
-{
- unsigned long len, end;
- unsigned long flags;
- int nr_pinned = 0;
- /*
-* Internally (within mm/gup.c), gup fast variants must set FOLL_GET,
-* because gup fast is always a "pin with a +1 page refcount" request.
-*/
- unsigned int gup_flags = FOLL_GET;
-
- if (write)
- gup_flags |= FOLL_WRITE;
-
- start = untagged_addr(start) & PAGE_MASK;
- len = (unsigned long) nr_pages << PAGE_SHIFT;
- end = start + len;
-
- if (end <= start)
- return 0;
- if (unlikely(!access_ok((void __user *)start, len)))
- return 0;
-
- /*
-* Disable interrupts. We use the nested form as we can already have
-* interrupts disabled by get_futex_key.
-*
-* With interrupts disabled, we block page table pages from being
-* freed from under us. See struct mmu_table_batch comments in
-* include/asm-generic/tlb.h for more details.
-*
-* We do not adopt an rcu_read_lock(.) here as we also want to
-* block IPIs that come from THPs splitting.
-*/
-
- if (IS_ENABLED(CONFIG_HAVE_FAST_GUP) &&
- gup_fast_permitted(start, end)) {
- local_irq_save(flags);
- gup_pgd_range(start, end, gup_flags, pages, _pinned);
- local_irq_restore(flags);
- }
-
- return nr_pinned;
-}
-EXPORT_SYMBOL_GPL(__get_user_pages_fast);
-
static int __gup_longterm_unlocked(unsigned long start, int nr_pages,
unsigned int gup_flags, struct page **pages)
{
@@ -2794,6 +2738,62 @@ static int internal_get_user_pages_fast(unsigned long
start, int nr_pages,
return ret;
}
+/*
+ * Like get_user_pages_fast() except it's IRQ-safe in that it won't fall back
to
+ * the regular GUP.
+ * Note a difference with get_user_pages_fast: this always returns the
+ * number of pages pinned, 0 if no pages were pinned.
+ *
+ * If the architecture does not support this function, simply return with no
+ * pages pinned.
+ */
+int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
+ struct page **pages)
+{
+ unsigned long len, end;
+ unsigned long flags;
+ int nr_pinned = 0;
+ /*
+* Internally (within mm/gup.c), gup fast variants must set FOLL_GET,
+* because gup fast is always a "pin with a +1 page refcount" request.
+*/
+ unsigned int gup_flags = FOLL_GET;
+
+ if (write)
+ gup_flags |= FOLL_WRITE;
+
+ start = untagged_addr(start) & PAGE_MASK;
+ len = (unsigned long) nr_pages << PAGE_SHIFT;
+ end = start + len;
+
+ if (end <= start)
+ return 0;
+ if (unlikely(!access_ok((void __user *)start, len)))
+ return 0;
+
+ /*
+* Disable interrupts. We use the nested form as we can already have
+* interrupts disabled by get_futex_key.
+*
+* With interrupts disabled, we block page table pages from being
+* freed from under us. See struct mmu_table_batch comments in
+* include/asm-generic/tlb.h for more details.
+*
+* We do not adopt an rcu_read_lock(.) here as we also want to
+* block IPIs that come from THPs splitting.
+*/
+
+ if (IS_ENABLED(CONFIG_HAVE_FAST_GUP) &&
+ gup_fast_permitted(start, end)) {
+ local_irq_save(flags);
+ gup_pgd_range(start, end, gup_flags, pages, _pinned);
+ local_irq_restore(flags);
+ }
+
+ return nr_pinned;
+}
+EXPORT_SYMBOL_GPL(__get_user_pages_fast);
+
/**
* get_user_pages_fast() - pin user pages in memory
* @start: starting user address
--
2.26.2
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[Intel-gfx] [PATCH 0/4] mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages()
This needs to go through Andrew's -mm tree, due to adding a new gup.c routine. However, I would really love to have some testing from the drm/i915 folks, because I haven't been able to run-time test that part of it. Otherwise, though, the series has passed my basic run time testing: some LTP tests, some xfs and etx4 non-destructive xfstests, and an assortment of other smaller ones: vm selftests, io_uring_register, a few more. But that's only on one particular machine. Also, cross-compile tests for half a dozen arches all pass. Details: In order to convert the drm/i915 driver from get_user_pages() to pin_user_pages(), a FOLL_PIN equivalent of __get_user_pages_fast() was required. That led to refactoring __get_user_pages_fast(), with the following goals: 1) As above: provide a pin_user_pages*() routine for drm/i915 to call, in place of __get_user_pages_fast(), 2) Get rid of the gup.c duplicate code for walking page tables with interrupts disabled. This duplicate code is a minor maintenance problem anyway. 3) Make it easy for an upcoming patch from Souptick, which aims to convert __get_user_pages_fast() to use a gup_flags argument, instead of a bool writeable arg. Also, if this series looks good, we can ask Souptick to change the name as well, to whatever the consensus is. My initial recommendation is: get_user_pages_fast_only(), to match the new pin_user_pages_only(). John Hubbard (4): mm/gup: move __get_user_pages_fast() down a few lines in gup.c mm/gup: refactor and de-duplicate gup_fast() code mm/gup: introduce pin_user_pages_fast_only() drm/i915: convert get_user_pages() --> pin_user_pages() drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 22 +-- include/linux/mm.h | 3 + mm/gup.c| 150 3 files changed, 107 insertions(+), 68 deletions(-) base-commit: 642b151f45dd54809ea00ecd3976a56c1ec9b53d -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: trace intel_uncore_*_fw()
On Tue, May 19, 2020 at 12:35:02AM +0100, Chris Wilson wrote: Quoting Lucas De Marchi (2020-05-19 00:30:49) Now that we have the declaration of trace_i915_reg_rw() in a separate header, start tracing intel_uncore_*_fw() mmio-accessors. These were untraced on purpose. humn... can you share why? I didn't find the purpose of being untraced anywhere. Right now I'm debugging the WA initialization and found it helpful to be able to trace them - https://gitlab.freedesktop.org/drm/intel/-/issues/1222#note_503179 thanks Lucas De Marchi -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Don't set queue-priority hint when supressing the reschedule
== Series Details == Series: series starting with [1/4] drm/i915: Don't set queue-priority hint when supressing the reschedule URL : https://patchwork.freedesktop.org/series/77377/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498 -> Patchwork_17702 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/index.html Known issues Here are the changes found in Patchwork_17702 that come from known issues: ### IGT changes ### Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][1] ([fdo#109271]) -> [FAIL][2] ([i915#62] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (52 -> 45) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8498 -> Patchwork_17702 CI-20190529: 20190529 CI_DRM_8498: 1493c649ae92207a758afa50a639275bd6c80e2e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17702: c9d0c46590ba517d45fc548ffdac9d81a19ddd37 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c9d0c46590ba drm/i915/selftests: Check for an initial-breadcrumb in wait_for_submit() 01cc89bf4af8 drm/i915/selftests: Restore to default heartbeat 4aca4773f1ae drm/i915/selftests: Change priority overflow detection c3388b20997e drm/i915: Don't set queue-priority hint when supressing the reschedule == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17702/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: trace intel_uncore_*_fw()
Quoting Lucas De Marchi (2020-05-19 00:30:49) > Now that we have the declaration of trace_i915_reg_rw() in a separate > header, start tracing intel_uncore_*_fw() mmio-accessors. These were untraced on purpose. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915: Don't set queue-priority hint when supressing the reschedule
== Series Details == Series: series starting with [1/4] drm/i915: Don't set queue-priority hint when supressing the reschedule URL : https://patchwork.freedesktop.org/series/77377/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Don't set queue-priority hint when supressing the reschedule
== Series Details == Series: series starting with [1/4] drm/i915: Don't set queue-priority hint when supressing the reschedule URL : https://patchwork.freedesktop.org/series/77377/ State : warning == Summary == $ dim checkpatch origin/drm-tip c3388b20997e drm/i915: Don't set queue-priority hint when supressing the reschedule -:10: WARNING:TYPO_SPELLING: 'runnning' may be misspelled - perhaps 'running'? #10: the HW runnning with only the inflight request. total: 0 errors, 1 warnings, 0 checks, 28 lines checked 4aca4773f1ae drm/i915/selftests: Change priority overflow detection 01cc89bf4af8 drm/i915/selftests: Restore to default heartbeat c9d0c46590ba drm/i915/selftests: Check for an initial-breadcrumb in wait_for_submit() ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/2] lib: Cleanup __igt_params_open()
The device always exist, so use it to derive the module name required to
lookup either the debugfs params directory or the sysfs module parameters.
Fixes: 2f5cee33ce55 ("igt/params: use igt_params_set_save for
igt_set_module_param*")
Signed-off-by: Chris Wilson
Cc: Jani Nikula
Cc: Juha-Pekka Heikkila
---
lib/igt_params.c | 165 +--
1 file changed, 29 insertions(+), 136 deletions(-)
diff --git a/lib/igt_params.c b/lib/igt_params.c
index 3decc5b2a..c06416988 100644
--- a/lib/igt_params.c
+++ b/lib/igt_params.c
@@ -80,9 +80,18 @@ static void igt_params_exit_handler(int sig)
* Notice that this function is called by igt_set_module_param(), so that one -
* or one of its wrappers - is the only function the test programs need to
call.
*/
-static void igt_params_save(int dir, const char *path, const char *name)
+static void igt_params_save(int dir, const char *name)
{
struct module_param_data *data;
+ char path[PATH_MAX];
+ char buf[80];
+ int len;
+
+ snprintf(buf, sizeof(buf), "/proc/self/fd/%d", dir);
+ len = readlink(buf, path, sizeof(path) - 1);
+ if (len < 0)
+ return;
+ path[len] = '\0';
/* Check if this parameter is already saved. */
for (data = module_params; data != NULL; data = data->next)
@@ -110,175 +119,59 @@ static void igt_params_save(int dir, const char *path,
const char *name)
}
/**
- * __igt_params_open:
- * @device: fd of the device or -1 for default
- * @outpath: full path to the sysfs directory if not NULL
- * @param: name of parameter of interest
- *
- * Find parameter of interest and return parameter directory fd, parameter
- * is first searched at debugfs/dri/N/_params and if not found will
- * look for parameter at /sys/module//parameters.
- *
- * Giving -1 here for default device will search for matching device from
- * debugfs/dri/N where N go from 0 to 63. First device found from debugfs
- * which exist also at /sys/module/ will be 'default'.
- * Default device will only be used for sysfs, not for debugfs.
+ * igt_params_open:
+ * @device: fd of the device
*
- * If outpath is not NULL caller is responsible to free given pointer.
+ * This opens the module parameters directory (under sysfs) corresponding
+ * to the device for use with igt_sysfs_set() and igt_sysfs_get().
*
* Returns:
- * Directory fd, or -1 on failure.
+ * The directory fd, or -1 on failure.
*/
-static int __igt_params_open(int device, char **outpath, const char *param)
+int igt_params_open(int device)
{
+ drm_version_t version;
int dir, params = -1;
- struct stat buffer;
- char searchname[64];
- char searchpath[PATH_MAX];
- char *foundname, *ctx;
+ char path[PATH_MAX];
+ char name[32] = "";
+
+ memset(, 0, sizeof(version));
+ version.name_len = sizeof(name);
+ version.name = name;
+ if (ioctl(device, DRM_IOCTL_VERSION, ))
+ return -1;
dir = igt_debugfs_dir(device);
if (dir >= 0) {
- int devname;
-
- devname = openat(dir, "name", O_RDONLY);
- igt_require_f(devname >= 0,
- "Driver need to name itself in debugfs!");
-
- read(devname, searchname, sizeof(searchname));
- close(devname);
-
- foundname = strtok_r(searchname, " ", );
- igt_require_f(foundname,
- "Driver need to name itself in debugfs!");
-
- snprintf(searchpath, PATH_MAX, "%s_params", foundname);
- params = openat(dir, searchpath, O_RDONLY);
-
- if (params >= 0) {
- char *debugfspath = malloc(PATH_MAX);
-
- igt_debugfs_path(device, debugfspath, PATH_MAX);
- if (param != NULL) {
- char filepath[PATH_MAX];
-
- snprintf(filepath, PATH_MAX, "%s/%s",
-debugfspath, param);
-
- if (stat(filepath, ) == 0) {
- if (outpath != NULL)
- *outpath = debugfspath;
- else
- free(debugfspath);
- } else {
- free(debugfspath);
- close(params);
- params = -1;
- }
- } else if (outpath != NULL) {
- /*
-* Caller is responsible to free this.
-*/
- *outpath = debugfspath;
- } else {
- free(debugfspath);
-
[Intel-gfx] [PATCH i-g-t 1/2] Always pass device to igt_params_set
Don't second guess, require the user to provide the device that wish to
set the module parameter for.
Signed-off-by: Chris Wilson
---
lib/igt_params.c | 8
lib/igt_params.h | 4 ++--
lib/igt_psr.c | 18 -
lib/igt_psr.h | 6 +++---
tests/i915/i915_pm_dc.c | 12 ++--
tests/kms_busy.c | 8
tests/kms_fbcon_fbt.c | 32 +++
tests/kms_force_connector_basic.c | 6 +++---
tests/kms_frontbuffer_tracking.c | 10 +-
tests/kms_panel_fitting.c | 2 +-
tests/kms_psr.c | 6 +++---
tests/kms_psr2_su.c | 6 --
12 files changed, 60 insertions(+), 58 deletions(-)
diff --git a/lib/igt_params.c b/lib/igt_params.c
index d8649dfd9..3decc5b2a 100644
--- a/lib/igt_params.c
+++ b/lib/igt_params.c
@@ -343,9 +343,9 @@ bool igt_params_save_and_set(int device, const char
*parameter, const char *fmt,
* Please consider using igt_set_module_param_int() for the integer and bool
* parameters.
*/
-void igt_set_module_param(const char *name, const char *val)
+void igt_set_module_param(int device, const char *name, const char *val)
{
- igt_assert(igt_params_save_and_set(-1, name, "%s", val));
+ igt_assert(igt_params_save_and_set(device, name, "%s", val));
}
/**
@@ -356,7 +356,7 @@ void igt_set_module_param(const char *name, const char *val)
* This is a wrapper for igt_set_module_param() that takes an integer instead
of
* a string. Please see igt_set_module_param().
*/
-void igt_set_module_param_int(const char *name, int val)
+void igt_set_module_param_int(int device, const char *name, int val)
{
- igt_assert(igt_params_save_and_set(-1, name, "%d", val));
+ igt_assert(igt_params_save_and_set(device, name, "%d", val));
}
diff --git a/lib/igt_params.h b/lib/igt_params.h
index ed17f34a5..bbd6f3ee6 100644
--- a/lib/igt_params.h
+++ b/lib/igt_params.h
@@ -34,7 +34,7 @@ bool igt_params_set(int device, const char *parameter, const
char *fmt, ...);
__attribute__((format(printf, 3, 4)))
bool igt_params_save_and_set(int device, const char *parameter, const char
*fmt, ...);
-void igt_set_module_param(const char *name, const char *val);
-void igt_set_module_param_int(const char *name, int val);
+void igt_set_module_param(int device, const char *name, const char *val);
+void igt_set_module_param_int(int device, const char *name, int val);
#endif /* __IGT_PARAMS_H__ */
diff --git a/lib/igt_psr.c b/lib/igt_psr.c
index c2a8d0e11..4109b5295 100644
--- a/lib/igt_psr.c
+++ b/lib/igt_psr.c
@@ -94,11 +94,11 @@ static int has_psr_debugfs(int debugfs_fd)
return -EINVAL;
}
-static bool psr_modparam_set(int val)
+static bool psr_modparam_set(int device, int val)
{
static int oldval = -1;
- igt_set_module_param_int("enable_psr", val);
+ igt_set_module_param_int(device, "enable_psr", val);
if (val == oldval)
return false;
@@ -114,7 +114,7 @@ static void restore_psr_debugfs(int sig)
psr_write(psr_restore_debugfs_fd, "0");
}
-static bool psr_set(int debugfs_fd, int mode)
+static bool psr_set(int device, int debugfs_fd, int mode)
{
int ret;
@@ -131,7 +131,7 @@ static bool psr_set(int debugfs_fd, int mode)
* version enabled and the PSR version of the test, it will
* fail in the first psr_wait_entry() of the test.
*/
- ret = psr_modparam_set(mode >= PSR_MODE_1);
+ ret = psr_modparam_set(device, mode >= PSR_MODE_1);
} else {
const char *debug_val;
@@ -161,18 +161,18 @@ static bool psr_set(int debugfs_fd, int mode)
return ret;
}
-bool psr_enable(int debugfs_fd, enum psr_mode mode)
+bool psr_enable(int device, int debugfs_fd, enum psr_mode mode)
{
- return psr_set(debugfs_fd, mode);
+ return psr_set(device, debugfs_fd, mode);
}
-bool psr_disable(int debugfs_fd)
+bool psr_disable(int device, int debugfs_fd)
{
/* Any mode different than PSR_MODE_1/2 will disable PSR */
- return psr_set(debugfs_fd, -1);
+ return psr_set(device, debugfs_fd, -1);
}
-bool psr_sink_support(int debugfs_fd, enum psr_mode mode)
+bool psr_sink_support(int device, int debugfs_fd, enum psr_mode mode)
{
char buf[PSR_STATUS_MAX_LEN];
int ret;
diff --git a/lib/igt_psr.h b/lib/igt_psr.h
index 02ce760b2..b2afb6119 100644
--- a/lib/igt_psr.h
+++ b/lib/igt_psr.h
@@ -39,9 +39,9 @@ bool psr_disabled_check(int debugfs_fd);
bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
-bool psr_enable(int debugfs_fd, enum psr_mode);
-bool psr_disable(int debugfs_fd);
-bool psr_sink_support(int debugfs_fd, enum psr_mode);
+bool psr_enable(int device, int
[Intel-gfx] [PATCH 2/2] drm/i915: trace intel_uncore_*_fw()
Now that we have the declaration of trace_i915_reg_rw() in a separate
header, start tracing intel_uncore_*_fw() mmio-accessors.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_uncore.h | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 8d3aa8b9acf9..0f95b32ff0f0 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -31,6 +31,7 @@
#include
#include "i915_reg.h"
+#include "i915_trace_reg_rw.h"
struct drm_i915_private;
struct intel_runtime_pm;
@@ -348,8 +349,9 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore,
#undef __uncore_read
#undef __uncore_write
-/* These are untraced mmio-accessors that are only valid to be used inside
- * critical sections, such as inside IRQ handlers, where forcewake is
explicitly
+/*
+ * These are mmio-accessors that are only valid to be used inside critical
+ * sections, such as inside IRQ handlers, where forcewake is explicitly
* controlled.
*
* Think twice, and think again, before using these.
@@ -374,9 +376,24 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore,
* therefore generally be serialised, by either the dev_priv->uncore.lock or
* a more localised lock guarding all access to that bank of registers.
*/
-#define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
-#define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
-#define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
+#define intel_uncore_read_fw(uncore, reg) ({ \
+ typeof(reg) reg___ = reg; \
+ u32 val___ = __raw_uncore_read32(uncore, (reg___)); \
+ trace_i915_reg_rw(false, reg___, val___, sizeof(val___), true); \
+ val___; })
+
+#define intel_uncore_write_fw(uncore, reg, val) ({ \
+ typeof(reg) reg___ = reg; \
+ typeof(val) val___ = val; \
+ trace_i915_reg_rw(true, reg___, val___, sizeof(val___), true); \
+ __raw_uncore_write32(uncore, reg___, val___); })
+
+#define intel_uncore_write64_fw(uncore, reg, val) ({ \
+ typeof(reg) reg___ = reg; \
+ typeof(val) val___ = val; \
+ trace_i915_reg_rw(true, reg___, val___, sizeof(val___), true); \
+ __raw_uncore_write64(uncore, reg___, val___); })
+
#define intel_uncore_posting_read_fw(...)
((void)intel_uncore_read_fw(__VA_ARGS__))
static inline void intel_uncore_rmw(struct intel_uncore *uncore,
--
2.26.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: move trace_i915_reg_rw() to a separate file
Currently we can't call trace_i915_reg_rw() from some headers due to
include order and i915_trace.h needing some struct definitions.
Move the declaration of trace_i915_reg_rw() to another file so it can be
included separately. Note that the trace points are still defined by
i915_trace_point.c which contains all trace points for i915. As such the
i915_trace_reg_rw() is just declared in a separate header, but its
definition is still in a single place.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_trace.h| 30 ++---
drivers/gpu/drm/i915/i915_trace_reg_rw.h | 42
2 files changed, 44 insertions(+), 28 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_trace_reg_rw.h
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index bc854ad60954..24b8e41600af 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -914,34 +914,6 @@ DEFINE_EVENT(i915_request, i915_request_wait_end,
TP_ARGS(rq)
);
-TRACE_EVENT_CONDITION(i915_reg_rw,
- TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace),
-
- TP_ARGS(write, reg, val, len, trace),
-
- TP_CONDITION(trace),
-
- TP_STRUCT__entry(
- __field(u64, val)
- __field(u32, reg)
- __field(u16, write)
- __field(u16, len)
- ),
-
- TP_fast_assign(
- __entry->val = (u64)val;
- __entry->reg = i915_mmio_reg_offset(reg);
- __entry->write = write;
- __entry->len = len;
- ),
-
- TP_printk("%s reg=0x%x, len=%d, val=(0x%x, 0x%x)",
- __entry->write ? "write" : "read",
- __entry->reg, __entry->len,
- (u32)(__entry->val & 0x),
- (u32)(__entry->val >> 32))
-);
-
TRACE_EVENT(intel_gpu_freq_change,
TP_PROTO(u32 freq),
TP_ARGS(freq),
@@ -1031,6 +1003,8 @@ DEFINE_EVENT(i915_context, i915_context_free,
TP_ARGS(ctx)
);
+#include "i915_trace_reg_rw.h"
+
#endif /* _I915_TRACE_H_ */
/* This part must be outside protection */
diff --git a/drivers/gpu/drm/i915/i915_trace_reg_rw.h
b/drivers/gpu/drm/i915/i915_trace_reg_rw.h
new file mode 100644
index ..2b0f2f00fbc9
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_trace_reg_rw.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * protect against inclusions if it has already being included by the main file
+ */
+#if !defined(_I915_TRACE_REG_RW_H_) || defined(TRACE_HEADER_MULTI_READ)
+#define _I915_TRACE_REG_RW_H_
+
+#include
+#include
+#include
+
+#include "i915_reg.h"
+
+TRACE_EVENT_CONDITION(i915_reg_rw,
+ TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace),
+
+ TP_ARGS(write, reg, val, len, trace),
+
+ TP_CONDITION(trace),
+
+ TP_STRUCT__entry(
+ __field(u64, val)
+ __field(u32, reg)
+ __field(u16, write)
+ __field(u16, len)
+ ),
+
+ TP_fast_assign(
+ __entry->val = (u64)val;
+ __entry->reg = i915_mmio_reg_offset(reg);
+ __entry->write = write;
+ __entry->len = len;
+ ),
+
+ TP_printk("%s reg=0x%x, len=%d, val=(0x%x, 0x%x)",
+ __entry->write ? "write" : "read",
+ __entry->reg, __entry->len,
+ (u32)(__entry->val & 0x),
+ (u32)(__entry->val >> 32))
+);
+
+#endif
--
2.26.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Resolve device hotunplug issues
== Series Details == Series: drm/i915: Resolve device hotunplug issues URL : https://patchwork.freedesktop.org/series/77372/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498 -> Patchwork_17701 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/index.html Known issues Here are the changes found in Patchwork_17701 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-crc-fast: - fi-icl-u2: [PASS][1] -> [FAIL][2] ([i915#262]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 Participating hosts (52 -> 45) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8498 -> Patchwork_17701 CI-20190529: 20190529 CI_DRM_8498: 1493c649ae92207a758afa50a639275bd6c80e2e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17701: 721e7aad8fe545ebf5b6c946880abbc18b0838e3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 721e7aad8fe5 drm/i915: Move UC firmware cleanup from driver_release to _remove 6790fa9abcae drm/i915: Move GGTT cleanup from driver_release to _remove 8fd9c3d7066d drm/i915: Release GT resources on driver remove 4d3df739b858 drm/i915: Drop user contexts on driver remove == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17701/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: Use ARRAY_SIZE for vgpu_types
== Series Details == Series: drm/i915/gvt: Use ARRAY_SIZE for vgpu_types URL : https://patchwork.freedesktop.org/series/77369/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498_full -> Patchwork_17699_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17699_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-apl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [PASS][3] -> [FAIL][4] ([IGT#5]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl10/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-skl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html * igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-untiled: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#177] / [i915#52] / [i915#54]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl5/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-untiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-skl4/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-untiled.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#69]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl8/igt@kms_fbcon_...@psr-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-skl10/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip_tiling@flip-changes-tiling: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl8/igt@kms_flip_til...@flip-changes-tiling.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-apl6/igt@kms_flip_til...@flip-changes-tiling.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#1188]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl7/igt@kms_...@bpc-switch-dpms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-skl5/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-kbl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-kbl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-iclb7/igt@kms_psr@psr2_sprite_render.html * igt@perf@blocking: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1542]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl5/igt@p...@blocking.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-skl4/igt@p...@blocking.html Possible fixes * igt@gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][21] ([i915#1436] / [i915#716]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-apl1/igt@gen9_exec_pa...@allowed-all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-apl7/igt@gen9_exec_pa...@allowed-all.html * igt@i915_selftest@live@execlists: - shard-skl: [INCOMPLETE][23] ([i915#1795] / [i915#1874]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/shard-skl2/igt@i915_selftest@l...@execlists.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/shard-skl7/igt@i915_selftest@l...@execlists.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][25] ([i915#180]) -> [PASS][26] +4 similar issues [25]:
[Intel-gfx] [PATCH 1/4] drm/i915: Don't set queue-priority hint when supressing the reschedule
We recorded the execlists->queue_priority_hint update for the inflight
request without kicking the tasklet. The next submitted request then
failed to be scheduled as it had a lower priority than the hint, leaving
the HW runnning with only the inflight request.
Fixes: 6cebcf746f3f ("drm/i915: Tweak scheduler's kick_submission()")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_scheduler.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index f4ea318781f0..cbb880b10c65 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -209,14 +209,6 @@ static void kick_submission(struct intel_engine_cs *engine,
if (!inflight)
goto unlock;
- ENGINE_TRACE(engine,
-"bumping queue-priority-hint:%d for rq:%llx:%lld,
inflight:%llx:%lld prio %d\n",
-prio,
-rq->fence.context, rq->fence.seqno,
-inflight->fence.context, inflight->fence.seqno,
-inflight->sched.attr.priority);
- engine->execlists.queue_priority_hint = prio;
-
/*
* If we are already the currently executing context, don't
* bother evaluating if we should preempt ourselves.
@@ -224,6 +216,14 @@ static void kick_submission(struct intel_engine_cs *engine,
if (inflight->context == rq->context)
goto unlock;
+ ENGINE_TRACE(engine,
+"bumping queue-priority-hint:%d for rq:%llx:%lld,
inflight:%llx:%lld prio %d\n",
+prio,
+rq->fence.context, rq->fence.seqno,
+inflight->fence.context, inflight->fence.seqno,
+inflight->sched.attr.priority);
+
+ engine->execlists.queue_priority_hint = prio;
if (need_preempt(prio, rq_prio(inflight)))
tasklet_hi_schedule(>execlists.tasklet);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/i915/selftests: Change priority overflow detection
Check for integer overflow in the priority chain, rather than against a type-constricted max-priority check. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 97447de92843..f128744ab09b 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -2735,12 +2735,12 @@ static int live_preempt_gang(void *arg) /* Submit each spinner at increasing priority */ engine->schedule(rq, ); + if (prio < attr.priority) + break; + if (prio <= I915_PRIORITY_MAX) continue; - if (prio > (INT_MAX >> I915_USER_PRIORITY_SHIFT)) - break; - if (__igt_timeout(end_time, NULL)) break; } while (1); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915/selftests: Check for an initial-breadcrumb in wait_for_submit()
When we look at i915_request_is_started() we must be careful in case we are using a request that does not have the initial-breadcrumb and instead the is-started is being compared against the end of the previous request. This will make wait_for_submit() declare that a request has been already submitted too early. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 3cf7c0b13ab4..c3d722840e2d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -75,7 +75,7 @@ static bool is_active(struct i915_request *rq) if (i915_request_on_hold(rq)) return true; - if (i915_request_started(rq)) + if (i915_request_has_initial_breadcrumb(rq) && i915_request_started(rq)) return true; return false; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/i915/selftests: Restore to default heartbeat
Since we temporarily disable the heartbeat and restore back to the
default value, we can use the stored defaults on the engine and avoid
using a local.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 25 +++
drivers/gpu/drm/i915/gt/selftest_lrc.c | 67 +++
drivers/gpu/drm/i915/gt/selftest_rps.c | 69
drivers/gpu/drm/i915/gt/selftest_timeline.c | 15 ++---
4 files changed, 67 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 2b2efff6e19d..4aa4cc917d8b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -310,22 +310,20 @@ static bool wait_until_running(struct hang *h, struct
i915_request *rq)
1000));
}
-static void engine_heartbeat_disable(struct intel_engine_cs *engine,
-unsigned long *saved)
+static void engine_heartbeat_disable(struct intel_engine_cs *engine)
{
- *saved = engine->props.heartbeat_interval_ms;
engine->props.heartbeat_interval_ms = 0;
intel_engine_pm_get(engine);
intel_engine_park_heartbeat(engine);
}
-static void engine_heartbeat_enable(struct intel_engine_cs *engine,
- unsigned long saved)
+static void engine_heartbeat_enable(struct intel_engine_cs *engine)
{
intel_engine_pm_put(engine);
- engine->props.heartbeat_interval_ms = saved;
+ engine->props.heartbeat_interval_ms =
+ engine->defaults.heartbeat_interval_ms;
}
static int igt_hang_sanitycheck(void *arg)
@@ -473,7 +471,6 @@ static int igt_reset_nop_engine(void *arg)
for_each_engine(engine, gt, id) {
unsigned int reset_count, reset_engine_count, count;
struct intel_context *ce;
- unsigned long heartbeat;
IGT_TIMEOUT(end_time);
int err;
@@ -485,7 +482,7 @@ static int igt_reset_nop_engine(void *arg)
reset_engine_count = i915_reset_engine_count(global, engine);
count = 0;
- engine_heartbeat_disable(engine, );
+ engine_heartbeat_disable(engine);
set_bit(I915_RESET_ENGINE + id, >reset.flags);
do {
int i;
@@ -529,7 +526,7 @@ static int igt_reset_nop_engine(void *arg)
}
} while (time_before(jiffies, end_time));
clear_bit(I915_RESET_ENGINE + id, >reset.flags);
- engine_heartbeat_enable(engine, heartbeat);
+ engine_heartbeat_enable(engine);
pr_info("%s(%s): %d resets\n", __func__, engine->name, count);
@@ -564,7 +561,6 @@ static int __igt_reset_engine(struct intel_gt *gt, bool
active)
for_each_engine(engine, gt, id) {
unsigned int reset_count, reset_engine_count;
- unsigned long heartbeat;
IGT_TIMEOUT(end_time);
if (active && !intel_engine_can_store_dword(engine))
@@ -580,7 +576,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool
active)
reset_count = i915_reset_count(global);
reset_engine_count = i915_reset_engine_count(global, engine);
- engine_heartbeat_disable(engine, );
+ engine_heartbeat_disable(engine);
set_bit(I915_RESET_ENGINE + id, >reset.flags);
do {
if (active) {
@@ -632,7 +628,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool
active)
}
} while (time_before(jiffies, end_time));
clear_bit(I915_RESET_ENGINE + id, >reset.flags);
- engine_heartbeat_enable(engine, heartbeat);
+ engine_heartbeat_enable(engine);
if (err)
break;
@@ -789,7 +785,6 @@ static int __igt_reset_engines(struct intel_gt *gt,
struct active_engine threads[I915_NUM_ENGINES] = {};
unsigned long device = i915_reset_count(global);
unsigned long count = 0, reported;
- unsigned long heartbeat;
IGT_TIMEOUT(end_time);
if (flags & TEST_ACTIVE &&
@@ -832,7 +827,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
yield(); /* start all threads before we begin */
- engine_heartbeat_disable(engine, );
+ engine_heartbeat_disable(engine);
set_bit(I915_RESET_ENGINE + id, >reset.flags);
do {
struct i915_request *rq = NULL;
@@ -906,7 +901,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
}
} while (time_before(jiffies, end_time));
clear_bit(I915_RESET_ENGINE + id,
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Resolve device hotunplug issues
== Series Details == Series: drm/i915: Resolve device hotunplug issues URL : https://patchwork.freedesktop.org/series/77372/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2312:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2313:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2314:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2315:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2316:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2317:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/compiler.h:199:9: warning: context imbalance in 'engines_sample' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' -
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Resolve device hotunplug issues
== Series Details == Series: drm/i915: Resolve device hotunplug issues URL : https://patchwork.freedesktop.org/series/77372/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4d3df739b858 drm/i915: Drop user contexts on driver remove -:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #19: <4> [36.901117] CPU: 0 PID: 39 Comm: kworker/u8:1 Tainted: G U W 5.7.0-rc5-CI-CI_DRM_8485+ #1 -:66: WARNING:UNNECESSARY_INT: Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary #66: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:937: + unsigned long int id; -:73: WARNING:UNNECESSARY_INT: Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary #73: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:944: + unsigned long int idx; total: 0 errors, 3 warnings, 0 checks, 59 lines checked 8fd9c3d7066d drm/i915: Release GT resources on driver remove -:22: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #22: <4> [39.201162] CPU: 6 PID: 7 Comm: kworker/u16:0 Tainted: G U W 5.7.0-rc5-CI-CI_DRM_8485+ #1 total: 0 errors, 1 warnings, 0 checks, 8 lines checked 6790fa9abcae drm/i915: Move GGTT cleanup from driver_release to _remove -:57: WARNING:BAD_SIGN_OFF: Duplicate signature #57: Signed-off-by: Janusz Krzysztofik total: 0 errors, 1 warnings, 0 checks, 53 lines checked 721e7aad8fe5 drm/i915: Move UC firmware cleanup from driver_release to _remove -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: <4> [93.336056] WARNING: CPU: 6 PID: 200 at drivers/gpu/drm/i915/intel_runtime_pm.c:361 __intel_runtime_pm_get+0x4d/0x60 [i915] total: 0 errors, 1 warnings, 0 checks, 15 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Check for an initial-breadcrumb in wait_for_submit()
== Series Details == Series: drm/i915/selftests: Check for an initial-breadcrumb in wait_for_submit() URL : https://patchwork.freedesktop.org/series/77371/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8498 -> Patchwork_17700 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17700 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17700, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17700/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17700: ### IGT changes ### Possible regressions * igt@i915_selftest@live@execlists: - fi-cfl-8700k: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17700/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html Known issues Here are the changes found in Patchwork_17700 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-tgl-y: [PASS][3] -> [INCOMPLETE][4] ([i915#1803]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-tgl-y/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17700/fi-tgl-y/igt@i915_selftest@l...@execlists.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][5] ([fdo#109271]) -> [FAIL][6] ([i915#62]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17700/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (52 -> 44) -- Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8498 -> Patchwork_17700 CI-20190529: 20190529 CI_DRM_8498: 1493c649ae92207a758afa50a639275bd6c80e2e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17700: 45dd86e4e757389f0092db49380a1587abb41da3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 45dd86e4e757 drm/i915/selftests: Check for an initial-breadcrumb in wait_for_submit() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17700/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] lib: Cleanup __igt_params_open()
The device always exist, so use it to derive the module name required to
lookup either the debugfs params directory or the sysfs module parameters.
Fixes: 2f5cee33ce55 ("igt/params: use igt_params_set_save for
igt_set_module_param*")
Signed-off-by: Chris Wilson
Cc: Jani Nikula
Cc: Juha-Pekka Heikkila
---
lib/igt_params.c | 165 +--
1 file changed, 29 insertions(+), 136 deletions(-)
diff --git a/lib/igt_params.c b/lib/igt_params.c
index d8649dfd9..23660f445 100644
--- a/lib/igt_params.c
+++ b/lib/igt_params.c
@@ -80,9 +80,18 @@ static void igt_params_exit_handler(int sig)
* Notice that this function is called by igt_set_module_param(), so that one -
* or one of its wrappers - is the only function the test programs need to
call.
*/
-static void igt_params_save(int dir, const char *path, const char *name)
+static void igt_params_save(int dir, const char *name)
{
struct module_param_data *data;
+ char path[PATH_MAX];
+ char buf[80];
+ int len;
+
+ snprintf(buf, sizeof(buf), "/proc/self/fd/%d", dir);
+ len = readlink(buf, path, sizeof(path) - 1);
+ if (len < 0)
+ return;
+ path[len] = '\0';
/* Check if this parameter is already saved. */
for (data = module_params; data != NULL; data = data->next)
@@ -110,175 +119,59 @@ static void igt_params_save(int dir, const char *path,
const char *name)
}
/**
- * __igt_params_open:
- * @device: fd of the device or -1 for default
- * @outpath: full path to the sysfs directory if not NULL
- * @param: name of parameter of interest
- *
- * Find parameter of interest and return parameter directory fd, parameter
- * is first searched at debugfs/dri/N/_params and if not found will
- * look for parameter at /sys/module//parameters.
- *
- * Giving -1 here for default device will search for matching device from
- * debugfs/dri/N where N go from 0 to 63. First device found from debugfs
- * which exist also at /sys/module/ will be 'default'.
- * Default device will only be used for sysfs, not for debugfs.
+ * igt_params_open:
+ * @device: fd of the device
*
- * If outpath is not NULL caller is responsible to free given pointer.
+ * This opens the module parameters directory (under sysfs) corresponding
+ * to the device for use with igt_sysfs_set() and igt_sysfs_get().
*
* Returns:
- * Directory fd, or -1 on failure.
+ * The directory fd, or -1 on failure.
*/
-static int __igt_params_open(int device, char **outpath, const char *param)
+int igt_params_open(int device)
{
+ drm_version_t version;
int dir, params = -1;
- struct stat buffer;
- char searchname[64];
- char searchpath[PATH_MAX];
- char *foundname, *ctx;
+ char path[PATH_MAX];
+ char name[32] = "";
+
+ memset(, 0, sizeof(version));
+ version.name_len = sizeof(name);
+ version.name = name;
+ if (ioctl(device, DRM_IOCTL_VERSION, ))
+ return -1;
dir = igt_debugfs_dir(device);
if (dir >= 0) {
- int devname;
-
- devname = openat(dir, "name", O_RDONLY);
- igt_require_f(devname >= 0,
- "Driver need to name itself in debugfs!");
-
- read(devname, searchname, sizeof(searchname));
- close(devname);
-
- foundname = strtok_r(searchname, " ", );
- igt_require_f(foundname,
- "Driver need to name itself in debugfs!");
-
- snprintf(searchpath, PATH_MAX, "%s_params", foundname);
- params = openat(dir, searchpath, O_RDONLY);
-
- if (params >= 0) {
- char *debugfspath = malloc(PATH_MAX);
-
- igt_debugfs_path(device, debugfspath, PATH_MAX);
- if (param != NULL) {
- char filepath[PATH_MAX];
-
- snprintf(filepath, PATH_MAX, "%s/%s",
-debugfspath, param);
-
- if (stat(filepath, ) == 0) {
- if (outpath != NULL)
- *outpath = debugfspath;
- else
- free(debugfspath);
- } else {
- free(debugfspath);
- close(params);
- params = -1;
- }
- } else if (outpath != NULL) {
- /*
-* Caller is responsible to free this.
-*/
- *outpath = debugfspath;
- } else {
- free(debugfspath);
-
[Intel-gfx] [PATCH i-g-t] perf: Hide any leak in gen8-unprivileged-single-ctx-counters
gen8-unprivileged-single-counters appears to leak contexts, and does not appear to be doing so intentionally.. Let's assume it's a bug in the test and see if the contexts are released along with the device fd. (If they are not released, that is more clearly an issue.) Signed-off-by: Chris Wilson --- tests/i915/gem_exec_fence.c | 2 +- tests/perf.c| 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c index 5b504e5c8..b88472c3a 100644 --- a/tests/i915/gem_exec_fence.c +++ b/tests/i915/gem_exec_fence.c @@ -1479,7 +1479,7 @@ static void test_syncobj_future_submit(int i915, unsigned int engine) /* * Here we submit client A waiting on client B, but internally client * B has a semaphore that waits on client A. This relies on timeslicing -* to reorder B before A, even though userspace has asked to submit +* to reorder A before B, even though userspace has asked to submit * A & B simultaneously (and due to the sequence we will submit B * then A). */ diff --git a/tests/perf.c b/tests/perf.c index d4ebae30d..c78f02a8d 100644 --- a/tests/perf.c +++ b/tests/perf.c @@ -3428,6 +3428,8 @@ gen8_test_single_ctx_render_target_writes_a_counter(void) .format = test_set->perf_oa_format }; + drm_fd = gem_reopen_driver(drm_fd); + bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096); drm_intel_bufmgr_gem_enable_reuse(bufmgr); -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] lib/i915: Reset all engine properties to defaults prior to the start of a test
We need each test in an isolated context, so that bad results from one
test do not interfere with the next. In particular, we want to clean up
the device and reset it to the defaults so that they are known for the
next test, and the test can focus on behaviour it wants to control.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
---
lib/i915/gem.c | 85
lib/igt_dummyload.c | 2 -
lib/igt_gt.c | 2 -
tests/i915/gem_ctx_persistence.c | 1 -
4 files changed, 85 insertions(+), 5 deletions(-)
diff --git a/lib/i915/gem.c b/lib/i915/gem.c
index cabd23768..3ef31ed33 100644
--- a/lib/i915/gem.c
+++ b/lib/i915/gem.c
@@ -22,6 +22,7 @@
*
*/
+#include
#include
#include
@@ -30,6 +31,89 @@
#include "igt_debugfs.h"
#include "igt_sysfs.h"
+static void __restore_defaults(int engine)
+{
+ struct dirent *de;
+ int defaults;
+ DIR *dir;
+
+ defaults = openat(engine, ".defaults", O_RDONLY);
+ if (defaults < 0)
+ return;
+
+ dir = fdopendir(defaults);
+ if (!dir) {
+ close(defaults);
+ return;
+ }
+
+ while ((de = readdir(dir))) {
+ char buf[256];
+ int fd, len;
+
+ if (*de->d_name == '.')
+ continue;
+
+ fd = openat(defaults, de->d_name, O_RDONLY);
+ if (fd < 0)
+ continue;
+
+ len = read(fd, buf, sizeof(buf));
+ close(fd);
+ if (len < 0)
+ continue;
+
+ fd = openat(engine, de->d_name, O_WRONLY);
+ if (fd < 0)
+ continue;
+
+ write(fd, buf, len);
+ close(fd);
+ }
+
+ closedir(dir);
+}
+
+static void restore_defaults(int i915)
+{
+ struct dirent *de;
+ int engines;
+ DIR *dir;
+ int sys;
+
+ sys = igt_sysfs_open(i915);
+ if (sys < 0)
+ return;
+
+ engines = openat(sys, "engine", O_RDONLY);
+ if (engines < 0)
+ goto close_sys;
+
+ dir = fdopendir(engines);
+ if (!dir) {
+ close(engines);
+ goto close_sys;
+ }
+
+ while ((de = readdir(dir))) {
+ int engine;
+
+ if (*de->d_name == '.')
+ continue;
+
+ engine = openat(engines, de->d_name, O_RDONLY);
+ if (engine < 0)
+ continue;
+
+ __restore_defaults(engine);
+ close(engine);
+ }
+
+ closedir(dir);
+close_sys:
+ close(sys);
+}
+
static void reset_device(int i915)
{
int dir;
@@ -66,6 +150,7 @@ void igt_require_gem(int i915)
* sequences of batches.
*/
reset_device(i915);
+ restore_defaults(i915);
err = 0;
if (ioctl(i915, DRM_IOCTL_I915_GEM_THROTTLE)) {
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 0b52eb5b5..a733bd674 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -355,8 +355,6 @@ igt_spin_factory(int fd, const struct igt_spin_factory
*opts)
{
igt_spin_t *spin;
- igt_require_gem(fd);
-
if (opts->engine != ALL_ENGINES) {
struct intel_execution_engine2 e;
int class;
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index a806b567a..101627973 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -172,8 +172,6 @@ igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned
flags)
* to recover from reset and for it to remain wedged. It's hard to
* say even if we do hang/reset making the test suspect.
*/
- igt_require_gem(fd);
-
if (!igt_check_boolean_env_var("IGT_HANG", true))
igt_skip("hang injection disabled by user [IGT_HANG=0]\n");
gem_context_require_bannable(fd);
diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index ce9f02350..cca4c3a91 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -56,7 +56,6 @@ static void cleanup(int i915)
DROP_RESET_ACTIVE | DROP_RESET_SEQNO |
/* cleanup */
DROP_ACTIVE | DROP_RETIRE | DROP_IDLE | DROP_FREED);
- igt_require_gem(i915);
}
static int wait_for_status(int fence, int timeout)
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gvt: Use ARRAY_SIZE for vgpu_types
Quoting Aishwarya Ramakrishnan (2020-05-18 16:03:36) > Prefer ARRAY_SIZE instead of using sizeof > > Fixes coccicheck warning: Use ARRAY_SIZE > > Signed-off-by: Aishwarya Ramakrishnan Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: Use ARRAY_SIZE for vgpu_types
== Series Details == Series: drm/i915/gvt: Use ARRAY_SIZE for vgpu_types URL : https://patchwork.freedesktop.org/series/77369/ State : success == Summary == CI Bug Log - changes from CI_DRM_8498 -> Patchwork_17699 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/index.html Known issues Here are the changes found in Patchwork_17699 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-crc-fast: - fi-icl-u2: [PASS][1] -> [FAIL][2] ([i915#262]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8498/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 Participating hosts (52 -> 44) -- Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8498 -> Patchwork_17699 CI-20190529: 20190529 CI_DRM_8498: 1493c649ae92207a758afa50a639275bd6c80e2e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17699: ccbbd4f3aab67ca12a16da43196fa26d1633bf87 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ccbbd4f3aab6 drm/i915/gvt: Use ARRAY_SIZE for vgpu_types == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17699/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] lib: Cleanup __igt_params_open()
The device always exist, so use it to derive the module name required to
lookup either the debugfs params directory or the sysfs module parameters.
Fixes: 2f5cee33ce55 ("igt/params: use igt_params_set_save for
igt_set_module_param*")
Signed-off-by: Chris Wilson
Cc: Jani Nikula
Cc: Juha-Pekka Heikkila
---
lib/igt_params.c | 116 +++
1 file changed, 17 insertions(+), 99 deletions(-)
diff --git a/lib/igt_params.c b/lib/igt_params.c
index d8649dfd9..9d9a11c0b 100644
--- a/lib/igt_params.c
+++ b/lib/igt_params.c
@@ -131,117 +131,35 @@ static void igt_params_save(int dir, const char *path,
const char *name)
*/
static int __igt_params_open(int device, char **outpath, const char *param)
{
+ drm_version_t version;
int dir, params = -1;
- struct stat buffer;
- char searchname[64];
- char searchpath[PATH_MAX];
- char *foundname, *ctx;
+ char path[PATH_MAX];
+ char name[32];
+
+ memset(, 0, sizeof(version));
+ version.name_len = sizeof(name);
+ version.name = name;
+ if (ioctl(device, DRM_IOCTL_VERSION, ))
+ return -1;
dir = igt_debugfs_dir(device);
if (dir >= 0) {
- int devname;
-
- devname = openat(dir, "name", O_RDONLY);
- igt_require_f(devname >= 0,
- "Driver need to name itself in debugfs!");
-
- read(devname, searchname, sizeof(searchname));
- close(devname);
-
- foundname = strtok_r(searchname, " ", );
- igt_require_f(foundname,
- "Driver need to name itself in debugfs!");
-
- snprintf(searchpath, PATH_MAX, "%s_params", foundname);
- params = openat(dir, searchpath, O_RDONLY);
-
- if (params >= 0) {
- char *debugfspath = malloc(PATH_MAX);
-
- igt_debugfs_path(device, debugfspath, PATH_MAX);
- if (param != NULL) {
- char filepath[PATH_MAX];
-
- snprintf(filepath, PATH_MAX, "%s/%s",
-debugfspath, param);
-
- if (stat(filepath, ) == 0) {
- if (outpath != NULL)
- *outpath = debugfspath;
- else
- free(debugfspath);
- } else {
- free(debugfspath);
- close(params);
- params = -1;
- }
- } else if (outpath != NULL) {
- /*
-* Caller is responsible to free this.
-*/
- *outpath = debugfspath;
- } else {
- free(debugfspath);
- }
- }
+ snprintf(path, PATH_MAX, "%s_params", name);
+ params = openat(dir, path, O_RDONLY);
close(dir);
}
if (params < 0) { /* builtin? */
- drm_version_t version;
- char name[32] = "";
- char path[PATH_MAX];
-
- if (device == -1) {
- /*
-* find default device
-*/
- int file, i;
- const char *debugfs_root = igt_debugfs_mount();
-
- igt_assert(debugfs_root);
-
- for (i = 0; i < 63; i++) {
- char testpath[PATH_MAX];
-
- snprintf(searchpath, PATH_MAX,
-"%s/dri/%d/name", debugfs_root, i);
-
- file = open(searchpath, O_RDONLY);
-
- if (file < 0)
- continue;
-
- read(file, searchname, sizeof(searchname));
- close(file);
-
- foundname = strtok_r(searchname, " ", );
- if (!foundname)
- continue;
-
- snprintf(testpath, PATH_MAX,
-"/sys/module/%s/parameters",
-foundname);
-
- if (stat(testpath, ) == 0 &&
- S_ISDIR(buffer.st_mode)) {
- snprintf(name, sizeof(name), "%s",
-foundname);
-
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: fix incorrect return of an error status
== Series Details == Series: drm/i915: fix incorrect return of an error status URL : https://patchwork.freedesktop.org/series/77368/ State : failure == Summary == Applying: drm/i915: fix incorrect return of an error status Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_pm.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_pm.c No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs
== Series Details == Series: series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs URL : https://patchwork.freedesktop.org/series/77366/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8497 -> Patchwork_17697 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17697 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17697, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17697: ### IGT changes ### Possible regressions * igt@gem_close_race@basic-process: - fi-ivb-3770:[PASS][1] -> [FAIL][2] +11 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-ivb-3770/igt@gem_close_r...@basic-process.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-ivb-3770/igt@gem_close_r...@basic-process.html * igt@gem_close_race@basic-threads: - fi-skl-6600u: [PASS][3] -> [FAIL][4] +10 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-skl-6600u/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-skl-6600u/igt@gem_close_r...@basic-threads.html - fi-skl-guc: [PASS][5] -> [FAIL][6] +10 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-skl-guc/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-skl-guc/igt@gem_close_r...@basic-threads.html - fi-bwr-2160:[PASS][7] -> [FAIL][8] +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-bwr-2160/igt@gem_close_r...@basic-threads.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-bwr-2160/igt@gem_close_r...@basic-threads.html - fi-icl-y: [PASS][9] -> [FAIL][10] +10 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-icl-y/igt@gem_close_r...@basic-threads.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-icl-y/igt@gem_close_r...@basic-threads.html * igt@gem_ctx_create@basic: - fi-cml-s: [PASS][11] -> [FAIL][12] +10 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-cml-s/igt@gem_ctx_cre...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-cml-s/igt@gem_ctx_cre...@basic.html - fi-elk-e7500: [PASS][13] -> [FAIL][14] +11 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-elk-e7500/igt@gem_ctx_cre...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-elk-e7500/igt@gem_ctx_cre...@basic.html - fi-skl-6700k2: [PASS][15] -> [FAIL][16] +10 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-skl-6700k2/igt@gem_ctx_cre...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-skl-6700k2/igt@gem_ctx_cre...@basic.html - fi-cfl-guc: [PASS][17] -> [FAIL][18] +10 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-cfl-guc/igt@gem_ctx_cre...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-cfl-guc/igt@gem_ctx_cre...@basic.html - fi-bsw-n3050: [PASS][19] -> [FAIL][20] +9 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-bsw-n3050/igt@gem_ctx_cre...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-bsw-n3050/igt@gem_ctx_cre...@basic.html * igt@gem_exec_basic@basic: - fi-kbl-x1275: NOTRUN -> [FAIL][21] +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-kbl-x1275/igt@gem_exec_ba...@basic.html - fi-snb-2520m: NOTRUN -> [FAIL][22] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-snb-2520m/igt@gem_exec_ba...@basic.html - fi-pnv-d510:NOTRUN -> [FAIL][23] +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-pnv-d510/igt@gem_exec_ba...@basic.html - fi-apl-guc: NOTRUN -> [FAIL][24] +4 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-apl-guc/igt@gem_exec_ba...@basic.html - fi-cfl-8700k: NOTRUN -> [FAIL][25] +4 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-cfl-8700k/igt@gem_exec_ba...@basic.html - fi-tgl-y: NOTRUN -> [FAIL][26] +4 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17697/fi-tgl-y/igt@gem_exec_ba...@basic.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Measure dispatch latency (rev8)
== Series Details ==
Series: drm/i915/selftests: Measure dispatch latency (rev8)
URL : https://patchwork.freedesktop.org/series/77308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8495_full -> Patchwork_17695_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17695_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-kbl7/igt@gem_soft...@noreloc-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-kbl3/igt@gem_soft...@noreloc-s3.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#69])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-skl4/igt@i915_susp...@fence-restore-tiled2untiled.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-skl5/igt@i915_susp...@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#54])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-256x256-sliding.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-256x256-sliding.html
* igt@kms_flip_tiling@flip-changes-tiling:
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#95])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-apl4/igt@kms_flip_til...@flip-changes-tiling.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-apl4/igt@kms_flip_til...@flip-changes-tiling.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-skl4/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-apl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-apl1/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html
Possible fixes
* {igt@gem_ctx_isolation@preservation-s3@bcs0}:
- shard-skl: [INCOMPLETE][13] ([i915#198]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-skl2/igt@gem_ctx_isolation@preservation...@bcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-skl4/igt@gem_ctx_isolation@preservation...@bcs0.html
* {igt@gem_ctx_isolation@preservation-s3@rcs0}:
- shard-apl: [DMESG-WARN][15] ([i915#180]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-apl6/igt@gem_ctx_isolation@preservation...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-apl2/igt@gem_ctx_isolation@preservation...@rcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-kbl: [DMESG-WARN][17] ([i915#180]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-kbl2/igt@gem_workarou...@suspend-resume-context.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-kbl6/igt@gem_workarou...@suspend-resume-context.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-90:
- shard-tglb: [FAIL][19] ([i915#1172] / [i915#1897] / [i915#402])
-> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-tglb3/igt@kms_big...@y-tiled-32bpp-rotate-90.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-tglb7/igt@kms_big...@y-tiled-32bpp-rotate-90.html
* igt@kms_color@pipe-b-ctm-max:
- shard-tglb: [FAIL][21] ([i915#1149]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-tglb5/igt@kms_co...@pipe-b-ctm-max.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-tglb1/igt@kms_co...@pipe-b-ctm-max.html
* igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
- shard-tglb: [FAIL][23] ([i915#1897]) -> [PASS][24] +9 similar
issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/shard-tglb7/igt@kms_cursor_...@pipe-c-cursor-64x64-onscreen.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/shard-tglb6/igt@kms_cursor_...@pipe-c-cursor-64x64-onscreen.html
* igt@kms_fbcon_fbt@fbc-suspend:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs
== Series Details == Series: series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs URL : https://patchwork.freedesktop.org/series/77366/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/compiler.h:199:9: warning: context imbalance in 'engines_sample' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Move saturated workload detection back to the context
== Series Details ==
Series: series starting with [1/7] drm/i915: Move saturated workload detection
back to the context
URL : https://patchwork.freedesktop.org/series/77365/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8497 -> Patchwork_17696
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17696 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17696, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17696/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17696:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@execlists:
- fi-tgl-y: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-tgl-y/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17696/fi-tgl-y/igt@i915_selftest@l...@execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17696/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
Known issues
Here are the changes found in Patchwork_17696 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#656])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-apl-guc/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17696/fi-apl-guc/igt@i915_selftest@l...@execlists.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-skl-lmem:[INCOMPLETE][7] ([i915#1874]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8497/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17696/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1874]: https://gitlab.freedesktop.org/drm/intel/issues/1874
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (51 -> 45)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper
Build changes
-
* Linux: CI_DRM_8497 -> Patchwork_17696
CI-20190529: 20190529
CI_DRM_8497: 7b24f369fbedaf37fdb3fc86176235d77d36e804 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17696: a839695e72b2526414d38e634b60295c0c381a91 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a839695e72b2 drm/i915/gt: Resubmit the virtual engine on schedule-out
802e652868f5 drm/i915/gt: Decouple inflight virtual engines
d70a6bfd13b1 drm/i915/gt: Use virtual_engine during execlists_dequeue
0d70aed9a12c drm/i915/gt: Incorporate the virtual engine into timeslicing
d4fa09cdb48e drm/i915/gt: Kick virtual siblings on timeslice out
b869aac79c29 drm/i915/selftests: Add tests for timeslicing virtual engines
a7577cd7f63b drm/i915: Move saturated workload detection back to the context
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17696/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs
== Series Details == Series: series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs URL : https://patchwork.freedesktop.org/series/77366/ State : warning == Summary == $ dim checkpatch origin/drm-tip 960f6e1f205d drm/i915/params: don't expose inject_probe_failure in debugfs b47f6ca436b3 drm/i915/params: fix i915.fake_lmem_start module param sysfs permissions -:27: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #27: FILE: drivers/gpu/drm/i915/i915_params.c:177: +i915_param_named_unsafe(fake_lmem_start, ulong, 0400, "Fake LMEM start offset (default: 0)"); total: 0 errors, 0 warnings, 1 checks, 8 lines checked 2b633b42e776 drm/i915/params: prevent changing module params runtime -:48: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #48: FILE: drivers/gpu/drm/i915/i915_params.c:62: +i915_param_named_unsafe(enable_fbc, int, 0400, "Enable frame buffer compression for power savings " -:57: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #57: FILE: drivers/gpu/drm/i915/i915_params.c:70: +i915_param_named_unsafe(panel_use_ssc, int, 0400, "Use Spread Spectrum Clock with panels [LVDS/eDP] " -:66: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #66: FILE: drivers/gpu/drm/i915/i915_params.c:78: +i915_param_named_unsafe(reset, int, 0400, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); -:74: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #74: FILE: drivers/gpu/drm/i915/i915_params.c:85: +i915_param_named(error_capture, bool, 0400, "Record the GPU state following a hang. " -:81: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #81: FILE: drivers/gpu/drm/i915/i915_params.c:91: +i915_param_named_unsafe(enable_hangcheck, bool, 0400, "Periodically check GPU activity for detecting hangs. " -:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #87: FILE: drivers/gpu/drm/i915/i915_params.c:96: +i915_param_named_unsafe(enable_psr, int, 0400, "Enable PSR " -:99: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #99: FILE: drivers/gpu/drm/i915/i915_params.c:111: +i915_param_named(fastboot, int, 0400, "Try to skip unnecessary mode sets at boot time " -:105: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #105: FILE: drivers/gpu/drm/i915/i915_params.c:116: +i915_param_named_unsafe(load_detect_test, bool, 0400, "Force-enable the VGA load detect code for testing (default:false). " -:110: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #110: FILE: drivers/gpu/drm/i915/i915_params.c:120: +i915_param_named_unsafe(force_reset_modeset_test, bool, 0400, "Force a modeset during gpu reset for testing (default:false). " -:115: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #115: FILE: drivers/gpu/drm/i915/i915_params.c:124: +i915_param_named_unsafe(invert_brightness, int, 0400, "Invert backlight brightness " -:124: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #124: FILE: drivers/gpu/drm/i915/i915_params.c:134: +i915_param_named(mmio_debug, int, 0400, "Enable the MMIO debug code for the first N failures (default: off). " -:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #137: FILE: drivers/gpu/drm/i915/i915_params.c:169: +i915_param_named_unsafe(enable_dp_mst, bool, 0400, "Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)"); -:146: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #146: FILE: drivers/gpu/drm/i915/i915_params.c:177: +i915_param_named(enable_dpcd_backlight, int, 0400, "Enable support for DPCD backlight control" total: 0 errors, 0 warnings, 13 checks, 115 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Move saturated workload detection back to the context
== Series Details == Series: series starting with [1/7] drm/i915: Move saturated workload detection back to the context URL : https://patchwork.freedesktop.org/series/77365/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/compiler.h:199:9: warning: context imbalance in 'engines_sample' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Move saturated workload detection back to the context
== Series Details ==
Series: series starting with [1/7] drm/i915: Move saturated workload detection
back to the context
URL : https://patchwork.freedesktop.org/series/77365/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a7577cd7f63b drm/i915: Move saturated workload detection back to the context
-:22: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#22:
References: 44d89409a12e ("drm/i915: Make the semaphore saturation mask global")
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 44d89409a12e ("drm/i915: Make
the semaphore saturation mask global")'
#22:
References: 44d89409a12e ("drm/i915: Make the semaphore saturation mask global")
total: 1 errors, 1 warnings, 0 checks, 68 lines checked
b869aac79c29 drm/i915/selftests: Add tests for timeslicing virtual engines
-:51: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#51: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:3632:
+
+}
total: 0 errors, 0 warnings, 1 checks, 218 lines checked
d4fa09cdb48e drm/i915/gt: Kick virtual siblings on timeslice out
0d70aed9a12c drm/i915/gt: Incorporate the virtual engine into timeslicing
d70a6bfd13b1 drm/i915/gt: Use virtual_engine during execlists_dequeue
802e652868f5 drm/i915/gt: Decouple inflight virtual engines
a839695e72b2 drm/i915/gt: Resubmit the virtual engine on schedule-out
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/7] drm/i915: Reverse preemph vs. voltage swing preference
On Fri, May 15, 2020 at 10:59:57PM +0300, Ville Syrjälä wrote:
> On Fri, May 15, 2020 at 12:18:22PM -0700, Manasi Navare wrote:
> > On Tue, May 12, 2020 at 08:41:43PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > The DP spec says:
> > > "When the combination of the requested pre-emphasis level and
> > > voltage swing exceeds the capability of a DPTX, the DPTX shall
> > > set the pre-emphasis level according to the request and use the
> > > highest voltage swing it can output with the given pre-emphasis level."
> > > and
> > > "When a DPTX reads a request beyond the limits of this Standard,
> > > the DPTX shall set the pre-emphasis level according to the request
> > > and set the highest voltage swing level it can output with the
> > > given pre-emphasis level. If a DPTX is requested for 9.5dB of
> > > pre-emphasis level (may be supported for a DPTX) and cannot support
> > > that level, it shall set the pre-emphasis level to the next
> > > highest level, 6dB."
> > >
> > > Ie. we should first validate the pre-emphasis, and then select
> > > the appropriate vswing for it.
> > >
> > > Signed-off-by: Ville Syrjälä
> >
> > So basically reverse the logic for selecting the vswing and pre emphasis
> >
> > > ---
> > > .../drm/i915/display/intel_dp_link_training.c | 32 +--
> > > 1 file changed, 16 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index 171d9e842fc0..573f93779449 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -34,18 +34,18 @@ intel_dp_dump_link_status(const u8
> > > link_status[DP_LINK_STATUS_SIZE])
> > > link_status[3], link_status[4], link_status[5]);
> > > }
> > >
> > > -static u8 dp_pre_emphasis_max(u8 voltage_swing)
> > > +static u8 dp_voltage_max(u8 preemph)
> > > {
> > > - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> > > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> > > - return DP_TRAIN_PRE_EMPH_LEVEL_3;
> > > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> > > - return DP_TRAIN_PRE_EMPH_LEVEL_2;
> > > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> > > - return DP_TRAIN_PRE_EMPH_LEVEL_1;
> > > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> > > + switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
> > > + case DP_TRAIN_PRE_EMPH_LEVEL_0:
> > > + return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> > > + case DP_TRAIN_PRE_EMPH_LEVEL_1:
> > > + return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> > > + case DP_TRAIN_PRE_EMPH_LEVEL_2:
> > > + return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
> > > + case DP_TRAIN_PRE_EMPH_LEVEL_3:
> > > default:
> > > - return DP_TRAIN_PRE_EMPH_LEVEL_0;
> > > + return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
> >
> > These vswing levels for that specific pre emph level comes from the Bspec
> > or from the DP spec? It wasnt clear to me how level3 of vswing was the max
> > for pre emphasis level 0 and all others?
>
> From DP 1.4 spec "Table 3-1: Allowed Vdiff_pre_pp and Pre-emphasis
> Combinations"
>
> Previosuly this was present in some semi-mangled way in each
> platform's max preeph calculation. Now we just have one canonical
> copy of it. Later on we could probably lift this into drm_dp_helper.
Okay great yes confirmed from that table and looks good to me
Reviewed-by: Manasi Navare
Manasi
>
> --
> Ville Syrjälä
> Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 0/4] drm/i915: Resolve device hotunplug issues
The idea is to revoke DMA mappings on driver remove in order to work around intel-iommu judging late unmapping on driver release after an open device is removed as bugs. That also resolves runtime power management warnings on late object removal. Janusz Krzysztofik (4): drm/i915: Drop user contexts on driver remove drm/i915: Release GT resources on driver remove drm/i915: Move GGTT cleanup from driver_release to _remove drm/i915: Move UC firmware cleanup from driver_release to _remove drivers/gpu/drm/i915/gem/i915_gem_context.c | 38 + drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 + drivers/gpu/drm/i915/gt/intel_ggtt.c| 13 --- drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++ drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + drivers/gpu/drm/i915/i915_drv.c | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 5 ++- 7 files changed, 57 insertions(+), 5 deletions(-) -- 2.21.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 3/4] drm/i915: Move GGTT cleanup from driver_release to _remove
GGTT including its scratch page is not cleaned up until driver release.
Since DMA mappings still exist before scratch page cleanup, unmapping
them on last device close after the driver has been already removed may
be judged by intel-iommu code as a bug and result in kernel panic.
Since we abort requests and block user access to hardware on device
removal, there seems not much sense in still keeping GGTT. Clean it up
on driver remove. However, skip GGTT address space cleanup as its
mutext may still be needed if there are objects to be freed. That
cleanup is always called on address space release after all.
[ 81.290284] [ cut here ]
[ 81.291602] kernel BUG at drivers/iommu/intel-iommu.c:3591!
[ 81.293558] invalid opcode: [#1] PREEMPT SMP
[ 81.294695] CPU: 0 PID: 207 Comm: core_hotunplug Tainted: G U
5.4.17 #2
[ 81.296579] Hardware name: Bochs Bochs, BIOS Bochs 01/01/2007
[ 81.297959] RIP: 0010:intel_unmap+0x200/0x230
[ 81.299015] Code: 00 e8 e4 45 c5 ff 85 c0 74 09 80 3d 2b 84 c0 00 00 74 19
65 ff 0d 78 9a b2 7e 0f 85 fa fe ff ff e8 95 57 b1 ff e9 f0 fe ff ff <0f> 0b e8
19 4c c5 ff 85 c0 75 de 48 c7 c2 48 d2 e1 81 be 57 00 00
[ 81.303425] RSP: 0018:c913fda0 EFLAGS: 00010246
[ 81.304683] RAX: RBX: 8882228dd0b0 RCX:
[ 81.306384] RDX: 1000 RSI: af801000 RDI: 8882228dd0b0
[ 81.308086] RBP: R08: R09:
[ 81.309788] R10: R11: R12: af801000
[ 81.311489] R13: 888223a0 R14: 1000 R15: 888223a0a2e8
[ 81.313191] FS: 7f5408e3c940() GS:88822860()
knlGS:
[ 81.315116] CS: 0010 DS: ES: CR0: 80050033
[ 81.316495] CR2: 01fc0048 CR3: 00022464a000 CR4: 06b0
[ 81.318196] Call Trace:
[ 81.318967] cleanup_scratch_page+0x44/0x80 [i915]
[ 81.320281] i915_ggtt_driver_release+0x15b/0x220 [i915]
[ 81.321717] i915_driver_release+0x33/0x90 [i915]
[ 81.322856] drm_release+0xbc/0xd0
[ 81.323691] __fput+0xcd/0x260
[ 81.324447] task_work_run+0x90/0xc0
[ 81.325323] do_syscall_64+0x3da/0x560
[ 81.326240] entry_SYSCALL_64_after_hwframe+0x49/0xbe
[ 81.327457] RIP: 0033:0x7f54096ecba3
[ 81.328332] Code: 00 00 f7 d8 64 89 02 48 c7 c0 ff ff ff ff eb bb 0f 1f 80
00 00 00 00 64 8b 04 25 18 00 00 00 85 c0 75 14 b8 03 00 00 00 0f 05 <48> 3d 00
f0 ff ff 77 45 c3 0f 1f 40 00 48 83 ec 18 89 7c 24 0c e8
[ 81.332741] RSP: 002b:7ffcc5165698 EFLAGS: 0246 ORIG_RAX:
0003
[ 81.334546] RAX: RBX: RCX: 7f54096ecba3
[ 81.336247] RDX: 005cc5d0 RSI: 0005 RDI: 0004
[ 81.337949] RBP: 0003 R08: 005b8014 R09: 0004
[ 81.339650] R10: 005cc650 R11: 0246 R12: 004022f0
[ 81.341352] R13: 7ffcc5165850 R14: R15:
[ 81.343059] Modules linked in: i915 mfd_core intel_gtt prime_numbers
[ 81.345015] ---[ end trace 010aae55e56f8998 ]---
Signed-off-by: Janusz Krzysztofik
drm/i915: Defer GGTT vm address space fini to vm release
Signed-off-by: Janusz Krzysztofik
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 13 +
drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
drivers/gpu/drm/i915/i915_drv.c | 2 ++
3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 66165b10256e..ff2b4f74149a 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -701,7 +701,6 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
ggtt->vm.cleanup(>vm);
mutex_unlock(>vm.mutex);
- i915_address_space_fini(>vm);
arch_phys_wc_del(ggtt->mtrr);
@@ -709,6 +708,15 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
io_mapping_fini(>iomap);
}
+void i915_ggtt_driver_remove(struct drm_i915_private *i915)
+{
+ struct i915_ggtt *ggtt = >ggtt;
+
+ fini_aliasing_ppgtt(ggtt);
+
+ ggtt_cleanup_hw(ggtt);
+}
+
/**
* i915_ggtt_driver_release - Clean up GGTT hardware initialization
* @i915: i915 device
@@ -718,10 +726,7 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
struct i915_ggtt *ggtt = >ggtt;
struct pagevec *pvec;
- fini_aliasing_ppgtt(ggtt);
-
intel_ggtt_fini_fences(ggtt);
- ggtt_cleanup_hw(ggtt);
pvec = >mm.wc_stash.pvec;
if (pvec->nr) {
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index d93ebdf3fa0e..f140ce5c171a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -501,6 +501,7 @@ int i915_ggtt_enable_hw(struct drm_i915_private *i915);
void i915_ggtt_enable_guc(struct
[Intel-gfx] [RFC PATCH 1/4] drm/i915: Drop user contexts on driver remove
Contexts associated with open device file descriptors together with
their assigned address spaces are now closed on device file close. On
address space closure its associated DMA mappings are revoked. If the
device is removed while being open, subsequent attempts to revoke
those mappings while closing the device file descriptor may may be
judged by intel-iommu code as a bug and result in kernel panic.
Since user contexts become useless after the device is no longer
available, drop them on device removal.
<4> [36.900985] [ cut here ]
<2> [36.901005] kernel BUG at drivers/iommu/intel-iommu.c:3717!
<4> [36.901105] invalid opcode: [#1] PREEMPT SMP NOPTI
<4> [36.901117] CPU: 0 PID: 39 Comm: kworker/u8:1 Tainted: G U W
5.7.0-rc5-CI-CI_DRM_8485+ #1
<4> [36.901133] Hardware name: Intel Corporation Elkhart Lake Embedded
Platform/ElkhartLake LPDDR4x T3 CRB, BIOS EHLSFWI1.R00.1484.A00.1911290833
11/29/2019
<4> [36.901250] Workqueue: i915 __i915_vm_release [i915]
<4> [36.901264] RIP: 0010:intel_unmap+0x1f5/0x230
<4> [36.901274] Code: 01 e8 9f bc a9 ff 85 c0 74 09 80 3d df 60 09 01 00 74 19
65 ff 0d 13 12 97 7e 0f 85 fc fe ff ff e8 82 b0 95 ff e9 f2 fe ff ff <0f> 0b e8
d4 bd a9 ff 85 c0 75 de 48 c7 c2 10 84 2c 82 be 54 00 00
<4> [36.901302] RSP: 0018:c91ebdc0 EFLAGS: 00010246
<4> [36.901313] RAX: RBX: 8882561dd000 RCX:
<4> [36.901324] RDX: 1000 RSI: ffd9c000 RDI:
888274c94000
<4> [36.901336] RBP: 888274c940b0 R08: R09:
0001
<4> [36.901348] R10: 0a25d812 R11: 112af2d4 R12:
888252c70200
<4> [36.901360] R13: ffd9c000 R14: 1000 R15:
8882561dd010
<4> [36.901372] FS: () GS:88827800()
knlGS:
<4> [36.901386] CS: 0010 DS: ES: CR0: 80050033
<4> [36.901396] CR2: 7f06def54950 CR3: 000255844000 CR4:
00340ef0
<4> [36.901408] Call Trace:
<4> [36.901418] ? process_one_work+0x1de/0x600
<4> [36.901494] cleanup_page_dma+0x37/0x70 [i915]
<4> [36.901573] free_pd+0x9/0x20 [i915]
<4> [36.901644] gen8_ppgtt_cleanup+0x59/0xc0 [i915]
<4> [36.901721] __i915_vm_release+0x14/0x30 [i915]
<4> [36.901733] process_one_work+0x268/0x600
<4> [36.901744] ? __schedule+0x307/0x8d0
<4> [36.901756] worker_thread+0x37/0x380
<4> [36.901766] ? process_one_work+0x600/0x600
<4> [36.901775] kthread+0x140/0x160
<4> [36.901783] ? kthread_park+0x80/0x80
<4> [36.901792] ret_from_fork+0x24/0x50
<4> [36.901804] Modules linked in: mei_hdcp i915 x86_pkg_temp_thermal coretemp
crct10dif_pclmul crc32_pclmul ghash_clmulni_intel ax88179_178a usbnet mii
mei_me mei prime_numbers intel_lpss_pci
<4> [36.901857] ---[ end trace 52d1b4d81f8d1ea7 ]---
Signed-off-by: Janusz Krzysztofik
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 38 +
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 2 ++
3 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 900ea8b7fc8f..0096a69fbfd3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -927,6 +927,44 @@ void i915_gem_driver_release__contexts(struct
drm_i915_private *i915)
rcu_barrier(); /* and flush the left over RCU frees */
}
+void i915_gem_driver_remove__contexts(struct drm_i915_private *i915)
+{
+ struct i915_gem_context *ctx, *cn;
+
+ list_for_each_entry_safe(ctx, cn, >gem.contexts.list, link) {
+ struct drm_i915_file_private *file_priv = ctx->file_priv;
+ struct i915_gem_context *entry;
+ unsigned long int id;
+
+ if (i915_gem_context_is_closed(ctx) || IS_ERR(file_priv))
+ continue;
+
+ xa_for_each(_priv->context_xa, id, entry) {
+ struct i915_address_space *vm;
+ unsigned long int idx;
+
+ if (entry != ctx)
+ continue;
+
+ xa_erase(_priv->context_xa, id);
+
+ if (id)
+ break;
+
+ xa_for_each(_priv->vm_xa, idx, vm) {
+ xa_erase(_priv->vm_xa, idx);
+ i915_vm_put(vm);
+ }
+
+ break;
+ }
+
+ context_close(ctx);
+ }
+
+ i915_gem_driver_release__contexts(i915);
+}
+
static int gem_context_register(struct i915_gem_context *ctx,
struct drm_i915_file_private *fpriv,
u32 *id)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 3702b2fb27ab..62808bea9239 100644
---
[Intel-gfx] [RFC PATCH 4/4] drm/i915: Move UC firmware cleanup from driver_release to _remove
UC firmware is stored in a GEM object. Clean it up on driver remove to avoid intel-iommu triggered kernel panic on late DMA unmapping or even an RPM related warning on object late removal in no IOMMU setups. <4> [93.335282] [ cut here ] <4> [93.335515] pm_runtime_get_sync() failed: -13 <4> [93.336056] WARNING: CPU: 6 PID: 200 at drivers/gpu/drm/i915/intel_runtime_pm.c:361 __intel_runtime_pm_get+0x4d/0x60 [i915] <4> [93.336104] Modules linked in: snd_hda_codec_hdmi mei_hdcp i915 x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel snd_hda_intel cdc_ether snd_intel_dspcfg usbnet snd_hda_codec mii snd_hwdep snd_hda_core e1000e snd_pcm ptp pps_core mei_me mei intel_lpss_pci prime_numbers <4> [93.336268] CPU: 6 PID: 200 Comm: kworker/u16:3 Tainted: G U 5.7.0-rc4-CI-Trybot_6405+ #1 <4> [93.336289] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake Y LPDDR4x T4 Crb, BIOS TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 <4> [93.336811] Workqueue: i915 __i915_gem_free_work [i915] <4> [93.337296] RIP: 0010:__intel_runtime_pm_get+0x4d/0x60 [i915] <4> [93.337332] Code: ff ff 48 89 df 5b 5d e9 a1 fa ff ff 80 3d 4b 7a 2e 00 00 75 e1 89 c6 48 c7 c7 a8 2d 40 a0 c6 05 39 7a 2e 00 01 e8 53 fc e9 e0 <0f> 0b eb c8 0f 1f 44 00 00 66 2e 0f 1f 84 00 00 00 00 00 41 57 41 <4> [93.337357] RSP: 0018:c9000144bdd8 EFLAGS: 00010282 <4> [93.337384] RAX: RBX: 88838ee5bc40 RCX: 0001 <4> [93.337409] RDX: 8001 RSI: 88839d264928 RDI: <4> [93.337440] RBP: 0001 R08: 88839d264928 R09: <4> [93.337467] R10: R11: R12: 88838ee5bc40 <4> [93.337493] R13: 0006 R14: 82769a30 R15: 88839376bab0 <4> [93.337515] FS: () GS:8883a410() knlGS: <4> [93.337542] CS: 0010 DS: ES: CR0: 80050033 <4> [93.337563] CR2: 55bc19b16ff8 CR3: 0003a11c4005 CR4: 00760ee0 <4> [93.337583] PKRU: 5554 <4> [93.337605] Call Trace: <4> [93.338148] i915_gem_object_release_mmap+0x23/0x70 [i915] <4> [93.338665] __i915_gem_free_objects.isra.21+0x10a/0x4b0 [i915] <4> [93.338741] process_one_work+0x268/0x600 <4> [93.338785] ? __schedule+0x307/0x8d0 <4> [93.338878] worker_thread+0x37/0x380 <4> [93.338929] ? process_one_work+0x600/0x600 <4> [93.338963] kthread+0x140/0x160 <4> [93.339006] ? kthread_park+0x80/0x80 <4> [93.339057] ret_from_fork+0x24/0x50 <4> [93.339181] irq event stamp: 204220 <4> [93.339219] hardirqs last enabled at (204219): [] console_unlock+0x4cd/0x5a0 <4> [93.339250] hardirqs last disabled at (204220): [] trace_hardirqs_off_thunk+0x1a/0x1c <4> [93.339277] softirqs last enabled at (204208): [] __do_softirq+0x395/0x49e <4> [93.339307] softirqs last disabled at (204197): [] irq_exit+0xba/0xc0 <4> [93.339330] ---[ end trace f066187622b8c484 ]--- Signed-off-by: Janusz Krzysztofik --- drivers/gpu/drm/i915/i915_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 87d3c4f5b6c6..f9d37c7e6d6f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1191,6 +1191,8 @@ void i915_gem_driver_remove(struct drm_i915_private *dev_priv) i915_gem_driver_remove__contexts(dev_priv); + intel_uc_cleanup_firmwares(_priv->gt.uc); + i915_gem_drain_freed_objects(dev_priv); } @@ -1202,7 +1204,6 @@ void i915_gem_driver_release(struct drm_i915_private *dev_priv) intel_wa_list_free(_priv->gt_wa_list); - intel_uc_cleanup_firmwares(_priv->gt.uc); i915_gem_cleanup_userptr(dev_priv); i915_gem_drain_freed_objects(dev_priv); -- 2.21.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 2/4] drm/i915: Release GT resources on driver remove
GT scratch page is now released and its DMA mappings revoked on driver release. If a device is removed while its file descriptor is still open, the driver is not released until last device file descriptor closure. In that case intel-iommu code may judge late DMA unmapping as a bug and kernel panic may occur. Since DMA mapped address space may be no longer usable after device removal, release GT resources including scratch page as well as a reference to its address space on driver remove. Implement that by just calling intel_gt_driver_release() on GT remove as that function has been already made safe to be called again on driver release even if already called before, e.g. on GEM initialization failure. <4> [39.201062] [ cut here ] <2> [39.201074] kernel BUG at drivers/iommu/intel-iommu.c:3717! <4> [39.201154] invalid opcode: [#1] PREEMPT SMP NOPTI <4> [39.201162] CPU: 6 PID: 7 Comm: kworker/u16:0 Tainted: G U W 5.7.0-rc5-CI-CI_DRM_8485+ #1 <4> [39.201172] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP, BIOS ICLSFWR1.R00.3175.A00.1904261428 04/26/2019 <4> [39.201243] Workqueue: i915 __i915_gem_free_work [i915] <4> [39.201252] RIP: 0010:intel_unmap+0x1f5/0x230 <4> [39.201260] Code: 01 e8 9f bc a9 ff 85 c0 74 09 80 3d df 60 09 01 00 74 19 65 ff 0d 13 12 97 7e 0f 85 fc fe ff ff e8 82 b0 95 ff e9 f2 fe ff ff <0f> 0b e8 d4 bd a9 ff 85 c0 75 de 48 c7 c2 10 84 2c 82 be 54 00 00 <4> [39.201278] RSP: 0018:c90dbc98 EFLAGS: 00010246 <4> [39.201285] RAX: RBX: RCX: ea0021d3 <4> [39.201293] RDX: 0005f000 RSI: fed0 RDI: 89eec000 <4> [39.201301] RBP: 89eec0b0 R08: R09: fffe <4> [39.201309] R10: 458139fc R11: f6c6d8b2 R12: 0025 <4> [39.201318] R13: fed0 R14: 0005f000 R15: 0025 <4> [39.201326] FS: () GS:9010() knlGS: <4> [39.201335] CS: 0010 DS: ES: CR0: 80050033 <4> [39.201342] CR2: 560f1308e148 CR3: 000881972002 CR4: 00760ee0 <4> [39.201350] PKRU: 5554 <4> [39.201355] Call Trace: <4> [39.201361] intel_unmap_sg+0x7b/0x180 <4> [39.201412] shmem_put_pages+0x43/0x250 [i915] <4> [39.201472] ? __i915_gem_object_unset_pages.part.12+0x11b/0x1d0 [i915] <4> [39.201531] ? __i915_gem_object_unset_pages.part.12+0x133/0x1d0 [i915] <4> [39.201590] __i915_gem_object_put_pages+0x81/0xc0 [i915] <4> [39.201646] __i915_gem_free_objects.isra.21+0x1a7/0x4b0 [i915] <4> [39.201658] process_one_work+0x268/0x600 <4> [39.201666] ? __schedule+0x307/0x8d0 <4> [39.201675] worker_thread+0x1d0/0x380 <4> [39.201682] ? process_one_work+0x600/0x600 <4> [39.201689] kthread+0x140/0x160 <4> [39.201695] ? kthread_park+0x80/0x80 <4> [39.201703] ret_from_fork+0x24/0x50 <4> [39.201712] Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg snd_hda_codec e1000e ax88179_178a usbnet snd_hwdep mii snd_hda_core ghash_clmulni_intel snd_pcm ptp pps_core mei_me mei intel_lpss_pci prime_numbers <4> [39.201764] ---[ end trace f3ec1bae3de04509 ]--- Signed-off-by: Janusz Krzysztofik --- drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index f069551e412f..5771e80e85a6 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -599,6 +599,8 @@ void intel_gt_driver_remove(struct intel_gt *gt) intel_uc_driver_remove(>uc); intel_engines_release(gt); + + intel_gt_driver_release(gt); } void intel_gt_driver_unregister(struct intel_gt *gt) -- 2.21.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Measure dispatch latency (rev8)
== Series Details == Series: drm/i915/selftests: Measure dispatch latency (rev8) URL : https://patchwork.freedesktop.org/series/77308/ State : success == Summary == CI Bug Log - changes from CI_DRM_8495 -> Patchwork_17695 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/index.html Known issues Here are the changes found in Patchwork_17695 that come from known issues: ### IGT changes ### Possible fixes * igt@debugfs_test@read_all_entries: - fi-bsw-nick:[INCOMPLETE][1] ([i915#1250] / [i915#1436]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/fi-bsw-nick/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/fi-bsw-nick/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@execlists: - fi-skl-lmem:[INCOMPLETE][3] ([i915#1874]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/fi-skl-lmem/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/fi-skl-lmem/igt@i915_selftest@l...@execlists.html - fi-whl-u: [INCOMPLETE][5] ([i915#656]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/fi-whl-u/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/fi-whl-u/igt@i915_selftest@l...@execlists.html - fi-kbl-guc: [INCOMPLETE][7] ([i915#656]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/fi-kbl-guc/igt@i915_selftest@l...@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/fi-kbl-guc/igt@i915_selftest@l...@execlists.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][9] ([fdo#109271]) -> [FAIL][10] ([i915#62]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8495/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1874]: https://gitlab.freedesktop.org/drm/intel/issues/1874 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (52 -> 44) -- Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8495 -> Patchwork_17695 CI-20190529: 20190529 CI_DRM_8495: 695b7d214a475060bb448c2609e4184fc450d69a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5659: 66ab5e42811fee3dea8c21ab29e70e323a0650de @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17695: 2633bb73f44c35def35771444a87a1cc99411d8a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2633bb73f44c drm/i915/selftests: Measure dispatch latency == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17695/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Check for an initial-breadcrumb in wait_for_submit()
When we look at i915_request_is_started() we must be careful in case we are using a request that does not have the initial-breadcrumb and instead the is-started is being compared against the end of the previous request. This will make wait_for_submit() declare that a request has been already submitted too early. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index d83ee0d09002..cd276b3badb2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -75,7 +75,7 @@ static bool is_active(struct i915_request *rq) if (i915_request_on_hold(rq)) return true; - if (i915_request_started(rq)) + if (i915_request_has_initial_breadcrumb(rq) && i915_request_started(rq)) return true; return false; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gvt: Use ARRAY_SIZE for vgpu_types
Prefer ARRAY_SIZE instead of using sizeof Fixes coccicheck warning: Use ARRAY_SIZE Signed-off-by: Aishwarya Ramakrishnan --- drivers/gpu/drm/i915/gvt/vgpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 1d5ff88078bd..7d361623ff67 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -124,7 +124,7 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) */ low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; - num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]); + num_types = ARRAY_SIZE(vgpu_types); gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type), GFP_KERNEL); -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Fix dbuf slice mask when turning off all the pipes
On Mon, May 18, 2020 at 02:14:15PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2020-05-18 13:13:54)
> > From: Ville Syrjälä
> >
> > The current dbuf slice computation only happens when there are
> > active pipes. If we are turning off all the pipes we just leave
> > the dbuf slice mask at it's previous value, which may be something
> > other that BIT(S1). If runtime PM will kick in it will however
> > turn off everything but S1. Then on the next atomic commit (if
> > the new dbuf slice mask matches the stale value we left behind)
> > the code will not turn on the other slices we now need. This will
> > lead to underruns as the planes are trying to use a dbuf slice
> > that's not powered up.
> >
> > To work around let's just just explicitly set the dbuf slice mask
> > to BIT(S1) when we are turning off all the pipes. Really the code
> > should just calculate this stuff the same way regardless whether
> > the pipes are on or off, but we're not quite there yet (need a
> > bit more work on the dbuf state for that).
> >
> > v2: Let's not put the fix into dead code
> >
> > Cc: Stanislav Lisovskiy
> > Acked-by: Chris Wilson #v1
> Acked-by: Chris Wilson
> > Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
> > Signed-off-by: Ville Syrjälä
> -Chris
v2 seems to have done the trick. CI gave up on the reverts anyway so
let's go with this one then. Pushed along with Chris's smatch fix.
Apologies for the massive cockup.
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix dbuf slice mask when turning off all the pipes (rev2)
== Series Details == Series: drm/i915: Fix dbuf slice mask when turning off all the pipes (rev2) URL : https://patchwork.freedesktop.org/series/77322/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8494_full -> Patchwork_17690_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17690_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17690_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17690_full: ### IGT changes ### Possible regressions * igt@kms_panel_fitting@atomic-fastset: - shard-tglb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb2/igt@kms_panel_fitt...@atomic-fastset.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb5/igt@kms_panel_fitt...@atomic-fastset.html Warnings * igt@i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][3] ([i915#668]) -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb7/igt@i915_pm...@dc6-psr.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-tglb1/igt@i915_pm...@dc6-psr.html * igt@kms_panel_fitting@atomic-fastset: - shard-iclb: [FAIL][5] ([i915#1757]) -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb6/igt@kms_panel_fitt...@atomic-fastset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-iclb1/igt@kms_panel_fitt...@atomic-fastset.html Known issues Here are the changes found in Patchwork_17690_full that come from known issues: ### IGT changes ### Issues hit * igt@gen9_exec_parse@allowed-all: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / [i915#716]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl3/igt@gen9_exec_pa...@allowed-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-kbl7/igt@gen9_exec_pa...@allowed-all.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl6/igt@i915_susp...@debugfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-apl1/igt@i915_susp...@debugfs-reader.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl1/igt@kms_cursor_...@pipe-a-cursor-128x128-offscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-128x128-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#300]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl8/igt@kms_frontbuffer_track...@fbc-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-apl1/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-kbl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html Possible fixes
[Intel-gfx] [PATCH][next] drm/i915: fix incorrect return of an error status
From: Colin Ian King
Currently when a call to intel_atomic_get_dbuf_state fails the
error value being returns is a potentially uninitialized value
in variable ret. Fix this by returning the error value of
new_dbuf_state.
Addresses-Coverity: ("Uninitialized scalar value")
Fixes: 3cf43cdc63fb ("drm/i915: Introduce proper dbuf state")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a21e36ed1a77..762a5184fc69 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5917,7 +5917,7 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state
*state)
new_dbuf_state = intel_atomic_get_dbuf_state(state);
if (IS_ERR(new_dbuf_state))
- return ret;
+ return PTR_ERR(new_dbuf_state);
old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
--
2.25.1
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[Intel-gfx] [PATCH 2/3] drm/i915/params: fix i915.fake_lmem_start module param sysfs permissions
fake_lmem_start does not need to be mutable via module param sysfs. It's
only used during driver probe.
Fixes: 1629224324b6 ("drm/i915/lmem: add the fake lmem region")
Cc: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_params.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index add00ec1f787..a3dde770226d 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -173,7 +173,7 @@ i915_param_named(enable_gvt, bool, 0400,
#endif
#if IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)
-i915_param_named_unsafe(fake_lmem_start, ulong, 0600,
+i915_param_named_unsafe(fake_lmem_start, ulong, 0400,
"Fake LMEM start offset (default: 0)");
#endif
--
2.20.1
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[Intel-gfx] [PATCH 3/3] drm/i915/params: prevent changing module params runtime
Only support runtime changes through the debugfs.
i915.verbose_state_checks remains an exception, and is not exposed via
debugfs.
This depends on IGT having been updated to use the debugfs for modifying
the parameters.
Cc: Juha-Pekka Heikkilä
Cc: Venkata Sandeep Dhanalakota
Reviewed-by: Juha-Pekka Heikkila
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_params.c | 38 +++---
1 file changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index a3dde770226d..ace44ad7e6df 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -40,6 +40,15 @@ struct i915_params i915_modparams __read_mostly = {
#undef MEMBER
};
+/*
+ * Note: As a rule, keep module parameter sysfs permissions read-only
+ * 0400. Runtime changes are only supported through i915 debugfs.
+ *
+ * For any exceptions requiring write access and runtime changes through module
+ * parameter sysfs, prevent debugfs file creation by setting the parameter's
+ * debugfs mode to 0.
+ */
+
i915_param_named(modeset, int, 0400,
"Use kernel modesetting [KMS] (0=disable, "
"1=on, -1=force vga console preference [default])");
@@ -49,7 +58,7 @@ i915_param_named_unsafe(enable_dc, int, 0400,
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
-i915_param_named_unsafe(enable_fbc, int, 0600,
+i915_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
@@ -57,7 +66,7 @@ i915_param_named_unsafe(lvds_channel_mode, int, 0400,
"Specify LVDS channel mode "
"(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
-i915_param_named_unsafe(panel_use_ssc, int, 0600,
+i915_param_named_unsafe(panel_use_ssc, int, 0400,
"Use Spread Spectrum Clock with panels [LVDS/eDP] "
"(default: auto from VBT)");
@@ -65,25 +74,25 @@ i915_param_named_unsafe(vbt_sdvo_panel_type, int, 0400,
"Override/Ignore selection of SDVO panel mode in the VBT "
"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
-i915_param_named_unsafe(reset, int, 0600,
+i915_param_named_unsafe(reset, int, 0400,
"Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset
[default])");
i915_param_named_unsafe(vbt_firmware, charp, 0400,
"Load VBT from specified file under /lib/firmware");
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
-i915_param_named(error_capture, bool, 0600,
+i915_param_named(error_capture, bool, 0400,
"Record the GPU state following a hang. "
"This information in /sys/class/drm/card/error is vital for "
"triaging and debugging hangs.");
#endif
-i915_param_named_unsafe(enable_hangcheck, bool, 0600,
+i915_param_named_unsafe(enable_hangcheck, bool, 0400,
"Periodically check GPU activity for detecting hangs. "
"WARNING: Disabling this can cause system wide hangs. "
"(default: true)");
-i915_param_named_unsafe(enable_psr, int, 0600,
+i915_param_named_unsafe(enable_psr, int, 0400,
"Enable PSR "
"(0=disabled, 1=enabled) "
"Default: -1 (use per-chip default)");
@@ -96,22 +105,22 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
"Disable display power wells when possible "
"(-1=auto [default], 0=power wells always on, 1=power wells disabled
when possible)");
-i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
+i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: true)");
-i915_param_named(fastboot, int, 0600,
+i915_param_named(fastboot, int, 0400,
"Try to skip unnecessary mode sets at boot time "
"(0=disabled, 1=enabled) "
"Default: -1 (use per-chip default)");
-i915_param_named_unsafe(load_detect_test, bool, 0600,
+i915_param_named_unsafe(load_detect_test, bool, 0400,
"Force-enable the VGA load detect code for testing (default:false). "
"For developers only.");
-i915_param_named_unsafe(force_reset_modeset_test, bool, 0600,
+i915_param_named_unsafe(force_reset_modeset_test, bool, 0400,
"Force a modeset during gpu reset for testing (default:false). "
"For developers only.");
-i915_param_named_unsafe(invert_brightness, int, 0600,
+i915_param_named_unsafe(invert_brightness, int, 0400,
"Invert backlight brightness "
"(-1 force normal, 0 machine defaults, 1 force inversion), please "
"report PCI device ID, subsystem vendor and subsystem device ID "
@@ -121,10 +130,11 @@ i915_param_named_unsafe(invert_brightness, int, 0600,
i915_param_named(disable_display, bool, 0400,
"Disable display (default: false)");
-i915_param_named(mmio_debug, int, 0600,
+i915_param_named(mmio_debug, int, 0400,
"Enable the MMIO debug code for the first N
[Intel-gfx] [PATCH 1/3] drm/i915/params: don't expose inject_probe_failure in debugfs
The parameter only makes sense as a module parameter only.
Fixes: c43c5a8818d4 ("drm/i915/params: add i915 parameters to debugfs")
Cc: Juha-Pekka Heikkilä
Cc: Venkata Sandeep Dhanalakota
Reviewed-by: Juha-Pekka Heikkila
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 45323732f099..4f21bfffbf0e 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -64,7 +64,7 @@ struct drm_printer;
param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
param(int, edp_vswing, 0, 0400) \
param(unsigned int, reset, 3, 0600) \
- param(unsigned int, inject_probe_failure, 0, 0600) \
+ param(unsigned int, inject_probe_failure, 0, 0) \
param(int, fastboot, -1, 0600) \
param(int, enable_dpcd_backlight, -1, 0600) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
--
2.20.1
___
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[Intel-gfx] drm/i915: device params part 1
This is the first 3 patches of [1], because apparently patch 4 breaks the world. I've yet to pinpoint the issue, but these could move forward in the meanwhile. BR, Jani. [1] https://patchwork.freedesktop.org/series/77272/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/7] drm/i915/gt: Kick virtual siblings on timeslice out
If we decide to timeslice out the current virtual request, we will unsubmit it while it is still busy (ve->context.inflight == sibling[0]). If the virtual tasklet and then the other sibling tasklets run before we completely schedule out the active virtual request for the preemption, those other tasklets will see that the virtul request is still inflight on sibling[0] and leave it be. Therefore when we finally schedule-out the virtual request and if we see that we have passed it back to the virtual engine, reschedule the virtual tasklet so that it may be resubmitted on any of the siblings. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 80885ba87db5..05486e801a63 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1402,7 +1402,7 @@ static void kick_siblings(struct i915_request *rq, struct intel_context *ce) struct virtual_engine *ve = container_of(ce, typeof(*ve), context); struct i915_request *next = READ_ONCE(ve->request); - if (next && next->execution_mask & ~rq->execution_mask) + if (next == rq || (next && next->execution_mask & ~rq->execution_mask)) tasklet_hi_schedule(>base.execlists.tasklet); } -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/7] drm/i915/gt: Incorporate the virtual engine into timeslicing
It was quite the oversight to only factor in the normal queue to decide
the timeslicing switch priority. By leaving out the next virtual request
from the priority decision, we would not timeslice the current engine if
there was an available virtual request.
Testcase: igt/gem_exec_balancer/sliced
Fixes: 3df2deed411e ("drm/i915/execlists: Enable timeslice on partial virtual
engine dequeue")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 30 +++--
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 05486e801a63..8524c5f3a329 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1895,7 +1895,8 @@ static void defer_active(struct intel_engine_cs *engine)
static bool
need_timeslice(const struct intel_engine_cs *engine,
- const struct i915_request *rq)
+ const struct i915_request *rq,
+ const struct rb_node *rb)
{
int hint;
@@ -1903,6 +1904,24 @@ need_timeslice(const struct intel_engine_cs *engine,
return false;
hint = engine->execlists.queue_priority_hint;
+
+ if (rb) {
+ const struct virtual_engine *ve =
+ rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
+ const struct intel_engine_cs *inflight =
+ intel_context_inflight(>context);
+
+ if (!inflight || inflight == engine) {
+ struct i915_request *next;
+
+ rcu_read_lock();
+ next = READ_ONCE(ve->request);
+ if (next)
+ hint = max(hint, rq_prio(next));
+ rcu_read_unlock();
+ }
+ }
+
if (!list_is_last(>sched.link, >active.requests))
hint = max(hint, rq_prio(list_next_entry(rq, sched.link)));
@@ -1977,10 +1996,9 @@ static void set_timeslice(struct intel_engine_cs *engine)
set_timer_ms(>execlists.timer, duration);
}
-static void start_timeslice(struct intel_engine_cs *engine)
+static void start_timeslice(struct intel_engine_cs *engine, int prio)
{
struct intel_engine_execlists *execlists = >execlists;
- const int prio = queue_prio(execlists);
unsigned long duration;
if (!intel_engine_has_timeslices(engine))
@@ -2140,7 +2158,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
__unwind_incomplete_requests(engine);
last = NULL;
- } else if (need_timeslice(engine, last) &&
+ } else if (need_timeslice(engine, last, rb) &&
timeslice_expired(execlists, last)) {
if (i915_request_completed(last)) {
tasklet_hi_schedule(>tasklet);
@@ -2188,7 +2206,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* Even if ELSP[1] is occupied and not worthy
* of timeslices, our queue might be.
*/
- start_timeslice(engine);
+ start_timeslice(engine, queue_prio(execlists));
return;
}
}
@@ -2223,7 +2241,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
if (last && !can_merge_rq(last, rq)) {
spin_unlock(>base.active.lock);
- start_timeslice(engine);
+ start_timeslice(engine, rq_prio(rq));
return; /* leave this for another sibling */
}
--
2.20.1
___
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[Intel-gfx] [PATCH 7/7] drm/i915/gt: Resubmit the virtual engine on schedule-out
Having recognised that we do not change the sibling until we schedule
out, we can then defer the decision to resubmit the virtual engine from
the unwind of the active queue to scheduling out of the virtual context.
By keeping the unwind order intact on the local engine, we can preserve
data dependency ordering while doing a preempt-to-busy pass until we
have determined the new ELSP. This means that if we try to timeslice
between a virtual engine and a data-dependent ordinary request, the pair
will maintain their relative ordering and we will avoid the
resubmission, cancelling the timeslicing until further change.
The dilemma though is that we then may end up in a situation where the
'demotion' of the virtual request to an ordinary request in the engine
queue results in filling the ELSP[] with virtual requests instead of
spreading the load across the engines. To compensate for this, we mark
each virtual request and refuse to resubmit a virtual request in the
secondary ELSP slots, thus forcing subsequent virtual requests to be
scheduled out after timeslicing. By delaying the decision until we
schedule out, we will avoid unnecessary resubmission.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 99 --
drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +-
2 files changed, 62 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3bc49f1b835f..4123020b8a29 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1114,46 +1114,17 @@ __unwind_incomplete_requests(struct intel_engine_cs
*engine)
__i915_request_unsubmit(rq);
- /*
-* Push the request back into the queue for later resubmission.
-* If this request is not native to this physical engine (i.e.
-* it came from a virtual source), push it back onto the virtual
-* engine so that it can be moved across onto another physical
-* engine as load dictates.
-*/
- if (likely(rq->execution_mask == engine->mask)) {
- GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
- if (rq_prio(rq) != prio) {
- prio = rq_prio(rq);
- pl = i915_sched_lookup_priolist(engine, prio);
- }
-
GEM_BUG_ON(RB_EMPTY_ROOT(>execlists.queue.rb_root));
-
- list_move(>sched.link, pl);
- set_bit(I915_FENCE_FLAG_PQUEUE, >fence.flags);
+ GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
+ if (rq_prio(rq) != prio) {
+ prio = rq_prio(rq);
+ pl = i915_sched_lookup_priolist(engine, prio);
+ }
+ GEM_BUG_ON(RB_EMPTY_ROOT(>execlists.queue.rb_root));
- active = rq;
- } else {
- struct intel_engine_cs *owner = rq->context->engine;
+ list_move(>sched.link, pl);
+ set_bit(I915_FENCE_FLAG_PQUEUE, >fence.flags);
- /*
-* Decouple the virtual breadcrumb before moving it
-* back to the virtual engine -- we don't want the
-* request to complete in the background and try
-* and cancel the breadcrumb on the virtual engine
-* (instead of the old engine where it is linked)!
-*/
- if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
->fence.flags)) {
- spin_lock_nested(>lock,
-SINGLE_DEPTH_NESTING);
- i915_request_cancel_breadcrumb(rq);
- spin_unlock(>lock);
- }
- WRITE_ONCE(rq->engine, owner);
- owner->submit_request(rq);
- active = NULL;
- }
+ active = rq;
}
return active;
@@ -1395,12 +1366,41 @@ execlists_schedule_in(struct i915_request *rq, int idx)
return i915_request_get(rq);
}
+static void
+resubmit_virtual_request(struct i915_request *rq, struct virtual_engine *ve)
+{
+ /*
+* Decouple the virtual breadcrumb before moving it back to the virtual
+* engine -- we don't want the request to complete in the background
+* and then try and cancel the breadcrumb on the virtual engine
+* (instead of the old engine where it is linked)!
+*/
+ if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags)) {
+ spin_lock_nested(>lock, SINGLE_DEPTH_NESTING);
+
[Intel-gfx] [PATCH 5/7] drm/i915/gt: Use virtual_engine during execlists_dequeue
Rather than going back and forth between the rb_node entry and the
virtual_engine type, store the ve local and reuse it. As the
container_of conversion from rb_node to virtual_engine requires a
variable offset, performing that conversion just once shaves off a bit
of code.
v2: Keep a single virtual engine lookup, for typical use.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 217 +---
1 file changed, 104 insertions(+), 113 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 8524c5f3a329..ea7e86e6ef82 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -451,7 +451,7 @@ static int queue_prio(const struct intel_engine_execlists
*execlists)
static inline bool need_preempt(const struct intel_engine_cs *engine,
const struct i915_request *rq,
- struct rb_node *rb)
+ struct virtual_engine *ve)
{
int last_prio;
@@ -488,9 +488,7 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
rq_prio(list_next_entry(rq, sched.link)) > last_prio)
return true;
- if (rb) {
- struct virtual_engine *ve =
- rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
+ if (ve) {
bool preempt = false;
if (engine == ve->siblings[0]) { /* only preempt one sibling */
@@ -1812,6 +1810,35 @@ static bool virtual_matches(const struct virtual_engine
*ve,
return true;
}
+static struct virtual_engine *
+first_virtual_engine(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlists *el = >execlists;
+ struct rb_node *rb = rb_first_cached(>virtual);
+
+ while (rb) {
+ struct virtual_engine *ve =
+ rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
+ struct i915_request *rq = READ_ONCE(ve->request);
+
+ if (!rq) { /* lazily cleanup after another engine handled rq */
+ rb_erase_cached(rb, >virtual);
+ RB_CLEAR_NODE(rb);
+ rb = rb_first_cached(>virtual);
+ continue;
+ }
+
+ if (!virtual_matches(ve, rq, engine)) {
+ rb = rb_next(rb);
+ continue;
+ }
+
+ return ve;
+ }
+
+ return NULL;
+}
+
static void virtual_xfer_breadcrumbs(struct virtual_engine *ve)
{
/*
@@ -1896,7 +1923,7 @@ static void defer_active(struct intel_engine_cs *engine)
static bool
need_timeslice(const struct intel_engine_cs *engine,
const struct i915_request *rq,
- const struct rb_node *rb)
+ struct virtual_engine *ve)
{
int hint;
@@ -1905,9 +1932,7 @@ need_timeslice(const struct intel_engine_cs *engine,
hint = engine->execlists.queue_priority_hint;
- if (rb) {
- const struct virtual_engine *ve =
- rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
+ if (ve) {
const struct intel_engine_cs *inflight =
intel_context_inflight(>context);
@@ -2057,7 +2082,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
struct i915_request ** const last_port = port + execlists->port_mask;
- struct i915_request * const *active;
+ struct i915_request * const *active = READ_ONCE(execlists->active);
+ struct virtual_engine *ve = first_virtual_engine(engine);
struct i915_request *last;
struct rb_node *rb;
bool submit = false;
@@ -2084,26 +2110,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* and context switches) submission.
*/
- for (rb = rb_first_cached(>virtual); rb; ) {
- struct virtual_engine *ve =
- rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
- struct i915_request *rq = READ_ONCE(ve->request);
-
- if (!rq) { /* lazily cleanup after another engine handled rq */
- rb_erase_cached(rb, >virtual);
- RB_CLEAR_NODE(rb);
- rb = rb_first_cached(>virtual);
- continue;
- }
-
- if (!virtual_matches(ve, rq, engine)) {
- rb = rb_next(rb);
- continue;
- }
-
- break;
- }
-
/*
* If the queue is higher priority than the last
* request in the currently active context, submit afresh.
@@ -2111,10 +2117,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
[Intel-gfx] [PATCH 2/7] drm/i915/selftests: Add tests for timeslicing virtual engines
Make sure that we can execute a virtual request on an already busy
engine, and conversely that we can execute a normal request if the
engines are already fully occupied by virtual requests.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 188 -
1 file changed, 185 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 94854a467e66..370630553871 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3600,9 +3600,11 @@ static int nop_virtual_engine(struct intel_gt *gt,
return err;
}
-static unsigned int select_siblings(struct intel_gt *gt,
- unsigned int class,
- struct intel_engine_cs **siblings)
+static unsigned int
+__select_siblings(struct intel_gt *gt,
+ unsigned int class,
+ struct intel_engine_cs **siblings,
+ bool (*filter)(const struct intel_engine_cs *))
{
unsigned int n = 0;
unsigned int inst;
@@ -3611,12 +3613,24 @@ static unsigned int select_siblings(struct intel_gt *gt,
if (!gt->engine_class[class][inst])
continue;
+ if (filter && !filter(gt->engine_class[class][inst]))
+ continue;
+
siblings[n++] = gt->engine_class[class][inst];
}
return n;
}
+static unsigned int
+select_siblings(struct intel_gt *gt,
+ unsigned int class,
+ struct intel_engine_cs **siblings)
+{
+ return __select_siblings(gt, class, siblings, NULL);
+
+}
+
static int live_virtual_engine(void *arg)
{
struct intel_gt *gt = arg;
@@ -3771,6 +3785,173 @@ static int live_virtual_mask(void *arg)
return 0;
}
+static int slicein_virtual_engine(struct intel_gt *gt,
+ struct intel_engine_cs **siblings,
+ unsigned int nsibling)
+{
+ struct intel_context *ce;
+ struct i915_request *rq;
+ struct igt_spinner spin;
+ unsigned int n;
+ int err = 0;
+
+ /*
+* Virtual requests must take part in timeslicing on the target engines.
+*/
+
+ if (igt_spinner_init(, gt))
+ return -ENOMEM;
+
+ for (n = 0; n < nsibling; n++) {
+ ce = intel_context_create(siblings[n]);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out;
+ }
+
+ rq = igt_spinner_create_request(, ce, MI_ARB_CHECK);
+ intel_context_put(ce);
+
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out;
+ }
+
+ i915_request_add(rq);
+ }
+
+ ce = intel_execlists_create_virtual(siblings, nsibling);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out;
+ }
+
+ rq = intel_context_create_request(ce);
+ intel_context_put(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 10) < 0) {
+ GEM_TRACE_ERR("%s(%s) failed to slice in virtual request\n",
+ __func__, rq->engine->name);
+ GEM_TRACE_DUMP();
+ intel_gt_set_wedged(gt);
+ err = -EIO;
+ }
+ i915_request_put(rq);
+
+out:
+ igt_spinner_end();
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+ igt_spinner_fini();
+ return err;
+}
+
+static int sliceout_virtual_engine(struct intel_gt *gt,
+ struct intel_engine_cs **siblings,
+ unsigned int nsibling)
+{
+ struct intel_context *ce;
+ struct i915_request *rq;
+ struct igt_spinner spin;
+ unsigned int n;
+ int err = 0;
+
+ /*
+* Virtual requests must allow others a fair timeslice.
+*/
+
+ if (igt_spinner_init(, gt))
+ return -ENOMEM;
+
+ for (n = 0; n <= nsibling; n++) { /* oversubscribed */
+ ce = intel_execlists_create_virtual(siblings, nsibling);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out;
+ }
+
+ rq = igt_spinner_create_request(, ce, MI_ARB_CHECK);
+ intel_context_put(ce);
+
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out;
+ }
+
+ i915_request_add(rq);
+ }
+
+ for (n = 0; !err && n < nsibling; n++) {
+ ce = intel_context_create(siblings[n]);
+ if (IS_ERR(ce)) {
+
[Intel-gfx] [PATCH 1/7] drm/i915: Move saturated workload detection back to the context
When we introduced the saturated workload detection to tell us to back
off from semaphore usage [semaphores have a noticeable impact on
contended bus cycles with the CPU for some heavy workloads], we first
introduced it as a per-context tracker. This allows individual contexts
to try and optimise their own usage, but we found that with the local
tracking and the no-semaphore boosting, the first context to disable
semaphores got a massive priority boost and so would starve the rest and
all new contexts (as they started with semaphores enabled and lower
priority). Hence we moved the saturated workload detection to the
engine, and a consequence had to disable semaphores on virtual engines.
Now that we do not have semaphore priority boosting, we can move the
tracking back to the context and virtual engines can now utilise the
faster inter-engine synchronisation.
References: 44d89409a12e ("drm/i915: Make the semaphore saturation mask global")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_context.c | 1 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 --
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 --
drivers/gpu/drm/i915/gt/intel_lrc.c | 15 ---
drivers/gpu/drm/i915/i915_request.c | 4 ++--
6 files changed, 5 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index e4aece20bc80..762a251d553b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -268,6 +268,7 @@ static int __intel_context_active(struct i915_active
*active)
if (err)
goto err_timeline;
+ ce->saturated = 0;
return 0;
err_timeline:
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 4954b0df4864..aed26d93c2ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -78,6 +78,8 @@ struct intel_context {
} lrc;
u32 tag; /* cookie passed to HW to track this context on submission */
+ intel_engine_mask_t saturated; /* submitting semaphores too late? */
+
/* Time on GPU as tracked by the hw. */
struct {
struct ewma_runtime avg;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index d0a1078ef632..6d7fdba5adef 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -229,8 +229,6 @@ static int __engine_park(struct intel_wakeref *wf)
struct intel_engine_cs *engine =
container_of(wf, typeof(*engine), wakeref);
- engine->saturated = 0;
-
/*
* If one and only one request is completed between pm events,
* we know that we are inside the kernel context and it is
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 2b6cdf47d428..c443b6bb884b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -332,8 +332,6 @@ struct intel_engine_cs {
struct intel_context *kernel_context; /* pinned */
- intel_engine_mask_t saturated; /* submitting semaphores too late? */
-
struct {
struct delayed_work work;
struct i915_request *systole;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d7ef3f8640d2..80885ba87db5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -5630,21 +5630,6 @@ intel_execlists_create_virtual(struct intel_engine_cs
**siblings,
ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
ve->base.uabi_instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
- /*
-* The decision on whether to submit a request using semaphores
-* depends on the saturated state of the engine. We only compute
-* this during HW submission of the request, and we need for this
-* state to be globally applied to all requests being submitted
-* to this engine. Virtual engines encompass more than one physical
-* engine and so we cannot accurately tell in advance if one of those
-* engines is already saturated and so cannot afford to use a semaphore
-* and be pessimized in priority for doing so -- if we are the only
-* context using semaphores after all other clients have stopped, we
-* will be starved on the saturated system. Such a global switch for
-* semaphores is less than ideal, but alas is the current compromise.
-*/
- ve->base.saturated = ALL_ENGINES;
-
snprintf(ve->base.name, sizeof(ve->base.name), "virtual");
intel_engine_init_active(>base, ENGINE_VIRTUAL);
diff --git
[Intel-gfx] [PATCH 6/7] drm/i915/gt: Decouple inflight virtual engines
Once a virtual engine has been bound to a sibling, it will remain bound
until we finally schedule out the last active request. We can not rebind
the context to a new sibling while it is inflight as the context save
will conflict, hence we wait. As we cannot then use any other sibliing
while the context is inflight, only kick the bound sibling while it
inflight and upon scheduling out the kick the rest (so that we can swap
engines on timeslicing if the previously bound engine becomes
oversubscribed).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 30 +
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index ea7e86e6ef82..3bc49f1b835f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1398,9 +1398,8 @@ execlists_schedule_in(struct i915_request *rq, int idx)
static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
{
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
- struct i915_request *next = READ_ONCE(ve->request);
- if (next == rq || (next && next->execution_mask & ~rq->execution_mask))
+ if (READ_ONCE(ve->request))
tasklet_hi_schedule(>base.execlists.tasklet);
}
@@ -1821,18 +1820,14 @@ first_virtual_engine(struct intel_engine_cs *engine)
rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
struct i915_request *rq = READ_ONCE(ve->request);
- if (!rq) { /* lazily cleanup after another engine handled rq */
+ /* lazily cleanup after another engine handled rq */
+ if (!rq || !virtual_matches(ve, rq, engine)) {
rb_erase_cached(rb, >virtual);
RB_CLEAR_NODE(rb);
rb = rb_first_cached(>virtual);
continue;
}
- if (!virtual_matches(ve, rq, engine)) {
- rb = rb_next(rb);
- continue;
- }
-
return ve;
}
@@ -5468,7 +5463,6 @@ static void virtual_submission_tasklet(unsigned long data)
if (unlikely(!mask))
return;
- local_irq_disable();
for (n = 0; n < ve->num_siblings; n++) {
struct intel_engine_cs *sibling = READ_ONCE(ve->siblings[n]);
struct ve_node * const node = >nodes[sibling->id];
@@ -5478,20 +5472,19 @@ static void virtual_submission_tasklet(unsigned long
data)
if (!READ_ONCE(ve->request))
break; /* already handled by a sibling's tasklet */
+ spin_lock_irq(>active.lock);
+
if (unlikely(!(mask & sibling->mask))) {
if (!RB_EMPTY_NODE(>rb)) {
- spin_lock(>active.lock);
rb_erase_cached(>rb,
>execlists.virtual);
RB_CLEAR_NODE(>rb);
- spin_unlock(>active.lock);
}
- continue;
- }
- spin_lock(>active.lock);
+ goto unlock_engine;
+ }
- if (!RB_EMPTY_NODE(>rb)) {
+ if (unlikely(!RB_EMPTY_NODE(>rb))) {
/*
* Cheat and avoid rebalancing the tree if we can
* reuse this node in situ.
@@ -5531,9 +5524,12 @@ static void virtual_submission_tasklet(unsigned long
data)
if (first && prio > sibling->execlists.queue_priority_hint)
tasklet_hi_schedule(>execlists.tasklet);
- spin_unlock(>active.lock);
+unlock_engine:
+ spin_unlock_irq(>active.lock);
+
+ if (intel_context_inflight(>context))
+ break;
}
- local_irq_enable();
}
static void virtual_submit_request(struct i915_request *rq)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 00/16] drm/i915: Add support for HDCP 1.4 over MST connectors
On 2020-05-18 at 10:32:09 -0400, Sean Paul wrote: > On Fri, May 15, 2020 at 10:48 AM Ramalingam C wrote: > > > > On 2020-04-29 at 15:54:46 -0400, Sean Paul wrote: > > > From: Sean Paul > > > > > > Changes in v6: > > > -Rebased on -tip > > > -Disabled HDCP over MST on GEN12 > > > -Addressed Lyude's review comments in the QUERY_STREAM_ENCRYPTION_STATUS > > > patch > > > > Sean, > > > > What is the test setup you have used? > > > > Hi Ram, > Thanks for the feedback. To be completely honest it's really > frustrating that I'm just now getting questions and review feedback > (which I've been begging for on IRC) on this review that could have > been addressed ~5 months ago. It's super disruptive to have to keep > switching back to this after a long hiatus and many i915 refactors > complicating my rebases. Hi Sean, As a developer I really feel bad for the delay happened in review. I couldn't spend required time for understanding MST part hence I couldn't review. Just for this series now I have started preparing myself on these topics, hence started reviewing the series. If you are still interested to work on this, I can commit for regular reviews. Thanks, Ram. > > If no one wants this patchset, that's fine, please just let me know so > I don't waste any more time. If Intel is interested, could we please > stop the review trickle and lay out exactly what needs to be done to > get this landed? > > Sean > > > > I am afraid our CI dont have the coverage for MST capability yet to provide > > the functional status of the code. > > > > -Ram. > > > > > > Sean Paul (16): > > > drm/i915: Fix sha_text population code > > > drm/i915: Clear the repeater bit on HDCP disable > > > drm/i915: WARN if HDCP signalling is enabled upon disable > > > drm/i915: Intercept Aksv writes in the aux hooks > > > drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP > > > signalling > > > drm/i915: Factor out hdcp->value assignments > > > drm/i915: Protect workers against disappearing connectors > > > drm/i915: Don't fully disable HDCP on a port if multiple pipes are > > > using it > > > drm/i915: Support DP MST in enc_to_dig_port() function > > > drm/i915: Use ddi_update_pipe in intel_dp_mst > > > drm/i915: Factor out HDCP shim functions from dp for use by dp_mst > > > drm/i915: Plumb port through hdcp init > > > drm/i915: Add connector to hdcp_shim->check_link() > > > drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband > > > message > > > drm/i915: Print HDCP version info for all connectors > > > drm/i915: Add HDCP 1.4 support for MST connectors > > > > > > drivers/gpu/drm/drm_dp_mst_topology.c | 142 > > > drivers/gpu/drm/i915/Makefile | 1 + > > > drivers/gpu/drm/i915/display/intel_ddi.c | 29 +- > > > drivers/gpu/drm/i915/display/intel_ddi.h | 2 + > > > .../drm/i915/display/intel_display_debugfs.c | 21 +- > > > .../drm/i915/display/intel_display_types.h| 30 +- > > > drivers/gpu/drm/i915/display/intel_dp.c | 654 +-- > > > drivers/gpu/drm/i915/display/intel_dp.h | 9 + > > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 743 ++ > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 + > > > drivers/gpu/drm/i915/display/intel_hdcp.c | 217 +++-- > > > drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- > > > drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +- > > > .../drm/selftests/test-drm_dp_mst_helper.c| 17 + > > > include/drm/drm_dp_helper.h | 3 + > > > include/drm/drm_dp_mst_helper.h | 44 ++ > > > include/drm/drm_hdcp.h| 3 + > > > 17 files changed, 1235 insertions(+), 726 deletions(-) > > > create mode 100644 drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > > > > > -- > > > Sean Paul, Software Engineer, Google / Chromium OS > > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for HDCP minor refactoring (rev2)
== Series Details ==
Series: HDCP minor refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/77224/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8494_full -> Patchwork_17688_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17688_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#1901])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-glk2/igt@gem_pp...@blt-vs-render-ctxn.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-glk7/igt@gem_pp...@blt-vs-render-ctxn.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] /
[i915#716])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl7/igt@gen9_exec_pa...@allowed-all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-apl7/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +2 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl3/igt@i915_susp...@forcewake.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-kbl3/igt@i915_susp...@forcewake.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-random:
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#54])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl6/igt@kms_cursor_...@pipe-a-cursor-64x64-random.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-64x64-random.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-kbl: [PASS][9] -> [FAIL][10] ([i915#54] / [i915#93] /
[i915#95])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-kbl1/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#1188]) +1 similar
issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl8/igt@kms_...@bpc-switch-dpms.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-skl4/igt@kms_...@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#69])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-skl9/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +2
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-iclb3/igt@kms_psr@psr2_sprite_blt.html
* igt@perf@enable-disable:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#1352])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl10/igt@p...@enable-disable.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-skl5/igt@p...@enable-disable.html
Possible fixes
* {igt@gem_exec_schedule@pi-shared-iova@rcs0}:
- shard-tglb: [INCOMPLETE][23] ([i915#1193]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb2/igt@gem_exec_schedule@pi-shared-i...@rcs0.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17688/shard-tglb6/igt@gem_exec_schedule@pi-shared-i...@rcs0.html
* {igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-b}:
- shard-kbl: [DMESG-WARN][25] ([i915#78]) -> [PASS][26]
[25]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/8] drm/i915: Move saturated workload detection back to the context (rev2)
== Series Details ==
Series: series starting with [1/8] drm/i915: Move saturated workload detection
back to the context (rev2)
URL : https://patchwork.freedesktop.org/series/77344/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8494 -> Patchwork_17693
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17693 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17693, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17693:
### IGT changes ###
Possible regressions
* igt@gem_exec_gttfill@basic:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-apl-guc/igt@gem_exec_gttf...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-apl-guc/igt@gem_exec_gttf...@basic.html
* igt@i915_selftest@live@execlists:
- fi-cfl-8109u: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
- fi-icl-u2: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-icl-u2/igt@i915_selftest@l...@execlists.html
- fi-tgl-y: [PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-tgl-y/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-tgl-y/igt@i915_selftest@l...@execlists.html
- fi-icl-y: [PASS][9] -> [INCOMPLETE][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-y/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-icl-y/igt@i915_selftest@l...@execlists.html
- fi-icl-guc: [PASS][11] -> [INCOMPLETE][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-guc/igt@i915_selftest@l...@execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-icl-guc/igt@i915_selftest@l...@execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-tgl-u}: [PASS][13] -> [INCOMPLETE][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-tgl-u/igt@i915_selftest@l...@execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-tgl-u/igt@i915_selftest@l...@execlists.html
- {fi-tgl-dsi}: [PASS][15] -> [INCOMPLETE][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
Known issues
Here are the changes found in Patchwork_17693 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@client:
- fi-bwr-2160:[PASS][17] -> [INCOMPLETE][18] ([i915#489])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-bwr-2160/igt@i915_selftest@l...@client.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-bwr-2160/igt@i915_selftest@l...@client.html
* igt@i915_selftest@live@execlists:
- fi-skl-lmem:[PASS][19] -> [INCOMPLETE][20] ([i915#1795])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-whl-u: [INCOMPLETE][21] ([i915#656]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-whl-u/igt@i915_selftest@l...@execlists.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-whl-u/igt@i915_selftest@l...@execlists.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][23] ([fdo#109271]) -> [FAIL][24] ([i915#62] /
[i915#95])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17693/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[Intel-gfx] [PATCH] drm/i915/selftests: Measure dispatch latency
A useful metric of the system's health is how fast we can tell the GPU
to do various actions, so measure our latency.
v2: Refactor all the instruction building into emitters.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/selftests/i915_request.c | 767 ++
1 file changed, 767 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 6014e8dfcbb1..3e8169c9b081 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -24,16 +24,20 @@
#include
#include
+#include
#include "gem/i915_gem_pm.h"
#include "gem/selftests/mock_context.h"
+#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gt.h"
+#include "gt/intel_gt_requests.h"
#include "i915_random.h"
#include "i915_selftest.h"
+#include "igt_flush_test.h"
#include "igt_live_test.h"
#include "igt_spinner.h"
#include "lib_sw_fence.h"
@@ -1524,6 +1528,768 @@ struct perf_series {
struct intel_context *ce[];
};
+static int cmp_u32(const void *A, const void *B)
+{
+ const u32 *a = A, *b = B;
+
+ return *a - *b;
+}
+
+static u32 trifilter(u32 *a)
+{
+ u64 sum;
+
+#define TF_COUNT 5
+ sort(a, TF_COUNT, sizeof(*a), cmp_u32, NULL);
+
+ sum = mul_u32_u32(a[2], 2);
+ sum += a[1];
+ sum += a[3];
+
+ GEM_BUG_ON(sum > U32_MAX);
+ return sum;
+#define TF_BIAS 2
+}
+
+static u64 cycles_to_ns(struct intel_engine_cs *engine, u32 cycles)
+{
+ u64 ns = i915_cs_timestamp_ticks_to_ns(engine->i915, cycles);
+
+ return DIV_ROUND_CLOSEST(ns, 1 << TF_BIAS);
+}
+
+static u32 *emit_timestamp_store(u32 *cs, struct intel_context *ce, u32 offset)
+{
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP((ce->engine->mmio_base)));
+ *cs++ = offset;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static u32 *emit_store_dw(u32 *cs, u32 offset, u32 value)
+{
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = offset;
+ *cs++ = 0;
+ *cs++ = value;
+
+ return cs;
+}
+
+static u32 *emit_semaphore_poll(u32 *cs, u32 mode, u32 value, u32 offset)
+{
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ mode;
+ *cs++ = value;
+ *cs++ = offset;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static u32 *emit_semaphore_poll_until(u32 *cs, u32 offset, u32 value)
+{
+ return emit_semaphore_poll(cs, MI_SEMAPHORE_SAD_EQ_SDD, value, offset);
+}
+
+static void semaphore_set(u32 *sema, u32 value)
+{
+ WRITE_ONCE(*sema, value);
+ wmb(); /* flush the update to the cache, and beyond */
+}
+
+static u32 *hwsp_scratch(const struct intel_context *ce)
+{
+ return memset32(ce->engine->status_page.addr + 1000, 0, 21);
+}
+
+static u32 hwsp_offset(const struct intel_context *ce, u32 *dw)
+{
+ return (i915_ggtt_offset(ce->engine->status_page.vma) +
+ offset_in_page(dw));
+}
+
+static int measure_semaphore_response(struct intel_context *ce)
+{
+ u32 *sema = hwsp_scratch(ce);
+ const u32 offset = hwsp_offset(ce, sema);
+ u32 elapsed[TF_COUNT], cycles;
+ struct i915_request *rq;
+ u32 *cs;
+ int i;
+
+ /*
+* Measure how many cycles it takes for the HW to detect the change
+* in a semaphore value.
+*
+*A: read CS_TIMESTAMP from CPU
+*poke semaphore
+*B: read CS_TIMESTAMP on GPU
+*
+* Semaphore latency: B - A
+*/
+
+ semaphore_set(sema, -1);
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ cs = intel_ring_begin(rq, 4 + 8 * ARRAY_SIZE(elapsed));
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ return PTR_ERR(cs);
+ }
+
+ cs = emit_store_dw(cs, offset, 0);
+ for (i = 1; i <= ARRAY_SIZE(elapsed); i++) {
+ cs = emit_semaphore_poll_until(cs, offset, i);
+ cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));
+ }
+
+ intel_ring_advance(rq, cs);
+ i915_request_add(rq);
+
+ if (wait_for(READ_ONCE(*sema) == 0, 50)) {
+ intel_gt_set_wedged(ce->engine->gt);
+ return -EIO;
+ }
+
+ for (i = 1; i <= ARRAY_SIZE(elapsed); i++) {
+ preempt_disable();
+ cycles = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP);
+ semaphore_set(sema, i);
+ preempt_enable();
+
+ if (wait_for(READ_ONCE(sema[i]), 50)) {
+ intel_gt_set_wedged(ce->engine->gt);
+ return -EIO;
+ }
+
+ elapsed[i - 1] = sema[i] - cycles;
+
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/selftests: Measure dispatch latency (rev7)
== Series Details == Series: drm/i915/selftests: Measure dispatch latency (rev7) URL : https://patchwork.freedesktop.org/series/77308/ State : failure == Summary == Applying: drm/i915/selftests: Measure dispatch latency error: corrupt patch at line 23 error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915/selftests: Measure dispatch latency When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/8] drm/i915: Move saturated workload detection back to the context (rev2)
== Series Details == Series: series starting with [1/8] drm/i915: Move saturated workload detection back to the context (rev2) URL : https://patchwork.freedesktop.org/series/77344/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/compiler.h:199:9: warning: context imbalance in 'engines_sample' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/i915: Move saturated workload detection back to the context (rev2)
== Series Details ==
Series: series starting with [1/8] drm/i915: Move saturated workload detection
back to the context (rev2)
URL : https://patchwork.freedesktop.org/series/77344/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ebeb414a1e8b drm/i915: Move saturated workload detection back to the context
-:22: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#22:
References: 44d89409a12e ("drm/i915: Make the semaphore saturation mask global")
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 44d89409a12e ("drm/i915: Make
the semaphore saturation mask global")'
#22:
References: 44d89409a12e ("drm/i915: Make the semaphore saturation mask global")
total: 1 errors, 1 warnings, 0 checks, 68 lines checked
c342f572622c drm/i915/selftests: Add tests for timeslicing virtual engines
e52d02f21091 drm/i915/gt: Reuse the tasklet priority for virtual as their
siblings
5738cd8b2a42 drm/i915/gt: Kick virtual siblings on timeslice out
003a59b1d9d0 drm/i915/gt: Incorporate the virtual engine into timeslicing
d9417a9630ea drm/i915/gt: Use virtual_engine during execlists_dequeue
040e56db9cd6 drm/i915/gt: Decouple inflight virtual engines
cb577ac5632e drm/i915/gt: Resubmit the virtual engine on schedule-out
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev9)
== Series Details ==
Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev9)
URL : https://patchwork.freedesktop.org/series/73036/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8494 -> Patchwork_17692
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17692 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17692, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17692/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17692:
### CI changes ###
Possible regressions
* boot:
- fi-icl-y: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-y/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17692/fi-icl-y/boot.html
- fi-icl-u2: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-u2/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17692/fi-icl-u2/boot.html
- fi-icl-dsi: [PASS][5] -> [FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-dsi/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17692/fi-icl-dsi/boot.html
- fi-icl-guc: [PASS][7] -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-guc/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17692/fi-icl-guc/boot.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* boot:
- {fi-ehl-1}: [PASS][9] -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-ehl-1/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17692/fi-ehl-1/boot.html
Known issues
Here are the changes found in Patchwork_17692 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hugepages:
- fi-bwr-2160:[PASS][11] -> [INCOMPLETE][12] ([i915#489])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-bwr-2160/igt@i915_selftest@l...@hugepages.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17692/fi-bwr-2160/igt@i915_selftest@l...@hugepages.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-whl-u: [INCOMPLETE][13] ([i915#656]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-whl-u/igt@i915_selftest@l...@execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17692/fi-whl-u/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (51 -> 44)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_8494 -> Patchwork_17692
CI-20190529: 20190529
CI_DRM_8494: 3d15348fde9b998e754da0b0655baf02b98e7f17 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5657: 649eae5c905a7460b44305800f95db83a6dd47cb @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17692: 694f96b3dba2b289b03894cad2c6eb35d7c63dfb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
694f96b3dba2 drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17692/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/8] drm/i915/gt: Decouple inflight virtual engines
Quoting Chris Wilson (2020-05-18 16:40:15)
> Quoting Tvrtko Ursulin (2020-05-18 15:55:46)
> >
> > On 18/05/2020 14:00, Chris Wilson wrote:
> > > Quoting Tvrtko Ursulin (2020-05-18 13:53:29)
> > >>
> > >> On 18/05/2020 09:14, Chris Wilson wrote:
> > >>> Once a virtual engine has been bound to a sibling, it will remain bound
> > >>> until we finally schedule out the last active request. We can not rebind
> > >>> the context to a new sibling while it is inflight as the context save
> > >>> will conflict, hence we wait. As we cannot then use any other sibliing
> > >>> while the context is inflight, only kick the bound sibling while it
> > >>> inflight and upon scheduling out the kick the rest (so that we can swap
> > >>> engines on timeslicing if the previously bound engine becomes
> > >>> oversubscribed).
> > >>>
> > >>> Signed-off-by: Chris Wilson
> > >>> ---
> > >>>drivers/gpu/drm/i915/gt/intel_lrc.c | 30
> > >>> +
> > >>>1 file changed, 13 insertions(+), 17 deletions(-)
> > >>>
> > >>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > >>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > >>> index 7a5ac3375225..fe8f3518d6b8 100644
> > >>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > >>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > >>> @@ -1398,9 +1398,8 @@ execlists_schedule_in(struct i915_request *rq,
> > >>> int idx)
> > >>>static void kick_siblings(struct i915_request *rq, struct
> > >>> intel_context *ce)
> > >>>{
> > >>>struct virtual_engine *ve = container_of(ce, typeof(*ve),
> > >>> context);
> > >>> - struct i915_request *next = READ_ONCE(ve->request);
> > >>>
> > >>> - if (next == rq || (next && next->execution_mask &
> > >>> ~rq->execution_mask))
> > >>> + if (READ_ONCE(ve->request))
> > >>>tasklet_hi_schedule(>base.execlists.tasklet);
> > >>>}
> > >>>
> > >>> @@ -1821,18 +1820,14 @@ first_virtual_engine(struct intel_engine_cs
> > >>> *engine)
> > >>>rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
> > >>>struct i915_request *rq = READ_ONCE(ve->request);
> > >>>
> > >>> - if (!rq) { /* lazily cleanup after another engine handled
> > >>> rq */
> > >>> + /* lazily cleanup after another engine handled rq */
> > >>> + if (!rq || !virtual_matches(ve, rq, engine)) {
> > >>>rb_erase_cached(rb, >virtual);
> > >>>RB_CLEAR_NODE(rb);
> > >>>rb = rb_first_cached(>virtual);
> > >>>continue;
> > >>>}
> > >>>
> > >>> - if (!virtual_matches(ve, rq, engine)) {
> > >>> - rb = rb_next(rb);
> > >>> - continue;
> > >>> - }
> > >>> -
> > >>>return ve;
> > >>>}
> > >>>
> > >>> @@ -5478,7 +5473,6 @@ static void virtual_submission_tasklet(unsigned
> > >>> long data)
> > >>>if (unlikely(!mask))
> > >>>return;
> > >>>
> > >>> - local_irq_disable();
> > >>>for (n = 0; n < ve->num_siblings; n++) {
> > >>>struct intel_engine_cs *sibling =
> > >>> READ_ONCE(ve->siblings[n]);
> > >>>struct ve_node * const node = >nodes[sibling->id];
> > >>> @@ -5488,20 +5482,19 @@ static void virtual_submission_tasklet(unsigned
> > >>> long data)
> > >>>if (!READ_ONCE(ve->request))
> > >>>break; /* already handled by a sibling's tasklet
> > >>> */
> > >>>
> > >>> + spin_lock_irq(>active.lock);
> > >>> +
> > >>>if (unlikely(!(mask & sibling->mask))) {
> > >>>if (!RB_EMPTY_NODE(>rb)) {
> > >>> - spin_lock(>active.lock);
> > >>>rb_erase_cached(>rb,
> > >>>
> > >>> >execlists.virtual);
> > >>>RB_CLEAR_NODE(>rb);
> > >>> - spin_unlock(>active.lock);
> > >>>}
> > >>> - continue;
> > >>> - }
> > >>>
> > >>> - spin_lock(>active.lock);
> > >>> + goto unlock_engine;
> > >>> + }
> > >>>
> > >>> - if (!RB_EMPTY_NODE(>rb)) {
> > >>> + if (unlikely(!RB_EMPTY_NODE(>rb))) {
> > >>>/*
> > >>> * Cheat and avoid rebalancing the tree if we can
> > >>> * reuse this node in situ.
> > >>> @@ -5541,9 +5534,12 @@ static void virtual_submission_tasklet(unsigned
> > >>> long data)
> > >>>if (first && prio >=
> > >>> sibling->execlists.queue_priority_hint)
> > >>>tasklet_hi_schedule(>execlists.tasklet);
> > >>>
> > >>> - spin_unlock(>active.lock);
> > >>> +unlock_engine:
> > >>> +
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Refactor sibling selection
== Series Details ==
Series: drm/i915/selftests: Refactor sibling selection
URL : https://patchwork.freedesktop.org/series/77352/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8494_full -> Patchwork_17687_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17687_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl3/igt@gem_workarou...@suspend-resume.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-kbl3/igt@gem_workarou...@suspend-resume.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] /
[i915#716])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl5/igt@gen9_exec_pa...@allowed-all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-skl8/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_selftest@live@execlists:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#1795] /
[i915#1874])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl7/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-skl9/igt@i915_selftest@l...@execlists.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#1188]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl8/igt@kms_...@bpc-switch-dpms.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-skl8/igt@kms_...@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-iclb3/igt@kms_psr@psr2_sprite_blt.html
Possible fixes
* {igt@gem_exec_schedule@pi-shared-iova@rcs0}:
- shard-tglb: [INCOMPLETE][13] ([i915#1193]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb2/igt@gem_exec_schedule@pi-shared-i...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-tglb8/igt@gem_exec_schedule@pi-shared-i...@rcs0.html
* {igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-b}:
- shard-kbl: [DMESG-WARN][15] ([i915#78]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl2/igt@kms_atomic_transition@plane-all-transition-nonblock...@pipe-b.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-kbl3/igt@kms_atomic_transition@plane-all-transition-nonblock...@pipe-b.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
- shard-tglb: [FAIL][17] ([i915#1897]) -> [PASS][18] +4 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb1/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-tglb2/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
- shard-skl: [FAIL][19] ([i915#54]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl4/igt@kms_cursor_...@pipe-c-cursor-64x64-onscreen.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-64x64-onscreen.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][21] ([fdo#109349]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb4/igt@kms_dp_...@basic-dsc-enable-edp.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1}:
- shard-skl: [FAIL][23] ([i915#79]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17687/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html
*
Re: [Intel-gfx] [PATCH 7/8] drm/i915/gt: Decouple inflight virtual engines
Quoting Tvrtko Ursulin (2020-05-18 15:55:46)
>
> On 18/05/2020 14:00, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-05-18 13:53:29)
> >>
> >> On 18/05/2020 09:14, Chris Wilson wrote:
> >>> Once a virtual engine has been bound to a sibling, it will remain bound
> >>> until we finally schedule out the last active request. We can not rebind
> >>> the context to a new sibling while it is inflight as the context save
> >>> will conflict, hence we wait. As we cannot then use any other sibliing
> >>> while the context is inflight, only kick the bound sibling while it
> >>> inflight and upon scheduling out the kick the rest (so that we can swap
> >>> engines on timeslicing if the previously bound engine becomes
> >>> oversubscribed).
> >>>
> >>> Signed-off-by: Chris Wilson
> >>> ---
> >>>drivers/gpu/drm/i915/gt/intel_lrc.c | 30 +
> >>>1 file changed, 13 insertions(+), 17 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>> index 7a5ac3375225..fe8f3518d6b8 100644
> >>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>> @@ -1398,9 +1398,8 @@ execlists_schedule_in(struct i915_request *rq, int
> >>> idx)
> >>>static void kick_siblings(struct i915_request *rq, struct
> >>> intel_context *ce)
> >>>{
> >>>struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
> >>> - struct i915_request *next = READ_ONCE(ve->request);
> >>>
> >>> - if (next == rq || (next && next->execution_mask &
> >>> ~rq->execution_mask))
> >>> + if (READ_ONCE(ve->request))
> >>>tasklet_hi_schedule(>base.execlists.tasklet);
> >>>}
> >>>
> >>> @@ -1821,18 +1820,14 @@ first_virtual_engine(struct intel_engine_cs
> >>> *engine)
> >>>rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
> >>>struct i915_request *rq = READ_ONCE(ve->request);
> >>>
> >>> - if (!rq) { /* lazily cleanup after another engine handled
> >>> rq */
> >>> + /* lazily cleanup after another engine handled rq */
> >>> + if (!rq || !virtual_matches(ve, rq, engine)) {
> >>>rb_erase_cached(rb, >virtual);
> >>>RB_CLEAR_NODE(rb);
> >>>rb = rb_first_cached(>virtual);
> >>>continue;
> >>>}
> >>>
> >>> - if (!virtual_matches(ve, rq, engine)) {
> >>> - rb = rb_next(rb);
> >>> - continue;
> >>> - }
> >>> -
> >>>return ve;
> >>>}
> >>>
> >>> @@ -5478,7 +5473,6 @@ static void virtual_submission_tasklet(unsigned
> >>> long data)
> >>>if (unlikely(!mask))
> >>>return;
> >>>
> >>> - local_irq_disable();
> >>>for (n = 0; n < ve->num_siblings; n++) {
> >>>struct intel_engine_cs *sibling =
> >>> READ_ONCE(ve->siblings[n]);
> >>>struct ve_node * const node = >nodes[sibling->id];
> >>> @@ -5488,20 +5482,19 @@ static void virtual_submission_tasklet(unsigned
> >>> long data)
> >>>if (!READ_ONCE(ve->request))
> >>>break; /* already handled by a sibling's tasklet */
> >>>
> >>> + spin_lock_irq(>active.lock);
> >>> +
> >>>if (unlikely(!(mask & sibling->mask))) {
> >>>if (!RB_EMPTY_NODE(>rb)) {
> >>> - spin_lock(>active.lock);
> >>>rb_erase_cached(>rb,
> >>>
> >>> >execlists.virtual);
> >>>RB_CLEAR_NODE(>rb);
> >>> - spin_unlock(>active.lock);
> >>>}
> >>> - continue;
> >>> - }
> >>>
> >>> - spin_lock(>active.lock);
> >>> + goto unlock_engine;
> >>> + }
> >>>
> >>> - if (!RB_EMPTY_NODE(>rb)) {
> >>> + if (unlikely(!RB_EMPTY_NODE(>rb))) {
> >>>/*
> >>> * Cheat and avoid rebalancing the tree if we can
> >>> * reuse this node in situ.
> >>> @@ -5541,9 +5534,12 @@ static void virtual_submission_tasklet(unsigned
> >>> long data)
> >>>if (first && prio >=
> >>> sibling->execlists.queue_priority_hint)
> >>>tasklet_hi_schedule(>execlists.tasklet);
> >>>
> >>> - spin_unlock(>active.lock);
> >>> +unlock_engine:
> >>> + spin_unlock_irq(>active.lock);
> >>> +
> >>> + if (intel_context_inflight(>context))
> >>> + break;
> >>
> >> So virtual request may not be added to all siblings any longer. Will it
> >> still be able to schedule it on any if time slicing kicks in under these
> >>
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] Revert "drm/i915: Clean up dbuf debugs during .atomic_check()"
== Series Details == Series: series starting with [1/4] Revert "drm/i915: Clean up dbuf debugs during .atomic_check()" URL : https://patchwork.freedesktop.org/series/77358/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8494 -> Patchwork_17691 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17691 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17691, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17691/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17691: ### IGT changes ### Possible regressions * igt@i915_selftest@live@hangcheck: - fi-cml-s: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-cml-s/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17691/fi-cml-s/igt@i915_selftest@l...@hangcheck.html Known issues Here are the changes found in Patchwork_17691 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-tgl-y: [PASS][3] -> [INCOMPLETE][4] ([i915#1803]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-tgl-y/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17691/fi-tgl-y/igt@i915_selftest@l...@execlists.html - fi-skl-6700k2: [PASS][5] -> [INCOMPLETE][6] ([i915#1795] / [i915#656]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17691/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html Possible fixes * igt@i915_selftest@live@execlists: - fi-whl-u: [INCOMPLETE][7] ([i915#656]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-whl-u/igt@i915_selftest@l...@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17691/fi-whl-u/igt@i915_selftest@l...@execlists.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][9] ([fdo#109271]) -> [FAIL][10] ([i915#62] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17691/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1795]: https://gitlab.freedesktop.org/drm/intel/issues/1795 [i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8494 -> Patchwork_17691 CI-20190529: 20190529 CI_DRM_8494: 3d15348fde9b998e754da0b0655baf02b98e7f17 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5657: 649eae5c905a7460b44305800f95db83a6dd47cb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17691: 0ede4a7df84889e374e588f8cf93260914a21975 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0ede4a7df848 Revert "drm/i915: Introduce proper dbuf state" 77a3d0811ea1 Revert "drm/i915: Nuke skl_ddb_get_hw_state()" 3358451aea83 Revert "drm/i915: Move the dbuf pre/post plane update" 4de007ca5a0f Revert "drm/i915: Clean up dbuf debugs during .atomic_check()" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17691/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/selftests: Measure dispatch latency
Quoting Chris Wilson (2020-05-18 16:14:43)
> Quoting Mika Kuoppala (2020-05-18 16:07:47)
> > Chris Wilson writes:
> > > + cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));
> >
> > Is the dual writes here so that when you kick the semaphore, you get the
> > latest no matter which side you were on?
>
> We wait on the first write in the CPU before releasing the semaphore. It
> was easier to copy the code, but now it can be an emit_store_dw() to
> make it clearer that we are not using it as timestamp -- and avoid the
> infinite wait if we hit CS_TIMESTAMP == 0.
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index c6dff5145a3c..887171ff21a0 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -1779,7 +1779,7 @@ static int measure_busy_dispatch(struct intel_context *ce)
return PTR_ERR(cs);
}
- cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));
+ cs = emit_store_dw(cs, offset + i * sizeof(u32), -1);
cs = emit_semaphore_poll_until(cs, offset, i);
cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));
@@ -1802,8 +1802,10 @@ static int measure_busy_dispatch(struct intel_context
*ce)
wait_for(READ_ONCE(sema[i - 1]), 500);
semaphore_set(sema, i - 1);
- for (i = 1; i <= COUNT; i++)
+ for (i = 1; i <= COUNT; i++) {
+ GEM_BUG_ON(sema[i] == -1);
elapsed[i - 1] = (sema[i] - elapsed[i]) << COUNT;
+ }
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/selftests: Measure dispatch latency
Quoting Mika Kuoppala (2020-05-18 16:07:47) > Chris Wilson writes: > > + cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32)); > > Is the dual writes here so that when you kick the semaphore, you get the > latest no matter which side you were on? We wait on the first write in the CPU before releasing the semaphore. It was easier to copy the code, but now it can be an emit_store_dw() to make it clearer that we are not using it as timestamp -- and avoid the infinite wait if we hit CS_TIMESTAMP == 0. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Measure dispatch latency (rev5)
== Series Details ==
Series: drm/i915/selftests: Measure dispatch latency (rev5)
URL : https://patchwork.freedesktop.org/series/77308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8494_full -> Patchwork_17686_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17686_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#1436] /
[i915#716])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-apl7/igt@gen9_exec_pa...@allowed-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-apl6/igt@gen9_exec_pa...@allowed-all.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#1188]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl8/igt@kms_...@bpc-switch-dpms.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-skl3/igt@kms_...@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108145] / [i915#265])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-skl6/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#173])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb8/igt@kms_psr@no_drrs.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#69])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl5/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-skl3/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html
Possible fixes
* {igt@gem_exec_schedule@pi-shared-iova@rcs0}:
- shard-tglb: [INCOMPLETE][15] ([i915#1193]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb2/igt@gem_exec_schedule@pi-shared-i...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-tglb2/igt@gem_exec_schedule@pi-shared-i...@rcs0.html
* {igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-b}:
- shard-kbl: [DMESG-WARN][17] ([i915#78]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-kbl2/igt@kms_atomic_transition@plane-all-transition-nonblock...@pipe-b.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-kbl6/igt@kms_atomic_transition@plane-all-transition-nonblock...@pipe-b.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
- shard-tglb: [FAIL][19] ([i915#1897]) -> [PASS][20] +4 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-tglb1/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-tglb5/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-64x64-onscreen:
- shard-skl: [FAIL][21] ([i915#54]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl4/igt@kms_cursor_...@pipe-c-cursor-64x64-onscreen.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-64x64-onscreen.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1}:
- shard-skl: [FAIL][23] ([i915#79]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17686/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html
* {igt@kms_flip@flip-vs-suspend-interruptible@a-dp1}:
Re: [Intel-gfx] [PATCH v2] drm/i915/selftests: Measure dispatch latency
Chris Wilson writes:
> A useful metric of the system's health is how fast we can tell the GPU
> to do various actions, so measure our latency.
>
> v2: Refactor all the instruction building into emitters.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/selftests/i915_request.c | 764 ++
> 1 file changed, 764 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
> b/drivers/gpu/drm/i915/selftests/i915_request.c
> index 6014e8dfcbb1..c6dff5145a3c 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
> @@ -24,16 +24,20 @@
>
> #include
> #include
> +#include
>
> #include "gem/i915_gem_pm.h"
> #include "gem/selftests/mock_context.h"
>
> +#include "gt/intel_engine_heartbeat.h"
> #include "gt/intel_engine_pm.h"
> #include "gt/intel_engine_user.h"
> #include "gt/intel_gt.h"
> +#include "gt/intel_gt_requests.h"
>
> #include "i915_random.h"
> #include "i915_selftest.h"
> +#include "igt_flush_test.h"
> #include "igt_live_test.h"
> #include "igt_spinner.h"
> #include "lib_sw_fence.h"
> @@ -1524,6 +1528,765 @@ struct perf_series {
> struct intel_context *ce[];
> };
>
> +#define COUNT 5
> +
> +static int cmp_u32(const void *A, const void *B)
> +{
> + const u32 *a = A, *b = B;
> +
> + return *a - *b;
> +}
> +
> +static u32 trifilter(u32 *a)
> +{
> + u64 sum;
> +
> + sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
> +
> + sum = mul_u32_u32(a[2], 2);
> + sum += a[1];
> + sum += a[3];
> +
> + return (sum + 2) >> 2;
> +}
> +
> +static u64 cycles_to_ns(struct intel_engine_cs *engine, u32 cycles)
> +{
> + u64 ns = i915_cs_timestamp_ticks_to_ns(engine->i915, cycles);
> +
> + return DIV_ROUND_CLOSEST(ns, 1 << COUNT);
> +}
> +
> +static u32 *emit_timestamp_store(u32 *cs, struct intel_context *ce, u32
> offset)
> +{
> + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
> + *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP((ce->engine->mmio_base)));
> + *cs++ = offset;
> + *cs++ = 0;
> +
> + return cs;
> +}
> +
> +static u32 *emit_store_dw(u32 *cs, u32 offset, u32 value)
> +{
> + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> + *cs++ = offset;
> + *cs++ = 0;
> + *cs++ = value;
> +
> + return cs;
> +}
> +
> +static u32 *emit_semaphore_poll(u32 *cs, u32 mode, u32 value, u32 offset)
> +{
> + *cs++ = MI_SEMAPHORE_WAIT |
> + MI_SEMAPHORE_GLOBAL_GTT |
> + MI_SEMAPHORE_POLL |
> + mode;
> + *cs++ = value;
> + *cs++ = offset;
> + *cs++ = 0;
> +
> + return cs;
> +}
> +
> +static u32 *emit_semaphore_poll_until(u32 *cs, u32 offset, u32 value)
> +{
> + return emit_semaphore_poll(cs, MI_SEMAPHORE_SAD_EQ_SDD, value, offset);
> +}
> +
> +static void semaphore_set(u32 *sema, u32 value)
> +{
> + WRITE_ONCE(*sema, value);
> + wmb(); /* flush the update to the cache, and beyond */
> +}
> +
> +static u32 *hwsp_scratch(const struct intel_context *ce)
> +{
> + return memset32(ce->engine->status_page.addr + 1000, 0, 21);
> +}
> +
> +static u32 hwsp_offset(const struct intel_context *ce, u32 *dw)
> +{
> + return (i915_ggtt_offset(ce->engine->status_page.vma) +
> + offset_in_page(dw));
> +}
> +
> +static int measure_semaphore_response(struct intel_context *ce)
> +{
> + u32 *sema = hwsp_scratch(ce);
> + const u32 offset = hwsp_offset(ce, sema);
> + u32 elapsed[COUNT], cycles;
> + struct i915_request *rq;
> + u32 *cs;
> + int i;
> +
> + /*
> + * Measure how many cycles it takes for the HW to detect the change
> + * in a semaphore value.
> + *
> + *A: read CS_TIMESTAMP from CPU
> + *poke semaphore
> + *B: read CS_TIMESTAMP on GPU
> + *
> + * Semaphore latency: B - A
> + */
> +
> + semaphore_set(sema, -1);
> +
> + rq = i915_request_create(ce);
> + if (IS_ERR(rq))
> + return PTR_ERR(rq);
> +
> + cs = intel_ring_begin(rq, 4 + 8 * ARRAY_SIZE(elapsed));
> + if (IS_ERR(cs)) {
> + i915_request_add(rq);
> + return PTR_ERR(cs);
> + }
> +
> + cs = emit_store_dw(cs, offset, 0);
> + for (i = 1; i <= ARRAY_SIZE(elapsed); i++) {
> + cs = emit_semaphore_poll_until(cs, offset, i);
> + cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));
> + }
> +
> + intel_ring_advance(rq, cs);
> + i915_request_add(rq);
> +
> + if (wait_for(READ_ONCE(*sema) == 0, 50)) {
> + intel_gt_set_wedged(ce->engine->gt);
> + return -EIO;
> + }
> +
> + for (i = 1; i <= ARRAY_SIZE(elapsed); i++) {
> + preempt_disable();
> + cycles = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP);
> + semaphore_set(sema, i);
> + preempt_enable();
> +
> + if (wait_for(READ_ONCE(sema[i]), 50))
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] Revert "drm/i915: Clean up dbuf debugs during .atomic_check()"
== Series Details == Series: series starting with [1/4] Revert "drm/i915: Clean up dbuf debugs during .atomic_check()" URL : https://patchwork.freedesktop.org/series/77358/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4de007ca5a0f Revert "drm/i915: Clean up dbuf debugs during .atomic_check()" 3358451aea83 Revert "drm/i915: Move the dbuf pre/post plane update" 77a3d0811ea1 Revert "drm/i915: Nuke skl_ddb_get_hw_state()" 0ede4a7df848 Revert "drm/i915: Introduce proper dbuf state" -:174: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #174: FILE: drivers/gpu/drm/i915/display/intel_display.c:18260: + dev_priv->active_pipes = cdclk_state->active_pipes = active_pipes; total: 0 errors, 0 warnings, 1 checks, 506 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix dbuf slice mask when turning off all the pipes (rev2)
== Series Details == Series: drm/i915: Fix dbuf slice mask when turning off all the pipes (rev2) URL : https://patchwork.freedesktop.org/series/77322/ State : success == Summary == CI Bug Log - changes from CI_DRM_8494 -> Patchwork_17690 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/index.html Known issues Here are the changes found in Patchwork_17690 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@active: - fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([i915#541]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-bsw-nick/igt@i915_selftest@l...@active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/fi-bsw-nick/igt@i915_selftest@l...@active.html * igt@i915_selftest@live@execlists: - fi-kbl-r: [PASS][3] -> [INCOMPLETE][4] ([i915#656]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-kbl-r/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/fi-kbl-r/igt@i915_selftest@l...@execlists.html Possible fixes * igt@i915_selftest@live@execlists: - fi-whl-u: [INCOMPLETE][5] ([i915#656]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-whl-u/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/fi-whl-u/igt@i915_selftest@l...@execlists.html [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (51 -> 43) -- Missing(8): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_8494 -> Patchwork_17690 CI-20190529: 20190529 CI_DRM_8494: 3d15348fde9b998e754da0b0655baf02b98e7f17 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5657: 649eae5c905a7460b44305800f95db83a6dd47cb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17690: fed553859a0fa75b2dac63ac5738561c2094e1ed @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fed553859a0f drm/i915: Fix dbuf slice mask when turning off all the pipes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17690/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/8] drm/i915/gt: Decouple inflight virtual engines
On 18/05/2020 14:00, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-05-18 13:53:29)
On 18/05/2020 09:14, Chris Wilson wrote:
Once a virtual engine has been bound to a sibling, it will remain bound
until we finally schedule out the last active request. We can not rebind
the context to a new sibling while it is inflight as the context save
will conflict, hence we wait. As we cannot then use any other sibliing
while the context is inflight, only kick the bound sibling while it
inflight and upon scheduling out the kick the rest (so that we can swap
engines on timeslicing if the previously bound engine becomes
oversubscribed).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 30 +
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7a5ac3375225..fe8f3518d6b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1398,9 +1398,8 @@ execlists_schedule_in(struct i915_request *rq, int idx)
static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
{
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
- struct i915_request *next = READ_ONCE(ve->request);
- if (next == rq || (next && next->execution_mask & ~rq->execution_mask))
+ if (READ_ONCE(ve->request))
tasklet_hi_schedule(>base.execlists.tasklet);
}
@@ -1821,18 +1820,14 @@ first_virtual_engine(struct intel_engine_cs *engine)
rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
struct i915_request *rq = READ_ONCE(ve->request);
- if (!rq) { /* lazily cleanup after another engine handled rq */
+ /* lazily cleanup after another engine handled rq */
+ if (!rq || !virtual_matches(ve, rq, engine)) {
rb_erase_cached(rb, >virtual);
RB_CLEAR_NODE(rb);
rb = rb_first_cached(>virtual);
continue;
}
- if (!virtual_matches(ve, rq, engine)) {
- rb = rb_next(rb);
- continue;
- }
-
return ve;
}
@@ -5478,7 +5473,6 @@ static void virtual_submission_tasklet(unsigned long data)
if (unlikely(!mask))
return;
- local_irq_disable();
for (n = 0; n < ve->num_siblings; n++) {
struct intel_engine_cs *sibling = READ_ONCE(ve->siblings[n]);
struct ve_node * const node = >nodes[sibling->id];
@@ -5488,20 +5482,19 @@ static void virtual_submission_tasklet(unsigned long
data)
if (!READ_ONCE(ve->request))
break; /* already handled by a sibling's tasklet */
+ spin_lock_irq(>active.lock);
+
if (unlikely(!(mask & sibling->mask))) {
if (!RB_EMPTY_NODE(>rb)) {
- spin_lock(>active.lock);
rb_erase_cached(>rb,
>execlists.virtual);
RB_CLEAR_NODE(>rb);
- spin_unlock(>active.lock);
}
- continue;
- }
- spin_lock(>active.lock);
+ goto unlock_engine;
+ }
- if (!RB_EMPTY_NODE(>rb)) {
+ if (unlikely(!RB_EMPTY_NODE(>rb))) {
/*
* Cheat and avoid rebalancing the tree if we can
* reuse this node in situ.
@@ -5541,9 +5534,12 @@ static void virtual_submission_tasklet(unsigned long
data)
if (first && prio >= sibling->execlists.queue_priority_hint)
tasklet_hi_schedule(>execlists.tasklet);
- spin_unlock(>active.lock);
+unlock_engine:
+ spin_unlock_irq(>active.lock);
+
+ if (intel_context_inflight(>context))
+ break;
So virtual request may not be added to all siblings any longer. Will it
still be able to schedule it on any if time slicing kicks in under these
conditions?
Yes.
This is equivalent to the hunk in first_virtual_engine which also
removes it from all other siblings.
I guess it's inline with what the commit messages says - that new
sibling will be picked upon time slicing. I just don't quite see the
path which would do it. Only path which shuffles the siblings array
around is in dequeue, and dequeue on other that the engine which first
picked it will not happen any more. I must be missing something..
It's all on the execlists_schedule_out. During timeslicing we call
unwind_incomplete_requests which moves the requests back to the priotree
(and in this patch back to the virtual engine).
But... We cannot use the virtual request on any
Re: [Intel-gfx] [PATCH 3/4] Revert "drm/i915: Nuke skl_ddb_get_hw_state()"
On Mon, May 18, 2020 at 03:23:02PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Dbuf slice tracking busted across runtime PM. Back to the
> drawing board.
>
> This reverts commit 0cde0e0ff5f5ebd27507069250728c763c14ac81.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 7 +++
> drivers/gpu/drm/i915/intel_pm.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a92d57d9b759..cb57786fdc9f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4315,6 +4315,12 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> intel_display_power_put(dev_priv, power_domain, wakeref);
> }
>
> +void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
> +{
> + dev_priv->dbuf.enabled_slices =
> + intel_enabled_dbuf_slices_mask(dev_priv);
> +}
> +
Reviewed-by: Stanislav Lisovskiy
> /*
> * Determines the downscale amount of a plane for the purposes of watermark
> calculations.
> * The bspec defines downscale amount as:
> @@ -6175,6 +6181,7 @@ void skl_wm_get_hw_state(struct drm_i915_private
> *dev_priv)
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
>
> + skl_ddb_get_hw_state(dev_priv);
> for_each_intel_crtc(_priv->drm, crtc) {
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 3fcc9b6e2cbf..9f75ac4c2bd1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -39,6 +39,7 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private
> *dev_priv);
> void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> struct skl_ddb_entry *ddb_y,
> struct skl_ddb_entry *ddb_uv);
> +void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
> void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> struct skl_pipe_wm *out);
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> --
> 2.26.2
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] Revert "drm/i915: Move the dbuf pre/post plane update"
On Mon, May 18, 2020 at 03:23:01PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Dbuf slice tracking busted across runtime PM. Back to the
> drawing board.
>
> This reverts commit c7c0e7ebe4d9963573f81399374e4e95f37fd8e3.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 41 +++-
> drivers/gpu/drm/i915/intel_pm.c | 37 --
> drivers/gpu/drm/i915/intel_pm.h | 2 -
> 3 files changed, 39 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e1407dc28ddc..49577f19ff9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15207,6 +15207,43 @@ static void intel_commit_modeset_enables(struct
> intel_atomic_state *state)
> }
> }
>
Reviewed-by: Stanislav Lisovskiy
> +static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_dbuf_state *new_dbuf_state =
> + intel_atomic_get_new_dbuf_state(state);
> + const struct intel_dbuf_state *old_dbuf_state =
> + intel_atomic_get_old_dbuf_state(state);
> +
> + if (!new_dbuf_state ||
> + new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
> + return;
> +
> + WARN_ON(!new_dbuf_state->base.changed);
> +
> + gen9_dbuf_slices_update(dev_priv,
> + old_dbuf_state->enabled_slices |
> + new_dbuf_state->enabled_slices);
> +}
> +
> +static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_dbuf_state *new_dbuf_state =
> + intel_atomic_get_new_dbuf_state(state);
> + const struct intel_dbuf_state *old_dbuf_state =
> + intel_atomic_get_old_dbuf_state(state);
> +
> + if (!new_dbuf_state ||
> + new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
> + return;
> +
> + WARN_ON(!new_dbuf_state->base.changed);
> +
> + gen9_dbuf_slices_update(dev_priv,
> + new_dbuf_state->enabled_slices);
> +}
> +
> static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> @@ -15447,7 +15484,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> if (state->modeset)
> intel_encoders_update_prepare(state);
>
> - intel_dbuf_pre_plane_update(state);
> + icl_dbuf_slice_pre_update(state);
>
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> dev_priv->display.commit_modeset_enables(state);
> @@ -15502,7 +15539,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> dev_priv->display.optimize_watermarks(state, crtc);
> }
>
> - intel_dbuf_post_plane_update(state);
> + icl_dbuf_slice_post_update(state);
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> intel_post_plane_update(state, crtc);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d40d22eb65da..a92d57d9b759 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7806,40 +7806,3 @@ int intel_dbuf_init(struct drm_i915_private *dev_priv)
>
> return 0;
> }
> -
> -void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - const struct intel_dbuf_state *new_dbuf_state =
> - intel_atomic_get_new_dbuf_state(state);
> - const struct intel_dbuf_state *old_dbuf_state =
> - intel_atomic_get_old_dbuf_state(state);
> -
> - if (!new_dbuf_state ||
> - new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
> - return;
> -
> - WARN_ON(!new_dbuf_state->base.changed);
> -
> - gen9_dbuf_slices_update(dev_priv,
> - old_dbuf_state->enabled_slices |
> - new_dbuf_state->enabled_slices);
> -}
> -
> -void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - const struct intel_dbuf_state *new_dbuf_state =
> - intel_atomic_get_new_dbuf_state(state);
> - const struct intel_dbuf_state *old_dbuf_state =
> - intel_atomic_get_old_dbuf_state(state);
> -
> - if (!new_dbuf_state ||
> - new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
> - return;
> -
> - WARN_ON(!new_dbuf_state->base.changed);
>
[Intel-gfx] [PATCH v2] drm/i915/selftests: Measure dispatch latency
A useful metric of the system's health is how fast we can tell the GPU
to do various actions, so measure our latency.
v2: Refactor all the instruction building into emitters.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/selftests/i915_request.c | 764 ++
1 file changed, 764 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 6014e8dfcbb1..c6dff5145a3c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -24,16 +24,20 @@
#include
#include
+#include
#include "gem/i915_gem_pm.h"
#include "gem/selftests/mock_context.h"
+#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gt.h"
+#include "gt/intel_gt_requests.h"
#include "i915_random.h"
#include "i915_selftest.h"
+#include "igt_flush_test.h"
#include "igt_live_test.h"
#include "igt_spinner.h"
#include "lib_sw_fence.h"
@@ -1524,6 +1528,765 @@ struct perf_series {
struct intel_context *ce[];
};
+#define COUNT 5
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const u32 *a = A, *b = B;
+
+ return *a - *b;
+}
+
+static u32 trifilter(u32 *a)
+{
+ u64 sum;
+
+ sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
+
+ sum = mul_u32_u32(a[2], 2);
+ sum += a[1];
+ sum += a[3];
+
+ return (sum + 2) >> 2;
+}
+
+static u64 cycles_to_ns(struct intel_engine_cs *engine, u32 cycles)
+{
+ u64 ns = i915_cs_timestamp_ticks_to_ns(engine->i915, cycles);
+
+ return DIV_ROUND_CLOSEST(ns, 1 << COUNT);
+}
+
+static u32 *emit_timestamp_store(u32 *cs, struct intel_context *ce, u32 offset)
+{
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP((ce->engine->mmio_base)));
+ *cs++ = offset;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static u32 *emit_store_dw(u32 *cs, u32 offset, u32 value)
+{
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = offset;
+ *cs++ = 0;
+ *cs++ = value;
+
+ return cs;
+}
+
+static u32 *emit_semaphore_poll(u32 *cs, u32 mode, u32 value, u32 offset)
+{
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ mode;
+ *cs++ = value;
+ *cs++ = offset;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static u32 *emit_semaphore_poll_until(u32 *cs, u32 offset, u32 value)
+{
+ return emit_semaphore_poll(cs, MI_SEMAPHORE_SAD_EQ_SDD, value, offset);
+}
+
+static void semaphore_set(u32 *sema, u32 value)
+{
+ WRITE_ONCE(*sema, value);
+ wmb(); /* flush the update to the cache, and beyond */
+}
+
+static u32 *hwsp_scratch(const struct intel_context *ce)
+{
+ return memset32(ce->engine->status_page.addr + 1000, 0, 21);
+}
+
+static u32 hwsp_offset(const struct intel_context *ce, u32 *dw)
+{
+ return (i915_ggtt_offset(ce->engine->status_page.vma) +
+ offset_in_page(dw));
+}
+
+static int measure_semaphore_response(struct intel_context *ce)
+{
+ u32 *sema = hwsp_scratch(ce);
+ const u32 offset = hwsp_offset(ce, sema);
+ u32 elapsed[COUNT], cycles;
+ struct i915_request *rq;
+ u32 *cs;
+ int i;
+
+ /*
+* Measure how many cycles it takes for the HW to detect the change
+* in a semaphore value.
+*
+*A: read CS_TIMESTAMP from CPU
+*poke semaphore
+*B: read CS_TIMESTAMP on GPU
+*
+* Semaphore latency: B - A
+*/
+
+ semaphore_set(sema, -1);
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ cs = intel_ring_begin(rq, 4 + 8 * ARRAY_SIZE(elapsed));
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ return PTR_ERR(cs);
+ }
+
+ cs = emit_store_dw(cs, offset, 0);
+ for (i = 1; i <= ARRAY_SIZE(elapsed); i++) {
+ cs = emit_semaphore_poll_until(cs, offset, i);
+ cs = emit_timestamp_store(cs, ce, offset + i * sizeof(u32));
+ }
+
+ intel_ring_advance(rq, cs);
+ i915_request_add(rq);
+
+ if (wait_for(READ_ONCE(*sema) == 0, 50)) {
+ intel_gt_set_wedged(ce->engine->gt);
+ return -EIO;
+ }
+
+ for (i = 1; i <= ARRAY_SIZE(elapsed); i++) {
+ preempt_disable();
+ cycles = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP);
+ semaphore_set(sema, i);
+ preempt_enable();
+
+ if (wait_for(READ_ONCE(sema[i]), 50)) {
+ intel_gt_set_wedged(ce->engine->gt);
+ return -EIO;
+ }
+
+ elapsed[i - 1] = (sema[i] - cycles) << COUNT;
+ }
+
+ cycles =
Re: [Intel-gfx] [PATCH 4/4] Revert "drm/i915: Introduce proper dbuf state"
On Mon, May 18, 2020 at 03:23:03PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Dbuf slice tracking busted across runtime PM. Back to the
> drawing board.
>
> This reverts commit 3cf43cdc63fbc3df19ea8398e9b8717ab44a6304.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 67 ++-
> .../drm/i915/display/intel_display_power.c| 8 +-
> .../drm/i915/display/intel_display_types.h| 13 ++
> drivers/gpu/drm/i915/i915_drv.h | 11 +-
> drivers/gpu/drm/i915/intel_pm.c | 185 ++
> drivers/gpu/drm/i915/intel_pm.h | 22 ---
> 6 files changed, 99 insertions(+), 207 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 49577f19ff9c..d6635d649dc8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7579,8 +7579,6 @@ static void intel_crtc_disable_noatomic(struct
> intel_crtc *crtc,
> to_intel_bw_state(dev_priv->bw_obj.state);
> struct intel_cdclk_state *cdclk_state =
> to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> - struct intel_dbuf_state *dbuf_state =
> - to_intel_dbuf_state(dev_priv->dbuf.obj.state);
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
> enum intel_display_power_domain domain;
> @@ -7654,8 +7652,6 @@ static void intel_crtc_disable_noatomic(struct
> intel_crtc *crtc,
> cdclk_state->min_voltage_level[pipe] = 0;
> cdclk_state->active_pipes &= ~BIT(pipe);
>
> - dbuf_state->active_pipes &= ~BIT(pipe);
> -
> bw_state->data_rate[pipe] = 0;
> bw_state->num_active_planes[pipe] = 0;
> }
> @@ -14012,10 +14008,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
> hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
>
> if (INTEL_GEN(dev_priv) >= 11 &&
> - hw_enabled_slices != dev_priv->dbuf.enabled_slices)
> + hw_enabled_slices != dev_priv->enabled_dbuf_slices_mask)
> drm_err(_priv->drm,
> "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
> - dev_priv->dbuf.enabled_slices,
> + dev_priv->enabled_dbuf_slices_mask,
> hw_enabled_slices);
>
> /* planes */
> @@ -14556,7 +14552,9 @@ static int intel_modeset_checks(struct
> intel_atomic_state *state)
> state->modeset = true;
> state->active_pipes = intel_calc_active_pipes(state,
> dev_priv->active_pipes);
>
> - if (state->active_pipes != dev_priv->active_pipes) {
> + state->active_pipe_changes = state->active_pipes ^
> dev_priv->active_pipes;
> +
> + if (state->active_pipe_changes) {
> ret = _intel_atomic_lock_global_state(state);
> if (ret)
> return ret;
> @@ -15210,38 +15208,22 @@ static void intel_commit_modeset_enables(struct
> intel_atomic_state *state)
> static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - const struct intel_dbuf_state *new_dbuf_state =
> - intel_atomic_get_new_dbuf_state(state);
> - const struct intel_dbuf_state *old_dbuf_state =
> - intel_atomic_get_old_dbuf_state(state);
> -
> - if (!new_dbuf_state ||
> - new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
> - return;
> + u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
> + u8 required_slices = state->enabled_dbuf_slices_mask;
> + u8 slices_union = hw_enabled_slices | required_slices;
>
> - WARN_ON(!new_dbuf_state->base.changed);
> -
> - gen9_dbuf_slices_update(dev_priv,
> - old_dbuf_state->enabled_slices |
> - new_dbuf_state->enabled_slices);
> + if (INTEL_GEN(dev_priv) >= 11 && slices_union != hw_enabled_slices)
> + gen9_dbuf_slices_update(dev_priv, slices_union);
> }
>
> static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - const struct intel_dbuf_state *new_dbuf_state =
> - intel_atomic_get_new_dbuf_state(state);
> - const struct intel_dbuf_state *old_dbuf_state =
> - intel_atomic_get_old_dbuf_state(state);
> -
> - if (!new_dbuf_state ||
> - new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
> - return;
> + u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
> + u8 required_slices = state->enabled_dbuf_slices_mask;
I guess that one opened the pandora box.. May be we shouldn't
even stick to checking against the old_dbuf_state? I mean,
this paradigm would work well only if we suppose that the last
Re: [Intel-gfx] [PATCH v6 00/16] drm/i915: Add support for HDCP 1.4 over MST connectors
On Fri, May 15, 2020 at 10:48 AM Ramalingam C wrote: > > On 2020-04-29 at 15:54:46 -0400, Sean Paul wrote: > > From: Sean Paul > > > > Changes in v6: > > -Rebased on -tip > > -Disabled HDCP over MST on GEN12 > > -Addressed Lyude's review comments in the QUERY_STREAM_ENCRYPTION_STATUS > > patch > > Sean, > > What is the test setup you have used? > Hi Ram, Thanks for the feedback. To be completely honest it's really frustrating that I'm just now getting questions and review feedback (which I've been begging for on IRC) on this review that could have been addressed ~5 months ago. It's super disruptive to have to keep switching back to this after a long hiatus and many i915 refactors complicating my rebases. If no one wants this patchset, that's fine, please just let me know so I don't waste any more time. If Intel is interested, could we please stop the review trickle and lay out exactly what needs to be done to get this landed? Sean > I am afraid our CI dont have the coverage for MST capability yet to provide > the functional status of the code. > > -Ram. > > > > Sean Paul (16): > > drm/i915: Fix sha_text population code > > drm/i915: Clear the repeater bit on HDCP disable > > drm/i915: WARN if HDCP signalling is enabled upon disable > > drm/i915: Intercept Aksv writes in the aux hooks > > drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP > > signalling > > drm/i915: Factor out hdcp->value assignments > > drm/i915: Protect workers against disappearing connectors > > drm/i915: Don't fully disable HDCP on a port if multiple pipes are > > using it > > drm/i915: Support DP MST in enc_to_dig_port() function > > drm/i915: Use ddi_update_pipe in intel_dp_mst > > drm/i915: Factor out HDCP shim functions from dp for use by dp_mst > > drm/i915: Plumb port through hdcp init > > drm/i915: Add connector to hdcp_shim->check_link() > > drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband > > message > > drm/i915: Print HDCP version info for all connectors > > drm/i915: Add HDCP 1.4 support for MST connectors > > > > drivers/gpu/drm/drm_dp_mst_topology.c | 142 > > drivers/gpu/drm/i915/Makefile | 1 + > > drivers/gpu/drm/i915/display/intel_ddi.c | 29 +- > > drivers/gpu/drm/i915/display/intel_ddi.h | 2 + > > .../drm/i915/display/intel_display_debugfs.c | 21 +- > > .../drm/i915/display/intel_display_types.h| 30 +- > > drivers/gpu/drm/i915/display/intel_dp.c | 654 +-- > > drivers/gpu/drm/i915/display/intel_dp.h | 9 + > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 743 ++ > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 + > > drivers/gpu/drm/i915/display/intel_hdcp.c | 217 +++-- > > drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- > > drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +- > > .../drm/selftests/test-drm_dp_mst_helper.c| 17 + > > include/drm/drm_dp_helper.h | 3 + > > include/drm/drm_dp_mst_helper.h | 44 ++ > > include/drm/drm_hdcp.h| 3 + > > 17 files changed, 1235 insertions(+), 726 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > > > -- > > Sean Paul, Software Engineer, Google / Chromium OS > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/params: don't expose inject_probe_failure in debugfs (rev2)
== Series Details == Series: series starting with [1/4] drm/i915/params: don't expose inject_probe_failure in debugfs (rev2) URL : https://patchwork.freedesktop.org/series/77272/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8494 -> Patchwork_17689 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17689 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17689, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17689: ### CI changes ### Possible regressions * boot: - fi-kbl-8809g: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-kbl-8809g/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-kbl-8809g/boot.html - fi-icl-y: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-y/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-icl-y/boot.html - fi-icl-u2: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-u2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-icl-u2/boot.html - fi-cfl-8109u: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-cfl-8109u/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-cfl-8109u/boot.html - fi-skl-6600u: [PASS][9] -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-skl-6600u/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-skl-6600u/boot.html - fi-cfl-8700k: [PASS][11] -> [FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-cfl-8700k/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-cfl-8700k/boot.html - fi-icl-dsi: [PASS][13] -> [FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-dsi/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-icl-dsi/boot.html - fi-whl-u: [PASS][15] -> [FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-whl-u/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-whl-u/boot.html - fi-cml-u2: [PASS][17] -> [FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-cml-u2/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-cml-u2/boot.html - fi-skl-6700k2: [PASS][19] -> [FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-skl-6700k2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-skl-6700k2/boot.html - fi-cfl-guc: [PASS][21] -> [FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-cfl-guc/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-cfl-guc/boot.html - fi-kbl-soraka: [PASS][23] -> [FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-kbl-soraka/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-kbl-soraka/boot.html - fi-icl-guc: [PASS][25] -> [FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-icl-guc/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-icl-guc/boot.html - fi-cml-s: [PASS][27] -> [FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-cml-s/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-cml-s/boot.html - fi-skl-lmem:[PASS][29] -> [FAIL][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-skl-lmem/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-skl-lmem/boot.html - fi-glk-dsi: [PASS][31] -> [FAIL][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-glk-dsi/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-glk-dsi/boot.html - fi-tgl-y: [PASS][33] -> [FAIL][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-tgl-y/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-tgl-y/boot.html - fi-kbl-guc: [PASS][35] -> [FAIL][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8494/fi-kbl-guc/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17689/fi-kbl-guc/boot.html - fi-kbl-x1275: [PASS][37] ->
