[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hdcp: Add additional R0' wait (rev2)
== Series Details ==
Series: drm/i915/hdcp: Add additional R0' wait (rev2)
URL : https://patchwork.freedesktop.org/series/77439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17731_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17731_full:
### Piglit changes ###
Possible regressions
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-0-int-2drect (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][1] +7 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/pig-icl-1065g7/spec@arb_gpu_shader5@texturegatheroff...@fs-rgba-0-int-2drect.html
New tests
-
New tests have been introduced between CI_DRM_8511_full and
Patchwork_17731_full:
### New Piglit tests (8) ###
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-0-int-2drect:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-0-int-2drect-const:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-1-int-2drect:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-1-int-2drect-const:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-2-int-2drect:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-2-int-2drect-const:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-3-int-2drect:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-3-int-2drect-const:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_17731_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][2] -> [DMESG-WARN][3] ([i915#180])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl4/igt@gem_exec_susp...@basic-s3.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/shard-kbl2/igt@gem_exec_susp...@basic-s3.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][4] -> [INCOMPLETE][5] ([i915#155])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/shard-kbl6/igt@gem_workarou...@suspend-resume-fd.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#300])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl9/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
- shard-skl: [PASS][8] -> [FAIL][9] ([i915#49]) +1 similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl9/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-render.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/shard-skl3/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#180]) +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-apl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/shard-apl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][12] -> [FAIL][13] ([fdo#108145] / [i915#265])
+1 similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/shard-skl3/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109441]) +2 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/shard-iclb5/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][16] -> [FAIL][17] ([i915#31])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl1/igt@kms_setm...@basic.html
[17]:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/hdcp: Avoid duplicate HDCP enables (rev2)
== Series Details == Series: drm/i915/hdcp: Avoid duplicate HDCP enables (rev2) URL : https://patchwork.freedesktop.org/series/77487/ State : failure == Summary == Applying: drm/i915/hdcp: Avoid duplicate HDCP enables error: patch failed: drivers/gpu/drm/drm_atomic_uapi.c:746 error: drivers/gpu/drm/drm_atomic_uapi.c: patch does not apply error: Did you hand edit your patch? It does not apply to blobs recorded in its index. hint: Use 'git am --show-current-patch=diff' to see the failed patch Using index info to reconstruct a base tree... Patch failed at 0001 drm/i915/hdcp: Avoid duplicate HDCP enables When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/hdcp: Add additional R0' wait
On 2020-05-20 at 15:50:15 -0400, Sean Paul wrote:
> On Wed, May 20, 2020 at 9:08 AM Sean Paul wrote:
> >
> > From: Sean Paul
> >
> > We're seeing some R0' mismatches in the field, particularly with
> > repeaters. I'm guessing the (already lenient) 300ms wait time isn't
> > enough for some setups. So add an additional wait when R0' is
> > mismatched.
> >
>
> I think my guess was wrong and now suspect this issue is fixed with
> "drm/i915/hdcp: Avoid duplicate HDCP enables".
>
> While this patch probably still has some value in cases where R0' is
> slow to update, I don't have any concrete examples where it helps.
Sean, completely agree it will help to authenticate the slower hdcp sink,
as this is not breaking the spec too. But could we please introduce extra
delays when we encounter such needs?
As you mentioned, We already have a 3 * 100 mSec,
where spec says HDCP sink should keep the R0' ready after the 100mSec
from aksv write.
-Ram
>
> Sean
>
>
> > Signed-off-by: Sean Paul
> >
> > Changes in v2:
> > - Actually add the delay in R0` wait (Ram)
> > ---
> >
> > Apologies, v1 was generated from a forward port from the CrOS kernel and
> > patch got confused and put the diff in V' wait instead of R0' wait.
> >
> > Pay closer attention, Sean.
> >
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 2cbc4619b4ce..3c2d8c0a6da6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -743,6 +743,9 @@ static int intel_hdcp_auth(struct intel_connector
> > *connector)
> > if (!wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv,
> > cpu_transcoder, port)) &
> > (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
> > break;
> > +
> > + /* Maybe the sink is lazy, give it some more time */
> > + usleep_range(1, 5);
> > }
> >
> > if (i == tries) {
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
> >
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/hdcp: Avoid duplicate HDCP enables
On 2020-05-20 at 15:47:44 -0400, Sean Paul wrote:
> From: Sean Paul
>
> If userspace sets the CP property to DESIRED while it's already ENABLED,
> the driver will try to re-enable HDCP. On some displays, this will
> result in R0' mismatches. I'm guessing this is because the display is
> still sending back Ri instead of re-authenticating.
>
> At any rate, we can fix this inefficiency easily enough by just nooping
> the DESIRED property set if HDCP is already ENABLED.
Sean,
This will skip the hdcp enable.
But at present too we will be getting below WARN_ON from intel_hdcp_enable,
to indicate userspace is going wrong with request.
drm_WARN_ON(_priv->drm,
hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
And if we need to filter this out, could we validate the incoming hdcp request
at
drm_atomic_connector_set_property() itself? No point in going into the
atomic commit without a valid request. something like
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index a1e5e262bae2..d98b2eeae78d 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -746,6 +746,12 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
DRM_DEBUG_KMS("only drivers can set CP Enabled\n");
return -EINVAL;
}
+ if (config->content_protection_property ==
+ DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+ val == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+ DRM_DEBUG_KMS("Redundant req for content protection\n");
+ return -EINVAL;
+ }
state->content_protection = val;
} else if (property == config->hdcp_content_type_property) {
state->hdcp_content_type = val;
-Ram
>
> Signed-off-by: Sean Paul
> ---
>
> I suspect this is the actual root cause I was chasing with
> "drm/i915/hdcp: Add additional R0' wait". I was able to reproduce the
> R0` messages by marking HDCP desired while it was already enabled. This
> _should_ work, but it seems like some displays handle it more graciously
> than others.
>
>
> drivers/gpu/drm/i915/display/intel_hdcp.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 2cbc4619b4ce..f770fe0c5595 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2156,12 +2156,16 @@ void intel_hdcp_atomic_check(struct drm_connector
> *connector,
> }
>
> /*
> - * Nothing to do if the state didn't change, or HDCP was activated since
> - * the last commit. And also no change in hdcp content type.
> + * Nothing to do if content type is unchanged and one of:
> + * - state didn't change
> + * - HDCP was activated since the last commit
> + * - attempting to set to desired while already enabled
>*/
> if (old_cp == new_cp ||
> (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
> - new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) {
> + new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) ||
> + (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
> + new_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED)) {
> if (old_state->hdcp_content_type ==
> new_state->hdcp_content_type)
> return;
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Replace deprecated function in drm_crtc_helper
== Series Details ==
Series: drm: Replace deprecated function in drm_crtc_helper
URL : https://patchwork.freedesktop.org/series/77467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17729_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17729_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl4/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-kbl3/igt@gem_exec_susp...@basic-s3.html
* igt@gem_workarounds@suspend-resume-context:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#165])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl7/igt@gem_workarou...@suspend-resume-context.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-kbl3/igt@gem_workarou...@suspend-resume-context.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#49]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl9/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-skl7/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar
issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-apl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-apl1/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) +2 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-iclb4/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#31])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl1/igt@kms_setm...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-kbl4/igt@kms_setm...@basic.html
Possible fixes
* igt@gem_ctx_persistence@legacy-engines-mixed-process@blt:
- shard-skl: [FAIL][15] ([i915#1528]) -> [PASS][16] +1 similar
issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl3/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-skl2/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html
* {igt@gem_exec_schedule@pi-distinct-iova@bcs0}:
- shard-glk: [FAIL][17] ([i915#859]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-glk6/igt@gem_exec_schedule@pi-distinct-i...@bcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-glk4/igt@gem_exec_schedule@pi-distinct-i...@bcs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][19] ([i915#454]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb6/igt@i915_pm...@dc6-psr.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-iclb2/igt@i915_pm...@dc6-psr.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [DMESG-WARN][21] ([i915#180]) -> [PASS][22] +1
similar issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl3/igt@i915_susp...@fence-restore-untiled.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-kbl1/igt@i915_susp...@fence-restore-untiled.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][23] ([i915#72]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-glk1/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/shard-glk9/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
* {igt@kms_flip@flip-vs-expired-vblank@a-edp1}:
- shard-skl:
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs (rev2)
== Series Details == Series: series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs (rev2) URL : https://patchwork.freedesktop.org/series/77366/ State : success == Summary == CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17728_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17728_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-skl: [PASS][1] -> [TIMEOUT][2] ([i915#1340]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl6/igt@gem_ctx_persiste...@close-replace-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-skl9/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_ctx_persistence@engines-hostile@vcs0: - shard-iclb: [PASS][3] -> [FAIL][4] ([i915#1622]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb3/igt@gem_ctx_persistence@engines-host...@vcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-iclb5/igt@gem_ctx_persistence@engines-host...@vcs0.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#69]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl9/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-skl1/igt@gem_soft...@noreloc-s3.html - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl7/igt@gem_soft...@noreloc-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-kbl1/igt@gem_soft...@noreloc-s3.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-apl8/igt@gem_workarou...@suspend-resume.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-apl6/igt@gem_workarou...@suspend-resume.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][11] -> [INCOMPLETE][12] ([i915#155]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-kbl1/igt@gem_workarou...@suspend-resume-fd.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([i915#1185]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb4/igt@kms_cursor_...@pipe-a-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-iclb3/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][15] -> [FAIL][16] ([IGT#5]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-skl10/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb2/igt@kms_psr@psr2_no_drrs.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-iclb5/igt@kms_psr@psr2_no_drrs.html * igt@kms_setmode@basic: - shard-kbl: [PASS][21] -> [FAIL][22] ([i915#31]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-kbl1/igt@kms_setm...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-kbl2/igt@kms_setm...@basic.html Possible fixes * igt@gem_ctx_persistence@engines-hostile@rcs0: - shard-iclb: [FAIL][23] ([i915#1622]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/shard-iclb3/igt@gem_ctx_persistence@engines-host...@rcs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/shard-iclb5/igt@gem_ctx_persistence@engines-host...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@blt: - shard-skl: [FAIL][25] ([i915#1528]) -> [PASS][26] +1 similar issue [25]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce DG1
== Series Details ==
Series: Introduce DG1
URL : https://patchwork.freedesktop.org/series/77496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17740
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17740/index.html
Known issues
Here are the changes found in Patchwork_17740 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [INCOMPLETE][1] ([i915#1803]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17740/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
Participating hosts (49 -> 41)
--
Missing(8): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc
fi-hsw-4770 fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_8515 -> Patchwork_17740
CI-20190529: 20190529
CI_DRM_8515: 41f9bb782f3bb2f30be09683184bbeecb1fd31bb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5665: c5e5b0ce26fc321591a6d0235c639a1e8ec3cdfa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17740: bc44bd9a82afa9176ff124f0b0772fb0e76f6851 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bc44bd9a82af drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
c2d80f1b6f74 drm/i915/dg1: Add initial DG1 workarounds
78c4ae0c9519 drm/i915/dg1: Load DMC
193af3a3fa98 drm/i915/dg1: enable PORT C/D aka D/E
f4fbfddf277b drm/i915/dg1: map/unmap pll clocks
4a55aec7a032 drm/i915/dg1: provide port/phy mapping for vbt
aa02226ddf5c drm/i915/dg1: Update voltage swing tables for DP
4b16f7612edc drm/i915/dg1: Update comp master/slave relationships for PHYs
abb9e6fb2b34 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
f09b2dfb4b4b drm/i915/dg1: Enable first 2 ports for DG1
1dade3145d62 drm/i915/dg1: Log counter on SLM ECC error
f97a2a7d014c drm/i915/dg1: Handle GRF/IC ECC error irq
cc507b9ee4a3 drm/i915/dg1: gmbus pin mapping
ec9aba37c1bc drm/i915/dg1: invert HPD pins
ee35c0b01372 drm/i915/dg1: add hpd interrupt handling
b71cffc572c1 drm/i915/dg1: Enable DPLL for DG1
a479afd96b2f drm/i915/dg1: Add and setup DPLLs for DG1
8ce1edf79a8b drm/i915/dg1: Add DPLL macros for DG1
1374e1028fdd drm/i915/dg1: Wait for pcode/uncore handshake at startup
ae8f9beefdc3 drm/i915/dg1: add support for the master unit interrupt
c3003b9fc682 drm/i915/dg1: Increase mmio size to 4MB
afeb7e41f94f drm/i915/dg1: Add DG1 power wells
56eeab2dc631 drm/i915/dg1: Define MOCS table for DG1
3dbe2b7cdf3b drm/i915/dg1: Initialize RAWCLK properly
cb1bcd5b7bed drm/i915/dg1: Add fake PCH
40ca1f1b6295 drm/i915/dg1: Add DG1 PCI IDs
5b325ece80ab drm/i915/dg1: add initial DG-1 definitions
24d7987fb08f drm/i915: add pcie snoop flag
4aa7cd7024ae drm/i915: Add has_master_unit_irq flag
84c20511222a drm/i915: make intel_{uncore, de}_rmw() more useful
7afbe335b525 drm/i915/rkl: Add initial workarounds
33974ed52c17 drm/i915/rkl: Handle comp master/slave relationships for PHYs
a33d8a84bd52 drm/i915/rkl: Handle HTI
03cb728ff5e5 drm/i915/rkl: provide port/phy mapping for vbt
470f943d8711 drm/i915/rkl: Setup ports/phys
8eb7430370e7 drm/i915/rkl: Add DDC pin mapping
eb8bcc051bcb drm/i915/rkl: Add DPLL4 support
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17740/index.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce DG1
== Series Details == Series: Introduce DG1 URL : https://patchwork.freedesktop.org/series/77496/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/compiler.h:199:9: warning: context imbalance in 'engines_sample' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1
== Series Details ==
Series: Introduce DG1
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eb8bcc051bcb drm/i915/rkl: Add DPLL4 support
8eb7430370e7 drm/i915/rkl: Add DDC pin mapping
470f943d8711 drm/i915/rkl: Setup ports/phys
03cb728ff5e5 drm/i915/rkl: provide port/phy mapping for vbt
-:20: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#20:
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
total: 0 errors, 1 warnings, 0 checks, 104 lines checked
a33d8a84bd52 drm/i915/rkl: Handle HTI
-:93: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#93: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:274:
+{
+
-:155: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2911:
+#define HDPORT_PHY_USED_DP(phy) REG_BIT(2*phy + 2)
^
-:155: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as
'(phy)' to avoid precedence issues
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2911:
+#define HDPORT_PHY_USED_DP(phy) REG_BIT(2*phy + 2)
-:156: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#156: FILE: drivers/gpu/drm/i915/i915_reg.h:2912:
+#define HDPORT_PHY_USED_HDMI(phy)REG_BIT(2*phy + 1)
^
-:156: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as
'(phy)' to avoid precedence issues
#156: FILE: drivers/gpu/drm/i915/i915_reg.h:2912:
+#define HDPORT_PHY_USED_HDMI(phy)REG_BIT(2*phy + 1)
total: 0 errors, 0 warnings, 5 checks, 116 lines checked
33974ed52c17 drm/i915/rkl: Handle comp master/slave relationships for PHYs
7afbe335b525 drm/i915/rkl: Add initial workarounds
84c20511222a drm/i915: make intel_{uncore, de}_rmw() more useful
-:53: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#53: FILE: drivers/gpu/drm/i915/intel_uncore.h:396:
+static inline u32 intel_uncore_rmw_fw(struct intel_uncore *uncore,
i915_reg_t reg, u32 clear, u32 set)
total: 0 errors, 0 warnings, 1 checks, 42 lines checked
4aa7cd7024ae drm/i915: Add has_master_unit_irq flag
24d7987fb08f drm/i915: add pcie snoop flag
5b325ece80ab drm/i915/dg1: add initial DG-1 definitions
-:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#40: FILE: drivers/gpu/drm/i915/i915_drv.h:1548:
+#define IS_DG1_REVID(p, since, until) \
+ (IS_DG1(p) && IS_REVID(p, since, until))
total: 0 errors, 0 warnings, 1 checks, 54 lines checked
40ca1f1b6295 drm/i915/dg1: Add DG1 PCI IDs
cb1bcd5b7bed drm/i915/dg1: Add fake PCH
3dbe2b7cdf3b drm/i915/dg1: Initialize RAWCLK properly
56eeab2dc631 drm/i915/dg1: Define MOCS table for DG1
afeb7e41f94f drm/i915/dg1: Add DG1 power wells
c3003b9fc682 drm/i915/dg1: Increase mmio size to 4MB
ae8f9beefdc3 drm/i915/dg1: add support for the master unit interrupt
1374e1028fdd drm/i915/dg1: Wait for pcode/uncore handshake at startup
8ce1edf79a8b drm/i915/dg1: Add DPLL macros for DG1
a479afd96b2f drm/i915/dg1: Add and setup DPLLs for DG1
b71cffc572c1 drm/i915/dg1: Enable DPLL for DG1
ee35c0b01372 drm/i915/dg1: add hpd interrupt handling
ec9aba37c1bc drm/i915/dg1: invert HPD pins
cc507b9ee4a3 drm/i915/dg1: gmbus pin mapping
f97a2a7d014c drm/i915/dg1: Handle GRF/IC ECC error irq
1dade3145d62 drm/i915/dg1: Log counter on SLM ECC error
f09b2dfb4b4b drm/i915/dg1: Enable first 2 ports for DG1
abb9e6fb2b34 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
4b16f7612edc drm/i915/dg1: Update comp master/slave relationships for PHYs
aa02226ddf5c drm/i915/dg1: Update voltage swing tables for DP
4a55aec7a032 drm/i915/dg1: provide port/phy mapping for vbt
f4fbfddf277b drm/i915/dg1: map/unmap pll clocks
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible
side-effects?
#244: FILE: drivers/gpu/drm/i915/i915_reg.h:10252:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) *
2)) + (2 * (phy / 2)))
total: 0 errors, 0 warnings, 1 checks, 204 lines checked
193af3a3fa98 drm/i915/dg1: enable PORT C/D aka D/E
78c4ae0c9519 drm/i915/dg1: Load DMC
c2d80f1b6f74 drm/i915/dg1: Add initial DG1 workarounds
bc44bd9a82af drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
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[Intel-gfx] [PATCH 28/37] drm/i915/dg1: Enable first 2 ports for DG1
From: Aditya Swarup
Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.
Cc: Clinton Taylor
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a17319d75b44..e99dc6658b25 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7213,6 +7213,9 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
+ else if (IS_DG1(dev_priv))
+ /* FIXME: Enable only two ports for now */
+ return phy <= PHY_B;
else if (IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_ELKHARTLAKE(dev_priv))
@@ -7225,7 +7228,7 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_ROCKETLAKE(dev_priv) || IS_DG1(dev_priv))
return false;
else if (INTEL_GEN(dev_priv) >= 12)
return phy >= PHY_D && phy <= PHY_I;
@@ -16736,7 +16739,11 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return;
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ /* FIXME: Enable only two ports for now */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_ROCKETLAKE(dev_priv)) {
/*
* If HTI (aka HDPORT) is enabled at boot, it may have taken
* over some of the PHYs and made them unavailable to the
--
2.26.2
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[Intel-gfx] [PATCH 06/37] drm/i915/rkl: Handle comp master/slave relationships for PHYs
From: Matt Roper
Certain combo PHYs act as a compensation master to other PHYs and need
to be initialized with a special irefgen bit in the PORT_COMP_DW8
register. Previously PHY A was the only compensation master (for PHYs
B & C), but RKL adds a fourth PHY which is slaved to PHY C instead.
Bspec: 49291
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Aditya Swarup
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-19-matthew.d.ro...@intel.com
---
.../gpu/drm/i915/display/intel_combo_phy.c| 25 +--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 43d8784f6fa0..77b04bb3ec62 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -234,6 +234,27 @@ static bool ehl_vbt_ddi_d_present(struct drm_i915_private
*i915)
return false;
}
+static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ /*
+* Certain PHYs are connected to compensation resistors and act
+* as masters to other PHYs.
+*
+* ICL,TGL:
+* A(master) -> B(slave), C(slave)
+* RKL:
+* A(master) -> B(slave)
+* C(master) -> D(slave)
+*
+* We must set the IREFGEN bit for any PHY acting as a master
+* to another PHY.
+*/
+ if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+ return true;
+
+ return phy == PHY_A;
+}
+
static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
enum phy phy)
{
@@ -245,7 +266,7 @@ static bool icl_combo_phy_verify_state(struct
drm_i915_private *dev_priv,
ret = cnl_verify_procmon_ref_values(dev_priv, phy);
- if (phy == PHY_A) {
+ if (phy_is_master(dev_priv, phy)) {
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
IREFGEN, IREFGEN);
@@ -356,7 +377,7 @@ static void icl_combo_phys_init(struct drm_i915_private
*dev_priv)
skip_phy_misc:
cnl_set_procmon_ref_values(dev_priv, phy);
- if (phy == PHY_A) {
+ if (phy_is_master(dev_priv, phy)) {
val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
val |= IREFGEN;
intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 26/37] drm/i915/dg1: Handle GRF/IC ECC error irq
From: Fernando Pacheco
The error detection and correction capability
for GRF and instruction cache (IC) will utilize
the new interrupt and error handling infrastructure
for dgfx products. The GFX device can generate
a number of classes of error under the new
infrastructure: correctable, non-fatal, and
fatal errors.
The non-fatal and fatal error classes distinguish
between levels of severity for uncorrectable errors.
All ECC uncorrectable errors will be reported as
fatal to produce the desired system response. Fatal
errors are expected to route as PCIe error messages
which should result in OS issuing a GFX device FLR.
But the option exists to route fatal errors as
interrupts.
Driver will only handle logging of errors. Anything
more will be handled at system level.
For errors that will route as interrupts, three
bits in the Master Interrupt Register will be used
to convey the class of error.
For each class of error:
1. Determine source of error (IP block) by reading
the Device Error Source Register (RW1C) that
corresponds to the class of error being serviced.
2. If the generating IP block is GT, read and log the
GT Error Register (RW1C) that corresponds to the
class of error being serviced. Non-GT errors will
be logged in aggregate for now.
Bspec: 50875
Cc: Paulo Zanoni
Cc: Daniele Ceraolo Spurio
Cc: Fernando Pacheco
Cc: Radhakrishna Sripada
Signed-off-by: Fernando Pacheco
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 121
drivers/gpu/drm/i915/i915_reg.h | 28
2 files changed, 149 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ebc80e8b1599..17e679b910da 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2515,6 +2515,124 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
return IRQ_HANDLED;
}
+static const char *
+hardware_error_type_to_str(const enum hardware_error hw_err)
+{
+ switch (hw_err) {
+ case HARDWARE_ERROR_CORRECTABLE:
+ return "CORRECTABLE";
+ case HARDWARE_ERROR_NONFATAL:
+ return "NONFATAL";
+ case HARDWARE_ERROR_FATAL:
+ return "FATAL";
+ default:
+ return "UNKNOWN";
+ }
+}
+
+static void
+gen12_gt_hw_error_handler(struct drm_i915_private * const i915,
+ const enum hardware_error hw_err)
+{
+ void __iomem * const regs = i915->uncore.regs;
+ const char *hw_err_str = hardware_error_type_to_str(hw_err);
+ u32 other_errors = ~(EU_GRF_ERROR | EU_IC_ERROR);
+ u32 errstat;
+
+ lockdep_assert_held(>irq_lock);
+
+ errstat = raw_reg_read(regs, ERR_STAT_GT_REG(hw_err));
+
+ if (unlikely(!errstat)) {
+ DRM_ERROR("ERR_STAT_GT_REG_%s blank!\n", hw_err_str);
+ return;
+ }
+
+ /*
+* TODO: The GT Non Fatal Error Status Register
+* only has reserved bitfields defined.
+* Remove once there is something to service.
+*/
+ if (hw_err == HARDWARE_ERROR_NONFATAL) {
+ DRM_ERROR("detected Non-Fatal hardware error\n");
+ raw_reg_write(regs, ERR_STAT_GT_REG(hw_err), errstat);
+ return;
+ }
+
+ if (errstat & EU_GRF_ERROR)
+ DRM_ERROR("detected EU GRF %s hardware error\n", hw_err_str);
+
+ if (errstat & EU_IC_ERROR)
+ DRM_ERROR("detected EU IC %s hardware error\n", hw_err_str);
+
+ /*
+* TODO: The remaining GT errors don't have a
+* need for targeted logging at the moment. We
+* still want to log detection of these errors, but
+* let's aggregate them until someone has a need for them.
+*/
+ if (errstat & other_errors)
+ DRM_ERROR("detected hardware error(s) in ERR_STAT_GT_REG_%s:
0x%08x\n",
+ hw_err_str, errstat & other_errors);
+
+ raw_reg_write(regs, ERR_STAT_GT_REG(hw_err), errstat);
+}
+
+static void
+gen12_hw_error_source_handler(struct drm_i915_private * const i915,
+ const enum hardware_error hw_err)
+{
+ void __iomem * const regs = i915->uncore.regs;
+ const char *hw_err_str = hardware_error_type_to_str(hw_err);
+ u32 errsrc;
+
+ spin_lock(>irq_lock);
+ errsrc = raw_reg_read(regs, DEV_ERR_STAT_REG(hw_err));
+
+ if (unlikely(!errsrc)) {
+ DRM_ERROR("DEV_ERR_STAT_REG_%s blank!\n", hw_err_str);
+ goto out_unlock;
+ }
+
+ if (errsrc & DEV_ERR_STAT_GT_ERROR)
+ gen12_gt_hw_error_handler(i915, hw_err);
+
+ if (errsrc & ~DEV_ERR_STAT_GT_ERROR)
+ DRM_ERROR("non-GT hardware error(s) in DEV_ERR_STAT_REG_%s:
0x%08x\n",
+ hw_err_str, errsrc & ~DEV_ERR_STAT_GT_ERROR);
+
+ raw_reg_write(regs, DEV_ERR_STAT_REG(hw_err), errsrc);
+
+out_unlock:
+
[Intel-gfx] [PATCH 33/37] drm/i915/dg1: map/unmap pll clocks
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functions for DG1 since it doesn't share much with ICL/TGL
anymore.
The previous values were correct for PHY A and B since they were using
the same register as before and the bitfields were matching.
Cc: José Roberto de Souza
Cc: Clinton Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 92 +++-
drivers/gpu/drm/i915/display/intel_display.c | 25 +-
drivers/gpu/drm/i915/i915_reg.h | 15
3 files changed, 128 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 13669813e17b..407ed2eb7820 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2778,6 +2778,38 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct
drm_i915_private *dev_priv,
return 0;
}
+static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
+
+ /*
+* If we fail this, something went very wrong: first 2 PLLs should be
+* used by first 2 phys and last 2 PLLs by last phys
+*/
+ if (WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
+ (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
+ return;
+
+ mutex_lock(_priv->dpll.lock);
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ WARN_ON((val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+
+ mutex_unlock(_priv->dpll.lock);
+}
+
static void icl_map_plls_to_ports(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -2815,6 +2847,19 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
mutex_unlock(_priv->dpll.lock);
}
+static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ mutex_lock(_priv->dpll.lock);
+
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+ mutex_unlock(_priv->dpll.lock);
+}
+
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2830,6 +2875,40 @@ static void icl_unmap_plls_to_ports(struct intel_encoder
*encoder)
mutex_unlock(_priv->dpll.lock);
}
+static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
+ u32 port_mask, bool ddi_clk_needed)
+{
+ enum port port;
+ u32 val;
+
+ for_each_port_masked(port, port_mask) {
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ bool ddi_clk_off;
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+
+ if (ddi_clk_needed == !ddi_clk_off)
+ continue;
+
+ /*
+* Punt on the case now where clock is gated, but it would
+* be needed by the port. Something else is really broken then.
+*/
+ if (ddi_clk_needed) {
+ WARN(1, "ddi_clk_needed=%u ddi_clk_off=%u phy=%u\n",
+ddi_clk_needed, ddi_clk_off, phy);
+ continue;
+ }
+
+ DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI
clock, gate it\n",
+phy_name(phy));
+
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ }
+}
+
static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
u32 port_mask, bool ddi_clk_needed)
{
@@ -2912,7 +2991,10 @@ void icl_sanitize_encoder_pll_mapping(struct
intel_encoder *encoder)
ddi_clk_needed =
[Intel-gfx] [PATCH 36/37] drm/i915/dg1: Add initial DG1 workarounds
From: Stuart Summers
DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.
Media power gating should not be applied so we just set it to
nop_init_clock_gating().
BSpec: 53508
Cc: Matt Atwood
Cc: Matt Roper
Cc: Radhakrishna Sripada
Cc: José Roberto de Souza
Signed-off-by: Stuart Summers
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 5 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 ---
drivers/gpu/drm/i915/i915_reg.h | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 17 +++-
5 files changed, 105 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 265183694c62..70e7bf57acda 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5455,8 +5455,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
const struct buddy_page_mask *table;
int i;
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
- /* Wa_1409767108: tgl */
+ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+ /* Wa_1409767108:tgl,dg1 */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 20eea81118da..1b7108b65d7d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2842,8 +2842,8 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0],rkl[all] */
- if (IS_ROCKETLAKE(dev_priv) ||
+ /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 31c5b85a5cf5..b19395f8a001 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -617,6 +617,20 @@ static void tgl_ctx_workarounds_init(struct
intel_engine_cs *engine,
FF_MODE2_TDS_TIMER_128, 0);
}
+static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
+ /* Wa_1409044764 */
+ WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
+
+ /* Wa_22010493298 */
+ WA_SET_BIT_MASKED(HIZ_CHICKEN,
+ DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -629,7 +643,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_ctx_workarounds_init(engine, wal);
+ else if (IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 12))
gen12_ctx_workarounds_init(engine, wal);
@@ -964,10 +980,30 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
}
+static void
+dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
+
+ /* Wa_1607087056:dg1 */
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+ wa_write_or(wal,
+ SLICE_UNIT_LEVEL_CLKGATE,
+ L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+ /* Wa_1409420604:dg1 */
+ if (IS_DG1(i915))
+ wa_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_gt_workarounds_init(i915, wal);
+ else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 12))
gen12_gt_workarounds_init(i915, wal);
@@ -1297,6 +1333,20 @@ static void tgl_whitelist_build(struct intel_engine_cs
*engine)
[Intel-gfx] [PATCH 37/37] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
From: Anusha Srivatsa Bspec asks us to remove the special programming of the SHPD_FILTER_CNT register which we have been doing since CNP+. Bspec: 49305 Cc: Matt Roper Signed-off-by: Anusha Srivatsa Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_irq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index ca35edef492d..d4061d5b4d67 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3274,7 +3274,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, hotplug_irqs = sde_ddi_mask | sde_tc_mask; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); - I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); + if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP) + I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 29/37] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
From: Matt Roper The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec details for that bit tell us that it need only be set for PHY-A and PHY-B. It also turns out that there isn't even an instance of the PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL logic that conditionally skips PHY_MISC usage to DG1 as well. Bspec: 50107 Cc: Aditya Swarup Cc: Clinton Taylor Signed-off-by: Matt Roper Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 77b04bb3ec62..8604d4392e6a 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) * other combo PHY's. */ if (IS_ELKHARTLAKE(i915) || - IS_ROCKETLAKE(i915)) + IS_ROCKETLAKE(i915) || + IS_DG1(i915)) return phy < PHY_C; return true; -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/37] drm/i915/dg1: add support for the master unit interrupt
DG1 has master unit interrupt register which is used to indicate the
correct source of interrupt.
Cc: Radhakrishna Sripada
Cc: Daniele Spurio Ceraolo
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++
drivers/gpu/drm/i915/i915_irq.c | 56 +++--
drivers/gpu/drm/i915/i915_reg.h | 4 +++
3 files changed, 61 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bca036ac6621..4e13f7d7dc5d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -492,6 +492,10 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
seq_printf(m, "PCU interrupt enable:\t%08x\n",
I915_READ(GEN8_PCU_IER));
} else if (INTEL_GEN(dev_priv) >= 11) {
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ seq_printf(m, "Master Unit Interrupt Control: %08x\n",
+ I915_READ(DG1_MSTR_UNIT_INTR));
+
seq_printf(m, "Master Interrupt Control: %08x\n",
I915_READ(GEN11_GFX_MSTR_IRQ));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 95996db46939..2e950387c179 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2583,6 +2583,46 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
gen11_master_intr_enable);
}
+static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
+{
+ u32 val;
+
+ /* First disable interrupts */
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
+
+ /* Get the indication levels and ack the master unit */
+ val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
+ if (unlikely(!val))
+ return 0;
+
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
+
+ /*
+* Now with master disabled, get a sample of level indications
+* for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
+* out as this bit doesn't exist anymore for DG1
+*/
+ val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
+ if (unlikely(!val))
+ return 0;
+
+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
+
+ return val;
+}
+
+static inline void dg1_master_intr_enable(void __iomem * const regs)
+{
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
+}
+
+static irqreturn_t dg1_irq_handler(int irq, void *arg)
+{
+ return __gen11_irq_handler(arg,
+ dg1_master_intr_disable_and_ack,
+ dg1_master_intr_enable);
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -2917,7 +2957,10 @@ static void gen11_irq_reset(struct drm_i915_private
*dev_priv)
{
struct intel_uncore *uncore = _priv->uncore;
- gen11_master_intr_disable(dev_priv->uncore.regs);
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
+ else
+ gen11_master_intr_disable(dev_priv->uncore.regs);
gen11_gt_irq_reset(_priv->gt);
gen11_display_irq_reset(dev_priv);
@@ -3511,8 +3554,13 @@ static void gen11_irq_postinstall(struct
drm_i915_private *dev_priv)
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
- gen11_master_intr_enable(uncore->regs);
- POSTING_READ(GEN11_GFX_MSTR_IRQ);
+ if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
+ dg1_master_intr_enable(uncore->regs);
+ POSTING_READ(DG1_MSTR_UNIT_INTR);
+ } else {
+ gen11_master_intr_enable(uncore->regs);
+ POSTING_READ(GEN11_GFX_MSTR_IRQ);
+ }
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -4037,6 +4085,8 @@ static irq_handler_t intel_irq_handler(struct
drm_i915_private *dev_priv)
else
return i8xx_irq_handler;
} else {
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ return dg1_irq_handler;
if (INTEL_GEN(dev_priv) >= 11)
return gen11_irq_handler;
else if (INTEL_GEN(dev_priv) >= 8)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95e903c01b2b..c1fde43867dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7651,6 +7651,10 @@ enum {
#define GEN11_GT_DW1_IRQ (1 << 1)
#define GEN11_GT_DW0_IRQ (1 << 0)
+#define DG1_MSTR_UNIT_INTR _MMIO(0x190008)
+#define DG1_MSTR_IRQ (1 << 31)
+#define DG1_MSTR_UNIT(u) (1 << (u))
+
#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
#define
[Intel-gfx] [PATCH 32/37] drm/i915/dg1: provide port/phy mapping for vbt
From: Matt Roper
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 9349364f4164..fb7b5e2f033e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1670,7 +1670,7 @@ static enum port dvo_port_to_port(struct drm_i915_private
*dev_priv,
[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping,
@@ -2635,10 +2635,12 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *dev_priv,
aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_D : AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_E : AUX_CH_D;
break;
case DP_AUX_E:
aux_ch = AUX_CH_E;
--
2.26.2
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[Intel-gfx] [PATCH 16/37] drm/i915/dg1: Add DG1 power wells
From: Uma Shankar
Most of TGL power wells are re-used for DG1. However, AUDIO Power
Domain is moved from PG3 to PG0. Handle the change and initialize
power wells with the new power well structure.
Some of the Audio Streaming logic still remains in PW3 so still
it needs to be enabled.
DDIA, DDIB, TC1 and TC2 are the active ports on DG1.
Need to keep Transcoder C and D to Pipe Power wells, this is against
the spec but else hitting unclaimed register warnings (kept the logic
same as TGL)
Bspec: 49182
Cc: Matt Roper
Cc: Anshuman Gupta
Signed-off-by: Uma Shankar
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 201 +-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 72312b67b57a..265183694c62 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define DG1_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_4_POWER_DOMAINS ( \
+ DG1_PW_5_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_3_POWER_DOMAINS ( \
+ DG1_PW_4_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_2_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc
rkl_power_wells[] = {
},
};
+static const struct i915_power_well_desc dg1_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = true,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = _always_on_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
+ .domains = 0,
+ .ops = _power_well_ops,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DC off",
+ .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = _dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ },
+ {
+ .name = "power well 2",
+ .domains = DG1_PW_2_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well 3",
+ .domains = DG1_PW_3_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
[Intel-gfx] [PATCH 22/37] drm/i915/dg1: Enable DPLL for DG1
From: Aditya Swarup
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.
Bspec: 49443, 49206
Cc: Clinton Taylor
Cc: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 ---
drivers/gpu/drm/i915/i915_reg.h | 4 +++
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d764b6438114..d7bf67125b17 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3860,12 +3860,14 @@ static bool combo_pll_get_hw_state(struct
drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv))
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ else if (IS_ELKHARTLAKE(dev_priv) && pll->info->id == DPLL_ID_EHL_DPLL4)
enable_reg = MG_PLL_ENABLE(0);
- }
+ else
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
}
@@ -4063,10 +4065,12 @@ static void icl_pll_enable(struct drm_i915_private
*dev_priv,
static void combo_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
/*
@@ -4076,6 +4080,8 @@ static void combo_pll_enable(struct drm_i915_private
*dev_priv,
*/
pll->wakeref = intel_display_power_get(dev_priv,
POWER_DOMAIN_DPLL_DC_OFF);
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -4175,16 +4181,20 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
icl_pll_disable(dev_priv, pll, enable_reg);
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
pll->wakeref);
return;
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_disable(dev_priv, pll, enable_reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f25720584903..850e029c702a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10209,6 +10209,10 @@ enum skl_power_gate {
#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
_MG_PLL2_ENABLE)
+/* DG1 PLL */
+#define DG1_DPLL_ENABLE(pll)_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+
#define _MG_REFCLKIN_CTL_PORT1 0x16892C
#define _MG_REFCLKIN_CTL_PORT2 0x16992C
#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
--
2.26.2
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[Intel-gfx] [PATCH 15/37] drm/i915/dg1: Define MOCS table for DG1
DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).
Bspec: 45101
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 632e08a4592b..7217c6e2087c 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -280,6 +280,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] =
{
GEN11_MOCS_ENTRIES
};
+static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
+ /* Error */
+ MOCS_ENTRY(0, 0, L3_0_DIRECT),
+
+ /* UC */
+ MOCS_ENTRY(1, 0, L3_1_UC),
+
+ /* Reserved */
+ MOCS_ENTRY(2, 0, L3_0_DIRECT),
+ MOCS_ENTRY(3, 0, L3_0_DIRECT),
+ MOCS_ENTRY(4, 0, L3_0_DIRECT),
+
+ /* WB - L3 */
+ MOCS_ENTRY(5, 0, L3_3_WB),
+ /* WB - L3 50% */
+ MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
+ /* WB - L3 25% */
+ MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
+ /* WB - L3 12.5% */
+ MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
+
+ /* HDC:L1 + L3 */
+ MOCS_ENTRY(48, 0, L3_3_WB),
+ /* HDC:L1 */
+ MOCS_ENTRY(49, 0, L3_1_UC),
+
+ /* HW Reserved */
+ MOCS_ENTRY(60, 0, L3_1_UC),
+ MOCS_ENTRY(61, 0, L3_1_UC),
+ MOCS_ENTRY(62, 0, L3_1_UC),
+ MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -306,7 +339,11 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
{
unsigned int flags;
- if (INTEL_GEN(i915) >= 12) {
+ if (IS_DG1(i915)) {
+ table->size = ARRAY_SIZE(dg1_mocs_table);
+ table->table = dg1_mocs_table;
+ table->n_entries = GEN11_NUM_MOCS_ENTRIES;
+ } else if (INTEL_GEN(i915) >= 12) {
table->size = ARRAY_SIZE(tgl_mocs_table);
table->table = tgl_mocs_table;
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
--
2.26.2
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[Intel-gfx] [PATCH 24/37] drm/i915/dg1: invert HPD pins
From: Clinton A Taylor
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza
Cc: Matt Roper
Signed-off-by: Clinton A Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 4
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index df82d8aa1a27..ebc80e8b1599 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3177,6 +3177,10 @@ static void jsp_hpd_irq_setup(struct drm_i915_private
*dev_priv)
static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
+ intel_de_rmw(dev_priv, SOUTH_CHICKEN1, 0,
+INVERT_DDIA_HPD | INVERT_DDIB_HPD |
+INVERT_DDIC_HPD | INVERT_DDID_HPD);
+
icp_hpd_irq_setup(dev_priv,
SDE_DDI_MASK_DG1, 0,
DG1_DDI_HPD_ENABLE_MASK, 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a9d7b93d79ce..e0bd9e02c3d1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8599,6 +8599,10 @@ enum {
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define INVERT_DDID_HPD (1 << 18)
+#define INVERT_DDIC_HPD (1 << 17)
+#define INVERT_DDIB_HPD (1 << 16)
+#define INVERT_DDIA_HPD (1 << 15)
#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) *
2)))
#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) *
2)))
#define FDI_BC_BIFURCATION_SELECT (1 << 12)
--
2.26.2
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[Intel-gfx] [PATCH 25/37] drm/i915/dg1: gmbus pin mapping
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
The values for VBT are currently not in BSpec. If we assume the latest
is ICL (like we did for TGL), then the mapping is wrong per VBT we can
currently parse.
>From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
mapping as in ICL/TGL.
BSpec: 49311, 49945, 20124
Cc: Aditya Swarup
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +++-
drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +--
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 -
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4f1a72a90b8f..9349364f4164 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1599,7 +1599,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv,
u8 vbt_pin)
const u8 *ddc_pin_map;
int n_entries;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+ return vbt_pin;
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
ddc_pin_map = icp_ddc_pin_map;
n_entries = ARRAY_SIZE(icp_ddc_pin_map);
} else if (HAS_PCH_CNP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a8d119b6b45c..528e48658340 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -90,11 +90,20 @@ static const struct gmbus_pin gmbus_pins_icp[] = {
[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
};
+static const struct gmbus_pin gmbus_pins_dg1[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ return _pins_dg1[pin];
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
return _pins_icp[pin];
else if (HAS_PCH_CNP(dev_priv))
return _pins_cnp[pin];
@@ -113,7 +122,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv,
{
unsigned int size;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ size = ARRAY_SIZE(gmbus_pins_dg1);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
size = ARRAY_SIZE(gmbus_pins_icp);
else if (HAS_PCH_CNP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_cnp);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index a31a98d26882..34f133e2a90d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3100,6 +3100,11 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return GMBUS_PIN_1_BXT + phy;
}
+static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+{
+ return intel_port_to_phy(dev_priv, port) + 1;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3137,7 +3142,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
*encoder)
return ddc_pin;
}
- if (IS_ROCKETLAKE(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
+ else if (IS_ROCKETLAKE(dev_priv))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
--
2.26.2
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[Intel-gfx] [PATCH 31/37] drm/i915/dg1: Update voltage swing tables for DP
From: Matt Roper
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
Bspec: 49291
Cc: Clinton Taylor
Cc: José Roberto de Souza
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index aa22465bb56e..13669813e17b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans
ehl_combo_phy_ddi_translations_dp[] = {
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
};
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[]
= {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A },/* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 },/* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500 900 5.1 */
+ { 0xC, 0x60, 0x3F, 0x00, 0x00 },/* 650 700 0.6 */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 },/* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2[]
= {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A },/* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 },/* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500 900 5.1 */
+ { 0xC, 0x58, 0x3F, 0x00, 0x00 },/* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -965,6 +993,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv,
int type, int rate,
} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
*n_entries =
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
return icl_combo_phy_ddi_translations_edp_hbr2;
+ } else if (IS_DG1(dev_priv) && rate > 27) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
+ return dg1_combo_phy_ddi_translations_dp_hbr2;
+ } else if (IS_DG1(dev_priv)) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
+ return dg1_combo_phy_ddi_translations_dp_hbr;
}
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
--
2.26.2
___
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[Intel-gfx] [PATCH 19/37] drm/i915/dg1: Wait for pcode/uncore handshake at startup
From: Matt Roper
DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this handshaking is complete.
The bspec doesn't give guidance on how long we may need to wait for this
handshaking to complete. For now, let's just set a really long timeout;
if we still don't get a completion status by the end of that timeout,
we'll just continue on and hope for the best.
Bspec: 52065
Cc: Clinton Taylor
Cc: Ville Syrjälä
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_sideband.c | 15 +++
drivers/gpu/drm/i915/intel_sideband.h | 2 ++
4 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 34ee12f3f02d..58b9c6b778aa 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -85,6 +85,7 @@
#include "intel_gvt.h"
#include "intel_memory_region.h"
#include "intel_pm.h"
+#include "intel_sideband.h"
#include "vlv_suspend.h"
static struct drm_driver driver;
@@ -741,6 +742,8 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
*/
intel_dram_detect(dev_priv);
+ intel_pcode_init(dev_priv);
+
intel_bw_init_hw(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1fde43867dc..53b0ad1805f6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9128,6 +9128,9 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define DG1_PCODE_STATUS 0x7E
+#define DG1_CHECK_UNCORE_INIT_STATUS 0x0
+#define DG1_UNCORE_INIT_COMPLETE 0x1
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
#define GEN6_PCODE_DATA_MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 916ccd1c0e96..8b093525240d 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32
mbox, u32 request,
return ret ? ret : status;
#undef COND
}
+
+void intel_pcode_init(struct drm_i915_private *i915)
+{
+ int ret;
+
+ if (!IS_DGFX(i915))
+ return;
+
+ ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
+ DG1_CHECK_UNCORE_INIT_STATUS,
+ DG1_UNCORE_INIT_COMPLETE,
+ DG1_UNCORE_INIT_COMPLETE, 50);
+ if (ret)
+ drm_err(>drm, "Pcode did not report uncore initialization
completion!\n");
+}
diff --git a/drivers/gpu/drm/i915/intel_sideband.h
b/drivers/gpu/drm/i915/intel_sideband.h
index 7fb95745a444..094c7b19c5d4 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private
*i915, u32 mbox,
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
+void intel_pcode_init(struct drm_i915_private *i915);
+
#endif /* _INTEL_SIDEBAND_H */
--
2.26.2
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[Intel-gfx] [PATCH 23/37] drm/i915/dg1: add hpd interrupt handling
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Cc: Imre Deak
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 57 +
drivers/gpu/drm/i915/i915_reg.h | 8 +
2 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2e950387c179..df82d8aa1a27 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
};
+static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
+ [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
+ [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
+};
+
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
struct i915_hotplug *hpd = _priv->hotplug;
@@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv)
else
hpd->hpd = hpd_ilk;
- if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
+ if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
+ (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
return;
- if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ hpd->pch_hpd = hpd_dg1_sde;
+ else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
hpd->pch_hpd = hpd_tgp;
else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
hpd->pch_hpd = hpd_icp;
@@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin
pin, u32 val)
}
}
+static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+ case HPD_PORT_B:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+ case HPD_PORT_D:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+ case HPD_PORT_E:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
+ default:
+ return false;
+ }
+}
+
static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
@@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir)
u32 ddi_hotplug_trigger, tc_hotplug_trigger;
u32 pin_mask = 0, long_mask = 0;
bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
+ bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
- if (HAS_PCH_TGP(dev_priv)) {
+ if (HAS_PCH_DG1(dev_priv)) {
+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
+ ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
+ tc_hotplug_trigger = 0;
+ } else if (HAS_PCH_TGP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
} else if (HAS_PCH_JSP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = 0;
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
@@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir)
INTEL_PCH_TYPE(dev_priv));
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
}
@@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, _mask, _mask,
ddi_hotplug_trigger, dig_hotplug_reg,
dev_priv->hotplug.pch_hpd,
- icp_ddi_port_hotplug_long_detect);
+ ddi_port_hotplug_long_detect);
}
if (tc_hotplug_trigger) {
@@ -3141,6 +3175,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private
*dev_priv)
TGP_DDI_HPD_ENABLE_MASK, 0);
}
+static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ icp_hpd_irq_setup(dev_priv,
+
[Intel-gfx] [PATCH 07/37] drm/i915/rkl: Add initial workarounds
From: Matt Roper
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
Cc: Matt Atwood
Signed-off-by: Matt Roper
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-23-matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +
2 files changed, 59 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 571c36f929bd..20eea81118da 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0] */
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+ /* Wa_14010477008:tgl[a0..c0],rkl[all] */
+ if (IS_ROCKETLAKE(dev_priv) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fa1e15657663..31c5b85a5cf5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -575,8 +575,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs
*engine,
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
}
-static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
-struct i915_wa_list *wal)
+static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
{
/*
* Wa_1409142259:tgl
@@ -586,12 +586,28 @@ static void tgl_ctx_workarounds_init(struct
intel_engine_cs *engine,
* Wa_1409207793:tgl
* Wa_1409178076:tgl
* Wa_1408979724:tgl
+* Wa_14010443199:rkl
+* Wa_14010698770:rkl
*/
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+ /* WaDisableGPGPUMidThreadPreemption:gen12 */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
+}
+
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
/*
-* Wa_1604555607:gen12 and Wa_1608008084:gen12
+* Wa_1604555607:tgl
+*
+* Note that the implementation of this workaround is further modified
+* according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
* FF_MODE2 register will return the wrong value when read. The default
* value for this register is zero for all fields and there are no bit
* masks. So instead of doing a RMW we should just write the TDS timer
@@ -599,11 +615,6 @@ static void tgl_ctx_workarounds_init(struct
intel_engine_cs *engine,
*/
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_TDS_TIMER_128, 0);
-
- /* WaDisableGPGPUMidThreadPreemption:tgl */
- WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
- GEN9_PREEMPT_GPGPU_LEVEL_MASK,
- GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
}
static void
@@ -618,8 +629,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 12))
+ if (IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 12))
+ gen12_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
@@ -927,9 +940,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+gen12_gt_workarounds_init(struct drm_i915_private *i915,
+ struct i915_wa_list *wal)
{
wa_init_mcr(i915, wal);
+}
+
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
/* Wa_1409420604:tgl */
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
@@ -947,8 +967,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
-
[Intel-gfx] [PATCH 03/37] drm/i915/rkl: Setup ports/phys
From: Matt Roper
RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D.
Bspec: 49181
Cc: Imre Deak
Cc: Aditya Swarup
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-14-matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 34
drivers/gpu/drm/i915/i915_reg.h | 4 ++-
2 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 321438ea7077..5b641c1fdfe6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7212,30 +7212,33 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
-
- if (IS_ELKHARTLAKE(dev_priv))
+ else if (IS_ROCKETLAKE(dev_priv))
+ return phy <= PHY_D;
+ else if (IS_ELKHARTLAKE(dev_priv))
return phy <= PHY_C;
-
- if (INTEL_GEN(dev_priv) >= 11)
+ else if (INTEL_GEN(dev_priv) >= 11)
return phy <= PHY_B;
-
- return false;
+ else
+ return false;
}
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (INTEL_GEN(dev_priv) >= 12)
+ if (IS_ROCKETLAKE(dev_priv))
+ return false;
+ else if (INTEL_GEN(dev_priv) >= 12)
return phy >= PHY_D && phy <= PHY_I;
-
- if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+ else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
return phy >= PHY_C && phy <= PHY_F;
-
- return false;
+ else
+ return false;
}
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+ if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+ return (enum phy)port - 1;
+ else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
return PHY_A;
return (enum phy)port;
@@ -16725,7 +16728,12 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_ROCKETLAKE(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
+ intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ } else if (INTEL_GEN(dev_priv) >= 12) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_D);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9d50fe0f375..5ad8b91bc3a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1869,9 +1869,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _ICL_COMBOPHY_A0x162000
#define _ICL_COMBOPHY_B0x6C000
#define _EHL_COMBOPHY_C0x16
+#define _RKL_COMBOPHY_D0x161000
#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
_ICL_COMBOPHY_B, \
- _EHL_COMBOPHY_C)
+ _EHL_COMBOPHY_C, \
+ _RKL_COMBOPHY_D)
/* CNL/ICL Port CL_DW registers */
#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
--
2.26.2
___
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[Intel-gfx] [PATCH 05/37] drm/i915/rkl: Handle HTI
From: Matt Roper
If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage. Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.
Bspec: 49189
Bspec: 53707
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-21-matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 30 ---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 22 ++
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 6
5 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5b641c1fdfe6..a17319d75b44 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
#include "display/intel_ddi.h"
#include "display/intel_dp.h"
#include "display/intel_dp_mst.h"
+#include "display/intel_dpll_mgr.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_gmbus.h"
@@ -16718,6 +16719,13 @@ static void intel_pps_init(struct drm_i915_private
*dev_priv)
intel_pps_unlock_regs_wa(dev_priv);
}
+static bool hti_uses_phy(u32 hdport_state, enum phy phy)
+{
+ return hdport_state & HDPORT_ENABLED &&
+ (hdport_state & HDPORT_PHY_USED_DP(phy) ||
+hdport_state & HDPORT_PHY_USED_HDMI(phy));
+}
+
static void intel_setup_outputs(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
@@ -16729,10 +16737,22 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
return;
if (IS_ROCKETLAKE(dev_priv)) {
- intel_ddi_init(dev_priv, PORT_A);
- intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
- intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ /*
+* If HTI (aka HDPORT) is enabled at boot, it may have taken
+* over some of the PHYs and made them unavailable to the
+* driver. In that case we should skip initializing the
+* corresponding outputs.
+*/
+ u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+
+ if (!hti_uses_phy(hdport_state, PHY_A))
+ intel_ddi_init(dev_priv, PORT_A);
+ if (!hti_uses_phy(hdport_state, PHY_B))
+ intel_ddi_init(dev_priv, PORT_B);
+ if (!hti_uses_phy(hdport_state, PHY_C))
+ intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
+ if (!hti_uses_phy(hdport_state, PHY_D))
+ intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
} else if (INTEL_GEN(dev_priv) >= 12) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
@@ -18263,6 +18283,8 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
intel_dpll_readout_hw_state(dev_priv);
+ dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv);
+
for_each_intel_encoder(dev, encoder) {
pipe = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 196d9eb3a77b..f8078a288379 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -265,6 +265,25 @@ void intel_disable_shared_dpll(const struct
intel_crtc_state *crtc_state)
mutex_unlock(_priv->dpll.lock);
}
+/*
+ * HTI (aka HDPORT) may be using some of the platform's PLL's, making them
+ * unavailable for use.
+ */
+u32 intel_get_hti_plls(struct drm_i915_private *dev_priv)
+{
+
+ u32 hdport_state;
+
+ if (!IS_ROCKETLAKE(dev_priv))
+ return 0;
+
+ hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+ if (!(hdport_state & HDPORT_ENABLED))
+ return 0;
+
+ return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state);
+}
+
static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
@@ -280,6 +299,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
drm_WARN_ON(_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
+ /* Eliminate DPLLs from consideration if reserved by HTI */
+ dpll_mask &= ~dev_priv->hti_pll_mask;
+
for_each_set_bit(i, _mask, I915_NUM_PLLS) {
pll = _priv->dpll.shared_dplls[i];
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index
[Intel-gfx] [PATCH 12/37] drm/i915/dg1: Add DG1 PCI IDs
From: Abdiel Janulgue
Bspec: 44463
Cc: Matthew Auld
Cc: James Ausmus
Cc: Joonas Lahtinen
Cc: Matt Roper
Signed-off-by: Abdiel Janulgue
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
include/drm/i915_pciids.h | 4
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e5a851a2dfe7..f1a3a59093c9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -879,7 +879,7 @@ static const struct intel_device_info rkl_info = {
.has_master_unit_irq = 1, \
.has_snoop_pcie = 1
-static const struct intel_device_info intel_dg1_info = {
+static const struct intel_device_info dg1_info = {
GEN12_DGFX_FEATURES,
PLATFORM(INTEL_DG1),
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
@@ -964,6 +964,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_EHL_IDS(_info),
INTEL_TGL_12_IDS(_info),
INTEL_RKL_IDS(_info),
+ INTEL_DG1_IDS(_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index bc989de2aac2..f44fe822880d 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -614,4 +614,8 @@
INTEL_VGA_DEVICE(0x4C90, info), \
INTEL_VGA_DEVICE(0x4C9A, info)
+/* DG1 */
+#define INTEL_DG1_IDS(info) \
+ INTEL_VGA_DEVICE(0x4905, info)
+
#endif /* _I915_PCIIDS_H */
--
2.26.2
___
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[Intel-gfx] [PATCH 00/37] Introduce DG1
DG1 is a gen12 dgfx platform. This is the first batch of patches to
support it. It also depends on some in-flight patches adding RKL. In
order for this series to be compiled, I'm including them here.
While converting some of these patches to the current
intel_uncore/intel_de APIs I thought it could be useful to return the
previous value. The patch for that is included here, but I ended up
not using and it can be dropped if there is no interest.
Abdiel Janulgue (2):
drm/i915/dg1: add initial DG-1 definitions
drm/i915/dg1: Add DG1 PCI IDs
Aditya Swarup (4):
drm/i915/dg1: Add DPLL macros for DG1
drm/i915/dg1: Add and setup DPLLs for DG1
drm/i915/dg1: Enable DPLL for DG1
drm/i915/dg1: Enable first 2 ports for DG1
Anusha Srivatsa (1):
drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
Clinton A Taylor (1):
drm/i915/dg1: invert HPD pins
Fernando Pacheco (2):
drm/i915/dg1: Handle GRF/IC ECC error irq
drm/i915/dg1: Log counter on SLM ECC error
Lucas De Marchi (9):
drm/i915/rkl: provide port/phy mapping for vbt
drm/i915: make intel_{uncore,de}_rmw() more useful
drm/i915/dg1: Add fake PCH
drm/i915/dg1: Define MOCS table for DG1
drm/i915/dg1: add support for the master unit interrupt
drm/i915/dg1: add hpd interrupt handling
drm/i915/dg1: gmbus pin mapping
drm/i915/dg1: map/unmap pll clocks
drm/i915/dg1: enable PORT C/D aka D/E
Matt Atwood (1):
drm/i915/dg1: Load DMC
Matt Roper (12):
drm/i915/rkl: Add DPLL4 support
drm/i915/rkl: Add DDC pin mapping
drm/i915/rkl: Setup ports/phys
drm/i915/rkl: Handle HTI
drm/i915/rkl: Handle comp master/slave relationships for PHYs
drm/i915/rkl: Add initial workarounds
drm/i915/dg1: Initialize RAWCLK properly
drm/i915/dg1: Wait for pcode/uncore handshake at startup
drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
drm/i915/dg1: Update comp master/slave relationships for PHYs
drm/i915/dg1: Update voltage swing tables for DP
drm/i915/dg1: provide port/phy mapping for vbt
Matthew Auld (1):
drm/i915: add pcie snoop flag
Stuart Summers (2):
drm/i915: Add has_master_unit_irq flag
drm/i915/dg1: Add initial DG1 workarounds
Uma Shankar (1):
drm/i915/dg1: Add DG1 power wells
Venkata Sandeep Dhanalakota (1):
drm/i915/dg1: Increase mmio size to 4MB
drivers/gpu/drm/i915/display/intel_bios.c | 78 --
drivers/gpu/drm/i915/display/intel_cdclk.c| 15 ++
.../gpu/drm/i915/display/intel_combo_phy.c| 28 +-
drivers/gpu/drm/i915/display/intel_csr.c | 19 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 126 -
drivers/gpu/drm/i915/display/intel_de.h | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 94 ++-
.../drm/i915/display/intel_display_power.c| 206 ++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 117 ++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 18 ++
drivers/gpu/drm/i915/display/intel_gmbus.c| 15 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 29 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 39 ++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 159 ---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/i915_irq.c | 249 +-
drivers/gpu/drm/i915/i915_pci.c | 16 +-
drivers/gpu/drm/i915/i915_reg.h | 110 +++-
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 3 +
drivers/gpu/drm/i915/intel_pch.c | 6 +
drivers/gpu/drm/i915/intel_pch.h | 4 +
drivers/gpu/drm/i915/intel_pm.c | 17 +-
drivers/gpu/drm/i915/intel_sideband.c | 15 ++
drivers/gpu/drm/i915/intel_sideband.h | 2 +
drivers/gpu/drm/i915/intel_uncore.c | 4 +
drivers/gpu/drm/i915/intel_uncore.h | 10 +-
include/drm/i915_pciids.h | 4 +
32 files changed, 1285 insertions(+), 131 deletions(-)
--
2.26.2
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[Intel-gfx] [PATCH 21/37] drm/i915/dg1: Add and setup DPLLs for DG1
From: Aditya Swarup
Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks.
Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for
DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1.
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +--
1 file changed, 37 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f8078a288379..d764b6438114 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3528,7 +3528,17 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
return false;
}
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ if (port == PORT_D || port == PORT_E) {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL2) |
+ BIT(DPLL_ID_DG1_DPLL3);
+ } else {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL0) |
+ BIT(DPLL_ID_DG1_DPLL1);
+ }
+ } else if (IS_ROCKETLAKE(dev_priv)) {
dpll_mask =
BIT(DPLL_ID_EHL_DPLL4) |
BIT(DPLL_ID_ICL_DPLL1) |
@@ -3818,7 +3828,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_DG1(dev_priv)) {
+ hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
+ } else if (INTEL_GEN(dev_priv) >= 12) {
hw_state->cfgcr0 = intel_de_read(dev_priv,
TGL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3871,7 +3884,10 @@ static void icl_dpll_write(struct drm_i915_private
*dev_priv,
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_DG1(dev_priv)) {
+ cfgcr0_reg = DG1_DPLL_CFGCR0(id);
+ cfgcr1_reg = DG1_DPLL_CFGCR1(id);
+ } else if (INTEL_GEN(dev_priv) >= 12) {
cfgcr0_reg = TGL_DPLL_CFGCR0(id);
cfgcr1_reg = TGL_DPLL_CFGCR1(id);
} else {
@@ -4317,6 +4333,21 @@ static const struct intel_dpll_mgr rkl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info dg1_plls[] = {
+ { "DPLL 0", _pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
+ { "DPLL 1", _pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
+ { "DPLL 2", _pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+ { "DPLL 3", _pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr dg1_pll_mgr = {
+ .dpll_info = dg1_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4330,7 +4361,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv))
+ dpll_mgr = _pll_mgr;
+ else if (IS_ROCKETLAKE(dev_priv))
dpll_mgr = _pll_mgr;
else if (INTEL_GEN(dev_priv) >= 12)
dpll_mgr = _pll_mgr;
--
2.26.2
___
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[Intel-gfx] [PATCH 09/37] drm/i915: Add has_master_unit_irq flag
From: Stuart Summers
Add flag to differentiate platforms with and without the master
IRQ control bit.
Signed-off-by: Stuart Summers
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bed12799495b..162b1ead88d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1580,6 +1580,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
+#define HAS_MASTER_UNIT_IRQ(dev_priv)
(INTEL_INFO(dev_priv)->has_master_unit_irq)
+
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index c912acd06109..ced979c9b366 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -121,6 +121,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_contexts); \
func(has_logical_ring_elsq); \
func(has_logical_ring_preemption); \
+ func(has_master_unit_irq); \
func(has_pooled_eu); \
func(has_rc6); \
func(has_rc6p); \
--
2.26.2
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[Intel-gfx] [PATCH 35/37] drm/i915/dg1: Load DMC
From: Matt Atwood
Add support to load DMC v2.0.2 on DG1
While we're at it, tweak the TGL and RKL firmware size definition to
follow the convention used in previous platforms. Remove obsolete
commenting.
Bpec: 49230
Cc: Matt Roper
Signed-off-by: Matt Atwood
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_csr.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
b/drivers/gpu/drm/i915/display/intel_csr.c
index 319932b03e88..1f05876620fe 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -38,15 +38,19 @@
* low-power state and comes back to normal.
*/
-#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin"
+#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
+#define DG1_CSR_MAX_FW_SIZEICL_CSR_MAX_FW_SIZE
+MODULE_FIRMWARE(DG1_CSR_PATH);
#define RKL_CSR_PATH "i915/rkl_dmc_ver2_01.bin"
#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
+#define RKL_CSR_MAX_FW_SIZEICL_CSR_MAX_FW_SIZE
MODULE_FIRMWARE(RKL_CSR_PATH);
#define TGL_CSR_PATH "i915/tgl_dmc_ver2_06.bin"
#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 6)
-#define TGL_CSR_MAX_FW_SIZE0x6000
+#define TGL_CSR_MAX_FW_SIZEICL_CSR_MAX_FW_SIZE
MODULE_FIRMWARE(TGL_CSR_PATH);
#define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin"
@@ -686,15 +690,18 @@ void intel_csr_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_csr_runtime_pm_get(dev_priv);
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ csr->fw_path = DG1_CSR_PATH;
+ csr->required_version = DG1_CSR_VERSION_REQUIRED;
+ csr->max_fw_size = DG1_CSR_MAX_FW_SIZE;
+ } else if (IS_ROCKETLAKE(dev_priv)) {
csr->fw_path = RKL_CSR_PATH;
csr->required_version = RKL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ csr->max_fw_size = RKL_CSR_MAX_FW_SIZE;
} else if (INTEL_GEN(dev_priv) >= 12) {
csr->fw_path = TGL_CSR_PATH;
csr->required_version = TGL_CSR_VERSION_REQUIRED;
- /* Allow to load fw via parameter using the last known size */
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ csr->max_fw_size = TGL_CSR_MAX_FW_SIZE;
} else if (IS_GEN(dev_priv, 11)) {
csr->fw_path = ICL_CSR_PATH;
csr->required_version = ICL_CSR_VERSION_REQUIRED;
--
2.26.2
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[Intel-gfx] [PATCH 01/37] drm/i915/rkl: Add DPLL4 support
From: Matt Roper
Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display. Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1. And despite its name, the DPLL4 registers
are offset as if it were DPLL2, so no extra offset handling is needed
either.
Bspec: 49202
Bspec: 49443
Bspec: 50288
Bspec: 50289
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-20-matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 28 +--
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b45185b80bec..196d9eb3a77b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
return false;
}
- if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
+ if (IS_ROCKETLAKE(dev_priv)) {
dpll_mask =
BIT(DPLL_ID_EHL_DPLL4) |
BIT(DPLL_ID_ICL_DPLL1) |
BIT(DPLL_ID_ICL_DPLL0);
- else
+ } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) {
+ dpll_mask =
+ BIT(DPLL_ID_EHL_DPLL4) |
+ BIT(DPLL_ID_ICL_DPLL1) |
+ BIT(DPLL_ID_ICL_DPLL0);
+ } else {
dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
+ }
port_dpll->pll = intel_find_shared_dpll(state, crtc,
_dpll->hw_state,
@@ -4275,6 +4281,20 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info rkl_plls[] = {
+ { "DPLL 0", _pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", _pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "DPLL 4", _pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr rkl_pll_mgr = {
+ .dpll_info = rkl_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4288,7 +4308,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (IS_ROCKETLAKE(dev_priv))
+ dpll_mgr = _pll_mgr;
+ else if (INTEL_GEN(dev_priv) >= 12)
dpll_mgr = _pll_mgr;
else if (IS_ELKHARTLAKE(dev_priv))
dpll_mgr = _pll_mgr;
--
2.26.2
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[Intel-gfx] [PATCH 27/37] drm/i915/dg1: Log counter on SLM ECC error
From: Fernando Pacheco
Correctable and uncorrectable Shared Local Memory (SLM)
ECC errors will be counted in two different Thread Dispatch
Logic (TDL) registers. GuC will receive a message
from TDL when the first correctable/uncorrectable error is
detected by SLM (first after a reset or register clear). This
message is then forwarded to the appropriate severity register.
Correctable errors will route to kernel driver and uncorrectable errors
are expected to route as PCIe Error. Although the option exists to route
both as interrupts.
Service the interrupt and read TDL registers for error count.
Cc: Paulo Zanoni
Cc: Daniele Ceraolo Spurio
Cc: Fernando Pacheco
Cc: Radhakrishna Sripada
Signed-off-by: Fernando Pacheco
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 7 +++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 17e679b910da..ca35edef492d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2536,7 +2536,7 @@ gen12_gt_hw_error_handler(struct drm_i915_private * const
i915,
{
void __iomem * const regs = i915->uncore.regs;
const char *hw_err_str = hardware_error_type_to_str(hw_err);
- u32 other_errors = ~(EU_GRF_ERROR | EU_IC_ERROR);
+ u32 other_errors = ~(EU_GRF_ERROR | EU_IC_ERROR | SLM_ERROR);
u32 errstat;
lockdep_assert_held(>irq_lock);
@@ -2565,6 +2565,14 @@ gen12_gt_hw_error_handler(struct drm_i915_private *
const i915,
if (errstat & EU_IC_ERROR)
DRM_ERROR("detected EU IC %s hardware error\n", hw_err_str);
+ if (errstat & SLM_ERROR) {
+ struct drm_i915_private *dev_priv = i915;
+
+ DRM_ERROR("detected %u SLM %s hardware error(s)\n",
+ I915_READ(SLM_ECC_ERROR_CNTR(hw_err)),
+ hw_err_str);
+ }
+
/*
* TODO: The remaining GT errors don't have a
* need for targeted logging at the moment. We
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 40cb361b4254..b9c142f86611 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7765,6 +7765,13 @@ enum hardware_error {
_ERR_STAT_GT_NONFATAL))
#define EU_GRF_ERROR (1 << 15)
#define EU_IC_ERROR (1 << 14)
+#define SLM_ERROR (1 << 13)
+
+#define _SLM_ECC_ERROR_CNT 0xe7f4
+#define _SLM_UNCORR_ECC_ERROR_CNT 0xe7c0
+#define SLM_ECC_ERROR_CNTR(x) _MMIO((x) == HARDWARE_ERROR_CORRECTABLE
? \
+ _SLM_ECC_ERROR_CNT : \
+ _SLM_UNCORR_ECC_ERROR_CNT)
#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
--
2.26.2
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[Intel-gfx] [PATCH 14/37] drm/i915/dg1: Initialize RAWCLK properly
From: Matt Roper
DG1 always uses a 38.4 MHz rawclk rather and we don't need to read
fuse straps like on CNP+. frequencies on CNP+. Note that register bits
associated with this frequency confusingly use 37 for the divider field
rather than 38 as you might expect.
For simplicity, let's just assume that this 38.4 MHz frequency will hold
true for other future platforms with "fake" PCH south displays and that
the CNP-style behavior will remain for other platforms with a real PCH.
Bspec: 49950
Bspec: 49309
Cc: Aditya Swarup
Cc: Clinton Taylor
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9419a4724357..567c36fc9fd7 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2659,6 +2659,19 @@ void intel_update_cdclk(struct drm_i915_private
*dev_priv)
DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
}
+static int dg1_rawclk(struct drm_i915_private *i915)
+{
+ /*
+* DG1 always uses a 38.4 MHz rawclk. The bspec tells us
+* "Program Numerator=2, Denominator=4, Divider=37 decimal."
+*/
+ intel_de_write(i915, PCH_RAWCLK_FREQ,
+ CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) |
+ ICP_RAWCLK_NUM(2));
+
+ return 38400;
+}
+
static int cnp_rawclk(struct drm_i915_private *dev_priv)
{
u32 rawclk;
@@ -2767,6 +2780,8 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
{
u32 freq;
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ freq = dg1_rawclk(dev_priv);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
--
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[Intel-gfx] [PATCH 08/37] drm/i915: make intel_{uncore, de}_rmw() more useful
Return the old value read so some places of the code can still do the
rmw but add warnings/errors about the value it read.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_de.h | 4 ++--
drivers/gpu/drm/i915/intel_uncore.h | 10 +++---
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h
b/drivers/gpu/drm/i915/display/intel_de.h
index 00da10bf35f5..d5441b1ba2fe 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -42,10 +42,10 @@ intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t
reg, u32 val)
intel_uncore_write_fw(>uncore, reg, val);
}
-static inline void
+static inline u32
intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
{
- intel_uncore_rmw(>uncore, reg, clear, set);
+ return intel_uncore_rmw(>uncore, reg, clear, set);
}
static inline int
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 8d3aa8b9acf9..5da43b56fa11 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -379,8 +379,8 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore,
#define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
#define intel_uncore_posting_read_fw(...)
((void)intel_uncore_read_fw(__VA_ARGS__))
-static inline void intel_uncore_rmw(struct intel_uncore *uncore,
- i915_reg_t reg, u32 clear, u32 set)
+static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,
+ i915_reg_t reg, u32 clear, u32 set)
{
u32 old, val;
@@ -388,9 +388,11 @@ static inline void intel_uncore_rmw(struct intel_uncore
*uncore,
val = (old & ~clear) | set;
if (val != old)
intel_uncore_write(uncore, reg, val);
+
+ return old;
}
-static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
+static inline u32 intel_uncore_rmw_fw(struct intel_uncore *uncore,
i915_reg_t reg, u32 clear, u32 set)
{
u32 old, val;
@@ -399,6 +401,8 @@ static inline void intel_uncore_rmw_fw(struct intel_uncore
*uncore,
val = (old & ~clear) | set;
if (val != old)
intel_uncore_write_fw(uncore, reg, val);
+
+ return old;
}
static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
--
2.26.2
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[Intel-gfx] [PATCH 17/37] drm/i915/dg1: Increase mmio size to 4MB
From: Venkata Sandeep Dhanalakota
On dgfx register range has been extended to go up to 4MB.
Cc: Daniele Ceraolo Spurio
Cc: Michael J. Ruhl
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_uncore.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index a61cb8ca4d50..9150fcda18a1 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1699,11 +1699,15 @@ static int uncore_mmio_setup(struct intel_uncore
*uncore)
* clobbering the GTT which we want ioremap_wc instead. Fortunately,
* the register BAR remains the same size for all the earlier
* generations up to Ironlake.
+* For dgfx chips register range is expanded to 4MB.
*/
if (INTEL_GEN(i915) < 5)
mmio_size = 512 * 1024;
+ else if (IS_DGFX(i915))
+ mmio_size = 4 * 1024 * 1024;
else
mmio_size = 2 * 1024 * 1024;
+
uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
if (uncore->regs == NULL) {
drm_err(>drm, "failed to map registers\n");
--
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[Intel-gfx] [PATCH 11/37] drm/i915/dg1: add initial DG-1 definitions
From: Abdiel Janulgue
Bspec: 33617, 33617
Cc: José Roberto de Souza
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
Cc: Vanshidhar Konda
Cc: Lucas De Marchi
Cc: Aravind Iddamsetty
Cc: Matt Roper
Signed-off-by: Abdiel Janulgue
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/i915_pci.c | 12
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a9846205a5e2..382703a6c17d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1421,6 +1421,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
+#define IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1541,6 +1542,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_RKL_REVID(p, since, until) \
(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
+#define DG1_REVID_A0 0x0
+#define DG1_REVID_B0 0x1
+
+#define IS_DG1_REVID(p, since, until) \
+ (IS_DG1(p) && IS_REVID(p, since, until))
+
#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index be52d1b76b2e..e5a851a2dfe7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -874,9 +874,21 @@ static const struct intel_device_info rkl_info = {
#define GEN12_DGFX_FEATURES \
GEN12_FEATURES, \
+ .memory_regions = REGION_SMEM | REGION_LMEM, \
.is_dgfx = 1, \
+ .has_master_unit_irq = 1, \
.has_snoop_pcie = 1
+static const struct intel_device_info intel_dg1_info = {
+ GEN12_DGFX_FEATURES,
+ PLATFORM(INTEL_DG1),
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .require_force_probe = 1,
+ .engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
+ BIT(VCS0) | BIT(VCS2),
+};
+
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index c245c10c9bee..207244b9a852 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -62,6 +62,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ELKHARTLAKE),
PLATFORM_NAME(TIGERLAKE),
PLATFORM_NAME(ROCKETLAKE),
+ PLATFORM_NAME(DG1),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 4bcaa0d6a9e6..64260faac006 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -81,6 +81,7 @@ enum intel_platform {
/* gen12 */
INTEL_TIGERLAKE,
INTEL_ROCKETLAKE,
+ INTEL_DG1,
INTEL_MAX_PLATFORMS
};
--
2.26.2
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[Intel-gfx] [PATCH 02/37] drm/i915/rkl: Add DDC pin mapping
From: Matt Roper
The pin mapping for the final two outputs varies according to which PCH
is present on the platform: with TGP the pins are remapped into the TC
range, whereas with CMP they stay in the traditional combo output range.
Bspec: 49181
Cc: Aditya Swarup
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-16-matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 010f37240710..a31a98d26882 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3082,6 +3082,24 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return ddc_pin;
}
+static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+{
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+
+ WARN_ON(port == PORT_C);
+
+ /*
+* Pin mapping for RKL depends on which PCH is present. With TGP, the
+* final two outputs use type-c pins, even though they're actually
+* combo outputs. With CMP, the traditional DDI A-D pins are used for
+* all outputs.
+*/
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
+ return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
+
+ return GMBUS_PIN_1_BXT + phy;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3119,7 +3137,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
*encoder)
return ddc_pin;
}
- if (HAS_PCH_MCC(dev_priv))
+ if (IS_ROCKETLAKE(dev_priv))
+ ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
+ else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
--
2.26.2
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[Intel-gfx] [PATCH 13/37] drm/i915/dg1: Add fake PCH
DG1 has the south engine display on the same PCI device. Ideally we
could use HAS_PCH_SPLIT(), but that macro is used all across the code
base to rather signify a range of gens. So add a fake one for DG1 to be
used where needed.
Cc: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_pch.c | 6 ++
drivers/gpu/drm/i915/intel_pch.h | 4
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 102b03d24f90..f148354008f0 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -174,6 +174,12 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
{
struct pci_dev *pch = NULL;
+ /* DG1 has south engine display on the same PCI device */
+ if (IS_DG1(dev_priv)) {
+ dev_priv->pch_type = PCH_DG1;
+ return;
+ }
+
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 3053d1ce398b..06d2cd50af0b 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,9 @@ enum intel_pch {
PCH_JSP,/* Jasper Lake PCH */
PCH_MCC,/* Mule Creek Canyon PCH */
PCH_TGP,/* Tiger Lake PCH */
+
+ /* Fake PCHs, functionality handled on the same PCI dev */
+ PCH_DG1 = 1024,
};
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -56,6 +59,7 @@ enum intel_pch {
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_DG1)
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_JSP)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_MCC)
#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_TGP)
--
2.26.2
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[Intel-gfx] [PATCH 20/37] drm/i915/dg1: Add DPLL macros for DG1
From: Aditya Swarup
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDIC/DDID.
Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.
Bspec: 50288, 50299
Cc: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +
drivers/gpu/drm/i915/i915_reg.h | 17 -
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index ac2238646fe7..fcc048a23560 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -154,6 +154,23 @@ enum intel_dpll_id {
* @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
*/
DPLL_ID_TGL_MGPLL6 = 8,
+
+ /**
+* @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
+*/
+ DPLL_ID_DG1_DPLL0 = 0,
+ /**
+* @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
+*/
+ DPLL_ID_DG1_DPLL1 = 1,
+ /**
+* @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
+*/
+ DPLL_ID_DG1_DPLL2 = 2,
+ /**
+* @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
+*/
+ DPLL_ID_DG1_DPLL3 = 3,
};
#define I915_NUM_PLLS 9
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 53b0ad1805f6..f25720584903 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
+#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
+
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -10422,6 +10423,20 @@ enum skl_power_gate {
_TGL_DPLL1_CFGCR1, \
_TGL_TBTPLL_CFGCR1)
+#define _DG1_DPLL2_CFGCR0 0x16C284
+#define _DG1_DPLL3_CFGCR0 0x16C28C
+#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _DG1_DPLL2_CFGCR0, \
+ _DG1_DPLL3_CFGCR0)
+
+#define _DG1_DPLL2_CFGCR1 0x16C288
+#define _DG1_DPLL3_CFGCR1 0x16C290
+#define DG1_DPLL_CFGCR1(pll)_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _DG1_DPLL2_CFGCR1, \
+ _DG1_DPLL3_CFGCR1)
+
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
#define _DKL_PHY3_BASE 0x16A000
--
2.26.2
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[Intel-gfx] [PATCH 04/37] drm/i915/rkl: provide port/phy mapping for vbt
RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
view, so all DDI/pipe/transcoder register use these indexes to refer to
them. Combo phy and IO functions follow another namespace that we keep
as "enum phy". The VBT in theory would use the DE point of view, but
that does not happen in practice.
Provide a table to convert the child devices to the "correct" port
numbering we use. Now this is the output we get while reading the VBT:
DDIA:
[drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on
[ENCODER:275:DDI A]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port A (VBT)
DDIB:
[drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (platform default)
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on
[ENCODER:291:DDI B]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port B (VBT)
DDI USBC1:
[drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:295:DDI D]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on
[ENCODER:295:DDI D]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x3 for port D (VBT)
DDI USBC2:
[drm:intel_bios_port_aux_ch [i915]] using AUX E for port E (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:306:DDI E]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on
[ENCODER:306:DDI E]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x9 for port E (VBT)
Cc: Clinton Taylor
Cc: Aditya Swarup
Signed-off-by: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-15-matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/display/intel_bios.c | 72 ---
1 file changed, 51 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 839124647202..4f1a72a90b8f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1619,30 +1619,18 @@ static u8 map_ddc_pin(struct drm_i915_private
*dev_priv, u8 vbt_pin)
return 0;
}
-static enum port dvo_port_to_port(u8 dvo_port)
+static enum port __dvo_port_to_port(int n_ports, int n_dvo,
+ const int port_mapping[][3], u8 dvo_port)
{
- /*
-* Each DDI port can have more than one value on the "DVO Port" field,
-* so look for all the possible values for each port.
-*/
- static const int dvo_ports[][3] = {
- [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
- [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
- [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
- [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
- [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
- [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
- [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
- };
enum port port;
int i;
- for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) {
- for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) {
- if (dvo_ports[port][i] == -1)
+ for (port = PORT_A; port < n_ports; port++) {
+ for (i = 0; i < n_dvo; i++) {
+ if (port_mapping[port][i] == -1)
break;
- if (dvo_port == dvo_ports[port][i])
+ if (dvo_port == port_mapping[port][i])
return port;
}
}
@@ -1650,6 +1638,48 @@ static enum port dvo_port_to_port(u8 dvo_port)
return PORT_NONE;
}
+static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
+ u8 dvo_port)
+{
+ /*
+* Each DDI port can have more than one value on the "DVO Port" field,
+* so look for all the possible values for each port.
+*/
+ static const int port_mapping[][3] = {
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+ [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+ [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 },
+ [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
+ [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
+ };
+ /*
+* Bspec lists the ports as A, B, C, D - however internally in our
+* driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
+* registers in Display Engine match the right offsets. Apply the
+* mapping
[Intel-gfx] [PATCH 34/37] drm/i915/dg1: enable PORT C/D aka D/E
For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the index of A, B, D and E. However in some places this is
not true:
- VBT: uses C and D and have to be mapped to D/E
- IO/Combo: uses C and D, but we already differentiate those when
we created the phy vs port distinction.
Ths additional mapping for VBT and phy are already covered in previous
patches, so now we can initialize the DDI as D/E.
Cc: Clinton Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 016f02d912e0..7f4e51ff0d63 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7213,10 +7213,7 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
- else if (IS_DG1(dev_priv))
- /* FIXME: Enable only two ports for now */
- return phy <= PHY_B;
- else if (IS_ROCKETLAKE(dev_priv))
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_ELKHARTLAKE(dev_priv))
return phy <= PHY_C;
@@ -7240,7 +7237,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv,
enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+ if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_D)
return (enum phy)port - 1;
else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
return PHY_A;
@@ -16763,9 +16760,18 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
return;
if (IS_DG1(dev_priv)) {
- /* FIXME: Enable only two ports for now */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
+
+ /*
+* Bspec lists the ports as A, B, C (USBC1) and D (USBC2).
+* However from the Display Engine perspective all registers are
+* actually wired to handle C and D as offsets of D/E. Instead
+* of fighting all our macros for handling them specially for
+* DG1, just call them D/E
+*/
+ intel_ddi_init(dev_priv, PORT_D);
+ intel_ddi_init(dev_priv, PORT_E);
} else if (IS_ROCKETLAKE(dev_priv)) {
/*
* If HTI (aka HDPORT) is enabled at boot, it may have taken
--
2.26.2
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[Intel-gfx] [PATCH 10/37] drm/i915: add pcie snoop flag
From: Matthew Auld
Gen 12 dgfx devices are coherent with system memory even over PCIe.
Therefore supporting coherent userptr should be possible.
Cc: Stuart Summers
Signed-off-by: Matthew Auld
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h| 1 +
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 8b0708708671..0a375befd893 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -757,7 +757,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
int ret;
u32 handle;
- if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv)) {
+ if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv) &&
+ !HAS_SNOOP_PCIE(dev_priv)) {
/* We cannot support coherent userptr objects on hw without
* LLC and broken snooping.
*/
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 162b1ead88d3..a9846205a5e2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1566,6 +1566,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
#define HAS_SNOOP(dev_priv)(INTEL_INFO(dev_priv)->has_snoop)
+#define HAS_SNOOP_PCIE(dev_priv)(INTEL_INFO(dev_priv)->has_snoop_pcie)
#define HAS_EDRAM(dev_priv)((dev_priv)->edram_size_mb)
#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7e3252fbad8e..be52d1b76b2e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -874,7 +874,8 @@ static const struct intel_device_info rkl_info = {
#define GEN12_DGFX_FEATURES \
GEN12_FEATURES, \
- .is_dgfx = 1
+ .is_dgfx = 1, \
+ .has_snoop_pcie = 1
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index ced979c9b366..4bcaa0d6a9e6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -128,6 +128,7 @@ enum intel_ppgtt_type {
func(has_rps); \
func(has_runtime_pm); \
func(has_snoop); \
+ func(has_snoop_pcie); \
func(has_coherent_ggtt); \
func(unfenced_needs_alignment); \
func(hws_needs_physical);
--
2.26.2
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[Intel-gfx] [PATCH 30/37] drm/i915/dg1: Update comp master/slave relationships for PHYs
From: Matt Roper As with RKL, DG1's PHY C acts as a comp master for PHY D. Bspec: 49291 Signed-off-by: Matt Roper Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 8604d4392e6a..2fad4871d4e6 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -243,14 +243,14 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) * * ICL,TGL: * A(master) -> B(slave), C(slave) -* RKL: +* RKL,DG1: * A(master) -> B(slave) * C(master) -> D(slave) * * We must set the IREFGEN bit for any PHY acting as a master * to another PHY. */ - if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C) + if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C) return true; return phy == PHY_A; -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable semaphore inter-engine sync without timeslicing (rev2)
== Series Details ==
Series: drm/i915: Disable semaphore inter-engine sync without timeslicing (rev2)
URL : https://patchwork.freedesktop.org/series/77462/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8509_full -> Patchwork_17726_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17726_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +4 similar
issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-kbl1/igt@gem_workarou...@suspend-resume-fd.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] /
[i915#716])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-apl8/igt@gen9_exec_pa...@allowed-all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-apl8/igt@gen9_exec_pa...@allowed-all.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#1188])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl10/igt@kms_...@bpc-switch-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-skl2/igt@kms_...@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108145] / [i915#265])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109642] / [fdo#111068])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-iclb2/igt@kms_psr2...@frontbuffer.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-iclb5/igt@kms_psr2...@frontbuffer.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) +1 similar
issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
Possible fixes
* {igt@kms_flip@flip-vs-suspend-interruptible@a-dp1}:
- shard-kbl: [DMESG-WARN][13] ([i915#180]) -> [PASS][14] +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-kbl2/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-kbl3/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
* {igt@kms_flip@flip-vs-suspend@a-dp1}:
- shard-apl: [DMESG-WARN][15] ([i915#180]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-apl6/igt@kms_flip@flip-vs-susp...@a-dp1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-apl8/igt@kms_flip@flip-vs-susp...@a-dp1.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][17] ([fdo#108145] / [i915#265]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl4/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][19] ([fdo#109441]) -> [PASS][20] +2 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
Warnings
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][21] ([i915#588]) -> [SKIP][22] ([i915#658])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-iclb2/igt@i915_pm...@dc3co-vpb-simulation.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-iclb5/igt@i915_pm...@dc3co-vpb-simulation.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [FAIL][23] ([fdo#110321] / [fdo#110336]) ->
[TIMEOUT][24] ([i915#1319])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-apl1/igt@kms_content_protect...@atomic-dpms.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17726/shard-apl7/igt@kms_content_protect...@atomic-dpms.html
* igt@kms_content_protection@srm:
- shard-apl:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Trace the CS interrupt (rev7)
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev7)
URL : https://patchwork.freedesktop.org/series/77441/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17739
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17739/index.html
Known issues
Here are the changes found in Patchwork_17739 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [INCOMPLETE][1] ([i915#1803]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17739/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17739/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Participating hosts (49 -> 42)
--
Missing(7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc
fi-hsw-4770 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_8515 -> Patchwork_17739
CI-20190529: 20190529
CI_DRM_8515: 41f9bb782f3bb2f30be09683184bbeecb1fd31bb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5665: c5e5b0ce26fc321591a6d0235c639a1e8ec3cdfa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17739: f2778a4785178622f07b3ea56d6127d6b137e9bd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f2778a478517 drm/i915/gt: Trace the CS interrupt
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17739/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add psr_safest_params
== Series Details ==
Series: drm/i915: Add psr_safest_params
URL : https://patchwork.freedesktop.org/series/77491/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17738
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/index.html
Known issues
Here are the changes found in Patchwork_17738 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2] ([i915#151] /
[i915#1844] / [i915#392])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-bsw-kefka/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/fi-bsw-kefka/igt@i915_pm_...@module-reload.html
- fi-kbl-guc: [PASS][3] -> [FAIL][4] ([i915#579])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-kbl-guc/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/fi-kbl-guc/igt@i915_pm_...@module-reload.html
Possible fixes
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [INCOMPLETE][5] ([i915#1803]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
[i915#1844]: https://gitlab.freedesktop.org/drm/intel/issues/1844
[i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (49 -> 42)
--
Missing(7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-hsw-4770
fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_8515 -> Patchwork_17738
CI-20190529: 20190529
CI_DRM_8515: 41f9bb782f3bb2f30be09683184bbeecb1fd31bb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5665: c5e5b0ce26fc321591a6d0235c639a1e8ec3cdfa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17738: 7f3095d8f257cc9646071b19df534a8a5df7ed60 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7f3095d8f257 drm/i915: Add psr_safest_params
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add psr_safest_params
== Series Details == Series: drm/i915: Add psr_safest_params URL : https://patchwork.freedesktop.org/series/77491/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7f3095d8f257 drm/i915: Add psr_safest_params -:98: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #98: FILE: drivers/gpu/drm/i915/i915_params.c:92: +i915_param_named(psr_safest_params, bool, 0400, + "Replace PSR VBT parameters by the safest and not optimal ones. This " -:99: WARNING:TYPO_SPELLING: 'helpfull' may be misspelled - perhaps 'helpful'? #99: FILE: drivers/gpu/drm/i915/i915_params.c:93: + "is helpfull to detect if PSR issues are related to bad values set in " -:100: WARNING:TYPO_SPELLING: 'paramters' may be misspelled - perhaps 'parameters'? #100: FILE: drivers/gpu/drm/i915/i915_params.c:94: + " VBT. (0=use VBT paramters, 1=use safest parameters)"); total: 0 errors, 2 warnings, 1 checks, 82 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Trace the CS interrupt (rev6)
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev6)
URL : https://patchwork.freedesktop.org/series/77441/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17737
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17737/index.html
Known issues
Here are the changes found in Patchwork_17737 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@objects:
- fi-bwr-2160:[PASS][1] -> [INCOMPLETE][2] ([i915#489])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-bwr-2160/igt@i915_selftest@l...@objects.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17737/fi-bwr-2160/igt@i915_selftest@l...@objects.html
Possible fixes
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [INCOMPLETE][3] ([i915#1803]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17737/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
Participating hosts (49 -> 43)
--
Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_8515 -> Patchwork_17737
CI-20190529: 20190529
CI_DRM_8515: 41f9bb782f3bb2f30be09683184bbeecb1fd31bb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5665: c5e5b0ce26fc321591a6d0235c639a1e8ec3cdfa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17737: 6c33c92ea5aec4b66d3df66cdd18a359d2345a75 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6c33c92ea5ae drm/i915/gt: Trace the CS interrupt
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17737/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add psr_safest_params
This parameter is meant to be used when PSR issues are found as some
issues in the past was due wrong values set in VBT so this would be
a quick and easy way to ask users or for us to check if the issue is
due VBT values.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 37 ++--
drivers/gpu/drm/i915/i915_params.c | 5
drivers/gpu/drm/i915/i915_params.h | 1 +
3 files changed, 34 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index b7a2c102648a..859780853f42 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -426,6 +426,12 @@ static u32 intel_psr1_get_tp_time(struct intel_dp
*intel_dp)
if (INTEL_GEN(dev_priv) >= 11)
val |= EDP_PSR_TP4_TIME_0US;
+ if (i915_modparams.psr_safest_params) {
+ val |= EDP_PSR_TP1_TIME_2500us;
+ val |= EDP_PSR_TP2_TP3_TIME_2500us;
+ goto check_tp3_sel;
+ }
+
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
val |= EDP_PSR_TP1_TIME_0us;
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
@@ -444,6 +450,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
else
val |= EDP_PSR_TP2_TP3_TIME_2500us;
+check_tp3_sel:
if (intel_dp_source_supports_hbr2(intel_dp) &&
drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL;
@@ -495,18 +502,13 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val);
}
-static void hsw_activate_psr2(struct intel_dp *intel_dp)
+static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 val;
-
- val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
-
- val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
- val |= EDP_Y_COORDINATE_ENABLE;
+ u32 val = 0;
- val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
+ if (i915_modparams.psr_safest_params)
+ return EDP_PSR2_TP2_TIME_2500us;
if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
@@ -518,6 +520,23 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
else
val |= EDP_PSR2_TP2_TIME_2500us;
+ return val;
+}
+
+static void hsw_activate_psr2(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 val;
+
+ val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
+
+ val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ val |= EDP_Y_COORDINATE_ENABLE;
+
+ val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
+ val |= intel_psr2_get_tp_time(intel_dp);
+
/*
* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
* recommending keep this bit unset while PSR2 is enabled.
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index add00ec1f787..307e4667fc62 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -88,6 +88,11 @@ i915_param_named_unsafe(enable_psr, int, 0600,
"(0=disabled, 1=enabled) "
"Default: -1 (use per-chip default)");
+i915_param_named(psr_safest_params, bool, 0400,
+ "Replace PSR VBT parameters by the safest and not optimal ones. This "
+ "is helpfull to detect if PSR issues are related to bad values set in "
+ " VBT. (0=use VBT paramters, 1=use safest parameters)");
+
i915_param_named_unsafe(force_probe, charp, 0400,
"Force probe the driver for specified devices. "
"See CONFIG_DRM_I915_FORCE_PROBE for details.");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 45323732f099..2a99c908c7c8 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -53,6 +53,7 @@ struct drm_printer;
param(int, enable_dc, -1, 0400) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
+ param(bool, psr_safest_params, false, 0600) \
param(int, disable_power_well, -1, 0400) \
param(int, enable_ips, 1, 0600) \
param(int, invert_brightness, 0, 0600) \
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Cancel the flush worker more thoroughly
== Series Details ==
Series: drm/i915/gt: Cancel the flush worker more thoroughly
URL : https://patchwork.freedesktop.org/series/77490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17736
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17736/index.html
Known issues
Here are the changes found in Patchwork_17736 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@active:
- fi-kbl-x1275: [PASS][1] -> [DMESG-FAIL][2] ([i915#666])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-kbl-x1275/igt@i915_selftest@l...@active.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17736/fi-kbl-x1275/igt@i915_selftest@l...@active.html
- fi-bdw-5557u: [PASS][3] -> [DMESG-FAIL][4] ([i915#765])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-bdw-5557u/igt@i915_selftest@l...@active.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17736/fi-bdw-5557u/igt@i915_selftest@l...@active.html
Possible fixes
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [INCOMPLETE][5] ([i915#1803]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17736/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
[i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765
Participating hosts (49 -> 43)
--
Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_8515 -> Patchwork_17736
CI-20190529: 20190529
CI_DRM_8515: 41f9bb782f3bb2f30be09683184bbeecb1fd31bb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5665: c5e5b0ce26fc321591a6d0235c639a1e8ec3cdfa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17736: a3dd258ba77810fb22af04b0e198f8a1cb0bf11b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a3dd258ba778 drm/i915/gt: Cancel the flush worker more thoroughly
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17736/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Cancel the flush worker more thoroughly
== Series Details == Series: drm/i915/gt: Cancel the flush worker more thoroughly URL : https://patchwork.freedesktop.org/series/77490/ State : warning == Summary == $ dim checkpatch origin/drm-tip a3dd258ba778 drm/i915/gt: Cancel the flush worker more thoroughly -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: <0> [314.146044] i915_mod-13212 299799443us : intel_gt_fini_buffer_pool: intel_gt_fini_buffer_pool:227 GEM_BUG_ON(!list_empty(>cache_list[n])) total: 0 errors, 1 warnings, 0 checks, 10 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Trace the CS interrupt (rev5)
== Series Details ==
Series: drm/i915/gt: Trace the CS interrupt (rev5)
URL : https://patchwork.freedesktop.org/series/77441/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17735
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17735/index.html
Known issues
Here are the changes found in Patchwork_17735 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [INCOMPLETE][1] ([i915#1803]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17735/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
Participating hosts (49 -> 43)
--
Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_8515 -> Patchwork_17735
CI-20190529: 20190529
CI_DRM_8515: 41f9bb782f3bb2f30be09683184bbeecb1fd31bb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5665: c5e5b0ce26fc321591a6d0235c639a1e8ec3cdfa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17735: 53dd02d91ffa9bb6ac734defd6489f34b12cb45e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
53dd02d91ffa drm/i915/gt: Trace the CS interrupt
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17735/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/22] drm/i915/gem: Suppress some random warnings
== Series Details == Series: series starting with [01/22] drm/i915/gem: Suppress some random warnings URL : https://patchwork.freedesktop.org/series/77459/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8509_full -> Patchwork_17724_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17724_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17724_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17724_full: ### CI changes ### Possible regressions * boot: - shard-skl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) -> ([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [FAIL][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl9/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl9/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl7/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl6/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl6/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl5/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl3/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl3/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl2/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl2/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl10/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl10/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl1/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8509/shard-skl1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl10/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl5/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl4/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl3/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17724/shard-skl3/boot.html
[Intel-gfx] [PATCH] drm/i915/gt: Cancel the flush worker more thoroughly
Since the worker may rearm, we currently are only guaranteed to flush
the work if we cancel the timer. If the work was running at the time we
try and cancel it, we will wait for it to complete, but it may leave
items in the pool and requeue the work. If we rearrange the immediate
discard of the pool then cancel the work, we know that the work cannot
rearm and so our flush will be final.
<0> [314.146044] i915_mod-13212 299799443us :
intel_gt_fini_buffer_pool: intel_gt_fini_buffer_pool:227
GEM_BUG_ON(!list_empty(>cache_list[n]))
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
index 1495054a4305..77487732d53f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
@@ -212,8 +212,8 @@ void intel_gt_flush_buffer_pool(struct intel_gt *gt)
{
struct intel_gt_buffer_pool *pool = >buffer_pool;
- if (cancel_delayed_work_sync(>work))
- pool_free_imm(pool);
+ pool_free_imm(pool);
+ cancel_delayed_work_sync(>work);
}
void intel_gt_fini_buffer_pool(struct intel_gt *gt)
--
2.27.0.rc0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hdcp: Avoid duplicate HDCP enables
== Series Details ==
Series: drm/i915/hdcp: Avoid duplicate HDCP enables
URL : https://patchwork.freedesktop.org/series/77487/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8515 -> Patchwork_17734
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17734/index.html
Known issues
Here are the changes found in Patchwork_17734 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@execlists:
- {fi-tgl-dsi}: [INCOMPLETE][1] ([i915#1803]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17734/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
Participating hosts (49 -> 44)
--
Missing(5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_8515 -> Patchwork_17734
CI-20190529: 20190529
CI_DRM_8515: 41f9bb782f3bb2f30be09683184bbeecb1fd31bb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5665: c5e5b0ce26fc321591a6d0235c639a1e8ec3cdfa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17734: db5d2afbad0bfe5323ee6ec2751931912e80af74 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
db5d2afbad0b drm/i915/hdcp: Avoid duplicate HDCP enables
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17734/index.html
___
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[Intel-gfx] [CI] drm/i915/gt: Trace the CS interrupt
We have traces for the semaphore and the error, but not the far more
frequent CS interrupts. This is likely to be too much, but for the
purpose of live_unlite_preempt it may answer a question or two.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
drivers/gpu/drm/i915/gt/intel_lrc.c| 4
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 0cc7dd54f4f9..4291d55c5457 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -48,8 +48,12 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
tasklet = true;
}
- if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
+ if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
+ ENGINE_TRACE(engine, "CS: %x %x\n",
+ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI),
+ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_LO));
tasklet = true;
+ }
if (iir & GT_RENDER_USER_INTERRUPT) {
intel_engine_signal_breadcrumbs(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index de5be57ed6d2..87103f19c91f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3105,6 +3105,10 @@ static void execlists_submission_tasklet(unsigned long
data)
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
bool timeout = preempt_timeout(engine);
+ ENGINE_TRACE(engine, "head:%d, tail:%d\n",
+engine->execlists.csb_head,
+READ_ONCE(*engine->execlists.csb_write));
+
process_csb(engine);
if (unlikely(READ_ONCE(engine->execlists.error_interrupt))) {
--
2.20.1
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for Consider DBuf bandwidth when calculating CDCLK (rev15)
== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev15) URL : https://patchwork.freedesktop.org/series/74739/ State : success == Summary == CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17718_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17718_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume-fd: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([i915#1185]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-iclb6/igt@gem_workarou...@suspend-resume-fd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-iclb3/igt@gem_workarou...@suspend-resume-fd.html - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#716]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl7/igt@gen9_exec_pa...@allowed-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-skl3/igt@gen9_exec_pa...@allowed-all.html * igt@i915_selftest@live@blt: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#750]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-tglb7/igt@i915_selftest@l...@blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-tglb3/igt@i915_selftest@l...@blt.html * igt@i915_selftest@live@execlists: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#1874]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl4/igt@i915_selftest@l...@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-skl4/igt@i915_selftest@l...@execlists.html * igt@kms_cursor_crc@pipe-c-cursor-128x128-sliding: - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([i915#58] / [k.org#198133]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-glk8/igt@kms_cursor_...@pipe-c-cursor-128x128-sliding.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-glk9/igt@kms_cursor_...@pipe-c-cursor-128x128-sliding.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#1188]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl3/igt@kms_...@bpc-switch-dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-skl2/igt@kms_...@bpc-switch-dpms.html * igt@kms_hdr@bpc-switch-suspend: - shard-kbl: [PASS][15] -> [INCOMPLETE][16] ([i915#155]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-kbl2/igt@kms_...@bpc-switch-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-kbl2/igt@kms_...@bpc-switch-suspend.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#31]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl3/igt@kms_setm...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-skl5/igt@kms_setm...@basic.html * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-apl8/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17718/shard-apl4/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html Possible fixes * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen: - shard-skl: [FAIL][25] ([i915#54]) -> [PASS][26] +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html [26]:
Re: [Intel-gfx] [PATCH v2] drm/i915/hdcp: Add additional R0' wait
On Wed, May 20, 2020 at 9:08 AM Sean Paul wrote:
>
> From: Sean Paul
>
> We're seeing some R0' mismatches in the field, particularly with
> repeaters. I'm guessing the (already lenient) 300ms wait time isn't
> enough for some setups. So add an additional wait when R0' is
> mismatched.
>
I think my guess was wrong and now suspect this issue is fixed with
"drm/i915/hdcp: Avoid duplicate HDCP enables".
While this patch probably still has some value in cases where R0' is
slow to update, I don't have any concrete examples where it helps.
Sean
> Signed-off-by: Sean Paul
>
> Changes in v2:
> - Actually add the delay in R0` wait (Ram)
> ---
>
> Apologies, v1 was generated from a forward port from the CrOS kernel and
> patch got confused and put the diff in V' wait instead of R0' wait.
>
> Pay closer attention, Sean.
>
> drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 2cbc4619b4ce..3c2d8c0a6da6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -743,6 +743,9 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> if (!wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv,
> cpu_transcoder, port)) &
> (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
> break;
> +
> + /* Maybe the sink is lazy, give it some more time */
> + usleep_range(1, 5);
> }
>
> if (i == tries) {
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
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[Intel-gfx] [PATCH] drm/i915/hdcp: Avoid duplicate HDCP enables
From: Sean Paul
If userspace sets the CP property to DESIRED while it's already ENABLED,
the driver will try to re-enable HDCP. On some displays, this will
result in R0' mismatches. I'm guessing this is because the display is
still sending back Ri instead of re-authenticating.
At any rate, we can fix this inefficiency easily enough by just nooping
the DESIRED property set if HDCP is already ENABLED.
Signed-off-by: Sean Paul
---
I suspect this is the actual root cause I was chasing with
"drm/i915/hdcp: Add additional R0' wait". I was able to reproduce the
R0` messages by marking HDCP desired while it was already enabled. This
_should_ work, but it seems like some displays handle it more graciously
than others.
drivers/gpu/drm/i915/display/intel_hdcp.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 2cbc4619b4ce..f770fe0c5595 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2156,12 +2156,16 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
}
/*
-* Nothing to do if the state didn't change, or HDCP was activated since
-* the last commit. And also no change in hdcp content type.
+* Nothing to do if content type is unchanged and one of:
+* - state didn't change
+* - HDCP was activated since the last commit
+* - attempting to set to desired while already enabled
*/
if (old_cp == new_cp ||
(old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
-new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) {
+new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) ||
+ (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+new_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED)) {
if (old_state->hdcp_content_type ==
new_state->hdcp_content_type)
return;
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ehl: Wa_22010271021 (rev2)
On Wed, 2020-05-20 at 11:45 +, Patchwork wrote: > == Series Details == > > Series: drm/i915/ehl: Wa_22010271021 (rev2) > URL : https://patchwork.freedesktop.org/series/77428/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17716_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17716_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17716_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_17716_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: > - shard-kbl: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-kbl6/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-kbl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html > > Not related to this changes. Merged, thanks for the patch. > > Known issues > > > Here are the changes found in Patchwork_17716_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_softpin@noreloc-s3: > - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-apl4/igt@gem_soft...@noreloc-s3.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-apl4/igt@gem_soft...@noreloc-s3.html > > * igt@gem_workarounds@suspend-resume-fd: > - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 > similar issue >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html > > * igt@kms_cursor_legacy@flip-vs-cursor-legacy: > - shard-skl: [PASS][7] -> [FAIL][8] ([IGT#5]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-skl2/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html > > * igt@kms_hdr@bpc-switch-dpms: > - shard-skl: [PASS][9] -> [FAIL][10] ([i915#1188]) +1 similar > issue >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl3/igt@kms_...@bpc-switch-dpms.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-skl2/igt@kms_...@bpc-switch-dpms.html > > * igt@kms_hdr@bpc-switch-suspend: > - shard-kbl: [PASS][11] -> [INCOMPLETE][12] ([i915#155]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-kbl2/igt@kms_...@bpc-switch-suspend.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-kbl4/igt@kms_...@bpc-switch-suspend.html > > * igt@kms_psr@psr2_primary_page_flip: > - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +2 similar > issues >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html > > * igt@kms_setmode@basic: > - shard-skl: [PASS][15] -> [FAIL][16] ([i915#31]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl3/igt@kms_setm...@basic.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-skl8/igt@kms_setm...@basic.html > > * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: > - shard-snb: [PASS][17] -> [DMESG-WARN][18] ([i915#42]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-snb2/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-snb4/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html > > > Possible fixes > > * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen: > - shard-skl: [FAIL][19] ([i915#54]) -> [PASS][20] +1 similar > issue >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17716/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html > > *
Re: [Intel-gfx] [PATCH 3/3] misc/habalabs: don't set default fence_ops->wait
On Wed, May 20, 2020 at 9:05 PM Daniel Vetter wrote: > > On Thu, May 14, 2020 at 02:38:38PM +0300, Oded Gabbay wrote: > > On Tue, May 12, 2020 at 9:12 AM Daniel Vetter > > wrote: > > > > > > On Tue, May 12, 2020 at 4:14 AM Dave Airlie wrote: > > > > > > > > On Mon, 11 May 2020 at 19:37, Oded Gabbay wrote: > > > > > > > > > > On Mon, May 11, 2020 at 12:11 PM Daniel Vetter > > > > > wrote: > > > > > > > > > > > > It's the default. > > > > > Thanks for catching that. > > > > > > > > > > > > > > > > > Also so much for "we're not going to tell the graphics people how to > > > > > > review their code", dma_fence is a pretty core piece of gpu driver > > > > > > infrastructure. And it's very much uapi relevant, including piles of > > > > > > corresponding userspace protocols and libraries for how to pass > > > > > > these > > > > > > around. > > > > > > > > > > > > Would be great if habanalabs would not use this (from a quick look > > > > > > it's not needed at all), since open source the userspace and playing > > > > > > by the usual rules isn't on the table. If that's not possible > > > > > > (because > > > > > > it's actually using the uapi part of dma_fence to interact with gpu > > > > > > drivers) then we have exactly what everyone promised we'd want to > > > > > > avoid. > > > > > > > > > > We don't use the uapi parts, we currently only using the fencing and > > > > > signaling ability of this module inside our kernel code. But maybe I > > > > > didn't understand what you request. You want us *not* to use this > > > > > well-written piece of kernel code because it is only used by graphics > > > > > drivers ? > > > > > I'm sorry but I don't get this argument, if this is indeed what you > > > > > meant. > > > > > > > > We would rather drivers using a feature that has requirements on > > > > correct userspace implementations of the feature have a userspace that > > > > is open source and auditable. > > > > > > > > Fencing is tricky, cross-device fencing is really tricky, and having > > > > the ability for a closed userspace component to mess up other people's > > > > drivers, think i915 shared with closed habana userspace and shared > > > > fences, decreases ability to debug things. > > > > > > > > Ideally we wouldn't offer users known untested/broken scenarios, so > > > > yes we'd prefer that drivers that intend to expose a userspace fencing > > > > api around dma-fence would adhere to the rules of the gpu drivers. > > > > > > > > I'm not say you have to drop using dma-fence, but if you move towards > > > > cross-device stuff I believe other drivers would be correct in > > > > refusing to interact with fences from here. > > > > > > The flip side is if you only used dma-fence.c "because it's there", > > > and not because it comes with an uapi attached and a cross-driver > > > kernel internal contract for how to interact with gpu drivers, then > > > there's really not much point in using it. It's a custom-rolled > > > wait_queue/event thing, that's all. Without the gpu uapi and gpu > > > cross-driver contract it would be much cleaner to just use wait_queue > > > directly, and that's a construct all kernel developers understand, not > > > just gpu folks. From a quick look at least habanalabs doesn't use any > > > of these uapi/cross-driver/gpu bits. > > > -Daniel > > > > Hi Daniel, > > I want to say explicitly that we don't use the dma-buf uapi parts, nor > > we intend to use them to communicate with any GPU device. We only use > > it as simple completion mechanism as it was convenient to use. > > I do understand I can exchange that mechanism with a simpler one, and > > I will add an internal task to do it (albeit not in a very high > > priority) and upstream it, its just that it is part of our data path > > so we need to thoroughly validate it first. > > Sounds good. > > Wrt merging this patch here, can you include that in one of your next > pulls? Or should I toss it entirely, waiting for you to remove dma_fence > outright? I'll include it in the next pull. Thanks, Oded > > Thanks, Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] misc/habalabs: don't set default fence_ops->wait
On Thu, May 14, 2020 at 02:38:38PM +0300, Oded Gabbay wrote: > On Tue, May 12, 2020 at 9:12 AM Daniel Vetter wrote: > > > > On Tue, May 12, 2020 at 4:14 AM Dave Airlie wrote: > > > > > > On Mon, 11 May 2020 at 19:37, Oded Gabbay wrote: > > > > > > > > On Mon, May 11, 2020 at 12:11 PM Daniel Vetter > > > > wrote: > > > > > > > > > > It's the default. > > > > Thanks for catching that. > > > > > > > > > > > > > > Also so much for "we're not going to tell the graphics people how to > > > > > review their code", dma_fence is a pretty core piece of gpu driver > > > > > infrastructure. And it's very much uapi relevant, including piles of > > > > > corresponding userspace protocols and libraries for how to pass these > > > > > around. > > > > > > > > > > Would be great if habanalabs would not use this (from a quick look > > > > > it's not needed at all), since open source the userspace and playing > > > > > by the usual rules isn't on the table. If that's not possible (because > > > > > it's actually using the uapi part of dma_fence to interact with gpu > > > > > drivers) then we have exactly what everyone promised we'd want to > > > > > avoid. > > > > > > > > We don't use the uapi parts, we currently only using the fencing and > > > > signaling ability of this module inside our kernel code. But maybe I > > > > didn't understand what you request. You want us *not* to use this > > > > well-written piece of kernel code because it is only used by graphics > > > > drivers ? > > > > I'm sorry but I don't get this argument, if this is indeed what you > > > > meant. > > > > > > We would rather drivers using a feature that has requirements on > > > correct userspace implementations of the feature have a userspace that > > > is open source and auditable. > > > > > > Fencing is tricky, cross-device fencing is really tricky, and having > > > the ability for a closed userspace component to mess up other people's > > > drivers, think i915 shared with closed habana userspace and shared > > > fences, decreases ability to debug things. > > > > > > Ideally we wouldn't offer users known untested/broken scenarios, so > > > yes we'd prefer that drivers that intend to expose a userspace fencing > > > api around dma-fence would adhere to the rules of the gpu drivers. > > > > > > I'm not say you have to drop using dma-fence, but if you move towards > > > cross-device stuff I believe other drivers would be correct in > > > refusing to interact with fences from here. > > > > The flip side is if you only used dma-fence.c "because it's there", > > and not because it comes with an uapi attached and a cross-driver > > kernel internal contract for how to interact with gpu drivers, then > > there's really not much point in using it. It's a custom-rolled > > wait_queue/event thing, that's all. Without the gpu uapi and gpu > > cross-driver contract it would be much cleaner to just use wait_queue > > directly, and that's a construct all kernel developers understand, not > > just gpu folks. From a quick look at least habanalabs doesn't use any > > of these uapi/cross-driver/gpu bits. > > -Daniel > > Hi Daniel, > I want to say explicitly that we don't use the dma-buf uapi parts, nor > we intend to use them to communicate with any GPU device. We only use > it as simple completion mechanism as it was convenient to use. > I do understand I can exchange that mechanism with a simpler one, and > I will add an internal task to do it (albeit not in a very high > priority) and upstream it, its just that it is part of our data path > so we need to thoroughly validate it first. Sounds good. Wrt merging this patch here, can you include that in one of your next pulls? Or should I toss it entirely, waiting for you to remove dma_fence outright? Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/writeback: don't set fence->ops to default
On Mon, May 11, 2020 at 06:12:32PM +, Ruhl, Michael J wrote:
> >-Original Message-
> >From: dri-devel On Behalf Of
> >Daniel Vetter
> >Sent: Monday, May 11, 2020 5:12 AM
> >To: LKML
> >Cc: David Airlie ; Daniel Vetter ;
> >Intel Graphics Development ; DRI
> >Development ; Thomas Zimmermann
> >; Vetter, Daniel
> >Subject: [PATCH 1/3] drm/writeback: don't set fence->ops to default
> >
> >It's the default.
>
> I can get behind that.
>
> Reviewed-by: Michael J. Ruhl
Applied to drm-misc-next, thanks for reviewing.
-Daniel
>
> >Signed-off-by: Daniel Vetter
> >Cc: Maarten Lankhorst
> >Cc: Maxime Ripard
> >Cc: Thomas Zimmermann
> >Cc: David Airlie
> >Cc: Daniel Vetter
> >---
> > drivers/gpu/drm/drm_writeback.c | 1 -
> > 1 file changed, 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/drm_writeback.c
> >b/drivers/gpu/drm/drm_writeback.c
> >index 43d9e3bb3a94..dccf4504f1bb 100644
> >--- a/drivers/gpu/drm/drm_writeback.c
> >+++ b/drivers/gpu/drm/drm_writeback.c
> >@@ -108,7 +108,6 @@ static const struct dma_fence_ops
> >drm_writeback_fence_ops = {
> > .get_driver_name = drm_writeback_fence_get_driver_name,
> > .get_timeline_name = drm_writeback_fence_get_timeline_name,
> > .enable_signaling = drm_writeback_fence_enable_signaling,
> >-.wait = dma_fence_default_wait,
> > };
> >
> > static int create_writeback_properties(struct drm_device *dev)
> >--
> >2.26.2
> >
> >___
> >dri-devel mailing list
> >dri-de...@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
On Wed, May 20, 2020 at 11:30:25AM +0200, Borislav Petkov wrote: On Tue, May 19, 2020 at 04:57:27PM -0700, Lucas De Marchi wrote: The following files are outside of i915 maintenance scope: arch/x86/kernel/early-quirks.c Can we get an ack? Acked-by: Borislav Petkov Going forward, for simple changes like this, do you prefer to still ack on it or should we just apply to our tree? Well, we are very quickly to give an ACK for trivial stuff like that if we get CCed upfront on the patch. It keeps us aware of what's being changed outside of tip. that works, thanks for quick reply and ack. Lucas De Marchi Thx. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Verify timeslicing between submit-fence
Use a spinner to create a fence, and then use that as to synchronise
another batch to cancel the spinner.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_exec_schedule.c | 121 +++--
1 file changed, 116 insertions(+), 5 deletions(-)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 62e387cc1..0a7deb5a1 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -65,6 +65,11 @@
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
+static unsigned int offset_in_page(void *addr)
+{
+ return (uintptr_t)addr & 4095;
+}
+
static inline
uint32_t __sync_read_u32(int fd, uint32_t handle, uint64_t offset)
{
@@ -670,6 +675,110 @@ static void lateslice(int i915, unsigned int engine)
igt_spin_free(i915, spin[1]);
}
+static void cancel_spinner(int i915,
+ uint32_t ctx, unsigned int engine,
+ igt_spin_t *spin)
+{
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = gem_create(i915, 4096),
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(),
+ .buffer_count = 1,
+ .flags = engine | I915_EXEC_FENCE_SUBMIT,
+ .rsvd1 = ctx, /* same vm */
+ .rsvd2 = spin->out_fence,
+ };
+ uint32_t *map, *cs;
+
+ map = gem_mmap__device_coherent(i915, obj.handle, 0, 4096, PROT_WRITE);
+ cs = map;
+
+ *cs++ = MI_STORE_DWORD_IMM;
+ *cs++ = spin->obj[IGT_SPIN_BATCH].offset +
+ offset_in_page(spin->condition);
+ *cs++ = spin->obj[IGT_SPIN_BATCH].offset >> 32;
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ *cs++ = MI_BATCH_BUFFER_END;
+ munmap(map, 4096);
+
+ gem_execbuf(i915, );
+ gem_close(i915, obj.handle);
+}
+
+static void submit_slice(int i915,
+const struct intel_execution_engine2 *e,
+unsigned int flags)
+#define EARLY_SUBMIT 0x1
+#define LATE_SUBMIT 0x2
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines , 1) = {};
+ const struct intel_execution_engine2 *cancel;
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(),
+ .size = sizeof(engines),
+ };
+
+ /*
+* When using a submit fence, we do not want to block concurrent work,
+* especially when that work is coperating with the spinner.
+*/
+
+ igt_require(gem_scheduler_has_semaphores(i915));
+ igt_require(gem_scheduler_has_preemption(i915));
+ igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
+
+ __for_each_physical_engine(i915, cancel) {
+ igt_spin_t *bg, *spin;
+ int timeline = -1;
+ int fence = -1;
+
+ if (!gem_class_can_store_dword(i915, cancel->class))
+ continue;
+
+ igt_debug("Testing cancellation from %s\n", e->name);
+
+ bg = igt_spin_new(i915, .engine = e->flags);
+
+ if (flags & LATE_SUBMIT) {
+ timeline = sw_sync_timeline_create();
+ fence = sw_sync_timeline_create_fence(timeline, 1);
+ }
+
+ engines.engines[0].engine_class = e->class;
+ engines.engines[0].engine_instance = e->instance;
+ gem_context_set_param(i915, );
+ spin = igt_spin_new(i915, .ctx = param.ctx_id,
+ .fence = fence,
+ .flags =
+ IGT_SPIN_POLL_RUN |
+ (flags & LATE_SUBMIT ? IGT_SPIN_FENCE_IN :
0) |
+ IGT_SPIN_FENCE_OUT);
+ if (fence != -1)
+ close(fence);
+
+ if (flags & EARLY_SUBMIT)
+ igt_spin_busywait_until_started(spin);
+
+ engines.engines[0].engine_class = cancel->class;
+ engines.engines[0].engine_instance = cancel->instance;
+ gem_context_set_param(i915, );
+ cancel_spinner(i915, param.ctx_id, 0, spin);
+
+ if (timeline != -1)
+ close(timeline);
+
+ gem_sync(i915, spin->handle);
+ igt_spin_free(i915, spin);
+ igt_spin_free(i915, bg);
+ }
+
+ gem_context_destroy(i915, param.ctx_id);
+}
+
static uint32_t __batch_create(int i915, uint32_t offset)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -812,11 +921,6 @@ static void semaphore_codependency(int i915)
}
}
-static unsigned int offset_in_page(void *addr)
-{
- return (uintptr_t)addr & 4095;
-}
-
static void semaphore_resolve(int i915)
[Intel-gfx] [PATCH i-g-t] i915/i915_pm_rc6_residency: Check we conserve power while waiting
Check that if we submit a request that is held up by an external fence,
that we conserve power during the wait as the GPU is idle.
Signed-off-by: Chris Wilson
Cc: Venkata Sandeep Dhanalakota
---
tests/i915/i915_pm_rc6_residency.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/tests/i915/i915_pm_rc6_residency.c
b/tests/i915/i915_pm_rc6_residency.c
index 144bcd028..810415b48 100644
--- a/tests/i915/i915_pm_rc6_residency.c
+++ b/tests/i915/i915_pm_rc6_residency.c
@@ -38,6 +38,7 @@
#include "igt_perf.h"
#include "igt_rapl.h"
#include "igt_sysfs.h"
+#include "sw_sync.h"
#define SLEEP_DURATION 3 /* in seconds */
@@ -447,6 +448,80 @@ static void rc6_idle(int i915)
}
}
+static void rc6_fence(int i915)
+{
+ const int64_t duration_ns = SLEEP_DURATION * (int64_t)NSEC_PER_SEC;
+ const int tolerance = 20; /* Some RC6 is better than none! */
+ const int gen = intel_gen(intel_get_drm_devid(i915));
+ const struct intel_execution_engine2 *e;
+ struct power_sample sample[2];
+ unsigned long slept;
+ uint64_t rc6, ts[2];
+ struct rapl rapl;
+ int fd;
+
+ igt_require_sw_sync();
+
+ fd = open_pmu(i915, I915_PMU_RC6_RESIDENCY);
+ igt_drop_caches_set(i915, DROP_IDLE);
+ igt_require(__pmu_wait_for_rc6(fd));
+ gpu_power_open();
+
+ /* While idle check full RC6. */
+ rapl_read(, [0]);
+ rc6 = -__pmu_read_single(fd, [0]);
+ slept = measured_usleep(duration_ns / 1000);
+ rc6 += __pmu_read_single(fd, [1]);
+ igt_debug("slept=%lu perf=%"PRIu64", rc6=%"PRIu64"\n",
+ slept, ts[1] - ts[0], rc6);
+ if (rapl_read(, [1])) {
+ double idle = power_J(, [0], [1]);
+ igt_log(IGT_LOG_DOMAIN,
+ idle > 1e-3 && gen > 6 ? IGT_LOG_WARN : IGT_LOG_INFO,
+ "Total energy used while idle: %.1fmJ\n", idle * 1e3);
+ }
+ assert_within_epsilon(rc6, ts[1] - ts[0], 5);
+
+ /* Submit but delay execution, we should be idle and conserving power */
+ __for_each_physical_engine(i915, e) {
+ igt_spin_t *spin;
+ int timeline;
+ int fence;
+
+ timeline = sw_sync_timeline_create();
+ fence = sw_sync_timeline_create_fence(timeline, 1);
+ spin = igt_spin_new(i915,
+ .engine = e->flags,
+ .fence = fence,
+ .flags = IGT_SPIN_FENCE_IN);
+ close(fence);
+
+ rapl_read(, [0]);
+ rc6 = -__pmu_read_single(fd, [0]);
+ slept = measured_usleep(duration_ns / 1000);
+ rc6 += __pmu_read_single(fd, [1]);
+ igt_debug("%s: slept=%lu perf=%"PRIu64", rc6=%"PRIu64"\n",
+ e->name, slept, ts[1] - ts[0], rc6);
+ if (rapl_read(, [1])) {
+ uint64_t power = power_J(, [0], [1]);
+ igt_info("Total energy used for %s: %.1fmJ (%.1fmW)\n",
+e->name,
+power * 1e3,
+power * 1e12 / slept);
+ }
+
+ igt_assert(gem_bo_busy(i915, spin->handle));
+ igt_spin_free(i915, spin);
+
+ close(timeline);
+
+ assert_within_epsilon(rc6, ts[1] - ts[0], tolerance);
+ }
+
+ rapl_close();
+ close(fd);
+}
+
igt_main
{
int i915 = -1;
@@ -463,6 +538,13 @@ igt_main
rc6_idle(i915);
}
+ igt_subtest("rc6-fence") {
+ igt_require_gem(i915);
+ gem_quiescent_gpu(i915);
+
+ rc6_fence(i915);
+ }
+
igt_subtest_group {
unsigned int rc6_enabled = 0;
unsigned int devid = 0;
--
2.27.0.rc0
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[Intel-gfx] ✓ Fi.CI.BAT: success for Consider DBuf bandwidth when calculating CDCLK (rev18)
== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev18) URL : https://patchwork.freedesktop.org/series/74739/ State : success == Summary == CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17733 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17733/index.html Known issues Here are the changes found in Patchwork_17733 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][1] -> [TIMEOUT][2] ([i915#1288]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-glk-dsi/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17733/fi-glk-dsi/igt@i915_pm_...@module-reload.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [SKIP][3] ([fdo#109271]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-guc/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17733/fi-kbl-guc/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1288]: https://gitlab.freedesktop.org/drm/intel/issues/1288 Participating hosts (48 -> 43) -- Missing(5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper Build changes - * Linux: CI_DRM_8511 -> Patchwork_17733 CI-20190529: 20190529 CI_DRM_8511: 504ee538bd65abff745914a6f0b7aad62bbc1d11 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5664: 404e2fa06b9c5986dec3fa210234fe8b034b157e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17733: 727bc2568e96653db48fa5821212abe6fb01b7a8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 727bc2568e96 drm/i915: Remove unneeded hack now for CDCLK cea1d50d43c0 drm/i915: Adjust CDCLK accordingly to our DBuf bw needs 89ece93a82af drm/i915: Introduce for_each_dbuf_slice_in_mask macro f6fbdfa19ab0 drm/i915: Plane configuration affects CDCLK in Gen11+ c013d7e44c52 drm/i915: Check plane configuration properly b0928a963b24 drm/i915: Extract cdclk requirements checking to separate function 27d0a2a78122 drm/i915: Decouple cdclk calculation from modeset checks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17733/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC
On Tue, 2020-05-19 at 13:12 -0700, Swathi Dhanavanthri wrote:
> This is a permanent w/a for JSL/EHL.This is to be applied to the
> PCH types on JSL/EHL ie JSP/MCC
> Bspec: 52888
>
> v2: Fixed the wrong usage of logical OR(ville)
>
> Signed-off-by: Swathi Dhanavanthri
> ---
> drivers/gpu/drm/i915/i915_irq.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4dc601dffc08..d60a66d8eb40 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2902,8 +2902,9 @@ static void gen11_display_irq_reset(struct
> drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:icl */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) {
> + /* Wa_14010685332:icl,jsl,ehl */
> + if ((INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) &&
> +(INTEL_PCH_TYPE(dev_priv) <= PCH_MCC)) {
Not comfortable with this checks based on order of intel_pch enum but looks
like we do it else where too.
Anyways, before send patch please run "dim
checkpatch" to catch style errors also no need of the parenthesis.
> intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
>SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Consider DBuf bandwidth when calculating CDCLK (rev18)
== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev18) URL : https://patchwork.freedesktop.org/series/74739/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +./include/linux/compiler.h:199:9: warning: context imbalance in 'engines_sample' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Consider DBuf bandwidth when calculating CDCLK (rev18)
== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev18) URL : https://patchwork.freedesktop.org/series/74739/ State : warning == Summary == $ dim checkpatch origin/drm-tip 27d0a2a78122 drm/i915: Decouple cdclk calculation from modeset checks b0928a963b24 drm/i915: Extract cdclk requirements checking to separate function c013d7e44c52 drm/i915: Check plane configuration properly f6fbdfa19ab0 drm/i915: Plane configuration affects CDCLK in Gen11+ 89ece93a82af drm/i915: Introduce for_each_dbuf_slice_in_mask macro -:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__slice' - possible side-effects? #25: FILE: drivers/gpu/drm/i915/display/intel_display.h:190: +#define for_each_dbuf_slice_in_mask(__slice, __mask) \ + for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ + for_each_if((BIT(__slice)) & (__mask)) total: 0 errors, 0 warnings, 1 checks, 20 lines checked cea1d50d43c0 drm/i915: Adjust CDCLK accordingly to our DBuf bw needs 727bc2568e96 drm/i915: Remove unneeded hack now for CDCLK ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 6/7] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs
According to BSpec max BW per slice is calculated using formula
Max BW = CDCLK * 64. Currently when calculating min CDCLK we
account only per plane requirements, however in order to avoid
FIFO underruns we need to estimate accumulated BW consumed by
all planes(ddb entries basically) residing on that particular
DBuf slice. This will allow us to put CDCLK lower and save power
when we don't need that much bandwidth or gain additional
performance once plane consumption grows.
v2: - Fix long line warning
- Limited new DBuf bw checks to only gens >= 11
v3: - Lets track used Dbuf bw per slice and per crtc in bw state
(or may be in DBuf state in future), that way we don't need
to have all crtcs in state and those only if we detect if
are actually going to change cdclk, just same way as we
do with other stuff, i.e intel_atomic_serialize_global_state
and co. Just as per Ville's paradigm.
- Made dbuf bw calculation procedure look nicer by introducing
for_each_dbuf_slice_in_mask - we often will now need to iterate
slices using mask.
- According to experimental results CDCLK * 64 accounts for
overall bandwidth across all dbufs, not per dbuf.
v4: - Fixed missing const(Ville)
- Removed spurious whitespaces(Ville)
- Fixed local variable init(reduced scope where not needed)
- Added some comments about data rate for planar formats
- Changed struct intel_crtc_bw to intel_dbuf_bw
- Moved dbuf bw calculation to intel_compute_min_cdclk(Ville)
v5: - Removed unneeded macro
v6: - Prevent too frequent CDCLK switching back and forth:
Always switch to higher CDCLK when needed to prevent bandwidth
issues, however don't switch to lower CDCLK earlier than once
in 30 minutes in order to prevent constant modeset blinking.
We could of course not switch back at all, however this is
bad from power consumption point of view.
v7: - Fixed to track cdclk using bw_state, modeset will be now
triggered only when CDCLK change is really needed.
v8: - Lock global state if bw_state->min_cdclk is changed.
- Try getting bw_state only if there are crtcs in the commit
(need to have read-locked global state)
v9: - Do not do Dbuf bw check for gens < 9 - triggers WARN
as ddb_size is 0.
v10: - Lock global state for older gens as well.
v11: - Define new bw_calc_min_cdclk hook, instead of using
a condition(Manasi Navare)
v12: - Fixed rebase conflict
v13: - Added spaces after declarations to make checkpatch happy.
Signed-off-by: Stanislav Lisovskiy
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_bw.c | 121 ++-
drivers/gpu/drm/i915/display/intel_bw.h | 10 ++
drivers/gpu/drm/i915/display/intel_cdclk.c | 28 -
drivers/gpu/drm/i915/display/intel_cdclk.h | 1 -
drivers/gpu/drm/i915/display/intel_display.c | 39 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 31 -
drivers/gpu/drm/i915/intel_pm.h | 4 +
8 files changed, 220 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index fef04e2d954e..a539b1ed7723 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -6,11 +6,12 @@
#include
#include "intel_bw.h"
+#include "intel_pm.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
#include "intel_atomic.h"
#include "intel_pm.h"
-
+#include "intel_cdclk.h"
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -343,7 +344,6 @@ static unsigned int intel_bw_crtc_data_rate(const struct
intel_crtc_state *crtc_
return data_rate;
}
-
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state)
{
@@ -420,6 +420,123 @@ intel_atomic_get_bw_state(struct intel_atomic_state
*state)
return to_intel_bw_state(bw_state);
}
+int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int i;
+ const struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int max_bw = 0;
+ int slice_id;
+ struct intel_bw_state *new_bw_state = NULL;
+ struct intel_bw_state *old_bw_state = NULL;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ enum plane_id plane_id;
+ struct intel_dbuf_bw *crtc_bw;
+
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
+
+ crtc_bw = _bw_state->dbuf_bw[crtc->pipe];
+
+ memset(_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct
[Intel-gfx] [PATCH v9 4/7] drm/i915: Plane configuration affects CDCLK in Gen11+
So lets support it.
v2: - Fixed "from" field which got corrupted for some weird reason
Reviewed-by: Manasi Navare
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8a2212115baf..8068dc96d5aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14638,7 +14638,7 @@ static bool active_planes_affects_min_cdclk(struct
drm_i915_private *dev_priv)
/* See {hsw,vlv,ivb}_plane_ratio() */
return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
- IS_IVYBRIDGE(dev_priv);
+ IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
}
static int intel_atomic_check_planes(struct intel_atomic_state *state)
--
2.24.1.485.gad05a3d8e5
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 3/7] drm/i915: Check plane configuration properly
Checking with hweight8 if plane configuration had changed seems to be wrong as different plane configs can result in a same hamming weight. So lets check the bitmask itself. v2: Fixed "from" field which got corrupted for some weird reason Reviewed-by: Manasi Navare Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_display.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b6f4076dfd5a..8a2212115baf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14683,7 +14683,13 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); - if (hweight8(old_active_planes) == hweight8(new_active_planes)) + /* +* Not only the number of planes, but if the plane configuration had +* changed might already mean we need to recompute min CDCLK, +* because different planes might consume different amount of Dbuf bandwidth +* according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor +*/ + if (old_active_planes == new_active_planes) continue; ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); -- 2.24.1.485.gad05a3d8e5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10)
== Series Details == Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10) URL : https://patchwork.freedesktop.org/series/73036/ State : success == Summary == CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17732 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/index.html Known issues Here are the changes found in Patchwork_17732 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [SKIP][1] ([fdo#109271]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-guc/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/fi-kbl-guc/igt@i915_pm_...@module-reload.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (48 -> 44) -- Missing(4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-4200u Build changes - * Linux: CI_DRM_8511 -> Patchwork_17732 CI-20190529: 20190529 CI_DRM_8511: 504ee538bd65abff745914a6f0b7aad62bbc1d11 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5664: 404e2fa06b9c5986dec3fa210234fe8b034b157e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17732: 8c8cb1efb20f5c596ec7ace6e9a023abb400ccd6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8c8cb1efb20f drm/i915/dsb: Pre allocate and late cleanup of cmd buffer == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17732/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hdcp: Add additional R0' wait (rev2)
== Series Details ==
Series: drm/i915/hdcp: Add additional R0' wait (rev2)
URL : https://patchwork.freedesktop.org/series/77439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17731
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/index.html
Known issues
Here are the changes found in Patchwork_17731 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#1803])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-tgl-y/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/fi-tgl-y/igt@i915_selftest@l...@execlists.html
- fi-skl-6700k2: [PASS][3] -> [INCOMPLETE][4] ([i915#1874])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@ring_submission:
- fi-bwr-2160:[PASS][5] -> [INCOMPLETE][6] ([i915#489])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-bwr-2160/igt@i915_selftest@live@ring_submission.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/fi-bwr-2160/igt@i915_selftest@live@ring_submission.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [SKIP][7] ([fdo#109271]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-guc/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/fi-kbl-guc/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
[i915#1874]: https://gitlab.freedesktop.org/drm/intel/issues/1874
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
Participating hosts (48 -> 44)
--
Missing(4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_8511 -> Patchwork_17731
CI-20190529: 20190529
CI_DRM_8511: 504ee538bd65abff745914a6f0b7aad62bbc1d11 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5664: 404e2fa06b9c5986dec3fa210234fe8b034b157e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17731: 2f923bf79607e9e1f5edbf555daf1ba40740b8cf @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2f923bf79607 drm/i915/hdcp: Add additional R0' wait
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17731/index.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/23] Revert "drm/i915/gem: Drop relocation slowpath".
== Series Details ==
Series: series starting with [01/23] Revert "drm/i915/gem: Drop relocation
slowpath".
URL : https://patchwork.freedesktop.org/series/77472/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17730
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17730 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17730, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17730:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gem_contexts:
- fi-cfl-8109u: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-cfl-8109u/igt@i915_selftest@live@gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-cfl-8109u/igt@i915_selftest@live@gem_contexts.html
- fi-skl-lmem:[PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
* igt@kms_busy@basic@flip:
- fi-bwr-2160:[PASS][5] -> [FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-bwr-2160/igt@kms_busy@ba...@flip.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-bwr-2160/igt@kms_busy@ba...@flip.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-pnv-d510/igt@run...@aborted.html
- fi-gdg-551: NOTRUN -> [FAIL][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-gdg-551/igt@run...@aborted.html
- fi-snb-2520m: NOTRUN -> [FAIL][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-snb-2520m/igt@run...@aborted.html
- fi-byt-n2820: NOTRUN -> [FAIL][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-byt-n2820/igt@run...@aborted.html
- fi-ivb-3770:NOTRUN -> [FAIL][11]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-ivb-3770/igt@run...@aborted.html
- fi-byt-j1900: NOTRUN -> [FAIL][12]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-byt-j1900/igt@run...@aborted.html
- fi-elk-e7500: NOTRUN -> [FAIL][13]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-elk-e7500/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][14]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-blb-e6850/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live@gem_execbuf}:
- fi-skl-6600u: [PASS][15] -> [INCOMPLETE][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-skl-6600u/igt@i915_selftest@live@gem_execbuf.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-skl-6600u/igt@i915_selftest@live@gem_execbuf.html
- fi-cfl-8109u: [PASS][17] -> [INCOMPLETE][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-cfl-8109u/igt@i915_selftest@live@gem_execbuf.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-cfl-8109u/igt@i915_selftest@live@gem_execbuf.html
- fi-kbl-7500u: [PASS][19] -> [INCOMPLETE][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-7500u/igt@i915_selftest@live@gem_execbuf.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-kbl-7500u/igt@i915_selftest@live@gem_execbuf.html
- fi-kbl-guc: [PASS][21] -> [INCOMPLETE][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-guc/igt@i915_selftest@live@gem_execbuf.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-kbl-guc/igt@i915_selftest@live@gem_execbuf.html
- fi-bsw-nick:[PASS][23] -> [INCOMPLETE][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-bsw-nick/igt@i915_selftest@live@gem_execbuf.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-bsw-nick/igt@i915_selftest@live@gem_execbuf.html
- fi-kbl-8809g: [PASS][25] -> [INCOMPLETE][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-8809g/igt@i915_selftest@live@gem_execbuf.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17730/fi-kbl-8809g/igt@i915_selftest@live@gem_execbuf.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/23] Revert "drm/i915/gem: Drop relocation slowpath".
== Series Details == Series: series starting with [01/23] Revert "drm/i915/gem: Drop relocation slowpath". URL : https://patchwork.freedesktop.org/series/77472/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/23] Revert "drm/i915/gem: Drop relocation slowpath".
== Series Details ==
Series: series starting with [01/23] Revert "drm/i915/gem: Drop relocation
slowpath".
URL : https://patchwork.freedesktop.org/series/77472/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e8a9ca7ebbde Revert "drm/i915/gem: Drop relocation slowpath".
-:80: WARNING:LINE_SPACING: Missing a blank line after declarations
#80: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1803:
+ int err = __get_user(c, addr);
+ if (err)
total: 0 errors, 1 warnings, 0 checks, 264 lines checked
72f5c5b30070 drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2.
-:493: WARNING:LONG_LINE: line over 100 characters
#493: FILE: drivers/gpu/drm/i915/i915_gem.c:1341:
+ while ((obj = list_first_entry_or_null(>obj_list, struct
drm_i915_gem_object, obj_link))) {
total: 0 errors, 1 warnings, 0 checks, 473 lines checked
a468a7cf573c drm/i915: Remove locking from i915_gem_object_prepare_read/write
0d1389fe4823 drm/i915: Parse command buffer earlier in eb_relocate(slow)
0959c95aca1a Revert "drm/i915/gem: Split eb_vma into its own allocation"
351faedf629a drm/i915/gem: Make eb_add_lut interruptible wait on object lock.
1e76b4db6002 drm/i915: Use per object locking in execbuf, v10.
-:463: CHECK:LINE_SPACING: Please don't use multiple blank lines
#463: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1398:
+
-:510: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#510: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1510:
+static int __reloc_entry_gpu(struct i915_execbuffer *eb,
struct i915_vma *vma,
-:530: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#530: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1583:
+static int reloc_entry_gpu(struct i915_execbuffer *eb,
struct i915_vma *vma,
-:542: ERROR:TRAILING_WHITESPACE: trailing whitespace
#542: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1608:
+^I$
-:801: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#801: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2948:
+ eb.reloc_pool = eb.batch_pool = NULL;
total: 1 errors, 0 warnings, 4 checks, 803 lines checked
710f752755c1 drm/i915: Use ww locking in intel_renderstate.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
Convert to using ww-waiting, and make sure we always pin intel_context_state,
total: 0 errors, 1 warnings, 0 checks, 209 lines checked
a42f3dac28b8 drm/i915: Add ww context handling to context_barrier_task
-:19: WARNING:LONG_LINE: line over 100 characters
#19: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:1097:
+ int (*pin)(struct intel_context *ce, struct
i915_gem_ww_ctx *ww, void *data),
total: 0 errors, 1 warnings, 0 checks, 146 lines checked
b428669fca95 drm/i915: Nuke arguments to eb_pin_engine
b5516731f269 drm/i915: Pin engine before pinning all objects, v4.
8e0a6a165baf drm/i915: Rework intel_context pinning to do everything outside of
pin_mutex
-:125: CHECK:LINE_SPACING: Please don't use multiple blank lines
#125: FILE: drivers/gpu/drm/i915/gt/intel_context.c:176:
+
+
-:338: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#338: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:3437:
+ *vaddr = i915_gem_object_pin_map(ce->state->obj,
+
i915_coherent_map_type(ce->engine->i915) |
total: 0 errors, 0 warnings, 2 checks, 435 lines checked
105f0b34fcf5 drm/i915: Make sure execbuffer always passes ww state to
i915_vma_pin.
-:95: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#95: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:596:
+ err = i915_vma_pin_ww(vma, >ww,
entry->pad_to_size, entry->alignment,
-:213: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#213: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2463:
+* hsw should have this fixed, but bdw mucks it up again. */
total: 0 errors, 1 warnings, 1 checks, 850 lines checked
12ec08c8537e drm/i915: Convert i915_gem_object/client_blt.c to use ww locking
as well, v2.
5a24cea35c94 drm/i915: Kill last user of intel_context_create_request outside
of selftests
99b1d3502005 drm/i915: Convert i915_perf to ww locking as well
30c1a144d8d8 drm/i915: Dirty hack to fix selftests locking inversion
dd08b28e8648 drm/i915/selftests: Fix locking inversion in lrc selftest.
cb9f17485972 drm/i915: Use ww pinning for intel_context_create_request()
a1c6650bd9c8 drm/i915: Move i915_vma_lock in the selftests to avoid lock
inversion, v2.
-:108: ERROR:TRAILING_WHITESPACE: trailing whitespace
#108: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c:154:
+^I^Ii915_gem_ww_ctx_fini(); $
total: 1 errors, 0 warnings, 0 checks, 347 lines checked
dd51ae3087a8 drm/i915: Add ww
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Replace deprecated function in drm_crtc_helper
== Series Details == Series: drm: Replace deprecated function in drm_crtc_helper URL : https://patchwork.freedesktop.org/series/77467/ State : success == Summary == CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17729 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/index.html Known issues Here are the changes found in Patchwork_17729 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@sanitycheck: - fi-bwr-2160:[PASS][1] -> [INCOMPLETE][2] ([i915#489]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-bwr-2160/igt@i915_selftest@l...@sanitycheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/fi-bwr-2160/igt@i915_selftest@l...@sanitycheck.html * igt@kms_chamelium@dp-crc-fast: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#262]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([i915#976]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [SKIP][7] ([fdo#109271]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-guc/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/fi-kbl-guc/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 [i915#976]: https://gitlab.freedesktop.org/drm/intel/issues/976 Participating hosts (48 -> 44) -- Missing(4): fi-byt-clapper fi-byt-squawks fi-bsw-cyan fi-hsw-4200u Build changes - * Linux: CI_DRM_8511 -> Patchwork_17729 CI-20190529: 20190529 CI_DRM_8511: 504ee538bd65abff745914a6f0b7aad62bbc1d11 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5664: 404e2fa06b9c5986dec3fa210234fe8b034b157e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17729: 537a8965a1f71bc4b8c3776e5c186c9d849b7cc4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 537a8965a1f7 drm: Replace deprecated function in drm_crtc_helper == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17729/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
function which also includes pinning and map in cpu domain.
No functional change is dsb write/commit functions.
Now dsb get/put function is removed and ref-count mechanism is
not needed. Below dsb api added to do respective job mentioned
below.
intel_dsb_prepare - Allocate, pin and map the buffer.
intel_dsb_cleanup - Unpin and release the gem object.
RFC: Initial patch for design review.
v2: included _init() part in _prepare(). [Daniel, Ville]
v3: dsb_cleanup called after cleanup_planes. [Daniel]
v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten]
v5: dsb get/put/ref-count mechanism removed. [Maarten]
v6: Based on review feedback following changes are added,
- replaced intel_dsb structure by pointer in intel_crtc_state. [Maarten]
- passing intel_crtc_state to dsp-api to simplify the code. [Maarten]
- few dsb functions prototype modified to simplify code.
v7: added few cosmetic changes suggested by Jani and null check for
crtc_state in dsb_cleanup removed as suggested by Maarten.
v8: changed the function parameter to intel_crtc_state* of
ivb_load_lut_ext_max() from intel_crtc. [Maarten]
v9: error handling improved in _write() and prepare(). [Maarten]
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Acked-by: Daniel Vetter
Reviewed-by: Maarten Lankhorst
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 3 +
drivers/gpu/drm/i915/display/intel_color.c| 66 ++---
drivers/gpu/drm/i915/display/intel_display.c | 58 +++-
.../drm/i915/display/intel_display_types.h| 6 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 250 --
drivers/gpu/drm/i915/display/intel_dsb.h | 17 +-
6 files changed, 206 insertions(+), 194 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index d043057d2fa0..3cb866f22e74 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -252,6 +252,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->wm.need_postvbl_update = false;
crtc_state->fb_bits = 0;
crtc_state->update_planes = 0;
+ crtc_state->dsb = NULL;
return _state->uapi;
}
@@ -292,6 +293,8 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
{
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
+ drm_WARN_ON(crtc->dev, crtc_state->dsb);
+
__drm_atomic_helper_crtc_destroy_state(_state->uapi);
intel_crtc_free_hw_state(crtc_state);
kfree(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 98ece9cd7cdd..945bb03bdd4d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -714,16 +714,16 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
}
-static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
+static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
/*
* Program the gc max 2 register to clamp values > 1.0.
@@ -731,15 +731,13 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
* from 3.0 to 7.0
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
- intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
1 << 16);
- intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
1 << 16);
- intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2),
1 << 16);
}
-
- intel_dsb_put(dsb);
}
static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
@@ -753,7 +751,7 @@ static void ivb_load_luts(const struct intel_crtc_state
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/hdcp: Add additional R0' wait
== Series Details ==
Series: drm/i915/hdcp: Add additional R0' wait
URL : https://patchwork.freedesktop.org/series/77439/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8506_full -> Patchwork_17719_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17719_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17719_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17719_full:
### IGT changes ###
Possible regressions
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-kbl6/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-kbl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
Known issues
Here are the changes found in Patchwork_17719_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-kbl7/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-kbl1/igt@gem_exec_susp...@basic-s3.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +3 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-apl3/igt@gem_workarou...@suspend-resume-context.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-apl4/igt@gem_workarou...@suspend-resume-context.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#1188])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl9/igt@kms_...@bpc-switch.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-skl6/igt@kms_...@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][9] -> [INCOMPLETE][10] ([i915#155])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-kbl2/igt@kms_...@bpc-switch-suspend.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-kbl6/igt@kms_...@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [i915#265])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#173])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-iclb4/igt@kms_psr@no_drrs.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#31])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl3/igt@kms_setm...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-skl8/igt@kms_setm...@basic.html
Possible fixes
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-skl: [FAIL][19] ([i915#54]) -> [PASS][20] +1 similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html
* {igt@kms_flip@flip-vs-suspend-interruptible@b-edp1}:
- shard-skl: [INCOMPLETE][21] ([i915#198]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8506/shard-skl5/igt@kms_flip@flip-vs-suspend-interrupti...@b-edp1.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17719/shard-skl1/igt@kms_flip@flip-vs-suspend-interrupti...@b-edp1.html
* {igt@kms_flip@flip-vs-suspend@a-dp1}:
- shard-kbl:
Re: [Intel-gfx] [PATCH v6 00/16] drm/i915: Add support for HDCP 1.4 over MST connectors
On Mon, May 18, 2020 at 12:41 PM Ramalingam C wrote: > > On 2020-05-18 at 10:32:09 -0400, Sean Paul wrote: > > On Fri, May 15, 2020 at 10:48 AM Ramalingam C > > wrote: > > > > > > On 2020-04-29 at 15:54:46 -0400, Sean Paul wrote: > > > > From: Sean Paul > > > > > > > > Changes in v6: > > > > -Rebased on -tip > > > > -Disabled HDCP over MST on GEN12 > > > > -Addressed Lyude's review comments in the > > > > QUERY_STREAM_ENCRYPTION_STATUS patch > > > > > > Sean, > > > > > > What is the test setup you have used? > > > > > > > Hi Ram, > > Thanks for the feedback. To be completely honest it's really > > frustrating that I'm just now getting questions and review feedback > > (which I've been begging for on IRC) on this review that could have > > been addressed ~5 months ago. It's super disruptive to have to keep > > switching back to this after a long hiatus and many i915 refactors > > complicating my rebases. > Hi Sean, > > As a developer I really feel bad for the delay happened in review. > I couldn't spend required time for understanding MST part hence I > couldn't review. > > Just for this series now I have started preparing myself on these topics, > hence started reviewing the series. > > If you are still interested to work on this, I can commit for regular reviews. > Thanks Ram. I'm still incentivized to get this in. Once you have had a chance to look over the whole series, I'll revise again. Sean > Thanks, > Ram. > > > > If no one wants this patchset, that's fine, please just let me know so > > I don't waste any more time. If Intel is interested, could we please > > stop the review trickle and lay out exactly what needs to be done to > > get this landed? > > > > Sean > > > > > > > I am afraid our CI dont have the coverage for MST capability yet to > > > provide > > > the functional status of the code. > > > > > > -Ram. > > > > > > > > Sean Paul (16): > > > > drm/i915: Fix sha_text population code > > > > drm/i915: Clear the repeater bit on HDCP disable > > > > drm/i915: WARN if HDCP signalling is enabled upon disable > > > > drm/i915: Intercept Aksv writes in the aux hooks > > > > drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP > > > > signalling > > > > drm/i915: Factor out hdcp->value assignments > > > > drm/i915: Protect workers against disappearing connectors > > > > drm/i915: Don't fully disable HDCP on a port if multiple pipes are > > > > using it > > > > drm/i915: Support DP MST in enc_to_dig_port() function > > > > drm/i915: Use ddi_update_pipe in intel_dp_mst > > > > drm/i915: Factor out HDCP shim functions from dp for use by dp_mst > > > > drm/i915: Plumb port through hdcp init > > > > drm/i915: Add connector to hdcp_shim->check_link() > > > > drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband > > > > message > > > > drm/i915: Print HDCP version info for all connectors > > > > drm/i915: Add HDCP 1.4 support for MST connectors > > > > > > > > drivers/gpu/drm/drm_dp_mst_topology.c | 142 > > > > drivers/gpu/drm/i915/Makefile | 1 + > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 29 +- > > > > drivers/gpu/drm/i915/display/intel_ddi.h | 2 + > > > > .../drm/i915/display/intel_display_debugfs.c | 21 +- > > > > .../drm/i915/display/intel_display_types.h| 30 +- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 654 +-- > > > > drivers/gpu/drm/i915/display/intel_dp.h | 9 + > > > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 743 ++ > > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 + > > > > drivers/gpu/drm/i915/display/intel_hdcp.c | 217 +++-- > > > > drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- > > > > drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +- > > > > .../drm/selftests/test-drm_dp_mst_helper.c| 17 + > > > > include/drm/drm_dp_helper.h | 3 + > > > > include/drm/drm_dp_mst_helper.h | 44 ++ > > > > include/drm/drm_hdcp.h| 3 + > > > > 17 files changed, 1235 insertions(+), 726 deletions(-) > > > > create mode 100644 drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > > > > > > > -- > > > > Sean Paul, Software Engineer, Google / Chromium OS > > > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/hdcp: Add additional R0' wait
From: Sean Paul
We're seeing some R0' mismatches in the field, particularly with
repeaters. I'm guessing the (already lenient) 300ms wait time isn't
enough for some setups. So add an additional wait when R0' is
mismatched.
Signed-off-by: Sean Paul
Changes in v2:
- Actually add the delay in R0` wait (Ram)
---
Apologies, v1 was generated from a forward port from the CrOS kernel and
patch got confused and put the diff in V' wait instead of R0' wait.
Pay closer attention, Sean.
drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 2cbc4619b4ce..3c2d8c0a6da6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -743,6 +743,9 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
if (!wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv,
cpu_transcoder, port)) &
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
break;
+
+ /* Maybe the sink is lazy, give it some more time */
+ usleep_range(1, 5);
}
if (i == tries) {
--
Sean Paul, Software Engineer, Google / Chromium OS
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs (rev2)
== Series Details == Series: series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs (rev2) URL : https://patchwork.freedesktop.org/series/77366/ State : success == Summary == CI Bug Log - changes from CI_DRM_8511 -> Patchwork_17728 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/index.html Known issues Here are the changes found in Patchwork_17728 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [SKIP][1] ([fdo#109271]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8511/fi-kbl-guc/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/fi-kbl-guc/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (48 -> 42) -- Missing(6): fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper Build changes - * Linux: CI_DRM_8511 -> Patchwork_17728 CI-20190529: 20190529 CI_DRM_8511: 504ee538bd65abff745914a6f0b7aad62bbc1d11 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5664: 404e2fa06b9c5986dec3fa210234fe8b034b157e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17728: acab80457ffc035232b81c5705851b097b3a442d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == acab80457ffc drm/i915/params: prevent changing module params runtime a76531f51fca drm/i915/params: fix i915.fake_lmem_start module param sysfs permissions 6190d8ce3829 drm/i915/params: don't expose inject_probe_failure in debugfs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17728/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/23] drm/i915: Use per object locking in execbuf, v10.
Now that we changed execbuf submission slightly to allow us to do all
pinning in one place, we can now simply add ww versions on top of
struct_mutex. All we have to do is a separate path for -EDEADLK
handling, which needs to unpin all gem bo's before dropping the lock,
then starting over.
This finally allows us to do parallel submission, but because not
all of the pinning code uses the ww ctx yet, we cannot completely
drop struct_mutex yet.
Changes since v1:
- Keep struct_mutex for now. :(
Changes since v2:
- Make sure we always lock the ww context in slowpath.
Changes since v3:
- Don't call __eb_unreserve_vma in eb_move_to_gpu now; this can be
done on normal unlock path.
- Unconditionally release vmas and context.
Changes since v4:
- Rebased on top of struct_mutex reduction.
Changes since v5:
- Remove training wheels.
Changes since v6:
- Fix accidentally broken -ENOSPC handling.
Changes since v7:
- Handle gt buffer pool better.
Changes since v8:
- Properly clear variables, to make -EDEADLK handling not BUG.
Change since v9:
- Fix unpinning fence on pnv and below.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 386 +++---
.../i915/gem/selftests/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 6 +
drivers/gpu/drm/i915/i915_gem.h | 1 +
4 files changed, 239 insertions(+), 156 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 19f1eced78a3..f6c087a20221 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -249,6 +249,8 @@ struct i915_execbuffer {
/** list of vma that have execobj.relocation_count */
struct list_head relocs;
+ struct i915_gem_ww_ctx ww;
+
/**
* Track the most recently used object for relocations, as we
* frequently have to perform multiple relocations within the same
@@ -269,14 +271,18 @@ struct i915_execbuffer {
struct i915_vma *rq_vma;
u32 *rq_cmd;
unsigned int rq_size;
+ struct intel_gt_buffer_pool_node *pool;
} reloc_cache;
+ struct intel_gt_buffer_pool_node *reloc_pool; /** relocation pool for
-EDEADLK handling */
+
u64 invalid_flags; /** Set of execobj.flags that are invalid */
u32 context_flags; /** Set of execobj.flags to insert from the ctx */
u32 batch_start_offset; /** Location within object of batch */
u32 batch_len; /** Length of batch within object */
u32 batch_flags; /** Flags composed for emit_bb_start() */
+ struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch
buffer */
/**
* Indicate either the size of the hastable used to resolve
@@ -443,23 +449,16 @@ eb_pin_vma(struct i915_execbuffer *eb,
return !eb_vma_misplaced(entry, vma, ev->flags);
}
-static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
-{
- GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
-
- if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
- __i915_vma_unpin_fence(vma);
-
- __i915_vma_unpin(vma);
-}
-
static inline void
eb_unreserve_vma(struct eb_vma *ev)
{
if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
return;
- __eb_unreserve_vma(ev->vma, ev->flags);
+ if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
+ __i915_vma_unpin_fence(ev->vma);
+
+ __i915_vma_unpin(ev->vma);
ev->flags &= ~__EXEC_OBJECT_RESERVED;
}
@@ -554,16 +553,6 @@ eb_add_vma(struct i915_execbuffer *eb,
eb->batch = ev;
}
-
- if (eb_pin_vma(eb, entry, ev)) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
- eb->args->flags |= __EXEC_HAS_RELOC;
- }
- } else {
- eb_unreserve_vma(ev);
- list_add_tail(>bind_link, >unbound);
- }
}
static inline int use_cpu_reloc(const struct reloc_cache *cache,
@@ -648,10 +637,6 @@ static int eb_reserve(struct i915_execbuffer *eb)
* This avoid unnecessary unbinding of later objects in order to make
* room for the earlier objects *unless* we need to defragment.
*/
-
- if (mutex_lock_interruptible(>i915->drm.struct_mutex))
- return -EINTR;
-
pass = 0;
do {
list_for_each_entry(ev, >unbound, bind_link) {
@@ -659,8 +644,8 @@ static int eb_reserve(struct i915_execbuffer *eb)
if (err)
break;
}
- if (!(err == -ENOSPC || err == -EAGAIN))
- break;
+ if (err != -ENOSPC)
+ return err;
/* Resort *all* the objects into priority order
[Intel-gfx] [PATCH 23/23] drm/i915: Ensure we hold the pin mutex
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 9 -
drivers/gpu/drm/i915/i915_vma.h | 1 +
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c
b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index 86a5a8ba4f80..bee35fd5a015 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -207,7 +207,7 @@ int intel_renderstate_init(struct intel_renderstate *so,
if (err)
goto err_context;
- err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ err = i915_vma_pin_ww(so->vma, >ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
if (err)
goto err_context;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 164e23e0fc11..837706d28cc5 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -869,6 +869,8 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
#ifdef CONFIG_PROVE_LOCKING
if (debug_locks && lockdep_is_held(>vm->i915->drm.struct_mutex))
WARN_ON(!ww);
+ if (debug_locks && ww && vma->resv)
+ assert_vma_held(vma);
#endif
BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND);
@@ -1009,8 +1011,13 @@ int i915_ggtt_pin(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
+ WARN_ON(!ww && vma->resv && dma_resv_held(vma->resv));
+
do {
- err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL);
+ if (ww)
+ err = i915_vma_pin_ww(vma, ww, 0, align, flags |
PIN_GLOBAL);
+ else
+ err = i915_vma_pin(vma, 0, align, flags | PIN_GLOBAL);
if (err != -ENOSPC) {
if (!err) {
err = i915_vma_wait_for_bind(vma);
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 2e3779a8a437..d937ce950481 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -242,6 +242,7 @@ i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
static inline int __must_check
i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
+ WARN_ON_ONCE(vma->resv && dma_resv_held(vma->resv));
return i915_vma_pin_ww(vma, NULL, size, alignment, flags);
}
--
2.26.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/23] drm/i915: Remove locking from i915_gem_object_prepare_read/write
Execbuffer submission will perform its own WW locking, and we
cannot rely on the implicit lock there.
This also makes it clear that the GVT code will get a lockdep splat when
multiple batchbuffer shadows need to be performed in the same instance,
fix that up.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 20 ++-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 13 ++--
drivers/gpu/drm/i915/gem/i915_gem_object.h| 1 -
.../gpu/drm/i915/gem/selftests/huge_pages.c | 5 -
.../i915/gem/selftests/i915_gem_coherency.c | 14 +
.../drm/i915/gem/selftests/i915_gem_context.c | 12 ---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 5 -
drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 -
drivers/gpu/drm/i915/i915_gem.c | 20 +--
9 files changed, 70 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index c0acfc97fae3..8ebceebd11b0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -576,19 +576,17 @@ int i915_gem_object_prepare_read(struct
drm_i915_gem_object *obj,
if (!i915_gem_object_has_struct_page(obj))
return -ENODEV;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
+ assert_object_held(obj);
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE,
MAX_SCHEDULE_TIMEOUT);
if (ret)
- goto err_unlock;
+ return ret;
ret = i915_gem_object_pin_pages(obj);
if (ret)
- goto err_unlock;
+ return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
!static_cpu_has(X86_FEATURE_CLFLUSH)) {
@@ -616,8 +614,6 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object
*obj,
err_unpin:
i915_gem_object_unpin_pages(obj);
-err_unlock:
- i915_gem_object_unlock(obj);
return ret;
}
@@ -630,20 +626,18 @@ int i915_gem_object_prepare_write(struct
drm_i915_gem_object *obj,
if (!i915_gem_object_has_struct_page(obj))
return -ENODEV;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
+ assert_object_held(obj);
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE |
I915_WAIT_ALL,
MAX_SCHEDULE_TIMEOUT);
if (ret)
- goto err_unlock;
+ return ret;
ret = i915_gem_object_pin_pages(obj);
if (ret)
- goto err_unlock;
+ return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
!static_cpu_has(X86_FEATURE_CLFLUSH)) {
@@ -680,7 +674,5 @@ int i915_gem_object_prepare_write(struct
drm_i915_gem_object *obj,
err_unpin:
i915_gem_object_unpin_pages(obj);
-err_unlock:
- i915_gem_object_unlock(obj);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 8861287df27a..f72f96863f8c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1098,11 +1098,14 @@ static void reloc_cache_reset(struct reloc_cache *cache)
vaddr = unmask_page(cache->vaddr);
if (cache->vaddr & KMAP) {
+ struct drm_i915_gem_object *obj =
+ (struct drm_i915_gem_object *)cache->node.mm;
if (cache->vaddr & CLFLUSH_AFTER)
mb();
kunmap_atomic(vaddr);
- i915_gem_object_finish_access((struct drm_i915_gem_object
*)cache->node.mm);
+ i915_gem_object_finish_access(obj);
+ i915_gem_object_unlock(obj);
} else {
struct i915_ggtt *ggtt = cache_to_ggtt(cache);
@@ -1137,10 +1140,16 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,
unsigned int flushes;
int err;
- err = i915_gem_object_prepare_write(obj, );
+ err = i915_gem_object_lock_interruptible(obj, NULL);
if (err)
return ERR_PTR(err);
+ err = i915_gem_object_prepare_write(obj, );
+ if (err) {
+ i915_gem_object_unlock(obj);
+ return ERR_PTR(err);
+ }
+
BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 37a9ee227ff1..aea18495c7a9 100644
[Intel-gfx] [PATCH 02/23] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2.
i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory
eviction. We don't use it yet, but lets start adding the definition
first.
To use it, we have to pass a non-NULL ww to gem_object_lock, and don't
unlock directly. It is done in i915_gem_ww_ctx_fini.
Changes since v1:
- Change ww_ctx and obj order in locking functions (Jonas Lahtinen)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 10 ++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 38 +++---
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../i915/gem/selftests/i915_gem_coherency.c | 10 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 4 +-
.../drm/i915/gem/selftests/i915_gem_phys.c| 2 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 52 +--
drivers/gpu/drm/i915/i915_gem.h | 11
drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++
drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +-
.../drm/i915/selftests/intel_memory_region.c | 2 +-
25 files changed, 174 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e1407dc28ddc..728796c6e4f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
{
- i915_gem_object_lock(vma->obj);
+ i915_gem_object_lock(vma->obj, NULL);
if (flags & PLANE_HAS_FENCE)
i915_vma_unpin_fence(vma);
i915_gem_object_unpin_from_display_plane(vma);
@@ -17013,7 +17013,7 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
if (!intel_fb->frontbuffer)
return -ENOMEM;
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
tiling = i915_gem_object_get_tiling(obj);
stride = i915_gem_object_get_stride(obj);
i915_gem_object_unlock(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index d3a86a4d5c04..c182091c00ff 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -286,7 +286,7 @@ int i915_gem_schedule_fill_pages_blt(struct
drm_i915_gem_object *obj,
dma_fence_init(>dma, _pages_work_ops, _lock, 0, 0);
i915_sw_fence_init(>wait, clear_pages_work_notify);
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
err = i915_sw_fence_await_reservation(>wait,
obj->base.resv, NULL, true, 0,
I915_FENCE_GFP);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 900ea8b7fc8f..7abb2deb1327 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx)
continue;
rcu_read_unlock();
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
list_for_each_entry(lut, >lut_list, obj_link) {
if (lut->ctx != ctx)
continue;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 7db5a793739d..cfadccfc2990 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf
*dma_buf, enum dma_data_dire
if (err)
return err;
- err = i915_gem_object_lock_interruptible(obj);
+ err = i915_gem_object_lock_interruptible(obj, NULL);
if (err)
goto out;
@@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf,
enum dma_data_direct
if (err)
return err;
- err = i915_gem_object_lock_interruptible(obj);
+
[Intel-gfx] [PATCH 06/23] drm/i915/gem: Make eb_add_lut interruptible wait on object lock.
The lock here should be interruptible, so we can backoff if needed.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 3bcaf9af590a..19f1eced78a3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -776,7 +776,12 @@ static int __eb_add_lut(struct i915_execbuffer *eb,
if (err == 0) { /* And nor has this handle */
struct drm_i915_gem_object *obj = vma->obj;
- i915_gem_object_lock(obj, NULL);
+ err = i915_gem_object_lock_interruptible(obj, NULL);
+ if (err) {
+ radix_tree_delete(>handles_vma, handle);
+ goto unlock;
+ }
+
if (idr_find(>file->object_idr, handle) == obj) {
list_add(>obj_link, >lut_list);
} else {
@@ -785,6 +790,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb,
}
i915_gem_object_unlock(obj);
}
+unlock:
mutex_unlock(>mutex);
}
if (unlikely(err))
--
2.26.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/23] drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin.
As a preparation step for full object locking and wait/wound handling
during pin and object mapping, ensure that we always pass the ww context
in i915_gem_execbuffer.c to i915_vma_pin, use lockdep to ensure this
happens.
This also requires changing the order of eb_parse slightly, to ensure
we pass ww at a point where we could still handle -EDEADLK safely.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 140 ++
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 4 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 4 +-
drivers/gpu/drm/i915/gt/intel_context.c | 65 +---
drivers/gpu/drm/i915/gt/intel_context.h | 13 ++
drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ring.c | 10 +-
drivers/gpu/drm/i915/gt/intel_ring.h | 3 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 15 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 12 +-
drivers/gpu/drm/i915/gt/intel_timeline.h | 3 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 13 +-
drivers/gpu/drm/i915/i915_gem.c | 11 +-
drivers/gpu/drm/i915/i915_vma.c | 13 +-
drivers/gpu/drm/i915/i915_vma.h | 13 +-
25 files changed, 215 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 728796c6e4f8..94bcf4ceca3a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3449,7 +3449,7 @@ initial_plane_vma(struct drm_i915_private *i915,
if (IS_ERR(vma))
goto err_obj;
- if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
+ if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
goto err_obj;
if (i915_gem_object_is_tiled(obj) &&
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c640f70f29f1..aaea0e51fd91 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1142,7 +1142,7 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
i915_gem_ww_ctx_init(, true);
retry:
- err = intel_context_pin(ce);
+ err = intel_context_pin_ww(ce, );
if (err)
goto err;
@@ -1235,7 +1235,7 @@ static int pin_ppgtt_update(struct intel_context *ce,
struct i915_gem_ww_ctx *ww
if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915))
/* ppGTT is not part of the legacy context image */
- return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm));
+ return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm), ww);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 35ff08441b4a..587f18142deb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -426,16 +426,17 @@ eb_pin_vma(struct i915_execbuffer *eb,
pin_flags |= PIN_GLOBAL;
/* Attempt to reuse the current location if available */
- if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) {
+ /* TODO: Add -EDEADLK handling here */
+ if (unlikely(i915_vma_pin_ww(vma, >ww, 0, 0, pin_flags))) {
if (entry->flags & EXEC_OBJECT_PINNED)
return false;
/* Failing that pick any _free_ space if suitable */
- if (unlikely(i915_vma_pin(vma,
- entry->pad_to_size,
- entry->alignment,
- eb_pin_flags(entry, ev->flags) |
- PIN_USER | PIN_NOEVICT)))
+ if (unlikely(i915_vma_pin_ww(vma, >ww,
+entry->pad_to_size,
+entry->alignment,
+eb_pin_flags(entry, ev->flags) |
+PIN_USER | PIN_NOEVICT)))
return false;
}
@@ -576,7 +577,7 @@ static inline int use_cpu_reloc(const struct reloc_cache
*cache,
obj->cache_level != I915_CACHE_NONE);
[Intel-gfx] [PATCH 09/23] drm/i915: Add ww context handling to context_barrier_task
This is required if we want to pass a ww context in intel_context_pin
and gen6_ppgtt_pin().
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 55 ++-
.../drm/i915/gem/selftests/i915_gem_context.c | 22 +++-
2 files changed, 48 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 7abb2deb1327..c640f70f29f1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1094,6 +1094,7 @@ I915_SELFTEST_DECLARE(static intel_engine_mask_t
context_barrier_inject_fault);
static int context_barrier_task(struct i915_gem_context *ctx,
intel_engine_mask_t engines,
bool (*skip)(struct intel_context *ce, void
*data),
+ int (*pin)(struct intel_context *ce, struct
i915_gem_ww_ctx *ww, void *data),
int (*emit)(struct i915_request *rq, void
*data),
void (*task)(void *data),
void *data)
@@ -1101,6 +1102,7 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
struct context_barrier_task *cb;
struct i915_gem_engines_iter it;
struct i915_gem_engines *e;
+ struct i915_gem_ww_ctx ww;
struct intel_context *ce;
int err = 0;
@@ -1138,10 +1140,21 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
if (skip && skip(ce, data))
continue;
- rq = intel_context_create_request(ce);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = intel_context_pin(ce);
+ if (err)
+ goto err;
+
+ if (pin)
+ err = pin(ce, , data);
+ if (err)
+ goto err_unpin;
+
+ rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- break;
+ goto err_unpin;
}
err = 0;
@@ -1151,6 +1164,16 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
err = i915_active_add_request(>base, rq);
i915_request_add(rq);
+err_unpin:
+ intel_context_unpin(ce);
+err:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+
if (err)
break;
}
@@ -1206,6 +1229,17 @@ static void set_ppgtt_barrier(void *data)
i915_vm_close(old);
}
+static int pin_ppgtt_update(struct intel_context *ce, struct i915_gem_ww_ctx
*ww, void *data)
+{
+ struct i915_address_space *vm = ce->vm;
+
+ if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915))
+ /* ppGTT is not part of the legacy context image */
+ return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm));
+
+ return 0;
+}
+
static int emit_ppgtt_update(struct i915_request *rq, void *data)
{
struct i915_address_space *vm = rq->context->vm;
@@ -1262,20 +1296,10 @@ static int emit_ppgtt_update(struct i915_request *rq,
void *data)
static bool skip_ppgtt_update(struct intel_context *ce, void *data)
{
- if (!test_bit(CONTEXT_ALLOC_BIT, >flags))
- return true;
-
if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
- return false;
-
- if (!atomic_read(>pin_count))
- return true;
-
- /* ppGTT is not part of the legacy context image */
- if (gen6_ppgtt_pin(i915_vm_to_ppgtt(ce->vm)))
- return true;
-
- return false;
+ return !ce->state;
+ else
+ return !atomic_read(>pin_count);
}
static int set_ppgtt(struct drm_i915_file_private *file_priv,
@@ -1326,6 +1350,7 @@ static int set_ppgtt(struct drm_i915_file_private
*file_priv,
*/
err = context_barrier_task(ctx, ALL_ENGINES,
skip_ppgtt_update,
+ pin_ppgtt_update,
emit_ppgtt_update,
set_ppgtt_barrier,
old);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 76671f587b9d..1217f7a43069 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1917,8 +1917,8 @@ static int mock_context_barrier(void *arg)
return -ENOMEM;
counter = 0;
- err = context_barrier_task(ctx, 0,
- NULL, NULL,
[Intel-gfx] [PATCH 01/23] Revert "drm/i915/gem: Drop relocation slowpath".
This reverts commit 7dc8f1143778 ("drm/i915/gem: Drop relocation
slowpath"). We need the slowpath relocation for taking ww-mutex
inside the page fault handler, and we will take this mutex when
pinning all objects.
[mlankhorst: Adjusted for reloc_gpu_flush() changes]
Cc: Chris Wilson
Cc: Matthew Auld
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 246 +-
1 file changed, 245 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index e4fb6c372537..9be3938b591f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1706,7 +1706,9 @@ static int eb_relocate_vma(struct i915_execbuffer *eb,
struct eb_vma *ev)
* we would try to acquire the struct mutex again. Obviously
* this is bad and so lockdep complains vehemently.
*/
- copied = __copy_from_user(r, urelocs, count * sizeof(r[0]));
+ pagefault_disable();
+ copied = __copy_from_user_inatomic(r, urelocs, count *
sizeof(r[0]));
+ pagefault_enable();
if (unlikely(copied)) {
remain = -EFAULT;
goto out;
@@ -1754,6 +1756,246 @@ static int eb_relocate_vma(struct i915_execbuffer *eb,
struct eb_vma *ev)
return remain;
}
+static int
+eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
+{
+ const struct drm_i915_gem_exec_object2 *entry = ev->exec;
+ struct drm_i915_gem_relocation_entry *relocs =
+ u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < entry->relocation_count; i++) {
+ u64 offset = eb_relocate_entry(eb, ev, [i]);
+
+ if ((s64)offset < 0) {
+ err = (int)offset;
+ goto err;
+ }
+ }
+ err = 0;
+err:
+ reloc_cache_reset(>reloc_cache);
+ return err;
+}
+
+static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
+{
+ const char __user *addr, *end;
+ unsigned long size;
+ char __maybe_unused c;
+
+ size = entry->relocation_count;
+ if (size == 0)
+ return 0;
+
+ if (size > N_RELOC(ULONG_MAX))
+ return -EINVAL;
+
+ addr = u64_to_user_ptr(entry->relocs_ptr);
+ size *= sizeof(struct drm_i915_gem_relocation_entry);
+ if (!access_ok(addr, size))
+ return -EFAULT;
+
+ end = addr + size;
+ for (; addr < end; addr += PAGE_SIZE) {
+ int err = __get_user(c, addr);
+ if (err)
+ return err;
+ }
+ return __get_user(c, end - 1);
+}
+
+static int eb_copy_relocations(const struct i915_execbuffer *eb)
+{
+ struct drm_i915_gem_relocation_entry *relocs;
+ const unsigned int count = eb->buffer_count;
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < count; i++) {
+ const unsigned int nreloc = eb->exec[i].relocation_count;
+ struct drm_i915_gem_relocation_entry __user *urelocs;
+ unsigned long size;
+ unsigned long copied;
+
+ if (nreloc == 0)
+ continue;
+
+ err = check_relocations(>exec[i]);
+ if (err)
+ goto err;
+
+ urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
+ size = nreloc * sizeof(*relocs);
+
+ relocs = kvmalloc_array(size, 1, GFP_KERNEL);
+ if (!relocs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ /* copy_from_user is limited to < 4GiB */
+ copied = 0;
+ do {
+ unsigned int len =
+ min_t(u64, BIT_ULL(31), size - copied);
+
+ if (__copy_from_user((char *)relocs + copied,
+(char __user *)urelocs + copied,
+len))
+ goto end;
+
+ copied += len;
+ } while (copied < size);
+
+ /*
+* As we do not update the known relocation offsets after
+* relocating (due to the complexities in lock handling),
+* we need to mark them as invalid now so that we force the
+* relocation processing next time. Just in case the target
+* object is evicted and then rebound into its old
+* presumed_offset before the next execbuffer - if that
+* happened we would make the mistake of assuming that the
+* relocations were valid.
+*/
[Intel-gfx] [PATCH 18/23] drm/i915/selftests: Fix locking inversion in lrc selftest.
This function does not use intel_context_create_request, so it has
to use the same locking order as normal code. This is required to
shut up lockdep in selftests.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 8864e90bbfc6..2abbbdfbbfd1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4794,6 +4794,7 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
{
struct intel_context *ce;
struct i915_request *rq;
+ struct i915_gem_ww_ctx ww;
enum {
RING_START_IDX = 0,
RING_TAIL_IDX,
@@ -4808,7 +4809,11 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
if (IS_ERR(ce))
return PTR_ERR(ce);
- err = intel_context_pin(ce);
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_gem_object_lock(scratch->obj, );
+ if (!err)
+ err = intel_context_pin_ww(ce, );
if (err)
goto err_put;
@@ -4837,11 +4842,9 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
*cs++ = 0;
- i915_vma_lock(scratch);
err = i915_request_await_object(rq, scratch->obj, true);
if (!err)
err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(scratch);
i915_request_get(rq);
i915_request_add(rq);
@@ -4878,6 +4881,12 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
err_unpin:
intel_context_unpin(ce);
err_put:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
intel_context_put(ce);
return err;
}
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 22/23] drm/i915: Add ww locking to pin_to_display_plane
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 65 --
drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 +
2 files changed, 49 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 8ebceebd11b0..c0d153284984 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -37,6 +37,12 @@ void i915_gem_object_flush_if_display(struct
drm_i915_gem_object *obj)
i915_gem_object_unlock(obj);
}
+void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj)
+{
+ if (i915_gem_object_is_framebuffer(obj))
+ __i915_gem_object_flush_for_display(obj);
+}
+
/**
* Moves a single object to the WC read, and possibly write domain.
* @obj: object to act on
@@ -197,18 +203,12 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
if (ret)
return ret;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
-
/* Always invalidate stale cachelines */
if (obj->cache_level != cache_level) {
i915_gem_object_set_cache_coherency(obj, cache_level);
obj->cache_dirty = true;
}
- i915_gem_object_unlock(obj);
-
/* The cache-level will be applied when each vma is rebound. */
return i915_gem_object_unbind(obj,
I915_GEM_OBJECT_UNBIND_ACTIVE |
@@ -255,6 +255,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void
*data,
struct drm_i915_gem_caching *args = data;
struct drm_i915_gem_object *obj;
enum i915_cache_level level;
+ struct i915_gem_ww_ctx ww;
int ret = 0;
switch (args->caching) {
@@ -293,7 +294,18 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev,
void *data,
goto out;
}
- ret = i915_gem_object_set_cache_level(obj, level);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ ret = i915_gem_object_lock(obj, );
+ if (!ret)
+ ret = i915_gem_object_set_cache_level(obj, level);
+
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff();
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
out:
i915_gem_object_put(obj);
@@ -313,6 +325,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
unsigned int flags)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct i915_gem_ww_ctx ww;
struct i915_vma *vma;
int ret;
@@ -320,6 +333,11 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj))
return ERR_PTR(-EINVAL);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ ret = i915_gem_object_lock(obj, );
+ if (ret)
+ goto err;
/*
* The display engine is not coherent with the LLC cache on gen6. As
* a result, we make sure that the pinning that is about to occur is
@@ -334,7 +352,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
HAS_WT(i915) ?
I915_CACHE_WT : I915_CACHE_NONE);
if (ret)
- return ERR_PTR(ret);
+ goto err;
/*
* As the user may map the buffer once pinned in the display plane
@@ -347,18 +365,31 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
vma = ERR_PTR(-ENOSPC);
if ((flags & PIN_MAPPABLE) == 0 &&
(!view || view->type == I915_GGTT_VIEW_NORMAL))
- vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
- flags |
- PIN_MAPPABLE |
- PIN_NONBLOCK);
- if (IS_ERR(vma))
- vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
- if (IS_ERR(vma))
- return vma;
+ vma = i915_gem_object_ggtt_pin_ww(obj, , view, 0, alignment,
+ flags | PIN_MAPPABLE |
+ PIN_NONBLOCK);
+ if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK))
+ vma = i915_gem_object_ggtt_pin_ww(obj, , view, 0,
+ alignment, flags);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto err;
+ }
vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
- i915_gem_object_flush_if_display(obj);
+ i915_gem_object_flush_if_display_locked(obj);
+
+err:
+
[Intel-gfx] [PATCH 08/23] drm/i915: Use ww locking in intel_renderstate.
We want to start using ww locking in intel_context_pin, for this
we need to lock multiple objects, and the single i915_gem_object_lock
is not enough.
Convert to using ww-waiting, and make sure we always pin intel_context_state,
even if we don't have a renderstate object.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_gt.c | 21 +++---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 78 ++---
drivers/gpu/drm/i915/gt/intel_renderstate.h | 9 ++-
3 files changed, 72 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f069551e412f..3c674aa76dae 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -398,21 +398,20 @@ static int __engines_record_defaults(struct intel_gt *gt)
/* We must be able to switch to something! */
GEM_BUG_ON(!engine->kernel_context);
- err = intel_renderstate_init(, engine);
- if (err)
- goto out;
-
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
err = PTR_ERR(ce);
goto out;
}
- rq = intel_context_create_request(ce);
+ err = intel_renderstate_init(, ce);
+ if (err)
+ goto err;
+
+ rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- intel_context_put(ce);
- goto out;
+ goto err_fini;
}
err = intel_engine_emit_ctx_wa(rq);
@@ -426,9 +425,13 @@ static int __engines_record_defaults(struct intel_gt *gt)
err_rq:
requests[id] = i915_request_get(rq);
i915_request_add(rq);
- intel_renderstate_fini();
- if (err)
+err_fini:
+ intel_renderstate_fini(, ce);
+err:
+ if (err) {
+ intel_context_put(ce);
goto out;
+ }
}
/* Flush the default context image to memory, and enable powersaving. */
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c
b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index d133e6b40d6c..a289f22ced3b 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -27,6 +27,7 @@
#include "i915_drv.h"
#include "intel_renderstate.h"
+#include "gt/intel_context.h"
#include "intel_ring.h"
static const struct intel_renderstate_rodata *
@@ -74,10 +75,9 @@ static int render_state_setup(struct intel_renderstate *so,
u32 *d;
int ret;
- i915_gem_object_lock(so->vma->obj, NULL);
ret = i915_gem_object_prepare_write(so->vma->obj, _clflush);
if (ret)
- goto out_unlock;
+ return ret;
d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0));
@@ -158,8 +158,6 @@ static int render_state_setup(struct intel_renderstate *so,
ret = 0;
out:
i915_gem_object_finish_access(so->vma->obj);
-out_unlock:
- i915_gem_object_unlock(so->vma->obj);
return ret;
err:
@@ -171,33 +169,47 @@ static int render_state_setup(struct intel_renderstate
*so,
#undef OUT_BATCH
int intel_renderstate_init(struct intel_renderstate *so,
- struct intel_engine_cs *engine)
+ struct intel_context *ce)
{
- struct drm_i915_gem_object *obj;
+ struct intel_engine_cs *engine = ce->engine;
+ struct drm_i915_gem_object *obj = NULL;
int err;
memset(so, 0, sizeof(*so));
so->rodata = render_state_get_rodata(engine);
- if (!so->rodata)
- return 0;
+ if (so->rodata) {
+ if (so->rodata->batch_items * 4 > PAGE_SIZE)
+ return -EINVAL;
+
+ obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ so->vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
+ if (IS_ERR(so->vma)) {
+ err = PTR_ERR(so->vma);
+ goto err_obj;
+ }
+ }
- if (so->rodata->batch_items * 4 > PAGE_SIZE)
- return -EINVAL;
+ i915_gem_ww_ctx_init(>ww, true);
+retry:
+ err = intel_context_pin(ce);
+ if (err)
+ goto err_fini;
- obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ /* return early if there's nothing to setup */
+ if (!err && !so->rodata)
+ return 0;
- so->vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
- if (IS_ERR(so->vma)) {
-
[Intel-gfx] [PATCH 17/23] drm/i915: Dirty hack to fix selftests locking inversion
Some i915 selftests still use i915_vma_lock() as inner lock, and intel_context_create_request() intel_timeline->mutex as outer lock. Fortunately for selftests this is not an issue, they should be fixed but we can move ahead and cleanify lockdep now. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_context.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 64948386630f..fe9fff5a63b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -459,6 +459,18 @@ struct i915_request *intel_context_create_request(struct intel_context *ce) rq = i915_request_create(ce); intel_context_unpin(ce); + if (IS_ERR(rq)) + return rq; + + /* +* timeline->mutex should be the inner lock, but is used as outer lock. +* Hack around this to shut up lockdep in selftests.. +*/ + lockdep_unpin_lock(>timeline->mutex, rq->cookie); + mutex_release(>timeline->mutex.dep_map, _RET_IP_); + mutex_acquire(>timeline->mutex.dep_map, SINGLE_DEPTH_NESTING, 0, _RET_IP_); + rq->cookie = lockdep_pin_lock(>timeline->mutex); + return rq; } -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
