[Intel-gfx] ✓ Fi.CI.BAT: success for Memory leak fix
== Series Details == Series: Memory leak fix URL : https://patchwork.freedesktop.org/series/82319/ State : success == Summary == CI Bug Log - changes from CI_DRM_9091 -> Patchwork_18609 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/index.html Known issues Here are the changes found in Patchwork_18609 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-byt-j1900/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-byt-j1900/igt@i915_module_l...@reload.html * igt@i915_selftest@live@coherency: - fi-gdg-551: [PASS][3] -> [DMESG-FAIL][4] ([i915#1748]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-gdg-551/igt@i915_selftest@l...@coherency.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-gdg-551/igt@i915_selftest@l...@coherency.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html * igt@vgem_basic@unload: - fi-skl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#2203]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-skl-guc/igt@vgem_ba...@unload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-skl-guc/igt@vgem_ba...@unload.html - fi-kbl-x1275: [PASS][9] -> [DMESG-WARN][10] ([i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@vgem_ba...@unload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-kbl-x1275/igt@vgem_ba...@unload.html Possible fixes * igt@kms_busy@basic@flip: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@kms_busy@ba...@flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-kbl-x1275/igt@kms_busy@ba...@flip.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [DMESG-WARN][13] ([i915#2203]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html Warnings * igt@gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][19] ([i915#62]) -> [DMESG-FAIL][20] ([i915#62] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-kbl-x1275/igt@i915_pm_...@module-reload.html * igt@kms_flip@basic-flip-vs-modeset@a-dp1: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-mode...@a-dp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18609/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-mode...@a-dp1.html * igt@kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@kms_force_connector_ba...@prune-stale-modes.html [24]:
[Intel-gfx] [PATCH] Memory leak fix
Static analysis detected a memory leak if the second kmalloc fails
and the first allocation is not freed.
Signed-off-by: Steve Hampson
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 12b30075134a..c8be7534a2fb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -234,8 +234,10 @@ i915_gem_userptr_init__mmu_notifier(struct
drm_i915_gem_object *obj,
return PTR_ERR(mn);
mo = kzalloc(sizeof(*mo), GFP_KERNEL);
- if (!mo)
+ if (!mo) {
+ kfree(mn);
return -ENOMEM;
+ }
mo->mn = mn;
mo->obj = obj;
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [drm-intel:drm-intel-next-queued 14/14] drivers/gpu/drm/i915/display/intel_lspcon.c:533:6: warning: no previous prototype for 'lspcon_init'
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: f542d671ffcec772a561cd41c7e2394392d9dafb
commit: f542d671ffcec772a561cd41c7e2394392d9dafb [14/14] drm/i915: Init lspcon
after HPD in intel_dp_detect()
config: x86_64-rhel (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
git remote add drm-intel git://anongit.freedesktop.org/drm-intel
git fetch --no-tags drm-intel drm-intel-next-queued
git checkout f542d671ffcec772a561cd41c7e2394392d9dafb
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_lspcon.c:533:6: warning: no previous
>> prototype for 'lspcon_init' [-Wmissing-prototypes]
533 | bool lspcon_init(struct intel_digital_port *dig_port)
| ^~~
vim +/lspcon_init +533 drivers/gpu/drm/i915/display/intel_lspcon.c
357c0ae9198ad7f drivers/gpu/drm/i915/intel_lspcon.c Imre Deak
2016-11-21 532
7801f3b792b0fd1 drivers/gpu/drm/i915/display/intel_lspcon.c Lucas De Marchi
2020-06-30 @533 bool lspcon_init(struct intel_digital_port *dig_port)
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 534 {
7801f3b792b0fd1 drivers/gpu/drm/i915/display/intel_lspcon.c Lucas De Marchi
2020-06-30 535 struct intel_dp *dp = _port->dp;
7801f3b792b0fd1 drivers/gpu/drm/i915/display/intel_lspcon.c Lucas De Marchi
2020-06-30 536 struct intel_lspcon *lspcon = _port->lspcon;
668b6c176c33f44 drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2018-10-12 537 struct drm_connector *connector =
>attached_connector->base;
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 538
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 539 lspcon->active = false;
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 540 lspcon->mode = DRM_LSPCON_MODE_INVALID;
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 541
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 542 if (!lspcon_probe(lspcon)) {
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 543 DRM_ERROR("Failed to probe lspcon\n");
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 544 return false;
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 545 }
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 546
b9936121d95b012 drivers/gpu/drm/i915/display/intel_lspcon.c Lyude Paul
2020-08-26 547 if (drm_dp_read_dpcd_caps(>aux, dp->dpcd) != 0) {
24e807e79f103cd drivers/gpu/drm/i915/intel_lspcon.c Imre Deak
2016-10-24 548 DRM_ERROR("LSPCON DPCD read failed\n");
24e807e79f103cd drivers/gpu/drm/i915/intel_lspcon.c Imre Deak
2016-10-24 549 return false;
24e807e79f103cd drivers/gpu/drm/i915/intel_lspcon.c Imre Deak
2016-10-24 550 }
24e807e79f103cd drivers/gpu/drm/i915/intel_lspcon.c Imre Deak
2016-10-24 551
96e35598cead98d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2018-10-12 552 if (!lspcon_detect_vendor(lspcon)) {
96e35598cead98d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2018-10-12 553 DRM_ERROR("LSPCON vendor detection failed\n");
96e35598cead98d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2018-10-12 554 return false;
96e35598cead98d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2018-10-12 555 }
12a47a422862214 drivers/gpu/drm/i915/intel_lspcon.c Imre Deak
2016-10-24 556
668b6c176c33f44 drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2018-10-12 557 connector->ycbcr_420_allowed = true;
96e35598cead98d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2018-10-12 558 lspcon->active = true;
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 559 DRM_DEBUG_KMS("Success: LSPCON init\n");
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 560 return true;
dbe9e61b8e4306d drivers/gpu/drm/i915/intel_lspcon.c Shashank Sharma
2016-10-14 561 }
f542d671ffcec77 drivers/gpu/drm/i915/display/intel_lspcon.c Kai-Heng Feng
2020-06-10 562
:: The code at line 533 was first introduced by commit
:: 7801f3b792b0fd171b02f2cb974e758295e68e0f drm/i915/display: prefer
dig_port to reference intel_digital_port
:: TO: Lucas De Marchi
:: CC: Lucas De Marchi
---
0-DAY CI
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/jsl: Update JSL Voltage swing table
== Series Details ==
Series: drm/i915/jsl: Update JSL Voltage swing table
URL : https://patchwork.freedesktop.org/series/82313/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9091 -> Patchwork_18608
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_18608 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18608, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_18608:
### IGT changes ###
Possible regressions
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
Known issues
Here are the changes found in Patchwork_18608 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-kbl-x1275: [PASS][3] -> [INCOMPLETE][4] ([i915#794])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
* igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html
* igt@vgem_basic@unload:
- fi-skl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#2203])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-skl-guc/igt@vgem_ba...@unload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-skl-guc/igt@vgem_ba...@unload.html
- fi-kbl-x1275: [PASS][9] -> [DMESG-WARN][10] ([i915#62] / [i915#92])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@vgem_ba...@unload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-kbl-x1275/igt@vgem_ba...@unload.html
Possible fixes
* igt@kms_busy@basic@flip:
- {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-tgl-dsi/igt@kms_busy@ba...@flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-tgl-dsi/igt@kms_busy@ba...@flip.html
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95])
-> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-WARN][15] ([i915#2203]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
Warnings
* igt@debugfs_test@read_all_entries:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) ->
[DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#1982] / [i915#62] / [i915#92]
/ [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9091/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18608/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
* igt@i915_pm_rpm@module-reload:
-
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/jsl: Update JSL Voltage swing table
== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82313/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_lspcon.c:533:6: warning: symbol 'lspcon_init' was not declared. Should it be static? +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/jsl: Update JSL Voltage swing table
== Series Details ==
Series: drm/i915/jsl: Update JSL Voltage swing table
URL : https://patchwork.freedesktop.org/series/82313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7c3e877540c1 drm/i915/jsl: Split EHL/JSL platform info and PCI ids
-:156: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around
'pll->info->id == DPLL_ID_EHL_DPLL4'
#156: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:155:
+ if (IS_EHL_JSL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
-:258: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible
side-effects?
#258: FILE: drivers/gpu/drm/i915/i915_drv.h:1420:
+#define IS_EHL_JSL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
+ IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
-:375: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#375: FILE: include/drm/i915_pciids.h:592:
+#define INTEL_JSL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4E71, info), \
INTEL_VGA_DEVICE(0x4E61, info), \
INTEL_VGA_DEVICE(0x4E57, info), \
INTEL_VGA_DEVICE(0x4E55, info), \
-:375: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible
side-effects?
#375: FILE: include/drm/i915_pciids.h:592:
+#define INTEL_JSL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4E71, info), \
INTEL_VGA_DEVICE(0x4E61, info), \
INTEL_VGA_DEVICE(0x4E57, info), \
INTEL_VGA_DEVICE(0x4E55, info), \
total: 1 errors, 0 warnings, 3 checks, 273 lines checked
5b220796eaf0 drm/i915/edp/jsl: Update vswing table for HBR and HBR2
-:94: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#94: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1227:
+ return jsl_combo_phy_ddi_translations_edp_hbr2;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 145 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
JSL has update in vswing table for eDP.
BSpec: 21257
Changes since V2 :
- Added IS_EHL_JSL to replace IS_ELKHARTLAKE
- EHL/JSL PCI ids split added
- Changes rebased as per new drm top commit
Changes since V1 :
- IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with
HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively
- Reverted EHL/JSL PCI ids split change
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/intel_ddi.c | 95 ++--
1 file changed, 89 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4c520348b3b..6c67232247ec 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans
ehl_combo_phy_ddi_translations_dp[] = {
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
};
+static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[]
= {
+ /* NT mV Trans mV db*/
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200 200 0.0 */
+ { 0x8, 0x7F, 0x38, 0x00, 0x07 },/* 200 250 1.9 */
+ { 0x1, 0x7F, 0x33, 0x00, 0x0C },/* 200 300 3.5 */
+ { 0xA, 0x35, 0x36, 0x00, 0x09 },/* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 250 250 0.0 */
+ { 0x1, 0x7F, 0x38, 0x00, 0x07 },/* 250 300 1.6 */
+ { 0xA, 0x35, 0x35, 0x00, 0x0A },/* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 300 300 0.0 */
+ { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 300 350 1.3 */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans
jsl_combo_phy_ddi_translations_edp_hbr2[] = {
+ /* NT mV Trans mV db*/
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200 200 0.0 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200 250 1.9 */
+ { 0x1, 0x7F, 0x3D, 0x00, 0x02 },/* 200 300 3.5 */
+ { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 250 250 0.0 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 250 300 1.6 */
+ { 0xA, 0x35, 0x3A, 0x00, 0x05 },/* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 300 300 0.0 */
+ { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 300 350 1.3 */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -1167,6 +1195,57 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder,
return ehl_get_combo_buf_trans_dp(encoder, crtc_state,
n_entries);
}
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+int *n_entries)
+{
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+}
+
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+ return icl_combo_phy_ddi_translations_dp_hbr2;
+}
+
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (dev_priv->vbt.edp.low_vswing) {
+ if (crtc_state->port_clock > 27) {
+ *n_entries =
ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
+ return jsl_combo_phy_ddi_translations_edp_hbr2;
+ } else {
+ *n_entries =
ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
+ return jsl_combo_phy_ddi_translations_edp_hbr;
+ }
+ }
+
+ return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state,
[Intel-gfx] [PATCH v3 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
Split the basic platform definition, macros, and PCI IDs to
differentiate between EHL and JSL platforms.
Changes since V2 :
- Added IS_EHL_JSL to replace IS_ELKHARTLAKE
- EHL/JSL PCI ids split added
Changes since V1 :
- IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with
HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively
- Reverted EHL/JSL PCI ids split change
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display.c | 8
drivers/gpu/drm/i915/display/intel_dp.c| 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 5 +++--
drivers/gpu/drm/i915/i915_pci.c| 9 +
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pch.c | 6 +++---
include/drm/i915_pciids.h | 9 ++---
14 files changed, 45 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index fe946a2e2082..fee23ac14edd 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
- if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
+ if (IS_EHL_JSL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
tmp = intel_de_read(dev_priv,
ICL_PORT_PCS_DW1_AUX(phy));
tmp &= ~LATENCY_OPTIM_MASK;
@@ -612,7 +612,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
}
}
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_EHL_JSL(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys) {
tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cb93f6cf6d37..2f39a4dc72f9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2588,7 +2588,7 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
*/
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_EHL_JSL(dev_priv)) {
if (dev_priv->cdclk.hw.ref == 24000)
dev_priv->max_cdclk_freq = 552000;
else
@@ -2815,7 +2815,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
- } else if (IS_ELKHARTLAKE(dev_priv)) {
+ } else if (IS_EHL_JSL(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 157d8c8c605a..acc7b0098026 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -188,7 +188,7 @@ static bool has_phy_misc(struct drm_i915_private *i915,
enum phy phy)
* PHY-B and may not even have instances of the register for the
* other combo PHY's.
*/
- if (IS_ELKHARTLAKE(i915) ||
+ if (IS_EHL_JSL(i915) ||
IS_ROCKETLAKE(i915))
return phy < PHY_C;
@@ -282,7 +282,7 @@ static bool icl_combo_phy_verify_state(struct
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
IREFGEN, IREFGEN);
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_EHL_JSL(dev_priv)) {
if (ehl_vbt_ddi_d_present(dev_priv))
expected_val = ICL_PHY_MISC_MUX_DDID;
@@ -376,7 +376,7 @@ static void icl_combo_phys_init(struct drm_i915_private
*dev_priv)
* "internal" child devices.
*/
val = intel_de_read(dev_priv,
[Intel-gfx] [PATCH v3 0/2] drm/i915/jsl: Update JSL Voltage swing table
Patch series covers following thigns: 1. Split and differentiate between EHL and JSL platfrom 2. Update voltage swing table for eDP on JSL platform Changes since V2 : - Added IS_EHL_JSL to replace IS_ELKHARTLAKE - EHL/JSL PCI ids split added - Rebased to drm master commit Changes since V1 : - IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively - Reverted EHL/JSL PCI ids split change Tejas Upadhyay (2): drm/i915/jsl: Split EHL/JSL platform info and PCI ids drm/i915/edp/jsl: Update vswing table for HBR and HBR2 drivers/gpu/drm/i915/display/icl_dsi.c| 4 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 4 +- .../gpu/drm/i915/display/intel_combo_phy.c| 6 +- drivers/gpu/drm/i915/display/intel_ddi.c | 95 +-- drivers/gpu/drm/i915/display/intel_display.c | 8 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++-- drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/i915_pci.c | 9 ++ drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_pch.c | 6 +- include/drm/i915_pciids.h | 9 +- 15 files changed, 134 insertions(+), 36 deletions(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 0/7] Convert the intel iommu driver to the dma-iommu api
Hi Lu, On 2020-09-27 12:34 a.m., Lu Baolu wrote: > Hi, > > The previous post of this series could be found here. > > https://lore.kernel.org/linux-iommu/20200912032200.11489-1-baolu...@linux.intel.com/ > > This version introduce a new patch [4/7] to fix an issue reported here. > > https://lore.kernel.org/linux-iommu/51a1baec-48d1-c0ac-181b-1fba92aa4...@linux.intel.com/ > > There aren't any other changes. > > Please help to test and review. I've tested this patchset on my Sandy Bridge machine and found no issues (while including a patch to ioat I've sent to that maintainer). Tested-By: Logan Gunthorpe Thanks, Logan ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt. hard-coded PLL freqs
On Thu, Oct 01, 2020 at 07:44:29PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 29, 2020 at 03:29:27AM +0300, Imre Deak wrote:
> > When selecting the WRPLL dividers for a given port clock/PLL freq, the
> > hard-coded PLL freq in a table entry can be calculated using the rest of
> > parameters in the same entry. Cross-check if the hard coded values match
> > what we calculate with the formula.
>
> We've never done this on any other plaform I think. Why is this special?
clock in icl_combo_pll_params is already defined by WRPLL params in the
same entry along with refclock. The driver needs to calculate already
this same clock when reading out the PLL HW state, so I thought it makes
sense to determine clock from WRPLL params when looking up an entry from
the PLL params table.
It's also used by the last patch in the patchset that needs to calculate
the clock both with the fractional divider WA applied and not applied.
> Also, shouldn't the state checker catch this anyway?
Afaics the PLL state verification only checks if the calculated /
programmed WRPLL parameters match what we read out. But the point in
this patch was only to make the table lookup and the clock calculation
during HW readout uniform.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 26 ++-
> > 1 file changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index e3370c8dccc8..ded2b2dfe319 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -3002,6 +3002,30 @@ static const struct skl_wrpll_params
> > tgl_tbt_pll_38_4MHz_values = {
> > .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
> > };
> >
> > +static int icl_wrpll_ref_clock(struct drm_i915_private *i915);
> > +
> > +static bool icl_dp_combo_pll_clock_match(struct drm_i915_private *i915,
> > int clock,
> > +const struct icl_combo_pll_params *p)
> > +{
> > + int ref_clock = icl_wrpll_ref_clock(i915);
> > + int pll_freq;
> > + u32 pdiv;
> > + u32 qdiv;
> > + u32 kdiv;
> > +
> > + cnl_wrpll_decode_divs(>wrpll, , , );
> > +
> > + pll_freq = skl_wrpll_calc_freq(ref_clock,
> > + p->wrpll.dco_integer,
> > p->wrpll.dco_fraction,
> > + pdiv, qdiv, kdiv);
> > + drm_WARN_ON(>drm, pll_freq != p->clock);
> > +
> > + if (clock == pll_freq)
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> > struct skl_wrpll_params *pll_params)
> > {
> > @@ -3014,7 +3038,7 @@ static bool icl_calc_dp_combo_pll(struct
> > intel_crtc_state *crtc_state,
> > int i;
> >
> > for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
> > - if (clock == params[i].clock) {
> > + if (icl_dp_combo_pll_clock_match(dev_priv, clock, [i])) {
> > *pll_params = params[i].wrpll;
> > return true;
> > }
> > --
> > 2.25.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/6] drm/i915: Shut down displays gracefully on reboot
== Series Details == Series: series starting with [v2,1/6] drm/i915: Shut down displays gracefully on reboot URL : https://patchwork.freedesktop.org/series/82308/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9089_full -> Patchwork_18607_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18607_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18607_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18607_full: ### IGT changes ### Possible regressions * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-iclb1/igt@gem_ctx_isolation@preservation...@bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-iclb3/igt@gem_ctx_isolation@preservation...@bcs0.html Known issues Here are the changes found in Patchwork_18607_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2389]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-glk8/igt@gem_exec_reloc@basic-many-act...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-glk9/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-skl: [PASS][5] -> [TIMEOUT][6] ([i915#1958] / [i915#2424]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-skl10/igt@gem_userptr_bl...@sync-unmap-cycles.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-skl6/igt@gem_userptr_bl...@sync-unmap-cycles.html * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-glk2/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-glk5/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +12 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-skl1/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-skl2/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html * igt@kms_flip@blocking-wf_vblank@a-edp1: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-tglb5/igt@kms_flip@blocking-wf_vbl...@a-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-tglb8/igt@kms_flip@blocking-wf_vbl...@a-edp1.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-kbl6/igt@kms_flip@flip-vs-susp...@c-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-kbl6/igt@kms_flip@flip-vs-susp...@c-dp1.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-iclb3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-iclb6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-skl4/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-skl6/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][19] -> [DMESG-FAIL][20] ([fdo#108145] / [i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_primary_blt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) [21]:
Re: [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers
On Thu, 2020-10-01 at 12:24 +0100, Mun, Gwan-gyeong wrote:
> On Thu, 2020-09-24 at 10:42 -0700, José Roberto de Souza wrote:
> > Another step towards PSR2 selective fetch, here programming plane
> > selective fetch registers and MAN_TRK_CTL enabling selective fetch
> > but
> > for now it is fetching the whole area of the planes.
> > The damaged area calculation will come as next and final step.
> >
> > v2:
> > - removed warn on when no plane is visible in state
> > - removed calculations using plane damaged area in
> > intel_psr2_program_plane_sel_fetch()
> >
> > v3:
> > - do not shift 16 positions the plane dst coordinates, only src is
> > shifted
> >
> > v4:
> > - only setting PLANE_SEL_FETCH_CTL_ENABLE and MCURSOR_MODE in
> > PLANE_SEL_FETCH_CTL
> >
> > BSpec: 55229
> > Cc: Gwan-gyeong Mun <
> > gwan-gyeong@intel.com
> > >
> > Cc: Ville Syrjälä <
> > ville.syrj...@linux.intel.com
> > >
> > Signed-off-by: José Roberto de Souza <
> > jose.so...@intel.com
> > >
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> > drivers/gpu/drm/i915/display/intel_psr.c | 118
> > ++-
> > drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> > drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> > 4 files changed, 132 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 5a9d933e425a..96bc515497c1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> > intel_plane *plane,
> > if (INTEL_GEN(dev_priv) >= 9)
> > skl_write_cursor_wm(plane, crtc_state);
> >
> > + if (!needs_modeset(crtc_state))
> > + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> > plane_state, 0);
> > +
> > if (plane->cursor.base != base ||
> > plane->cursor.size != fbc_ctl ||
> > plane->cursor.cntl != cntl) {
> > @@ -12823,8 +12826,11 @@ static int intel_crtc_atomic_check(struct
> > intel_atomic_state *state,
> >
> > }
> >
> > - if (!mode_changed)
> > - intel_psr2_sel_fetch_update(state, crtc);
> > + if (!mode_changed) {
> > + ret = intel_psr2_sel_fetch_update(state, crtc);
> > + if (ret)
> > + return ret;
> > + }
> >
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 02f74b0ddec1..f6e0a192d5e5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1166,6 +1166,39 @@ static void psr_force_hw_tracking_exit(struct
> > drm_i915_private *dev_priv)
> > intel_psr_exit(dev_priv);
> > }
> >
> > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct intel_plane_state
> > *plane_state,
> > + int color_plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum pipe pipe = plane->pipe;
> > + u32 val;
> > +
> > + if (!crtc_state->enable_psr2_sel_fetch)
> > + return;
> > +
> > + val = plane_state ? plane_state->ctl : 0;
> > + val = plane->id == PLANE_CURSOR ? val & MCURSOR_MODE :
> > + val &
> > PLANE_SEL_FETCH_CTL_ENABLE;
>
> I could not find details of MCURSOR_MODE for selective_fetch. (on bspec
> 50420) why do you set MCURSOR_MODE here?
Bsepc: 55229
SEL_FETCH_CUR_CTL Cursor Mode Select = If update region, translated to pipe
source coordinates, overlaps this cursor ? CUR_CTL Cursor Mode Select :
Disable
Oh and I missed this: Program the other fields in SEL_FETCH_CUR_CTL to match
CUR_CTL.
So the v3 version of this patch is better, unless you still think that
SEL_FETCH_PLANE_CTL only needs to have the bit 31 set, like I said spares are
different than reserved, we can set spares.
>
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> > > id), val);
> >
> > + if (!val || plane->id == PLANE_CURSOR)
> > + return;
> > +
>
> in order to set just PLANE_SEL_FETCH_CTL_ENABLE bit, I suggest to use
> like this
> val = intel_de_read_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> > id));
>
> intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> val|PLANE_SEL_FETCH_CTL_ENABLE);
All the plane and pipe programming must be fast to not evade vblank, so
registers reads are not a good idea here.
Also why? plane_state->ctl will have the same value as the register for gen11+.
>
> > + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> > > uapi.dst.x1;
> >
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> > > id), val);
> >
> > +
> > + val =
Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt. hard-coded PLL freqs
On Thu, Oct 01, 2020 at 07:44:29PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 29, 2020 at 03:29:27AM +0300, Imre Deak wrote:
> > When selecting the WRPLL dividers for a given port clock/PLL freq, the
> > hard-coded PLL freq in a table entry can be calculated using the rest of
> > parameters in the same entry. Cross-check if the hard coded values match
> > what we calculate with the formula.
>
> We've never done this on any other plaform I think. Why is this special?
I think if we do this we should do at init time for all such tables.
Ideally we'd do it at compile time but no constexpr in C :(
> Also, shouldn't the state checker catch this anyway?
>
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 26 ++-
> > 1 file changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index e3370c8dccc8..ded2b2dfe319 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -3002,6 +3002,30 @@ static const struct skl_wrpll_params
> > tgl_tbt_pll_38_4MHz_values = {
> > .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
> > };
> >
> > +static int icl_wrpll_ref_clock(struct drm_i915_private *i915);
> > +
> > +static bool icl_dp_combo_pll_clock_match(struct drm_i915_private *i915,
> > int clock,
> > +const struct icl_combo_pll_params *p)
> > +{
> > + int ref_clock = icl_wrpll_ref_clock(i915);
> > + int pll_freq;
> > + u32 pdiv;
> > + u32 qdiv;
> > + u32 kdiv;
> > +
> > + cnl_wrpll_decode_divs(>wrpll, , , );
> > +
> > + pll_freq = skl_wrpll_calc_freq(ref_clock,
> > + p->wrpll.dco_integer,
> > p->wrpll.dco_fraction,
> > + pdiv, qdiv, kdiv);
> > + drm_WARN_ON(>drm, pll_freq != p->clock);
> > +
> > + if (clock == pll_freq)
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> > struct skl_wrpll_params *pll_params)
> > {
> > @@ -3014,7 +3038,7 @@ static bool icl_calc_dp_combo_pll(struct
> > intel_crtc_state *crtc_state,
> > int i;
> >
> > for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
> > - if (clock == params[i].clock) {
> > + if (icl_dp_combo_pll_clock_match(dev_priv, clock, [i])) {
> > *pll_params = params[i].wrpll;
> > return true;
> > }
> > --
> > 2.25.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
--
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
On Thu, Oct 01, 2020 at 07:41:48PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 29, 2020 at 03:29:25AM +0300, Imre Deak wrote:
> > The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> > the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> > bit#0 incorrectly set.
> >
> > This happens with the
> >
> > "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
> >
> > HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
> >
> > ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
> >
> > WRPLL parameters (assuming PDIV=7 was the intended setting). This
> > corresponds to 262749 PLL frequency/port clock.
> >
> > Later the driver sets the same mode for which it calculates the same
> > dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
> >
> > Based on the above, let's assume that PDIV=7 was intended and the HW
> > just ignores bit#0 in the PDIV register field for this setting, treating
> > 100b and 101b encodings the same way.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 9 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index e08684e34078..095b53fe3a21 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -1602,6 +1602,14 @@ static int skl_ddi_wrpll_get_freq(struct
> > drm_i915_private *i915,
> > case DPLL_CFGCR2_PDIV_3:
> > p0 = 3;
> > break;
> > + case DPLL_CFGCR2_PDIV_7 | (1 << DPLL_CFGCR2_PDIV_SHIFT):
>
> Maybe we want a define for this?
Ok.
>
> > + /*
> > +* Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore
> > bit#0,
> > +* handling it the same way as PDIV_7.
> > +*/
> > + drm_err(>drm, "Invalid WRPLL PDIV divider value, fixing
> > it.\n");
>
> I wonder how many bug reports that will generate. Might want to make
> it debug insteead.
I thought having reports for this is actually good, since BIOS vendors
should be notified then, but can change this to debug.
>
> > + p0 = 7;
> > + break;
>
> Or maybe fallthrough?
can do if you have an idea how to do that with the MISSING_CASE() added
later setting pdiv=7 by default.
>
> > case DPLL_CFGCR2_PDIV_7:
> > p0 = 7;
> > break;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 47730a176698..f70e45bd3810 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10253,6 +10253,7 @@ enum skl_power_gate {
> > #define DPLL_CFGCR2_KDIV_3 (2 << 5)
> > #define DPLL_CFGCR2_KDIV_1 (3 << 5)
> > #define DPLL_CFGCR2_PDIV_MASK (7 << 2)
> > +#define DPLL_CFGCR2_PDIV_SHIFT2
> > #define DPLL_CFGCR2_PDIV(x) ((x) << 2)
> > #define DPLL_CFGCR2_PDIV_1 (0 << 2)
> > #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> > --
> > 2.25.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
On Tue, Sep 29, 2020 at 03:29:28AM +0300, Imre Deak wrote:
> Apply Display WA #22010492432 for combo PHY PLLs too. This should fix a
> problem where the PLL output frequency is slightly off with the current
> PLL fractional divider value.
>
> I haven't seen an actual case where this causes a problem, but let's
> follow the spec. It's also needed on some EHL platforms, but for that we
> also need a way to distinguish the affected EHL SKUs, so I leave that
> for a follow-up.
>
> v2:
> - Apply the WA at one place when calculating the PLL dividers from the
> frequency and the frequency from the dividers for all the combo PLL
> use cases (DP, HDMI, TBT). (Ville)
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 34 +++
> 1 file changed, 20 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index ded2b2dfe319..e7b058340a1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2694,6 +2694,16 @@ static void cnl_wrpll_decode_divs(const struct
> skl_wrpll_params *wrpll_params,
> }
> }
>
> +/*
> + * Display WA #22010492432: tgl
> + * Program half of the nominal DCO divider fraction value.
> + */
> +static bool
> +tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
> +{
> + return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
> +}
> +
> static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> const struct intel_shared_dpll *pll,
> int ref_clock)
> @@ -2719,6 +2729,9 @@ static int __cnl_ddi_wrpll_get_freq(struct
> drm_i915_private *dev_priv,
> dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> DPLL_CFGCR0_DCO_FRACTION_SHIFT;
>
> + if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
> + dco_fraction *= 2;
> +
> return skl_wrpll_calc_freq(ref_clock, dco_integer, dco_fraction, pdiv,
> qdiv, kdiv);
> }
>
> @@ -2992,16 +3005,6 @@ static const struct skl_wrpll_params
> tgl_tbt_pll_24MHz_values = {
> /* the following params are unused */
> };
>
> -/*
> - * Display WA #22010492432: tgl
> - * Divide the nominal .dco_fraction value by 2.
> - */
> -static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = {
> - .dco_integer = 0x54, .dco_fraction = 0x1800,
> - /* the following params are unused */
> - .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
> -};
> -
> static int icl_wrpll_ref_clock(struct drm_i915_private *i915);
>
> static bool icl_dp_combo_pll_clock_match(struct drm_i915_private *i915, int
> clock,
> @@ -3059,14 +3062,12 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state
> *crtc_state,
> MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
> fallthrough;
> case 19200:
> + case 38400:
> *pll_params = tgl_tbt_pll_19_2MHz_values;
> break;
> case 24000:
> *pll_params = tgl_tbt_pll_24MHz_values;
> break;
> - case 38400:
> - *pll_params = tgl_tbt_pll_38_4MHz_values;
> - break;
> }
> } else {
> switch (dev_priv->dpll.ref_clks.nssc) {
> @@ -3133,9 +3134,14 @@ static void icl_calc_dpll_state(struct
> drm_i915_private *i915,
> const struct skl_wrpll_params *pll_params,
> struct intel_dpll_hw_state *pll_state)
> {
> + u32 dco_fraction = pll_params->dco_fraction;
> +
> memset(pll_state, 0, sizeof(*pll_state));
>
> - pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params->dco_fraction) |
> + if (tgl_combo_pll_div_frac_wa_needed(i915))
> + dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
> +
> + pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
> pll_params->dco_integer;
>
> pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
> --
> 2.25.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt. hard-coded PLL freqs
On Tue, Sep 29, 2020 at 03:29:27AM +0300, Imre Deak wrote:
> When selecting the WRPLL dividers for a given port clock/PLL freq, the
> hard-coded PLL freq in a table entry can be calculated using the rest of
> parameters in the same entry. Cross-check if the hard coded values match
> what we calculate with the formula.
We've never done this on any other plaform I think. Why is this special?
Also, shouldn't the state checker catch this anyway?
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 26 ++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e3370c8dccc8..ded2b2dfe319 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3002,6 +3002,30 @@ static const struct skl_wrpll_params
> tgl_tbt_pll_38_4MHz_values = {
> .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
> };
>
> +static int icl_wrpll_ref_clock(struct drm_i915_private *i915);
> +
> +static bool icl_dp_combo_pll_clock_match(struct drm_i915_private *i915, int
> clock,
> + const struct icl_combo_pll_params *p)
> +{
> + int ref_clock = icl_wrpll_ref_clock(i915);
> + int pll_freq;
> + u32 pdiv;
> + u32 qdiv;
> + u32 kdiv;
> +
> + cnl_wrpll_decode_divs(>wrpll, , , );
> +
> + pll_freq = skl_wrpll_calc_freq(ref_clock,
> +p->wrpll.dco_integer,
> p->wrpll.dco_fraction,
> +pdiv, qdiv, kdiv);
> + drm_WARN_ON(>drm, pll_freq != p->clock);
> +
> + if (clock == pll_freq)
> + return true;
> +
> + return false;
> +}
> +
> static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *pll_params)
> {
> @@ -3014,7 +3038,7 @@ static bool icl_calc_dp_combo_pll(struct
> intel_crtc_state *crtc_state,
> int i;
>
> for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
> - if (clock == params[i].clock) {
> + if (icl_dp_combo_pll_clock_match(dev_priv, clock, [i])) {
> *pll_params = params[i].wrpll;
> return true;
> }
> --
> 2.25.1
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
On Tue, Sep 29, 2020 at 03:29:25AM +0300, Imre Deak wrote:
> The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> bit#0 incorrectly set.
>
> This happens with the
>
> "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>
> HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
>
> ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
>
> WRPLL parameters (assuming PDIV=7 was the intended setting). This
> corresponds to 262749 PLL frequency/port clock.
>
> Later the driver sets the same mode for which it calculates the same
> dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
>
> Based on the above, let's assume that PDIV=7 was intended and the HW
> just ignores bit#0 in the PDIV register field for this setting, treating
> 100b and 101b encodings the same way.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e08684e34078..095b53fe3a21 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1602,6 +1602,14 @@ static int skl_ddi_wrpll_get_freq(struct
> drm_i915_private *i915,
> case DPLL_CFGCR2_PDIV_3:
> p0 = 3;
> break;
> + case DPLL_CFGCR2_PDIV_7 | (1 << DPLL_CFGCR2_PDIV_SHIFT):
Maybe we want a define for this?
> + /*
> + * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore
> bit#0,
> + * handling it the same way as PDIV_7.
> + */
> + drm_err(>drm, "Invalid WRPLL PDIV divider value, fixing
> it.\n");
I wonder how many bug reports that will generate. Might want to make
it debug insteead.
> + p0 = 7;
> + break;
Or maybe fallthrough?
> case DPLL_CFGCR2_PDIV_7:
> p0 = 7;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 47730a176698..f70e45bd3810 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10253,6 +10253,7 @@ enum skl_power_gate {
> #define DPLL_CFGCR2_KDIV_3 (2 << 5)
> #define DPLL_CFGCR2_KDIV_1 (3 << 5)
> #define DPLL_CFGCR2_PDIV_MASK (7 << 2)
> +#define DPLL_CFGCR2_PDIV_SHIFT 2
> #define DPLL_CFGCR2_PDIV(x) ((x) << 2)
> #define DPLL_CFGCR2_PDIV_1 (0 << 2)
> #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> --
> 2.25.1
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH tip/core/rcu 11/15] drm/i915: Cleanup PREEMPT_COUNT leftovers
On Thu, Oct 01, 2020 at 10:25:06AM +0200, Thomas Gleixner wrote: > On Thu, Oct 01 2020 at 10:17, Joonas Lahtinen wrote: > > Quoting paul...@kernel.org (2020-09-29 02:30:58) > >> CONFIG_PREEMPT_COUNT is now unconditionally enabled and will be > >> removed. Cleanup the leftovers before doing so. > > > > Change looks fine: > > > > Reviewed-by: Joonas Lahtinen Applied, thank you! > > Are you looking for us to merge or merge through another tree? > > > > If us, did the base patch always enabling PREEMPT_COUNT go into 5.9 or is > > it heading to 5.10? We can queue this earliest for 5.11 as drm-next closed > > for 5.10 at week of -rc5. > > If at all it goes through rcu/tip because it depends on the earlier patches. I was figuring on sending a pull request later today, Pacific Time. Thanx, Paul ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6] drm/i915: Init lspcon after HPD in intel_dp_detect()
On Wed, Jun 10, 2020 at 03:55:10PM +0800, Kai-Heng Feng wrote:
> On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port
> becomes useless and never responds to cable hotplugging:
> [3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon
> [3.031945] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port
> D
>
> Seems like the lspcon chip on the system only gets powered after the
> cable is plugged.
>
> Consilidate lspcon_init() into lspcon_resume() to dynamically init
> lspcon chip, and make HDMI port work.
>
> Signed-off-by: Kai-Heng Feng
> ---
> v6:
> - Rebase on latest for-linux-next.
>
> v5:
> - Consolidate lspcon_resume() with lspcon_init().
> - Move more logic into lspcon code.
>
> v4:
> - Trust VBT in intel_infoframe_init().
> - Init lspcon in intel_dp_detect().
>
> v3:
> - Make sure it's handled under long HPD case.
>
> v2:
> - Move lspcon_init() inside of intel_dp_hpd_pulse().
Hoisted the changelog above --- where it belongs in drm land,
amended with
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/203
and pushed the patch to dinq.
Thanks, and sorry for the horrendous latency.
PS. This will cause some headache for Uma's lspcon HDR stuff, but
so be it.
>
> drivers/gpu/drm/i915/display/intel_ddi.c| 19 +--
> drivers/gpu/drm/i915/display/intel_dp.c | 10 ++--
> drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +-
> drivers/gpu/drm/i915/display/intel_lspcon.c | 63 -
> drivers/gpu/drm/i915/display/intel_lspcon.h | 3 +-
> 5 files changed, 43 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index aa22465bb56e..af755b1aa24b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4805,7 +4805,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> {
> struct intel_digital_port *intel_dig_port;
> struct intel_encoder *encoder;
> - bool init_hdmi, init_dp, init_lspcon = false;
> + bool init_hdmi, init_dp;
> enum phy phy = intel_port_to_phy(dev_priv, port);
>
> init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
> @@ -4819,7 +4819,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
>* is initialized before lspcon.
>*/
> init_dp = true;
> - init_lspcon = true;
> init_hdmi = false;
> drm_dbg_kms(_priv->drm, "VBT says port %c has lspcon\n",
> port_name(port));
> @@ -4904,22 +4903,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> goto err;
> }
>
> - if (init_lspcon) {
> - if (lspcon_init(intel_dig_port))
> - /* TODO: handle hdmi info frame part */
> - drm_dbg_kms(_priv->drm,
> - "LSPCON init success on port %c\n",
> - port_name(port));
> - else
> - /*
> - * LSPCON init faied, but DP init was success, so
> - * lets try to drive as DP++ port.
> - */
> - drm_err(_priv->drm,
> - "LSPCON init failed on port %c\n",
> - port_name(port));
> - }
> -
> if (INTEL_GEN(dev_priv) >= 11) {
> if (intel_phy_is_tc(dev_priv, phy))
> intel_dig_port->connected = intel_tc_port_connected;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index ed9e53c373a7..398a104158a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5962,15 +5962,14 @@ static enum drm_connector_status
> intel_dp_detect_dpcd(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> u8 *dpcd = intel_dp->dpcd;
> u8 type;
>
> if (WARN_ON(intel_dp_is_edp(intel_dp)))
> return connector_status_connected;
>
> - if (lspcon->active)
> - lspcon_resume(lspcon);
> + lspcon_resume(dig_port);
>
> if (!intel_dp_get_dpcd(intel_dp))
> return connector_status_disconnected;
> @@ -7056,14 +7055,13 @@ void intel_dp_encoder_reset(struct drm_encoder
> *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
> - struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> intel_wakeref_t wakeref;
>
> if
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915: Shut down displays gracefully on reboot
== Series Details ==
Series: series starting with [v2,1/6] drm/i915: Shut down displays gracefully
on reboot
URL : https://patchwork.freedesktop.org/series/82308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9089 -> Patchwork_18607
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/index.html
Known issues
Here are the changes found in Patchwork_18607 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] /
[i915#95]) +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
* igt@vgem_basic@unload:
- fi-skl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#2203])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-skl-guc/igt@vgem_ba...@unload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-skl-guc/igt@vgem_ba...@unload.html
Possible fixes
* {igt@core_hotunplug@unbind-rebind}:
- fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-kbl-x1275/igt@core_hotunp...@unbind-rebind.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-kbl-x1275/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- {fi-kbl-7560u}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [DMESG-FAIL][19] ([i915#62]) -> [DMESG-FAIL][20]
([i915#62] / [i915#95])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [INCOMPLETE][21] ([i915#2203]) -> [DMESG-WARN][22]
([i915#2203])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18607/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) ->
[DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9089/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
[24]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/6] drm/i915: Shut down displays gracefully on reboot
== Series Details == Series: series starting with [v2,1/6] drm/i915: Shut down displays gracefully on reboot URL : https://patchwork.freedesktop.org/series/82308/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Revert "drm/i915: Force state->modeset=true when distrust_bios_wm==true"
On Wed, Sep 30, 2020 at 03:47:06PM +0200, Stefan Joosten wrote: > The fix of flagging state->modeset whenever distrust_bios_wm is set > causes a regression when initializing display(s) attached to a Lenovo > USB-C docking station. The display remains blank until the dock is > reattached. Revert to bring the behavior of the functional v5.6 stable. > > This reverts commit 0f8839f5f323da04a800e6ced1136e4b1e1689a9. > > BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1879442 > Signed-off-by: Stefan Joosten > --- > drivers/gpu/drm/i915/display/intel_display.c | 14 -- > 1 file changed, 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index b18c5ac2934d..ece1c28278f7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -14942,20 +14942,6 @@ static int intel_atomic_check(struct drm_device *dev, > if (ret) > goto fail; > > - /* > - * distrust_bios_wm will force a full dbuf recomputation > - * but the hardware state will only get updated accordingly > - * if state->modeset==true. Hence distrust_bios_wm==true && > - * state->modeset==false is an invalid combination which > - * would cause the hardware and software dbuf state to get > - * out of sync. We must prevent that. > - * > - * FIXME clean up this mess and introduce better > - * state tracking for dbuf. > - */ > - if (dev_priv->wm.distrust_bios_wm) > - any_ms = true; > - Argh. If only I had managed to land the full dbuf rework and nuke this mess before it came back to bite us... This is definitely going to break something else, so not great. Can you file an upstream bug at https://gitlab.freedesktop.org/drm/intel/issues/new and attach dmesgs from booting both good and bad kernels with drm.debug=0x1e passed to the kernel cmdline? Bump log_buf_len= if necessary to capture the full log. > intel_fbc_choose_crtc(dev_priv, state); > ret = calc_watermark_data(state); > if (ret) > -- > 2.25.4 > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/6] drm/i915: Replace the VLV/CHV eDP reboot notifier with the .shutdown() hook
From: Ville Syrjälä
Currently VLV/CHV use a reboot notifier to make sure the panel
power cycle delay isn't violated across a system reboot. Replace
that with the new encoder .shutdown() hook.
And let's also stop overriding the power cycle delay with the
max value. No idea why the current code does that. The already
programmed delay should be correct.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 2 -
drivers/gpu/drm/i915/display/intel_dp.c | 58 +--
2 files changed, 14 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6f3e3d756383..9b9ed1a2f412 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1319,8 +1319,6 @@ struct intel_dp {
unsigned long last_backlight_off;
ktime_t panel_power_off_time;
- struct notifier_block edp_notifier;
-
/*
* Pipe whose power sequencer is currently locked into
* this port. Only relevant on VLV/CHV.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 70e0b85442f9..e0f2e9236785 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -28,7 +28,6 @@
#include
#include
#include
-#include
#include
#include
@@ -1191,41 +1190,6 @@ _pp_stat_reg(struct intel_dp *intel_dp)
return regs.pp_stat;
}
-/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
- This function only applicable when panel PM state is not to be tracked */
-static int edp_notify_handler(struct notifier_block *this, unsigned long code,
- void *unused)
-{
- struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
-edp_notifier);
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- intel_wakeref_t wakeref;
-
- if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
- return 0;
-
- with_pps_lock(intel_dp, wakeref) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
- i915_reg_t pp_ctrl_reg, pp_div_reg;
- u32 pp_div;
-
- pp_ctrl_reg = PP_CONTROL(pipe);
- pp_div_reg = PP_DIVISOR(pipe);
- pp_div = intel_de_read(dev_priv, pp_div_reg);
- pp_div &= PP_REFERENCE_DIVIDER_MASK;
-
- /* 0x1F write to PP_DIV_REG sets max cycle delay */
- intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
- intel_de_write(dev_priv, pp_ctrl_reg,
- PANEL_UNLOCK_REGS);
- msleep(intel_dp->panel_power_cycle_delay);
- }
- }
-
- return 0;
-}
-
static bool edp_have_panel_power(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -6690,11 +6654,6 @@ void intel_dp_encoder_flush_work(struct drm_encoder
*encoder)
*/
with_pps_lock(intel_dp, wakeref)
edp_panel_vdd_off_sync(intel_dp);
-
- if (intel_dp->edp_notifier.notifier_call) {
- unregister_reboot_notifier(_dp->edp_notifier);
- intel_dp->edp_notifier.notifier_call = NULL;
- }
}
intel_dp_aux_fini(intel_dp);
@@ -6725,6 +6684,18 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
edp_panel_vdd_off_sync(intel_dp);
}
+static void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
+ intel_wakeref_t wakeref;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ with_pps_lock(intel_dp, wakeref)
+ wait_panel_power_cycle(intel_dp);
+}
+
static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -7838,9 +7809,6 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
mutex_unlock(>mode_config.mutex);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- intel_dp->edp_notifier.notifier_call = edp_notify_handler;
- register_reboot_notifier(_dp->edp_notifier);
-
/*
* Figure out the current pipe for the initial backlight setup.
* If the current pipe isn't valid, try the PPS pipe, and if
that
@@ -8061,6 +8029,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->get_config = intel_dp_get_config;
[Intel-gfx] [PATCH v2 5/6] drm/i915: Wait for LVDS panel power cycle delay on reboot
From: Ville Syrjälä
Just like with eDP let's wait for the power sequencer power
cycle delay before we reboot the machine, as otherwise we
can't guarantee the panel's minimum power cycle delay will
be respected.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_lvds.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
b/drivers/gpu/drm/i915/display/intel_lvds.c
index e65c2de522c3..c6c7c0b9989b 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -371,6 +371,15 @@ static void pch_post_disable_lvds(struct
intel_atomic_state *state,
intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
}
+static void intel_lvds_shutdown(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0),
PP_CYCLE_DELAY_ACTIVE, 5000))
+ drm_err(_priv->drm,
+ "timed out waiting for panel power cycle delay\n");
+}
+
static enum drm_mode_status
intel_lvds_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -897,6 +906,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
intel_encoder->get_hw_state = intel_lvds_get_hw_state;
intel_encoder->get_config = intel_lvds_get_config;
intel_encoder->update_pipe = intel_panel_update_backlight;
+ intel_encoder->shutdown = intel_lvds_shutdown;
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector_attach_encoder(intel_connector, intel_encoder);
--
2.26.2
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[Intel-gfx] [PATCH v2 6/6] drm/i915: Wait for VLV/CHV/BXT/GLK DSI panel power cycle delay on reboot
From: Ville Syrjälä
As with eDP and LVDS we should also respect the power cycle
delay on DSI panels. We are not using the power sequencer
for these, and we have no optimizations around the sleep
duration, so we just msleep() the whole thing away.
Note that the ICL+ DSI code doesn't seem to have any power
off/power cycle delay handling whatsoever. The only thing it
handles is the power on delay. As that looks pretty busted
in general I won't bother dealing with it for the time being.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/vlv_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 5e5522923b1e..d52f9c177908 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -985,6 +985,13 @@ static void intel_dsi_post_disable(struct
intel_atomic_state *state,
intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
}
+static void intel_dsi_shutdown(struct intel_encoder *encoder)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+
+ intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
+}
+
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
@@ -1843,6 +1850,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
intel_encoder->get_hw_state = intel_dsi_get_hw_state;
intel_encoder->get_config = intel_dsi_get_config;
intel_encoder->update_pipe = intel_panel_update_backlight;
+ intel_encoder->shutdown = intel_dsi_shutdown;
intel_connector->get_hw_state = intel_connector_get_hw_state;
--
2.26.2
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[Intel-gfx] [PATCH v2 4/6] drm/i915: Wait for eDP panel power cycle delay on reboot on all platforms
From: Ville Syrjälä
Extend the eDP panel power cycle delay wait on reboot handling
to cover all platforms. No reason to think that VLV/CHV are
in any way special since the documentation states that the
hardware power cycle delay goes back to its default value on
reset, and that may not be enough for all panels.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5742394c8292..e3fcd2591a6c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5175,6 +5175,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
encoder->suspend = intel_dp_encoder_suspend;
+ encoder->shutdown = intel_dp_encoder_shutdown;
encoder->get_power_domains = intel_ddi_get_power_domains;
encoder->type = INTEL_OUTPUT_DDI;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index e0f2e9236785..3a14a003b4c9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6684,7 +6684,7 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
edp_panel_vdd_off_sync(intel_dp);
}
-static void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
+void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
{
struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
intel_wakeref_t wakeref;
@@ -8029,8 +8029,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_encoder->get_config = intel_dp_get_config;
intel_encoder->update_pipe = intel_panel_update_backlight;
intel_encoder->suspend = intel_dp_encoder_suspend;
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- intel_encoder->shutdown = intel_dp_encoder_shutdown;
+ intel_encoder->shutdown = intel_dp_encoder_shutdown;
if (IS_CHERRYVIEW(dev_priv)) {
intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
intel_encoder->pre_enable = chv_pre_enable_dp;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 66854aab9887..7466498d4c01 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -57,6 +57,7 @@ void intel_dp_sink_set_decompression_state(struct intel_dp
*intel_dp,
bool enable);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
+void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
int intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
--
2.26.2
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[Intel-gfx] [PATCH v2 2/6] drm/i915: Add an encoder .shutdown() hook
From: Ville Syrjälä
Add a new encoder hook .shutdown() which will get called at the end
of the pci .shutdown() hook. We shall use this to deal with the
panel power cycle delay issues.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display_types.h | 5 +
drivers/gpu/drm/i915/i915_drv.c| 13 +
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5dc18cb8c39..6f3e3d756383 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -199,6 +199,11 @@ struct intel_encoder {
* device interrupts are disabled.
*/
void (*suspend)(struct intel_encoder *);
+ /*
+* Called during system reboot/shutdown after all the
+* encoders have been disabled and suspended.
+*/
+ void (*shutdown)(struct intel_encoder *encoder);
enum hpd_pin hpd_pin;
enum intel_display_power_domain power_domain;
/* for communication with audio component; protected by av_mutex */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 062b61ebd9c4..d38fceb239ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1036,6 +1036,18 @@ static void intel_suspend_encoders(struct
drm_i915_private *dev_priv)
drm_modeset_unlock_all(dev);
}
+static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
+{
+ struct drm_device *dev = _priv->drm;
+ struct intel_encoder *encoder;
+
+ drm_modeset_lock_all(dev);
+ for_each_intel_encoder(dev, encoder)
+ if (encoder->shutdown)
+ encoder->shutdown(encoder);
+ drm_modeset_unlock_all(dev);
+}
+
void i915_driver_shutdown(struct drm_i915_private *i915)
{
i915_gem_suspend(i915);
@@ -1050,6 +1062,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_hpd_cancel_work(i915);
intel_suspend_encoders(i915);
+ intel_shutdown_encoders(i915);
}
static bool suspend_to_idle(struct drm_i915_private *dev_priv)
--
2.26.2
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[Intel-gfx] [PATCH v2 1/6] drm/i915: Shut down displays gracefully on reboot
From: Ville Syrjälä
Implement the pci .shutdown() hook in order to quiesce the
hardware prior to reboot. The main purpose here is to turn
all displays off. Some displays/other drivers tend to get
confused if the state after reboot isn't exactly as they
expected.
One specific example was the Dell UP2414Q in MST mode.
It would require me to pull the power cord after a reboot
or else it would just not come back to life. Sadly I don't
have that at hand anymore so not sure if it's still
misbehaving without the graceful shutdown, or if we
managed to fix something else since I last tested it.
For good measure we do a gem suspend as well, so that
we match the suspend flow more closely. Also stopping
all DMA and whatnot is probably a good idea for kexec.
I would expect that some kind of GT reset happens on
normal reboot so probably not totally necessary there.
v2: Use the pci .shutdown() hook instead of a reboot notifier (Lukas)
Do the gem suspend for kexec (Chris)
Cc: Lukas Wunner
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 16
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 8
3 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 45e719c79183..062b61ebd9c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1036,6 +1036,22 @@ static void intel_suspend_encoders(struct
drm_i915_private *dev_priv)
drm_modeset_unlock_all(dev);
}
+void i915_driver_shutdown(struct drm_i915_private *i915)
+{
+ i915_gem_suspend(i915);
+
+ drm_kms_helper_poll_disable(>drm);
+
+ drm_atomic_helper_shutdown(>drm);
+
+ intel_dp_mst_suspend(i915);
+
+ intel_runtime_pm_disable_interrupts(i915);
+ intel_hpd_cancel_work(i915);
+
+ intel_suspend_encoders(i915);
+}
+
static bool suspend_to_idle(struct drm_i915_private *dev_priv)
{
#if IS_ENABLED(CONFIG_ACPI_SLEEP)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eef9a821c49c..9c2672c56cc1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1779,6 +1779,7 @@ extern const struct dev_pm_ops i915_pm_ops;
int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
void i915_driver_remove(struct drm_i915_private *i915);
+void i915_driver_shutdown(struct drm_i915_private *i915);
int i915_resume_switcheroo(struct drm_i915_private *i915);
int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 366ddfc8df6b..249730561b6c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1090,11 +1090,19 @@ static int i915_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
return 0;
}
+static void i915_pci_shutdown(struct pci_dev *pdev)
+{
+ struct drm_i915_private *i915 = pci_get_drvdata(pdev);
+
+ i915_driver_shutdown(i915);
+}
+
static struct pci_driver i915_pci_driver = {
.name = DRIVER_NAME,
.id_table = pciidlist,
.probe = i915_pci_probe,
.remove = i915_pci_remove,
+ .shutdown = i915_pci_shutdown,
.driver.pm = _pm_ops,
};
--
2.26.2
___
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Re: [Intel-gfx] linux-next: manual merge of the akpm tree with the drm-intel tree
On Thu, Oct 1, 2020 at 5:08 PM Jani Nikula wrote:
>
> On Thu, 01 Oct 2020, Daniel Vetter wrote:
> > On Thu, Oct 1, 2020 at 3:53 PM Christoph Hellwig wrote:
> >>
> >> On Thu, Oct 01, 2020 at 08:39:17PM +1000, Stephen Rothwell wrote:
> >> > Hi all,
> >> >
> >> > Today's linux-next merge of the akpm tree got a conflict in:
> >> >
> >> > drivers/gpu/drm/i915/gem/i915_gem_pages.c
> >> >
> >> > between commit:
> >> >
> >> > 4caf017ee937 ("drm/i915/gem: Avoid implicit vmap for highmem on
> >> > x86-32")
> >> > ba2ebf605d5f ("drm/i915/gem: Prevent using pgprot_writecombine() if
> >> > PAT is not supported")
> >
> > Uh these patches shouldn't be in linux-next because they're for 5.11,
> > not the 5.10 merge window that will open soon. Joonas?
>
> I don't know anything else, but both are tagged Cc: stable.
Uh right I got confused, they're on -fixes now. Well -next-fixes,
which seems like the wrong one for a cc: stable, I guess this should
go into 5.9 even. Apologies for my confusion.
-Daniel
>
> BR,
> Jani.
>
> >
> >> > from the drm-intel tree and patch:
> >> >
> >> > "drm/i915: use vmap in i915_gem_object_map"
> >> >
> >> > from the akpm tree.
> >> >
> >> > I fixed it up (I just dropped the changes in the former commits) and
> >>
> >> Sigh. The solution is a bit more complicated, but I just redid my
> >> patches to not depend on the above ones. I can revert back to the old
> >> version, though. Andrew, let me know what works for you.
> >
> > Imo ignore, rebasing onto linux-next without those intel patches was
> > the right thing for the 5.10 merge window.
> > -Daniel
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] linux-next: manual merge of the akpm tree with the drm-intel tree
On Thu, 01 Oct 2020, Daniel Vetter wrote:
> On Thu, Oct 1, 2020 at 3:53 PM Christoph Hellwig wrote:
>>
>> On Thu, Oct 01, 2020 at 08:39:17PM +1000, Stephen Rothwell wrote:
>> > Hi all,
>> >
>> > Today's linux-next merge of the akpm tree got a conflict in:
>> >
>> > drivers/gpu/drm/i915/gem/i915_gem_pages.c
>> >
>> > between commit:
>> >
>> > 4caf017ee937 ("drm/i915/gem: Avoid implicit vmap for highmem on x86-32")
>> > ba2ebf605d5f ("drm/i915/gem: Prevent using pgprot_writecombine() if PAT
>> > is not supported")
>
> Uh these patches shouldn't be in linux-next because they're for 5.11,
> not the 5.10 merge window that will open soon. Joonas?
I don't know anything else, but both are tagged Cc: stable.
BR,
Jani.
>
>> > from the drm-intel tree and patch:
>> >
>> > "drm/i915: use vmap in i915_gem_object_map"
>> >
>> > from the akpm tree.
>> >
>> > I fixed it up (I just dropped the changes in the former commits) and
>>
>> Sigh. The solution is a bit more complicated, but I just redid my
>> patches to not depend on the above ones. I can revert back to the old
>> version, though. Andrew, let me know what works for you.
>
> Imo ignore, rebasing onto linux-next without those intel patches was
> the right thing for the 5.10 merge window.
> -Daniel
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v6 23/24] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
On Wed, Sep 30, 2020 at 10:16:02PM -0700, Lucas De Marchi wrote:
> On Wed, Sep 30, 2020 at 10:20:41AM -0700, Matt Roper wrote:
> > On Tue, Sep 29, 2020 at 11:42:33PM -0700, Lucas De Marchi wrote:
> > > From: Anshuman Gupta
> > >
> > > DGFX devices have different DMC_DEBUG* counter MMIO address
> > > offset. Incorporate these changes in i915_reg.h for DG1
> > > and handle i915_dmc_info accordingly.
> > >
> > > Cc: Uma Shankar
> > > Signed-off-by: Anshuman Gupta
> > > Signed-off-by: Lucas De Marchi
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++--
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > 2 files changed, 8 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > index 0bf31f9a8af5..472f119fe246 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > @@ -518,8 +518,13 @@ static int i915_dmc_info(struct seq_file *m, void
> > > *unused)
> > > CSR_VERSION_MINOR(csr->version));
> > >
> > > if (INTEL_GEN(dev_priv) >= 12) {
> > > - dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > - dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > + if (IS_DG1(dev_priv)) {
> >
> > I think we'd want IS_DGFX here since this change should hold true for
> > any future dgfx platform as well. Aside from that,
>
> not sure where this info came from, but it's not true. Not having DC6 is
> not related to being DGFX an future platforms may as well support it.
My comment here was referring to the fact that the DMC_DEBUG registers
move to the new sgunit offsets. All future dgfx would be expected to
follow that trend; future igfx could potentially go either way.
Matt
>
> >
> > Reviewed-by: Matt Roper
> >
> > I notice the bspec does have a new DC6 residency register offset listed
> > as well, which seems odd if we don't have DC6 support on this platform.
> >
>
> previous version of this patch was defining that but it's unused so I
> removed it.
>
> Lucas De Marchi
>
> >
> > Matt
> >
> >
> > > + dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > > + } else {
> > > + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > + }
> > > +
> > > /*
> > >* NOTE: DMC_DEBUG3 is a general purpose reg.
> > >* According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index bb5094b80f15..b856a1fb0a32 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7538,6 +7538,7 @@ enum {
> > > #define BXT_CSR_DC3_DC5_COUNT_MMIO(0x80038)
> > > #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
> > > #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
> > > +#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
> > >
> > > #define DMC_DEBUG3 _MMIO(0x101090)
> > >
> > > --
> > > 2.28.0
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] linux-next: manual merge of the akpm tree with the drm-intel tree
On Thu, Oct 1, 2020 at 3:53 PM Christoph Hellwig wrote:
>
> On Thu, Oct 01, 2020 at 08:39:17PM +1000, Stephen Rothwell wrote:
> > Hi all,
> >
> > Today's linux-next merge of the akpm tree got a conflict in:
> >
> > drivers/gpu/drm/i915/gem/i915_gem_pages.c
> >
> > between commit:
> >
> > 4caf017ee937 ("drm/i915/gem: Avoid implicit vmap for highmem on x86-32")
> > ba2ebf605d5f ("drm/i915/gem: Prevent using pgprot_writecombine() if PAT
> > is not supported")
Uh these patches shouldn't be in linux-next because they're for 5.11,
not the 5.10 merge window that will open soon. Joonas?
> > from the drm-intel tree and patch:
> >
> > "drm/i915: use vmap in i915_gem_object_map"
> >
> > from the akpm tree.
> >
> > I fixed it up (I just dropped the changes in the former commits) and
>
> Sigh. The solution is a bit more complicated, but I just redid my
> patches to not depend on the above ones. I can revert back to the old
> version, though. Andrew, let me know what works for you.
Imo ignore, rebasing onto linux-next without those intel patches was
the right thing for the 5.10 merge window.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code
On Wed, Sep 30, 2020 at 02:34:38AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Another attempt at plumbing the crtc state to the depths of
> the link training code. This time I tried to preserve the
> PHY test stuff in a somewhat working condition.
>
> The DDI buf trans stuff also started to bug me again so had
> to toss in a few cleanups in that area. Still pretty messy,
> but with a bit more regular structure we could perhaps toss
> in a few vfuncs to get rid of some if ladders at least.
> Not entirely sure yet...
Pushed to dinq. Thanks for the reviews.
>
> Ville Syrjälä (11):
> drm/i915: s/pre_empemph/preemph/
> drm/i915: s/old_crtc_state/crtc_state/
> drm/i915: Make intel_dp_process_phy_request() static
> drm/i915: Shove the PHY test into the hotplug work
> drm/i915: Split ICL combo PHY buf trans per output type
> drm/i915: Split ICL MG PHY buf trans per output type
> drm/i915: Split EHL combo PHY buf trans per output type
> drm/i915: Split TGL combo PHY buf trans per output type
> drm/i915: Split TGL DKL PHY buf trans per output type
> drm/i915: Plumb crtc_state to link training
> drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}
>
> drivers/gpu/drm/i915/display/intel_ddi.c | 677 ++
> drivers/gpu/drm/i915/display/intel_ddi.h | 11 +-
> .../drm/i915/display/intel_display_types.h| 25 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 289 ++--
> drivers/gpu/drm/i915/display/intel_dp.h | 11 +-
> .../drm/i915/display/intel_dp_link_training.c | 102 +--
> .../drm/i915/display/intel_dp_link_training.h | 8 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 +-
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 23 +-
> drivers/gpu/drm/i915/display/intel_dpio_phy.h | 2 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 7 +-
> 11 files changed, 718 insertions(+), 461 deletions(-)
>
> --
> 2.26.2
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] linux-next: manual merge of the akpm tree with the drm-intel tree
On Thu, Oct 01, 2020 at 08:39:17PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the akpm tree got a conflict in:
>
> drivers/gpu/drm/i915/gem/i915_gem_pages.c
>
> between commit:
>
> 4caf017ee937 ("drm/i915/gem: Avoid implicit vmap for highmem on x86-32")
> ba2ebf605d5f ("drm/i915/gem: Prevent using pgprot_writecombine() if PAT is
> not supported")
>
> from the drm-intel tree and patch:
>
> "drm/i915: use vmap in i915_gem_object_map"
>
> from the akpm tree.
>
> I fixed it up (I just dropped the changes in the former commits) and
Sigh. The solution is a bit more complicated, but I just redid my
patches to not depend on the above ones. I can revert back to the old
version, though. Andrew, let me know what works for you.
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plumb crtc state to link training code (rev5)
== Series Details ==
Series: drm/i915: Plumb crtc state to link training code (rev5)
URL : https://patchwork.freedesktop.org/series/76993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9086_full -> Patchwork_18606_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18606_full:
### Piglit changes ###
Possible regressions
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-neg-ivec4-int
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][1] +7 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functi...@tcs-op-bitor-neg-ivec4-int.html
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-eq-mat2x3-mat2x3-using-if
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functi...@tcs-op-eq-mat2x3-mat2x3-using-if.html
New tests
-
New tests have been introduced between CI_DRM_9086_full and
Patchwork_18606_full:
### New Piglit tests (9) ###
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-ceil-vec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-neg-ivec4-int:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-not-ivec4-ivec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitxor-not-uvec3-uint:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-div-uvec2-uvec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-eq-mat2x3-mat2x3-using-if:
- Statuses : 1 crash(s)
- Exec time: [0.44] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-ne-uvec4-uvec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-sub-uint-uint:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-sub-vec3-float:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18606_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-iclb2/igt@feature_discov...@psr2.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-iclb8/igt@feature_discov...@psr2.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#644])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl7/igt@gem_pp...@flink-and-close-vma-leak.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl1/igt@gem_pp...@flink-and-close-vma-leak.html
* igt@i915_pm_dc@dc5-psr:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#1899])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-iclb2/igt@i915_pm...@dc5-psr.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-iclb8/igt@i915_pm...@dc5-psr.html
* igt@kms_cursor_crc@pipe-b-cursor-size-change:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#54])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-size-change.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-size-change.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#72])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#2346])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl5/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/shard-skl9/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
* igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled:
- shard-skl:
Re: [Intel-gfx] [PATCH v4 0/7] Convert the intel iommu driver to the dma-iommu api
Hi Baolu, On Tue, Sep 29, 2020 at 08:11:35AM +0800, Lu Baolu wrote: > I have no preference. It depends on which patch goes first. Let the > maintainers help here. No preference on my side, except that it is too late for this now to make it into v5.10. Besides that I let the decission up to you when this is ready. Just send me a pull-request when it should get into the iommu-tree. Regards, Joerg ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Skip over MI_NOOP when parsing (rev2)
== Series Details == Series: drm/i915: Skip over MI_NOOP when parsing (rev2) URL : https://patchwork.freedesktop.org/series/82268/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9086_full -> Patchwork_18605_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18605_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18605_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18605_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@execlists: - shard-glk: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-glk2/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-glk4/igt@i915_selftest@l...@execlists.html * igt@kms_flip@modeset-vs-vblank-race@a-hdmi-a1: - shard-hsw: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-hsw2/igt@kms_flip@modeset-vs-vblank-r...@a-hdmi-a1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-hsw4/igt@kms_flip@modeset-vs-vblank-r...@a-hdmi-a1.html Known issues Here are the changes found in Patchwork_18605_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#658]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-iclb2/igt@feature_discov...@psr2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-iclb3/igt@feature_discov...@psr2.html * igt@gem_exec_reloc@basic-gtt-cpu-active: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1635] / [i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-apl4/igt@gem_exec_re...@basic-gtt-cpu-active.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-apl1/igt@gem_exec_re...@basic-gtt-cpu-active.html * igt@gem_exec_whisper@basic-contexts-priority: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-glk7/igt@gem_exec_whis...@basic-contexts-priority.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-glk1/igt@gem_exec_whis...@basic-contexts-priority.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([i915#1436] / [i915#1635]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-apl4/igt@gem_workarou...@suspend-resume.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-apl4/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_dc@dc5-psr: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#1899]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-iclb2/igt@i915_pm...@dc5-psr.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-iclb3/igt@i915_pm...@dc5-psr.html * igt@kms_big_fb@linear-32bpp-rotate-0: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-glk5/igt@kms_big...@linear-32bpp-rotate-0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-glk8/igt@kms_big...@linear-32bpp-rotate-0.html * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl3/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-skl2/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1: - shard-glk: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plumb crtc state to link training code (rev5)
== Series Details == Series: drm/i915: Plumb crtc state to link training code (rev5) URL : https://patchwork.freedesktop.org/series/76993/ State : success == Summary == CI Bug Log - changes from CI_DRM_9086 -> Patchwork_18606 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/index.html Known issues Here are the changes found in Patchwork_18606 that come from known issues: ### IGT changes ### Issues hit * igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html Possible fixes * igt@i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-byt-j1900/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-byt-j1900/igt@i915_module_l...@reload.html - fi-icl-y: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-icl-y/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-icl-y/igt@i915_module_l...@reload.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [DMESG-WARN][7] ([i915#2203]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html * igt@vgem_basic@unload: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@vgem_ba...@unload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@vgem_ba...@unload.html Warnings * igt@gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][13] ([fdo#109271]) -> [DMESG-FAIL][14] ([i915#62]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@i915_pm_...@module-reload.html * igt@kms_flip@basic-flip-vs-dpms@a-dp1: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-d...@a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-d...@a-dp1.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18606/fi-kbl-x1275/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (45 -> 38) -- Additional (1): fi-tgl-dsi Missing(8): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_9086 -> Patchwork_18606 CI-20190529: 20190529 CI_DRM_9086: b86053f8eb427de294c64eea6b3554c78326bd10 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5796: 19ae9421a5af7b03a1c9a577c57f2cf8b16a0116 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18606: 17947177aa4e93a32bad457c7225b1f59dbe611d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits ==
Re: [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2
On Wed, 30 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"
wrote:
> -Original Message-
> From: Intel-gfx On Behalf Of José
> Roberto de Souza
> Sent: 29 September 2020 01:33
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2
>
> Recent update in documentation defeatured eDP HBR3 for EHL and JSL.
>
> v2:
> - Remove dead code in ehl_get_combo_buf_trans()
>
> BSpec: 32247
> Cc: Matt Roper
> Cc: Vidya Srinivas
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++---
> drivers/gpu/drm/i915/display/intel_dp.c | 11 ++-
> 2 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d06178cd76c..ef06b7b82be9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1082,13 +1082,8 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder,
> int type, int rate,
> return icl_combo_phy_ddi_translations_hdmi;
> case INTEL_OUTPUT_EDP:
> if (dev_priv->vbt.edp.low_vswing) {
> - if (rate > 54) {
> - *n_entries =
> ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> - return icl_combo_phy_ddi_translations_edp_hbr3;
> - } else {
> - *n_entries =
> ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> - return icl_combo_phy_ddi_translations_edp_hbr2;
> - }
> + *n_entries =
> ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> + return icl_combo_phy_ddi_translations_edp_hbr2;
>
> As pe Bspec, ehl_edp_hbr2 does not match with icl_edp_hbr2 values. Rather I
> see (icl_edp_hbr2 == ehl_edp_hbr) true.
>
> Thanks,
> Tejas
Tejas, please fix your email quoting when interacting on the public
lists. Using Outlook defaults is not acceptable. Please use settings to
prepend "> " to all lines of the email being quoted. Better yet, use a
mail client that gets this right out of the box.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev5)
== Series Details ==
Series: drm/i915: Plumb crtc state to link training code (rev5)
URL : https://patchwork.freedesktop.org/series/76993/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d4651ba92742 drm/i915: s/pre_empemph/preemph/
d2dcd064491e drm/i915: s/old_crtc_state/crtc_state/
f40c6b9eb99a drm/i915: Make intel_dp_process_phy_request() static
582bcff90ebb drm/i915: Shove the PHY test into the hotplug work
5606e8d70bc2 drm/i915: Split ICL combo PHY buf trans per output type
a1ebc02e12c4 drm/i915: Split ICL MG PHY buf trans per output type
f41ab4bb8812 drm/i915: Split EHL combo PHY buf trans per output type
-:63: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#63: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1138:
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 70 lines checked
cf80a68f2857 drm/i915: Split TGL combo PHY buf trans per output type
-:73: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#73: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1177:
+ return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 100 lines checked
2fa06f11cdf9 drm/i915: Split TGL DKL PHY buf trans per output type
680bf95e8d06 drm/i915: Plumb crtc_state to link training
17947177aa4e drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}
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Re: [Intel-gfx] [PATCH v4 3/3] drm/i915/display: Program PSR2 selective fetch registers
On Thu, 2020-09-24 at 10:42 -0700, José Roberto de Souza wrote:
> Another step towards PSR2 selective fetch, here programming plane
> selective fetch registers and MAN_TRK_CTL enabling selective fetch
> but
> for now it is fetching the whole area of the planes.
> The damaged area calculation will come as next and final step.
>
> v2:
> - removed warn on when no plane is visible in state
> - removed calculations using plane damaged area in
> intel_psr2_program_plane_sel_fetch()
>
> v3:
> - do not shift 16 positions the plane dst coordinates, only src is
> shifted
>
> v4:
> - only setting PLANE_SEL_FETCH_CTL_ENABLE and MCURSOR_MODE in
> PLANE_SEL_FETCH_CTL
>
> BSpec: 55229
> Cc: Gwan-gyeong Mun
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 118
> ++-
> drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> 4 files changed, 132 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5a9d933e425a..96bc515497c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> intel_plane *plane,
> if (INTEL_GEN(dev_priv) >= 9)
> skl_write_cursor_wm(plane, crtc_state);
>
> + if (!needs_modeset(crtc_state))
> + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> plane_state, 0);
> +
> if (plane->cursor.base != base ||
> plane->cursor.size != fbc_ctl ||
> plane->cursor.cntl != cntl) {
> @@ -12823,8 +12826,11 @@ static int intel_crtc_atomic_check(struct
> intel_atomic_state *state,
>
> }
>
> - if (!mode_changed)
> - intel_psr2_sel_fetch_update(state, crtc);
> + if (!mode_changed) {
> + ret = intel_psr2_sel_fetch_update(state, crtc);
> + if (ret)
> + return ret;
> + }
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 02f74b0ddec1..f6e0a192d5e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1166,6 +1166,39 @@ static void psr_force_hw_tracking_exit(struct
> drm_i915_private *dev_priv)
> intel_psr_exit(dev_priv);
> }
>
> +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> + const struct intel_crtc_state
> *crtc_state,
> + const struct intel_plane_state
> *plane_state,
> + int color_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> + u32 val;
> +
> + if (!crtc_state->enable_psr2_sel_fetch)
> + return;
> +
> + val = plane_state ? plane_state->ctl : 0;
> + val = plane->id == PLANE_CURSOR ? val & MCURSOR_MODE :
> + val &
> PLANE_SEL_FETCH_CTL_ENABLE;
I could not find details of MCURSOR_MODE for selective_fetch. (on bspec
50420) why do you set MCURSOR_MODE here?
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> >id), val);
> + if (!val || plane->id == PLANE_CURSOR)
> + return;
> +
in order to set just PLANE_SEL_FETCH_CTL_ENABLE bit, I suggest to use
like this
val = intel_de_read_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
>id));
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
val|PLANE_SEL_FETCH_CTL_ENABLE);
> + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> >uapi.dst.x1;
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> >id), val);
> +
> + val = plane_state->color_plane[color_plane].y << 16;
> + val |= plane_state->color_plane[color_plane].x;
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> >id),
> + val);
> +
> + /* Sizes are 0 based */
> + val = ((drm_rect_height(_state->uapi.src) >> 16) - 1) <<
> 16;
> + val |= (drm_rect_width(_state->uapi.src) >> 16) - 1;
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> >id), val);
> +}
> +
> void intel_psr2_program_trans_man_trk_ctl(const struct
> intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -1180,16 +1213,91 @@ void
> intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> *crtc_st
> crtc_state->psr2_man_track_ctl);
> }
>
> -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> *crtc_state,
> +
[Intel-gfx] [PATCH v4 10/11] drm/i915: Plumb crtc_state to link training
From: Ville Syrjälä
Get rid of mode crtc->config usage, and some ad-hoc intel_dp state
usage by plumbing the crtc state all the way down to the link training
code.
Unfortunately we do have to keep some cached state in intel_dp so
that we can do the "does the link need retraining?" checks from
the short hpd handler.
v2: Add intel_crtc_state forward declaration
v3: Don't kill the PHY test code totally since it's
now in the hotplug work where we can get at the states
v4: Don't resurrect the debug scrambling disable bit (Imre)
Use intel_dp_mst_is_master_trans() (Imre)
Reviewed-by: Imre Deak
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 413 +-
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h| 17 +-
drivers/gpu/drm/i915/display/intel_dp.c | 123 --
drivers/gpu/drm/i915/display/intel_dp.h | 10 +-
.../drm/i915/display/intel_dp_link_training.c | 102 +++--
.../drm/i915/display/intel_dp_link_training.h | 8 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 23 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.h | 2 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 7 +-
10 files changed, 386 insertions(+), 325 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7032c367075a..dbf0ffc05c8f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1034,7 +1034,8 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int
*n_entries)
}
static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -1042,7 +1043,8 @@ icl_get_combo_buf_trans_hdmi(struct intel_encoder
*encoder, int type, int rate,
}
static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
@@ -1050,12 +1052,13 @@ icl_get_combo_buf_trans_dp(struct intel_encoder
*encoder, int type, int rate,
}
static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (rate > 54) {
+ if (crtc_state->port_clock > 54) {
*n_entries =
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
return icl_combo_phy_ddi_translations_edp_hbr3;
} else if (dev_priv->vbt.edp.low_vswing) {
@@ -1063,23 +1066,25 @@ icl_get_combo_buf_trans_edp(struct intel_encoder
*encoder, int type, int rate,
return icl_combo_phy_ddi_translations_edp_hbr2;
}
- return icl_get_combo_buf_trans_dp(encoder, type, rate, n_entries);
+ return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
}
static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+icl_get_combo_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- if (type == INTEL_OUTPUT_HDMI)
- return icl_get_combo_buf_trans_hdmi(encoder, type, rate,
n_entries);
- else if (type == INTEL_OUTPUT_EDP)
- return icl_get_combo_buf_trans_edp(encoder, type, rate,
n_entries);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return icl_get_combo_buf_trans_hdmi(encoder, crtc_state,
n_entries);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ return icl_get_combo_buf_trans_edp(encoder, crtc_state,
n_entries);
else
- return icl_get_combo_buf_trans_dp(encoder, type, rate,
n_entries);
+ return icl_get_combo_buf_trans_dp(encoder, crtc_state,
n_entries);
}
static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, int type, int rate,
+icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
int *n_entries)
{
*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
@@ -1087,10 +1092,11 @@ icl_get_mg_buf_trans_hdmi(struct
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skip over MI_NOOP when parsing (rev2)
== Series Details ==
Series: drm/i915: Skip over MI_NOOP when parsing (rev2)
URL : https://patchwork.freedesktop.org/series/82268/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9086 -> Patchwork_18605
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/index.html
Known issues
Here are the changes found in Patchwork_18605 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] /
[i915#95])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
* igt@vgem_basic@unload:
- fi-skl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#2203])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-skl-guc/igt@vgem_ba...@unload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-skl-guc/igt@vgem_ba...@unload.html
Possible fixes
* {igt@core_hotunplug@unbind-rebind}:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-kbl-x1275/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-byt-j1900/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-byt-j1900/igt@i915_module_l...@reload.html
- fi-icl-y: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-icl-y/igt@i915_module_l...@reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-icl-y/igt@i915_module_l...@reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-WARN][15] ([i915#2203]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
Warnings
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#1982] / [i915#62] / [i915#92]
/ [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][20] ([i915#62] / [i915#92]) +1 similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@gem_exec_susp...@basic-s3.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-kbl-x1275/igt@gem_exec_susp...@basic-s3.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][21] ([fdo#109271]) -> [DMESG-FAIL][22]
([i915#62])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18605/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) ->
[DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9086/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
[24]:
[Intel-gfx] linux-next: manual merge of the akpm tree with the drm-intel tree
Hi all,
Today's linux-next merge of the akpm tree got a conflict in:
drivers/gpu/drm/i915/gem/i915_gem_pages.c
between commit:
4caf017ee937 ("drm/i915/gem: Avoid implicit vmap for highmem on x86-32")
ba2ebf605d5f ("drm/i915/gem: Prevent using pgprot_writecombine() if PAT is
not supported")
from the drm-intel tree and patch:
"drm/i915: use vmap in i915_gem_object_map"
from the akpm tree.
I fixed it up (I just dropped the changes in the former commits) and
can carry the fix as necessary. This is now fixed as far as linux-next
is concerned, but any non trivial conflicts should be mentioned to your
upstream maintainer when your tree is submitted for merging. You may
also want to consider cooperating with the maintainer of the conflicting
tree to minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
pgpDq6xXPZ9sK.pgp
Description: OpenPGP digital signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915: Skip over MI_NOOP when parsing
Though less likely in practice, igt uses MI_NOOP frequently to pad out
its batch buffers. The lookup and valiation of so many MI_NOOP command
descriptions is noticeable, though the side-effect of poisoning the
last-validated-command cache is more likely to impact upon real CS.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 67 +-
1 file changed, 33 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index e88970256e8e..93265951fdbb 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1452,43 +1452,42 @@ int intel_engine_cmd_parser(struct intel_engine_cs
*engine,
* space. Parsing should be faster in some cases this way.
*/
batch_end = cmd + batch_length / sizeof(*batch_end);
- do {
- u32 length;
-
- if (*cmd == MI_BATCH_BUFFER_END)
- break;
-
- desc = find_cmd(engine, *cmd, desc, _desc);
- if (!desc) {
- DRM_DEBUG("CMD: Unrecognized command: 0x%08X\n", *cmd);
- ret = -EINVAL;
- break;
- }
+ while (*cmd != MI_BATCH_BUFFER_END) {
+ u32 length = 1;
+
+ if (*cmd != MI_NOOP) { /* MI_NOOP == 0 */
+ desc = find_cmd(engine, *cmd, desc, _desc);
+ if (!desc) {
+ DRM_DEBUG("CMD: Unrecognized command:
0x%08X\n", *cmd);
+ ret = -EINVAL;
+ break;
+ }
- if (desc->flags & CMD_DESC_FIXED)
- length = desc->length.fixed;
- else
- length = (*cmd & desc->length.mask) + LENGTH_BIAS;
+ if (desc->flags & CMD_DESC_FIXED)
+ length = desc->length.fixed;
+ else
+ length = (*cmd & desc->length.mask) +
LENGTH_BIAS;
- if ((batch_end - cmd) < length) {
- DRM_DEBUG("CMD: Command length exceeds batch length:
0x%08X length=%u batchlen=%td\n",
- *cmd,
- length,
- batch_end - cmd);
- ret = -EINVAL;
- break;
- }
+ if ((batch_end - cmd) < length) {
+ DRM_DEBUG("CMD: Command length exceeds batch
length: 0x%08X length=%u batchlen=%td\n",
+ *cmd,
+ length,
+ batch_end - cmd);
+ ret = -EINVAL;
+ break;
+ }
- if (!check_cmd(engine, desc, cmd, length)) {
- ret = -EACCES;
- break;
- }
+ if (!check_cmd(engine, desc, cmd, length)) {
+ ret = -EACCES;
+ break;
+ }
- if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
- ret = check_bbstart(cmd, offset, length, batch_length,
- batch_addr, shadow_addr,
- jump_whitelist);
- break;
+ if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
+ ret = check_bbstart(cmd, offset, length,
batch_length,
+ batch_addr, shadow_addr,
+ jump_whitelist);
+ break;
+ }
}
if (!IS_ERR_OR_NULL(jump_whitelist))
@@ -1501,7 +1500,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs
*engine,
ret = -EINVAL;
break;
}
- } while (1);
+ }
if (trampoline) {
/*
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915: don't conflate is_dgfx with fake lmem
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: don't conflate is_dgfx with
fake lmem
URL : https://patchwork.freedesktop.org/series/82283/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9085_full -> Patchwork_18604_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_18604_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18604_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18604_full:
### IGT changes ###
Possible regressions
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-skl: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-skl4/igt@kms_color_chamel...@pipe-a-ctm-0-75.html
Known issues
Here are the changes found in Patchwork_18604_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_whisper@basic-contexts-priority:
- shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#118] / [i915#95])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-glk8/igt@gem_exec_whis...@basic-contexts-priority.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-glk2/igt@gem_exec_whis...@basic-contexts-priority.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][4] -> [INCOMPLETE][5] ([i915#151])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-skl7/igt@i915_pm_...@system-suspend.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-skl10/igt@i915_pm_...@system-suspend.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
- shard-skl: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) +10
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-skl5/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-skl5/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#180])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-kbl4/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-kbl7/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
* igt@kms_flip_tiling@flip-y-tiled:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#1635] /
[i915#1982])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-apl7/igt@kms_flip_til...@flip-y-tiled.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-apl7/igt@kms_flip_til...@flip-y-tiled.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-tglb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-tglb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][14] -> [FAIL][15] ([fdo#108145] / [i915#265])
+1 similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109441])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][18] -> [FAIL][19] ([i915#1635] / [i915#31])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-apl4/igt@kms_setm...@basic.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-apl8/igt@kms_setm...@basic.html
Possible fixes
* {igt@core_hotunplug@unbind-rebind}:
- shard-skl: [DMESG-WARN][20] ([i915#1982]) -> [PASS][21] +3
similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-skl2/igt@core_hotunp...@unbind-rebind.html
[21]:
Re: [Intel-gfx] [PATCH tip/core/rcu 11/15] drm/i915: Cleanup PREEMPT_COUNT leftovers
On Thu, Oct 01 2020 at 10:17, Joonas Lahtinen wrote: > Quoting paul...@kernel.org (2020-09-29 02:30:58) >> CONFIG_PREEMPT_COUNT is now unconditionally enabled and will be >> removed. Cleanup the leftovers before doing so. > > Change looks fine: > > Reviewed-by: Joonas Lahtinen > > Are you looking for us to merge or merge through another tree? > > If us, did the base patch always enabling PREEMPT_COUNT go into 5.9 or is > it heading to 5.10? We can queue this earliest for 5.11 as drm-next closed > for 5.10 at week of -rc5. If at all it goes through rcu/tip because it depends on the earlier patches. Thanks, tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: don't conflate is_dgfx with fake lmem
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: don't conflate is_dgfx with
fake lmem
URL : https://patchwork.freedesktop.org/series/82283/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9085 -> Patchwork_18604
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/index.html
Known issues
Here are the changes found in Patchwork_18604 that come from known issues:
### IGT changes ###
Issues hit
* igt@vgem_basic@unload:
- fi-skl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#2203])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/fi-skl-guc/igt@vgem_ba...@unload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/fi-skl-guc/igt@vgem_ba...@unload.html
Possible fixes
* igt@i915_module_load@reload:
- fi-apl-guc: [DMESG-WARN][3] ([i915#1635] / [i915#1982]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/fi-apl-guc/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/fi-apl-guc/igt@i915_module_l...@reload.html
- fi-icl-y: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/fi-icl-y/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/fi-icl-y/igt@i915_module_l...@reload.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar
issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/fi-kbl-x1275/igt@vgem_ba...@unload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/fi-kbl-x1275/igt@vgem_ba...@unload.html
Warnings
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) ->
[DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/fi-kbl-x1275/igt@kms_force_connector_ba...@force-edid.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/fi-kbl-x1275/igt@kms_force_connector_ba...@force-edid.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][14] ([i915#62] / [i915#92]) +3 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/fi-kbl-x1275/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/fi-kbl-x1275/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (44 -> 38)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper
Build changes
-
* Linux: CI_DRM_9085 -> Patchwork_18604
CI-20190529: 20190529
CI_DRM_9085: aa4b8d5f7de07ec566086ca7c2bdb5138284d3a3 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5796: 19ae9421a5af7b03a1c9a577c57f2cf8b16a0116 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18604: df6fee7006e59c974479e04644e8dc8102d5ea54 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
df6fee7006e5 drm/i915/dg1: Wait for pcode/uncore handshake at startup
ef65c75e79ef drm/i915: don't conflate is_dgfx with fake lmem
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/index.html
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[Intel-gfx] [PULL] drm-misc-fixes
drm-misc-fixes-2020-10-01: drm-misc-fixes for v5.9: - Small doc fix. - Re-add FB_ARMCLCD for android. - Fix global-out-of-bounds read in fbcon_get_font(). The following changes since commit 19a508bd1ad8e444de86873bf2f2b2ab8edd6552: dmabuf: fix NULL pointer dereference in dma_buf_release() (2020-09-21 11:17:06 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2020-10-01 for you to fetch changes up to 27204b99b08289d0993cb77c22470034b5eb974d: drm: drm_dsc.h: fix a kernel-doc markup (2020-09-30 16:40:44 +0200) drm-misc-fixes for v5.9: - Small doc fix. - Re-add FB_ARMCLCD for android. - Fix global-out-of-bounds read in fbcon_get_font(). Mauro Carvalho Chehab (1): drm: drm_dsc.h: fix a kernel-doc markup Peilin Ye (3): fbdev, newport_con: Move FONT_EXTRA_WORDS macros into linux/font.h Fonts: Support FONT_EXTRA_WORDS macros for built-in fonts fbcon: Fix global-out-of-bounds read in fbcon_get_font() Peter Collingbourne (1): Partially revert "video: fbdev: amba-clcd: Retire elder CLCD driver" MAINTAINERS | 5 + drivers/video/console/newport_con.c | 7 +- drivers/video/fbdev/Kconfig | 20 + drivers/video/fbdev/Makefile| 1 + drivers/video/fbdev/amba-clcd.c | 986 drivers/video/fbdev/core/fbcon.c| 12 + drivers/video/fbdev/core/fbcon.h| 7 - drivers/video/fbdev/core/fbcon_rotate.c | 1 + drivers/video/fbdev/core/tileblit.c | 1 + include/drm/drm_dsc.h | 2 +- include/linux/amba/clcd-regs.h | 87 +++ include/linux/amba/clcd.h | 290 ++ include/linux/font.h| 13 + lib/fonts/font_10x18.c | 9 +- lib/fonts/font_6x10.c | 9 +- lib/fonts/font_6x11.c | 9 +- lib/fonts/font_7x14.c | 9 +- lib/fonts/font_8x16.c | 9 +- lib/fonts/font_8x8.c| 9 +- lib/fonts/font_acorn_8x8.c | 9 +- lib/fonts/font_mini_4x6.c | 8 +- lib/fonts/font_pearl_8x8.c | 9 +- lib/fonts/font_sun12x22.c | 9 +- lib/fonts/font_sun8x16.c| 7 +- lib/fonts/font_ter16x32.c | 9 +- 25 files changed, 1469 insertions(+), 68 deletions(-) create mode 100644 drivers/video/fbdev/amba-clcd.c create mode 100644 include/linux/amba/clcd-regs.h create mode 100644 include/linux/amba/clcd.h ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH tip/core/rcu 11/15] drm/i915: Cleanup PREEMPT_COUNT leftovers
Quoting paul...@kernel.org (2020-09-29 02:30:58)
> From: Thomas Gleixner
>
> CONFIG_PREEMPT_COUNT is now unconditionally enabled and will be
> removed. Cleanup the leftovers before doing so.
Change looks fine:
Reviewed-by: Joonas Lahtinen
Are you looking for us to merge or merge through another tree?
If us, did the base patch always enabling PREEMPT_COUNT go into 5.9 or is
it heading to 5.10? We can queue this earliest for 5.11 as drm-next closed
for 5.10 at week of -rc5.
Regards, Joonas
> Signed-off-by: Thomas Gleixner
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Paul E. McKenney
> ---
> drivers/gpu/drm/i915/Kconfig.debug | 1 -
> drivers/gpu/drm/i915/i915_utils.h | 3 +--
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/Kconfig.debug
> b/drivers/gpu/drm/i915/Kconfig.debug
> index 1cb28c2..17d9b00 100644
> --- a/drivers/gpu/drm/i915/Kconfig.debug
> +++ b/drivers/gpu/drm/i915/Kconfig.debug
> @@ -20,7 +20,6 @@ config DRM_I915_DEBUG
> bool "Enable additional driver debugging"
> depends on DRM_I915
> select DEBUG_FS
> - select PREEMPT_COUNT
> select I2C_CHARDEV
> select STACKDEPOT
> select DRM_DP_AUX_CHARDEV
> diff --git a/drivers/gpu/drm/i915/i915_utils.h
> b/drivers/gpu/drm/i915/i915_utils.h
> index 5477337..ecfed86 100644
> --- a/drivers/gpu/drm/i915/i915_utils.h
> +++ b/drivers/gpu/drm/i915/i915_utils.h
> @@ -337,8 +337,7 @@ wait_remaining_ms_from_jiffies(unsigned long
> timestamp_jiffies, int to_wait_ms)
>(Wmax))
> #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10,
> 1000)
>
> -/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
> -#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
> +#ifdef CONFIG_DRM_I915_DEBUG
> # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) &&
> !in_atomic())
> #else
> # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
> --
> 2.9.5
>
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[Intel-gfx] [CI 1/2] drm/i915: don't conflate is_dgfx with fake lmem
When using fake lmem for tests, we are overriding the setting in
device info for dgfx devices. Current users of IS_DGFX() except one are
correct. However, as we add support for DG1, we are going to use it in
additional places to trigger dgfx-only code path.
In future if we need we can use HAS_LMEM() instead of IS_DGFX() in the
places that make sense to also contemplate fake lmem use.
v2: update gen8_gmch_probe() to use HAS_LMEM(): we need to steal the
mappable aperture later(which is fine since it doesn't exist on "DGFX"),
and use it as a substitute for LMEMBAR. The !mappable aperture property
is also useful since it exercises some other parts of the code too.
(Matthew Auld)
Signed-off-by: Lucas De Marchi
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 81c05f551b9c..188a5f70177d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -835,7 +835,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
u16 snb_gmch_ctl;
/* TODO: We're not aware of mappable constraints on gen8 yet */
- if (!IS_DGFX(i915)) {
+ if (!HAS_LMEM(i915)) {
ggtt->gmadr = pci_resource(pdev, 2);
ggtt->mappable_end = resource_size(>gmadr);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 45e719c79183..3f6ed142198c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -840,9 +840,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
i915->params.fake_lmem_start) {
mkwrite_device_info(i915)->memory_regions =
REGION_SMEM | REGION_LMEM | REGION_STOLEN;
- mkwrite_device_info(i915)->is_dgfx = true;
GEM_BUG_ON(!HAS_LMEM(i915));
- GEM_BUG_ON(!IS_DGFX(i915));
}
}
#endif
--
2.28.0
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[Intel-gfx] [CI 2/2] drm/i915/dg1: Wait for pcode/uncore handshake at startup
From: Matt Roper
DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this handshaking is complete.
The bspec doesn't give guidance on how long we may need to wait for this
handshaking to complete. For now, let's just set a really long timeout;
if we still don't get a completion status by the end of that timeout,
we'll just continue on and hope for the best.
v2 (Lucas): Rename macros to make clear the relation between command and
result (requested by José)
Bspec: 52065
Cc: Clinton Taylor
Cc: Ville Syrjälä
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_sideband.c | 15 +++
drivers/gpu/drm/i915/intel_sideband.h | 2 ++
4 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3f6ed142198c..ebc15066d108 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -84,6 +84,7 @@
#include "intel_gvt.h"
#include "intel_memory_region.h"
#include "intel_pm.h"
+#include "intel_sideband.h"
#include "vlv_suspend.h"
static struct drm_driver driver;
@@ -616,6 +617,8 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
*/
intel_dram_detect(dev_priv);
+ intel_pcode_init(dev_priv);
+
intel_bw_init_hw(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47730a176698..8582dbe6ef69 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9224,6 +9224,9 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define DG1_PCODE_STATUS 0x7E
+#define DG1_UNCORE_GET_INIT_STATUS 0x0
+#define DG1_UNCORE_INIT_STATUS_COMPLETE0x1
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
#define GEN6_PCODE_DATA_MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 5b3279262123..02ebf5a04a9b 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -555,3 +555,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32
mbox, u32 request,
return ret ? ret : status;
#undef COND
}
+
+void intel_pcode_init(struct drm_i915_private *i915)
+{
+ int ret;
+
+ if (!IS_DGFX(i915))
+ return;
+
+ ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
+ DG1_UNCORE_GET_INIT_STATUS,
+ DG1_UNCORE_INIT_STATUS_COMPLETE,
+ DG1_UNCORE_INIT_STATUS_COMPLETE, 50);
+ if (ret)
+ drm_err(>drm, "Pcode did not report uncore initialization
completion!\n");
+}
diff --git a/drivers/gpu/drm/i915/intel_sideband.h
b/drivers/gpu/drm/i915/intel_sideband.h
index 7fb95745a444..094c7b19c5d4 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private
*i915, u32 mbox,
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
+void intel_pcode_init(struct drm_i915_private *i915);
+
#endif /* _INTEL_SIDEBAND_H */
--
2.28.0
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