Re: [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support
On Thu, Oct 22, 2020 at 04:26:15PM -0700, Aditya Swarup wrote:
On 10/21/20 10:28 AM, Lucas De Marchi wrote:
On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
From: Anusha Srivatsa
ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
ADLS DDI and HPD masks for setting up hpd interrupts.
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/i915_irq.c | 20
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b753c77c9a77..9033221995ad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv)
you still need to assign hpd_pin to do the mapping between port and hpd
pin. Earlier this was done in the irq handler itself, but now is done in
intel_ddi_init(). See what I did for DG1:
https://patchwork.freedesktop.org/patch/396062/?series=82905=1
I don't think that is required as for all Gen12+ platforms, tgl_hpd_pin is used
for assignment
and the logic works for adl-s with PORT A mapping staying the same and for
ports greater than
PORT D, HPD_PORT_TC1 is used as starting offset.
From intel_ddi_init()
else if (INTEL_GEN(dev_priv) >= 12)
encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
right... this is not like rkl/dg1 in which the hpd doesn't match the
port.
Reviewed-by: Lucas De Marchi
Lucas De Marchi
Also, I have tested this code wrt hotplugs on the system and it works for all
ports.
Regards,
Aditya Swarup
Lucas De Marchi
if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
return;
- if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
- HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
+ HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
+ HAS_PCH_MCC(dev_priv))
hpd->pch_hpd = hpd_icp;
else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
hpd->pch_hpd = hpd_spt;
@@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir)
u32 ddi_hotplug_trigger, tc_hotplug_trigger;
u32 pin_mask = 0, long_mask = 0;
- if (HAS_PCH_TGP(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
+ tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
+ } else if (HAS_PCH_TGP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
} else if (HAS_PCH_JSP(dev_priv)) {
@@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private
*dev_priv)
TGP_DDI_HPD_ENABLE_MASK, 0);
}
+static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ icp_hpd_irq_setup(dev_priv,
+ ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
+}
+
static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (I915_HAS_HOTPLUG(dev_priv))
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else {
- if (HAS_PCH_JSP(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
+ else if (HAS_PCH_JSP(dev_priv))
dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
else if (HAS_PCH_MCC(dev_priv))
dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 83ddea1cd174..f6b844ca7a9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8343,6 +8343,7 @@ enum {
SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_ADLS SDE_DDI_HOTPLUG_ICP(PORT_A)
#define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004)
@@ -8438,6 +8439,8 @@ enum {
ICP_TC_HPD_ENABLE(PORT_TC5) | \
ICP_TC_HPD_ENABLE_MASK)
+#define ADLS_DDI_HPD_ENABLE_MASK SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
+
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
--
2.27.0
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Re: [Intel-gfx] [PATCH] drm/i915: Add plane .{min, max}_width() and .max_height() vfuncs
On 10/16/20 4:40 PM, Aditya Swarup wrote:
> On 9/24/20 11:51 AM, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Reduce this maintenance nightmare a bit by converting the plane
>> min/max width/height stuff into vfuncs.
>>
>> Now, if I could just think of a nice way to also use this for
>> intel_mode_valid_max_plane_size()...
>>
>> Signed-off-by: Ville Syrjälä
> LGTM..
> Reviewed-by: Aditya Swarup
Hi Ville
Are you going to push this patch to drm-tip or are you planning to rework this
patch?
This patch simplifies the max/min plane width plane assignment and fixes the
NV12 aux surface bug
and is good enough to push.
Regards,
Aditya Swarup
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 194 +-
>> .../drm/i915/display/intel_display_types.h| 9 +
>> drivers/gpu/drm/i915/display/intel_sprite.c | 140 +
>> 3 files changed, 196 insertions(+), 147 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 5a9d933e425a..a823d406f0ee 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -3696,127 +3696,6 @@ intel_find_initial_plane_obj(struct intel_crtc
>> *intel_crtc,
>>_intel_frontbuffer(fb)->bits);
>> }
>>
>> -static int skl_max_plane_width(const struct drm_framebuffer *fb,
>> - int color_plane,
>> - unsigned int rotation)
>> -{
>> -int cpp = fb->format->cpp[color_plane];
>> -
>> -switch (fb->modifier) {
>> -case DRM_FORMAT_MOD_LINEAR:
>> -case I915_FORMAT_MOD_X_TILED:
>> -/*
>> - * Validated limit is 4k, but has 5k should
>> - * work apart from the following features:
>> - * - Ytile (already limited to 4k)
>> - * - FP16 (already limited to 4k)
>> - * - render compression (already limited to 4k)
>> - * - KVMR sprite and cursor (don't care)
>> - * - horizontal panning (TODO verify this)
>> - * - pipe and plane scaling (TODO verify this)
>> - */
>> -if (cpp == 8)
>> -return 4096;
>> -else
>> -return 5120;
>> -case I915_FORMAT_MOD_Y_TILED_CCS:
>> -case I915_FORMAT_MOD_Yf_TILED_CCS:
>> -case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>> -/* FIXME AUX plane? */
>> -case I915_FORMAT_MOD_Y_TILED:
>> -case I915_FORMAT_MOD_Yf_TILED:
>> -if (cpp == 8)
>> -return 2048;
>> -else
>> -return 4096;
>> -default:
>> -MISSING_CASE(fb->modifier);
>> -return 2048;
>> -}
>> -}
>> -
>> -static int glk_max_plane_width(const struct drm_framebuffer *fb,
>> - int color_plane,
>> - unsigned int rotation)
>> -{
>> -int cpp = fb->format->cpp[color_plane];
>> -
>> -switch (fb->modifier) {
>> -case DRM_FORMAT_MOD_LINEAR:
>> -case I915_FORMAT_MOD_X_TILED:
>> -if (cpp == 8)
>> -return 4096;
>> -else
>> -return 5120;
>> -case I915_FORMAT_MOD_Y_TILED_CCS:
>> -case I915_FORMAT_MOD_Yf_TILED_CCS:
>> -/* FIXME AUX plane? */
>> -case I915_FORMAT_MOD_Y_TILED:
>> -case I915_FORMAT_MOD_Yf_TILED:
>> -if (cpp == 8)
>> -return 2048;
>> -else
>> -return 5120;
>> -default:
>> -MISSING_CASE(fb->modifier);
>> -return 2048;
>> -}
>> -}
>> -
>> -static int icl_min_plane_width(const struct drm_framebuffer *fb)
>> -{
>> -/* Wa_14011264657, Wa_14011050563: gen11+ */
>> -switch (fb->format->format) {
>> -case DRM_FORMAT_C8:
>> -return 18;
>> -case DRM_FORMAT_RGB565:
>> -return 10;
>> -case DRM_FORMAT_XRGB:
>> -case DRM_FORMAT_XBGR:
>> -case DRM_FORMAT_ARGB:
>> -case DRM_FORMAT_ABGR:
>> -case DRM_FORMAT_XRGB2101010:
>> -case DRM_FORMAT_XBGR2101010:
>> -case DRM_FORMAT_ARGB2101010:
>> -case DRM_FORMAT_ABGR2101010:
>> -case DRM_FORMAT_XVYU2101010:
>> -case DRM_FORMAT_Y212:
>> -case DRM_FORMAT_Y216:
>> -return 6;
>> -case DRM_FORMAT_NV12:
>> -return 20;
>> -case DRM_FORMAT_P010:
>> -case DRM_FORMAT_P012:
>> -case DRM_FORMAT_P016:
>> -return 12;
>> -case DRM_FORMAT_XRGB16161616F:
>> -case DRM_FORMAT_XBGR16161616F:
>> -case DRM_FORMAT_ARGB16161616F:
>> -case DRM_FORMAT_ABGR16161616F:
>> -case DRM_FORMAT_XVYU12_16161616:
>> -case DRM_FORMAT_XVYU16161616:
>> -return 4;
>> -default:
>> -return 1;
>> -}
>> -}
>> -
>> -static int icl_max_plane_width(const struct drm_framebuffer *fb,
>> - int color_plane,
>> -
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Skip RPS tests on Ironlake (only IPS)
== Series Details == Series: drm/i915/selftests: Skip RPS tests on Ironlake (only IPS) URL : https://patchwork.freedesktop.org/series/82965/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9186_full -> Patchwork_18768_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18768_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18768_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18768_full: ### IGT changes ### Possible regressions * igt@prime_vgem@coherency-blt: - shard-snb: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-snb2/igt@prime_v...@coherency-blt.html Warnings * igt@core_hotunplug@hotrebind-lateclose: - shard-hsw: [WARN][2] ([i915#2283]) -> [FAIL][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-hsw6/igt@core_hotunp...@hotrebind-lateclose.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-hsw2/igt@core_hotunp...@hotrebind-lateclose.html * igt@gem_exec_whisper@basic-queues-priority-all: - shard-glk: [INCOMPLETE][4] -> [FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-glk4/igt@gem_exec_whis...@basic-queues-priority-all.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-glk3/igt@gem_exec_whis...@basic-queues-priority-all.html Known issues Here are the changes found in Patchwork_18768_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([i915#180]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-kbl6/igt@gem_ctx_isolation@preservation...@bcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-kbl4/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-snb: [PASS][8] -> [FAIL][9] ([i915#2389]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-snb7/igt@gem_exec_reloc@basic-many-act...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-snb5/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_reloc@basic-many-active@vecs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2389]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-glk5/igt@gem_exec_reloc@basic-many-act...@vecs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-glk1/igt@gem_exec_reloc@basic-many-act...@vecs0.html * igt@gem_exec_whisper@basic-forked-all: - shard-glk: [PASS][12] -> [DMESG-WARN][13] ([i915#118] / [i915#95]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-glk1/igt@gem_exec_whis...@basic-forked-all.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-glk3/igt@gem_exec_whis...@basic-forked-all.html * igt@i915_pm_dc@dc6-psr: - shard-skl: [PASS][14] -> [FAIL][15] ([i915#454]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-skl7/igt@i915_pm...@dc6-psr.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-skl4/igt@i915_pm...@dc6-psr.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [PASS][16] -> [INCOMPLETE][17] ([i915#155]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-kbl7/igt@i915_susp...@debugfs-reader.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-kbl4/igt@i915_susp...@debugfs-reader.html * igt@kms_big_fb@y-tiled-8bpp-rotate-180: - shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-kbl7/igt@kms_big...@y-tiled-8bpp-rotate-180.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-kbl4/igt@kms_big...@y-tiled-8bpp-rotate-180.html - shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#1635] / [i915#1982]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-apl8/igt@kms_big...@y-tiled-8bpp-rotate-180.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/shard-apl4/igt@kms_big...@y-tiled-8bpp-rotate-180.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: - shard-skl: [PASS][22] -> [DMESG-WARN][23] ([i915#1982]) +7 similar issues [22]:
Re: [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn
On Fri, Oct 23, 2020 at 02:56:21AM +0300, Ville Syrjälä wrote:
On Thu, Oct 08, 2020 at 01:52:30AM -0700, Lucas De Marchi wrote:
On Thu, Oct 08, 2020 at 11:40:28AM +0300, Ville Syrjälä wrote:
>On Wed, Oct 07, 2020 at 03:51:11PM -0700, Lucas De Marchi wrote:
>> On Tue, Oct 06, 2020 at 05:33:34PM +0300, Ville Syrjälä wrote:
>> >From: Ville Syrjälä
>> >
>> >Just like with the DDIs tgl+ renamed the AUX CHs to reflect
>> >the type of the DDI. Let's add the aliasing enum values for
>> >the type-C AUX CHs.
>> >
>> >Signed-off-by: Ville Syrjälä
>> >---
>> > drivers/gpu/drm/i915/display/intel_display.h | 8 +++
>> > drivers/gpu/drm/i915/display/intel_dp.c | 53 ++--
>> > 2 files changed, 58 insertions(+), 3 deletions(-)
>> >
>> >diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
>> >index a39be3c9e0cf..cba876721ea0 100644
>> >--- a/drivers/gpu/drm/i915/display/intel_display.h
>> >+++ b/drivers/gpu/drm/i915/display/intel_display.h
>> >@@ -290,6 +290,14 @@ enum aux_ch {
>> > AUX_CH_G,
>> > AUX_CH_H,
>> > AUX_CH_I,
>> >+
>> >+ /* tgl+ */
>> >+ AUX_CH_USBC1 = AUX_CH_D,
>> >+ AUX_CH_USBC2,
>> >+ AUX_CH_USBC3,
>> >+ AUX_CH_USBC4,
>> >+ AUX_CH_USBC5,
>> >+ AUX_CH_USBC6,
>> > };
>> >
>> > #define aux_ch_name(a) ((a) + 'A')
>> >diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
>> >index 239016dcd544..a73c354c920e 100644
>> >--- a/drivers/gpu/drm/i915/display/intel_dp.c
>> >+++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> >@@ -1792,7 +1792,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp
*intel_dp)
>> > case AUX_CH_D:
>> > case AUX_CH_E:
>> > case AUX_CH_F:
>> >- case AUX_CH_G:
>> > return DP_AUX_CH_CTL(aux_ch);
>> > default:
>> > MISSING_CASE(aux_ch);
>> >@@ -1813,7 +1812,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp
*intel_dp, int index)
>> > case AUX_CH_D:
>> > case AUX_CH_E:
>> > case AUX_CH_F:
>> >- case AUX_CH_G:
>> >+ return DP_AUX_CH_DATA(aux_ch, index);
>> >+ default:
>> >+ MISSING_CASE(aux_ch);
>> >+ return DP_AUX_CH_DATA(AUX_CH_A, index);
>> >+ }
>> >+}
>> >+
>> >+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
>> >+{
>> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >+ enum aux_ch aux_ch = dig_port->aux_ch;
>> >+
>> >+ switch (aux_ch) {
>> >+ case AUX_CH_A:
>> >+ case AUX_CH_B:
>> >+ case AUX_CH_C:
>> >+ case AUX_CH_USBC1:
>> >+ case AUX_CH_USBC2:
>> >+ case AUX_CH_USBC3:
>> >+ case AUX_CH_USBC4:
>> >+ case AUX_CH_USBC5:
>> >+ case AUX_CH_USBC6:
>> >+ return DP_AUX_CH_CTL(aux_ch);
>> >+ default:
>> >+ MISSING_CASE(aux_ch);
>> >+ return DP_AUX_CH_CTL(AUX_CH_A);
>> >+ }
>> >+}
>> >+
>> >+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
>> >+{
>> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> >+ enum aux_ch aux_ch = dig_port->aux_ch;
>> >+
>> >+ switch (aux_ch) {
>> >+ case AUX_CH_A:
>> >+ case AUX_CH_B:
>> >+ case AUX_CH_C:
>> >+ case AUX_CH_USBC1:
>> >+ case AUX_CH_USBC2:
>> >+ case AUX_CH_USBC3:
>> >+ case AUX_CH_USBC4:
>> >+ case AUX_CH_USBC5:
>> >+ case AUX_CH_USBC6:
>> > return DP_AUX_CH_DATA(aux_ch, index);
>> > default:
>> > MISSING_CASE(aux_ch);
>> >@@ -1834,7 +1878,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
>> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> > struct intel_encoder *encoder = _port->base;
>> >
>> >- if (INTEL_GEN(dev_priv) >= 9) {
>> >+ if (INTEL_GEN(dev_priv) >= 12) {
>> >+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
>>
>> why is this even a function pointer rather than just the reg? AFAICS it
>> only depends on dig_port->aux_ch that is initialized in intel_ddi_init()
>
>Just for consistency with .aux_ch_data_reg() I guess. Can't remember
>a more specific reason at least.
even that may be overkill since all the users just use index to
do `+ index * 4`
The code used to do that but we got rid of it when the i915_reg
stuff was introduced to discourage people from doing hand rolled
arithmetic on register offsets. I think the tradeoff has been
generally worth it because I can't remeber the last time someone
messed up the register offsets. Before type safety it was a
somewhat regular occurance.
ok. Just so patchwork gets it now:
Reviewed-by: Lucas De Marchi
Lucas De Marchi
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 3/6] drm/i915/dg1: map/unmap pll clocks
On Thu, Oct 22, 2020 at 04:22:01PM -0700, Matt Roper wrote: On Wed, Oct 21, 2020 at 01:20:31AM -0700, Lucas De Marchi wrote: +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \ + val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2))) This sure is ugly. But it looks correct. Admittedly this deserves a comment on top /* don't touch, it's correct */ Although the code might wind up being slightly longer, I wonder if it would help clarify if we wrote a few at least the last part of this expression with ternary operators and symbolic names. E.g., "... + (phy >= PHY_C ? DPLL_ID_DG1_DPLL2 : DPLL_ID_DG1_DPLL0)" I will think about Up to you; the patch looks fine either way. Reviewed-by: Matt Roper thanks Lucas De Marchi + /* CNL PLL */ #define DPLL0_ENABLE 0x46010 #define DPLL1_ENABLE 0x46014 -- 2.28.0 -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/20] drm/i915: Introduce AUX_CH_USBCn
On Thu, Oct 08, 2020 at 01:52:30AM -0700, Lucas De Marchi wrote:
> On Thu, Oct 08, 2020 at 11:40:28AM +0300, Ville Syrjälä wrote:
> >On Wed, Oct 07, 2020 at 03:51:11PM -0700, Lucas De Marchi wrote:
> >> On Tue, Oct 06, 2020 at 05:33:34PM +0300, Ville Syrjälä wrote:
> >> >From: Ville Syrjälä
> >> >
> >> >Just like with the DDIs tgl+ renamed the AUX CHs to reflect
> >> >the type of the DDI. Let's add the aliasing enum values for
> >> >the type-C AUX CHs.
> >> >
> >> >Signed-off-by: Ville Syrjälä
> >> >---
> >> > drivers/gpu/drm/i915/display/intel_display.h | 8 +++
> >> > drivers/gpu/drm/i915/display/intel_dp.c | 53 ++--
> >> > 2 files changed, 58 insertions(+), 3 deletions(-)
> >> >
> >> >diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> >> >b/drivers/gpu/drm/i915/display/intel_display.h
> >> >index a39be3c9e0cf..cba876721ea0 100644
> >> >--- a/drivers/gpu/drm/i915/display/intel_display.h
> >> >+++ b/drivers/gpu/drm/i915/display/intel_display.h
> >> >@@ -290,6 +290,14 @@ enum aux_ch {
> >> > AUX_CH_G,
> >> > AUX_CH_H,
> >> > AUX_CH_I,
> >> >+
> >> >+ /* tgl+ */
> >> >+ AUX_CH_USBC1 = AUX_CH_D,
> >> >+ AUX_CH_USBC2,
> >> >+ AUX_CH_USBC3,
> >> >+ AUX_CH_USBC4,
> >> >+ AUX_CH_USBC5,
> >> >+ AUX_CH_USBC6,
> >> > };
> >> >
> >> > #define aux_ch_name(a) ((a) + 'A')
> >> >diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> >b/drivers/gpu/drm/i915/display/intel_dp.c
> >> >index 239016dcd544..a73c354c920e 100644
> >> >--- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> >+++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> >@@ -1792,7 +1792,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp
> >> >*intel_dp)
> >> > case AUX_CH_D:
> >> > case AUX_CH_E:
> >> > case AUX_CH_F:
> >> >- case AUX_CH_G:
> >> > return DP_AUX_CH_CTL(aux_ch);
> >> > default:
> >> > MISSING_CASE(aux_ch);
> >> >@@ -1813,7 +1812,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp
> >> >*intel_dp, int index)
> >> > case AUX_CH_D:
> >> > case AUX_CH_E:
> >> > case AUX_CH_F:
> >> >- case AUX_CH_G:
> >> >+ return DP_AUX_CH_DATA(aux_ch, index);
> >> >+ default:
> >> >+ MISSING_CASE(aux_ch);
> >> >+ return DP_AUX_CH_DATA(AUX_CH_A, index);
> >> >+ }
> >> >+}
> >> >+
> >> >+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
> >> >+{
> >> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> >+ enum aux_ch aux_ch = dig_port->aux_ch;
> >> >+
> >> >+ switch (aux_ch) {
> >> >+ case AUX_CH_A:
> >> >+ case AUX_CH_B:
> >> >+ case AUX_CH_C:
> >> >+ case AUX_CH_USBC1:
> >> >+ case AUX_CH_USBC2:
> >> >+ case AUX_CH_USBC3:
> >> >+ case AUX_CH_USBC4:
> >> >+ case AUX_CH_USBC5:
> >> >+ case AUX_CH_USBC6:
> >> >+ return DP_AUX_CH_CTL(aux_ch);
> >> >+ default:
> >> >+ MISSING_CASE(aux_ch);
> >> >+ return DP_AUX_CH_CTL(AUX_CH_A);
> >> >+ }
> >> >+}
> >> >+
> >> >+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
> >> >+{
> >> >+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >> >+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> >+ enum aux_ch aux_ch = dig_port->aux_ch;
> >> >+
> >> >+ switch (aux_ch) {
> >> >+ case AUX_CH_A:
> >> >+ case AUX_CH_B:
> >> >+ case AUX_CH_C:
> >> >+ case AUX_CH_USBC1:
> >> >+ case AUX_CH_USBC2:
> >> >+ case AUX_CH_USBC3:
> >> >+ case AUX_CH_USBC4:
> >> >+ case AUX_CH_USBC5:
> >> >+ case AUX_CH_USBC6:
> >> > return DP_AUX_CH_DATA(aux_ch, index);
> >> > default:
> >> > MISSING_CASE(aux_ch);
> >> >@@ -1834,7 +1878,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
> >> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >> > struct intel_encoder *encoder = _port->base;
> >> >
> >> >- if (INTEL_GEN(dev_priv) >= 9) {
> >> >+ if (INTEL_GEN(dev_priv) >= 12) {
> >> >+ intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
> >>
> >> why is this even a function pointer rather than just the reg? AFAICS it
> >> only depends on dig_port->aux_ch that is initialized in intel_ddi_init()
> >
> >Just for consistency with .aux_ch_data_reg() I guess. Can't remember
> >a more specific reason at least.
>
> even that may be overkill since all the users just use index to
> do `+ index * 4`
The code used to do that but we got rid of it when the i915_reg
stuff was introduced to discourage people from doing hand rolled
arithmetic on register offsets. I think the tradeoff has been
generally worth it because I can't remeber the last time someone
messed up the register offsets. Before type safety it was a
somewhat regular occurance.
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 6/6] drm/i915/dg1: Implement WA_16011163337
On Wed, Oct 21, 2020 at 01:20:34AM -0700, Lucas De Marchi wrote: > From: Swathi Dhanavanthri > > Set GS Timer to 224. > Bspec: 53508 > > Cc: Matt Roper > Signed-off-by: Swathi Dhanavanthri > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 8d24ea769fe6..cd0c5847e2df 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -684,6 +684,11 @@ static void dg1_ctx_workarounds_init(struct > intel_engine_cs *engine, > /* Wa_22010493298 */ > WA_SET_BIT_MASKED(HIZ_CHICKEN, > DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); > + > + /* Wa_16011163337 */ > + wa_add(wal, > +FF_MODE2, > +FF_MODE2_GS_TIMER_MASK, FF_MODE2_GS_TIMER_224, 0); It looks like with the latest bspec updates we can just move this into gen12_ctx_workarounds_init() (and remove the copy in the tgl_ function); it now applies to all platforms that will be using that function. Matt > } > > static void > -- > 2.28.0 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/6] drm/i915/dg1: make Wa_22010271021 permanent
On Wed, Oct 21, 2020 at 01:20:33AM -0700, Lucas De Marchi wrote:
> Just like for rkl and tgl, this should be permanent as well for dg1
> instead just for A0. The commit making it permanent for those platforms
> ended up "racing" with the commit adding the DG1 WAs, so now fix that up.
>
> Cc: Swathi Dhanavanthri
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index fed9503a7c4e..8d24ea769fe6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1768,6 +1768,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
>*/
> wa_write_or(wal, GEN7_FF_THREAD_MODE,
> GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
> +
> + /*
> + * Wa_1606700617
Not sure if you meant to drop the ":tgl" suffix here when you moved it?
This alternate number also shows up in the DG1 database now (but not
RKL) so we could make this "tgl,dg1" to match the spec.
Either way,
Reviewed-by: Matt Roper
> + * Wa_22010271021:tgl,rkl,dg1
> + */
> + wa_masked_en(wal,
> + GEN9_CS_DEBUG_MODE1,
> + FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> @@ -1796,14 +1804,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
>GEN6_RC_SLEEP_PSMI_CONTROL,
>GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
>GEN8_RC_SEMA_IDLE_MSG_DISABLE);
> -
> - /*
> - * Wa_1606700617:tgl
> - * Wa_22010271021:tgl,rkl
> - */
> - wa_masked_en(wal,
> - GEN9_CS_DEBUG_MODE1,
> - FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> if (IS_GEN(i915, 12)) {
> --
> 2.28.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 04/18] drm/i915/adl_s: Add Interrupt Support
On 10/21/20 10:28 AM, Lucas De Marchi wrote:
> On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
>> From: Anusha Srivatsa
>>
>> ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
>> ADLS DDI and HPD masks for setting up hpd interrupts.
>>
>> Cc: Lucas De Marchi
>> Cc: Jani Nikula
>> Cc: Ville Syrjälä
>> Cc: Imre Deak
>> Cc: Matt Roper
>> Cc: José Roberto de Souza
>> Signed-off-by: Anusha Srivatsa
>> Signed-off-by: Aditya Swarup
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 20
>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> 2 files changed, 19 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c
>> b/drivers/gpu/drm/i915/i915_irq.c
>> index b753c77c9a77..9033221995ad 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private
>> *dev_priv)
>
> you still need to assign hpd_pin to do the mapping between port and hpd
> pin. Earlier this was done in the irq handler itself, but now is done in
> intel_ddi_init(). See what I did for DG1:
> https://patchwork.freedesktop.org/patch/396062/?series=82905=1
I don't think that is required as for all Gen12+ platforms, tgl_hpd_pin is used
for assignment
and the logic works for adl-s with PORT A mapping staying the same and for
ports greater than
PORT D, HPD_PORT_TC1 is used as starting offset.
From intel_ddi_init()
else if (INTEL_GEN(dev_priv) >= 12)
encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
Also, I have tested this code wrt hotplugs on the system and it works for all
ports.
Regards,
Aditya Swarup
>
> Lucas De Marchi
>
>> if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
>> return;
>>
>> - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
>> - HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>> + if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
>> + HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
>> + HAS_PCH_MCC(dev_priv))
>> hpd->pch_hpd = hpd_icp;
>> else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
>> hpd->pch_hpd = hpd_spt;
>> @@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private
>> *dev_priv, u32 pch_iir)
>> u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>> u32 pin_mask = 0, long_mask = 0;
>>
>> - if (HAS_PCH_TGP(dev_priv)) {
>> + if (IS_ALDERLAKE_S(dev_priv)) {
>> + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
>> + tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>> + } else if (HAS_PCH_TGP(dev_priv)) {
>> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>> } else if (HAS_PCH_JSP(dev_priv)) {
>> @@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private
>> *dev_priv)
>> TGP_DDI_HPD_ENABLE_MASK, 0);
>> }
>>
>> +static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
>> +{
>> + icp_hpd_irq_setup(dev_priv,
>> + ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
>> +}
>> +
>> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
>> {
>> u32 hotplug;
>> @@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>> if (I915_HAS_HOTPLUG(dev_priv))
>> dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>> } else {
>> - if (HAS_PCH_JSP(dev_priv))
>> + if (IS_ALDERLAKE_S(dev_priv))
>> + dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
>> + else if (HAS_PCH_JSP(dev_priv))
>> dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
>> else if (HAS_PCH_MCC(dev_priv))
>> dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 83ddea1cd174..f6b844ca7a9f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8343,6 +8343,7 @@ enum {
>> SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>> SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>> SDE_TC_HOTPLUG_ICP(PORT_TC1))
>> +#define SDE_DDI_MASK_ADLS SDE_DDI_HOTPLUG_ICP(PORT_A)
>>
>> #define SDEISR _MMIO(0xc4000)
>> #define SDEIMR _MMIO(0xc4004)
>> @@ -8438,6 +8439,8 @@ enum {
>> ICP_TC_HPD_ENABLE(PORT_TC5) | \
>> ICP_TC_HPD_ENABLE_MASK)
>>
>> +#define ADLS_DDI_HPD_ENABLE_MASK SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
>> +
>> #define _PCH_DPLL_A 0xc6014
>> #define _PCH_DPLL_B 0xc6018
>> #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
>> --
>> 2.27.0
>>
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Re: [Intel-gfx] [PATCH 3/6] drm/i915/dg1: map/unmap pll clocks
On Wed, Oct 21, 2020 at 01:20:31AM -0700, Lucas De Marchi wrote:
> DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
> DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
> single macro that chooses the correct register according to the phy
> being accessed, use the correct bitfields for each pll/phy and implement
> separate functions for DG1 since it doesn't share much with ICL/TGL
> anymore.
>
> The previous values were correct for PHY A and B since they were using
> the same register as before and the bitfields were matching.
>
> Cc: José Roberto de Souza
> Cc: Clinton Taylor
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 92 +++-
> drivers/gpu/drm/i915/display/intel_display.c | 25 +-
> drivers/gpu/drm/i915/i915_reg.h | 15
> 3 files changed, 128 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3a99f209f1e6..feb9512fb204 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2970,6 +2970,38 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> +static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> + u32 val;
> +
> + /*
> + * If we fail this, something went very wrong: first 2 PLLs should be
> + * used by first 2 phys and last 2 PLLs by last phys
> + */
> + if (WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
> + (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
> + return;
> +
> + mutex_lock(_priv->dpll.lock);
Not specifically related to this patch, but since we're adding more uses
of it --- is dpll.lock actually necessary on any modern platform? My
understanding is that it was added to prevent racing rmw operations if
we had parallel modesets on different CRTCs. But I think any modeset on
a gen9+ platform needs to update other global state (the DDB) and would
have already grabbed all CRTC locks to prevent racing commits. Am I
missing something?
> +
> + val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
> + WARN_ON((val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
> +
> + val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
> + intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
> +
> + val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
> +
> + mutex_unlock(_priv->dpll.lock);
> +}
> +
> static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -3017,6 +3049,19 @@ static void icl_map_plls_to_ports(struct intel_encoder
> *encoder,
> mutex_unlock(_priv->dpll.lock);
> }
>
> +static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> +
> + mutex_lock(_priv->dpll.lock);
> +
> + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
> + DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> +
> + mutex_unlock(_priv->dpll.lock);
> +}
> +
> static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -3032,6 +3077,40 @@ static void icl_unmap_plls_to_ports(struct
> intel_encoder *encoder)
> mutex_unlock(_priv->dpll.lock);
> }
>
> +static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
> + u32 port_mask, bool ddi_clk_needed)
> +{
> + enum port port;
> + u32 val;
> +
> + for_each_port_masked(port, port_mask) {
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> + bool ddi_clk_off;
> +
> + val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
> + ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> +
> + if (ddi_clk_needed == !ddi_clk_off)
> + continue;
> +
> + /*
> + * Punt on the case now where clock is gated, but it would
> + * be needed by the port. Something else is really broken then.
> + */
> + if (ddi_clk_needed) {
> + WARN(1, "ddi_clk_needed=%u ddi_clk_off=%u phy=%u\n",
> +
Re: [Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs
On Wed, Oct 07, 2020 at 03:11:56PM -0700, Lucas De Marchi wrote:
On Tue, Oct 06, 2020 at 05:33:30PM +0300, Ville Syrjälä wrote:
From: Ville Syrjälä
Move the DSC stuff out from the middle of the ICP HPD register
definitions. The location seems to have been selected by a
dice roll.
SHPD_FILTER_CNT addition also went astray due to the DSC
mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 215
1 file changed, 107 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ad9ee4243a0..efe51a4ef719 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4618,6 +4618,110 @@ enum {
#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
+/* Icelake DSC Rate Control Range Parameter Registers */
+#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
+#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
+#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
+
_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
+
_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
+
_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
+
_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define RC_BPG_OFFSET_SHIFT10
+#define RC_MAX_QP_SHIFT5
+#define RC_MIN_QP_SHIFT0
+
+#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
+#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
+#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
+
_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
+
_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
+
_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
+
_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
+#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/modes: Switch to 64bit maths to avoid integer overflow
== Series Details == Series: drm/modes: Switch to 64bit maths to avoid integer overflow URL : https://patchwork.freedesktop.org/series/82963/ State : success == Summary == CI Bug Log - changes from CI_DRM_9186_full -> Patchwork_18767_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_18767_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-snb: [PASS][1] -> [FAIL][2] ([i915#2389]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-snb7/igt@gem_exec_reloc@basic-many-act...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-snb7/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_whisper@basic-forked-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-glk1/igt@gem_exec_whis...@basic-forked-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-glk7/igt@gem_exec_whis...@basic-forked-all.html * igt@i915_pm_dc@dc6-psr: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#454]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-skl7/igt@i915_pm...@dc6-psr.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-skl7/igt@i915_pm...@dc6-psr.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([i915#155]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-kbl7/igt@i915_susp...@debugfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-kbl4/igt@i915_susp...@debugfs-reader.html * igt@kms_big_fb@linear-32bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-glk7/igt@kms_big...@linear-32bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-glk5/igt@kms_big...@linear-32bpp-rotate-180.html * igt@kms_big_fb@y-tiled-16bpp-rotate-0: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#1119]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-skl1/igt@kms_big...@y-tiled-16bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-skl9/igt@kms_big...@y-tiled-16bpp-rotate-0.html * igt@kms_big_fb@y-tiled-8bpp-rotate-180: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-kbl7/igt@kms_big...@y-tiled-8bpp-rotate-180.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-kbl4/igt@kms_big...@y-tiled-8bpp-rotate-180.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-skl9/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions-varying-size.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-skl10/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#2346]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-skl7/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html * igt@kms_draw_crc@draw-method-xrgb-render-xtiled: - shard-snb: [PASS][19] -> [FAIL][20] ([i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-snb4/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-snb2/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-skl1/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-skl4/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#2122]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/shard-skl9/igt@kms_flip@plain-flip-ts-check-interrupti...@c-edp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/shard-skl10/igt@kms_flip@plain-flip-ts-check-interrupti...@c-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt: -
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Skip RPS tests on Ironlake (only IPS)
Quoting Ville Syrjälä (2020-10-22 23:38:16) > On Thu, Oct 22, 2020 at 10:08:14PM +0100, Chris Wilson wrote: > > Since Ironlake uses intel_ips.ko for its dynamic frequency adjustment, > > we do not have direct control over the frequency management so such > > tests are defunct. > > We could just ignore what ips is saying, but maybe we don't want to. The idea of the test is to set minimum frequency, run a spinner and check we eventually reach maximum, and then go back to minimum. ips has a really slow response time, iirc it was on the order of 2 minutes, though my memory may be over exaggerating it, but certainly you can watch glxgears tick up over many of its 5s iterations. So that rules it out for BAT selftests as being too slow. In place of the rps cycle counters and threshold checks, we could investigate the registers used by gen5_rps_irq_handle: busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG); busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG); max_avg = intel_uncore_read(uncore, RCBMAXAVG); min_avg = intel_uncore_read(uncore, RCBMINAVG); Basic tests like busy spin, do those registers say to clock up etc. The other test that would be worth seeing if we can do something about is the "frequency response/scaling", i.e. check that the GPU does run faster if we ask for a higher frequency. That would require thinking of a nice way to measure throughput on ilk. Hmm, the blitter should scale with frequency [one would hope!]. But the blitter includes memory bw, so not as pure as the CS measurements we have on gen8+. So with a bit of time, we could have a couple of selftests to confirm that ilk can detect high/low loads, which may come in handy at some point. A task for later. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/6] drm/i915/dg1: add hpd interrupt handling
On Thu, Oct 22, 2020 at 03:36:43PM -0700, Matt Roper wrote:
On Wed, Oct 21, 2020 at 01:20:29AM -0700, Lucas De Marchi wrote:
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
v2: Also change intel_hpd_pin_default() to include DG1 mapping
v3, v4: Rebase on hpd refactor
Cc: Ville Syrjälä
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Cc: Imre Deak
Signed-off-by: Lucas De Marchi
Looks good to me.
Reviewed-by: Matt Roper
I sort of wish we'd named hpd->pch_hpd as hpd->sde_hpd (and hpd->hpd as
hpd->nde_hpd) back when we did that refactor, but it doesn't really
matter too much.
Agreed. I think this would be something good to do once DG1, ADL-S and
the refactors from Ville land.
thanks
Lucas De Marchi
Matt
---
drivers/gpu/drm/i915/display/intel_ddi.c | 13 -
drivers/gpu/drm/i915/i915_irq.c | 37
drivers/gpu/drm/i915/i915_reg.h | 8 +
3 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bb0b9930958f..3a99f209f1e6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5066,6 +5066,15 @@ static bool hti_uses_phy(struct drm_i915_private *i915,
enum phy phy)
i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
}
+static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
+ enum port port)
+{
+ if (port >= PORT_D)
+ return HPD_PORT_C + port - PORT_D;
+ else
+ return HPD_PORT_A + port - PORT_A;
+}
+
static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -5195,7 +5204,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv))
+ encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
+ else if (IS_ROCKETLAKE(dev_priv))
encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
else if (INTEL_GEN(dev_priv) >= 12)
encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b753c77c9a77..b6169fbadb1d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -152,6 +152,13 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
};
+static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
+ [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
+ [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PORT_D),
+};
+
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
struct i915_hotplug *hpd = _priv->hotplug;
@@ -176,11 +183,14 @@ static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv)
else
hpd->hpd = hpd_ilk;
- if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
+ if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
+ (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
return;
- if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
- HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ hpd->pch_hpd = hpd_sde_dg1;
+ else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
+HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
hpd->pch_hpd = hpd_icp;
else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
hpd->pch_hpd = hpd_spt;
@@ -1074,6 +1084,8 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin
pin, u32 val)
return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
case HPD_PORT_C:
return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+ case HPD_PORT_D:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
default:
return false;
}
@@ -1864,7 +1876,10 @@ static void icp_irq_handler(struct drm_i915_private
*dev_priv, u32 pch_iir)
u32 ddi_hotplug_trigger, tc_hotplug_trigger;
u32 pin_mask = 0, long_mask = 0;
- if (HAS_PCH_TGP(dev_priv)) {
+ if (HAS_PCH_DG1(dev_priv)) {
+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
+ tc_hotplug_trigger = 0;
+ } else if (HAS_PCH_TGP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
} else if (HAS_PCH_JSP(dev_priv)) {
@@ -3252,6 +3267,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private
*dev_priv)
TGP_DDI_HPD_ENABLE_MASK, 0);
}
+static void
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Skip RPS tests on Ironlake (only IPS)
On Thu, Oct 22, 2020 at 10:08:14PM +0100, Chris Wilson wrote: > Since Ironlake uses intel_ips.ko for its dynamic frequency adjustment, > we do not have direct control over the frequency management so such > tests are defunct. We could just ignore what ips is saying, but maybe we don't want to. > Similarly, we can't check the gen6+ RPS registers on > Ironlake. I can definitely get behind that one. Reviewed-by: Ville Syrjälä > > Hopefully this catches all the invalid tests now that Ironlake has > rejoined the dynamic GPU frequency club. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gt/selftest_rps.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c > b/drivers/gpu/drm/i915/gt/selftest_rps.c > index 3540ba9bd459..aa5675ecb5cc 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_rps.c > +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c > @@ -219,7 +219,7 @@ int live_rps_clock_interval(void *arg) > struct igt_spinner spin; > int err = 0; > > - if (!intel_rps_is_enabled(rps)) > + if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6) > return 0; > > if (igt_spinner_init(, gt)) > @@ -1028,7 +1028,7 @@ int live_rps_interrupt(void *arg) >* First, let's check whether or not we are receiving interrupts. >*/ > > - if (!intel_rps_has_interrupts(rps)) > + if (!intel_rps_has_interrupts(rps) || INTEL_GEN(gt->i915) < 6) > return 0; > > intel_gt_pm_get(gt); > @@ -1133,7 +1133,7 @@ int live_rps_power(void *arg) >* that theory. >*/ > > - if (!intel_rps_is_enabled(rps)) > + if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6) > return 0; > > if (!librapl_energy_uJ()) > @@ -1237,7 +1237,7 @@ int live_rps_dynamic(void *arg) >* moving parts into dynamic reclocking based on load. >*/ > > - if (!intel_rps_is_enabled(rps)) > + if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6) > return 0; > > if (igt_spinner_init(, gt)) > -- > 2.20.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for VRR/Adaptive Sync enabling in i915
== Series Details == Series: VRR/Adaptive Sync enabling in i915 URL : https://patchwork.freedesktop.org/series/82966/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h HDRTEST drivers/gpu/drm/i915/display/intel_vrr.h In file included from : ./drivers/gpu/drm/i915/display/intel_vrr.h:24:34: error: ‘struct intel_crtc’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] void intel_vrr_get_config(struct intel_crtc *crtc, ^~ cc1: all warnings being treated as errors drivers/gpu/drm/i915/Makefile:305: recipe for target 'drivers/gpu/drm/i915/display/intel_vrr.hdrtest' failed make[4]: *** [drivers/gpu/drm/i915/display/intel_vrr.hdrtest] Error 1 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1784: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/6] drm/i915/dg1: add hpd interrupt handling
On Wed, Oct 21, 2020 at 01:20:29AM -0700, Lucas De Marchi wrote:
> DG1 has one more combo phy port, no TC and all irq handling goes through
> SDE, like for MCC.
>
> v2: Also change intel_hpd_pin_default() to include DG1 mapping
> v3, v4: Rebase on hpd refactor
>
> Cc: Ville Syrjälä
> Cc: Anshuman Gupta
> Cc: José Roberto de Souza
> Cc: Imre Deak
> Signed-off-by: Lucas De Marchi
Looks good to me.
Reviewed-by: Matt Roper
I sort of wish we'd named hpd->pch_hpd as hpd->sde_hpd (and hpd->hpd as
hpd->nde_hpd) back when we did that refactor, but it doesn't really
matter too much.
Matt
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 13 -
> drivers/gpu/drm/i915/i915_irq.c | 37
> drivers/gpu/drm/i915/i915_reg.h | 8 +
> 3 files changed, 51 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bb0b9930958f..3a99f209f1e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5066,6 +5066,15 @@ static bool hti_uses_phy(struct drm_i915_private
> *i915, enum phy phy)
>i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
> }
>
> +static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
> + enum port port)
> +{
> + if (port >= PORT_D)
> + return HPD_PORT_C + port - PORT_D;
> + else
> + return HPD_PORT_A + port - PORT_A;
> +}
> +
> static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
> enum port port)
> {
> @@ -5195,7 +5204,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> encoder->cloneable = 0;
> encoder->pipe_mask = ~0;
>
> - if (IS_ROCKETLAKE(dev_priv))
> + if (IS_DG1(dev_priv))
> + encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
> + else if (IS_ROCKETLAKE(dev_priv))
> encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
> else if (INTEL_GEN(dev_priv) >= 12)
> encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b753c77c9a77..b6169fbadb1d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -152,6 +152,13 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
> [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
> };
>
> +static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
> + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> + [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
> + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PORT_D),
> +};
> +
> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> {
> struct i915_hotplug *hpd = _priv->hotplug;
> @@ -176,11 +183,14 @@ static void intel_hpd_init_pins(struct drm_i915_private
> *dev_priv)
> else
> hpd->hpd = hpd_ilk;
>
> - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
> + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
> + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
> return;
>
> - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
> - HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> + if (HAS_PCH_DG1(dev_priv))
> + hpd->pch_hpd = hpd_sde_dg1;
> + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
> + HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> hpd->pch_hpd = hpd_icp;
> else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
> hpd->pch_hpd = hpd_spt;
> @@ -1074,6 +1084,8 @@ static bool icp_ddi_port_hotplug_long_detect(enum
> hpd_pin pin, u32 val)
> return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
> case HPD_PORT_C:
> return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
> + case HPD_PORT_D:
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
> default:
> return false;
> }
> @@ -1864,7 +1876,10 @@ static void icp_irq_handler(struct drm_i915_private
> *dev_priv, u32 pch_iir)
> u32 ddi_hotplug_trigger, tc_hotplug_trigger;
> u32 pin_mask = 0, long_mask = 0;
>
> - if (HAS_PCH_TGP(dev_priv)) {
> + if (HAS_PCH_DG1(dev_priv)) {
> + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
> + tc_hotplug_trigger = 0;
> + } else if (HAS_PCH_TGP(dev_priv)) {
> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> } else if (HAS_PCH_JSP(dev_priv)) {
> @@ -3252,6 +3267,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private
> *dev_priv)
> TGP_DDI_HPD_ENABLE_MASK, 0);
> }
>
> +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
> +{
> +
[Intel-gfx] [PATCH 09/11] drm/i915/display/vrr: Disable VRR in modeset disable path
This patch disables the VRR enable and VRR PUSH
bits in the HW during commit modeset disable sequence.
Thsi disable will happen when the port is disabled
or when the userspace sets VRR prop to false and
requests to disable VRR.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++
drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
3 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 391c51979334..565155af3fb9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3819,6 +3819,8 @@ static void intel_ddi_post_disable(struct
intel_atomic_state *state,
intel_disable_pipe(old_crtc_state);
+ intel_vrr_disable(old_crtc_state);
+
intel_ddi_disable_transcoder_func(old_crtc_state);
intel_dsc_disable(old_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index ec1ce88e869c..5075ecb9b5a7 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -119,3 +119,25 @@ void intel_vrr_send_push(const struct intel_crtc_state
*crtc_state)
pipe_name(pipe));
}
+void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 trans_vrr_ctl = 0, trans_push = 0;
+
+ if (!old_crtc_state->vrr.enable)
+ return;
+
+ trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(pipe));
+ trans_vrr_ctl &= ~(VRR_CTL_FLIP_LINE_EN | VRR_CTL_VRR_ENABLE);
+ intel_de_write(dev_priv, TRANS_VRR_CTL(pipe), trans_vrr_ctl);
+
+ trans_push = intel_de_read(dev_priv, TRANS_PUSH(pipe));
+ trans_push &= ~TRANS_PUSH_EN;
+ intel_de_write(dev_priv, TRANS_PUSH(pipe), trans_push);
+
+ drm_dbg(_priv->drm, "Disabling VRR on Pipe (%c)\n",
+ pipe_name(pipe));
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
b/drivers/gpu/drm/i915/display/intel_vrr.h
index a6b78e1676cb..8c6fd2d1bee5 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -20,5 +20,6 @@ void intel_vrr_compute_config(struct intel_dp *intel_dp,
void intel_vrr_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
+void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
#endif /* __INTEL_VRR_H__ */
--
2.19.1
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[Intel-gfx] [PATCH 03/11] drm/i915/display/dp: Attach and set drm connector VRR property
From: Aditya Swarup
This function sets the VRR property for connector based
on the platform support, EDID monitor range and DP sink
DPCD capability of outputing video without msa
timing information.
v7:
* Move the helper to separate file (Manasi)
v6:
* Remove unset of prop
v5:
* Fix the vrr prop not being set in kernel (Manasi)
* Unset the prop on connector disconnect (Manasi)
v4:
* Rebase (Mansi)
v3:
* intel_dp_is_vrr_capable can be used for debugfs, make it
non static (Manasi)
v2:
* Just set this in intel_dp_get_modes instead of new hook (Jani)
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Aditya Swarup
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..3794b8f35edc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -62,6 +62,7 @@
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
+#include "intel_vrr.h"
#define DP_DPRX_ESI_LEN 14
@@ -6622,6 +6623,10 @@ static int intel_dp_get_modes(struct drm_connector
*connector)
edid = intel_connector->detect_edid;
if (edid) {
int ret = intel_connector_update_modes(connector, edid);
+
+ if (intel_is_vrr_capable(connector))
+ drm_connector_set_vrr_capable_property(connector,
+ true);
if (ret)
return ret;
}
@@ -7080,6 +7085,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct
drm_connector *connect
connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
}
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ drm_connector_attach_vrr_capable_property(connector);
}
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 3f862b4fd34f..aaf0a41582d7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -15,6 +15,7 @@ enum pipe;
enum port;
struct drm_connector_state;
struct drm_encoder;
+struct drm_connector;
struct drm_i915_private;
struct drm_modeset_acquire_ctx;
struct drm_dp_vsc_sdp;
--
2.19.1
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[Intel-gfx] [PATCH 06/11] drm/i915/display/dp: Do not enable PSR if VRR is enabled
Even though our HW supports PSR + VRR, the available panels do not work reliably with PSR and VRR together. So if user requested VRR and is supported by HW enable that and do not enable PSR in that case. Cc: Ville Syrjälä Cc: Gwan-gyeong Mun Cc: Imre Deak Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_psr.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a591a475f148..56d3fbfad719 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -811,6 +811,13 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, _state->hw.adjusted_mode; int psr_setup_time; + /* +* Current PSR panels dont work reliably with VRR enabled +* So if VRR is enabled, do not enable PSR. +*/ + if (crtc_state->vrr.enable) + return; + if (!CAN_PSR(dev_priv)) return; -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/11] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_ddi.c | 25
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 565155af3fb9..195449dfec1e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3322,6 +3322,22 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder
*encoder,
return DP_TP_STATUS(encoder->port);
}
+static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp
*intel_dp,
+ const struct
intel_crtc_state *crtc_state,
+ bool enable)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ if (!crtc_state->vrr.enable)
+ return;
+
+ if (drm_dp_dpcd_writeb(_dp->aux, DP_DOWNSPREAD_CTRL,
+ enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
+ drm_dbg_kms(>drm,
+ "Failed to set MSA_TIMING_PAR_IGNORE %s in the
sink\n",
+ enable ? "enable" : "disable");
+}
+
static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state)
{
@@ -3493,6 +3509,12 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
*/
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
+ /*
+* Sink device should ignore MSA parameters and regenerate
+* incoming video stream in case of VRR/Adaptive Sync
+*/
+ intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, crtc_state,
true);
+
/*
* 7.i Follow DisplayPort specification training sequence (see notes for
* failure handling)
@@ -4089,6 +4111,9 @@ static void intel_disable_ddi_dp(struct
intel_atomic_state *state,
/* Disable the decompression in DP Sink */
intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
false);
+ /* Disable Ignore_MSA bit in DP Sink */
+ intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
+ false);
}
static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
--
2.19.1
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[Intel-gfx] [PATCH 00/11] VRR/Adaptive Sync enabling in i915
This patch series adds support for DP 1.4 feature of Adaptive Sync also called as Variable Refresh rate which is used to match the display rate with the render rate by stretching or shrinking the blanking time of the frame. Aditya Swarup (1): drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare (10): drm/i915: Add REG_FIELD_PREP to VRR register def drm/i915/display/vrr: Create VRR file and add VRR capability check drm/i915/display/dp: Add VRR crtc state variables drm/i915/display/dp: Compute VRR state in atomic_check drm/i915/display/dp: Do not enable PSR if VRR is enabled drm/i915/display/vrr: Configure and enable VRR in modeset enable drm/i915/display/vrr: Send VRR push to flip the frame drm/i915/display/vrr: Disable VRR in modeset disable path drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink drm/i915/display: Add HW state readout for VRR drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 32 drivers/gpu/drm/i915/display/intel_display.c | 11 +- .../drm/i915/display/intel_display_types.h| 7 + drivers/gpu/drm/i915/display/intel_dp.c | 9 + drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 7 + drivers/gpu/drm/i915/display/intel_sprite.c | 5 + drivers/gpu/drm/i915/display/intel_vrr.c | 160 ++ drivers/gpu/drm/i915/display/intel_vrr.h | 27 +++ drivers/gpu/drm/i915/i915_reg.h | 1 + 11 files changed, 260 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/11] drm/i915/display/dp: Add VRR crtc state variables
Introduce VRR struct in intel_crtc_state and add
VRR crtc state variables Enable, Vtotalmin and Vtotalmax
to be derived from mode timings and VRR crtc property.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display_types.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..f6f7ec024da7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1092,6 +1092,13 @@ struct intel_crtc_state {
struct intel_dsb *dsb;
u32 psr2_man_track_ctl;
+
+ /* Variable Refresh Rate state */
+ struct {
+ bool enable;
+ u16 vtotalmin;
+ u16 vtotalmax;
+ } vrr;
};
enum intel_pipe_crc_source {
--
2.19.1
___
Intel-gfx mailing list
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[Intel-gfx] [PATCH 07/11] drm/i915/display/vrr: Configure and enable VRR in modeset enable
This patch computes the VRR parameters from VRR crtc states
and configures them in VRR registers during CRTC enable in
the modeset enable sequence.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5
drivers/gpu/drm/i915/display/intel_vrr.c | 38
drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 09811be08cfe..391c51979334 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -49,6 +49,7 @@
#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
+#include "intel_vrr.h"
struct ddi_buf_trans {
u32 trans1; /* balance leg enable, de-emph level */
@@ -4046,6 +4047,10 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
intel_ddi_enable_transcoder_func(encoder, crtc_state);
+ /* Enable VRR if requested through CRTC property */
+ if (crtc_state->vrr.enable)
+ intel_vrr_enable(encoder, crtc_state);
+
intel_enable_pipe(crtc_state);
intel_crtc_vblank_on(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 56114f535f94..7f1353bac583 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -64,3 +64,41 @@ intel_vrr_compute_config(struct intel_dp *intel_dp,
crtc_state->vrr.vtotalmax);
}
+void intel_vrr_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+ const struct drm_display_mode *adjusted_mode =
+ _state->hw.adjusted_mode;
+ u32 trans_vrr_ctl = 0, trans_vrr_vmax = 0, trans_vrr_vmin = 0,
trans_vrr_flipline = 0, trans_push = 0;
+ u16 framestart_to_pipelinefull_linecnt = 0;
+
+ framestart_to_pipelinefull_linecnt =
+ min_t(u16, 255, (crtc_state->vrr.vtotalmin -
adjusted_mode->crtc_vdisplay));
+
+ trans_vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_IGN_MAX_SHIFT |
+ VRR_CTL_FLIP_LINE_EN |
VRR_CTL_LINE_COUNT(framestart_to_pipelinefull_linecnt) |
+ VRR_CTL_SW_FULLLINE_COUNT;
+
+ /* Programming adjustments for 0 based regs */
+ trans_vrr_vmax = crtc_state->vrr.vtotalmax - 1;
+ trans_vrr_vmin = crtc_state->vrr.vtotalmin - 1;
+ trans_vrr_flipline = crtc_state->vrr.vtotalmin - 1;
+
+ trans_push = TRANS_PUSH_EN;
+
+ intel_de_write(dev_priv, TRANS_VRR_VMIN(pipe), trans_vrr_vmin);
+ intel_de_write(dev_priv, TRANS_VRR_VMAX(pipe), trans_vrr_vmax);
+ intel_de_write(dev_priv, TRANS_VRR_CTL(pipe), trans_vrr_ctl);
+ intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(pipe), trans_vrr_flipline);
+ intel_de_write(dev_priv, TRANS_PUSH(pipe), trans_push);
+
+ drm_dbg(_priv->drm, "Enabling VRR on pipe (%c)\n", pipe_name(pipe));
+ drm_dbg(_priv->drm, "VRR Parameters: Vblank - Min = %d, Max = %d
Flipline Count = %d, CTL Reg = 0x%08x, TRANS PUSH reg = 0x%08x",
+ crtc_state->vrr.vtotalmin, crtc_state->vrr.vtotalmax,
+ crtc_state->vrr.vtotalmin, trans_vrr_ctl,
+ trans_push);
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
b/drivers/gpu/drm/i915/display/intel_vrr.h
index 1e6fe8fe92ec..05d982d6fbae 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -17,5 +17,7 @@ struct intel_dp;
bool intel_is_vrr_capable(struct drm_connector *connector);
void intel_vrr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
+void intel_vrr_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VRR_H__ */
--
2.19.1
___
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[Intel-gfx] [PATCH 05/11] drm/i915/display/dp: Compute VRR state in atomic_check
This forces a complete modeset if vrr drm crtc state goes
from enabled to disabled and vice versa.
This patch also computes vrr state variables from the mode timings
and based on the vrr property set by userspace as well as hardware's
vrr capability.
v2:
*Rebase
v3:
* Vmin = max (vtotal, vmin) (Manasi)
v4:
* set crtc_state->vrr.enable = 0 for disable request
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +++-
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 38
drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++
4 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f41b6f8b5618..f70cc3b2a1a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14213,6 +14213,10 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(mst_master_transcoder);
+ PIPE_CONF_CHECK_BOOL(vrr.enable);
+ PIPE_CONF_CHECK_I(vrr.vtotalmin);
+ PIPE_CONF_CHECK_I(vrr.vtotalmax);
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_BOOL
@@ -15202,7 +15206,8 @@ static int intel_atomic_check(struct drm_device *dev,
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (new_crtc_state->inherited != old_crtc_state->inherited)
+ if (new_crtc_state->inherited != old_crtc_state->inherited ||
+ new_crtc_state->uapi.vrr_enabled !=
old_crtc_state->uapi.vrr_enabled)
new_crtc_state->uapi.mode_changed = true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3794b8f35edc..3185c4ca523d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2752,6 +2752,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (!HAS_DDI(dev_priv))
intel_dp_set_clock(encoder, pipe_config);
+ intel_vrr_compute_config(intel_dp, pipe_config);
intel_psr_compute_config(intel_dp, pipe_config);
intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
constant_n);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 0c8a91fabb64..56114f535f94 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -26,3 +26,41 @@ bool intel_is_vrr_capable(struct drm_connector *connector)
info->monitor_range.max_vfreq - info->monitor_range.min_vfreq >
10;
}
+void
+intel_vrr_compute_config(struct intel_dp *intel_dp,
+struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = _connector->base;
+ struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
+ const struct drm_display_info *info = >display_info;
+
+ if (!intel_is_vrr_capable(connector))
+ return;
+
+ if (!crtc_state->uapi.vrr_enabled) {
+ drm_dbg(_priv->drm,
+ "VRR disable requested by Userspace\n");
+ crtc_state->vrr.enable = false;
+ return;
+ }
+
+ crtc_state->vrr.enable = true;
+ crtc_state->vrr.vtotalmin =
+ max_t(u16, adjusted_mode->crtc_vtotal,
+ DIV_ROUND_CLOSEST(adjusted_mode->crtc_clock * 1000,
+ adjusted_mode->crtc_htotal *
+ info->monitor_range.max_vfreq));
+ crtc_state->vrr.vtotalmax =
+ max_t(u16, adjusted_mode->crtc_vtotal,
+ DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
+ adjusted_mode->crtc_htotal *
+ info->monitor_range.min_vfreq));
+
+ drm_dbg(_priv->drm,
+ "VRR Config: Enable = %s Vtotal Min = %d Vtotal Max = %d\n",
+yesno(crtc_state->vrr.enable), crtc_state->vrr.vtotalmin,
+crtc_state->vrr.vtotalmax);
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
b/drivers/gpu/drm/i915/display/intel_vrr.h
index 755746c7525c..1e6fe8fe92ec 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -15,5 +15,7 @@ struct intel_encoder;
struct intel_dp;
bool intel_is_vrr_capable(struct drm_connector *connector);
+void intel_vrr_compute_config(struct intel_dp *intel_dp,
+ struct
[Intel-gfx] [PATCH 02/11] drm/i915/display/vrr: Create VRR file and add VRR capability check
We create a new file for all VRR related helpers.
Also add a function to check vrr capability based on
platform support, DPCD bits and EDID monitor range.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 28
drivers/gpu/drm/i915/display/intel_vrr.h | 19
3 files changed, 48 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c
create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..3beeaf517191 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -249,6 +249,7 @@ i915-y += \
display/intel_sdvo.o \
display/intel_tv.o \
display/intel_vdsc.o \
+ display/intel_vrr.o \
display/vlv_dsi.o \
display/vlv_dsi_pll.o
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
new file mode 100644
index ..0c8a91fabb64
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Author: Manasi Navare
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+#include "intel_vrr.h"
+
+bool intel_is_vrr_capable(struct drm_connector *connector)
+{
+ struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
+ const struct drm_display_info *info = >display_info;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+ /*
+* DP Sink is capable of Variable refresh video timings if
+* Ignore MSA bit is set in DPCD.
+* EDID monitor range also should be atleast 10 for reasonable
+* Adaptive sync/ VRR end user experience.
+*/
+ return INTEL_GEN(dev_priv) >= 12 &&
+ drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
+ info->monitor_range.max_vfreq - info->monitor_range.min_vfreq >
10;
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
b/drivers/gpu/drm/i915/display/intel_vrr.h
new file mode 100644
index ..755746c7525c
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+*/
+
+#ifndef __INTEL_VRR_H__
+#define __INTEL_VRR_H__
+
+#include
+
+struct drm_connector;
+struct drm_i915_private;
+struct intel_crtc_state;
+struct intel_encoder;
+struct intel_dp;
+
+bool intel_is_vrr_capable(struct drm_connector *connector);
+
+#endif /* __INTEL_VRR_H__ */
--
2.19.1
___
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[Intel-gfx] [PATCH 08/11] drm/i915/display/vrr: Send VRR push to flip the frame
VRR achieves vblank stretching using the HW PUSH functionality.
So once the VRR is enabled during modeset then for each flip
request from userspace, in the atomic tail pipe_update_end()
we need to set the VRR push bit in HW for it to terminate
the vblank at configured flipline or anytime after flipline
or latest at the Vmax.
The HW clears the PUSH bit after the double buffer updates
are completed.
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +
drivers/gpu/drm/i915/display/intel_vrr.c| 17 +
drivers/gpu/drm/i915/display/intel_vrr.h| 1 +
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index b6deeb338477..cb10fe462f06 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -49,6 +49,7 @@
#include "intel_psr.h"
#include "intel_dsi.h"
#include "intel_sprite.h"
+#include "intel_vrr.h"
int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
int usecs)
@@ -217,6 +218,10 @@ void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state)
intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
icl_dsi_frame_update(new_crtc_state);
+ /* Send VRR Push to terminate Vblank */
+ if (new_crtc_state->vrr.enable)
+ intel_vrr_send_push(new_crtc_state);
+
/* We're still in the vblank-evade critical section, this can't race.
* Would be slightly nice to just grab the vblank count and arm the
* event outside of the critical section - the spinlock might spin for a
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 7f1353bac583..ec1ce88e869c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -102,3 +102,20 @@ void intel_vrr_enable(struct intel_encoder *encoder,
trans_push);
}
+void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 trans_push;
+
+ trans_push = intel_de_read(dev_priv, TRANS_PUSH(pipe));
+ WARN_ON(!(trans_push & TRANS_PUSH_EN));
+
+ trans_push |= TRANS_PUSH_SEND;
+ intel_de_write(dev_priv, TRANS_PUSH(pipe), trans_push);
+
+ drm_dbg(_priv->drm, "Sending VRR Push on Pipe (%c)\n",
+ pipe_name(pipe));
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
b/drivers/gpu/drm/i915/display/intel_vrr.h
index 05d982d6fbae..a6b78e1676cb 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -19,5 +19,6 @@ void intel_vrr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
void intel_vrr_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VRR_H__ */
--
2.19.1
___
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[Intel-gfx] [PATCH 01/11] drm/i915: Add REG_FIELD_PREP to VRR register def
VRR_CTL register onloy had a GENMASK but no field prep
define for TRANS_VRR_CTL_LINE_COUNT field so add that
Cc: Aditya Swarup
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4952c9875fb..9792c931b4c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4348,6 +4348,7 @@ enum {
#define VRR_CTL_IGN_MAX_SHIFTREG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3)
+#define VRR_CTL_LINE_COUNT(x)
REG_FIELD_PREP(VRR_CTL_LINE_COUNT_MASK, (x))
#define VRR_CTL_SW_FULLLINE_COUNTREG_BIT(0)
#define _TRANS_VRR_VMAX_A 0x60424
--
2.19.1
___
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[Intel-gfx] [PATCH 11/11] drm/i915/display: Add HW state readout for VRR
This functions gets the VRR config from the VRR registers
to match the crtc state variables for VRR.
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 4
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f70cc3b2a1a4..30904e466cb5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -56,6 +56,7 @@
#include "display/intel_sdvo.h"
#include "display/intel_tv.h"
#include "display/intel_vdsc.h"
+#include "display/intel_vrr.h"
#include "gt/intel_rps.h"
@@ -11387,6 +11388,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
intel_get_transcoder_timings(crtc, pipe_config);
}
+ if (INTEL_GEN(dev_priv) >= 12)
+ intel_vrr_get_config(crtc, pipe_config);
+
intel_get_pipe_src_size(crtc, pipe_config);
if (IS_HASWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5075ecb9b5a7..aede2c86cc71 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -141,3 +141,20 @@ void intel_vrr_disable(const struct intel_crtc_state
*old_crtc_state)
pipe_name(pipe));
}
+void intel_vrr_get_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 trans_vrr_ctl;
+
+ trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(pipe));
+ pipe_config->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ if (!pipe_config->vrr.enable)
+ return;
+
+ pipe_config->vrr.vtotalmax = intel_de_read(dev_priv,
TRANS_VRR_VMAX(pipe)) + 1;
+ pipe_config->vrr.vtotalmin = intel_de_read(dev_priv,
TRANS_VRR_VMIN(pipe)) + 1;
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
b/drivers/gpu/drm/i915/display/intel_vrr.h
index 8c6fd2d1bee5..dc20359d0821 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -21,5 +21,7 @@ void intel_vrr_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
+void intel_vrr_get_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config);
#endif /* __INTEL_VRR_H__ */
--
2.19.1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Skip RPS tests on Ironlake (only IPS)
== Series Details ==
Series: drm/i915/selftests: Skip RPS tests on Ironlake (only IPS)
URL : https://patchwork.freedesktop.org/series/82965/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9186 -> Patchwork_18768
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/index.html
Known issues
Here are the changes found in Patchwork_18768 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1635])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
Warnings
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [SKIP][7] ([fdo#109271]) -> [DMESG-FAIL][8]
([i915#2203])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/fi-kbl-guc/igt@i915_pm_...@basic-rte.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/fi-kbl-guc/igt@i915_pm_...@basic-rte.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
Participating hosts (44 -> 39)
--
Additional (1): fi-skl-lmem
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper
Build changes
-
* Linux: CI_DRM_9186 -> Patchwork_18768
CI-20190529: 20190529
CI_DRM_9186: 88e88abb49e9b08d25ba928cc34ed09082f209b0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18768: cf81628ecd458dcabed380aeedd62d5ae61b1a5d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cf81628ecd45 drm/i915/selftests: Skip RPS tests on Ironlake (only IPS)
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18768/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Skip RPS tests on Ironlake (only IPS)
Since Ironlake uses intel_ips.ko for its dynamic frequency adjustment, we do not have direct control over the frequency management so such tests are defunct. Similarly, we can't check the gen6+ RPS registers on Ironlake. Hopefully this catches all the invalid tests now that Ironlake has rejoined the dynamic GPU frequency club. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/selftest_rps.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 3540ba9bd459..aa5675ecb5cc 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -219,7 +219,7 @@ int live_rps_clock_interval(void *arg) struct igt_spinner spin; int err = 0; - if (!intel_rps_is_enabled(rps)) + if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6) return 0; if (igt_spinner_init(, gt)) @@ -1028,7 +1028,7 @@ int live_rps_interrupt(void *arg) * First, let's check whether or not we are receiving interrupts. */ - if (!intel_rps_has_interrupts(rps)) + if (!intel_rps_has_interrupts(rps) || INTEL_GEN(gt->i915) < 6) return 0; intel_gt_pm_get(gt); @@ -1133,7 +1133,7 @@ int live_rps_power(void *arg) * that theory. */ - if (!intel_rps_is_enabled(rps)) + if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6) return 0; if (!librapl_energy_uJ()) @@ -1237,7 +1237,7 @@ int live_rps_dynamic(void *arg) * moving parts into dynamic reclocking based on load. */ - if (!intel_rps_is_enabled(rps)) + if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6) return 0; if (igt_spinner_init(, gt)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-next-fixes
Hi Dave and Daniel, Here is probably the last drm-intel-next-fixes before -rc1. This includes a few patches from dinq and a bunch from drm-intel-gt-next. drm-intel-next-fixes-2020-10-22: - Tweak initia DPCD backlight.enabled value (Sean) - Initialize reserved MOCS indices (Ayaz) - Mark initial fb obj as WT on eLLC machines to avoid rcu lockup (Ville) - Support parsing of oversize batches (Chris) - Delay execlists processing for TGL (Chris) - Use the active reference on the vma during error capture (Chris) - Widen CSB pointer (Chris) - Wait for CSB entries on TGL (Chris) - Fix unwind for scratch page allocation (Chris) - Exclude low patches of stolen memory (Chris) - Force VT'd workarounds when running as a guest OS (Chris) - Drop runtime-pm assert from vpgu io accessors (Chris) The following changes since commit 214bba50616f65264dfc30d095daef3ab7500f52: drm/i915: Set all unused color plane offsets to ~0xfff again (2020-10-12 14:23:22 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2020-10-22 for you to fetch changes up to 5c6c13cd1102caf92d006a3cf4591c0229019daf: drm/i915: Drop runtime-pm assert from vgpu io accessors (2020-10-21 08:32:32 -0400) - Tweak initia DPCD backlight.enabled value (Sean) - Initialize reserved MOCS indices (Ayaz) - Mark initial fb obj as WT on eLLC machines to avoid rcu lockup (Ville) - Support parsing of oversize batches (Chris) - Delay execlists processing for TGL (Chris) - Use the active reference on the vma during error capture (Chris) - Widen CSB pointer (Chris) - Wait for CSB entries on TGL (Chris) - Fix unwind for scratch page allocation (Chris) - Exclude low patches of stolen memory (Chris) - Force VT'd workarounds when running as a guest OS (Chris) - Drop runtime-pm assert from vpgu io accessors (Chris) Ayaz A Siddiqui (1): drm/i915/gt: Initialize reserved and unspecified MOCS indices Chris Wilson (10): drm/i915/gem: Support parsing of oversize batches drm/i915/gt: Delay execlist processing for tgl drm/i915/gt: Undo forced context restores after trivial preemptions drm/i915: Use the active reference on the vma while capturing drm/i915/gt: Widen CSB pointer to u64 for the parsers drm/i915/gt: Wait for CSB entries on Tigerlake drm/i915/gt: Onion unwind for scratch page allocation failure drm/i915: Exclude low pages (128KiB) of stolen from use drm/i915: Force VT'd workarounds when running as a guest OS drm/i915: Drop runtime-pm assert from vgpu io accessors Sean Paul (1): drm/i915/dp: Tweak initial dpcd backlight.enabled value Ville Syrjälä (1): drm/i915: Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init drivers/gpu/drm/i915/Kconfig.debug | 1 + drivers/gpu/drm/i915/display/intel_display.c | 8 + .../gpu/drm/i915/display/intel_dp_aux_backlight.c | 31 ++-- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 2 + drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 18 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c| 58 +++--- drivers/gpu/drm/i915/gt/intel_mocs.c | 16 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 196 + drivers/gpu/drm/i915/i915_drv.h| 6 +- drivers/gpu/drm/i915/i915_gpu_error.c | 3 +- drivers/gpu/drm/i915/intel_uncore.c| 27 ++- 15 files changed, 334 insertions(+), 53 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/modes: Switch to 64bit maths to avoid integer overflow
== Series Details == Series: drm/modes: Switch to 64bit maths to avoid integer overflow URL : https://patchwork.freedesktop.org/series/82963/ State : success == Summary == CI Bug Log - changes from CI_DRM_9186 -> Patchwork_18767 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/index.html Known issues Here are the changes found in Patchwork_18767 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1635]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9186/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 Participating hosts (44 -> 39) -- Additional (1): fi-skl-lmem Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes - * Linux: CI_DRM_9186 -> Patchwork_18767 CI-20190529: 20190529 CI_DRM_9186: 88e88abb49e9b08d25ba928cc34ed09082f209b0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18767: af56b064d8e01c158fb67bbc7f7475f4cb6a5ba7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == af56b064d8e0 drm/modes: Switch to 64bit maths to avoid integer overflow == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18767/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/atomic-helpers: remove legacy_cursor_update hacks (rev2)
== Series Details == Series: series starting with [1/3] drm/atomic-helpers: remove legacy_cursor_update hacks (rev2) URL : https://patchwork.freedesktop.org/series/82926/ State : failure == Summary == Applying: drm/atomic-helpers: remove legacy_cursor_update hacks error: patch failed: drivers/gpu/drm/msm/msm_atomic.c:215 error: drivers/gpu/drm/msm/msm_atomic.c: patch does not apply error: Did you hand edit your patch? It does not apply to blobs recorded in its index. hint: Use 'git am --show-current-patch=diff' to see the failed patch Using index info to reconstruct a base tree... Patch failed at 0001 drm/atomic-helpers: remove legacy_cursor_update hacks When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/modes: Switch to 64bit maths to avoid integer overflow
From: Ville Syrjälä The new >8k CEA modes have dotclocks reaching 5.94 GHz, which means our clock*1000 will now overflow the 32bit unsigned integer. Switch to 64bit maths to avoid it. Cc: sta...@vger.kernel.org Reported-by: Randy Dunlap Signed-off-by: Ville Syrjälä --- An interesting question how many other place might suffer from similar overflows. I think i915 should be mostly OK. The one place I know we use Hz instead kHz is the hsw DPLL code, which I would prefer we also change to use kHz. The other concern is whether we have any potential overflows before we check this against the platform's max dotclock. I do have this unreviewed igt series https://patchwork.freedesktop.org/series/69531/ which extends the current testing with some other forms of invalid modes. Could probably extend that with a mode.clock=INT_MAX test to see if anything else might trip up. No idea about other drivers. drivers/gpu/drm/drm_modes.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 501b4fe55a3d..511cde5c7fa6 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -762,7 +762,7 @@ int drm_mode_vrefresh(const struct drm_display_mode *mode) if (mode->htotal == 0 || mode->vtotal == 0) return 0; - num = mode->clock * 1000; + num = mode->clock; den = mode->htotal * mode->vtotal; if (mode->flags & DRM_MODE_FLAG_INTERLACE) @@ -772,7 +772,7 @@ int drm_mode_vrefresh(const struct drm_display_mode *mode) if (mode->vscan > 1) den *= mode->vscan; - return DIV_ROUND_CLOSEST(num, den); + return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(num, 1000), den); } EXPORT_SYMBOL(drm_mode_vrefresh); -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/atomic-helpers: remove legacy_cursor_update hacks
On Thu, Oct 22, 2020 at 7:22 PM Rob Clark wrote:
>
> On Thu, Oct 22, 2020 at 10:02 AM Rob Clark wrote:
> >
> > On Wed, Oct 21, 2020 at 9:32 AM Daniel Vetter
> > wrote:
> > >
> > > The stuff never really worked, and leads to lots of fun because it
> > > out-of-order frees atomic states. Which upsets KASAN, among other
> > > things.
> > >
> > > For async updates we now have a more solid solution with the
> > > ->atomic_async_check and ->atomic_async_commit hooks. Support for that
> > > for msm and vc4 landed. nouveau and i915 have their own commit
> > > routines, doing something similar.
> > >
> > > For everyone else it's probably better to remove the use-after-free
> > > bug, and encourage folks to use the async support instead. The
> > > affected drivers which register a legacy cursor plane and don't either
> > > use the new async stuff or their own commit routine are: amdgpu,
> > > atmel, mediatek, qxl, rockchip, sti, sun4i, tegra, virtio, and vmwgfx.
> > >
> > > Inspired by an amdgpu bug report.
> > >
> > > v2: Drop RFC, I think with amdgpu converted over to use
> > > atomic_async_check/commit done in
> > >
> > > commit 674e78acae0dfb4beb56132e41cbae5b60f7d662
> > > Author: Nicholas Kazlauskas
> > > Date: Wed Dec 5 14:59:07 2018 -0500
> > >
> > > drm/amd/display: Add fast path for cursor plane updates
> > >
> > > we don't have any driver anymore where we have userspace expecting
> > > solid legacy cursor support _and_ they are using the atomic helpers in
> > > their fully glory. So we can retire this.
> > >
> > > References: https://bugzilla.kernel.org/show_bug.cgi?id=199425
> > > Cc: mikita.lip...@amd.com
> > > Cc: Michel Dänzer
> > > Cc: harry.wentl...@amd.com
> > > Signed-off-by: Daniel Vetter
> >
> > This *completely* destroys fps when there is cursor movement, it would
> > be a pretty bad regression, so nak
>
> Which I *guess* is due to dpu not wiring up the plane->async_* funcs,
> effectively making cursor updates synchronous.. but it will take some
> time to sort out :-(
Does something like the below (not even compile tested) get dpu back in order?
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 561bfa48841c..ec8b4f74da49 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -215,6 +215,8 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state)
/* async updates are limited to single-crtc updates: */
WARN_ON(crtc_mask != drm_crtc_mask(async_crtc));
+ complete_all(async_crtc->state->flip_done);
+
/*
* Start timer if we don't already have an update pending
* on this crtc:
That way we could perhaps still move ahead with removing the hacks
from shared helpers, and msm-dpu can keep doing what it does. The
other hunk is in a function that dpu code doesn't even use, so can't
see how that would change anything.
-Daniel
>
> > BR,
> > -R
> >
> > > ---
> > > drivers/gpu/drm/drm_atomic_helper.c | 13 -
> > > 1 file changed, 13 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > > b/drivers/gpu/drm/drm_atomic_helper.c
> > > index a7bcb4b4586c..549a31e6042c 100644
> > > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > > @@ -1481,13 +1481,6 @@ drm_atomic_helper_wait_for_vblanks(struct
> > > drm_device *dev,
> > > int i, ret;
> > > unsigned crtc_mask = 0;
> > >
> > > -/*
> > > - * Legacy cursor ioctls are completely unsynced, and userspace
> > > - * relies on that (by doing tons of cursor updates).
> > > - */
> > > - if (old_state->legacy_cursor_update)
> > > - return;
> > > -
> > > for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state,
> > > new_crtc_state, i) {
> > > if (!new_crtc_state->active)
> > > continue;
> > > @@ -2106,12 +2099,6 @@ int drm_atomic_helper_setup_commit(struct
> > > drm_atomic_state *state,
> > > continue;
> > > }
> > >
> > > - /* Legacy cursor updates are fully unsynced. */
> > > - if (state->legacy_cursor_update) {
> > > - complete_all(>flip_done);
> > > - continue;
> > > - }
> > > -
> > > if (!new_crtc_state->event) {
> > > commit->event = kzalloc(sizeof(*commit->event),
> > > GFP_KERNEL);
> > > --
> > > 2.28.0
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Re: [Intel-gfx] [PATCH] drm/i915: Reset the interrupt mask on disabling interrupts
Quoting Ville Syrjälä (2020-10-22 18:33:43) > On Thu, Oct 22, 2020 at 12:42:46PM +0100, Chris Wilson wrote: > > As we disable the interrupt during suspend, also reset the irq_mask to > > short-circuit subsystems that later try to turn off their interrupt > > source. > > > > <4>[ 101.816730] i915 :00:02.0: > > drm_WARN_ON(!intel_irqs_enabled(dev_priv)) > > <4>[ 101.816853] WARNING: CPU: 3 PID: 4241 at > > drivers/gpu/drm/i915/i915_irq.c:343 ilk_update_display_irq+0xb3/0x130 [i915] > > > > v2: Reset irq_mask for i8xx_irq_reset as well, and split patch to focus > > on only i915->irq_mask > > > > Signed-off-by: Chris Wilson > > Cc: Ville Syrjälä > > Reviewed-by: Ville Syrjälä And fingers crossed for fi-ilk-m making a speedy recovery. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: skip disabling CTBs before sanitizing the GuC
On Wed, Oct 21, 2020 at 12:14:54PM -0700, Daniele Ceraolo Spurio wrote: > If we're about to sanitize the GuC, something might have gone wrong > beforehand, so we should avoid trying to talk to it. Even if GuC is > still running fine, the sanitize will reset its internal state and clear > the CTB registration, so there is still no need to explicitly do so. > > References: https://gitlab.freedesktop.org/drm/intel/-/issues/2469 > Signed-off-by: Daniele Ceraolo Spurio Looks good to me. Reviewed-by: Matthew Brost > Cc: Michal Wajdeczko > Cc: Matthew Brost > Cc: John Harrison > --- > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +--- > 1 file changed, 1 insertion(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > index 4e6070e95fe9..309eef9313e8 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c > @@ -486,7 +486,7 @@ static int __uc_init_hw(struct intel_uc *uc) > > ret = intel_guc_sample_forcewake(guc); > if (ret) > - goto err_communication; > + goto err_log_capture; > > if (intel_uc_uses_guc_submission(uc)) > intel_guc_submission_enable(guc); > @@ -511,8 +511,6 @@ static int __uc_init_hw(struct intel_uc *uc) > /* >* We've failed to load the firmware :( >*/ > -err_communication: > - guc_disable_communication(guc); > err_log_capture: > __uc_capture_load_err_log(uc); > err_out: > @@ -540,9 +538,6 @@ static void __uc_fini_hw(struct intel_uc *uc) > if (intel_uc_uses_guc_submission(uc)) > intel_guc_submission_disable(guc); > > - if (guc_communication_enabled(guc)) > - guc_disable_communication(guc); > - > __uc_sanitize(uc); > } > > @@ -559,7 +554,6 @@ void intel_uc_reset_prepare(struct intel_uc *uc) > if (!intel_guc_is_ready(guc)) > return; > > - guc_disable_communication(guc); > __uc_sanitize(uc); > } > > -- > 2.24.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Reset the interrupt mask on disabling interrupts
On Thu, Oct 22, 2020 at 12:42:46PM +0100, Chris Wilson wrote:
> As we disable the interrupt during suspend, also reset the irq_mask to
> short-circuit subsystems that later try to turn off their interrupt
> source.
>
> <4>[ 101.816730] i915 :00:02.0:
> drm_WARN_ON(!intel_irqs_enabled(dev_priv))
> <4>[ 101.816853] WARNING: CPU: 3 PID: 4241 at
> drivers/gpu/drm/i915/i915_irq.c:343 ilk_update_display_irq+0xb3/0x130 [i915]
>
> v2: Reset irq_mask for i8xx_irq_reset as well, and split patch to focus
> on only i915->irq_mask
>
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 09221ca1ffb2..53e67c796d09 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -337,17 +337,14 @@ void ilk_update_display_irq(struct drm_i915_private
> *dev_priv,
> u32 new_val;
>
> lockdep_assert_held(_priv->irq_lock);
> -
> drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
>
> - if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
> - return;
> -
> new_val = dev_priv->irq_mask;
> new_val &= ~interrupt_mask;
> new_val |= (~enabled_irq_mask & interrupt_mask);
>
> - if (new_val != dev_priv->irq_mask) {
> + if (new_val != dev_priv->irq_mask &&
> + !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
> dev_priv->irq_mask = new_val;
> I915_WRITE(DEIMR, dev_priv->irq_mask);
> POSTING_READ(DEIMR);
> @@ -2951,6 +2948,8 @@ static void ilk_irq_reset(struct drm_i915_private
> *dev_priv)
> struct intel_uncore *uncore = _priv->uncore;
>
> GEN3_IRQ_RESET(uncore, DE);
> + dev_priv->irq_mask = ~0u;
> +
> if (IS_GEN(dev_priv, 7))
> intel_uncore_write(uncore, GEN7_ERR_INT, 0x);
>
> @@ -3695,6 +3694,7 @@ static void i8xx_irq_reset(struct drm_i915_private
> *dev_priv)
> i9xx_pipestat_irq_reset(dev_priv);
>
> GEN2_IRQ_RESET(uncore);
> + dev_priv->irq_mask = ~0u;
> }
>
> static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -3864,6 +3864,7 @@ static void i915_irq_reset(struct drm_i915_private
> *dev_priv)
> i9xx_pipestat_irq_reset(dev_priv);
>
> GEN3_IRQ_RESET(uncore, GEN2_);
> + dev_priv->irq_mask = ~0u;
> }
>
> static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -3970,6 +3971,7 @@ static void i965_irq_reset(struct drm_i915_private
> *dev_priv)
> i9xx_pipestat_irq_reset(dev_priv);
>
> GEN3_IRQ_RESET(uncore, GEN2_);
> + dev_priv->irq_mask = ~0u;
> }
>
> static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
> --
> 2.20.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 1/3] drm/atomic-helpers: remove legacy_cursor_update hacks
On Thu, Oct 22, 2020 at 10:02 AM Rob Clark wrote:
>
> On Wed, Oct 21, 2020 at 9:32 AM Daniel Vetter wrote:
> >
> > The stuff never really worked, and leads to lots of fun because it
> > out-of-order frees atomic states. Which upsets KASAN, among other
> > things.
> >
> > For async updates we now have a more solid solution with the
> > ->atomic_async_check and ->atomic_async_commit hooks. Support for that
> > for msm and vc4 landed. nouveau and i915 have their own commit
> > routines, doing something similar.
> >
> > For everyone else it's probably better to remove the use-after-free
> > bug, and encourage folks to use the async support instead. The
> > affected drivers which register a legacy cursor plane and don't either
> > use the new async stuff or their own commit routine are: amdgpu,
> > atmel, mediatek, qxl, rockchip, sti, sun4i, tegra, virtio, and vmwgfx.
> >
> > Inspired by an amdgpu bug report.
> >
> > v2: Drop RFC, I think with amdgpu converted over to use
> > atomic_async_check/commit done in
> >
> > commit 674e78acae0dfb4beb56132e41cbae5b60f7d662
> > Author: Nicholas Kazlauskas
> > Date: Wed Dec 5 14:59:07 2018 -0500
> >
> > drm/amd/display: Add fast path for cursor plane updates
> >
> > we don't have any driver anymore where we have userspace expecting
> > solid legacy cursor support _and_ they are using the atomic helpers in
> > their fully glory. So we can retire this.
> >
> > References: https://bugzilla.kernel.org/show_bug.cgi?id=199425
> > Cc: mikita.lip...@amd.com
> > Cc: Michel Dänzer
> > Cc: harry.wentl...@amd.com
> > Signed-off-by: Daniel Vetter
>
> This *completely* destroys fps when there is cursor movement, it would
> be a pretty bad regression, so nak
Which I *guess* is due to dpu not wiring up the plane->async_* funcs,
effectively making cursor updates synchronous.. but it will take some
time to sort out :-(
> BR,
> -R
>
> > ---
> > drivers/gpu/drm/drm_atomic_helper.c | 13 -
> > 1 file changed, 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > b/drivers/gpu/drm/drm_atomic_helper.c
> > index a7bcb4b4586c..549a31e6042c 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -1481,13 +1481,6 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device
> > *dev,
> > int i, ret;
> > unsigned crtc_mask = 0;
> >
> > -/*
> > - * Legacy cursor ioctls are completely unsynced, and userspace
> > - * relies on that (by doing tons of cursor updates).
> > - */
> > - if (old_state->legacy_cursor_update)
> > - return;
> > -
> > for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > if (!new_crtc_state->active)
> > continue;
> > @@ -2106,12 +2099,6 @@ int drm_atomic_helper_setup_commit(struct
> > drm_atomic_state *state,
> > continue;
> > }
> >
> > - /* Legacy cursor updates are fully unsynced. */
> > - if (state->legacy_cursor_update) {
> > - complete_all(>flip_done);
> > - continue;
> > - }
> > -
> > if (!new_crtc_state->event) {
> > commit->event = kzalloc(sizeof(*commit->event),
> > GFP_KERNEL);
> > --
> > 2.28.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 1/3] drm/atomic-helpers: remove legacy_cursor_update hacks
On Wed, Oct 21, 2020 at 9:32 AM Daniel Vetter wrote:
>
> The stuff never really worked, and leads to lots of fun because it
> out-of-order frees atomic states. Which upsets KASAN, among other
> things.
>
> For async updates we now have a more solid solution with the
> ->atomic_async_check and ->atomic_async_commit hooks. Support for that
> for msm and vc4 landed. nouveau and i915 have their own commit
> routines, doing something similar.
>
> For everyone else it's probably better to remove the use-after-free
> bug, and encourage folks to use the async support instead. The
> affected drivers which register a legacy cursor plane and don't either
> use the new async stuff or their own commit routine are: amdgpu,
> atmel, mediatek, qxl, rockchip, sti, sun4i, tegra, virtio, and vmwgfx.
>
> Inspired by an amdgpu bug report.
>
> v2: Drop RFC, I think with amdgpu converted over to use
> atomic_async_check/commit done in
>
> commit 674e78acae0dfb4beb56132e41cbae5b60f7d662
> Author: Nicholas Kazlauskas
> Date: Wed Dec 5 14:59:07 2018 -0500
>
> drm/amd/display: Add fast path for cursor plane updates
>
> we don't have any driver anymore where we have userspace expecting
> solid legacy cursor support _and_ they are using the atomic helpers in
> their fully glory. So we can retire this.
>
> References: https://bugzilla.kernel.org/show_bug.cgi?id=199425
> Cc: mikita.lip...@amd.com
> Cc: Michel Dänzer
> Cc: harry.wentl...@amd.com
> Signed-off-by: Daniel Vetter
This *completely* destroys fps when there is cursor movement, it would
be a pretty bad regression, so nak
BR,
-R
> ---
> drivers/gpu/drm/drm_atomic_helper.c | 13 -
> 1 file changed, 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c
> index a7bcb4b4586c..549a31e6042c 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -1481,13 +1481,6 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device
> *dev,
> int i, ret;
> unsigned crtc_mask = 0;
>
> -/*
> - * Legacy cursor ioctls are completely unsynced, and userspace
> - * relies on that (by doing tons of cursor updates).
> - */
> - if (old_state->legacy_cursor_update)
> - return;
> -
> for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if (!new_crtc_state->active)
> continue;
> @@ -2106,12 +2099,6 @@ int drm_atomic_helper_setup_commit(struct
> drm_atomic_state *state,
> continue;
> }
>
> - /* Legacy cursor updates are fully unsynced. */
> - if (state->legacy_cursor_update) {
> - complete_all(>flip_done);
> - continue;
> - }
> -
> if (!new_crtc_state->event) {
> commit->event = kzalloc(sizeof(*commit->event),
> GFP_KERNEL);
> --
> 2.28.0
>
> ___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Reset the interrupt mask on disabling interrupts (rev2)
== Series Details == Series: drm/i915: Reset the interrupt mask on disabling interrupts (rev2) URL : https://patchwork.freedesktop.org/series/82945/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9182_full -> Patchwork_18765_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18765_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18765_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18765_full: ### IGT changes ### Possible regressions * igt@i915_suspend@debugfs-reader: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-skl6/igt@i915_susp...@debugfs-reader.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-skl7/igt@i915_susp...@debugfs-reader.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180: - shard-skl: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-skl9/igt@kms_...@pipe-a-crc-primary-rotation-180.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-skl9/igt@kms_...@pipe-a-crc-primary-rotation-180.html Known issues Here are the changes found in Patchwork_18765_full that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@hotrebind-lateclose: - shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-snb4/igt@core_hotunp...@hotrebind-lateclose.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-snb5/igt@core_hotunp...@hotrebind-lateclose.html * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#198]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-skl2/igt@gem_ctx_isolation@preservation...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-skl6/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_exec_reloc@basic-many-active@vcs0: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2389]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-glk3/igt@gem_exec_reloc@basic-many-act...@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-glk9/igt@gem_exec_reloc@basic-many-act...@vcs0.html * igt@gem_exec_whisper@basic-contexts: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#118] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-glk8/igt@gem_exec_whis...@basic-contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-glk3/igt@gem_exec_whis...@basic-contexts.html * igt@gem_softpin@noreloc-s3: - shard-snb: [PASS][13] -> [DMESG-WARN][14] ([i915#42]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-snb7/igt@gem_soft...@noreloc-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-snb2/igt@gem_soft...@noreloc-s3.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-hsw: [PASS][15] -> [WARN][16] ([i915#1519]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-hsw8/igt@i915_pm_rc6_reside...@rc6-fence.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-hsw6/igt@i915_pm_rc6_reside...@rc6-fence.html * igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +5 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-skl9/igt@kms_cursor_edge_w...@pipe-b-256x256-right-edge.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-skl6/igt@kms_cursor_edge_w...@pipe-b-256x256-right-edge.html * igt@kms_dp_aux_dev: - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#2344]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-iclb1/igt@kms_dp_aux_dev.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-iclb7/igt@kms_dp_aux_dev.html * igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#2122]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-skl4/igt@kms_flip@plain-flip-ts-check-interrupti...@a-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/shard-skl7/igt@kms_flip@plain-flip-ts-check-interrupti...@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack: - shard-snb:
[Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP 2.2 DP MST Support (rev5)
== Series Details == Series: HDCP 2.2 DP MST Support (rev5) URL : https://patchwork.freedesktop.org/series/81538/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9182_full -> Patchwork_18764_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18764_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18764_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18764_full: ### IGT changes ### Possible regressions * igt@i915_pm_sseu@full-enable: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-skl8/igt@i915_pm_s...@full-enable.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-skl10/igt@i915_pm_s...@full-enable.html Known issues Here are the changes found in Patchwork_18764_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-many-active@vcs0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2389]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-glk3/igt@gem_exec_reloc@basic-many-act...@vcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-glk1/igt@gem_exec_reloc@basic-many-act...@vcs0.html * igt@gem_exec_whisper@basic-forked-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-glk8/igt@gem_exec_whis...@basic-forked-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-glk4/igt@gem_exec_whis...@basic-forked-all.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#198]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-skl2/igt@gem_soft...@noreloc-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-skl1/igt@gem_soft...@noreloc-s3.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [PASS][9] -> [INCOMPLETE][10] ([i915#155]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-kbl1/igt@i915_susp...@debugfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-kbl6/igt@i915_susp...@debugfs-reader.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-270: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-apl3/igt@kms_big...@yf-tiled-32bpp-rotate-270.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-apl7/igt@kms_big...@yf-tiled-32bpp-rotate-270.html * igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-snb: [PASS][13] -> [FAIL][14] ([i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-snb4/igt@kms_draw_...@draw-method-xrgb2101010-blt-untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-snb5/igt@kms_draw_...@draw-method-xrgb2101010-blt-untiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#2122]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#79]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html * igt@kms_frontbuffer_tracking@fbc-modesetfrombusy: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#49]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-glk7/igt@kms_frontbuffer_track...@fbc-modesetfrombusy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/shard-glk7/igt@kms_frontbuffer_track...@fbc-modesetfrombusy.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/shard-glk8/igt@kms_frontbuffer_track...@fbc-stridechange.html [22]:
Re: [Intel-gfx] [PATCH CI v2 0/4] drm/i915/guc: Update to GuC v49
+ Joonas for maintainer class question. On 15/10/2020 19:28, john.c.harri...@intel.com wrote: From: John Harrison Update to the latest GuC firmware v2: Rebase to newer tree, updated a commit message (review feedback from Daniele) and dropped the patch to enable GuC/HuC loading by default as apparently this is not allowed. Signed-off-by: John Harrison John Harrison (4): drm/i915/guc: Update to use firmware v49.0.1 drm/i915/guc: Improved reporting when GuC fails to load drm/i915/guc: Clear pointers on free CI: turn on GuC/HuC auto mode by default drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 18 --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 132 +++ drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c| 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c| 31 +++-- drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 80 +-- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 5 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 29 ++-- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 6 +- drivers/gpu/drm/i915/i915_params.h | 2 +- 11 files changed, 202 insertions(+), 107 deletions(-) I tried to merge this for John today but the series applies to drm-intel-next-queued and not drm-intel-gt-next, which I thought is where GT/GuC should go to. Long story short, where to merge GuC patches and how is the question? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_mmap_gtt: Trim object size for ptracing
For verifying vm_ops.access we only need a page or two to check we both
advance across a page boundary and find the right offset within a page.
16MiB is overkill for the slow uncached reads through the slow ptrace
interface, so reduce the object size by a couple of orders of magnitude.
Signed-off-by: Chris Wilson
---
tests/i915/gem_mmap_gtt.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_gtt.c
index 6637bba06..3cce19e9a 100644
--- a/tests/i915/gem_mmap_gtt.c
+++ b/tests/i915/gem_mmap_gtt.c
@@ -525,6 +525,7 @@ static void *memchr_inv(const void *s, int c, size_t n)
static void
test_ptrace(int fd)
{
+ unsigned long sz = 16 * 4096;
unsigned long AA, CC;
unsigned long *gtt, *cpy;
uint32_t bo;
@@ -533,16 +534,16 @@ test_ptrace(int fd)
memset(, 0xaa, sizeof(AA));
memset(, 0x55, sizeof(CC));
- cpy = malloc(OBJECT_SIZE);
- memset(cpy, AA, OBJECT_SIZE);
+ cpy = malloc(sz);
+ memset(cpy, AA, sz);
- bo = gem_create(fd, OBJECT_SIZE);
- gtt = mmap_bo(fd, bo, OBJECT_SIZE);
- memset(gtt, CC, OBJECT_SIZE);
+ bo = gem_create(fd, sz);
+ gtt = mmap_bo(fd, bo, sz);
+ memset(gtt, CC, sz);
gem_close(fd, bo);
- igt_assert(!memchr_inv(gtt, CC, OBJECT_SIZE));
- igt_assert(!memchr_inv(cpy, AA, OBJECT_SIZE));
+ igt_assert(!memchr_inv(gtt, CC, sz));
+ igt_assert(!memchr_inv(cpy, AA, sz));
igt_fork(child, 1) {
ptrace(PTRACE_TRACEME, 0, NULL, NULL);
@@ -553,7 +554,7 @@ test_ptrace(int fd)
pid = wait(NULL);
ptrace(PTRACE_ATTACH, pid, NULL, NULL);
- for (int i = 0; i < OBJECT_SIZE / sizeof(long); i++) {
+ for (int i = 0; i < sz / sizeof(long); i++) {
long ret;
ret = ptrace(PTRACE_PEEKDATA, pid, gtt + i);
@@ -570,10 +571,10 @@ test_ptrace(int fd)
igt_waitchildren();
/* The contents of the two buffers should now be swapped */
- igt_assert(!memchr_inv(gtt, AA, OBJECT_SIZE));
- igt_assert(!memchr_inv(cpy, CC, OBJECT_SIZE));
+ igt_assert(!memchr_inv(gtt, AA, sz));
+ igt_assert(!memchr_inv(cpy, CC, sz));
- munmap(gtt, OBJECT_SIZE);
+ munmap(gtt, sz);
free(cpy);
}
--
2.28.0
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Re: [Intel-gfx] [PATCH 1/3] drm/atomic-helpers: remove legacy_cursor_update hacks
On Thu, Oct 22, 2020 at 09:36:23AM -0400, Kazlauskas, Nicholas wrote:
> On 2020-10-21 12:32 p.m., Daniel Vetter wrote:
> > The stuff never really worked, and leads to lots of fun because it
> > out-of-order frees atomic states. Which upsets KASAN, among other
> > things.
> >
> > For async updates we now have a more solid solution with the
> > ->atomic_async_check and ->atomic_async_commit hooks. Support for that
> > for msm and vc4 landed. nouveau and i915 have their own commit
> > routines, doing something similar.
> >
> > For everyone else it's probably better to remove the use-after-free
> > bug, and encourage folks to use the async support instead. The
> > affected drivers which register a legacy cursor plane and don't either
> > use the new async stuff or their own commit routine are: amdgpu,
> > atmel, mediatek, qxl, rockchip, sti, sun4i, tegra, virtio, and vmwgfx.
> >
> > Inspired by an amdgpu bug report.
> >
> > v2: Drop RFC, I think with amdgpu converted over to use
> > atomic_async_check/commit done in
> >
> > commit 674e78acae0dfb4beb56132e41cbae5b60f7d662
> > Author: Nicholas Kazlauskas
> > Date: Wed Dec 5 14:59:07 2018 -0500
> >
> > drm/amd/display: Add fast path for cursor plane updates
> >
> > we don't have any driver anymore where we have userspace expecting
> > solid legacy cursor support _and_ they are using the atomic helpers in
> > their fully glory. So we can retire this.
> >
> > References: https://bugzilla.kernel.org/show_bug.cgi?id=199425
> > Cc: mikita.lip...@amd.com
> > Cc: Michel Dänzer
> > Cc: harry.wentl...@amd.com
> > Signed-off-by: Daniel Vetter
>
> I'm fine with the idea but it looks like we need modification to amdgpu to
> not break anything:
>
> if (state->legacy_cursor_update) {
> /* ... */
> state->async_update =
> !drm_atomic_helper_async_check(dev, state);
>
>
> We only check async update for legacy_cursor_updates here which won't cover
> the atomic path. I think it's safe to drop the check here but that should
> probably be done before or as part of this series.
This part is fine, you're essentially duplicating what the helpers are
doing too. I'm not sure whether we should lift this to core atomic
semantics or something else, but should be all ok as-is. Might still be
good to test this in case something isn't 100% complete and amdgpu atomic
commit still relies on legacy_cursor_update semantics somewhere.
But after this patch your atomic code and atomic helpers check/commit
functions match (I think), so we /should/ be good.
Cheers, Daniel
>
> Regards,
> Nicholas Kazlauskas
>
> > ---
> > drivers/gpu/drm/drm_atomic_helper.c | 13 -
> > 1 file changed, 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > b/drivers/gpu/drm/drm_atomic_helper.c
> > index a7bcb4b4586c..549a31e6042c 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -1481,13 +1481,6 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device
> > *dev,
> > int i, ret;
> > unsigned crtc_mask = 0;
> > -/*
> > - * Legacy cursor ioctls are completely unsynced, and userspace
> > - * relies on that (by doing tons of cursor updates).
> > - */
> > - if (old_state->legacy_cursor_update)
> > - return;
> > -
> > for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > if (!new_crtc_state->active)
> > continue;
> > @@ -2106,12 +2099,6 @@ int drm_atomic_helper_setup_commit(struct
> > drm_atomic_state *state,
> > continue;
> > }
> > - /* Legacy cursor updates are fully unsynced. */
> > - if (state->legacy_cursor_update) {
> > - complete_all(>flip_done);
> > - continue;
> > - }
> > -
> > if (!new_crtc_state->event) {
> > commit->event = kzalloc(sizeof(*commit->event),
> > GFP_KERNEL);
> >
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: wait PSR state back to idle when turn PSR off
On Thu, Oct. 22, 2020, 3:24 a.m, Lee Shawn C wrote:
>On Wed, Oct. 21, 2020, 5:13 p.m, Souza, Jose wrote:
>>On Wed, 2020-10-21 at 22:24 +0800, Lee Shawn C wrote:
>>> Driver should refer to commit 'b2fc2252ce41 ("drm/i915/psr:
>>> Always wait for idle state when disabling PSR")' to wait for idle
>>> state when turn PSR off. But it did not follow previous method.
>>> Driver just call intel_psr_exit() in
>>> intel_psr_invalidate() and psr_force_hw_tracking_exit().
>>> Then leave the function right away.
>>>
>>> After PSR disabled, we found some user space applications would
>>> enabled PSR again immediately. That caused particular TCON to get
>>> into incorrect state machine and can't recognize video data from
>>> source properly.
>>
>>How? I don't see how this is possible this change is only adding delay
>>between userspace calls.
>>
>>Take a look at intel_psr_work(), PSR will only be enabled again when idle.
>>
>
>Thanks for clarification! Per our finding, the problem was found on specific
>TCON support PSR2.
>Below is our observation on customer board.
>
>After psr exit called at intel_psr_invalidate(), PSR2_STATUS (0x6f940, bit
>31:28) report 0x3 sometimes.
>Which means source PSR state still active. Then we check sink's DPCD 2008h
>before re-enable PSR2 in intel_psr_work().
>DPCD 2008h shows 0x2 (PSR active - display from RFB) sometimes.
>
>Seems problem occurred when source re-enable PSR2 but sink still at PSR2
>active state.
>TCON is not able to recognize video data. And corrupt display shows on eDP
>panel.
>Abnormal display is recoverable after modeset.
>
>Looks like my change to wait PSR2 state idle adding more delay here to give
>more times for TCON back to normal state.
>Read DPCD 2008h to confirm sink's PSR2 status before re-enable PSR2 in
>intel_psr_work().
>It will be 0x4 (Sink device Transition to PSR inactive - capture and display;
>timing re-sync) always.
>Then we can't replicate corrupt display issue anymore.
>
>In my opinion, confirm DPCD 2008h moved to 0x4 before re-enable PSR2 may help
>this customer issue.
>What do you think?
>
>Best regards,
>Shawn
>
Per previous comment, it is a little complicated from source to align sink's
PSR state.
Even source PSR2 state already idle. But sink PSR2 state still at "active"
sometimes.
Here is another idea. How about to disable/re-enable sink's PSR2 just like
driver did for source as well?
Sink would back to normal display mode after PSR disabled. Then we can enable
PSR again in intel_psr_work()
before driver try to turn source PSR on.
Best regards,
Shawn
>>>
>>> Add this change to wait PSR idle state in intel_psr_invalidate() and
>>> psr_force_hw_tracking_exit(). This symptom is not able to replicate
>>> anymore.
>>>
>>> Fixes: b2fc2252ce41 (drm/i915/psr: Always wait for idle state when
>>> disabling PSR).
>>>
>>> Cc: Manasi Navare
>>> Cc: Jani Nikula
>>> Cc: Ville Syrjala
>>> Cc: José Roberto de Souza
>>> Cc: Cooper Chiou
>>> Cc: Khaled Almahallawy
>>> Signed-off-by: Lee Shawn C
>>> ---
>>> drivers/gpu/drm/i915/display/intel_psr.c | 43
>>> ++--
>>> 1 file changed, 26 insertions(+), 17 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index a591a475f148..83b642a5567e 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -1036,6 +1036,25 @@ void intel_psr_enable(struct intel_dp
>>> *intel_dp, mutex_unlock(_priv->psr.lock);
>>> }
>>>
>>>
>>>
>>>
>>> +static void intel_psr_wait_idle(struct drm_i915_private *dev_priv) {
>>> +i915_reg_t psr_status;
>>> +u32 psr_status_mask;
>>> +
>>> +if (dev_priv->psr.psr2_enabled) {
>>> +psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
>>> +psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; } else { psr_status =
>>> +EDP_PSR_STATUS(dev_priv->psr.transcoder);
>>> +psr_status_mask = EDP_PSR_STATUS_STATE_MASK; }
>>> +
>>> +/* Wait till PSR is idle */
>>> +if (intel_de_wait_for_clear(dev_priv, psr_status,
>>> +psr_status_mask, 2000))
>>> +drm_err(_priv->drm, "Timed out waiting PSR idle state\n"); }
>>> +
>>> static void intel_psr_exit(struct drm_i915_private *dev_priv) {
>>> u32 val;
>>> @@ -1076,8 +1095,6 @@ static void intel_psr_exit(struct
>>> drm_i915_private *dev_priv) static void
>>> intel_psr_disable_locked(struct intel_dp *intel_dp) { struct
>>> drm_i915_private *dev_priv = dp_to_i915(intel_dp); -i915_reg_t
>>> psr_status;
>>> -u32 psr_status_mask;
>>>
>>>
>>>
>>>
>>> lockdep_assert_held(_priv->psr.lock);
>>>
>>>
>>>
>>>
>>> @@ -1088,19 +1105,7 @@ static void intel_psr_disable_locked(struct intel_dp
>>> *intel_dp)
>>> dev_priv->psr.psr2_enabled ? "2" : "1");
>>>
>>>
>>>
>>>
>>> intel_psr_exit(dev_priv);
>>> -
>>> -if (dev_priv->psr.psr2_enabled) {
>>> -psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
>>> -psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; -} else {
Re: [Intel-gfx] [PATCH 1/3] drm/atomic-helpers: remove legacy_cursor_update hacks
On 2020-10-21 12:32 p.m., Daniel Vetter wrote:
The stuff never really worked, and leads to lots of fun because it
out-of-order frees atomic states. Which upsets KASAN, among other
things.
For async updates we now have a more solid solution with the
->atomic_async_check and ->atomic_async_commit hooks. Support for that
for msm and vc4 landed. nouveau and i915 have their own commit
routines, doing something similar.
For everyone else it's probably better to remove the use-after-free
bug, and encourage folks to use the async support instead. The
affected drivers which register a legacy cursor plane and don't either
use the new async stuff or their own commit routine are: amdgpu,
atmel, mediatek, qxl, rockchip, sti, sun4i, tegra, virtio, and vmwgfx.
Inspired by an amdgpu bug report.
v2: Drop RFC, I think with amdgpu converted over to use
atomic_async_check/commit done in
commit 674e78acae0dfb4beb56132e41cbae5b60f7d662
Author: Nicholas Kazlauskas
Date: Wed Dec 5 14:59:07 2018 -0500
drm/amd/display: Add fast path for cursor plane updates
we don't have any driver anymore where we have userspace expecting
solid legacy cursor support _and_ they are using the atomic helpers in
their fully glory. So we can retire this.
References: https://bugzilla.kernel.org/show_bug.cgi?id=199425
Cc: mikita.lip...@amd.com
Cc: Michel Dänzer
Cc: harry.wentl...@amd.com
Signed-off-by: Daniel Vetter
I'm fine with the idea but it looks like we need modification to amdgpu
to not break anything:
if (state->legacy_cursor_update) {
/* ... */
state->async_update =
!drm_atomic_helper_async_check(dev, state);
We only check async update for legacy_cursor_updates here which won't
cover the atomic path. I think it's safe to drop the check here but that
should probably be done before or as part of this series.
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/drm_atomic_helper.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index a7bcb4b4586c..549a31e6042c 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1481,13 +1481,6 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device
*dev,
int i, ret;
unsigned crtc_mask = 0;
- /*
- * Legacy cursor ioctls are completely unsynced, and userspace
- * relies on that (by doing tons of cursor updates).
- */
- if (old_state->legacy_cursor_update)
- return;
-
for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!new_crtc_state->active)
continue;
@@ -2106,12 +2099,6 @@ int drm_atomic_helper_setup_commit(struct
drm_atomic_state *state,
continue;
}
- /* Legacy cursor updates are fully unsynced. */
- if (state->legacy_cursor_update) {
- complete_all(>flip_done);
- continue;
- }
-
if (!new_crtc_state->event) {
commit->event = kzalloc(sizeof(*commit->event),
GFP_KERNEL);
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Re: [Intel-gfx] [PATCH 2/3] drm/vc4: Drop legacy_cursor_update override
On Wed, Oct 21, 2020 at 06:32:41PM +0200, Daniel Vetter wrote: > With the removal of helper support it doesn't do anything anymore. > Also, we already have async plane update code in vc4. > > Signed-off-by: Daniel Vetter > Cc: Eric Anholt > Cc: Maxime Ripard Acked-by: Maxime Ripard Maxime signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications
On Thu, 2020-10-22 at 12:43 +, Mun, Gwan-gyeong wrote:
> 1. While testing the problematic scenario, it has not always shown
> the
> IOMMU DAMR related below errors on the drm-tip.
>(sometimes the error messages raised, but some times it has not
> happened on the same kernel and scenario.
>
> DMAR: DRHD: handling fault status reg 2
> DMAR: [DMA Read] Request device [00:02.0] PASID 0x fault addr
> 0xfc001000 [fault reason 06] PTE Read access is not set
> DMAR: DRHD: handling fault status reg 3
> DMAR: [DMA Read] Request device [00:02.0] PASID 0x fault addr
> 0xfc00 [fault reason 06] PTE Read access is not set
>
> 2 After applying this patch the screen glitch issues have been
> remarkably alleviated.
> - Eventhough there infrequently showed the screen glitch issues.
> - But I agree to apply this patch as a workaround by adding the
> explanation below.
>
> 3. The dc state and PSR enable/disable scenarios has been changed by
> this patch.
>
> (1)Before applying patch
> enable psr
> -> (front buffer updates)
> -> intel_psr_flush
> ^ -> psr_force_hw_tracking_exit()
> | : write CURSURFLIVE
> | |
> | (front buffer updates) |
> +--+
>
> PSR enabled -- -->
>( DC state controlled by DMC firmware)
>
>
> (2) After applying patch
> enable psr
>^ -> (front buffer updates)
>| -> intel_psr_flush
>| -> psr_force_hw_tracking_exit()
>| : call intel_psr_exit()
>| -> disable psr
>| |
>| |
>+-+
>
> PSR enabled ---> PSR disabled
> ^ |
> | |
> +--+
>( DC state controlled by DMC firmware)
>
> the repeating of enabling and disabling of PSR by the rapid screen
> updates prevents entering of low power dc states.
> Infereing from this scenario, it indirectly touches DC state and it
> alleviates the issue.
>
with the previous comments,
Tested-by: Gwan-gyeong Mun
Reviewed-by: Gwan-gyeong Mun
>
> On Fri, 2020-10-02 at 16:16 -0700, José Roberto de Souza wrote:
> > Writes to CURSURFLIVE in TGL are causing IOMMU errors and visual
> > glitches that are often reproduced when executing CPU intensive
> > workloads while a eDP 4K panel is attached.
> >
> > Manually exiting PSR causes the frontbuffer to be updated without
> > glitches and the IOMMU errors are also gone but this comes at the
> > cost
> > of less time with PSR active.
> >
> > So using this workaround until this issue is root caused and a
> > better
> > fix is found.
> >
> > The current code is already ready to enable PSR after this exit if
> > there is not other frontbuffer modifications.
> >
> > Adding a new if block in psr_force_hw_tracking_exit() instead of
> > reuse
> > the else/gen8- block because the plan is to revert this workaround
> > as soon as a better solution is found.
> >
> > Cc: Gwan-gyeong Mun
> > Cc: Ville Syrjälä
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 16 +++-
> > 1 file changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 8a9d0bdde1bf..8630121dbbbe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1152,7 +1152,21 @@ void intel_psr_disable(struct intel_dp
> > *intel_dp,
> >
> > static void psr_force_hw_tracking_exit(struct drm_i915_private
> > *dev_priv)
> > {
> > - if (INTEL_GEN(dev_priv) >= 9)
> > + if (IS_TIGERLAKE(dev_priv))
> > + /*
> > +* Writes to CURSURFLIVE in TGL are causing IOMMU
> > errors and
> > +* visual glitches that are often reproduced when
> > executing
> > +* CPU intensive workloads while a eDP 4K panel is
> > attached.
> > +*
> > +* Manually exiting PSR causes the frontbuffer to be
> > updated
> > +* without glitches and the IOMMU errors are also gone
> > but
> > +* this comes at the cost of less time with PSR active.
> > +*
> > +* So using this workaround until this issue is root
> > caused
> > +* and a better fix is found.
> > +*/
> > + intel_psr_exit(dev_priv);
> > + else if (INTEL_GEN(dev_priv) >= 9)
> > /*
> > * Display WA #0884: skl+
> > * This documented WA for bxt can be safely applied
>
Re: [Intel-gfx] [PATCH] drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications
1. While testing the problematic scenario, it has not always shown the
IOMMU DAMR related below errors on the drm-tip.
(sometimes the error messages raised, but some times it has not
happened on the same kernel and scenario.
DMAR: DRHD: handling fault status reg 2
DMAR: [DMA Read] Request device [00:02.0] PASID 0x fault addr
0xfc001000 [fault reason 06] PTE Read access is not set
DMAR: DRHD: handling fault status reg 3
DMAR: [DMA Read] Request device [00:02.0] PASID 0x fault addr
0xfc00 [fault reason 06] PTE Read access is not set
2 After applying this patch the screen glitch issues have been
remarkably alleviated.
- Eventhough there infrequently showed the screen glitch issues.
- But I agree to apply this patch as a workaround by adding the
explanation below.
3. The dc state and PSR enable/disable scenarios has been changed by
this patch.
(1)Before applying patch
enable psr
-> (front buffer updates)
-> intel_psr_flush
^ -> psr_force_hw_tracking_exit()
| : write CURSURFLIVE
| |
| (front buffer updates) |
+--+
PSR enabled -- -->
( DC state controlled by DMC firmware)
(2) After applying patch
enable psr
^ -> (front buffer updates)
| -> intel_psr_flush
| -> psr_force_hw_tracking_exit()
| : call intel_psr_exit()
| -> disable psr
| |
| |
+-+
PSR enabled ---> PSR disabled
^ |
| |
+--+
( DC state controlled by DMC firmware)
the repeating of enabling and disabling of PSR by the rapid screen
updates prevents entering of low power dc states.
Infereing from this scenario, it indirectly touches DC state and it
alleviates the issue.
On Fri, 2020-10-02 at 16:16 -0700, José Roberto de Souza wrote:
> Writes to CURSURFLIVE in TGL are causing IOMMU errors and visual
> glitches that are often reproduced when executing CPU intensive
> workloads while a eDP 4K panel is attached.
>
> Manually exiting PSR causes the frontbuffer to be updated without
> glitches and the IOMMU errors are also gone but this comes at the
> cost
> of less time with PSR active.
>
> So using this workaround until this issue is root caused and a better
> fix is found.
>
> The current code is already ready to enable PSR after this exit if
> there is not other frontbuffer modifications.
>
> Adding a new if block in psr_force_hw_tracking_exit() instead of
> reuse
> the else/gen8- block because the plan is to revert this workaround
> as soon as a better solution is found.
>
> Cc: Gwan-gyeong Mun
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8a9d0bdde1bf..8630121dbbbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1152,7 +1152,21 @@ void intel_psr_disable(struct intel_dp
> *intel_dp,
>
> static void psr_force_hw_tracking_exit(struct drm_i915_private
> *dev_priv)
> {
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (IS_TIGERLAKE(dev_priv))
> + /*
> + * Writes to CURSURFLIVE in TGL are causing IOMMU
> errors and
> + * visual glitches that are often reproduced when
> executing
> + * CPU intensive workloads while a eDP 4K panel is
> attached.
> + *
> + * Manually exiting PSR causes the frontbuffer to be
> updated
> + * without glitches and the IOMMU errors are also gone
> but
> + * this comes at the cost of less time with PSR active.
> + *
> + * So using this workaround until this issue is root
> caused
> + * and a better fix is found.
> + */
> + intel_psr_exit(dev_priv);
> + else if (INTEL_GEN(dev_priv) >= 9)
> /*
>* Display WA #0884: skl+
>* This documented WA for bxt can be safely applied
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reset the interrupt mask on disabling interrupts (rev2)
== Series Details ==
Series: drm/i915: Reset the interrupt mask on disabling interrupts (rev2)
URL : https://patchwork.freedesktop.org/series/82945/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9182 -> Patchwork_18765
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/index.html
Known issues
Here are the changes found in Patchwork_18765 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] ([i915#2203])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
Possible fixes
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
Participating hosts (45 -> 39)
--
Additional (1): fi-apl-guc
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9182 -> Patchwork_18765
CI-20190529: 20190529
CI_DRM_9182: 5d76506480cdfef424b52f63a0d21093b2c78dc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18765: 57c1554fa7c3bdc6373a3e10f97d84cc1cce477e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
57c1554fa7c3 drm/i915: Reset the interrupt mask on disabling interrupts
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18765/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Reset the interrupt mask on disabling interrupts (rev2)
== Series Details == Series: drm/i915: Reset the interrupt mask on disabling interrupts (rev2) URL : https://patchwork.freedesktop.org/series/82945/ State : warning == Summary == $ dim checkpatch origin/drm-tip 57c1554fa7c3 drm/i915: Reset the interrupt mask on disabling interrupts -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: <4>[ 101.816730] i915 :00:02.0: drm_WARN_ON(!intel_irqs_enabled(dev_priv)) total: 0 errors, 1 warnings, 0 checks, 48 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for HDCP 2.2 DP MST Support (rev5)
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev5)
URL : https://patchwork.freedesktop.org/series/81538/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9182 -> Patchwork_18764
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/index.html
Known issues
Here are the changes found in Patchwork_18764 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9182/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
Participating hosts (45 -> 39)
--
Additional (1): fi-apl-guc
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9182 -> Patchwork_18764
CI-20190529: 20190529
CI_DRM_9182: 5d76506480cdfef424b52f63a0d21093b2c78dc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18764: 3f09be950b9e6adb84ba3105116cf84549c743dc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3f09be950b9e drm/i915/hdcp: Enable HDCP 2.2 MST support
7286d357f37e drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
844bace9a8bb drm/i915/hdcp: Add HDCP 2.2 stream register
fe282dce943b drm/i915/hdcp: Pass connector to check_2_2_link
14aea2bd217e drm/i915/hdcp: MST streams support in hdcp port_data
c62cbbaece50 drm/hdcp: Max MST content streams
587b272daea6 misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
5524d56ad1d9 drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
d1d2ae46766e drm/i915/hdcp: Pass dig_port to intel_hdcp_init
c563af8ef24a drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
a3c2628d301d drm/i915/hdcp: HDCP stream encryption support
cd7dfdf4d705 drm/i915/hdcp: Move HDCP enc status timeout to header
ce083eb6afcb drm/i915/hdcp: DP MST transcoder for link and stream
e6ea1e5d0a69 drm/i915/hotplug: Handle CP_IRQ for DP-MST
ed3fec051c2e drm/i915/hdcp: Get conn while content_type changed
3c203819df03 drm/i915/hdcp: Update CP property in update_pipe
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18764/index.html
___
Intel-gfx mailing list
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[Intel-gfx] [PATCH] drm/i915: Reset the interrupt mask on disabling interrupts
As we disable the interrupt during suspend, also reset the irq_mask to
short-circuit subsystems that later try to turn off their interrupt
source.
<4>[ 101.816730] i915 :00:02.0: drm_WARN_ON(!intel_irqs_enabled(dev_priv))
<4>[ 101.816853] WARNING: CPU: 3 PID: 4241 at
drivers/gpu/drm/i915/i915_irq.c:343 ilk_update_display_irq+0xb3/0x130 [i915]
v2: Reset irq_mask for i8xx_irq_reset as well, and split patch to focus
on only i915->irq_mask
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 09221ca1ffb2..53e67c796d09 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -337,17 +337,14 @@ void ilk_update_display_irq(struct drm_i915_private
*dev_priv,
u32 new_val;
lockdep_assert_held(_priv->irq_lock);
-
drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
- if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
- return;
-
new_val = dev_priv->irq_mask;
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != dev_priv->irq_mask) {
+ if (new_val != dev_priv->irq_mask &&
+ !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
dev_priv->irq_mask = new_val;
I915_WRITE(DEIMR, dev_priv->irq_mask);
POSTING_READ(DEIMR);
@@ -2951,6 +2948,8 @@ static void ilk_irq_reset(struct drm_i915_private
*dev_priv)
struct intel_uncore *uncore = _priv->uncore;
GEN3_IRQ_RESET(uncore, DE);
+ dev_priv->irq_mask = ~0u;
+
if (IS_GEN(dev_priv, 7))
intel_uncore_write(uncore, GEN7_ERR_INT, 0x);
@@ -3695,6 +3694,7 @@ static void i8xx_irq_reset(struct drm_i915_private
*dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
GEN2_IRQ_RESET(uncore);
+ dev_priv->irq_mask = ~0u;
}
static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3864,6 +3864,7 @@ static void i915_irq_reset(struct drm_i915_private
*dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN2_);
+ dev_priv->irq_mask = ~0u;
}
static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3970,6 +3971,7 @@ static void i965_irq_reset(struct drm_i915_private
*dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN2_);
+ dev_priv->irq_mask = ~0u;
}
static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.20.1
___
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Re: [Intel-gfx] [PATCH] drm/i915: Reset the interrupt mask on disabling interrupts
Quoting Ville Syrjälä (2020-10-22 12:32:52)
> On Thu, Oct 22, 2020 at 08:16:37AM +0100, Chris Wilson wrote:
> > As we disable the interrupt during suspend, also reset the irq_mask to
> > short-circuit subsystems that later try to turn off their interrupt
> > source.
> >
> > <4>[ 101.816730] i915 :00:02.0:
> > drm_WARN_ON(!intel_irqs_enabled(dev_priv))
> > <4>[ 101.816853] WARNING: CPU: 3 PID: 4241 at
> > drivers/gpu/drm/i915/i915_irq.c:343 ilk_update_display_irq+0xb3/0x130 [i915]
>
> Doh. Lack of irq symmetry in suspend vs. resume strikes again :(
>
> >
> > Signed-off-by: Chris Wilson
> > Cc: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 25 ++---
> > 1 file changed, 10 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 09221ca1ffb2..cbb71fc73313 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -337,17 +337,14 @@ void ilk_update_display_irq(struct drm_i915_private
> > *dev_priv,
> > u32 new_val;
> >
> > lockdep_assert_held(_priv->irq_lock);
> > -
> > drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
> >
> > - if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
> > - return;
> > -
> > new_val = dev_priv->irq_mask;
> > new_val &= ~interrupt_mask;
> > new_val |= (~enabled_irq_mask & interrupt_mask);
> >
> > - if (new_val != dev_priv->irq_mask) {
> > + if (new_val != dev_priv->irq_mask &&
> > + !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
> > dev_priv->irq_mask = new_val;
> > I915_WRITE(DEIMR, dev_priv->irq_mask);
> > POSTING_READ(DEIMR);
> > @@ -368,19 +365,16 @@ static void bdw_update_port_irq(struct
> > drm_i915_private *dev_priv,
> > u32 old_val;
> >
> > lockdep_assert_held(_priv->irq_lock);
> > -
> > drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
> >
> > - if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
> > - return;
> > -
> > old_val = I915_READ(GEN8_DE_PORT_IMR);
> >
> > new_val = old_val;
> > new_val &= ~interrupt_mask;
> > new_val |= (~enabled_irq_mask & interrupt_mask);
> >
> > - if (new_val != old_val) {
> > + if (new_val != old_val &&
> > + !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
> > I915_WRITE(GEN8_DE_PORT_IMR, new_val);
> > POSTING_READ(GEN8_DE_PORT_IMR);
> > }
> > @@ -401,17 +395,14 @@ void bdw_update_pipe_irq(struct drm_i915_private
> > *dev_priv,
> > u32 new_val;
> >
> > lockdep_assert_held(_priv->irq_lock);
> > -
> > drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
> >
> > - if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
> > - return;
> > -
> > new_val = dev_priv->de_irq_mask[pipe];
> > new_val &= ~interrupt_mask;
> > new_val |= (~enabled_irq_mask & interrupt_mask);
> >
> > - if (new_val != dev_priv->de_irq_mask[pipe]) {
> > + if (new_val != dev_priv->de_irq_mask[pipe] &&
> > + !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
> > dev_priv->de_irq_mask[pipe] = new_val;
> > I915_WRITE(GEN8_DE_PIPE_IMR(pipe),
> > dev_priv->de_irq_mask[pipe]);
> > POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
>
> Not resetting de_irq_mask[] anywhere? Hmm. we seem to be lacking a
> gen8_de_irq_reset()...
Maybe I was being a bit optimistic, and erred on the side of sticking to
the simple resets.
> > @@ -2951,6 +2942,8 @@ static void ilk_irq_reset(struct drm_i915_private
> > *dev_priv)
> > struct intel_uncore *uncore = _priv->uncore;
> >
> > GEN3_IRQ_RESET(uncore, DE);
> > + dev_priv->irq_mask = ~0u;
> > +
> > if (IS_GEN(dev_priv, 7))
> > intel_uncore_write(uncore, GEN7_ERR_INT, 0x);
> >
> > @@ -3864,6 +3857,7 @@ static void i915_irq_reset(struct drm_i915_private
> > *dev_priv)
> > i9xx_pipestat_irq_reset(dev_priv);
> >
> > GEN3_IRQ_RESET(uncore, GEN2_);
> > + dev_priv->irq_mask = ~0u;
> > }
> >
> > static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
> > @@ -3970,6 +3964,7 @@ static void i965_irq_reset(struct drm_i915_private
> > *dev_priv)
> > i9xx_pipestat_irq_reset(dev_priv);
> >
> > GEN3_IRQ_RESET(uncore, GEN2_);
> > + dev_priv->irq_mask = ~0u;
> > }
>
> Missing gen2?
Hmm, I saw GEN2 and assumed it was covered. i8xx_irq_reset() looks
straightforward.
I guess split this patch to only think about dev_priv->irq_mask...
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Reset the interrupt mask on disabling interrupts
On Thu, Oct 22, 2020 at 08:16:37AM +0100, Chris Wilson wrote:
> As we disable the interrupt during suspend, also reset the irq_mask to
> short-circuit subsystems that later try to turn off their interrupt
> source.
>
> <4>[ 101.816730] i915 :00:02.0:
> drm_WARN_ON(!intel_irqs_enabled(dev_priv))
> <4>[ 101.816853] WARNING: CPU: 3 PID: 4241 at
> drivers/gpu/drm/i915/i915_irq.c:343 ilk_update_display_irq+0xb3/0x130 [i915]
Doh. Lack of irq symmetry in suspend vs. resume strikes again :(
>
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.c | 25 ++---
> 1 file changed, 10 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 09221ca1ffb2..cbb71fc73313 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -337,17 +337,14 @@ void ilk_update_display_irq(struct drm_i915_private
> *dev_priv,
> u32 new_val;
>
> lockdep_assert_held(_priv->irq_lock);
> -
> drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
>
> - if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
> - return;
> -
> new_val = dev_priv->irq_mask;
> new_val &= ~interrupt_mask;
> new_val |= (~enabled_irq_mask & interrupt_mask);
>
> - if (new_val != dev_priv->irq_mask) {
> + if (new_val != dev_priv->irq_mask &&
> + !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
> dev_priv->irq_mask = new_val;
> I915_WRITE(DEIMR, dev_priv->irq_mask);
> POSTING_READ(DEIMR);
> @@ -368,19 +365,16 @@ static void bdw_update_port_irq(struct drm_i915_private
> *dev_priv,
> u32 old_val;
>
> lockdep_assert_held(_priv->irq_lock);
> -
> drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
>
> - if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
> - return;
> -
> old_val = I915_READ(GEN8_DE_PORT_IMR);
>
> new_val = old_val;
> new_val &= ~interrupt_mask;
> new_val |= (~enabled_irq_mask & interrupt_mask);
>
> - if (new_val != old_val) {
> + if (new_val != old_val &&
> + !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
> I915_WRITE(GEN8_DE_PORT_IMR, new_val);
> POSTING_READ(GEN8_DE_PORT_IMR);
> }
> @@ -401,17 +395,14 @@ void bdw_update_pipe_irq(struct drm_i915_private
> *dev_priv,
> u32 new_val;
>
> lockdep_assert_held(_priv->irq_lock);
> -
> drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
>
> - if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
> - return;
> -
> new_val = dev_priv->de_irq_mask[pipe];
> new_val &= ~interrupt_mask;
> new_val |= (~enabled_irq_mask & interrupt_mask);
>
> - if (new_val != dev_priv->de_irq_mask[pipe]) {
> + if (new_val != dev_priv->de_irq_mask[pipe] &&
> + !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
> dev_priv->de_irq_mask[pipe] = new_val;
> I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
> POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
Not resetting de_irq_mask[] anywhere? Hmm. we seem to be lacking a
gen8_de_irq_reset()...
> @@ -2951,6 +2942,8 @@ static void ilk_irq_reset(struct drm_i915_private
> *dev_priv)
> struct intel_uncore *uncore = _priv->uncore;
>
> GEN3_IRQ_RESET(uncore, DE);
> + dev_priv->irq_mask = ~0u;
> +
> if (IS_GEN(dev_priv, 7))
> intel_uncore_write(uncore, GEN7_ERR_INT, 0x);
>
> @@ -3864,6 +3857,7 @@ static void i915_irq_reset(struct drm_i915_private
> *dev_priv)
> i9xx_pipestat_irq_reset(dev_priv);
>
> GEN3_IRQ_RESET(uncore, GEN2_);
> + dev_priv->irq_mask = ~0u;
> }
>
> static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -3970,6 +3964,7 @@ static void i965_irq_reset(struct drm_i915_private
> *dev_priv)
> i9xx_pipestat_irq_reset(dev_priv);
>
> GEN3_IRQ_RESET(uncore, GEN2_);
> + dev_priv->irq_mask = ~0u;
> }
Missing gen2?
>
> static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
> --
> 2.20.1
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 DP MST Support (rev5)
== Series Details == Series: HDCP 2.2 DP MST Support (rev5) URL : https://patchwork.freedesktop.org/series/81538/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 DP MST Support (rev5)
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev5)
URL : https://patchwork.freedesktop.org/series/81538/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3c203819df03 drm/i915/hdcp: Update CP property in update_pipe
ed3fec051c2e drm/i915/hdcp: Get conn while content_type changed
e6ea1e5d0a69 drm/i915/hotplug: Handle CP_IRQ for DP-MST
ce083eb6afcb drm/i915/hdcp: DP MST transcoder for link and stream
cd7dfdf4d705 drm/i915/hdcp: Move HDCP enc status timeout to header
-:13: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 7e90e8d0c0ea ("drm/i915:
Increase timeout for Encrypt status change")'
#13:
Related: 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
total: 1 errors, 0 warnings, 0 checks, 47 lines checked
a3c2628d301d drm/i915/hdcp: HDCP stream encryption support
c563af8ef24a drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
d1d2ae46766e drm/i915/hdcp: Pass dig_port to intel_hdcp_init
5524d56ad1d9 drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
587b272daea6 misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
c62cbbaece50 drm/hdcp: Max MST content streams
14aea2bd217e drm/i915/hdcp: MST streams support in hdcp port_data
fe282dce943b drm/i915/hdcp: Pass connector to check_2_2_link
844bace9a8bb drm/i915/hdcp: Add HDCP 2.2 stream register
7286d357f37e drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
3f09be950b9e drm/i915/hdcp: Enable HDCP 2.2 MST support
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Set drm_crtc_state.active=false for all added disconnected CRTCs sharing MST stream.
On Wed, Oct 21, 2020 at 05:25:40PM -0400, Lyude Paul wrote:
> On Wed, 2020-10-21 at 16:26 +0300, Ville Syrjälä wrote:
> > On Tue, Oct 20, 2020 at 11:25:53PM +, Souza, Jose wrote:
> > > On Tue, 2020-10-20 at 15:41 +0300, Ville Syrjälä wrote:
> > > > On Tue, Oct 20, 2020 at 12:45:55AM -0700, Khaled Almahallawy wrote:
> > > > > This patch avoids failing atomic commits sent by user space by making
> > > > > sure CRTC/Connector added to drm_atomic_state by the driver are in
> > > > > valid
> > > > > state.
> > > > >
> > > > > When disconnecting MST hub with two or more connected displays. The
> > > > > user
> > > > > space sends IOCTL for each MST pipe to disable.
> > > > > drm_atomic_state object sent from user space contains only the state
> > > > > of
> > > > > the crtc/pipe intended to disable.
> > > > > In TGL, intel_dp_mst_atomic_master_trans_check will add all other CRTC
> > > > > and connectors that share the MST stream to drm_atomic_state:
> > > > >
> > > > > drm_atomic_commit
> > > > >    drm_atomic_helper_check_modeset
> > > > >        update_connector_routing
> > > > >        intel_dp_mst_atomic_check = funcs-
> > > > > >atomic_check(connector, state);
> > > > >        intel_dp_mst_atomic_master_trans_chec
> > > > > k
> > > > > intel_atomic_get_digital_connector_state
> > > > > drm_atomic_get_connector_state <-- Add all
> > > > > Connectors
> > > > > drm_atomic_get_crtc_state <-- Add all CRTCs
> > > > >        update_connector_routing <-- Check added
> > > > > Connector/CRTCs - Will fail
> > > > >
> > > > > However the added crtc/connector pair will be in invalid state
> > > > > (enabled
> > > > > state for a removed connector)
> > > > > triggering this condition in
> > > > > drm_atomic_helper.c/update_connector_routing:
> > > > >
> > > > > if (!state->duplicated &&
> > > > > drm_connector_is_unregistered(connector) &&
> > > > > crtc_state->active) {
> > > > > DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] is not
> > > > > registered\n",
> > > > >connector->base.id, connector->name);
> > > > > return -EINVAL;
> > > > > }
> > > >
> > > > Yeah, I think that "reject modeset on unregistered connectors" idea is
> > > > a bit broken given how the uapi has worked in the past. Cc:ing danvet
> > > > and lyude who IIRC were involved with that.
> > > >
> > > > Hmm. Maybe we could add the other stuff to the state only after the
> > > > connector .atomic_check() stuff has been done? I don't quite remember
> > > > why we decided to do it here. José do you recall the details?
> > >
> > > Because the connector check function runs twice in
> > > drm_atomic_helper_check_modeset(), in the first iteration it will add all
> > > connectors that share the
> > > same MST stream to state, the second one will make sure all other checks
> > > passed in all connectors of the MST stream.
> > >
> > > To me looks like the Chrome userspace is not doing the right thing, it is
> > > sending asynchronous atomic commits with conflicting state between each
> > > commit.
> > > If it had a pool that dispatch one atomic state at time waiting for
> > > completion before dispatch the next one it would not be a issue.
> >
> > Yeah, with atomic userspace could avoid this potentially. Though it
> > may be racy depending on whether it has noticed all the MST connectors
> > disappearing yet or not. Either way it's still an issue for legacy
> > uapi.
>
> Sigh-I had hoped that we would have hooked this up such that we'd avoid this
> (as
> I've already had to fix some issues this caused with legacy modesetting) but I
> guess not. Have you guys considered trying to use the connector epochs
> whenever
> you receive a hotplug event to differentiate between removed ('stale')
> connectors and other connectors? tbh, if you can't find a connector with the
> same mst path and epoch you last had as your stale connector then it's safe to
> just assume it's gone.
>
> Also - I'm totally open to better ideas for handling this or making it more
> obvious when a connector has been removed, most of the reason for adding these
> checks was to try our best (as this is impossible to fully guarantee) to avoid
> situations where a host tried to enable an MST display that no longer existed
> and put the hardware into a weird state. At least if I remember correctly,
> it's
> been a while.
It's all racy anyway is it not? Because of that I'm pretty firmly in
the "just plow ahead blindly" camp.
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reset the interrupt mask on disabling interrupts
== Series Details ==
Series: drm/i915: Reset the interrupt mask on disabling interrupts
URL : https://patchwork.freedesktop.org/series/82945/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180_full -> Patchwork_18763_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18763_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@core_hotunplug@hotrebind}:
- shard-hsw: NOTRUN -> [WARN][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-hsw5/igt@core_hotunp...@hotrebind.html
Known issues
Here are the changes found in Patchwork_18763_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@hotrebind-lateclose:
- shard-snb: [PASS][2] -> [INCOMPLETE][3] ([i915#82])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-snb5/igt@core_hotunp...@hotrebind-lateclose.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-snb7/igt@core_hotunp...@hotrebind-lateclose.html
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2389]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk9/igt@gem_exec_reloc@basic-many-act...@vecs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-glk6/igt@gem_exec_reloc@basic-many-act...@vecs0.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-skl: [PASS][6] -> [TIMEOUT][7] ([i915#2424])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl10/igt@gem_userptr_bl...@sync-unmap-cycles.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-skl3/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-hsw: [PASS][8] -> [WARN][9] ([i915#1519])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-hsw7/igt@i915_pm_rc6_reside...@rc6-fence.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-hsw6/igt@i915_pm_rc6_reside...@rc6-fence.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][10] -> [INCOMPLETE][11] ([i915#155])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-kbl1/igt@i915_susp...@debugfs-reader.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-kbl4/igt@i915_susp...@debugfs-reader.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#1119])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk7/igt@kms_big...@y-tiled-16bpp-rotate-0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-glk1/igt@kms_big...@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#1982])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-kbl1/igt@kms_big...@y-tiled-8bpp-rotate-180.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-kbl4/igt@kms_big...@y-tiled-8bpp-rotate-180.html
* igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge:
- shard-skl: [PASS][16] -> [DMESG-WARN][17] ([i915#1982]) +6
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl6/igt@kms_cursor_edge_w...@pipe-b-256x256-right-edge.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-skl6/igt@kms_cursor_edge_w...@pipe-b-256x256-right-edge.html
* igt@kms_draw_crc@draw-method-xrgb-render-xtiled:
- shard-snb: [PASS][18] -> [FAIL][19] ([i915#54])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-snb5/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-snb4/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-tglb: [PASS][20] -> [DMESG-WARN][21] ([i915#1982])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-tglb5/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/shard-tglb7/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_plane@plane-panning-bottom-right-pipe-a-planes:
- shard-iclb: [PASS][22] -> [DMESG-WARN][23] ([i915#1982])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-iclb1/igt@kms_pl...@plane-panning-bottom-right-pipe-a-planes.html
[23]:
Re: [Intel-gfx] drm_modes: signed integer overflow
On Wed, Oct 21, 2020 at 08:13:43PM -0700, Randy Dunlap wrote: > Hi, > > With linux-next 20201021, when booting up, I am seeing this: > > [0.560896] UBSAN: signed-integer-overflow in > ../drivers/gpu/drm/drm_modes.c:765:20 > [0.560903] 2376000 * 1000 cannot be represented in type 'int' Dang. Didn't realize these new crazy >8k modes have dotclocks reaching almost 6 GHz, which would overflow even u32. I guess we'll switch to 64bit maths. Now I wonder how many other places can hit this overflow in practice... > [0.560909] CPU: 3 PID: 7 Comm: kworker/u16:0 Not tainted > 5.9.0-next-20201021 #2 > [0.560914] Hardware name: TOSHIBA PORTEGE R835/Portable PC, BIOS Version > 4.10 01/08/2013 > [0.560924] Workqueue: events_unbound async_run_entry_fn > > [0.560930] Call Trace: > [0.560938] dump_stack+0x5e/0x74 > [0.560943] ubsan_epilogue+0x9/0x45 > [0.560948] handle_overflow+0x8b/0x98 > [0.560953] ? set_track+0x3f/0xad > [0.560958] __ubsan_handle_mul_overflow+0xe/0x10 > [0.560964] drm_mode_vrefresh+0x4a/0xbc > [0.560970] initcall i915_init+0x0/0x6a returned 0 after 116076 usecs > [0.560974] calling cn_proc_init+0x0/0x36 @ 1 > [0.560978] cea_mode_alternate_clock+0x11/0x62 > [0.560985] drm_match_cea_mode+0xc7/0x1e7 > [0.560987] initcall cn_proc_init+0x0/0x36 returned 0 after 3 usecs > [0.560990] calling topology_sysfs_init+0x0/0x2d @ 1 > [0.561000] drm_mode_validate_ycbcr420+0xd/0x48 > [0.561005] drm_helper_probe_single_connector_modes+0x6db/0x7da > [0.561012] drm_client_modeset_probe+0x225/0x143f > [0.561018] ? bitmap_fold+0x8a/0x8a > [0.561023] ? update_cfs_rq_load_avg+0x192/0x1a2 > [0.561029] __drm_fb_helper_initial_config_and_unlock+0x3f/0x5b7 > [0.561035] ? get_sd_balance_interval+0x1c/0x40 > [0.561040] drm_fb_helper_initial_config+0x48/0x4f > [0.561047] intel_fbdev_initial_config+0x13/0x23 > [0.561052] async_run_entry_fn+0x89/0x15c > [0.561058] process_one_work+0x15c/0x1f3 > [0.561064] worker_thread+0x1ac/0x25d > [0.561069] ? process_scheduled_works+0x2e/0x2e > [0.561074] kthread+0x10e/0x116 > [0.561078] ? kthread_parkme+0x1c/0x1c > [0.561083] ret_from_fork+0x22/0x30 > [0.561087] > > > -- > ~Randy > Reported-by: Randy Dunlap > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during
submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9180_full -> Patchwork_18762_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_18762_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18762_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18762_full:
### IGT changes ###
Possible regressions
* igt@kms_flip@2x-dpms-vs-vblank-race@bc-vga1-hdmi-a1:
- shard-hsw: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-hsw7/igt@kms_flip@2x-dpms-vs-vblank-r...@bc-vga1-hdmi-a1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-hsw5/igt@kms_flip@2x-dpms-vs-vblank-r...@bc-vga1-hdmi-a1.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@core_hotunplug@hotrebind}:
- shard-hsw: NOTRUN -> [WARN][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-hsw5/igt@core_hotunp...@hotrebind.html
Known issues
Here are the changes found in Patchwork_18762_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2389]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk9/igt@gem_exec_reloc@basic-many-act...@vecs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-glk6/igt@gem_exec_reloc@basic-many-act...@vecs0.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][6] -> [INCOMPLETE][7] ([i915#155])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-kbl1/igt@i915_susp...@debugfs-reader.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-kbl6/igt@i915_susp...@debugfs-reader.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-kbl1/igt@kms_big...@y-tiled-8bpp-rotate-180.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-kbl6/igt@kms_big...@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#1635] /
[i915#1982])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-apl4/igt@kms_big...@yf-tiled-32bpp-rotate-270.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-apl3/igt@kms_big...@yf-tiled-32bpp-rotate-270.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
- shard-hsw: [PASS][12] -> [DMESG-WARN][13] ([IGT#6])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-hsw2/igt@kms_cursor_leg...@flip-vs-cursor-busy-crc-legacy.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-hsw1/igt@kms_cursor_leg...@flip-vs-cursor-busy-crc-legacy.html
* igt@kms_draw_crc@draw-method-xrgb-render-xtiled:
- shard-snb: [PASS][14] -> [FAIL][15] ([i915#54])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-snb5/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-snb2/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][16] -> [FAIL][17] ([i915#79])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) +2
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk7/igt@kms_frontbuffer_track...@fbc-stridechange.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/shard-glk3/igt@kms_frontbuffer_track...@fbc-stridechange.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
- shard-tglb: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +5
similar issues
[20]:
[Intel-gfx] [PATCH i-g-t v2] tests/i915/perf_pmu: PCI unbind test
From: Tvrtko Ursulin
Test driver unbind from device with active PMU client.
v2:
* Verify successful open after rebind. (Chris)
Signed-off-by: Tvrtko Ursulin
---
tests/i915/perf_pmu.c | 113 ++
1 file changed, 113 insertions(+)
diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index cb7273142b8f..76bfa0d40e2c 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -43,6 +43,7 @@
#include "igt.h"
#include "igt_core.h"
#include "igt_device.h"
+#include "igt_device_scan.h"
#include "igt_kmod.h"
#include "igt_perf.h"
#include "igt_sysfs.h"
@@ -2011,6 +2012,80 @@ static void test_unload(unsigned int num_engines)
igt_assert_eq(unload_i915(), 0);
}
+static void set_filter_from_device(int fd)
+{
+ const char *filter_type = "sys:";
+ char filter[strlen(filter_type) + PATH_MAX + 1];
+ char *dst = stpcpy(filter, filter_type);
+ char path[PATH_MAX + 1];
+
+ igt_assert(igt_sysfs_path(fd, path, PATH_MAX));
+ igt_ignore_warn(strncat(path, "/device", PATH_MAX - strlen(path)));
+ igt_assert(realpath(path, dst));
+
+ igt_device_filter_free_all();
+ igt_assert_eq(igt_device_filter_add(filter), 1);
+}
+
+struct rebind_data
+{
+ int sysfs;
+ uint64_t perf_type;
+ char *bus_addr;
+};
+
+static void test_rebind(struct rebind_data *data)
+{
+ struct igt_helper_process pmu_client = { };
+ const unsigned int timeout = 5;
+ int pmu;
+
+ /* Start rapid PMU traffic from a background process. */
+ igt_fork_helper(_client) {
+ pmu = igt_perf_open(data->perf_type, I915_PMU_INTERRUPTS);
+ igt_assert(pmu >= 0);
+
+ for (;;) {
+ pmu_read_single(pmu);
+ usleep(500);
+ }
+ }
+
+ /* Let the child run for a bit. */
+ usleep(1e6);
+
+ /* Unbind the device. */
+ igt_set_timeout(timeout, "Driver unbind timeout!");
+ igt_assert_f(igt_sysfs_set(data->sysfs, "unbind", data->bus_addr),
+"Driver unbind failure!\n");
+ igt_reset_timeout();
+
+ /* Check new PMUs cannot be opened. */
+ pmu = igt_perf_open(data->perf_type, I915_PMU_INTERRUPTS);
+ igt_assert(pmu < 0);
+ usleep(1e6);
+ pmu = igt_perf_open(data->perf_type, I915_PMU_INTERRUPTS);
+ igt_assert(pmu < 0);
+
+ /* Stop background PMU traffic. */
+ usleep(1e6);
+ igt_stop_helper(_client);
+
+ /* Bind the device back. */
+ igt_set_timeout(timeout, "Driver bind timeout!");
+ igt_assert_f(igt_sysfs_set(data->sysfs, "bind", data->bus_addr),
+"Driver bind failure\n!");
+ igt_reset_timeout();
+
+ igt_fail_on_f(faccessat(data->sysfs, data->bus_addr, F_OK, 0),
+ "Device not present!\n");
+
+ /* Check new PMUs can be opened. */
+ pmu = igt_perf_open(data->perf_type, I915_PMU_INTERRUPTS);
+ igt_assert(pmu >= 0);
+ close(pmu);
+}
+
#define test_each_engine(T, i915, e) \
igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
igt_dynamic_f("%s", e->name)
@@ -2026,6 +2101,7 @@ igt_main
const unsigned int num_other_metrics =
I915_PMU_LAST - __I915_PMU_OTHER(0) + 1;
unsigned int num_engines = 0;
+ struct rebind_data rebind;
int fd = -1;
igt_fixture {
@@ -2269,9 +2345,46 @@ igt_main
}
igt_fixture {
+ const char *filter;
+ char *sysfs_path;
+ int sysfs_dev;
+
+ /* Prepare for the rebind test before closing the device. */
+ set_filter_from_device(fd);
+
+ filter = igt_device_filter_get(0);
+ igt_assert(filter);
+
+ rebind.bus_addr = strrchr(filter, '/');
+ igt_assert(rebind.bus_addr++);
+
+ sysfs_path = strchr(filter, ':');
+ igt_assert(sysfs_path++);
+ igt_debug("sysfs path = %s\n", sysfs_path);
+
+ sysfs_dev = open(sysfs_path, O_DIRECTORY);
+ igt_assert_fd(sysfs_dev);
+
+ rebind.sysfs = openat(sysfs_dev, "driver", O_DIRECTORY);
+ igt_assert_fd(rebind.sysfs);
+
+ close(sysfs_dev);
+
+ rebind.perf_type = i915_perf_type_id(fd);
+ igt_debug("type id = %"PRIu64"\n", rebind.perf_type);
+
+ /* Close the device - REQUIRED step for following tests! */
close(fd);
}
+ igt_subtest("rebind")
+ test_rebind();
+
+ igt_fixture {
+ close(rebind.sysfs);
+ igt_device_filter_free_all();
+ }
+
igt_subtest("module-unload") {
igt_require(unload_i915() == 0);
for (int pass = 0; pass < 3; pass++)
--
2.25.1
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/pmu: Fix CPU hotplug with multiple GPUs
On 20/10/2020 17:19, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-10-20 17:11:44)
From: Tvrtko Ursulin
Since we keep a driver global mask of online CPUs and base the decision
whether PMU needs to be migrated upon it, we need to make sure the
migration is done for all registered PMUs (so GPUs).
To do this we need to track the current CPU for each PMU and base the
decision on whether to migrate on a comparison between global and local
state.
At the same time, since dynamic CPU hotplug notification slots are a
scarce resource and given how we already register the multi instance type
state, we can and should add multiple instance of the i915 PMU to this
same state and not allocate a new one for every GPU.
v2:
* Use pr_notice. (Chris)
v3:
* Handle a nasty interaction where unregistration which triggers a false
CPU offline event. (Chris)
Signed-off-by: Tvrtko Ursulin
Suggested-by: Daniel Vetter # dynamic slot
optimisation
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 7 +++-
drivers/gpu/drm/i915/i915_pmu.c | 57 +
drivers/gpu/drm/i915/i915_pmu.h | 6 +++-
3 files changed, 48 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 27964ac0638a..a384f51c91c1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1150,9 +1150,13 @@ static int __init i915_init(void)
return 0;
}
+ i915_pmu_init();
+
err = pci_register_driver(_pci_driver);
- if (err)
+ if (err) {
+ i915_pmu_exit();
return err;
We could do an onion bhaji and call i915_globals_exit() as well.
+ }
i915_perf_sysctl_register();
return 0;
@@ -1166,6 +1170,7 @@ static void __exit i915_exit(void)
i915_perf_sysctl_unregister();
pci_unregister_driver(_pci_driver);
i915_globals_exit();
+ i915_pmu_exit();
pmu_exit then globals_exit to pair with i915_init?
Maybe later, sorry.
}
module_init(i915_init);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 51ed7d0efcdc..cd786ad12be7 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -30,6 +30,7 @@
#define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
static cpumask_t i915_pmu_cpumask;
+static unsigned int i915_pmu_target_cpu = -1;
static u8 engine_config_sample(u64 config)
{
@@ -1049,25 +1050,39 @@ static int i915_pmu_cpu_online(unsigned int cpu, struct
hlist_node *node)
static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
{
struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu),
cpuhp.node);
- unsigned int target;
+ unsigned int target = i915_pmu_target_cpu;
GEM_BUG_ON(!pmu->base.event_init);
+ /*
+* Unregistering an instance generates a CPU offline event which we must
+* ignore to avoid incorrectly modifying the shared i915_pmu_cpumask.
+*/
+ if (pmu->closed)
+ return 0;
+
if (cpumask_test_and_clear_cpu(cpu, _pmu_cpumask)) {
target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
+
/* Migrate events if there is a valid target */
if (target < nr_cpu_ids) {
cpumask_set_cpu(target, _pmu_cpumask);
- perf_pmu_migrate_context(>base, cpu, target);
+ i915_pmu_target_cpu = target;
}
}
+ if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
+ perf_pmu_migrate_context(>base, cpu, target);
+ pmu->cpuhp.cpu = target;
+ }
+
return 0;
}
-static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu)
+static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
+
+void i915_pmu_init(void)
{
- enum cpuhp_state slot;
int ret;
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
@@ -1075,27 +1090,29 @@ static int i915_pmu_register_cpuhp_state(struct
i915_pmu *pmu)
i915_pmu_cpu_online,
i915_pmu_cpu_offline);
if (ret < 0)
- return ret;
+ pr_notice("Failed to setup cpuhp state for i915 PMU! (%d)\n",
+ ret);
+ else
+ cpuhp_slot = ret;
+}
- slot = ret;
- ret = cpuhp_state_add_instance(slot, >cpuhp.node);
- if (ret) {
- cpuhp_remove_multi_state(slot);
- return ret;
- }
+void i915_pmu_exit(void)
+{
+ if (cpuhp_slot != CPUHP_INVALID)
+ cpuhp_remove_multi_state(cpuhp_slot);
+}
- pmu->cpuhp.slot = slot;
- return 0;
+static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu)
+{
+ if (cpuhp_slot == CPUHP_INVALID)
+
[Intel-gfx] [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86a9a5145e47..cb6ec2c241f2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9882,6 +9882,7 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
+
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
#define _TRANSA_HDCP2_AUTH 0x66498
#define _TRANSB_HDCP2_AUTH 0x66598
@@ -9921,6 +9922,35 @@ enum skl_power_gate {
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
+#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
+
_TRANSA_HDCP2_STREAM_STATUS, \
+ _TRANSB_HDCP2_STREAM_STATUS)
+#define STREAM_ENCRYPTION_STATUS BIT(31)
+#define STREAM_TYPE_STATUS BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_STREAM_STATUS(trans) : \
+PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
+ _PORTA_HDCP2_AUTH_STREAM, \
+ _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_AUTH_STREAM, \
+ _TRANSB_HDCP2_AUTH_STREAM)
+#define AUTH_STREAM_TYPE BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_AUTH_STREAM(trans) : \
+PORT_HDCP2_AUTH_STREAM(port))
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support
Enable HDCP 2.2 over DP MST.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++-
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 86a3ffadd97f..98225777c9f9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1696,6 +1696,32 @@ static int hdcp2_authenticate_sink(struct
intel_connector *connector)
return ret;
}
+static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
+{
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = >hdcp;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ enum port port = dig_port->base.port;
+ int ret = 0;
+
+ if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder,
port)) &
+ LINK_ENCRYPTION_STATUS)) {
+ drm_err(_priv->drm, "HDCP 2.2 Link is not encrypted\n");
+ return -EPERM;
+ }
+
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, true);
+ if (ret) {
+ drm_err(_priv->drm, "Failed to enable HDCP 2.2
stream enc\n");
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int hdcp2_enable_encryption(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -1834,7 +1860,7 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
drm_dbg_kms(>drm, "Port deauth failed.\n");
}
- if (!ret) {
+ if (!ret && !dig_port->port_auth) {
/*
* Ensuring the required 200mSec min time interval between
* Session Key Exchange and encryption.
@@ -1849,6 +1875,8 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
}
}
+ ret = hdcp2_enable_stream_encryption(connector);
+
return ret;
}
@@ -1893,11 +1921,23 @@ static int _intel_hdcp2_disable(struct intel_connector
*connector)
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = _port->port_data;
+ struct intel_hdcp *hdcp = >hdcp;
int ret;
drm_dbg_kms(>drm, "[%s:%d] HDCP2.2 is being Disabled\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, false);
+ if (ret) {
+ drm_err(>drm, "Failed to disable HDCP 2.2 stream
enc\n");
+ return ret;
+ }
+ }
+
+ if (dig_port->num_hdcp_streams > 0)
+ return ret;
+
ret = hdcp2_disable_encryption(connector);
if (hdcp2_deauthenticate_port(connector) < 0)
@@ -1921,6 +1961,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
int ret = 0;
mutex_lock(>mutex);
+ mutex_lock(_port->hdcp_mutex);
cpu_transcoder = hdcp->cpu_transcoder;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
@@ -1998,6 +2039,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
}
out:
+ mutex_unlock(_port->hdcp_mutex);
mutex_unlock(>mutex);
return ret;
}
@@ -2179,7 +2221,7 @@ int intel_hdcp_init(struct intel_connector *connector,
if (!shim)
return -EINVAL;
- if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
+ if (is_hdcp2_supported(dev_priv))
intel_hdcp2_init(connector, dig_port, shim);
ret =
--
2.26.2
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 00/16] HDCP 2.2 DP MST Support
v3 version of this series has fixed the CI reported failures and added below patch in this series. [PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed It has also added the Ack of Tomas to merge the mei_hdcp.c patch via drm-intel. This series has been tested with IGT changes to do a single commit to enable HDCP on all DP-MST connector. HDCP 2.2 support over DP MST actually starts from below patch [PATCH v3 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init. Gen12 HDCP 1.4 support of this series has also floated separately with below series. (https://patchwork.freedesktop.org/series/82605/) Anshuman Gupta (16): drm/i915/hdcp: Update CP property in update_pipe drm/i915/hdcp: Get conn while content_type changed drm/i915/hotplug: Handle CP_IRQ for DP-MST drm/i915/hdcp: DP MST transcoder for link and stream drm/i915/hdcp: Move HDCP enc status timeout to header drm/i915/hdcp: HDCP stream encryption support drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support drm/i915/hdcp: Pass dig_port to intel_hdcp_init drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len drm/hdcp: Max MST content streams drm/i915/hdcp: MST streams support in hdcp port_data drm/i915/hdcp: Pass connector to check_2_2_link drm/i915/hdcp: Add HDCP 2.2 stream register drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks drm/i915/hdcp: Enable HDCP 2.2 MST support drivers/gpu/drm/i915/display/intel_ddi.c | 14 +- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- .../drm/i915/display/intel_display_types.h| 20 +- drivers/gpu/drm/i915/display/intel_dp.c | 14 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 168 +-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 12 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 282 ++ drivers/gpu/drm/i915/display/intel_hdcp.h | 8 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 19 +- drivers/gpu/drm/i915/i915_reg.h | 31 ++ drivers/misc/mei/hdcp/mei_hdcp.c | 3 +- include/drm/drm_hdcp.h| 8 +- 12 files changed, 465 insertions(+), 120 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
connectors")
Cc: Sean Paul
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 0d9e8d3b5603..42cf91cf4f20 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
if (content_protection_type_changed) {
mutex_lock(>mutex);
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ drm_connector_get(>base);
schedule_work(>prop_work);
mutex_unlock(>mutex);
}
--
2.26.2
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[Intel-gfx] [PATCH v3 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
This requires for HDCP 2.2 MST check link.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 24e0067c2e7c..dfb5be64e03a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -375,7 +375,8 @@ struct intel_hdcp_shim {
bool is_repeater, u8 type);
/* HDCP2.2 Link Integrity Check */
- int (*check_2_2_link)(struct intel_digital_port *dig_port);
+ int (*check_2_2_link)(struct intel_digital_port *dig_port,
+ struct intel_connector *connector);
};
struct intel_hdcp {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 384e384cb9e2..a0c62e363c39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct
intel_digital_port *dig_port,
}
static
-int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 2e719df1e5b1..86a3ffadd97f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1942,7 +1942,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
goto out;
}
- ret = hdcp->shim->check_2_2_link(dig_port);
+ ret = hdcp->shim->check_2_2_link(dig_port, connector);
if (ret == HDCP_LINK_PROTECTED) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
intel_hdcp_update_value(connector,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0788de04711b..bd0d91101464 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port
*dig_port,
}
static
-int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
int ret;
--
2.26.2
___
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[Intel-gfx] [PATCH v3 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
.../drm/i915/display/intel_display_types.h| 5 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 56 +++
3 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index fbeffdfd1a0d..a46ba4e6a835 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4746,6 +4746,8 @@ static void intel_ddi_encoder_destroy(struct drm_encoder
*encoder)
intel_dp_encoder_flush_work(encoder);
drm_encoder_cleanup(encoder);
+ if (dig_port)
+ kfree(dig_port->port_data.streams);
kfree(dig_port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 59b8fc21e3e8..749c3a7e0b45 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -402,7 +402,6 @@ struct intel_hdcp {
* content can flow only through a link protected by HDCP2.2.
*/
u8 content_type;
- struct hdcp_port_data port_data;
bool is_paired;
bool is_repeater;
@@ -1446,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count */
+ /* protects num_hdcp_streams reference count, port_data */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* HDCP port data need to pass to security f/w */
+ struct hdcp_port_data port_data;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 10770bf0e85e..207fa17129ae 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -15,6 +15,7 @@
#include
#include
+#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
@@ -1031,7 +1032,8 @@ static int
hdcp2_prepare_ake_init(struct intel_connector *connector,
struct hdcp2_ake_init *ake_data)
{
- struct hdcp_port_data *data = >hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = _port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1060,7 +1062,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
struct hdcp2_ake_no_stored_km *ek_pub_km,
size_t *msg_sz)
{
- struct hdcp_port_data *data = >hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = _port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1087,7 +1090,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
static int hdcp2_verify_hprime(struct intel_connector *connector,
struct hdcp2_ake_send_hprime *rx_hprime)
{
- struct hdcp_port_data *data = >hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = _port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1112,7 +1116,8 @@ static int
hdcp2_store_pairing_info(struct intel_connector *connector,
struct hdcp2_ake_send_pairing_info *pairing_info)
{
- struct hdcp_port_data *data = >hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = _port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1138,7 +1143,8 @@ static int
hdcp2_prepare_lc_init(struct intel_connector *connector,
struct hdcp2_lc_init *lc_init)
{
- struct hdcp_port_data *data = >hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = _port->port_data;
struct drm_i915_private *dev_priv =
[Intel-gfx] [PATCH v3 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 81 +--
2 files changed, 77 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index dfb5be64e03a..4cbb151ff3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -374,6 +374,10 @@ struct intel_hdcp_shim {
int (*config_stream_type)(struct intel_digital_port *dig_port,
bool is_repeater, u8 type);
+ /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
+ int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
+bool enable);
+
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index a0c62e363c39..7e45b9964a29 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,18 +698,14 @@ intel_dp_mst_hdcp_strem_encryption(struct
intel_digital_port *dig_port,
return 0;
}
-static
-bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
- struct intel_connector *connector)
+static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
+struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_dp *intel_dp = _port->dp;
struct drm_dp_query_stream_enc_status_ack_reply reply;
+ struct intel_dp *intel_dp = _port->dp;
int ret;
- if (!intel_dp_hdcp_check_link(dig_port, connector))
- return false;
-
ret = drm_dp_send_query_stream_enc_status(_dp->mst_mgr,
connector->port, );
if (ret) {
@@ -722,6 +718,70 @@ bool intel_dp_mst_hdcp_check_link(struct
intel_digital_port *dig_port,
return reply.auth_completed && reply.encryption_enabled;
}
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ if (!intel_dp_hdcp_check_link(dig_port, connector))
+ return false;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector);
+}
+
+static int
+intel_dp_mst_hdcp2_strem_encryption(struct intel_digital_port *dig_port,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_dp *dp = _port->dp;
+ struct intel_hdcp *hdcp = >attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ /* HDCP2.x register uses stream transcoder */
+ enum transcoder cpu_transcoder = hdcp->stream_transcoder;
+ int ret;
+
+ if (enable && (intel_de_read(i915, HDCP2_AUTH_STREAM(i915,
cpu_transcoder, port)) &
+ AUTH_STREAM_TYPE) != hdcp->content_type) {
+ drm_err(>drm, "Seurity f/w didn't set correct auth
strem_type\n");
+ return -EINVAL;
+ }
+
+ ret = intel_dp_mst_toggle_select_hdcp_stream(dig_port, enable);
+ if (ret)
+ return ret;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP2_STREAM_STATUS(i915,
cpu_transcoder, port),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(>drm, "Timed out waiting for stream encryption
%s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * DP v2.0 I.3.3 ignore the stream signature L' is QSES reply msg reply.
+ * I.3.5 MST source device may use a QSES msg to query downstream status
+ * for a particular stream.
+ */
+static
+int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ int ret;
+
+ ret = intel_dp_hdcp2_check_link(dig_port, connector);
+ if (ret)
+ return ret;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
+}
+
static const struct intel_hdcp_shim
[Intel-gfx] [PATCH v3 04/16] drm/i915/hdcp: DP MST transcoder for link and stream
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
on Gen12.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
.../gpu/drm/i915/display/intel_display_types.h| 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
5 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 09811be08cfe..bf8730267cfd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..c47124a679b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -432,6 +432,8 @@ struct intel_hdcp {
* Hence caching the transcoder here.
*/
enum transcoder cpu_transcoder;
+ /* Only used for DP MST stream encryption */
+ enum transcoder stream_transcoder;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c8fcec4d0788..16865b200062 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state
*state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- pipe_config->cpu_transcoder,
+ pipe_config,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 42cf91cf4f20..a9b652c6e742 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
}
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type)
+ const struct intel_crtc_state *pipe_config, u8
content_type)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
drm_WARN_ON(_priv->drm,
hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
hdcp->content_type = content_type;
- hdcp->cpu_transcoder = cpu_transcoder;
+
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
+ hdcp->stream_transcoder = pipe_config->cpu_transcoder;
+ } else {
+ hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
+ hdcp->stream_transcoder = INVALID_TRANSCODER;
+ }
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ hdcp->port_data.fw_tc =
intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2231,7 +2238,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
if (desired_and_not_enabled || content_protection_type_changed)
intel_hdcp_enable(connector,
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 1bbf5b67ed0a..bc51c1e9b481 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -25,7 +25,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector,
int
[Intel-gfx] [PATCH v3 11/16] drm/hdcp: Max MST content streams
Let's define Maximum MST content streams up to four generically which can be supported by modern display controllers. Cc: Sean Paul Cc: Ramalingam C Acked-by: Maarten Lankhorst Signed-off-by: Anshuman Gupta --- include/drm/drm_hdcp.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index fe58dbb46962..ac22c246542a 100644 --- a/include/drm/drm_hdcp.h +++ b/include/drm/drm_hdcp.h @@ -101,11 +101,11 @@ /* Following Macros take a byte at a time for bit(s) masking */ /* - * TODO: This has to be changed for DP MST, as multiple stream on - * same port is possible. - * For HDCP2.2 on HDMI and DP SST this value is always 1. + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual + * H/W MST streams capacity. + * This required to be moved out to platform specific header. */ -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4 #define HDCP_2_2_TXCAP_MASK_LEN2 #define HDCP_2_2_RXCAPS_LEN3 #define HDCP_2_2_RX_REPEATER(x)((x) & BIT(0)) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä"
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..21c6c9828cd7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5657,6 +5657,17 @@ static void intel_dp_handle_test_request(struct intel_dp
*intel_dp)
"Could not write test response to sink\n");
}
+static void
+intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
+{
+ drm_dp_mst_hpd_irq(_dp->mst_mgr, esi, handled);
+
+ if (esi[1] & DP_CP_IRQ) {
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
+ *handled = true;
+ }
+}
+
/**
* intel_dp_check_mst_status - service any pending MST interrupts, check link
status
* @intel_dp: Intel DP struct
@@ -5701,7 +5712,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
drm_dbg_kms(>drm, "got esi %3ph\n", esi);
- drm_dp_mst_hpd_irq(_dp->mst_mgr, esi, );
+ intel_dp_mst_hpd_irq(intel_dp, esi, );
+
if (!handled)
break;
--
2.26.2
___
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[Intel-gfx] [PATCH v3 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c| 12 +++-
drivers/gpu/drm/i915/display/intel_hdcp.h| 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 652d4645f255..384e384cb9e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port
*dig_port,
return 0;
if (intel_connector->mst_port)
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
_dp_mst_hdcp_shim);
else if (!intel_dp_is_edp(intel_dp))
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
_dp_hdcp_shim);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 46c9bd588db1..10770bf0e85e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1985,12 +1985,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum
transcoder cpu_transcoder)
}
static int initialize_hdcp_port_data(struct intel_connector *connector,
-enum port port,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = >hdcp;
struct hdcp_port_data *data = >port_data;
+ enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
data->fw_ddi = intel_get_mei_fw_ddi_index(port);
@@ -2063,14 +2064,15 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
+static void intel_hdcp2_init(struct intel_connector *connector,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = >hdcp;
int ret;
- ret = initialize_hdcp_port_data(connector, port, shim);
+ ret = initialize_hdcp_port_data(connector, dig_port, shim);
if (ret) {
drm_dbg_kms(>drm, "Mei hdcp data init failed\n");
return;
@@ -2080,7 +2082,7 @@ static void intel_hdcp2_init(struct intel_connector
*connector, enum port port,
}
int intel_hdcp_init(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -2091,7 +2093,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return -EINVAL;
if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
- intel_hdcp2_init(connector, port, shim);
+ intel_hdcp2_init(connector, dig_port, shim);
ret =
drm_connector_attach_content_protection_property(>base,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index b912a3a0f5b8..8f53b0c7fe5c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -18,13 +18,15 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdcp_shim;
+struct intel_digital_port;
enum port;
enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
-int intel_hdcp_init(struct intel_connector *connector, enum port port,
+int intel_hdcp_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
const struct intel_crtc_state *pipe_config, u8
content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f58469226694..0788de04711b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@
[Intel-gfx] [PATCH v3 06/16] drm/i915/hdcp: HDCP stream encryption support
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
in order to enable/disable the stream encryption.
Both of above requirement are same for all Gen with respect to
B.Spec Documentation.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
6 files changed, 90 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bf8730267cfd..fbeffdfd1a0d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
}
}
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable)
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask)
{
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder
*intel_encoder,
tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (enable)
- tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ tmp |= hdcp_mask;
else
- tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ tmp &= ~hdcp_mask;
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
b/drivers/gpu/drm/i915/display/intel_ddi.h
index dcc711cfe4fe..a4dd815c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
u32 ddi_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable);
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index c47124a679b6..59b8fc21e3e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -339,6 +339,10 @@ struct intel_hdcp_shim {
enum transcoder cpu_transcoder,
bool enable);
+ /* Enable/Disable stream encryption on DP MST Transport Link */
+ int (*stream_encryption)(struct intel_digital_port *dig_port,
+bool enable);
+
/* Ensures the link is still protected */
bool (*check_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 03424d20e9f7..652d4645f255 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -16,6 +16,30 @@
#include "intel_dp.h"
#include "intel_hdcp.h"
+static unsigned int transcoder_to_stream_enc_status(enum transcoder
cpu_transcoder)
+{
+ u32 stream_enc_mask;
+
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
+ break;
+ case TRANSCODER_B:
+ stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
+ break;
+ case TRANSCODER_C:
+ stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
+ break;
+ case TRANSCODER_D:
+ stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
+ break;
+
[Intel-gfx] [PATCH v3 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
v2:
Init the hdcp port data k for HDMI/DP SST strem.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 100 +++---
2 files changed, 90 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 749c3a7e0b45..24e0067c2e7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1445,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count, port_data */
+ /* protects num_hdcp_streams reference count, port_data and port_auth */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* port HDCP auth status */
+ bool port_auth;
/* HDCP port data need to pass to security f/w */
struct hdcp_port_data port_data;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 207fa17129ae..2e719df1e5b1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -26,6 +26,62 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
+static int intel_conn_to_vcpi(struct intel_connector *connector)
+{
+ /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+ return connector->port ? connector->port->vcpi.vcpi : 0;
+}
+
+static int
+intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct intel_hdcp *hdcp;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = _port->port_data;
+ bool enforce_type0 = false;
+ int k;
+
+ if (dig_port->port_auth)
+ return 0;
+
+ drm_connector_list_iter_begin(>drm, _iter);
+ for_each_intel_connector_iter(connector, _iter) {
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ hdcp = >hdcp;
+ if (!enforce_type0 && (hdcp->content_type &&
!intel_hdcp2_capable(connector)))
+ enforce_type0 = true;
+
+ data->streams[data->k].stream_id =
intel_conn_to_vcpi(connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(_iter);
+
+ if (drm_WARN_ON(>drm, data->k > INTEL_NUM_PIPES(i915) || data->k
== 0))
+ return -EINVAL;
+
+ for (k = 0; k < data->k; k++)
+ data->streams[k].stream_type =
+ enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 :
hdcp->content_type;
+
+ return 0;
+}
+
static
bool intel_hdcp_is_ksv_valid(u8 *ksv)
{
@@ -1296,6 +1352,7 @@ static int hdcp2_authenticate_port(struct intel_connector
*connector)
if (ret < 0)
drm_dbg_kms(_priv->drm, "Enable hdcp auth failed. %d\n",
ret);
+
mutex_unlock(_priv->hdcp_comp_mutex);
return ret;
@@ -1477,13 +1534,14 @@ static
int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = _port->port_data;
struct intel_hdcp *hdcp = >hdcp;
union {
struct hdcp2_rep_stream_manage stream_manage;
struct hdcp2_rep_stream_ready stream_ready;
} msgs;
const struct intel_hdcp_shim *shim = hdcp->shim;
- int ret;
+ int ret, streams_size_delta, i;
if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
return -ERANGE;
@@ -1493,15 +1551,18 @@ int _hdcp2_propagate_stream_management_info(struct
intel_connector *connector)
drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
/* K no of streams is fixed as 1. Stored as big-endian. */
- msgs.stream_manage.k = cpu_to_be16(1);
+ msgs.stream_manage.k = cpu_to_be16(data->k);
- /* For HDMI
[Intel-gfx] [PATCH v3 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used by both HDCP{1.x,2.x} stream status timeout.
Related: 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
status change")
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 9 -
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 ++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index a9b652c6e742..61252d4be3dd 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -23,7 +23,6 @@
#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
-#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
#define HDCP2_LC_RETRY_CNT 3
static
@@ -762,7 +761,7 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
if (intel_de_wait_for_set(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
HDCP_STATUS_ENC,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(_priv->drm, "Timed out waiting for encryption\n");
return -ETIMEDOUT;
}
@@ -809,7 +808,7 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
if (intel_de_wait_for_clear(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
- ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS))
{
drm_err(_priv->drm,
"Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1641,7 +1640,7 @@ static int hdcp2_enable_encryption(struct intel_connector
*connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
return ret;
}
@@ -1665,7 +1664,7 @@ static int hdcp2_disable_encryption(struct
intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
drm_dbg_kms(_priv->drm, "Disable Encryption Timedout");
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index bc51c1e9b481..b912a3a0f5b8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -8,6 +8,8 @@
#include
+#define HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
+
struct drm_connector;
struct drm_connector_state;
struct drm_i915_private;
--
2.26.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
Enable HDCP 1.4 over DP MST for Gen12.
This also enable the stream encryption support for
older generations, which was missing earlier.
v2:
- Added debug print for stream encryption.
- Disable the hdcp on port after disabling last stream
encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++---
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 16865b200062..f00e12fc83e8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -826,13 +826,9 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
-
- /* TODO: Figure out how to make HDCP work on GEN12+ */
- if (INTEL_GEN(dev_priv) < 12) {
- ret = intel_dp_init_hdcp(dig_port, intel_connector);
- if (ret)
- DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
- }
+ ret = intel_dp_init_hdcp(dig_port, intel_connector);
+ if (ret)
+ drm_dbg_kms(_priv->drm, "HDCP init failed, skipping.\n");
/*
* Reuse the prop from the SST connector because we're
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 61252d4be3dd..46c9bd588db1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
return ret;
}
-/* Implements Part 1 of the HDCP authorization procedure */
+/*
+ * Implements Part 1 of the HDCP authorization procedure.
+ * Authentication Part 1 steps for Multi-stream DisplayPort.
+ * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
+ * Step 2. Enable encryption for each stream that requires encryption.
+ */
static int intel_hdcp_auth(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
return -ETIMEDOUT;
}
- /*
-* XXX: If we have MST-connected devices, we need to enable encryption
-* on those as well.
-*/
+ /* DP MST Auth Part 1 Step 2.a and Step 2.b */
+ if (shim->stream_encryption) {
+ ret = shim->stream_encryption(dig_port, true);
+ if (ret) {
+ drm_err(_priv->drm, "Failed to enable HDCP 1.4
stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(_priv->drm, "HDCP 1.4 tras %s stream
encrypted\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
if (repeater_present)
return intel_hdcp_auth_downstream(connector);
@@ -790,19 +801,26 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
drm_dbg_kms(_priv->drm, "[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
+ /*
+* Step 1: Deselect HDCP Multiplestream Bit.
+* Step 2: poll for stream encryption status to be disable.
+*/
+ if (hdcp->shim->stream_encryption) {
+ ret = hdcp->shim->stream_encryption(dig_port, false);
+ if (ret) {
+ drm_err(_priv->drm, "Failed to disable HDCP 1.4
stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(_priv->drm, "HDCP 1.4 trans %s stream
encryption disabled\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
/*
-* If there are other connectors on this port using HDCP, don't disable
-* it. Instead, toggle the HDCP signalling off on that particular
-* connector/pipe and exit.
+* If there are other connectors on this port using HDCP, don't disable
it.
+* Repeat steps 1-2 for each stream that no longer requires encryption.
*/
- if (dig_port->num_hdcp_streams > 0) {
- ret = hdcp->shim->toggle_signalling(dig_port,
- cpu_transcoder, false);
- if (ret)
- DRM_ERROR("Failed to disable HDCP signalling\n");
+ if (dig_port->num_hdcp_streams > 0)
return ret;
- }
hdcp->hdcp_encrypted = false;
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 01/16] drm/i915/hdcp: Update CP property in update_pipe
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
update_pipe instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actually hdcp->value was ENABLED.
This caught with DP MST setup, when disabling HDCP on a connector
sets the crtc state need_modeset to true for all crtc driving
the other DP-MST topology connectors.
v2:
Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal
state")
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b2a4bbcfdcd2..0d9e8d3b5603 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2221,6 +2221,11 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
desired_and_not_enabled =
hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
mutex_unlock(>mutex);
+
+ if (!desired_and_not_enabled &&
!content_protection_type_changed) {
+ drm_connector_get(>base);
+ schedule_work(>prop_work);
+ }
}
if (desired_and_not_enabled || content_protection_type_changed)
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size. It is based upon the actual number of MST streams and size of wired_cmd_repeater_auth_stream_req_in. Excluding the size of hdcp_cmd_header. v2: hdcp_cmd_header size annotation nitpick. [Tomas] Cc: Tomas Winkler Cc: Ramalingam C Acked-by: Tomas Winkler Signed-off-by: Anshuman Gupta --- drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c index 9ae9669e46ea..3506a3534294 100644 --- a/drivers/misc/mei/hdcp/mei_hdcp.c +++ b/drivers/misc/mei/hdcp/mei_hdcp.c @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev, verify_mprime_in->header.api_version = HDCP_API_VERSION; verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ; verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS; - verify_mprime_in->header.buffer_len = - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN; + verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header); verify_mprime_in->port.integrated_port_type = data->port_type; verify_mprime_in->port.physical_port = (u8)data->fw_ddi; -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Do not share hwsp across contexts any more, v5.1
Op 21-10-2020 om 16:44 schreef Chris Wilson: > Quoting Maarten Lankhorst (2020-10-21 15:39:48) >> Instead of sharing pages with breadcrumbs, give each timeline a >> single page. This allows unrelated timelines not to share locks >> any more during command submission. > This is designed to fail. No. The hwsp is observed externally with a > lifetime outside of the local timeline's control. > -Chris Hey, Thank you for looking at the patch. It seems you're worried about lifetime issues. When the timeline is pinned, i915_active takes a reference on the vma pin and timeline. intel_timeline_read_hwsp() uses the existing i915_active trick to keep the timeline alive, so this will stay working correctly as intended. :) Can I add your reviewed-by for the patch when I submit it to the ml again? Cheers, ~Maarten ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Big joiner enabling
== Series Details ==
Series: Big joiner enabling
URL : https://patchwork.freedesktop.org/series/82944/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180_full -> Patchwork_18761_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18761_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@core_hotunplug@hotrebind}:
- shard-hsw: NOTRUN -> [WARN][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-hsw6/igt@core_hotunp...@hotrebind.html
Known issues
Here are the changes found in Patchwork_18761_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_busy@extended@bcs0:
- shard-snb: [PASS][2] -> [INCOMPLETE][3] ([i915#82])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-snb5/igt@gem_busy@exten...@bcs0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-snb2/igt@gem_busy@exten...@bcs0.html
* igt@gem_exec_suspend@basic:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#1888])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-glk7/igt@gem_exec_susp...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-glk7/igt@gem_exec_susp...@basic.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][6] -> [DMESG-WARN][7] ([i915#1436] /
[i915#1635] / [i915#716])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-apl8/igt@gen9_exec_pa...@allowed-all.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-apl1/igt@gen9_exec_pa...@allowed-all.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-hsw: [PASS][8] -> [WARN][9] ([i915#1519])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-hsw7/igt@i915_pm_rc6_reside...@rc6-fence.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-hsw8/igt@i915_pm_rc6_reside...@rc6-fence.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][10] -> [INCOMPLETE][11] ([i915#155])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-kbl1/igt@i915_susp...@debugfs-reader.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-kbl6/igt@i915_susp...@debugfs-reader.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-skl: [PASS][12] -> [INCOMPLETE][13] ([i915#198])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl2/igt@i915_susp...@fence-restore-tiled2untiled.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-skl7/igt@i915_susp...@fence-restore-tiled2untiled.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-kbl1/igt@kms_big...@y-tiled-8bpp-rotate-180.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-kbl6/igt@kms_big...@y-tiled-8bpp-rotate-180.html
* igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge:
- shard-skl: [PASS][16] -> [DMESG-WARN][17] ([i915#1982]) +3
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl6/igt@kms_cursor_edge_w...@pipe-b-256x256-right-edge.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-skl10/igt@kms_cursor_edge_w...@pipe-b-256x256-right-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [PASS][18] -> [FAIL][19] ([i915#2346])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-skl3/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-skl3/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled:
- shard-hsw: [PASS][20] -> [DMESG-WARN][21] ([i915#1982])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-hsw1/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-untiled.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-hsw6/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-untiled.html
* igt@kms_draw_crc@draw-method-xrgb-render-xtiled:
- shard-snb: [PASS][22] -> [FAIL][23] ([i915#54]) +1 similar issue
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/shard-snb5/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/shard-snb2/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html
* igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reset the interrupt mask on disabling interrupts
== Series Details ==
Series: drm/i915: Reset the interrupt mask on disabling interrupts
URL : https://patchwork.freedesktop.org/series/82945/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180 -> Patchwork_18763
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/index.html
Known issues
Here are the changes found in Patchwork_18763 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-soraka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-soraka/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/fi-kbl-soraka/igt@core_hotunp...@unbind-rebind.html
Possible fixes
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [DMESG-WARN][3] ([i915#2203]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
- fi-icl-u2: [FAIL][5] ([i915#1161]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
Participating hosts (45 -> 38)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9180 -> Patchwork_18763
CI-20190529: 20190529
CI_DRM_9180: b174cec7fd714a954d4a65088ca53e32ae9cd45e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18763: 34e2194f7c0af3ff5ede47cf9702b2ac3cb61b5a @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
34e2194f7c0a drm/i915: Reset the interrupt mask on disabling interrupts
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18763/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Reset the interrupt mask on disabling interrupts
== Series Details == Series: drm/i915: Reset the interrupt mask on disabling interrupts URL : https://patchwork.freedesktop.org/series/82945/ State : warning == Summary == $ dim checkpatch origin/drm-tip 34e2194f7c0a drm/i915: Reset the interrupt mask on disabling interrupts -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: <4>[ 101.816730] i915 :00:02.0: drm_WARN_ON(!intel_irqs_enabled(dev_priv)) total: 0 errors, 1 warnings, 0 checks, 81 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
== Series Details ==
Series: series starting with drm/i915/gt: Use the local HWSP offset during
submission (rev2)
URL : https://patchwork.freedesktop.org/series/82935/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180 -> Patchwork_18762
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/index.html
Known issues
Here are the changes found in Patchwork_18762 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982] /
[k.org#205379])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-tgl-u2/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-tgl-u2/igt@i915_module_l...@reload.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#1161] / [i915#262])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-r: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-r/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-kbl-r/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [DMESG-WARN][9] ([i915#2203]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
- fi-icl-u2: [FAIL][11] ([i915#1161]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 38)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9180 -> Patchwork_18762
CI-20190529: 20190529
CI_DRM_9180: b174cec7fd714a954d4a65088ca53e32ae9cd45e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18762: 9004d18b0348b7f3c79e6f9753339b042f6c028d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9004d18b0348 drm/i915/selftests: Exercise intel_timeline_read_hwsp()
a0a057614518 drm/i915/gt: Use the local HWSP offset during submission
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18762/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Reset the interrupt mask on disabling interrupts
As we disable the interrupt during suspend, also reset the irq_mask to
short-circuit subsystems that later try to turn off their interrupt
source.
<4>[ 101.816730] i915 :00:02.0: drm_WARN_ON(!intel_irqs_enabled(dev_priv))
<4>[ 101.816853] WARNING: CPU: 3 PID: 4241 at
drivers/gpu/drm/i915/i915_irq.c:343 ilk_update_display_irq+0xb3/0x130 [i915]
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 25 ++---
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 09221ca1ffb2..cbb71fc73313 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -337,17 +337,14 @@ void ilk_update_display_irq(struct drm_i915_private
*dev_priv,
u32 new_val;
lockdep_assert_held(_priv->irq_lock);
-
drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
- if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
- return;
-
new_val = dev_priv->irq_mask;
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != dev_priv->irq_mask) {
+ if (new_val != dev_priv->irq_mask &&
+ !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
dev_priv->irq_mask = new_val;
I915_WRITE(DEIMR, dev_priv->irq_mask);
POSTING_READ(DEIMR);
@@ -368,19 +365,16 @@ static void bdw_update_port_irq(struct drm_i915_private
*dev_priv,
u32 old_val;
lockdep_assert_held(_priv->irq_lock);
-
drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
- if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
- return;
-
old_val = I915_READ(GEN8_DE_PORT_IMR);
new_val = old_val;
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != old_val) {
+ if (new_val != old_val &&
+ !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
I915_WRITE(GEN8_DE_PORT_IMR, new_val);
POSTING_READ(GEN8_DE_PORT_IMR);
}
@@ -401,17 +395,14 @@ void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv,
u32 new_val;
lockdep_assert_held(_priv->irq_lock);
-
drm_WARN_ON(_priv->drm, enabled_irq_mask & ~interrupt_mask);
- if (drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv)))
- return;
-
new_val = dev_priv->de_irq_mask[pipe];
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != dev_priv->de_irq_mask[pipe]) {
+ if (new_val != dev_priv->de_irq_mask[pipe] &&
+ !drm_WARN_ON(_priv->drm, !intel_irqs_enabled(dev_priv))) {
dev_priv->de_irq_mask[pipe] = new_val;
I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
@@ -2951,6 +2942,8 @@ static void ilk_irq_reset(struct drm_i915_private
*dev_priv)
struct intel_uncore *uncore = _priv->uncore;
GEN3_IRQ_RESET(uncore, DE);
+ dev_priv->irq_mask = ~0u;
+
if (IS_GEN(dev_priv, 7))
intel_uncore_write(uncore, GEN7_ERR_INT, 0x);
@@ -3864,6 +3857,7 @@ static void i915_irq_reset(struct drm_i915_private
*dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN2_);
+ dev_priv->irq_mask = ~0u;
}
static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3970,6 +3964,7 @@ static void i965_irq_reset(struct drm_i915_private
*dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN2_);
+ dev_priv->irq_mask = ~0u;
}
static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
== Series Details == Series: series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2) URL : https://patchwork.freedesktop.org/series/82935/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' -
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2)
== Series Details == Series: series starting with drm/i915/gt: Use the local HWSP offset during submission (rev2) URL : https://patchwork.freedesktop.org/series/82935/ State : warning == Summary == $ dim checkpatch origin/drm-tip a0a057614518 drm/i915/gt: Use the local HWSP offset during submission 9004d18b0348 drm/i915/selftests: Exercise intel_timeline_read_hwsp() -:270: WARNING:LINE_SPACING: Missing a blank line after declarations #270: FILE: drivers/gpu/drm/i915/gt/selftest_timeline.c:991: + unsigned long count = 0; + IGT_TIMEOUT(end_time); total: 0 errors, 1 warnings, 0 checks, 396 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Use the local HWSP offset during submission
We wrap the timeline on construction of the next request, but there may
still be requests in flight that have not yet finalized the breadcrumb.
(The breadcrumb is delayed as we need engine-local offsets, and for the
virtual engine that is not known until execution.) As such, by the time
we write to the timeline's HWSP offset it may have changed, and we
should use the value we preserved in the request instead.
Though the window is small and infrequent (at full flow we can expect a
timeline's seqno to wrap once every 30 minutes), the impact of writing
the old seqno into the new HWSP is severe: the old requests are never
completed, and the new requests are completed before they are even
submitted.
Fixes: ebece7539242 ("drm/i915: Keep timeline HWSP allocated until idle across
the system")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: # v5.2+
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 27 +--
drivers/gpu/drm/i915/gt/intel_timeline.c | 18 +++--
.../gpu/drm/i915/gt/intel_timeline_types.h| 2 ++
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index c22d47cc6701..d0be98b67138 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3597,6 +3597,19 @@ static const struct intel_context_ops
execlists_context_ops = {
.destroy = execlists_context_destroy,
};
+static u32 hwsp_offset(const struct i915_request *rq)
+{
+ const struct intel_timeline_cacheline *cl;
+
+ /* Before the request is executed, the timeline/cachline is fixed */
+
+ cl = rcu_dereference_protected(rq->hwsp_cacheline, 1);
+ if (cl)
+ return cl->ggtt_offset;
+
+ return rcu_dereference_protected(rq->timeline, 1)->hwsp_offset;
+}
+
static int gen8_emit_init_breadcrumb(struct i915_request *rq)
{
u32 *cs;
@@ -3619,7 +3632,7 @@ static int gen8_emit_init_breadcrumb(struct i915_request
*rq)
*cs++ = MI_NOOP;
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
- *cs++ = i915_request_timeline(rq)->hwsp_offset;
+ *cs++ = hwsp_offset(rq);
*cs++ = 0;
*cs++ = rq->fence.seqno - 1;
@@ -4939,11 +4952,9 @@ gen8_emit_fini_breadcrumb_tail(struct i915_request
*request, u32 *cs)
return gen8_emit_wa_tail(request, cs);
}
-static u32 *emit_xcs_breadcrumb(struct i915_request *request, u32 *cs)
+static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
{
- u32 addr = i915_request_active_timeline(request)->hwsp_offset;
-
- return gen8_emit_ggtt_write(cs, request->fence.seqno, addr, 0);
+ return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
}
static u32 *gen8_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
@@ -4962,7 +4973,7 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct
i915_request *request, u32 *cs)
/* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
cs = gen8_emit_ggtt_write_rcs(cs,
request->fence.seqno,
-
i915_request_active_timeline(request)->hwsp_offset,
+ hwsp_offset(request),
PIPE_CONTROL_FLUSH_ENABLE |
PIPE_CONTROL_CS_STALL);
@@ -4974,7 +4985,7 @@ gen11_emit_fini_breadcrumb_rcs(struct i915_request
*request, u32 *cs)
{
cs = gen8_emit_ggtt_write_rcs(cs,
request->fence.seqno,
-
i915_request_active_timeline(request)->hwsp_offset,
+ hwsp_offset(request),
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
@@ -5044,7 +5055,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request
*request, u32 *cs)
{
cs = gen12_emit_ggtt_write_rcs(cs,
request->fence.seqno,
-
i915_request_active_timeline(request)->hwsp_offset,
+ hwsp_offset(request),
PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH |
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index a2f74cefe4c3..7ea94d201fe6 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -188,10 +188,14 @@ cacheline_alloc(struct intel_timeline_hwsp *hwsp,
unsigned int cacheline)
return cl;
}
-static void cacheline_acquire(struct intel_timeline_cacheline *cl)
+static void
[Intel-gfx] ✓ Fi.CI.BAT: success for Big joiner enabling
== Series Details ==
Series: Big joiner enabling
URL : https://patchwork.freedesktop.org/series/82944/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9180 -> Patchwork_18761
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/index.html
Known issues
Here are the changes found in Patchwork_18761 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [PASS][1] -> [DMESG-FAIL][2] ([i915#165])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
Possible fixes
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [DMESG-WARN][5] ([i915#2203]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
- fi-icl-u2: [FAIL][7] ([i915#1161]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [DMESG-WARN][11] ([i915#2203]) -> [DMESG-FAIL][12]
([i915#2203])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9180/fi-kbl-guc/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/fi-kbl-guc/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
Participating hosts (45 -> 36)
--
Missing(9): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-glk-dsi fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9180 -> Patchwork_18761
CI-20190529: 20190529
CI_DRM_9180: b174cec7fd714a954d4a65088ca53e32ae9cd45e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5822: b4bcf05cb9839037128905deda7146434155cc41 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18761: 040cc02e306c96264ba552adc8c96a7fcd09d386 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
040cc02e306c drm/i915: Add debugfs dumping for bigjoiner, v3.
bf37cfa8496f drm/i915: Add bigjoiner aware plane clipping checks
ed5b71b1f929 drm/i915: Link planes in a bigjoiner configuration, v3.
c95ea184d537 drm/i915: HW state readout for Bigjoiner case
eeb383630551 drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
c5aeb07221de drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner
slave
f5dd757111ef drm/i915: Try to make bigjoiner work in atomic check
4e7811e6d8ed drm/i915/dp: Prep for bigjoiner atomic check
f2fbe5b3f867 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
c4a7f00c7188 drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner
modes
4e9e1fe595d7 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
28921f36dd2c HAX to make DSC work on the icelake test system
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18761/index.html
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Big joiner enabling
== Series Details == Series: Big joiner enabling URL : https://patchwork.freedesktop.org/series/82944/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Big joiner enabling
== Series Details ==
Series: Big joiner enabling
URL : https://patchwork.freedesktop.org/series/82944/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
28921f36dd2c HAX to make DSC work on the icelake test system
4e9e1fe595d7 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:7: WARNING:TYPO_SPELLING: 'halfs' may be misspelled - perhaps 'halves'?
#7:
With bigjoiner, there will be 2 pipes driving 2 halfs of 1 transcoder,
-:134: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#134: FILE: drivers/gpu/drm/i915/display/intel_display.c:13460:
+ crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode =
crtc_state->uapi.adjusted_mode;
total: 0 errors, 1 warnings, 1 checks, 366 lines checked
c4a7f00c7188 drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner
modes
f2fbe5b3f867 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
4e7811e6d8ed drm/i915/dp: Prep for bigjoiner atomic check
f5dd757111ef drm/i915: Try to make bigjoiner work in atomic check
-:100: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#100: FILE: drivers/gpu/drm/i915/display/intel_display.c:13472:
+
crtc_state->bigjoiner_linked_crtc);
-:146: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#146: FILE: drivers/gpu/drm/i915/display/intel_display.c:13546:
+ crtc_state->nv12_planes = crtc_state->c8_planes =
crtc_state->update_planes = 0;
-:231: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#231: FILE: drivers/gpu/drm/i915/display/intel_display.c:15153:
+ slave = new_crtc_state->bigjoiner_linked_crtc =
-:265: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#265: FILE: drivers/gpu/drm/i915/display/intel_display.c:15187:
+ slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner =
false;
-:266: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#266: FILE: drivers/gpu/drm/i915/display/intel_display.c:15188:
+ slave_crtc_state->bigjoiner_slave =
master_crtc_state->bigjoiner_slave = false;
-:267: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#267: FILE: drivers/gpu/drm/i915/display/intel_display.c:15189:
+ slave_crtc_state->bigjoiner_linked_crtc =
master_crtc_state->bigjoiner_linked_crtc = NULL;
-:267: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#267: FILE: drivers/gpu/drm/i915/display/intel_display.c:15189:
+ slave_crtc_state->bigjoiner_linked_crtc =
master_crtc_state->bigjoiner_linked_crtc = NULL;
-:315: WARNING:BRACES: braces {} are not necessary for any arm of this statement
#315: FILE: drivers/gpu/drm/i915/display/intel_display.c:15723:
+ if (new_crtc_state->bigjoiner) {
[...]
+ } else if (INTEL_GEN(dev_priv) >= 9)
[...]
else
[...]
total: 0 errors, 3 warnings, 5 checks, 337 lines checked
c5aeb07221de drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner
slave
eeb383630551 drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
-:120: ERROR:CODE_INDENT: code indent should use tabs where possible
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:7263:
+ * Enable sequence steps 1-7 on bigjoiner master$
-:121: ERROR:CODE_INDENT: code indent should use tabs where possible
#121: FILE: drivers/gpu/drm/i915/display/intel_display.c:7264:
+ */$
-:164: ERROR:SPACING: space required before the open brace '{'
#164: FILE: drivers/gpu/drm/i915/display/intel_display.c:7302:
+ if (!new_crtc_state->bigjoiner_slave ||
!transcoder_is_dsi(cpu_transcoder)){
-:165: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (16, 16)
#165: FILE: drivers/gpu/drm/i915/display/intel_display.c:7303:
+ if (!transcoder_is_dsi(cpu_transcoder))
+ intel_set_transcoder_timings(new_crtc_state);
total: 3 errors, 1 warnings, 0 checks, 242 lines checked
c95ea184d537 drm/i915: HW state readout for Bigjoiner case
-:79: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#79: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4529:
+ /* Our own transcoder needs to be disabled when reading it in
intel_ddi_read_func_ctl() */
-:81: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#81: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4531:
+ pipe_config->cpu_transcoder = (enum
transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
-:106: WARNING:TABSTOP: Statements should start on a tabstop
#106: FILE: drivers/gpu/drm/i915/display/intel_display.c:3634:
+struct intel_crtc_state *crtc_state =
-:246: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#246: FILE: drivers/gpu/drm/i915/display/intel_display.c:11501:
+^I} else ^Iif (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||$
-:258: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#258: FILE:
