[Intel-gfx] ✓ Fi.CI.BAT: success for Enable HDR on MCA LSPCON based Gen9 devices (rev10)
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev10)
URL : https://patchwork.freedesktop.org/series/68081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9260 -> Patchwork_18849
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/index.html
New tests
-
New tests have been introduced between CI_DRM_9260 and Patchwork_18849:
### New CI tests (1) ###
* boot:
- Statuses : 38 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18849 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
* igt@i915_module_load@reload:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-icl-u2/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/fi-icl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live@active:
- fi-icl-u2: [PASS][9] -> [DMESG-FAIL][10] ([i915#765])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-icl-u2/igt@i915_selftest@l...@active.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/fi-icl-u2/igt@i915_selftest@l...@active.html
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][11] ([i915#1161] / [i915#262]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9260 -> Patchwork_18849
CI-20190529: 20190529
CI_DRM_9260: ac7c5c0c0d9c3475169572ccbd5f28f612a2c5a0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5831: b6247cc06d76b48ec2a3a0b13ffbd25aec8a42ff @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18849: 4031ba5793c0d3484f6ad5ede6a7cee67a6ceee6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4031ba5793c0 drm/i915/display: [NOT FOR MERGE] Reduce blanking to support
4k60@10bpp for LSPCON
10549dbe552e drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks
dd2812964cd8 drm/i915/lspcon: Create separate infoframe_enabled helper
65e33553e3ac drm/i915/display: Implement DRM infoframe read for LSPCON
3b1d8c7620a6 drm/i915/display: Implement infoframes readback for LSPCON
beba142c70b1 drm/i915/display: Enable HDR for Parade based lspcon
1ca01e1aacd1 drm/i915/display: Enable BT2020 for HDR on LSPCON devices
d9e635f7c9ac drm/i915/display: Nuke bogus lspcon check
88b5fbb99a2f drm/i915/display: Attach content type property for LSPCON
d73d7c3ca651 drm/i915/display: Attach HDR property for capable Gen9 devices
bf9c35469dac
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev10)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev10) URL : https://patchwork.freedesktop.org/series/68081/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev10)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev10) URL : https://patchwork.freedesktop.org/series/68081/ State : warning == Summary == $ dim checkpatch origin/drm-tip 78d17307adc1 drm/i915/display: Add HDR Capability detection for LSPCON bf9c35469dac drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon d73d7c3ca651 drm/i915/display: Attach HDR property for capable Gen9 devices -:48: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #48: FILE: drivers/gpu/drm/i915/display/intel_dp.c:6740: + connector->dev->mode_config.hdr_output_metadata_property, total: 0 errors, 1 warnings, 0 checks, 41 lines checked 88b5fbb99a2f drm/i915/display: Attach content type property for LSPCON d9e635f7c9ac drm/i915/display: Nuke bogus lspcon check 1ca01e1aacd1 drm/i915/display: Enable BT2020 for HDR on LSPCON devices beba142c70b1 drm/i915/display: Enable HDR for Parade based lspcon 3b1d8c7620a6 drm/i915/display: Implement infoframes readback for LSPCON 65e33553e3ac drm/i915/display: Implement DRM infoframe read for LSPCON dd2812964cd8 drm/i915/lspcon: Create separate infoframe_enabled helper 10549dbe552e drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks 4031ba5793c0 drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v10 03/12] drm/i915/display: Attach HDR property for capable Gen9 devices
Attach HDR property for Gen9 devices with MCA LSPCON
chips.
v2: Cleaned HDR property attachment logic based on capability
as per Jani Nikula's suggestion.
v3: Fixed the HDR property attachment logic as per the new changes
by Kai-Feng to align with lspcon detection failure on some devices.
v4: Add HDR proprty in late_register to handle lspcon detection,
as suggested by Ville.
v5: Init Lspcon only if advertized from BIOS.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 ++
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
drivers/gpu/drm/i915/display/intel_lspcon.h | 1 +
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cf09aca7607b..07eda10f8add 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6714,6 +6714,8 @@ intel_dp_connector_register(struct drm_connector
*connector)
{
struct drm_i915_private *i915 = to_i915(connector->dev);
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_lspcon *lspcon = _port->lspcon;
int ret;
ret = intel_connector_register(connector);
@@ -6727,6 +6729,18 @@ intel_dp_connector_register(struct drm_connector
*connector)
ret = drm_dp_aux_register(_dp->aux);
if (!ret)
drm_dp_cec_register_connector(_dp->aux, connector);
+
+ if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
+ return ret;
+
+ if (lspcon_init(dig_port)) {
+ lspcon_detect_hdr_capability(lspcon);
+ if (lspcon->hdr_supported)
+ drm_object_attach_property(>base,
+
connector->dev->mode_config.hdr_output_metadata_property,
+ 0);
+ }
+
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 46565ae555b1..336494b60d11 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -553,7 +553,7 @@ void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon)
lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON);
}
-static bool lspcon_init(struct intel_digital_port *dig_port)
+bool lspcon_init(struct intel_digital_port *dig_port)
{
struct intel_dp *dp = _port->dp;
struct intel_lspcon *lspcon = _port->lspcon;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 98043ba50dd4..42ccb21c908f 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -15,6 +15,7 @@ struct intel_digital_port;
struct intel_encoder;
struct intel_lspcon;
+bool lspcon_init(struct intel_digital_port *dig_port);
void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon);
void lspcon_resume(struct intel_digital_port *dig_port);
void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Implement W/A 22010492432 (rev3)
== Series Details ==
Series: drm/i915/ehl: Implement W/A 22010492432 (rev3)
URL : https://patchwork.freedesktop.org/series/83135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9260 -> Patchwork_18848
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/index.html
New tests
-
New tests have been introduced between CI_DRM_9260 and Patchwork_18848:
### New CI tests (1) ###
* boot:
- Statuses : 38 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18848 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982] /
[k.org#205379])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-tgl-u2/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/fi-tgl-u2/igt@i915_module_l...@reload.html
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][5] ([i915#1161] / [i915#262]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +2 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9260 -> Patchwork_18848
CI-20190529: 20190529
CI_DRM_9260: ac7c5c0c0d9c3475169572ccbd5f28f612a2c5a0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5831: b6247cc06d76b48ec2a3a0b13ffbd25aec8a42ff @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18848: 22008c258ae8af75c6d146a390fa7345aca56d1b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
22008c258ae8 drm/i915/ehl: Implement W/A 22010492432
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix typo during output setup
== Series Details == Series: drm/i915/tgl: Fix typo during output setup URL : https://patchwork.freedesktop.org/series/83465/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9258_full -> Patchwork_18847_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18847_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18847_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18847_full: ### IGT changes ### Possible regressions * igt@kms_flip@2x-flip-vs-absolute-wf_vblank@bc-vga1-hdmi-a1: - shard-hsw: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-hsw4/igt@kms_flip@2x-flip-vs-absolute-wf_vbl...@bc-vga1-hdmi-a1.html New tests - New tests have been introduced between CI_DRM_9258_full and Patchwork_18847_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18847_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_caching@writes: - shard-skl: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) +13 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-skl8/igt@gem_cach...@writes.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-skl1/igt@gem_cach...@writes.html * igt@i915_module_load@reload: - shard-iclb: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-iclb4/igt@i915_module_l...@reload.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-iclb8/igt@i915_module_l...@reload.html * igt@kms_cursor_crc@pipe-b-cursor-128x42-random: - shard-skl: [PASS][6] -> [FAIL][7] ([i915#54]) +5 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-128x42-random.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-128x42-random.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][8] -> [FAIL][9] ([i915#96]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_cursor_legacy@cursora-vs-flipa-varying-size: - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#1635] / [i915#1982]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-apl1/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-apl6/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-hsw: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-hsw8/igt@kms_cursor_leg...@cursorb-vs-flipb-toggle.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-hsw1/igt@kms_cursor_leg...@cursorb-vs-flipb-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-skl: [PASS][14] -> [FAIL][15] ([i915#2346]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1: - shard-glk: [PASS][16] -> [FAIL][17] ([i915#2122]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html * igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1: - shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-glk5/igt@kms_flip@flip-vs-wf_vblank-interrupti...@a-hdmi-a1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-glk8/igt@kms_flip@flip-vs-wf_vblank-interrupti...@a-hdmi-a1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-tglb:
[Intel-gfx] [PATCH V3] drm/i915/ehl: Implement W/A 22010492432
As per W/A implemented for TGL to program half of the nominal
DCO divider fraction value which is also applicable on EHL.
Changes since V2:
- Apply stepping B0 till FOREVER
- B0 - revid update as per Bspec 29153
Changes since V1:
- ehl_ used as to keep earliest platform prefix
- WA required B0 stepping onwards
Cc: Deak Imre
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 -
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index eaef7a2d041f..a95e6a2ac698 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2636,13 +2636,16 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
intel_crtc_state *crtc_state)
}
/*
- * Display WA #22010492432: tgl
+ * Display WA #22010492432: ehl, tgl
* Program half of the nominal DCO divider fraction value.
*/
static bool
-tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
{
- return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
+ return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
+IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
+IS_TIGERLAKE(i915)) &&
+i915->dpll.ref_clks.nssc == 38400;
}
static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
@@ -2696,7 +2699,7 @@ static int __cnl_ddi_wrpll_get_freq(struct
drm_i915_private *dev_priv,
dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
- if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
+ if (ehl_combo_pll_div_frac_wa_needed(dev_priv))
dco_fraction *= 2;
dco_freq += (dco_fraction * ref_clock) / 0x8000;
@@ -3086,7 +3089,7 @@ static void icl_calc_dpll_state(struct drm_i915_private
*i915,
memset(pll_state, 0, sizeof(*pll_state));
- if (tgl_combo_pll_div_frac_wa_needed(i915))
+ if (ehl_combo_pll_div_frac_wa_needed(i915))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d548e10e1600..1a5645498cb7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1560,6 +1560,7 @@ extern const struct i915_rev_steppings kbl_revids[];
(IS_ICELAKE(p) && IS_REVID(p, since, until))
#define EHL_REVID_A00x0
+#define EHL_REVID_B00x1
#define IS_JSL_EHL_REVID(p, since, until) \
(IS_JSL_EHL(p) && IS_REVID(p, since, until))
--
2.28.0
___
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Re: [Intel-gfx] [PATCH] drm/i915/gvt: Remove incorrect kerneldoc marking
On 2020.11.03 20:43:07 +, Chris Wilson wrote: > Just a normal comment, not a kerneldoc function description. > > drivers/gpu/drm/i915/gvt/handlers.c:1666: warning: Function parameter or > member 'vgpu' not described in 'bxt_ppat_low_write' > drivers/gpu/drm/i915/gvt/handlers.c:1666: warning: Function parameter or > member 'offset' not described in 'bxt_ppat_low_write' > drivers/gpu/drm/i915/gvt/handlers.c:1666: warning: Function parameter or > member 'p_data' not described in 'bxt_ppat_low_write' > drivers/gpu/drm/i915/gvt/handlers.c:1666: warning: Function parameter or > member 'bytes' not described in 'bxt_ppat_low_write' > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c > b/drivers/gpu/drm/i915/gvt/handlers.c > index ce93079cf933..4ddc9c847470 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -1651,7 +1651,7 @@ static int edp_psr_imr_iir_write(struct intel_vgpu > *vgpu, > return 0; > } > > -/** > +/* > * FixMe: > * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 > did: > * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of > pwrite.) > -- > 2.20.1 > I'd need to run more checks...btw, please also include intel-gvt-dev list for any gvt changes. Thanks Acked-by: Zhenyu Wang -- $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v2,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/83446/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9256_full -> Patchwork_18845_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18845_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18845_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18845_full: ### IGT changes ### Possible regressions * igt@kms_flip@2x-flip-vs-panning@ab-vga1-hdmi-a1: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-hsw1/igt@kms_flip@2x-flip-vs-pann...@ab-vga1-hdmi-a1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-hsw8/igt@kms_flip@2x-flip-vs-pann...@ab-vga1-hdmi-a1.html New tests - New tests have been introduced between CI_DRM_9256_full and Patchwork_18845_full: ### New CI tests (1) ### * boot: - Statuses : 199 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18845_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-hsw: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-hsw4/igt@gem_...@unwedge-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-hsw7/igt@gem_...@unwedge-stress.html * igt@gem_exec_params@rs-invalid: - shard-hsw: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-hsw1/igt@gem_exec_par...@rs-invalid.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-hsw8/igt@gem_exec_par...@rs-invalid.html * igt@gem_workarounds@suspend-resume-context: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#198]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl3/igt@gem_workarou...@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-skl8/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-hsw: [PASS][9] -> [WARN][10] ([i915#1519]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-hsw6/igt@i915_pm_rc6_reside...@rc6-fence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-hsw7/igt@i915_pm_rc6_reside...@rc6-fence.html * igt@i915_pm_rpm@i2c: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl4/igt@i915_pm_...@i2c.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-skl4/igt@i915_pm_...@i2c.html * igt@i915_suspend@sysfs-reader: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#146] / [i915#198]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl6/igt@i915_susp...@sysfs-reader.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-skl8/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl1/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-64x21-offscreen.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][17] -> [FAIL][18] ([i915#96]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-hsw: [PASS][19] -> [FAIL][20] ([i915#2370]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-hsw4/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-glk4/igt@kms_cursor_leg...@cursorb-vs-flipb-toggle.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix typo during output setup
== Series Details ==
Series: drm/i915/tgl: Fix typo during output setup
URL : https://patchwork.freedesktop.org/series/83465/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9258 -> Patchwork_18847
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/index.html
New tests
-
New tests have been introduced between CI_DRM_9258 and Patchwork_18847:
### New CI tests (1) ###
* boot:
- Statuses : 38 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18847 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-icl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/fi-icl-y/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/fi-icl-y/igt@i915_module_l...@reload.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/fi-icl-u2/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/fi-icl-u2/igt@i915_module_l...@reload.html
- fi-tgl-u2: [DMESG-WARN][7] ([i915#1982] / [k.org#205379]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/fi-tgl-u2/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/fi-tgl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-ehl-1}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
- fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][13] ([i915#1161] / [i915#262]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (42 -> 38)
--
Additional (1): fi-kbl-7500u
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9258 -> Patchwork_18847
CI-20190529: 20190529
CI_DRM_9258: a9c138cdeb8819048da5d488bdddf6bc81122585 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5831: b6247cc06d76b48ec2a3a0b13ffbd25aec8a42ff @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18847: 5bd3d12bcb0ffe821ec14983542c818b7baab6a3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5bd3d12bcb0f drm/i915/tgl: Fix typo during output setup
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/index.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Pass intel_atomic_state to skl_build_pipe_wm()
== Series Details == Series: series starting with [1/3] drm/i915: Pass intel_atomic_state to skl_build_pipe_wm() URL : https://patchwork.freedesktop.org/series/83445/ State : success == Summary == CI Bug Log - changes from CI_DRM_9256_full -> Patchwork_18844_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9256_full and Patchwork_18844_full: ### New CI tests (1) ### * boot: - Statuses : 175 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18844_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - shard-tglb: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-tglb6/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-tglb5/igt@i915_module_l...@reload.html - shard-iclb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-iclb4/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-iclb6/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@i2c: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +10 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl4/igt@i915_pm_...@i2c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-skl10/igt@i915_pm_...@i2c.html * igt@i915_pm_rpm@modeset-non-lpsp: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-glk9/igt@i915_pm_...@modeset-non-lpsp.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-glk5/igt@i915_pm_...@modeset-non-lpsp.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl1/igt@kms_cursor_...@pipe-c-cursor-64x21-offscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-skl2/igt@kms_cursor_...@pipe-c-cursor-64x21-offscreen.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-apl2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-apl8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html * igt@kms_flip@plain-flip-fb-recreate@c-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#2122]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl1/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-skl2/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#49]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-glk4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-glk5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [DMESG-FAIL][22] ([fdo#108145] / [i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]:
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix typo during output setup
On Wed, Nov 04, 2020 at 03:00:00AM +0200, Imre Deak wrote:
Fix a typo that led to some MST short pulse event handling issue (the
short pulse event was handled for both encoder instances, each having
its own state).
Fixes: 1d8ca002456b6 ("drm/i915: Add PORT_TCn aliases to enum port")
Cc: Ville Syrjälä
Cc: Lucas De Marchi
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cddbda5303ff..19a4d81558c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17223,7 +17223,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_TC1);
intel_ddi_init(dev_priv, PORT_TC2);
- intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC3);
uggh... Thanks!
Reviewed-by: Lucas De Marchi
Lucas De Marchi
intel_ddi_init(dev_priv, PORT_TC4);
intel_ddi_init(dev_priv, PORT_TC5);
intel_ddi_init(dev_priv, PORT_TC6);
--
2.25.1
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/dg1: map/unmap pll clocks
On Mon, Nov 02, 2020 at 08:59:32AM -0800, Aditya Swarup wrote:
On 10/26/20 9:35 PM, Lucas De Marchi wrote:
On Mon, Oct 26, 2020 at 09:32:26PM -0700, Lucas De Marchi wrote:
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functions for DG1 since it doesn't share much with ICL/TGL
anymore.
The previous values were correct for PHY A and B since they were using
the same register as before and the bitfields were matching.
v2: Add comment and try to simplify DG1_DPCLKA* macros by reusing
previous ones
Cc: José Roberto de Souza
Cc: Clinton Taylor
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
Matt, you had given you R-b but since I changed the macros considerably,
please take a look if it still stands.
thanks
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 92 +++-
drivers/gpu/drm/i915/display/intel_display.c | 25 +-
drivers/gpu/drm/i915/i915_reg.h | 23 +
3 files changed, 136 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 63380b166c25..f6343a950b3a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2970,6 +2970,38 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct
drm_i915_private *dev_priv,
return 0;
}
+static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
+
+ /*
+ * If we fail this, something went very wrong: first 2 PLLs should be
+ * used by first 2 phys and last 2 PLLs by last phys
+ */
+ if (WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
+ (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
+ return;
+
+ mutex_lock(_priv->dpll.lock);
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ WARN_ON((val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+
+ mutex_unlock(_priv->dpll.lock);
+}
+
static void icl_map_plls_to_ports(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -3017,6 +3049,19 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
mutex_unlock(_priv->dpll.lock);
}
+static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ mutex_lock(_priv->dpll.lock);
+
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+ DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+ mutex_unlock(_priv->dpll.lock);
+}
+
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -3032,6 +3077,40 @@ static void icl_unmap_plls_to_ports(struct intel_encoder
*encoder)
mutex_unlock(_priv->dpll.lock);
}
+static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
+ u32 port_mask, bool ddi_clk_needed)
+{
+ enum port port;
+ u32 val;
+
+ for_each_port_masked(port, port_mask) {
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ bool ddi_clk_off;
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+
+ if (ddi_clk_needed == !ddi_clk_off)
+ continue;
+
+ /*
+ * Punt on the case now where clock is gated, but it would
+ * be needed by the port. Something else is really broken then.
+ */
+ if (ddi_clk_needed) {
+ WARN(1, "ddi_clk_needed=%u ddi_clk_off=%u phy=%u\n",
+ ddi_clk_needed, ddi_clk_off, phy);
+ continue;
+ }
+
+ DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate
it\n",
+ phy_name(phy));
+
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ }
+}
+
static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
u32 port_mask, bool ddi_clk_needed)
{
@@ -3114,7 +3193,10 @@ void
[Intel-gfx] [PATCH] drm/i915/tgl: Fix typo during output setup
Fix a typo that led to some MST short pulse event handling issue (the
short pulse event was handled for both encoder instances, each having
its own state).
Fixes: 1d8ca002456b6 ("drm/i915: Add PORT_TCn aliases to enum port")
Cc: Ville Syrjälä
Cc: Lucas De Marchi
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cddbda5303ff..19a4d81558c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17223,7 +17223,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_TC1);
intel_ddi_init(dev_priv, PORT_TC2);
- intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC3);
intel_ddi_init(dev_priv, PORT_TC4);
intel_ddi_init(dev_priv, PORT_TC5);
intel_ddi_init(dev_priv, PORT_TC6);
--
2.25.1
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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Remove invalid PCI ID
> -Original Message- > From: Ville Syrjälä > Sent: Monday, November 2, 2020 9:29 AM > To: Srivatsa, Anusha > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/i915/ehl: Remove invalid PCI ID > > On Fri, Oct 30, 2020 at 02:26:14PM -0700, Anusha Srivatsa wrote: > > Update the EHL PCI IDs from BSpec. > > Remove the invalid ones. > > > > Cc: Ville Syrjälä > > Signed-off-by: Anusha Srivatsa > > Reviewed-by: Ville Syrjälä > > Pls sort out the ci fail so we can merge this. Merged. Anusha > > --- > > include/drm/i915_pciids.h | 1 - > > 1 file changed, 1 deletion(-) > > > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > > index 3b5ed1e4f3ec..28428e08a8d3 100644 > > --- a/include/drm/i915_pciids.h > > +++ b/include/drm/i915_pciids.h > > @@ -584,7 +584,6 @@ > > > > /* EHL */ > > #define INTEL_EHL_IDS(info) \ > > - INTEL_VGA_DEVICE(0x4500, info), \ > > INTEL_VGA_DEVICE(0x4571, info), \ > > INTEL_VGA_DEVICE(0x4551, info), \ > > INTEL_VGA_DEVICE(0x4541, info), \ > > -- > > 2.25.0 > > -- > Ville Syrjälä > Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-next: build failure after merge of the drm-intel-fixes tree
On Wed, Nov 04, 2020 at 09:37:05AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-intel-fixes tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/gpu/drm/i915/gt/intel_lrc.c: In function 'gen12_emit_fini_breadcrumb':
> drivers/gpu/drm/i915/gt/intel_lrc.c:4998:31: error: implicit declaration of
> function '__gen8_emit_flush_dw'; did you mean 'gen8_emit_flush'?
> [-Werror=implicit-function-declaration]
> 4998 | cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
> | ^~~~
> | gen8_emit_flush
> drivers/gpu/drm/i915/gt/intel_lrc.c:4998:31: warning: passing argument 2 of
> 'emit_xcs_breadcrumb' makes pointer from integer without a cast
> [-Wint-conversion]
> 4998 | cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
> | ^
> | |
> | int
> drivers/gpu/drm/i915/gt/intel_lrc.c:4902:63: note: expected 'u32 *' {aka
> 'unsigned int *'} but argument is of type 'int'
> 4902 | static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
> | ~^~
>
> Caused by commit
>
> c94d65d2ff6d ("drm/i915/gt: Flush xcs before tgl breadcrumbs")
>
> I have reverted that commit for today.
Sorry for the trouble. Dependency picked to drm-intel-fixes now.
Thanks for reporting,
Rodrigo.
>
> --
> Cheers,
> Stephen Rothwell
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3)
== Series Details == Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3) URL : https://patchwork.freedesktop.org/series/83373/ State : success == Summary == CI Bug Log - changes from CI_DRM_9255_full -> Patchwork_18843_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9255_full and Patchwork_18843_full: ### New CI tests (1) ### * boot: - Statuses : 175 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18843_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_blits@basic: - shard-skl: [PASS][1] -> [TIMEOUT][2] ([i915#2502]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl6/igt@gem_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl3/igt@gem_bl...@basic.html * igt@i915_pm_rpm@gem-mmap-type@uc: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl4/igt@i915_pm_rpm@gem-mmap-t...@uc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl2/igt@i915_pm_rpm@gem-mmap-t...@uc.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-kbl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-64x21-sliding.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-64x21-sliding.html * igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-glk6/igt@kms_cursor_edge_w...@pipe-c-256x256-right-edge.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-glk7/igt@kms_cursor_edge_w...@pipe-c-256x256-right-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#2346]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl10/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl6/igt@kms_flip@flip-vs-expired-vbl...@b-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl8/igt@kms_flip@flip-vs-expired-vbl...@b-edp1.html * igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a2: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2122]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-glk5/igt@kms_flip@plain-flip-ts-check-interrupti...@b-hdmi-a2.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-glk3/igt@kms_flip@plain-flip-ts-check-interrupti...@b-hdmi-a2.html * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#2122]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl2/igt@kms_flip@plain-flip-ts-check-interrupti...@c-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl1/igt@kms_flip@plain-flip-ts-check-interrupti...@c-edp1.html * igt@kms_flip_tiling@flip-to-yf-tiled: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-kbl3/igt@kms_flip_til...@flip-to-yf-tiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-kbl6/igt@kms_flip_til...@flip-to-yf-tiled.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl6/igt@kms_...@bpc-switch-dpms.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl3/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Include fb modidier in state dumps
== Series Details == Series: drm/i915: Include fb modidier in state dumps URL : https://patchwork.freedesktop.org/series/83438/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9255_full -> Patchwork_18842_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18842_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18842_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18842_full: ### IGT changes ### Possible regressions * igt@gem_exec_fence@invalid-fence-array: - shard-snb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-snb6/igt@gem_exec_fe...@invalid-fence-array.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-snb6/igt@gem_exec_fe...@invalid-fence-array.html Warnings * igt@kms_flip@flip-vs-suspend-interruptible@d-edp1: - shard-tglb: [DMESG-WARN][3] ([i915#2411]) -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-tglb8/igt@kms_flip@flip-vs-suspend-interrupti...@d-edp1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-tglb7/igt@kms_flip@flip-vs-suspend-interrupti...@d-edp1.html New tests - New tests have been introduced between CI_DRM_9255_full and Patchwork_18842_full: ### New CI tests (1) ### * boot: - Statuses : 175 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18842_full that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl10/igt@core_hotunp...@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-skl10/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_create@forked: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-glk1/igt@gem_exec_cre...@forked.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-glk7/igt@gem_exec_cre...@forked.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1436] / [i915#716]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl1/igt@gen9_exec_pa...@allowed-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-skl8/igt@gen9_exec_pa...@allowed-all.html * igt@kms_cursor_crc@pipe-b-cursor-128x128-random: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-128x128-random.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-128x128-random.html * igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-glk6/igt@kms_cursor_edge_w...@pipe-c-256x256-right-edge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-glk6/igt@kms_cursor_edge_w...@pipe-c-256x256-right-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#2346]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl10/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1635] / [i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-apl7/igt@kms_flip@absolute-wf_vblank-interrupti...@a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-apl6/igt@kms_flip@absolute-wf_vblank-interrupti...@a-dp1.html * igt@kms_flip@plain-flip-ts-check@a-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#2122]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl7/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/shard-skl6/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html *
[Intel-gfx] linux-next: build failure after merge of the drm-intel-fixes tree
Hi all,
After merging the drm-intel-fixes tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/gpu/drm/i915/gt/intel_lrc.c: In function 'gen12_emit_fini_breadcrumb':
drivers/gpu/drm/i915/gt/intel_lrc.c:4998:31: error: implicit declaration of
function '__gen8_emit_flush_dw'; did you mean 'gen8_emit_flush'?
[-Werror=implicit-function-declaration]
4998 | cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
| ^~~~
| gen8_emit_flush
drivers/gpu/drm/i915/gt/intel_lrc.c:4998:31: warning: passing argument 2 of
'emit_xcs_breadcrumb' makes pointer from integer without a cast
[-Wint-conversion]
4998 | cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
| ^
| |
| int
drivers/gpu/drm/i915/gt/intel_lrc.c:4902:63: note: expected 'u32 *' {aka
'unsigned int *'} but argument is of type 'int'
4902 | static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
| ~^~
Caused by commit
c94d65d2ff6d ("drm/i915/gt: Flush xcs before tgl breadcrumbs")
I have reverted that commit for today.
--
Cheers,
Stephen Rothwell
pgpKskYJwwc_a.pgp
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Re: [Intel-gfx] [PATCH] drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms
On Fri, Oct 30, 2020 at 11:46:58AM +0530, Anshuman Gupta wrote:
> From: Bob Paauwe
>
> The WA specifies that we need to toggle a SDE chicken bit on and then
> off as the final step in preparation for s0ix entry.
>
> Bspec: 33450
> Bspec: 8402
>
> However, something is happening after we toggle the bit that causes
> the WA to be invalidated. This makes dispcnlunit1_cp_xosc_clkreq
> active being already in s0ix state i.e SLP_S0 counter incremented.
> Tweaking the Wa_14010685332 by setting the bit on suspend and clearing
> it on resume turns down the dispcnlunit1_cp_xosc_clkreq.
> B.Spec has Documented this tweaked sequence of WA as an alternative.
> Let keep this tweaked WA for Gen11 platforms and keep untweaked WA for
> other platforms which never observed this issue.
>
> v2 (MattR):
> - Change the comment on the workaround to give PCH names rather than
>platform names. Although the bspec is setup to list workarounds by
>platform, the hardware team has confirmed that the actual issue being
>worked around here is something that was introduced back in the
>Cannon Lake PCH and carried forward to subsequent PCH's.
> - Extend the untweaked version of the workaround to include PCH_CNP as
>well. Note that since PCH_CNP is used to represent CMP, this will
>apply on CML and some variants of RKL too.
> - Cap the untweaked version of the workaround so that it won't apply to
>"fake" PCH's (i.e., DG1). The issue we're working around really is
>an issue in the PCH itself, not the South Display, so it shouldn't
>apply when there isn't a real PCH.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Bob Paauwe
> Signed-off-by: Anshuman Gupta
> Signed-off-by: Matt Roper
> ---
> .../drm/i915/display/intel_display_power.c| 21 +--
> drivers/gpu/drm/i915/i915_irq.c | 6 --
> 2 files changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 689922480661..d2a6518329d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5858,17 +5858,34 @@ static void intel_power_domains_verify_state(struct
> drm_i915_private *i915)
>
> void intel_display_power_suspend_late(struct drm_i915_private *i915)
> {
> - if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915))
> + u32 val;
> +
> + if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> bxt_enable_dc9(i915);
> - else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> + /* Tweaked Wa_14010685332:icp,jsp,mcc */
> + if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> PCH_MCC) {
> + val = intel_de_read(i915, SOUTH_CHICKEN1);
> + val |= SBCLK_RUN_REFCLK_DIS;
> + intel_de_write(i915, SOUTH_CHICKEN1, val);
could we use intel_de_rmw here?
> + }
> + } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_enable_pc8(i915);
> + }
> }
>
> void intel_display_power_resume_early(struct drm_i915_private *i915)
> {
> + u32 val;
> +
> if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> gen9_sanitize_dc_state(i915);
> bxt_disable_dc9(i915);
> + /* Tweaked Wa_14010685332:icp,jsp,mcc */
> + if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> PCH_MCC) {
> + val = intel_de_read(i915, SOUTH_CHICKEN1);
> + val &= ~SBCLK_RUN_REFCLK_DIS;
> + intel_de_write(i915, SOUTH_CHICKEN1, val);
and here?
sorry for not having spotted that sooner.
> + }
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_disable_pc8(i915);
> }
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dc33c96d741d..410c03624c6a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3055,8 +3055,10 @@ static void gen11_display_irq_reset(struct
> drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
> + /* Wa_14010685332:cnp/cmp,tgp,adp */
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> + INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
>SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> --
> 2.26.2
>
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Re: [Intel-gfx] [PATCH] drm/i915/tgl, rkl, dg1: Apply WA_1406941453 to TGL, RKL and DG1
On 11/2/20 5:59 PM, Swathi Dhanavanthri wrote:
This workaround is applicable only for tgl,rkl and dg1.
Bspec: 52890, 53273, 53508.
Signed-off-by: Swathi Dhanavanthri
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fed9503a7c4e..45c082070bd9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1768,6 +1768,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
*/
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
+
+ /* Wa_1406941453:tgl,rkl,dg1 */
+ wa_masked_en(wal,
+GEN10_SAMPLER_MODE,
+ENABLE_SMALLPL);
}
if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
@@ -1806,13 +1811,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
FF_DOP_CLOCK_GATE_DISABLE);
}
- if (IS_GEN(i915, 12)) {
- /* Wa_1406941453:gen12 */
- wa_masked_en(wal,
-GEN10_SAMPLER_MODE,
-ENABLE_SMALLPL);
- }
-
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
Reviewed-by: Clint Taylor
-Clint
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gvt: Remove incorrect kerneldoc marking
== Series Details ==
Series: drm/i915/gvt: Remove incorrect kerneldoc marking
URL : https://patchwork.freedesktop.org/series/83451/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9256 -> Patchwork_18846
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_18846 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18846, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_18846:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
New tests
-
New tests have been introduced between CI_DRM_9256 and Patchwork_18846:
### New CI tests (1) ###
* boot:
- Statuses : 38 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18846 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +2 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-icl-u2/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/fi-icl-u2/igt@i915_module_l...@reload.html
- fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-byt-j1900/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/fi-byt-j1900/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-apl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#1635] /
[i915#1982])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem:[PASS][9] -> [DMESG-WARN][10] ([i915#2605])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-skl-lmem/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/fi-skl-lmem/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@active:
- fi-bsw-n3050: [PASS][11] -> [DMESG-FAIL][12] ([i915#541])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-bsw-n3050/igt@i915_selftest@l...@active.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/fi-bsw-n3050/igt@i915_selftest@l...@active.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][13] -> [FAIL][14] ([i915#1161] / [i915#262])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [INCOMPLETE][15] ([i915#1635]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18846/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2417]: https://gitlab.freedesktop.org/drm/intel/issues/2417
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (43 -> 38)
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ehl: Implement W/A 22010492432 (rev2)
== Series Details == Series: drm/i915/ehl: Implement W/A 22010492432 (rev2) URL : https://patchwork.freedesktop.org/series/83135/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9253_full -> Patchwork_18840_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18840_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18840_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18840_full: ### IGT changes ### Possible regressions * igt@gem_exec_create@forked: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-tglb5/igt@gem_exec_cre...@forked.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-tglb6/igt@gem_exec_cre...@forked.html Warnings * igt@kms_flip@flip-vs-suspend-interruptible@d-edp1: - shard-tglb: [DMESG-WARN][3] ([i915#2411]) -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-tglb1/igt@kms_flip@flip-vs-suspend-interrupti...@d-edp1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-tglb6/igt@kms_flip@flip-vs-suspend-interrupti...@d-edp1.html New tests - New tests have been introduced between CI_DRM_9253_full and Patchwork_18840_full: ### New CI tests (1) ### * boot: - Statuses : 175 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18840_full that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +9 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-skl10/igt@core_hotunp...@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-skl1/igt@core_hotunp...@unbind-rebind.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-kbl2/igt@gem_ctx_isolation@preservation...@bcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-kbl2/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_eio@kms: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-snb7/igt@gem_...@kms.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-snb7/igt@gem_...@kms.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][11] -> [SKIP][12] ([i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-tglb1/igt@gem_huc_c...@huc-copy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_partial_pwrite_pread@writes-after-reads-uncached: - shard-snb: [PASS][13] -> [INCOMPLETE][14] ([i915#82]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-snb6/igt@gem_partial_pwrite_pr...@writes-after-reads-uncached.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-snb2/igt@gem_partial_pwrite_pr...@writes-after-reads-uncached.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1436] / [i915#716]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-skl9/igt@gen9_exec_pa...@allowed-all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-skl8/igt@gen9_exec_pa...@allowed-all.html * igt@kms_big_fb@y-tiled-16bpp-rotate-0: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-kbl1/igt@kms_big...@y-tiled-16bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-kbl4/igt@kms_big...@y-tiled-16bpp-rotate-0.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#54]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#300]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[Intel-gfx] [PATCH] drm/i915/gvt: Remove incorrect kerneldoc marking
Just a normal comment, not a kerneldoc function description. drivers/gpu/drm/i915/gvt/handlers.c:1666: warning: Function parameter or member 'vgpu' not described in 'bxt_ppat_low_write' drivers/gpu/drm/i915/gvt/handlers.c:1666: warning: Function parameter or member 'offset' not described in 'bxt_ppat_low_write' drivers/gpu/drm/i915/gvt/handlers.c:1666: warning: Function parameter or member 'p_data' not described in 'bxt_ppat_low_write' drivers/gpu/drm/i915/gvt/handlers.c:1666: warning: Function parameter or member 'bytes' not described in 'bxt_ppat_low_write' Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index ce93079cf933..4ddc9c847470 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1651,7 +1651,7 @@ static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, return 0; } -/** +/* * FixMe: * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83446/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9256 -> Patchwork_18845
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/index.html
New tests
-
New tests have been introduced between CI_DRM_9256 and Patchwork_18845:
### New CI tests (1) ###
* boot:
- Statuses : 34 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18845 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_hangman@error-state-basic:
- fi-gdg-551: [PASS][1] -> [INCOMPLETE][2] ([i915#172])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-gdg-551/igt@i915_hang...@error-state-basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/fi-gdg-551/igt@i915_hang...@error-state-basic.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem:[PASS][5] -> [DMESG-WARN][6] ([i915#2605])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-skl-lmem/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/fi-skl-lmem/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [DMESG-FAIL][8] ([i915#165])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [INCOMPLETE][13] ([i915#1635]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18845/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#172]: https://gitlab.freedesktop.org/drm/intel/issues/172
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
Participating hosts (43 -> 34)
--
Missing(9): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-glk-dsi fi-bsw-cyan
fi-bwr-2160 fi-snb-2520m fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9256 -> Patchwork_18845
CI-20190529: 20190529
CI_DRM_9256: f6c52739f73952279713aec3c98d9805e1c1a3ae @
git://anongit.freedesktop.org/gfx-ci/linux
Re: [Intel-gfx] [PATCH] drm/i915/display: Use initial_fastset_check() to compute and apply the initial PSR state
On Mon, Nov 02, 2020 at 02:10:48PM -0800, José Roberto de Souza wrote:
> Replace the previous approach to force compute the initial PSR state
> after i915 take over from firmware by the better and recently added
> initial_fastset_check() hook.
>
> Cc: Imre Deak
> Signed-off-by: José Roberto de Souza
Looks ok to me:
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 1 -
> drivers/gpu/drm/i915/display/intel_display.c | 2 -
> drivers/gpu/drm/i915/display/intel_dp.c | 6 +++
> drivers/gpu/drm/i915/display/intel_psr.c | 41
> drivers/gpu/drm/i915/display/intel_psr.h | 4 --
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> 6 files changed, 6 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 86be032bcf96..63d8d6840655 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -133,7 +133,6 @@ int intel_digital_connector_atomic_check(struct
> drm_connector *conn,
> struct drm_crtc_state *crtc_state;
>
> intel_hdcp_atomic_check(conn, old_state, new_state);
> - intel_psr_atomic_check(conn, old_state, new_state);
>
> if (!new_state->crtc)
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index cddbda5303ff..3c3adaee7b49 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18373,8 +18373,6 @@ int intel_modeset_init(struct drm_i915_private *i915)
>
> intel_init_ipc(i915);
>
> - intel_psr_set_force_mode_changed(i915->psr.dp);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index cf09aca7607b..3b0dbda5919a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3778,6 +3778,12 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
> return false;
> }
>
> + if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
> + drm_dbg_kms(>drm, "Forcing full modeset to compute PSR
> state\n");
> + crtc_state->uapi.mode_changed = true;
> + return false;
> + }
> +
> return true;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1576c3722d0b..b3631b722de3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1024,8 +1024,6 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp)
> return;
>
> - dev_priv->psr.force_mode_changed = false;
> -
> if (!crtc_state->has_psr)
> return;
>
> @@ -1334,8 +1332,6 @@ void intel_psr_update(struct intel_dp *intel_dp,
> if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
> return;
>
> - dev_priv->psr.force_mode_changed = false;
> -
> mutex_lock(_priv->psr.lock);
>
> enable = crtc_state->has_psr;
> @@ -1869,40 +1865,3 @@ bool intel_psr_enabled(struct intel_dp *intel_dp)
>
> return ret;
> }
> -
> -void intel_psr_atomic_check(struct drm_connector *connector,
> - struct drm_connector_state *old_state,
> - struct drm_connector_state *new_state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> - struct intel_connector *intel_connector;
> - struct intel_digital_port *dig_port;
> - struct drm_crtc_state *crtc_state;
> -
> - if (!CAN_PSR(dev_priv) || !new_state->crtc ||
> - !dev_priv->psr.force_mode_changed)
> - return;
> -
> - intel_connector = to_intel_connector(connector);
> - dig_port = enc_to_dig_port(to_intel_encoder(new_state->best_encoder));
> - if (dev_priv->psr.dp != _port->dp)
> - return;
> -
> - crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
> -new_state->crtc);
> - crtc_state->mode_changed = true;
> -}
> -
> -void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *dev_priv;
> -
> - if (!intel_dp)
> - return;
> -
> - dev_priv = dp_to_i915(intel_dp);
> - if (!CAN_PSR(dev_priv) || intel_dp != dev_priv->psr.dp)
> - return;
> -
> - dev_priv->psr.force_mode_changed = true;
> -}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 3eca9dcec3c0..0a517978e8af 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -43,10 +43,6 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
> int
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v2,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/83446/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83446/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0a126bd8ea31 drm/i915/display: Support PSR Multiple Transcoders
-:1565: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#1565: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1704:
+ if (encoder->type == INTEL_OUTPUT_EDP && CAN_PSR(intel_dp)) {
+
-:1760: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible
side-effects?
#1760: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21:
+#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) &&
intel_dp->psr.sink_support)
total: 0 errors, 0 warnings, 2 checks, 1800 lines checked
546b794ed5a7 drm/i915/display: Support Multiple Transcoders' PSR status on
debugfs
___
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[Intel-gfx] [PATCH v2 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
---
.../drm/i915/display/intel_display_debugfs.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 8402e6ac9f76..37805615a221 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2093,6 +2093,23 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (connector->status != connector_status_connected)
+ return -ENODEV;
+
+ if (!HAS_PSR(dev_priv))
+ return -ENODEV;
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
@@ -2268,6 +2285,12 @@ int intel_connector_debugfs_add(struct drm_connector
*connector)
connector, _psr_sink_status_fops);
}
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ debugfs_create_file("i915_psr_status", 0444, root,
+ connector, _psr_status_fops);
+ }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
2.25.0
___
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[Intel-gfx] [PATCH v2 1/2] drm/i915/display: Support PSR Multiple Transcoders
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR.
v2: Fix indentation and add comments
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
.../drm/i915/display/intel_display_debugfs.c | 111 +++-
.../drm/i915/display/intel_display_types.h| 39 ++
drivers/gpu/drm/i915/display/intel_dp.c | 21 +-
drivers/gpu/drm/i915/display/intel_psr.c | 614 +-
drivers/gpu/drm/i915/display/intel_psr.h | 16 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 39 --
drivers/gpu/drm/i915/i915_irq.c | 47 +-
10 files changed, 504 insertions(+), 400 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 19b16517a502..983781ce3683 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4127,7 +4127,10 @@ static void intel_ddi_update_pipe_dp(struct
intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
+ //TODO: move PSR related functions into intel_psr_update()
+ intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
intel_psr_update(intel_dp, crtc_state, conn_state);
+
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_update(intel_dp, crtc_state);
@@ -5275,6 +5278,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
goto err;
dig_port->hpd_pulse = intel_dp_hpd_pulse;
+
+ intel_psr_init(_port->dp);
}
/* In theory we don't need the encoder->type check, but leave it just in
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cddbda5303ff..be5238e5d587 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15506,8 +15506,6 @@ static void commit_pipe_config(struct
intel_atomic_state *state,
if (new_crtc_state->update_pipe)
intel_pipe_fastset(old_crtc_state, new_crtc_state);
-
- intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
if (dev_priv->display.atomic_update_watermarks)
@@ -17435,8 +17433,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_dvo_init(dev_priv);
}
- intel_psr_init(dev_priv);
-
for_each_intel_encoder(_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
@@ -18373,7 +18369,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
intel_init_ipc(i915);
- intel_psr_set_force_mode_changed(i915->psr.dp);
+ intel_psr_set_force_mode_changed(i915);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cfb4c1474982..8402e6ac9f76 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -248,18 +248,17 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
"sink internal error",
};
struct drm_connector *connector = m->private;
- struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
int ret;
- if (!CAN_PSR(dev_priv)) {
- seq_puts(m, "PSR Unsupported\n");
+ if (connector->status != connector_status_connected)
return -ENODEV;
- }
- if (connector->status != connector_status_connected)
+ if (!CAN_PSR(intel_dp)) {
+ seq_puts(m, "PSR Unsupported\n");
return -ENODEV;
+ }
ret = drm_dp_dpcd_readb(_dp->aux, DP_PSR_STATUS, );
@@ -279,12 +278,13 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static void
-psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
+psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
{
u32 val, status_val;
const char *status = "unknown";
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (dev_priv->psr.psr2_enabled) {
+
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Pass intel_atomic_state to skl_build_pipe_wm()
== Series Details ==
Series: series starting with [1/3] drm/i915: Pass intel_atomic_state to
skl_build_pipe_wm()
URL : https://patchwork.freedesktop.org/series/83445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9256 -> Patchwork_18844
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/index.html
New tests
-
New tests have been introduced between CI_DRM_9256 and Patchwork_18844:
### New CI tests (1) ###
* boot:
- Statuses : 38 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18844 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [INCOMPLETE][7] ([i915#1635]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9256/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9256 -> Patchwork_18844
CI-20190529: 20190529
CI_DRM_9256: f6c52739f73952279713aec3c98d9805e1c1a3ae @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5831: b6247cc06d76b48ec2a3a0b13ffbd25aec8a42ff @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18844: 04db1efa9d4d3890b476e7da849620ed187c37e1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
04db1efa9d4d drm/i915: Pimp the watermark documentation a bit
82fba54d07f0 drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from
skl+ wm code
32d744b404ab drm/i915: Pass intel_atomic_state to skl_build_pipe_wm()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18844/index.html
___
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Re: [Intel-gfx] [patch V3 22/37] highmem: High implementation details and document API
On Tue, Nov 03 2020 at 09:48, Linus Torvalds wrote: > I have no complaints about the patch, but it strikes me that if people > want to actually have much better debug coverage, this is where it > should be (I like the "every other address" thing too, don't get me > wrong). > > In particular, instead of these PageHighMem(page) tests, I think > something like this would be better: > >#ifdef CONFIG_DEBUG_HIGHMEM > #define page_use_kmap(page) ((page),1) >#else > #define page_use_kmap(page) PageHighMem(page) >#endif > > adn then replace those "if (!PageHighMem(page))" tests with "if > (!page_use_kmap())" instead. > > IOW, in debug mode, it would _always_ remap the page, whether it's > highmem or not. That would really stress the highmem code and find any > fragilities. Yes, that makes a lot of sense. We just have to avoid that for the architectures with aliasing issues. > Anyway, this is all sepatrate from the series, which still looks fine > to me. Just a reaction to seeing the patch, and Thomas' earlier > mention that the highmem debugging doesn't actually do much. Right, forcing it for both kmap and kmap_local is straight forward. I'll cook a patch on top for that. Thanks, tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Pass intel_atomic_state to skl_build_pipe_wm()
== Series Details == Series: series starting with [1/3] drm/i915: Pass intel_atomic_state to skl_build_pipe_wm() URL : https://patchwork.freedesktop.org/series/83445/ State : warning == Summary == $ dim checkpatch origin/drm-tip 32d744b404ab drm/i915: Pass intel_atomic_state to skl_build_pipe_wm() 82fba54d07f0 drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code -:18: WARNING:TYPO_SPELLING: 'swithcing' may be misspelled - perhaps 'switching'? #18: easily do by swithcing to the g4x/vlv "raw" watermark approach. total: 0 errors, 1 warnings, 0 checks, 98 lines checked 04db1efa9d4d drm/i915: Pimp the watermark documentation a bit ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Pimp the watermark documentation a bit
From: Ville Syrjälä
Document what each of the "raw" vs. "optimal" vs. "intermediate"
watermarks do.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 48 ++-
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6b249969c394..b977e70e34d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -737,25 +737,34 @@ struct g4x_wm_state {
struct intel_crtc_wm_state {
union {
+ /*
+* raw:
+* The "raw" watermark values produced by the formula
+* given the plane's current state. They do not consider
+* how much FIFO is actually allocated for each plane.
+*
+* optimal:
+* The "optimal" watermark values given the current
+* state of the planes and the amount of FIFO
+* allocated to each, ignoring any previous state
+* of the planes.
+*
+* intermediate:
+* The "intermediate" watermark values when transitioning
+* between the old and new "optimal" values. Used when
+* the watermark registers are single buffered and hence
+* their state changes asynchronously with regards to the
+* actual plane registers. These are essentially the
+* worst case combination of the old and new "optimal"
+* watermarks, which are therefore safe to use when the
+* plane is in either its old or new state.
+*/
struct {
- /*
-* Intermediate watermarks; these can be
-* programmed immediately since they satisfy
-* both the current configuration we're
-* switching away from and the new
-* configuration we're switching to.
-*/
struct intel_pipe_wm intermediate;
-
- /*
-* Optimal watermarks, programmed post-vblank
-* when this state is committed.
-*/
struct intel_pipe_wm optimal;
} ilk;
struct {
- /* "raw" watermarks */
struct skl_pipe_wm raw;
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
@@ -765,22 +774,15 @@ struct intel_crtc_wm_state {
} skl;
struct {
- /* "raw" watermarks (not inverted) */
- struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
- /* intermediate watermarks (inverted) */
- struct vlv_wm_state intermediate;
- /* optimal watermarks (inverted) */
- struct vlv_wm_state optimal;
- /* display FIFO split */
+ struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not
inverted */
+ struct vlv_wm_state intermediate; /* inverted */
+ struct vlv_wm_state optimal; /* inverted */
struct vlv_fifo_state fifo_state;
} vlv;
struct {
- /* "raw" watermarks */
struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
- /* intermediate watermarks */
struct g4x_wm_state intermediate;
- /* optimal watermarks */
struct g4x_wm_state optimal;
} g4x;
};
--
2.26.2
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[Intel-gfx] [PATCH 2/3] drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code
From: Ville Syrjälä
intel_atomic_crtc_state_for_each_plane_state() peeks at the
plane's current state without holding the plane's mutex, trusting
that the crtc's mutex will protect it. In practice that does work
since our planes can't move between pipes, but it sets a bad
example. intel_atomic_crtc_state_for_each_plane_state() also
relies on crtc_state.uapi.plane_mask which may be full of lies
when it comes to the bigjoiner stuff, so soon we can't use it as
is anyway. So best to just get rid of it entirely. Which we can
easily do by swithcing to the g4x/vlv "raw" watermark approach.
Later on we should even be able to move the "raw" watermark
computation into the normal .plane_check() code, leaving only
the merging/clamping of the final watermarks to the later
stages. But that will require adjusting the ilk+ wm code
similarly as well.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 2 +
drivers/gpu/drm/i915/intel_pm.c | 41 +++
2 files changed, 27 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..6b249969c394 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -755,6 +755,8 @@ struct intel_crtc_wm_state {
} ilk;
struct {
+ /* "raw" watermarks */
+ struct skl_pipe_wm raw;
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
struct skl_ddb_entry ddb;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 47b27ee54568..6b4838efcd59 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5478,7 +5478,7 @@ static int skl_build_plane_wm_single(struct
intel_crtc_state *crtc_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct skl_plane_wm *wm = _state->wm.skl.optimal.planes[plane_id];
+ struct skl_plane_wm *wm = _state->wm.skl.raw.planes[plane_id];
struct skl_wm_params wm_params;
int ret;
@@ -5501,7 +5501,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state
*crtc_state,
const struct intel_plane_state *plane_state,
enum plane_id plane_id)
{
- struct skl_plane_wm *wm = _state->wm.skl.optimal.planes[plane_id];
+ struct skl_plane_wm *wm = _state->wm.skl.raw.planes[plane_id];
struct skl_wm_params wm_params;
int ret;
@@ -5522,10 +5522,13 @@ static int skl_build_plane_wm(struct intel_crtc_state
*crtc_state,
const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- const struct drm_framebuffer *fb = plane_state->hw.fb;
enum plane_id plane_id = plane->id;
+ struct skl_plane_wm *wm = _state->wm.skl.raw.planes[plane_id];
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
int ret;
+ memset(wm, 0, sizeof(*wm));
+
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
@@ -5547,10 +5550,14 @@ static int skl_build_plane_wm(struct intel_crtc_state
*crtc_state,
static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ struct skl_plane_wm *wm = _state->wm.skl.raw.planes[plane_id];
int ret;
+ memset(wm, 0, sizeof(*wm));
+
/* Watermarks calculated in master */
if (plane_state->planar_slave)
return 0;
@@ -5589,19 +5596,18 @@ static int skl_build_pipe_wm(struct intel_atomic_state
*state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct skl_pipe_wm *pipe_wm = _state->wm.skl.optimal;
- struct intel_plane *plane;
const struct intel_plane_state *plane_state;
- int ret;
+ struct intel_plane *plane;
+ int ret, i;
- /*
-* We'll only calculate watermarks for planes that are actually
-* enabled, so make sure all other planes are set as disabled.
-*/
- memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
-
-
[Intel-gfx] [PATCH 1/3] drm/i915: Pass intel_atomic_state to skl_build_pipe_wm()
From: Ville Syrjälä
Pass the whole intel_atomic_state to skl_build_pipe_wm() so we
can start to iterate stuff containerd in the commit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f54375b11964..47b27ee54568 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5583,9 +5583,12 @@ static int icl_build_plane_wm(struct intel_crtc_state
*crtc_state,
return 0;
}
-static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
+static int skl_build_pipe_wm(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct skl_pipe_wm *pipe_wm = _state->wm.skl.optimal;
struct intel_plane *plane;
const struct intel_plane_state *plane_state;
@@ -6092,7 +6095,6 @@ skl_compute_wm(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
struct intel_crtc_state *new_crtc_state;
- struct intel_crtc_state *old_crtc_state;
int ret, i;
ret = skl_ddb_add_affected_pipes(state);
@@ -6104,9 +6106,8 @@ skl_compute_wm(struct intel_atomic_state *state)
* Note that skl_ddb_add_affected_pipes may have added more CRTC's that
* weren't otherwise being modified if pipe allocations had to change.
*/
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
- new_crtc_state, i) {
- ret = skl_build_pipe_wm(new_crtc_state);
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ ret = skl_build_pipe_wm(state, crtc);
if (ret)
return ret;
}
@@ -6124,8 +6125,7 @@ skl_compute_wm(struct intel_atomic_state *state)
* based on how much ddb is available. Now we can actually
* check if the final watermarks changed.
*/
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
- new_crtc_state, i) {
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
ret = skl_wm_add_affected_planes(state, crtc);
if (ret)
return ret;
--
2.26.2
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Re: [Intel-gfx] [PATCH v3] vfio/pci: Bypass IGD init in case of -ENODEV
On Tue, 3 Nov 2020 02:01:20 +0800
Fred Gao wrote:
> Bypass the IGD initialization when -ENODEV returns,
> that should be the case if opregion is not available for IGD
> or within discrete graphics device's option ROM,
> or host/lpc bridge is not found.
>
> Then use of -ENODEV here means no special device resources found
> which needs special care for VFIO, but we still allow other normal
> device resource access.
>
> Cc: Zhenyu Wang
> Cc: Xiong Zhang
> Cc: Hang Yuan
> Cc: Stuart Summers
> Signed-off-by: Fred Gao
> ---
> drivers/vfio/pci/vfio_pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to vfio for-linus branch for v5.10. Thanks,
Alex
>
> diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c
> index f634c81998bb..c88cf9937469 100644
> --- a/drivers/vfio/pci/vfio_pci.c
> +++ b/drivers/vfio/pci/vfio_pci.c
> @@ -341,7 +341,7 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev)
> pdev->vendor == PCI_VENDOR_ID_INTEL &&
> IS_ENABLED(CONFIG_VFIO_PCI_IGD)) {
> ret = vfio_pci_igd_init(vdev);
> - if (ret) {
> + if (ret && ret != -ENODEV) {
> pci_warn(pdev, "Failed to setup Intel IGD regions\n");
> goto disable_exit;
> }
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Re: [Intel-gfx] [patch V3 22/37] highmem: High implementation details and document API
On Tue, Nov 3, 2020 at 2:33 AM Thomas Gleixner wrote:
>
> +static inline void *kmap(struct page *page)
> +{
> + void *addr;
> +
> + might_sleep();
> + if (!PageHighMem(page))
> + addr = page_address(page);
> + else
> + addr = kmap_high(page);
> + kmap_flush_tlb((unsigned long)addr);
> + return addr;
> +}
> +
> +static inline void kunmap(struct page *page)
> +{
> + might_sleep();
> + if (!PageHighMem(page))
> + return;
> + kunmap_high(page);
> +}
I have no complaints about the patch, but it strikes me that if people
want to actually have much better debug coverage, this is where it
should be (I like the "every other address" thing too, don't get me
wrong).
In particular, instead of these PageHighMem(page) tests, I think
something like this would be better:
#ifdef CONFIG_DEBUG_HIGHMEM
#define page_use_kmap(page) ((page),1)
#else
#define page_use_kmap(page) PageHighMem(page)
#endif
adn then replace those "if (!PageHighMem(page))" tests with "if
(!page_use_kmap())" instead.
IOW, in debug mode, it would _always_ remap the page, whether it's
highmem or not. That would really stress the highmem code and find any
fragilities.
No?
Anyway, this is all sepatrate from the series, which still looks fine
to me. Just a reaction to seeing the patch, and Thomas' earlier
mention that the highmem debugging doesn't actually do much.
Linus
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Re: [Intel-gfx] [PATCH V2] drm/i915/ehl: Implement W/A 22010492432
On Tue, Nov 03, 2020 at 06:31:58PM +0200, Surendrakumar Upadhyay, TejaskumarX
wrote:
> > -Original Message-
> > From: Imre Deak
> > Sent: 03 November 2020 21:13
> > To: Surendrakumar Upadhyay, TejaskumarX
> >
> > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> >
> > Subject: Re: [PATCH V2] drm/i915/ehl: Implement W/A 22010492432
> >
> > On Tue, Nov 03, 2020 at 07:16:51PM +0530, Tejas Upadhyay wrote:
> > > As per W/A implemented for TGL to program half of the nominal DCO
> > > divider fraction value which is also applicable on EHL.
> > >
> > > Changes since V1:
> > > - ehl_ used as to keep earliest platform prefix
> > > - WA required B0 stepping onwards
> > >
> > > Cc: Deak Imre
> > > Signed-off-by: Tejas Upadhyay
> > >
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 -
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > 2 files changed, 9 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > index eaef7a2d041f..cb6ebf627c04 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > @@ -2636,13 +2636,16 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
> > > intel_crtc_state *crtc_state) }
> > >
> > > /*
> > > - * Display WA #22010492432: tgl
> > > + * Display WA #22010492432: ehl, tgl
> > > * Program half of the nominal DCO divider fraction value.
> > > */
> > > static bool
> > > -tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
> > > +ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
> > > {
> > > -return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
> > > +return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
> > > +IS_JSL_EHL_REVID(i915, EHL_REVID_B0, EHL_REVID_B0)) ||
> >
> > Imo, better to add a definition for IS_ELKHARTLAKE() and IS_EHL_REVID().
> >
> It has been already discussed in previous EHL/JSL PCI id split patch
> (between Matt Roper/Ville/Me) that we will not keep IS_ELKHARTLAKE()
> and IS_EHL_REVID() instead we will replace with IS_PLATFORM(i915,
> INTEL_ELKHARTLAKE) and IS_JSL_EHL_REVID .
Ok, missed that discussion.
> > It also applies after B0, so it'd be
> > IS_EHL_REVID(EHL_REVID_B0, REVID_FOREVER);
>
> B0 is latest revision. So current logic should be fine.
Until a new revision appears. The spec says to apply the WA on all
steppings starting with B0, I don't see a reason to do otherwise.
> > > +IS_TIGERLAKE(i915)) &&
> > > +i915->dpll.ref_clks.nssc == 38400;
> > > }
> > >
> > > static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private
> > > *dev_priv, @@ -2696,7 +2699,7 @@ static int
> > __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > > dco_fraction = (pll_state->cfgcr0 &
> > DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> > > DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> > >
> > > -if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
> > > +if (ehl_combo_pll_div_frac_wa_needed(dev_priv))
> > > dco_fraction *= 2;
> > >
> > > dco_freq += (dco_fraction * ref_clock) / 0x8000; @@ -3086,7 +3089,7
> > > @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
> > >
> > > memset(pll_state, 0, sizeof(*pll_state));
> > >
> > > -if (tgl_combo_pll_div_frac_wa_needed(i915))
> > > +if (ehl_combo_pll_div_frac_wa_needed(i915))
> > > dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
> > >
> > > pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | diff
> > > --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index d548e10e1600..8bf59b57efc9
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1560,6 +1560,7 @@ extern const struct i915_rev_steppings
> > kbl_revids[];
> > > (IS_ICELAKE(p) && IS_REVID(p, since, until))
> > >
> > > #define EHL_REVID_A00x0
> > > +#define EHL_REVID_B00x2
> >
> > Where are the steppings specified for EHL? At least on the BSpec/29153 page
> > I see EHL/B0 being 1.
> >
> > >
> > > #define IS_JSL_EHL_REVID(p, since, until) \
> > > (IS_JSL_EHL(p) && IS_REVID(p, since, until))
> > > --
> > > 2.28.0
> > >
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3)
== Series Details == Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3) URL : https://patchwork.freedesktop.org/series/83373/ State : success == Summary == CI Bug Log - changes from CI_DRM_9255 -> Patchwork_18843 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/index.html New tests - New tests have been introduced between CI_DRM_9255 and Patchwork_18843: ### New CI tests (1) ### * boot: - Statuses : 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18843 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982] / [k.org#205379]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-tgl-u2/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-tgl-u2/igt@i915_module_l...@reload.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html Possible fixes * igt@i915_module_load@reload: - fi-icl-y: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-icl-y/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-icl-y/igt@i915_module_l...@reload.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379 Participating hosts (42 -> 38) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9255 -> Patchwork_18843 CI-20190529: 20190529 CI_DRM_9255: 10bed1eeb88d1ebe8f7b00b57c37329068b06ca4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18843: d4ce6b762592e81747632f613162cff88a1bdf26 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d4ce6b762592 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3. 7004b13da2f6 drm/i915/dp: Prep for bigjoiner atomic check bd6d793e3861 drm/i915: Pass intel_atomic_state instead of drm_atomic_state fa9cc802e92e drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split 54c92c312833 drm/i915: Move encoder->get_config to a new function ef45baae1b4d drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/amdgpu: Paper over the drm_driver mangling for virt
On Sun, Nov 1, 2020 at 5:01 AM Daniel Vetter wrote:
>
> On Sat, Oct 31, 2020 at 2:57 PM Daniel Vetter wrote:
> >
> > On Fri, Oct 30, 2020 at 7:47 PM Alex Deucher wrote:
> > >
> > > On Fri, Oct 30, 2020 at 6:11 AM Daniel Vetter
> > > wrote:
> > > >
> > > > Prep work to make drm_device->driver const.
> > > >
> > > > Signed-off-by: Daniel Vetter
> > > > Cc: Alex Deucher
> > > > Cc: "Christian König"
> > > > Cc: Evan Quan
> > > > Cc: Felix Kuehling
> > > > Cc: Hawking Zhang
> > > > Cc: Andrey Grodzovsky
> > > > Cc: Luben Tuikov
> > > > Cc: Thomas Zimmermann
> > > > Cc: Monk Liu
> > > > Cc: Yintian Tao
> > > > Cc: Dennis Li
> > > > Cc: shaoyunl
> > > > Cc: Bokun Zhang
> > > > Cc: "Stanley.Yang"
> > > > Cc: Wenhui Sheng
> > > > Cc: chen gong
> > > > Signed-off-by: Daniel Vetter
> > > > ---
> > > > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
> > > > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 12 +++-
> > > > 2 files changed, 15 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > > > index 024c3b70b1aa..3d337f13ae4e 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > > > @@ -1093,7 +1093,7 @@ static const struct pci_device_id pciidlist[] = {
> > > >
> > > > MODULE_DEVICE_TABLE(pci, pciidlist);
> > > >
> > > > -static struct drm_driver kms_driver;
> > > > +struct drm_driver amdgpu_kms_driver;
> > > >
> > > > static int amdgpu_pci_probe(struct pci_dev *pdev,
> > > > const struct pci_device_id *ent)
> > > > @@ -1164,7 +1164,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
> > > > if (ret)
> > > > return ret;
> > > >
> > > > - adev = devm_drm_dev_alloc(>dev, _driver,
> > > > typeof(*adev), ddev);
> > > > + adev = devm_drm_dev_alloc(>dev, _kms_driver,
> > > > typeof(*adev), ddev);
> > > > if (IS_ERR(adev))
> > > > return PTR_ERR(adev);
> > > >
> > > > @@ -1508,7 +1508,7 @@ int amdgpu_file_to_fpriv(struct file *filp,
> > > > struct amdgpu_fpriv **fpriv)
> > > > return 0;
> > > > }
> > > >
> > > > -static struct drm_driver kms_driver = {
> > > > +struct drm_driver amdgpu_kms_driver = {
> > > > .driver_features =
> > > > DRIVER_ATOMIC |
> > > > DRIVER_GEM |
> > > > @@ -1571,7 +1571,7 @@ static int __init amdgpu_init(void)
> > > > goto error_fence;
> > > >
> > > > DRM_INFO("amdgpu kernel modesetting enabled.\n");
> > > > - kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
> > > > + amdgpu_kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
> > > > amdgpu_register_atpx_handler();
> > > >
> > > > /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not
> > > > set. */
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > index d0aea5e39531..dde4c449c284 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > @@ -45,13 +45,23 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device
> > > > *adev)
> > > > return RREG32_NO_KIQ(0xc040) == 0x;
> > > > }
> > > >
> > > > +extern struct drm_driver amdgpu_kms_driver;
> > > > +
> > > > void amdgpu_virt_init_setting(struct amdgpu_device *adev)
> > > > {
> > > > /* enable virtual display */
> > > > if (adev->mode_info.num_crtc == 0)
> > > > adev->mode_info.num_crtc = 1;
> > > > adev->enable_virtual_display = true;
> > > > - adev_to_drm(adev)->driver->driver_features &= ~DRIVER_ATOMIC;
> > > > +
> > > > + /*
> > > > +* FIXME: Either make virt support atomic or make sure you have
> > > > two
> > > > +* drm_driver structs, these kind of tricks are only ok when
> > > > there's
> > > > +* guaranteed only a single device per system. This should also
> > > > be done
> > > > +* before struct drm_device is initialized.
> > > > +*/
> > > > + amdgpu_kms_driver.driver_features &= ~DRIVER_ATOMIC;
> > >
> > > There is additional DRIVER_ATOMIC in amdgpu_pci_probe() for older
> > > chips without atomic support.
> >
> > That would need to be fixed for making the amdgpu drm_driver
> > structures constant, but that's not what I'm doing here. I'm only
> > removing the usage of the drm_device->driver pointer, to allow that to
> > become constant. Untangling the flow to make the amdgpu_kms_driver
> > const looked a bit more involved than just a simple patch.
>
> On second look, this changes the drm_device->driver_features flag,
> which was added to avoid having to change the drm_driver one. So
> that's actually all ok (and just the virt code here is broken). But
> amdgpu also updates num_ioctl and other stuff, and that's a fairly
> invasive patch.
We don't
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3)
== Series Details ==
Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes (rev3)
URL : https://patchwork.freedesktop.org/series/83373/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ef45baae1b4d drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner
modes
54c92c312833 drm/i915: Move encoder->get_config to a new function
fa9cc802e92e drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:172: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#172: FILE: drivers/gpu/drm/i915/display/intel_display.c:13475:
+ crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode =
crtc_state->uapi.adjusted_mode;
total: 0 errors, 0 warnings, 1 checks, 392 lines checked
bd6d793e3861 drm/i915: Pass intel_atomic_state instead of drm_atomic_state
7004b13da2f6 drm/i915/dp: Prep for bigjoiner atomic check
d4ce6b762592 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
-:191: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the
previous line
#191: FILE: drivers/gpu/drm/i915/display/intel_dp.c:774:
+ if ((target_clock > max_dotclk || mode->hdisplay > 5120)
+ && intel_dp_can_bigjoiner(intel_dp)) {
total: 0 errors, 0 warnings, 1 checks, 211 lines checked
___
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Re: [Intel-gfx] [PATCH V2] drm/i915/ehl: Implement W/A 22010492432
> -Original Message-
> From: Imre Deak
> Sent: 03 November 2020 21:13
> To: Surendrakumar Upadhyay, TejaskumarX
>
> Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
>
> Subject: Re: [PATCH V2] drm/i915/ehl: Implement W/A 22010492432
>
> On Tue, Nov 03, 2020 at 07:16:51PM +0530, Tejas Upadhyay wrote:
> > As per W/A implemented for TGL to program half of the nominal DCO
> > divider fraction value which is also applicable on EHL.
> >
> > Changes since V1:
> > - ehl_ used as to keep earliest platform prefix
> > - WA required B0 stepping onwards
> >
> > Cc: Deak Imre
> > Signed-off-by: Tejas Upadhyay
> >
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 -
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > 2 files changed, 9 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index eaef7a2d041f..cb6ebf627c04 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -2636,13 +2636,16 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
> > intel_crtc_state *crtc_state) }
> >
> > /*
> > - * Display WA #22010492432: tgl
> > + * Display WA #22010492432: ehl, tgl
> > * Program half of the nominal DCO divider fraction value.
> > */
> > static bool
> > -tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
> > +ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
> > {
> > - return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
> > + return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
> > + IS_JSL_EHL_REVID(i915, EHL_REVID_B0, EHL_REVID_B0)) ||
>
> Imo, better to add a definition for IS_ELKHARTLAKE() and IS_EHL_REVID().
>
It has been already discussed in previous EHL/JSL PCI id split patch (between
Matt Roper/Ville/Me) that we will not keep IS_ELKHARTLAKE() and IS_EHL_REVID()
instead we will replace with IS_PLATFORM(i915, INTEL_ELKHARTLAKE) and
IS_JSL_EHL_REVID .
> It also applies after B0, so it'd be
> IS_EHL_REVID(EHL_REVID_B0, REVID_FOREVER);
B0 is latest revision. So current logic should be fine.
>
> > + IS_TIGERLAKE(i915)) &&
> > + i915->dpll.ref_clks.nssc == 38400;
> > }
> >
> > static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private
> > *dev_priv, @@ -2696,7 +2699,7 @@ static int
> __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > dco_fraction = (pll_state->cfgcr0 &
> DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> >DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> >
> > - if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
> > + if (ehl_combo_pll_div_frac_wa_needed(dev_priv))
> > dco_fraction *= 2;
> >
> > dco_freq += (dco_fraction * ref_clock) / 0x8000; @@ -3086,7 +3089,7
> > @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
> >
> > memset(pll_state, 0, sizeof(*pll_state));
> >
> > - if (tgl_combo_pll_div_frac_wa_needed(i915))
> > + if (ehl_combo_pll_div_frac_wa_needed(i915))
> > dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
> >
> > pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | diff
> > --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index d548e10e1600..8bf59b57efc9
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1560,6 +1560,7 @@ extern const struct i915_rev_steppings
> kbl_revids[];
> > (IS_ICELAKE(p) && IS_REVID(p, since, until))
> >
> > #define EHL_REVID_A00x0
> > +#define EHL_REVID_B00x2
>
> Where are the steppings specified for EHL? At least on the BSpec/29153 page
> I see EHL/B0 being 1.
>
> >
> > #define IS_JSL_EHL_REVID(p, since, until) \
> > (IS_JSL_EHL(p) && IS_REVID(p, since, until))
> > --
> > 2.28.0
> >
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Include fb modidier in state dumps
== Series Details ==
Series: drm/i915: Include fb modidier in state dumps
URL : https://patchwork.freedesktop.org/series/83438/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9255 -> Patchwork_18842
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/index.html
New tests
-
New tests have been introduced between CI_DRM_9255 and Patchwork_18842:
### New CI tests (1) ###
* boot:
- Statuses : 38 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18842 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-byt-j1900/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/fi-byt-j1900/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [PASS][5] -> [INCOMPLETE][6] ([i915#1250] /
[i915#1436])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar
issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
Possible fixes
* igt@i915_module_load@reload:
- fi-icl-y: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-icl-y/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/fi-icl-y/igt@i915_module_l...@reload.html
* igt@kms_busy@basic@flip:
- {fi-kbl-7560u}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-kbl-7560u/igt@kms_busy@ba...@flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/fi-kbl-7560u/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
Participating hosts (42 -> 38)
--
Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_9255 -> Patchwork_18842
CI-20190529: 20190529
CI_DRM_9255: 10bed1eeb88d1ebe8f7b00b57c37329068b06ca4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18842: 843ae78a11bbd8e0cd15eae4ad4eaa26a6df7e7b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
843ae78a11bb drm/i915: Include fb modidier in state dumps
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18842/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Include fb modidier in state dumps
== Series Details == Series: drm/i915: Include fb modidier in state dumps URL : https://patchwork.freedesktop.org/series/83438/ State : warning == Summary == $ dim checkpatch origin/drm-tip 843ae78a11bb drm/i915: Include fb modidier in state dumps -:43: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #43: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:776: + seq_printf(m, "\t\tuapi: [FB:%d] %s,0x%llx,%dx%d, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", -:54: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #54: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:801: + seq_printf(m, "\t\thw: [FB:%d] %s,0x%llx,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", total: 0 errors, 2 warnings, 0 checks, 34 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable HDR on MCA LSPCON based Gen9 devices (rev9)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev9) URL : https://patchwork.freedesktop.org/series/68081/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9255 -> Patchwork_18841 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18841 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18841, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18841: ### IGT changes ### Possible regressions * igt@i915_selftest@live@client: - fi-ivb-3770:[PASS][1] -> [DMESG-WARN][2] +33 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-ivb-3770/igt@i915_selftest@l...@client.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-ivb-3770/igt@i915_selftest@l...@client.html * igt@i915_selftest@live@dmabuf: - fi-cfl-8700k: [PASS][3] -> [DMESG-WARN][4] +34 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-cfl-8700k/igt@i915_selftest@l...@dmabuf.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-cfl-8700k/igt@i915_selftest@l...@dmabuf.html - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] +34 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-icl-u2/igt@i915_selftest@l...@dmabuf.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-icl-u2/igt@i915_selftest@l...@dmabuf.html * igt@i915_selftest@live@gem: - fi-snb-2600:[PASS][7] -> [DMESG-WARN][8] +33 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-snb-2600/igt@i915_selftest@l...@gem.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-snb-2600/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@gt_engines: - fi-skl-lmem:[PASS][9] -> [DMESG-WARN][10] +34 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-skl-lmem/igt@i915_selftest@live@gt_engines.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-skl-lmem/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_heartbeat: - fi-skl-6600u: [PASS][11] -> [DMESG-WARN][12] +34 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html - fi-kbl-x1275: [PASS][13] -> [DMESG-WARN][14] +34 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_lrc: - fi-ilk-650: [PASS][15] -> [DMESG-WARN][16] +33 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-ilk-650/igt@i915_selftest@live@gt_lrc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-ilk-650/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_mocs: - fi-byt-j1900: [PASS][17] -> [DMESG-WARN][18] +34 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-byt-j1900/igt@i915_selftest@live@gt_mocs.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-byt-j1900/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@gt_pm: - fi-cml-s: [PASS][19] -> [DMESG-WARN][20] +34 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-cml-s/igt@i915_selftest@live@gt_pm.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-cml-s/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@gt_timelines: - fi-skl-6700k2: [PASS][21] -> [DMESG-WARN][22] +34 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-skl-6700k2/igt@i915_selftest@live@gt_timelines.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-skl-6700k2/igt@i915_selftest@live@gt_timelines.html * igt@i915_selftest@live@gtt: - fi-skl-guc: [PASS][23] -> [DMESG-WARN][24] +34 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-skl-guc/igt@i915_selftest@l...@gtt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18841/fi-skl-guc/igt@i915_selftest@l...@gtt.html * igt@i915_selftest@live@hangcheck: - fi-elk-e7500: [PASS][25] -> [DMESG-WARN][26] +33 similar issues
[Intel-gfx] [PATCH v6 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v13:
* Allow bigjoiner if hdisplay >5120
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can_bigjoiner non static
so it can be used in intel_display (Manasi)
v10:
* Simplify logic (Ville)
* Allow bigjoiner on edp (Ville)
v9:
* Restric Bigjoiner on PORT A (Ville)
v8:
* use source dotclock for max dotclock (Manasi)
v7:
* Add can_bigjoiner() helper (Ville)
* Pass bigjoiner to plane_size validation (Ville)
v6:
* Rebase after dp_downstream mode valid changes (Manasi)
v5:
* Increase max plane width to support 8K with bigjoiner (Maarten)
v4:
* Rebase (Manasi)
Changes since v1:
- Disallow bigjoiner on eDP.
Changes since v2:
- Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
and split off the downstream and source checking to its own function.
(Ville)
v3:
* Rebase (Manasi)
Signed-off-by: Manasi Navare
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
drivers/gpu/drm/i915/display/intel_display.h | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 78
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
7 files changed, 73 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c59d9c2bd473..73bd9721c1a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17779,7 +17779,8 @@ intel_mode_valid(struct drm_device *dev,
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
- const struct drm_display_mode *mode)
+ const struct drm_display_mode *mode,
+ bool bigjoiner)
{
int plane_width_max, plane_height_max;
@@ -17796,7 +17797,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private
*dev_priv,
* too big for that.
*/
if (INTEL_GEN(dev_priv) >= 11) {
- plane_width_max = 5120;
+ plane_width_max = 5120 << bigjoiner;
plane_height_max = 4320;
} else {
plane_width_max = 5120;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index be774f216065..d24077df1711 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -513,7 +513,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private
*dev_priv,
bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
- const struct drm_display_mode *mode);
+ const struct drm_display_mode *mode,
+ bool bigjoiner);
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ca4d4a8122d9..d2023fc54a18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -254,6 +254,17 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return max_link_clock * max_lanes;
}
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = _dig_port->base;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ return INTEL_GEN(dev_priv) >= 12 ||
+ (INTEL_GEN(dev_priv) == 11 &&
+encoder->port != PORT_A);
+}
+
static int cnl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -519,7 +530,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay)
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -537,6 +549,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev9)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev9) URL : https://patchwork.freedesktop.org/series/68081/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev9)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev9) URL : https://patchwork.freedesktop.org/series/68081/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7ce78e26d315 drm/i915/display: Add HDR Capability detection for LSPCON 0fac40ec244f drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon f5cbc62d4680 drm/i915/display: Attach HDR property for capable Gen9 devices -:43: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #43: FILE: drivers/gpu/drm/i915/display/intel_dp.c:6737: + connector->dev->mode_config.hdr_output_metadata_property, total: 0 errors, 1 warnings, 0 checks, 38 lines checked 5a973896bb8d drm/i915/display: Attach content type property for LSPCON dbed4b7913ed drm/i915/display: Nuke bogus lspcon check efdec80a4db4 drm/i915/display: Enable BT2020 for HDR on LSPCON devices dd9e7eca60c8 drm/i915/display: Enable HDR for Parade based lspcon 8f4bf660df48 drm/i915/display: Implement infoframes readback for LSPCON a2460c40ac7f drm/i915/display: Implement DRM infoframe read for LSPCON 58caffcf5821 drm/i915/lspcon: Create separate infoframe_enabled helper aca13428895f drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks 59892e378eb7 drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V2] drm/i915/ehl: Implement W/A 22010492432
On Tue, Nov 03, 2020 at 07:16:51PM +0530, Tejas Upadhyay wrote:
> As per W/A implemented for TGL to program half of the nominal
> DCO divider fraction value which is also applicable on EHL.
>
> Changes since V1:
> - ehl_ used as to keep earliest platform prefix
> - WA required B0 stepping onwards
>
> Cc: Deak Imre
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 -
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index eaef7a2d041f..cb6ebf627c04 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2636,13 +2636,16 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
> intel_crtc_state *crtc_state)
> }
>
> /*
> - * Display WA #22010492432: tgl
> + * Display WA #22010492432: ehl, tgl
> * Program half of the nominal DCO divider fraction value.
> */
> static bool
> -tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
> +ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
> {
> - return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
> + return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
> + IS_JSL_EHL_REVID(i915, EHL_REVID_B0, EHL_REVID_B0)) ||
Imo, better to add a definition for IS_ELKHARTLAKE() and IS_EHL_REVID().
It also applies after B0, so it'd be
IS_EHL_REVID(EHL_REVID_B0, REVID_FOREVER);
> + IS_TIGERLAKE(i915)) &&
> + i915->dpll.ref_clks.nssc == 38400;
> }
>
> static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> @@ -2696,7 +2699,7 @@ static int __cnl_ddi_wrpll_get_freq(struct
> drm_i915_private *dev_priv,
> dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> DPLL_CFGCR0_DCO_FRACTION_SHIFT;
>
> - if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
> + if (ehl_combo_pll_div_frac_wa_needed(dev_priv))
> dco_fraction *= 2;
>
> dco_freq += (dco_fraction * ref_clock) / 0x8000;
> @@ -3086,7 +3089,7 @@ static void icl_calc_dpll_state(struct drm_i915_private
> *i915,
>
> memset(pll_state, 0, sizeof(*pll_state));
>
> - if (tgl_combo_pll_div_frac_wa_needed(i915))
> + if (ehl_combo_pll_div_frac_wa_needed(i915))
> dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
>
> pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d548e10e1600..8bf59b57efc9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1560,6 +1560,7 @@ extern const struct i915_rev_steppings kbl_revids[];
> (IS_ICELAKE(p) && IS_REVID(p, since, until))
>
> #define EHL_REVID_A00x0
> +#define EHL_REVID_B00x2
Where are the steppings specified for EHL? At least on the BSpec/29153
page I see EHL/B0 being 1.
>
> #define IS_JSL_EHL_REVID(p, since, until) \
> (IS_JSL_EHL(p) && IS_REVID(p, since, until))
> --
> 2.28.0
>
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Include fb modidier in state dumps
Thanks! Acked-by: Simon Ser ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Include fb modidier in state dumps
From: Ville Syrjälä To help diagnose modifier related issues let's include that information in the various state dumps. Cc: Simon Ser Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 7 --- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index cddbda5303ff..6af89bf4c241 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13218,11 +13218,11 @@ static void intel_dump_plane_state(const struct intel_plane_state *plane_state) } drm_dbg_kms(>drm, - "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n", + "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s modifier = 0x%llx, visible: %s\n", plane->base.base.id, plane->base.name, fb->base.id, fb->width, fb->height, drm_get_format_name(fb->format->format, _name), - yesno(plane_state->uapi.visible)); + fb->modifier, yesno(plane_state->uapi.visible)); drm_dbg_kms(>drm, "\trotation: 0x%x, scaler: %d\n", plane_state->hw.rotation, plane_state->scaler_id); if (plane_state->uapi.visible) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index cfb4c1474982..00b79593bcef 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -773,8 +773,9 @@ static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane) plane_rotation(rot_str, sizeof(rot_str), plane_state->uapi.rotation); - seq_printf(m, "\t\tuapi: fb=%d,%s,%dx%d, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", + seq_printf(m, "\t\tuapi: [FB:%d] %s,0x%llx,%dx%d, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", fb ? fb->base.id : 0, fb ? format_name.str : "n/a", + fb ? fb->modifier : 0, fb ? fb->width : 0, fb ? fb->height : 0, DRM_RECT_FP_ARG(), DRM_RECT_ARG(), @@ -797,9 +798,9 @@ static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane) plane_rotation(rot_str, sizeof(rot_str), plane_state->hw.rotation); - seq_printf(m, "\t\thw: fb=%d,%s,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", + seq_printf(m, "\t\thw: [FB:%d] %s,0x%llx,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", fb->base.id, format_name.str, - fb->width, fb->height, + fb->modifier, fb->width, fb->height, yesno(plane_state->uapi.visible), DRM_RECT_FP_ARG(_state->uapi.src), DRM_RECT_ARG(_state->uapi.dst), -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v9 08/12] drm/i915/display: Implement infoframes readback for LSPCON
Implemented Infoframes enabled readback for LSPCON devices.
This will help align the implementation with state readback
infrastructure.
v2: Added proper bitmask of enabled infoframes as per Ville's
recommendation.
v3: Added pcon specific infoframe types instead of using the HSW
one's, as recommended by Ville.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 57 -
drivers/gpu/drm/i915/i915_reg.h | 2 +
2 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 0cd3e0853cbf..d83e1d220658 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -567,11 +567,64 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
buf, ret);
}
+static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)
+{
+ int ret;
+ u32 val = 0;
+ u16 reg = LSPCON_MCA_AVI_IF_CTRL;
+
+ ret = drm_dp_dpcd_read(aux, reg, , 1);
+ if (ret < 0) {
+ DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+ return false;
+ }
+
+ return val & LSPCON_MCA_AVI_IF_KICKOFF;
+}
+
+static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux)
+{
+ int ret;
+ u32 val = 0;
+ u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
+
+ ret = drm_dp_dpcd_read(aux, reg, , 1);
+ if (ret < 0) {
+ DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+ return false;
+ }
+
+ return val & LSPCON_PARADE_AVI_IF_KICKOFF;
+}
+
u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
- /* FIXME actually read this from the hw */
- return 0;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ bool infoframes_enabled;
+ u32 val = 0;
+ u32 mask, tmp;
+
+ if (lspcon->vendor == LSPCON_VENDOR_MCA)
+ infoframes_enabled =
_lspcon_read_avi_infoframe_enabled_mca(_dp->aux);
+ else
+ infoframes_enabled =
_lspcon_read_avi_infoframe_enabled_parade(_dp->aux);
+
+ if (infoframes_enabled)
+ val |= VIDEO_DIP_ENABLE_AVI_PCON;
+
+ if (lspcon->hdr_supported) {
+ tmp = intel_de_read(dev_priv,
+
HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
+ mask = VIDEO_DIP_ENABLE_GMP_PCON;
+
+ if (tmp & mask)
+ val |= mask;
+ }
+
+ return val;
}
void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb0656875697..465ec00afbff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5084,6 +5084,8 @@ enum {
#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
+#define VIDEO_DIP_ENABLE_AVI_PCON(1 << 12)
+#define VIDEO_DIP_ENABLE_GMP_PCON(1 << 4)
/* Panel power sequencing */
#define PPS_BASE 0x61200
--
2.26.2
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[Intel-gfx] [v9 05/12] drm/i915/display: Nuke bogus lspcon check
Dropped a irrelevant lspcon check from intel_hdmi_add_properties
function.
Suggested-by: Ville Syrjälä"
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 8e4b820b715a..f1a927cdf798 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2950,20 +2950,12 @@ static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector
*connector)
{
struct drm_i915_private *dev_priv = to_i915(connector->dev);
- struct intel_digital_port *dig_port =
- hdmi_to_dig_port(intel_hdmi);
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
intel_attach_aspect_ratio_property(connector);
- /*
-* Attach Colorspace property for Non LSPCON based device
-* ToDo: This needs to be extended for LSPCON implementation
-* as well. Will be implemented separately.
-*/
- if (!dig_port->lspcon.active)
- intel_attach_colorspace_property(connector);
+ intel_attach_colorspace_property(connector);
drm_connector_attach_content_type_property(connector);
--
2.26.2
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[Intel-gfx] [v9 09/12] drm/i915/display: Implement DRM infoframe read for LSPCON
Implement Read back of HDR metadata infoframes i.e Dynamic Range
and Mastering Infoframe for LSPCON devices.
v2: Added proper bitmask of enabled infoframes as per Ville's
recommendation.
v3: Dropped a redundant wrapper as per Ville's comment.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 7 +++
drivers/gpu/drm/i915/display/intel_lspcon.c | 7 ++-
drivers/gpu/drm/i915/display/intel_lspcon.h | 4
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f1a927cdf798..81dabffbb3e6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -555,10 +555,9 @@ void hsw_write_infoframe(struct intel_encoder *encoder,
intel_de_posting_read(dev_priv, ctl_reg);
}
-static void hsw_read_infoframe(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- unsigned int type,
- void *frame, ssize_t len)
+void hsw_read_infoframe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type, void *frame, ssize_t len)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d83e1d220658..8a4fd8ca8016 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -486,7 +486,12 @@ void lspcon_read_infoframe(struct intel_encoder *encoder,
unsigned int type,
void *frame, ssize_t len)
{
- /* FIXME implement this */
+ /* FIXME implement for AVI Infoframe as well */
+ if (type == HDMI_PACKET_TYPE_GAMUT_METADATA) {
+ drm_dbg_kms(encoder->base.dev, "Read HDR metadata for
lspcon\n");
+ hsw_read_infoframe(encoder, crtc_state, type,
+ frame, len);
+ }
}
void lspcon_set_infoframes(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 42ccb21c908f..d622156d0c4e 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -37,5 +37,9 @@ void hsw_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
const void *frame, ssize_t len);
+void hsw_read_infoframe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type,
+ void *frame, ssize_t len);
#endif /* __INTEL_LSPCON_H__ */
--
2.26.2
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[Intel-gfx] [v9 11/12] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks
Non-HDMI sinks shouldn't be sent Dynamic Range and Mastering infoframes.
Check for that when using LSPCON.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index d50dd1f1292a..5993c49824d2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3938,6 +3938,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state
*state,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum port port = encoder->port;
if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
@@ -3945,7 +3946,14 @@ static void intel_enable_ddi_dp(struct
intel_atomic_state *state,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state, conn_state);
- intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+
+ if (dig_port->lspcon.active) {
+ if (dig_port->dp.has_hdmi_sink)
+ intel_dp_set_infoframes(encoder, true, crtc_state,
conn_state);
+ } else {
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+ }
+
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
--
2.26.2
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[Intel-gfx] [v9 00/12] Enable HDR on MCA LSPCON based Gen9 devices
Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR support for MCA and Parade LSPCON based GEN9 devices. SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP packets. LSPCON will be set to operate in PCON mode, will receive the metadata and create Dynamic Range and Mastering Infoframe (DRM packets) and send it to HDR capable HDMI sink devices. v2: Fixed Ville's review comments. Suppressed some warnings. Patch 8 of the series is marked "Not for Merge" and is just for reference to userspace people to incorporate in order to support 10bit content with 4K@60 resolutions. v3: Added Infoframe readout support for DRM infoframes. Addressed Jani Nikula's review comments. v4: Addressed Ville's review comments and added proper bitmask for enabled infoframes. Series also incorporates Ville's patch for stopping infoframes to be sent to DVI sinks. Extended the same for DRM as well. v5: Created separate helper function for lspcon_infoframes_enabled as per Ville's suggestion. v6: Rebase v7: Addressed Ville's review comments. v8: Addressed Ville's review comments. Fixed the colorspace handling for Pcon and property attachment logic based on new lspcon detetction changes. v9: Rebase Thanks Ville for all the suggestions and inputs. Note: Patch 12 of the series is for reference to userspace, not to be merged to driver. Uma Shankar (12): drm/i915/display: Add HDR Capability detection for LSPCON drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon drm/i915/display: Attach HDR property for capable Gen9 devices drm/i915/display: Attach content type property for LSPCON drm/i915/display: Nuke bogus lspcon check drm/i915/display: Enable BT2020 for HDR on LSPCON devices drm/i915/display: Enable HDR for Parade based lspcon drm/i915/display: Implement infoframes readback for LSPCON drm/i915/display: Implement DRM infoframe read for LSPCON drm/i915/lspcon: Create separate infoframe_enabled helper drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON drivers/gpu/drm/i915/display/intel_ddi.c | 20 +- .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 29 +++ drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +-- drivers/gpu/drm/i915/display/intel_lspcon.c | 181 +++--- drivers/gpu/drm/i915/display/intel_lspcon.h | 12 ++ drivers/gpu/drm/i915/i915_reg.h | 2 + 7 files changed, 226 insertions(+), 44 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v9 04/12] drm/i915/display: Attach content type property for LSPCON
Content type is supported on HDMI sink devices. Attached the property for the same for LSPCON based devices. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_dp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0ce3204473fa..79a49d1cbb21 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6736,6 +6736,7 @@ intel_dp_connector_register(struct drm_connector *connector) drm_object_attach_property(>base, connector->dev->mode_config.hdr_output_metadata_property, 0); + drm_connector_attach_content_type_property(connector); } return ret; -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v9 06/12] drm/i915/display: Enable BT2020 for HDR on LSPCON devices
Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
data for HDR using AVI infoframe. LSPCON firmware expects this and though
SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
which transfers the same to HDMI sink.
v2: Dropped state managed in drm core as per Jani Nikula's suggestion.
v3: Aligned colorimetry handling for lspcon as per compute_avi_infoframes,
as suggested by Ville.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 31 +
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 336494b60d11..19831f5e51bf 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -524,12 +524,31 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
else
frame.avi.colorspace = HDMI_COLORSPACE_RGB;
- drm_hdmi_avi_infoframe_quant_range(,
- conn_state->connector,
- adjusted_mode,
- crtc_state->limited_color_range ?
- HDMI_QUANTIZATION_RANGE_LIMITED :
- HDMI_QUANTIZATION_RANGE_FULL);
+ /*
+* Set the HDMI Colorspace which are supported by DP as well.
+* For all others (3 combinations which are exclusive for DP),
+* Let the colorspace be set to default i.e No Data.
+* Fixme: Expose HDMI colorspaces for instead of DP counterparts
+*/
+ drm_hdmi_avi_infoframe_colorspace(, conn_state);
+
+ /* nonsense combination */
+ drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
+ crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
+
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
+ drm_hdmi_avi_infoframe_quant_range(,
+ conn_state->connector,
+ adjusted_mode,
+
crtc_state->limited_color_range ?
+
HDMI_QUANTIZATION_RANGE_LIMITED :
+
HDMI_QUANTIZATION_RANGE_FULL);
+ } else {
+ frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
+ frame.avi.ycc_quantization_range =
HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
+ }
+
+ drm_hdmi_avi_infoframe_content_type(, conn_state);
ret = hdmi_infoframe_pack(, buf, sizeof(buf));
if (ret < 0) {
--
2.26.2
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[Intel-gfx] [v9 03/12] drm/i915/display: Attach HDR property for capable Gen9 devices
Attach HDR property for Gen9 devices with MCA LSPCON
chips.
v2: Cleaned HDR property attachment logic based on capability
as per Jani Nikula's suggestion.
v3: Fixed the HDR property attachment logic as per the new changes
by Kai-Feng to align with lspcon detection failure on some devices.
v4: Add HDR proprty in late_register to handle lspcon detection,
as suggested by Ville.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +++
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
drivers/gpu/drm/i915/display/intel_lspcon.h | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cf09aca7607b..0ce3204473fa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6714,6 +6714,8 @@ intel_dp_connector_register(struct drm_connector
*connector)
{
struct drm_i915_private *i915 = to_i915(connector->dev);
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_lspcon *lspcon = _port->lspcon;
int ret;
ret = intel_connector_register(connector);
@@ -6727,6 +6729,15 @@ intel_dp_connector_register(struct drm_connector
*connector)
ret = drm_dp_aux_register(_dp->aux);
if (!ret)
drm_dp_cec_register_connector(_dp->aux, connector);
+
+ if (lspcon_init(dig_port)) {
+ lspcon_detect_hdr_capability(lspcon);
+ if (lspcon->hdr_supported)
+ drm_object_attach_property(>base,
+
connector->dev->mode_config.hdr_output_metadata_property,
+ 0);
+ }
+
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 46565ae555b1..336494b60d11 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -553,7 +553,7 @@ void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon)
lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON);
}
-static bool lspcon_init(struct intel_digital_port *dig_port)
+bool lspcon_init(struct intel_digital_port *dig_port)
{
struct intel_dp *dp = _port->dp;
struct intel_lspcon *lspcon = _port->lspcon;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 98043ba50dd4..42ccb21c908f 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -15,6 +15,7 @@ struct intel_digital_port;
struct intel_encoder;
struct intel_lspcon;
+bool lspcon_init(struct intel_digital_port *dig_port);
void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon);
void lspcon_resume(struct intel_digital_port *dig_port);
void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
--
2.26.2
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[Intel-gfx] [v9 02/12] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
Gen9 hardware supports HDMI2.0 through LSPCON chips.
Extending HDR support for MCA LSPCON based GEN9 devices.
SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering Infoframe (DRM packets) and send it to HDR capable
HDMI sink devices.
v2: Re-used hsw infoframe write implementation for HDR metadata
for LSPCON as per Ville's suggestion.
v3: Addressed Jani Nikula's review comments.
v4: Addressed Ville's review comments, removed redundant wrapper
and checks, passed arguments instead of hardcodings.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +++---
drivers/gpu/drm/i915/display/intel_lspcon.c | 31 -
drivers/gpu/drm/i915/display/intel_lspcon.h | 4 +++
3 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..8e4b820b715a 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -518,10 +518,10 @@ static u32 vlv_infoframes_enabled(struct intel_encoder
*encoder,
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
}
-static void hsw_write_infoframe(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- unsigned int type,
- const void *frame, ssize_t len)
+void hsw_write_infoframe(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+unsigned int type,
+const void *frame, ssize_t len)
{
const u32 *data = frame;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 076b21885a30..46565ae555b1 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -446,27 +446,32 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
{
- bool ret;
+ bool ret = true;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
- /* LSPCON only needs AVI IF */
- if (type != HDMI_INFOFRAME_TYPE_AVI)
+ switch (type) {
+ case HDMI_INFOFRAME_TYPE_AVI:
+ if (lspcon->vendor == LSPCON_VENDOR_MCA)
+ ret = _lspcon_write_avi_infoframe_mca(_dp->aux,
+ frame, len);
+ else
+ ret = _lspcon_write_avi_infoframe_parade(_dp->aux,
+frame, len);
+ break;
+ case HDMI_PACKET_TYPE_GAMUT_METADATA:
+ drm_dbg_kms(encoder->base.dev, "Update HDR metadata for
lspcon\n");
+ /* It uses the legacy hsw implementation for the same */
+ hsw_write_infoframe(encoder, crtc_state, type, frame, len);
+ break;
+ default:
return;
-
- if (lspcon->vendor == LSPCON_VENDOR_MCA)
- ret = _lspcon_write_avi_infoframe_mca(_dp->aux,
- frame, len);
- else
- ret = _lspcon_write_avi_infoframe_parade(_dp->aux,
-frame, len);
+ }
if (!ret) {
- DRM_ERROR("Failed to write AVI infoframes\n");
+ DRM_ERROR("Failed to write infoframes\n");
return;
}
-
- DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
}
void lspcon_read_infoframe(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index a19b3564c635..98043ba50dd4 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -32,5 +32,9 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state);
u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config);
+void hsw_write_infoframe(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+unsigned int type,
+const void *frame, ssize_t len);
#endif /* __INTEL_LSPCON_H__ */
--
2.26.2
___
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[Intel-gfx] [v9 01/12] drm/i915/display: Add HDR Capability detection for LSPCON
LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES
DPCD register. LSPCON implementations capable of supporting
HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch
reads the same, detects the HDR capability and adds this to
intel_lspcon struct.
v2: Addressed Jani Nikula's review comment and fixed the HDR
capability detection logic
v3: Deferred HDR detection from lspcon_init (Ville)
Signed-off-by: Uma Shankar
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 28 +++
drivers/gpu/drm/i915/display/intel_lspcon.h | 1 +
3 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..25b2db337174 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1417,6 +1417,7 @@ struct intel_lspcon {
bool active;
enum drm_lspcon_mode mode;
enum lspcon_vendor vendor;
+ bool hdr_supported;
};
struct intel_digital_port {
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index e37d45e531df..076b21885a30 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -35,6 +35,8 @@
#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
#define LSPCON_VENDOR_MCA_OUI 0x0060AD
+#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
+
/* AUX addresses to write MCA AVI IF */
#define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
#define LSPCON_MCA_AVI_IF_CTRL 0x5DF
@@ -104,6 +106,32 @@ static bool lspcon_detect_vendor(struct intel_lspcon
*lspcon)
return true;
}
+void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
+{
+ struct intel_digital_port *dig_port =
+ container_of(lspcon, struct intel_digital_port, lspcon);
+ struct drm_device *dev = dig_port->base.base.dev;
+ struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ u8 hdr_caps;
+ int ret;
+
+ /* Enable HDR for MCA based LSPCON devices */
+ if (lspcon->vendor == LSPCON_VENDOR_MCA)
+ ret = drm_dp_dpcd_read(>aux, DPCD_MCA_LSPCON_HDR_STATUS,
+ _caps, 1);
+ else
+ return;
+
+ if (ret < 0) {
+ drm_dbg_kms(dev, "hdr capability detection failed\n");
+ lspcon->hdr_supported = false;
+ return;
+ } else if (hdr_caps & 0x1) {
+ drm_dbg_kms(dev, "lspcon capable of HDR\n");
+ lspcon->hdr_supported = true;
+ }
+}
+
static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon
*lspcon)
{
enum drm_lspcon_mode current_mode;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index b03dcb7076d8..a19b3564c635 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -15,6 +15,7 @@ struct intel_digital_port;
struct intel_encoder;
struct intel_lspcon;
+void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon);
void lspcon_resume(struct intel_digital_port *dig_port);
void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
void lspcon_write_infoframe(struct intel_encoder *encoder,
--
2.26.2
___
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[Intel-gfx] [v9 07/12] drm/i915/display: Enable HDR for Parade based lspcon
Enable HDR for LSPCON based on Parade along with MCA.
v2: Added a helper for status reg as suggested by Ville.
Signed-off-by: Uma Shankar
Signed-off-by: Vipin Anand
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 19831f5e51bf..0cd3e0853cbf 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -36,6 +36,7 @@
#define LSPCON_VENDOR_MCA_OUI 0x0060AD
#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
+#define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511
/* AUX addresses to write MCA AVI IF */
#define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
@@ -106,21 +107,27 @@ static bool lspcon_detect_vendor(struct intel_lspcon
*lspcon)
return true;
}
+static u32 get_hdr_status_reg(struct intel_lspcon *lspcon)
+{
+ if (lspcon->vendor == LSPCON_VENDOR_MCA)
+ return DPCD_MCA_LSPCON_HDR_STATUS;
+ else
+ return DPCD_PARADE_LSPCON_HDR_STATUS;
+}
+
void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
{
struct intel_digital_port *dig_port =
container_of(lspcon, struct intel_digital_port, lspcon);
struct drm_device *dev = dig_port->base.base.dev;
struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ u32 lspcon_hdr_status_reg;
u8 hdr_caps;
int ret;
- /* Enable HDR for MCA based LSPCON devices */
- if (lspcon->vendor == LSPCON_VENDOR_MCA)
- ret = drm_dp_dpcd_read(>aux, DPCD_MCA_LSPCON_HDR_STATUS,
- _caps, 1);
- else
- return;
+ lspcon_hdr_status_reg = get_hdr_status_reg(lspcon);
+ ret = drm_dp_dpcd_read(>aux, lspcon_hdr_status_reg,
+ _caps, 1);
if (ret < 0) {
drm_dbg_kms(dev, "hdr capability detection failed\n");
--
2.26.2
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[Intel-gfx] [v9 10/12] drm/i915/lspcon: Create separate infoframe_enabled helper
Lspcon has Infoframes as well as DIP for HDR metadata(DRM Infoframe).
Create a separate mechanism for lspcon compared to HDMI in order to
address the same and ensure future scalability.
Suggested-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c| 10 +++---
drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++
drivers/gpu/drm/i915/display/intel_lspcon.h | 2 ++
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 19b16517a502..d50dd1f1292a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4402,6 +4402,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
u32 temp, flags = 0;
/* XXX: DSI transcoder paranoia */
@@ -4482,9 +4483,12 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->fec_enable);
}
- pipe_config->infoframes.enable |=
- intel_hdmi_infoframes_enabled(encoder, pipe_config);
-
+ if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
+ pipe_config->infoframes.enable |=
+ intel_lspcon_infoframes_enabled(encoder,
pipe_config);
+ else
+ pipe_config->infoframes.enable |=
+ intel_hdmi_infoframes_enabled(encoder,
pipe_config);
break;
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 8a4fd8ca8016..9c8dfd2fb949 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -30,6 +30,7 @@
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_lspcon.h"
+#include "intel_hdmi.h"
/* LSPCON OUI Vendor ID(signatures) */
#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
@@ -667,6 +668,23 @@ bool lspcon_init(struct intel_digital_port *dig_port)
return true;
}
+u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ u32 val, enabled = 0;
+
+ val = dig_port->infoframes_enabled(encoder, pipe_config);
+
+ if (val & VIDEO_DIP_ENABLE_AVI_HSW)
+ enabled |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
+
+ if (val & VIDEO_DIP_ENABLE_GMP_HSW)
+ enabled |=
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+
+ return enabled;
+}
+
void lspcon_resume(struct intel_digital_port *dig_port)
{
struct intel_lspcon *lspcon = _port->lspcon;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index d622156d0c4e..e92735408443 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -41,5 +41,7 @@ void hsw_read_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
void *frame, ssize_t len);
+u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config);
#endif /* __INTEL_LSPCON_H__ */
--
2.26.2
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[Intel-gfx] [v9 12/12] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON
Blanking needs to be reduced to incorporate DP and HDMI timing/link
bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
This will cause mode to blank out. Reduced Htotal by shortening the
back porch and front porch within permissible limits.
Note: This is for reference for userspace, not to be merged in kernel.
v2: This is marked as Not for merge and the responsibilty to program
these custom timings will be on userspace. This patch is just for
reference purposes. This is based on Ville's recommendation.
v3: updated commit message.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 79a49d1cbb21..1ad4c08f850b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -709,8 +709,10 @@ intel_dp_mode_valid(struct drm_connector *connector,
{
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct intel_encoder *intel_encoder =
intel_attached_encoder(intel_connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder);
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk = dev_priv->max_dotclk_freq;
@@ -731,6 +733,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock = fixed_mode->clock;
}
+ /*
+* Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
+* limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
+* while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
+* cause mode to blank out. Reduced Htotal by shortening the back porch
+* and front porch within permissible limits.
+*/
+ if (lspcon->active && lspcon->hdr_supported &&
+ mode->clock > 57) {
+ mode->clock = 57;
+ mode->htotal -= 180;
+ mode->hsync_start -= 72;
+ mode->hsync_end -= 72;
+ }
+
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
--
2.26.2
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Implement W/A 22010492432 (rev2)
== Series Details ==
Series: drm/i915/ehl: Implement W/A 22010492432 (rev2)
URL : https://patchwork.freedesktop.org/series/83135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9253 -> Patchwork_18840
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/index.html
New tests
-
New tests have been introduced between CI_DRM_9253 and Patchwork_18840:
### New CI tests (1) ###
* boot:
- Statuses : 38 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18840 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
Possible fixes
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9253/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-tgl-dsi fi-hsw-4200u fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9253 -> Patchwork_18840
CI-20190529: 20190529
CI_DRM_9253: a8c030d641dc0961d180b866ab6e5e9032dcbdf4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18840: 003c5f8bf5bd155956d52b3f05de0e745a7d5d7c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
003c5f8bf5bd drm/i915/ehl: Implement W/A 22010492432
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18840/index.html
___
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Flush xcs before tgl breadcrumbs
Quoting Mika Kuoppala (2020-11-03 12:44:53) > Chris Wilson writes: > > > In a simple test case that writes to scratch and then busy-waits for the > > batch to be signaled, we observe that the signal is before the write is > > posted. That is bad news. > > > > Splitting the flush + write_dword into two separate flush_dw prevents > > the issue from being reproduced, we can presume the post-sync op is not > > so post-sync. > > > > Only thing that is mildly surpricing is that first one doesnt > need postop write. The MI_FLUSH_DW is stalling, so the second will^W should wait for the first to complete. (And we don't want to do the write from the first as we observe that write is too early.) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch V3 05/37] asm-generic: Provide kmap_size.h
On Tue, Nov 3, 2020 at 10:27 AM Thomas Gleixner wrote: > > kmap_types.h is a misnomer because the old atomic MAP based array does not > exist anymore and the whole indirection of architectures including > kmap_types.h is inconinstent and does not allow to provide guard page > debugging for this misfeature. > > Add a common header file which defines the mapping stack size for all > architectures. Will be used when converting architectures over to a > generic kmap_local/atomic implementation. > > The array size is chosen with the following constraints in mind: > > - The deepest nest level in one context is 3 according to code > inspection. > > - The worst case nesting for the upcoming reemptible version would be: > > 2 maps in task context and a fault inside > 2 maps in the fault handler > 3 maps in softirq > 2 maps in interrupt > > So a total of 16 is sufficient and probably overestimated. > > Signed-off-by: Thomas Gleixner Acked-by: Arnd Bergmann ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 4/7] iommu: Add quirk for Intel graphic devices in map_sg
On 2020-09-27 07:34, Lu Baolu wrote:
Combining the sg segments exposes a bug in the Intel i915 driver which
causes visual artifacts and the screen to freeze. This is most likely
because of how the i915 handles the returned list. It probably doesn't
respect the returned value specifying the number of elements in the list
and instead depends on the previous behaviour of the Intel iommu driver
which would return the same number of elements in the output list as in
the input list.
Signed-off-by: Tom Murphy
Signed-off-by: Lu Baolu
---
drivers/iommu/dma-iommu.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 3526db774611..e7e4d758f51a 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -879,6 +879,33 @@ static int __finalise_sg(struct device *dev, struct
scatterlist *sg, int nents,
unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
int i, count = 0;
+ /*
+* The Intel graphic driver is used to assume that the returned
+* sg list is not combound. This blocks the efforts of converting
+* Intel IOMMU driver to dma-iommu api's. Add this quirk to make the
+* device driver work and should be removed once it's fixed in i915
+* driver.
+*/
+ if (IS_ENABLED(CONFIG_DRM_I915) && dev_is_pci(dev) &&
+ to_pci_dev(dev)->vendor == PCI_VENDOR_ID_INTEL &&
+ (to_pci_dev(dev)->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
+ for_each_sg(sg, s, nents, i) {
+ unsigned int s_iova_off = sg_dma_address(s);
+ unsigned int s_length = sg_dma_len(s);
+ unsigned int s_iova_len = s->length;
+
+ s->offset += s_iova_off;
+ s->length = s_length;
+ sg_dma_address(s) = dma_addr + s_iova_off;
+ sg_dma_len(s) = s_length;
+ dma_addr += s_iova_len;
+
+ pr_info_once("sg combining disabled due to i915
driver\n");
+ }
+
+ return nents;
+ }
BTW, a much less invasive workaround would be to simply override
seg_mask to 0. That's enough to make sure that no segment looks eligible
for merging.
Robin.
+
for_each_sg(sg, s, nents, i) {
/* Restore this segment's original unaligned fields first */
unsigned int s_iova_off = sg_dma_address(s);
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/ehl: Implement W/A 22010492432 (rev2)
== Series Details == Series: drm/i915/ehl: Implement W/A 22010492432 (rev2) URL : https://patchwork.freedesktop.org/series/83135/ State : warning == Summary == $ dim checkpatch origin/drm-tip 003c5f8bf5bd drm/i915/ehl: Implement W/A 22010492432 -:34: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #34: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2646: + return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) && + IS_JSL_EHL_REVID(i915, EHL_REVID_B0, EHL_REVID_B0)) || total: 0 errors, 0 warnings, 1 checks, 42 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for mm/highmem: Preemptible variant of kmap_atomic & friends (rev2)
== Series Details == Series: mm/highmem: Preemptible variant of kmap_atomic & friends (rev2) URL : https://patchwork.freedesktop.org/series/83421/ State : failure == Summary == Applying: mm/highmem: Un-EXPORT __kmap_atomic_idx() Applying: highmem: Remove unused functions Applying: fs: Remove asm/kmap_types.h includes Applying: sh/highmem: Remove all traces of unused cruft Applying: asm-generic: Provide kmap_size.h Applying: highmem: Provide generic variant of kmap_atomic* Applying: highmem: Make DEBUG_HIGHMEM functional Applying: x86/mm/highmem: Use generic kmap atomic implementation Applying: arc/mm/highmem: Use generic kmap atomic implementation Applying: ARM: highmem: Switch to generic kmap atomic Applying: csky/mm/highmem: Switch to generic kmap atomic Applying: microblaze/mm/highmem: Switch to generic kmap atomic Applying: mips/mm/highmem: Switch to generic kmap atomic Applying: nds32/mm/highmem: Switch to generic kmap atomic Applying: powerpc/mm/highmem: Switch to generic kmap atomic Applying: sparc/mm/highmem: Switch to generic kmap atomic Applying: xtensa/mm/highmem: Switch to generic kmap atomic Applying: highmem: Get rid of kmap_types.h Applying: mm/highmem: Remove the old kmap_atomic cruft Applying: io-mapping: Cleanup atomic iomap Applying: Documentation/io-mapping: Remove outdated blurb Applying: highmem: High implementation details and document API Applying: sched: Make migrate_disable/enable() independent of RT error: sha1 information is lacking or useless (include/linux/kernel.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0023 sched: Make migrate_disable/enable() independent of RT When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH V2] drm/i915/ehl: Implement W/A 22010492432
As per W/A implemented for TGL to program half of the nominal
DCO divider fraction value which is also applicable on EHL.
Changes since V1:
- ehl_ used as to keep earliest platform prefix
- WA required B0 stepping onwards
Cc: Deak Imre
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 -
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index eaef7a2d041f..cb6ebf627c04 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2636,13 +2636,16 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
intel_crtc_state *crtc_state)
}
/*
- * Display WA #22010492432: tgl
+ * Display WA #22010492432: ehl, tgl
* Program half of the nominal DCO divider fraction value.
*/
static bool
-tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
{
- return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
+ return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
+ IS_JSL_EHL_REVID(i915, EHL_REVID_B0, EHL_REVID_B0)) ||
+ IS_TIGERLAKE(i915)) &&
+ i915->dpll.ref_clks.nssc == 38400;
}
static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
@@ -2696,7 +2699,7 @@ static int __cnl_ddi_wrpll_get_freq(struct
drm_i915_private *dev_priv,
dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
DPLL_CFGCR0_DCO_FRACTION_SHIFT;
- if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
+ if (ehl_combo_pll_div_frac_wa_needed(dev_priv))
dco_fraction *= 2;
dco_freq += (dco_fraction * ref_clock) / 0x8000;
@@ -3086,7 +3089,7 @@ static void icl_calc_dpll_state(struct drm_i915_private
*i915,
memset(pll_state, 0, sizeof(*pll_state));
- if (tgl_combo_pll_div_frac_wa_needed(i915))
+ if (ehl_combo_pll_div_frac_wa_needed(i915))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d548e10e1600..8bf59b57efc9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1560,6 +1560,7 @@ extern const struct i915_rev_steppings kbl_revids[];
(IS_ICELAKE(p) && IS_REVID(p, since, until))
#define EHL_REVID_A00x0
+#define EHL_REVID_B00x2
#define IS_JSL_EHL_REVID(p, since, until) \
(IS_JSL_EHL(p) && IS_REVID(p, since, until))
--
2.28.0
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Re: [Intel-gfx] [PATCH v4 21/61] drm/i915: Pass ww ctx to intel_pin_to_display_plane
On 10/16/20 12:44 PM, Maarten Lankhorst wrote: Instead of multiple lockings, lock the object once, and perform the ww dance around attach_phys and pin_pages. Signed-off-by: Maarten Lankhorst --- Not familiar with the code, but looks good from what I can tell. Reviewed-by: Thomas Hellström ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [patch V4 24/37] sched: highmem: Store local kmaps in task struct
Instead of storing the map per CPU provide and use per task storage. That
prepares for local kmaps which are preemptible.
The context switch code is preparatory and not yet in use because
kmap_atomic() runs with preemption disabled. Will be made usable in the
next step.
The context switch logic is safe even when an interrupt happens after
clearing or before restoring the kmaps. The kmap index in task struct is
not modified so any nesting kmap in an interrupt will use unused indices
and on return the counter is the same as before.
Also add an assert into the return to user space code. Going back to user
space with an active kmap local is a nono.
Signed-off-by: Thomas Gleixner
---
V4: Use the version which actually compiles and works
V3: Handle the debug case correctly
---
include/linux/highmem-internal.h | 10 +++
include/linux/sched.h|9 +++
kernel/entry/common.c|2
kernel/fork.c|1
kernel/sched/core.c | 18 +++
mm/highmem.c | 99 +++
6 files changed, 129 insertions(+), 10 deletions(-)
--- a/include/linux/highmem-internal.h
+++ b/include/linux/highmem-internal.h
@@ -9,6 +9,16 @@
void *__kmap_local_pfn_prot(unsigned long pfn, pgprot_t prot);
void *__kmap_local_page_prot(struct page *page, pgprot_t prot);
void kunmap_local_indexed(void *vaddr);
+void kmap_local_fork(struct task_struct *tsk);
+void __kmap_local_sched_out(void);
+void __kmap_local_sched_in(void);
+static inline void kmap_assert_nomap(void)
+{
+ DEBUG_LOCKS_WARN_ON(current->kmap_ctrl.idx);
+}
+#else
+static inline void kmap_local_fork(struct task_struct *tsk) { }
+static inline void kmap_assert_nomap(void) { }
#endif
#ifdef CONFIG_HIGHMEM
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
/* task_struct member predeclarations (sorted alphabetically): */
struct audit_context;
@@ -629,6 +630,13 @@ struct wake_q_node {
struct wake_q_node *next;
};
+struct kmap_ctrl {
+#ifdef CONFIG_KMAP_LOCAL
+ int idx;
+ pte_t pteval[KM_MAX_IDX];
+#endif
+};
+
struct task_struct {
#ifdef CONFIG_THREAD_INFO_IN_TASK
/*
@@ -1294,6 +1302,7 @@ struct task_struct {
unsigned intsequential_io;
unsigned intsequential_io_avg;
#endif
+ struct kmap_ctrlkmap_ctrl;
#ifdef CONFIG_DEBUG_ATOMIC_SLEEP
unsigned long task_state_change;
#endif
--- a/kernel/entry/common.c
+++ b/kernel/entry/common.c
@@ -2,6 +2,7 @@
#include
#include
+#include
#include
#include
@@ -194,6 +195,7 @@ static void exit_to_user_mode_prepare(st
/* Ensure that the address limit is intact and no locks are held */
addr_limit_user_check();
+ kmap_assert_nomap();
lockdep_assert_irqs_disabled();
lockdep_sys_exit();
}
--- a/kernel/fork.c
+++ b/kernel/fork.c
@@ -930,6 +930,7 @@ static struct task_struct *dup_task_stru
account_kernel_stack(tsk, 1);
kcov_task_init(tsk);
+ kmap_local_fork(tsk);
#ifdef CONFIG_FAULT_INJECTION
tsk->fail_nth = 0;
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -4053,6 +4053,22 @@ static inline void finish_lock_switch(st
# define finish_arch_post_lock_switch()do { } while (0)
#endif
+static inline void kmap_local_sched_out(void)
+{
+#ifdef CONFIG_KMAP_LOCAL
+ if (unlikely(current->kmap_ctrl.idx))
+ __kmap_local_sched_out();
+#endif
+}
+
+static inline void kmap_local_sched_in(void)
+{
+#ifdef CONFIG_KMAP_LOCAL
+ if (unlikely(current->kmap_ctrl.idx))
+ __kmap_local_sched_in();
+#endif
+}
+
/**
* prepare_task_switch - prepare to switch tasks
* @rq: the runqueue preparing to switch
@@ -4075,6 +4091,7 @@ prepare_task_switch(struct rq *rq, struc
perf_event_task_sched_out(prev, next);
rseq_preempt(prev);
fire_sched_out_preempt_notifiers(prev, next);
+ kmap_local_sched_out();
prepare_task(next);
prepare_arch_switch(next);
}
@@ -4141,6 +4158,7 @@ static struct rq *finish_task_switch(str
finish_lock_switch(rq);
finish_arch_post_lock_switch();
kcov_finish_switch(current);
+ kmap_local_sched_in();
fire_sched_in_preempt_notifiers(current);
/*
--- a/mm/highmem.c
+++ b/mm/highmem.c
@@ -365,8 +365,6 @@ EXPORT_SYMBOL(kunmap_high);
#include
-static DEFINE_PER_CPU(int, __kmap_local_idx);
-
/*
* With DEBUG_HIGHMEM the stack depth is doubled and every second
* slot is unused which acts as a guard page
@@ -379,23 +377,21 @@ static DEFINE_PER_CPU(int, __kmap_local_
static inline int kmap_local_idx_push(void)
{
- int idx = __this_cpu_add_return(__kmap_local_idx, KM_INCR) - 1;
-
WARN_ON_ONCE(in_irq() && !irqs_disabled());
-
Re: [Intel-gfx] [PATCH v4 01/61] drm/i915: Move cmd parser pinning to execbuffer
On 10/16/20 12:43 PM, Maarten Lankhorst wrote: We need to get rid of allocations in the cmd parser, because it needs to be called from a signaling context, first move all pinning to execbuf, where we already hold all locks. Allocate jump_whitelist in the execbuffer, and add annotations around intel_engine_cmd_parser(), to ensure we only call the command parser without allocating any memory, or taking any locks we're not supposed to. Because i915_gem_object_get_page() may also allocate memory, add a path to i915_gem_object_get_sg() that prevents memory allocations, and walk the sg list manually. It should be similarly fast. This has the added benefit of being able to catch all memory allocation errors before the point of no return, and return -ENOMEM safely to the execbuf submitter. Signed-off-by: Maarten Lankhorst Acked-by: Thomas Hellström ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch V3 24/37] sched: highmem: Store local kmaps in task struct
On Tue, Nov 03 2020 at 10:27, Thomas Gleixner wrote:
> +struct kmap_ctrl {
> +#ifdef CONFIG_KMAP_LOCAL
> + int idx;
> + pte_t pteval[KM_TYPE_NR];
I'm a moron. Fixed it on the test machine ...
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for mm/highmem: Preemptible variant of kmap_atomic & friends
== Series Details == Series: mm/highmem: Preemptible variant of kmap_atomic & friends URL : https://patchwork.freedesktop.org/series/83421/ State : failure == Summary == Applying: mm/highmem: Un-EXPORT __kmap_atomic_idx() Applying: highmem: Remove unused functions Applying: fs: Remove asm/kmap_types.h includes Applying: sh/highmem: Remove all traces of unused cruft Applying: asm-generic: Provide kmap_size.h Applying: highmem: Provide generic variant of kmap_atomic* Applying: highmem: Make DEBUG_HIGHMEM functional Applying: x86/mm/highmem: Use generic kmap atomic implementation Applying: arc/mm/highmem: Use generic kmap atomic implementation Applying: ARM: highmem: Switch to generic kmap atomic Applying: csky/mm/highmem: Switch to generic kmap atomic Applying: microblaze/mm/highmem: Switch to generic kmap atomic Applying: mips/mm/highmem: Switch to generic kmap atomic Applying: nds32/mm/highmem: Switch to generic kmap atomic Applying: powerpc/mm/highmem: Switch to generic kmap atomic Applying: sparc/mm/highmem: Switch to generic kmap atomic Applying: xtensa/mm/highmem: Switch to generic kmap atomic Applying: highmem: Get rid of kmap_types.h Applying: mm/highmem: Remove the old kmap_atomic cruft Applying: io-mapping: Cleanup atomic iomap Applying: Documentation/io-mapping: Remove outdated blurb Applying: highmem: High implementation details and document API Applying: sched: Make migrate_disable/enable() independent of RT error: sha1 information is lacking or useless (include/linux/kernel.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0023 sched: Make migrate_disable/enable() independent of RT When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 59/61] drm/i915/selftests: Prepare gtt tests for obj->mm.lock removal
On 11/3/20 2:27 PM, Thomas Hellström wrote: On 10/16/20 12:44 PM, Maarten Lankhorst wrote: We need to lock the global gtt dma_resv, use i915_vm_lock_objects to handle this correctly. Add ww handling for this where required. Add the object lock around unpin/put pages, and use the unlocked versions of pin_pages and pin_map where required. Signed-off-by: Maarten Lankhorst For this and the patches in the series that start with drm/i915/selftests: Reviewed-by: Thomas Hellström Sigh. Confused by all email addresses :) Reviewed-by: Thomas Hellström ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 60/61] drm/i915: Finally remove obj->mm.lock.
On 10/16/20 12:44 PM, Maarten Lankhorst wrote: With all callers and selftests fixed to use ww locking, we can now finally remove this lock. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 - drivers/gpu/drm/i915/gem/i915_gem_object.h| 5 +-- .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 - drivers/gpu/drm/i915/gem/i915_gem_pages.c | 38 --- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 34 - drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 37 +- drivers/gpu/drm/i915/gem/i915_gem_shrinker.h | 4 +- drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 2 - drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +- drivers/gpu/drm/i915/i915_debugfs.c | 4 +- drivers/gpu/drm/i915/i915_gem.c | 8 +--- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 13 files changed, 53 insertions(+), 89 deletions(-) Reviewed-by: Thomas Hellström ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 59/61] drm/i915/selftests: Prepare gtt tests for obj->mm.lock removal
On 10/16/20 12:44 PM, Maarten Lankhorst wrote: We need to lock the global gtt dma_resv, use i915_vm_lock_objects to handle this correctly. Add ww handling for this where required. Add the object lock around unpin/put pages, and use the unlocked versions of pin_pages and pin_map where required. Signed-off-by: Maarten Lankhorst For this and the patches in the series that start with drm/i915/selftests: Reviewed-by: Thomas Hellström ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 40/61] drm/i915/selftests: Prepare huge_pages testcases for obj->mm.lock removal.
On 10/16/20 12:44 PM, Maarten Lankhorst wrote: Straightforward conversion, just convert a bunch of calls to unlocked versions. Signed-off-by: Maarten Lankhorst --- Reviewed-by: Thomas Hellström ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Flush xcs before tgl breadcrumbs
Chris Wilson writes:
> In a simple test case that writes to scratch and then busy-waits for the
> batch to be signaled, we observe that the signal is before the write is
> posted. That is bad news.
>
> Splitting the flush + write_dword into two separate flush_dw prevents
> the issue from being reproduced, we can presume the post-sync op is not
> so post-sync.
>
Only thing that is mildly surpricing is that first one doesnt
need postop write.
> Testcase: igt/gem_exec_fence/parallel
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: sta...@vger.kernel.org
Acked-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index d0be98b67138..a437140a987d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -5047,7 +5047,8 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request
> *request, u32 *cs)
>
> static u32 *gen12_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
> {
> - return gen12_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
> + cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
> + return gen12_emit_fini_breadcrumb_tail(rq, cs);
> }
>
> static u32 *
> --
> 2.20.1
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[Intel-gfx] [PULL] drm-intel-next-queued
Hi Dave & Daniel - Here's the first batch of i915 changes for v5.11. I'm trying out tagging and generating the pull request directly from drm-intel-next-queued in one step this time, skipping the previous two-step process. The idea is to ditch drm-intel-next-queued in the future, and do everything directly to/from drm-intel-next. BR, Jani. drm-intel-next-queued-2020-11-03: drm/i915 features for v5.11 Highlights: - More DG1 enabling (Lucas, Matt, Aditya, Anshuman, Clinton, Matt, Stuart, Venkata) - Integer scaling filter support (Pankaj Bharadiya) - Asynchronous flip support (Karthik) Generic: - Fix gen12 forcewake tables (Matt) - Haswell PCI ID updates (Alexei Podtelezhnikov) Display: - ICL+ DSI command mode enabling (Vandita) - Shutdown displays grafecully on reboot/shutdown (Ville) - Don't register display debugfs when there is no display (Lucas) - Fix RKL CDCLK table (Matt) - Limit EHL/JSL eDP to HBR2 (José) - Handle incorrectly set (by BIOS) PLLs and DP link rates at probe (Imre) - Fix mode valid check wrt bpp for "YCbCr 4:2:0 only" modes (Ville) - State checker and dump fixes (Ville) - DP AUX backlight updates (Aaron Ma, Sean Paul) - Add DP LTTPR non-transparent link training mode (Imre) - PSR2 selective fetch enabling (José) - VBT updates (José) - HDCP updates (Ramalingam) Cleanups and refactoring: - HPD pin, AUX channel, and Type-C port identifier cleanup (Ville) - Hotplug and irq refactoring (Ville) - Better DDI encoder and AUX channel names (Ville) - Color LUT code cleanups (Ville) - Combo PHY code cleanups (Ville) - LSPCON code cleanups (Ville) - Documentation fixes (Mauro, Chris) BR, Jani. The following changes since commit 8fea92536e3efff14fa4cde7ed37c595b40a52b5: drm/i915: Update DRIVER_DATE to 20200917 (2020-09-17 16:43:57 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-queued-2020-11-03 for you to fetch changes up to 139caf7ca2866cd0a45814ff938cb0c33920a266: drm/i915: Update DRIVER_DATE to 20201103 (2020-11-03 14:21:25 +0200) drm/i915 features for v5.11 Highlights: - More DG1 enabling (Lucas, Matt, Aditya, Anshuman, Clinton, Matt, Stuart, Venkata) - Integer scaling filter support (Pankaj Bharadiya) - Asynchronous flip support (Karthik) Generic: - Fix gen12 forcewake tables (Matt) - Haswell PCI ID updates (Alexei Podtelezhnikov) Display: - ICL+ DSI command mode enabling (Vandita) - Shutdown displays grafecully on reboot/shutdown (Ville) - Don't register display debugfs when there is no display (Lucas) - Fix RKL CDCLK table (Matt) - Limit EHL/JSL eDP to HBR2 (José) - Handle incorrectly set (by BIOS) PLLs and DP link rates at probe (Imre) - Fix mode valid check wrt bpp for "YCbCr 4:2:0 only" modes (Ville) - State checker and dump fixes (Ville) - DP AUX backlight updates (Aaron Ma, Sean Paul) - Add DP LTTPR non-transparent link training mode (Imre) - PSR2 selective fetch enabling (José) - VBT updates (José) - HDCP updates (Ramalingam) Cleanups and refactoring: - HPD pin, AUX channel, and Type-C port identifier cleanup (Ville) - Hotplug and irq refactoring (Ville) - Better DDI encoder and AUX channel names (Ville) - Color LUT code cleanups (Ville) - Combo PHY code cleanups (Ville) - LSPCON code cleanups (Ville) - Documentation fixes (Mauro, Chris) Aaron Ma (2): drm/i915/dpcd_bl: uncheck PWM_PIN_CAP when detect eDP backlight capabilities drm/i915: Force DPCD backlight mode for BOE 2270 panel Aditya Swarup (3): drm/i915/display: allow to skip certain power wells drm/i915/dg1: Add DPLL macros for DG1 drm/i915/dg1: Add and setup DPLLs for DG1 Alexei Podtelezhnikov (4): drm/i915: Update Haswell PCI IDs drm/i915: Reclassify SKL 0x192a as GT3 drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT drm/i915: Add SKL GT1.5 PCI IDs Anshuman Gupta (2): drm/i915/dg1: DG1 does not support DC6 drm/i915/dg1: Update DMC_DEBUG register Chris Wilson (5): drm/i915: Force VT'd workarounds when running as a guest OS drm/i915: Drop runtime-pm assert from vgpu io accessors drm/i915/display: Unkerneldoc cnl_program_nearest_filter_coefs drm/i915: Reset the interrupt mask on disabling interrupts drm/i915: Reduce severity for fixing up mistaken VBT tc->legacy_port Clinton A Taylor (1): drm/i915/dg1: invert HPD pins Imre Deak (12): drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming drm/i915: Move the initial fastset commit check to encoder hooks drm/i915: Check for unsupported DP link rates during initial commit drm/i915: Add an encoder hook to sanitize its state during init/resume drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock drm/i915: Fix DP link training pattern mask drm/i915: Simplify
Re: [Intel-gfx] [patch V3 03/37] fs: Remove asm/kmap_types.h includes
On Tue, Nov 03, 2020 at 10:27:15AM +0100, Thomas Gleixner wrote: > Historical leftovers from the time where kmap() had fixed slots. > > Signed-off-by: Thomas Gleixner > Cc: Alexander Viro > Cc: Benjamin LaHaise > Cc: linux-fsde...@vger.kernel.org > Cc: linux-...@kvack.org > Cc: Chris Mason > Cc: Josef Bacik > Cc: David Sterba Acked-by: David Sterba For the btrfs bits > fs/btrfs/ctree.h |1 - > --- a/fs/btrfs/ctree.h > +++ b/fs/btrfs/ctree.h > @@ -17,7 +17,6 @@ > #include > #include > #include > -#include > #include > #include > #include ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 0/7] Convert the intel iommu driver to the dma-iommu api
Hi, On Tue, Nov 03, 2020 at 11:58:26AM +0200, Joonas Lahtinen wrote: > Would that work for you? We intend to send the feature pull requests > to DRM for 5.11 in the upcoming weeks. For the IOMMU side it is best to include the workaround for now. When the DRM fixes are merged into v5.11-rc1 together with this conversion, it can be reverted and will not be in 5.11-final. Regards, Joerg ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [patch V3 21/37] Documentation/io-mapping: Remove outdated blurb
The implementation details in the documentation are outdated and not really helpful. Remove them. Signed-off-by: Thomas Gleixner --- V3: New patch --- Documentation/driver-api/io-mapping.rst | 22 -- 1 file changed, 22 deletions(-) --- a/Documentation/driver-api/io-mapping.rst +++ b/Documentation/driver-api/io-mapping.rst @@ -73,25 +73,3 @@ for pages mapped with io_mapping_map_wc. At driver close time, the io_mapping object must be freed:: void io_mapping_free(struct io_mapping *mapping) - -Current Implementation -== - -The initial implementation of these functions uses existing mapping -mechanisms and so provides only an abstraction layer and no new -functionality. - -On 64-bit processors, io_mapping_create_wc calls ioremap_wc for the whole -range, creating a permanent kernel-visible mapping to the resource. The -map_atomic and map functions add the requested offset to the base of the -virtual address returned by ioremap_wc. - -On 32-bit processors with HIGHMEM defined, io_mapping_map_atomic_wc uses -kmap_atomic_pfn to map the specified page in an atomic fashion; -kmap_atomic_pfn isn't really supposed to be used with device pages, but it -provides an efficient mapping for this usage. - -On 32-bit processors without HIGHMEM defined, io_mapping_map_atomic_wc and -io_mapping_map_wc both use ioremap_wc, a terribly inefficient function which -performs an IPI to inform all processors about the new mapping. This results -in a significant performance penalty. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [patch V3 25/37] mm/highmem: Provide kmap_local*
Now that the kmap atomic index is stored in task struct provide a
preemptible variant. On context switch the maps of an outgoing task are
removed and the map of the incoming task are restored. That's obviously
slow, but highmem is slow anyway.
The kmap_local.*() functions can be invoked from both preemptible and
atomic context. kmap local sections disable migration to keep the resulting
virtual mapping address correct, but disable neither pagefaults nor
preemption.
A wholesale conversion of kmap_atomic to be fully preemptible is not
possible because some of the usage sites might rely on the preemption
disable for serialization or on the implicit pagefault disable. Needs to be
done on a case by case basis.
Signed-off-by: Thomas Gleixner
---
V3: Move migrate disable into the actual highmem mapping code so it only
affects real highmem mappings.
V2: Make it more consistent and add commentry
---
include/linux/highmem-internal.h | 48 +++
include/linux/highmem.h | 43 +-
mm/highmem.c |6
3 files changed, 81 insertions(+), 16 deletions(-)
--- a/include/linux/highmem-internal.h
+++ b/include/linux/highmem-internal.h
@@ -69,6 +69,26 @@ static inline void kmap_flush_unused(voi
__kmap_flush_unused();
}
+static inline void *kmap_local_page(struct page *page)
+{
+ return __kmap_local_page_prot(page, kmap_prot);
+}
+
+static inline void *kmap_local_page_prot(struct page *page, pgprot_t prot)
+{
+ return __kmap_local_page_prot(page, prot);
+}
+
+static inline void *kmap_local_pfn(unsigned long pfn)
+{
+ return __kmap_local_pfn_prot(pfn, kmap_prot);
+}
+
+static inline void __kunmap_local(void *vaddr)
+{
+ kunmap_local_indexed(vaddr);
+}
+
static inline void *kmap_atomic_prot(struct page *page, pgprot_t prot)
{
preempt_disable();
@@ -141,6 +161,28 @@ static inline void kunmap(struct page *p
#endif
}
+static inline void *kmap_local_page(struct page *page)
+{
+ return page_address(page);
+}
+
+static inline void *kmap_local_page_prot(struct page *page, pgprot_t prot)
+{
+ return kmap_local_page(page);
+}
+
+static inline void *kmap_local_pfn(unsigned long pfn)
+{
+ return kmap_local_page(pfn_to_page(pfn));
+}
+
+static inline void __kunmap_local(void *addr)
+{
+#ifdef ARCH_HAS_FLUSH_ON_KUNMAP
+ kunmap_flush_on_unmap(addr);
+#endif
+}
+
static inline void *kmap_atomic(struct page *page)
{
preempt_disable();
@@ -182,4 +224,10 @@ do {
\
__kunmap_atomic(__addr);\
} while (0)
+#define kunmap_local(__addr) \
+do { \
+ BUILD_BUG_ON(__same_type((__addr), struct page *)); \
+ __kunmap_local(__addr); \
+} while (0)
+
#endif
--- a/include/linux/highmem.h
+++ b/include/linux/highmem.h
@@ -60,24 +60,22 @@ static inline struct page *kmap_to_page(
static inline void kmap_flush_unused(void);
/**
- * kmap_atomic - Atomically map a page for temporary usage
+ * kmap_local_page - Map a page for temporary usage
* @page: Pointer to the page to be mapped
*
* Returns: The virtual address of the mapping
*
- * Side effect: On return pagefaults and preemption are disabled.
- *
* Can be invoked from any context.
*
* Requires careful handling when nesting multiple mappings because the map
* management is stack based. The unmap has to be in the reverse order of
* the map operation:
*
- * addr1 = kmap_atomic(page1);
- * addr2 = kmap_atomic(page2);
+ * addr1 = kmap_local_page(page1);
+ * addr2 = kmap_local_page(page2);
* ...
- * kunmap_atomic(addr2);
- * kunmap_atomic(addr1);
+ * kunmap_local(addr2);
+ * kunmap_local(addr1);
*
* Unmapping addr1 before addr2 is invalid and causes malfunction.
*
@@ -88,10 +86,26 @@ static inline void kmap_flush_unused(voi
* virtual address of the direct mapping. Only real highmem pages are
* temporarily mapped.
*
- * While it is significantly faster than kmap() it comes with restrictions
- * about the pointer validity and the side effects of disabling page faults
- * and preemption. Use it only when absolutely necessary, e.g. from non
- * preemptible contexts.
+ * While it is significantly faster than kmap() for the higmem case it
+ * comes with restrictions about the pointer validity. Only use when really
+ * necessary.
+ *
+ * On HIGHMEM enabled systems mapping a highmem page has the side effect of
+ * disabling migration in order to keep the virtual address stable across
+ * preemption. No caller of kmap_local_page() can rely on this side effect.
+ */
+static inline void *kmap_local_page(struct page *page);
+
+/**
+ * kmap_atomic - Atomically map a page for temporary usage - Deprecated!
+ * @page: Pointer to the page to be
[Intel-gfx] [patch V3 20/37] io-mapping: Cleanup atomic iomap
Switch the atomic iomap implementation over to kmap_local and stick the
preempt/pagefault mechanics into the generic code similar to the
kmap_atomic variants.
Rename the x86 map function in preparation for a non-atomic variant.
Signed-off-by: Thomas Gleixner
---
V2: New patch to make review easier
---
arch/x86/include/asm/iomap.h |9 +
arch/x86/mm/iomap_32.c |6 ++
include/linux/io-mapping.h |8 ++--
3 files changed, 9 insertions(+), 14 deletions(-)
--- a/arch/x86/include/asm/iomap.h
+++ b/arch/x86/include/asm/iomap.h
@@ -13,14 +13,7 @@
#include
#include
-void __iomem *iomap_atomic_pfn_prot(unsigned long pfn, pgprot_t prot);
-
-static inline void iounmap_atomic(void __iomem *vaddr)
-{
- kunmap_local_indexed((void __force *)vaddr);
- pagefault_enable();
- preempt_enable();
-}
+void __iomem *__iomap_local_pfn_prot(unsigned long pfn, pgprot_t prot);
int iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot);
--- a/arch/x86/mm/iomap_32.c
+++ b/arch/x86/mm/iomap_32.c
@@ -44,7 +44,7 @@ void iomap_free(resource_size_t base, un
}
EXPORT_SYMBOL_GPL(iomap_free);
-void __iomem *iomap_atomic_pfn_prot(unsigned long pfn, pgprot_t prot)
+void __iomem *__iomap_local_pfn_prot(unsigned long pfn, pgprot_t prot)
{
/*
* For non-PAT systems, translate non-WB request to UC- just in
@@ -60,8 +60,6 @@ void __iomem *iomap_atomic_pfn_prot(unsi
/* Filter out unsupported __PAGE_KERNEL* bits: */
pgprot_val(prot) &= __default_kernel_pte_mask;
- preempt_disable();
- pagefault_disable();
return (void __force __iomem *)__kmap_local_pfn_prot(pfn, prot);
}
-EXPORT_SYMBOL_GPL(iomap_atomic_pfn_prot);
+EXPORT_SYMBOL_GPL(__iomap_local_pfn_prot);
--- a/include/linux/io-mapping.h
+++ b/include/linux/io-mapping.h
@@ -69,13 +69,17 @@ io_mapping_map_atomic_wc(struct io_mappi
BUG_ON(offset >= mapping->size);
phys_addr = mapping->base + offset;
- return iomap_atomic_pfn_prot(PHYS_PFN(phys_addr), mapping->prot);
+ preempt_disable();
+ pagefault_disable();
+ return __iomap_local_pfn_prot(PHYS_PFN(phys_addr), mapping->prot);
}
static inline void
io_mapping_unmap_atomic(void __iomem *vaddr)
{
- iounmap_atomic(vaddr);
+ kunmap_local_indexed((void __force *)vaddr);
+ pagefault_enable();
+ preempt_enable();
}
static inline void __iomem *
___
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[Intel-gfx] [patch V3 18/37] highmem: Get rid of kmap_types.h
The header is not longer used and on alpha, ia64, openrisc, parisc and um it was completely unused anyway as these architectures have no highmem support. Signed-off-by: Thomas Gleixner --- V3: New patch --- arch/alpha/include/asm/kmap_types.h | 15 --- arch/ia64/include/asm/kmap_types.h | 13 - arch/openrisc/mm/init.c |1 - arch/openrisc/mm/ioremap.c |1 - arch/parisc/include/asm/kmap_types.h | 13 - arch/um/include/asm/fixmap.h |1 - arch/um/include/asm/kmap_types.h | 13 - include/asm-generic/Kbuild |1 - include/asm-generic/kmap_types.h | 11 --- include/linux/highmem.h |2 -- 10 files changed, 71 deletions(-) --- a/arch/alpha/include/asm/kmap_types.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_KMAP_TYPES_H -#define _ASM_KMAP_TYPES_H - -/* Dummy header just to define km_type. */ - -#ifdef CONFIG_DEBUG_HIGHMEM -#define __WITH_KM_FENCE -#endif - -#include - -#undef __WITH_KM_FENCE - -#endif --- a/arch/ia64/include/asm/kmap_types.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_IA64_KMAP_TYPES_H -#define _ASM_IA64_KMAP_TYPES_H - -#ifdef CONFIG_DEBUG_HIGHMEM -#define __WITH_KM_FENCE -#endif - -#include - -#undef __WITH_KM_FENCE - -#endif /* _ASM_IA64_KMAP_TYPES_H */ --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include #include --- a/arch/openrisc/mm/ioremap.c +++ b/arch/openrisc/mm/ioremap.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include --- a/arch/parisc/include/asm/kmap_types.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_KMAP_TYPES_H -#define _ASM_KMAP_TYPES_H - -#ifdef CONFIG_DEBUG_HIGHMEM -#define __WITH_KM_FENCE -#endif - -#include - -#undef __WITH_KM_FENCE - -#endif --- a/arch/um/include/asm/fixmap.h +++ b/arch/um/include/asm/fixmap.h @@ -3,7 +3,6 @@ #define __UM_FIXMAP_H #include -#include #include #include #include --- a/arch/um/include/asm/kmap_types.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2002 Jeff Dike (jd...@karaya.com) - */ - -#ifndef __UM_KMAP_TYPES_H -#define __UM_KMAP_TYPES_H - -/* No more #include "asm/arch/kmap_types.h" ! */ - -#define KM_TYPE_NR 14 - -#endif --- a/include/asm-generic/Kbuild +++ b/include/asm-generic/Kbuild @@ -30,7 +30,6 @@ mandatory-y += irq.h mandatory-y += irq_regs.h mandatory-y += irq_work.h mandatory-y += kdebug.h -mandatory-y += kmap_types.h mandatory-y += kmap_size.h mandatory-y += kprobes.h mandatory-y += linkage.h --- a/include/asm-generic/kmap_types.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_GENERIC_KMAP_TYPES_H -#define _ASM_GENERIC_KMAP_TYPES_H - -#ifdef __WITH_KM_FENCE -# define KM_TYPE_NR 41 -#else -# define KM_TYPE_NR 20 -#endif - -#endif --- a/include/linux/highmem.h +++ b/include/linux/highmem.h @@ -29,8 +29,6 @@ static inline void invalidate_kernel_vma } #endif -#include - /* * Outside of CONFIG_HIGHMEM to support X86 32bit iomap_atomic() cruft. */ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [patch V3 17/37] xtensa/mm/highmem: Switch to generic kmap atomic
No reason having the same code in every architecture
Signed-off-by: Thomas Gleixner
Cc: Chris Zankel
Cc: Max Filippov
Cc: linux-xte...@linux-xtensa.org
---
V3: Remove the kmap types cruft
---
arch/xtensa/Kconfig |1
arch/xtensa/include/asm/fixmap.h |4 +--
arch/xtensa/include/asm/highmem.h | 12 -
arch/xtensa/mm/highmem.c | 46 --
4 files changed, 18 insertions(+), 45 deletions(-)
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -666,6 +666,7 @@ endchoice
config HIGHMEM
bool "High Memory Support"
depends on MMU
+ select KMAP_LOCAL
help
Linux can use the full amount of RAM in the system by
default. However, the default MMUv2 setup only maps the
--- a/arch/xtensa/include/asm/fixmap.h
+++ b/arch/xtensa/include/asm/fixmap.h
@@ -16,7 +16,7 @@
#ifdef CONFIG_HIGHMEM
#include
#include
-#include
+#include
#endif
/*
@@ -39,7 +39,7 @@ enum fixed_addresses {
/* reserved pte's for temporary kernel mappings */
FIX_KMAP_BEGIN,
FIX_KMAP_END = FIX_KMAP_BEGIN +
- (KM_TYPE_NR * NR_CPUS * DCACHE_N_COLORS) - 1,
+ (KM_MAX_IDX * NR_CPUS * DCACHE_N_COLORS) - 1,
#endif
__end_of_fixed_addresses
};
--- a/arch/xtensa/include/asm/highmem.h
+++ b/arch/xtensa/include/asm/highmem.h
@@ -16,9 +16,8 @@
#include
#include
#include
-#include
-#define PKMAP_BASE ((FIXADDR_START - \
+#define PKMAP_BASE ((FIXADDR_START - \
(LAST_PKMAP + 1) * PAGE_SIZE) & PMD_MASK)
#define LAST_PKMAP (PTRS_PER_PTE * DCACHE_N_COLORS)
#define LAST_PKMAP_MASK(LAST_PKMAP - 1)
@@ -68,6 +67,15 @@ static inline void flush_cache_kmaps(voi
flush_cache_all();
}
+enum fixed_addresses kmap_local_map_idx(int type, unsigned long pfn);
+#define arch_kmap_local_map_idxkmap_local_map_idx
+
+enum fixed_addresses kmap_local_unmap_idx(int type, unsigned long addr);
+#define arch_kmap_local_unmap_idx kmap_local_unmap_idx
+
+#define arch_kmap_local_post_unmap(vaddr) \
+ local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE)
+
void kmap_init(void);
#endif
--- a/arch/xtensa/mm/highmem.c
+++ b/arch/xtensa/mm/highmem.c
@@ -12,8 +12,6 @@
#include
#include
-static pte_t *kmap_pte;
-
#if DCACHE_WAY_SIZE > PAGE_SIZE
unsigned int last_pkmap_nr_arr[DCACHE_N_COLORS];
wait_queue_head_t pkmap_map_wait_arr[DCACHE_N_COLORS];
@@ -33,59 +31,25 @@ static inline void kmap_waitqueues_init(
static inline enum fixed_addresses kmap_idx(int type, unsigned long color)
{
- return (type + KM_TYPE_NR * smp_processor_id()) * DCACHE_N_COLORS +
+ return (type + KM_MAX_IDX * smp_processor_id()) * DCACHE_N_COLORS +
color;
}
-void *kmap_atomic_high_prot(struct page *page, pgprot_t prot)
+enum fixed_addresses kmap_local_map_idx(int type, unsigned long pfn)
{
- enum fixed_addresses idx;
- unsigned long vaddr;
-
- idx = kmap_idx(kmap_atomic_idx_push(),
- DCACHE_ALIAS(page_to_phys(page)));
- vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-#ifdef CONFIG_DEBUG_HIGHMEM
- BUG_ON(!pte_none(*(kmap_pte + idx)));
-#endif
- set_pte(kmap_pte + idx, mk_pte(page, prot));
-
- return (void *)vaddr;
+ return kmap_idx(type, DCACHE_ALIAS(pfn << PAGE_SHIFT));
}
-EXPORT_SYMBOL(kmap_atomic_high_prot);
-void kunmap_atomic_high(void *kvaddr)
+enum fixed_addresses kmap_local_unmap_idx(int type, unsigned long addr)
{
- if (kvaddr >= (void *)FIXADDR_START &&
- kvaddr < (void *)FIXADDR_TOP) {
- int idx = kmap_idx(kmap_atomic_idx(),
- DCACHE_ALIAS((unsigned long)kvaddr));
-
- /*
-* Force other mappings to Oops if they'll try to access this
-* pte without first remap it. Keeping stale mappings around
-* is a bad idea also, in case the page changes cacheability
-* attributes or becomes a protected page in a hypervisor.
-*/
- pte_clear(_mm, kvaddr, kmap_pte + idx);
- local_flush_tlb_kernel_range((unsigned long)kvaddr,
-(unsigned long)kvaddr + PAGE_SIZE);
-
- kmap_atomic_idx_pop();
- }
+ return kmap_idx(type, DCACHE_ALIAS(addr));
}
-EXPORT_SYMBOL(kunmap_atomic_high);
void __init kmap_init(void)
{
- unsigned long kmap_vstart;
-
/* Check if this memory layout is broken because PKMAP overlaps
* page table.
*/
BUILD_BUG_ON(PKMAP_BASE < TLBTEMP_BASE_1 + TLBTEMP_SIZE);
- /* cache the first kmap pte */
- kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN);
- kmap_pte = virt_to_kpte(kmap_vstart);
kmap_waitqueues_init();
}
[Intel-gfx] [patch V3 28/37] mips/crashdump: Simplify copy_oldmem_page()
Replace kmap_atomic_pfn() with kmap_local_pfn() which is preemptible and
can take page faults.
Remove the indirection of the dump page and the related cruft which is not
longer required.
Signed-off-by: Thomas Gleixner
Cc: Thomas Bogendoerfer
Cc: linux-m...@vger.kernel.org
---
V3: New patch
---
arch/mips/kernel/crash_dump.c | 42 +++---
1 file changed, 7 insertions(+), 35 deletions(-)
--- a/arch/mips/kernel/crash_dump.c
+++ b/arch/mips/kernel/crash_dump.c
@@ -5,8 +5,6 @@
#include
#include
-static void *kdump_buf_page;
-
/**
* copy_oldmem_page - copy one page from "oldmem"
* @pfn: page frame number to be copied
@@ -17,51 +15,25 @@ static void *kdump_buf_page;
* @userbuf: if set, @buf is in user address space, use copy_to_user(),
* otherwise @buf is in kernel address space, use memcpy().
*
- * Copy a page from "oldmem". For this page, there is no pte mapped
+ * Copy a page from "oldmem". For this page, there might be no pte mapped
* in the current kernel.
- *
- * Calling copy_to_user() in atomic context is not desirable. Hence first
- * copying the data to a pre-allocated kernel page and then copying to user
- * space in non-atomic context.
*/
-ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
-size_t csize, unsigned long offset, int userbuf)
+ssize_t copy_oldmem_page(unsigned long pfn, char *buf, size_t csize,
+unsigned long offset, int userbuf)
{
void *vaddr;
if (!csize)
return 0;
- vaddr = kmap_atomic_pfn(pfn);
+ vaddr = kmap_local_pfn(pfn);
if (!userbuf) {
- memcpy(buf, (vaddr + offset), csize);
- kunmap_atomic(vaddr);
+ memcpy(buf, vaddr + offset, csize);
} else {
- if (!kdump_buf_page) {
- pr_warn("Kdump: Kdump buffer page not allocated\n");
-
- return -EFAULT;
- }
- copy_page(kdump_buf_page, vaddr);
- kunmap_atomic(vaddr);
- if (copy_to_user(buf, (kdump_buf_page + offset), csize))
- return -EFAULT;
+ if (copy_to_user(buf, vaddr + offset, csize))
+ csize = -EFAULT;
}
return csize;
}
-
-static int __init kdump_buf_page_init(void)
-{
- int ret = 0;
-
- kdump_buf_page = kmalloc(PAGE_SIZE, GFP_KERNEL);
- if (!kdump_buf_page) {
- pr_warn("Kdump: Failed to allocate kdump buffer page\n");
- ret = -ENOMEM;
- }
-
- return ret;
-}
-arch_initcall(kdump_buf_page_init);
___
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[Intel-gfx] [patch V3 37/37] io-mapping: Remove io_mapping_map_atomic_wc()
No more users. Get rid of it and remove the traces in documentation.
Signed-off-by: Thomas Gleixner
---
V3: New patch
---
Documentation/driver-api/io-mapping.rst | 22 +---
include/linux/io-mapping.h | 42 +---
2 files changed, 9 insertions(+), 55 deletions(-)
--- a/Documentation/driver-api/io-mapping.rst
+++ b/Documentation/driver-api/io-mapping.rst
@@ -21,19 +21,15 @@ mappable, while 'size' indicates how lar
enable. Both are in bytes.
This _wc variant provides a mapping which may only be used with
-io_mapping_map_atomic_wc(), io_mapping_map_local_wc() or
-io_mapping_map_wc().
+io_mapping_map_local_wc() or io_mapping_map_wc().
With this mapping object, individual pages can be mapped either temporarily
or long term, depending on the requirements. Of course, temporary maps are
-more efficient. They come in two flavours::
+more efficient.
void *io_mapping_map_local_wc(struct io_mapping *mapping,
unsigned long offset)
- void *io_mapping_map_atomic_wc(struct io_mapping *mapping,
- unsigned long offset)
-
'offset' is the offset within the defined mapping region. Accessing
addresses beyond the region specified in the creation function yields
undefined results. Using an offset which is not page aligned yields an
@@ -50,9 +46,6 @@ io_mapping_map_local_wc() has a side eff
migration to make the mapping code work. No caller can rely on this side
effect.
-io_mapping_map_atomic_wc() has the side effect of disabling preemption and
-pagefaults. Don't use in new code. Use io_mapping_map_local_wc() instead.
-
Nested mappings need to be undone in reverse order because the mapping
code uses a stack for keeping track of them::
@@ -65,11 +58,10 @@ Nested mappings need to be undone in rev
The mappings are released with::
void io_mapping_unmap_local(void *vaddr)
- void io_mapping_unmap_atomic(void *vaddr)
-'vaddr' must be the value returned by the last io_mapping_map_local_wc() or
-io_mapping_map_atomic_wc() call. This unmaps the specified mapping and
-undoes the side effects of the mapping functions.
+'vaddr' must be the value returned by the last io_mapping_map_local_wc()
+call. This unmaps the specified mapping and undoes eventual side effects of
+the mapping function.
If you need to sleep while holding a mapping, you can use the regular
variant, although this may be significantly slower::
@@ -77,8 +69,8 @@ If you need to sleep while holding a map
void *io_mapping_map_wc(struct io_mapping *mapping,
unsigned long offset)
-This works like io_mapping_map_atomic/local_wc() except it has no side
-effects and the pointer is globaly visible.
+This works like io_mapping_map_local_wc() except it has no side effects and
+the pointer is globaly visible.
The mappings are released with::
--- a/include/linux/io-mapping.h
+++ b/include/linux/io-mapping.h
@@ -60,28 +60,7 @@ io_mapping_fini(struct io_mapping *mappi
iomap_free(mapping->base, mapping->size);
}
-/* Atomic map/unmap */
-static inline void __iomem *
-io_mapping_map_atomic_wc(struct io_mapping *mapping,
-unsigned long offset)
-{
- resource_size_t phys_addr;
-
- BUG_ON(offset >= mapping->size);
- phys_addr = mapping->base + offset;
- preempt_disable();
- pagefault_disable();
- return __iomap_local_pfn_prot(PHYS_PFN(phys_addr), mapping->prot);
-}
-
-static inline void
-io_mapping_unmap_atomic(void __iomem *vaddr)
-{
- kunmap_local_indexed((void __force *)vaddr);
- pagefault_enable();
- preempt_enable();
-}
-
+/* Temporary mappings which are only valid in the current context */
static inline void __iomem *
io_mapping_map_local_wc(struct io_mapping *mapping, unsigned long offset)
{
@@ -163,24 +142,7 @@ io_mapping_unmap(void __iomem *vaddr)
{
}
-/* Atomic map/unmap */
-static inline void __iomem *
-io_mapping_map_atomic_wc(struct io_mapping *mapping,
-unsigned long offset)
-{
- preempt_disable();
- pagefault_disable();
- return io_mapping_map_wc(mapping, offset, PAGE_SIZE);
-}
-
-static inline void
-io_mapping_unmap_atomic(void __iomem *vaddr)
-{
- io_mapping_unmap(vaddr);
- pagefault_enable();
- preempt_enable();
-}
-
+/* Temporary mappings which are only valid in the current context */
static inline void __iomem *
io_mapping_map_local_wc(struct io_mapping *mapping, unsigned long offset)
{
___
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[Intel-gfx] [patch V3 31/37] drm/ttm: Replace kmap_atomic() usage
There is no reason to disable pagefaults and preemption as a side effect of kmap_atomic_prot(). Use kmap_local_page_prot() instead and document the reasoning for the mapping usage with the given pgprot. Remove the NULL pointer check for the map. These functions return a valid address for valid pages and the return was bogus anyway as it would have left preemption and pagefaults disabled. Signed-off-by: Thomas Gleixner Cc: Christian Koenig Cc: Huang Rui Cc: David Airlie Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org --- V3: New patch --- drivers/gpu/drm/ttm/ttm_bo_util.c | 20 1 file changed, 12 insertions(+), 8 deletions(-) --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -181,13 +181,15 @@ static int ttm_copy_io_ttm_page(struct t return -ENOMEM; src = (void *)((unsigned long)src + (page << PAGE_SHIFT)); - dst = kmap_atomic_prot(d, prot); - if (!dst) - return -ENOMEM; + /* +* Ensure that a highmem page is mapped with the correct +* pgprot. For non highmem the mapping is already there. +*/ + dst = kmap_local_page_prot(d, prot); memcpy_fromio(dst, src, PAGE_SIZE); - kunmap_atomic(dst); + kunmap_local(dst); return 0; } @@ -203,13 +205,15 @@ static int ttm_copy_ttm_io_page(struct t return -ENOMEM; dst = (void *)((unsigned long)dst + (page << PAGE_SHIFT)); - src = kmap_atomic_prot(s, prot); - if (!src) - return -ENOMEM; + /* +* Ensure that a highmem page is mapped with the correct +* pgprot. For non highmem the mapping is already there. +*/ + src = kmap_local_page_prot(s, prot); memcpy_toio(dst, src, PAGE_SIZE); - kunmap_atomic(src); + kunmap_local(src); return 0; } ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [patch V3 29/37] ARM: mm: Replace kmap_atomic_pfn()
There is no requirement to disable pagefaults and preemption for these
cache management mappings.
Replace kmap_atomic_pfn() with kmap_local_pfn(). This allows to remove
kmap_atomic_pfn() in the next step.
Signed-off-by: Thomas Gleixner
Cc: Russell King
Cc: linux-arm-ker...@lists.infradead.org
---
V3: New patch
---
arch/arm/mm/cache-feroceon-l2.c |6 +++---
arch/arm/mm/cache-xsc3l2.c |4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -49,9 +49,9 @@ static inline unsigned long l2_get_va(un
* we simply install a virtual mapping for it only for the
* TLB lookup to occur, hence no need to flush the untouched
* memory mapping afterwards (note: a cache flush may happen
-* in some circumstances depending on the path taken in kunmap_atomic).
+* in some circumstances depending on the path taken in kunmap_local).
*/
- void *vaddr = kmap_atomic_pfn(paddr >> PAGE_SHIFT);
+ void *vaddr = kmap_local_pfn(paddr >> PAGE_SHIFT);
return (unsigned long)vaddr + (paddr & ~PAGE_MASK);
#else
return __phys_to_virt(paddr);
@@ -61,7 +61,7 @@ static inline unsigned long l2_get_va(un
static inline void l2_put_va(unsigned long vaddr)
{
#ifdef CONFIG_HIGHMEM
- kunmap_atomic((void *)vaddr);
+ kunmap_local((void *)vaddr);
#endif
}
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -59,7 +59,7 @@ static inline void l2_unmap_va(unsigned
{
#ifdef CONFIG_HIGHMEM
if (va != -1)
- kunmap_atomic((void *)va);
+ kunmap_local((void *)va);
#endif
}
@@ -75,7 +75,7 @@ static inline unsigned long l2_map_va(un
* in place for it.
*/
l2_unmap_va(prev_va);
- va = (unsigned long)kmap_atomic_pfn(pa >> PAGE_SHIFT);
+ va = (unsigned long)kmap_local_pfn(pa >> PAGE_SHIFT);
}
return va + (pa_offset >> (32 - PAGE_SHIFT));
#else
___
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[Intel-gfx] [patch V3 32/37] drm/vmgfx: Replace kmap_atomic()
There is no reason to disable pagefaults and preemption as a side effect of
kmap_atomic_prot().
Use kmap_local_page_prot() instead and document the reasoning for the
mapping usage with the given pgprot.
Remove the NULL pointer check for the map. These functions return a valid
address for valid pages and the return was bogus anyway as it would have
left preemption and pagefaults disabled.
Signed-off-by: Thomas Gleixner
Cc: VMware Graphics
Cc: Roland Scheidegger
Cc: David Airlie
Cc: Daniel Vetter
Cc: dri-de...@lists.freedesktop.org
---
V3: New patch
---
drivers/gpu/drm/vmwgfx/vmwgfx_blit.c | 30 --
1 file changed, 12 insertions(+), 18 deletions(-)
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
@@ -375,12 +375,12 @@ static int vmw_bo_cpu_blit_line(struct v
copy_size = min_t(u32, copy_size, PAGE_SIZE - src_page_offset);
if (unmap_src) {
- kunmap_atomic(d->src_addr);
+ kunmap_local(d->src_addr);
d->src_addr = NULL;
}
if (unmap_dst) {
- kunmap_atomic(d->dst_addr);
+ kunmap_local(d->dst_addr);
d->dst_addr = NULL;
}
@@ -388,12 +388,8 @@ static int vmw_bo_cpu_blit_line(struct v
if (WARN_ON_ONCE(dst_page >= d->dst_num_pages))
return -EINVAL;
- d->dst_addr =
- kmap_atomic_prot(d->dst_pages[dst_page],
-d->dst_prot);
- if (!d->dst_addr)
- return -ENOMEM;
-
+ d->dst_addr =
kmap_local_page_prot(d->dst_pages[dst_page],
+ d->dst_prot);
d->mapped_dst = dst_page;
}
@@ -401,12 +397,8 @@ static int vmw_bo_cpu_blit_line(struct v
if (WARN_ON_ONCE(src_page >= d->src_num_pages))
return -EINVAL;
- d->src_addr =
- kmap_atomic_prot(d->src_pages[src_page],
-d->src_prot);
- if (!d->src_addr)
- return -ENOMEM;
-
+ d->src_addr =
kmap_local_page_prot(d->src_pages[src_page],
+ d->src_prot);
d->mapped_src = src_page;
}
diff->do_cpy(diff, d->dst_addr + dst_page_offset,
@@ -436,8 +428,10 @@ static int vmw_bo_cpu_blit_line(struct v
*
* Performs a CPU blit from one buffer object to another avoiding a full
* bo vmap which may exhaust- or fragment vmalloc space.
- * On supported architectures (x86), we're using kmap_atomic which avoids
- * cross-processor TLB- and cache flushes and may, on non-HIGHMEM systems
+ *
+ * On supported architectures (x86), we're using kmap_local_prot() which
+ * avoids cross-processor TLB- and cache flushes. kmap_local_prot() will
+ * either map a highmem page with the proper pgprot on HIGHMEM=y systems or
* reference already set-up mappings.
*
* Neither of the buffer objects may be placed in PCI memory
@@ -500,9 +494,9 @@ int vmw_bo_cpu_blit(struct ttm_buffer_ob
}
out:
if (d.src_addr)
- kunmap_atomic(d.src_addr);
+ kunmap_local(d.src_addr);
if (d.dst_addr)
- kunmap_atomic(d.dst_addr);
+ kunmap_local(d.dst_addr);
return ret;
}
___
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[Intel-gfx] [patch V3 27/37] x86/crashdump/32: Simplify copy_oldmem_page()
Replace kmap_atomic_pfn() with kmap_local_pfn() which is preemptible and
can take page faults.
Remove the indirection of the dump page and the related cruft which is not
longer required.
Signed-off-by: Thomas Gleixner
---
V3: New patch
---
arch/x86/kernel/crash_dump_32.c | 48
1 file changed, 10 insertions(+), 38 deletions(-)
--- a/arch/x86/kernel/crash_dump_32.c
+++ b/arch/x86/kernel/crash_dump_32.c
@@ -13,8 +13,6 @@
#include
-static void *kdump_buf_page;
-
static inline bool is_crashed_pfn_valid(unsigned long pfn)
{
#ifndef CONFIG_X86_PAE
@@ -41,15 +39,11 @@ static inline bool is_crashed_pfn_valid(
* @userbuf: if set, @buf is in user address space, use copy_to_user(),
* otherwise @buf is in kernel address space, use memcpy().
*
- * Copy a page from "oldmem". For this page, there is no pte mapped
- * in the current kernel. We stitch up a pte, similar to kmap_atomic.
- *
- * Calling copy_to_user() in atomic context is not desirable. Hence first
- * copying the data to a pre-allocated kernel page and then copying to user
- * space in non-atomic context.
+ * Copy a page from "oldmem". For this page, there might be no pte mapped
+ * in the current kernel.
*/
-ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
- size_t csize, unsigned long offset, int userbuf)
+ssize_t copy_oldmem_page(unsigned long pfn, char *buf, size_t csize,
+unsigned long offset, int userbuf)
{
void *vaddr;
@@ -59,38 +53,16 @@ ssize_t copy_oldmem_page(unsigned long p
if (!is_crashed_pfn_valid(pfn))
return -EFAULT;
- vaddr = kmap_atomic_pfn(pfn);
+ vaddr = kmap_local_pfn(pfn);
if (!userbuf) {
- memcpy(buf, (vaddr + offset), csize);
- kunmap_atomic(vaddr);
+ memcpy(buf, vaddr + offset, csize);
} else {
- if (!kdump_buf_page) {
- printk(KERN_WARNING "Kdump: Kdump buffer page not"
- " allocated\n");
- kunmap_atomic(vaddr);
- return -EFAULT;
- }
- copy_page(kdump_buf_page, vaddr);
- kunmap_atomic(vaddr);
- if (copy_to_user(buf, (kdump_buf_page + offset), csize))
- return -EFAULT;
+ if (copy_to_user(buf, vaddr + offset, csize))
+ csize = -EFAULT;
}
- return csize;
-}
+ kunmap_local(vaddr);
-static int __init kdump_buf_page_init(void)
-{
- int ret = 0;
-
- kdump_buf_page = kmalloc(PAGE_SIZE, GFP_KERNEL);
- if (!kdump_buf_page) {
- printk(KERN_WARNING "Kdump: Failed to allocate kdump buffer"
-" page\n");
- ret = -ENOMEM;
- }
-
- return ret;
+ return csize;
}
-arch_initcall(kdump_buf_page_init);
___
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[Intel-gfx] [patch V3 36/37] drm/i915: Replace io_mapping_map_atomic_wc()
None of these mapping requires the side effect of disabling pagefaults and
preemption.
Use io_mapping_map_local_wc() instead, and clean up gtt_user_read() and
gtt_user_write() to use a plain copy_from_user() as the local maps are not
disabling pagefaults.
Signed-off-by: Thomas Gleixner
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: David Airlie
Cc: Daniel Vetter
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
---
V3: New patch
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c |7 +---
drivers/gpu/drm/i915/i915_gem.c| 40 -
drivers/gpu/drm/i915/selftests/i915_gem.c |4 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |8 ++---
4 files changed, 22 insertions(+), 37 deletions(-)
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1081,7 +1081,7 @@ static void reloc_cache_reset(struct rel
struct i915_ggtt *ggtt = cache_to_ggtt(cache);
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
- io_mapping_unmap_atomic((void __iomem *)vaddr);
+ io_mapping_unmap_local((void __iomem *)vaddr);
if (drm_mm_node_allocated(>node)) {
ggtt->vm.clear_range(>vm,
@@ -1147,7 +1147,7 @@ static void *reloc_iomap(struct drm_i915
if (cache->vaddr) {
intel_gt_flush_ggtt_writes(ggtt->vm.gt);
- io_mapping_unmap_atomic((void __force __iomem *)
unmask_page(cache->vaddr));
+ io_mapping_unmap_local((void __force __iomem *)
unmask_page(cache->vaddr));
} else {
struct i915_vma *vma;
int err;
@@ -1195,8 +1195,7 @@ static void *reloc_iomap(struct drm_i915
offset += page << PAGE_SHIFT;
}
- vaddr = (void __force *)io_mapping_map_atomic_wc(>iomap,
-offset);
+ vaddr = (void __force *)io_mapping_map_local_wc(>iomap, offset);
cache->page = page;
cache->vaddr = (unsigned long)vaddr;
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -379,22 +379,15 @@ gtt_user_read(struct io_mapping *mapping
char __user *user_data, int length)
{
void __iomem *vaddr;
- unsigned long unwritten;
+ bool fail = false;
/* We can use the cpu mem copy function because this is X86. */
- vaddr = io_mapping_map_atomic_wc(mapping, base);
- unwritten = __copy_to_user_inatomic(user_data,
- (void __force *)vaddr + offset,
- length);
- io_mapping_unmap_atomic(vaddr);
- if (unwritten) {
- vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
- unwritten = copy_to_user(user_data,
-(void __force *)vaddr + offset,
-length);
- io_mapping_unmap(vaddr);
- }
- return unwritten;
+ vaddr = io_mapping_map_local_wc(mapping, base);
+ if (copy_to_user(user_data, (void __force *)vaddr + offset, length))
+ fail = true;
+ io_mapping_unmap_local(vaddr);
+
+ return fail;
}
static int
@@ -557,21 +550,14 @@ ggtt_write(struct io_mapping *mapping,
char __user *user_data, int length)
{
void __iomem *vaddr;
- unsigned long unwritten;
+ bool fail = false;
/* We can use the cpu mem copy function because this is X86. */
- vaddr = io_mapping_map_atomic_wc(mapping, base);
- unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr +
offset,
- user_data, length);
- io_mapping_unmap_atomic(vaddr);
- if (unwritten) {
- vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
- unwritten = copy_from_user((void __force *)vaddr + offset,
- user_data, length);
- io_mapping_unmap(vaddr);
- }
-
- return unwritten;
+ vaddr = io_mapping_map_local_wc(mapping, base);
+ if (copy_from_user((void __force *)vaddr + offset, user_data, length))
+ fail = true;
+ io_mapping_unmap_local(vaddr);
+ return fail;
}
/**
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -57,12 +57,12 @@ static void trash_stolen(struct drm_i915
ggtt->vm.insert_page(>vm, dma, slot, I915_CACHE_NONE, 0);
- s = io_mapping_map_atomic_wc(>iomap, slot);
+ s = io_mapping_map_local_wc(>iomap, slot);
for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) {
prng = next_pseudo_random32(prng);
iowrite32(prng, [x]);
}
-
[Intel-gfx] [patch V3 30/37] highmem: Remove kmap_atomic_pfn()
No more users.
Signed-off-by: Thomas Gleixner
---
V3: New patch
---
include/linux/highmem-internal.h | 12
1 file changed, 12 deletions(-)
--- a/include/linux/highmem-internal.h
+++ b/include/linux/highmem-internal.h
@@ -99,13 +99,6 @@ static inline void *kmap_atomic(struct p
return kmap_atomic_prot(page, kmap_prot);
}
-static inline void *kmap_atomic_pfn(unsigned long pfn)
-{
- preempt_disable();
- pagefault_disable();
- return __kmap_local_pfn_prot(pfn, kmap_prot);
-}
-
static inline void __kunmap_atomic(void *addr)
{
kunmap_local_indexed(addr);
@@ -193,11 +186,6 @@ static inline void *kmap_atomic_prot(str
return kmap_atomic(page);
}
-static inline void *kmap_atomic_pfn(unsigned long pfn)
-{
- return kmap_atomic(pfn_to_page(pfn));
-}
-
static inline void __kunmap_atomic(void *addr)
{
#ifdef ARCH_HAS_FLUSH_ON_KUNMAP
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[Intel-gfx] [patch V3 26/37] io-mapping: Provide iomap_local variant
Similar to kmap local provide a iomap local variant which only disables migration, but neither disables pagefaults nor preemption. Signed-off-by: Thomas Gleixner --- V3: Restrict migrate disable to the 32bit mapping case and update documentation. V2: Split out from the large combo patch and add the !IOMAP_ATOMIC variants --- Documentation/driver-api/io-mapping.rst | 76 +++- include/linux/io-mapping.h | 30 +++- 2 files changed, 74 insertions(+), 32 deletions(-) --- a/Documentation/driver-api/io-mapping.rst +++ b/Documentation/driver-api/io-mapping.rst @@ -20,55 +20,71 @@ as it would consume too much of the kern mappable, while 'size' indicates how large a mapping region to enable. Both are in bytes. -This _wc variant provides a mapping which may only be used -with the io_mapping_map_atomic_wc or io_mapping_map_wc. +This _wc variant provides a mapping which may only be used with +io_mapping_map_atomic_wc(), io_mapping_map_local_wc() or +io_mapping_map_wc(). + +With this mapping object, individual pages can be mapped either temporarily +or long term, depending on the requirements. Of course, temporary maps are +more efficient. They come in two flavours:: -With this mapping object, individual pages can be mapped either atomically -or not, depending on the necessary scheduling environment. Of course, atomic -maps are more efficient:: + void *io_mapping_map_local_wc(struct io_mapping *mapping, + unsigned long offset) void *io_mapping_map_atomic_wc(struct io_mapping *mapping, unsigned long offset) -'offset' is the offset within the defined mapping region. -Accessing addresses beyond the region specified in the -creation function yields undefined results. Using an offset -which is not page aligned yields an undefined result. The -return value points to a single page in CPU address space. - -This _wc variant returns a write-combining map to the -page and may only be used with mappings created by -io_mapping_create_wc +'offset' is the offset within the defined mapping region. Accessing +addresses beyond the region specified in the creation function yields +undefined results. Using an offset which is not page aligned yields an +undefined result. The return value points to a single page in CPU address +space. -Note that the task may not sleep while holding this page -mapped. +This _wc variant returns a write-combining map to the page and may only be +used with mappings created by io_mapping_create_wc() -:: +Temporary mappings are only valid in the context of the caller. The mapping +is not guaranteed to be globaly visible. - void io_mapping_unmap_atomic(void *vaddr) +io_mapping_map_local_wc() has a side effect on X86 32bit as it disables +migration to make the mapping code work. No caller can rely on this side +effect. + +io_mapping_map_atomic_wc() has the side effect of disabling preemption and +pagefaults. Don't use in new code. Use io_mapping_map_local_wc() instead. -'vaddr' must be the value returned by the last -io_mapping_map_atomic_wc call. This unmaps the specified -page and allows the task to sleep once again. +Nested mappings need to be undone in reverse order because the mapping +code uses a stack for keeping track of them:: -If you need to sleep while holding the lock, you can use the non-atomic -variant, although they may be significantly slower. + addr1 = io_mapping_map_local_wc(map1, offset1); + addr2 = io_mapping_map_local_wc(map2, offset2); + ... + io_mapping_unmap_local(addr2); + io_mapping_unmap_local(addr1); -:: +The mappings are released with:: + + void io_mapping_unmap_local(void *vaddr) + void io_mapping_unmap_atomic(void *vaddr) + +'vaddr' must be the value returned by the last io_mapping_map_local_wc() or +io_mapping_map_atomic_wc() call. This unmaps the specified mapping and +undoes the side effects of the mapping functions. + +If you need to sleep while holding a mapping, you can use the regular +variant, although this may be significantly slower:: void *io_mapping_map_wc(struct io_mapping *mapping, unsigned long offset) -This works like io_mapping_map_atomic_wc except it allows -the task to sleep while holding the page mapped. - +This works like io_mapping_map_atomic/local_wc() except it has no side +effects and the pointer is globaly visible. -:: +The mappings are released with:: void io_mapping_unmap(void *vaddr) -This works like io_mapping_unmap_atomic, except it is used -for pages mapped with io_mapping_map_wc. +Use for pages mapped with io_mapping_map_wc(). At driver close time, the io_mapping object must be freed:: --- a/include/linux/io-mapping.h +++ b/include/linux/io-mapping.h @@ -83,6 +83,21 @@ io_mapping_unmap_atomic(void __iomem *va } static inline void __iomem * +io_mapping_map_local_wc(struct io_mapping *mapping, unsigned
[Intel-gfx] [patch V3 33/37] highmem: Remove kmap_atomic_prot()
No more users.
Signed-off-by: Thomas Gleixner
---
V3: New patch
---
include/linux/highmem-internal.h | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
--- a/include/linux/highmem-internal.h
+++ b/include/linux/highmem-internal.h
@@ -87,16 +87,11 @@ static inline void __kunmap_local(void *
kunmap_local_indexed(vaddr);
}
-static inline void *kmap_atomic_prot(struct page *page, pgprot_t prot)
+static inline void *kmap_atomic(struct page *page)
{
preempt_disable();
pagefault_disable();
- return __kmap_local_page_prot(page, prot);
-}
-
-static inline void *kmap_atomic(struct page *page)
-{
- return kmap_atomic_prot(page, kmap_prot);
+ return __kmap_local_page_prot(page, kmap_prot);
}
static inline void __kunmap_atomic(void *addr)
@@ -181,11 +176,6 @@ static inline void *kmap_atomic(struct p
return page_address(page);
}
-static inline void *kmap_atomic_prot(struct page *page, pgprot_t prot)
-{
- return kmap_atomic(page);
-}
-
static inline void __kunmap_atomic(void *addr)
{
#ifdef ARCH_HAS_FLUSH_ON_KUNMAP
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