[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ehl: Implement W/A 22010492432 (rev3)
== Series Details == Series: drm/i915/ehl: Implement W/A 22010492432 (rev3) URL : https://patchwork.freedesktop.org/series/83135/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9260_full -> Patchwork_18848_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18848_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18848_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18848_full: ### IGT changes ### Possible regressions * igt@gem_eio@unwedge-stress: - shard-hsw: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-hsw4/igt@gem_...@unwedge-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-hsw7/igt@gem_...@unwedge-stress.html New tests - New tests have been introduced between CI_DRM_9260_full and Patchwork_18848_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18848_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_whisper@basic-fds-all: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-snb2/igt@gem_exec_whis...@basic-fds-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-snb6/igt@gem_exec_whis...@basic-fds-all.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][5] -> [SKIP][6] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-tglb8/igt@gem_huc_c...@huc-copy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / [i915#716]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-skl4/igt@gen9_exec_pa...@allowed-single.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-skl10/igt@gen9_exec_pa...@allowed-single.html * igt@i915_selftest@live@blt: - shard-snb: [PASS][9] -> [DMESG-FAIL][10] ([i915#1409]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-snb7/igt@i915_selftest@l...@blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-snb2/igt@i915_selftest@l...@blt.html * igt@i915_suspend@forcewake: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#636]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-skl2/igt@i915_susp...@forcewake.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-skl1/igt@i915_susp...@forcewake.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-64x21-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-64x21-sliding.html * igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge: - shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-hsw6/igt@kms_cursor_edge_w...@pipe-b-256x256-right-edge.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-hsw1/igt@kms_cursor_edge_w...@pipe-b-256x256-right-edge.html * igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-snb: [PASS][17] -> [FAIL][18] ([i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-snb6/igt@kms_draw_...@draw-method-xrgb2101010-blt-untiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-snb4/igt@kms_draw_...@draw-method-xrgb2101010-blt-untiled.html * igt@kms_flip@2x-wf_vblank-ts-check@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#118] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-glk4/igt@kms_flip@2x-wf_vblank-ts-ch...@ab-hdmi-a1-hdmi-a2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18848/shard-glk7/igt@kms_flip@2x-wf_vblank-ts-ch...@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@blocking-wf_vblank@a-edp1: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +7 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-skl7/igt@kms_flip@blocking-wf_vbl...@a-edp1.html [2
Re: [Intel-gfx] [PATCH 3/5] drm/amdgpu: Paper over the drm_driver mangling for virt
On Tue, Nov 03, 2020 at 11:49:40AM -0500, Alex Deucher wrote:
> On Sun, Nov 1, 2020 at 5:01 AM Daniel Vetter wrote:
> >
> > On Sat, Oct 31, 2020 at 2:57 PM Daniel Vetter
> > wrote:
> > >
> > > On Fri, Oct 30, 2020 at 7:47 PM Alex Deucher
> > > wrote:
> > > >
> > > > On Fri, Oct 30, 2020 at 6:11 AM Daniel Vetter
> > > > wrote:
> > > > >
> > > > > Prep work to make drm_device->driver const.
> > > > >
> > > > > Signed-off-by: Daniel Vetter
> > > > > Cc: Alex Deucher
> > > > > Cc: "Christian König"
> > > > > Cc: Evan Quan
> > > > > Cc: Felix Kuehling
> > > > > Cc: Hawking Zhang
> > > > > Cc: Andrey Grodzovsky
> > > > > Cc: Luben Tuikov
> > > > > Cc: Thomas Zimmermann
> > > > > Cc: Monk Liu
> > > > > Cc: Yintian Tao
> > > > > Cc: Dennis Li
> > > > > Cc: shaoyunl
> > > > > Cc: Bokun Zhang
> > > > > Cc: "Stanley.Yang"
> > > > > Cc: Wenhui Sheng
> > > > > Cc: chen gong
> > > > > Signed-off-by: Daniel Vetter
> > > > > ---
> > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
> > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 12 +++-
> > > > > 2 files changed, 15 insertions(+), 5 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > > > > index 024c3b70b1aa..3d337f13ae4e 100644
> > > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > > > > @@ -1093,7 +1093,7 @@ static const struct pci_device_id pciidlist[] =
> > > > > {
> > > > >
> > > > > MODULE_DEVICE_TABLE(pci, pciidlist);
> > > > >
> > > > > -static struct drm_driver kms_driver;
> > > > > +struct drm_driver amdgpu_kms_driver;
> > > > >
> > > > > static int amdgpu_pci_probe(struct pci_dev *pdev,
> > > > > const struct pci_device_id *ent)
> > > > > @@ -1164,7 +1164,7 @@ static int amdgpu_pci_probe(struct pci_dev
> > > > > *pdev,
> > > > > if (ret)
> > > > > return ret;
> > > > >
> > > > > - adev = devm_drm_dev_alloc(&pdev->dev, &kms_driver,
> > > > > typeof(*adev), ddev);
> > > > > + adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver,
> > > > > typeof(*adev), ddev);
> > > > > if (IS_ERR(adev))
> > > > > return PTR_ERR(adev);
> > > > >
> > > > > @@ -1508,7 +1508,7 @@ int amdgpu_file_to_fpriv(struct file *filp,
> > > > > struct amdgpu_fpriv **fpriv)
> > > > > return 0;
> > > > > }
> > > > >
> > > > > -static struct drm_driver kms_driver = {
> > > > > +struct drm_driver amdgpu_kms_driver = {
> > > > > .driver_features =
> > > > > DRIVER_ATOMIC |
> > > > > DRIVER_GEM |
> > > > > @@ -1571,7 +1571,7 @@ static int __init amdgpu_init(void)
> > > > > goto error_fence;
> > > > >
> > > > > DRM_INFO("amdgpu kernel modesetting enabled.\n");
> > > > > - kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
> > > > > + amdgpu_kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
> > > > > amdgpu_register_atpx_handler();
> > > > >
> > > > > /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is
> > > > > not set. */
> > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > > index d0aea5e39531..dde4c449c284 100644
> > > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > > > > @@ -45,13 +45,23 @@ bool amdgpu_virt_mmio_blocked(struct
> > > > > amdgpu_device *adev)
> > > > > return RREG32_NO_KIQ(0xc040) == 0x;
> > > > > }
> > > > >
> > > > > +extern struct drm_driver amdgpu_kms_driver;
> > > > > +
> > > > > void amdgpu_virt_init_setting(struct amdgpu_device *adev)
> > > > > {
> > > > > /* enable virtual display */
> > > > > if (adev->mode_info.num_crtc == 0)
> > > > > adev->mode_info.num_crtc = 1;
> > > > > adev->enable_virtual_display = true;
> > > > > - adev_to_drm(adev)->driver->driver_features &= ~DRIVER_ATOMIC;
> > > > > +
> > > > > + /*
> > > > > +* FIXME: Either make virt support atomic or make sure you
> > > > > have two
> > > > > +* drm_driver structs, these kind of tricks are only ok when
> > > > > there's
> > > > > +* guaranteed only a single device per system. This should
> > > > > also be done
> > > > > +* before struct drm_device is initialized.
> > > > > +*/
> > > > > + amdgpu_kms_driver.driver_features &= ~DRIVER_ATOMIC;
> > > >
> > > > There is additional DRIVER_ATOMIC in amdgpu_pci_probe() for older
> > > > chips without atomic support.
> > >
> > > That would need to be fixed for making the amdgpu drm_driver
> > > structures constant, but that's not what I'm doing here. I'm only
> > > removing the usage of the drm_device->driver pointer, to allow that to
> > > become constant. Untangling the flow to make the amdgpu_kms_driver
> > > const looked a
[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable HDR on MCA LSPCON based Gen9 devices (rev10)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev10) URL : https://patchwork.freedesktop.org/series/68081/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9260_full -> Patchwork_18849_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18849_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18849_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18849_full: ### IGT changes ### Possible regressions * igt@gem_exec_whisper@basic-fds-all: - shard-snb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-snb2/igt@gem_exec_whis...@basic-fds-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-snb5/igt@gem_exec_whis...@basic-fds-all.html New tests - New tests have been introduced between CI_DRM_9260_full and Patchwork_18849_full: ### New CI tests (1) ### * boot: - Statuses : 199 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18849_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_params@rs-invalid: - shard-hsw: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-hsw6/igt@gem_exec_par...@rs-invalid.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-hsw6/igt@gem_exec_par...@rs-invalid.html * igt@gem_exec_suspend@basic: - shard-hsw: [PASS][5] -> [FAIL][6] ([i915#1888]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-hsw4/igt@gem_exec_susp...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-hsw4/igt@gem_exec_susp...@basic.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][7] -> [SKIP][8] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-tglb8/igt@gem_huc_c...@huc-copy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_rpm@i2c: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-skl10/igt@i915_pm_...@i2c.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-skl4/igt@i915_pm_...@i2c.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#198]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-skl10/igt@i915_susp...@fence-restore-tiled2untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-skl8/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-random: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-256x85-random.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-256x85-random.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-glk8/igt@kms_cursor_leg...@cursorb-vs-flipb-toggle.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-glk4/igt@kms_cursor_leg...@cursorb-vs-flipb-toggle.html * igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-snb: [PASS][17] -> [FAIL][18] ([i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-snb6/igt@kms_draw_...@draw-method-xrgb2101010-blt-untiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-snb6/igt@kms_draw_...@draw-method-xrgb2101010-blt-untiled.html * igt@kms_flip@blocking-wf_vblank@a-dp1: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-kbl4/igt@kms_flip@blocking-wf_vbl...@a-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18849/shard-kbl6/igt@kms_flip@blocking-wf_vbl...@a-dp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2598]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9260/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html [22]: https://intel-g
Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR
Quoting Lucas De Marchi (2020-10-27 06:46:18)
> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
> Bridge"). Other than printing their values in debugfs we don't do
> anything with them. There's not much useful information in them. These
> registers may change location in future platforms, but instead of adding
> new locations, it's simpler to just remove them.
This code seems to have been updated for Gen9LP, so that would indicate
the debugging information is useful, right? The value is even decoded, not
simply dumped as most registers. So I would be hesitant to drop it for
not being useful.
The second question is why we have a huge block of 1-to-1 duplicated
code in there. Has there been an incorrect merge or some transition has
been left mid-way?
Regards, Joonas
> Cc: Matt Roper
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 17 ++---
> drivers/gpu/drm/i915/i915_debugfs.c | 17 ++---
> drivers/gpu/drm/i915/i915_reg.h | 3 ---
> 3 files changed, 4 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index 174a24553322..8a68088c12ea 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -296,8 +296,6 @@ static int frequency_show(struct seq_file *m, void
> *unused)
> seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
>intel_gpu_freq(rps, rps->efficient_freq));
> } else if (INTEL_GEN(i915) >= 6) {
> - u32 rp_state_limits;
> - u32 gt_perf_status;
> u32 rp_state_cap;
> u32 rpmodectl, rpinclimit, rpdeclimit;
> u32 rpstat, cagf, reqf;
> @@ -307,14 +305,10 @@ static int frequency_show(struct seq_file *m, void
> *unused)
> u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
> int max_freq;
>
> - rp_state_limits = intel_uncore_read(uncore,
> GEN6_RP_STATE_LIMITS);
> - if (IS_GEN9_LP(i915)) {
> + if (IS_GEN9_LP(i915))
> rp_state_cap = intel_uncore_read(uncore,
> BXT_RP_STATE_CAP);
> - gt_perf_status = intel_uncore_read(uncore,
> BXT_GT_PERF_STATUS);
> - } else {
> + else
> rp_state_cap = intel_uncore_read(uncore,
> GEN6_RP_STATE_CAP);
> - gt_perf_status = intel_uncore_read(uncore,
> GEN6_GT_PERF_STATUS);
> - }
>
> /* RPSTAT1 is in the GT power well */
> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> @@ -390,13 +384,6 @@ static int frequency_show(struct seq_file *m, void
> *unused)
>pm_isr, pm_iir);
> seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>rps->pm_intrmsk_mbz);
> - seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> - seq_printf(m, "Render p-state ratio: %d\n",
> - (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00
> : 0xff00)) >> 8);
> - seq_printf(m, "Render p-state VID: %d\n",
> - gt_perf_status & 0xff);
> - seq_printf(m, "Render p-state limit: %d\n",
> - rp_state_limits & 0xff);
> seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
> seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
> seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index ea469168cd44..c01f27eebf9c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -838,8 +838,6 @@ static int i915_frequency_info(struct seq_file *m, void
> *unused)
>"efficient (RPe) frequency: %d MHz\n",
>intel_gpu_freq(rps, rps->efficient_freq));
> } else if (INTEL_GEN(dev_priv) >= 6) {
> - u32 rp_state_limits;
> - u32 gt_perf_status;
> u32 rp_state_cap;
> u32 rpmodectl, rpinclimit, rpdeclimit;
> u32 rpstat, cagf, reqf;
> @@ -848,14 +846,10 @@ static int i915_frequency_info(struct seq_file *m, void
> *unused)
> u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
> int max_freq;
>
> - rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> - if (IS_GEN9_LP(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv))
> rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> - gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> - } else {
> + else
>
Re: [Intel-gfx] [CI 3/3] drm/i915/gt: Move pm debug files into a gt aware debugfs
Quoting Chris Wilson (2019-12-22 16:40:46) > From: Andi Shyti > > The GT system is becoming more and more a stand-alone system in > i915 and it's fair to assign it its own debugfs directory. > > rc6, rps and llc debugfs files are gt related, move them into the > gt debugfs directory. > > Signed-off-by: Andi Shyti > Reviewed-by: Chris Wilson > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/Makefile | 3 + > drivers/gpu/drm/i915/gt/debugfs_engines.c | 36 ++ > drivers/gpu/drm/i915/gt/debugfs_engines.h | 15 + > drivers/gpu/drm/i915/gt/debugfs_gt.c | 42 ++ > drivers/gpu/drm/i915/gt/debugfs_gt.h | 39 ++ > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 601 ++ > drivers/gpu/drm/i915/gt/debugfs_gt_pm.h | 14 + > drivers/gpu/drm/i915/gt/intel_gt.c| 3 + > 8 files changed, 753 insertions(+) > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_engines.c > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_engines.h > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.c > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.h > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_pm.h This patch seems to actually copy the code, forgetting to remove the old code. Let's have a follow-up patch that eliminates the duplication. Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 3/3] drm/i915/gt: Move pm debug files into a gt aware debugfs
Quoting Joonas Lahtinen (2020-11-04 10:05:32) > Quoting Chris Wilson (2019-12-22 16:40:46) > > From: Andi Shyti > > > > The GT system is becoming more and more a stand-alone system in > > i915 and it's fair to assign it its own debugfs directory. > > > > rc6, rps and llc debugfs files are gt related, move them into the > > gt debugfs directory. > > > > Signed-off-by: Andi Shyti > > Reviewed-by: Chris Wilson > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/Makefile | 3 + > > drivers/gpu/drm/i915/gt/debugfs_engines.c | 36 ++ > > drivers/gpu/drm/i915/gt/debugfs_engines.h | 15 + > > drivers/gpu/drm/i915/gt/debugfs_gt.c | 42 ++ > > drivers/gpu/drm/i915/gt/debugfs_gt.h | 39 ++ > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 601 ++ > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.h | 14 + > > drivers/gpu/drm/i915/gt/intel_gt.c| 3 + > > 8 files changed, 753 insertions(+) > > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_engines.c > > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_engines.h > > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.c > > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.h > > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c > > create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_pm.h > > This patch seems to actually copy the code, forgetting to remove the old > code. Let's have a follow-up patch that eliminates the duplication. We couldn't remove the old code without making changes to igt to work out what the appropriate GT directory would be for the test. That is still unknowable from userspace... So as a matter of convenience we kept the old entry point so that we could dump everything under the device. More work could be done to remove the duplication of debug code, but equally we could use more specialised debug info for the igts. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/18] drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA
+ Rodrigo,
Quoting Aditya Swarup (2020-10-21 16:32:08)
> From: Anusha Srivatsa
>
> - Inherit the gen12 workarounds.
> - Add placeholders to setup GT WA.
> - Extend permanent driver WA Wa_1409767108 to adl-s and
> Wa_14010685332 to adl-s.
> - Extend permanent driver WA Wa_1606054188 to adl-s
> - Add Wa_14011765242 for adl-s A0 stepping.
Rodrigo, Jani, any thoughts on if this patch should be split
between display and GT? In my thinking we should have a small
topic branch that introduces the base platform support, which
is merged to both trees. Then the respective patches split and
merged to -next and -gt-next. That way we would avoid the
conflicts that came from the Jasperlake patches.
Although, I'm not sure if our code splitting is yet as far that
we could enable the display with separate set of patches. I guess
it would be worthy testing if that can happen.
Regards, Joonas
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: Anusha Srivatsa
> Signed-off-by: Aditya Swarup
> ---
> .../drm/i915/display/intel_display_power.c| 7 +++--
> drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 29 +--
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 6 +++-
> 5 files changed, 37 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 689922480661..acc63ab2bc78 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5288,9 +5288,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private
> *dev_priv)
> unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
> int config, i;
>
> - if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> + if (IS_ALDERLAKE_S(dev_priv) ||
> + IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> - /* Wa_1409767108:tgl,dg1 */
> + /* Wa_1409767108:tgl,dg1,adl-s */
> table = wa_1409767108_buddy_page_masks;
> else
> table = tgl_buddy_page_masks;
> @@ -5328,7 +5329,7 @@ static void icl_display_core_init(struct
> drm_i915_private *dev_priv,
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> - /* Wa_14011294188:ehl,jsl,tgl,rkl */
> + /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
> INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
> intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 88bfebdf9228..d4b5fc9e2704 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2226,7 +2226,7 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
> }
>
> /* Wa_1606054188:tgl */
> - if (IS_TIGERLAKE(dev_priv) &&
> + if ((IS_TIGERLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) &&
> plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
> intel_format_is_p01x(fb->format->format)) {
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index fed9503a7c4e..8136d13462b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -686,6 +686,12 @@ static void dg1_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
> }
>
> +static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
> + struct i915_wa_list *wal)
> +{
> + gen12_ctx_workarounds_init(engine, wal);
> +}
> +
> static void
> __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>struct i915_wa_list *wal,
> @@ -698,7 +704,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>
> wa_init_start(wal, name, engine->name);
>
> - if (IS_DG1(i915))
> + if (IS_ALDERLAKE_S(i915))
> + adls_ctx_workarounds_init(engine, wal);
> + else if (IS_DG1(i915))
> dg1_ctx_workarounds_init(engine, wal);
> else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
> tgl_ctx_workarounds_init(engine, wal);
> @@ -1284,10 +1292,18 @@ dg1_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> VSUNIT_CLKGATE_DIS_TGL);
> }
>
> +static void
> +adls_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal)
> +{
> +
[Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state
From: Tvrtko Ursulin
Between events which trigger engine and GPU resets and capturing the error
state we lose information on which engine triggered the reset. Improve
this by passing in the hung engine mask down to error capture.
Result is that the list of engines in user visible "GPU HANG: ecode
::, " is now a list of hanging and not just
active engines. Most importantly the displayed process is now the one
which was actually hung.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 35 ++-
drivers/gpu/drm/i915/i915_gpu_error.h | 7 --
5 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f3eb68a76a25..8a51c1c3a091 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3037,6 +3037,8 @@ static struct execlists_capture *capture_regs(struct
intel_engine_cs *engine)
if (!cap->error->gt->engine)
goto err_gt;
+ cap->error->gt->engine->hung = true;
+
return cap;
err_gt:
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 4e5e13dc95da..9fb4306b2900 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1251,7 +1251,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
engine_mask &= gt->info.engine_mask;
if (flags & I915_ERROR_CAPTURE) {
- i915_capture_error_state(gt->i915);
+ i915_capture_error_state(gt, engine_mask);
intel_gt_clear_error_registers(gt, engine_mask);
}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 200f6b86f864..77e76b665098 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -725,7 +725,7 @@ static int i915_gpu_info_open(struct inode *inode, struct
file *file)
gpu = NULL;
with_intel_runtime_pm(&i915->runtime_pm, wakeref)
- gpu = i915_gpu_coredump(i915);
+ gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES);
if (IS_ERR(gpu))
return PTR_ERR(gpu);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b3f3a2e07408..857db66cc4a3 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -570,6 +570,7 @@ static void error_print_engine(struct
drm_i915_error_state_buf *m,
ee->vm_info.pp_dir_base);
}
}
+ err_printf(m, " hung: %u\n", ee->hung);
err_printf(m, " engine reset count: %u\n", ee->reset_count);
for (n = 0; n < ee->num_ports; n++) {
@@ -1456,6 +1457,7 @@ capture_engine(struct intel_engine_cs *engine,
static void
gt_record_engines(struct intel_gt_coredump *gt,
+ intel_engine_mask_t engine_mask,
struct i915_vma_compress *compress)
{
struct intel_engine_cs *engine;
@@ -1471,6 +1473,8 @@ gt_record_engines(struct intel_gt_coredump *gt,
if (!ee)
continue;
+ ee->hung = engine->mask & engine_mask;
+
gt->simulated |= ee->simulated;
if (ee->simulated) {
kfree(ee);
@@ -1663,11 +1667,13 @@ static const char *error_msg(struct i915_gpu_coredump
*error)
for (gt = error->gt; gt; gt = gt->next) {
struct intel_engine_coredump *cs;
- if (gt->engine && !first)
- first = gt->engine;
-
- for (cs = gt->engine; cs; cs = cs->next)
- engines |= cs->engine->mask;
+ for (cs = gt->engine; cs; cs = cs->next) {
+ if (cs->hung) {
+ engines |= cs->engine->mask;
+ if (!first)
+ first = cs;
+ }
+ }
}
len = scnprintf(error->error_msg, sizeof(error->error_msg),
@@ -1781,8 +1787,10 @@ void i915_vma_capture_finish(struct intel_gt_coredump
*gt,
kfree(compress);
}
-struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
+struct i915_gpu_coredump *
+i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask)
{
+ struct drm_i915_private *i915 = gt->i915;
struct i915_gpu_coredump *error;
/* Check if GPU capture has been disabled */
@@ -1794,7 +1802,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct
drm_i915_private *i915)
if (!error)
return ERR_PTR(-ENOMEM);
- error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL);
+ error->gt = intel_gt_core
[Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode
From: Tvrtko Ursulin
Instead of printing out the internal engine mask, which can change between
kernel versions making it difficult to map to actual engines, list user
friendly engine names in the ecode string. For example:
[drm] GPU HANG: ecode 9:vcs1:a77ffefe, in gem_exec_captur [929]
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 38 ---
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
2 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 857db66cc4a3..ce876e3f3ec5 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1659,32 +1659,40 @@ static u32 generate_ecode(const struct
intel_engine_coredump *ee)
static const char *error_msg(struct i915_gpu_coredump *error)
{
struct intel_engine_coredump *first = NULL;
+ int space = sizeof(error->error_msg) - 1, len;
struct intel_gt_coredump *gt;
- intel_engine_mask_t engines;
- int len;
+ char *p = error->error_msg;
+
+ len = scnprintf(p, space, "GPU HANG: ecode %d:",
+ INTEL_GEN(error->i915));
+ p += len;
+ space -= len;
- engines = 0;
for (gt = error->gt; gt; gt = gt->next) {
struct intel_engine_coredump *cs;
for (cs = gt->engine; cs; cs = cs->next) {
- if (cs->hung) {
- engines |= cs->engine->mask;
- if (!first)
- first = cs;
- }
+ if (!cs->hung)
+ continue;
+
+ len = scnprintf(p, space, "%s%s",
+ first ? "," : "",
+ cs->engine->name);
+ p += len;
+ space -= len;
+
+ if (!first)
+ first = cs;
}
}
- len = scnprintf(error->error_msg, sizeof(error->error_msg),
- "GPU HANG: ecode %d:%x:%08x",
- INTEL_GEN(error->i915), engines,
- generate_ecode(first));
+ len = scnprintf(p, space, ":%08x", generate_ecode(first));
+ p += len;
+ space -= len;
+
if (first && first->context.pid) {
/* Just show the first executing process, more is confusing */
- len += scnprintf(error->error_msg + len,
-sizeof(error->error_msg) - len,
-", in %s [%d]",
+ len += scnprintf(p, space, ", in %s [%d]",
first->context.comm, first->context.pid);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
b/drivers/gpu/drm/i915/i915_gpu_error.h
index 3a7ca90a3436..6b8573ddbe67 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -168,7 +168,7 @@ struct i915_gpu_coredump {
struct intel_gt_coredump *gt;
- char error_msg[128];
+ char error_msg[256];
bool simulated;
bool wakelock;
bool suspended;
--
2.25.1
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Re: [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state
Quoting Tvrtko Ursulin (2020-11-04 12:20:42)
> From: Tvrtko Ursulin
>
> Between events which trigger engine and GPU resets and capturing the error
> state we lose information on which engine triggered the reset. Improve
> this by passing in the hung engine mask down to error capture.
>
> Result is that the list of engines in user visible "GPU HANG: ecode
> ::, " is now a list of hanging and not just
> active engines. Most importantly the displayed process is now the one
> which was actually hung.
You could also suggest to only include the hanging engine in the report,
as is intended to be the normal means of generating the report
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
> b/drivers/gpu/drm/i915/i915_gpu_error.h
> index 0220b0992808..3a7ca90a3436 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.h
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h
> @@ -59,6 +59,7 @@ struct i915_request_coredump {
> struct intel_engine_coredump {
> const struct intel_engine_cs *engine;
>
> + bool hung;
> bool simulated;
> u32 reset_count;
>
> @@ -218,8 +219,10 @@ struct drm_i915_error_state_buf {
> __printf(2, 3)
> void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f,
> ...);
>
> -struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915);
> -void i915_capture_error_state(struct drm_i915_private *i915);
> +struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
> + intel_engine_mask_t engine_mask);
> +void i915_capture_error_state(struct intel_gt *gt,
> + intel_engine_mask_t engine_mask);
Don't forget the stubs.
-Chris
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Re: [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode
Quoting Tvrtko Ursulin (2020-11-04 12:20:43) > From: Tvrtko Ursulin > > Instead of printing out the internal engine mask, which can change between > kernel versions making it difficult to map to actual engines, list user > friendly engine names in the ecode string. For example: Nah. It's a nonsense number, just exists for quick and futile discrimination. Trying to interpret it is pointless. There's very little value to be gained from it, it should just serve as a tale-tell that we have captured an error state. The action and impact of the reset should be separately recorded. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/2] drm/i915/display: Support PSR Multiple Transcoders
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR.
v2: Fix indentation and add comments
v3: Remove Blank line
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
.../drm/i915/display/intel_display_debugfs.c | 111 +++-
.../drm/i915/display/intel_display_types.h| 39 ++
drivers/gpu/drm/i915/display/intel_dp.c | 21 +-
drivers/gpu/drm/i915/display/intel_psr.c | 621 +-
drivers/gpu/drm/i915/display/intel_psr.h | 16 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 39 --
drivers/gpu/drm/i915/i915_irq.c | 47 +-
10 files changed, 507 insertions(+), 404 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 19b16517a502..983781ce3683 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4127,7 +4127,10 @@ static void intel_ddi_update_pipe_dp(struct
intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
+ //TODO: move PSR related functions into intel_psr_update()
+ intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
intel_psr_update(intel_dp, crtc_state, conn_state);
+
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_update(intel_dp, crtc_state);
@@ -5275,6 +5278,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
goto err;
dig_port->hpd_pulse = intel_dp_hpd_pulse;
+
+ intel_psr_init(&dig_port->dp);
}
/* In theory we don't need the encoder->type check, but leave it just in
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cddbda5303ff..be5238e5d587 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15506,8 +15506,6 @@ static void commit_pipe_config(struct
intel_atomic_state *state,
if (new_crtc_state->update_pipe)
intel_pipe_fastset(old_crtc_state, new_crtc_state);
-
- intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
if (dev_priv->display.atomic_update_watermarks)
@@ -17435,8 +17433,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_dvo_init(dev_priv);
}
- intel_psr_init(dev_priv);
-
for_each_intel_encoder(&dev_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
@@ -18373,7 +18369,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
intel_init_ipc(i915);
- intel_psr_set_force_mode_changed(i915->psr.dp);
+ intel_psr_set_force_mode_changed(i915);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cfb4c1474982..8402e6ac9f76 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -248,18 +248,17 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
"sink internal error",
};
struct drm_connector *connector = m->private;
- struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
int ret;
- if (!CAN_PSR(dev_priv)) {
- seq_puts(m, "PSR Unsupported\n");
+ if (connector->status != connector_status_connected)
return -ENODEV;
- }
- if (connector->status != connector_status_connected)
+ if (!CAN_PSR(intel_dp)) {
+ seq_puts(m, "PSR Unsupported\n");
return -ENODEV;
+ }
ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
@@ -279,12 +278,13 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static void
-psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
+psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
{
u32 val, status_val;
const char *status = "unknown";
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if
[Intel-gfx] [PATCH v3 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
---
.../drm/i915/display/intel_display_debugfs.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 8402e6ac9f76..37805615a221 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2093,6 +2093,23 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (connector->status != connector_status_connected)
+ return -ENODEV;
+
+ if (!HAS_PSR(dev_priv))
+ return -ENODEV;
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
@@ -2268,6 +2285,12 @@ int intel_connector_debugfs_add(struct drm_connector
*connector)
connector, &i915_psr_sink_status_fops);
}
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ debugfs_create_file("i915_psr_status", 0444, root,
+ connector, &i915_psr_status_fops);
+ }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state
On 04/11/2020 12:30, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-11-04 12:20:42)
From: Tvrtko Ursulin
Between events which trigger engine and GPU resets and capturing the error
state we lose information on which engine triggered the reset. Improve
this by passing in the hung engine mask down to error capture.
Result is that the list of engines in user visible "GPU HANG: ecode
::, " is now a list of hanging and not just
active engines. Most importantly the displayed process is now the one
which was actually hung.
You could also suggest to only include the hanging engine in the report,
as is intended to be the normal means of generating the report
I thought it is potentially useful to have a full picture, but can do
that as well.
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
b/drivers/gpu/drm/i915/i915_gpu_error.h
index 0220b0992808..3a7ca90a3436 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -59,6 +59,7 @@ struct i915_request_coredump {
struct intel_engine_coredump {
const struct intel_engine_cs *engine;
+ bool hung;
bool simulated;
u32 reset_count;
@@ -218,8 +219,10 @@ struct drm_i915_error_state_buf {
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f,
...);
-struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915);
-void i915_capture_error_state(struct drm_i915_private *i915);
+struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask);
+void i915_capture_error_state(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask);
Don't forget the stubs.
Right, thanks.
Regards,
Tvrtko
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode
On 04/11/2020 12:33, Chris Wilson wrote: Quoting Tvrtko Ursulin (2020-11-04 12:20:43) From: Tvrtko Ursulin Instead of printing out the internal engine mask, which can change between kernel versions making it difficult to map to actual engines, list user friendly engine names in the ecode string. For example: Nah. It's a nonsense number, just exists for quick and futile discrimination. Trying to interpret it is pointless. There's very little value to be gained from it, it should just serve as a tale-tell that we have captured an error state. The action and impact of the reset should be separately recorded. My problem with the nonsense number is that we have it, but that is is unstable and people are interpreting it. How about a bitmask of uabi classes instead? As you can see I really want something from the ABI-land, or not at all. Classes might be just the thing for the purpose of a signature. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines
in error state
URL : https://patchwork.freedesktop.org/series/83493/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9263 -> Patchwork_18850
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/index.html
New tests
-
New tests have been introduced between CI_DRM_9263 and Patchwork_18850:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18850 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-byt-j1900/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-byt-j1900/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#541])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar
issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#165]) +15
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-byt-j1900/igt@i915_pm_...@module-reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-byt-j1900/igt@i915_pm_...@module-reload.html
- fi-apl-guc: [DMESG-WARN][17] ([i915#1635] / [i915#1982]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-apl-guc/igt@i915_pm_...@module-reload.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-apl-guc/igt@i915_pm_...@module-reload.html
* igt@kms_flip@basic-flip-vs-modeset@d-dsi1:
- {fi-tgl-dsi}: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] +1
similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-mode...@d-dsi1.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-mode...@d-dsi1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (45 -> 40)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build chang
Re: [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode
Quoting Tvrtko Ursulin (2020-11-04 13:06:43) > > On 04/11/2020 12:33, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-11-04 12:20:43) > >> From: Tvrtko Ursulin > >> > >> Instead of printing out the internal engine mask, which can change between > >> kernel versions making it difficult to map to actual engines, list user > >> friendly engine names in the ecode string. For example: > > > > Nah. It's a nonsense number, just exists for quick and futile > > discrimination. > > Trying to interpret it is pointless. > > > > There's very little value to be gained from it, it should just serve as a > > tale-tell that we have captured an error state. The action and impact of > > the reset should be separately recorded. > > My problem with the nonsense number is that we have it, but that is is > unstable and people are interpreting it. > > How about a bitmask of uabi classes instead? As you can see I really > want something from the ABI-land, or not at all. Classes might be just > the thing for the purpose of a signature. You can probably tell I've been pushing for the not-at-all :) I've personally not found it helpful, it's too simplistic and unstable even for repeated GL hangs. The concept of having a hash that can summarise the hang is definitely a good idea, but the input to that hash is flawed. Given that we record the reset action, and the context that was impacted, I wonder how much we need to say here. Just announce a new error state has been captured? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v3,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/83495/ State : warning == Summary == $ dim checkpatch origin/drm-tip 215ae488cdd7 drm/i915/display: Support PSR Multiple Transcoders -:1764: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects? #1764: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21: +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support) total: 0 errors, 0 warnings, 1 checks, 1803 lines checked f422291bce21 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v3,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/83495/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinl
[Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state
From: Tvrtko Ursulin
Between events which trigger engine and GPU resets and capturing the error
state we lose information on which engine triggered the reset. Improve
this by passing in the hung engine mask down to error capture.
Result is that the list of engines in user visible "GPU HANG: ecode
::, " is now a list of hanging and not just
active engines. Most importantly the displayed process is now the one
which was actually hung.
v2:
* Stub prototype. (Chris)
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 35 ++-
drivers/gpu/drm/i915/i915_gpu_error.h | 10 +---
5 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f3eb68a76a25..8a51c1c3a091 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3037,6 +3037,8 @@ static struct execlists_capture *capture_regs(struct
intel_engine_cs *engine)
if (!cap->error->gt->engine)
goto err_gt;
+ cap->error->gt->engine->hung = true;
+
return cap;
err_gt:
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 4e5e13dc95da..9fb4306b2900 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1251,7 +1251,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
engine_mask &= gt->info.engine_mask;
if (flags & I915_ERROR_CAPTURE) {
- i915_capture_error_state(gt->i915);
+ i915_capture_error_state(gt, engine_mask);
intel_gt_clear_error_registers(gt, engine_mask);
}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 200f6b86f864..77e76b665098 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -725,7 +725,7 @@ static int i915_gpu_info_open(struct inode *inode, struct
file *file)
gpu = NULL;
with_intel_runtime_pm(&i915->runtime_pm, wakeref)
- gpu = i915_gpu_coredump(i915);
+ gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES);
if (IS_ERR(gpu))
return PTR_ERR(gpu);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b3f3a2e07408..857db66cc4a3 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -570,6 +570,7 @@ static void error_print_engine(struct
drm_i915_error_state_buf *m,
ee->vm_info.pp_dir_base);
}
}
+ err_printf(m, " hung: %u\n", ee->hung);
err_printf(m, " engine reset count: %u\n", ee->reset_count);
for (n = 0; n < ee->num_ports; n++) {
@@ -1456,6 +1457,7 @@ capture_engine(struct intel_engine_cs *engine,
static void
gt_record_engines(struct intel_gt_coredump *gt,
+ intel_engine_mask_t engine_mask,
struct i915_vma_compress *compress)
{
struct intel_engine_cs *engine;
@@ -1471,6 +1473,8 @@ gt_record_engines(struct intel_gt_coredump *gt,
if (!ee)
continue;
+ ee->hung = engine->mask & engine_mask;
+
gt->simulated |= ee->simulated;
if (ee->simulated) {
kfree(ee);
@@ -1663,11 +1667,13 @@ static const char *error_msg(struct i915_gpu_coredump
*error)
for (gt = error->gt; gt; gt = gt->next) {
struct intel_engine_coredump *cs;
- if (gt->engine && !first)
- first = gt->engine;
-
- for (cs = gt->engine; cs; cs = cs->next)
- engines |= cs->engine->mask;
+ for (cs = gt->engine; cs; cs = cs->next) {
+ if (cs->hung) {
+ engines |= cs->engine->mask;
+ if (!first)
+ first = cs;
+ }
+ }
}
len = scnprintf(error->error_msg, sizeof(error->error_msg),
@@ -1781,8 +1787,10 @@ void i915_vma_capture_finish(struct intel_gt_coredump
*gt,
kfree(compress);
}
-struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
+struct i915_gpu_coredump *
+i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask)
{
+ struct drm_i915_private *i915 = gt->i915;
struct i915_gpu_coredump *error;
/* Check if GPU capture has been disabled */
@@ -1794,7 +1802,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct
drm_i915_private *i915)
if (!error)
return ERR_PTR(-ENOMEM);
- error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL);
[Intel-gfx] [RFC 2/2] drm/i915: Use ABI engine class in error state ecode
From: Tvrtko Ursulin
Instead of printing out the internal engine mask, which can change between
kernel versions making it difficult to map to actual engines, present a
bitmask of hanging engines ABI classes. For example:
[drm] GPU HANG: ecode 9:24dd:8, in gem_exec_schedu [1334]
Notice the swapped the order of ecode and bitmask which makes the new
versus old bug reports are obvious.
Engine ABI class is useful to quickly categorize render vs media etc hangs
in bug reports. Considering virtual engine even more so than the current
scheme.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 857db66cc4a3..e7d9af184d58 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1659,17 +1659,16 @@ static u32 generate_ecode(const struct
intel_engine_coredump *ee)
static const char *error_msg(struct i915_gpu_coredump *error)
{
struct intel_engine_coredump *first = NULL;
+ unsigned int hung_classes = 0;
struct intel_gt_coredump *gt;
- intel_engine_mask_t engines;
int len;
- engines = 0;
for (gt = error->gt; gt; gt = gt->next) {
struct intel_engine_coredump *cs;
for (cs = gt->engine; cs; cs = cs->next) {
if (cs->hung) {
- engines |= cs->engine->mask;
+ hung_classes |= BIT(cs->engine->uabi_class);
if (!first)
first = cs;
}
@@ -1677,9 +1676,11 @@ static const char *error_msg(struct i915_gpu_coredump
*error)
}
len = scnprintf(error->error_msg, sizeof(error->error_msg),
- "GPU HANG: ecode %d:%x:%08x",
- INTEL_GEN(error->i915), engines,
- generate_ecode(first));
+ "GPU HANG: ecode %d:%08x:%x",
+ INTEL_GEN(error->i915),
+ generate_ecode(first),
+ hung_classes);
+
if (first && first->context.pid) {
/* Just show the first executing process, more is confusing */
len += scnprintf(error->error_msg + len,
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gvt: replace idr_init() by idr_init_base()
idr_init() uses base 0 which is an invalid identifier. The new function
idr_init_base allows IDR to set the ID lookup from base 1. This avoids
all lookups that otherwise starts from 0 since 0 is always unused.
References: commit 6ce711f27500 ("idr: Make 1-based IDRs more efficient")
Signed-off-by: Deepak R Varma
---
drivers/gpu/drm/i915/gvt/gvt.c | 2 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index c7c561237883..45b492edbb19 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -312,7 +312,7 @@ int intel_gvt_init_device(struct drm_i915_private *i915)
gvt_dbg_core("init gvt device\n");
- idr_init(&gvt->vgpu_idr);
+ idr_init_base(&gvt->vgpu_idr, 1);
spin_lock_init(&gvt->scheduler.mmio_context_lock);
mutex_init(&gvt->lock);
mutex_init(&gvt->sched_lock);
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index f6d7e33c7099..1c8e63f84134 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -393,7 +393,7 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct
intel_gvt *gvt,
mutex_init(&vgpu->dmabuf_lock);
INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
- idr_init(&vgpu->object_idr);
+ idr_init_base(&vgpu->object_idr, 1);
intel_vgpu_init_cfg_space(vgpu, param->primary);
vgpu->d3_entered = false;
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83495/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9263 -> Patchwork_18851
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/index.html
New tests
-
New tests have been introduced between CI_DRM_9263 and Patchwork_18851:
### New CI tests (1) ###
* boot:
- Statuses : 1 fail(s) 35 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18851 that come from known issues:
### CI changes ###
Issues hit
* boot (NEW):
- {fi-tgl-dsi}: [PASS][1] -> [FAIL][2] ([i915#2448])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-dsi/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/fi-tgl-dsi/boot.html
### IGT changes ###
Issues hit
* igt@i915_hangman@error-state-basic:
- fi-gdg-551: [PASS][3] -> [INCOMPLETE][4] ([i915#172])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-gdg-551/igt@i915_hang...@error-state-basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/fi-gdg-551/igt@i915_hang...@error-state-basic.html
* igt@i915_module_load@reload:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/fi-icl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-ehl-1}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-apl-guc: [DMESG-WARN][15] ([i915#1635] / [i915#1982]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-apl-guc/igt@i915_pm_...@module-reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/fi-apl-guc/igt@i915_pm_...@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#172]: https://gitlab.freedesktop.org/drm/intel/issues/172
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2448]: https://gitlab.freedesktop.org/drm/intel/issues/2448
Participating hosts (45 -> 36)
--
Missing(9): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-glk-dsi fi-bsw-cyan
fi-bwr-2160 fi-snb-2520m fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9263 -> Patchwork_18851
CI-20190529: 20190529
CI_DRM_9263: d024f57bbf34cd9dedaff4d026a7ed8f58325bad @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5832: 9c583f7e2a6638b5ff6a3682fea548a1313512e7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18851: f422291bce21ca09a3981d89940896b5e2f9af28 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f422291bce21 drm/i915/display: Support Multiple Transcoders'
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state
== Series Details == Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state URL : https://patchwork.freedesktop.org/series/83497/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux
Re: [Intel-gfx] [PATCH 13/18] drm/i915/adl_s: Add display, gt, ctx and ADL-S whitelist WA
On Wed, Nov 04, 2020 at 12:38:00PM +0200, Joonas Lahtinen wrote:
> + Rodrigo,
>
> Quoting Aditya Swarup (2020-10-21 16:32:08)
> > From: Anusha Srivatsa
> >
> > - Inherit the gen12 workarounds.
> > - Add placeholders to setup GT WA.
> > - Extend permanent driver WA Wa_1409767108 to adl-s and
> > Wa_14010685332 to adl-s.
> > - Extend permanent driver WA Wa_1606054188 to adl-s
> > - Add Wa_14011765242 for adl-s A0 stepping.
>
> Rodrigo, Jani, any thoughts on if this patch should be split
> between display and GT?
I believe for this patch specifically it should be easy to break
the gt/ part of it as a preparation for the workarounds...
> In my thinking we should have a small
> topic branch that introduces the base platform support, which
> is merged to both trees. Then the respective patches split and
> merged to -next and -gt-next. That way we would avoid the
> conflicts that came from the Jasperlake patches.
With only this patch in mind I believe a topic branch is to heavy
of a process and that small conflicts should be okay to handle.
However I like the idea of the topic branch for the big chunk of
platform enabling patches.
>
> Although, I'm not sure if our code splitting is yet as far that
> we could enable the display with separate set of patches. I guess
> it would be worthy testing if that can happen.
I agree.
>
> Regards, Joonas
>
> > Cc: Jani Nikula
> > Cc: Ville Syrjälä
> > Cc: Imre Deak
> > Cc: Matt Roper
> > Cc: Lucas De Marchi
> > Cc: Anusha Srivatsa
> > Signed-off-by: Aditya Swarup
> > ---
> > .../drm/i915/display/intel_display_power.c| 7 +++--
> > drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 29 +--
> > drivers/gpu/drm/i915/i915_irq.c | 2 +-
> > drivers/gpu/drm/i915/intel_device_info.c | 6 +++-
> > 5 files changed, 37 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 689922480661..acc63ab2bc78 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -5288,9 +5288,10 @@ static void tgl_bw_buddy_init(struct
> > drm_i915_private *dev_priv)
> > unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
> > int config, i;
> >
> > - if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> > + if (IS_ALDERLAKE_S(dev_priv) ||
> > + IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> > IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> > - /* Wa_1409767108:tgl,dg1 */
> > + /* Wa_1409767108:tgl,dg1,adl-s */
> > table = wa_1409767108_buddy_page_masks;
> > else
> > table = tgl_buddy_page_masks;
> > @@ -5328,7 +5329,7 @@ static void icl_display_core_init(struct
> > drm_i915_private *dev_priv,
> >
> > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >
> > - /* Wa_14011294188:ehl,jsl,tgl,rkl */
> > + /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
> > INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
> > intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 88bfebdf9228..d4b5fc9e2704 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -2226,7 +2226,7 @@ static int skl_plane_check_fb(const struct
> > intel_crtc_state *crtc_state,
> > }
> >
> > /* Wa_1606054188:tgl */
> > - if (IS_TIGERLAKE(dev_priv) &&
> > + if ((IS_TIGERLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv)) &&
> > plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
> > intel_format_is_p01x(fb->format->format)) {
> > drm_dbg_kms(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index fed9503a7c4e..8136d13462b5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -686,6 +686,12 @@ static void dg1_ctx_workarounds_init(struct
> > intel_engine_cs *engine,
> > DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
> > }
> >
> > +static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
> > + struct i915_wa_list *wal)
> > +{
> > + gen12_ctx_workarounds_init(engine, wal);
> > +}
> > +
> > static void
> > __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> >struct i915_wa_list *wal,
> > @@ -698,7 +704,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs
> > *engine,
> >
> > wa_init_start(wal
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915/display: Support PSR Multiple Transcoders
On Wed, 2020-11-04 at 13:24 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v3,1/2] drm/i915/display: Support PSR > Multiple Transcoders > URL : https://patchwork.freedesktop.org/series/83495/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > 215ae488cdd7 drm/i915/display: Support PSR Multiple Transcoders > -:1764: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - > possible side-effects? > #1764: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21: > +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && > intel_dp->psr.sink_support) > HAS_PSR() Macro does not change internal data of intel_dp, therefore there are no possible side-effects. > total: 0 errors, 0 warnings, 1 checks, 1803 lines checked > f422291bce21 drm/i915/display: Support Multiple Transcoders' PSR > status on debugfs > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915/display: Support PSR Multiple Transcoders
On Wed, 2020-11-04 at 13:26 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v3,1/2] drm/i915/display: Support PSR > Multiple Transcoders > URL : https://patchwork.freedesktop.org/series/83495/ > State : warning > > == Summary == > > $ dim sparse --fast origin/drm-tip > Sparse version: v0.6.2 > Fast mode used, each commit won't be checked separately. > - > +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context > imbalance in 'intel_gt_reset_trylock' - different lock contexts for > basic block > +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void > *in > +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void > [noderef] __iomem *[assigned] s > +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect > type in assignment (different address spaces) > +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void > const *src > +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void > [noderef] __iomem *[assigned] s > +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect > type in argument 2 (different address spaces) > +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void > *in > +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void > [noderef] __iomem *[assigned] s > +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect > type in assignment (different address spaces) > +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void > const *src > +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void > [noderef] __iomem *[assigned] s > +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect > type in argument 2 (different address spaces) > +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned > int [usertype] *s > +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void > [noderef] __iomem *[assigned] s > +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect > type in argument 1 (different address spaces) > +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte > count of 279040 > +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte > count of 16777216 > +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte > count of 16777216 > +./include/linux/seqlock.h:838:24: warning: trying to copy expression > type 31 > +./include/linux/seqlock.h:838:24: warning: trying to copy expression > type 31 > +./include/linux/seqlock.h:864:16: warning: trying to copy expression > type 31 > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'fwtable_read16' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'fwtable_read32' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'fwtable_read64' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'fwtable_read8' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'fwtable_write16' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'fwtable_write32' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'fwtable_write8' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen11_fwtable_read16' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen11_fwtable_read32' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen11_fwtable_read64' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen11_fwtable_read8' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen11_fwtable_write16' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen11_fwtable_write32' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen11_fwtable_write8' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen12_fwtable_read16' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen12_fwtable_read32' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen12_fwtable_read64' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen12_fwtable_read8' - different lock contexts for basic block > +./include/linux/spinlock.h:409:9: warning: context imbalance in > 'gen12_fwta
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines
in error state
URL : https://patchwork.freedesktop.org/series/83497/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9263 -> Patchwork_18852
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/index.html
New tests
-
New tests have been introduced between CI_DRM_9263 and Patchwork_18852:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18852 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
* igt@i915_module_load@reload:
- fi-bxt-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] /
[i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-bxt-dsi/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-bxt-dsi/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
- fi-bsw-n3050: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
- fi-bsw-kefka: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
- fi-icl-u2: [PASS][13] -> [FAIL][14] ([i915#1161] / [i915#262])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-ehl-1}: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-apl-guc: [DMESG-WARN][23] ([i915#1635] / [i915#1982]) ->
[PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-apl-guc/igt@i915_pm_...@module-reload.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/fi-apl-guc/igt@i915_pm_...@module-reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-soraka: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix typo during output setup
On Wed, Nov 04, 2020 at 05:54:25AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/tgl: Fix typo during output setup > URL : https://patchwork.freedesktop.org/series/83465/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_9258_full -> Patchwork_18847_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_18847_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_18847_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_18847_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_flip@2x-flip-vs-absolute-wf_vblank@bc-vga1-hdmi-a1: > - shard-hsw: NOTRUN -> [INCOMPLETE][1] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-hsw4/igt@kms_flip@2x-flip-vs-absolute-wf_vbl...@bc-vga1-hdmi-a1.html Unrelated platform. Pused to -dinq thanks for the review. > > > New tests > - > > New tests have been introduced between CI_DRM_9258_full and > Patchwork_18847_full: > > ### New CI tests (1) ### > > * boot: > - Statuses : 200 pass(s) > - Exec time: [0.0] s > > > > Known issues > > > Here are the changes found in Patchwork_18847_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_caching@writes: > - shard-skl: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) +13 > similar issues >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-skl8/igt@gem_cach...@writes.html >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-skl1/igt@gem_cach...@writes.html > > * igt@i915_module_load@reload: > - shard-iclb: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) +1 > similar issue >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-iclb4/igt@i915_module_l...@reload.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-iclb8/igt@i915_module_l...@reload.html > > * igt@kms_cursor_crc@pipe-b-cursor-128x42-random: > - shard-skl: [PASS][6] -> [FAIL][7] ([i915#54]) +5 similar issues >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-128x42-random.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-128x42-random.html > > * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: > - shard-hsw: [PASS][8] -> [FAIL][9] ([i915#96]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html > > * igt@kms_cursor_legacy@cursora-vs-flipa-varying-size: > - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#1635] / > [i915#1982]) +1 similar issue >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-apl1/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-apl6/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html > > * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: > - shard-hsw: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-hsw8/igt@kms_cursor_leg...@cursorb-vs-flipb-toggle.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-hsw1/igt@kms_cursor_leg...@cursorb-vs-flipb-toggle.html > > * igt@kms_cursor_legacy@flip-vs-cursor-toggle: > - shard-skl: [PASS][14] -> [FAIL][15] ([i915#2346]) >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html > > * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1: > - shard-glk: [PASS][16] -> [FAIL][17] ([i915#2122]) >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9258/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18847/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html > > * igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a1: > - shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) +3 > similar issues >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: replace idr_init() by idr_init_base()
== Series Details ==
Series: drm/i915/gvt: replace idr_init() by idr_init_base()
URL : https://patchwork.freedesktop.org/series/83498/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9263 -> Patchwork_18853
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/index.html
New tests
-
New tests have been introduced between CI_DRM_9263 and Patchwork_18853:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18853 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-bsw-kefka/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-bsw-kefka/igt@i915_module_l...@reload.html
- fi-icl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-y/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-icl-y/igt@i915_module_l...@reload.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([i915#1161] / [i915#262])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-ehl-1}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-apl-guc: [DMESG-WARN][13] ([i915#1635] / [i915#1982]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-apl-guc/igt@i915_pm_...@module-reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-apl-guc/igt@i915_pm_...@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@d-dsi1:
- {fi-tgl-dsi}: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] +1
similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-mode...@d-dsi1.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-mode...@d-dsi1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 40)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9263 -
Re: [Intel-gfx] [PATCH 1/8] drm/i915: Extract intel_crtc_ddb_weight()
On Tue, Oct 27, 2020 at 10:39:48PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> skl_ddb_get_pipe_allocation_limits() doesn't care how the weights
> for distributing the ddb are caclculated for each pipe. Put that
> calculation into a separate function so that such mundane details
> are hidden from view.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/intel_pm.c | 46 -
> 1 file changed, 28 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0ef01a01ef8d..d14cdedc4ac3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4084,6 +4084,25 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private
> *dev_priv,
> return slice_mask;
> }
>
> +static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state
> *crtc_state)
> +{
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + int hdisplay, vdisplay;
> +
> + if (!crtc_state->hw.active)
> + return 0;
> +
> + /*
> + * Watermark/ddb requirement highly depends upon width of the
> + * framebuffer, So instead of allocating DDB equally among pipes
> + * distribute DDB based on resolution/width of the display.
> + */
> + drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> +
> + return hdisplay;
> +}
> +
> static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
> u8 active_pipes);
>
> @@ -4098,7 +4117,7 @@ skl_ddb_get_pipe_allocation_limits(struct
> drm_i915_private *dev_priv,
> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
> const struct intel_crtc *crtc;
> - u32 pipe_width = 0, total_width_in_range = 0,
> width_before_pipe_in_range = 0;
> + unsigned int pipe_weight = 0, total_weight = 0, weight_before_pipe = 0;
> enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
> struct intel_dbuf_state *new_dbuf_state =
> intel_atomic_get_new_dbuf_state(intel_state);
> @@ -4167,18 +4186,11 @@ skl_ddb_get_pipe_allocation_limits(struct
> drm_i915_private *dev_priv,
>*/
> ddb_range_size = hweight8(dbuf_slice_mask) * slice_size;
>
> - /*
> - * Watermark/ddb requirement highly depends upon width of the
> - * framebuffer, So instead of allocating DDB equally among pipes
> - * distribute DDB based on resolution/width of the display.
> - */
> total_slice_mask = dbuf_slice_mask;
> for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> enum pipe pipe = crtc->pipe;
> - int hdisplay, vdisplay;
> - u32 pipe_dbuf_slice_mask;
> + unsigned int weight;
> + u8 pipe_dbuf_slice_mask;
>
> if (!crtc_state->hw.active)
> continue;
> @@ -4205,14 +4217,13 @@ skl_ddb_get_pipe_allocation_limits(struct
> drm_i915_private *dev_priv,
> if (dbuf_slice_mask != pipe_dbuf_slice_mask)
> continue;
>
> - drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> -
> - total_width_in_range += hdisplay;
> + weight = intel_crtc_ddb_weight(crtc_state);
> + total_weight += weight;
>
> if (pipe < for_pipe)
> - width_before_pipe_in_range += hdisplay;
> + weight_before_pipe += weight;
> else if (pipe == for_pipe)
> - pipe_width = hdisplay;
> + pipe_weight = weight;
> }
>
> /*
> @@ -4227,9 +4238,8 @@ skl_ddb_get_pipe_allocation_limits(struct
> drm_i915_private *dev_priv,
> return ret;
> }
>
> - start = ddb_range_size * width_before_pipe_in_range /
> total_width_in_range;
> - end = ddb_range_size *
> - (width_before_pipe_in_range + pipe_width) /
> total_width_in_range;
> + start = ddb_range_size * weight_before_pipe / total_weight;
> + end = ddb_range_size * (weight_before_pipe + pipe_weight) /
> total_weight;
>
> alloc->start = offset + start;
> alloc->end = offset + end;
> --
> 2.26.2
>
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state
== Series Details == Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state URL : https://patchwork.freedesktop.org/series/83493/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9263_full -> Patchwork_18850_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18850_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18850_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18850_full: ### IGT changes ### Possible regressions * igt@gen7_exec_parse@basic-allowed: - shard-hsw: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw6/igt@gen7_exec_pa...@basic-allowed.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-hsw1/igt@gen7_exec_pa...@basic-allowed.html New tests - New tests have been introduced between CI_DRM_9263_full and Patchwork_18850_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18850_full that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@hotrebind-lateclose: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-snb4/igt@core_hotunp...@hotrebind-lateclose.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-snb5/igt@core_hotunp...@hotrebind-lateclose.html * igt@gem_exec_schedule@submit-late-slice@rcs0: - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#1888]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk6/igt@gem_exec_schedule@submit-late-sl...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk2/igt@gem_exec_schedule@submit-late-sl...@rcs0.html * igt@gem_exec_whisper@basic-fds-priority: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk2/igt@gem_exec_whis...@basic-fds-priority.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk3/igt@gem_exec_whis...@basic-fds-priority.html * igt@gem_exec_whisper@basic-normal-all: - shard-hsw: [PASS][9] -> [FAIL][10] ([i915#1888]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw6/igt@gem_exec_whis...@basic-normal-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-hsw1/igt@gem_exec_whis...@basic-normal-all.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#454]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb6/igt@i915_pm...@dc6-psr.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-iclb4/igt@i915_pm...@dc6-psr.html * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +6 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl2/igt@i915_pm_...@modeset-lpsp-stress.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl4/igt@i915_pm_...@modeset-lpsp-stress.html * igt@kms_color@pipe-b-ctm-0-5: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#182]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk3/igt@kms_co...@pipe-b-ctm-0-5.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk4/igt@kms_co...@pipe-b-ctm-0-5.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#300]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-128x42-offscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl9/igt@kms_cursor_...@pipe-c-cursor-128x42-offscreen.html * igt@kms_cursor_legacy@flip-vs-cursor-varying-size: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2346]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-tglb6/igt@kms_cursor_leg...@flip-vs-cursor-varying-size.html [22]: http
Re: [Intel-gfx] [PATCH v4 31/61] drm/i915: Prepare for obj->mm.lock removal
Op 02-11-2020 om 11:13 schreef Thomas Hellström:
>
> On 10/16/20 12:44 PM, Maarten Lankhorst wrote:
>> From: Thomas Hellström
>>
>> Stolen objects need to lock, and we may call put_pages when
>> refcount drops to 0, ensure all calls are handled correctly.
>>
>> Idea-from: Thomas Hellström
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_object.h | 14 ++
>> drivers/gpu/drm/i915/gem/i915_gem_pages.c | 14 --
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 10 +-
>> 3 files changed, 35 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> index 8db84ce09d9f..a3a701d849bf 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> @@ -112,6 +112,20 @@ i915_gem_object_put(struct drm_i915_gem_object *obj)
>> #define assert_object_held(obj) dma_resv_assert_held((obj)->base.resv)
>> +/*
>> + * If more than one potential simultaneous locker, assert held.
>> + */
>> +static inline void assert_object_held_shared(struct drm_i915_gem_object
>> *obj)
>> +{
>> + /*
>> + * Note mm list lookup is protected by
>> + * kref_get_unless_zero().
>> + */
>> + if (IS_ENABLED(CONFIG_LOCKDEP) &&
>> + kref_read(&obj->base.refcount) > 0)
>> + lockdep_assert_held(&obj->mm.lock);
>> +}
>> +
>> static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj,
>> struct i915_gem_ww_ctx *ww,
>> bool intr)
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
>> index ef1d5fabd077..429ec652c394 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
>> @@ -18,7 +18,7 @@ void __i915_gem_object_set_pages(struct
>> drm_i915_gem_object *obj,
>> unsigned long supported = INTEL_INFO(i915)->page_sizes;
>> int i;
>> - lockdep_assert_held(&obj->mm.lock);
>> + assert_object_held_shared(obj);
>> if (i915_gem_object_is_volatile(obj))
>> obj->mm.madv = I915_MADV_DONTNEED;
>> @@ -67,6 +67,7 @@ void __i915_gem_object_set_pages(struct
>> drm_i915_gem_object *obj,
>> struct list_head *list;
>> unsigned long flags;
>> + lockdep_assert_held(&obj->mm.lock);
>> spin_lock_irqsave(&i915->mm.obj_lock, flags);
>> i915->mm.shrink_count++;
>> @@ -88,6 +89,8 @@ int i915_gem_object_get_pages(struct
>> drm_i915_gem_object *obj)
>> struct drm_i915_private *i915 = to_i915(obj->base.dev);
>> int err;
>> + assert_object_held_shared(obj);
>> +
>> if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
>> drm_dbg(&i915->drm,
>> "Attempting to obtain a purgeable object\n");
>> @@ -115,6 +118,8 @@ int __i915_gem_object_get_pages(struct
>> drm_i915_gem_object *obj)
>> if (err)
>> return err;
>> + assert_object_held_shared(obj);
>> +
>> if (unlikely(!i915_gem_object_has_pages(obj))) {
>> GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
>> @@ -142,7 +147,7 @@ void i915_gem_object_truncate(struct
>> drm_i915_gem_object *obj)
>> /* Try to discard unwanted pages */
>> void i915_gem_object_writeback(struct drm_i915_gem_object *obj)
>> {
>> - lockdep_assert_held(&obj->mm.lock);
>> + assert_object_held_shared(obj);
>> GEM_BUG_ON(i915_gem_object_has_pages(obj));
>> if (obj->ops->writeback)
>> @@ -175,6 +180,8 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
>> *obj)
>> {
>> struct sg_table *pages;
>> + assert_object_held_shared(obj);
>> +
>> pages = fetch_and_zero(&obj->mm.pages);
>> if (IS_ERR_OR_NULL(pages))
>> return pages;
>> @@ -202,6 +209,9 @@ int __i915_gem_object_put_pages_locked(struct
>> drm_i915_gem_object *obj)
>> if (i915_gem_object_has_pinned_pages(obj))
>> return -EBUSY;
>> + /* May be called by shrinker from within get_pages() (on another bo)
>> */
>> + assert_object_held_shared(obj);
>> +
>> i915_gem_object_release_mmap_offset(obj);
>> /*
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> index 9a9242b5a99f..1fd287ce86f4 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>> @@ -593,11 +593,19 @@ __i915_gem_object_create_stolen(struct
>> intel_memory_region *mem,
>> cache_level = HAS_LLC(mem->i915) ? I915_CACHE_LLC : I915_CACHE_NONE;
>> i915_gem_object_set_cache_coherency(obj, cache_level);
>> + if (WARN_ON(!i915_gem_object_trylock(obj))) {
>> + err = -EBUSY;
>> + goto cleanup;
>> + }
>
> We should probably keep the _isolated annotation here. I think it needs to be
> used elsewhere anyway.
>
> Otherwise
>
> Signed-off-by
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v3,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/83495/ State : success == Summary == CI Bug Log - changes from CI_DRM_9263_full -> Patchwork_18851_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9263_full and Patchwork_18851_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18851_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#54]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-128x42-offscreen.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-128x42-offscreen.html * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl4/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-skl1/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html * igt@kms_flip@plain-flip-fb-recreate@a-edp1: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#2122]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl4/igt@kms_flip@plain-flip-fb-recre...@a-edp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-skl1/igt@kms_flip@plain-flip-fb-recre...@a-edp1.html * igt@kms_flip_tiling@flip-yf-tiled: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-kbl3/igt@kms_flip_til...@flip-yf-tiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-kbl6/igt@kms_flip_til...@flip-yf-tiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-snb: [PASS][9] -> [FAIL][10] ([i915#2546]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-snb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-snb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-2p-rte: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#49]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk3/igt@kms_frontbuffer_track...@fbc-2p-rte.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-glk5/igt@kms_frontbuffer_track...@fbc-2p-rte.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack: - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-tglb2/igt@kms_frontbuffer_track...@fbcpsr-1p-indfb-fliptrack.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-tglb1/igt@kms_frontbuffer_track...@fbcpsr-1p-indfb-fliptrack.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb4/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-iclb5/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl8/igt@kms_...@bpc-switch-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-skl6/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18851/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_universal_plane@universal-plane-gen9-features-pipe-b: - shard-apl: [PASS][23]
[Intel-gfx] [PATCH i-g-t v2] gem_wsim: Use CTX_TIMESTAMP for timed spinners
Use MI_MATH and MI_COND_BBE we can construct a loop that runs for a
precise number of clock cycles, as measured by the CTX_TIMESTAMP. We use
the CTX_TIMESTAMP (as opposed to the CS_TIMESTAMP) so that the elapsed
time is measured local to the context, and the length of the batch is
unaffected by preemption. Since the clock ticks at a known frequency, we
can directly translate the batch durations into cycles and so remove the
requirement for nop calibration, and the often excessively large nop
batches.
The downside to this is that we need to use engine local registers, and
before gen11 there is no support in the CS for relative mmio and so this
technique does not support transparent load balancing on a virtual
engine before Icelake.
v2: More commentary, more code removal.
Signed-off-by: Chris Wilson
---
benchmarks/gem_wsim.c | 538 ++
1 file changed, 181 insertions(+), 357 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index dbb46b9aa..ecad4a8dc 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -176,10 +176,9 @@ struct w_step
struct drm_i915_gem_execbuffer2 eb;
struct drm_i915_gem_exec_object2 *obj;
- struct drm_i915_gem_relocation_entry reloc[1];
- unsigned long bb_sz;
+ struct drm_i915_gem_relocation_entry reloc[3];
uint32_t bb_handle;
- uint32_t *recursive_bb_start;
+ uint32_t *bb_duration;
};
struct ctx {
@@ -227,10 +226,6 @@ struct workload
unsigned int nrequest[NUM_ENGINES];
};
-static const unsigned int nop_calibration_us = 1000;
-static bool has_nop_calibration = false;
-static bool sequential = true;
-
static unsigned int master_prng;
static int verbose = 1;
@@ -253,59 +248,71 @@ static const char *ring_str_map[NUM_ENGINES] = {
[VECS] = "VECS",
};
-/* stores calibrations for particular engines */
-static unsigned long engine_calib_map[NUM_ENGINES];
-
-static enum intel_engine_id
-ci_to_engine_id(int class, int instance)
-{
- static const struct {
- int class;
- int instance;
- unsigned int id;
- } map[] = {
- { I915_ENGINE_CLASS_RENDER, 0, RCS },
- { I915_ENGINE_CLASS_COPY, 0, BCS },
- { I915_ENGINE_CLASS_VIDEO, 0, VCS1 },
- { I915_ENGINE_CLASS_VIDEO, 1, VCS2 },
- { I915_ENGINE_CLASS_VIDEO, 2, VCS2 }, /* FIXME/ICL */
- { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, VECS },
+static int read_timestamp_frequency(int i915)
+{
+ int value = 0;
+ drm_i915_getparam_t gp = {
+ .value = &value,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
};
-
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(map); i++) {
- if (class == map[i].class && instance == map[i].instance)
- return map[i].id;
- }
- return -1;
+ ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
+ return value;
}
-static void
-apply_unset_calibrations(unsigned long raw_number)
+static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
{
- for (int i = 0; i < NUM_ENGINES; i++)
- engine_calib_map[i] += engine_calib_map[i] ? 0 : raw_number;
+ return (x + y - 1) / y;
}
-static void
-print_engine_calibrations(void)
+static uint64_t ns_to_ctx_ticks(uint64_t ns)
{
- bool first_entry = true;
+ static long f;
- printf("Nop calibration for %uus delay is: ", nop_calibration_us);
- for (int i = 0; i < NUM_ENGINES; i++) {
- /* skip engines not present and DEFAULT and VCS */
- if (i != DEFAULT && i != VCS && engine_calib_map[i]) {
- if (first_entry) {
- printf("%s=%lu", ring_str_map[i],
engine_calib_map[i]);
- first_entry = false;
- } else {
- printf(",%s=%lu", ring_str_map[i],
engine_calib_map[i]);
- }
- }
+ if (!f) {
+ f = read_timestamp_frequency(fd);
+ if (intel_gen(intel_get_drm_devid(fd)) == 11)
+ f = 1250; /* icl!!! are you feeling alright? */
}
- printf("\n");
+
+ return div64_u64_round_up(ns * f, NSEC_PER_SEC);
+}
+
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+
+#define MI_ARB_CHECK MI_INSTR(0x5, 0)
+
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2)MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1)MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1)MI_M
[Intel-gfx] [PATCH] drm/i915: Prevent GGTT access if not available for pread/pwrite
If there is no mappable GGTT aperture, trying to use it for
copy_(from|to)_user is a dangerous experience. Report ENODEV to indicate
the operation is not supported to the upper layer.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bb0c12975f38..a1f1ffe18682 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -61,6 +61,9 @@ insert_mappable_node(struct i915_ggtt *ggtt, struct
drm_mm_node *node, u32 size)
{
int err;
+ if (!i915_ggtt_has_aperture(ggtt))
+ return -ENODEV;
+
err = mutex_lock_interruptible(&ggtt->vm.mutex);
if (err)
return err;
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state
== Series Details == Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state URL : https://patchwork.freedesktop.org/series/83497/ State : success == Summary == CI Bug Log - changes from CI_DRM_9263_full -> Patchwork_18852_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_18852_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18852_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18852_full: ### IGT changes ### Warnings * igt@core_hotunplug@hotrebind-lateclose: - shard-hsw: [WARN][1] ([i915#2283]) -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw6/igt@core_hotunp...@hotrebind-lateclose.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-hsw8/igt@core_hotunp...@hotrebind-lateclose.html New tests - New tests have been introduced between CI_DRM_9263_full and Patchwork_18852_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18852_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#198]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl2/igt@gem_ctx_isolation@preservation...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-skl1/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@gtt: - shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@gtt.html * igt@kms_big_fb@linear-16bpp-rotate-180: - shard-hsw: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw2/igt@kms_big...@linear-16bpp-rotate-180.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-hsw6/igt@kms_big...@linear-16bpp-rotate-180.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-kbl3/igt@kms_cursor_...@pipe-b-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-kbl4/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-128x42-offscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-128x42-offscreen.html * igt@kms_cursor_legacy@flip-vs-cursor-varying-size: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2346]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-tglb6/igt@kms_cursor_leg...@flip-vs-cursor-varying-size.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-tglb6/igt@kms_cursor_leg...@flip-vs-cursor-varying-size.html * igt@kms_flip@bo-too-big-interruptible@a-edp1: - shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb2/igt@kms_flip@bo-too-big-interrupti...@a-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-iclb7/igt@kms_flip@bo-too-big-interrupti...@a-edp1.html * igt@kms_flip@dpms-vs-vblank-race@a-dp1: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-kbl2/igt@kms_flip@dpms-vs-vblank-r...@a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-kbl3/igt@kms_flip@dpms-vs-vblank-r...@a-dp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18852/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a1.html * ig
[Intel-gfx] [PATCH] drm/i915/perf: replace idr_init() by idr_init_base()
idr_init() uses base 0 which is an invalid identifier. The new function
idr_init_base allows IDR to set the ID lookup from base 1. This avoids
all lookups that otherwise starts from 0 since 0 is always unused.
References: commit 6ce711f27500 ("idr: Make 1-based IDRs more efficient")
Signed-off-by: Deepak R Varma
---
drivers/gpu/drm/i915/i915_perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e94976976571..2d033255b7cf 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4367,7 +4367,7 @@ void i915_perf_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 2;
mutex_init(&perf->metrics_lock);
- idr_init(&perf->metrics_idr);
+ idr_init_base(&perf->metrics_idr, 1);
/* We set up some ratelimit state to potentially throttle any
* _NOTES about spurious, invalid OA reports which we don't
--
2.25.1
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[Intel-gfx] [PATCH 2/2] drm/i915/gem: Pull phys pread/pwrite implementations to the backend
More the specialised interation with the physical GEM object from the
pread/pwrite ioctl handler into the phys backend.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 55
drivers/gpu/drm/i915/i915_gem.c | 26 ---
2 files changed, 55 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 28147aab47b9..3a4dfe2ef1da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -134,6 +134,58 @@ i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj,
vaddr, dma);
}
+static int
+phys_pwrite(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *args)
+{
+ void *vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
+ char __user *user_data = u64_to_user_ptr(args->data_ptr);
+ int err;
+
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ if (err)
+ return err;
+
+ /*
+* We manually control the domain here and pretend that it
+* remains coherent i.e. in the GTT domain, like shmem_pwrite.
+*/
+ i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
+
+ if (copy_from_user(vaddr, user_data, args->size))
+ return -EFAULT;
+
+ drm_clflush_virt_range(vaddr, args->size);
+ intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
+
+ i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
+ return 0;
+}
+
+static int
+phys_pread(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *args)
+{
+ void *vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
+ char __user *user_data = u64_to_user_ptr(args->data_ptr);
+ int err;
+
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (err)
+ return err;
+
+ drm_clflush_virt_range(vaddr, args->size);
+ if (copy_to_user(user_data, vaddr, args->size))
+ return -EFAULT;
+
+ return 0;
+}
+
static void phys_release(struct drm_i915_gem_object *obj)
{
fput(obj->base.filp);
@@ -144,6 +196,9 @@ static const struct drm_i915_gem_object_ops
i915_gem_phys_ops = {
.get_pages = i915_gem_object_get_pages_phys,
.put_pages = i915_gem_object_put_pages_phys,
+ .pread = phys_pread,
+ .pwrite = phys_pwrite,
+
.release = phys_release,
};
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d58fe1ddc3e1..58276694c848 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -179,30 +179,6 @@ int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
return ret;
}
-static int
-i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
-struct drm_i915_gem_pwrite *args,
-struct drm_file *file)
-{
- void *vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
- char __user *user_data = u64_to_user_ptr(args->data_ptr);
-
- /*
-* We manually control the domain here and pretend that it
-* remains coherent i.e. in the GTT domain, like shmem_pwrite.
-*/
- i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
-
- if (copy_from_user(vaddr, user_data, args->size))
- return -EFAULT;
-
- drm_clflush_virt_range(vaddr, args->size);
- intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
-
- i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
- return 0;
-}
-
static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
@@ -872,8 +848,6 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
if (ret == -EFAULT || ret == -ENOSPC) {
if (i915_gem_object_has_struct_page(obj))
ret = i915_gem_shmem_pwrite(obj, args);
- else
- ret = i915_gem_phys_pwrite(obj, args, file);
}
i915_gem_object_unpin_pages(obj);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/gem: Allow backends to override pread implementation
From: Matthew Auld
As there are more complicated interactions between the different backing
stores and userspace, push the control into the backends rather than
accumulate them all inside the ioctl handlers.
Signed-off-by: Matthew Auld
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 2 ++
drivers/gpu/drm/i915/i915_gem.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index fedfebf13344..e2d9b7e1e152 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -56,6 +56,8 @@ struct drm_i915_gem_object_ops {
void (*truncate)(struct drm_i915_gem_object *obj);
void (*writeback)(struct drm_i915_gem_object *obj);
+ int (*pread)(struct drm_i915_gem_object *obj,
+const struct drm_i915_gem_pread *arg);
int (*pwrite)(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pwrite *arg);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bb0c12975f38..d58fe1ddc3e1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -527,6 +527,12 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
trace_i915_gem_object_pread(obj, args->offset, args->size);
+ ret = -ENODEV;
+ if (obj->ops->pread)
+ ret = obj->ops->pread(obj, args);
+ if (ret != -ENODEV)
+ goto out;
+
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE,
MAX_SCHEDULE_TIMEOUT);
--
2.20.1
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gvt: replace idr_init() by idr_init_base()
== Series Details == Series: drm/i915/gvt: replace idr_init() by idr_init_base() URL : https://patchwork.freedesktop.org/series/83498/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9263_full -> Patchwork_18853_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18853_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18853_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18853_full: ### IGT changes ### Possible regressions * igt@gem_exec_whisper@basic-normal-all: - shard-hsw: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw6/igt@gem_exec_whis...@basic-normal-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-hsw2/igt@gem_exec_whis...@basic-normal-all.html New tests - New tests have been introduced between CI_DRM_9263_full and Patchwork_18853_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18853_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_userptr_blits@sync-unmap: - shard-hsw: [PASS][5] -> [FAIL][6] ([i915#1888]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw8/igt@gem_userptr_bl...@sync-unmap.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-hsw6/igt@gem_userptr_bl...@sync-unmap.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / [i915#716]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl10/igt@gen9_exec_pa...@allowed-single.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-skl2/igt@gen9_exec_pa...@allowed-single.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-random: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-256x85-random.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-skl4/igt@kms_cursor_...@pipe-a-cursor-256x85-random.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2122]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-hdmi-a1.html * igt@kms_flip@plain-flip-fb-recreate@c-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#2122]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl4/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-skl2/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html * igt@kms_flip_tiling@flip-yf-tiled: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-kbl3/igt@kms_flip_til...@flip-yf-tiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-kbl7/igt@kms_flip_til...@flip-yf-tiled.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl8/igt@kms_...@bpc-switch-dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18853/shard-skl10/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane@plane-position-hole-pipe-a-planes: - shard-skl: [PASS][21] -> [DM
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prevent GGTT access if not available for pread/pwrite
== Series Details ==
Series: drm/i915: Prevent GGTT access if not available for pread/pwrite
URL : https://patchwork.freedesktop.org/series/83505/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9265 -> Patchwork_18854
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/index.html
New tests
-
New tests have been introduced between CI_DRM_9265 and Patchwork_18854:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18854 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-7500u: [DMESG-WARN][3] -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar
issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-byt-j1900/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/fi-byt-j1900/igt@i915_pm_...@module-reload.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
Warnings
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-gdg-551: [FAIL][11] -> [SKIP][12] ([fdo#109271])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-gdg-551/igt@amdgpu/amd_pr...@i915-to-amd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/fi-gdg-551/igt@amdgpu/amd_pr...@i915-to-amd.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
Participating hosts (45 -> 40)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9265 -> Patchwork_18854
CI-20190529: 20190529
CI_DRM_9265: 4152d4ab08d937cfb9254d0e880f1daea64db549 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5832: 9c583f7e2a6638b5ff6a3682fea548a1313512e7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18854: 855f92fde80f0299418641a2b60bc7db602a004f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
855f92fde80f drm/i915: Prevent GGTT access if not available for pread/pwrite
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Re-enable FBC on TGL
FBC was disabled on TGL due to random underruns. It has been determined that FBC will not work reliably with PSR2. This series re-enables fbc along with taking care of the PSR2 limitations for TGL. Test-with: 20201104195142.3223-1-uma.shan...@intel.com Uma Shankar (2): drm/i915/display/tgl: Disable FBC with PSR2 Revert "drm/i915/display/fbc: Disable fbc by default on TGL" drivers/gpu/drm/i915/display/intel_fbc.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with PSR2
There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index a5b072816a7b..32c411414908 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -799,6 +799,12 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
struct intel_fbc *fbc = &dev_priv->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
+ if (dev_priv->psr.sink_psr2_support &&
+ IS_TIGERLAKE(dev_priv)) {
+ fbc->no_fbc_reason = "not supported with PSR2";
+ return false;
+ }
+
if (!intel_fbc_can_enable(dev_priv))
return false;
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
FBC can be re-enabled on TGL with WA of keeping it disabled while PSR2 is enabled. This reverts commit 2982ded2ff5ce0cf1a49bc39a526da182782b664. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_fbc.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 32c411414908..c159d501fa52 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1439,13 +1439,6 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) if (!HAS_FBC(dev_priv)) return 0; - /* -* Fbc is causing random underruns in CI execution on TGL platforms. -* Disabling the same while the problem is being debugged and analyzed. -*/ - if (IS_TIGERLAKE(dev_priv)) - return 0; - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) return 1; -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: replace idr_init() by idr_init_base()
== Series Details ==
Series: drm/i915/perf: replace idr_init() by idr_init_base()
URL : https://patchwork.freedesktop.org/series/83506/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9265 -> Patchwork_18855
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/index.html
New tests
-
New tests have been introduced between CI_DRM_9265 and Patchwork_18855:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18855 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem:[PASS][1] -> [DMESG-WARN][2] ([i915#2605])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-skl-lmem/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/fi-skl-lmem/igt@i915_pm_...@module-reload.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +2 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-7500u: [DMESG-WARN][5] -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-tgl-u2: [DMESG-WARN][7] ([i915#1982] / [k.org#205379]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-tgl-u2/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/fi-tgl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-byt-j1900/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/fi-byt-j1900/igt@i915_pm_...@module-reload.html
* igt@kms_busy@basic@flip:
- {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-tgl-dsi/igt@kms_busy@ba...@flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/fi-tgl-dsi/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 40)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9265 -> Patchwork_18855
CI-20190529: 20190529
CI_DRM_9265: 4152d4ab08d937cfb9254d0e880f1daea64db549 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5832: 9c583f7e2a6638b5ff6a3682fea548a1313512e7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18855: 44c13256094b27144f62ba4c3fc6b36d66fc1149 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
44c13256094b drm/i915/perf: replace idr_init() by idr_init_base()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/gem: Allow backends to override pread implementation
== Series Details == Series: series starting with [1/2] drm/i915/gem: Allow backends to override pread implementation URL : https://patchwork.freedesktop.org/series/83508/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/lin
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gem: Allow backends to override pread implementation
== Series Details ==
Series: series starting with [1/2] drm/i915/gem: Allow backends to override
pread implementation
URL : https://patchwork.freedesktop.org/series/83508/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9265 -> Patchwork_18856
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/index.html
New tests
-
New tests have been introduced between CI_DRM_9265 and Patchwork_18856:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18856 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic@flip:
- fi-kbl-soraka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#1161] / [i915#262])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-cml-s: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-cml-s/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-cml-s/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-7500u: [DMESG-WARN][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-tgl-u2: [DMESG-WARN][9] ([i915#1982] / [k.org#205379]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-tgl-u2/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-tgl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-n3050: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-byt-j1900/igt@i915_pm_...@module-reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-byt-j1900/igt@i915_pm_...@module-reload.html
* igt@kms_busy@basic@flip:
- {fi-kbl-7560u}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-kbl-7560u/igt@kms_busy@ba...@flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-kbl-7560u/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
Warnings
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-gdg-551: [FAIL][19] -> [SKIP][20] ([fdo#109271])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-gdg-551/igt@amdgpu/amd_pr...@i915-to-amd.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/fi-gdg-551/igt@amdgpu/amd_pr...@i915-to-amd.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 40)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-b
[Intel-gfx] ✓ Fi.CI.BAT: success for Re-enable FBC on TGL
== Series Details ==
Series: Re-enable FBC on TGL
URL : https://patchwork.freedesktop.org/series/83510/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9265 -> Patchwork_18857
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/index.html
New tests
-
New tests have been introduced between CI_DRM_9265 and Patchwork_18857:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18857 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-7500u: [DMESG-WARN][5] -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-tgl-u2: [DMESG-WARN][7] ([i915#1982] / [k.org#205379]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-tgl-u2/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/fi-tgl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-n3050: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-byt-j1900/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/fi-byt-j1900/igt@i915_pm_...@module-reload.html
* igt@kms_busy@basic@flip:
- {fi-kbl-7560u}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-kbl-7560u/igt@kms_busy@ba...@flip.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/fi-kbl-7560u/igt@kms_busy@ba...@flip.html
- {fi-tgl-dsi}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-tgl-dsi/igt@kms_busy@ba...@flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/fi-tgl-dsi/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 40)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* IGT: IGT_5832 -> IGTPW_5128
* Linux: CI_DRM_9265 -> Patchwork_18857
CI-20190529: 20190529
CI_DRM_9265: 4152d4ab08d937cfb9254d0e880f1daea64db549 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5128: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5128/index.html
IGT_5832: 9c583f7e2a6638b5ff6a3682fea548a1313512e7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18857: 46fef39380272d067f0d057fecd4a175d0fd21e0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
46fef3938027 Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
3aca96da289a drm/i915/display/tgl: Disable FBC with PSR2
== Logs ==
For more details see:
https
[Intel-gfx] [PATCH i-g-t] i915/gem_userptr_blits: Explicitly check userptr termination
Check that everything works as expected with nohangcheck after a broken
app.
Signed-off-by: Chris Wilson
---
tests/i915/gem_userptr_blits.c | 148 +
1 file changed, 148 insertions(+)
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index dbc82fb0d..26e06d253 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -62,6 +62,7 @@
#include "i915/gem.h"
#include "igt.h"
+#include "igt_sysfs.h"
#include "intel_bufmgr.h"
#include "sw_sync.h"
@@ -559,6 +560,142 @@ static int test_input_checking(int fd)
return 0;
}
+static bool __enable_hangcheck(int dir, bool state)
+{
+ return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static int __execbuf(int i915, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+ int err;
+
+ err = 0;
+ if (ioctl(i915, DRM_IOCTL_I915_GEM_EXECBUFFER2_WR, execbuf)) {
+ err = -errno;
+ igt_assume(err);
+ }
+
+ errno = 0;
+ return err;
+}
+
+static void alarm_handler(int sig)
+{
+}
+
+static int fill_ring(int i915, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+ struct sigaction old_sa, sa = { .sa_handler = alarm_handler };
+ int fence = execbuf->rsvd2 >> 32;
+ struct itimerval itv;
+ bool once = false;
+
+ sigaction(SIGALRM, &sa, &old_sa);
+ itv.it_interval.tv_sec = 0;
+ itv.it_interval.tv_usec = 1000;
+ itv.it_value.tv_sec = 0;
+ itv.it_value.tv_usec = 1;
+ setitimer(ITIMER_REAL, &itv, NULL);
+
+ igt_assert(execbuf->flags & I915_EXEC_FENCE_OUT);
+ do {
+ int err = __execbuf(i915, execbuf);
+
+ if (err == 0) {
+ close(fence);
+ fence = execbuf->rsvd2 >> 32;
+ continue;
+ }
+
+ if (err == -EWOULDBLOCK || once)
+ break;
+
+ /* sleep until the next timer interrupt (woken on signal) */
+ pause();
+ once = true;
+ } while (1);
+
+ memset(&itv, 0, sizeof(itv));
+ setitimer(ITIMER_REAL, &itv, NULL);
+ sigaction(SIGALRM, &old_sa, NULL);
+
+ return fence;
+}
+
+static void test_nohangcheck_hostile(int i915)
+{
+ const struct intel_execution_engine2 *e;
+ igt_hang_t hang;
+ uint32_t ctx;
+ int fence = -1;
+ int err = 0;
+ int dir;
+
+ /*
+* Even if the user disables hangcheck, we must still recover.
+*/
+
+ i915 = gem_reopen_driver(i915);
+
+ dir = igt_params_open(i915);
+ igt_require(dir != -1);
+
+ ctx = gem_context_create(i915);
+ hang = igt_allow_hang(i915, ctx, 0);
+ igt_require(__enable_hangcheck(dir, false));
+
+ for_each_physical_engine(i915, ctx, e) {
+ igt_spin_t *spin;
+ int new;
+
+ /* Set a fast hang detection to speed up the test */
+ gem_engine_property_printf(i915, e->name,
+ "preempt_timeout_ms", "%d", 50);
+
+ spin = __igt_spin_new(i915, ctx,
+ .engine = e->flags,
+ .flags = (IGT_SPIN_NO_PREEMPTION |
+ IGT_SPIN_USERPTR |
+ IGT_SPIN_FENCE_OUT));
+
+ new = fill_ring(i915, &spin->execbuf);
+ igt_assert(new != -1);
+ spin->out_fence = -1;
+
+ if (fence < 0) {
+ fence = new;
+ } else {
+ int tmp;
+
+ tmp = sync_fence_merge(fence, new);
+ close(fence);
+ close(new);
+
+ fence = tmp;
+ }
+ }
+ gem_context_destroy(i915, ctx);
+ igt_assert(fence != -1);
+
+ if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */
+ igt_debugfs_dump(i915, "i915_engine_info");
+ err = -ETIME;
+ }
+
+ __enable_hangcheck(dir, true);
+ gem_quiescent_gpu(i915);
+ igt_disallow_hang(i915, hang);
+
+ igt_assert_f(err == 0,
+"Hostile unpreemptable userptr was not cancelled
immediately upon closure\n");
+
+ igt_assert_eq(sync_fence_status(fence), -EIO);
+ close(fence);
+
+ close(dir);
+ close(i915);
+}
+
static int test_access_control(int fd)
{
/* CAP_SYS_ADMIN is needed for UNSYNCHRONIZED mappings. */
@@ -2382,6 +2519,17 @@ igt_main_args("c:", NULL, help_str, opt_handler, NULL)
igt_stop_signal_helper();
}
+ igt_subtest_group {
+ igt_fixture {
+ gem_userptr_test_synchronized();
+ if (!has_userptr(fd))
+
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Prevent GGTT access if not available for pread/pwrite
== Series Details ==
Series: drm/i915: Prevent GGTT access if not available for pread/pwrite
URL : https://patchwork.freedesktop.org/series/83505/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9265_full -> Patchwork_18854_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_18854_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18854_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18854_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_whisper@basic-normal-all:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-snb5/igt@gem_exec_whis...@basic-normal-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-snb7/igt@gem_exec_whis...@basic-normal-all.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_capture@pi@rcs0}:
- shard-skl: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl4/igt@gem_exec_capture@p...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
New tests
-
New tests have been introduced between CI_DRM_9265_full and
Patchwork_18854_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18854_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@gtt:
- shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@gtt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@gtt.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@wb:
- shard-hsw: [PASS][7] -> [FAIL][8] ([i915#1888])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@wb.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@wb.html
* igt@gem_workarounds@suspend-resume:
- shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([i915#1185])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-iclb4/igt@gem_workarou...@suspend-resume.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-iclb3/igt@gem_workarou...@suspend-resume.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#182])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-glk4/igt@kms_co...@pipe-b-ctm-0-5.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-glk2/igt@kms_co...@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-random:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-64x21-random.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-64x21-random.html
* igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +5
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl9/igt@kms_cursor_edge_w...@pipe-c-128x128-left-edge.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-skl10/igt@kms_cursor_edge_w...@pipe-c-128x128-left-edge.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge:
- shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-tglb2/igt@kms_cursor_edge_w...@pipe-c-256x256-top-edge.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-tglb2/igt@kms_cursor_edge_w...@pipe-c-256x256-top-edge.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][19] -> [FAIL][20] ([i915#96])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-hsw7/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18854/shard-hsw8/igt@
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_parallel: Reopen the existing device
Avoid any unnecessary filtering inside drm_open_driver() by explicitly
reopening the same device.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_parallel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_parallel.c b/tests/i915/gem_exec_parallel.c
index bdb8e3e90..1a988b957 100644
--- a/tests/i915/gem_exec_parallel.c
+++ b/tests/i915/gem_exec_parallel.c
@@ -77,7 +77,7 @@ static void *thread(void *data)
pthread_mutex_unlock(t->mutex);
if (t->flags & FDS) {
- fd = drm_open_driver(DRIVER_INTEL);
+ fd = gem_reopen_driver(t->fd);
gem_context_copy_engines(t->fd, 0, fd, 0);
} else {
fd = t->fd;
--
2.29.2
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/perf: replace idr_init() by idr_init_base()
== Series Details == Series: drm/i915/perf: replace idr_init() by idr_init_base() URL : https://patchwork.freedesktop.org/series/83506/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9265_full -> Patchwork_18855_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18855_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18855_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18855_full: ### IGT changes ### Possible regressions * igt@gem_exec_whisper@basic-queues-priority: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-iclb7/igt@gem_exec_whis...@basic-queues-priority.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-iclb2/igt@gem_exec_whis...@basic-queues-priority.html New tests - New tests have been introduced between CI_DRM_9265_full and Patchwork_18855_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18855_full that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-tglb6/igt@core_hotunp...@unbind-rebind.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-tglb2/igt@core_hotunp...@unbind-rebind.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#54]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html * igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1635] / [i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-apl6/igt@kms_cursor_edge_w...@pipe-c-128x128-left-edge.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-apl7/igt@kms_cursor_edge_w...@pipe-c-128x128-left-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#2346]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-skl9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#79]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-glk8/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-glk5/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a1.html * igt@kms_flip@plain-flip-fb-recreate@b-edp1: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#2122]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl9/igt@kms_flip@plain-flip-fb-recre...@b-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-skl4/igt@kms_flip@plain-flip-fb-recre...@b-edp1.html * igt@kms_frontbuffer_tracking@fbc-2p-rte: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-glk4/igt@kms_frontbuffer_track...@fbc-2p-rte.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-glk7/igt@kms_frontbuffer_track...@fbc-2p-rte.html * igt@kms_plane@plane-position-hole-dpms-pipe-a-planes: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-glk7/igt@kms_pl...@plane-position-hole-dpms-pipe-a-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-glk8/igt@kms_pl...@plane-position-hole-dpms-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18855/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.
Re: [Intel-gfx] [RFC 2/2] drm/i915: Use ABI engine class in error state ecode
Quoting Tvrtko Ursulin (2020-11-04 13:47:43)
> From: Tvrtko Ursulin
>
> Instead of printing out the internal engine mask, which can change between
> kernel versions making it difficult to map to actual engines, present a
> bitmask of hanging engines ABI classes. For example:
>
> [drm] GPU HANG: ecode 9:24dd:8, in gem_exec_schedu [1334]
>
> Notice the swapped the order of ecode and bitmask which makes the new
> versus old bug reports are obvious.
>
> Engine ABI class is useful to quickly categorize render vs media etc hangs
> in bug reports. Considering virtual engine even more so than the current
> scheme.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 857db66cc4a3..e7d9af184d58 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1659,17 +1659,16 @@ static u32 generate_ecode(const struct
> intel_engine_coredump *ee)
> static const char *error_msg(struct i915_gpu_coredump *error)
> {
> struct intel_engine_coredump *first = NULL;
> + unsigned int hung_classes = 0;
> struct intel_gt_coredump *gt;
> - intel_engine_mask_t engines;
> int len;
>
> - engines = 0;
> for (gt = error->gt; gt; gt = gt->next) {
> struct intel_engine_coredump *cs;
>
> for (cs = gt->engine; cs; cs = cs->next) {
> if (cs->hung) {
> - engines |= cs->engine->mask;
> + hung_classes |= BIT(cs->engine->uabi_class);
Your argument makes sense.
> if (!first)
> first = cs;
> }
> @@ -1677,9 +1676,11 @@ static const char *error_msg(struct i915_gpu_coredump
> *error)
> }
>
> len = scnprintf(error->error_msg, sizeof(error->error_msg),
> - "GPU HANG: ecode %d:%x:%08x",
> - INTEL_GEN(error->i915), engines,
> - generate_ecode(first));
> + "GPU HANG: ecode %d:%08x:%x",
> + INTEL_GEN(error->i915),
> + generate_ecode(first),
> + hung_classes);
I vote for keeping gen:engines:ecode order, for me that is biggest to
smallest.
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_parallel: Reopen the existing device
On Wed, 04 Nov 2020 14:23:21 -0800, Chris Wilson wrote:
>
> Avoid any unnecessary filtering inside drm_open_driver() by explicitly
> reopening the same device.
>
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_exec_parallel.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/i915/gem_exec_parallel.c b/tests/i915/gem_exec_parallel.c
> index bdb8e3e90..1a988b957 100644
> --- a/tests/i915/gem_exec_parallel.c
> +++ b/tests/i915/gem_exec_parallel.c
> @@ -77,7 +77,7 @@ static void *thread(void *data)
> pthread_mutex_unlock(t->mutex);
>
> if (t->flags & FDS) {
> - fd = drm_open_driver(DRIVER_INTEL);
> + fd = gem_reopen_driver(t->fd);
Reviewed-by: Ashutosh Dixit
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/gem: Allow backends to override pread implementation
== Series Details == Series: series starting with [1/2] drm/i915/gem: Allow backends to override pread implementation URL : https://patchwork.freedesktop.org/series/83508/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9265_full -> Patchwork_18856_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18856_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18856_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18856_full: ### IGT changes ### Possible regressions * igt@kms_ccs@pipe-a-crc-primary-basic: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-glk8/igt@kms_...@pipe-a-crc-primary-basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/shard-glk2/igt@kms_...@pipe-a-crc-primary-basic.html New tests - New tests have been introduced between CI_DRM_9265_full and Patchwork_18856_full: ### New CI tests (1) ### * boot: - Statuses : 199 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18856_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy@wc: - shard-hsw: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@wc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-b...@wc.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#716]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl1/igt@gen9_exec_pa...@allowed-single.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/shard-skl10/igt@gen9_exec_pa...@allowed-single.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels@edp-1-pipe-a: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl10/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-pan...@edp-1-pipe-a.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/shard-skl2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-pan...@edp-1-pipe-a.html * igt@kms_color@pipe-b-ctm-0-5: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#182]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-glk4/igt@kms_co...@pipe-b-ctm-0-5.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/shard-glk1/igt@kms_co...@pipe-b-ctm-0-5.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-64x21-random.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-64x21-random.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][13] -> [FAIL][14] ([i915#96]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-hsw7/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_flip@plain-flip-fb-recreate@b-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#2122]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl9/igt@kms_flip@plain-flip-fb-recre...@b-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/shard-skl9/igt@kms_flip@plain-flip-fb-recre...@b-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18856/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#198]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl1/igt@kms_pipe_crc_ba...@suspend-read-crc
[Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_whisper: Reopen existing device
Reopen the existing device, rather than relying on the filtering in
drm_open_driver().
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_whisper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/i915/gem_exec_whisper.c b/tests/i915/gem_exec_whisper.c
index 9acf6c306..b63d791d1 100644
--- a/tests/i915/gem_exec_whisper.c
+++ b/tests/i915/gem_exec_whisper.c
@@ -87,12 +87,12 @@ struct hang {
int fd;
};
-static void init_hang(struct hang *h)
+static void init_hang(struct hang *h, int fd)
{
uint32_t *batch;
int i, gen;
- h->fd = drm_open_driver(DRIVER_INTEL);
+ h->fd = gem_reopen_driver(fd);
igt_allow_hang(h->fd, 0, 0);
gen = intel_gen(intel_get_drm_devid(h->fd));
@@ -224,7 +224,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
igt_require(gem_has_queues(fd));
if (flags & HANG)
- init_hang(&hang);
+ init_hang(&hang, fd);
nchild = 1;
if (flags & FORKED)
@@ -304,7 +304,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
}
if (flags & FDS) {
for (n = 0; n < 64; n++)
- fds[n] = drm_open_driver(DRIVER_INTEL);
+ fds[n] = gem_reopen_driver(fd);
}
memset(batches, 0, sizeof(batches));
--
2.29.2
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[Intel-gfx] [PATCH i-g-t 2/2] i915/gem_ctx_thrash: Reopen the same device
Use gem_reopen_driver() to always reopen the same device without relying
on the filtering in drm_open_driver().
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_thrash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/gem_ctx_thrash.c b/tests/i915/gem_ctx_thrash.c
index d32619d5d..d9ddd6689 100644
--- a/tests/i915/gem_ctx_thrash.c
+++ b/tests/i915/gem_ctx_thrash.c
@@ -250,7 +250,7 @@ static void processes(void)
fds = malloc(num_ctx * sizeof(int));
igt_assert(fds);
for (unsigned n = 0; n < num_ctx; n++) {
- fds[n] = drm_open_driver(DRIVER_INTEL);
+ fds[n] = gem_reopen_driver(fd);
if (fds[n] == -1) {
int err = errno;
for (unsigned i = n; i--; )
--
2.29.2
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Re: [Intel-gfx] linux-next: manual merge of the drm-misc tree with the amdgpu tree
Hi all,
On Wed, 28 Oct 2020 12:06:31 +1100 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the drm-misc tree got a conflict in:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>
> between commit:
>
> ff72bc403170 ("drm/amdgpu: Add debugfs entry for printing VM info")
>
> from the amdgpu tree and commit:
>
> 4671078eb8e3 ("drm/amdgpu: switch over to the new pin interface")
>
> from the drm-misc tree.
>
> I fixed it up (I used the former version of this file and added the
> following patch) and can carry the fix as necessary. This is now fixed
> as far as linux-next is concerned, but any non trivial conflicts should
> be mentioned to your upstream maintainer when your tree is submitted
> for merging. You may also want to consider cooperating with the
> maintainer of the conflicting tree to minimise any particularly complex
> conflicts.
>
> From: Stephen Rothwell
> Date: Wed, 28 Oct 2020 11:52:31 +1100
> Subject: [PATCH] merge fix up for "drm/amdgpu: Add debugfs entry for printing
> VM info"
>
> Signed-off-by: Stephen Rothwell
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index baca32263ec4..06dfe9b1c7e6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1555,7 +1555,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo,
> struct seq_file *m)
> seq_printf(m, "\t\t0x%08x: %12lld byte %s",
> id, size, placement);
>
> - pin_count = READ_ONCE(bo->pin_count);
> + pin_count = READ_ONCE(bo->tbo.pin_count);
> if (pin_count)
> seq_printf(m, " pin count %d", pin_count);
>
This fix up is now needed in the merge between the drm tree and the
amdgpu tree.
--
Cheers,
Stephen Rothwell
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[Intel-gfx] linux-next: manual merge of the drm-msm tree with the drm-misc tree
Hi all,
Today's linux-next merge of the drm-msm tree got a conflict in:
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
between commit:
29b77ad7b9ca ("drm/atomic: Pass the full state to CRTC atomic_check")
from the drm-misc tree and commit:
91693cbc13c2 ("drm/msm/dpu: Add newline to printks")
from the drm-msm tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index e55be2922c2f,d4662e8184cc..
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@@ -844,12 -838,12 +844,12 @@@ static int dpu_crtc_atomic_check(struc
goto end;
}
- mode = &state->adjusted_mode;
+ mode = &crtc_state->adjusted_mode;
- DPU_DEBUG("%s: check", dpu_crtc->name);
+ DPU_DEBUG("%s: check\n", dpu_crtc->name);
/* force a full mode set if active state changed */
- if (state->active_changed)
- state->mode_changed = true;
+ if (crtc_state->active_changed)
+ crtc_state->mode_changed = true;
memset(pipe_staged, 0, sizeof(pipe_staged));
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR
On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
Quoting Lucas De Marchi (2020-10-27 06:46:18)
GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
Bridge"). Other than printing their values in debugfs we don't do
anything with them. There's not much useful information in them. These
registers may change location in future platforms, but instead of adding
new locations, it's simpler to just remove them.
This code seems to have been updated for Gen9LP, so that would indicate
the debugging information is useful, right? The value is even decoded, not
simply dumped as most registers. So I would be hesitant to drop it for
not being useful.
but just updating the register in itself for a new gen doesn't mean it's
actually useful... the commit message where this happened is pretty
vague: 350405623ff3 ("drm/i915: Update rps frequencies for BXT")
My first reaction would be to do the same if the register had moved or
if it ceased to exist in a new platform. Talking with Matt Roper some
time ago we arrived to the conclusion that just printing these values is
not giving us much benefit and it could very well be accomplished by
intel_reg.
So answering the question: is it really useful as is? IMO, no.
The second question is why we have a huge block of 1-to-1 duplicated
code in there. Has there been an incorrect merge or some transition has
been left mid-way?
not a bad merge, no. It seems to be to preserve the previous file
location since now it moved to be inside a gt dir. Long term I think
this is bad both because of the code duplication and because it's easy
to update one and forget the other.
Lucas De Marchi
Regards, Joonas
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 17 ++---
drivers/gpu/drm/i915/i915_debugfs.c | 17 ++---
drivers/gpu/drm/i915/i915_reg.h | 3 ---
3 files changed, 4 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 174a24553322..8a68088c12ea 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -296,8 +296,6 @@ static int frequency_show(struct seq_file *m, void *unused)
seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(rps, rps->efficient_freq));
} else if (INTEL_GEN(i915) >= 6) {
- u32 rp_state_limits;
- u32 gt_perf_status;
u32 rp_state_cap;
u32 rpmodectl, rpinclimit, rpdeclimit;
u32 rpstat, cagf, reqf;
@@ -307,14 +305,10 @@ static int frequency_show(struct seq_file *m, void
*unused)
u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
int max_freq;
- rp_state_limits = intel_uncore_read(uncore,
GEN6_RP_STATE_LIMITS);
- if (IS_GEN9_LP(i915)) {
+ if (IS_GEN9_LP(i915))
rp_state_cap = intel_uncore_read(uncore,
BXT_RP_STATE_CAP);
- gt_perf_status = intel_uncore_read(uncore,
BXT_GT_PERF_STATUS);
- } else {
+ else
rp_state_cap = intel_uncore_read(uncore,
GEN6_RP_STATE_CAP);
- gt_perf_status = intel_uncore_read(uncore,
GEN6_GT_PERF_STATUS);
- }
/* RPSTAT1 is in the GT power well */
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
@@ -390,13 +384,6 @@ static int frequency_show(struct seq_file *m, void *unused)
pm_isr, pm_iir);
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
rps->pm_intrmsk_mbz);
- seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
- seq_printf(m, "Render p-state ratio: %d\n",
- (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 :
0xff00)) >> 8);
- seq_printf(m, "Render p-state VID: %d\n",
- gt_perf_status & 0xff);
- seq_printf(m, "Render p-state limit: %d\n",
- rp_state_limits & 0xff);
seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ea469168cd44..c01f27eebf9c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -838,8 +838,6 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(rps, rps->efficient_freq));
} else if (INTEL_GEN(dev_priv) >= 6) {
- u32 rp_
[Intel-gfx] ✗ Fi.CI.IGT: failure for Re-enable FBC on TGL
== Series Details == Series: Re-enable FBC on TGL URL : https://patchwork.freedesktop.org/series/83510/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9265_full -> Patchwork_18857_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18857_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18857_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18857_full: ### IGT changes ### Possible regressions * igt@gem_exec_flush@basic-uc-pro-default: - shard-hsw: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-hsw8/igt@gem_exec_fl...@basic-uc-pro-default.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-hsw2/igt@gem_exec_fl...@basic-uc-pro-default.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-tglb: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-tglb6/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-tglb2/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-tglb: [PASS][5] -> [SKIP][6] +65 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-tglb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu: - shard-tglb: NOTRUN -> [SKIP][7] +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-tglb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-glk: [PASS][8] -> [INCOMPLETE][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-glk2/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-glk4/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html - shard-hsw: [PASS][10] -> [INCOMPLETE][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-hsw4/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-hsw8/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Warnings * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - shard-tglb: [DMESG-WARN][12] ([i915#2411]) -> [SKIP][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-suspend.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-tglb7/igt@kms_frontbuffer_track...@fbcpsr-suspend.html New tests - New tests have been introduced between CI_DRM_9265_full and Patchwork_18857_full: ### New CI tests (1) ### * boot: - Statuses : 198 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18857_full that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@hotrebind-lateclose: - shard-snb: [PASS][14] -> [INCOMPLETE][15] ([i915#82]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-snb5/igt@core_hotunp...@hotrebind-lateclose.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-snb4/igt@core_hotunp...@hotrebind-lateclose.html * igt@drm_read@short-buffer-wakeup: - shard-apl: [PASS][16] -> [DMESG-WARN][17] ([i915#1635] / [i915#1982]) +7 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-apl7/igt@drm_r...@short-buffer-wakeup.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-apl7/igt@drm_r...@short-buffer-wakeup.html * igt@gem_blits@basic: - shard-skl: [PASS][18] -> [TIMEOUT][19] ([i915#2502]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl3/igt@gem_bl...@basic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18857/shard-skl10/igt@gem_bl...@basic.html * igt@gem_exec_reloc@basic-cpu-gtt-noreloc: - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +42 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9265/shard-skl3/igt@gem_exec_re...@basic-cpu-gtt-noreloc.html [21]: https://intel-
Re: [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_whisper: Reopen existing device
On Wed, 04 Nov 2020 16:21:23 -0800, Chris Wilson wrote:
>
> Reopen the existing device, rather than relying on the filtering in
> drm_open_driver().
Reviewed-by: Ashutosh Dixit
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_exec_whisper.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tests/i915/gem_exec_whisper.c b/tests/i915/gem_exec_whisper.c
> index 9acf6c306..b63d791d1 100644
> --- a/tests/i915/gem_exec_whisper.c
> +++ b/tests/i915/gem_exec_whisper.c
> @@ -87,12 +87,12 @@ struct hang {
> int fd;
> };
>
> -static void init_hang(struct hang *h)
> +static void init_hang(struct hang *h, int fd)
> {
> uint32_t *batch;
> int i, gen;
>
> - h->fd = drm_open_driver(DRIVER_INTEL);
> + h->fd = gem_reopen_driver(fd);
> igt_allow_hang(h->fd, 0, 0);
>
> gen = intel_gen(intel_get_drm_devid(h->fd));
> @@ -224,7 +224,7 @@ static void whisper(int fd, unsigned engine, unsigned
> flags)
> igt_require(gem_has_queues(fd));
>
> if (flags & HANG)
> - init_hang(&hang);
> + init_hang(&hang, fd);
>
> nchild = 1;
> if (flags & FORKED)
> @@ -304,7 +304,7 @@ static void whisper(int fd, unsigned engine, unsigned
> flags)
> }
> if (flags & FDS) {
> for (n = 0; n < 64; n++)
> - fds[n] = drm_open_driver(DRIVER_INTEL);
> + fds[n] = gem_reopen_driver(fd);
> }
>
> memset(batches, 0, sizeof(batches));
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Re: [Intel-gfx] [PATCH i-g-t 2/2] i915/gem_ctx_thrash: Reopen the same device
On Wed, 04 Nov 2020 16:21:24 -0800, Chris Wilson wrote:
>
> Use gem_reopen_driver() to always reopen the same device without relying
> on the filtering in drm_open_driver().
Reviewed-by: Ashutosh Dixit
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_ctx_thrash.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/i915/gem_ctx_thrash.c b/tests/i915/gem_ctx_thrash.c
> index d32619d5d..d9ddd6689 100644
> --- a/tests/i915/gem_ctx_thrash.c
> +++ b/tests/i915/gem_ctx_thrash.c
> @@ -250,7 +250,7 @@ static void processes(void)
> fds = malloc(num_ctx * sizeof(int));
> igt_assert(fds);
> for (unsigned n = 0; n < num_ctx; n++) {
> - fds[n] = drm_open_driver(DRIVER_INTEL);
> + fds[n] = gem_reopen_driver(fd);
> if (fds[n] == -1) {
> int err = errno;
> for (unsigned i = n; i--; )
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Re: [Intel-gfx] [PATCH] drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms
On 2020-11-03 at 17:06:42 -0500, Rodrigo Vivi wrote:
> On Fri, Oct 30, 2020 at 11:46:58AM +0530, Anshuman Gupta wrote:
> > From: Bob Paauwe
> >
> > The WA specifies that we need to toggle a SDE chicken bit on and then
> > off as the final step in preparation for s0ix entry.
> >
> > Bspec: 33450
> > Bspec: 8402
> >
> > However, something is happening after we toggle the bit that causes
> > the WA to be invalidated. This makes dispcnlunit1_cp_xosc_clkreq
> > active being already in s0ix state i.e SLP_S0 counter incremented.
> > Tweaking the Wa_14010685332 by setting the bit on suspend and clearing
> > it on resume turns down the dispcnlunit1_cp_xosc_clkreq.
> > B.Spec has Documented this tweaked sequence of WA as an alternative.
> > Let keep this tweaked WA for Gen11 platforms and keep untweaked WA for
> > other platforms which never observed this issue.
> >
> > v2 (MattR):
> > - Change the comment on the workaround to give PCH names rather than
> >platform names. Although the bspec is setup to list workarounds by
> >platform, the hardware team has confirmed that the actual issue being
> >worked around here is something that was introduced back in the
> >Cannon Lake PCH and carried forward to subsequent PCH's.
> > - Extend the untweaked version of the workaround to include PCH_CNP as
> >well. Note that since PCH_CNP is used to represent CMP, this will
> >apply on CML and some variants of RKL too.
> > - Cap the untweaked version of the workaround so that it won't apply to
> >"fake" PCH's (i.e., DG1). The issue we're working around really is
> >an issue in the PCH itself, not the South Display, so it shouldn't
> >apply when there isn't a real PCH.
> >
> > Cc: Rodrigo Vivi
> > Signed-off-by: Bob Paauwe
> > Signed-off-by: Anshuman Gupta
> > Signed-off-by: Matt Roper
> > ---
> > .../drm/i915/display/intel_display_power.c| 21 +--
> > drivers/gpu/drm/i915/i915_irq.c | 6 --
> > 2 files changed, 23 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 689922480661..d2a6518329d7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -5858,17 +5858,34 @@ static void intel_power_domains_verify_state(struct
> > drm_i915_private *i915)
> >
> > void intel_display_power_suspend_late(struct drm_i915_private *i915)
> > {
> > - if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915))
> > + u32 val;
> > +
> > + if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> > bxt_enable_dc9(i915);
> > - else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> > + /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > + if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> > PCH_MCC) {
> > + val = intel_de_read(i915, SOUTH_CHICKEN1);
> > + val |= SBCLK_RUN_REFCLK_DIS;
> > + intel_de_write(i915, SOUTH_CHICKEN1, val);
>
> could we use intel_de_rmw here?
May be i had misunderstod it earlier, i thought it was your recommendation
to use manual read, modify write without using intel_uncore_rmw(),
Was the actual idea to use intel_de_rmw flavour of API instead of
intel_uncore_rmw?
Also would it require to use at original Wa in gen11_display_irq_reset as well?
Thanks,
Anshuman Gupta.
>
> > + }
> > + } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> > hsw_enable_pc8(i915);
> > + }
> > }
> >
> > void intel_display_power_resume_early(struct drm_i915_private *i915)
> > {
> > + u32 val;
> > +
> > if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> > gen9_sanitize_dc_state(i915);
> > bxt_disable_dc9(i915);
> > + /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > + if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> > PCH_MCC) {
> > + val = intel_de_read(i915, SOUTH_CHICKEN1);
> > + val &= ~SBCLK_RUN_REFCLK_DIS;
> > + intel_de_write(i915, SOUTH_CHICKEN1, val);
>
> and here?
>
> sorry for not having spotted that sooner.
>
> > + }
> > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> > hsw_disable_pc8(i915);
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index dc33c96d741d..410c03624c6a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3055,8 +3055,10 @@ static void gen11_display_irq_reset(struct
> > drm_i915_private *dev_priv)
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE);
> >
> > - /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
> > - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
> > + /* Wa_14010685332:cnp/cmp,tgp,adp */
> > + if (INTEL_PCH_TYPE
Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with PSR2
On 2020-11-05 at 01:26:03 +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a5b072816a7b..32c411414908 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -799,6 +799,12 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc)
> struct intel_fbc *fbc = &dev_priv->fbc;
> struct intel_fbc_state_cache *cache = &fbc->state_cache;
>
> + if (dev_priv->psr.sink_psr2_support &&
> + IS_TIGERLAKE(dev_priv)) {
IMHO we need to use state boolean crtc_state->has_psr2, we can have sink
supports PSR2
but it may not be enabled due to any reason.
Thanks,
Anshuman Gupta.
> + fbc->no_fbc_reason = "not supported with PSR2";
> + return false;
> + }
> +
> if (!intel_fbc_can_enable(dev_priv))
> return false;
>
> --
> 2.26.2
>
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Re: [Intel-gfx] [PATCH v4 20/61] drm/i915: Rework clflush to work correctly without obj->mm.lock.
On 11/2/20 10:22 AM, Thomas Hellström wrote:
On 11/2/20 9:48 AM, Maarten Lankhorst wrote:
Op 30-10-2020 om 16:08 schreef Thomas Hellström:
On 10/16/20 12:44 PM, Maarten Lankhorst wrote:
Pin in the caller, not in the work itself. This should also
work better for dma-fence annotations.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index bc0223716906..daf9284ef1f5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -27,15 +27,8 @@ static void __do_clflush(struct
drm_i915_gem_object *obj)
static int clflush_work(struct dma_fence_work *base)
{
struct clflush *clflush = container_of(base,
typeof(*clflush), base);
- struct drm_i915_gem_object *obj = clflush->obj;
- int err;
- err = i915_gem_object_pin_pages(obj);
- if (err)
- return err;
-
- __do_clflush(obj);
- i915_gem_object_unpin_pages(obj);
+ __do_clflush(clflush->obj);
return 0;
}
@@ -44,6 +37,7 @@ static void clflush_release(struct dma_fence_work
*base)
{
struct clflush *clflush = container_of(base,
typeof(*clflush), base);
+ i915_gem_object_unpin_pages(clflush->obj);
Hmm, Could we do without pinning here? Pages present are protected
first by the object lock, then by the fence?
/Thomas
I felt the least chance of regressions was to copy the existing code. :)
At least until we have completed obj->mm.lock removal, we shouldn't
try to be smart with these kind of things.
Likely, we've already pinned the pages, so it's a simple ref increase.
Later on, we can try to be smart, but whenever I tried to change
behavior so far, I was forced to hunt down bugs.
OK, sounds good.
Reviewed-by: Thomas Hellström
/Thomas
~Maarten
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with PSR2
> -Original Message-
> From: Anshuman Gupta
> Sent: Thursday, November 5, 2020 12:12 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with
> PSR2
>
> On 2020-11-05 at 01:26:03 +0530, Uma Shankar wrote:
> > There are some corner cases wrt underrun when we enable FBC with PSR2
> > on TGL. Recommendation from hardware is to keep this combination
> > disabled.
> >
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a5b072816a7b..32c411414908 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -799,6 +799,12 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc)
> > struct intel_fbc *fbc = &dev_priv->fbc;
> > struct intel_fbc_state_cache *cache = &fbc->state_cache;
> >
> > + if (dev_priv->psr.sink_psr2_support &&
> > + IS_TIGERLAKE(dev_priv)) {
> IMHO we need to use state boolean crtc_state->has_psr2, we can have sink
> supports PSR2 but it may not be enabled due to any reason.
Yeah agree, will update this check. Thanks.
Regards,
Uma Shankar
> Thanks,
> Anshuman Gupta.
> > + fbc->no_fbc_reason = "not supported with PSR2";
> > + return false;
> > + }
> > +
> > if (!intel_fbc_can_enable(dev_priv))
> > return false;
> >
> > --
> > 2.26.2
> >
> > ___
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