[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev3)
URL   : https://patchwork.freedesktop.org/series/84039/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9364_full -> Patchwork_18947_full


Summary
---

  **SUCCESS**

  No regressions found.

  

New tests
-

  New tests have been introduced between CI_DRM_9364_full and 
Patchwork_18947_full:

### New CI tests (1) ###

  * boot:
- Statuses : 175 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18947_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][1] -> [SKIP][2] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb1/igt@gem_huc_c...@huc-copy.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
- shard-skl:  [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +6 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl9/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-skl8/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2598])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb8/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-tglb6/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html

  * igt@kms_flip@nonexisting-fb-interruptible@a-dp1:
- shard-apl:  [PASS][7] -> [DMESG-WARN][8] ([i915#1635] / 
[i915#1982]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-apl1/igt@kms_flip@nonexisting-fb-interrupti...@a-dp1.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-apl6/igt@kms_flip@nonexisting-fb-interrupti...@a-dp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl:  [PASS][9] -> [FAIL][10] ([i915#2122])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl9/igt@kms_flip@plain-flip-ts-check-interrupti...@c-edp1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-skl6/igt@kms_flip@plain-flip-ts-check-interrupti...@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-kbl:  [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-kbl3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_hdr@bpc-switch-suspend:
- shard-skl:  [PASS][13] -> [FAIL][14] ([i915#1188])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl8/igt@kms_...@bpc-switch-suspend.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-skl1/igt@kms_...@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl:  [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar 
issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_cpu.html

  * igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
- shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 
similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb1/igt@kms_universal_pl...@universal-plane-gen9-features-pipe-a.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-iclb7/igt@kms_universal_pl...@universal-plane-gen9-features-pipe-a.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- shard-iclb: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb8/igt@core_hotunp...@unbind-rebind.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/shard-iclb6/igt@core_hotunp...@unbind-rebind.html

  * igt@drm_mm@all@color_evict_range:
- shard-skl:  [INCOMPLETE][23] ([i915#198] / 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Plug IPS into intel_rps_set (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Plug IPS into intel_rps_set (rev2)
URL   : https://patchwork.freedesktop.org/series/84081/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9364_full -> Patchwork_18946_full


Summary
---

  **SUCCESS**

  No regressions found.

  

New tests
-

  New tests have been introduced between CI_DRM_9364_full and 
Patchwork_18946_full:

### New CI tests (1) ###

  * boot:
- Statuses : 175 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18946_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl:  [PASS][1] -> [FAIL][2] ([i915#1635] / [i915#2389])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-apl1/igt@gem_exec_reloc@basic-many-act...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-apl7/igt@gem_exec_reloc@basic-many-act...@rcs0.html

  * igt@gem_workarounds@suspend-resume:
- shard-skl:  [PASS][3] -> [INCOMPLETE][4] ([i915#198])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl2/igt@gem_workarou...@suspend-resume.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-skl1/igt@gem_workarou...@suspend-resume.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
- shard-skl:  [PASS][5] -> [FAIL][6] ([i915#54])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-128x128-onscreen.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-128x128-onscreen.html

  * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
- shard-skl:  [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +6 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl9/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-skl8/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled:
- shard-apl:  [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / 
[i915#1982]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-apl2/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-xtiled.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-apl3/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-xtiled.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
- shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb7/igt@kms_flip@basic-plain-f...@a-edp1.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-tglb8/igt@kms_flip@basic-plain-f...@a-edp1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-dp1:
- shard-kbl:  [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-kbl7/igt@kms_flip@flip-vs-absolute-wf_vbl...@a-dp1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-kbl6/igt@kms_flip@flip-vs-absolute-wf_vbl...@a-dp1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2598])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb8/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-tglb1/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible@a-hdmi-a1:
- shard-glk:  [PASS][17] -> [FAIL][18] ([i915#407])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-glk4/igt@kms_flip@modeset-vs-vblank-race-interrupti...@a-hdmi-a1.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-glk7/igt@kms_flip@modeset-vs-vblank-race-interrupti...@a-hdmi-a1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl:  [PASS][19] -> [FAIL][20] ([i915#2122])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl9/igt@kms_flip@plain-flip-ts-check-interrupti...@b-edp1.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-skl9/igt@kms_flip@plain-flip-ts-check-interrupti...@b-edp1.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
- shard-skl:  [PASS][21] -> [FAIL][22] ([i915#49])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl1/igt@kms_frontbuffer_track...@psr-rgb101010-draw-render.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/shard-skl7/igt@kms_frontbuffer_track...@psr-rgb101010-draw-render.html

  * 

[Intel-gfx] ✓ Fi.CI.IGT: success for Re-enable FBC on TGL (rev3)

[Patchwork]

== Series Details ==

Series: Re-enable FBC on TGL (rev3)
URL   : https://patchwork.freedesktop.org/series/83510/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9364_full -> Patchwork_18945_full


Summary
---

  **SUCCESS**

  No regressions found.

  

New tests
-

  New tests have been introduced between CI_DRM_9364_full and 
Patchwork_18945_full:

### New CI tests (1) ###

  * boot:
- Statuses : 175 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18945_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_whisper@basic-contexts-priority:
- shard-glk:  [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-glk6/igt@gem_exec_whis...@basic-contexts-priority.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-glk4/igt@gem_exec_whis...@basic-contexts-priority.html

  * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
- shard-skl:  [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +8 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl9/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl6/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- shard-apl:  [PASS][5] -> [DMESG-WARN][6] ([i915#1635] / 
[i915#1982]) +2 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-apl1/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-apl6/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
- shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-tglb7/igt@kms_flip@basic-plain-f...@a-edp1.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-tglb7/igt@kms_flip@basic-plain-f...@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-kbl:  [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-kbl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
- shard-skl:  [PASS][11] -> [FAIL][12] ([i915#49])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl1/igt@kms_frontbuffer_track...@psr-rgb101010-draw-render.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl8/igt@kms_frontbuffer_track...@psr-rgb101010-draw-render.html

  * igt@kms_plane@plane-panning-top-left-pipe-a-planes:
- shard-glk:  [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-glk1/igt@kms_pl...@plane-panning-top-left-pipe-a-planes.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-glk2/igt@kms_pl...@plane-panning-top-left-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl:  [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) 
+2 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-skl4/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-iclb3/igt@kms_psr@psr2_sprite_render.html

  * igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
- shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 
similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb1/igt@kms_universal_pl...@universal-plane-gen9-features-pipe-a.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/shard-iclb4/igt@kms_universal_pl...@universal-plane-gen9-features-pipe-a.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- shard-iclb: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/shard-iclb8/igt@core_hotunp...@unbind-rebind.html
   [22]: 

[Intel-gfx] ✗ Fi.CI.BUILD: failure for i915/gem_flink_race.c: Use statistics over list of numbers

[Patchwork]

== Series Details ==

Series: i915/gem_flink_race.c: Use statistics over list of numbers
URL   : https://patchwork.freedesktop.org/series/84084/
State : failure

== Summary ==

Applying: i915/gem_flink_race.c: Use statistics over list of numbers
error: sha1 information is lacking or useless (tests/i915/gem_flink_race.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 i915/gem_flink_race.c: Use statistics over list of numbers
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


___
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[Intel-gfx] [PATCH] i915/gem_flink_race.c: Use statistics over list of numbers

[Steve Hampson]

Print median and range instead of a list of numbers in function test_flink_name.

Signed-off-by: Steve Hampson 
---
 tests/i915/gem_flink_race.c | 18 +++---
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/tests/i915/gem_flink_race.c b/tests/i915/gem_flink_race.c
index cf07aedf1..04b7bd42c 100644
--- a/tests/i915/gem_flink_race.c
+++ b/tests/i915/gem_flink_race.c
@@ -83,14 +83,14 @@ static void test_flink_name(int timeout)
struct flink_name *threads;
int r, i, num_threads;
unsigned long count;
-   char buf[512];
void *status;
-   int len;
+   igt_stats_t s;
 
num_threads = sysconf(_SC_NPROCESSORS_ONLN) - 1;
if (!num_threads)
num_threads = 1;
 
+   igt_stats_init_with_size(, num_threads);
threads = calloc(num_threads, sizeof(*threads));
 
fd = drm_open_driver(DRIVER_INTEL);
@@ -114,19 +114,15 @@ static void test_flink_name(int timeout)
 
pls_die = 1;
 
-   len = snprintf(buf, sizeof(buf), "Completed %lu cycles with [", count);
+   igt_info("Completed %lu cycles\n", count);
for (i = 0;  i < num_threads; i++) {
pthread_join(threads[i].thread, );
igt_assert(status == 0);
-   /* Below, constant 11 is 8 digit number, comma, space and null 
byte */
-   if ((len + 11 + 1) < sizeof(buf))
-   len += snprintf(buf + len, sizeof(buf) - len, "%8lu, ", 
threads[i].count);
+   igt_stats_push(, threads[i].count);
}
-   /* Below, constant 9 is 7 bytes for terminating string plus \n and null 
byte */
-   if (len + 9 < sizeof(buf))
-   snprintf(buf + len - 2, sizeof(buf) - len + 2, "] races");
-   igt_info("%s\n", buf);
-
+   igt_info("Threads %d\n", num_threads);
+   igt_info("Range   %ld\n", igt_stats_get_range());
+   igt_info("Median  %g\n", igt_stats_get_median());
close(fd);
 }
 
-- 
2.21.0

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Re: [Intel-gfx] [PATCH v5] drm/i915/rkl: new rkl ddc map for different PCH

[Lee, Shawn C]

On Thu, Nov. 19, 2020 at 11:51 PM, Matt Roper wrote:
>On Tue, Nov 17, 2020 at 10:26:29PM +0800, Lee Shawn C wrote:
>> After boot into kernel. Driver configured ddc pin mapping based on 
>> predefined table in parse_ddi_port(). Now driver configure rkl ddc pin 
>> mapping depends on icp_ddc_pin_map[]. Then this table will give 
>> incorrect gmbus port number to cause HDMI can't work.
>> 
>> Refer to commit cd0a89527d06 ("drm/i915/rkl: Add DDC pin mapping").
>> Create two ddc pin table for rkl TGP and CMP pch. Then HDMI can works 
>> properly on rkl.
>> 
>> v2: update patch based on latest dinq branch.
>> v3: update ddc table for RKL+TGP sku.
>> RKL+CNP sku will load cnp_ddc_pin_map[] setting.
>> v4: modify the if/else judgment to avoid nesting.
>> v5: fix typo in v4.
>> 
>> Cc: Matt Roper 
>> Cc: Aditya Swarup 
>> Cc: Anusha Srivatsa 
>> Cc: Jani Nikula 
>> Cc: Cooper Chiou 
>> Cc: Khaled Almahallawy 
>> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2577
>> Signed-off-by: Lee Shawn C 
>
>Reviewed-by: Matt Roper 
>
>Do you plan to follow up with a separate patch to fix the CMP handling in 
>rkl_port_to_ddc_pin that I mentioned previously?  I want to make sure that 
>part doesn't fall through the cracks.
>

Do you mean the modification like this in rkl_port_to_ddc_pin()? If so, I will 
commit a separate patch to fix it later.

return GMBUS_PIN_1_BXT + phy - 1;

Best regards,
Shawn

>
>Matt
>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bios.c | 10 ++
>>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  2 ++
>>  2 files changed, 12 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
>> b/drivers/gpu/drm/i915/display/intel_bios.c
>> index 4cc949b228f2..cf2fba490b7b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> @@ -1623,6 +1623,13 @@ static const u8 icp_ddc_pin_map[] = {
>>  [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,  };
>>  
>> +static const u8 rkl_pch_tgp_ddc_pin_map[] = {
>> +[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
>> +[ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
>> +[RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,
>> +[RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, };
>> +
>>  static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)  
>> {
>>  const u8 *ddc_pin_map;
>> @@ -1630,6 +1637,9 @@ static u8 map_ddc_pin(struct drm_i915_private 
>> *dev_priv, u8 vbt_pin)
>>  
>>  if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
>>  return vbt_pin;
>> +} else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == 
>> PCH_TGP) {
>> +ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
>> +n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
>>  } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
>>  ddc_pin_map = icp_ddc_pin_map;
>>  n_entries = ARRAY_SIZE(icp_ddc_pin_map); diff --git 
>> a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
>> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> index 49b4b5fca941..187ec573de59 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> @@ -319,6 +319,8 @@ enum vbt_gmbus_ddi {
>>  ICL_DDC_BUS_DDI_A = 0x1,
>>  ICL_DDC_BUS_DDI_B,
>>  TGL_DDC_BUS_DDI_C,
>> +RKL_DDC_BUS_DDI_D = 0x3,
>> +RKL_DDC_BUS_DDI_E,
>>  ICL_DDC_BUS_PORT_1 = 0x4,
>>  ICL_DDC_BUS_PORT_2,
>>  ICL_DDC_BUS_PORT_3,
>> --
>> 2.17.1
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev3)
URL   : https://patchwork.freedesktop.org/series/84039/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9364 -> Patchwork_18947


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/index.html

New tests
-

  New tests have been introduced between CI_DRM_9364 and Patchwork_18947:

### New CI tests (1) ###

  * boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18947 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot (NEW):
- {fi-tgl-dsi}:   [FAIL][1] ([i915#2448]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-dsi/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-tgl-dsi/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@kms_busy@basic@flip:
- fi-kbl-soraka:  [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@kms_busy@ba...@flip.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-tgl-y/igt@kms_busy@ba...@flip.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +2 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@i915_module_load@reload:
- fi-icl-y:   [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-icl-y/igt@i915_module_l...@reload.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-icl-y/igt@i915_module_l...@reload.html

  * igt@kms_busy@basic@flip:
- {fi-kbl-7560u}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-7560u/igt@kms_busy@ba...@flip.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-kbl-7560u/igt@kms_busy@ba...@flip.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2:  [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html

  * igt@kms_psr@cursor_plane_move:
- fi-tgl-y:   [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@kms_psr@cursor_plane_move.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-tgl-y/igt@kms_psr@cursor_plane_move.html

  
 Warnings 

  * igt@runner@aborted:
- fi-kbl-8809g:   [FAIL][19] ([i915#1186] / [i915#1784] / [i915#2426] / 
[i915#2439]) -> [FAIL][20] ([i915#1186] / [i915#2426])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-8809g/igt@run...@aborted.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18947/fi-kbl-8809g/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1186]: https://gitlab.freedesktop.org/drm/intel/issues/1186
  [i915#1784]: https://gitlab.freedesktop.org/drm/intel/issues/1784
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2448]: https://gitlab.freedesktop.org/drm/intel/issues/2448
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [k.org#204565]: https://bugzilla.kernel.org/show_bug.cgi?id=204565


Participating hosts (43 -> 

Re: [Intel-gfx] [PATCH 11/21] drm/i915/adl_s: Add adl-s ddc pin mapping

[Matt Roper]

On Tue, Nov 17, 2020 at 10:50:19AM -0800, Aditya Swarup wrote:
> ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
> Combo PHY A still uses the old ddc pin mapping.
> 
> From VBT, ddc pin info suggests the following mapping:
> VBT  DRIVER
> DDI B->ddc_pin=2 should translate to PORT_D->0x9
> DDI C->ddc_pin=3 should translate to PORT_E->0xa
> DDI D->ddc_pin=4 should translate to PORT_F->0xb
> DDI E->ddc_pin=5 should translate to PORT_G->0xc
> 
> Adding pin map to facilitate this translation as we cannot use existing
> icl ddc pin map due to conflict with DDI B and DDI C info.
> 
> Bspec:20124
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Cc: Matt Roper 
> Cc: Lucas De Marchi 
> Signed-off-by: Aditya Swarup 
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 13 +++-
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  4 
>  3 files changed, 35 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..716a15f87632 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = {
>   [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
>  };
>  
> +static const u8 adls_ddc_pin_map[] = {
> + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> + [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
> + [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
> + [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
> + [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
> +};
> +
>  static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
>  {
>   const u8 *ddc_pin_map;
>   int n_entries;
>  
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
> + if (IS_ALDERLAKE_S(dev_priv)) {

As I mentioned on an earlier patch, these kind of conditions should
probably just be HAS_PCH_ADP().

It's possible that in the future we'll run into a pairing of ADP with a
different GPU that should be handled in a special manner (like we have
with RKL+TGP differing from TGL+TGP), but the first platform should
still stay the "default" for conditions if that happens.

Alternatively if we wind up with another variant of ADP in the future
that behaves differently in general, then presumably it would also have
a different device ID and we could just treat them separately as
HAS_PCH_ADP_S() vs HAS_PCH_ADP_X() or whatever.

But we can cross that bridge if/when we get to it.  For now it's
probably cleanest to just make this condition (and others like it later)
be HAS_PCH_ADP().


Matt

> + ddc_pin_map = adls_ddc_pin_map;
> + n_entries = ARRAY_SIZE(adls_ddc_pin_map);
> + } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
>   return vbt_pin;
>   } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
>   ddc_pin_map = icp_ddc_pin_map;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..8fdf0623d663 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3145,6 +3145,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private 
> *dev_priv, enum port port)
>   return intel_port_to_phy(dev_priv, port) + 1;
>  }
>  
> +static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port 
> port)
> +{
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> + WARN_ON(port == PORT_B || port == PORT_C);
> +
> + /*
> +  * Pin mapping for ADL-S requires TC pins for all combo phy outputs
> +  * except first combo output.
> +  */
> + if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B)
> + return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
> +
> + return GMBUS_PIN_1_BXT + phy;
> +}
> +
>  static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
> enum port port)
>  {
> @@ -3182,7 +3198,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder 
> *encoder)
>   return ddc_pin;
>   }
>  
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> + if (IS_ALDERLAKE_S(dev_priv))
> + ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>   ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
>   else if (IS_ROCKETLAKE(dev_priv))
>   ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 49b4b5fca941..32d1b4f05760 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -325,6 +325,10 @@ enum vbt_gmbus_ddi {
>   ICL_DDC_BUS_PORT_4,
>   TGL_DDC_BUS_PORT_5,
>   TGL_DDC_BUS_PORT_6,
> +  

Re: [Intel-gfx] [PATCH 10/21] drm/i915/adl_s: Add HTI support and initialize display for ADL-S

[Matt Roper]

On Tue, Nov 17, 2020 at 10:50:18AM -0800, Aditya Swarup wrote:
> Initialize display outputs and add HTI support for ADL-S. ADL-S has 5
> display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
> 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Cc: Matt Roper 
> Cc: Lucas De Marchi 
> Signed-off-by: Aditya Swarup 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 +++-
>  drivers/gpu/drm/i915/i915_pci.c  | 1 +
>  drivers/gpu/drm/i915/i915_reg.h  | 2 +-
>  3 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index dcb70efbfa3b..db8ba5e297ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17261,7 +17261,13 @@ static void intel_setup_outputs(struct 
> drm_i915_private *dev_priv)
>   if (!HAS_DISPLAY(dev_priv))
>   return;
>  
> - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
> + if (IS_ALDERLAKE_S(dev_priv)) {
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_D);   /* DDI TC1 */
> + intel_ddi_init(dev_priv, PORT_E);   /* DDI TC2 */
> + intel_ddi_init(dev_priv, PORT_F);   /* DDI TC3 */
> + intel_ddi_init(dev_priv, PORT_G);   /* DDI TC4 */
> + } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
>   intel_ddi_init(dev_priv, PORT_A);
>   intel_ddi_init(dev_priv, PORT_B);
>   intel_ddi_init(dev_priv, PORT_TC1);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 069ac0c28bb3..26e4bf8bb4ef 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -930,6 +930,7 @@ static const struct intel_device_info adl_s_info = {
>   PLATFORM(INTEL_ALDERLAKE_S),
>   .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>   .require_force_probe = 1,
> + .display.has_hti = 1,
>   .display.has_psr_hw_tracking = 0,
>   .platform_engine_mask =
>   BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),

This part should probably just go in the patch that added the initial
platform definition.

> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5416d04373ae..4c8d0d84af6a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2928,7 +2928,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
>  
>  #define HDPORT_STATE _MMIO(0x45050)
> -#define   HDPORT_DPLL_USED_MASK  REG_GENMASK(14, 12)
> +#define   HDPORT_DPLL_USED_MASK  REG_GENMASK(15, 12)

This doesn't seem like it belongs in this patch.  The DPLL patch might
be a better match for it?


Matt

>  #define   HDPORT_PHY_USED_DP(phy)REG_BIT(2 * (phy) + 2)
>  #define   HDPORT_PHY_USED_HDMI(phy)  REG_BIT(2 * (phy) + 1)
>  #define   HDPORT_ENABLED REG_BIT(0)
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Plug IPS into intel_rps_set (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Plug IPS into intel_rps_set (rev2)
URL   : https://patchwork.freedesktop.org/series/84081/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9364 -> Patchwork_18946


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/index.html

New tests
-

  New tests have been introduced between CI_DRM_9364 and Patchwork_18946:

### New CI tests (1) ###

  * boot:
- Statuses : 1 fail(s) 39 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18946 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([i915#2675] / 
[i915#541])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#1635])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html

  * igt@prime_vgem@basic-read:
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#402])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@prime_v...@basic-read.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/fi-tgl-y/igt@prime_v...@basic-read.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@i915_module_load@reload:
- fi-icl-y:   [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-icl-y/igt@i915_module_l...@reload.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/fi-icl-y/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka:   [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@kms_psr@cursor_plane_move:
- fi-tgl-y:   [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@kms_psr@cursor_plane_move.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/fi-tgl-y/igt@kms_psr@cursor_plane_move.html

  
 Warnings 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [DMESG-WARN][15] ([i915#2411]) -> [DMESG-WARN][16] 
([i915#2411] / [i915#402])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@runner@aborted:
- fi-kbl-8809g:   [FAIL][17] ([i915#1186] / [i915#1784] / [i915#2426] / 
[i915#2439]) -> [FAIL][18] ([i915#1186] / [i915#2426])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-8809g/igt@run...@aborted.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18946/fi-kbl-8809g/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1186]: https://gitlab.freedesktop.org/drm/intel/issues/1186
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1784]: https://gitlab.freedesktop.org/drm/intel/issues/1784
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2675]: https://gitlab.freedesktop.org/drm/intel/issues/2675
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [k.org#204565]: https://bugzilla.kernel.org/show_bug.cgi?id=204565


Participating hosts (43 -> 40)
--

  Additional (1): fi-bxt-dsi 
  Missing(4): fi-ilk-m540 fi-bsw-cyan 

Re: [Intel-gfx] [PATCH 07/21] drm/i915/adl_s: Add PHYs for Alderlake S

[Matt Roper]

On Tue, Nov 17, 2020 at 10:50:15AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa 
> 
> Alderlake-S has 5 combo phys, add reg definitions for
> combo phys and update the port to phy helper for ADL-S.
> 
> Cc: Lucas De Marchi 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Cc: Matt Roper 
> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Aditya Swarup 
> Reviewed-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
>  drivers/gpu/drm/i915/i915_reg.h  | 5 -
>  2 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e8874cd22abf..848bcd83b15f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7343,6 +7343,8 @@ bool intel_phy_is_combo(struct drm_i915_private 
> *dev_priv, enum phy phy)
>  {
>   if (phy == PHY_NONE)
>   return false;
> + else if (IS_ALDERLAKE_S(dev_priv))
> + return phy <= PHY_E;
>   else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
>   return phy <= PHY_D;
>   else if (IS_JSL_EHL(dev_priv))
> @@ -7355,7 +7357,8 @@ bool intel_phy_is_combo(struct drm_i915_private 
> *dev_priv, enum phy phy)
>  
>  bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  {
> - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) ||
> + IS_ROCKETLAKE(dev_priv))
>   return false;
>   else if (INTEL_GEN(dev_priv) >= 12)
>   return phy >= PHY_D && phy <= PHY_I;

Since ICL/TGL are the exception rather than the rule for actually having
Type-C ports, it might make more sense to just flip this around and have

if (TGL)
...
else if (ICL)
...
else
return false;


Matt

> @@ -7367,7 +7370,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, 
> enum phy phy)
>  
>  enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>  {
> - if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
> + if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
> + return PHY_B + port - PORT_TC1;
> + else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
>   return PHY_C + port - PORT_TC1;
>   else if (IS_JSL_EHL(i915) && port == PORT_D)
>   return PHY_A;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7ea70b7ffcc6..402ea8cd602b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1872,10 +1872,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _ICL_COMBOPHY_B  0x6C000
>  #define _EHL_COMBOPHY_C  0x16
>  #define _RKL_COMBOPHY_D  0x161000
> +#define _ADL_COMBOPHY_E  0x16B000
> +
>  #define _ICL_COMBOPHY(phy)   _PICK(phy, _ICL_COMBOPHY_A, \
> _ICL_COMBOPHY_B, \
> _EHL_COMBOPHY_C, \
> -   _RKL_COMBOPHY_D)
> +   _RKL_COMBOPHY_D, \
> +   _ADL_COMBOPHY_E)
>  
>  /* CNL/ICL Port CL_DW registers */
>  #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> -- 
> 2.27.0
> 

-- 
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VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 06/21] drm/i915/adl_s: Add Interrupt Support

[Matt Roper]

On Tue, Nov 17, 2020 at 10:50:14AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa 
> 
> ADLS follows ICP/TGP like interrupts.
> 
> v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas)
> 
> Cc: Lucas De Marchi 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Cc: Matt Roper 
> Cc: José Roberto de Souza 
> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Lucas De Marchi 
> Signed-off-by: Aditya Swarup 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dc6febc63f1c..758ed4f6c9f3 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -191,8 +191,7 @@ static void intel_hpd_init_pins(struct drm_i915_private 
> *dev_priv)
>  
>   if (HAS_PCH_DG1(dev_priv))
>   hpd->pch_hpd = hpd_sde_dg1;
> - else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
> -  HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>   hpd->pch_hpd = hpd_icp;
>   else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
>   hpd->pch_hpd = hpd_spt;
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 05/21] drm/i915/adl_s: Add PCH support

[Matt Roper]

On Tue, Nov 17, 2020 at 10:50:13AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa 
> 
> Add support for Alderpoint(ADP) PCH used with Alderlake-S.
> 
> v2:
> - Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)
> 

This patch looks okay, so

Reviewed-by: Matt Roper 

but I'll have some comments on later patches which are basing south
display conditions on a check for ADL-S rather than a check for ADP.
Even if we anticipate future platforms re-using ADP and needing
different logic in those areas (like we do with TGP when paired with
RKL), I think we might want to handle that differently if/when the time
comes.


Matt

> Cc: Matt Roper 
> Cc: Lucas De Marchi 
> Cc: Caz Yokoyama 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Aditya Swarup 
> ---
>  drivers/gpu/drm/i915/intel_pch.c | 8 +++-
>  drivers/gpu/drm/i915/intel_pch.h | 3 +++
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pch.c 
> b/drivers/gpu/drm/i915/intel_pch.c
> index f31c0dabd0cc..2a6d70f247e8 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, 
> unsigned short id)
>   drm_dbg_kms(_priv->drm, "Found Jasper Lake PCH\n");
>   drm_WARN_ON(_priv->drm, !IS_JSL_EHL(dev_priv));
>   return PCH_JSP;
> + case INTEL_PCH_ADP_DEVICE_ID_TYPE:
> + drm_dbg_kms(_priv->drm, "Found Alder Lake PCH\n");
> + drm_WARN_ON(_priv->drm, !IS_ALDERLAKE_S(dev_priv));
> + return PCH_ADP;
>   default:
>   return PCH_NONE;
>   }
> @@ -155,7 +159,9 @@ intel_virt_detect_pch(const struct drm_i915_private 
> *dev_priv)
>* make an educated guess as to which PCH is really there.
>*/
>  
> - if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv))
> + id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
> + else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
>   id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
>   else if (IS_JSL_EHL(dev_priv))
>   id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
> diff --git a/drivers/gpu/drm/i915/intel_pch.h 
> b/drivers/gpu/drm/i915/intel_pch.h
> index 06d2cd50af0b..7318377503b0 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -26,6 +26,7 @@ enum intel_pch {
>   PCH_JSP,/* Jasper Lake PCH */
>   PCH_MCC,/* Mule Creek Canyon PCH */
>   PCH_TGP,/* Tiger Lake PCH */
> + PCH_ADP,/* Alder Lake PCH */
>  
>   /* Fake PCHs, functionality handled on the same PCI dev */
>   PCH_DG1 = 1024,
> @@ -53,12 +54,14 @@ enum intel_pch {
>  #define INTEL_PCH_TGP2_DEVICE_ID_TYPE0x4380
>  #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
>  #define INTEL_PCH_JSP2_DEVICE_ID_TYPE0x3880
> +#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
>  #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
>  #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
>  #define INTEL_PCH_QEMU_DEVICE_ID_TYPE0x2900 /* qemu q35 has 
> 2918 */
>  
>  #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
>  #define INTEL_PCH_ID(dev_priv)   ((dev_priv)->pch_id)
> +#define HAS_PCH_ADP(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
>  #define HAS_PCH_DG1(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
>  #define HAS_PCH_JSP(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
>  #define HAS_PCH_MCC(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
> -- 
> 2.27.0
> 

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
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Re: [Intel-gfx] [PATCH v5] drm/i915/rkl: new rkl ddc map for different PCH

[Matt Roper]

On Tue, Nov 17, 2020 at 10:26:29PM +0800, Lee Shawn C wrote:
> After boot into kernel. Driver configured ddc pin mapping based on
> predefined table in parse_ddi_port(). Now driver configure rkl
> ddc pin mapping depends on icp_ddc_pin_map[]. Then this table will
> give incorrect gmbus port number to cause HDMI can't work.
> 
> Refer to commit cd0a89527d06 ("drm/i915/rkl: Add DDC pin mapping").
> Create two ddc pin table for rkl TGP and CMP pch. Then HDMI can
> works properly on rkl.
> 
> v2: update patch based on latest dinq branch.
> v3: update ddc table for RKL+TGP sku.
> RKL+CNP sku will load cnp_ddc_pin_map[] setting.
> v4: modify the if/else judgment to avoid nesting.
> v5: fix typo in v4.
> 
> Cc: Matt Roper 
> Cc: Aditya Swarup 
> Cc: Anusha Srivatsa 
> Cc: Jani Nikula 
> Cc: Cooper Chiou 
> Cc: Khaled Almahallawy 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2577
> Signed-off-by: Lee Shawn C 

Reviewed-by: Matt Roper 

Do you plan to follow up with a separate patch to fix the CMP handling
in rkl_port_to_ddc_pin that I mentioned previously?  I want to make sure
that part doesn't fall through the cracks.


Matt

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 10 ++
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  2 ++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..cf2fba490b7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1623,6 +1623,13 @@ static const u8 icp_ddc_pin_map[] = {
>   [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
>  };
>  
> +static const u8 rkl_pch_tgp_ddc_pin_map[] = {
> + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> + [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
> + [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,
> + [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
> +};
> +
>  static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
>  {
>   const u8 *ddc_pin_map;
> @@ -1630,6 +1637,9 @@ static u8 map_ddc_pin(struct drm_i915_private 
> *dev_priv, u8 vbt_pin)
>  
>   if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
>   return vbt_pin;
> + } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == 
> PCH_TGP) {
> + ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
> + n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
>   } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
>   ddc_pin_map = icp_ddc_pin_map;
>   n_entries = ARRAY_SIZE(icp_ddc_pin_map);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 49b4b5fca941..187ec573de59 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -319,6 +319,8 @@ enum vbt_gmbus_ddi {
>   ICL_DDC_BUS_DDI_A = 0x1,
>   ICL_DDC_BUS_DDI_B,
>   TGL_DDC_BUS_DDI_C,
> + RKL_DDC_BUS_DDI_D = 0x3,
> + RKL_DDC_BUS_DDI_E,
>   ICL_DDC_BUS_PORT_1 = 0x4,
>   ICL_DDC_BUS_PORT_2,
>   ICL_DDC_BUS_PORT_3,
> -- 
> 2.17.1
> 

-- 
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Intel Corporation
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[Intel-gfx] ✓ Fi.CI.BAT: success for Re-enable FBC on TGL (rev3)

[Patchwork]

== Series Details ==

Series: Re-enable FBC on TGL (rev3)
URL   : https://patchwork.freedesktop.org/series/83510/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9364 -> Patchwork_18945


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/index.html

New tests
-

  New tests have been introduced between CI_DRM_9364 and Patchwork_18945:

### New CI tests (1) ###

  * boot:
- Statuses : 1 fail(s) 38 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18945 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_parallel@engines@fds:
- fi-icl-u2:  [PASS][1] -> [INCOMPLETE][2] ([i915#2295])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-icl-u2/igt@gem_exec_parallel@engi...@fds.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-icl-u2/igt@gem_exec_parallel@engi...@fds.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900:   [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
- fi-apl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1635] / 
[i915#1982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-soraka:  [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-soraka/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-kbl-soraka/igt@i915_pm_...@module-reload.html

  * igt@kms_busy@basic@flip:
- fi-tgl-y:   [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@kms_busy@ba...@flip.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@kms_busy@ba...@flip.html

  * igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y:   [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +2 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +2 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka:   [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
- {fi-kbl-7560u}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-7560u/igt@kms_busy@ba...@flip.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-kbl-7560u/igt@kms_busy@ba...@flip.html

  * igt@kms_psr@cursor_plane_move:
- fi-tgl-y:   [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@kms_psr@cursor_plane_move.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@kms_psr@cursor_plane_move.html

  
 Warnings 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-y:   [DMESG-WARN][21] ([i915#2411]) -> [DMESG-WARN][22] 
([i915#1982] / [i915#2411])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@runner@aborted:
- fi-kbl-8809g:   [FAIL][23] ([i915#1186] / [i915#1784] / [i915#2426] / 
[i915#2439]) -> [FAIL][24] ([i915#1186] / [i915#2426] / [i915#2439])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9364/fi-kbl-8809g/igt@run...@aborted.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18945/fi-kbl-8809g/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the 

Re: [Intel-gfx] [PATCH v3] drm/i915: Do not call hsw_set_frame_start_delay for dsi

[Matt Roper]

On Thu, Nov 19, 2020 at 03:26:15PM -0800, Manasi Navare wrote:
> This should fix the boot oops for dsi
> 
> v2:
> * Fix indent (Manasi)
> v3:
> * Remove redundant condition (Matt Roper)
> 
> Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for 
> bigjoiner")
> Signed-off-by: Manasi Navare 

Looks like the right change; the old condition didn't make sense since
it would always be true.

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1a0f00f37ca9..0038f14c8bfb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7211,12 +7211,10 @@ static void hsw_crtc_enable(struct intel_atomic_state 
> *state,
>   if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>   bdw_set_pipemisc(new_crtc_state);
>  
> - if (!new_crtc_state->bigjoiner_slave || 
> !transcoder_is_dsi(cpu_transcoder)) {
> - if (!transcoder_is_dsi(cpu_transcoder))
> - intel_set_transcoder_timings(new_crtc_state);
> + if (!new_crtc_state->bigjoiner_slave && 
> !transcoder_is_dsi(cpu_transcoder)) {
> + intel_set_transcoder_timings(new_crtc_state);
>  
> - if (cpu_transcoder != TRANSCODER_EDP &&
> - !transcoder_is_dsi(cpu_transcoder))
> + if (cpu_transcoder != TRANSCODER_EDP)
>   intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
>  new_crtc_state->pixel_multiplier - 1);
>  
> -- 
> 2.19.1
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH v3] drm/i915: Do not call hsw_set_frame_start_delay for dsi

[Manasi Navare]

This should fix the boot oops for dsi

v2:
* Fix indent (Manasi)
v3:
* Remove redundant condition (Matt Roper)

Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for 
bigjoiner")
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 1a0f00f37ca9..0038f14c8bfb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7211,12 +7211,10 @@ static void hsw_crtc_enable(struct intel_atomic_state 
*state,
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
 
-   if (!new_crtc_state->bigjoiner_slave || 
!transcoder_is_dsi(cpu_transcoder)) {
-   if (!transcoder_is_dsi(cpu_transcoder))
-   intel_set_transcoder_timings(new_crtc_state);
+   if (!new_crtc_state->bigjoiner_slave && 
!transcoder_is_dsi(cpu_transcoder)) {
+   intel_set_transcoder_timings(new_crtc_state);
 
-   if (cpu_transcoder != TRANSCODER_EDP &&
-   !transcoder_is_dsi(cpu_transcoder))
+   if (cpu_transcoder != TRANSCODER_EDP)
intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
   new_crtc_state->pixel_multiplier - 1);
 
-- 
2.19.1

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Re: [Intel-gfx] [PATCH v2] drm/i915: Do not call hsw_set_frame_start_delay for dsi

[Matt Roper]

On Thu, Nov 19, 2020 at 10:20:57AM -0800, Manasi Navare wrote:
> This should fix the boot oops for dsi
> 
> v2:
> * Fix indent (Manasi)
> 
> Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for 
> bigjoiner")
> Signed-off-by: Manasi Navare 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5c07c74d4397..cbbe92d47e11 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7211,7 +7211,7 @@ static void hsw_crtc_enable(struct intel_atomic_state 
> *state,
>   if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>   bdw_set_pipemisc(new_crtc_state);
>  
> - if (!new_crtc_state->bigjoiner_slave || 
> !transcoder_is_dsi(cpu_transcoder)) {
> + if (!new_crtc_state->bigjoiner_slave && 
> !transcoder_is_dsi(cpu_transcoder)) {
>   if (!transcoder_is_dsi(cpu_transcoder))

This check is now redundant (always true), right?  I think there's
another nested check for transcoder_is_dsi() inside this block too
(below the context lines shown by this patch).


Matt

>   intel_set_transcoder_timings(new_crtc_state);
>  
> -- 
> 2.19.1
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH] drm/i915/gt: Plug IPS into intel_rps_set

[Chris Wilson]

The old IPS interface did not match the RPS interface that we tried to
plug it into (bool vs int return). Once repaired, our minimal
selftesting is finally happy!

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/intel_rps.c | 34 +++--
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 0d88f17799ff..b13e7845d483 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -400,7 +400,7 @@ static unsigned int gen5_invert_freq(struct intel_rps *rps,
return val;
 }
 
-static bool gen5_rps_set(struct intel_rps *rps, u8 val)
+static int __gen5_rps_set(struct intel_rps *rps, u8 val)
 {
struct intel_uncore *uncore = rps_to_uncore(rps);
u16 rgvswctl;
@@ -410,7 +410,7 @@ static bool gen5_rps_set(struct intel_rps *rps, u8 val)
rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
if (rgvswctl & MEMCTL_CMD_STS) {
DRM_DEBUG("gpu busy, RCS change rejected\n");
-   return false; /* still busy with another command */
+   return -EBUSY; /* still busy with another command */
}
 
/* Invert the frequency bin into an ips delay */
@@ -426,7 +426,18 @@ static bool gen5_rps_set(struct intel_rps *rps, u8 val)
rgvswctl |= MEMCTL_CMD_STS;
intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
 
-   return true;
+   return 0;
+}
+
+static int gen5_rps_set(struct intel_rps *rps, u8 val)
+{
+   int err;
+
+   spin_lock_irq(_lock);
+   err = __gen5_rps_set(rps, val);
+   spin_unlock_irq(_lock);
+
+   return err;
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
@@ -557,7 +568,7 @@ static bool gen5_rps_enable(struct intel_rps *rps)
"stuck trying to change perf mode\n");
mdelay(1);
 
-   gen5_rps_set(rps, rps->cur_freq);
+   __gen5_rps_set(rps, rps->cur_freq);
 
rps->ips.last_count1 = intel_uncore_read(uncore, DMIEC);
rps->ips.last_count1 += intel_uncore_read(uncore, DDREC);
@@ -599,7 +610,7 @@ static void gen5_rps_disable(struct intel_rps *rps)
intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
 
/* Go back to the starting frequency */
-   gen5_rps_set(rps, rps->idle_freq);
+   __gen5_rps_set(rps, rps->idle_freq);
mdelay(1);
rgvswctl |= MEMCTL_CMD_STS;
intel_uncore_write(uncore, MEMSWCTL, rgvswctl);
@@ -797,20 +808,19 @@ static int rps_set(struct intel_rps *rps, u8 val, bool 
update)
struct drm_i915_private *i915 = rps_to_i915(rps);
int err;
 
-   if (INTEL_GEN(i915) < 6)
-   return 0;
-
if (val == rps->last_freq)
return 0;
 
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_rps_set(rps, val);
-   else
+   else if (INTEL_GEN(i915) >= 6)
err = gen6_rps_set(rps, val);
+   else
+   err = gen5_rps_set(rps, val);
if (err)
return err;
 
-   if (update)
+   if (update && INTEL_GEN(i915) >= 6)
gen6_rps_set_thresholds(rps, val);
rps->last_freq = val;
 
@@ -1794,7 +1804,7 @@ void gen5_rps_irq_handler(struct intel_rps *rps)
 rps->min_freq_softlimit,
 rps->max_freq_softlimit);
 
-   if (new_freq != rps->cur_freq && gen5_rps_set(rps, new_freq))
+   if (new_freq != rps->cur_freq && !__gen5_rps_set(rps, new_freq))
rps->cur_freq = new_freq;
 
spin_unlock(_lock);
@@ -2105,7 +2115,7 @@ bool i915_gpu_turbo_disable(void)
 
spin_lock_irq(_lock);
rps->max_freq_softlimit = rps->min_freq;
-   ret = gen5_rps_set(>gt.rps, rps->min_freq);
+   ret = !__gen5_rps_set(>gt.rps, rps->min_freq);
spin_unlock_irq(_lock);
 
drm_dev_put(>drm);
-- 
2.20.1

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[Intel-gfx] [PATCH] drm/i915/gt: Plug IPS into intel_rps_set

[Chris Wilson]

The old IPS interface did not match the RPS interface that we tried to
plug it into (bool vs int return). Once repaired, our minimal
selftesting is finally happy!

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/intel_rps.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 0d88f17799ff..9785fdc088ce 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -400,7 +400,7 @@ static unsigned int gen5_invert_freq(struct intel_rps *rps,
return val;
 }
 
-static bool gen5_rps_set(struct intel_rps *rps, u8 val)
+static int gen5_rps_set(struct intel_rps *rps, u8 val)
 {
struct intel_uncore *uncore = rps_to_uncore(rps);
u16 rgvswctl;
@@ -410,7 +410,7 @@ static bool gen5_rps_set(struct intel_rps *rps, u8 val)
rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
if (rgvswctl & MEMCTL_CMD_STS) {
DRM_DEBUG("gpu busy, RCS change rejected\n");
-   return false; /* still busy with another command */
+   return -EBUSY; /* still busy with another command */
}
 
/* Invert the frequency bin into an ips delay */
@@ -426,7 +426,7 @@ static bool gen5_rps_set(struct intel_rps *rps, u8 val)
rgvswctl |= MEMCTL_CMD_STS;
intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
 
-   return true;
+   return 0;
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
@@ -797,7 +797,7 @@ static int rps_set(struct intel_rps *rps, u8 val, bool 
update)
struct drm_i915_private *i915 = rps_to_i915(rps);
int err;
 
-   if (INTEL_GEN(i915) < 6)
+   if (INTEL_GEN(i915) < 5)
return 0;
 
if (val == rps->last_freq)
@@ -805,12 +805,14 @@ static int rps_set(struct intel_rps *rps, u8 val, bool 
update)
 
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_rps_set(rps, val);
-   else
+   else if (INTEL_GEN(i915) >= 6)
err = gen6_rps_set(rps, val);
+   else
+   err = gen5_rps_set(rps, val);
if (err)
return err;
 
-   if (update)
+   if (update && INTEL_GEN(i915) >= 6)
gen6_rps_set_thresholds(rps, val);
rps->last_freq = val;
 
@@ -1794,7 +1796,7 @@ void gen5_rps_irq_handler(struct intel_rps *rps)
 rps->min_freq_softlimit,
 rps->max_freq_softlimit);
 
-   if (new_freq != rps->cur_freq && gen5_rps_set(rps, new_freq))
+   if (new_freq != rps->cur_freq && !gen5_rps_set(rps, new_freq))
rps->cur_freq = new_freq;
 
spin_unlock(_lock);
@@ -2105,7 +2107,7 @@ bool i915_gpu_turbo_disable(void)
 
spin_lock_irq(_lock);
rps->max_freq_softlimit = rps->min_freq;
-   ret = gen5_rps_set(>gt.rps, rps->min_freq);
+   ret = !gen5_rps_set(>gt.rps, rps->min_freq);
spin_unlock_irq(_lock);
 
drm_dev_put(>drm);
-- 
2.20.1

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up the plane data_rate stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up the plane data_rate stuff
URL   : https://patchwork.freedesktop.org/series/84075/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9362_full -> Patchwork_18944_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18944_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18944_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_18944_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
- shard-kbl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-kbl6/igt@kms_cursor_...@pipe-c-cursor-64x21-sliding.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-kbl6/igt@kms_cursor_...@pipe-c-cursor-64x21-sliding.html

  
New tests
-

  New tests have been introduced between CI_DRM_9362_full and 
Patchwork_18944_full:

### New CI tests (1) ###

  * boot:
- Statuses : 198 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18944_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_read@empty-nonblock:
- shard-glk:  [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-glk6/igt@drm_r...@empty-nonblock.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-glk3/igt@drm_r...@empty-nonblock.html

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#658])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-iclb2/igt@feature_discov...@psr2.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-iclb5/igt@feature_discov...@psr2.html

  * igt@gem_eio@kms:
- shard-snb:  [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-snb6/igt@gem_...@kms.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-snb7/igt@gem_...@kms.html

  * igt@gem_partial_pwrite_pread@reads:
- shard-apl:  [PASS][9] -> [INCOMPLETE][10] ([i915#1635])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-apl6/igt@gem_partial_pwrite_pr...@reads.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-apl3/igt@gem_partial_pwrite_pr...@reads.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
- shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-iclb1/igt@gem_render_c...@y-tiled-ccs-to-y-tiled-ccs.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-iclb4/igt@gem_render_c...@y-tiled-ccs-to-y-tiled-ccs.html

  * igt@gem_workarounds@suspend-resume-context:
- shard-apl:  [PASS][13] -> [DMESG-WARN][14] ([i915#1436] / 
[i915#1635] / [i915#2635])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-apl2/igt@gem_workarou...@suspend-resume-context.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-apl4/igt@gem_workarou...@suspend-resume-context.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  [PASS][15] -> [DMESG-WARN][16] ([i915#1436] / 
[i915#716])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-skl7/igt@gen9_exec_pa...@allowed-single.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-skl9/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#454])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-iclb1/igt@i915_pm...@dc6-psr.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-iclb4/igt@i915_pm...@dc6-psr.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-skl:  [PASS][19] -> [FAIL][20] ([i915#54]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-128x42-onscreen.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-128x42-onscreen.html

  * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
- shard-kbl:  [PASS][21] -> [DMESG-FAIL][22] ([i915#70] / 
[i915#95]) +11 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-kbl6/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html
   [22]: 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev2)
URL   : https://patchwork.freedesktop.org/series/84039/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9362_full -> Patchwork_18943_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_18943_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18943_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_18943_full:

### IGT changes ###

 Warnings 

  * igt@kms_chamelium@hdmi-hpd:
- shard-hsw:  [SKIP][1] ([fdo#109271] / [fdo#111827]) -> 
[INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-hsw7/igt@kms_chamel...@hdmi-hpd.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-hsw7/igt@kms_chamel...@hdmi-hpd.html

  
New tests
-

  New tests have been introduced between CI_DRM_9362_full and 
Patchwork_18943_full:

### New CI tests (1) ###

  * boot:
- Statuses : 197 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18943_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-iclb2/igt@feature_discov...@psr2.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-iclb5/igt@feature_discov...@psr2.html

  * igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-glk:  [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-glk1/igt@gem_exec_whis...@basic-contexts-priority-all.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-glk9/igt@gem_exec_whis...@basic-contexts-priority-all.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl:  [PASS][7] -> [FAIL][8] ([i915#1635] / [i915#644])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-apl1/igt@gem_pp...@flink-and-close-vma-leak.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-apl7/igt@gem_pp...@flink-and-close-vma-leak.html

  * igt@gem_workarounds@suspend-resume-context:
- shard-hsw:  [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-hsw6/igt@gem_workarou...@suspend-resume-context.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-hsw1/igt@gem_workarou...@suspend-resume-context.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#454])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-iclb1/igt@i915_pm...@dc6-psr.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-iclb4/igt@i915_pm...@dc6-psr.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-180:
- shard-apl:  [PASS][13] -> [DMESG-WARN][14] ([i915#1635] / 
[i915#1982]) +4 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-apl1/igt@kms_big...@x-tiled-8bpp-rotate-180.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-apl7/igt@kms_big...@x-tiled-8bpp-rotate-180.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen:
- shard-skl:  [PASS][15] -> [FAIL][16] ([i915#54]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-128x128-offscreen.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-skl1/igt@kms_cursor_...@pipe-c-cursor-128x128-offscreen.html

  * igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy:
- shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2346])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-tglb6/igt@kms_cursor_leg...@flip-vs-cursor-crc-legacy.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-tglb7/igt@kms_cursor_leg...@flip-vs-cursor-crc-legacy.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
- shard-skl:  [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +6 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/shard-skl6/igt@kms_flip@basic-plain-f...@a-edp1.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/shard-skl2/igt@kms_flip@basic-plain-f...@a-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-vga1:
- shard-snb:  [PASS][21] -> [DMESG-WARN][22] ([i915#42])
   [21]: 

[Intel-gfx] [PULL] drm-intel-fixes

[Rodrigo Vivi]

Hi Dave and Daniel,

Here goes another round for 5.10

drm-intel-fixes-2020-11-19:
- Fix tgl power gating issue (Rodrigo)
- Memory leak fixes (Tvrtko, Chris)
- Selftest fixes (Zhang)
- Display bpc fix (Ville)
- Fix TGL MOCS for PTE tracking (Chris)

GVT Fixes: It temporarily disables VFIO edid
feature on BXT/APL until its virtual display is really fixed to make
it work properly. And fixes for DPCD 1.2 and error return in taking
module reference.

Thanks,
Rodrigo.

The following changes since commit 5ce6861d36ed5207aff9e5eead4c7cc38a986586:

  drm/i915: Correctly set SFC capability for video engines (2020-11-12 19:47:30 
-0500)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2020-11-19

for you to fetch changes up to be33805c65297611971003d72e7f9235e23ec84d:

  drm/i915/gt: Fixup tgl mocs for PTE tracking (2020-11-19 15:10:49 -0500)


- Fix tgl power gating issue (Rodrigo)
- Memory leak fixes (Tvrtko, Chris)
- Selftest fixes (Zhang)
- Display bpc fix (Ville)
- Fix TGL MOCS for PTE tracking (Chris)

GVT Fixes: It temporarily disables VFIO edid
feature on BXT/APL until its virtual display is really fixed to make
it work properly. And fixes for DPCD 1.2 and error return in taking
module reference.


Chris Wilson (2):
  drm/i915/gt: Remember to free the virtual breadcrumbs
  drm/i915/gt: Fixup tgl mocs for PTE tracking

Colin Xu (1):
  drm/i915/gvt: Temporarily disable vfio_edid for BXT/APL

Rodrigo Vivi (2):
  drm/i915/tgl: Fix Media power gate sequence.
  Merge tag 'gvt-fixes-2020-11-17' of https://github.com/intel/gvt-linux 
into drm-intel-fixes

Tina Zhang (1):
  drm/i915/gvt: Set ENHANCED_FRAME_CAP bit

Tvrtko Ursulin (1):
  drm/i915: Avoid memory leak with more than 16 workarounds on a list

Ville Syrjälä (1):
  drm/i915: Handle max_bpc==16

Xiongfeng Wang (1):
  drm/i915/gvt: return error when failing to take the module reference

Zhang Xiaoxu (2):
  drm/i915/selftests: Fix wrong return value of perf_series_engines()
  drm/i915/selftests: Fix wrong return value of perf_request_latency()

 drivers/gpu/drm/i915/display/intel_display.c  |  3 ++-
 drivers/gpu/drm/i915/gt/intel_lrc.c   |  1 +
 drivers/gpu/drm/i915/gt/intel_mocs.c  |  5 +++--
 drivers/gpu/drm/i915/gt/intel_rc6.c   | 22 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  4 +++-
 drivers/gpu/drm/i915/gvt/display.c|  2 +-
 drivers/gpu/drm/i915/gvt/kvmgt.c  |  4 +++-
 drivers/gpu/drm/i915/gvt/vgpu.c   |  3 ++-
 drivers/gpu/drm/i915/i915_reg.h   | 12 +---
 drivers/gpu/drm/i915/intel_pm.c   | 13 -
 drivers/gpu/drm/i915/selftests/i915_request.c |  8 ++--
 11 files changed, 43 insertions(+), 34 deletions(-)
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up the plane data_rate stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up the plane data_rate stuff
URL   : https://patchwork.freedesktop.org/series/84075/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9362 -> Patchwork_18944


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/index.html

New tests
-

  New tests have been introduced between CI_DRM_9362 and Patchwork_18944:

### New CI tests (1) ###

  * boot:
- Statuses : 39 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18944 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot (NEW):
- {fi-tgl-dsi}:   [FAIL][1] ([i915#2448]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-dsi/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-tgl-dsi/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#1982] / 
[i915#402])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html

  * igt@i915_module_load@reload:
- fi-icl-u2:  [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-icl-u2/igt@i915_module_l...@reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-icl-u2/igt@i915_module_l...@reload.html

  * igt@kms_busy@basic@flip:
- fi-kbl-soraka:  [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-kbl-soraka/igt@kms_busy@ba...@flip.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2:  [PASS][11] -> [INCOMPLETE][12] ([i915#146] / 
[i915#2405])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2:  [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2:  [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +2 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@gem_mmap_...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka:   [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18944/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of 

Re: [Intel-gfx] [PATCH] drm/i915/display: Whitespace cleanups

[Navare, Manasi]

Pushed to dinq

Manasi

On Thu, Nov 19, 2020 at 09:07:17AM +, Chris Wilson wrote:
> drivers/gpu/drm/i915/display/intel_display.c:3634 
> intel_find_initial_plane_obj() warn: inconsistent indenting
> drivers/gpu/drm/i915/display/intel_display.c:15367 kill_bigjoiner_slave() 
> warn: inconsistent indenting
> 
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 23 ++--
>  1 file changed, 11 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5c07c74d4397..1a0f00f37ca9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3631,8 +3631,8 @@ intel_find_initial_plane_obj(struct intel_crtc 
> *intel_crtc,
>   struct intel_plane *intel_plane = to_intel_plane(primary);
>   struct intel_plane_state *intel_state =
>   to_intel_plane_state(plane_state);
> -  struct intel_crtc_state *crtc_state =
> -  to_intel_crtc_state(intel_crtc->base.state);
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(intel_crtc->base.state);
>   struct drm_framebuffer *fb;
>   struct i915_vma *vma;
>  
> @@ -15361,17 +15361,17 @@ static int kill_bigjoiner_slave(struct 
> intel_atomic_state *state,
>   struct intel_crtc_state *master_crtc_state)
>  {
>   struct intel_crtc_state *slave_crtc_state =
> - intel_atomic_get_crtc_state(>base,
> - 
> master_crtc_state->bigjoiner_linked_crtc);
> + intel_atomic_get_crtc_state(>base,
> + 
> master_crtc_state->bigjoiner_linked_crtc);
>  
> - if (IS_ERR(slave_crtc_state))
> - return PTR_ERR(slave_crtc_state);
> + if (IS_ERR(slave_crtc_state))
> + return PTR_ERR(slave_crtc_state);
>  
> - slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = 
> false;
> - slave_crtc_state->bigjoiner_slave = 
> master_crtc_state->bigjoiner_slave = false;
> - slave_crtc_state->bigjoiner_linked_crtc = 
> master_crtc_state->bigjoiner_linked_crtc = NULL;
> - intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
> - return 0;
> + slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
> + slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave 
> = false;
> + slave_crtc_state->bigjoiner_linked_crtc = 
> master_crtc_state->bigjoiner_linked_crtc = NULL;
> + intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
> + return 0;
>  }
>  
>  /**
> @@ -15949,7 +15949,6 @@ static void intel_update_crtc(struct 
> intel_atomic_state *state,
>   intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
>  }
>  
> -
>  static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> struct intel_crtc_state 
> *old_crtc_state,
> struct intel_crtc_state 
> *new_crtc_state,
> -- 
> 2.20.1
> 
> ___
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Re: [Intel-gfx] [PATCH] drm/i915/display: Whitespace cleanups

[Navare, Manasi]

On Thu, Nov 19, 2020 at 09:07:17AM +, Chris Wilson wrote:
> drivers/gpu/drm/i915/display/intel_display.c:3634 
> intel_find_initial_plane_obj() warn: inconsistent indenting
> drivers/gpu/drm/i915/display/intel_display.c:15367 kill_bigjoiner_slave() 
> warn: inconsistent indenting
> 
> Signed-off-by: Chris Wilson 

Thank you for the whitespace fixes, probably got introduced in the rebasing

Reviewed-by: Manasi Navare 

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 23 ++--
>  1 file changed, 11 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5c07c74d4397..1a0f00f37ca9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3631,8 +3631,8 @@ intel_find_initial_plane_obj(struct intel_crtc 
> *intel_crtc,
>   struct intel_plane *intel_plane = to_intel_plane(primary);
>   struct intel_plane_state *intel_state =
>   to_intel_plane_state(plane_state);
> -  struct intel_crtc_state *crtc_state =
> -  to_intel_crtc_state(intel_crtc->base.state);
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(intel_crtc->base.state);
>   struct drm_framebuffer *fb;
>   struct i915_vma *vma;
>  
> @@ -15361,17 +15361,17 @@ static int kill_bigjoiner_slave(struct 
> intel_atomic_state *state,
>   struct intel_crtc_state *master_crtc_state)
>  {
>   struct intel_crtc_state *slave_crtc_state =
> - intel_atomic_get_crtc_state(>base,
> - 
> master_crtc_state->bigjoiner_linked_crtc);
> + intel_atomic_get_crtc_state(>base,
> + 
> master_crtc_state->bigjoiner_linked_crtc);
>  
> - if (IS_ERR(slave_crtc_state))
> - return PTR_ERR(slave_crtc_state);
> + if (IS_ERR(slave_crtc_state))
> + return PTR_ERR(slave_crtc_state);
>  
> - slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = 
> false;
> - slave_crtc_state->bigjoiner_slave = 
> master_crtc_state->bigjoiner_slave = false;
> - slave_crtc_state->bigjoiner_linked_crtc = 
> master_crtc_state->bigjoiner_linked_crtc = NULL;
> - intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
> - return 0;
> + slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
> + slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave 
> = false;
> + slave_crtc_state->bigjoiner_linked_crtc = 
> master_crtc_state->bigjoiner_linked_crtc = NULL;
> + intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
> + return 0;
>  }
>  
>  /**
> @@ -15949,7 +15949,6 @@ static void intel_update_crtc(struct 
> intel_atomic_state *state,
>   intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
>  }
>  
> -
>  static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> struct intel_crtc_state 
> *old_crtc_state,
> struct intel_crtc_state 
> *new_crtc_state,
> -- 
> 2.20.1
> 
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up the plane data_rate stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up the plane data_rate stuff
URL   : https://patchwork.freedesktop.org/series/84075/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c0d1ad9d577b drm/i915: Drop pointless total_data_rate argument
076ed52a6259 drm/i915: Drop pointless dev_priv argument
cdea900f9957 drm/i915: Extract skl_ddb_entry_init()
7ff8f6d0 drm/i915: Introduce skl_plane_ddb_iter
a7add21a42fe drm/i915: Extract skl_allocate_plane_ddb()
c961619d2c21 drm/i915: Extract skl_crtc_calc_dbuf_bw()
1f668e243573 drm/i915: Tweak plane ddb allocation tracking
43279666b42c drm/i915: Split plane data_rate into data_rate+data_rate_y
36eeeb55b1ed drm/i915: Extract intel_adjusted_rate()
c2bbd552bb85 drm/i915: Reuse intel_adjusted_rate() for pfit pixel rate 
adjustment
571740d244d0 drm/i915: Pre-calculate plane relative data rate
-:454: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#454: FILE: drivers/gpu/drm/i915/intel_pm.c:4814:
+   iter.start + 
iter.uv_total[plane_id]);

total: 0 errors, 1 warnings, 0 checks, 403 lines checked
bee9dd701f76 drm/i915: Remove total[] and uv_total[] from ddb allocation
6837c02a30f5 drm/i915: s/plane_res_b/blocks/ etc.


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi (rev2)
URL   : https://patchwork.freedesktop.org/series/84039/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9362 -> Patchwork_18943


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/index.html

New tests
-

  New tests have been introduced between CI_DRM_9362 and Patchwork_18943:

### New CI tests (1) ###

  * boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18943 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot (NEW):
- {fi-tgl-dsi}:   [FAIL][1] ([i915#2448]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-dsi/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-tgl-dsi/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-icl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-icl-y/igt@core_hotunp...@unbind-rebind.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-icl-y/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_linear_blits@basic:
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#402])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@gem_linear_bl...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-tgl-y/igt@gem_linear_bl...@basic.html

  * igt@i915_module_load@reload:
- fi-tgl-y:   [PASS][7] -> [DMESG-WARN][8] ([i915#1982] / 
[k.org#205379])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@i915_module_l...@reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-tgl-y/igt@i915_module_l...@reload.html

  * igt@kms_busy@basic@flip:
- fi-tgl-y:   [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 
similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@kms_busy@ba...@flip.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-tgl-y/igt@kms_busy@ba...@flip.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2:  [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2:  [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [DMESG-WARN][15] ([i915#402]) -> [PASS][16] +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@gem_mmap_...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900:   [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- {fi-kbl-7560u}: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18943/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2448]: https://gitlab.freedesktop.org/drm/intel/issues/2448
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379


Participating hosts (42 -> 41)
--

  Additional (3): fi-glk-dsi fi-bxt-dsi fi-cfl-guc 
  Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-

  * Linux: CI_DRM_9362 -> Patchwork_18943

  CI-20190529: 20190529
  CI_DRM_9362: 

[Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Uma Shankar]

There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.

Bspec: 50422 HSD: 14010260002

v2: Added psr2 enabled check from crtc_state (Anshuman)
Added Bspec link and HSD referneces (Jose)

v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
and removed the crtc->config usages, as per Ville's recommendation.

Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index a5b072816a7b..cb29c6f068f9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct intel_crtc 
*crtc,
struct drm_framebuffer *fb = plane_state->hw.fb;
 
cache->plane.visible = plane_state->uapi.visible;
+
+   /*
+* Tigerlake is not supporting FBC with PSR2.
+* Recommendation is to keep this combination disabled
+* Bspec: 50422 HSD: 14010260002
+*/
+   if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
+   cache->plane.visible = false;
+
if (!cache->plane.visible)
return;
 
-- 
2.26.2

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[Intel-gfx] [PATCH 12/13] drm/i915: Remove total[] and uv_total[] from ddb allocation

[Ville Syrjala]

From: Ville Syrjälä 

There's really no need to maintain these total[] arrays to
track the size of each plane's ddb allocation. We just stick
the results straight into the crtc_state ddb tracking structures.

The main annoyance with all this is the mismatch between
wm_uv vs. ddb_y on pre-icl. If only the hw was consistent in
what it considers the primary source of information we could
avoid some of the uglyness. But since that is not the case
we need a bit of special casing for planar formats.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c | 105 
 1 file changed, 51 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a0ec7a102270..30f2de715398 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4627,13 +4627,12 @@ skl_plane_wm_level(const struct intel_crtc_state 
*crtc_state,
 
 struct skl_plane_ddb_iter {
u64 data_rate;
-   u16 total[I915_MAX_PLANES];
-   u16 uv_total[I915_MAX_PLANES];
u16 start, size;
 };
 
-static u16
+static void
 skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
+  struct skl_ddb_entry *ddb,
   const struct skl_wm_level *wm,
   u64 data_rate)
 {
@@ -4644,7 +4643,8 @@ skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
iter->size -= extra;
iter->data_rate -= data_rate;
 
-   return wm->min_ddb_alloc + extra;
+   iter->start = skl_ddb_entry_init(ddb, iter->start,
+iter->start + wm->min_ddb_alloc + 
extra);
 }
 
 static int
@@ -4655,8 +4655,9 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct skl_ddb_entry *alloc = _state->wm.skl.ddb;
-   struct skl_plane_ddb_iter iter = {};
+   struct skl_plane_ddb_iter iter;
enum plane_id plane_id;
+   u16 cursor_size;
int num_active;
u32 blocks;
int level;
@@ -4701,15 +4702,16 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
if (ret)
return ret;
 
+   iter.start = alloc->start;
iter.size = skl_ddb_entry_size(alloc);
if (iter.size == 0)
return 0;
 
/* Allocate fixed number of blocks for cursor. */
-   iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, 
num_active);
-   iter.size -= iter.total[PLANE_CURSOR];
+   cursor_size = skl_cursor_allocation(crtc_state, num_active);
+   iter.size -= cursor_size;
skl_ddb_entry_init(_state->wm.skl.plane_ddb[PLANE_CURSOR],
-  alloc->end - iter.total[PLANE_CURSOR], alloc->end);
+  alloc->end - cursor_size, alloc->end);
 
iter.data_rate = skl_total_relative_data_rate(crtc_state);
if (iter.data_rate == 0)
@@ -4722,11 +4724,13 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
for_each_plane_id_on_crtc(crtc, plane_id) {
+   const struct skl_ddb_entry *ddb =
+   _state->wm.skl.plane_ddb[plane_id];
const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
 
if (plane_id == PLANE_CURSOR) {
-   if (wm->wm[level].min_ddb_alloc > 
iter.total[PLANE_CURSOR]) {
+   if (wm->wm[level].min_ddb_alloc > 
skl_ddb_entry_size(ddb)) {
drm_WARN_ON(_priv->drm,
wm->wm[level].min_ddb_alloc 
!= U16_MAX);
blocks = U32_MAX;
@@ -4759,6 +4763,10 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
 * proportional to its relative data rate.
 */
for_each_plane_id_on_crtc(crtc, plane_id) {
+   struct skl_ddb_entry *ddb =
+   _state->wm.skl.plane_ddb[plane_id];
+   struct skl_ddb_entry *ddb_y =
+   _state->wm.skl.plane_ddb_y[plane_id];
const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
 
@@ -4774,51 +4782,17 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
 
if (INTEL_GEN(dev_priv) < 11 &&
crtc_state->nv12_planes & BIT(plane_id)) {
-   iter.total[plane_id] =
-   skl_allocate_plane_ddb(, >wm[level],
-  
crtc_state->rel_data_rate_y[plane_id]);
-   iter.uv_total[plane_id] =
-   

[Intel-gfx] [PATCH 11/13] drm/i915: Pre-calculate plane relative data rate

[Ville Syrjala]

From: Ville Syrjälä 

Handle the plane relative data rate in exactly the same
way as we already handle the real data rate. Ie. pre-calculate
it during intel_plane_atomic_check_with_state(), and assign/clear
it for the Y plane as needed. This should guarantee that the
tracking is 100% consistent, and makes me have to think less
when the same apporach is used by both types of data rate.

We might even want to consider replacing the relative
data rate with the real data rate entirely, but it's not
clear if that will produce less optimal plane ddb
allocations. So for now lets keep using the current approach.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_atomic_plane.c |  45 +++-
 .../gpu/drm/i915/display/intel_atomic_plane.h |   7 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   6 +
 .../drm/i915/display/intel_display_types.h|   6 +-
 drivers/gpu/drm/i915/intel_pm.c   | 229 +++---
 5 files changed, 89 insertions(+), 204 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 999a060ac951..d1e426949e17 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -133,9 +133,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
kfree(plane_state);
 }
 
-unsigned int intel_adjusted_rate(const struct drm_rect *src,
-const struct drm_rect *dst,
-unsigned int rate)
+u64 intel_adjusted_rate(const struct drm_rect *src,
+   const struct drm_rect *dst,
+   unsigned int rate)
 {
unsigned int src_w, src_h, dst_w, dst_h;
 
@@ -176,6 +176,35 @@ unsigned int intel_plane_data_rate(const struct 
intel_crtc_state *crtc_state,
fb->format->cpp[color_plane];
 }
 
+static u64 intel_plane_relative_data_rate(const struct intel_plane_state 
*plane_state,
+ int color_plane)
+{
+   const struct drm_framebuffer *fb = plane_state->hw.fb;
+   int width, height;
+
+   if (!plane_state->uapi.visible)
+   return 0;
+
+   /*
+* Src coordinates are already rotated by 270 degrees for
+* the 90/270 degree plane rotation cases (to match the
+* GTT mapping), hence no need to account for rotation here.
+*/
+   width = drm_rect_width(_state->uapi.src) >> 16;
+   height = drm_rect_height(_state->uapi.src) >> 16;
+
+   /* UV plane does 1/2 pixel sub-sampling */
+   if (color_plane == 1) {
+   width /= 2;
+   height /= 2;
+   }
+
+   return intel_adjusted_rate(_state->uapi.src,
+  _state->uapi.dst,
+  width * height) *
+   fb->format->cpp[color_plane];
+}
+
 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
   struct intel_plane *plane,
   bool *need_cdclk_calc)
@@ -296,6 +325,8 @@ void intel_plane_set_invisible(struct intel_crtc_state 
*crtc_state,
crtc_state->c8_planes &= ~BIT(plane->id);
crtc_state->data_rate[plane->id] = 0;
crtc_state->data_rate_y[plane->id] = 0;
+   crtc_state->rel_data_rate[plane->id] = 0;
+   crtc_state->rel_data_rate_y[plane->id] = 0;
crtc_state->min_cdclk[plane->id] = 0;
 
plane_state->uapi.visible = false;
@@ -340,9 +371,17 @@ int intel_plane_atomic_check_with_state(const struct 
intel_crtc_state *old_crtc_
intel_plane_data_rate(new_crtc_state, new_plane_state, 
0);
new_crtc_state->data_rate[plane->id] =
intel_plane_data_rate(new_crtc_state, new_plane_state, 
1);
+
+   new_crtc_state->rel_data_rate_y[plane->id] =
+   intel_plane_relative_data_rate(new_plane_state, 0);
+   new_crtc_state->rel_data_rate[plane->id] =
+   intel_plane_relative_data_rate(new_plane_state, 1);
} else if (new_plane_state->uapi.visible) {
new_crtc_state->data_rate[plane->id] =
intel_plane_data_rate(new_crtc_state, new_plane_state, 
0);
+
+   new_crtc_state->rel_data_rate[plane->id] =
+   intel_plane_relative_data_rate(new_plane_state, 0);
}
 
return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index a27bc091acc8..76e5243be204 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -19,12 +19,11 @@ struct intel_plane_state;
 
 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
 
-unsigned int intel_adjusted_rate(const struct drm_rect *src,
-

[Intel-gfx] [PATCH 10/13] drm/i915: Reuse intel_adjusted_rate() for pfit pixel rate adjustment

[Ville Syrjala]

From: Ville Syrjälä 

Replace the hand rolled pfit downscale calculations with
intel_adjusted_rate().

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_atomic_plane.c |  6 ++---
 .../gpu/drm/i915/display/intel_atomic_plane.h |  4 
 drivers/gpu/drm/i915/display/intel_display.c  | 23 +--
 3 files changed, 13 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 5c92147975fe..999a060ac951 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -133,9 +133,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
kfree(plane_state);
 }
 
-static unsigned int intel_adjusted_rate(const struct drm_rect *src,
-   const struct drm_rect *dst,
-   unsigned int rate)
+unsigned int intel_adjusted_rate(const struct drm_rect *src,
+const struct drm_rect *dst,
+unsigned int rate)
 {
unsigned int src_w, src_h, dst_w, dst_h;
 
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 912b311f153e..a27bc091acc8 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -10,6 +10,7 @@
 
 struct drm_plane;
 struct drm_property;
+struct drm_rect;
 struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
@@ -18,6 +19,9 @@ struct intel_plane_state;
 
 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
 
+unsigned int intel_adjusted_rate(const struct drm_rect *src,
+const struct drm_rect *dst,
+unsigned int rate);
 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state 
*plane_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 141d84118279..24684273b8d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8156,7 +8156,7 @@ static bool intel_crtc_supports_double_wide(const struct 
intel_crtc *crtc)
 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
 {
u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
-   unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
+   struct drm_rect src;
 
/*
 * We only use IF-ID interlacing. If we ever use
@@ -8166,23 +8166,12 @@ static u32 ilk_pipe_pixel_rate(const struct 
intel_crtc_state *crtc_state)
if (!crtc_state->pch_pfit.enabled)
return pixel_rate;
 
-   pipe_w = crtc_state->pipe_src_w;
-   pipe_h = crtc_state->pipe_src_h;
+   drm_rect_init(, 0, 0,
+ crtc_state->pipe_src_w << 16,
+ crtc_state->pipe_src_h << 16);
 
-   pfit_w = drm_rect_width(_state->pch_pfit.dst);
-   pfit_h = drm_rect_height(_state->pch_pfit.dst);
-
-   if (pipe_w < pfit_w)
-   pipe_w = pfit_w;
-   if (pipe_h < pfit_h)
-   pipe_h = pfit_h;
-
-   if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
-   !pfit_w || !pfit_h))
-   return pixel_rate;
-
-   return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
-  pfit_w * pfit_h);
+   return intel_adjusted_rate(, _state->pch_pfit.dst,
+  pixel_rate);
 }
 
 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
-- 
2.26.2

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[Intel-gfx] [PATCH 13/13] drm/i915: s/plane_res_b/blocks/ etc.

[Ville Syrjala]

From: Ville Syrjälä 

Rename a bunch of the skl+ watermark struct members to
have sensible names. Avoids me having to think what
plane_res_b/etc. means.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c  |  48 ++---
 .../drm/i915/display/intel_display_types.h|   6 +-
 drivers/gpu/drm/i915/intel_pm.c   | 182 +-
 3 files changed, 116 insertions(+), 120 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index a6ba155ee8f3..6bb07a6b162b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14507,12 +14507,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(_priv->drm,
"mismatch in WM pipe %c plane %d level %d 
(expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
pipe_name(pipe), plane + 1, level,
-   sw_plane_wm->wm[level].plane_en,
-   sw_plane_wm->wm[level].plane_res_b,
-   sw_plane_wm->wm[level].plane_res_l,
-   hw_plane_wm->wm[level].plane_en,
-   hw_plane_wm->wm[level].plane_res_b,
-   hw_plane_wm->wm[level].plane_res_l);
+   sw_plane_wm->wm[level].enable,
+   sw_plane_wm->wm[level].blocks,
+   sw_plane_wm->wm[level].lines,
+   hw_plane_wm->wm[level].enable,
+   hw_plane_wm->wm[level].blocks,
+   hw_plane_wm->wm[level].lines);
}
 
if (!skl_wm_level_equals(_plane_wm->trans_wm,
@@ -14520,12 +14520,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(_priv->drm,
"mismatch in trans WM pipe %c plane %d 
(expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
pipe_name(pipe), plane + 1,
-   sw_plane_wm->trans_wm.plane_en,
-   sw_plane_wm->trans_wm.plane_res_b,
-   sw_plane_wm->trans_wm.plane_res_l,
-   hw_plane_wm->trans_wm.plane_en,
-   hw_plane_wm->trans_wm.plane_res_b,
-   hw_plane_wm->trans_wm.plane_res_l);
+   sw_plane_wm->trans_wm.enable,
+   sw_plane_wm->trans_wm.blocks,
+   sw_plane_wm->trans_wm.lines,
+   hw_plane_wm->trans_wm.enable,
+   hw_plane_wm->trans_wm.blocks,
+   hw_plane_wm->trans_wm.lines);
}
 
/* DDB */
@@ -14564,12 +14564,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(_priv->drm,
"mismatch in WM pipe %c cursor level %d 
(expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
pipe_name(pipe), level,
-   sw_plane_wm->wm[level].plane_en,
-   sw_plane_wm->wm[level].plane_res_b,
-   sw_plane_wm->wm[level].plane_res_l,
-   hw_plane_wm->wm[level].plane_en,
-   hw_plane_wm->wm[level].plane_res_b,
-   hw_plane_wm->wm[level].plane_res_l);
+   sw_plane_wm->wm[level].enable,
+   sw_plane_wm->wm[level].blocks,
+   sw_plane_wm->wm[level].lines,
+   hw_plane_wm->wm[level].enable,
+   hw_plane_wm->wm[level].blocks,
+   hw_plane_wm->wm[level].lines);
}
 
if (!skl_wm_level_equals(_plane_wm->trans_wm,
@@ -14577,12 +14577,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
drm_err(_priv->drm,
"mismatch in trans WM pipe %c cursor (expected 
e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
pipe_name(pipe),
-   sw_plane_wm->trans_wm.plane_en,
-   sw_plane_wm->trans_wm.plane_res_b,
-   sw_plane_wm->trans_wm.plane_res_l,
-   hw_plane_wm->trans_wm.plane_en,
-   hw_plane_wm->trans_wm.plane_res_b,
-   hw_plane_wm->trans_wm.plane_res_l);
+   sw_plane_wm->trans_wm.enable,
+   sw_plane_wm->trans_wm.blocks,
+   

[Intel-gfx] [PATCH 08/13] drm/i915: Split plane data_rate into data_rate+data_rate_y

[Ville Syrjala]

From: Ville Syrjälä 

Split the currently combined plane data_rate into the proper
Y vs. CbCr components. This matches how we now track the
plane dbuf allocations, and thus will make the dbuf bandwidth
calculations actually produce the correct numbers for each
dbuf slice.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 34 --
 .../gpu/drm/i915/display/intel_atomic_plane.h |  3 +-
 drivers/gpu/drm/i915/display/intel_bw.c   | 36 +--
 drivers/gpu/drm/i915/display/intel_display.c  |  4 +++
 .../drm/i915/display/intel_display_types.h|  3 ++
 5 files changed, 42 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index eaa1e83b6fdd..318b2d0c0844 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -153,29 +153,16 @@ unsigned int intel_plane_pixel_rate(const struct 
intel_crtc_state *crtc_state,
 }
 
 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
-  const struct intel_plane_state *plane_state)
+  const struct intel_plane_state *plane_state,
+  int color_plane)
 {
const struct drm_framebuffer *fb = plane_state->hw.fb;
-   unsigned int cpp;
-   unsigned int pixel_rate;
 
if (!plane_state->uapi.visible)
return 0;
 
-   pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
-
-   cpp = fb->format->cpp[0];
-
-   /*
-* Based on HSD#:1408715493
-* NV12 cpp == 4, P010 cpp == 8
-*
-* FIXME what is the logic behind this?
-*/
-   if (fb->format->is_yuv && fb->format->num_planes > 1)
-   cpp *= 4;
-
-   return pixel_rate * cpp;
+   return intel_plane_pixel_rate(crtc_state, plane_state) *
+   fb->format->cpp[color_plane];
 }
 
 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
@@ -297,6 +284,7 @@ void intel_plane_set_invisible(struct intel_crtc_state 
*crtc_state,
crtc_state->nv12_planes &= ~BIT(plane->id);
crtc_state->c8_planes &= ~BIT(plane->id);
crtc_state->data_rate[plane->id] = 0;
+   crtc_state->data_rate_y[plane->id] = 0;
crtc_state->min_cdclk[plane->id] = 0;
 
plane_state->uapi.visible = false;
@@ -335,8 +323,16 @@ int intel_plane_atomic_check_with_state(const struct 
intel_crtc_state *old_crtc_
if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
new_crtc_state->update_planes |= BIT(plane->id);
 
-   new_crtc_state->data_rate[plane->id] =
-   intel_plane_data_rate(new_crtc_state, new_plane_state);
+   if (new_plane_state->uapi.visible &&
+   intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+   new_crtc_state->data_rate_y[plane->id] =
+   intel_plane_data_rate(new_crtc_state, new_plane_state, 
0);
+   new_crtc_state->data_rate[plane->id] =
+   intel_plane_data_rate(new_crtc_state, new_plane_state, 
1);
+   } else if (new_plane_state->uapi.visible) {
+   new_crtc_state->data_rate[plane->id] =
+   intel_plane_data_rate(new_crtc_state, new_plane_state, 
0);
+   }
 
return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
   old_plane_state, 
new_plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 5c78a087ed86..912b311f153e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -22,7 +22,8 @@ unsigned int intel_plane_pixel_rate(const struct 
intel_crtc_state *crtc_state,
const struct intel_plane_state 
*plane_state);
 
 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
-  const struct intel_plane_state *plane_state);
+  const struct intel_plane_state *plane_state,
+  int color_plane);
 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
   const struct intel_plane_state 
*from_plane_state,
   struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index a33a8a2784e9..98aa32beee2e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -335,6 +335,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const 
struct intel_crtc_stat
 static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state 

[Intel-gfx] [PATCH 09/13] drm/i915: Extract intel_adjusted_rate()

[Ville Syrjala]

From: Ville Syrjälä 

Extract a small helper to calculate the downscaling
adjusted pixel rate/data rate/etc.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 27 +--
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 318b2d0c0844..5c92147975fe 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -133,25 +133,36 @@ intel_plane_destroy_state(struct drm_plane *plane,
kfree(plane_state);
 }
 
-unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
-   const struct intel_plane_state *plane_state)
+static unsigned int intel_adjusted_rate(const struct drm_rect *src,
+   const struct drm_rect *dst,
+   unsigned int rate)
 {
unsigned int src_w, src_h, dst_w, dst_h;
-   unsigned int pixel_rate = crtc_state->pixel_rate;
 
-   src_w = drm_rect_width(_state->uapi.src) >> 16;
-   src_h = drm_rect_height(_state->uapi.src) >> 16;
-   dst_w = drm_rect_width(_state->uapi.dst);
-   dst_h = drm_rect_height(_state->uapi.dst);
+   src_w = drm_rect_width(src) >> 16;
+   src_h = drm_rect_height(src) >> 16;
+   dst_w = drm_rect_width(dst);
+   dst_h = drm_rect_height(dst);
 
/* Downscaling limits the maximum pixel rate */
dst_w = min(src_w, dst_w);
dst_h = min(src_h, dst_h);
 
-   return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, src_w * src_h),
+   return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
dst_w * dst_h);
 }
 
+unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
+   const struct intel_plane_state *plane_state)
+{
+   if (!plane_state->uapi.visible)
+   return 0;
+
+   return intel_adjusted_rate(_state->uapi.src,
+  _state->uapi.dst,
+  crtc_state->pixel_rate);
+}
+
 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
   const struct intel_plane_state *plane_state,
   int color_plane)
-- 
2.26.2

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[Intel-gfx] [PATCH 06/13] drm/i915: Extract skl_crtc_calc_dbuf_bw()

[Ville Syrjala]

From: Ville Syrjälä 

Extract the dbuf slice data_rate calculation into a small
helper. Should make it a bit easier to handle the different
color planes of planar formats correctly.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 81 ++---
 1 file changed, 44 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..f6de0b9bca90 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -428,6 +428,49 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
return to_intel_bw_state(bw_state);
 }
 
+static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
+ const struct intel_crtc_state *crtc_state)
+{
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+   struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+   struct intel_dbuf_bw *crtc_bw = _state->dbuf_bw[crtc->pipe];
+   enum plane_id plane_id;
+
+   memset(_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
+
+   if (!crtc_state->hw.active)
+   return;
+
+   for_each_plane_id_on_crtc(crtc, plane_id) {
+   const struct skl_ddb_entry *ddb_y =
+   _state->wm.skl.plane_ddb_y[plane_id];
+   const struct skl_ddb_entry *ddb_uv =
+   _state->wm.skl.plane_ddb_uv[plane_id];
+   unsigned int data_rate = crtc_state->data_rate[plane_id];
+   unsigned int dbuf_mask = 0;
+   int slice_id;
+
+   dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
+   dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_uv);
+
+   /*
+* FIXME: To calculate that more properly we probably
+* need to split per plane data_rate into data_rate_y
+* and data_rate_uv for multiplanar formats in order not
+* to get accounted those twice if they happen to reside
+* on different slices.
+* However for pre-icl this would work anyway because
+* we have only single slice and for icl+ uv plane has
+* non-zero data rate.
+* So in worst case those calculation are a bit
+* pessimistic, which shouldn't pose any significant
+* problem anyway.
+*/
+   for_each_dbuf_slice_in_mask(slice_id, dbuf_mask)
+   crtc_bw->used_bw[slice_id] += data_rate;
+   }
+}
+
 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -441,49 +484,13 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state 
*state)
int i;
 
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-   enum plane_id plane_id;
-   struct intel_dbuf_bw *crtc_bw;
-
new_bw_state = intel_atomic_get_bw_state(state);
if (IS_ERR(new_bw_state))
return PTR_ERR(new_bw_state);
 
old_bw_state = intel_atomic_get_old_bw_state(state);
 
-   crtc_bw = _bw_state->dbuf_bw[crtc->pipe];
-
-   memset(_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
-
-   if (!crtc_state->hw.active)
-   continue;
-
-   for_each_plane_id_on_crtc(crtc, plane_id) {
-   const struct skl_ddb_entry *plane_alloc =
-   _state->wm.skl.plane_ddb_y[plane_id];
-   const struct skl_ddb_entry *uv_plane_alloc =
-   _state->wm.skl.plane_ddb_uv[plane_id];
-   unsigned int data_rate = 
crtc_state->data_rate[plane_id];
-   unsigned int dbuf_mask = 0;
-
-   dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, 
plane_alloc);
-   dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, 
uv_plane_alloc);
-
-   /*
-* FIXME: To calculate that more properly we probably
-* need to to split per plane data_rate into data_rate_y
-* and data_rate_uv for multiplanar formats in order not
-* to get accounted those twice if they happen to reside
-* on different slices.
-* However for pre-icl this would work anyway because
-* we have only single slice and for icl+ uv plane has
-* non-zero data rate.
-* So in worst case those calculation are a bit
-* pessimistic, which shouldn't pose any significant
-* problem anyway.
-*/
-   

[Intel-gfx] [PATCH 07/13] drm/i915: Tweak plane ddb allocation tracking

[Ville Syrjala]

From: Ville Syrjälä 

Let's store the plane allocation in a manner which more closely
matches how the hw operates. That is, we store the packed/CbCr
ddb in one struct, and the Y ddb in another. Currently we're
storing packed/Y in one struct, CbCr in the other.

This also works pretty well for icl+ where the UV plane is
the main plane and the Y plane is subservient to it. Although
in this case we do not even use ddb_y as we do the ddb allocation
in terms of hw planes.

Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 32 +++---
 drivers/gpu/drm/i915/display/intel_bw.c   |  6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 12 +--
 .../drm/i915/display/intel_display_debugfs.c  |  4 +-
 .../drm/i915/display/intel_display_types.h|  7 +-
 drivers/gpu/drm/i915/intel_pm.c   | 97 ---
 6 files changed, 71 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 7e9f84b00859..eaa1e83b6fdd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -399,8 +399,8 @@ int intel_plane_atomic_check(struct intel_atomic_state 
*state,
 static struct intel_plane *
 skl_next_plane_to_commit(struct intel_atomic_state *state,
 struct intel_crtc *crtc,
-struct skl_ddb_entry entries_y[I915_MAX_PLANES],
-struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
+struct skl_ddb_entry ddb[I915_MAX_PLANES],
+struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
 unsigned int *update_mask)
 {
struct intel_crtc_state *crtc_state =
@@ -419,17 +419,15 @@ skl_next_plane_to_commit(struct intel_atomic_state *state,
!(*update_mask & BIT(plane_id)))
continue;
 
-   if 
(skl_ddb_allocation_overlaps(_state->wm.skl.plane_ddb_y[plane_id],
-   entries_y,
-   I915_MAX_PLANES, plane_id) ||
-   
skl_ddb_allocation_overlaps(_state->wm.skl.plane_ddb_uv[plane_id],
-   entries_uv,
-   I915_MAX_PLANES, plane_id))
+   if 
(skl_ddb_allocation_overlaps(_state->wm.skl.plane_ddb[plane_id],
+   ddb, I915_MAX_PLANES, plane_id) 
||
+   
skl_ddb_allocation_overlaps(_state->wm.skl.plane_ddb_y[plane_id],
+   ddb_y, I915_MAX_PLANES, 
plane_id))
continue;
 
*update_mask &= ~BIT(plane_id);
-   entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
-   entries_uv[plane_id] = 
crtc_state->wm.skl.plane_ddb_uv[plane_id];
+   ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
+   ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
 
return plane;
}
@@ -470,19 +468,17 @@ void skl_update_planes_on_crtc(struct intel_atomic_state 
*state,
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
-   struct skl_ddb_entry entries_y[I915_MAX_PLANES];
-   struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
+   struct skl_ddb_entry ddb[I915_MAX_PLANES];
+   struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
u32 update_mask = new_crtc_state->update_planes;
struct intel_plane *plane;
 
-   memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
+   memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
+  sizeof(old_crtc_state->wm.skl.plane_ddb));
+   memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
   sizeof(old_crtc_state->wm.skl.plane_ddb_y));
-   memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
-  sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
 
-   while ((plane = skl_next_plane_to_commit(state, crtc,
-entries_y, entries_uv,
-_mask))) {
+   while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, 
_mask))) {
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index f6de0b9bca90..a33a8a2784e9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -442,16 +442,16 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state 
*bw_state,
return;
 
for_each_plane_id_on_crtc(crtc, plane_id) {
+

[Intel-gfx] [PATCH 05/13] drm/i915: Extract skl_allocate_plane_ddb()

[Ville Syrjala]

From: Ville Syrjälä 

Replace some copy-pasta with a function.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c | 35 -
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d951dab840f9..c2851bb1975d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4808,6 +4808,21 @@ struct skl_plane_ddb_iter {
u16 start, size;
 };
 
+static u16
+skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
+  const struct skl_wm_level *wm,
+  u64 data_rate)
+{
+   u16 extra;
+
+   extra = min_t(u16, iter->size,
+ DIV64_U64_ROUND_UP(iter->size * data_rate, 
iter->data_rate));
+   iter->size -= extra;
+   iter->data_rate -= data_rate;
+
+   return wm->min_ddb_alloc + extra;
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_atomic_state *state,
  struct intel_crtc *crtc)
@@ -4926,8 +4941,6 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
for_each_plane_id_on_crtc(crtc, plane_id) {
const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
-   u64 data_rate;
-   u16 extra;
 
if (plane_id == PLANE_CURSOR)
continue;
@@ -4939,22 +4952,16 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
if (iter.data_rate == 0)
break;
 
-   data_rate = crtc_state->plane_data_rate[plane_id];
-   extra = min_t(u16, iter.size,
- DIV64_U64_ROUND_UP(iter.size * data_rate, 
iter.data_rate));
-   iter.total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
-   iter.size -= extra;
-   iter.data_rate -= data_rate;
+   iter.total[plane_id] =
+   skl_allocate_plane_ddb(, >wm[level],
+  
crtc_state->plane_data_rate[plane_id]);
 
if (iter.data_rate == 0)
break;
 
-   data_rate = crtc_state->uv_plane_data_rate[plane_id];
-   extra = min_t(u16, iter.size,
- DIV64_U64_ROUND_UP(iter.size * data_rate, 
iter.data_rate));
-   iter.uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + 
extra;
-   iter.size -= extra;
-   iter.data_rate -= data_rate;
+   iter.uv_total[plane_id] =
+   skl_allocate_plane_ddb(, >uv_wm[level],
+  
crtc_state->uv_plane_data_rate[plane_id]);
}
drm_WARN_ON(_priv->drm, iter.size != 0 || iter.data_rate != 0);
 
-- 
2.26.2

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[Intel-gfx] [PATCH 04/13] drm/i915: Introduce skl_plane_ddb_iter

[Ville Syrjala]

From: Ville Syrjälä 

Collect a bit of the stuff used during the plane ddb
allocation into a struct we can pass around.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c | 94 -
 1 file changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2b14f23759ec..d951dab840f9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4801,6 +4801,13 @@ skl_plane_wm_level(const struct intel_crtc_state 
*crtc_state,
return >wm[level];
 }
 
+struct skl_plane_ddb_iter {
+   u64 data_rate;
+   u16 total[I915_MAX_PLANES];
+   u16 uv_total[I915_MAX_PLANES];
+   u16 start, size;
+};
+
 static int
 skl_allocate_pipe_ddb(struct intel_atomic_state *state,
  struct intel_crtc *crtc)
@@ -4809,10 +4816,7 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct skl_ddb_entry *alloc = _state->wm.skl.ddb;
-   u16 alloc_size, start = 0;
-   u16 total[I915_MAX_PLANES] = {};
-   u16 uv_total[I915_MAX_PLANES] = {};
-   u64 total_data_rate;
+   struct skl_plane_ddb_iter iter = {};
enum plane_id plane_id;
int num_active;
u32 blocks;
@@ -4854,28 +4858,26 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
}
 
if (INTEL_GEN(dev_priv) >= 11)
-   total_data_rate =
-   icl_get_total_relative_data_rate(state, crtc);
+   iter.data_rate = icl_get_total_relative_data_rate(state, crtc);
else
-   total_data_rate =
-   skl_get_total_relative_data_rate(state, crtc);
+   iter.data_rate = skl_get_total_relative_data_rate(state, crtc);
 
ret = skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
 alloc, _active);
if (ret)
return ret;
 
-   alloc_size = skl_ddb_entry_size(alloc);
-   if (alloc_size == 0)
+   iter.size = skl_ddb_entry_size(alloc);
+   if (iter.size == 0)
return 0;
 
/* Allocate fixed number of blocks for cursor. */
-   total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
-   alloc_size -= total[PLANE_CURSOR];
+   iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, 
num_active);
+   iter.size -= iter.total[PLANE_CURSOR];
skl_ddb_entry_init(_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
-  alloc->end - total[PLANE_CURSOR], alloc->end);
+  alloc->end - iter.total[PLANE_CURSOR], alloc->end);
 
-   if (total_data_rate == 0)
+   if (iter.data_rate == 0)
return 0;
 
/*
@@ -4889,7 +4891,7 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
_state->wm.skl.optimal.planes[plane_id];
 
if (plane_id == PLANE_CURSOR) {
-   if (wm->wm[level].min_ddb_alloc > 
total[PLANE_CURSOR]) {
+   if (wm->wm[level].min_ddb_alloc > 
iter.total[PLANE_CURSOR]) {
drm_WARN_ON(_priv->drm,
wm->wm[level].min_ddb_alloc 
!= U16_MAX);
blocks = U32_MAX;
@@ -4902,8 +4904,8 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
blocks += wm->uv_wm[level].min_ddb_alloc;
}
 
-   if (blocks <= alloc_size) {
-   alloc_size -= blocks;
+   if (blocks <= iter.size) {
+   iter.size -= blocks;
break;
}
}
@@ -4912,7 +4914,7 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
drm_dbg_kms(_priv->drm,
"Requested display configuration exceeds system DDB 
limitations");
drm_dbg_kms(_priv->drm, "minimum required %d/%d\n",
-   blocks, alloc_size);
+   blocks, iter.size);
return -EINVAL;
}
 
@@ -4924,7 +4926,7 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
for_each_plane_id_on_crtc(crtc, plane_id) {
const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
-   u64 rate;
+   u64 data_rate;
u16 extra;
 
if (plane_id == PLANE_CURSOR)
@@ -4934,32 +4936,30 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
 * We've accounted for all active planes; remaining planes are
 * all disabled.
 */
-   if (total_data_rate == 0)
+ 

[Intel-gfx] [PATCH 03/13] drm/i915: Extract skl_ddb_entry_init()

[Ville Syrjala]

From: Ville Syrjälä 

Extract a small helper to populate a ddb entry.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c | 48 +
 1 file changed, 25 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index be8eacac8e62..2b14f23759ec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4017,6 +4017,15 @@ static int intel_compute_sagv_mask(struct 
intel_atomic_state *state)
return 0;
 }
 
+static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
+ u16 start, u16 end)
+{
+   entry->start = start;
+   entry->end = end;
+
+   return end;
+}
+
 /*
  * Calculate initial DBuf slice offset, based on slice size
  * and mask(i.e if slice size is 1024 and second slice is enabled
@@ -4110,8 +4119,8 @@ skl_ddb_get_pipe_allocation_limits(struct 
drm_i915_private *dev_priv,
*num_active = hweight8(active_pipes);
 
if (!crtc_state->hw.active) {
-   alloc->start = 0;
-   alloc->end = 0;
+   skl_ddb_entry_init(alloc, 0, 0);
+
return 0;
}
 
@@ -4223,8 +4232,7 @@ skl_ddb_get_pipe_allocation_limits(struct 
drm_i915_private *dev_priv,
end = ddb_range_size *
(width_before_pipe_in_range + pipe_width) / 
total_width_in_range;
 
-   alloc->start = offset + start;
-   alloc->end = offset + end;
+   skl_ddb_entry_init(alloc, offset + start, offset + end);
 
drm_dbg_kms(_priv->drm,
"[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 
0x%x\n",
@@ -4278,12 +4286,10 @@ skl_cursor_allocation(const struct intel_crtc_state 
*crtc_state,
 
 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
 {
-
-   entry->start = reg & DDB_ENTRY_MASK;
-   entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
-
+   skl_ddb_entry_init(entry, reg & DDB_ENTRY_MASK,
+  (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK);
if (entry->end)
-   entry->end += 1;
+   entry->end++;
 }
 
 static void
@@ -4842,7 +4848,8 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
}
}
 
-   alloc->start = alloc->end = 0;
+   skl_ddb_entry_init(alloc, 0, 0);
+
return 0;
}
 
@@ -4865,9 +4872,8 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
/* Allocate fixed number of blocks for cursor. */
total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
alloc_size -= total[PLANE_CURSOR];
-   crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
-   alloc->end - total[PLANE_CURSOR];
-   crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
+   skl_ddb_entry_init(_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
+  alloc->end - total[PLANE_CURSOR], alloc->end);
 
if (total_data_rate == 0)
return 0;
@@ -4968,17 +4974,13 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
 
/* Leave disabled planes at (0,0) */
-   if (total[plane_id]) {
-   plane_alloc->start = start;
-   start += total[plane_id];
-   plane_alloc->end = start;
-   }
+   if (total[plane_id])
+   start = skl_ddb_entry_init(plane_alloc, start,
+  start + total[plane_id]);
 
-   if (uv_total[plane_id]) {
-   uv_plane_alloc->start = start;
-   start += uv_total[plane_id];
-   uv_plane_alloc->end = start;
-   }
+   if (uv_total[plane_id])
+   start = skl_ddb_entry_init(uv_plane_alloc, start,
+  start + uv_total[plane_id]);
}
 
/*
-- 
2.26.2

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[Intel-gfx] [PATCH 02/13] drm/i915: Drop pointless dev_priv argument

[Ville Syrjala]

From: Ville Syrjälä 

skl_ddb_entry_init_from_hw() has no need for dev_priv.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 846597919019..be8eacac8e62 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4276,8 +4276,7 @@ skl_cursor_allocation(const struct intel_crtc_state 
*crtc_state,
return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
 }
 
-static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
-  struct skl_ddb_entry *entry, u32 reg)
+static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
 {
 
entry->start = reg & DDB_ENTRY_MASK;
@@ -4300,7 +4299,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private 
*dev_priv,
/* Cursor doesn't support NV12/planar, so no extra calculation needed */
if (plane_id == PLANE_CURSOR) {
val = I915_READ(CUR_BUF_CFG(pipe));
-   skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+   skl_ddb_entry_init_from_hw(ddb_y, val);
return;
}
 
@@ -4314,7 +4313,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private 
*dev_priv,
 
if (INTEL_GEN(dev_priv) >= 11) {
val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-   skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+   skl_ddb_entry_init_from_hw(ddb_y, val);
} else {
val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
@@ -4323,8 +4322,8 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private 
*dev_priv,
drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
swap(val, val2);
 
-   skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
-   skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
+   skl_ddb_entry_init_from_hw(ddb_y, val);
+   skl_ddb_entry_init_from_hw(ddb_uv, val2);
}
 }
 
-- 
2.26.2

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Re: [Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Shankar, Uma]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Thursday, November 19, 2020 9:12 PM
> To: Shankar, Uma 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2
> 
> On Thu, Nov 19, 2020 at 09:20:49PM +0530, Uma Shankar wrote:
> > There are some corner cases wrt underrun when we enable FBC with PSR2
> > on TGL. Recommendation from hardware is to keep this combination
> > disabled.
> >
> > Bspec: 50422 HSD: 14010260002
> >
> > v2: Added psr2 enabled check from crtc_state (Anshuman) Added Bspec
> > link and HSD referneces (Jose)
> >
> > Signed-off-by: Uma Shankar 
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a5b072816a7b..c64ed1cd29b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -799,6 +799,17 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc)
> > struct intel_fbc *fbc = _priv->fbc;
> > struct intel_fbc_state_cache *cache = >state_cache;
> >
> > +   /*
> > +* Tigerlake is not supporting FBC with PSR2.
> > +* Recommendation is to keep this combination disabled
> > +* Bspec: 50422 HSD: 14010260002
> > +*/
> > +   if (crtc->config && crtc->config->has_psr2 &&
> 
> Please don't add more crtc->config usages. After several years we've almost
> reached the point where we can finally remove it.
> I should porbably take a look at how much work would be required to at least
> make it always NULL on g4x+.
> 
> The fbc state tracking is a total mess atm, but I think you can stuff this 
> into
> intel_fbc_update_state_cache() and either just set cache->plane.visible=false
> (which is a bit of a lie but would work), or add a new thing into the
> params/cache.

Ok sure, so I hope below logic will keep this disabled:
  if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
cache->plane.visible = false;

if (!cache->plane.visible)
return;

Will update and re-send the patch.

Thanks & Regards,
Uma Shankar

> My plan is to eliminate most of the this params/cache mess and just cache the
> things fbc really needs for hw activate/deactivate. I do have a wip branch but
> haven't had time recently to continue the work.
> 
> > +   IS_TIGERLAKE(dev_priv)) {
> > +   fbc->no_fbc_reason = "not supported with PSR2";
> > +   return false;
> > +   }
> > +
> > if (!intel_fbc_can_enable(dev_priv))
> > return false;
> >
> > --
> > 2.26.2
> 
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH 01/13] drm/i915: Drop pointless total_data_rate argument

[Ville Syrjala]

From: Ville Syrjälä 

skl_ddb_get_pipe_allocation_limits() has no need for
the total relative data rate.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_pm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a20b5051f18c..846597919019 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4083,7 +4083,6 @@ static u8 skl_compute_dbuf_slices(const struct 
intel_crtc_state *crtc_state,
 static int
 skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
   const struct intel_crtc_state *crtc_state,
-  const u64 total_data_rate,
   struct skl_ddb_entry *alloc, /* out */
   int *num_active /* out */)
 {
@@ -4856,7 +4855,6 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
skl_get_total_relative_data_rate(state, crtc);
 
ret = skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
-total_data_rate,
 alloc, _active);
if (ret)
return ret;
-- 
2.26.2

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[Intel-gfx] [PATCH 00/13] drm/i915: Clean up the plane data_rate stuff

[Ville Syrjala]

From: Ville Syrjälä 

Let's sort out the plane data_rate stuff properly by
accounting each color plane independently. And we reuse the same
code and approach for the relative data rate (which is used for
plane ddb allocation).

Currently it's not even obvious if the relative data rate is
really correct in all the cases. The normal data rate stuff
is much more obvious with the way it's getting computed ahead
of time. Also reusing the same code for both means we at least
have just the one set of bugs to fix.

I was also pondering potentially replacing the relative data
rate entirely with the real data rate, but it's not obvious
what effect that would have to the watermarks. Smaller
planes would certainly get a bigger proportion of ddb allocated
to them, which might result in worse power consumption I guess.
But at least with data_rate and rel_data_rate being handled 
almost identically we could easily change the strategy at
any time.

Ville Syrjälä (13):
  drm/i915: Drop pointless total_data_rate argument
  drm/i915: Drop pointless dev_priv argument
  drm/i915: Extract skl_ddb_entry_init()
  drm/i915: Introduce skl_plane_ddb_iter
  drm/i915: Extract skl_allocate_plane_ddb()
  drm/i915: Extract skl_crtc_calc_dbuf_bw()
  drm/i915: Tweak plane ddb allocation tracking
  drm/i915: Split plane data_rate into data_rate+data_rate_y
  drm/i915: Extract intel_adjusted_rate()
  drm/i915: Reuse intel_adjusted_rate() for pfit pixel rate adjustment
  drm/i915: Pre-calculate plane relative data rate
  drm/i915: Remove total[] and uv_total[] from ddb allocation
  drm/i915: s/plane_res_b/blocks/ etc.

 .../gpu/drm/i915/display/intel_atomic_plane.c | 122 ++--
 .../gpu/drm/i915/display/intel_atomic_plane.h |   8 +-
 drivers/gpu/drm/i915/display/intel_bw.c   |  81 +--
 drivers/gpu/drm/i915/display/intel_display.c  |  93 ++-
 .../drm/i915/display/intel_display_debugfs.c  |   4 +-
 .../drm/i915/display/intel_display_types.h|  22 +-
 drivers/gpu/drm/i915/intel_pm.c   | 629 +++---
 7 files changed, 421 insertions(+), 538 deletions(-)

-- 
2.26.2

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Re: [Intel-gfx] [PATCH] i915/gem_flink_race: Fix error in buffer usage

[Chris Wilson]

Quoting Hampson, Steven T (2020-11-19 18:18:14)
> Chris,
> 
> Is this acceptable?  Can it be merged?

It is of little use to print out that many numbers, so lets not and just
show some statistics instead as this is just meant to be a guide to the
reader as to whether the threads each received a reasonably fair
proportion of the _CPU_ time.
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/6] drm/i915/gt: Include semaphore status in print_request()

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/6] drm/i915/gt: Include semaphore status in 
print_request()
URL   : https://patchwork.freedesktop.org/series/84073/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9362 -> Patchwork_18942


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18942 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18942, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_18942:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_suspend@basic-s0:
- fi-glk-dsi: NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-glk-dsi/igt@gem_exec_susp...@basic-s0.html

  
New tests
-

  New tests have been introduced between CI_DRM_9362 and Patchwork_18942:

### New CI tests (1) ###

  * boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18942 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot (NEW):
- {fi-tgl-dsi}:   [FAIL][2] ([i915#2448]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-dsi/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-tgl-dsi/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +1 similar 
issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-y:   [PASS][6] -> [DMESG-FAIL][7] ([i915#2601] / 
[i915#541])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [PASS][8] -> [INCOMPLETE][9] ([i915#1635])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html

  * igt@kms_busy@basic@flip:
- fi-tgl-y:   [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1 
similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@kms_busy@ba...@flip.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-tgl-y/igt@kms_busy@ba...@flip.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2:  [PASS][12] -> [DMESG-WARN][13] ([i915#1982])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2:  [DMESG-WARN][14] ([i915#1982]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [DMESG-WARN][16] ([i915#402]) -> [PASS][17] +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@gem_mmap_...@basic.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900:   [DMESG-WARN][18] ([i915#1982]) -> [PASS][19] +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18942/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  
 Warnings 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-y:   [DMESG-WARN][20] ([i915#2411]) -> [DMESG-WARN][21] 
([i915#1982] / [i915#2411])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html
   [21]: 

[Intel-gfx] [PATCH v2] drm/i915: Do not call hsw_set_frame_start_delay for dsi

[Manasi Navare]

This should fix the boot oops for dsi

v2:
* Fix indent (Manasi)

Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for 
bigjoiner")
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 5c07c74d4397..cbbe92d47e11 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7211,7 +7211,7 @@ static void hsw_crtc_enable(struct intel_atomic_state 
*state,
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
 
-   if (!new_crtc_state->bigjoiner_slave || 
!transcoder_is_dsi(cpu_transcoder)) {
+   if (!new_crtc_state->bigjoiner_slave && 
!transcoder_is_dsi(cpu_transcoder)) {
if (!transcoder_is_dsi(cpu_transcoder))
intel_set_transcoder_timings(new_crtc_state);
 
-- 
2.19.1

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Re: [Intel-gfx] [PATCH] i915/gem_flink_race: Fix error in buffer usage

[Hampson, Steven T]

Chris,

Is this acceptable?  Can it be merged?

-Original Message-
From: Hampson, Steven T 
Sent: Wednesday, November 18, 2020 12:41 PM
To: 'Chris Wilson' 
Cc: intel-gfx@ 
Subject: RE: [Intel-gfx] [PATCH] i915/gem_flink_race: Fix error in buffer usage

The problem is that the machine it was running on had 32 cpus, so one set of 
numbers per cpu filled the buffer.

-Original Message-
From: Chris Wilson 
Sent: Wednesday, November 18, 2020 2:52 AM
To: Hampson, Steven T 
Cc: intel-gfx@ 
Subject: Re: [Intel-gfx] [PATCH] i915/gem_flink_race: Fix error in buffer usage

Quoting Hampson, Steven T (2020-11-17 23:45:23)
> 
> 
> Sent from my iPhone
> 
> > On Nov 17, 2020, at 2:28 PM, Chris Wilson  wrote:
> > 
> > Quoting Steve Hampson (2020-11-17 22:23:08)
> >> A buffer in function test_flink_name was both too small and never 
> >> checked for overflow.  Both errors are fixed.
> > 
> > That many numbers is not interesting. Show the range and median instead.
> > -Chris
> 
> I don’t understand what you are talking about.  

The reason I printed the individual numbers was so that we could see the 
distribution in case one thread was being starved or not. That is fine for a 
few numbers, but beyond that we can summarise with statistics.
-Chris
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Re: [Intel-gfx] [CI 4/6] drm/i915/gt: Show all active timelines for debugging

[Chris Wilson]

Quoting Tvrtko Ursulin (2020-11-19 18:08:49)
> 
> On 19/11/2020 16:56, Chris Wilson wrote:
> > Include the active timelines for debugfs/i915_engine_info, so that we
> > can see which have unready requests inflight which are not shown
> > otherwise.
> > 
> > Suggested-by: Tvrtko Ursulin 
> > Signed-off-by: Chris Wilson 
> > Reviewd-by: Chris Wilson 
> 
> Wrong paste, I believe I r-b-ed this one.

Pebkac. I shall have to sit in the corner for a bit.
-Chris
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Re: [Intel-gfx] [CI 4/6] drm/i915/gt: Show all active timelines for debugging

[Tvrtko Ursulin]

On 19/11/2020 16:56, Chris Wilson wrote:

Include the active timelines for debugfs/i915_engine_info, so that we
can see which have unready requests inflight which are not shown
otherwise.

Suggested-by: Tvrtko Ursulin 
Signed-off-by: Chris Wilson 
Reviewd-by: Chris Wilson 


Wrong paste, I believe I r-b-ed this one.

Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko


---
  drivers/gpu/drm/i915/gt/intel_timeline.c | 80 
  drivers/gpu/drm/i915/gt/intel_timeline.h |  9 +++
  drivers/gpu/drm/i915/i915_debugfs.c  | 16 ++---
  3 files changed, 98 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c 
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 7ea94d201fe6..512afacd2bdc 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -617,6 +617,86 @@ void intel_gt_fini_timelines(struct intel_gt *gt)
GEM_BUG_ON(!list_empty(>hwsp_free_list));
  }
  
+void intel_gt_show_timelines(struct intel_gt *gt,

+struct drm_printer *m,
+void (*show_request)(struct drm_printer *m,
+ const struct i915_request *rq,
+ const char *prefix,
+ int indent))
+{
+   struct intel_gt_timelines *timelines = >timelines;
+   struct intel_timeline *tl, *tn;
+   LIST_HEAD(free);
+
+   spin_lock(>lock);
+   list_for_each_entry_safe(tl, tn, >active_list, link) {
+   unsigned long count, ready, inflight;
+   struct i915_request *rq, *rn;
+   struct dma_fence *fence;
+
+   if (!mutex_trylock(>mutex)) {
+   drm_printf(m, "Timeline %llx: busy; skipping\n",
+  tl->fence_context);
+   continue;
+   }
+
+   intel_timeline_get(tl);
+   GEM_BUG_ON(!atomic_read(>active_count));
+   atomic_inc(>active_count); /* pin the list element */
+   spin_unlock(>lock);
+
+   count = 0;
+   ready = 0;
+   inflight = 0;
+   list_for_each_entry_safe(rq, rn, >requests, link) {
+   if (i915_request_completed(rq))
+   continue;
+
+   count++;
+   if (i915_request_is_ready(rq))
+   ready++;
+   if (i915_request_is_active(rq))
+   inflight++;
+   }
+
+   drm_printf(m, "Timeline %llx: { ", tl->fence_context);
+   drm_printf(m, "count: %lu, ready: %lu, inflight: %lu",
+  count, ready, inflight);
+   drm_printf(m, ", seqno: { current: %d, last: %d }",
+  *tl->hwsp_seqno, tl->seqno);
+   fence = i915_active_fence_get(>last_request);
+   if (fence) {
+   drm_printf(m, ", engine: %s",
+  to_request(fence)->engine->name);
+   dma_fence_put(fence);
+   }
+   drm_printf(m, " }\n");
+
+   if (show_request) {
+   list_for_each_entry_safe(rq, rn, >requests, link)
+   show_request(m, rq, "", 2);
+   }
+
+   mutex_unlock(>mutex);
+   spin_lock(>lock);
+
+   /* Resume list iteration after reacquiring spinlock */
+   list_safe_reset_next(tl, tn, link);
+   if (atomic_dec_and_test(>active_count))
+   list_del(>link);
+
+   /* Defer the final release to after the spinlock */
+   if (refcount_dec_and_test(>kref.refcount)) {
+   GEM_BUG_ON(atomic_read(>active_count));
+   list_add(>link, );
+   }
+   }
+   spin_unlock(>lock);
+
+   list_for_each_entry_safe(tl, tn, , link)
+   __intel_timeline_free(>kref);
+}
+
  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
  #include "gt/selftests/mock_timeline.c"
  #include "gt/selftest_timeline.c"
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h 
b/drivers/gpu/drm/i915/gt/intel_timeline.h
index 9882cd911d8e..634acebd0c4b 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -31,6 +31,8 @@
  #include "i915_syncmap.h"
  #include "intel_timeline_types.h"
  
+struct drm_printer;

+
  struct intel_timeline *
  __intel_timeline_create(struct intel_gt *gt,
struct i915_vma *global_hwsp,
@@ -106,4 +108,11 @@ int intel_timeline_read_hwsp(struct i915_request *from,
  void intel_gt_init_timelines(struct intel_gt *gt);
  void intel_gt_fini_timelines(struct intel_gt *gt);
  
+void intel_gt_show_timelines(struct intel_gt *gt,

+ 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/6] drm/i915/gt: Include semaphore status in print_request()

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/6] drm/i915/gt: Include semaphore status in 
print_request()
URL   : https://patchwork.freedesktop.org/series/84073/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
93a1f698eabf drm/i915/gt: Include semaphore status in print_request()
b4a8a32b2827 drm/i915: Lift i915_request_show()
b181d794d0c7 drm/i915/gt: Update request status flags for debug pretty-printer
d57734fd8c75 drm/i915/gt: Show all active timelines for debugging
-:12: WARNING:BAD_SIGN_OFF: Non-standard signature: Reviewd-by:
#12: 
Reviewd-by: Chris Wilson 

total: 0 errors, 1 warnings, 0 checks, 138 lines checked
f9256f4ad02d drm/i915: Lift waiter/signaler iterators
1761480b7c1c drm/i915: Show timeline dependencies for debug
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#13: 
Timeline 886: { count 1, ready: 0, inflight: 0, seqno: { current: 664, last: 
666 }, engine: rcs0 }

total: 0 errors, 1 warnings, 0 checks, 66 lines checked


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[Intel-gfx] ✗ Fi.CI.BAT: failure for Re-enable FBC on TGL (rev2)

[Patchwork]

== Series Details ==

Series: Re-enable FBC on TGL (rev2)
URL   : https://patchwork.freedesktop.org/series/83510/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9362 -> Patchwork_18941


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18941 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18941, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_18941:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_suspend@basic-s3:
- fi-glk-dsi: NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-glk-dsi/igt@gem_exec_susp...@basic-s3.html

  
New tests
-

  New tests have been introduced between CI_DRM_9362 and Patchwork_18941:

### New CI tests (1) ###

  * boot:
- Statuses : 1 fail(s) 38 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18941 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_busy@basic@flip:
- fi-kbl-soraka:  [PASS][2] -> [DMESG-WARN][3] ([i915#1982])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-kbl-soraka/igt@kms_busy@ba...@flip.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2:  [DMESG-WARN][4] ([i915#1982]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2:  [DMESG-WARN][6] ([i915#1982]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900:   [DMESG-WARN][8] ([i915#1982]) -> [PASS][9] +1 similar 
issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- {fi-kbl-7560u}: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9362/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982


Participating hosts (42 -> 39)
--

  Additional (2): fi-glk-dsi fi-cfl-guc 
  Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-tgl-y fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9362 -> Patchwork_18941

  CI-20190529: 20190529
  CI_DRM_9362: 374246282b84ca52149ecb9a83a4ad7a515d01d9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5859: 5bc1047cc8f38a9e0c5a914b6511a639b15a740e @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18941: fef9c94372d16d2bf3d5289d44264b292922250a @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

fef9c94372d1 Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
489e02f189b4 drm/i915/display/tgl: Disable FBC with PSR2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18941/index.html
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Update request status flags for debug pretty-printer (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Update request status flags for debug pretty-printer (rev2)
URL   : https://patchwork.freedesktop.org/series/84061/
State : failure

== Summary ==

Applying: drm/i915/gt: Update request status flags for debug pretty-printer
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/gt/intel_lrc.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/gt: Update request status flags for debug 
pretty-printer
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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[Intel-gfx] [CI 4/6] drm/i915/gt: Show all active timelines for debugging

[Chris Wilson]

Include the active timelines for debugfs/i915_engine_info, so that we
can see which have unready requests inflight which are not shown
otherwise.

Suggested-by: Tvrtko Ursulin 
Signed-off-by: Chris Wilson 
Reviewd-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/intel_timeline.c | 80 
 drivers/gpu/drm/i915/gt/intel_timeline.h |  9 +++
 drivers/gpu/drm/i915/i915_debugfs.c  | 16 ++---
 3 files changed, 98 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c 
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 7ea94d201fe6..512afacd2bdc 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -617,6 +617,86 @@ void intel_gt_fini_timelines(struct intel_gt *gt)
GEM_BUG_ON(!list_empty(>hwsp_free_list));
 }
 
+void intel_gt_show_timelines(struct intel_gt *gt,
+struct drm_printer *m,
+void (*show_request)(struct drm_printer *m,
+ const struct i915_request *rq,
+ const char *prefix,
+ int indent))
+{
+   struct intel_gt_timelines *timelines = >timelines;
+   struct intel_timeline *tl, *tn;
+   LIST_HEAD(free);
+
+   spin_lock(>lock);
+   list_for_each_entry_safe(tl, tn, >active_list, link) {
+   unsigned long count, ready, inflight;
+   struct i915_request *rq, *rn;
+   struct dma_fence *fence;
+
+   if (!mutex_trylock(>mutex)) {
+   drm_printf(m, "Timeline %llx: busy; skipping\n",
+  tl->fence_context);
+   continue;
+   }
+
+   intel_timeline_get(tl);
+   GEM_BUG_ON(!atomic_read(>active_count));
+   atomic_inc(>active_count); /* pin the list element */
+   spin_unlock(>lock);
+
+   count = 0;
+   ready = 0;
+   inflight = 0;
+   list_for_each_entry_safe(rq, rn, >requests, link) {
+   if (i915_request_completed(rq))
+   continue;
+
+   count++;
+   if (i915_request_is_ready(rq))
+   ready++;
+   if (i915_request_is_active(rq))
+   inflight++;
+   }
+
+   drm_printf(m, "Timeline %llx: { ", tl->fence_context);
+   drm_printf(m, "count: %lu, ready: %lu, inflight: %lu",
+  count, ready, inflight);
+   drm_printf(m, ", seqno: { current: %d, last: %d }",
+  *tl->hwsp_seqno, tl->seqno);
+   fence = i915_active_fence_get(>last_request);
+   if (fence) {
+   drm_printf(m, ", engine: %s",
+  to_request(fence)->engine->name);
+   dma_fence_put(fence);
+   }
+   drm_printf(m, " }\n");
+
+   if (show_request) {
+   list_for_each_entry_safe(rq, rn, >requests, link)
+   show_request(m, rq, "", 2);
+   }
+
+   mutex_unlock(>mutex);
+   spin_lock(>lock);
+
+   /* Resume list iteration after reacquiring spinlock */
+   list_safe_reset_next(tl, tn, link);
+   if (atomic_dec_and_test(>active_count))
+   list_del(>link);
+
+   /* Defer the final release to after the spinlock */
+   if (refcount_dec_and_test(>kref.refcount)) {
+   GEM_BUG_ON(atomic_read(>active_count));
+   list_add(>link, );
+   }
+   }
+   spin_unlock(>lock);
+
+   list_for_each_entry_safe(tl, tn, , link)
+   __intel_timeline_free(>kref);
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "gt/selftests/mock_timeline.c"
 #include "gt/selftest_timeline.c"
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h 
b/drivers/gpu/drm/i915/gt/intel_timeline.h
index 9882cd911d8e..634acebd0c4b 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -31,6 +31,8 @@
 #include "i915_syncmap.h"
 #include "intel_timeline_types.h"
 
+struct drm_printer;
+
 struct intel_timeline *
 __intel_timeline_create(struct intel_gt *gt,
struct i915_vma *global_hwsp,
@@ -106,4 +108,11 @@ int intel_timeline_read_hwsp(struct i915_request *from,
 void intel_gt_init_timelines(struct intel_gt *gt);
 void intel_gt_fini_timelines(struct intel_gt *gt);
 
+void intel_gt_show_timelines(struct intel_gt *gt,
+struct drm_printer *m,
+void (*show_request)(struct drm_printer *m,
+   

[Intel-gfx] [CI 3/6] drm/i915/gt: Update request status flags for debug pretty-printer

[Chris Wilson]

We plan to expand upon the number of available statuses for when we
pretty-print the requests along the timelines, and so need a new set of
flags. We have settled upon:

Unready [U]
  - initial status after being submitted, the request is not
ready for execution as it is waiting for external fences

Ready [R]
  - all fences the request was waiting on have been signaled,
and the request is now ready for execution and will be
in a backend queue

  - a ready request may still need to wait on semaphores
[internal fences]

Ready/virtual [V]
  - same as ready, but queued over multiple backends

Executing [E]
  - the request has been transferred from the backend queue and
submitted for execution on HW

  - a completed request may still be regarded as executing, its
status may not be updated until it is retired and removed
from the lists

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  6 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c   | 15 ++--
 drivers/gpu/drm/i915/gt/intel_lrc.h   |  3 +-
 drivers/gpu/drm/i915/i915_request.c   | 85 +++
 drivers/gpu/drm/i915/i915_request.h   |  3 +-
 5 files changed, 88 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c3bb2e9546e6..d4e988b2816a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1491,7 +1491,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
intel_context_is_banned(rq->context) ? 
"*" : "");
len += print_ring(hdr + len, sizeof(hdr) - len, rq);
scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
-   i915_request_show(m, rq, hdr);
+   i915_request_show(m, rq, hdr, 0);
}
for (port = execlists->pending; (rq = *port); port++) {
char hdr[160];
@@ -1505,7 +1505,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
intel_context_is_banned(rq->context) ? 
"*" : "");
len += print_ring(hdr + len, sizeof(hdr) - len, rq);
scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
-   i915_request_show(m, rq, hdr);
+   i915_request_show(m, rq, hdr, 0);
}
rcu_read_unlock();
execlists_active_unlock_bh(execlists);
@@ -1649,7 +1649,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (rq) {
struct intel_timeline *tl = get_timeline(rq);
 
-   i915_request_show(m, rq, "\t\tactive ");
+   i915_request_show(m, rq, "\t\tactive ", 0);
 
drm_printf(m, "\t\tring->start:  0x%08x\n",
   i915_ggtt_offset(rq->ring->vma));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b6ab1161942a..5257f3c71366 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -5982,7 +5982,8 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
   struct drm_printer *m,
   void (*show_request)(struct drm_printer *m,
const struct 
i915_request *rq,
-   const char *prefix),
+   const char *prefix,
+   int indent),
   unsigned int max)
 {
const struct intel_engine_execlists *execlists = >execlists;
@@ -5997,7 +5998,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
count = 0;
list_for_each_entry(rq, >active.requests, sched.link) {
if (count++ < max - 1)
-   show_request(m, rq, "\t\tE ");
+   show_request(m, rq, "\t\t", 0);
else
last = rq;
}
@@ -6007,7 +6008,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
   "\t\t...skipping %d executing requests...\n",
   count - max);
}
-   show_request(m, last, "\t\tE ");
+   show_request(m, last, "\t\t", 0);
}
 
if (execlists->switch_priority_hint != INT_MIN)
@@ -6025,7 +6026,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
 
priolist_for_each_request(rq, 

[Intel-gfx] [CI 2/6] drm/i915: Lift i915_request_show()

[Chris Wilson]

Extract i915_request_show for reuse in other request chain pretty
printers.

For a bonus point, quietly change the seqno format from %llx to %lld to
match everywhere else.

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 47 ++-
 drivers/gpu/drm/i915/gt/intel_lrc.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_lrc.h   |  2 +-
 drivers/gpu/drm/i915/i915_request.c   | 39 +++
 drivers/gpu/drm/i915/i915_request.h   |  5 +++
 5 files changed, 50 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1ed84ee8ce41..c3bb2e9546e6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1294,45 +1294,6 @@ bool intel_engine_can_store_dword(struct intel_engine_cs 
*engine)
}
 }
 
-static int print_sched_attr(const struct i915_sched_attr *attr,
-   char *buf, int x, int len)
-{
-   if (attr->priority == I915_PRIORITY_INVALID)
-   return x;
-
-   x += snprintf(buf + x, len - x,
- " prio=%d", attr->priority);
-
-   return x;
-}
-
-static void print_request(struct drm_printer *m,
- struct i915_request *rq,
- const char *prefix)
-{
-   const char *name = rq->fence.ops->get_timeline_name(>fence);
-   char buf[80] = "";
-   int x = 0;
-
-   x = print_sched_attr(>sched.attr, buf, x, sizeof(buf));
-
-   drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n",
-  prefix,
-  rq->fence.context, rq->fence.seqno,
-  i915_request_completed(rq) ? "!" :
-  i915_request_started(rq) ? "*" :
-  !i915_sw_fence_signaled(>semaphore) ? "&" :
-  "",
-  test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
-   >fence.flags) ? "+" :
-  test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
-   >fence.flags) ? "-" :
-  "",
-  buf,
-  jiffies_to_msecs(jiffies - rq->emitted_jiffies),
-  name);
-}
-
 static struct intel_timeline *get_timeline(struct i915_request *rq)
 {
struct intel_timeline *tl;
@@ -1530,7 +1491,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
intel_context_is_banned(rq->context) ? 
"*" : "");
len += print_ring(hdr + len, sizeof(hdr) - len, rq);
scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
-   print_request(m, rq, hdr);
+   i915_request_show(m, rq, hdr);
}
for (port = execlists->pending; (rq = *port); port++) {
char hdr[160];
@@ -1544,7 +1505,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
intel_context_is_banned(rq->context) ? 
"*" : "");
len += print_ring(hdr + len, sizeof(hdr) - len, rq);
scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
-   print_request(m, rq, hdr);
+   i915_request_show(m, rq, hdr);
}
rcu_read_unlock();
execlists_active_unlock_bh(execlists);
@@ -1688,7 +1649,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (rq) {
struct intel_timeline *tl = get_timeline(rq);
 
-   print_request(m, rq, "\t\tactive ");
+   i915_request_show(m, rq, "\t\tactive ");
 
drm_printf(m, "\t\tring->start:  0x%08x\n",
   i915_ggtt_offset(rq->ring->vma));
@@ -1726,7 +1687,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
drm_printf(m, "\tDevice is asleep; skipping register dump\n");
}
 
-   intel_execlists_show_requests(engine, m, print_request, 8);
+   intel_execlists_show_requests(engine, m, i915_request_show, 8);
 
drm_printf(m, "HWSP:\n");
hexdump(m, engine->status_page.addr, PAGE_SIZE);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f7eca93f04bc..b6ab1161942a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -5981,7 +5981,7 @@ int intel_virtual_engine_attach_bond(struct 
intel_engine_cs *engine,
 void intel_execlists_show_requests(struct intel_engine_cs *engine,
   struct drm_printer *m,
   void (*show_request)(struct drm_printer *m,
-   struct i915_request *rq,
+   const struct 
i915_request *rq,
 

[Intel-gfx] [CI 6/6] drm/i915: Show timeline dependencies for debug

[Chris Wilson]

From: Tvrtko Ursulin 

Include the signalers each request in the timeline is waiting on, as a
means to try and identify the cause of a stall. This can be quite
verbose, even as for now we only show each request in the timeline and
its immediate antecedents.

This generates output like:

Timeline 886: { count 1, ready: 0, inflight: 0, seqno: { current: 664, last: 
666 }, engine: rcs0 }
  U 886:29a-  prio=0 @ 134ms: gem_exec_parall<4621>
U bc1:27a-  prio=0 @ 134ms: gem_exec_parall[4917]
Timeline 825: { count 1, ready: 0, inflight: 0, seqno: { current: 802, last: 
804 }, engine: vcs0 }
  U 825:324  prio=0 @ 107ms: gem_exec_parall<4518>
U b75:140-  prio=0 @ 110ms: gem_exec_parall<5486>
Timeline b46: { count 1, ready: 0, inflight: 0, seqno: { current: 782, last: 
784 }, engine: vcs0 }
  U b46:310-  prio=0 @ 70ms: gem_exec_parall<5428>
U c11:170-  prio=0 @ 70ms: gem_exec_parall[5501]
Timeline 96b: { count 1, ready: 0, inflight: 0, seqno: { current: 632, last: 
634 }, engine: vcs0 }
  U 96b:27a-  prio=0 @ 67ms: gem_exec_parall<4878>
U b75:19e-  prio=0 @ 67ms: gem_exec_parall<5486>

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c   |  3 ++-
 drivers/gpu/drm/i915/i915_scheduler.c | 28 +++
 drivers/gpu/drm/i915/i915_scheduler.h |  7 +++
 3 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 354b95c438d0..263074c2c097 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -45,6 +45,7 @@
 #include "i915_debugfs.h"
 #include "i915_debugfs_params.h"
 #include "i915_irq.h"
+#include "i915_scheduler.h"
 #include "i915_trace.h"
 #include "intel_pm.h"
 #include "intel_sideband.h"
@@ -1323,7 +1324,7 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
for_each_uabi_engine(engine, i915)
intel_engine_dump(engine, , "%s\n", engine->name);
 
-   intel_gt_show_timelines(>gt, , NULL);
+   intel_gt_show_timelines(>gt, , i915_request_show_with_schedule);
 
intel_runtime_pm_put(>runtime_pm, wakeref);
 
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c 
b/drivers/gpu/drm/i915/i915_scheduler.c
index cbb880b10c65..b9cf9931ebd7 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -504,6 +504,34 @@ void i915_sched_node_fini(struct i915_sched_node *node)
spin_unlock_irq(_lock);
 }
 
+void i915_request_show_with_schedule(struct drm_printer *m,
+const struct i915_request *rq,
+const char *prefix,
+int indent)
+{
+   struct i915_dependency *dep;
+
+   i915_request_show(m, rq, prefix, indent);
+   if (i915_request_completed(rq))
+   return;
+
+   rcu_read_lock();
+   for_each_signaler(dep, rq) {
+   const struct i915_request *signaler =
+   node_to_request(dep->signaler);
+
+   /* Dependencies along the same timeline are expected. */
+   if (signaler->timeline == rq->timeline)
+   continue;
+
+   if (i915_request_completed(signaler))
+   continue;
+
+   i915_request_show(m, signaler, prefix, indent + 2);
+   }
+   rcu_read_unlock();
+}
+
 static void i915_global_scheduler_shrink(void)
 {
kmem_cache_shrink(global.slab_dependencies);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h 
b/drivers/gpu/drm/i915/i915_scheduler.h
index 6f0bf00fc569..4501e5ac2637 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -13,6 +13,8 @@
 
 #include "i915_scheduler_types.h"
 
+struct drm_printer;
+
 #define priolist_for_each_request(it, plist, idx) \
for (idx = 0; idx < ARRAY_SIZE((plist)->requests); idx++) \
list_for_each_entry(it, &(plist)->requests[idx], sched.link)
@@ -54,4 +56,9 @@ static inline void i915_priolist_free(struct i915_priolist *p)
__i915_priolist_free(p);
 }
 
+void i915_request_show_with_schedule(struct drm_printer *m,
+const struct i915_request *rq,
+const char *prefix,
+int indent);
+
 #endif /* _I915_SCHEDULER_H_ */
-- 
2.20.1

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[Intel-gfx] [CI 5/6] drm/i915: Lift waiter/signaler iterators

[Chris Wilson]

Lift the list iteration defines for traversing the signaler/waiter lists
into i915_scheduler.h for reuse.

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 10 --
 drivers/gpu/drm/i915/i915_scheduler_types.h | 10 ++
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 5257f3c71366..30759e95da0e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1836,16 +1836,6 @@ static void virtual_xfer_context(struct virtual_engine 
*ve,
}
 }
 
-#define for_each_waiter(p__, rq__) \
-   list_for_each_entry_lockless(p__, \
-&(rq__)->sched.waiters_list, \
-wait_link)
-
-#define for_each_signaler(p__, rq__) \
-   list_for_each_entry_rcu(p__, \
-   &(rq__)->sched.signalers_list, \
-   signal_link)
-
 static void defer_request(struct i915_request *rq, struct list_head * const pl)
 {
LIST_HEAD(list);
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h 
b/drivers/gpu/drm/i915/i915_scheduler_types.h
index f72e6c397b08..343ed44d5ed4 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -81,4 +81,14 @@ struct i915_dependency {
 #define I915_DEPENDENCY_WEAK   BIT(2)
 };
 
+#define for_each_waiter(p__, rq__) \
+   list_for_each_entry_lockless(p__, \
+&(rq__)->sched.waiters_list, \
+wait_link)
+
+#define for_each_signaler(p__, rq__) \
+   list_for_each_entry_rcu(p__, \
+   &(rq__)->sched.signalers_list, \
+   signal_link)
+
 #endif /* _I915_SCHEDULER_TYPES_H_ */
-- 
2.20.1

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[Intel-gfx] [CI 1/6] drm/i915/gt: Include semaphore status in print_request()

[Chris Wilson]

When pretty-printing the requests for debug, also show the status of any
semaphore waits as part of its runnable status.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0b31670343f5..1ed84ee8ce41 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1321,6 +1321,7 @@ static void print_request(struct drm_printer *m,
   rq->fence.context, rq->fence.seqno,
   i915_request_completed(rq) ? "!" :
   i915_request_started(rq) ? "*" :
+  !i915_sw_fence_signaled(>semaphore) ? "&" :
   "",
   test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
>fence.flags) ? "+" :
-- 
2.20.1

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Re: [Intel-gfx] [PATCH 14/28] drm/i915/gt: Free stale request on destroying the virtual engine

[Tvrtko Ursulin]

On 19/11/2020 14:22, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2020-11-19 14:06:00)


On 18/11/2020 12:10, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2020-11-18 11:38:43)


On 18/11/2020 11:24, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2020-11-18 11:05:24)


On 17/11/2020 11:30, Chris Wilson wrote:

Since preempt-to-busy, we may unsubmit a request while it is still on
the HW and completes asynchronously. That means it may be retired and in
the process destroy the virtual engine (as the user has closed their
context), but that engine may still be holding onto the unsubmitted
compelted request. Therefore we need to potentially cleanup the old
request on destroying the virtual engine. We also have to keep the
virtual_engine alive until after the sibling's execlists_dequeue() have
finished peeking into the virtual engines, for which we serialise with
RCU.

v2: Be paranoid and flush the tasklet as well.
v3: And flush the tasklet before the engines, as the tasklet may
re-attach an rb_node after our removal from the siblings.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 61 +
 1 file changed, 54 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 17cb7060eb29..c11433884cf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -182,6 +182,7 @@
 struct virtual_engine {
 struct intel_engine_cs base;
 struct intel_context context;
+ struct rcu_work rcu;
 
 /*

  * We allow only a single request through the virtual engine at a time
@@ -5470,44 +5471,90 @@ static struct list_head *virtual_queue(struct 
virtual_engine *ve)
 return >base.execlists.default_priolist.requests[0];
 }
 
-static void virtual_context_destroy(struct kref *kref)

+static void rcu_virtual_context_destroy(struct work_struct *wrk)
 {
 struct virtual_engine *ve =
- container_of(kref, typeof(*ve), context.ref);
+ container_of(wrk, typeof(*ve), rcu.work);
 unsigned int n;
 
- GEM_BUG_ON(!list_empty(virtual_queue(ve)));

- GEM_BUG_ON(ve->request);
 GEM_BUG_ON(ve->context.inflight);
 
+ /* Preempt-to-busy may leave a stale request behind. */

+ if (unlikely(ve->request)) {
+ struct i915_request *old;
+
+ spin_lock_irq(>base.active.lock);
+
+ old = fetch_and_zero(>request);
+ if (old) {
+ GEM_BUG_ON(!i915_request_completed(old));
+ __i915_request_submit(old);
+ i915_request_put(old);
+ }
+
+ spin_unlock_irq(>base.active.lock);
+ }
+
+ /*
+  * Flush the tasklet in case it is still running on another core.
+  *
+  * This needs to be done before we remove ourselves from the siblings'
+  * rbtrees as in the case it is running in parallel, it may reinsert
+  * the rb_node into a sibling.
+  */
+ tasklet_kill(>base.execlists.tasklet);


Can it still be running after an RCU period?


I think there is a window between checking to see if the request is
completed and kicking the tasklet, that is not under the rcu lock and
opportunity for the request to be retired, and barrier flushed to drop
the context references.


   From where would that check come?


The window of opportunity extends all the way from the
i915_request_completed check during unsubmit right until the virtual
engine tasklet is executed -- we do not hold a reference to the virtual
engine for the tasklet, and that request may be retired in the
background, and along with it the virtual engine destroyed.


In this case aren't sibling tasklets also a problem?


The next stanza decouples the siblings. At this point, we know that the
request must have been completed (to retire and drop the context
reference) so at this point nothing should be allowed to kick the
virtual engine tasklet, it's just the outstanding execution we need to
serialise. So the following assertion that nothing did kick the tasklet
as we decoupled the siblings holds. After that assertion, there should
be nothing else that knows about the virtual tasklet.


Let me see in step by step because I am slow today.

1. Tasklet runs, decides to preempt the VE away.
2. VE completes despite that.
3. Userspace closes the context.
4. RCU period.
5. All tasklets which were active during 1 have exited.
   + VE decoupled and
6. VE unlinked from siblings and destroyed.

Re-submit VE tasklet may start as soon after 1 and any time after. If it 
starts after 4, then RCU period from context close does not see it. Okay 
makes sense.


Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko
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Re: [Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Ville Syrjälä]

On Thu, Nov 19, 2020 at 09:20:49PM +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
> 
> Bspec: 50422 HSD: 14010260002
> 
> v2: Added psr2 enabled check from crtc_state (Anshuman)
> Added Bspec link and HSD referneces (Jose)
> 
> Signed-off-by: Uma Shankar 
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a5b072816a7b..c64ed1cd29b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -799,6 +799,17 @@ static bool intel_fbc_can_activate(struct intel_crtc 
> *crtc)
>   struct intel_fbc *fbc = _priv->fbc;
>   struct intel_fbc_state_cache *cache = >state_cache;
>  
> + /*
> +  * Tigerlake is not supporting FBC with PSR2.
> +  * Recommendation is to keep this combination disabled
> +  * Bspec: 50422 HSD: 14010260002
> +  */
> + if (crtc->config && crtc->config->has_psr2 &&

Please don't add more crtc->config usages. After several years
we've almost reached the point where we can finally remove it.
I should porbably take a look at how much work would be required
to at least make it always NULL on g4x+.

The fbc state tracking is a total mess atm, but I think you can
stuff this into intel_fbc_update_state_cache() and either just
set cache->plane.visible=false (which is a bit of a lie but would
work), or add a new thing into the params/cache.

My plan is to eliminate most of the this params/cache mess
and just cache the things fbc really needs for hw
activate/deactivate. I do have a wip branch but haven't had
time recently to continue the work.

> + IS_TIGERLAKE(dev_priv)) {
> + fbc->no_fbc_reason = "not supported with PSR2";
> + return false;
> + }
> +
>   if (!intel_fbc_can_enable(dev_priv))
>   return false;
>  
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [v2 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL"

[Uma Shankar]

FBC can be re-enabled on TGL with WA of keeping it disabled
while PSR2 is enabled.

This reverts commit 2982ded2ff5ce0cf1a49bc39a526da182782b664.

Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index c64ed1cd29b1..7a5783564a0f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1444,13 +1444,6 @@ static int intel_sanitize_fbc_option(struct 
drm_i915_private *dev_priv)
if (!HAS_FBC(dev_priv))
return 0;
 
-   /*
-* Fbc is causing random underruns in CI execution on TGL platforms.
-* Disabling the same while the problem is being debugged and analyzed.
-*/
-   if (IS_TIGERLAKE(dev_priv))
-   return 0;
-
if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
return 1;
 
-- 
2.26.2

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[Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Uma Shankar]

There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.

Bspec: 50422 HSD: 14010260002

v2: Added psr2 enabled check from crtc_state (Anshuman)
Added Bspec link and HSD referneces (Jose)

Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index a5b072816a7b..c64ed1cd29b1 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -799,6 +799,17 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
struct intel_fbc *fbc = _priv->fbc;
struct intel_fbc_state_cache *cache = >state_cache;
 
+   /*
+* Tigerlake is not supporting FBC with PSR2.
+* Recommendation is to keep this combination disabled
+* Bspec: 50422 HSD: 14010260002
+*/
+   if (crtc->config && crtc->config->has_psr2 &&
+   IS_TIGERLAKE(dev_priv)) {
+   fbc->no_fbc_reason = "not supported with PSR2";
+   return false;
+   }
+
if (!intel_fbc_can_enable(dev_priv))
return false;
 
-- 
2.26.2

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[Intel-gfx] [v2 0/2] Re-enable FBC on TGL

[Uma Shankar]

FBC was disabled on TGL due to random underruns. It has
been determined that FBC will not work reliably with PSR2.
This series re-enables fbc along with taking care of the
PSR2 limitations for TGL.

Bspec: 50422 HSD: 14010260002

v2: Addressed review comments and added bspec links

Uma Shankar (2):
  drm/i915/display/tgl: Disable FBC with PSR2
  Revert "drm/i915/display/fbc: Disable fbc by default on TGL"

 drivers/gpu/drm/i915/display/intel_fbc.c | 18 +++---
 1 file changed, 11 insertions(+), 7 deletions(-)

-- 
2.26.2

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Re: [Intel-gfx] [PATCH 14/28] drm/i915/gt: Free stale request on destroying the virtual engine

[Chris Wilson]

Quoting Tvrtko Ursulin (2020-11-19 14:06:00)
> 
> On 18/11/2020 12:10, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-11-18 11:38:43)
> >>
> >> On 18/11/2020 11:24, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2020-11-18 11:05:24)
> 
>  On 17/11/2020 11:30, Chris Wilson wrote:
> > Since preempt-to-busy, we may unsubmit a request while it is still on
> > the HW and completes asynchronously. That means it may be retired and in
> > the process destroy the virtual engine (as the user has closed their
> > context), but that engine may still be holding onto the unsubmitted
> > compelted request. Therefore we need to potentially cleanup the old
> > request on destroying the virtual engine. We also have to keep the
> > virtual_engine alive until after the sibling's execlists_dequeue() have
> > finished peeking into the virtual engines, for which we serialise with
> > RCU.
> >
> > v2: Be paranoid and flush the tasklet as well.
> > v3: And flush the tasklet before the engines, as the tasklet may
> > re-attach an rb_node after our removal from the siblings.
> >
> > Signed-off-by: Chris Wilson 
> > Cc: Tvrtko Ursulin 
> > ---
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 61 
> > +
> > 1 file changed, 54 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
> > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 17cb7060eb29..c11433884cf6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -182,6 +182,7 @@
> > struct virtual_engine {
> > struct intel_engine_cs base;
> > struct intel_context context;
> > + struct rcu_work rcu;
> > 
> > /*
> >  * We allow only a single request through the virtual engine at 
> > a time
> > @@ -5470,44 +5471,90 @@ static struct list_head *virtual_queue(struct 
> > virtual_engine *ve)
> > return >base.execlists.default_priolist.requests[0];
> > }
> > 
> > -static void virtual_context_destroy(struct kref *kref)
> > +static void rcu_virtual_context_destroy(struct work_struct *wrk)
> > {
> > struct virtual_engine *ve =
> > - container_of(kref, typeof(*ve), context.ref);
> > + container_of(wrk, typeof(*ve), rcu.work);
> > unsigned int n;
> > 
> > - GEM_BUG_ON(!list_empty(virtual_queue(ve)));
> > - GEM_BUG_ON(ve->request);
> > GEM_BUG_ON(ve->context.inflight);
> > 
> > + /* Preempt-to-busy may leave a stale request behind. */
> > + if (unlikely(ve->request)) {
> > + struct i915_request *old;
> > +
> > + spin_lock_irq(>base.active.lock);
> > +
> > + old = fetch_and_zero(>request);
> > + if (old) {
> > + GEM_BUG_ON(!i915_request_completed(old));
> > + __i915_request_submit(old);
> > + i915_request_put(old);
> > + }
> > +
> > + spin_unlock_irq(>base.active.lock);
> > + }
> > +
> > + /*
> > +  * Flush the tasklet in case it is still running on another core.
> > +  *
> > +  * This needs to be done before we remove ourselves from the 
> > siblings'
> > +  * rbtrees as in the case it is running in parallel, it may 
> > reinsert
> > +  * the rb_node into a sibling.
> > +  */
> > + tasklet_kill(>base.execlists.tasklet);
> 
>  Can it still be running after an RCU period?
> >>>
> >>> I think there is a window between checking to see if the request is
> >>> completed and kicking the tasklet, that is not under the rcu lock and
> >>> opportunity for the request to be retired, and barrier flushed to drop
> >>> the context references.
> >>
> >>   From where would that check come?
> > 
> > The window of opportunity extends all the way from the
> > i915_request_completed check during unsubmit right until the virtual
> > engine tasklet is executed -- we do not hold a reference to the virtual
> > engine for the tasklet, and that request may be retired in the
> > background, and along with it the virtual engine destroyed.
> 
> In this case aren't sibling tasklets also a problem?

The next stanza decouples the siblings. At this point, we know that the
request must have been completed (to retire and drop the context
reference) so at this point nothing should be allowed to kick the
virtual engine tasklet, it's just the outstanding execution we need to
serialise. So the following assertion that nothing did kick the tasklet
as we decoupled the siblings holds. After that assertion, there should
be nothing else that knows about the virtual tasklet.
-Chris

Re: [Intel-gfx] [PATCH 14/28] drm/i915/gt: Free stale request on destroying the virtual engine

[Tvrtko Ursulin]

On 18/11/2020 12:10, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2020-11-18 11:38:43)


On 18/11/2020 11:24, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2020-11-18 11:05:24)


On 17/11/2020 11:30, Chris Wilson wrote:

Since preempt-to-busy, we may unsubmit a request while it is still on
the HW and completes asynchronously. That means it may be retired and in
the process destroy the virtual engine (as the user has closed their
context), but that engine may still be holding onto the unsubmitted
compelted request. Therefore we need to potentially cleanup the old
request on destroying the virtual engine. We also have to keep the
virtual_engine alive until after the sibling's execlists_dequeue() have
finished peeking into the virtual engines, for which we serialise with
RCU.

v2: Be paranoid and flush the tasklet as well.
v3: And flush the tasklet before the engines, as the tasklet may
re-attach an rb_node after our removal from the siblings.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 61 +
1 file changed, 54 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 17cb7060eb29..c11433884cf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -182,6 +182,7 @@
struct virtual_engine {
struct intel_engine_cs base;
struct intel_context context;
+ struct rcu_work rcu;

/*

 * We allow only a single request through the virtual engine at a time
@@ -5470,44 +5471,90 @@ static struct list_head *virtual_queue(struct 
virtual_engine *ve)
return >base.execlists.default_priolist.requests[0];
}

-static void virtual_context_destroy(struct kref *kref)

+static void rcu_virtual_context_destroy(struct work_struct *wrk)
{
struct virtual_engine *ve =
- container_of(kref, typeof(*ve), context.ref);
+ container_of(wrk, typeof(*ve), rcu.work);
unsigned int n;

- GEM_BUG_ON(!list_empty(virtual_queue(ve)));

- GEM_BUG_ON(ve->request);
GEM_BUG_ON(ve->context.inflight);

+ /* Preempt-to-busy may leave a stale request behind. */

+ if (unlikely(ve->request)) {
+ struct i915_request *old;
+
+ spin_lock_irq(>base.active.lock);
+
+ old = fetch_and_zero(>request);
+ if (old) {
+ GEM_BUG_ON(!i915_request_completed(old));
+ __i915_request_submit(old);
+ i915_request_put(old);
+ }
+
+ spin_unlock_irq(>base.active.lock);
+ }
+
+ /*
+  * Flush the tasklet in case it is still running on another core.
+  *
+  * This needs to be done before we remove ourselves from the siblings'
+  * rbtrees as in the case it is running in parallel, it may reinsert
+  * the rb_node into a sibling.
+  */
+ tasklet_kill(>base.execlists.tasklet);


Can it still be running after an RCU period?


I think there is a window between checking to see if the request is
completed and kicking the tasklet, that is not under the rcu lock and
opportunity for the request to be retired, and barrier flushed to drop
the context references.


  From where would that check come?


The window of opportunity extends all the way from the
i915_request_completed check during unsubmit right until the virtual
engine tasklet is executed -- we do not hold a reference to the virtual
engine for the tasklet, and that request may be retired in the
background, and along with it the virtual engine destroyed.


In this case aren't sibling tasklets also a problem?

Regards,

Tvrtko
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Whitespace cleanups

[Patchwork]

== Series Details ==

Series: drm/i915/display: Whitespace cleanups
URL   : https://patchwork.freedesktop.org/series/84054/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9360 -> Patchwork_18939


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18939 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18939, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_18939:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_suspend@basic-s0:
- fi-glk-dsi: NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-glk-dsi/igt@gem_exec_susp...@basic-s0.html

  
New tests
-

  New tests have been introduced between CI_DRM_9360 and Patchwork_18939:

### New CI tests (1) ###

  * boot:
- Statuses : 1 fail(s) 39 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18939 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0:
- fi-apl-guc: [PASS][2] -> [DMESG-WARN][3] ([i915#1635] / 
[i915#62]) +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html

  * igt@gem_tiled_pread_basic:
- fi-tgl-y:   [PASS][4] -> [DMESG-WARN][5] ([i915#402])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-tgl-y/igt@gem_tiled_pread_basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-tgl-y/igt@gem_tiled_pread_basic.html

  * igt@i915_module_load@reload:
- fi-byt-j1900:   [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) +1 similar 
issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-byt-j1900/igt@i915_module_l...@reload.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-byt-j1900/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-apl-guc: [PASS][8] -> [DMESG-WARN][9] ([i915#1635] / 
[i915#1982])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
- fi-kbl-soraka:  [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-kbl-soraka/igt@kms_busy@ba...@flip.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka:   [PASS][12] -> [DMESG-WARN][13] ([i915#1982])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-tgl-y:   [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@gem_ctx_exec@basic:
- fi-tgl-y:   [DMESG-WARN][16] ([i915#1982]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-tgl-y/igt@gem_ctx_e...@basic.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-tgl-y/igt@gem_ctx_e...@basic.html

  * igt@gem_flink_basic@double-flink:
- fi-tgl-y:   [DMESG-WARN][18] ([i915#402]) -> [PASS][19] +2 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-tgl-y/igt@gem_flink_ba...@double-flink.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-tgl-y/igt@gem_flink_ba...@double-flink.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-ehl-1}: [DMESG-WARN][20] ([i915#1982]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18939/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2:  

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Whitespace cleanups

[Patchwork]

== Series Details ==

Series: drm/i915/display: Whitespace cleanups
URL   : https://patchwork.freedesktop.org/series/84054/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fa13fd9ed600 drm/i915/display: Whitespace cleanups
-:45: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#45: FILE: drivers/gpu/drm/i915/display/intel_display.c:15370:
+   slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;

-:46: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#46: FILE: drivers/gpu/drm/i915/display/intel_display.c:15371:
+   slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave 
= false;

-:47: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#47: FILE: drivers/gpu/drm/i915/display/intel_display.c:15372:
+   slave_crtc_state->bigjoiner_linked_crtc = 
master_crtc_state->bigjoiner_linked_crtc = NULL;

total: 0 errors, 0 warnings, 3 checks, 43 lines checked


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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/lspcon: enter standby mode to enhance power saving (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/lspcon: enter standby mode to enhance power saving (rev4)
URL   : https://patchwork.freedesktop.org/series/83886/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9360 -> Patchwork_18938


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18938 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18938, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_18938:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_suspend@basic-s0:
- fi-glk-dsi: NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-glk-dsi/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_selftest@live@hugepages:
- fi-cfl-8109u:   NOTRUN -> [DMESG-FAIL][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-cfl-8109u/igt@i915_selftest@l...@hugepages.html

  
New tests
-

  New tests have been introduced between CI_DRM_9360 and Patchwork_18938:

### New CI tests (1) ###

  * boot:
- Statuses : 1 fail(s) 39 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18938 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_module_load@reload:
- fi-byt-j1900:   [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-byt-j1900/igt@i915_module_l...@reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-byt-j1900/igt@i915_module_l...@reload.html
- fi-bsw-n3050:   [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-bsw-n3050/igt@i915_module_l...@reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-bsw-n3050/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-7500u:   [PASS][7] -> [SKIP][8] ([fdo#109271])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-kbl-7500u/igt@i915_pm_...@basic-pci-d3-state.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-kbl-7500u/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka:  [PASS][9] -> [DMESG-FAIL][10] ([i915#541])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
- fi-tgl-y:   [PASS][11] -> [DMESG-FAIL][12] ([i915#2601] / 
[i915#541])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2:  [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][15] -> [FAIL][16] ([i915#227])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka:   [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-icl-u2:  [PASS][19] -> [DMESG-WARN][20] ([i915#1982])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9360/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18938/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html

  * igt@prime_self_import@basic-with_one_bo:
- fi-tgl-y:   [PASS][21] -> [DMESG-WARN][22] ([i915#402]) +1 
similar issue
   [21]: 

Re: [Intel-gfx] [PATCH v2] drm/i915/gt: Update request status flags for debug pretty-printer

[Chris Wilson]

Quoting Tvrtko Ursulin (2020-11-19 13:18:10)
> 
> On 19/11/2020 12:24, Chris Wilson wrote:
> > We plan to expand upon the number of available statuses for when we
> > pretty-print the requests along the timelines, and so need a new set of
> > flags. We have settled upon:
> > 
> >   Unready [U]
> > - initial status after being submitted, the request is not
> >   ready for execution as it is waiting for external fences
> > 
> >   Ready [R]
> > - all fences the request was waiting on have been signaled,
> >  and the request is now ready for execution and will be
> >   in a backend queue
> > 
> > - a ready request may still need to wait on semaphores
> >   [internal fences]
> > 
> >   Ready/virtual [V]
> > - same as ready, but queued over multiple backends
> > 
> 
> You do not like my idea of R/Rv? I think it would be more intuitive, but 
> anyway patch looks good.

Started with Rv, but then thought restricting it to a single character
and constant width was more important for the vertical alignment. That
may not be that much of an issue in practice. ~o~
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915/gt: Update request status flags for debug pretty-printer

[Tvrtko Ursulin]

On 19/11/2020 12:24, Chris Wilson wrote:

We plan to expand upon the number of available statuses for when we
pretty-print the requests along the timelines, and so need a new set of
flags. We have settled upon:

Unready [U]
  - initial status after being submitted, the request is not
ready for execution as it is waiting for external fences

Ready [R]
  - all fences the request was waiting on have been signaled,
 and the request is now ready for execution and will be
in a backend queue

  - a ready request may still need to wait on semaphores
[internal fences]

Ready/virtual [V]
  - same as ready, but queued over multiple backends



You do not like my idea of R/Rv? I think it would be more intuitive, but 
anyway patch looks good.


Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko


Executing [E]
  - the request has been transferred from the backend queue and
submitted for execution on HW

  - a completed request may still be regarded as executing, its
status may not be updated until it is retired and removed
from the lists

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c |  6 +-
  drivers/gpu/drm/i915/gt/intel_lrc.c   | 15 ++--
  drivers/gpu/drm/i915/gt/intel_lrc.h   |  3 +-
  drivers/gpu/drm/i915/i915_request.c   | 85 +++
  drivers/gpu/drm/i915/i915_request.h   |  3 +-
  5 files changed, 88 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c3bb2e9546e6..d4e988b2816a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1491,7 +1491,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
intel_context_is_banned(rq->context) ? "*" : 
"");
len += print_ring(hdr + len, sizeof(hdr) - len, rq);
scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
-   i915_request_show(m, rq, hdr);
+   i915_request_show(m, rq, hdr, 0);
}
for (port = execlists->pending; (rq = *port); port++) {
char hdr[160];
@@ -1505,7 +1505,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
intel_context_is_banned(rq->context) ? "*" : 
"");
len += print_ring(hdr + len, sizeof(hdr) - len, rq);
scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
-   i915_request_show(m, rq, hdr);
+   i915_request_show(m, rq, hdr, 0);
}
rcu_read_unlock();
execlists_active_unlock_bh(execlists);
@@ -1649,7 +1649,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (rq) {
struct intel_timeline *tl = get_timeline(rq);
  
-		i915_request_show(m, rq, "\t\tactive ");

+   i915_request_show(m, rq, "\t\tactive ", 0);
  
  		drm_printf(m, "\t\tring->start:  0x%08x\n",

   i915_ggtt_offset(rq->ring->vma));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b6ab1161942a..5257f3c71366 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -5982,7 +5982,8 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
   struct drm_printer *m,
   void (*show_request)(struct drm_printer *m,
const struct 
i915_request *rq,
-   const char *prefix),
+   const char *prefix,
+   int indent),
   unsigned int max)
  {
const struct intel_engine_execlists *execlists = >execlists;
@@ -5997,7 +5998,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
count = 0;
list_for_each_entry(rq, >active.requests, sched.link) {
if (count++ < max - 1)
-   show_request(m, rq, "\t\tE ");
+   show_request(m, rq, "\t\t", 0);
else
last = rq;
}
@@ -6007,7 +6008,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
   "\t\t...skipping %d executing requests...\n",
   count - max);
}
-   show_request(m, last, "\t\tE ");
+   show_request(m, last, "\t\t", 0);
}
  
  	if (execlists->switch_priority_hint 

[Intel-gfx] [PATCH v2] drm/i915/gt: Update request status flags for debug pretty-printer

[Chris Wilson]

We plan to expand upon the number of available statuses for when we
pretty-print the requests along the timelines, and so need a new set of
flags. We have settled upon:

Unready [U]
  - initial status after being submitted, the request is not
ready for execution as it is waiting for external fences

Ready [R]
  - all fences the request was waiting on have been signaled,
and the request is now ready for execution and will be
in a backend queue

  - a ready request may still need to wait on semaphores
[internal fences]

Ready/virtual [V]
  - same as ready, but queued over multiple backends

Executing [E]
  - the request has been transferred from the backend queue and
submitted for execution on HW

  - a completed request may still be regarded as executing, its
status may not be updated until it is retired and removed
from the lists

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  6 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c   | 15 ++--
 drivers/gpu/drm/i915/gt/intel_lrc.h   |  3 +-
 drivers/gpu/drm/i915/i915_request.c   | 85 +++
 drivers/gpu/drm/i915/i915_request.h   |  3 +-
 5 files changed, 88 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c3bb2e9546e6..d4e988b2816a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1491,7 +1491,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
intel_context_is_banned(rq->context) ? 
"*" : "");
len += print_ring(hdr + len, sizeof(hdr) - len, rq);
scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
-   i915_request_show(m, rq, hdr);
+   i915_request_show(m, rq, hdr, 0);
}
for (port = execlists->pending; (rq = *port); port++) {
char hdr[160];
@@ -1505,7 +1505,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
intel_context_is_banned(rq->context) ? 
"*" : "");
len += print_ring(hdr + len, sizeof(hdr) - len, rq);
scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
-   i915_request_show(m, rq, hdr);
+   i915_request_show(m, rq, hdr, 0);
}
rcu_read_unlock();
execlists_active_unlock_bh(execlists);
@@ -1649,7 +1649,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (rq) {
struct intel_timeline *tl = get_timeline(rq);
 
-   i915_request_show(m, rq, "\t\tactive ");
+   i915_request_show(m, rq, "\t\tactive ", 0);
 
drm_printf(m, "\t\tring->start:  0x%08x\n",
   i915_ggtt_offset(rq->ring->vma));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b6ab1161942a..5257f3c71366 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -5982,7 +5982,8 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
   struct drm_printer *m,
   void (*show_request)(struct drm_printer *m,
const struct 
i915_request *rq,
-   const char *prefix),
+   const char *prefix,
+   int indent),
   unsigned int max)
 {
const struct intel_engine_execlists *execlists = >execlists;
@@ -5997,7 +5998,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
count = 0;
list_for_each_entry(rq, >active.requests, sched.link) {
if (count++ < max - 1)
-   show_request(m, rq, "\t\tE ");
+   show_request(m, rq, "\t\t", 0);
else
last = rq;
}
@@ -6007,7 +6008,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
   "\t\t...skipping %d executing requests...\n",
   count - max);
}
-   show_request(m, last, "\t\tE ");
+   show_request(m, last, "\t\t", 0);
}
 
if (execlists->switch_priority_hint != INT_MIN)
@@ -6025,7 +6026,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
 
priolist_for_each_request(rq, p, i) {
  

Re: [Intel-gfx] [PATCH v2 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder

[Shankar, Uma]

> -Original Message-
> From: Nautiyal, Ankit K 
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2 
> Subject: [PATCH v2 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON
> encoder
> 
> This patch adds support to read and store the DSC capabilities of the
> HDMI2.1 PCon encoder. It also adds a new field to store these caps, The caps 
> are
> read during dfp update and can later be used to get the PPS parameters for
> PCON-HDMI2.1 sink pair. Which inturn will be used to take a call to override 
> the
> existing PPS-metadata, by either writing the entire new PPS metadata, or by
> writing only the PPS override parameters.
> 
> v2: Restructured the code to read all capability DPCDs at once and store in an
> array in intel_dp structure.
> 
> Signed-off-by: Ankit Nautiyal 
> ---
>  .../drm/i915/display/intel_display_types.h|  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c   | 20 +++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2c58d63928b8..f43ded030c14 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1309,6 +1309,7 @@ struct intel_dp {
>   u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
>   u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
>   u8 fec_capable;
> + u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
>   /* source rates */
>   int num_source_rates;
>   const int *source_rates;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6177169c4401..2e7ddb062efe 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3869,6 +3869,24 @@ cpt_set_link_train(struct intel_dp *intel_dp,
>   intel_de_posting_read(dev_priv, intel_dp->output_reg);  }
> 
> +static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) {
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + /* Clear the cached register set to avoid using stale values */
> +

Drop this extra line. With this fixed
Reviewed-by: Uma Shankar 

> + memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
> +
> + if (drm_dp_dpcd_read(_dp->aux, DP_PCON_DSC_ENCODER,
> +  intel_dp->pcon_dsc_dpcd,
> +  sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
> + drm_err(>drm, "Failed to read DPCD register 0x%x\n",
> + DP_PCON_DSC_ENCODER);
> +
> + drm_dbg_kms(>drm, "PCON ENCODER DSC DPCD: %*ph\n",
> +(int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp-
> >pcon_dsc_dpcd); }
> +
>  static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp)  {
>   int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps; @@ -
> 6645,6 +6663,8 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
>   intel_dp->dfp.max_tmds_clock,
>   intel_dp->dfp.pcon_max_frl_bw,
>   intel_dp->dfp.sink_max_frl_bw);
> +
> + intel_dp_get_pcon_dsc_cap(intel_dp);
>  }
> 
>  static void
> --
> 2.17.1

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Re: [Intel-gfx] [PATCH v2 10/13] drm/i915: Add support for enabling link status and recovery

[Shankar, Uma]

> -Original Message-
> From: Nautiyal, Ankit K 
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2 
> Subject: [PATCH v2 10/13] drm/i915: Add support for enabling link status and
> recovery
> 
> From: Swati Sharma 
> 
> In this patch enables support for detecting link failures between PCON and 
> HDMI
> sink in i915 driver. HDMI link loss indication to upstream DP source is 
> indicated
> via IRQ_HPD. This is followed by reading of HDMI link configuration status
> (HDMI_TX_LINK_ACTIVE_STATUS).
> If the PCON → HDMI 2.1 link status is off; reinitiate frl link training to 
> recover.
> Also, report HDMI FRL link error count range for each individual FRL active 
> lane is
> indicated by DOWNSTREAM_HDMI_ERROR_STATUS_LN registers.
> 
> v2: Checked for dpcd read and write failures and added debug message.
> (Uma Shankar)

Reviewed-by: Uma Shankar 

> Signed-off-by: Swati Sharma 
> Signed-off-by: Ankit Nautiyal 
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 56 +++--
>  1 file changed, 53 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9047b620c0d0..6177169c4401 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5932,6 +5932,31 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
>   return link_ok;
>  }
> 
> +static void
> +intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) {
> + bool is_active;
> + u8 buf = 0;
> +
> + is_active = drm_dp_pcon_hdmi_link_active(_dp->aux);
> + if (intel_dp->frl.is_trained && !is_active) {
> + if (drm_dp_dpcd_readb(_dp->aux,
> DP_PCON_HDMI_LINK_CONFIG_1, ) < 0)
> + return;
> +
> + buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
> + if (drm_dp_dpcd_writeb(_dp->aux,
> DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
> + return;
> +
> + drm_dp_pcon_hdmi_frl_link_error_count(_dp->aux,
> +_dp->attached_connector->base);
> +
> + intel_dp->frl.is_trained = false;
> + intel_dp->frl.trained_rate_gbps = 0;
> +
> + /* Restart FRL training or fall back to TMDS mode */
> + intel_dp_check_frl_training(intel_dp);
> + }
> +}
> +
>  static bool
>  intel_dp_needs_link_retrain(struct intel_dp *intel_dp)  { @@ -6297,7 +6322,7
> @@ intel_dp_hotplug(struct intel_encoder *encoder,
>   return state;
>  }
> 
> -static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
> +static void intel_dp_check_device_service_irq(struct intel_dp
> +*intel_dp)
>  {
>   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>   u8 val;
> @@ -6321,6 +6346,30 @@ static void intel_dp_check_service_irq(struct intel_dp
> *intel_dp)
>   drm_dbg_kms(>drm, "Sink specific irq unhandled\n");  }
> 
> +static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + u8 val;
> +
> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
> + return;
> +
> + if (drm_dp_dpcd_readb(_dp->aux,
> +   DP_LINK_SERVICE_IRQ_VECTOR_ESI0, ) != 1 ||
> !val) {
> + drm_dbg_kms(>drm, "Error in reading link service irq
> vector\n");
> + return;
> + }
> +
> + if (drm_dp_dpcd_writeb(_dp->aux,
> +DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
> + drm_dbg_kms(>drm, "Error in writing link service irq
> vector\n");
> + return;
> + }
> +
> + if (val & HDMI_LINK_STATUS_CHANGED)
> + intel_dp_handle_hdmi_link_status_change(intel_dp);
> +}
> +
>  /*
>   * According to DP spec
>   * 5.1.2:
> @@ -6360,7 +6409,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
>   return false;
>   }
> 
> - intel_dp_check_service_irq(intel_dp);
> + intel_dp_check_device_service_irq(intel_dp);
> + intel_dp_check_link_service_irq(intel_dp);
> 
>   /* Handle CEC interrupts, if any */
>   drm_dp_cec_irq(_dp->aux);
> @@ -6794,7 +6844,7 @@ intel_dp_detect(struct drm_connector *connector,
>   to_intel_connector(connector)->detect_edid)
>   status = connector_status_connected;
> 
> - intel_dp_check_service_irq(intel_dp);
> + intel_dp_check_device_service_irq(intel_dp);
> 
>  out:
>   if (status != connector_status_connected && !intel_dp->is_mst)
> --
> 2.17.1

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Re: [Intel-gfx] [PATCH v2 09/13] drm/i915: Check for FRL training before DP Link training

[Shankar, Uma]

> -Original Message-
> From: Nautiyal, Ankit K 
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2 
> Subject: [PATCH v2 09/13] drm/i915: Check for FRL training before DP Link
> training
> 
> This patch calls functions to check FRL training requirements for an HDMI2.1 
> sink,
> when connected through PCON.
> The call is made before the DP link training. In case FRL is not required or 
> failure
> during FRL training, the TMDS mode is selected for the pcon.
> 
> v2: moved check_frl_training() just after FEC READY, before starting DP link
> training.

Reviewed-by: Uma Shankar 

> Signed-off-by: Ankit Nautiyal 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
> drivers/gpu/drm/i915/display/intel_dp.c  | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 09811be08cfe..3e76fb1117df 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3492,6 +3492,8 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
>*/
>   intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> 
> + intel_dp_check_frl_training(intel_dp);
> +
>   /*
>* 7.i Follow DisplayPort specification training sequence (see notes for
>* failure handling)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7feee2adf9b2..9047b620c0d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4183,6 +4183,7 @@ static void intel_enable_dp(struct intel_atomic_state
> *state,
> 
>   intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
>   intel_dp_configure_protocol_converter(intel_dp);
> + intel_dp_check_frl_training(intel_dp);
>   intel_dp_start_link_train(intel_dp, pipe_config);
>   intel_dp_stop_link_train(intel_dp, pipe_config);
> 
> @@ -6104,6 +6105,7 @@ int intel_dp_retrain_link(struct intel_encoder
> *encoder,
>   !intel_dp_mst_is_master_trans(crtc_state))
>   continue;
> 
> + intel_dp_check_frl_training(intel_dp);
>   intel_dp_start_link_train(intel_dp, crtc_state);
>   intel_dp_stop_link_train(intel_dp, crtc_state);
>   break;
> --
> 2.17.1

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[Intel-gfx] [PATCH] drm/i915/gt: Update request status flags for debug pretty-printer

[Chris Wilson]

We plan to expand upon the number of available statuses for when we
pretty-print the requests along the timelines, and so need a new set of
flags. We have settled upon:

Unready [U]
  - initial status after being submitted, the request is not
ready for execution as it is waiting for external fences

Ready [R]
  - all fences the request was waiting on have been signaled,
and the request is now ready for execution and will be
in a backend queue

  - a ready request may still need to wait on semaphores
[internal fences]

Ready/virtual [V]
  - same as ready, but queued over multiple backends

Executing [E]
  - the request has been transferred from the backend queue and
submitted for execution on HW

  - a completed request may still be regarded as executing, its
status may not be updated until it is retired and removed
from the lists

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c |  4 ++--
 drivers/gpu/drm/i915/i915_request.c | 30 +
 2 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b6ab1161942a..3a1b25c0e43e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -6025,7 +6025,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
 
priolist_for_each_request(rq, p, i) {
if (count++ < max - 1)
-   show_request(m, rq, "\t\tQ ");
+   show_request(m, rq, "\t\tR ");
else
last = rq;
}
@@ -6036,7 +6036,7 @@ void intel_execlists_show_requests(struct intel_engine_cs 
*engine,
   "\t\t...skipping %d queued requests...\n",
   count - max);
}
-   show_request(m, last, "\t\tQ ");
+   show_request(m, last, "\t\tR ");
}
 
last = NULL;
diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 673991718ae6..d3610418e9ae 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1875,6 +1875,36 @@ void i915_request_show(struct drm_printer *m,
char buf[80] = "";
int x = 0;
 
+   /*
+* Often the prefix is used to show the queue status,
+* in which case we use the following flags:
+*
+*  Unready [U]
+*- initial status upon being submitted by the user
+*
+*- the request is not ready for execution as it is waiting
+*  for external fences
+*
+*  Ready [R]
+*- all fences the request was waiting on have been signaled,
+*  and the request is now ready for execution and will be
+*  in a backend queue
+*
+*- a ready request may still need to wait on semaphores
+*  [internal fences]
+*
+*  Ready/virtual [V]
+*- same as ready, but queued over multiple backends
+*
+*  Executing [E]
+*- the request has been transferred from the backend queue and
+*  submitted for execution on HW
+*
+*- a completed request may still be regarded as executing, its
+*  status may not be updated until it is retired and removed
+*  from the lists
+*/
+
x = print_sched_attr(>sched.attr, buf, x, sizeof(buf));
 
drm_printf(m, "%s %llx:%lld%s%s %s @ %dms: %s\n",
-- 
2.20.1

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Re: [Intel-gfx] [PATCH 8/8] drm/i915/perf: Map OA buffer to user space for gen12 performance query

[Maciejewski, Piotr]

Hi,

Indeed, we use i915 perf changes introduced by Umesh within Metrics Library (a 
common library used to obtain performance counters from various operating 
systems and graphics api).

Metrics Library repo: https://github.com/intel/metrics-library  
Io controls usage: 
https://github.com/intel/metrics-library/blob/master/instrumentation/metrics_library/traits/kernel_interface/linux/ml_io_control.h
 
Tbs usage: 
https://github.com/intel/metrics-library/blob/master/instrumentation/metrics_library/traits/kernel_interface/linux/ml_tbs_interface.h
 

Piotr

-Original Message-
From: Lionel Landwerlin  
Sent: Wednesday, November 18, 2020 12:57 PM
To: Joonas Lahtinen ; Chris Wilson 
; intel-gfx@lists.freedesktop.org; Nerlige Ramappa, 
Umesh 
Cc: Maciejewski, Piotr 
Subject: Re: [Intel-gfx] [PATCH 8/8] drm/i915/perf: Map OA buffer to user space 
for gen12 performance query

Tests are on the IGT ml : 
https://patchwork.freedesktop.org/series/82352/


This feature was requested by the metrics-discovery team.
Pretty sure this was tested with it, maybe a branch can be shared by Piotr?

Cheers,

-Lionel

On 18/11/2020 13:41, Joonas Lahtinen wrote:
> + Umesh, Lionel
>
> Do we have a link to the userspace changes and IGT tests? Those are 
> absolutely needed before we can do a final review and merge.
>
> We should really test and review the kernel and userspace changes 
> together to make sure that we're coming up with a solid uAPI.
>
> Regards, Joonas
>
> Quoting Chris Wilson (2020-11-17 13:01:32)
>> From: Umesh Nerlige Ramappa 
>>
>> i915 used to support time based sampling mode which is good for 
>> overall system monitoring, but is not enough for query mode used to 
>> measure a single draw call or dispatch. Gen9-Gen11 are using current 
>> i915 perf implementation for query, but Gen12+ requires a new 
>> approach for query based on triggered reports within oa buffer.
>>
>> Triggering reports into the OA buffer is achieved by writing into a a 
>> trigger register. Optionally an unused counter/register is set with a 
>> marker value such that a triggered report can be identified in the OA 
>> buffer. Reports are usually triggered at the start and end of work 
>> that is measured.
>>
>> Since OA buffer is large and queries can be frequent, an efficient 
>> way to look for triggered reports is required. By knowing the current 
>> head and tail offsets into the OA buffer, it is easier to determine 
>> the locality of the reports of interest.
>>
>> Current perf OA interface does not expose head/tail information to 
>> the user and it filters out invalid reports before sending data to user.
>> Also considering limited size of user buffer used during a query, 
>> creating a 1:1 copy of the OA buffer at the user space added 
>> undesired complexity.
>>
>> The solution was to map the OA buffer to user space provided
>>
>> (1) that it is accessed from a privileged user.
>> (2) OA report filtering is not used.
>>
>> These 2 conditions would satisfy the safety criteria that the current 
>> perf interface addresses.
>>
>> To enable the query:
>> - Add an ioctl to expose head and tail to the user
>> - Add an ioctl to return size and offset of the OA buffer
>> - Map the OA buffer to the user space
>>
>> v2:
>> - Improve commit message (Chris)
>> - Do not mmap based on gem object filp. Instead, use perf_fd and support
>>mmap syscall (Chris)
>> - Pass non-zero offset in mmap to enforce the right object is
>>mapped (Chris)
>> - Do not expose gpu_address (Chris)
>> - Verify start and length of vma for page alignment (Lionel)
>> - Move SQNTL config out (Lionel)
>>
>> v3: (Chris)
>> - Omit redundant checks
>> - Return VM_FAULT_SIGBUS is old stream is closed
>> - Maintain reference counts to stream in vm_open and vm_close
>> - Use switch to identify object to be mapped
>>
>> v4: Call kref_put on closing perf fd (Chris)
>> v5:
>> - Strip access to OA buffer from unprivileged child of a privileged
>>parent. Use VM_DONTCOPY
>> - Enforce MAP_PRIVATE by checking for VM_MAYSHARE
>>
>> v6:
>> (Chris)
>> - Use len of -1 in unmap_mapping_range
>> - Don't use stream->oa_buffer.vma->obj in vm_fault_oa
>> - Use kernel block comment style
>> - do_mmap gets a reference to the file and puts it in do_munmap, so
>>no need to maintain a reference to i915_perf_stream. Hence, remove
>>vm_open/vm_close and stream->closed hooks/checks.
>> (Umesh)
>> - Do not allow mmap if SAMPLE_OA_REPORT is not set during
>>i915_perf_open_ioctl.
>> - Drop ioctl returning head/tail since this information is already
>>whitelisted. Remove hooks to read head register.
>>
>> v7: (Chris)
>> - unmap before destroy
>> - change ioctl argument struct
>>
>> v8: Documentation and more checks (Chris)
>>
>> Signed-off-by: Piotr Maciejewski 
>> Signed-off-by: Umesh Nerlige Ramappa 
>> 
>> Reviewed-by: Chris Wilson 
>> ---
>>   drivers/gpu/drm/i915/gem/i915_gem_mman.c |   2 +-
>>   

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Do not call hsw_set_frame_start_delay for dsi

[Patchwork]

== Series Details ==

Series: drm/i915: Do not call hsw_set_frame_start_delay for dsi
URL   : https://patchwork.freedesktop.org/series/84039/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/display/intel_display.o
drivers/gpu/drm/i915/display/intel_display.c: In function ‘hsw_crtc_enable’:
drivers/gpu/drm/i915/display/intel_display.c:7223:3: error: this ‘if’ clause 
does not guard... [-Werror=misleading-indentation]
   if (new_crtc_state->has_pch_encoder)
   ^~
drivers/gpu/drm/i915/display/intel_display.c:7227:4: note: ...this statement, 
but the latter is misleadingly indented as if it were guarded by the ‘if’
hsw_set_frame_start_delay(new_crtc_state);
^
cc1: all warnings being treated as errors
scripts/Makefile.build:283: recipe for target 
'drivers/gpu/drm/i915/display/intel_display.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_display.o] Error 1
scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:500: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1799: recipe for target 'drivers' failed
make: *** [drivers] Error 2


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Re: [Intel-gfx] [PATCH 08/28] drm/i915/gt: Show all active timelines for debugging

[Chris Wilson]

Quoting Tvrtko Ursulin (2020-11-18 15:51:41)
> 
> On 17/11/2020 13:25, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-11-17 12:59:44)
> >>
> >> On 17/11/2020 11:30, Chris Wilson wrote:
> >>> + if (show_request) {
> >>> + list_for_each_entry_safe(rq, rn, >requests, 
> >>> link)
> >>> + show_request(m, rq,
> >>> +  i915_request_is_active(rq) ? " 
> >>>  E" :
> >>> +  i915_request_is_ready(rq) ? "  
> >>> Q" :
> >>> +  "  U");
> >>
> >> Can we get some consistency between the category counts and flags.
> >>
> >> s/count/queued/ -> Q
> > 
> > Hmm, if you are sure. Q would then not match with the engine info.
> 
> Sure? Not really. What do we have there? You mean "!/*/+/-" flags? Or 
> "E/Q/V" from intel_execlists_show_requests? Right, 'Q' there means 
> runnable and it doesn't show queued at all. Yes, why not change everything.
> 
> > Still favouring count over queued; I think count indicates more clearly
> > that it is the superset, but queued may imply it excludes ready and
> > definitely sounds like it should not include inflight.
> 
> I am okay with that.
> 
> >> ready -> R (also matches with term runnable)
> >> active -> E ? hmmm E is consistent with the engine info dump.
> >>
> >> Not ideal but perhaps every bit of more consistency is good.
> > 
> > Not sold yet, but not happy with the current flags either.
> > 
> > If we go with 'R' for ready, we should also update engine info.
> 
> Okay we seem to have plenty of options.
> 
> U or Q - queued/unready
> R or Q - ready/queued (to backend) (Rv/Qv for virtual?)
> E or R, or I - executing/running/in-flight
> 
> Q -> R -> E
> U -> R -> E
> U -> Q -> E/R/I
> U -> R -> E/I
> 
> I don't know.. either one as long as all places use the same.

URE.

Unready -> ready -> executing.

Unready -> ready is a good pairing, and executing over inflight to avoid
being confused for an infection.

And unready opens up a plethora of jokes by just dropping the 'y'.
-Chris
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Re: [Intel-gfx] [PATCH v2 08/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON

[Shankar, Uma]

> -Original Message-
> From: Nautiyal, Ankit K 
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2 
> Subject: [PATCH v2 08/13] drm/i915: Add support for starting FRL training for
> HDMI2.1 via PCON
> 
> This patch adds functions to start FRL training for an HDMI2.1 sink, 
> connected via
> a PCON as a DP branch device.
> This patch also adds a new structure for storing frl training related data, 
> when
> FRL training is completed.
> 
> v2: As suggested by Uma Shankar:
> -renamed couple of variables for better clarity -tweaked the macros used for
> correct semantics for true/false -fixed other styling issues.

Reviewed-by: Uma Shankar 

> Signed-off-by: Ankit Nautiyal 
> ---
>  .../drm/i915/display/intel_display_types.h|   7 +
>  drivers/gpu/drm/i915/display/intel_dp.c   | 189 ++
>  drivers/gpu/drm/i915/display/intel_dp.h   |   2 +
>  3 files changed, 198 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 282c6ee76384..2c58d63928b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1286,6 +1286,11 @@ struct intel_dp_compliance {
>   u8 test_lane_count;
>  };
> 
> +struct intel_dp_pcon_frl {
> + bool is_trained;
> + int trained_rate_gbps;
> +};
> +
>  struct intel_dp {
>   i915_reg_t output_reg;
>   u32 DP;
> @@ -1407,6 +1412,8 @@ struct intel_dp {
> 
>   bool hobl_failed;
>   bool hobl_active;
> +
> + struct intel_dp_pcon_frl frl;
>  };
> 
>  enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index caf7666f1892..7feee2adf9b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2871,6 +2871,9 @@ static void intel_dp_prepare(struct intel_encoder
> *encoder,
>   intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
>   else
>   intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
> +
> + intel_dp->frl.is_trained = false;
> + intel_dp->frl.trained_rate_gbps = 0;
>   }
>  }
> 
> @@ -3769,6 +3772,8 @@ static void intel_disable_dp(struct intel_atomic_state
> *state,
>   intel_edp_backlight_off(old_conn_state);
>   intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
>   intel_edp_panel_off(intel_dp);
> + intel_dp->frl.is_trained = false;
> + intel_dp->frl.trained_rate_gbps = 0;
>  }
> 
>  static void g4x_disable_dp(struct intel_atomic_state *state, @@ -3864,6
> +3869,190 @@ cpt_set_link_train(struct intel_dp *intel_dp,
>   intel_de_posting_read(dev_priv, intel_dp->output_reg);  }
> 
> +static int intel_dp_get_max_rate_gbps(struct intel_dp *intel_dp) {
> + int max_link_clock, max_lanes, max_rate_khz, max_rate_gbps;
> +
> + max_link_clock = intel_dp_max_link_rate(intel_dp);
> + max_lanes = intel_dp_max_lane_count(intel_dp);
> + max_rate_khz = intel_dp_max_data_rate(max_link_clock, max_lanes);
> + max_rate_gbps = 8 * DIV_ROUND_UP(max_rate_khz, 100);
> +
> + return max_rate_gbps;
> +}
> +
> +static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) {
> + int bw_gbps[] = {9, 18, 24, 32, 40, 48};
> + int i;
> +
> + for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
> + if (frl_bw_mask & (1 << i))
> + return bw_gbps[i];
> + }
> + return 0;
> +}
> +
> +static int intel_dp_pcon_set_frl_mask(int max_frl) {
> +
> + switch (max_frl) {
> + case 48:
> + return DP_PCON_FRL_BW_MASK_48GBPS;
> + case 40:
> + return DP_PCON_FRL_BW_MASK_40GBPS;
> + case 32:
> + return DP_PCON_FRL_BW_MASK_32GBPS;
> + case 24:
> + return DP_PCON_FRL_BW_MASK_24GBPS;
> + case 18:
> + return DP_PCON_FRL_BW_MASK_18GBPS;
> + case 9:
> + return DP_PCON_FRL_BW_MASK_9GBPS;
> + }
> +
> + return 0;
> +}
> +
> +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) {
> + struct intel_connector *intel_connector = intel_dp->attached_connector;
> + struct drm_connector *connector = _connector->base;
> +
> + return (connector->display_info.hdmi.max_frl_rate_per_lane *
> + connector->display_info.hdmi.max_lanes);
> +}
> +
> +static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
> +{ #define PCON_EXTENDED_TRAIN_MODE (1 > 0) #define
> PCON_CONCURRENT_MODE
> +(1 > 0) #define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE #define
> +PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE #define
> +TIMEOUT_FRL_READY_MS 500 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
> +
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + int max_frl_bw, 

Re: [Intel-gfx] [PATCH v2 07/13] drm/i915: Capture max frl rate for PCON in dfp cap structure

[Shankar, Uma]

> -Original Message-
> From: Nautiyal, Ankit K 
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2 
> Subject: [PATCH v2 07/13] drm/i915: Capture max frl rate for PCON in dfp cap
> structure
> 
> HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and by the
> sink.
> 
> This patch captures these in dfp cap structure in intel_dp and uses these to
> prune connector modes that cannot be supported by the PCON and sink FRL
> bandwidth.
> 
> v2: Addressed review comments from Uma Shankar:
> -tweaked the comparison of target bw and pcon frl bw to avoid roundup errors.
> -minor modification of field names and comments.

Reviewed-by: Uma Shankar 

> Signed-off-by: Ankit Nautiyal 
> ---
>  .../drm/i915/display/intel_display_types.h|  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c   | 38 ++-
>  2 files changed, 37 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..282c6ee76384 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1397,6 +1397,7 @@ struct intel_dp {
>   struct {
>   int min_tmds_clock, max_tmds_clock;
>   int max_dotclock;
> + int pcon_max_frl_bw, sink_max_frl_bw;
>   u8 max_bpc;
>   bool ycbcr_444_to_420;
>   } dfp;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 818daab252f3..caf7666f1892 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -684,6 +684,29 @@ intel_dp_mode_valid_downstream(struct
> intel_connector *connector,
>   const struct drm_display_info *info = >base.display_info;
>   int tmds_clock;
> 
> + /*
> +  * If PCON and HDMI2.1 sink both support FRL MODE, check FRL
> +  * bandwidth constraints.
> +  */
> + if (intel_dp->dfp.pcon_max_frl_bw) {
> + int target_bw;
> + int max_frl_bw;
> + int bpp = intel_dp_mode_min_output_bpp(>base,
> mode);
> +
> + target_bw = bpp * target_clock;
> +
> + max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
> +  intel_dp->dfp.sink_max_frl_bw);
> +
> + /* converting bw from Gbps to Kbps*/
> + max_frl_bw = max_frl_bw * 100;
> +
> + if (target_bw > max_frl_bw)
> + return MODE_CLOCK_HIGH;
> +
> + return MODE_OK;
> + }
> +
>   if (intel_dp->dfp.max_dotclock &&
>   target_clock > intel_dp->dfp.max_dotclock)
>   return MODE_CLOCK_HIGH;
> @@ -6366,13 +6389,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
>intel_dp->downstream_ports,
>edid);
> 
> + intel_dp->dfp.pcon_max_frl_bw =
> + drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
> +intel_dp->downstream_ports);
> +
> + intel_dp->dfp.sink_max_frl_bw =
> +drm_dp_get_hdmi_sink_max_frl_bw(_dp->aux);
> +
>   drm_dbg_kms(>drm,
> - "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d,
> TMDS clock %d-%d\n",
> + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d,
> TMDS clock
> +%d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n",
>   connector->base.base.id, connector->base.name,
>   intel_dp->dfp.max_bpc,
>   intel_dp->dfp.max_dotclock,
>   intel_dp->dfp.min_tmds_clock,
> - intel_dp->dfp.max_tmds_clock);
> + intel_dp->dfp.max_tmds_clock,
> + intel_dp->dfp.pcon_max_frl_bw,
> + intel_dp->dfp.sink_max_frl_bw);
>  }
> 
>  static void
> @@ -6464,6 +6495,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
>   intel_dp->dfp.min_tmds_clock = 0;
>   intel_dp->dfp.max_tmds_clock = 0;
> 
> + intel_dp->dfp.pcon_max_frl_bw = 0;
> + intel_dp->dfp.sink_max_frl_bw = 0;
> +
>   intel_dp->dfp.ycbcr_444_to_420 = false;
>   connector->base.ycbcr_420_allowed = false;  }
> --
> 2.17.1

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Re: [Intel-gfx] [PATCH] drm/i915: Do not call hsw_set_frame_start_delay for dsi

[Hans de Goede]

Hi,

On 11/19/20 8:13 AM, Manasi Navare wrote:
> This should fix the boot oops for dsi
> 
> Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for 
> bigjoiner")
> Signed-off-by: Manasi Navare 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5c07c74d4397..739be96e998d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7211,7 +7211,7 @@ static void hsw_crtc_enable(struct intel_atomic_state 
> *state,
>   if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>   bdw_set_pipemisc(new_crtc_state);
>  
> - if (!new_crtc_state->bigjoiner_slave || 
> !transcoder_is_dsi(cpu_transcoder)) {
> + if (!new_crtc_state->bigjoiner_slave && 
> !transcoder_is_dsi(cpu_transcoder)) {
>   if (!transcoder_is_dsi(cpu_transcoder))

This condition is now always true so this nested if can be dropped now and the
code it guards can be executed unconditionally now (within the parent if).

Regards,

Hans



>   intel_set_transcoder_timings(new_crtc_state);
>  
> @@ -7224,7 +7224,7 @@ static void hsw_crtc_enable(struct intel_atomic_state 
> *state,
>   intel_cpu_transcoder_set_m_n(new_crtc_state,
>_crtc_state->fdi_m_n, 
> NULL);
>  
> - hsw_set_frame_start_delay(new_crtc_state);
> + hsw_set_frame_start_delay(new_crtc_state);
>   }
>  
>   if (!transcoder_is_dsi(cpu_transcoder))
> 

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Re: [Intel-gfx] [PATCH 4/6] ath11k: make relay callbacks const

[Jani Nikula]

On Wed, 18 Nov 2020, Jani Nikula  wrote:
> Now that relay_open() accepts const callbacks, make relay callbacks
> const.
>
> Cc: Kalle Valo 
> Cc: ath...@lists.infradead.org
> Signed-off-by: Jani Nikula 

Kalle, thanks for the acks on the other two ath patches - can I have
your ack on this one too please?

BR,
Jani.

> ---
>  drivers/net/wireless/ath/ath11k/spectral.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/wireless/ath/ath11k/spectral.c 
> b/drivers/net/wireless/ath/ath11k/spectral.c
> index ac2a8cfdc1c0..1afe67759659 100644
> --- a/drivers/net/wireless/ath/ath11k/spectral.c
> +++ b/drivers/net/wireless/ath/ath11k/spectral.c
> @@ -148,7 +148,7 @@ static int remove_buf_file_handler(struct dentry *dentry)
>   return 0;
>  }
>  
> -static struct rchan_callbacks rfs_scan_cb = {
> +static const struct rchan_callbacks rfs_scan_cb = {
>   .create_buf_file = create_buf_file_handler,
>   .remove_buf_file = remove_buf_file_handler,
>  };

-- 
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH] drm/i915/display: Whitespace cleanups

[Chris Wilson]

drivers/gpu/drm/i915/display/intel_display.c:3634 
intel_find_initial_plane_obj() warn: inconsistent indenting
drivers/gpu/drm/i915/display/intel_display.c:15367 kill_bigjoiner_slave() warn: 
inconsistent indenting

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/display/intel_display.c | 23 ++--
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 5c07c74d4397..1a0f00f37ca9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3631,8 +3631,8 @@ intel_find_initial_plane_obj(struct intel_crtc 
*intel_crtc,
struct intel_plane *intel_plane = to_intel_plane(primary);
struct intel_plane_state *intel_state =
to_intel_plane_state(plane_state);
-struct intel_crtc_state *crtc_state =
-to_intel_crtc_state(intel_crtc->base.state);
+   struct intel_crtc_state *crtc_state =
+   to_intel_crtc_state(intel_crtc->base.state);
struct drm_framebuffer *fb;
struct i915_vma *vma;
 
@@ -15361,17 +15361,17 @@ static int kill_bigjoiner_slave(struct 
intel_atomic_state *state,
struct intel_crtc_state *master_crtc_state)
 {
struct intel_crtc_state *slave_crtc_state =
-   intel_atomic_get_crtc_state(>base,
-   
master_crtc_state->bigjoiner_linked_crtc);
+   intel_atomic_get_crtc_state(>base,
+   
master_crtc_state->bigjoiner_linked_crtc);
 
-   if (IS_ERR(slave_crtc_state))
-   return PTR_ERR(slave_crtc_state);
+   if (IS_ERR(slave_crtc_state))
+   return PTR_ERR(slave_crtc_state);
 
-   slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = 
false;
-   slave_crtc_state->bigjoiner_slave = 
master_crtc_state->bigjoiner_slave = false;
-   slave_crtc_state->bigjoiner_linked_crtc = 
master_crtc_state->bigjoiner_linked_crtc = NULL;
-   intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
-   return 0;
+   slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
+   slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave 
= false;
+   slave_crtc_state->bigjoiner_linked_crtc = 
master_crtc_state->bigjoiner_linked_crtc = NULL;
+   intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
+   return 0;
 }
 
 /**
@@ -15949,7 +15949,6 @@ static void intel_update_crtc(struct intel_atomic_state 
*state,
intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
 }
 
-
 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
  struct intel_crtc_state 
*old_crtc_state,
  struct intel_crtc_state 
*new_crtc_state,
-- 
2.20.1

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[Intel-gfx] [PULL] drm-misc-fixes

[Maxime Ripard]

Hi Dave, Daniel,

Here's this week round of fixes for drm-misc

Maxime

drm-misc-fixes-2020-11-19:
two patches to fix dw-hdmi bind and detection code, and one fix for
sun4i shared with arm-soc
The following changes since commit a6c40b8032b845f132abfcbcbed6bddebbcc3b4a:

  drm/mcde: Fix unbalanced regulator (2020-11-11 00:27:53 +0100)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2020-11-19

for you to fetch changes up to cdf117d6d38a127026e74114d63f32972f620c06:

  Merge tag 'drm/sun4i-dma-fix-pull-request' of 
ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mripard/linux into 
drm-misc-fixes (2020-11-19 09:26:07 +0100)


two patches to fix dw-hdmi bind and detection code, and one fix for
sun4i shared with arm-soc


Jonathan Liu (1):
  drm: bridge: dw-hdmi: Avoid resetting force in the detect function

Maxime Ripard (2):
  drm/sun4i: backend: Fix probe failure with multiple backends
  Merge tag 'drm/sun4i-dma-fix-pull-request' of 
ssh://gitolite.kernel.org/.../mripard/linux into drm-misc-fixes

Xiongfeng Wang (1):
  drm/sun4i: dw-hdmi: fix error return code in sun8i_dw_hdmi_bind()

 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 --
 drivers/gpu/drm/sun4i/sun4i_backend.c | 8 +++-
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 1 +
 3 files changed, 8 insertions(+), 7 deletions(-)


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Re: [Intel-gfx] [PATCH] drm/i915: Do not call hsw_set_frame_start_delay for dsi

[Petri Latvala]

On Wed, Nov 18, 2020 at 11:13:31PM -0800, Manasi Navare wrote:
> This should fix the boot oops for dsi
> 
> Fixes: 4e3cdb4535e7 ("drm/i915/dp: Master/Slave enable/disable sequence for 
> bigjoiner")
> Signed-off-by: Manasi Navare 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5c07c74d4397..739be96e998d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7211,7 +7211,7 @@ static void hsw_crtc_enable(struct intel_atomic_state 
> *state,
>   if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>   bdw_set_pipemisc(new_crtc_state);
>  
> - if (!new_crtc_state->bigjoiner_slave || 
> !transcoder_is_dsi(cpu_transcoder)) {
> + if (!new_crtc_state->bigjoiner_slave && 
> !transcoder_is_dsi(cpu_transcoder)) {
>   if (!transcoder_is_dsi(cpu_transcoder))
>   intel_set_transcoder_timings(new_crtc_state);
>  
> @@ -7224,7 +7224,7 @@ static void hsw_crtc_enable(struct intel_atomic_state 
> *state,
>   intel_cpu_transcoder_set_m_n(new_crtc_state,
>_crtc_state->fdi_m_n, 
> NULL);
>  
> - hsw_set_frame_start_delay(new_crtc_state);
> + hsw_set_frame_start_delay(new_crtc_state);


Indentation for this is wrong now.


-- 
Petri Latvala
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Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series

[Saarinen, Jani]

Hi, 

> -Original Message-
> From: Intel-gfx  On Behalf Of Navare,
> Manasi
> Sent: torstai 19. marraskuuta 2020 7.58
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson 
> Subject: Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series
> 
> On Wed, Nov 18, 2020 at 11:49:25AM -0800, Navare, Manasi wrote:
> > Series pushed to dinq
> >
> > Manasi
> 
> By Chris Wilson:
> 
> Oops on boot:
> 
> <1>[   44.315382] BUG: unable to handle page fault for address: 
> c90049e02100
> <1>[   44.315422] #PF: supervisor read access in kernel mode
> <1>[   44.315442] #PF: error_code(0x) - not-present page
> <6>[   44.315462] PGD 10067 P4D 10067 PUD 0
> <4>[   44.315497] Oops:  [#1] PREEMPT SMP NOPTI
> <4>[   44.315522] CPU: 7 PID: 276 Comm: systemd-udevd Tainted: G U
> 5.10.0-rc3-CI-CI_DRM_9355+ #1
> <4>[   44.315552] Hardware name: Intel Corporation Tiger Lake Client
> Platform/TigerLake Y LPDDR4x T4 Crb, BIOS TGLSFWI1.R00.2527.A03.2001170231
> 01/17/2020
> <4>[   44.315981] RIP: 0010:gen12_fwtable_read32+0x6f/0x2f0 [i915]
> <4>[   44.316016] Code: c6 48 8b 43 08 8b b0 98 0d 00 00 85 f6 0f 85 53 01 00 
> 00 89
> ee 48 89 df e8 fe a6 ff ff 85 c0 0f 85 bc 00 00 00 89 e8 48 03 03 <44> 8b 38 
> 48 8b 43
> 08 8b 90 98 0d 00 00 85 d2 0f 85 a8 01 00 00 4c
> 16893]  hsw_crtc_enable+0x188/0x780 [i915]
> <4>[   44.317423]  intel_enable_crtc+0x56/0x70 [i915]
> <4>[   44.317931]  skl_commit_modeset_enables+0x34a/0x530 [i915]
> <4>[   44.318444]  intel_atomic_commit_tail+0x3a0/0x1330 [i915]
> <4>[   44.318488]  ? queue_work_on+0x5e/0x70
> <4>[   44.318965]  intel_atomic_commit+0x371/0x3f0 [i915]
> <4>[   44.319458]  intel_initial_commit+0x156/0x1e0 [i915]
> <4>[   44.319949]  intel_modeset_init_nogem+0xb59/0x1c00 [i915]
> <4>[   44.320336]  i915_driver_probe+0x79c/0xd90 [i915]
> <4>[   44.320374]  ? __pm_runtime_resume+0x4f/0x80
> <4>[   44.320741]  i915_pci_probe+0x43/0x1d0 [i915]
> <4>[   44.320772]  ? _raw_spin_unlock_irqrestore+0x2f/0x50
> <4>[   44.320804]  pci_device_probe+0x9e/0x110
> <4>[   44.320830]  really_probe+0x1c4/0x430
> <4>[   44.320852]  driver_probe_device+0xd9/0x140
> <4>[   44.320875]  device_driver_attach+0x4a/0x50
> <4>[   44.320897]  __driver_attach+0x83/0x140
> <4>[   44.320917]  ? device_driver_attach+0x50/0x50
> <4>[   44.320938]  ? device_driver_attach+0x50/0x50
> 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 
> 8b 0d 1f
> f6 2c 00 f7 d8 64 89 01 48
> <4>[   44.321749] RSP: 002b:7ffda8ea9358 EFLAGS: 0246 ORIG_RAX:
> 0139
> <4>[   44.321782] RAX: ffda RBX: 56004d10ffc0 RCX:
> 7fad885f5839
> <4>[   44.321808] RDX:  RSI: 56004d0f5490 RDI:
> 000f
> <4>[   44.321834] RBP: 56004d0f5490 R08:  R09:
> 7ffda8ea9470
> <4>[   44.321859] R10: 000f R11: 0246 R12:
> 
> <4>[   44.321884] R13: 56004d0f20c0 R14: 0002 R15:
> 
> <4>[   44.321921] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal
> coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg
> ghash_clmulni_intel snd_hda_codec cdc_ether snd_hwdep usbnet snd_hda_core mii
> e1000e ptp snd_pcm pps_core mei_me mei prime_numbers intel_lpss_pci(+)
> <4>[   44.322105] CR2: c90049e02100
> <4>[   44.322130] ---[ end trace 87c6ef683da5ac08 ]---
> 
> 
> But Chris, we havent seen this on CI nor in our testing.
It was at least on 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/index.html?testfilter=boot
 

> 
> Manasi
> 
> >
> > On Tue, Nov 17, 2020 at 11:47:03AM -0800, Manasi Navare wrote:
> > >
> > >
> > > Maarten Lankhorst (4):
> > >   drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
> > >   drm/i915: Try to make bigjoiner work in atomic check
> > >   drm/i915: Add bigjoiner aware plane clipping checks
> > >   drm/i915: Add debugfs dumping for bigjoiner, v3.
> > >
> > > Manasi Navare (3):
> > >   drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
> > >   drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
> > >   drm/i915: HW state readout for Bigjoiner case
> > >
> > > Ville Syrjälä (8):
> > >   drm/i915: Copy the plane hw state directly for Y planes
> > >   drm/i915: Add crtcs affected by bigjoiner to the state
> > >   drm/i915: Add planes affected by bigjoiner to the state
> > >   drm/i915: Get the uapi state from the correct plane when bigjoiner is
> > > used
> > >   drm/i915: Disable legacy cursor fastpath for bigjoiner
> > >   drm/i915: Fix cursor src/dst rectangle with bigjoiner
> > >   drm/i915: Add bigjoiner state dump
> > >   drm/i915: Enable bigjoiner
> > >
> > >  drivers/gpu/drm/i915/display/icl_dsi.c|   2 -
> > >  .../gpu/drm/i915/display/intel_atomic_plane.c | 131 +++-
> > >  .../gpu/drm/i915/display/intel_atomic_plane.h |   9 +-
> > >  drivers/gpu/drm/i915/display/intel_ddi.c  |  69 +-
> > >  

Re: [Intel-gfx] [CI 00/15] Rebased remaining big joiner series

[Chris Wilson]

Quoting Navare, Manasi (2020-11-19 05:58:03)
> On Wed, Nov 18, 2020 at 11:49:25AM -0800, Navare, Manasi wrote:
> > Series pushed to dinq
> > 
> > Manasi
> 
> By Chris Wilson:
> 
> Oops on boot:
> 
> <1>[   44.315382] BUG: unable to handle page fault for address: 
> c90049e02100
> <1>[   44.315422] #PF: supervisor read access in kernel mode
> <1>[   44.315442] #PF: error_code(0x) - not-present page
> <6>[   44.315462] PGD 10067 P4D 10067 PUD 0
> <4>[   44.315497] Oops:  [#1] PREEMPT SMP NOPTI
> <4>[   44.315522] CPU: 7 PID: 276 Comm: systemd-udevd Tainted: G U
> 5.10.0-rc3-CI-CI_DRM_9355+ #1
> <4>[   44.315552] Hardware name: Intel Corporation Tiger Lake Client 
> Platform/TigerLake Y LPDDR4x T4 Crb, BIOS TGLSFWI1.R00.2527.A03.2001170231 
> 01/17/2020
> <4>[   44.315981] RIP: 0010:gen12_fwtable_read32+0x6f/0x2f0 [i915]
> <4>[   44.316016] Code: c6 48 8b 43 08 8b b0 98 0d 00 00 85 f6 0f 85 53 01 00 
> 00 89 ee 48 89 df e8 fe a6 ff ff 85 c0 0f 85 bc 00 00 00 89 e8 48 03 03 <44> 
> 8b 38 48 8b 43 08 8b 90 98 0d 00 00 85 d2 0f 85 a8 01 00 00 4c
> 16893]  hsw_crtc_enable+0x188/0x780 [i915]
> <4>[   44.317423]  intel_enable_crtc+0x56/0x70 [i915]
> <4>[   44.317931]  skl_commit_modeset_enables+0x34a/0x530 [i915]
> <4>[   44.318444]  intel_atomic_commit_tail+0x3a0/0x1330 [i915]
> <4>[   44.318488]  ? queue_work_on+0x5e/0x70
> <4>[   44.318965]  intel_atomic_commit+0x371/0x3f0 [i915]
> <4>[   44.319458]  intel_initial_commit+0x156/0x1e0 [i915]
> <4>[   44.319949]  intel_modeset_init_nogem+0xb59/0x1c00 [i915]
> <4>[   44.320336]  i915_driver_probe+0x79c/0xd90 [i915]
> <4>[   44.320374]  ? __pm_runtime_resume+0x4f/0x80
> <4>[   44.320741]  i915_pci_probe+0x43/0x1d0 [i915]
> <4>[   44.320772]  ? _raw_spin_unlock_irqrestore+0x2f/0x50
> <4>[   44.320804]  pci_device_probe+0x9e/0x110
> <4>[   44.320830]  really_probe+0x1c4/0x430
> <4>[   44.320852]  driver_probe_device+0xd9/0x140
> <4>[   44.320875]  device_driver_attach+0x4a/0x50
> <4>[   44.320897]  __driver_attach+0x83/0x140
> <4>[   44.320917]  ? device_driver_attach+0x50/0x50
> <4>[   44.320938]  ? device_driver_attach+0x50/0x50
> 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 
> 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
> <4>[   44.321749] RSP: 002b:7ffda8ea9358 EFLAGS: 0246 ORIG_RAX: 
> 0139
> <4>[   44.321782] RAX: ffda RBX: 56004d10ffc0 RCX: 
> 7fad885f5839
> <4>[   44.321808] RDX:  RSI: 56004d0f5490 RDI: 
> 000f
> <4>[   44.321834] RBP: 56004d0f5490 R08:  R09: 
> 7ffda8ea9470
> <4>[   44.321859] R10: 000f R11: 0246 R12: 
> 
> <4>[   44.321884] R13: 56004d0f20c0 R14: 0002 R15: 
> 
> <4>[   44.321921] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal 
> coretemp crct10dif_pclmul crc32_pclmul snd_hda_intel snd_intel_dspcfg 
> ghash_clmulni_intel snd_hda_codec cdc_ether snd_hwdep usbnet snd_hda_core mii 
> e1000e ptp snd_pcm pps_core mei_me mei prime_numbers intel_lpss_pci(+)
> <4>[   44.322105] CR2: c90049e02100
> <4>[   44.322130] ---[ end trace 87c6ef683da5ac08 ]---
> 
> 
> But Chris, we havent seen this on CI nor in our testing.

This is CI. CI is also reporting massive display powerwell breakage.
-Chris
___
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Re: [Intel-gfx] [PATCH v2 06/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon

[Shankar, Uma]

> -Original Message-
> From: Nautiyal, Ankit K 
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> Kulkarni, Vandita ; ville.syrj...@linux.intel.com;
> Sharma, Swati2 
> Subject: [PATCH v2 06/13] drm/dp_helper: Add support for Configuring DSC for
> HDMI2.1 Pcon
> 
> This patch adds registers for getting DSC encoder capability for a HDMI2.1 
> PCon.
> It also addes helper functions to configure DSC between the PCON and HDMI2.1
> sink.
> 
> v2: Corrected offset for DSC encoder bpc and minor changes.
> Also added helper functions for getting pcon dsc encoder capabilities as
> suggested by Uma Shankar.
> 
> Signed-off-by: Ankit Nautiyal 
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 197 
>  include/drm/drm_dp_helper.h | 114 ++
>  2 files changed, 311 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c index 05782091e7e1..8162ee856b5d 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -2932,3 +2932,200 @@ void drm_dp_pcon_hdmi_frl_link_error_count(struct
> drm_dp_aux *aux,
>   }
>  }
>  EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
> +
> +/*
> + * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
> + * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
> + *
> + * Returns true is PCON encoder is DSC 1.2 else returns false.
> + */
> +bool drm_dp_pcon_enc_is_dsc_1_2(const u8
> +pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
> +{
> + u8 buf;
> + u8 major_v, minor_v;
> +
> + buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION -
> DP_PCON_DSC_ENCODER];
> + major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >>
> DP_PCON_DSC_MAJOR_SHIFT;
> + minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >>
> DP_PCON_DSC_MINOR_SHIFT;
> +
> + if (major_v == 1 && minor_v == 2)
> + return true;
> +
> + return false;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
> +
> +/*
> + * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC
> +Encoder
> + * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
> + *
> + * Returns maximum no. of slices supported by the PCON DSC Encoder.
> + */
> +int drm_dp_pcon_dsc_max_slices(const u8
> +pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
> +{
> + u8 slice_cap1, slice_cap2;
> +
> + slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 -
> DP_PCON_DSC_ENCODER];
> + slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 -
> +DP_PCON_DSC_ENCODER];
> +
> + if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
> + return 24;

You can use else if to optimize this up.

> + if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
> + return 20;
> + if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
> + return 16;
> + if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
> + return 12;
> + if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
> + return 10;
> + if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
> + return 8;
> + if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
> + return 6;
> + if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
> + return 4;
> + if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
> + return 2;
> + if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
> + return 1;

Add else return 0.

With this fixed:
Reviewed-by: Uma Shankar 

> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
> +
> +/*
> + * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC
> +encoder
> + * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
> + *
> + * Returns maximum width of the slices in pixel width i.e. no. of pixels x 
> 320.
> + */
> +int drm_dp_pcon_dsc_max_slice_width(const u8
> +pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
> +{
> + u8 buf;
> +
> + buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH -
> +DP_PCON_DSC_ENCODER];
> +
> + return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER; }
> +EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
> +
> +/*
> + * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON
> +DSC encoder
> + * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
> + *
> + * Returns the bpp precision supported by the PCON encoder.
> + */
> +int drm_dp_pcon_dsc_bpp_incr(const u8
> +pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
> +{
> + u8 buf;
> +
> + buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR -
> DP_PCON_DSC_ENCODER];
> +
> + switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
> + case DP_PCON_DSC_ONE_16TH_BPP:
> + return 16;
> + case DP_PCON_DSC_ONE_8TH_BPP:
> + return 8;
> + case DP_PCON_DSC_ONE_4TH_BPP:
> + return 4;
> + case DP_PCON_DSC_ONE_HALF_BPP:
> + return 2;
> + case DP_PCON_DSC_ONE_BPP:
> + return 1;
> + }
> +
> + return 0;
> +}
>