Re: [Intel-gfx] [PATCH] Revert "drm/i915: re-order if/else ladder for hpd_irq_setup"
On Fri, Nov 27, 2020 at 02:57:48PM +, Chris Wilson wrote:
We now use ilk_hpd_irq_setup for all GMCH platforms that do not have
hotplug. These are early gen3 and gen2 devices that now explode on boot
as they try to access non-existent registers.
humn... true, my bad. But I don't think a revert is the right fix. It
would be much better if we would not be setting up the hpd setup
function at all for platforms that do not have hotplug. I think a
separate early check for I915_HAS_HOTPLUG() would be deserved.
Lucas De Marchi
Fixes: 794d61a19090 ("drm/i915: re-order if/else ladder for hpd_irq_setup")
Signed-off-by: Chris Wilson
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_irq.c | 27 +++
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dc6febc63f1c..c80eeac53952 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4242,18 +4242,21 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
*/
dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
- if (HAS_PCH_DG1(dev_priv))
- dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
- else if (INTEL_GEN(dev_priv) >= 11)
- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
- else if (IS_GEN9_LP(dev_priv))
- dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
- else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
- else if (HAS_GMCH(dev_priv) && I915_HAS_HOTPLUG(dev_priv))
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
- else
- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ if (HAS_GMCH(dev_priv)) {
+ if (I915_HAS_HOTPLUG(dev_priv))
+ dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ } else {
+ if (HAS_PCH_DG1(dev_priv))
+ dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ else if (INTEL_GEN(dev_priv) >= 11)
+ dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+ else if (IS_GEN9_LP(dev_priv))
+ dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
+ dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ else
+ dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ }
}
/**
--
2.20.1
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Disable outputs during unregister
== Series Details == Series: drm/i915: Disable outputs during unregister URL : https://patchwork.freedesktop.org/series/84371/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9401 -> Patchwork_19008 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19008 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19008, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19008: ### IGT changes ### Possible regressions * igt@core_hotunplug@unbind-rebind: - fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html New tests - New tests have been introduced between CI_DRM_9401 and Patchwork_19008: ### New CI tests (1) ### * boot: - Statuses : 41 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19008 that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html * igt@i915_module_load@reload: - fi-bxt-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-bxt-dsi/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-bxt-dsi/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-byt-j1900/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-byt-j1900/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@execlists: - fi-icl-y: [PASS][9] -> [INCOMPLETE][10] ([i915#1037] / [i915#2276]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-icl-y/igt@i915_selftest@l...@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-icl-y/igt@i915_selftest@l...@execlists.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html Possible fixes * igt@core_hotunplug@unbind-rebind: - fi-blb-e6850: [INCOMPLETE][15] ([i915#2540]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html * igt@i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-icl-u2/igt@i915_module_l...@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-icl-u2/igt@i915_module_l...@reload.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][19] ([i915#1161] / [i915#262]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19008/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [22]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Differentiate oom failures from invalid map types
== Series Details == Series: drm/i915/gem: Differentiate oom failures from invalid map types URL : https://patchwork.freedesktop.org/series/84365/ State : success == Summary == CI Bug Log - changes from CI_DRM_9401_full -> Patchwork_19006_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9401_full and Patchwork_19006_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19006_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][1] -> [DMESG-WARN][2] ([i915#1037] / [i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-skl2/igt@gem_...@in-flight-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-skl3/igt@gem_...@in-flight-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding: - shard-skl: [PASS][3] -> [FAIL][4] ([i915#54]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-128x42-sliding.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-128x42-sliding.html * igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge: - shard-hsw: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-hsw8/igt@kms_cursor_edge_w...@pipe-c-128x128-top-edge.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-hsw1/igt@kms_cursor_edge_w...@pipe-c-128x128-top-edge.html * igt@kms_cursor_legacy@cursora-vs-flipa-varying-size: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-skl10/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-skl1/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2346]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-glk8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-glk6/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-apl8/igt@kms_flip@absolute-wf_vblank-interrupti...@a-dp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-apl1/igt@kms_flip@absolute-wf_vblank-interrupti...@a-dp1.html * igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible@a-hdmi-a1: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-glk1/igt@kms_flip@flip-vs-dpms-off-vs-modeset-interrupti...@a-hdmi-a1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-glk3/igt@kms_flip@flip-vs-dpms-off-vs-modeset-interrupti...@a-hdmi-a1.html * igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([i915#2295]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-hsw8/igt@kms_flip@flip-vs-suspend-interrupti...@b-hdmi-a1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-hsw4/igt@kms_flip@flip-vs-suspend-interrupti...@b-hdmi-a1.html * igt@kms_flip@flip-vs-suspend@a-dp1: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-kbl7/igt@kms_flip@flip-vs-susp...@a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-kbl2/igt@kms_flip@flip-vs-susp...@a-dp1.html * igt@kms_flip@flip-vs-suspend@a-edp1: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#198]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-skl10/igt@kms_flip@flip-vs-susp...@a-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-skl3/igt@kms_flip@flip-vs-susp...@a-edp1.html * igt@kms_flip@wf_vblank-ts-check-interruptible@a-dp1: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/shard-kbl2/igt@kms_flip@wf_vblank-ts-check-interrupti...@a-dp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/shard-kbl7/igt@kms_flip@wf_vblank-ts-check-interrupti...@a-dp1.html *
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Suppress "Combo PHY A HW state changed unexpectedly"
== Series Details == Series: drm/i915/display: Suppress "Combo PHY A HW state changed unexpectedly" URL : https://patchwork.freedesktop.org/series/84368/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9401 -> Patchwork_19007 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19007 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19007, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19007/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19007: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_timelines: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19007/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html New tests - New tests have been introduced between CI_DRM_9401 and Patchwork_19007: ### New CI tests (1) ### * boot: - Statuses : 41 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19007 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-tgl-y/igt@gem_huc_c...@huc-copy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19007/fi-tgl-y/igt@gem_huc_c...@huc-copy.html * igt@kms_busy@basic@flip: - fi-kbl-soraka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-kbl-soraka/igt@kms_busy@ba...@flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19007/fi-kbl-soraka/igt@kms_busy@ba...@flip.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-tgl-y/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19007/fi-tgl-y/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html Possible fixes * igt@i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-icl-u2/igt@i915_module_l...@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19007/fi-icl-u2/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@module-reload: - fi-tgl-y: [DMESG-WARN][11] ([i915#2411]) -> [PASS][12] +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-tgl-y/igt@i915_pm_...@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19007/fi-tgl-y/igt@i915_pm_...@module-reload.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][13] ([i915#1161] / [i915#262]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19007/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@prime_vgem@basic-fence-flip: - fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19007/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (46 -> 41) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9401 -> Patchwork_19007 CI-20190529: 20190529 CI_DRM_9401: a88f54b9c003dd8ee5442caa8212cf507e0172c1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5873: b6321b58dcaa41ba1d28aced42d6b15dc3d49ca2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19007: 54db25f2ae038484f4883c80da95e688b19df42a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 54db25f2ae03 drm/i915/display: Suppress "Combo PHY A HW state changed unexpectedly" == Logs
[Intel-gfx] [PATCH] drm/i915: Disable outputs during unregister
Switch off the scanout during driver unregister, so we can shutdown the HW immediately for unbind. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 320856b665a1..62d188e5cb8d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -738,6 +738,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) * events. */ drm_kms_helper_poll_fini(_priv->drm); + drm_atomic_helper_shutdown(_priv->drm); intel_gt_driver_unregister(_priv->gt); acpi_video_unregister(); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Differentiate oom failures from invalid map types
== Series Details == Series: drm/i915/gem: Differentiate oom failures from invalid map types URL : https://patchwork.freedesktop.org/series/84365/ State : success == Summary == CI Bug Log - changes from CI_DRM_9401 -> Patchwork_19006 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/index.html New tests - New tests have been introduced between CI_DRM_9401 and Patchwork_19006: ### New CI tests (1) ### * boot: - Statuses : 40 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19006 that come from known issues: ### IGT changes ### Issues hit * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html Possible fixes * igt@i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-icl-u2/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/fi-icl-u2/igt@i915_module_l...@reload.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][5] ([i915#1161] / [i915#262]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9401/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 Participating hosts (46 -> 40) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-tgl-y fi-bdw-samus Build changes - * Linux: CI_DRM_9401 -> Patchwork_19006 CI-20190529: 20190529 CI_DRM_9401: a88f54b9c003dd8ee5442caa8212cf507e0172c1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5873: b6321b58dcaa41ba1d28aced42d6b15dc3d49ca2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19006: ad2e08132de7264587ae23dd57dbc7659f287983 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ad2e08132de7 drm/i915/gem: Differentiate oom failures from invalid map types == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19006/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_capture: Trim the blocking workload
While we want the capture to last long enough to delay the concurrent
client, we don't want to wait forever for the capture to complete to
proceed with the testing.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2559
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_capture.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c
index cb0d3151b..3da78d632 100644
--- a/tests/i915/gem_exec_capture.c
+++ b/tests/i915/gem_exec_capture.c
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
+#include
#include
#include "i915/gem.h"
@@ -524,6 +525,7 @@ static void prioinv(int fd, int dir, unsigned ring, const
char *name)
gtt, ram);
count = min(gtt, ram) / 4;
+ count = min(count, 256); /* Keep the duration within reason */
igt_require(count > 1);
intel_require_memory(count, size, CHECK_RAM);
@@ -535,18 +537,26 @@ static void prioinv(int fd, int dir, unsigned ring, const
char *name)
igt_assert(pipe(link) == 0);
igt_fork(child, 1) {
fd = gem_reopen_driver(fd);
- igt_debug("Submitting large hang + capture\n");
+ igt_debug("Submitting large capture [%ld x %dMiB objects]\n",
+ count, (int)(size >> 20));
free(__captureN(fd, dir, ring, size, count, ASYNC));
write(link[1], , sizeof(fd)); /* wake the parent up */
igt_force_gpu_reset(fd);
+ write(link[1], , sizeof(fd)); /* wake the parent up */
}
read(link[0], , sizeof(dummy));
+ igt_require_f(poll(&(struct pollfd){link[0], POLLIN}, 1, 500) == 0,
+ "Capture completed too quickly! Will not block\n");
igt_debug("Submitting nop\n");
gem_execbuf(fd, );
igt_assert_eq(gem_wait(fd, obj.handle, ), 0);
gem_close(fd, obj.handle);
+ igt_assert_f(poll(&(struct pollfd){link[0], POLLIN}, 1, 0) == 0,
+"Capture completed before nop!\n");
+
+ igt_debug("Waiting for capture/reset to complete\n");
igt_waitchildren();
close(link[0]);
close(link[1]);
--
2.29.2
___
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Re: [Intel-gfx] [PATCH] drm/i915/display: Suppress "Combo PHY A HW state changed unexpectedly"
On Fri, 2020-11-27 at 21:00 +, Chris Wilson wrote:
> We know a problem exists in the ifwi shipped with the early
> pre-production Tigerlake and DG1 prototypes, later revisions are fine.
> However, CI still relies on the earlier ifwi and we grow tired of
> the volume of warnings as we wait for replacements.
>
> Since the warning is a bug, we do not want to lose the warning in its
> entirety, so only suppress the warning for the platforms currently
> exhibiting the issue.
>
Reviewed-by: José Roberto de Souza
> Suggested-by: José Roberto de Souza
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2411
> Signed-off-by: Chris Wilson
> Cc: José Roberto de Souza
> ---
> .../gpu/drm/i915/display/intel_combo_phy.c| 20 +++
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index d5ad61e4083e..996ae0608a62 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -427,10 +427,22 @@ static void icl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
> u32 val;
>
>
>
>
> if (phy == PHY_A &&
> - !icl_combo_phy_verify_state(dev_priv, phy))
> - drm_warn(_priv->drm,
> - "Combo PHY %c HW state changed unexpectedly\n",
> - phy_name(phy));
> + !icl_combo_phy_verify_state(dev_priv, phy)) {
> + if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
> + /*
> + * A known problem with old ifwi:
> + *
> https://gitlab.freedesktop.org/drm/intel/-/issues/2411
> + * Suppress the warning for CI. Remove ASAP!
> + */
> + drm_dbg_kms(_priv->drm,
> + "Combo PHY %c HW state changed
> unexpectedly\n",
> + phy_name(phy));
> + } else {
> + drm_warn(_priv->drm,
> + "Combo PHY %c HW state changed
> unexpectedly\n",
> + phy_name(phy));
> + }
> + }
>
>
>
>
> if (!has_phy_misc(dev_priv, phy))
> goto skip_phy_misc;
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[Intel-gfx] [PATCH] drm/i915/display: Suppress "Combo PHY A HW state changed unexpectedly"
We know a problem exists in the ifwi shipped with the early
pre-production Tigerlake and DG1 prototypes, later revisions are fine.
However, CI still relies on the earlier ifwi and we grow tired of
the volume of warnings as we wait for replacements.
Since the warning is a bug, we do not want to lose the warning in its
entirety, so only suppress the warning for the platforms currently
exhibiting the issue.
Suggested-by: José Roberto de Souza
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2411
Signed-off-by: Chris Wilson
Cc: José Roberto de Souza
---
.../gpu/drm/i915/display/intel_combo_phy.c| 20 +++
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index d5ad61e4083e..996ae0608a62 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -427,10 +427,22 @@ static void icl_combo_phys_uninit(struct drm_i915_private
*dev_priv)
u32 val;
if (phy == PHY_A &&
- !icl_combo_phy_verify_state(dev_priv, phy))
- drm_warn(_priv->drm,
-"Combo PHY %c HW state changed unexpectedly\n",
-phy_name(phy));
+ !icl_combo_phy_verify_state(dev_priv, phy)) {
+ if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
+ /*
+* A known problem with old ifwi:
+*
https://gitlab.freedesktop.org/drm/intel/-/issues/2411
+* Suppress the warning for CI. Remove ASAP!
+*/
+ drm_dbg_kms(_priv->drm,
+ "Combo PHY %c HW state changed
unexpectedly\n",
+ phy_name(phy));
+ } else {
+ drm_warn(_priv->drm,
+"Combo PHY %c HW state changed
unexpectedly\n",
+phy_name(phy));
+ }
+ }
if (!has_phy_misc(dev_priv, phy))
goto skip_phy_misc;
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Record the plane update times for debugging (rev8)
== Series Details ==
Series: drm/i915/display: Record the plane update times for debugging (rev8)
URL : https://patchwork.freedesktop.org/series/84174/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9399_full -> Patchwork_19004_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19004_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_flip_tiling@flip-yf-tiled@edp-1-pipe-b}:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl2/igt@kms_flip_tiling@flip-yf-ti...@edp-1-pipe-b.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-skl2/igt@kms_flip_tiling@flip-yf-ti...@edp-1-pipe-b.html
New tests
-
New tests have been introduced between CI_DRM_9399_full and
Patchwork_19004_full:
### New CI tests (1) ###
* boot:
- Statuses : 199 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19004_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-iclb2/igt@feature_discov...@psr2.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-iclb1/igt@feature_discov...@psr2.html
* igt@gem_exec_whisper@basic-fds-priority:
- shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-glk3/igt@gem_exec_whis...@basic-fds-priority.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-glk8/igt@gem_exec_whis...@basic-fds-priority.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#54])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl10/igt@kms_cursor_...@pipe-c-cursor-128x42-sliding.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#2346])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [i915#265])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +2 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-iclb5/igt@kms_psr@psr2_no_drrs.html
* igt@perf@short-reads:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#51])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl9/igt@p...@short-reads.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-skl4/igt@p...@short-reads.html
* igt@sysfs_preempt_timeout@timeout@bcs0:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#2060])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl4/igt@sysfs_preempt_timeout@time...@bcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-skl9/igt@sysfs_preempt_timeout@time...@bcs0.html
Possible fixes
* igt@gem_eio@in-flight-suspend:
- shard-skl: [DMESG-WARN][19] ([i915#1037] / [i915#1982]) ->
[PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl9/igt@gem_...@in-flight-suspend.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-skl5/igt@gem_...@in-flight-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-skl: [FAIL][21] ([i915#54]) -> [PASS][22] +6 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-bottom-edge:
- shard-skl:
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Remove require_force_probe protection
Quoting Pandey, Hariom (2020-10-28 11:55:04) > Ok, I have initiated the steps to upgrade the CI machine's silicon & BIOS. The single ehl we have in CI is still failing to enter rc6, both in the selftest and runtime testing. And I note that RAPL doesn't recognise it, so it doesn't report the power consumption. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 006/162] drm/i915: split gen8+ flush and bb_start emission functions to their own file
Quoting Matthew Auld (2020-11-27 12:04:42) > From: Daniele Ceraolo Spurio > > These functions are independent from the backend used and can therefore > be split out of the exelists submission file, so they can be re-used by > the upcoming GuC submission backend. > > Based on a patch by Chris Wilson. > > Signed-off-by: Daniele Ceraolo Spurio > Cc: Chris P Wilson > Cc: Tvrtko Ursulin > Reviewed-by: John Harrison > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 393 ++ > drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 26 ++ > .../drm/i915/gt/intel_execlists_submission.c | 385 + > 4 files changed, 421 insertions(+), 384 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/gen8_engine_cs.c > create mode 100644 drivers/gpu/drm/i915/gt/gen8_engine_cs.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index aedbd8f52be8..f9ef5199b124 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -82,6 +82,7 @@ gt-y += \ > gt/gen6_engine_cs.o \ > gt/gen6_ppgtt.o \ > gt/gen7_renderclear.o \ > + gt/gen8_engine_cs.o \ > gt/gen8_ppgtt.o \ > gt/intel_breadcrumbs.o \ > gt/intel_context.o \ > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > new file mode 100644 > index ..a96fe108685e > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -0,0 +1,393 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2014 Intel Corporation > + */ > + > +#include "i915_drv.h" > +#include "intel_execlists_submission.h" /* XXX */ > +#include "intel_gpu_commands.h" > +#include "intel_ring.h" > + > +int gen8_emit_flush_render(struct i915_request *request, u32 mode) Refresh the names to make the recent schemes. (rcs when specific, xcs when not) -Chris - Intel Corporation (UK) Limited Registered No. 1134945 (England) Registered Office: Pipers Way, Swindon SN3 1RJ VAT No: 860 2173 47 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 005/162] drm/i915/gt: Rename lrc.c to execlists_submission.c
Quoting Matthew Auld (2020-11-27 12:04:41) > From: Chris Wilson > > We want to separate the utility functions for controlling the logical > ring context from the execlists submission mechanism (which is an > overgrown scheduler). > > This is similar to Daniele's work to split up the files, but being > selfish I wanted to base it after my own changes to intel_lrc.c petered > out. Note in accordance with recent intel_ring_submission.c vs intel_ring_scheduler.c, this would be intel_execlists_scheduler.c -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 004/162] drm/i915/gt: Move move context layout registers and offsets to lrc_reg.h
Quoting Matthew Auld (2020-11-27 12:04:40)
> From: Chris Wilson
>
> Cleanup intel_lrc.h by moving some of the residual common register
> definitions into intel_lrc_reg.h, prior to rebranding and splitting off
> the submission backends.
>
> v2: keep the SCHEDULE enum in the old file, since it is specific to the
> gvt usage of the execlists submission backend (John)
>
> Signed-off-by: Chris Wilson
> Signed-off-by: Daniele Ceraolo Spurio #v2
> Cc: John Harrison
> Reviewed-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_irq.c| 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.h | 39 ---
> drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 39 +++
> drivers/gpu/drm/i915/gvt/mmio_context.h | 2 ++
> 5 files changed, 43 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index d4e988b2816a..02ea16b29c9f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -36,7 +36,7 @@
> #include "intel_gt.h"
> #include "intel_gt_requests.h"
> #include "intel_gt_pm.h"
> -#include "intel_lrc.h"
> +#include "intel_lrc_reg.h"
> #include "intel_reset.h"
> #include "intel_ring.h"
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 257063a57101..9830342aa6f4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -11,6 +11,7 @@
> #include "intel_breadcrumbs.h"
> #include "intel_gt.h"
> #include "intel_gt_irq.h"
> +#include "intel_lrc_reg.h"
> #include "intel_uncore.h"
> #include "intel_rps.h"
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h
> b/drivers/gpu/drm/i915/gt/intel_lrc.h
> index 802585a308e9..9116b46844a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
> @@ -34,45 +34,6 @@ struct i915_request;
> struct intel_context;
> struct intel_engine_cs;
>
> -/* Execlists regs */
> -#define RING_ELSP(base)_MMIO((base) + 0x230)
> -#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
> -#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
> -#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
> -#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
> -#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
> -#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
> -#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
> -#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE (1 << 8)
> -#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
> -#define RING_EXECLIST_SQ_CONTENTS(base)_MMIO((base) + 0x510)
> -#define RING_EXECLIST_CONTROL(base)_MMIO((base) + 0x550)
> -
> -#define EL_CTRL_LOAD (1 << 0)
> -
> -/* The docs specify that the write pointer wraps around after 5h, "After
> status
> - * is written out to the last available status QW at offset 5h, this pointer
> - * wraps to 0."
> - *
> - * Therefore, one must infer than even though there are 3 bits available, 6
> and
> - * 7 appear to be * reserved.
> - */
> -#define GEN8_CSB_ENTRIES 6
> -#define GEN8_CSB_PTR_MASK 0x7
> -#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
> -#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
> -
> -#define GEN11_CSB_ENTRIES 12
> -#define GEN11_CSB_PTR_MASK 0xf
> -#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
> -#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
> -
> -#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
> -#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
> -#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
> -/* in Gen12 ID 0x7FF is reserved to indicate idle */
> -#define GEN12_MAX_CONTEXT_HW_ID(GEN11_MAX_CONTEXT_HW_ID - 1)
> -
> enum {
> INTEL_CONTEXT_SCHEDULE_IN = 0,
> INTEL_CONTEXT_SCHEDULE_OUT,
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> index 1b51f7b9a5c3..b2e03ce35599 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> @@ -52,4 +52,43 @@
> #define GEN8_EXECLISTS_STATUS_BUF 0x370
> #define GEN11_EXECLISTS_STATUS_BUF2 0x3c0
>
> +/* Execlists regs */
> +#define RING_ELSP(base)_MMIO((base) + 0x230)
> +#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
> +#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
> +#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
> +#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
> +#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
> +#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT
[Intel-gfx] [PATCH] drm/i915/gem: Differentiate oom failures from invalid map types
After a cursory check on the parameters to i915_gem_object_pin_map(),
where we return a precise error, if the backend rejects the mapping we
always return PTR_ERR(-ENOMEM). Let us also return a more precise error
here so we can differentiate between running out of memory and
programming errors (or situations where we may be trying different paths
and looking for an error from an unsupported map).
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 26 +++
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index e2c7b2a7895f..6dad9ea8eaa3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -238,7 +238,7 @@ int __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj)
/* The 'mapping' part of i915_gem_object_pin_map() below */
static void *i915_gem_object_map_page(struct drm_i915_gem_object *obj,
- enum i915_map_type type)
+ enum i915_map_type type)
{
unsigned long n_pages = obj->base.size >> PAGE_SHIFT, i;
struct page *stack[32], **pages = stack, *page;
@@ -281,7 +281,7 @@ static void *i915_gem_object_map_page(struct
drm_i915_gem_object *obj,
/* Too big for stack -- allocate temporary array instead */
pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_KERNEL);
if (!pages)
- return NULL;
+ return ERR_PTR(-ENOMEM);
}
i = 0;
@@ -294,7 +294,7 @@ static void *i915_gem_object_map_page(struct
drm_i915_gem_object *obj,
}
static void *i915_gem_object_map_pfn(struct drm_i915_gem_object *obj,
- enum i915_map_type type)
+enum i915_map_type type)
{
resource_size_t iomap = obj->mm.region->iomap.base -
obj->mm.region->region.start;
@@ -305,13 +305,13 @@ static void *i915_gem_object_map_pfn(struct
drm_i915_gem_object *obj,
void *vaddr;
if (type != I915_MAP_WC)
- return NULL;
+ return ERR_PTR(-ENODEV);
if (n_pfn > ARRAY_SIZE(stack)) {
/* Too big for stack -- allocate temporary array instead */
pfns = kvmalloc_array(n_pfn, sizeof(*pfns), GFP_KERNEL);
if (!pfns)
- return NULL;
+ return ERR_PTR(-ENOMEM);
}
i = 0;
@@ -349,8 +349,10 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
err = i915_gem_object_get_pages(obj);
- if (err)
- goto err_unlock;
+ if (err) {
+ ptr = ERR_PTR(err);
+ goto out_unlock;
+ }
smp_mb__before_atomic();
}
@@ -362,7 +364,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
ptr = page_unpack_bits(obj->mm.mapping, _type);
if (ptr && has_type != type) {
if (pinned) {
- err = -EBUSY;
+ ptr = ERR_PTR(-EBUSY);
goto err_unpin;
}
@@ -374,15 +376,13 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
if (!ptr) {
if (GEM_WARN_ON(type == I915_MAP_WC &&
!static_cpu_has(X86_FEATURE_PAT)))
- ptr = NULL;
+ ptr = ERR_PTR(-ENODEV);
else if (i915_gem_object_has_struct_page(obj))
ptr = i915_gem_object_map_page(obj, type);
else
ptr = i915_gem_object_map_pfn(obj, type);
- if (!ptr) {
- err = -ENOMEM;
+ if (IS_ERR(ptr))
goto err_unpin;
- }
obj->mm.mapping = page_pack_bits(ptr, type);
}
@@ -393,8 +393,6 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
err_unpin:
atomic_dec(>mm.pages_pin_count);
-err_unlock:
- ptr = ERR_PTR(err);
goto out_unlock;
}
--
2.20.1
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[Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915: re-order if/else ladder for hpd_irq_setup"
== Series Details == Series: Revert "drm/i915: re-order if/else ladder for hpd_irq_setup" URL : https://patchwork.freedesktop.org/series/84352/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9399_full -> Patchwork_19003_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19003_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19003_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19003_full: ### IGT changes ### Possible regressions * igt@i915_pm_sseu@full-enable: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl5/igt@i915_pm_s...@full-enable.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-skl9/igt@i915_pm_s...@full-enable.html New tests - New tests have been introduced between CI_DRM_9399_full and Patchwork_19003_full: ### New CI tests (1) ### * boot: - Statuses : 199 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19003_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-iclb2/igt@feature_discov...@psr2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-iclb1/igt@feature_discov...@psr2.html * igt@gem_exec_whisper@basic-fds-forked: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-glk6/igt@gem_exec_whis...@basic-fds-forked.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-glk5/igt@gem_exec_whis...@basic-fds-forked.html * igt@gem_exec_whisper@basic-queues-priority-all: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([i915#1895]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-iclb4/igt@gem_exec_whis...@basic-queues-priority-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-iclb6/igt@gem_exec_whis...@basic-queues-priority-all.html * igt@i915_suspend@sysfs-reader: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#198]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl8/igt@i915_susp...@sysfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-skl5/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-apl8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-apl7/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2346]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-tglb6/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-tglb6/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html * igt@kms_flip@basic-flip-vs-modeset@a-edp1: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-skl2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#79]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-render.html *
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: remove trailing semicolon in macro definition
== Series Details ==
Series: drm/i915: remove trailing semicolon in macro definition
URL : https://patchwork.freedesktop.org/series/84354/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19005
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19005 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19005, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19005:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
New tests
-
New tests have been introduced between CI_DRM_9399 and Patchwork_19005:
### New CI tests (1) ###
* boot:
- Statuses : 39 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19005 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_pm:
- fi-cml-s: [PASS][3] -> [DMESG-FAIL][4] ([i915#2420])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-cml-s/igt@i915_selftest@live@gt_pm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-cml-s/igt@i915_selftest@live@gt_pm.html
* igt@kms_busy@basic@flip:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@kms_busy@ba...@flip.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-tgl-y/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-snb-2520m: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-snb-2520m/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-snb-2520m/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +2 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@prime_v...@basic-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-tgl-y/igt@prime_v...@basic-read.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-tgl-y/igt@debugfs_test@read_all_entries.html
- {fi-kbl-7560u}: [INCOMPLETE][13] ([i915#2417]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [DMESG-FAIL][15] ([i915#541]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_busy@basic@flip:
- fi-kbl-soraka: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19005/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2417]:
Re: [Intel-gfx] [RFC PATCH 001/162] drm/i915/selftest: also consider non-contiguous objects
Quoting Matthew Auld (2020-11-27 12:04:37) > In igt_ppgtt_sanity_check we should also exercise the non-contiguous > option for LMEM, since this will give us slightly different sg layouts > and alignment. > > Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: remove trailing semicolon in macro definition
Quoting t...@redhat.com (2020-11-27 16:28:28) > From: Tom Rix > > The macro use will already have a semicolon. > > Signed-off-by: Tom Rix > --- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > b/drivers/gpu/drm/i915/intel_device_info.c > index e67cec8fa2aa..ef767f04c37c 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -104,7 +104,7 @@ void intel_device_info_print_static(const struct > intel_device_info *info, > drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); > drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); > > -#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)); > +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)) > DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); I thought that this was a macro that avoided adding the ';' to each invocation. Perhaps another time. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 092/162] drm/i915/uapi: introduce drm_i915_gem_create_ext
Quoting Matthew Auld (2020-11-27 12:06:08)
> +int
> +i915_gem_create_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file)
> +{
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct create_ext ext_data = { .i915 = i915 };
> + struct drm_i915_gem_create_ext *args = data;
> + int ret;
> +
> + i915_gem_flush_free_objects(i915);
> +
> + ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
> + create_extensions,
> + ARRAY_SIZE(create_extensions),
> + _data);
> + if (ret)
> + goto err_free;
> +
> + if (!ext_data.placements) {
> + struct intel_memory_region **placements;
> + enum intel_memory_type mem_type = INTEL_MEMORY_SYSTEM;
> +
> + placements = kmalloc(sizeof(struct intel_memory_region *),
> +GFP_KERNEL);
> + if (!placements)
> + return -ENOMEM;
> +
> + placements[0] = intel_memory_region_by_type(i915, mem_type);
> +
> + ext_data.placements = placements;
> + ext_data.n_placements = 1;
> + }
> +
> + ret = i915_gem_create(file,
> + ext_data.placements,
> + ext_data.n_placements,
> + >size, >handle);
> + if (!ret)
> + return 0;
Applying the extensions has to happen after creating the vanilla object.
It literally is the equivalent of applying the setparam ioctl to a fresh
object.
Look at the PXP series for how badly wrong this goes if you try it this
way around.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: remove trailing semicolon in macro definition
== Series Details == Series: drm/i915: remove trailing semicolon in macro definition URL : https://patchwork.freedesktop.org/series/84354/ State : warning == Summary == $ dim checkpatch origin/drm-tip ba9e1a69788c drm/i915: remove trailing semicolon in macro definition -:19: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues #19: FILE: drivers/gpu/drm/i915/intel_device_info.c:107: +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)) total: 0 errors, 0 warnings, 1 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Record the plane update times for debugging (rev8)
== Series Details ==
Series: drm/i915/display: Record the plane update times for debugging (rev8)
URL : https://patchwork.freedesktop.org/series/84174/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19004
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/index.html
New tests
-
New tests have been introduced between CI_DRM_9399 and Patchwork_19004:
### New CI tests (1) ###
* boot:
- Statuses : 37 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19004 that come from known issues:
### IGT changes ###
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-kbl-7560u}: [INCOMPLETE][1] ([i915#2417]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [DMESG-FAIL][3] ([i915#541]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-kbl-soraka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar
issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-apl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-apl-guc/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/fi-apl-guc/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2417]: https://gitlab.freedesktop.org/drm/intel/issues/2417
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (45 -> 37)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bsw-kefka fi-blb-e6850 fi-tgl-y fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9399 -> Patchwork_19004
CI-20190529: 20190529
CI_DRM_9399: b3d976d7d7851bcfcd64b5d6c29672a9e2462442 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5873: b6321b58dcaa41ba1d28aced42d6b15dc3d49ca2 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19004: 99d7669d313b92c07e13b17e49f0f90e868f69fc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
99d7669d313b drm/i915/display: Record the plane update times for debugging
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19004/index.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for Enable HDR on MCA LSPCON based Gen9 devices (rev14)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev14) URL : https://patchwork.freedesktop.org/series/68081/ State : success == Summary == CI Bug Log - changes from CI_DRM_9399_full -> Patchwork_19001_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9399_full and Patchwork_19001_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19001_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-iclb2/igt@feature_discov...@psr2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-iclb4/igt@feature_discov...@psr2.html * igt@gem_exec_whisper@basic-fds-priority: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-glk3/igt@gem_exec_whis...@basic-fds-priority.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-glk7/igt@gem_exec_whis...@basic-fds-priority.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][5] -> [SKIP][6] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-tglb5/igt@gem_huc_c...@huc-copy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl1/igt@kms_cursor_...@pipe-a-cursor-128x128-offscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-128x128-offscreen.html * igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge: - shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-hsw6/igt@kms_cursor_edge_w...@pipe-c-128x128-top-edge.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-hsw8/igt@kms_cursor_edge_w...@pipe-c-128x128-top-edge.html * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-apl7/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-apl3/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1: - shard-apl: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-dp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#2122]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interrupti...@c-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interrupti...@c-edp1.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render: - shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-tglb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-skl6/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-skl4/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html * igt@kms_plane_lowres@pipe-a-tiling-yf: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#165] / [i915#180] / [i915#78]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/shard-kbl7/igt@kms_plane_low...@pipe-a-tiling-yf.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/shard-kbl2/igt@kms_plane_low...@pipe-a-tiling-yf.html * igt@kms_psr@psr2_no_drrs: - shard-iclb:
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915: re-order if/else ladder for hpd_irq_setup"
== Series Details == Series: Revert "drm/i915: re-order if/else ladder for hpd_irq_setup" URL : https://patchwork.freedesktop.org/series/84352/ State : success == Summary == CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19003 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/index.html New tests - New tests have been introduced between CI_DRM_9399 and Patchwork_19003: ### New CI tests (1) ### * boot: - Statuses : 40 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19003 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@gem_mmap_...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/fi-tgl-y/igt@gem_mmap_...@basic.html * igt@kms_busy@basic@flip: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@kms_busy@ba...@flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/fi-tgl-y/igt@kms_busy@ba...@flip.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html Possible fixes * igt@gem_flink_basic@bad-open: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@gem_flink_ba...@bad-open.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/fi-tgl-y/igt@gem_flink_ba...@bad-open.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][9] ([i915#541]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_busy@basic@flip: - fi-kbl-soraka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-soraka/igt@kms_busy@ba...@flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/fi-kbl-soraka/igt@kms_busy@ba...@flip.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (45 -> 40) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9399 -> Patchwork_19003 CI-20190529: 20190529 CI_DRM_9399: b3d976d7d7851bcfcd64b5d6c29672a9e2462442 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5873: b6321b58dcaa41ba1d28aced42d6b15dc3d49ca2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19003: 46cf953013d1c2629d31da6a063523a5263fee94 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 46cf953013d1 Revert "drm/i915: re-order if/else ladder for hpd_irq_setup" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19003/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
On Fri, Nov 27, 2020 at 04:19:20PM +0100, Daniel Vetter wrote:
> On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> > Hi Daniel, Jani,
> >
> > is it ok to merge this patch along with 2/2 via the i915 tree?
>
> Ack from mesa (userspace in general, but mesa is kinda mandatory) is
> missing I think. With that
> Acked-by: Daniel Vetter
Thanks.
Nanley, could you ACK the patchset if they look ok from Mesa's POV? It
works as expected at least with the igt/kms_ccs RC-CC subtest.
--Imre
> > On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> > > From: Radhakrishna Sripada
> > >
> > > Gen12 display can decompress surfaces compressed by render engine with
> > > Clear Color, add a new modifier as the driver needs to know the surface
> > > was compressed by render engine.
> > >
> > > V2: Description changes as suggested by Rafael.
> > > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > > v4: Fix trailing whitespaces
> > > v5: Explain Clear Color in the documentation.
> > > v6: Documentation Nitpicks(Nanley)
> > >
> > > Cc: Ville Syrjala
> > > Cc: Dhinakaran Pandiyan
> > > Cc: Kalyan Kondapally
> > > Cc: Rafael Antognolli
> > > Cc: Nanley Chery
> > > Signed-off-by: Radhakrishna Sripada
> > > Signed-off-by: Imre Deak
> > > ---
> > > include/uapi/drm/drm_fourcc.h | 19 +++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > index ca48ed0e6bc1..0a1b2c4c4bee 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -527,6 +527,25 @@ extern "C" {
> > > */
> > > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
> > >
> > > +/*
> > > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> > > + * compression.
> > > + *
> > > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> > > linear
> > > + * and at index 1. The clear color is stored at index 2, and the pitch
> > > should
> > > + * be ignored. The clear color structure is 256 bits. The first 128 bits
> > > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> > > represented
> > > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> > > generates
> > > + * the converted clear color of size 64 bits. The first 32 bits store
> > > the Lower
> > > + * Converted Clear Color value and the next 32 bits store the Higher
> > > Converted
> > > + * Clear Color value when applicable. The Converted Clear Color values
> > > are
> > > + * consumed by the DE. The last 64 bits are used to store Color Discard
> > > Enable
> > > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache
> > > line
> > > + * corresponds to an area of 4x1 tiles in the main surface. The main
> > > surface
> > > + * pitch is required to be a multiple of 4 tile widths.
> > > + */
> > > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > +
> > > /*
> > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > *
> > > --
> > > 2.25.1
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/4] drm/i915/display/psr: Calculate selective fetch plane registers
== Series Details == Series: series starting with [v3,1/4] drm/i915/display/psr: Calculate selective fetch plane registers URL : https://patchwork.freedesktop.org/series/84350/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19002 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19002 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19002, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19002: ### IGT changes ### Possible regressions * igt@gem_exec_parallel@engines@fds: - fi-skl-guc: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-skl-guc/igt@gem_exec_parallel@engi...@fds.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-skl-guc/igt@gem_exec_parallel@engi...@fds.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-tgl-y: [PASS][3] -> [FAIL][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-tgl-u2: [PASS][5] -> [FAIL][6] +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-tgl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html New tests - New tests have been introduced between CI_DRM_9399 and Patchwork_19002: ### New CI tests (1) ### * boot: - Statuses : 40 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19002 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-tgl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#402] / [k.org#205379]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-u2/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-tgl-u2/igt@i915_module_l...@reload.html * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html * igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1: - fi-tgl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +12 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-tgl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html * igt@kms_psr@primary_page_flip: - fi-tgl-u2: [PASS][15] -> [SKIP][16] ([i915#668]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-u2/igt@kms_psr@primary_page_flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-tgl-u2/igt@kms_psr@primary_page_flip.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@debugfs_test@read_all_entries.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][19] ([i915#541]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19002/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_busy@basic@flip: - fi-kbl-soraka: [DMESG-WARN][21]
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915/gt: Replace direct submit with direct call to tasklet
== Series Details == Series: series starting with [CI,1/2] drm/i915/gt: Replace direct submit with direct call to tasklet URL : https://patchwork.freedesktop.org/series/84345/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9398_full -> Patchwork_19000_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19000_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19000_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19000_full: ### IGT changes ### Possible regressions * igt@gem_exec_balancer@full-late-pulse: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-tglb2/igt@gem_exec_balan...@full-late-pulse.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/shard-tglb3/igt@gem_exec_balan...@full-late-pulse.html * igt@gem_exec_balancer@sliced: - shard-tglb: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-tglb3/igt@gem_exec_balan...@sliced.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/shard-tglb5/igt@gem_exec_balan...@sliced.html - shard-iclb: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-iclb6/igt@gem_exec_balan...@sliced.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/shard-iclb4/igt@gem_exec_balan...@sliced.html * igt@i915_selftest@mock@shmem: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-iclb4/igt@i915_selftest@m...@shmem.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/shard-iclb4/igt@i915_selftest@m...@shmem.html - shard-kbl: [PASS][9] -> [INCOMPLETE][10] +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-kbl2/igt@i915_selftest@m...@shmem.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/shard-kbl3/igt@i915_selftest@m...@shmem.html ### Piglit changes ### Possible regressions * spec@arb_texture_buffer_object@render-no-bo (NEW): - pig-skl-6260u: NOTRUN -> [INCOMPLETE][11] +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/pig-skl-6260u/spec@arb_texture_buffer_obj...@render-no-bo.html New tests - New tests have been introduced between CI_DRM_9398_full and Patchwork_19000_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s ### New Piglit tests (4) ### * spec@arb_point_parameters@arb_point_parameters-point-attenuation: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_texture_buffer_object@max-size: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_texture_buffer_object@render-no-bo: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_texture_buffer_object@unused-name: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19000_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1037] / [i915#1982]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-skl2/igt@gem_...@in-flight-suspend.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/shard-skl1/igt@gem_...@in-flight-suspend.html * igt@gem_exec_balancer@full: - shard-kbl: [PASS][14] -> [INCOMPLETE][15] ([i915#794]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-kbl6/igt@gem_exec_balan...@full.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/shard-kbl2/igt@gem_exec_balan...@full.html * igt@gem_exec_whisper@basic-fds-forked: - shard-glk: [PASS][16] -> [DMESG-WARN][17] ([i915#118] / [i915#95]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-glk8/igt@gem_exec_whis...@basic-fds-forked.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/shard-glk2/igt@gem_exec_whis...@basic-fds-forked.html * igt@gen9_exec_parse@allowed-all: - shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#1436] / [i915#716]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-kbl7/igt@gen9_exec_pa...@allowed-all.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/shard-kbl3/igt@gen9_exec_pa...@allowed-all.html *
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/4] drm/i915/display/psr: Calculate selective fetch plane registers
== Series Details == Series: series starting with [v3,1/4] drm/i915/display/psr: Calculate selective fetch plane registers URL : https://patchwork.freedesktop.org/series/84350/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable HDR on MCA LSPCON based Gen9 devices (rev14)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev14) URL : https://patchwork.freedesktop.org/series/68081/ State : success == Summary == CI Bug Log - changes from CI_DRM_9399 -> Patchwork_19001 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/index.html New tests - New tests have been introduced between CI_DRM_9399 and Patchwork_19001: ### New CI tests (1) ### * boot: - Statuses : 40 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19001 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-byt-j1900/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/fi-byt-j1900/igt@i915_module_l...@reload.html * igt@vgem_basic@setversion: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@vgem_ba...@setversion.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/fi-tgl-y/igt@vgem_ba...@setversion.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@debugfs_test@read_all_entries.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][7] ([i915#541]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_busy@basic@flip: - fi-kbl-soraka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-kbl-soraka/igt@kms_busy@ba...@flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/fi-kbl-soraka/igt@kms_busy@ba...@flip.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-tgl-y: [DMESG-WARN][13] ([i915#2411]) -> [DMESG-WARN][14] ([i915#1982] / [i915#2411]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9399/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19001/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (45 -> 40) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9399 -> Patchwork_19001 CI-20190529: 20190529 CI_DRM_9399: b3d976d7d7851bcfcd64b5d6c29672a9e2462442 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5873: b6321b58dcaa41ba1d28aced42d6b15dc3d49ca2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19001: de26a0b2bb4bae9572b9a722768ea8af4cb8c9df @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == de26a0b2bb4b drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON 9d54f5aa21a3 drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks 0fc199846536 drm/i915/display: Implement DRM infoframe read for LSPCON 617df78a8179 drm/i915/display: Implement infoframes readback for LSPCON 2897d74df2af drm/i915/lspcon: Create separate infoframe_enabled helper a62b61152c33 drm/i915/display: Enable HDR for Parade based lspcon 0d908347d855 drm/i915/display: Nuke bogus lspcon check 952e986183d7 drm/i915/display: Enable colorspace programming for LSPCON devices 953887a7e7fa drm/i915: Split intel_attach_colorspace_property() into HDMI vs. DP variants 8c6662304756 drm/i915/display: Attach content type property for LSPCON 5518242f17cc drm/i915/display: Add a WARN for invalid output range and format 36eb79c62329
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev14)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev14) URL : https://patchwork.freedesktop.org/series/68081/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev14)
== Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev14) URL : https://patchwork.freedesktop.org/series/68081/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7f90737a12fb drm/i915/display: Add HDR Capability detection for LSPCON a44d7eb6654e drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon 1319993255f3 drm/i915/display: Attach HDR property for capable Gen9 devices -:58: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #58: FILE: drivers/gpu/drm/i915/display/intel_dp.c:6804: + connector->dev->mode_config.hdr_output_metadata_property, total: 0 errors, 1 warnings, 0 checks, 45 lines checked 36eb79c62329 drm/i915/display: Fixes quantization range for YCbCr output 5518242f17cc drm/i915/display: Add a WARN for invalid output range and format 8c6662304756 drm/i915/display: Attach content type property for LSPCON 953887a7e7fa drm/i915: Split intel_attach_colorspace_property() into HDMI vs. DP variants 952e986183d7 drm/i915/display: Enable colorspace programming for LSPCON devices 0d908347d855 drm/i915/display: Nuke bogus lspcon check a62b61152c33 drm/i915/display: Enable HDR for Parade based lspcon 2897d74df2af drm/i915/lspcon: Create separate infoframe_enabled helper 617df78a8179 drm/i915/display: Implement infoframes readback for LSPCON 0fc199846536 drm/i915/display: Implement DRM infoframe read for LSPCON 9d54f5aa21a3 drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks de26a0b2bb4b drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Record the plane update times for debugging (rev7)
== Series Details == Series: drm/i915/display: Record the plane update times for debugging (rev7) URL : https://patchwork.freedesktop.org/series/84174/ State : success == Summary == CI Bug Log - changes from CI_DRM_9398_full -> Patchwork_18998_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9398_full and Patchwork_18998_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18998_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_whisper@basic-fds-priority: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-glk9/igt@gem_exec_whis...@basic-fds-priority.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-glk9/igt@gem_exec_whis...@basic-fds-priority.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-kbl6/igt@gem_soft...@noreloc-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-kbl1/igt@gem_soft...@noreloc-s3.html * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#72]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-glk5/igt@kms_cursor_leg...@2x-flip-vs-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-glk9/igt@kms_cursor_leg...@2x-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2346]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-tglb8/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-tglb8/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#79]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1: - shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([i915#2295]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-hsw6/igt@kms_flip@flip-vs-suspend-interrupti...@c-hdmi-a1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-hsw2/igt@kms_flip@flip-vs-suspend-interrupti...@c-hdmi-a1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#2122]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-edp1.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-skl6/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#165] / [i915#2621] / [i915#78]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-kbl3/igt@kms_plane_low...@pipe-a-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-kbl2/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_cpu.html * igt@kms_sequence@get-idle: - shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/shard-snb7/igt@kms_seque...@get-idle.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/shard-snb4/igt@kms_seque...@get-idle.html Possible fixes * igt@i915_pm_sseu@full-enable: - shard-skl: [FAIL][23] -> [PASS][24] [23]:
[Intel-gfx] [PATCH] drm/i915: remove trailing semicolon in macro definition
From: Tom Rix The macro use will already have a semicolon. Signed-off-by: Tom Rix --- drivers/gpu/drm/i915/intel_device_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index e67cec8fa2aa..ef767f04c37c 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -104,7 +104,7 @@ void intel_device_info_print_static(const struct intel_device_info *info, drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); -#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)); +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)) DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); #undef PRINT_FLAG -- 2.18.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/display: Record the plane update times for debugging
Since we try and estimate how long we require to update the registers to
perform a plane update, it is of vital importance that we measure the
distribution of plane updates to better guide our estimate. If we
underestimate how long it takes to perform the plane update, we may
slip into the next scanout frame causing a tear. If we overestimate, we
may unnecessarily delay the update to the next frame, causing visible
jitter.
Replace the warning that we exceed some arbitrary threshold for the
vblank update with a histogram for debugfs.
v2: Add a per-crtc debugfs entry so that the information is easier to
extract when testing individual CRTC, and so that it can be reset before
a test.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1982
Signed-off-by: Chris Wilson
Cc: Jani Nikula
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
.../drm/i915/display/intel_display_debugfs.c | 117 ++
.../drm/i915/display/intel_display_debugfs.h | 3 +
.../drm/i915/display/intel_display_types.h| 9 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 49 +---
drivers/gpu/drm/i915/display/intel_sprite.h | 10 ++
6 files changed, 180 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ba26545392bc..9187a20a8aca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -45,6 +45,7 @@
#include "display/intel_crt.h"
#include "display/intel_ddi.h"
+#include "display/intel_display_debugfs.h"
#include "display/intel_dp.h"
#include "display/intel_dp_mst.h"
#include "display/intel_dpll_mgr.h"
@@ -17266,6 +17267,12 @@ intel_cursor_plane_create(struct drm_i915_private
*dev_priv,
return ERR_PTR(ret);
}
+static int intel_crtc_late_register(struct drm_crtc *crtc)
+{
+ intel_crtc_debugfs_add(crtc);
+ return 0;
+}
+
#define INTEL_CRTC_FUNCS \
.gamma_set = drm_atomic_helper_legacy_gamma_set, \
.set_config = drm_atomic_helper_set_config, \
@@ -17275,7 +17282,8 @@ intel_cursor_plane_create(struct drm_i915_private
*dev_priv,
.atomic_destroy_state = intel_crtc_destroy_state, \
.set_crc_source = intel_crtc_set_crc_source, \
.verify_crc_source = intel_crtc_verify_crc_source, \
- .get_crc_sources = intel_crtc_get_crc_sources
+ .get_crc_sources = intel_crtc_get_crc_sources, \
+ .late_register = intel_crtc_late_register
static const struct drm_crtc_funcs bdw_crtc_funcs = {
INTEL_CRTC_FUNCS,
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index ca41e8c00ad7..08db0ff022e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -18,6 +18,7 @@
#include "intel_pm.h"
#include "intel_psr.h"
#include "intel_sideband.h"
+#include "intel_sprite.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
@@ -865,6 +866,103 @@ static void intel_scaler_info(struct seq_file *m, struct
intel_crtc *crtc)
}
}
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
+static void crtc_updates_info(struct seq_file *m,
+ struct intel_crtc *crtc,
+ const char *hdr)
+{
+ char buf[ARRAY_SIZE(crtc->debug.vbl.times) + 1] = {};
+ int h, row, max;
+ u64 count;
+
+ max = 0;
+ count = 0;
+ for (h = 0; h < ARRAY_SIZE(crtc->debug.vbl.times); h++) {
+ if (crtc->debug.vbl.times[h] > max)
+ max = crtc->debug.vbl.times[h];
+ count += crtc->debug.vbl.times[h];
+ }
+ seq_printf(m, "%sUpdates: %llu\n", hdr, count);
+ if (!count)
+ return;
+
+ memset(buf, '-', sizeof(buf) - 1);
+ seq_printf(m, "%s |%s|\n", hdr, buf);
+
+ for (row = ilog2(max) - 1; row; row--) {
+ memset(buf, ' ', sizeof(buf) - 1);
+ for (h = 0; h < ARRAY_SIZE(crtc->debug.vbl.times); h++) {
+ if (ilog2(crtc->debug.vbl.times[h]) >= row)
+ buf[h] = '*';
+ }
+ seq_printf(m, "%s |%s|\n", hdr, buf);
+ }
+
+ memset(buf, '-', sizeof(buf) - 1);
+ seq_printf(m, "%s |%s|\n", hdr, buf);
+ seq_printf(m, "%s1us (log) 1ms\n", hdr);
+
+ seq_printf(m, "%sMin update: %lluns\n",
+ hdr, crtc->debug.vbl.min);
+ seq_printf(m, "%sMax update: %lluns\n",
+ hdr, crtc->debug.vbl.max);
+ seq_printf(m, "%sAverage update: %lluns\n",
+ hdr, div64_u64(crtc->debug.vbl.sum, count));
+ seq_printf(m, "%sOverruns > %uus: %lu\n",
+ hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over);
+}
+
+static int crtc_updates_show(struct seq_file *m,
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/gt: Replace direct submit with direct call to tasklet
== Series Details == Series: series starting with [CI,1/2] drm/i915/gt: Replace direct submit with direct call to tasklet URL : https://patchwork.freedesktop.org/series/84345/ State : success == Summary == CI Bug Log - changes from CI_DRM_9398 -> Patchwork_19000 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/index.html New tests - New tests have been introduced between CI_DRM_9398 and Patchwork_19000: ### New CI tests (1) ### * boot: - Statuses : 40 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19000 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([i915#2292]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-icl-u2/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-icl-u2/igt@i915_module_l...@reload.html - fi-cfl-8700k: [PASS][3] -> [INCOMPLETE][4] ([i915#2292]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-cfl-8700k/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-cfl-8700k/igt@i915_module_l...@reload.html - fi-kbl-r: [PASS][5] -> [DMESG-WARN][6] ([i915#2292]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-kbl-r/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-kbl-r/igt@i915_module_l...@reload.html - fi-apl-guc: [PASS][7] -> [INCOMPLETE][8] ([i915#2292]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-apl-guc/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-apl-guc/igt@i915_module_l...@reload.html - fi-bxt-dsi: [PASS][9] -> [INCOMPLETE][10] ([i915#2292]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bxt-dsi/igt@i915_module_l...@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-bxt-dsi/igt@i915_module_l...@reload.html - fi-kbl-soraka: [PASS][11] -> [INCOMPLETE][12] ([i915#2292]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-kbl-soraka/igt@i915_module_l...@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-kbl-soraka/igt@i915_module_l...@reload.html - fi-cml-s: [PASS][13] -> [INCOMPLETE][14] ([i915#2292]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-cml-s/igt@i915_module_l...@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-cml-s/igt@i915_module_l...@reload.html - fi-skl-6600u: [PASS][15] -> [DMESG-WARN][16] ([i915#2292]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-skl-6600u/igt@i915_module_l...@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-skl-6600u/igt@i915_module_l...@reload.html - fi-cfl-guc: [PASS][17] -> [INCOMPLETE][18] ([i915#2292]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-cfl-guc/igt@i915_module_l...@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-cfl-guc/igt@i915_module_l...@reload.html - fi-tgl-u2: [PASS][19] -> [INCOMPLETE][20] ([i915#2292]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-u2/igt@i915_module_l...@reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-tgl-u2/igt@i915_module_l...@reload.html - fi-bsw-n3050: [PASS][21] -> [INCOMPLETE][22] ([i915#2292]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bsw-n3050/igt@i915_module_l...@reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-bsw-n3050/igt@i915_module_l...@reload.html - fi-skl-6700k2: [PASS][23] -> [INCOMPLETE][24] ([i915#2292]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-skl-6700k2/igt@i915_module_l...@reload.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-skl-6700k2/igt@i915_module_l...@reload.html - fi-bsw-kefka: [PASS][25] -> [INCOMPLETE][26] ([i915#2292]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bsw-kefka/igt@i915_module_l...@reload.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-bsw-kefka/igt@i915_module_l...@reload.html - fi-bdw-5557u: [PASS][27] -> [INCOMPLETE][28] ([i915#2292]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bdw-5557u/igt@i915_module_l...@reload.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19000/fi-bdw-5557u/igt@i915_module_l...@reload.html - fi-glk-dsi: [PASS][29] -> [INCOMPLETE][30] ([i915#2292]) [29]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/2] drm/i915/gt: Replace direct submit with direct call to tasklet
== Series Details == Series: series starting with [CI,1/2] drm/i915/gt: Replace direct submit with direct call to tasklet URL : https://patchwork.freedesktop.org/series/84345/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1328:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1447:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1501:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.BAT: failure for DG1 + LMEM enabling
== Series Details ==
Series: DG1 + LMEM enabling
URL : https://patchwork.freedesktop.org/series/84344/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9398 -> Patchwork_18999
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_18999 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18999, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_18999:
### IGT changes ###
Possible regressions
* igt@core_hotunplug@unbind-rebind:
- fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-byt-j1900/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-byt-j1900/igt@core_hotunp...@unbind-rebind.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
- fi-glk-dsi: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-glk-dsi/igt@i915_selftest@live@gt_lrc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-glk-dsi/igt@i915_selftest@live@gt_lrc.html
- fi-bsw-nick:[PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bsw-nick/igt@i915_selftest@live@gt_lrc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-bsw-nick/igt@i915_selftest@live@gt_lrc.html
- fi-apl-guc: [PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-apl-guc/igt@i915_selftest@live@gt_lrc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-apl-guc/igt@i915_selftest@live@gt_lrc.html
- fi-bxt-dsi: [PASS][11] -> [DMESG-FAIL][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bxt-dsi/igt@i915_selftest@live@gt_lrc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-bxt-dsi/igt@i915_selftest@live@gt_lrc.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_parallel@engines@userptr}:
- fi-kbl-r: [PASS][13] -> [FAIL][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-kbl-r/igt@gem_exec_parallel@engi...@userptr.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-kbl-r/igt@gem_exec_parallel@engi...@userptr.html
- fi-cfl-8109u: [PASS][15] -> [FAIL][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-cfl-8109u/igt@gem_exec_parallel@engi...@userptr.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-cfl-8109u/igt@gem_exec_parallel@engi...@userptr.html
- {fi-tgl-dsi}: [PASS][17] -> [FAIL][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-dsi/igt@gem_exec_parallel@engi...@userptr.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-tgl-dsi/igt@gem_exec_parallel@engi...@userptr.html
- fi-blb-e6850: [PASS][19] -> [FAIL][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-blb-e6850/igt@gem_exec_parallel@engi...@userptr.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-blb-e6850/igt@gem_exec_parallel@engi...@userptr.html
- fi-bsw-nick:[PASS][21] -> [FAIL][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bsw-nick/igt@gem_exec_parallel@engi...@userptr.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-bsw-nick/igt@gem_exec_parallel@engi...@userptr.html
- fi-bxt-dsi: [PASS][23] -> [FAIL][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bxt-dsi/igt@gem_exec_parallel@engi...@userptr.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-bxt-dsi/igt@gem_exec_parallel@engi...@userptr.html
- fi-apl-guc: [PASS][25] -> [FAIL][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-apl-guc/igt@gem_exec_parallel@engi...@userptr.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18999/fi-apl-guc/igt@gem_exec_parallel@engi...@userptr.html
- fi-icl-y: [PASS][27] -> [FAIL][28]
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-icl-y/igt@gem_exec_parallel@engi...@userptr.html
Re: [Intel-gfx] [PATCH] Revert "drm/i915: re-order if/else ladder for hpd_irq_setup"
On Fri, 27 Nov 2020, Chris Wilson wrote:
> We now use ilk_hpd_irq_setup for all GMCH platforms that do not have
> hotplug. These are early gen3 and gen2 devices that now explode on boot
> as they try to access non-existent registers.
>
> Fixes: 794d61a19090 ("drm/i915: re-order if/else ladder for hpd_irq_setup")
> Signed-off-by: Chris Wilson
> Cc: Lucas De Marchi
> Cc: José Roberto de Souza
> Cc: Jani Nikula
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_irq.c | 27 +++
> 1 file changed, 15 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index dc6febc63f1c..c80eeac53952 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4242,18 +4242,21 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>*/
> dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
>
> - if (HAS_PCH_DG1(dev_priv))
> - dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
> - else if (INTEL_GEN(dev_priv) >= 11)
> - dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> - else if (IS_GEN9_LP(dev_priv))
> - dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> - dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> - else if (HAS_GMCH(dev_priv) && I915_HAS_HOTPLUG(dev_priv))
> - dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> - else
> - dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
> + if (HAS_GMCH(dev_priv)) {
> + if (I915_HAS_HOTPLUG(dev_priv))
> + dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> + } else {
> + if (HAS_PCH_DG1(dev_priv))
> + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
> + else if (INTEL_GEN(dev_priv) >= 11)
> + dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> + else if (IS_GEN9_LP(dev_priv))
> + dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> + dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> + else
> + dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
> + }
> }
>
> /**
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
On Fri, Nov 27, 2020 at 04:31:00PM +0200, Imre Deak wrote:
> Hi Daniel, Jani,
>
> is it ok to merge this patch along with 2/2 via the i915 tree?
Ack from mesa (userspace in general, but mesa is kinda mandatory) is
missing I think. With that
Acked-by: Daniel Vetter
>
> --Imre
>
> On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> > From: Radhakrishna Sripada
> >
> > Gen12 display can decompress surfaces compressed by render engine with
> > Clear Color, add a new modifier as the driver needs to know the surface
> > was compressed by render engine.
> >
> > V2: Description changes as suggested by Rafael.
> > V3: Mention the Clear Color size of 64 bits in the comments(DK)
> > v4: Fix trailing whitespaces
> > v5: Explain Clear Color in the documentation.
> > v6: Documentation Nitpicks(Nanley)
> >
> > Cc: Ville Syrjala
> > Cc: Dhinakaran Pandiyan
> > Cc: Kalyan Kondapally
> > Cc: Rafael Antognolli
> > Cc: Nanley Chery
> > Signed-off-by: Radhakrishna Sripada
> > Signed-off-by: Imre Deak
> > ---
> > include/uapi/drm/drm_fourcc.h | 19 +++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index ca48ed0e6bc1..0a1b2c4c4bee 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -527,6 +527,25 @@ extern "C" {
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
> >
> > +/*
> > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> > + * compression.
> > + *
> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> > linear
> > + * and at index 1. The clear color is stored at index 2, and the pitch
> > should
> > + * be ignored. The clear color structure is 256 bits. The first 128 bits
> > + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> > represented
> > + * by 32 bits. The raw clear color is consumed by the 3d engine and
> > generates
> > + * the converted clear color of size 64 bits. The first 32 bits store the
> > Lower
> > + * Converted Clear Color value and the next 32 bits store the Higher
> > Converted
> > + * Clear Color value when applicable. The Converted Clear Color values are
> > + * consumed by the DE. The last 64 bits are used to store Color Discard
> > Enable
> > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache
> > line
> > + * corresponds to an area of 4x1 tiles in the main surface. The main
> > surface
> > + * pitch is required to be a multiple of 4 tile widths.
> > + */
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > *
> > --
> > 2.25.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for DG1 + LMEM enabling
== Series Details == Series: DG1 + LMEM enabling URL : https://patchwork.freedesktop.org/series/84344/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1414: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1414: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1414: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1414: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1414: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -sphinx-version 1.7.9 -function Logical Rings, Logical Ring Contexts and Execlists ./drivers/gpu/drm/i915/gt/intel_lrc.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DG1 + LMEM enabling
== Series Details == Series: DG1 + LMEM enabling URL : https://patchwork.freedesktop.org/series/84344/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1237:15:expected void *vaddr +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1237:15:got void [noderef] __iomem * +drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1237:15: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_object.c:496:21:expected void *vaddr +drivers/gpu/drm/i915/gem/i915_gem_object.c:496:21:got void [noderef] __iomem * +drivers/gpu/drm/i915/gem/i915_gem_object.c:496:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_object.c:503:30:expected void [noderef] __iomem *vaddr +drivers/gpu/drm/i915/gem/i915_gem_object.c:503:30:got void *vaddr +drivers/gpu/drm/i915/gem/i915_gem_object.c:503:30: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_region.c:299:34:expected unsigned long long [usertype] *s +drivers/gpu/drm/i915/gem/i915_gem_region.c:299:34:got void [noderef] __iomem *[assigned] vaddr +drivers/gpu/drm/i915/gem/i915_gem_region.c:299:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/gen8_engine_cs.c:109:5: warning: symbol 'gen11_emit_flush_render' was not declared. Should it be static? +drivers/gpu/drm/i915/gt/gen8_engine_cs.c:11:5: warning: symbol 'gen8_emit_flush_render' was not declared. Should it be static? +drivers/gpu/drm/i915/gt/gen8_engine_cs.c:201:5: warning: symbol 'gen12_emit_flush_render' was not declared. Should it be static? +drivers/gpu/drm/i915/gt/gen8_engine_cs.c:271:5: warning: symbol 'gen12_emit_flush' was not declared. Should it be static? +drivers/gpu/drm/i915/gt/gen8_engine_cs.c:332:5: warning: symbol 'gen8_emit_bb_start_noarb' was not declared. Should it be static? +drivers/gpu/drm/i915/gt/gen8_engine_cs.c:368:5: warning: symbol 'gen8_emit_bb_start' was not declared. Should it be static? +drivers/gpu/drm/i915/gt/gen8_engine_cs.c:77:5: warning: symbol 'gen8_emit_flush' was not declared. Should it be static? +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1229:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:616:35:expected void const *from +drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:616:35:got void [noderef] __iomem * +drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:616:35: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +drivers/gpu/drm/i915/selftests/intel_memory_region.c:689:23:expected void [noderef] __iomem *vaddr +drivers/gpu/drm/i915/selftests/intel_memory_region.c:689:23:got void * +drivers/gpu/drm/i915/selftests/intel_memory_region.c:689:23: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/selftests/intel_memory_region.c:698:40:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/selftests/intel_memory_region.c:698:40:got void [noderef] __iomem * +drivers/gpu/drm/i915/selftests/intel_memory_region.c:698:40: warning: incorrect type in argument 1 (different address spaces) +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 -O:drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s -O:drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s -O:drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] Revert "drm/i915: re-order if/else ladder for hpd_irq_setup"
We now use ilk_hpd_irq_setup for all GMCH platforms that do not have
hotplug. These are early gen3 and gen2 devices that now explode on boot
as they try to access non-existent registers.
Fixes: 794d61a19090 ("drm/i915: re-order if/else ladder for hpd_irq_setup")
Signed-off-by: Chris Wilson
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_irq.c | 27 +++
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dc6febc63f1c..c80eeac53952 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4242,18 +4242,21 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
*/
dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
- if (HAS_PCH_DG1(dev_priv))
- dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
- else if (INTEL_GEN(dev_priv) >= 11)
- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
- else if (IS_GEN9_LP(dev_priv))
- dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
- else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
- else if (HAS_GMCH(dev_priv) && I915_HAS_HOTPLUG(dev_priv))
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
- else
- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ if (HAS_GMCH(dev_priv)) {
+ if (I915_HAS_HOTPLUG(dev_priv))
+ dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ } else {
+ if (HAS_PCH_DG1(dev_priv))
+ dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ else if (INTEL_GEN(dev_priv) >= 11)
+ dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+ else if (IS_GEN9_LP(dev_priv))
+ dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
+ dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ else
+ dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ }
}
/**
--
2.20.1
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG1 + LMEM enabling
== Series Details ==
Series: DG1 + LMEM enabling
URL : https://patchwork.freedesktop.org/series/84344/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ecc99f864651 drm/i915/selftest: also consider non-contiguous objects
3c1e72a3ebbe drm/i915/selftest: assert we get 2M GTT pages
-:21: CHECK:LINE_SPACING: Please don't use multiple blank lines
#21: FILE: drivers/gpu/drm/i915/gem/selftests/huge_pages.c:371:
+
-:41: CHECK:LINE_SPACING: Please don't use multiple blank lines
#41: FILE: drivers/gpu/drm/i915/gem/selftests/huge_pages.c:391:
+
+
total: 0 errors, 0 warnings, 2 checks, 27 lines checked
37a823615518 drm/i915/selftest: handle local-memory in perf_memcpy
5e4d77873cee drm/i915/gt: Move move context layout registers and offsets to
lrc_reg.h
ec25b9b7e7bf drm/i915/gt: Rename lrc.c to execlists_submission.c
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#79:
rename from drivers/gpu/drm/i915/gt/intel_lrc.c
total: 0 errors, 1 warnings, 0 checks, 177 lines checked
eb9b76584a33 drm/i915: split gen8+ flush and bb_start emission functions to
their own file
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#31:
new file mode 100644
-:220: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'aux_inv_reg', this function's name, in a string
#220: FILE: drivers/gpu/drm/i915/gt/gen8_engine_cs.c:185:
+ GEM_BUG_ON("unknown aux_inv_reg\n");
-:428: CHECK:LINE_SPACING: Please don't use multiple blank lines
#428: FILE: drivers/gpu/drm/i915/gt/gen8_engine_cs.c:393:
+
+
total: 0 errors, 2 warnings, 1 checks, 829 lines checked
4d3a6e1b drm/i915: split wa_bb code to its own file
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#29:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 701 lines checked
151185a3fc12 HAX drm/i915: Work around the selftest timeline lock splat
workaround
450f75d41b63 drm/i915: Introduce drm_i915_lock_isolated
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'obj' - possible side-effects?
#25: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:110:
+#define object_is_isolated(obj)\
+ (!IS_ENABLED(CONFIG_LOCKDEP) || \
+((kref_read(>base.refcount) == 0) || \
+ ((kref_read(>base.refcount) == 1) && \
+ list_empty_careful(>mm.link) && \
+ list_empty_careful(>vma.list
-:25: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'obj' may be better as '(obj)'
to avoid precedence issues
#25: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:110:
+#define object_is_isolated(obj)\
+ (!IS_ENABLED(CONFIG_LOCKDEP) || \
+((kref_read(>base.refcount) == 0) || \
+ ((kref_read(>base.refcount) == 1) && \
+ list_empty_careful(>mm.link) && \
+ list_empty_careful(>vma.list
total: 0 errors, 0 warnings, 2 checks, 28 lines checked
dcd32ce75f16 drm/i915: Lock hwsp objects isolated for pinning at create time
2e77f388c53a drm/i915: Pin timeline map after first timeline pin, v5.
4277aa6901de drm/i915: Move cmd parser pinning to execbuffer
1ac931e19fb2 drm/i915: Add missing -EDEADLK handling to execbuf pinning, v2.
-:55: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#55: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:451:
+ err = i915_vma_pin_ww(vma, >ww,
entry->pad_to_size,
total: 0 errors, 0 warnings, 1 checks, 75 lines checked
52b472892a57 drm/i915: Ensure we hold the object mutex in pin correctly v2
67281c042a1c drm/i915: Add gem object locking to madvise.
d6f3a6ff8ec5 drm/i915: Move HAS_STRUCT_PAGE to obj->flags
-:110: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#110: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.c:63:
+ struct lock_class_key *key, unsigned flags)
-:133: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#133: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:27:
+ unsigned alloc_flags);
total: 0 errors, 2 warnings, 0 checks, 348 lines checked
f5fd74ff0eb5 drm/i915: Rework struct phys attachment handling
f2139104bdcb drm/i915: Convert i915_gem_object_attach_phys() to ww locking, v2.
8625ed6419dc drm/i915: make lockdep slightly happier about execbuf.
1eaf989afae0 drm/i915: Disable userptr pread/pwrite support.
eae3f2ab3922 drm/i915: No longer allow exporting userptr through dma-buf
b78c8c467a1f drm/i915: Reject more ioctls for userptr
cccfa9edcf51 drm/i915: Reject UNSYNCHRONIZED for userptr, v2.
154de4c68c26 drm/i915: Make compilation of userptr code depend on MMU_NOTIFIER.
7523423fd46d drm/i915: Fix userptr so we do not
Re: [Intel-gfx] [v12 11/15] drm/i915/lspcon: Create separate infoframe_enabled helper
On Fri, Nov 27, 2020 at 02:33:10AM +0530, Uma Shankar wrote:
> Lspcon has Infoframes as well as DIP for HDR metadata(DRM Infoframe).
> Create a separate mechanism for lspcon compared to HDMI in order to
> address the same and ensure future scalability.
>
> v2: Streamlined this as per Ville's suggestions, making sure that
> HDMI infoframe versions are directly returned instead of a redundant
> and confusing DIP overhead.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c| 10 +++---
> drivers/gpu/drm/i915/display/intel_lspcon.c | 9 +
> drivers/gpu/drm/i915/display/intel_lspcon.h | 2 ++
> 3 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 92940a0c5ef8..48da5dc59939 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4583,6 +4583,7 @@ static void intel_ddi_read_func_ctl(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> u32 temp, flags = 0;
>
> temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> @@ -4657,9 +4658,12 @@ static void intel_ddi_read_func_ctl(struct
> intel_encoder *encoder,
> pipe_config->fec_enable);
> }
>
> - pipe_config->infoframes.enable |=
> - intel_hdmi_infoframes_enabled(encoder, pipe_config);
> -
> + if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
> + pipe_config->infoframes.enable |=
> + intel_lspcon_infoframes_enabled(encoder,
> pipe_config);
> + else
> + pipe_config->infoframes.enable |=
> + intel_hdmi_infoframes_enabled(encoder,
> pipe_config);
> break;
> case TRANS_DDI_MODE_SELECT_DP_MST:
> pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 592c19deba00..303f23d35020 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -30,6 +30,7 @@
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_lspcon.h"
> +#include "intel_hdmi.h"
Why do you need that header?
With that potentially removed if it's not needed.
Reviewed-by: Ville Syrjälä
>
> /* LSPCON OUI Vendor ID(signatures) */
> #define LSPCON_VENDOR_PARADE_OUI 0x001CF8
> @@ -601,6 +602,14 @@ bool lspcon_init(struct intel_digital_port *dig_port)
> return true;
> }
>
> +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
> + const struct intel_crtc_state *pipe_config)
> +{
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> + return dig_port->infoframes_enabled(encoder, pipe_config);
> +}
> +
> void lspcon_resume(struct intel_digital_port *dig_port)
> {
> struct intel_lspcon *lspcon = _port->lspcon;
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
> b/drivers/gpu/drm/i915/display/intel_lspcon.h
> index 42ccb21c908f..44aa6bc38512 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> @@ -33,6 +33,8 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state);
> u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config);
> +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
> + const struct intel_crtc_state *pipe_config);
> void hsw_write_infoframe(struct intel_encoder *encoder,
>const struct intel_crtc_state *crtc_state,
>unsigned int type,
> --
> 2.26.2
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [v12 14/15] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks
On Fri, Nov 27, 2020 at 02:33:13AM +0530, Uma Shankar wrote:
> Non-HDMI sinks shouldn't be sent Dynamic Range and Mastering infoframes.
> Check for that when using LSPCON.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 48da5dc59939..07bef90e149e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4118,6 +4118,7 @@ static void intel_enable_ddi_dp(struct
> intel_atomic_state *state,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> enum port port = encoder->port;
>
> if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
> @@ -4125,7 +4126,14 @@ static void intel_enable_ddi_dp(struct
> intel_atomic_state *state,
>
> intel_edp_backlight_on(crtc_state, conn_state);
> intel_psr_enable(intel_dp, crtc_state, conn_state);
> - intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> +
> + if (dig_port->lspcon.active) {
> + if (dig_port->dp.has_hdmi_sink)
> + intel_dp_set_infoframes(encoder, true, crtc_state,
> conn_state);
> + } else {
> + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> + }
Simplify to
if (!lspcon || has_hdmi_sink)
intel_dp_set_infoframes()
?
Some time ago I was pondering if we should start to use
crtc_state->has_hdmi_sink for DP too, but since we have no
way to do readout for it I'm not sure it can be done in a sane way.
I guess in the meantime I guess we need something like this.
Reviewed-by: Ville Syrjälä
> +
> intel_edp_drrs_enable(intel_dp, crtc_state);
>
> if (crtc_state->has_audio)
> --
> 2.26.2
--
Ville Syrjälä
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Record the plane update times for debugging (rev7)
== Series Details ==
Series: drm/i915/display: Record the plane update times for debugging (rev7)
URL : https://patchwork.freedesktop.org/series/84174/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9398 -> Patchwork_18998
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/index.html
New tests
-
New tests have been introduced between CI_DRM_9398 and Patchwork_18998:
### New CI tests (1) ###
* boot:
- Statuses : 39 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18998 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-open:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@gem_flink_ba...@bad-open.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-tgl-y/igt@gem_flink_ba...@bad-open.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-y: [PASS][3] -> [DMESG-FAIL][4] ([i915#2601])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
Possible fixes
* igt@gem_flink_basic@bad-flink:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-ehl-1}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-ehl-1/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-y: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-n3050: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-kbl-soraka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-apl-guc: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-apl-guc/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-apl-guc/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][19] ([i915#165]) -> [PASS][20] +15
similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18998/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 39)
--
Re: [Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2
On Wed, Nov 25, 2020 at 05:52:10PM +, Souza, Jose wrote: > On Wed, 2020-11-25 at 18:17 +0200, Ville Syrjälä wrote: > > On Tue, Nov 24, 2020 at 10:03:35PM +, Souza, Jose wrote: > > > On Fri, 2020-11-20 at 01:06 +0530, Uma Shankar wrote: > > > > There are some corner cases wrt underrun when we enable > > > > FBC with PSR2 on TGL. Recommendation from hardware is to > > > > keep this combination disabled. > > > > > > > > Bspec: 50422 HSD: 14010260002 > > > > > > > > v2: Added psr2 enabled check from crtc_state (Anshuman) > > > > Added Bspec link and HSD referneces (Jose) > > > > > > > > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache > > > > and removed the crtc->config usages, as per Ville's recommendation. > > > > > > > > Signed-off-by: Uma Shankar > > > > --- > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 9 + > > > > 1 file changed, 9 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > index a5b072816a7b..cb29c6f068f9 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > @@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct > > > > intel_crtc *crtc, > > > > struct drm_framebuffer *fb = plane_state->hw.fb; > > > > > > > > > > > > > > > > > > > > cache->plane.visible = plane_state->uapi.visible; > > > > + > > > > + /* > > > > +* Tigerlake is not supporting FBC with PSR2. > > > > +* Recommendation is to keep this combination disabled > > > > +* Bspec: 50422 HSD: 14010260002 > > > > +*/ > > > > + if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv)) > > > > + cache->plane.visible = false; > > > > > > Looks like a hack to me, would be better add a psr2 variable in > > > intel_fbc_state_cache. > > > > The plan is to remove most things from that cache anyway since it's > > mostly pointless stuff that should just be handled directly via > > the plane/crtc states. Not really convinced it makes sense to add > > more crap to it at this time. So IMO this is good enough for now. > > When this will happen? if soon okay. > If there is no ETA IMHO is better do the right thing. I was hoping to get back to it soon, but looks like there's quite a bit more urgent work ahead for the moment. So don't know when I'll get back to this. So I guess path of least resitance would be for Uma to respin with your suggested approach. It was one of the solutions I also suggested originally, but I did also suggest this simpler version Uma actually did. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 160/162] drm/i915/dg1: Fix GPU hang due to shmemfs page drop
Quoting Matthew Auld (2020-11-27 12:07:16)
> From: Venkata Ramana Nayana
>
> This is to fix a bug in upstream
> commit a6326a4f8ffb ("drm/i915/gt: Keep a no-frills swappable copy of the
> default context state")
>
> We allocate context state obj ce->state from lmem, so in
> __engines_record_defaults(),
> we call shmem_create_from_object(). Because it is lmem object, this call will
> create a new shmemfs file, copy the contents into it, and return the file
> pointer and assign to engine->default_state. Of course ce->state lmem object
> is freed at the end of function __engines_record_redefaults().
>
> Because a new shmemfs file is create for engine->default_state,
> and more importantly, we DON'T mark the pages dirty after we write into it,
> the OS page cache eviction will drop these pages.
>
> Now with the test move forward, it will create new request/context, and will
> copy the saved engine->default_state into ce->state. If the default_state
> pages are dropped during page cache eviction, the copying will get new pages,
> and copy garbage from the new pages. Next, ce->state will have wrong
> instruction and causes GPU to hang.
>
> The fixing is very simple, we just mark the shmemfs pages to be dirty when
> writing into it, and also mark the pages to accessed when read/write to them.
>
> Fixes: a6326a4f8ffb("drm/i915/gt: Keep a no-frills swappable copy of the
> default context state")
A bug fix, send it. But please write a concise changelog first.
I missed setting the dirty bit, and so the contents were not being saved
on swap out as expected. Impact is severe; any context created after
resume may be gibberish.
-Chris
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Re: [Intel-gfx] [RFC PATCH 157/162] drm/i915: Improve accuracy of eviction stats
Quoting Matthew Auld (2020-11-27 12:07:13) > From: Tvrtko Ursulin > > Current code uses jiffie time to do the accounting and then does: > > diff = jiffies - start; > msec = diff * 1000 / HZ; > ... > atomic_long_add(msec, >time_swap_out_ms); > > If we assume jiffie can be as non-granular as 10ms and that the current > accounting records all evictions faster than one jiffie as infinite speed, > we can end up over-estimating the reported eviction throughput. > > Fix this by accumulating ktime_t and only dividing to more user friendly > granularity at presentation time (debugfs read). > > At the same time consolidate the code a bit and convert from multiple > atomics to single seqlock per stat. > > Signed-off-by: Tvrtko Ursulin > Cc: CQ Tang > Cc: Sudeep Dutt > Cc: Mika Kuoppala A lot of effort to fix up patches after the fact, might as well make it a real PMU interface. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 150/162] drm/i915: need consider system BO snoop for dgfx
Quoting Matthew Auld (2020-11-27 12:07:06)
> From: CQ Tang
>
> When cache_level is NONE, we check HAS_LLC(i915).
> But additionally for DGFX, we also need to check
> HAS_SNOOP(i915) on system memory object to use
> I915_BO_CACHE_COHERENT_FOR_READ. on dg1, has_llc=0, and
> has_snoop=1. Otherwise, we set obj->cache_choerent=0 and
> have performance impact.
>
> Cc: Chris P Wilson
> Cc: Ramalingam C
> Cc: Sudeep Dutt
> Cc: Matthew Auld
> Signed-off-by: CQ Tang
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index ddb448f275eb..be603171c444 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -95,6 +95,20 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
> mutex_init(>mm.get_dma_page.lock);
> }
>
> +static bool i915_gem_object_use_llc(struct drm_i915_gem_object *obj)
> +{
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> +
> + if (HAS_LLC(i915))
> + return true;
> +
> + if (IS_DGFX(i915) && HAS_SNOOP(i915) &&
> + !i915_gem_object_is_lmem(obj))
> + return true;
> +
> + return false;
> +}
> +
> /**
> * Mark up the object's coherency levels for a given cache_level
> * @obj: #drm_i915_gem_object
> @@ -108,7 +122,7 @@ void i915_gem_object_set_cache_coherency(struct
> drm_i915_gem_object *obj,
> if (cache_level != I915_CACHE_NONE)
> obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ |
>I915_BO_CACHE_COHERENT_FOR_WRITE);
> - else if (HAS_LLC(to_i915(obj->base.dev)))
> + else if (i915_gem_object_use_llc(obj))
> obj->cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ;
> else
> obj->cache_coherent = 0;
You must also define obj->cache_level correctly. You can not just assume
the object will be snooped.
-Chris
-
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[Intel-gfx] [PATCH v3 3/4] drm/i915/display/psr: Program plane's calculated offset to plane SF register
It programs Plane's calculated x, y, offset to Plane SF register. It does the calculation of x and y offsets using skl_calc_main_surface_offset(). v3: Update commit message Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun Tested-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d9a395c486d3..463654e2c1c7 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1186,7 +1186,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; const struct drm_rect *clip; - u32 val; + u32 val, offset; + int ret, x, y; if (!crtc_state->enable_psr2_sel_fetch) return; @@ -1203,9 +1204,14 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, val |= plane_state->uapi.dst.x1; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); - /* TODO: consider tiling and auxiliary surfaces */ - val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16; - val |= plane_state->color_plane[color_plane].x; + /* TODO: consider auxiliary surfaces */ + x = plane_state->uapi.src.x1 >> 16; + y = (plane_state->uapi.src.y1 >> 16) + clip->y1; + ret = skl_calc_main_surface_offset(plane_state, , , ); + if (ret) + drm_warn_once(_priv->drm, "skl_calc_main_surface_offset() returned %i\n", + ret); + val = y << 16 | x; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), val); -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 4/4] HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing
Enabling it to check if it causes regressions in CI but the feature is still not ready to be enabled by default. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 330c03e2b4f7..b8b19270c339 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,7 +54,7 @@ struct drm_printer; param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0600) \ - param(bool, enable_psr2_sel_fetch, false, 0600) \ + param(bool, enable_psr2_sel_fetch, true, 0600) \ param(int, disable_power_well, -1, 0400) \ param(int, enable_ips, 1, 0600) \ param(int, invert_brightness, 0, 0600) \ -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/4] drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c | 78
drivers/gpu/drm/i915/display/intel_display.h | 2 +
2 files changed, 51 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ba26545392bc..1844dd028db2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3817,33 +3817,19 @@ static int intel_plane_max_height(struct intel_plane
*plane,
return INT_MAX;
}
-static int skl_check_main_surface(struct intel_plane_state *plane_state)
+int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
+int *x, int *y, u32 *offset)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
- unsigned int rotation = plane_state->hw.rotation;
- int x = plane_state->uapi.src.x1 >> 16;
- int y = plane_state->uapi.src.y1 >> 16;
- int w = drm_rect_width(_state->uapi.src) >> 16;
- int h = drm_rect_height(_state->uapi.src) >> 16;
- int min_width = intel_plane_min_width(plane, fb, 0, rotation);
- int max_width = intel_plane_max_width(plane, fb, 0, rotation);
- int max_height = intel_plane_max_height(plane, fb, 0, rotation);
- int aux_plane = intel_main_to_aux_plane(fb, 0);
- u32 aux_offset = plane_state->color_plane[aux_plane].offset;
- u32 alignment, offset;
+ const int aux_plane = intel_main_to_aux_plane(fb, 0);
+ const u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ const u32 alignment = intel_surf_alignment(fb, 0);
+ const int w = drm_rect_width(_state->uapi.src) >> 16;
- if (w > max_width || w < min_width || h > max_height) {
- drm_dbg_kms(_priv->drm,
- "requested Y/RGB source size %dx%d outside limits
(min: %dx1 max: %dx%d)\n",
- w, h, min_width, max_width, max_height);
- return -EINVAL;
- }
-
- intel_add_fb_offsets(, , plane_state, 0);
- offset = intel_plane_compute_aligned_offset(, , plane_state, 0);
- alignment = intel_surf_alignment(fb, 0);
+ intel_add_fb_offsets(x, y, plane_state, 0);
+ *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
if (drm_WARN_ON(_priv->drm, alignment && !is_power_of_2(alignment)))
return -EINVAL;
@@ -3852,9 +3838,10 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
* main surface offset, and it must be non-negative. Make
* sure that is what we will get.
*/
- if (aux_plane && offset > aux_offset)
- offset = intel_plane_adjust_aligned_offset(, , plane_state,
0,
- offset, aux_offset &
~(alignment - 1));
+ if (aux_plane && *offset > aux_offset)
+ *offset = intel_plane_adjust_aligned_offset(x, y, plane_state,
0,
+ *offset,
+ aux_offset &
~(alignment - 1));
/*
* When using an X-tiled surface, the plane blows up
@@ -3865,18 +3852,51 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
int cpp = fb->format->cpp[0];
- while ((x + w) * cpp > plane_state->color_plane[0].stride) {
- if (offset == 0) {
+ while ((*x + w) * cpp > plane_state->color_plane[0].stride) {
+ if (*offset == 0) {
drm_dbg_kms(_priv->drm,
"Unable to find suitable display
surface offset due to X-tiling\n");
return -EINVAL;
}
- offset = intel_plane_adjust_aligned_offset(, ,
plane_state, 0,
- offset,
offset - alignment);
+ *offset = intel_plane_adjust_aligned_offset(x, y,
plane_state, 0,
+ *offset,
+ *offset -
alignment);
}
}
+ return 0;
+}
+
+static int skl_check_main_surface(struct intel_plane_state *plane_state)
[Intel-gfx] [PATCH v3 1/4] drm/i915/display/psr: Calculate selective fetch plane registers
Add the calculations to set plane selective fetch registers depending
in the value of the area damaged.
It is still using the whole plane area as damaged but that will change
in next patches.
v2:
- fixed new_plane_state->uapi.dst.y2 typo in
intel_psr2_sel_fetch_update()
- do not shifthing new_plane_state->uapi.dst only src is in 16.16 format
BSpec: 55229
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by: Gwan-gyeong Mun
---
.../drm/i915/display/intel_display_types.h| 2 ++
drivers/gpu/drm/i915/display/intel_psr.c | 22 ++-
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ce82d654d0f2..3a18aaf907cc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -604,6 +604,8 @@ struct intel_plane_state {
u32 planar_slave;
struct drm_intel_sprite_colorkey ckey;
+
+ struct drm_rect psr2_sel_fetch_area;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index b3631b722de3..d9a395c486d3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1185,6 +1185,7 @@ void intel_psr2_program_plane_sel_fetch(struct
intel_plane *plane,
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
+ const struct drm_rect *clip;
u32 val;
if (!crtc_state->enable_psr2_sel_fetch)
@@ -1196,16 +1197,20 @@ void intel_psr2_program_plane_sel_fetch(struct
intel_plane *plane,
if (!val || plane->id == PLANE_CURSOR)
return;
- val = plane_state->uapi.dst.y1 << 16 | plane_state->uapi.dst.x1;
+ clip = _state->psr2_sel_fetch_area;
+
+ val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
+ val |= plane_state->uapi.dst.x1;
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
- val = plane_state->color_plane[color_plane].y << 16;
+ /* TODO: consider tiling and auxiliary surfaces */
+ val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16;
val |= plane_state->color_plane[color_plane].x;
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
val);
/* Sizes are 0 based */
- val = ((drm_rect_height(_state->uapi.src) >> 16) - 1) << 16;
+ val = (drm_rect_height(clip) - 1) << 16;
val |= (drm_rect_width(_state->uapi.src) >> 16) - 1;
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
}
@@ -1279,7 +1284,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state
*state,
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
new_plane_state, i) {
- struct drm_rect temp;
+ struct drm_rect *sel_fetch_area, temp;
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
continue;
@@ -1302,8 +1307,13 @@ int intel_psr2_sel_fetch_update(struct
intel_atomic_state *state,
* For now doing a selective fetch in the whole plane area,
* optimizations will come in the future.
*/
- temp.y1 = new_plane_state->uapi.dst.y1;
- temp.y2 = new_plane_state->uapi.dst.y2;
+ sel_fetch_area = _plane_state->psr2_sel_fetch_area;
+ sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16;
+ sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16;
+
+ temp = *sel_fetch_area;
+ temp.y1 += new_plane_state->uapi.dst.y1;
+ temp.y2 += new_plane_state->uapi.dst.y2;
clip_area_update(_clip, );
}
--
2.29.2
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Re: [Intel-gfx] [RFC PATCH 148/162] drm/i915: suspend/resume enable blitter eviction
Quoting Matthew Auld (2020-11-27 12:07:04) > From: Venkata Ramana Nayana > > In suspend mode use blitter eviction before disable the runtime > interrupts and in resume use blitter after the gem resume happens. Consider add it to the suspend prepare function. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
Hi Daniel, Jani,
is it ok to merge this patch along with 2/2 via the i915 tree?
--Imre
On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote:
> From: Radhakrishna Sripada
>
> Gen12 display can decompress surfaces compressed by render engine with
> Clear Color, add a new modifier as the driver needs to know the surface
> was compressed by render engine.
>
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
>
> Cc: Ville Syrjala
> Cc: Dhinakaran Pandiyan
> Cc: Kalyan Kondapally
> Cc: Rafael Antognolli
> Cc: Nanley Chery
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Imre Deak
> ---
> include/uapi/drm/drm_fourcc.h | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ca48ed0e6bc1..0a1b2c4c4bee 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -527,6 +527,25 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128 bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> + * the converted clear color of size 64 bits. The first 32 bits store the
> Lower
> + * Converted Clear Color value and the next 32 bits store the Higher
> Converted
> + * Clear Color value when applicable. The Converted Clear Color values are
> + * consumed by the DE. The last 64 bits are used to store Color Discard
> Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> --
> 2.25.1
>
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Re: [Intel-gfx] [RFC PATCH 147/162] drm/i915/gt: Allocate default ctx objects in SMEM
Quoting Matthew Auld (2020-11-27 12:07:03) > From: Venkata Ramana Nayana > > If record default objects are created in LMEM and in suspend > pin the pages of obj (src) and use blitter for eviction. But > during request creation using blitter context and try to pin the same > default object, to restore the ctx with default HW values, will leads to > the dead lock situation. To avoid this, safe to keep these > objects in SMEM. Dead patch. Default object state should be recorded as shmemfs. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 146/162] drm/i915/pm: suspend and restore ppgtt mapping
Quoting Matthew Auld (2020-11-27 12:07:02)
> From: Prathap Kumar Valsan
>
> During suspend we will lose all page tables as they are allocated in
> LMEM. In-order to make sure that the contexts do not access the
> corrupted page table after we restore, we are evicting all vma's that
> are bound to vm's. This includes kernel vm.
>
> During resume, we are restoring the page tables back to scratch page.
>
> Signed-off-by: Prathap Kumar Valsan
> Signed-off-by: Venkata Ramana Nayana
> Cc: CQ Tang
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 13
> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 2 +
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 4 +
> drivers/gpu/drm/i915/i915_drv.c | 102 +++---
> 4 files changed, 112 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index b6fcebeef02a..704cab807e0b 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -775,3 +775,16 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> kfree(ppgtt);
> return ERR_PTR(err);
> }
> +
> +void gen8_restore_ppgtt_mappings(struct i915_address_space *vm)
> +{
> + const unsigned int count = gen8_pd_top_count(vm);
> + int i;
> +
> + for (i = 1; i <= vm->top; i++)
> + fill_px(vm->scratch[i], vm->scratch[i - 1]->encode);
> +
> + fill_page_dma(px_base(i915_vm_to_ppgtt(vm)->pd),
> + vm->scratch[vm->top]->encode, count);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> index 76a08b9c1f5c..3fa4b95aaabd 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> @@ -6,8 +6,10 @@
> #ifndef __GEN8_PPGTT_H__
> #define __GEN8_PPGTT_H__
>
> +struct i915_address_space;
> struct intel_gt;
>
> +void gen8_restore_ppgtt_mappings(struct i915_address_space *vm);
> struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 34a02643bb75..9b3eacd12a7e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -9,6 +9,8 @@
> #include "intel_gtt.h"
> #include "gem/i915_gem_lmem.h"
> #include "gem/i915_gem_region.h"
> +#include "gem/i915_gem_context.h"
> +#include "gem/i915_gem_region.h"
> #include "gen6_ppgtt.h"
> #include "gen8_ppgtt.h"
>
> @@ -317,3 +319,5 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt
> *gt)
> ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
> ppgtt->vm.vma_ops.clear_pages = clear_pages;
> }
> +
> +
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e8c4931fc818..7115f4db5043 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -64,6 +64,7 @@
> #include "gem/i915_gem_context.h"
> #include "gem/i915_gem_ioctls.h"
> #include "gem/i915_gem_mman.h"
> +#include "gt/gen8_ppgtt.h"
> #include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_rc6.h"
> @@ -1136,13 +1137,13 @@ static int intel_dmem_evict_buffers(struct drm_device
> *dev, bool in_suspend)
>
> mutex_unlock(>objects.lock);
>
> - if (in_suspend)
> - i915_gem_object_unbind(obj, 0);
> -
> if (in_suspend) {
> obj->swapto = NULL;
> obj->evicted = false;
> obj->do_swapping = true;
> +
> + i915_gem_object_unbind(obj, 0);
> +
> ret =
> __i915_gem_object_put_pages(obj);
> obj->do_swapping = false;
> if (ret) {
> @@ -1176,6 +1177,43 @@ static int intel_dmem_evict_buffers(struct drm_device
> *dev, bool in_suspend)
> return ret;
> }
>
> +static int i915_gem_suspend_ppgtt_mappings(struct drm_i915_private *i915)
> +{
> + struct i915_gem_context *ctx, *cn;
> + int ret;
> +
> + spin_lock(>gem.contexts.lock);
> + list_for_each_entry_safe(ctx, cn, >gem.contexts.list, link) {
Wrong list. Bad starting point from GEM.
-Chris
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Re: [Intel-gfx] [RFC PATCH 144/162] drm/i915: Reset blitter context when unpark engine
Quoting Matthew Auld (2020-11-27 12:07:00) > From: Venkata Ramana Nayana > > We are only doing it now for kernel_context. We also need to do for the > copy engine blitter context. > > Signed-off-by: Venkata Ramana Nayana > --- > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c > b/drivers/gpu/drm/i915/gt/intel_engine_pm.c > index 1b2009b4dcb7..69c8ea70d1e8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c > @@ -66,6 +66,11 @@ static int __engine_unpark(struct intel_wakeref *wf) > ce->ops->reset(ce); > } Add a list of pinned volatile contexts to the engine that must be restored across resume. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 143/162] drm/i915: suspend/resume eviction
Quoting Matthew Auld (2020-11-27 12:06:59)
> +static int intel_dmem_evict_buffers(struct drm_device *dev, bool in_suspend)
> +{
> + struct drm_i915_private *i915 = to_i915(dev);
> + struct drm_i915_gem_object *obj;
> + struct intel_memory_region *mem;
> + int id, ret = 0;
> +
> + /*
> +* FIXME: Presently using memcpy,
> +* will replace with blitter once
> +* fix the issues.
> +*/
Why hasn't it been fixed then?
-Chris
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Re: [Intel-gfx] [RFC PATCH 141/162] drm/i915: Lmem eviction statistics by category
Quoting Matthew Auld (2020-11-27 12:06:57)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 82f431cc38cd..6f0ab363bdee 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1225,6 +1225,11 @@ struct drm_i915_private {
> atomic_long_t num_bytes_swapped_in;
> atomic_long_t time_swap_out_ms;
> atomic_long_t time_swap_in_ms;
> +
> + atomic_long_t num_bytes_swapped_out_memcpy;
> + atomic_long_t num_bytes_swapped_in_memcpy;
> + atomic_long_t time_swap_out_ms_memcpy;
> + atomic_long_t time_swap_in_ms_memcpy;
See earlier comments about why this will be rejected.
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Record the plane update times for debugging (rev7)
== Series Details == Series: drm/i915/display: Record the plane update times for debugging (rev7) URL : https://patchwork.freedesktop.org/series/84174/ State : warning == Summary == $ dim checkpatch origin/drm-tip 36f4f615f69a drm/i915/display: Record the plane update times for debugging -:73: WARNING:PREFER_SEQ_PUTS: Prefer seq_puts to seq_printf #73: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:901: + seq_printf(m, "\t1us (log) 1ms\n"); total: 0 errors, 1 warnings, 0 checks, 163 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 140/162] drm/i915: window_blt_copy is used for swapin and swapout
Quoting Matthew Auld (2020-11-27 12:06:56) > From: Ramalingam C > > window_blt_copy feature is used for swapin and swapout based on the i915 > module parameter called enable_eviction. A module parameter? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 137/162] drm/i915: blt copy between objs using pre-created vma windows
Quoting Matthew Auld (2020-11-27 12:06:53)
> +int i915_window_blt_copy(struct drm_i915_gem_object *dst,
> +struct drm_i915_gem_object *src)
> +{
> + struct drm_i915_private *i915 = to_i915(src->base.dev);
> + struct intel_context *ce = i915->gt.engine[BCS0]->blitter_context;
> + bool src_is_lmem = i915_gem_object_is_lmem(src);
> + bool dst_is_lmem = i915_gem_object_is_lmem(dst);
> + struct scatterlist *last_sgl;
> + struct i915_vma *src_vma, *dst_vma;
> + struct i915_request *rq;
> + u64 cur_win_sz, blt_copied, offset;
> + long timeout;
> + u32 size;
> + int err;
> +
> + src_vma = src_is_lmem ? i915->mm.lmem_window[0] :
> + i915->mm.smem_window[0];
> + dst_vma = dst_is_lmem ? i915->mm.lmem_window[1] :
> + i915->mm.smem_window[1];
> +
> + if (!src_vma || !dst_vma)
> + return -ENODEV;
> +
> + blt_copied = 0;
> +
> + err = i915_window_blt_copy_prepare_obj(src);
> + if (err)
> + return err;
> +
> + err = i915_window_blt_copy_prepare_obj(dst);
> + if (err) {
> + i915_gem_object_unpin_pages(src);
> + return err;
> + }
> +
> + mutex_lock(>mm.window_mutex);
> + src_vma->obj = src;
> + dst_vma->obj = dst;
> + do {
> + cur_win_sz = min_t(u64, BLT_WINDOW_SZ,
> + (src->base.size - blt_copied));
> + offset = blt_copied >> PAGE_SHIFT;
> + size = ALIGN(cur_win_sz, src->mm.region->min_page_size) >>
> + PAGE_SHIFT;
> + intel_partial_pages_for_sg_table(src, src_vma->pages, offset,
> +size, _sgl);
> +
> + /*
> +* Insert pages into vm, expects the pages to the full
> +* length of VMA. But we may have the pages of <= vma_size.
> +* Hence altering the vma size to match the total size of
> +* the pages attached.
> +*/
> + src_vma->size = size << PAGE_SHIFT;
> + i915_insert_vma_pages(src_vma, src_is_lmem);
> + sg_unmark_end(last_sgl);
> +
> + /*
> +* Source obj size could be smaller than the dst obj size,
> +* due to the varying min_page_size of the mem regions the
> +* obj belongs to. But when we insert the pages into vm,
> +* the total size of the pages supposed to be multiples of
> +* the min page size of that mem region.
> +*/
> + size = ALIGN(cur_win_sz, dst->mm.region->min_page_size) >>
> + PAGE_SHIFT;
> + intel_partial_pages_for_sg_table(dst, dst_vma->pages, offset,
> +size, _sgl);
> +
> + dst_vma->size = size << PAGE_SHIFT;
> + i915_insert_vma_pages(dst_vma, dst_is_lmem);
> + sg_unmark_end(last_sgl);
> +
> + rq = i915_request_create(ce);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + break;
> + }
> + if (rq->engine->emit_init_breadcrumb) {
> + err = rq->engine->emit_init_breadcrumb(rq);
> + if (unlikely(err)) {
> + DRM_ERROR("init_breadcrumb failed. %d\n",
> err);
> + break;
> + }
> + }
> + err = i915_window_blt_copy_batch_prepare(rq, src_vma, dst_vma,
> +cur_win_sz);
> + if (err) {
> + DRM_ERROR("Batch preparation failed. %d\n", err);
> + i915_request_set_error_once(rq, -EIO);
> + }
> +
> + i915_request_get(rq);
> + i915_request_add(rq);
> +
> + timeout = i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
Locked waits.
> + if (timeout < 0) {
> + DRM_ERROR("BLT Request is not completed. %ld\n",
> + timeout);
> + err = timeout;
> + i915_request_put(rq);
> + break;
> + }
> +
> + blt_copied += cur_win_sz;
> + err = 0;
> + i915_request_put(rq);
> + flush_work(>gt.engine[BCS0]->retire_work);
Papering (doubtful the paper is successful) over bugs by introducing a
whole load more.
This fails the basic premise that eviction must be pipelined. The PTE
are transient and can be written prior to the copy and kept within the
non-preemptible window of the blt. Thus allowing many evictions to
scheduled in
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers
== Series Details == Series: series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers URL : https://patchwork.freedesktop.org/series/84340/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9398 -> Patchwork_18997 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18997 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18997, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18997: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-tgl-y: [PASS][1] -> [FAIL][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html Warnings * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [DMESG-WARN][3] ([i915#1982]) -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html New tests - New tests have been introduced between CI_DRM_9398 and Patchwork_18997: ### New CI tests (1) ### * boot: - Statuses : 40 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18997 that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html * igt@i915_module_load@reload: - fi-tgl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#402] / [k.org#205379]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-u2/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-u2/igt@i915_module_l...@reload.html - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#1982] / [k.org#205379]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@i915_module_l...@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@module-reload: - fi-tgl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-u2/igt@i915_pm_...@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-u2/igt@i915_pm_...@module-reload.html * igt@kms_busy@basic@flip: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@kms_busy@ba...@flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@kms_busy@ba...@flip.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html * igt@kms_psr@primary_page_flip: - fi-tgl-u2: [PASS][17] -> [SKIP][18] ([i915#668]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-u2/igt@kms_psr@primary_page_flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-u2/igt@kms_psr@primary_page_flip.html * igt@vgem_basic@setversion: - fi-tgl-y: [PASS][19] -> [DMESG-WARN][20] ([i915#402]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@vgem_ba...@setversion.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@vgem_ba...@setversion.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][21] ([i915#402]) -> [PASS][22] +2 similar issues
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Declare gen9 has 64 mocs entries!
== Series Details == Series: drm/i915/gt: Declare gen9 has 64 mocs entries! URL : https://patchwork.freedesktop.org/series/84339/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9397_full -> Patchwork_18996_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18996_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18996_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18996_full: ### IGT changes ### Possible regressions * igt@i915_pm_dc@dc5-dpms: - shard-glk: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-glk8/igt@i915_pm...@dc5-dpms.html - shard-kbl: NOTRUN -> [FAIL][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-kbl7/igt@i915_pm...@dc5-dpms.html New tests - New tests have been introduced between CI_DRM_9397_full and Patchwork_18996_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18996_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][3] -> [SKIP][4] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/shard-tglb2/igt@gem_huc_c...@huc-copy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/shard-tglb1/igt@kms_flip@flip-vs-blocking-wf-vbl...@b-edp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-tglb7/igt@kms_flip@flip-vs-blocking-wf-vbl...@b-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#79]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-hdmi-a1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-hdmi-a1.html * igt@kms_flip@flip-vs-wf_vblank-interruptible@a-dp1: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/shard-apl2/igt@kms_flip@flip-vs-wf_vblank-interrupti...@a-dp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-apl6/igt@kms_flip@flip-vs-wf_vblank-interrupti...@a-dp1.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html * igt@kms_psr@psr2_primary_render: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/shard-iclb2/igt@kms_psr@psr2_primary_render.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-iclb1/igt@kms_psr@psr2_primary_render.html * igt@perf_pmu@module-unload: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982] / [i915#262]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/shard-tglb1/igt@perf_...@module-unload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-tglb7/igt@perf_...@module-unload.html Possible fixes * igt@gem_ctx_persistence@engines-hostile@vcs0: - shard-iclb: [FAIL][17] -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/shard-iclb1/igt@gem_ctx_persistence@engines-host...@vcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-iclb8/igt@gem_ctx_persistence@engines-host...@vcs0.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-hsw: [WARN][19] ([i915#1519]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/shard-hsw1/igt@i915_pm_rc6_reside...@rc6-fence.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/shard-hsw5/igt@i915_pm_rc6_reside...@rc6-fence.html * igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge: - shard-apl:
Re: [Intel-gfx] [RFC PATCH 134/162] drm/i915/dg1: Measure swap in/out timing stats
Quoting Matthew Auld (2020-11-27 12:06:50)
> From: Sudeep Dutt
>
> Signed-off-by: Sudeep Dutt
> ---
> drivers/gpu/drm/i915/gem/i915_gem_region.c | 16 ++--
> drivers/gpu/drm/i915/i915_debugfs.c| 3 +++
> drivers/gpu/drm/i915/i915_drv.h| 2 ++
> 3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
> b/drivers/gpu/drm/i915/gem/i915_gem_region.c
> index ed108dbcb34e..4fab9f6b4bee 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
> @@ -15,6 +15,7 @@ i915_gem_object_swapout_pages(struct drm_i915_gem_object
> *obj,
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> struct drm_i915_gem_object *dst, *src;
> + unsigned long start, diff, msec;
> int err;
>
> GEM_BUG_ON(obj->swapto);
> @@ -24,6 +25,7 @@ i915_gem_object_swapout_pages(struct drm_i915_gem_object
> *obj,
> GEM_BUG_ON(!i915->params.enable_eviction);
>
> assert_object_held(obj);
> + start = jiffies;
>
> /* create a shadow object on smem region */
> dst = i915_gem_object_create_shmem(i915, obj->base.size);
> @@ -64,8 +66,12 @@ i915_gem_object_swapout_pages(struct drm_i915_gem_object
> *obj,
> else
> i915_gem_object_put(dst);
>
> - if (!err)
> + if (!err) {
> + diff = jiffies - start;
> + msec = diff * 1000 / HZ;
> + atomic_long_add(msec, >time_swap_out_ms);
> atomic_long_add(sizes, >num_bytes_swapped_out);
> + }
This can be done using a kprobe, and with prettier statistics as builtin
functionality.
-Chris
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Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
On Fri, 2020-11-27 at 12:50 +0200, Gwan-gyeong Mun wrote:
> From: José Roberto de Souza
>
> The calculation the offsets of the main surface will be needed by PSR2
> selective fetch code so here splitting and exporting it.
> No functional changes were done here.
>
> v3: Rebased
>
> Cc: Gwan-gyeong Mun
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> Reviewed-by: Gwan-gyeong Mun
> Tested-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 62 +---
> drivers/gpu/drm/i915/display/intel_display.h | 2 +
> 2 files changed, 42 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 595183f7b60f..da24f654a2f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3817,22 +3817,21 @@ static int intel_plane_max_height(struct intel_plane
> *plane,
> return INT_MAX;
> }
>
>
>
>
>
>
>
>
> -static int skl_check_main_surface(struct intel_plane_state *plane_state)
> +int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
> + int *x, int *y, u32 *offset)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> - unsigned int rotation = plane_state->hw.rotation;
> - int x = plane_state->uapi.src.x1 >> 16;
> - int y = plane_state->uapi.src.y1 >> 16;
> - int w = drm_rect_width(_state->uapi.src) >> 16;
> - int h = drm_rect_height(_state->uapi.src) >> 16;
> - int min_width = intel_plane_min_width(plane, fb, 0, rotation);
> - int max_width = intel_plane_max_width(plane, fb, 0, rotation);
> - int max_height = intel_plane_max_height(plane, fb, 0, rotation);
> - int aux_plane = intel_main_to_aux_plane(fb, 0);
> - u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> - u32 alignment, offset;
> + const unsigned int rotation = plane_state->hw.rotation;
> + const int min_width = intel_plane_min_width(plane, fb, 0, rotation);
> + const int max_width = intel_plane_max_width(plane, fb, 0, rotation);
> + const int max_height = intel_plane_max_height(plane, fb, 0, rotation);
> + const int aux_plane = intel_main_to_aux_plane(fb, 0);
> + const u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> + const u32 alignment = intel_surf_alignment(fb, 0);
> + const int w = drm_rect_width(_state->uapi.src) >> 16;
> + const int h = drm_rect_height(_state->uapi.src) >> 16;
>
>
>
>
>
>
>
>
> if (w > max_width || w < min_width || h > max_height) {
This block should be kept in skl_check_main_surface(), also some variables
above.
We don't need to run this checks again for PSR code.
> drm_dbg_kms(_priv->drm,
> @@ -3841,9 +3840,8 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
> return -EINVAL;
> }
>
>
>
>
> - intel_add_fb_offsets(, , plane_state, 0);
> - offset = intel_plane_compute_aligned_offset(, , plane_state, 0);
> - alignment = intel_surf_alignment(fb, 0);
> + intel_add_fb_offsets(x, y, plane_state, 0);
> + *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
> if (drm_WARN_ON(_priv->drm, alignment && !is_power_of_2(alignment)))
> return -EINVAL;
>
>
>
>
> @@ -3852,9 +3850,10 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
> * main surface offset, and it must be non-negative. Make
> * sure that is what we will get.
> */
> - if (aux_plane && offset > aux_offset)
> - offset = intel_plane_adjust_aligned_offset(, , plane_state,
> 0,
> -offset, aux_offset &
> ~(alignment - 1));
> + if (aux_plane && *offset > aux_offset)
> + *offset = intel_plane_adjust_aligned_offset(x, y, plane_state,
> 0,
> + *offset,
> + aux_offset &
> ~(alignment - 1));
>
>
>
>
> /*
> * When using an X-tiled surface, the plane blows up
> @@ -3865,18 +3864,37 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
> if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
> int cpp = fb->format->cpp[0];
>
>
>
>
> - while ((x + w) * cpp > plane_state->color_plane[0].stride) {
> - if (offset == 0) {
> + while ((*x + w) * cpp > plane_state->color_plane[0].stride) {
> + if (*offset == 0) {
> drm_dbg_kms(_priv->drm,
> "Unable to find suitable display
>
Re: [Intel-gfx] [RFC PATCH 133/162] drm/i915/dg1: Track swap in/out stats via debugfs
Quoting Matthew Auld (2020-11-27 12:06:49)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1366b53ac8c9..7b1e95d494e6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1214,6 +1214,9 @@ struct drm_i915_private {
> * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your
> patch
> * will be rejected. Instead look for a better place.
> */
> +
> + atomic_long_t num_bytes_swapped_out;
> + atomic_long_t num_bytes_swapped_in;
Enough said. Don't mindlessly add fields.
-Chris
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Re: [Intel-gfx] [RFC PATCH 128/162] drm/i915/dg1: intel_memory_region_evict() changes for eviction
Quoting Matthew Auld (2020-11-27 12:06:44) > From: CQ Tang > > Function i915_gem_shrink_memory_region() is changed to > intel_memory_region_evict() and moved from i915_gem_shrinker.c > to intel_memory_region.c, this function is used to handle local > memory swapping, in addition to evict purgeable objects only. We really do not want to conflate the system shrinker with eviction. Reservation based eviction looks nothing like the shrinker. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 126/162] drm/i915/gem: Update shmem available memory
Quoting Matthew Auld (2020-11-27 12:06:42) > From: Bommu Krishnaiah > > Update shmem available memory in “intel_memory_region” Was avail ever set? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v12 08/15] drm/i915/display: Enable colorspace programming for LSPCON devices
> -Original Message- > From: Ville Syrjälä > Sent: Friday, November 27, 2020 7:15 PM > To: Shankar, Uma > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [v12 08/15] drm/i915/display: Enable colorspace programming for > LSPCON devices > > On Fri, Nov 27, 2020 at 02:33:07AM +0530, Uma Shankar wrote: > > Enable HDMI Colorspace for LSPCON based devices. Sending Colorimetry > > data for HDR using AVI infoframe. LSPCON firmware expects this and > > though SOC drives DP, for HDMI panel AVI infoframe is sent to the > > LSPCON device which transfers the same to HDMI sink. > > > > v2: Dropped state managed in drm core as per Jani Nikula's suggestion. > > > > v3: Aligned colorimetry handling for lspcon as per > > compute_avi_infoframes, as suggested by Ville. > > > > v4: Finally fixed this with Ville's help, re-phrased the commit header > > and description. > > Still missing the "expose the hdmi variant of the prop on lspcon" > part. I didn't include that in my patch since we didn't use > drm_hdmi_avi_infoframe_colorspace() yes on lspcon. Although maybe I should > have just done that change anyway since we were already registering the prop > anyway even if we didn't actually put the data into the infoframe. Yeah just sent the fix for that Ville. We had to create the properties early so moved the checks to intel_dp_add_properties. Just see if the new version looks ok Regards, Uma Shankar > > > > Credits-to: Ville Syrjälä > > Signed-off-by: Uma Shankar > > --- > > drivers/gpu/drm/i915/display/intel_lspcon.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > index 0a4c05d67108..cb768a1ae4c9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > @@ -523,6 +523,9 @@ void lspcon_set_infoframes(struct intel_encoder > *encoder, > > else > > frame.avi.colorspace = HDMI_COLORSPACE_RGB; > > > > + /* Set the Colorspace as per the HDMI spec */ > > + drm_hdmi_avi_infoframe_colorspace(, conn_state); > > + > > /* nonsense combination */ > > drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && > > crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); > > -- > > 2.26.2 > > -- > Ville Syrjälä > Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 125/162] drm/i915/lmem: Limit block size to 4G
Quoting Matthew Auld (2020-11-27 12:06:41) > From: Venkata Sandeep Dhanalakota > > when allocating pages to lmem object of size 4G or greater > we allocate memory blocks from buddy system. Any lmem object is from the buddy system. > In this scenario > buddy sytem can allocate blocks that can have size >= 4G and > these blocks require >32b to represent block size with these > blocks we run into an issue with sg list construction because > sg->length field is only 32b wide. Just say the when using scatterlist, the maximum segment size is 4G. In fact, we can ask sg what the backend maximum is, and use that as our max order. The only question is whether this merits a flag, or we just assume that the buddy allocator is only used for objects and so always presented via sg? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 124/162] drm/i915/lmem: allocate HWSP in lmem
Quoting Matthew Auld (2020-11-27 12:06:40) > From: Michel Thierry Rationale goes here. Is this wise? HWSP is very frequently read by the CPU, and expected to be cached on the CPU. What do the performance profiles indicate? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v13 08/15] drm/i915/display: Enable colorspace programming for LSPCON devices
Enable HDMI Colorspace for LSPCON based devices. Sending Colorimetry
data for HDR using AVI infoframe. LSPCON firmware expects this and though
SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
which transfers the same to HDMI sink.
v2: Dropped state managed in drm core as per Jani Nikula's suggestion.
v3: Aligned colorimetry handling for lspcon as per compute_avi_infoframes,
as suggested by Ville.
v4: Finally fixed this with Ville's help, re-phrased the commit header
and description.
v5: Register HDMI colorspace for lspcon and move this to
intel_dp_add_properties as we can't create property at late_register.
Credits-to: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++---
drivers/gpu/drm/i915/display/intel_lspcon.c | 3 +++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f066031af162..21a0ca6ae2a6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7193,10 +7193,13 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
struct drm_connector *connect
else if (INTEL_GEN(dev_priv) >= 5)
drm_connector_attach_max_bpc_property(connector, 6, 12);
- intel_attach_dp_colorspace_property(connector);
-
- if (intel_bios_is_lspcon_present(dev_priv, port))
+ /* Register HDMI colorspace for case of lspcon */
+ if (intel_bios_is_lspcon_present(dev_priv, port)) {
drm_connector_attach_content_type_property(connector);
+ intel_attach_hdmi_colorspace_property(connector);
+ } else {
+ intel_attach_dp_colorspace_property(connector);
+ }
if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
drm_object_attach_property(>base,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 0a4c05d67108..cb768a1ae4c9 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -523,6 +523,9 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
else
frame.avi.colorspace = HDMI_COLORSPACE_RGB;
+ /* Set the Colorspace as per the HDMI spec */
+ drm_hdmi_avi_infoframe_colorspace(, conn_state);
+
/* nonsense combination */
drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
--
2.26.2
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[Intel-gfx] [v13 06/15] drm/i915/display: Attach content type property for LSPCON
Content type is supported on HDMI sink devices. Attached the
property for the same for LSPCON based devices.
v2: Added the content type programming when we are attaching
the property to connector, as suggested by Ville.
v3: Need to attach content type on intel_dp_add_properties
as creating of new properties is not possible at late_register.
Signed-off-by: Uma Shankar
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5aaa06d73609..69de163be776 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7195,6 +7195,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct
drm_connector *connect
intel_attach_colorspace_property(connector);
+ if (intel_bios_is_lspcon_present(dev_priv, port))
+ drm_connector_attach_content_type_property(connector);
+
if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
drm_object_attach_property(>base,
connector->dev->mode_config.hdr_output_metadata_property,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 9552dfc55e20..0a4c05d67108 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -539,6 +539,8 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
frame.avi.ycc_quantization_range =
HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
}
+ drm_hdmi_avi_infoframe_content_type(, conn_state);
+
ret = hdmi_infoframe_pack(, buf, sizeof(buf));
if (ret < 0) {
DRM_ERROR("Failed to pack AVI IF\n");
--
2.26.2
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Re: [Intel-gfx] [RFC PATCH 118/162] drm/i915/dg1: Reserve first 1MB of local memory
Quoting Matthew Auld (2020-11-27 12:06:34)
> From: Imre Deak
>
> On DG1 A0/B0 steppings the first 1MB of local memory must be reserved.
> One reason for this is that the 0xA-0xB range is not accessible
> by the display, probably since this region is redirected to another
> memory location for legacy VGA compatibility.
>
> BSpec: 50586
> Testcase: igt/kms_big_fb/linear-64bpp-rotate-0
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_region_lmem.c | 52
> 1 file changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
> b/drivers/gpu/drm/i915/intel_region_lmem.c
> index 939cf0d195a5..eafef7034680 100644
> --- a/drivers/gpu/drm/i915/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/intel_region_lmem.c
> @@ -137,6 +137,48 @@ intel_setup_fake_lmem(struct drm_i915_private *i915)
> return mem;
> }
>
> +static void get_legacy_lowmem_region(struct intel_uncore *uncore,
> +u64 *start, u32 *size)
> +{
> + *start = 0;
> + *size = 0;
> +
> + if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
> + return;
> +
> + *size = SZ_1M;
> +
> + DRM_DEBUG_DRIVER("LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n",
> +*start, *start + *size);
> +}
> +
> +static int reserve_lowmem_region(struct intel_uncore *uncore,
> +struct intel_memory_region *mem)
> +{
> + u64 reserve_start;
> + u64 reserve_end;
> + u64 region_start;
> + u32 region_size;
> + int ret;
> +
> + get_legacy_lowmem_region(uncore, _start, _size);
> + reserve_start = region_start;
> + reserve_end = region_start + region_size;
> +
> + if (!reserve_end)
> + return 0;
> +
> + DRM_INFO("LMEM: reserving low-memory region [0x%llx-0x%llx]\n",
> +reserve_start, reserve_end);
> + ret = i915_buddy_alloc_range(>mm, >reserved,
> +reserve_start,
> +reserve_end - reserve_start);
Isn't this now relative to the stolen offset? Should this be reserved,
or excluded like stolen?
-Chris
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers
== Series Details == Series: series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers URL : https://patchwork.freedesktop.org/series/84340/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/display/psr: Calculate selective
fetch plane registers
URL : https://patchwork.freedesktop.org/series/84340/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0519f1c556bc drm/i915/display/psr: Calculate selective fetch plane registers
a394d94d01f2 drm/i915/display/psr: Calculate Trancoder's SU rect and plane's SF
rect
-:42: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#42: FILE: drivers/gpu/drm/i915/display/intel_display.h:468:
+#define for_each_oldnew_intel_plane_in_state_reverse(__state, plane,
old_plane_state, new_plane_state, __i) \
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible
side-effects?
#42: FILE: drivers/gpu/drm/i915/display/intel_display.h:468:
+#define for_each_oldnew_intel_plane_in_state_reverse(__state, plane,
old_plane_state, new_plane_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_total_plane - 1; \
+(__i) >= 0 && \
+((plane) =
to_intel_plane((__state)->base.planes[__i].ptr), \
+ (old_plane_state) =
to_intel_plane_state((__state)->base.planes[__i].old_state), \
+ (new_plane_state) =
to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
+(__i)--) \
+ for_each_if(plane)
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'plane' - possible
side-effects?
#42: FILE: drivers/gpu/drm/i915/display/intel_display.h:468:
+#define for_each_oldnew_intel_plane_in_state_reverse(__state, plane,
old_plane_state, new_plane_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_total_plane - 1; \
+(__i) >= 0 && \
+((plane) =
to_intel_plane((__state)->base.planes[__i].ptr), \
+ (old_plane_state) =
to_intel_plane_state((__state)->base.planes[__i].old_state), \
+ (new_plane_state) =
to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
+(__i)--) \
+ for_each_if(plane)
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/display/intel_display.h:468:
+#define for_each_oldnew_intel_plane_in_state_reverse(__state, plane,
old_plane_state, new_plane_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_total_plane - 1; \
+(__i) >= 0 && \
+((plane) =
to_intel_plane((__state)->base.planes[__i].ptr), \
+ (old_plane_state) =
to_intel_plane_state((__state)->base.planes[__i].old_state), \
+ (new_plane_state) =
to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
+(__i)--) \
+ for_each_if(plane)
-:46: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/intel_display.h:472:
+ (old_plane_state) =
to_intel_plane_state((__state)->base.planes[__i].old_state), \
-:47: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#47: FILE: drivers/gpu/drm/i915/display/intel_display.h:473:
+ (new_plane_state) =
to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
-:92: CHECK:LINE_SPACING: Please don't use multiple blank lines
#92: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1277:
+
+
-:261: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#261: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1418:
+new_plane_state, i) {
+
total: 0 errors, 3 warnings, 5 checks, 292 lines checked
6f2d0e56e996 drm/i915/display: Split and export main surface calculation from
skl_check_main_surface()
4286e9f831a3 drm/i915/display/psr: Program Plane's calculated offset to Plane
SF register
968a799d4c11 HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch
for testing
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Re: [Intel-gfx] [PATCH 07/15] drm/i915: Remove references to struct drm_device.pdev
Hi
Am 27.11.20 um 14:20 schrieb Joonas Lahtinen:
Quoting Thomas Zimmermann (2020-11-24 13:38:16)
Using struct drm_device.pdev is deprecated. Convert i915 to struct
drm_device.dev. No functional changes.
Signed-off-by: Thomas Zimmermann
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Any chance of sharing used a cocci script(s)? think this will
hit many in-flight series, so life would made easier :)
There's no script, sorry. I did this by hand.
Or is this done manually? I notice a few places hoist the pdev
variable and others repeat the call. Regardless, using the cocci
script as baseline would make review bit more comforting.
The gvt changes would go in through the gvt tree, and we also
probably need to split between drm-intel-next/drm-intel-gt-next,
too.
My hope is that patches can be merged through driver trees and do not
create too many conflicts there. After the dust has settled, the final
patch would go through drm-misc. If any uses of pdev were added
meanwhile, I'd fix them through drm-misc as well.
Best regards
Thomas
Jani or Rodrigo, any thoughts?
Regards, Joonas
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_cdclk.c| 14 ++---
drivers/gpu/drm/i915/display/intel_csr.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c| 2 +-
drivers/gpu/drm/i915/display/intel_gmbus.c| 2 +-
.../gpu/drm/i915/display/intel_lpe_audio.c| 5 +++--
drivers/gpu/drm/i915/display/intel_opregion.c | 6 +++---
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_panel.c| 4 ++--
drivers/gpu/drm/i915/display/intel_quirks.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
drivers/gpu/drm/i915/display/intel_vga.c | 8
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +++---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 10 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_reset.c | 6 +++---
drivers/gpu/drm/i915/gvt/cfg_space.c | 5 +++--
drivers/gpu/drm/i915/gvt/firmware.c | 10 +-
drivers/gpu/drm/i915/gvt/gtt.c| 12 +--
drivers/gpu/drm/i915/gvt/gvt.c| 6 +++---
drivers/gpu/drm/i915/gvt/kvmgt.c | 4 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 20 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_getparam.c | 5 +++--
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
drivers/gpu/drm/i915/i915_pmu.c | 5 +++--
drivers/gpu/drm/i915/i915_suspend.c | 4 ++--
drivers/gpu/drm/i915/i915_switcheroo.c| 4 ++--
drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_region_lmem.c | 8
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 -
drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 +-
42 files changed, 99 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4cc949b228f2..8879676372a3 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2088,7 +2088,7 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t size)
static struct vbt_header *oprom_get_vbt(struct drm_i915_private *dev_priv)
{
- struct pci_dev *pdev = dev_priv->drm.pdev;
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
void __iomem *p = NULL, *oprom;
struct vbt_header *vbt;
u16 vbt_size;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c449d28d0560..a6e13208dc50 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -96,7 +96,7 @@ static void fixed_450mhz_get_cdclk(struct drm_i915_private
*dev_priv,
static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- struct pci_dev *pdev = dev_priv->drm.pdev;
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
u16 hpllcc = 0;
/*
@@ -138,7 +138,7 @@ static void i85x_get_cdclk(struct drm_i915_private
*dev_priv,
static void i915gm_get_cdclk(struct
Re: [Intel-gfx] [v12 08/15] drm/i915/display: Enable colorspace programming for LSPCON devices
On Fri, Nov 27, 2020 at 02:33:07AM +0530, Uma Shankar wrote: > Enable HDMI Colorspace for LSPCON based devices. Sending Colorimetry > data for HDR using AVI infoframe. LSPCON firmware expects this and though > SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device > which transfers the same to HDMI sink. > > v2: Dropped state managed in drm core as per Jani Nikula's suggestion. > > v3: Aligned colorimetry handling for lspcon as per compute_avi_infoframes, > as suggested by Ville. > > v4: Finally fixed this with Ville's help, re-phrased the commit header > and description. Still missing the "expose the hdmi variant of the prop on lspcon" part. I didn't include that in my patch since we didn't use drm_hdmi_avi_infoframe_colorspace() yes on lspcon. Although maybe I should have just done that change anyway since we were already registering the prop anyway even if we didn't actually put the data into the infoframe. > > Credits-to: Ville Syrjälä > Signed-off-by: Uma Shankar > --- > drivers/gpu/drm/i915/display/intel_lspcon.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > b/drivers/gpu/drm/i915/display/intel_lspcon.c > index 0a4c05d67108..cb768a1ae4c9 100644 > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > @@ -523,6 +523,9 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, > else > frame.avi.colorspace = HDMI_COLORSPACE_RGB; > > + /* Set the Colorspace as per the HDMI spec */ > + drm_hdmi_avi_infoframe_colorspace(, conn_state); > + > /* nonsense combination */ > drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && > crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); > -- > 2.26.2 -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 103/162] drm/i915: allocate context from LMEM
Quoting Matthew Auld (2020-11-27 12:06:19)
> Based on a patch from Michel Thierry.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 31 ++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 582a9044727e..c640b90711fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -108,6 +108,8 @@
> */
> #include
>
> +#include "gem/i915_gem_lmem.h"
> +
> #include "i915_drv.h"
> #include "i915_perf.h"
> #include "i915_trace.h"
> @@ -4660,6 +4662,21 @@ static struct intel_timeline *pinned_timeline(struct
> intel_context *ce)
> page_unmask_bits(tl));
> }
>
> +static int context_clear_lmem(struct drm_i915_gem_object *ctx_obj)
> +{
> + void *vaddr;
> +
> + vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WC);
> + if (IS_ERR(vaddr))
> + return PTR_ERR(vaddr);
> +
> + memset64(vaddr, 0, ctx_obj->base.size / sizeof(u64));
> +
> + i915_gem_object_unpin_map(ctx_obj);
What? We copy over the entire object with the default state.
-Chris
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Re: [Intel-gfx] [RFC PATCH 101/162] drm/i915/gtt/dg1: add PTE_LM plumbing for PPGTT
Quoting Matthew Auld (2020-11-27 12:06:17)
> For the PTEs we get an LM bit, to signal whether the page resides in
> SMEM or LMEM.
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Niranjana Vishwanathapura
> Signed-off-by: Venkata Sandeep Dhanalakota
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 35 ++-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 4 +++
> 3 files changed, 36 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index e2f1dfc48d43..b6fcebeef02a 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -5,6 +5,7 @@
>
> #include
>
> +#include "gem/i915_gem_lmem.h"
> #include "gen8_ppgtt.h"
> #include "i915_scatterlist.h"
> #include "i915_trace.h"
> @@ -50,6 +51,21 @@ static u64 gen8_pte_encode(dma_addr_t addr,
> return pte;
> }
>
> +static u64 gen12_pte_encode(dma_addr_t addr,
> + enum i915_cache_level level,
> + u32 flags)
> +{
> + gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
> +
> + if (unlikely(flags & PTE_READ_ONLY))
> + pte &= ~_PAGE_RW;
> +
> + if (flags & PTE_LM)
> + pte |= GEN12_PPGTT_PTE_LM;
> +
> + return pte;
> +}
> +
> static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
> {
> struct drm_i915_private *i915 = ppgtt->vm.i915;
> @@ -365,7 +381,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
> u32 flags)
> {
> struct i915_page_directory *pd;
> - const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
> + const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level,
> flags);
We don't need the vfunc, since that flag will not be sent for gen8.
That bit test will be cheaper than the retpoline.
-Chris
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Re: [Intel-gfx] [RFC PATCH 098/162] drm/i915/gtt: map the PD up front
Quoting Matthew Auld (2020-11-27 12:06:14) > We need to general our accessor for the page directories and tables from > using the simple kmap_atomic to support local memory, and this setup > must be done on acquisition of the backing storage prior to entering > fence execution contexts. Here we replace the kmap with the object > maping code that for simple single page shmemfs object will return a > plain kmap, that is then kept for the lifetime of the page directory. > > Signed-off-by: Matthew Auld > Signed-off-by: Chris Wilson We are going to really struggle with this on 32b :( -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 097/162] drm/i915: Distinction of memory regions
Quoting Matthew Auld (2020-11-27 12:06:13) > From: Zbigniew Kempczyński > > IGTs should be able to choose testing strategy depending on memory > regions and its sizes. Add region instance number to make this > easier and descriptive. > > Cc: Matthew Auld > Cc: Ramalingam C > Cc: Tvrtko Ursulin > Cc: Adam Miszczak > Signed-off-by: Zbigniew Kempczyński > --- > drivers/gpu/drm/i915/intel_memory_region.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_memory_region.c > b/drivers/gpu/drm/i915/intel_memory_region.c > index 1f26bc06ec20..cea44ddebe46 100644 > --- a/drivers/gpu/drm/i915/intel_memory_region.c > +++ b/drivers/gpu/drm/i915/intel_memory_region.c > @@ -329,6 +329,10 @@ int intel_memory_regions_hw_probe(struct > drm_i915_private *i915) > mem->instance = instance; > mem->gt = >gt; > > + if (HAS_LMEM(mem->i915) && type != INTEL_MEMORY_SYSTEM) > + intel_memory_region_set_name(mem, "%s%u", > +mem->name, > mem->instance); sprintf(mem->name, "%s", mem->name) is that even defined behaviour? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 093/162] drm/i915/lmem: allocate cmd ring in lmem
Quoting Matthew Auld (2020-11-27 12:06:09)
> From: Michel Thierry
>
> Signed-off-by: Michel Thierry
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Abdiel Janulgue
> ---
> drivers/gpu/drm/i915/gt/intel_ring.c | 15 +++
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c
> b/drivers/gpu/drm/i915/gt/intel_ring.c
> index d636c6ed88b7..aa75e644f3f2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring.c
> @@ -4,6 +4,7 @@
> * Copyright © 2019 Intel Corporation
> */
>
> +#include "gem/i915_gem_lmem.h"
> #include "gem/i915_gem_object.h"
> #include "i915_drv.h"
> #include "i915_vma.h"
> @@ -111,10 +112,16 @@ static struct i915_vma *create_ring_vma(struct
> i915_ggtt *ggtt, int size)
> struct i915_vma *vma;
>
> obj = ERR_PTR(-ENODEV);
> - if (i915_ggtt_has_aperture(ggtt))
> - obj = i915_gem_object_create_stolen(i915, size);
> - if (IS_ERR(obj))
> - obj = i915_gem_object_create_internal(i915, size);
> + if (HAS_LMEM(i915)) {
> + obj = i915_gem_object_create_lmem(i915, size,
> + I915_BO_ALLOC_CONTIGUOUS |
> + I915_BO_ALLOC_VOLATILE);
Just create, and keep trying when !lmem returns an error.
Why contiguous, it's vmapped anyway?
> + } else {
> + if (i915_ggtt_has_aperture(ggtt))
> + obj = i915_gem_object_create_stolen(i915, size);
> + if (IS_ERR(obj))
> + obj = i915_gem_object_create_internal(i915, size);
> + }
> if (IS_ERR(obj))
> return ERR_CAST(obj);
>
> --
> 2.26.2
>
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[Intel-gfx] [PULL] drm-intel-next-queued
Hi Dave & Daniel -
Last feature pull for v5.11.
drm-intel-next-queued-2020-11-27:
drm/i915 features for v5.11:
Highlights:
- Enable big joiner to join two pipes to one port to overcome pipe restrictions
(Manasi, Ville, Maarten)
Display:
- More DG1 enabling (Lucas, Aditya)
- Fixes to cases without display (Lucas, José, Jani)
- Initial PSR state improvements (José)
- JSL eDP vswing updates (Tejas)
- Handle EDID declared max 16 bpc (Ville)
- Display refactoring (Ville)
Other:
- GVT features
- Backmerge
BR,
Jani.
The following changes since commit e047c7be173caab95f3876ab30c03ebcf654c300:
Merge tag 'drm-intel-next-queued-2020-11-03' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next (2020-11-04 12:17:34
+1000)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel
tags/drm-intel-next-queued-2020-11-27
for you to fetch changes up to b3bf99daaee96a141536ce5c60a0d6dba6ec1d23:
drm/i915/display: Defer initial modeset until after GGTT is initialised
(2020-11-26 11:01:52 +)
drm/i915 features for v5.11:
Highlights:
- Enable big joiner to join two pipes to one port to overcome pipe restrictions
(Manasi, Ville, Maarten)
Display:
- More DG1 enabling (Lucas, Aditya)
- Fixes to cases without display (Lucas, José, Jani)
- Initial PSR state improvements (José)
- JSL eDP vswing updates (Tejas)
- Handle EDID declared max 16 bpc (Ville)
- Display refactoring (Ville)
Other:
- GVT features
- Backmerge
Aditya Swarup (1):
drm/i915/dg1: Enable ports
Anusha Srivatsa (1):
drm/i915/ehl: Remove invalid PCI ID
Bob Paauwe (1):
drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms
Chris Wilson (2):
drm/i915/display: Whitespace cleanups
drm/i915/display: Defer initial modeset until after GGTT is initialised
Colin Xu (3):
drm/i915/gvt: Save/restore HW status to support GVT suspend/resume
drm/i915: Add GVT resume routine to i915
drm/i915/gvt: Fix virtual display setup for BXT/APL
Deepak R Varma (1):
drm/i915/gvt: replace idr_init() by idr_init_base()
Imre Deak (1):
drm/i915/tgl: Fix typo during output setup
Jani Nikula (3):
Merge drm/drm-next into drm-intel-next-queued
drm/i915/display: return earlier from intel_modeset_init() without display
Merge tag 'gvt-next-2020-11-23' of https://github.com/intel/gvt-linux
into drm-intel-next-queued
José Roberto de Souza (4):
drm/i915/display: Use initial_fastset_check() to compute and apply the
initial PSR state
drm/i915/display: Do not reset display when there is none
drm/i915/display: Group DC9 mask set
drm/i915/display: Make get_allowed_dc_mask().max_dc set a chain of if and
elses
Julian Stecklina (1):
drm/i915/gvt: treat intel_gvt_mpt as const in gvt code
Lionel Landwerlin (1):
drm/i915/perf: workaround register corruption in OATAILPTR
Lucas De Marchi (6):
drm/i915/dg1: map/unmap pll clocks
drm/i915/display: add namespace to intel_prepare_reset
drm/i915/display: add namespace to intel_finish_reset
drm/i915: re-order if/else ladder for hpd_irq_setup
drm/i915: move display-related to the end of intel_irq_init()
drm/i915: Do not setup hpd without display
Maarten Lankhorst (5):
drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
drm/i915: Try to make bigjoiner work in atomic check
drm/i915: Add bigjoiner aware plane clipping checks
drm/i915: Add debugfs dumping for bigjoiner, v3.
Manasi Navare (9):
drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
drm/i915: Move encoder->get_config to a new function
drm/i915: Add a wrapper function around get_pipe_config
drm/i915: Pass intel_atomic_state instead of drm_atomic_state
drm/i915/dp: Add from_crtc_state to copy color blobs
drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
drm/i915: HW state readout for Bigjoiner case
drm/i915: Do not call hsw_set_frame_start_delay for dsi
Tejas Upadhyay (2):
drm/i915/ehl: Implement W/A 22010492432
drm/i915/edp/jsl: Update vswing table for HBR and HBR2
Ville Syrjälä (26):
drm/i915: Sort EHL/JSL PCI IDs
drm/i915: Include fb modifier in state dumps
drm/i915: Add plane .{min,max}_width() and .max_height() vfuncs
drm/i915: Move hw.active assignment into intel_crtc_get_pipe_config()
drm/i915: s/intel_mode_from_pipe_config/intel_mode_from_crtc_timings/
drm/i915: Introduce intel_crtc_readout_derived_state()
drm/i915: Pass intel_atomic_state around
drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+
wm code
Re: [Intel-gfx] [PULL] gvt-next
Quoting Zhenyu Wang (2020-11-24 05:13:59) > On 2020.11.23 11:32:38 +0200, Joonas Lahtinen wrote: > > Quoting Zhenyu Wang (2020-11-23 11:05:17) > > > > > > Hi, > > > > > > Here's gvt next pull for v5.11. Mostly it's for host suspend/resume > > > fix with vGPU active and with some other enhancement as details below. > > > Note that this includes some minor i915 driver change to add gvt hook > > > in suspend/resume function which has been sent and reviewed on > > > intel-gfx list. > > > > > > I just generated against drm-intel-next-queued-2020-11-03 which this > > > tree bases on now. Let me know if there's any issue in merge. > > > > Sometimes GVT changes are paired with changes related the i915 side > > to adjust the running virtual clients. The changes are more often > > related to GT side, but there's also been display related changes. > > > > Going forward, would we want to continue to apply gvt-next to > > drm-intel-next (-queued is planned to be deprecated) or > > should we use drm-intel-gt-next? > > > > Is there any clear criteria on patches for -next or -gt-next now? > Something might be only gvt specific, e.g we'll have some enhancement patches > for guest context parse, this might be considered as 'gt' part? I'm not sure. > But yes, I hope we just stick with one, currently thinking drm-intel-next. For anything self-contained in gvt directory only, we can make a choice. I think the patches that concern vgpu, have most often been around the GT related code (opposed to display and PM). That kind of makes me think we would get away with least amount of topic branches and backmerges in the future if we also merged gvt-next to drm-intel-gt-next. Thoughts? That'd just mean a shift in timeline to send gvt-next latest early in -rc4 week. Regards, Joonas > > Or should we always strictly apply the GVT changes to drm-intel-next, > > and then any related i915 changes to drm-intel-next or drm-intel-gt-next > > depending on which one they are related to? > > > > How about basically we just apply to drm-intel-next, but there might be gvt > specific pull required for -gt-next e.g ww-lock fixes? I think we can do that > way > now to see if there'll be any real issue popup. > > Thanks > > > > > > Thanks > > > -- > > > The following changes since commit > > > 139caf7ca2866cd0a45814ff938cb0c33920a266: > > > > > > drm/i915: Update DRIVER_DATE to 20201103 (2020-11-03 14:21:25 +0200) > > > > > > are available in the Git repository at: > > > > > > https://github.com/intel/gvt-linux tags/gvt-next-2020-11-23 > > > > > > for you to fetch changes up to 9a3a238b3de97b4210c6de66aa88b2d7021ac086: > > > > > > drm/i915/gvt: treat intel_gvt_mpt as const in gvt code (2020-11-23 > > > 17:14:20 +0800) > > > > > > > > > gvt-next-2020-11-23 > > > > > > - Fix host suspend/resume with vGPU (Colin) > > > - optimize idr init (Varma) > > > - Change intel_gvt_mpt as const (Julian) > > > - One comment error fix (Yan) > > > > > > > > > Colin Xu (3): > > > drm/i915/gvt: Save/restore HW status to support GVT suspend/resume > > > drm/i915: Add GVT resume routine to i915 > > > drm/i915/gvt: Fix virtual display setup for BXT/APL > > > > > > Deepak R Varma (1): > > > drm/i915/gvt: replace idr_init() by idr_init_base() > > > > > > Julian Stecklina (1): > > > drm/i915/gvt: treat intel_gvt_mpt as const in gvt code > > > > > > Yan Zhao (1): > > > drm/i915/gvt: correct a false comment of flag F_UNALIGN > > > > > > drivers/gpu/drm/i915/gvt/display.c | 179 > > > > > > drivers/gpu/drm/i915/gvt/gtt.c | 64 + > > > drivers/gpu/drm/i915/gvt/gtt.h | 4 + > > > drivers/gpu/drm/i915/gvt/gvt.c | 13 ++- > > > drivers/gpu/drm/i915/gvt/gvt.h | 7 +- > > > drivers/gpu/drm/i915/gvt/handlers.c | 44 - > > > drivers/gpu/drm/i915/gvt/kvmgt.c| 2 +- > > > drivers/gpu/drm/i915/gvt/mmio.c | 5 + > > > drivers/gpu/drm/i915/gvt/mmio.h | 4 + > > > drivers/gpu/drm/i915/gvt/mpt.h | 2 +- > > > drivers/gpu/drm/i915/gvt/vgpu.c | 2 +- > > > drivers/gpu/drm/i915/i915_drv.c | 2 + > > > drivers/gpu/drm/i915/intel_gvt.c| 15 +++ > > > drivers/gpu/drm/i915/intel_gvt.h| 5 + > > > 14 files changed, 338 insertions(+), 10 deletions(-) > > > > > > -- > > > > > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 > > ___ > > intel-gvt-dev mailing list > > intel-gvt-...@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev > > -- > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 092/162] drm/i915/uapi: introduce drm_i915_gem_create_ext
Quoting Matthew Auld (2020-11-27 12:06:08)
> Same old gem_create but with now with extensions support. This is needed
> to support various upcoming usecases. For now we use the extensions
> mechanism to support setting an immutable-priority-list of potential
> placements, at creation time.
>
> If we wish to set the placements/regions we can simply do:
>
> struct drm_i915_gem_object_param region_param = { … }; /* Unchanged */
> struct drm_i915_gem_create_ext_setparam setparam_region = {
> .base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
> .param = region_param,
> }
>
> struct drm_i915_gem_create_ext create_ext = {
> .size = 16 * PAGE_SIZE,
> .extensions = (uintptr_t)_region,
> };
> int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, _ext);
> if (err) ...
>
> If we use the normal gem_create or gem_create_ext without the
> extensions/placements then we still get the old behaviour with only
> placing the object in system memory.
>
> One important change here is the returned size will now be rounded up to
> the correct size, depending on the list of placements, where we might
> have minimum page-size restrictions on some platforms when dealing with
> device local-memory.
>
> Also, we still keep around the i915_gem_object_setparam ioctl, although
> that is now restricted by the placement list(i.e we are not allowed to
> add new placements), and longer term that will be going away wrt setting
> placements, since it was deemed that the kernel doesn't need to support
> a dynamic list of placements, which is now solidified by this uapi
> change.
>
> Testcase: igt/gem_create/create-ext-placement-sanity-check
> Testcase: igt/gem_create/create-ext-placement-each
> Testcase: igt/gem_create/create-ext-placement-all
> Signed-off-by: Matthew Auld
> Signed-off-by: CQ Tang
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gem/i915_gem_create.c| 398 ++
> drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +
> drivers/gpu/drm/i915/gem/i915_gem_region.c| 4 +
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 103 +
> drivers/gpu/drm/i915/intel_memory_region.c| 20 +
> drivers/gpu/drm/i915/intel_memory_region.h| 4 +
> include/uapi/drm/i915_drm.h | 60 +++
> 10 files changed, 500 insertions(+), 103 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_create.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index ec361d61230b..3955134feca7 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -134,6 +134,7 @@ gem-y += \
> gem/i915_gem_clflush.o \
> gem/i915_gem_client_blt.o \
> gem/i915_gem_context.o \
> + gem/i915_gem_create.o \
> gem/i915_gem_dmabuf.o \
> gem/i915_gem_domain.o \
> gem/i915_gem_execbuffer.o \
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> new file mode 100644
> index ..6f6dd4f1ce7e
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -0,0 +1,398 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#include "gem/i915_gem_ioctls.h"
> +#include "gem/i915_gem_lmem.h"
> +#include "gem/i915_gem_object_blt.h"
> +#include "gem/i915_gem_region.h"
> +
> +#include "i915_drv.h"
> +#include "i915_user_extensions.h"
> +
> +static u32 max_page_size(struct intel_memory_region **placements,
> +int n_placements)
> +{
> + u32 max_page_size = 0;
> + int i;
> +
> + for (i = 0; i < n_placements; ++i) {
> + max_page_size = max_t(u32, max_page_size,
> + placements[i]->min_page_size);
> + }
> +
> + GEM_BUG_ON(!max_page_size);
> + return max_page_size;
> +}
> +
> +static int
> +i915_gem_create(struct drm_file *file,
> + struct intel_memory_region **placements,
> + int n_placements,
> + u64 *size_p,
> + u32 *handle_p)
> +{
> + struct drm_i915_gem_object *obj;
> + u32 handle;
> + u64 size;
> + int ret;
> +
> + size = round_up(*size_p, max_page_size(placements, n_placements));
> + if (size == 0)
> + return -EINVAL;
> +
> + /* For most of the ABI (e.g. mmap) we think in system pages */
> + GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
> +
> + /* Allocate the new object */
> + obj = i915_gem_object_create_region(placements[0], size, 0);
> + if (IS_ERR(obj))
> + return PTR_ERR(obj);
> +
> + if (i915_gem_object_is_lmem(obj)) {
> + struct intel_gt *gt = obj->mm.region->gt;
> + struct intel_context *ce =
Re: [Intel-gfx] [PATCH 07/15] drm/i915: Remove references to struct drm_device.pdev
Quoting Thomas Zimmermann (2020-11-24 13:38:16)
> Using struct drm_device.pdev is deprecated. Convert i915 to struct
> drm_device.dev. No functional changes.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
Any chance of sharing used a cocci script(s)? think this will
hit many in-flight series, so life would made easier :)
Or is this done manually? I notice a few places hoist the pdev
variable and others repeat the call. Regardless, using the cocci
script as baseline would make review bit more comforting.
The gvt changes would go in through the gvt tree, and we also
probably need to split between drm-intel-next/drm-intel-gt-next,
too.
Jani or Rodrigo, any thoughts?
Regards, Joonas
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c| 14 ++---
> drivers/gpu/drm/i915/display/intel_csr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbdev.c| 2 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c| 2 +-
> .../gpu/drm/i915/display/intel_lpe_audio.c| 5 +++--
> drivers/gpu/drm/i915/display/intel_opregion.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
> drivers/gpu/drm/i915/display/intel_panel.c| 4 ++--
> drivers/gpu/drm/i915/display/intel_quirks.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
> drivers/gpu/drm/i915/display/intel_vga.c | 8
> drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +++---
> drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 10 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rc6.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_reset.c | 6 +++---
> drivers/gpu/drm/i915/gvt/cfg_space.c | 5 +++--
> drivers/gpu/drm/i915/gvt/firmware.c | 10 +-
> drivers/gpu/drm/i915/gvt/gtt.c| 12 +--
> drivers/gpu/drm/i915/gvt/gvt.c| 6 +++---
> drivers/gpu/drm/i915/gvt/kvmgt.c | 4 ++--
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.c | 20 +--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
> drivers/gpu/drm/i915/i915_getparam.c | 5 +++--
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 6 +++---
> drivers/gpu/drm/i915/i915_pmu.c | 5 +++--
> drivers/gpu/drm/i915/i915_suspend.c | 4 ++--
> drivers/gpu/drm/i915/i915_switcheroo.c| 4 ++--
> drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> drivers/gpu/drm/i915/intel_region_lmem.c | 8
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 -
> drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 +-
> 42 files changed, 99 insertions(+), 98 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..8879676372a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2088,7 +2088,7 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t
> size)
>
> static struct vbt_header *oprom_get_vbt(struct drm_i915_private *dev_priv)
> {
> - struct pci_dev *pdev = dev_priv->drm.pdev;
> + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> void __iomem *p = NULL, *oprom;
> struct vbt_header *vbt;
> u16 vbt_size;
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c449d28d0560..a6e13208dc50 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -96,7 +96,7 @@ static void fixed_450mhz_get_cdclk(struct drm_i915_private
> *dev_priv,
> static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
>struct intel_cdclk_config *cdclk_config)
> {
> - struct pci_dev *pdev = dev_priv->drm.pdev;
> + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> u16 hpllcc = 0;
>
> /*
> @@ -138,7 +138,7 @@ static void i85x_get_cdclk(struct drm_i915_private
> *dev_priv,
> static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config)
> {
> - struct pci_dev *pdev = dev_priv->drm.pdev;
> + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> u16 gcfgc = 0;
>
>
Re: [Intel-gfx] [drm/i915/gem] 59dd13ad31: phoronix-test-suite.jxrendermark.RadialGradientPaint.1024x1024.operations_per_second -54.0% regression
Quoting Xing Zhengjun (2020-11-27 01:51:41) > > > On 11/27/2020 5:34 AM, Chris Wilson wrote: > > Quoting Xing Zhengjun (2020-11-26 01:44:55) > >> > >> > >> On 11/25/2020 4:47 AM, Chris Wilson wrote: > >>> Quoting Oliver Sang (2020-11-19 07:20:18) > On Fri, Nov 13, 2020 at 04:27:13PM +0200, Joonas Lahtinen wrote: > > Hi, > > > > Could you add intel-gfx@lists.freedesktop.org into reports going > > forward. > > > > Quoting kernel test robot (2020-11-11 17:58:11) > >> > >> Greeting, > >> > >> FYI, we noticed a -54.0% regression of > >> phoronix-test-suite.jxrendermark.RadialGradientPaint.1024x1024.operations_per_second > >> due to commit: > > > > How many runs are there on the bad version to ensure the bisect is > > repeatable? > > test 4 times. > zxing@inn:/result/phoronix-test-suite/performance-true-Radial_Gradient_Paint-1024x1024-jxrendermark-1.2.4-ucode=0xd6-monitor=da39a3ee/lkp-cfl-d1/debian-x86_64-phoronix/x86_64-rhel-8.3/gcc-9/59dd13ad310793757e34afa489dd6fc8544fc3da$ > grep -r "operations_per_second" */stats.json > 0/stats.json: > "phoronix-test-suite.jxrendermark.RadialGradientPaint.1024x1024.operations_per_second": > 4133.487932, > 1/stats.json: > "phoronix-test-suite.jxrendermark.RadialGradientPaint.1024x1024.operations_per_second": > 4120.421503, > 2/stats.json: > "phoronix-test-suite.jxrendermark.RadialGradientPaint.1024x1024.operations_per_second": > 4188.414835, > 3/stats.json: > "phoronix-test-suite.jxrendermark.RadialGradientPaint.1024x1024.operations_per_second": > 4068.549514, > >>> > >>> a w/o revert (drm-tip) > >>> b w/ revert > >>> +mB+ > >>> | ..b > >>> | > >>> | ..b.aa > >>> | > >>> | a.a > >>> | > >>> | a.a > >>> | > >>> | b b a > >>> | > >>> | b b b b. a > >>> | > >>> | b bb bbb... > >>> | > >>> |b ab bbab.bb.bba b a aab > >>> a| > >>> | |__A__| > >>> | > >>> | |MA_| > >>> | > >>> +--+ > >>> NMin MaxMedian Avg > >>> Stddev > >>> a 120 3621.8761 7356.4442 4606.7895 4607.9132 > >>> 156.17693 > >>> b 120 2664.0563 6359.9686 4519.5036 4534.4463 > >>> 95.471121 > >>> > >>> The patch is not expected to have any impact on the machine you are > >>> testing on. > >>> -Chris > >>> > >> > >> What's your code base? > >> For my side: > >> 1) sync the code to the head of Linux mainline > >> 2) git reset --hard 59dd13ad31 > >> 3) git revert 59dd13ad3107 > >> We compare the test result of commit 59dd13ad3107 (step 2) and > >> 2052847b06f8 (step 3, revert 59dd13ad3107), the regression should > >> related with 59dd13ad3107. Each test case we run 5 times. > > > > a 59dd13ad31 > > b revert > > +mB+ > > |a > >| > > | aa > >| > > | .bba > >| > > | .bbaab > >| > > | .b . b b > >| > > |a b.. ..bb bb > >| > > | b a b.b.a bb > >| > > |aa b..aaa..b.b..bab b a > > .| > > | |__A__| > >| > > | |___A_| > >| > > +--+ > > NMin MaxMedian Avg > > Stddev > > a 120 3658.3435 6363.7812 4527.4406 4536.612 > > 86.095459 > > b 120 3928.9643 6375.829 4576.0482 4585.4224 > > 157.284 > > >
Re: [Intel-gfx] [PATCH 03/17] drivers/gpu: Convert to mem*_page()
+ intel-gfx mailing list
Quoting ira.we...@intel.com (2020-11-24 08:07:41)
> From: Ira Weiny
>
> The pattern of kmap/mem*/kunmap is repeated. Use the new mem*_page()
> calls instead.
>
> Cc: Patrik Jakobsson
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Signed-off-by: Ira Weiny
> ---
> drivers/gpu/drm/gma500/gma_display.c | 7 +++
> drivers/gpu/drm/gma500/mmu.c | 4 ++--
> drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 6 ++
> drivers/gpu/drm/i915/gt/intel_gtt.c | 9 ++---
> drivers/gpu/drm/i915/gt/shmem_utils.c | 8 +++-
Are you looking to merge all these from the same tree, or first merge
the first patch and then trickle the rest through their own trees?
Our last -next PR was already sent for i915, so I would queue this
only for 5.12.
In any case, if you could split the i915 changes to a separate patch
(we have multiple sub-trees in drm), those are:
Reviewed-by: Joonas Lahtinen
The gma500 changes also appear correct, so feel free to apply the
R-b for those, too.
Regards, Joonas
> 5 files changed, 12 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/gma_display.c
> b/drivers/gpu/drm/gma500/gma_display.c
> index 3df6d6e850f5..f81114594211 100644
> --- a/drivers/gpu/drm/gma500/gma_display.c
> +++ b/drivers/gpu/drm/gma500/gma_display.c
> @@ -9,6 +9,7 @@
>
> #include
> #include
> +#include
>
> #include
> #include
> @@ -334,7 +335,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
> struct gtt_range *gt;
> struct gtt_range *cursor_gt = gma_crtc->cursor_gt;
> struct drm_gem_object *obj;
> - void *tmp_dst, *tmp_src;
> + void *tmp_dst;
> int ret = 0, i, cursor_pages;
>
> /* If we didn't get a handle then turn the cursor off */
> @@ -400,9 +401,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
> /* Copy the cursor to cursor mem */
> tmp_dst = dev_priv->vram_addr + cursor_gt->offset;
> for (i = 0; i < cursor_pages; i++) {
> - tmp_src = kmap(gt->pages[i]);
> - memcpy(tmp_dst, tmp_src, PAGE_SIZE);
> - kunmap(gt->pages[i]);
> + memcpy_from_page(tmp_dst, gt->pages[i], 0, PAGE_SIZE);
> tmp_dst += PAGE_SIZE;
> }
>
> diff --git a/drivers/gpu/drm/gma500/mmu.c b/drivers/gpu/drm/gma500/mmu.c
> index 505044c9a673..8a0856c7f439 100644
> --- a/drivers/gpu/drm/gma500/mmu.c
> +++ b/drivers/gpu/drm/gma500/mmu.c
> @@ -5,6 +5,7 @@
> **/
>
> #include
> +#include
>
> #include "mmu.h"
> #include "psb_drv.h"
> @@ -204,8 +205,7 @@ struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver
> *driver,
>
> kunmap(pd->p);
>
> - clear_page(kmap(pd->dummy_page));
> - kunmap(pd->dummy_page);
> + memzero_page(pd->dummy_page, 0, PAGE_SIZE);
>
> pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
> if (!pd->tables)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> index 75e8b71c18b9..8a25e08edd18 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> @@ -558,7 +558,7 @@ i915_gem_object_create_shmem_from_data(struct
> drm_i915_private *dev_priv,
> do {
> unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
> struct page *page;
> - void *pgdata, *vaddr;
> + void *pgdata;
>
> err = pagecache_write_begin(file, file->f_mapping,
> offset, len, 0,
> @@ -566,9 +566,7 @@ i915_gem_object_create_shmem_from_data(struct
> drm_i915_private *dev_priv,
> if (err < 0)
> goto fail;
>
> - vaddr = kmap(page);
> - memcpy(vaddr, data, len);
> - kunmap(page);
> + memcpy_to_page(page, 0, data, len);
>
> err = pagecache_write_end(file, file->f_mapping,
> offset, len, len,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
> b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 3f1114b58b01..f3d7c601d362 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -153,13 +153,8 @@ static void poison_scratch_page(struct
> drm_i915_gem_object *scratch)
> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> val = POISON_FREE;
>
> - for_each_sgt_page(page, sgt, scratch->mm.pages) {
> - void *vaddr;
> -
> - vaddr = kmap(page);
> - memset(vaddr, val, PAGE_SIZE);
> - kunmap(page);
> - }
> + for_each_sgt_page(page, sgt, scratch->mm.pages)
> + memset_page(page, val, 0,
[Intel-gfx] [CI 2/2] drm/i915/gt: ce->inflight updates are now serialised
Since schedule-in and schedule-out are now both always under the tasklet
bitlock, we can reduce the individual atomic operations to simple
instructions and worry less.
This notably eliminates the race observed with intel_context_inflight in
__engine_unpark().
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2583
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 52 ++---
1 file changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 49a80f940e73..3a6a9539b54e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1358,11 +1358,11 @@ __execlists_schedule_in(struct i915_request *rq)
ce->lrc.ccid = ce->tag;
} else {
/* We don't need a strict matching tag, just different values */
- unsigned int tag = ffs(READ_ONCE(engine->context_tag));
+ unsigned int tag = __ffs(engine->context_tag);
- GEM_BUG_ON(tag == 0 || tag >= BITS_PER_LONG);
- clear_bit(tag - 1, >context_tag);
- ce->lrc.ccid = tag << (GEN11_SW_CTX_ID_SHIFT - 32);
+ GEM_BUG_ON(tag >= BITS_PER_LONG);
+ __clear_bit(tag, >context_tag);
+ ce->lrc.ccid = (1 + tag) << (GEN11_SW_CTX_ID_SHIFT - 32);
BUILD_BUG_ON(BITS_PER_LONG > GEN12_MAX_CONTEXT_HW_ID);
}
@@ -1375,6 +1375,8 @@ __execlists_schedule_in(struct i915_request *rq)
execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
intel_engine_context_in(engine);
+ CE_TRACE(ce, "schedule-in, ccid:%x\n", ce->lrc.ccid);
+
return engine;
}
@@ -1386,13 +1388,10 @@ static inline void execlists_schedule_in(struct
i915_request *rq, int idx)
GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine));
trace_i915_request_in(rq, idx);
- old = READ_ONCE(ce->inflight);
- do {
- if (!old) {
- WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq));
- break;
- }
- } while (!try_cmpxchg(>inflight, , ptr_inc(old)));
+ old = ce->inflight;
+ if (!old)
+ old = __execlists_schedule_in(rq);
+ WRITE_ONCE(ce->inflight, ptr_inc(old));
GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
}
@@ -1406,12 +1405,11 @@ static void kick_siblings(struct i915_request *rq,
struct intel_context *ce)
tasklet_hi_schedule(>base.execlists.tasklet);
}
-static inline void
-__execlists_schedule_out(struct i915_request *rq,
-struct intel_engine_cs * const engine,
-unsigned int ccid)
+static inline void __execlists_schedule_out(struct i915_request *rq)
{
struct intel_context * const ce = rq->context;
+ struct intel_engine_cs * const engine = rq->engine;
+ unsigned int ccid;
/*
* NB process_csb() is not under the engine->active.lock and hence
@@ -1419,6 +1417,8 @@ __execlists_schedule_out(struct i915_request *rq,
* refrain from doing non-trivial work here.
*/
+ CE_TRACE(ce, "schedule-out, ccid:%x\n", ce->lrc.ccid);
+
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
execlists_check_context(ce, engine, "after");
@@ -1430,12 +1430,13 @@ __execlists_schedule_out(struct i915_request *rq,
i915_request_completed(rq))
intel_engine_add_retire(engine, ce->timeline);
+ ccid = ce->lrc.ccid;
ccid >>= GEN11_SW_CTX_ID_SHIFT - 32;
ccid &= GEN12_MAX_CONTEXT_HW_ID;
if (ccid < BITS_PER_LONG) {
GEM_BUG_ON(ccid == 0);
GEM_BUG_ON(test_bit(ccid - 1, >context_tag));
- set_bit(ccid - 1, >context_tag);
+ __set_bit(ccid - 1, >context_tag);
}
intel_context_update_runtime(ce);
@@ -1456,26 +1457,23 @@ __execlists_schedule_out(struct i915_request *rq,
*/
if (ce->engine != engine)
kick_siblings(rq, ce);
-
- intel_context_put(ce);
}
static inline void
execlists_schedule_out(struct i915_request *rq)
{
struct intel_context * const ce = rq->context;
- struct intel_engine_cs *cur, *old;
- u32 ccid;
trace_i915_request_out(rq);
- ccid = rq->context->lrc.ccid;
- old = READ_ONCE(ce->inflight);
- do
- cur = ptr_unmask_bits(old, 2) ? ptr_dec(old) : NULL;
- while (!try_cmpxchg(>inflight, , cur));
- if (!cur)
- __execlists_schedule_out(rq, old, ccid);
+ GEM_BUG_ON(!ce->inflight);
+ ce->inflight = ptr_dec(ce->inflight);
+ if (!intel_context_inflight_count(ce)) {
+ GEM_BUG_ON(ce->inflight != rq->engine);
+ __execlists_schedule_out(rq);
+ WRITE_ONCE(ce->inflight,
[Intel-gfx] [CI 1/2] drm/i915/gt: Replace direct submit with direct call to tasklet
Rather than having special case code for opportunistically calling
process_csb() and performing a direct submit while holding the engine
spinlock for submitting the request, simply call the tasklet directly.
This allows us to retain the direct submission path, including the CS
draining to allow fast/immediate submissions, without requiring any
duplicated code paths, and most importantly greatly simplifying the
control flow by removing reentrancy. This will enable us to close a few
races in the virtual engines in the next few patches.
The trickiest part here is to ensure that paired operations (such as
schedule_in/schedule_out) remain under consistent locking domains,
e.g. when pulled outside of the engine->active.lock
v2: Use bh kicking, see commit 3c53776e29f8 ("Mark HI and TASKLET
softirq synchronous").
v3: Update engine-reset to be tasklet aware
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +++--
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 134 +++---
drivers/gpu/drm/i915/gt/intel_reset.c | 60 +---
drivers/gpu/drm/i915/gt/intel_reset.h | 2 +
drivers/gpu/drm/i915/gt/selftest_context.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 7 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 27 ++--
drivers/gpu/drm/i915/gt/selftest_reset.c | 8 +-
drivers/gpu/drm/i915/i915_request.c | 12 +-
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_scheduler.c | 4 -
drivers/gpu/drm/i915/selftests/i915_request.c | 6 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 3 +
15 files changed, 158 insertions(+), 148 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d4e988b2816a..2ed03b88ec12 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1002,32 +1002,39 @@ static unsigned long stop_timeout(const struct
intel_engine_cs *engine)
return READ_ONCE(engine->props.stop_timeout_ms);
}
-int intel_engine_stop_cs(struct intel_engine_cs *engine)
+static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
+ int fast_timeout_us,
+ int slow_timeout_ms)
{
struct intel_uncore *uncore = engine->uncore;
- const u32 base = engine->mmio_base;
- const i915_reg_t mode = RING_MI_MODE(base);
+ const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
int err;
+ intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
+ err = __intel_wait_for_register_fw(engine->uncore, mode,
+ MODE_IDLE, MODE_IDLE,
+ fast_timeout_us,
+ slow_timeout_ms,
+ NULL);
+
+ /* A final mmio read to let GPU writes be hopefully flushed to memory */
+ intel_uncore_posting_read_fw(uncore, mode);
+ return err;
+}
+
+int intel_engine_stop_cs(struct intel_engine_cs *engine)
+{
+ int err = 0;
+
if (INTEL_GEN(engine->i915) < 3)
return -ENODEV;
ENGINE_TRACE(engine, "\n");
-
- intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
-
- err = 0;
- if (__intel_wait_for_register_fw(uncore,
-mode, MODE_IDLE, MODE_IDLE,
-1000, stop_timeout(engine),
-NULL)) {
+ if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n");
err = -ETIMEDOUT;
}
- /* A final mmio read to let GPU writes be hopefully flushed to memory */
- intel_uncore_posting_read_fw(uncore, mode);
-
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 499b09cb4acf..99574378047f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -136,7 +136,7 @@ __queue_and_release_pm(struct i915_request *rq,
list_add_tail(>link, >active_list);
/* Hand the request over to HW and so engine_retire() */
- __i915_request_queue(rq, NULL);
+ __i915_request_queue_bh(rq);
/* Let new submissions commence (and maybe retire this timeline) */
__intel_wakeref_defer_park(>wakeref);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index ee6312601c56..e71eef157231 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Declare gen9 has 64 mocs entries!
== Series Details ==
Series: drm/i915/gt: Declare gen9 has 64 mocs entries!
URL : https://patchwork.freedesktop.org/series/84339/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9397 -> Patchwork_18996
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/index.html
New tests
-
New tests have been introduced between CI_DRM_9397 and Patchwork_18996:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18996 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0:
- fi-apl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#62]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_psr@cursor_plane_move:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-tgl-y/igt@kms_psr@cursor_plane_move.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-tgl-y/igt@kms_psr@cursor_plane_move.html
* igt@vgem_basic@debugfs:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-tgl-y/igt@vgem_ba...@debugfs.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-tgl-y/igt@vgem_ba...@debugfs.html
Possible fixes
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +2
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-icl-u2/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-icl-u2/igt@i915_module_l...@reload.html
- fi-tgl-u2: [DMESG-WARN][11] ([i915#1982] / [k.org#205379]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-tgl-u2/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-tgl-u2/igt@i915_module_l...@reload.html
* igt@i915_selftest@live@active:
- fi-icl-u2: [DMESG-FAIL][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-icl-u2/igt@i915_selftest@l...@active.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-icl-u2/igt@i915_selftest@l...@active.html
* igt@prime_vgem@basic-gtt:
- fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-tgl-y/igt@prime_v...@basic-gtt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-tgl-y/igt@prime_v...@basic-gtt.html
Warnings
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-y: [DMESG-WARN][17] ([i915#2411]) -> [DMESG-WARN][18]
([i915#1982] / [i915#2411])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html
* igt@runner@aborted:
- fi-kbl-8809g: [FAIL][19] ([i915#1569] / [i915#192] / [i915#193] /
[i915#194] / [i915#2295] / [i915#2722]) -> [FAIL][20] ([i915#1186] /
[i915#2426] / [i915#2722])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9397/fi-kbl-8809g/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18996/fi-kbl-8809g/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1186]: https://gitlab.freedesktop.org/drm/intel/issues/1186
[i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
[i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
[i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2411]:
[Intel-gfx] [RFC PATCH 162/162] drm/i915: drop fake lmem
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c| 15
drivers/gpu/drm/i915/i915_params.c | 5 --
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_memory_region.c | 11 +--
drivers/gpu/drm/i915/intel_region_lmem.c | 96 --
drivers/gpu/drm/i915/intel_region_lmem.h | 3 -
6 files changed, 1 insertion(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c41865d5bf1e..ee7272abc2b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -836,21 +836,6 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (!i915->params.nuclear_pageflip && match_info->gen < 5)
i915->drm.driver_features &= ~DRIVER_ATOMIC;
- /*
-* Check if we support fake LMEM -- for now we only unleash this for
-* the live selftests(test-and-exit).
-*/
-#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
- if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
- if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
- i915->params.fake_lmem_start) {
- mkwrite_device_info(i915)->memory_regions =
- REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
- GEM_BUG_ON(!HAS_LMEM(i915));
- }
- }
-#endif
-
ret = pci_enable_device(pdev);
if (ret)
goto out_fini;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 9fa58ed76614..819341f77488 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -192,11 +192,6 @@ i915_param_named(enable_gvt, bool, 0400,
"Enable support for Intel GVT-g graphics virtualization host
support(default:false)");
#endif
-#if IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)
-i915_param_named_unsafe(fake_lmem_start, ulong, 0400,
- "Fake LMEM start offset (default: 0)");
-#endif
-
i915_param_named_unsafe(enable_eviction, uint, 0600,
"Enable eviction which does not rely on DMA resv refactoring "
"0=disabled, 1=memcpy based only, 2=blt based only, "
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c835e592ee5f..ea6e99735ff2 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -70,7 +70,6 @@ struct drm_printer;
param(int, fastboot, -1, 0600) \
param(int, enable_dpcd_backlight, -1, 0600) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
- param(unsigned long, fake_lmem_start, 0, 0400) \
param(unsigned int, lmem_size, 0, 0400) \
param(unsigned int, enable_eviction, 3, 0600) \
/* leave bools at the end to not create holes */ \
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c
b/drivers/gpu/drm/i915/intel_memory_region.c
index 6b26b6cd5958..045efb9b01d9 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -447,16 +447,7 @@ int intel_memory_regions_hw_probe(struct drm_i915_private
*i915)
mem = i915_gem_stolen_setup(i915);
break;
case INTEL_MEMORY_LOCAL:
-#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
- if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
- if (INTEL_GEN(i915) >= 9 && i915_selftest.live
< 0 &&
- i915->params.fake_lmem_start)
- mem = intel_setup_fake_lmem(i915);
- }
-#endif
-
- if (IS_ERR(mem))
- mem = i915_gem_setup_lmem(i915);
+ mem = i915_gem_setup_lmem(i915);
break;
}
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index 1cdb6354b968..e3f5ca619318 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -9,64 +9,9 @@
#include "gem/i915_gem_region.h"
#include "intel_region_lmem.h"
-static int init_fake_lmem_bar(struct intel_memory_region *mem)
-{
- struct drm_i915_private *i915 = mem->i915;
- struct i915_ggtt *ggtt = >ggtt;
- unsigned long n;
- int ret;
-
- /* We want to 1:1 map the mappable aperture to our reserved region */
-
- mem->fake_mappable.start = 0;
- mem->fake_mappable.size = resource_size(>region);
- mem->fake_mappable.color = I915_COLOR_UNEVICTABLE;
-
- ret = drm_mm_reserve_node(>vm.mm, >fake_mappable);
- if (ret)
- return ret;
-
- mem->remap_addr = dma_map_resource(>drm.pdev->dev,
- mem->region.start,
-
[Intel-gfx] [RFC PATCH 159/162] drm/i915/dg1: Fix mapping type for default state object
From: Venkata Ramana Nayana Use I915_MAP_WC when default state object is allocated on LMEM. Signed-off-by: Venkata Ramana Nayana --- drivers/gpu/drm/i915/gt/shmem_utils.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c b/drivers/gpu/drm/i915/gt/shmem_utils.c index 041e2a50160d..1fbc070a4651 100644 --- a/drivers/gpu/drm/i915/gt/shmem_utils.c +++ b/drivers/gpu/drm/i915/gt/shmem_utils.c @@ -8,6 +8,7 @@ #include #include "gem/i915_gem_object.h" +#include "gem/i915_gem_lmem.h" #include "shmem_utils.h" struct file *shmem_create_from_data(const char *name, void *data, size_t len) @@ -39,7 +40,8 @@ struct file *shmem_create_from_object(struct drm_i915_gem_object *obj) return file; } - ptr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB); + ptr = i915_gem_object_pin_map_unlocked(obj, i915_gem_object_is_lmem(obj) ? + I915_MAP_WC : I915_MAP_WB); if (IS_ERR(ptr)) return ERR_CAST(ptr); -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 158/162] drm/i915: Support ww locks in suspend/resume
From: Venkata Ramana Nayana
Add ww locks during suspend/resume.
Signed-off-by: Venkata Ramana Nayana
---
drivers/gpu/drm/i915/i915_drv.c | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b7d40a9c00bf..c41865d5bf1e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1099,7 +1099,7 @@ static int i915_drm_prepare(struct drm_device *dev)
struct drm_i915_private *i915 = to_i915(dev);
if (HAS_LMEM(i915)) {
- struct intel_gt *gt= >gt;
+ struct intel_gt *gt = >gt;
long timeout = I915_GEM_IDLE_TIMEOUT;
int ret;
@@ -1182,7 +1182,8 @@ static int intel_dmem_evict_buffers(struct drm_device
*dev, bool in_suspend,
struct drm_i915_private *i915 = to_i915(dev);
struct drm_i915_gem_object *obj;
struct intel_memory_region *mem;
- int id, ret = 0;
+ struct i915_gem_ww_ctx ww;
+ int id, ret = 0, err = 0;
for_each_memory_region(mem, i915, id) {
struct list_head still_in_list;
@@ -1204,19 +1205,20 @@ static int intel_dmem_evict_buffers(struct drm_device
*dev, bool in_suspend,
mutex_unlock(>objects.lock);
+ i915_gem_ww_ctx_init (, true);
+retry:
+ err = i915_gem_object_lock(obj, );
+ if (err)
+ goto out_err;
+
if (in_suspend) {
obj->swapto = NULL;
obj->evicted = false;
ret = i915_gem_object_unbind(obj, 0);
if (ret ||
i915_gem_object_has_pinned_pages(obj)) {
- if
(!i915_gem_object_trylock(obj)) {
- ret = -EBUSY;
- goto next;
- }
ret =
i915_gem_perma_pinned_object_swapout(obj);
- i915_gem_object_unlock(obj);
- goto next;
+ goto out_err;
}
obj->do_swapping = true;
@@ -1228,13 +1230,7 @@ static int intel_dmem_evict_buffers(struct drm_device
*dev, bool in_suspend,
obj->evicted = true;
} else {
if
(i915_gem_object_has_pinned_pages(obj) && perma_pin) {
- if
(!i915_gem_object_trylock(obj)) {
- ret = -EBUSY;
- goto next;
- }
ret =
i915_gem_perma_pinned_object_swapin(obj);
- /* FIXME: Where is this error
message taken care of? */
- i915_gem_object_unlock(obj);
}
if (obj->swapto && obj->evicted &&
!perma_pin) {
@@ -1247,7 +1243,14 @@ static int intel_dmem_evict_buffers(struct drm_device
*dev, bool in_suspend,
}
}
}
-next:
+out_err:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+
mutex_lock(>objects.lock);
if (ret)
break;
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 161/162] drm/i915/dg1: allow pci to auto probe
From: Lucas De Marchi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c3d9b36ef651..603976b9a973 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1001,6 +1001,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_JSL_IDS(_info),
INTEL_TGL_12_IDS(_info),
INTEL_RKL_IDS(_info),
+ INTEL_DG1_IDS(_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
--
2.26.2
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH 160/162] drm/i915/dg1: Fix GPU hang due to shmemfs page drop
From: Venkata Ramana Nayana
This is to fix a bug in upstream
commit a6326a4f8ffb ("drm/i915/gt: Keep a no-frills swappable copy of the
default context state")
We allocate context state obj ce->state from lmem, so in
__engines_record_defaults(),
we call shmem_create_from_object(). Because it is lmem object, this call will
create a new shmemfs file, copy the contents into it, and return the file
pointer and assign to engine->default_state. Of course ce->state lmem object
is freed at the end of function __engines_record_redefaults().
Because a new shmemfs file is create for engine->default_state,
and more importantly, we DON'T mark the pages dirty after we write into it,
the OS page cache eviction will drop these pages.
Now with the test move forward, it will create new request/context, and will
copy the saved engine->default_state into ce->state. If the default_state
pages are dropped during page cache eviction, the copying will get new pages,
and copy garbage from the new pages. Next, ce->state will have wrong
instruction and causes GPU to hang.
The fixing is very simple, we just mark the shmemfs pages to be dirty when
writing into it, and also mark the pages to accessed when read/write to them.
Fixes: a6326a4f8ffb("drm/i915/gt: Keep a no-frills swappable copy of the
default context state")
Cc: Sudeep Dutt
Cc: Matthew Auld
Cc: Tvrtko Ursulin
Cc: Ramalingam C
Cc: Chris Wilson
Signed-off-by: CQ Tang
Signed-off-by: Venkata Ramana Nayana
---
drivers/gpu/drm/i915/gt/shmem_utils.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c
b/drivers/gpu/drm/i915/gt/shmem_utils.c
index 1fbc070a4651..e24c2c2342bb 100644
--- a/drivers/gpu/drm/i915/gt/shmem_utils.c
+++ b/drivers/gpu/drm/i915/gt/shmem_utils.c
@@ -105,10 +105,13 @@ static int __shmem_rw(struct file *file, loff_t off,
return PTR_ERR(page);
vaddr = kmap(page);
- if (write)
+ if (write) {
memcpy(vaddr + offset_in_page(off), ptr, this);
- else
+ set_page_dirty(page);
+ } else {
memcpy(ptr, vaddr + offset_in_page(off), this);
+ }
+ mark_page_accessed(page);
kunmap(page);
put_page(page);
--
2.26.2
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