Re: [Intel-gfx] [PATCH 03/17] drivers/gpu: Convert to mem*_page()
On Fri, Dec 04, 2020 at 11:33:08PM +0100, Thomas Gleixner wrote: > On Fri, Dec 04 2020 at 08:05, Ira Weiny wrote: > > So I think I'm going to submit the base patch to Andrew today (with some > > cleanups per the comments in this thread). > > Could you please base that on tip core/mm where the kmap_local() muck is > and use kmap_local() right away? Sure. Would that mean it should go through you and not Andrew? Ira > > Thanks, > > tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC-v1 16/16] drm/i915/pxp: Add plane decryption support
Could u please add the change details in patch as below
v3:
Chnage in API intel_pxp_gem_object_status()
On 2020-12-06 at 16:21:34 -0800, Huang, Sean Z wrote:
> From: Anshuman Gupta
>
> Add support to enable/disable PLANE_SURF Decryption Request bit.
> It requires only to enable plane decryption support when following
> condition met.
> 1. PAVP session is enabled.
for uniformity PAVP -> pxp here too.
Thanks,
Anshuman Gupta.
> 2. Buffer object is protected.
>
> v2:
> - Rebased to libva_cp-drm-tip_tgl_cp tree.
> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
>
> Cc: Bommu Krishnaiah
> Cc: Huang, Sean Z
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 019a2d6d807a..158c8dea0930 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -39,6 +39,8 @@
> #include
> #include
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_drv.h"
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> @@ -752,6 +754,11 @@ icl_program_input_csc(struct intel_plane *plane,
> PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
> }
>
> +static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
> +{
> + return obj->user_flags & I915_BO_PROTECTED ? true : false;
> +}
> +
> static void
> skl_plane_async_flip(struct intel_plane *plane,
>const struct intel_crtc_state *crtc_state,
> @@ -788,6 +795,7 @@ skl_program_plane(struct intel_plane *plane,
> u32 surf_addr = plane_state->color_plane[color_plane].offset;
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> @@ -798,7 +806,7 @@ skl_program_plane(struct intel_plane *plane,
> u8 alpha = plane_state->hw.alpha >> 8;
> u32 plane_color_ctl = 0, aux_dist = 0;
> unsigned long irqflags;
> - u32 keymsk, keymax;
> + u32 keymsk, keymax, plane_surf;
> u32 plane_ctl = plane_state->ctl;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> @@ -874,8 +882,15 @@ skl_program_plane(struct intel_plane *plane,
>* the control register just before the surface register.
>*/
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> - intel_plane_ggtt_offset(plane_state) + surf_addr);
> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> +
> + if (intel_pxp_gem_object_status(dev_priv) &&
> + intel_fb_obj_protected(obj))
> + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> + else
> + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
> +
> + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
>
> if (plane_state->scaler_id >= 0)
> skl_program_scaler(plane, crtc_state, plane_state);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c3b9ca142539..ebb66fbab7d9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7208,6 +7208,7 @@ enum {
> #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> #define PLANE_SURF(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
>
> #define _PLANE_OFFSET_1_B0x711a4
> #define _PLANE_OFFSET_2_B0x712a4
> --
> 2.17.1
>
___
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Re: [Intel-gfx] [PATCH v3 1/4] irq: export kstat_irqs
On Fri, Dec 04, 2020 at 06:43:37PM -0700, Jerry Snitselaar wrote: > To try and detect potential interrupt storms that > have been occurring with tpm_tis devices it was suggested > to use kstat_irqs() to get the number of interrupts. > Since tpm_tis can be built as a module it needs kstat_irqs > exported. I think you should also have a paragraph explicitly stating that i915_pmu.c contains a duplicate of kstat_irqs() because it is not exported as of today. It adds a lot more weight to this given that there is already existing mainline usage (kind of). > > Reported-by: kernel test robot I'm not sure if this makes much sense. > Cc: Thomas Gleixner > Cc: Jarkko Sakkinen > Cc: Jason Gunthorpe > Cc: Peter Huewe > Cc: James Bottomley > Cc: Matthew Garrett > Cc: Hans de Goede > Signed-off-by: Jerry Snitselaar /Jarkko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Intel PXP component - Mesa single session
== Series Details == Series: Introduce Intel PXP component - Mesa single session URL : https://patchwork.freedesktop.org/series/84620/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9451_full -> Patchwork_19073_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19073_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19073_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19073_full: ### IGT changes ### Possible regressions * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-iclb6/igt@kms_frontbuffer_track...@fbc-rgb565-draw-mmap-wc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-iclb7/igt@kms_frontbuffer_track...@fbc-rgb565-draw-mmap-wc.html New tests - New tests have been introduced between CI_DRM_9451_full and Patchwork_19073_full: ### New CI tests (1) ### * boot: - Statuses : 174 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19073_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2597]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-tglb1/igt@kms_async_fl...@test-time-stamp.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk3/igt@kms_cursor_...@pipe-a-cursor-128x42-offscreen.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk8/igt@kms_cursor_...@pipe-a-cursor-128x42-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-snb: [PASS][7] -> [DMESG-WARN][8] ([i915#42]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-snb5/igt@kms_cursor_...@pipe-a-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-snb7/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-64x21-offscreen.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2346]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-tglb5/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-tglb3/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html * igt@kms_draw_crc@draw-method-xrgb-blt-ytiled: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#52] / [i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk3/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk8/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#79]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@dpms-vs-vblank-race-interruptible@c-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#407]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl9/igt@kms_flip@dpms-vs-vblank-race-interrupti...@c-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl5/igt@kms_flip@dpms-vs-vblank-race-interrupti...@c-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html [20]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Intel PXP component - Mesa single session
== Series Details == Series: Introduce Intel PXP component - Mesa single session URL : https://patchwork.freedesktop.org/series/84620/ State : success == Summary == CI Bug Log - changes from CI_DRM_9451 -> Patchwork_19073 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/index.html New tests - New tests have been introduced between CI_DRM_9451 and Patchwork_19073: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19073 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-tgl-y/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@execlists: - fi-kbl-7500u: [PASS][3] -> [INCOMPLETE][4] ([i915#1037] / [i915#794]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-kbl-7500u/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-kbl-7500u/igt@i915_selftest@l...@execlists.html Possible fixes * igt@gem_ctx_exec@basic: - fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-tgl-y/igt@gem_ctx_e...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-tgl-y/igt@gem_ctx_e...@basic.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [DMESG-WARN][7] ([i915#2411] / [i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [FAIL][9] ([i915#579]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-kbl-guc/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-kbl-guc/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@gt_heartbeat: - fi-tgl-y: [DMESG-FAIL][11] ([i915#2601]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9451 -> Patchwork_19073 CI-20190529: 20190529 CI_DRM_9451: e5d4ddd912799f4fdaeadfc50507b3150e1ae9e8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5882: 47f770e8e544831ae5a984b2083df73f71067762 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19073: 2c2a5ec977c5c0462ecd664e07527d1017464105 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2c2a5ec977c5 drm/i915/pxp: Add plane decryption support 835fa00f2104 drm/i915/pxp: User interface for Protected buffer cb5b82433cec drm/i915/uapi: introduce drm_i915_gem_create_ext ad81178c888f mei: pxp: export pavp client to me client bus 61c300f2e8e9 drm/i915/pxp: Expose session state for display protection flip f363d53b2c55 drm/i915/pxp: Enable PXP power management 8d1a900379e7 drm/i915/pxp: Destroy arb session upon teardown f3d2af9143ce drm/i915/pxp: Func to send hardware session termination dce0eab4952c drm/i915/pxp: Create the arbitrary session after boot 6535c3768f7b drm/i915/pxp: Implement funcs to create the TEE channel 21ed306a5303 drm/i915/pxp: Implement funcs to get/set PXP tag 1f58bdf3d44d drm/i915/pxp: Read register to check hardware session state dbe74e292313 drm/i915/pxp: set KCR reg init during the boot time a44a71ee8f7a drm/i915/pxp: Add PXP context for logical hardware states. 900074c203b4 drm/i915/pxp: Enable PXP irq worker and callback stub 56ffa1e5dc43 drm/i915/pxp: Introduce Intel PXP component == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/index.html ___ Intel-gfx mailing list
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session
== Series Details == Series: Introduce Intel PXP component - Mesa single session URL : https://patchwork.freedesktop.org/series/84620/ State : warning == Summary == $ dim checkpatch origin/drm-tip 56ffa1e5dc43 drm/i915/pxp: Introduce Intel PXP component -:108: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #108: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 125 lines checked 900074c203b4 drm/i915/pxp: Enable PXP irq worker and callback stub a44a71ee8f7a drm/i915/pxp: Add PXP context for logical hardware states. -:106: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #106: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 165 lines checked dbe74e292313 drm/i915/pxp: set KCR reg init during the boot time -:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #69: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 102 lines checked 1f58bdf3d44d drm/i915/pxp: Read register to check hardware session state -:19: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #19: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.h:15: +#define pxp_session_list(i915, session_type) (((session_type) == SESSION_TYPE_TYPE0) ? \ + &(i915)->pxp.ctx->active_pxp_type0_sessions : &(i915)->pxp.ctx->active_pxp_type1_sessions) total: 0 errors, 0 warnings, 1 checks, 255 lines checked 21ed306a5303 drm/i915/pxp: Implement funcs to get/set PXP tag 6535c3768f7b drm/i915/pxp: Implement funcs to create the TEE channel -:87: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #87: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 244 lines checked dce0eab4952c drm/i915/pxp: Create the arbitrary session after boot f3d2af9143ce drm/i915/pxp: Func to send hardware session termination 8d1a900379e7 drm/i915/pxp: Destroy arb session upon teardown f363d53b2c55 drm/i915/pxp: Enable PXP power management -:67: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #67: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 140 lines checked 61c300f2e8e9 drm/i915/pxp: Expose session state for display protection flip ad81178c888f mei: pxp: export pavp client to me client bus -:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #32: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 277 lines checked cb5b82433cec drm/i915/uapi: introduce drm_i915_gem_create_ext -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas Lahtinen joonas.lahti...@linux.intel.com' #12: Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com -:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld matthew.a...@intel.com' #13: Cc: Matthew Auld matthew.a...@intel.com -:46: ERROR:CODE_INDENT: code indent should use tabs where possible #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #50: FILE: drivers/gpu/drm/i915/i915_gem.c:269: +static int __create_setparam(struct drm_i915_gem_object_param *args, + struct create_ext *ext_data) -:95: CHECK:LINE_SPACING: Please don't use multiple blank lines #95: FILE: drivers/gpu/drm/i915/i915_gem.c:317: + + -:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #107: FILE: include/uapi/drm/i915_drm.h:394: +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext) -:155: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #155: FILE: include/uapi/drm/i915_drm.h:1735: +#define I915_OBJECT_PARAM (1ull<<32) ^ total: 3 errors, 2 warnings, 3 checks, 136 lines checked 835fa00f2104 drm/i915/pxp: User interface for Protected buffer 2c2a5ec977c5 drm/i915/pxp: Add plane decryption support ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v1 16/16] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah
Cc: Huang, Sean Z
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 019a2d6d807a..158c8dea0930 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include
#include
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -752,6 +754,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -788,6 +795,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -798,7 +806,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -874,8 +882,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3b9ca142539..ebb66fbab7d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7208,6 +7208,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v1 08/16] drm/i915/pxp: Create the arbitrary session after boot
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 47 ++-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 7 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 165 +++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 8 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 34 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 11 ++
6 files changed, 271 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 332d9baff29f..10f4b1de07c4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -9,6 +9,43 @@
#include "intel_pxp_sm.h"
#include "intel_pxp_tee.h"
+int intel_pxp_create_arb_session(struct drm_i915_private *i915)
+{
+ struct pxp_tag pxptag;
+ int ret;
+
+ lockdep_assert_held(>pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->flag_display_hm_surface_keys) {
+ drm_err(>drm, "%s: arb session is alive so skipping the
creation\n",
+ __func__);
+ return 0;
+ }
+
+ ret = intel_pxp_sm_reserve_arb_session(i915, );
+ if (ret) {
+ drm_err(>drm, "Failed to reserve session\n");
+ goto end;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(i915);
+ if (ret) {
+ drm_err(>drm, "Failed to send tee cmd for arb session
creation\n");
+ goto end;
+ }
+
+ ret = pxp_sm_mark_protected_session_in_play(i915, ARB_SESSION_TYPE,
pxptag.session_id);
+ if (ret) {
+ drm_err(>drm, "Failed to mark session status in play\n");
+ goto end;
+ }
+
+ i915->pxp.ctx->flag_display_hm_surface_keys = true;
+
+end:
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
/* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
@@ -47,9 +84,17 @@ static int
intel_pxp_global_terminate_complete_callback(struct drm_i915_private
mutex_lock(>pxp.ctx->ctx_mutex);
- if (i915->pxp.ctx->global_state_attacked)
+ if (i915->pxp.ctx->global_state_attacked) {
i915->pxp.ctx->global_state_attacked = false;
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_create_arb_session(i915);
+ if (ret) {
+ drm_err(>drm, "Failed to create arb session\n");
+ goto end;
+ }
+ }
+end:
mutex_unlock(>pxp.ctx->ctx_mutex);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 308d8d312a6d..e5f6e2b1bdfd 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -41,6 +41,8 @@ struct intel_gt;
struct drm_i915_private;
#ifdef CONFIG_DRM_I915_PXP
+int intel_pxp_create_arb_session(struct drm_i915_private *i915);
+
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
@@ -48,6 +50,11 @@ int i915_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915);
int intel_pxp_init(struct drm_i915_private *i915);
void intel_pxp_uninit(struct drm_i915_private *i915);
#else
+static inline int intel_pxp_create_arb_session(struct drm_i915_private *i915)
+{
+ return 0;
+};
+
static inline void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
{
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 38c8b6d08b61..056f65fbaf4e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -41,6 +41,18 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return 0;
}
+static int pxp_get_session_index(struct drm_i915_private *i915, u32 pxp_tag,
+int *session_index_out, int *session_type_out)
+{
+ if (!session_index_out || !session_type_out)
+ return -EINVAL;
+
+ *session_type_out = (pxp_tag & SESSION_TYPE_MASK) ? SESSION_TYPE_TYPE1
: SESSION_TYPE_TYPE0;
+ *session_index_out = pxp_tag & SESSION_ID_MASK;
+
+ return 0;
+}
+
static u8 pxp_get_session_id(int session_index, int session_type)
{
u8 session_id = session_index & SESSION_ID_MASK;
@@ -266,6 +278,159 @@ static int sync_hw_sw_state(struct
[Intel-gfx] [RFC-v1 03/16] drm/i915/pxp: Add PXP context for logical hardware states.
Add PXP context which represents combined view
of driver and logical HW states.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 -
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 45
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 44 +++
5 files changed, 122 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a53ea3c88f71..99efac469cc2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -256,7 +256,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 07faaadb0031..769bfd9bc6b8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_context.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
@@ -28,12 +29,28 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32
mask)
static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
{
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ i915->pxp.ctx->global_state_attacked = true;
+ i915->pxp.ctx->flag_display_hm_surface_keys = false;
+
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+
return 0;
}
static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
{
- return 0;
+ int ret = 0;
+
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->global_state_attacked)
+ i915->pxp.ctx->global_state_attacked = false;
+
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+
+ return ret;
}
static void intel_pxp_irq_work(struct work_struct *work)
@@ -69,6 +86,12 @@ int intel_pxp_init(struct drm_i915_private *i915)
drm_info(>drm, "i915 PXP is inited with i915=[%p]\n", i915);
+ i915->pxp.ctx = intel_pxp_create_ctx(i915);
+ if (!i915->pxp.ctx) {
+ drm_err(>drm, "Failed to create pxp ctx\n");
+ return -EFAULT;
+ }
+
INIT_WORK(>pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
@@ -80,6 +103,10 @@ int intel_pxp_init(struct drm_i915_private *i915)
void intel_pxp_uninit(struct drm_i915_private *i915)
{
+ if (!i915 || INTEL_GEN(i915) < 12)
+ return;
+
+ intel_pxp_destroy_ctx(i915);
}
/**
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 7966dc275b54..eb0ec4a07d3d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define MAX_TYPE0_SESSIONS 16
+#define MAX_TYPE1_SESSIONS 6
+
enum pxp_sm_session_req {
/* Request KMD to allocate session id and move it to IN INIT */
PXP_SM_REQ_SESSION_ID_INIT = 0x0,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
new file mode 100644
index ..c340c375daac
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_context.h"
+
+/**
+ * intel_pxp_create_ctx - To create a new pxp context.
+ * @i915: i915 device handle.
+ *
+ * Return: pointer to new_ctx, NULL for failure
+ */
+struct pxp_context *intel_pxp_create_ctx(struct drm_i915_private *i915)
+{
+ struct pxp_context *new_ctx = NULL;
+
+ new_ctx = kzalloc(sizeof(*new_ctx), GFP_KERNEL);
+ if (!new_ctx)
+ return NULL;
+
+ get_random_bytes(_ctx->ctx_id, sizeof(new_ctx->ctx_id));
+
+ new_ctx->global_state_attacked = false;
+
+ mutex_init(_ctx->ctx_mutex);
+
+ INIT_LIST_HEAD(_ctx->active_pxp_type0_sessions);
+ INIT_LIST_HEAD(_ctx->active_pxp_type1_sessions);
+ INIT_LIST_HEAD(_ctx->user_ctx_list);
+
+ return new_ctx;
+}
+
+/**
+ * intel_pxp_destroy_ctx - To destroy the pxp context.
+ * @i915: i915 device handle.
+ *
+ * Return: return 0 for success, failure otherwise.
+ */
+void intel_pxp_destroy_ctx(struct drm_i915_private *i915)
+{
+ kfree(i915->pxp.ctx);
+ i915->pxp.ctx = NULL;
+}
diff
[Intel-gfx] [RFC-v1 11/16] drm/i915/pxp: Enable PXP power management
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 8 +++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 70 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++
4 files changed, 110 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3cc5fc250b33..11309f2634f1 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_sm.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 64399386292f..e0c31c1b0b36 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1093,6 +1095,8 @@ static int i915_drm_prepare(struct drm_device *dev)
*/
i915_gem_suspend(i915);
+ intel_pxp_pm_prepare_suspend(i915);
+
return 0;
}
@@ -1278,6 +1282,8 @@ static int i915_drm_resume(struct drm_device *dev)
intel_gvt_resume(dev_priv);
+ intel_pxp_pm_resume(dev_priv);
+
enable_rpm_wakeref_asserts(_priv->runtime_pm);
return 0;
@@ -1349,6 +1355,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(dev_priv);
+
enable_rpm_wakeref_asserts(_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..454351a70565
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct drm_i915_private *i915)
+{
+ if (!i915->pxp.ctx)
+ return;
+
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ /* Disable PXP-IOCTLs */
+ i915->pxp.ctx->global_state_in_suspend = true;
+
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+}
+
+void intel_pxp_pm_resume_early(struct drm_i915_private *i915)
+{
+ if (!i915->pxp.ctx)
+ return;
+
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ i915->pxp.ctx->global_state_attacked = false;
+
+ i915->pxp.ctx->flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+}
+
+int intel_pxp_pm_resume(struct drm_i915_private *i915)
+{
+ int ret = 0;
+
+ if (!i915->pxp.ctx)
+ return 0;
+
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (i915->pxp.ctx->global_state_in_suspend) {
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE0);
+ if (ret) {
+ drm_err(>drm, "Failed to
intel_pxp_sm_terminate_all_active_sessions with type0\n");
+ goto end;
+ }
+
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE1);
+ if (ret) {
+ drm_err(>drm, "Failed to
intel_pxp_sm_terminate_all_active_sessions with type1\n");
+ goto end;
+ }
+
+ i915->pxp.ctx->global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index ..b66b7e95e211
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_pm_prepare_suspend(struct drm_i915_private *i915);
+
+void intel_pxp_pm_resume_early(struct drm_i915_private *i915);
+int intel_pxp_pm_resume(struct drm_i915_private
[Intel-gfx] [RFC-v1 12/16] drm/i915/pxp: Expose session state for display protection flip
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
drivers/gpu/drm/i915/pxp/intel_pxp.h | 7 +++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 48a0eb16f1d9..0fbdd7eecefe 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -201,3 +201,11 @@ void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
i915->pxp.current_events |= events;
schedule_work(>pxp.irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->pxp.ctx && i915->pxp.ctx->flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 425cafe24392..88919f8a2403 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -52,6 +52,8 @@ int i915_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915);
int intel_pxp_init(struct drm_i915_private *i915);
void intel_pxp_uninit(struct drm_i915_private *i915);
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
#else
static inline int intel_pxp_create_arb_session(struct drm_i915_private *i915)
{
@@ -80,6 +82,11 @@ static inline int intel_pxp_init(struct drm_i915_private
*i915)
static inline void intel_pxp_uninit(struct drm_i915_private *i915)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
#endif
#endif /* __INTEL_PXP_PM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag
Implement the functions to get/set the PXP tag, which is 32-bit
bitwise value containing the hardware session info, such as its
session id, protection mode or whether it's enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 125 ++--
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 18
2 files changed, 112 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 6413f401d939..38c8b6d08b61 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -41,6 +41,16 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return 0;
}
+static u8 pxp_get_session_id(int session_index, int session_type)
+{
+ u8 session_id = session_index & SESSION_ID_MASK;
+
+ if (session_type == SESSION_TYPE_TYPE1)
+ session_id |= SESSION_TYPE_MASK;
+
+ return session_id;
+}
+
/**
* is_sw_session_active - Check if the given sw session id is active.
* @i915: i915 device handle.
@@ -78,6 +88,90 @@ static bool is_sw_session_active(struct drm_i915_private
*i915, int session_type
return false;
}
+static int pxp_set_pxp_tag(struct drm_i915_private *i915, int session_type,
+ int session_idx, int protection_mode)
+{
+ struct pxp_tag *pxp_tag;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX)
+ return -EINVAL;
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx <
MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)>pxp.ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx <
MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)>pxp.ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ drm_err(>drm, "Failed to %s, bad params
session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ return -EINVAL;
+ }
+
+ switch (protection_mode) {
+ case PROTECTION_MODE_NONE:
+ {
+ pxp_tag->enable = false;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ break;
+ }
+ case PROTECTION_MODE_LM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_HM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_SM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = true;
+ pxp_tag->instance_id++;
+ break;
+ }
+ default:
+ drm_err(>drm, "Failed to %s, bad params
protection_mode=[%d]\n",
+ __func__, protection_mode);
+ return -EINVAL;
+ }
+
+ pxp_tag->session_id = pxp_get_session_id(session_idx, session_type);
+ return 0;
+}
+
+u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
+ int session_type, u32 *session_is_alive)
+{
+ struct pxp_tag *pxp_tag;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX)
+ return -EINVAL;
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx <
MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)>pxp.ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx <
MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)>pxp.ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ drm_err(>drm, "Failed to %s, bad params
session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ return -EINVAL;
+ }
+
+ if (session_is_alive)
+ *session_is_alive = pxp_tag->enable;
+
+ return pxp_tag->value;
+}
+
static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int
session_index)
{
u32 regval_sip = 0;
@@ -172,37 +266,6 @@ static int sync_hw_sw_state(struct drm_i915_private *i915,
int session_index, in
return ret;
}
-/**
- * check_if_protected_type0_sessions_are_attacked - To check if type0 active
sessions are attacked.
- * @i915: i915 device handle.
- *
- * Return: true if HW shows protected sessions are attacked, false otherwise.
- */
-static bool check_if_protected_type0_sessions_are_attacked(struct
drm_i915_private *i915)
-{
- i915_reg_t kcr_status_reg = KCR_STATUS_1;
- u32 reg_value = 0;
- u32 mask = 0x8000;
- int ret;
-
- if (!i915)
-
[Intel-gfx] [RFC-v1 14/16] drm/i915/uapi: introduce drm_i915_gem_create_ext
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Cc: Matthew Auld matthew.a...@intel.com
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 -
include/uapi/drm/i915_drm.h | 47 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e0c31c1b0b36..14b0fa04ed14 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1742,7 +1742,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..41698a823737 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
>size, >handle);
}
+struct create_ext {
+struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ _data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fa1f3d62f9a6..2c1ce2761d55 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size for the object.
+*
+
[Intel-gfx] [RFC-v1 13/16] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index c06581ffa7bd..36884b0a6395 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -57,3 +57,5 @@ config INTEL_MEI_VIRTIO
device over virtio.
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index 52aefaab5c1b..cab19c96ba7a 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -29,3 +29,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = _pxp_ops;
+
[Intel-gfx] [RFC-v1 05/16] drm/i915/pxp: Read register to check hardware session state
Implement the functions to check the hardware protected session
state via reading the hardware register session in play.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.h| 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 177
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 51 +++
3 files changed, 231 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index eb0ec4a07d3d..308d8d312a6d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define pxp_session_list(i915, session_type) (((session_type) ==
SESSION_TYPE_TYPE0) ? \
+ &(i915)->pxp.ctx->active_pxp_type0_sessions :
&(i915)->pxp.ctx->active_pxp_type1_sessions)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index a2c9c71d2372..6413f401d939 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -10,6 +10,21 @@
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+static int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32
*regval)
+{
+ intel_wakeref_t wakeref;
+
+ if (!i915 || !regval)
+ return -EINVAL;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+ *regval = intel_uncore_read(>uncore, reg_offset);
+ }
+
+ return 0;
+}
+
static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
{
intel_wakeref_t wakeref;
@@ -26,6 +41,168 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return 0;
}
+/**
+ * is_sw_session_active - Check if the given sw session id is active.
+ * @i915: i915 device handle.
+ * @session_type: Specified session type
+ * @session_index: Numeric session identifier.
+ * @is_in_play: Set false to return true if the specified session is active.
+ * Set true to also check if the session is active and in_play.
+ * @protection_mode: get the protection mode of specified session.
+ *
+ * The caller needs to use ctx_mutex lock to protect the session_list
+ * inside this function.
+ *
+ * Return : true if session with the same identifier is active (and in_play).
+ */
+static bool is_sw_session_active(struct drm_i915_private *i915, int
session_type,
+int session_index, bool is_in_play, int
*protection_mode)
+{
+ struct pxp_protected_session *current_session;
+
+ lockdep_assert_held(>pxp.ctx->ctx_mutex);
+
+ list_for_each_entry(current_session, pxp_session_list(i915,
session_type), session_list) {
+ if (current_session->session_index == session_index) {
+ if (protection_mode)
+ *protection_mode =
current_session->protection_mode;
+
+ if (is_in_play && !current_session->session_is_in_play)
+ return false;
+
+ return true;
+ }
+ }
+
+ /* session id not found. return false */
+ return false;
+}
+
+static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int
session_index)
+{
+ u32 regval_sip = 0;
+ u32 reg_session_id_mask;
+ bool hw_session_is_in_play = false;
+ int ret = 0;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE0_SESSIONS)
+ goto end;
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_SIP.reg, _sip);
+ if (ret) {
+ drm_err(>drm, "Failed to read()\n");
+ goto end;
+ }
+
+ reg_session_id_mask = (1 << session_index);
+ hw_session_is_in_play = (bool)(regval_sip & reg_session_id_mask);
+end:
+ return hw_session_is_in_play;
+}
+
+static bool is_hw_type1_session_in_play(struct drm_i915_private *i915, int
session_index)
+{
+ int ret = 0;
+ u32 regval_tsip_low = 0;
+ u32 regval_tsip_high = 0;
+ u64 reg_session_id_mask;
+ u64 regval_tsip;
+ bool hw_session_is_in_play = false;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE1_SESSIONS)
+ goto end;
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_LOW.reg, _tsip_low);
+ if (ret) {
+ drm_err(>drm, "Failed to pxp_sm_reg_read()\n");
+ goto end;
+ }
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_HIGH.reg, _tsip_high);
+ if (ret) {
+ drm_err(>drm, "Failed to pxp_sm_reg_read()\n");
+ goto end;
+ }
+
+ reg_session_id_mask = (1 << session_index);
+ regval_tsip = ((u64)regval_tsip_high << 32) | regval_tsip_low;
+
[Intel-gfx] [RFC-v1 07/16] drm/i915/pxp: Implement funcs to create the TEE channel
Currently ring3 driver sends the TEE commands directly to TEE, but
later, as our design, we would like to make ring3 sending the TEE
commands via the ring0 PXP ioctl action instead of TEE ioctl, so
we can centralize those protection operations at ring0 PXP.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 127 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
8 files changed, 201 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 131bd8921565..3cc5fc250b33 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
- pxp/intel_pxp_sm.o
+ pxp/intel_pxp_sm.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1e5ecaff571f..64399386292f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
mutex_init(_priv->wm.wm_mutex);
mutex_init(_priv->pps_mutex);
mutex_init(_priv->hdcp_comp_mutex);
+ mutex_init(_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 33a3f5c387b0..32e9cce925d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1219,6 +1219,12 @@ struct drm_i915_private {
struct intel_pxp pxp;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index d74a32b29716..332d9baff29f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
+#include "intel_pxp_tee.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
@@ -101,6 +102,8 @@ int intel_pxp_init(struct drm_i915_private *i915)
return ret;
}
+ intel_pxp_tee_component_init(i915);
+
INIT_WORK(>pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
@@ -115,6 +118,8 @@ void intel_pxp_uninit(struct drm_i915_private *i915)
if (!i915 || INTEL_GEN(i915) < 12)
return;
+ intel_pxp_tee_component_fini(i915);
+
intel_pxp_destroy_ctx(i915);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..fa617546bdd4
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct drm_i915_private *i915,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(>pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size,
true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in,
msg_in_size);
+ if (ret) {
+ drm_err(>drm, "Failed to send TEE message\n");
+ return -EFAULT;
+ }
+
+ ret =
[Intel-gfx] [RFC-v1 15/16] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6299da64de4..dd5d24a13cb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2060,12 +2060,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..5897e7ca11a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, >user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, >user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..81ae94c2be86 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -135,7 +135,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41698a823737..6a791fd24eaa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, >base, );
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
[Intel-gfx] [RFC-v1 10/16] drm/i915/pxp: Destroy arb session upon teardown
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 6 +-
drivers/gpu/drm/i915/pxp/intel_pxp.h| 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 207
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 17 ++
4 files changed, 232 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 10f4b1de07c4..48a0eb16f1d9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -68,14 +68,18 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32
mask)
static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
{
+ int ret;
+
mutex_lock(>pxp.ctx->ctx_mutex);
i915->pxp.ctx->global_state_attacked = true;
i915->pxp.ctx->flag_display_hm_surface_keys = false;
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE0);
+
mutex_unlock(>pxp.ctx->ctx_mutex);
- return 0;
+ return ret;
}
static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index e5f6e2b1bdfd..425cafe24392 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -15,6 +15,9 @@
#define pxp_session_list(i915, session_type) (((session_type) ==
SESSION_TYPE_TYPE0) ? \
&(i915)->pxp.ctx->active_pxp_type0_sessions :
&(i915)->pxp.ctx->active_pxp_type1_sessions)
+#define pxp_session_max(session_type) (((session_type) == SESSION_TYPE_TYPE0)
? \
+ MAX_TYPE0_SESSIONS : MAX_TYPE1_SESSIONS)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index c88243e02a3c..f8bb5248247f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -581,6 +581,213 @@ int pxp_sm_mark_protected_session_in_play(struct
drm_i915_private *i915, int ses
return -EINVAL;
}
+static int add_pxp_prolog(struct drm_i915_private *i915, u32 *cmd, int
session_type,
+ int session_index)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_prolog = cmd;
+ const int cmd_prolog_size_in_dw = 10;
+
+ if (!cmd)
+ return cmd_prolog_size_in_dw;
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are
cmopleted */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_prolog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_prolog++ = 0;/* DW1 */
+ *cmd_prolog++ = 0;/* DW2 */
+
+ /* MI_SET_APPID */
+ if (session_type == SESSION_TYPE_TYPE1) {
+ if (session_index >= MAX_TYPE1_SESSIONS) {
+ drm_err(>drm, "Failed to %s invalid
session_index\n", __func__);
+ goto end;
+ }
+
+ *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_TYPE1_APP |
+MI_SET_APPID_SESSION_ID(session_index));
+ } else {
+ if (session_index >= MAX_TYPE0_SESSIONS) {
+ drm_err(>drm, "Failed to %s invalid
session_index\n", __func__);
+ goto end;
+ }
+
+ *cmd_prolog++ = (MI_SET_APPID |
MI_SET_APPID_SESSION_ID(session_index));
+ }
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp on */
+ *cmd_prolog++ = (MI_FLUSH_DW |
MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE); /* DW0 */
+ *cmd_prolog++ = 0;
/* DW1 */
+ *cmd_prolog++ = 0;
/* DW2 */
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ increased_size_in_dw = (cmd_prolog - cmd);
+end:
+ return increased_size_in_dw;
+}
+
+static int add_pxp_epilog(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_epilog = cmd;
+ const int cmd_epilog_size_in_dw = 5;
+
+ if (!cmd)
+ return cmd_epilog_size_in_dw;
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_epilog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_epilog++ = 0;/* DW1 */
+ *cmd_epilog++ = 0;/* DW2 */
+
[Intel-gfx] [RFC-v1 04/16] drm/i915/pxp: set KCR reg init during the boot time
Set the KCR init during the boot time, which is required by
hardware, to allow us doing further protection operation such
as sending commands to GPU or TEE
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c| 11 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 38 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 20 +
4 files changed, 70 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 99efac469cc2..131bd8921565 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -257,7 +257,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_sm.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 769bfd9bc6b8..d74a32b29716 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
@@ -77,6 +78,8 @@ static void intel_pxp_irq_work(struct work_struct *work)
int intel_pxp_init(struct drm_i915_private *i915)
{
+ int ret;
+
if (!i915)
return -EINVAL;
@@ -92,13 +95,19 @@ int intel_pxp_init(struct drm_i915_private *i915)
return -EFAULT;
}
+ ret = pxp_sm_set_kcr_init_reg(i915);
+ if (ret) {
+ drm_err(>drm, "Failed to set kcr init reg\n");
+ return ret;
+ }
+
INIT_WORK(>pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
- return 0;
+ return ret;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
new file mode 100644
index ..a2c9c71d2372
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_context.h"
+
+static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
+{
+ intel_wakeref_t wakeref;
+
+ if (!i915)
+ return -EINVAL;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+
+ intel_uncore_write(>uncore, reg_offset, regval);
+ }
+
+ return 0;
+}
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
+{
+ int ret;
+
+ ret = pxp_reg_write(i915, KCR_INIT.reg,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ if (ret)
+ drm_err(>drm, "Failed to write()\n");
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
new file mode 100644
index ..d061f395aa16
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_SM_H__
+#define __INTEL_PXP_SM_H__
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+
+/* KCR register definitions */
+#define KCR_INIT_MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
+
+#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v1 09/16] drm/i915/pxp: Func to send hardware session termination
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 150
1 file changed, 150 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 056f65fbaf4e..c88243e02a3c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -3,13 +3,163 @@
* Copyright(c) 2020, Intel Corporation. All rights reserved.
*/
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
#include "gt/intel_context.h"
+#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_engine_pm.h"
#include "intel_pxp.h"
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+static struct i915_vma *pxp_get_batch(struct drm_i915_private *i915,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>drm, "Failed to %s, invalid
cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>drm, "Failed to i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+static int pxp_submit_cmd(struct drm_i915_private *i915, u32 *cmd, int
cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = NULL;
+
+ if (!i915 || !HAS_ENGINE(>gt, VCS0) ||
+ !i915->gt.engine[VCS0]->kernel_context) {
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(>drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ gt = >gt;
+ ce = i915->gt.engine[VCS0]->kernel_context;
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_err(>drm, "Failed to intel_engine_get_pool()\n");
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = pxp_get_batch(i915, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_err(>drm, "Failed to pxp_get_batch()\n");
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_err(>drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_err(>drm, "Failed to
intel_context_create_request()\n");
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+ drm_err(>drm, "Failed to
intel_engine_pool_mark_active()\n");
+ goto end;
+ }
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err) {
+ drm_err(>drm, "Failed to i915_request_await_object()\n");
+ goto end;
+ }
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err) {
+ drm_err(>drm, "Failed to
emit_init_breadcrumb()\n");
+ goto end;
+ }
+ }
+
+ err = ce->engine->emit_bb_start(rq, batch->node.start,
+
[Intel-gfx] [RFC-v1 02/16] drm/i915/pxp: Enable PXP irq worker and callback stub
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 ++
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 88 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 36 +++
4 files changed, 129 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 257063a57101..d64013d0afb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_gt_irq.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(gt, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5375b219cc3b..c3b9ca142539 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7943,6 +7943,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3de4593ca495..07faaadb0031 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,58 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
+{
+ /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
+ intel_uncore_write(>uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask <<
16);
+}
+
+static void intel_pxp_unmask_irq(struct intel_gt *gt)
+{
+ lockdep_assert_held(>irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, 0);
+}
+
+static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, mask);
+}
+
+static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
+{
+ return 0;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
+{
+ return 0;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp_ptr = container_of(work, typeof(*pxp_ptr),
irq_work);
+ struct drm_i915_private *i915 = container_of(pxp_ptr, typeof(*i915),
pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>gt.irq_lock);
+ events = fetch_and_zero(_ptr->current_events);
+ spin_unlock_irq(>gt.irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(i915);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(i915);
+
+ spin_lock_irq(>gt.irq_lock);
+ intel_pxp_unmask_irq(>gt);
+ spin_unlock_irq(>gt.irq_lock);
+}
+
int intel_pxp_init(struct drm_i915_private *i915)
{
if (!i915)
@@ -17,9 +69,45 @@ int intel_pxp_init(struct drm_i915_private *i915)
drm_info(>drm, "i915 PXP is inited with i915=[%p]\n", i915);
+ INIT_WORK(>pxp.irq_work, intel_pxp_irq_work);
+
+ i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
+
return 0;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
{
}
+
+/**
+ * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
+ * @gt: valid GT instance
+ * @iir: GT interrupt vector associated with the interrupt
+ *
+ * Dispatches each vector element into an IRQ to PXP.
+ */
+void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
+{
+ struct drm_i915_private *i915;
+ const u32 events = iir & i915->pxp.handled_irr;
+
+ if (!gt || !gt->i915 || INTEL_GEN(i915) < 12)
+ return;
+
+ i915 = gt->i915;
+
+ lockdep_assert_held(>irq_lock);
+
+ if (unlikely(!events)) {
+ drm_err(>drm, "%s returned due to iir=[0x%04x]\n",
__func__, iir);
+ return;
+ }
+
+ intel_pxp_mask_irq(gt, i915->pxp.handled_irr);
+
+ i915->pxp.current_events |= events;
+ schedule_work(>pxp.irq_work);
+}
diff
[Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session
PXP is an i915 componment, that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. This patch series is to allow the kernel space to create and manage a single hardware session (a.k.a default session or arbitrary session). So Mesa can allocate the protected buffer, which is encrypted with the leverage of the arbitrary hardware session. Anshuman Gupta (1): drm/i915/pxp: Add plane decryption support Bommu Krishnaiah (2): drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915/pxp: User interface for Protected buffer Huang, Sean Z (12): drm/i915/pxp: Introduce Intel PXP component drm/i915/pxp: Enable PXP irq worker and callback stub drm/i915/pxp: Add PXP context for logical hardware states. drm/i915/pxp: set KCR reg init during the boot time drm/i915/pxp: Read register to check hardware session state drm/i915/pxp: Implement funcs to get/set PXP tag drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Func to send hardware session termination drm/i915/pxp: Destroy arb session upon teardown drm/i915/pxp: Enable PXP power management drm/i915/pxp: Expose session state for display protection flip Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Kconfig | 19 + drivers/gpu/drm/i915/Makefile | 8 + drivers/gpu/drm/i915/display/intel_sprite.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 4 + drivers/gpu/drm/i915/i915_drv.c | 15 +- drivers/gpu/drm/i915/i915_drv.h | 10 + drivers/gpu/drm/i915/i915_gem.c | 63 +- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 211 + drivers/gpu/drm/i915/pxp/intel_pxp.h | 92 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 45 + drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 44 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 70 ++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 + drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 800 ++ drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 114 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 161 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 25 + drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c| 230 + drivers/misc/mei/pxp/mei_pxp.h| 18 + include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 + include/uapi/drm/i915_drm.h | 66 ++ 31 files changed, 2139 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h create mode 100644 drivers/misc/mei/pxp/Kconfig create mode 100644 drivers/misc/mei/pxp/Makefile create mode 100644 drivers/misc/mei/pxp/mei_pxp.c create mode 100644 drivers/misc/mei/pxp/mei_pxp.h create mode 100644 include/drm/i915_pxp_tee_interface.h -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps user space to establish the hardware protected session
and manage the status of each alive software session, as well as
the life cycle of each session.
By design PXP will expose ioctl so allow user space to create, set,
and destroy each session. It will also provide the communication
chanel to TEE (Trusted Execution Environment) for the protected
hardware session creation.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Kconfig | 19
drivers/gpu/drm/i915/Makefile| 4
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/pxp/intel_pxp.c | 25 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 33
6 files changed, 89 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..f82ccc901b1e 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI_PXP
+ default n
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP is an i915 componment, available on Gen12+, that helps user
+ space to establish the hardware protected session and manage the
+ status of each alive software session, as well as the life cycle
+ of each session.
+
+ PXP expose ioctl so allow user space to create, set, and destroy
+ each session. It will also provide the communication chanel to
+ TEE (Trusted Execution Environment) for the protected hardware
+ session creation.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..a53ea3c88f71 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -254,6 +254,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 320856b665a1..1e5ecaff571f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -889,6 +889,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
goto out_cleanup_gem;
+ intel_pxp_init(i915);
+
i915_driver_register(i915);
enable_rpm_wakeref_asserts(>runtime_pm);
@@ -938,6 +940,8 @@ void i915_driver_remove(struct drm_i915_private *i915)
/* Flush any external code that still may be under the RCU lock */
synchronize_rcu();
+ intel_pxp_uninit(i915);
+
i915_gem_suspend(i915);
drm_atomic_helper_shutdown(>drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fecb5899cbac..33a3f5c387b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -105,6 +105,8 @@
#include "intel_region_lmem.h"
+#include "pxp/intel_pxp.h"
+
/* General customization:
*/
@@ -1215,6 +1217,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct intel_pxp pxp;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..3de4593ca495
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "intel_pxp.h"
+
+int intel_pxp_init(struct drm_i915_private *i915)
+{
+ if (!i915)
+ return -EINVAL;
+
+ /* PXP only available for GEN12+ */
+ if (INTEL_GEN(i915) < 12)
+ return 0;
+
+ drm_info(>drm, "i915 PXP is inited with i915=[%p]\n", i915);
+
+ return 0;
+}
+
+void intel_pxp_uninit(struct drm_i915_private *i915)
+{
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index ..0b83d33045f3
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier:
Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/pmu: Use kstat_irqs to get interrupt count
On Sun, Dec 06 2020 at 14:47, Jerry Snitselaar wrote: > Thomas Gleixner @ 2020-12-06 09:38 MST: > > I don't know the history behind this bit. I stumbled across it in cscope > when looking for places using kstat_irqs. I'm not ranting at you. The i915 people are on Cc. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for tpm_tis: Detect interrupt storms (rev2)
== Series Details == Series: tpm_tis: Detect interrupt storms (rev2) URL : https://patchwork.freedesktop.org/series/84608/ State : success == Summary == CI Bug Log - changes from CI_DRM_9450_full -> Patchwork_19072_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9450_full and Patchwork_19072_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19072_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([i915#2405]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-apl6/igt@gem_soft...@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-apl2/igt@gem_soft...@noreloc-s3.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#2405] / [i915#300]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][5] -> [FAIL][6] ([i915#96]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-hsw2/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2346]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-tglb2/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-tglb1/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#49]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-apl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-apl4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html - shard-glk: [PASS][11] -> [FAIL][12] ([i915#49]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-glk1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-glk4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#49]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-kbl6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-skl9/igt@kms_...@bpc-switch-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-skl7/igt@kms_...@bpc-switch-suspend.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-iclb2/igt@kms_psr2...@frontbuffer.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-iclb7/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-iclb2/igt@kms_psr@psr2_basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/shard-iclb8/igt@kms_psr@psr2_basic.html Possible fixes * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [FAIL][23] ([i915#54]) -> [PASS][24] +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-skl1/igt@kms_cursor_...@pipe-c-cursor-suspend.html [24]:
Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/pmu: Use kstat_irqs to get interrupt count
Thomas Gleixner @ 2020-12-06 09:38 MST:
> On Fri, Dec 04 2020 at 18:43, Jerry Snitselaar wrote:
>
>> Now that kstat_irqs is exported, get rid of count_interrupts in
>> i915_pmu.c
>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>> @@ -423,22 +423,6 @@ static enum hrtimer_restart i915_sample(struct hrtimer
>> *hrtimer)
>> return HRTIMER_RESTART;
>> }
>>
>> -static u64 count_interrupts(struct drm_i915_private *i915)
>> -{
>> -/* open-coded kstat_irqs() */
>> -struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
>> -u64 sum = 0;
>> -int cpu;
>> -
>> -if (!desc || !desc->kstat_irqs)
>> -return 0;
>> -
>> -for_each_possible_cpu(cpu)
>> -sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
>> -
>> -return sum;
>> -}
>
> May I ask why this has been merged in the first place?
>
> Nothing in a driver has ever to fiddle with the internals of an irq
> descriptor. We have functions for properly accessing them. Just because
> C allows to fiddle with everything is not a justification. If the
> required function is not exported then adding the export with a proper
> explanation is not asked too much.
>
> Also this lacks protection or at least a comment why this can be called
> safely and is not subject to a concurrent removal of the irq descriptor.
> The same problem exists when calling kstat_irqs(). It's even documented
> at the top of the function.
>
> Thanks,
>
> tglx
I don't know the history behind this bit. I stumbled across it in cscope
when looking for places using kstat_irqs.
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Re: [Intel-gfx] [PATCH v3 1/4] irq: export kstat_irqs
Thomas Gleixner @ 2020-12-06 10:54 MST: > Jerry, > > On Fri, Dec 04 2020 at 18:43, Jerry Snitselaar wrote: > > The proper prefix is 'genirq:' git log kernel/irq/irqdesc.c would have > told you. > >> To try and detect potential interrupt storms that >> have been occurring with tpm_tis devices it was suggested >> to use kstat_irqs() to get the number of interrupts. >> Since tpm_tis can be built as a module it needs kstat_irqs >> exported. > > I'm not really enthused about exporting this without making it at least > safe. Using it from an interrupt handler is obviously safe vs. concurrent > removal, but the next driver writer who thinks this is cool is going to > get it wrong for sure. > > Though I still have to figure out what the advantage of invoking a > function which needs to do a radix tree lookup over a device local > counter is just to keep track of this. > > I'll reply on the TPM part of this as well. > > Thanks, > > tglx I can rework it to use a device local counter. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/pmu: Use kstat_irqs to get interrupt count
On Sun, Dec 06 2020 at 17:38, Thomas Gleixner wrote: > On Fri, Dec 04 2020 at 18:43, Jerry Snitselaar wrote: >> Now that kstat_irqs is exported, get rid of count_interrupts in >> i915_pmu.c > > May I ask why this has been merged in the first place? > > Nothing in a driver has ever to fiddle with the internals of an irq > descriptor. We have functions for properly accessing them. Just because > C allows to fiddle with everything is not a justification. If the > required function is not exported then adding the export with a proper > explanation is not asked too much. > > Also this lacks protection or at least a comment why this can be called > safely and is not subject to a concurrent removal of the irq descriptor. > The same problem exists when calling kstat_irqs(). It's even documented > at the top of the function. And as pointed out vs. that TPM thing this really could have been a trivial i915->irqs++; in the interrupt handler and a read of that instead of iterating over all possible cpus and summing it up. Oh well... Thanks, tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for tpm_tis: Detect interrupt storms (rev2)
== Series Details == Series: tpm_tis: Detect interrupt storms (rev2) URL : https://patchwork.freedesktop.org/series/84608/ State : success == Summary == CI Bug Log - changes from CI_DRM_9450 -> Patchwork_19072 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/index.html New tests - New tests have been introduced between CI_DRM_9450 and Patchwork_19072: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19072 that come from known issues: ### IGT changes ### Issues hit * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html Possible fixes * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][3] ([i915#402]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9450 -> Patchwork_19072 CI-20190529: 20190529 CI_DRM_9450: 83b8d6ab0631ef13a095c7818d3c2c40f52f42ce @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19072: 605edf549fdee6b005f49176d476260cd18cf306 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 605edf549fde tpm_tis: Disable Interrupts on the ThinkPad L490 61225780bab4 tpm_tis: Disable interrupts if interrupt storm detected f275d76d2070 drm/i915/pmu: Use kstat_irqs to get interrupt count f8859e000a36 irq: export kstat_irqs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19072/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for tpm_tis: Detect interrupt storms (rev2)
== Series Details == Series: tpm_tis: Detect interrupt storms (rev2) URL : https://patchwork.freedesktop.org/series/84608/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for tpm_tis: Detect interrupt storms (rev2)
== Series Details == Series: tpm_tis: Detect interrupt storms (rev2) URL : https://patchwork.freedesktop.org/series/84608/ State : warning == Summary == $ dim checkpatch origin/drm-tip f8859e000a36 irq: export kstat_irqs f275d76d2070 drm/i915/pmu: Use kstat_irqs to get interrupt count 61225780bab4 tpm_tis: Disable interrupts if interrupt storm detected -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: > @@ -715,9 +717,23 @@ static irqreturn_t tis_int_handler(int dummy, void > *dev_id) -:149: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 1 warnings, 0 checks, 41 lines checked 605edf549fde tpm_tis: Disable Interrupts on the ThinkPad L490 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/4] irq: export kstat_irqs
On Sun, Dec 06 2020 at 09:40, James Bottomley wrote: > On Sun, 2020-12-06 at 17:40 +0100, Thomas Gleixner wrote: >> On Sat, Dec 05 2020 at 12:39, Jarkko Sakkinen wrote: >> > On Fri, Dec 04, 2020 at 06:43:37PM -0700, Jerry Snitselaar wrote: >> > > To try and detect potential interrupt storms that >> > > have been occurring with tpm_tis devices it was suggested >> > > to use kstat_irqs() to get the number of interrupts. >> > > Since tpm_tis can be built as a module it needs kstat_irqs >> > > exported. >> > >> > I think you should also have a paragraph explicitly stating that >> > i915_pmu.c contains a duplicate of kstat_irqs() because it is not >> > exported as of today. It adds a lot more weight to this given that >> > there is already existing mainline usage (kind of). >> >> It's abusage and just the fact that it exists is not an argument by >> itself. > > What we want is a count of the interrupts to see if we're having an > interrupt storm from the TPM device (some seem to be wired to fire the > interrupt even when there's no event to warrant it). Since > kstat_irqs_user() does the correct RCU locking, should we be using that > instead? If we need to export it, yes. But I still have to understand the value. See my other reply. Thanks, tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 3/4] tpm_tis: Disable interrupts if interrupt storm detected
Jerry,
On Fri, Dec 04 2020 at 18:43, Jerry Snitselaar wrote:
> @@ -715,9 +717,23 @@ static irqreturn_t tis_int_handler(int dummy, void
> *dev_id)
> {
> struct tpm_chip *chip = dev_id;
> struct tpm_tis_data *priv = dev_get_drvdata(>dev);
> + static bool check_storm = true;
> + static unsigned int check_start;
So this assumes that there can't be two TPMs which is probably true, but
everything else in this driver has stuff in tpm_tis_data per device.
> u32 interrupt;
> int i, rc;
>
> + if (unlikely(check_storm)) {
> + if (!check_start) {
> + check_start = jiffies_to_msecs(jiffies);
Yuck. I had to read that twice to figure out that it's correct vs. the
truncation of the result to unsigned int. You can spare that conversion
by simply doing
unsigned long end_of_check = jiffies + HZ / 2;
and then the check becomes
time_before(jiffies, end_of_check)
> + } else if ((kstat_irqs(priv->irq) > 1000) &&
> +(jiffies_to_msecs(jiffies) - check_start < 500)) {
I assume you can't call disable_irq_nosync() here, but shouldn't this
shut up the interrupt at the TPM level right here?
> + check_storm = false;
> + schedule_work(>storm_work);
> + } else if (jiffies_to_msecs(jiffies) - check_start >= 500) {
> + check_storm = false;
> + }
> + }
So back to kstat_irqs(). As this needs two extra variables anyway:
init()
priv->irq_check = 1;
priv->end_check = 0;
isr()
if (unlikely(priv->irq_check)) {
if (!priv->end_check) {
priv->end_check = jiffies + HZ / 2;
} else if (time_before(jiffies, priv->end_check)) {
if (priv->irq_check++ > 1000)
schedule_work(...);
} else {
priv->irq_check = 0;
}
}
Hmm? I still need to see an argument for an kstat_irqs() export being
superior.
Though I wonder whether such an infrastructure should be provided in the
irq core. Let me think about it.
Just as a side note. I was looking at tpm_tis_probe_irq_single() and
that function is leaking the interrupt request if any of the checks
afterwards fails, except for the final interrupt probe check which does
a cleanup. That means on fail before that the interrupt handler stays
requested up to the point where the module is removed. If that's a
shared interrupt and some other device is active on the same line, then
each interrupt from that device will call into the TPM code. Something
like the below is needed.
Also the X86 autoprobe mechanism is interesting:
if (IS_ENABLED(CONFIG_X86))
for (i = 3; i <= 15; i++)
if (!tpm_tis_probe_irq_single(chip, intmask, 0, i))
return;
The third argument is 'flags' which is handed to request_irq(). So that
won't ever be able to probe a shared interrupt. But if an interrupt
number > 0 is handed to tpm_tis_core_init() the interrupt is requested
with IRQF_SHARED. Same issue when the chip has an interrupt number in
the register. It's also requested exclusive which is pretty likely
to fail on ancient x86 machines.
The vast amount of comments didn't help to figure out what the reasoning
is.
Thanks,
tglx
---
drivers/char/tpm/tpm_tis_core.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
--- a/drivers/char/tpm/tpm_tis_core.c
+++ b/drivers/char/tpm/tpm_tis_core.c
@@ -782,26 +782,26 @@ static int tpm_tis_probe_irq_single(stru
rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality),
_int_vec);
if (rc < 0)
- return rc;
+ goto fail;
rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), irq);
if (rc < 0)
- return rc;
+ goto fail;
rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), _status);
if (rc < 0)
- return rc;
+ goto fail;
/* Clear all existing */
rc = tpm_tis_write32(priv, TPM_INT_STATUS(priv->locality), int_status);
if (rc < 0)
- return rc;
+ goto fail;
/* Turn on */
rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality),
intmask | TPM_GLOBAL_INT_ENABLE);
if (rc < 0)
- return rc;
+ goto fail;
priv->irq_tested = false;
@@ -825,6 +825,10 @@ static int tpm_tis_probe_irq_single(stru
}
return 0;
+
+fail:
+ disable_interrupts(chip);
+ return rc;
}
/* Try to find the IRQ the TPM is using. This is for legacy x86 systems that
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Inject a failure into the initial modeset (rev3)
== Series Details == Series: drm/i915/display: Inject a failure into the initial modeset (rev3) URL : https://patchwork.freedesktop.org/series/84592/ State : success == Summary == CI Bug Log - changes from CI_DRM_9450_full -> Patchwork_19071_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9450_full and Patchwork_19071_full: ### New CI tests (1) ### * boot: - Statuses : 174 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19071_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] ([i915#155] / [i915#180] / [i915#2369]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-kbl6/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-kbl1/igt@gem_exec_susp...@basic-s3.html * igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding: - shard-skl: [PASS][3] -> [FAIL][4] ([i915#54]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2346]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-tglb2/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-tglb3/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#2346]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-skl3/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#49]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-apl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-apl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html - shard-glk: [PASS][11] -> [FAIL][12] ([i915#49]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-glk1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-glk9/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#49]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-kbl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][15] -> [INCOMPLETE][16] ([i915#155] / [i915#180]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-kbl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-kbl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-c-tiling-none: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#165] / [i915#180] / [i915#78]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-kbl6/igt@kms_plane_low...@pipe-c-tiling-none.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-kbl2/igt@kms_plane_low...@pipe-c-tiling-none.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/shard-iclb2/igt@kms_psr2...@frontbuffer.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/shard-iclb4/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]:
Re: [Intel-gfx] [PATCH v3 1/4] irq: export kstat_irqs
Jerry, On Fri, Dec 04 2020 at 18:43, Jerry Snitselaar wrote: The proper prefix is 'genirq:' git log kernel/irq/irqdesc.c would have told you. > To try and detect potential interrupt storms that > have been occurring with tpm_tis devices it was suggested > to use kstat_irqs() to get the number of interrupts. > Since tpm_tis can be built as a module it needs kstat_irqs > exported. I'm not really enthused about exporting this without making it at least safe. Using it from an interrupt handler is obviously safe vs. concurrent removal, but the next driver writer who thinks this is cool is going to get it wrong for sure. Though I still have to figure out what the advantage of invoking a function which needs to do a radix tree lookup over a device local counter is just to keep track of this. I'll reply on the TPM part of this as well. Thanks, tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/4] irq: export kstat_irqs
On Sun, 2020-12-06 at 17:40 +0100, Thomas Gleixner wrote: > On Sat, Dec 05 2020 at 12:39, Jarkko Sakkinen wrote: > > On Fri, Dec 04, 2020 at 06:43:37PM -0700, Jerry Snitselaar wrote: > > > To try and detect potential interrupt storms that > > > have been occurring with tpm_tis devices it was suggested > > > to use kstat_irqs() to get the number of interrupts. > > > Since tpm_tis can be built as a module it needs kstat_irqs > > > exported. > > > > I think you should also have a paragraph explicitly stating that > > i915_pmu.c contains a duplicate of kstat_irqs() because it is not > > exported as of today. It adds a lot more weight to this given that > > there is already existing mainline usage (kind of). > > It's abusage and just the fact that it exists is not an argument by > itself. What we want is a count of the interrupts to see if we're having an interrupt storm from the TPM device (some seem to be wired to fire the interrupt even when there's no event to warrant it). Since kstat_irqs_user() does the correct RCU locking, should we be using that instead? James ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/4] irq: export kstat_irqs
On Sat, Dec 05 2020 at 12:39, Jarkko Sakkinen wrote: > On Fri, Dec 04, 2020 at 06:43:37PM -0700, Jerry Snitselaar wrote: >> To try and detect potential interrupt storms that >> have been occurring with tpm_tis devices it was suggested >> to use kstat_irqs() to get the number of interrupts. >> Since tpm_tis can be built as a module it needs kstat_irqs >> exported. > > I think you should also have a paragraph explicitly stating that > i915_pmu.c contains a duplicate of kstat_irqs() because it is not > exported as of today. It adds a lot more weight to this given that > there is already existing mainline usage (kind of). It's abusage and just the fact that it exists is not an argument by itself. Thanks, tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/pmu: Use kstat_irqs to get interrupt count
On Fri, Dec 04 2020 at 18:43, Jerry Snitselaar wrote:
> Now that kstat_irqs is exported, get rid of count_interrupts in
> i915_pmu.c
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -423,22 +423,6 @@ static enum hrtimer_restart i915_sample(struct hrtimer
> *hrtimer)
> return HRTIMER_RESTART;
> }
>
> -static u64 count_interrupts(struct drm_i915_private *i915)
> -{
> - /* open-coded kstat_irqs() */
> - struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
> - u64 sum = 0;
> - int cpu;
> -
> - if (!desc || !desc->kstat_irqs)
> - return 0;
> -
> - for_each_possible_cpu(cpu)
> - sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
> -
> - return sum;
> -}
May I ask why this has been merged in the first place?
Nothing in a driver has ever to fiddle with the internals of an irq
descriptor. We have functions for properly accessing them. Just because
C allows to fiddle with everything is not a justification. If the
required function is not exported then adding the export with a proper
explanation is not asked too much.
Also this lacks protection or at least a comment why this can be called
safely and is not subject to a concurrent removal of the irq descriptor.
The same problem exists when calling kstat_irqs(). It's even documented
at the top of the function.
Thanks,
tglx
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Inject a failure into the initial modeset (rev3)
== Series Details == Series: drm/i915/display: Inject a failure into the initial modeset (rev3) URL : https://patchwork.freedesktop.org/series/84592/ State : success == Summary == CI Bug Log - changes from CI_DRM_9450 -> Patchwork_19071 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/index.html New tests - New tests have been introduced between CI_DRM_9450 and Patchwork_19071: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19071 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_module_load@reload: - fi-kbl-7500u: [PASS][5] -> [DMESG-WARN][6] ([i915#2605]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/fi-kbl-7500u/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/fi-kbl-7500u/igt@i915_module_l...@reload.html * igt@i915_selftest@live@coherency: - fi-gdg-551: [PASS][7] -> [DMESG-FAIL][8] ([i915#1748]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/fi-gdg-551/igt@i915_selftest@l...@coherency.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/fi-gdg-551/igt@i915_selftest@l...@coherency.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-snb-2600:[INCOMPLETE][9] -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9450/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9450 -> Patchwork_19071 CI-20190529: 20190529 CI_DRM_9450: 83b8d6ab0631ef13a095c7818d3c2c40f52f42ce @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19071: 8eb4f1621e6b6404be721797f0276964ec9d2553 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8eb4f1621e6b drm/i915/display: Inject a failure into the initial modeset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19071/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display: Inject a failure into the initial modeset
Experiment with how fault tolerant we are if the initial modeset fails
and we need to abort the driver load.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c567c0cada7e..875a7c1ddf08 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18495,8 +18495,12 @@ static int intel_initial_commit(struct drm_device *dev)
}
}
- ret = drm_atomic_commit(state);
+ if (i915_inject_probe_failure(to_i915(dev))) {
+ ret = -ENODEV;
+ goto out;
+ }
+ ret = drm_atomic_commit(state);
out:
if (ret == -EDEADLK) {
drm_atomic_state_clear(state);
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915/display: Inject a failure into the initial modeset
On Fri, 04 Dec 2020, Chris Wilson wrote:
> Experiment with how fault tolerant we are if the initial modeset fails
> and we need to abort the driver load.
>
> Suggested-by: Tvrtko Ursulin
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6e5b93f6a25e..86124b8d156d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18456,7 +18456,9 @@ static int intel_initial_commit(struct drm_device
> *dev)
> }
> }
>
> - ret = drm_atomic_commit(state);
> + ret = -ENODEV;
> + if (!i915_inject_probe_failure(to_i915(dev)))
> + ret = drm_atomic_commit(state);
If this is just for CI testing, fine. But for actual merging, please
don't hide the happy day scenario in the probe failure if branch.
BR,
Jani.
>
> out:
> if (ret == -EDEADLK) {
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [ANNOUNCE] upcoming mandated dim upgrade due to drm-intel branch change
On Mon, 30 Nov 2020, Jani Nikula wrote:
> TL;DR:
> - On 2020-12-05, drm-intel-next-queued will be decommissioned
> - drm-intel committers need to start using drm-intel-next instead
> - Everyone needs to upgrade dim *after* the change
This has now been done. Please update dim, and start using
drm-intel-next for applying i915 patches. Thank you.
BR,
Jani.
> Full story:
>
> For historical reasons, we've had separate drm-intel-next-queued
> ("dinq") and drm-intel-next ("din") branches for development and pull
> requests, respectively. This split has not been necessary for a while
> now, so we'll finally remove dinq, and start applying patches directly
> to drm-intel-next.
>
> We'll make the switch on 2020-12-05.
>
> This change requires a flag-day change in dim, i.e. everyone will need
> to upgrade dim *after* the switch. (The details of the flag-day change
> are covered in [1].)
>
> All the current dinq related commands and aliases (such as 'dim conq',
> 'dim aq', and 'dim pq') will continue to work, except they'll operate on
> drm-intel-next.
>
>
> BR,
> Jani.
>
>
> [1] http://marc.info/?i=20201113095658.16655-1-jani.nik...@intel.com
--
Jani Nikula, Intel Open Source Graphics Center
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