Re: [Intel-gfx] [PATCH v5] drm/i915/rkl: new rkl ddc map for different PCH
Hi,
Progress here seems to have stalled, or did I miss something?
On 20.11.2020 4.21, Lee, Shawn C wrote:
On Thu, Nov. 19, 2020 at 11:51 PM, Matt Roper wrote:
On Tue, Nov 17, 2020 at 10:26:29PM +0800, Lee Shawn C wrote:
After boot into kernel. Driver configured ddc pin mapping based on
predefined table in parse_ddi_port(). Now driver configure rkl ddc pin
mapping depends on icp_ddc_pin_map[]. Then this table will give
incorrect gmbus port number to cause HDMI can't work.
Refer to commit cd0a89527d06 ("drm/i915/rkl: Add DDC pin mapping").
Create two ddc pin table for rkl TGP and CMP pch. Then HDMI can works
properly on rkl.
v2: update patch based on latest dinq branch.
v3: update ddc table for RKL+TGP sku.
RKL+CNP sku will load cnp_ddc_pin_map[] setting.
v4: modify the if/else judgment to avoid nesting.
v5: fix typo in v4.
Cc: Matt Roper
Cc: Aditya Swarup
Cc: Anusha Srivatsa
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Khaled Almahallawy
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2577
Signed-off-by: Lee Shawn C
Reviewed-by: Matt Roper
Do you plan to follow up with a separate patch to fix the CMP handling in
rkl_port_to_ddc_pin that I mentioned previously? I want to make sure that part
doesn't fall through the cracks.
Do you mean the modification like this in rkl_port_to_ddc_pin()? If so, I will
commit a separate patch to fix it later.
return GMBUS_PIN_1_BXT + phy - 1;
Best regards,
Shawn
Matt
---
drivers/gpu/drm/i915/display/intel_bios.c | 10 ++
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4cc949b228f2..cf2fba490b7b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1623,6 +1623,13 @@ static const u8 icp_ddc_pin_map[] = {
[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, };
+static const u8 rkl_pch_tgp_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+ [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,
+ [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, };
+
static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
{
const u8 *ddc_pin_map;
@@ -1630,6 +1637,9 @@ static u8 map_ddc_pin(struct drm_i915_private
*dev_priv, u8 vbt_pin)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
return vbt_pin;
+ } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) ==
PCH_TGP) {
+ ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
ddc_pin_map = icp_ddc_pin_map;
n_entries = ARRAY_SIZE(icp_ddc_pin_map); diff --git
a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 49b4b5fca941..187ec573de59 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -319,6 +319,8 @@ enum vbt_gmbus_ddi {
ICL_DDC_BUS_DDI_A = 0x1,
ICL_DDC_BUS_DDI_B,
TGL_DDC_BUS_DDI_C,
+ RKL_DDC_BUS_DDI_D = 0x3,
+ RKL_DDC_BUS_DDI_E,
ICL_DDC_BUS_PORT_1 = 0x4,
ICL_DDC_BUS_PORT_2,
ICL_DDC_BUS_PORT_3,
--
2.17.1
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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t
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts from execlist submission
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85017/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9495_full -> Patchwork_19165_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19165_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19165_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19165_full:
### IGT changes ###
Possible regressions
* igt@api_intel_bb@blit-noreloc-purge-cache:
- shard-hsw: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/shard-hsw2/igt@api_intel...@blit-noreloc-purge-cache.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-hsw2/igt@api_intel...@blit-noreloc-purge-cache.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_schedule@u-fairslice-all}:
- shard-iclb: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/shard-iclb3/igt@gem_exec_sched...@u-fairslice-all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-iclb3/igt@gem_exec_sched...@u-fairslice-all.html
New tests
-
New tests have been introduced between CI_DRM_9495_full and
Patchwork_19165_full:
### New IGT tests (1) ###
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
- Statuses :
- Exec time: [None] s
Known issues
Here are the changes found in Patchwork_19165_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@drm_mm@all@color_evict:
- shard-skl: NOTRUN -> [INCOMPLETE][5] ([i915#2485])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-skl9/igt@drm_mm@all@color_evict.html
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#658])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/shard-iclb2/igt@feature_discov...@psr2.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-iclb1/igt@feature_discov...@psr2.html
* igt@gem_userptr_blits@process-exit-mmap@wb:
- shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1699]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-skl6/igt@gem_userptr_blits@process-exit-m...@wb.html
* igt@gen7_exec_parse@basic-allowed:
- shard-tglb: NOTRUN -> [SKIP][9] ([fdo#109289]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-tglb5/igt@gen7_exec_pa...@basic-allowed.html
* igt@gen9_exec_parse@allowed-all:
- shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([i915#1436] /
[i915#716])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/shard-kbl3/igt@gen9_exec_pa...@allowed-all.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-kbl3/igt@gen9_exec_pa...@allowed-all.html
* igt@gen9_exec_parse@secure-batches:
- shard-tglb: NOTRUN -> [SKIP][12] ([fdo#112306])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-tglb5/igt@gen9_exec_pa...@secure-batches.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271]) +18 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-apl2/igt@kms_big...@linear-16bpp-rotate-90.html
- shard-tglb: NOTRUN -> [SKIP][14] ([fdo#111614])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-tglb5/igt@kms_big...@linear-16bpp-rotate-90.html
* igt@kms_chamelium@dp-audio-edid:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109284] / [fdo#111827]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-tglb5/igt@kms_chamel...@dp-audio-edid.html
* igt@kms_chamelium@vga-hpd-enable-disable-mode:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-apl2/igt@kms_chamel...@vga-hpd-enable-disable-mode.html
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/shard-kbl7/igt@kms_chamel...@vga-hpd-enable-disable-mode.html
* igt@kms_color@pipe-b-ctm-green-to-red:
- shard-skl: [PASS][18] -> [DMESG-WARN][19]
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP component - Mesa single session (rev10)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev10) URL : https://patchwork.freedesktop.org/series/84620/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_types.h In file included from : ./drivers/gpu/drm/i915/pxp/intel_pxp_types.h:35:15: error: field ‘mutex’ has incomplete type struct mutex mutex; ^ drivers/gpu/drm/i915/Makefile:314: recipe for target 'drivers/gpu/drm/i915/pxp/intel_pxp_types.hdrtest' failed make[4]: *** [drivers/gpu/drm/i915/pxp/intel_pxp_types.hdrtest] Error 1 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1805: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v10 10/13] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = _pxp_ops;
+
[Intel-gfx] [RFC-v10 13/13] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah
Cc: Huang, Sean Z
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7e208816074..273bdc031e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include
#include
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -767,6 +769,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -803,6 +810,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -813,7 +821,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -889,8 +897,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e8dfe435ca8..0ea7e2a402ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7209,6 +7209,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
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[Intel-gfx] [RFC-v10 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Cc: Matthew Auld matthew.a...@intel.com
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 -
include/uapi/drm/i915_drm.h | 47 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af06c85e6ba7..3dbda949bf71 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1733,7 +1733,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 17a4636ee542..c53b13c02e59 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
>size, >handle);
}
+struct create_ext {
+struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ _data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6edcb2b6c708..e918ccc81c74 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size for the object.
+*
+
[Intel-gfx] [RFC-v10 09/13] drm/i915/pxp: Expose session state for display protection flip
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 8
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 884e9c367911..a36f73bae480 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -140,3 +140,12 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
pxp->current_events |= events;
schedule_work(>irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->gt.pxp.ctx.inited &&
+ i915->gt.pxp.ctx.flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index cdaa6ce6fdca..976baf9b08e3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -29,6 +29,8 @@ enum pxp_protection_modes {
PROTECTION_MODE_ALL
};
+struct drm_i915_private;
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
@@ -36,6 +38,7 @@ int i915_pxp_global_terminate_complete_callback(struct
intel_pxp *pxp);
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -58,6 +61,11 @@ static inline void intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
#endif
#endif /* __INTEL_PXP_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v10 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 24 -
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 -
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 7 ++
7 files changed, 140 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 9830342aa6f4..b92072554ab3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -14,6 +14,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -107,6 +108,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..1e8dfe435ca8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7944,6 +7944,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
@@ -7966,7 +7967,7 @@ enum {
#define GEN11_VECS0_VECS1_INTR_MASK_MMIO(0x1900d0)
#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
-#define GEN11_CRYPTO_RSVD_INTR_MASK_MMIO(0x1900f0)
+#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in
bit31-16 (Engine1 Interrupt Mask) */
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
#define ENGINE1_MASK REG_GENMASK(31, 16)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2203464c76bc..f1bcfdc716ec 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -14,6 +14,70 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>irq_lock);
+
+ intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16);
+}
+
+static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ int ret;
+
+ mutex_lock(>ctx.mutex);
+
+ pxp->ctx.global_state_attacked = true;
+
+ mutex_unlock(>ctx.mutex);
+
+ return ret;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_attacked) {
+ pxp->ctx.global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_arb_create_session(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to create arb
session\n");
+ goto end;
+ }
+ }
+end:
+ mutex_unlock(>ctx.mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>irq_lock);
+ events = fetch_and_zero(>current_events);
+ spin_unlock_irq(>irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(pxp);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(pxp);
+
+ spin_lock_irq(>irq_lock);
+ intel_pxp_write_irq_mask_reg(gt, 0);
+ spin_unlock_irq(>irq_lock);
+}
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -27,6 +91,12 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_tee_component_init(pxp);
+ INIT_WORK(>irq_work, intel_pxp_irq_work);
+
+ pxp->handled_irr =
[Intel-gfx] [RFC-v10 00/13] Introduce Intel PXP component - Mesa single session
PXP (Protected Xe Path) is an i915 componment, available on GEN12+ that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. This patch series is to allow the kernel space to create and manage a single hardware session (a.k.a default session or arbitrary session). So user can allocate the protected buffer, which is encrypted with the leverage of the arbitrary hardware session. v2: - modification based on code reivew feedbacks received - passing pxp instead of i915 as funciton argument - remove dead code only for multi-session - move the pxp init call from i915_drv.c to intel_gt.c - reove the tautology naming v3: - rebase to latest drm-tip v4: - Append the split non-mesa patch sereis (commit #14 - #21) into this patch series v5: - include "intel_pxp.h" in intel_pxp_sm.h at commit #14 to fix the build problem. v6: - Fix the null pointer arb_session access bug in intel_pxp_arb.c in "04 [RFC-v5] drm/i915/pxp: Create the arbitrary session after boot" v7: - Use list_for_each_entry_safe instead of list_for_each_entry v8: - Add MEI vtag support for PXP multi-session usage v9: - Fix error handling bug in commit #5 "Func to send hardware session termination". In intel_pxp_cmd.c, we should properly assign "err = PTR_ERR(x)" if hitting the error case "IS_ERR(x)", this is the only change in v9. v10 - Remove the multi session commits #14-#21, for now we would like to keep the multi session patches as downstream. - Adopt the code review suggestion from Wilson in commit #1 Reference links: WIP Vulkan: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8064 WIP Iris: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092 WIP Gallium bits: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8094 Anshuman Gupta (1): drm/i915/pxp: Add plane decryption support Bommu Krishnaiah (2): drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915/pxp: User interface for Protected buffer Huang, Sean Z (9): drm/i915/pxp: Introduce Intel PXP component drm/i915/pxp: set KCR reg init during the boot time drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Func to send hardware session termination drm/i915/pxp: Enable PXP irq worker and callback stub drm/i915/pxp: Destroy arb session upon teardown drm/i915/pxp: Enable PXP power management drm/i915/pxp: Expose session state for display protection flip Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Kconfig | 22 ++ drivers/gpu/drm/i915/Makefile | 9 + drivers/gpu/drm/i915/display/intel_sprite.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 + drivers/gpu/drm/i915/gt/intel_gt.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/i915_drv.c | 7 +- drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_gem.c | 63 +++- drivers/gpu/drm/i915/i915_reg.h | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 151 ++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 71 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 209 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 16 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 279 ++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 20 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 170 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 20 ++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 55 drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c| 230 +++ drivers/misc/mei/pxp/mei_pxp.h| 18 ++ include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 +++ include/uapi/drm/i915_drm.h | 66 + 37 files changed, 1680 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h create mode
[Intel-gfx] [RFC-v10 07/13] drm/i915/pxp: Destroy arb session upon teardown
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 130 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++-
5 files changed, 212 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index f1bcfdc716ec..884e9c367911 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct
intel_pxp *pxp)
mutex_lock(>ctx.mutex);
pxp->ctx.global_state_attacked = true;
+ pxp->ctx.flag_display_hm_surface_keys = false;
+
+ ret = intel_pxp_arb_terminate_session(pxp);
mutex_unlock(>ctx.mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
index d3da72969349..54a5d7c26e4b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -10,6 +10,7 @@
#include "intel_pxp_arb.h"
#include "intel_pxp.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_cmd.h"
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
@@ -131,3 +132,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
end:
return ret;
}
+
+static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to intel_pxp_cmd_submit()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_terminate_session - Terminate the arb hw session and its
entries.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be
protected by
+ * ctx.mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_arb_session_with_global_termination(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to
intel_pxp_arb_session_with_global_termination\n");
+ return ret;
+ }
+
+ arb->is_in_play = false;
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
index 1eb8db6deb0e..c1ed4ab176aa 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -11,5 +11,6 @@
struct intel_pxp;
int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index e86d914e7629..57eca04963a9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -5,13 +5,33 @@
#include "intel_pxp_cmd.h"
#include "i915_drv.h"
+#include "gt/intel_gpu_commands.h"
[Intel-gfx] [RFC-v10 12/13] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c7363036765a..12847edec751 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2019,12 +2019,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index b5c908f3f4f2..f991e882bbe0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, >user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, >user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 1449f54924e0..0917c9431c65 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -134,7 +134,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c53b13c02e59..611a0b5ab51f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, >base, );
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
[Intel-gfx] [RFC-v10 01/13] drm/i915/pxp: Introduce Intel PXP component
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
arbitrary session). So Mesa can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Kconfig | 22 +
drivers/gpu/drm/i915/Makefile| 5
drivers/gpu/drm/i915/gt/intel_gt.c | 4
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 24 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 25
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 21
9 files changed, 144 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..594775c11e19 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,28 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI
+ select INTEL_MEI_ME
+ select INTEL_MEI_TXE
+ select INTEL_MEI_PXP
+ default y
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
+ that helps to establish the hardware protected session and manage
+ the status of the alive software session, as well as its life cycle.
+
+ This patch series is to allow the kernel space to create and
+ manage a single hardware session (a.k.a default session or
+ arbitrary session). So Mesa can allocate the protected buffer,
+ which is encrypted with the leverage of the arbitrary hardware
+ session.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f9ef5199b124..53be29dbc07d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -255,6 +255,11 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 44f1d51e5ae5..d2448be36ded 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -18,6 +18,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_pxp_init(>pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -638,6 +641,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
if (vm) /* FIXME being called twice on error paths :( */
i915_vm_put(vm);
+ intel_pxp_fini(>pxp);
intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6d39a4a11bf3..caa3e1403945 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -120,6 +121,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..1e757efb7f5f
--- /dev/null
+++
[Intel-gfx] [RFC-v10 08/13] drm/i915/pxp: Enable PXP power management
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++
drivers/gpu/drm/i915/i915_drv.c| 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c| 65 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h| 31 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
6 files changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index abe52189986a..d419dfa4923d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -261,6 +261,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_arb.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 274aa0dd7050..09a64d0feafe 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -20,6 +20,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -241,6 +242,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>uc);
+ intel_pxp_pm_resume(>pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -275,6 +278,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>pxp);
intel_uc_suspend(>uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9299a456adb0..af06c85e6ba7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1344,6 +1346,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..ebe89262485c
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(>ctx.mutex);
+
+ /* Disable PXP-IOCTLs */
+ pxp->ctx.global_state_in_suspend = true;
+
+ mutex_unlock(>ctx.mutex);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ pxp->ctx.global_state_attacked = false;
+
+ pxp->ctx.flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(>ctx.mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!pxp->ctx.inited)
+ return 0;
+
+ mutex_lock(>ctx.mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (pxp->ctx.global_state_in_suspend) {
+ ret = intel_pxp_arb_terminate_session(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to terminate the arb
session\n");
+ goto end;
+ }
+
+ pxp->ctx.global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(>ctx.mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index ..135bfb59aaf7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void
[Intel-gfx] [RFC-v10 04/13] drm/i915/pxp: Create the arbitrary session after boot
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 133 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 15 +++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 38 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 6 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 26
9 files changed, 237 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 57447887d352..2c84f75b41da 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_arb.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 5a3461272fe9..2203464c76bc 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index f47bc6bea34f..8fc91e900b16 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,6 +8,22 @@
#include "intel_pxp_types.h"
+enum pxp_session_types {
+ SESSION_TYPE_TYPE0 = 0,
+ SESSION_TYPE_TYPE1 = 1,
+
+ SESSION_TYPE_MAX
+};
+
+enum pxp_protection_modes {
+ PROTECTION_MODE_NONE = 0,
+ PROTECTION_MODE_LM = 2,
+ PROTECTION_MODE_HM = 3,
+ PROTECTION_MODE_SM = 6,
+
+ PROTECTION_MODE_ALL
+};
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
new file mode 100644
index ..d3da72969349
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp_types.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
+
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
+#define ARB_PROTECTION_MODE PROTECTION_MODE_HM
+
+static bool is_hw_arb_session_in_play(struct intel_pxp *pxp)
+{
+ u32 regval_sip = 0;
+ intel_wakeref_t wakeref;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ with_intel_runtime_pm(>i915->runtime_pm, wakeref) {
+ regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ }
+
+ return regval_sip & BIT(ARB_SESSION_INDEX);
+}
+
+/* wait hw session_in_play reg to match the current sw state */
+static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (is_hw_arb_session_in_play(pxp) ==
+ arb->is_in_play) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+static void arb_session_entry_init(struct intel_pxp *pxp)
+{
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ arb->type = ARB_SESSION_TYPE;
+ arb->protection_mode = ARB_PROTECTION_MODE;
+ arb->index = ARB_SESSION_INDEX;
+ arb->is_in_play = false;
+}
+
+int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
+{
+ int ret;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ arb_session_entry_init(pxp);
+ ret = wait_arb_hw_sw_state(pxp);
+
+ return ret;
+}
+
+/**
+ *
[Intel-gfx] [RFC-v10 02/13] drm/i915/pxp: set KCR reg init during the boot time
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 1e757efb7f5f..cf22006222ce 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,12 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+/* KCR register definitions */
+#define KCR_INIT_MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -15,6 +21,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_ctx_init(>ctx);
+ intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
}
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v10 05/13] drm/i915/pxp: Func to send hardware session termination
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 159 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
3 files changed, 178 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2c84f75b41da..abe52189986a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -259,6 +259,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index ..e86d914e7629
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+struct intel_context *ce,
+struct intel_gt_buffer_pool_node *pool,
+u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>i915->drm, "Failed to %s, invalid
cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>i915->drm, "Failed to
i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (!HAS_ENGINE(gt, VCS0) ||
+ !gt->engine[VCS0]->kernel_context) {
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(>i915->drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ ce = gt->engine[VCS0]->kernel_context;
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_err(>i915->drm, "Failed to intel_engine_get_pool()\n");
+ err = PTR_ERR(pool);
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_err(>i915->drm, "Failed to
intel_pxp_cmd_get_batch()\n");
+ err = PTR_ERR(batch);
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_err(>i915->drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_err(>i915->drm, "Failed to
intel_context_create_request()\n");
+ err = PTR_ERR(rq);
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+
[Intel-gfx] [RFC-v10 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 132 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
8 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 53be29dbc07d..57447887d352 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..9299a456adb0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
mutex_init(_priv->wm.wm_mutex);
mutex_init(_priv->pps_mutex);
mutex_init(_priv->hdcp_comp_mutex);
+ mutex_init(_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c2d0156e8a5d..aaf452115c2f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1212,6 +1212,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index cf22006222ce..5a3461272fe9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
@@ -23,10 +24,14 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ intel_pxp_tee_component_init(pxp);
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
}
void intel_pxp_fini(struct intel_pxp *pxp)
{
+ intel_pxp_tee_component_fini(pxp);
+
intel_pxp_ctx_fini(>ctx);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..ca6b61099aee
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(>pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size,
true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in,
msg_in_size);
+ if (ret) {
+ drm_err(>drm, "Failed to send TEE message\n");
+ return -EFAULT;
+ }
+
+
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/cml : Add TGP PCH support
== Series Details == Series: drm/i915/cml : Add TGP PCH support URL : https://patchwork.freedesktop.org/series/85013/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9494_full -> Patchwork_19163_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19163_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19163_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19163_full: ### IGT changes ### Possible regressions * igt@kms_plane@plane-panning-top-left-pipe-c-planes: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-kbl3/igt@kms_pl...@plane-panning-top-left-pipe-c-planes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-kbl3/igt@kms_pl...@plane-panning-top-left-pipe-c-planes.html * igt@sysfs_timeslice_duration@timeout@rcs0: - shard-skl: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-skl7/igt@sysfs_timeslice_duration@time...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-skl7/igt@sysfs_timeslice_duration@time...@rcs0.html Known issues Here are the changes found in Patchwork_19163_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_mm@all@color_evict_range: - shard-skl: NOTRUN -> [INCOMPLETE][5] ([i915#198] / [i915#2485]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-skl5/igt@drm_mm@all@color_evict_range.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2389]) +5 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_mmap_gtt@coherency: - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#109292]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-iclb1/igt@gem_mmap_...@coherency.html * igt@gem_pwrite@basic-exhaustion: - shard-iclb: NOTRUN -> [WARN][8] ([i915#2658]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-iclb1/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@process-exit-mmap@wb: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1699]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-skl10/igt@gem_userptr_blits@process-exit-m...@wb.html * igt@i915_pm_rpm@pc8-residency: - shard-iclb: NOTRUN -> [SKIP][10] ([fdo#109293] / [fdo#109506]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-iclb1/igt@i915_pm_...@pc8-residency.html * igt@kms_color@pipe-b-ctm-green-to-red: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#129]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-skl3/igt@kms_co...@pipe-b-ctm-green-to-red.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-skl8/igt@kms_co...@pipe-b-ctm-green-to-red.html * igt@kms_color@pipe-c-ctm-0-75: - shard-skl: NOTRUN -> [DMESG-WARN][13] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-skl7/igt@kms_co...@pipe-c-ctm-0-75.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-iclb: NOTRUN -> [SKIP][14] ([fdo#109284] / [fdo#111827]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-iclb1/igt@kms_color_chamel...@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-skl7/igt@kms_color_chamel...@pipe-b-ctm-max.html * igt@kms_cursor_crc@pipe-b-cursor-128x42-random: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#54]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-128x42-random.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-128x42-random.html * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271]) +33 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/shard-skl7/igt@kms_cursor_edge_w...@pipe-d-128x128-right-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][19] -> [FAIL][20] ([i915#96]) [19]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Encode fence specific waitqueue behaviour into the wait.flags
== Series Details == Series: drm/i915: Encode fence specific waitqueue behaviour into the wait.flags URL : https://patchwork.freedesktop.org/series/85012/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9494_full -> Patchwork_19162_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19162_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19162_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19162_full: ### IGT changes ### Possible regressions * igt@kms_vblank@pipe-b-query-forked-busy-hang: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-hsw7/igt@kms_vbl...@pipe-b-query-forked-busy-hang.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-hsw4/igt@kms_vbl...@pipe-b-query-forked-busy-hang.html Known issues Here are the changes found in Patchwork_19162_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_mm@all@color_evict: - shard-skl: NOTRUN -> [INCOMPLETE][3] ([i915#2485]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-skl5/igt@drm_mm@all@color_evict.html * igt@gem_exec_gttfill@engines@rcs0: - shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#118] / [i915#95]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-glk5/igt@gem_exec_gttfill@engi...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-glk9/igt@gem_exec_gttfill@engi...@rcs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2389]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-iclb2/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_mmap_gtt@coherency: - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#109292]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-iclb2/igt@gem_mmap_...@coherency.html * igt@gem_pwrite@basic-exhaustion: - shard-iclb: NOTRUN -> [WARN][8] ([i915#2658]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-iclb2/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@process-exit-mmap@wb: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1699]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-skl10/igt@gem_userptr_blits@process-exit-m...@wb.html * igt@i915_pm_rpm@pc8-residency: - shard-iclb: NOTRUN -> [SKIP][10] ([fdo#109293] / [fdo#109506]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-iclb2/igt@i915_pm_...@pc8-residency.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-iclb: NOTRUN -> [SKIP][11] ([fdo#109284] / [fdo#111827]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-iclb2/igt@kms_color_chamel...@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-skl9/igt@kms_color_chamel...@pipe-b-ctm-max.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-skl2/igt@kms_cursor_...@pipe-c-cursor-128x42-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-skl4/igt@kms_cursor_...@pipe-c-cursor-128x42-sliding.html * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +33 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-skl9/igt@kms_cursor_edge_w...@pipe-d-128x128-right-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][16] -> [FAIL][17] ([i915#96]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-hsw2/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][18] -> [FAIL][19] ([i915#2370]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html [19]:
Re: [Intel-gfx] [RFC-v4 02/21] drm/i915/pxp: set KCR reg init during the boot time
Hi Wilson,
Thanks for bring up this. This is a necessary step during the booting to allow
the ME communicate with display but we don't need turn off for unload actually.
Best regards,
Sean
-Original Message-
From: Chris Wilson
Sent: Thursday, December 10, 2020 12:45 AM
To: Huang, Sean Z ; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v4 02/21] drm/i915/pxp: set KCR reg init during
the boot time
Quoting Huang, Sean Z (2020-12-10 07:24:16)
> Set the KCR init during the boot time, which is required by hardware,
> to allow us doing further protection operation such as sending
> commands to GPU or TEE.
>
> Signed-off-by: Huang, Sean Z
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index ba43b2c923c7..c4815950567d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,12 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
>
> +/* KCR register definitions */
> +#define KCR_INIT_MMIO(0x320f0)
> +#define KCR_INIT_MASK_SHIFT (16)
> +/* Setting KCR Init bit is required after system boot */ #define
> +KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
> +KCR_INIT_MASK_SHIFT))
> +
> int intel_pxp_init(struct intel_pxp *pxp) {
> struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> @@ -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> intel_pxp_ctx_init(>ctx);
>
> + intel_uncore_write(gt->uncore, KCR_INIT,
> + KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
So this looks dangerous to leave enabled after driver unload?
-Chris
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts from execlist submission
== Series Details == Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts from execlist submission URL : https://patchwork.freedesktop.org/series/85017/ State : success == Summary == CI Bug Log - changes from CI_DRM_9495 -> Patchwork_19165 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/index.html Known issues Here are the changes found in Patchwork_19165 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#142] / [i915#2405]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-byt-j1900/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/fi-byt-j1900/igt@i915_pm_...@module-reload.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][5] ([i915#2029] / [i915#2722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/fi-bdw-5557u/igt@run...@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][6] ([i915#1814]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/fi-byt-j1900/igt@run...@aborted.html Possible fixes * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 39) -- Missing(3): fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9495 -> Patchwork_19165 CI-20190529: 20190529 CI_DRM_9495: 2960e86fd8fd7659400d05f40a1e06d3a97b6987 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5905: 3d0934900bddeb7a68f1abab4cd05077f0609e32 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19165: ec652f702ec9bff7f02889bfcd1d1eb5c57c02d3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ec652f702ec9 drm/i915/gt: Provide a utility to create a scratch buffer d46ab2bc6044 drm/i915/gt: Split logical ring contexts from execlist submission == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19165/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts from execlist submission
== Series Details == Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts from execlist submission URL : https://patchwork.freedesktop.org/series/85017/ State : warning == Summary == $ dim checkpatch origin/drm-tip d46ab2bc6044 drm/i915/gt: Split logical ring contexts from execlist submission -:1796: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #1796: new file mode 100644 -:1827: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'count' - possible side-effects? #1827: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:27: +#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6))) -:1829: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #1829: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:29: +#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) -:1830: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #1830: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:30: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) -:1830: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #1830: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:30: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) -:1833: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #1833: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:33: +#define END(total_state_size) 0, (total_state_size) -:5792: WARNING:MEMORY_BARRIER: memory barrier without comment #5792: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:637: + wmb(); -:5821: WARNING:MEMORY_BARRIER: memory barrier without comment #5821: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:666: + wmb(); -:5953: WARNING:MEMORY_BARRIER: memory barrier without comment #5953: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:798: + wmb(); -:6501: WARNING:MEMORY_BARRIER: memory barrier without comment #6501: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:1346: + wmb(); -:6915: WARNING:LINE_SPACING: Missing a blank line after declarations #6915: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:1760: + struct i915_request *rq; + IGT_TIMEOUT(end_time); total: 2 errors, 6 warnings, 3 checks, 5222 lines checked ec652f702ec9 drm/i915/gt: Provide a utility to create a scratch buffer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/7] drm/i915/gt: Track all timelines created using the HWSP
== Series Details == Series: series starting with [CI,1/7] drm/i915/gt: Track all timelines created using the HWSP URL : https://patchwork.freedesktop.org/series/85007/ State : success == Summary == CI Bug Log - changes from CI_DRM_9494_full -> Patchwork_19161_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19161_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_mm@all@color_evict: - shard-skl: NOTRUN -> [INCOMPLETE][1] ([i915#2485]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-skl9/igt@drm_mm@all@color_evict.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][2] ([i915#2389]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-glk8/igt@gem_exec_whis...@basic-contexts-forked-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-glk3/igt@gem_exec_whis...@basic-contexts-forked-all.html * igt@gem_mmap_gtt@coherency: - shard-iclb: NOTRUN -> [SKIP][5] ([fdo#109292]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-iclb6/igt@gem_mmap_...@coherency.html * igt@gem_pwrite@basic-exhaustion: - shard-iclb: NOTRUN -> [WARN][6] ([i915#2658]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-iclb6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@process-exit-mmap@wb: - shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1699]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-skl8/igt@gem_userptr_blits@process-exit-m...@wb.html * igt@i915_pm_rpm@pc8-residency: - shard-iclb: NOTRUN -> [SKIP][8] ([fdo#109293] / [fdo#109506]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-iclb6/igt@i915_pm_...@pc8-residency.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2597]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-tglb7/igt@kms_async_fl...@test-time-stamp.html * igt@kms_color@pipe-b-ctm-green-to-red: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#129]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-skl3/igt@kms_co...@pipe-b-ctm-green-to-red.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-skl10/igt@kms_co...@pipe-b-ctm-green-to-red.html * igt@kms_color@pipe-c-ctm-0-75: - shard-skl: NOTRUN -> [DMESG-WARN][13] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-skl10/igt@kms_co...@pipe-c-ctm-0-75.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-iclb: NOTRUN -> [SKIP][14] ([fdo#109284] / [fdo#111827]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-iclb6/igt@kms_color_chamel...@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-skl10/igt@kms_color_chamel...@pipe-b-ctm-max.html * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271]) +33 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-skl10/igt@kms_cursor_edge_w...@pipe-d-128x128-right-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][17] -> [FAIL][18] ([i915#96]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109274] / [fdo#109278]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-iclb6/igt@kms_cursor_leg...@cursora-vs-flipb-toggle.html * igt@kms_cursor_legacy@pipe-d-single-move: - shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109278]) +3 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/shard-iclb6/igt@kms_cursor_leg...@pipe-d-single-move.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
[Intel-gfx] ✗ Fi.CI.IGT: failure for gpu/drm/i915: convert comma to semicolon
== Series Details == Series: gpu/drm/i915: convert comma to semicolon URL : https://patchwork.freedesktop.org/series/85006/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9494_full -> Patchwork_19160_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19160_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19160_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19160_full: ### IGT changes ### Possible regressions * igt@kms_vblank@pipe-b-query-forked-busy-hang: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-hsw7/igt@kms_vbl...@pipe-b-query-forked-busy-hang.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-hsw2/igt@kms_vbl...@pipe-b-query-forked-busy-hang.html Known issues Here are the changes found in Patchwork_19160_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_mm@all@color_evict_range: - shard-skl: NOTRUN -> [INCOMPLETE][3] ([i915#198] / [i915#2485]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-skl7/igt@drm_mm@all@color_evict_range.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][4] ([i915#2389]) +4 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_mmap_gtt@coherency: - shard-iclb: NOTRUN -> [SKIP][5] ([fdo#109292]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-iclb5/igt@gem_mmap_...@coherency.html * igt@gem_pwrite@basic-exhaustion: - shard-iclb: NOTRUN -> [WARN][6] ([i915#2658]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-iclb5/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@process-exit-mmap@wb: - shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1699]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-skl9/igt@gem_userptr_blits@process-exit-m...@wb.html * igt@i915_pm_rpm@pc8-residency: - shard-iclb: NOTRUN -> [SKIP][8] ([fdo#109293] / [fdo#109506]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-iclb5/igt@i915_pm_...@pc8-residency.html * igt@kms_ccs@pipe-c-ccs-on-another-bo: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111304]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-skl5/igt@kms_...@pipe-c-ccs-on-another-bo.html * igt@kms_color@pipe-a-ctm-negative: - shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-skl8/igt@kms_co...@pipe-a-ctm-negative.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-skl7/igt@kms_co...@pipe-a-ctm-negative.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-iclb: NOTRUN -> [SKIP][12] ([fdo#109284] / [fdo#111827]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-iclb5/igt@kms_color_chamel...@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-skl8/igt@kms_color_chamel...@pipe-b-ctm-max.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding: - shard-skl: [PASS][14] -> [FAIL][15] ([i915#54]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-256x85-sliding.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-256x85-sliding.html * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271]) +53 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-skl8/igt@kms_cursor_edge_w...@pipe-d-128x128-right-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][17] -> [FAIL][18] ([i915#96]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html *
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v7,1/5] drm: Add function to convert rect in 16.16 fixed format to regular format
== Series Details == Series: series starting with [v7,1/5] drm: Add function to convert rect in 16.16 fixed format to regular format URL : https://patchwork.freedesktop.org/series/85015/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9495 -> Patchwork_19164 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19164 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19164, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19164: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [PASS][1] -> [FAIL][2] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-tgl-y/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-tgl-u2: [PASS][3] -> [FAIL][4] +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-tgl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html Known issues Here are the changes found in Patchwork_19164 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][5] -> [FAIL][6] ([i915#1888]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html * igt@i915_module_load@reload: - fi-tgl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#402] / [k.org#205379]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-u2/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-tgl-u2/igt@i915_module_l...@reload.html * igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1: - fi-tgl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +12 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html * igt@kms_psr@primary_page_flip: - fi-tgl-u2: [PASS][11] -> [SKIP][12] ([i915#668]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-u2/igt@kms_psr@primary_page_flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-tgl-u2/igt@kms_psr@primary_page_flip.html * igt@prime_vgem@basic-read: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-y/igt@prime_v...@basic-read.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-tgl-y/igt@prime_v...@basic-read.html * igt@runner@aborted: - fi-kbl-r: NOTRUN -> [FAIL][15] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#2295] / [i915#2722]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-kbl-r/igt@run...@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][16] ([i915#2029] / [i915#2722]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9495/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19164/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2722]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v7,1/5] drm: Add function to convert rect in 16.16 fixed format to regular format
== Series Details == Series: series starting with [v7,1/5] drm: Add function to convert rect in 16.16 fixed format to regular format URL : https://patchwork.freedesktop.org/series/85015/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed:
[Intel-gfx] [CI 2/2] drm/i915/gt: Provide a utility to create a scratch buffer
Primarily used by selftests, but also by runtime debugging of engine
w/a, is a routine to create a temporarily bound buffer for readback.
Almagamate the duplicated routines into one.
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Chris Wilson
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 29 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 36 ++-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 30 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c| 24 +
drivers/gpu/drm/i915/gt/selftest_mocs.c | 29 +--
.../gpu/drm/i915/gt/selftest_workarounds.c| 11 +++---
7 files changed, 45 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 7bfe9072be9a..04aa6601e984 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -422,6 +422,35 @@ void setup_private_pat(struct intel_uncore *uncore)
bdw_setup_private_ppat(uncore);
}
+struct i915_vma *
+__vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(vm->i915, PAGE_ALIGN(size));
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0,
+ i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
+ if (err) {
+ i915_vma_put(vma);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_gtt.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 8a33940a71f3..29c10fde8ce3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -573,6 +573,9 @@ int i915_vm_pin_pt_stash(struct i915_address_space *vm,
void i915_vm_free_pt_stash(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash);
+struct i915_vma *
+__vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long
size);
+
static inline struct sgt_dma {
struct scatterlist *sg;
dma_addr_t dma, max;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 38868c5c038e..42d320e68b60 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2086,39 +2086,6 @@ void intel_engine_apply_workarounds(struct
intel_engine_cs *engine)
wa_list_apply(engine->uncore, >wa_list);
}
-static struct i915_vma *
-create_scratch(struct i915_address_space *vm, int count)
-{
- struct drm_i915_gem_object *obj;
- struct i915_vma *vma;
- unsigned int size;
- int err;
-
- size = round_up(count * sizeof(u32), PAGE_SIZE);
- obj = i915_gem_object_create_internal(vm->i915, size);
- if (IS_ERR(obj))
- return ERR_CAST(obj);
-
- i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
-
- vma = i915_vma_instance(obj, vm, NULL);
- if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto err_obj;
- }
-
- err = i915_vma_pin(vma, 0, 0,
- i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
- if (err)
- goto err_obj;
-
- return vma;
-
-err_obj:
- i915_gem_object_put(obj);
- return ERR_PTR(err);
-}
-
struct mcr_range {
u32 start;
u32 end;
@@ -2221,7 +2188,8 @@ static int engine_wa_list_verify(struct intel_context *ce,
if (!wal->count)
return 0;
- vma = create_scratch(>engine->gt->ggtt->vm, wal->count);
+ vma = __vm_create_scratch_for_read(>engine->gt->ggtt->vm,
+ wal->count * sizeof(u32));
if (IS_ERR(vma))
return PTR_ERR(vma);
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 34c2bb8313eb..7f2a6421f220 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -25,33 +25,6 @@
#define NUM_GPR 16
#define NUM_GPR_DW (NUM_GPR * 2) /* each GPR is 2 dwords */
-static struct i915_vma *create_scratch(struct intel_gt *gt)
-{
- struct drm_i915_gem_object *obj;
- struct i915_vma *vma;
- int err;
-
- obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
- if (IS_ERR(obj))
- return ERR_CAST(obj);
-
-
Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between misplaced vma check and vma insert
> -Original Message-
> From: Chris Wilson
> Sent: Wednesday, December 16, 2020 12:44 PM
> To: Tang, CQ ; intel-gfx@lists.freedesktop.org
> Cc: stable@
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between misplaced
> vma check and vma insert
>
> Quoting Tang, CQ (2020-12-16 17:27:40)
> >
> >
> > > -Original Message-
> > > From: Chris Wilson
> > > Sent: Wednesday, December 16, 2020 12:43 AM
> > > To: Tang, CQ ; intel-gfx@lists.freedesktop.org
> > > Cc: stable@
> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between
> > > misplaced vma check and vma insert
> > >
> > > Quoting Tang, CQ (2020-12-16 00:51:21)
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Chris Wilson
> > > > > Sent: Tuesday, December 15, 2020 2:02 PM
> > > > > To: Tang, CQ ;
> > > > > intel-gfx@lists.freedesktop.org
> > > > > Cc: stable@
> > > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between
> > > > > misplaced vma check and vma insert
> > > > >
> > > > > Quoting Tang, CQ (2020-12-15 21:50:53)
> > > > > >
> > > > > >
> > > > > > > -Original Message-
> > > > > > > From: Chris Wilson
> > > > > > > Sent: Tuesday, December 15, 2020 12:31 PM
> > > > > > > To: intel-gfx@lists.freedesktop.org
> > > > > > > Cc: Chris Wilson ; Tang, CQ
> > > > > > > ; sta...@vger.kernel.org
> > > > > > > Subject: [PATCH] drm/i915: Fix mismatch between misplaced
> > > > > > > vma check and vma insert
> > > > > > >
> > > > > > > When inserting a VMA, we restrict the placement to the low
> > > > > > > 4G unless the caller opts into using the full range. This
> > > > > > > was done to allow usersapce the opportunity to transition
> > > > > > > slowly from a 32b address space, and to avoid breaking
> > > > > > > inherent 32b assumptions of some
> > > > > commands.
> > > > > > >
> > > > > > > However, for insert we limited ourselves to 4G-4K, but on
> > > > > > > verification we allowed the full 4G. This causes some
> > > > > > > attempts to bind a new buffer to sporadically fail with
> > > > > > > -ENOSPC, but at other times be
> > > > > bound successfully.
> > > > > > >
> > > > > > > commit 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to
> > > 4GB
> > > > > > > - 1
> > > > > > > page") suggests that there is a genuine problem with
> > > > > > > stateless addressing that cannot utilize the last page in 4G
> > > > > > > and so we purposefully
> > > > > excluded it.
> > > > > > >
> > > > > > > Reported-by: CQ Tang
> > > > > > > Fixes: 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to
> > > > > > > 4GB
> > > > > > > - 1
> > > > > > > page")
> > > > > > > Signed-off-by: Chris Wilson
> > > > > > > Cc: CQ Tang
> > > > > > > Cc: sta...@vger.kernel.org
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
> > > > > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > > > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > > > index 193996144c84..2ff32daa50bd 100644
> > > > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > > > @@ -382,7 +382,7 @@ eb_vma_misplaced(const struct
> > > > > > > drm_i915_gem_exec_object2 *entry,
> > > > > > > return true;
> > > > > > >
> > > > > > > if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
> > > > > > > - (vma->node.start + vma->node.size - 1) >> 32)
> > > > > > > + (vma->node.start + vma->node.size + 4095) >> 32)
> > > > > >
> > > > > > Why 4095 not 4096?
> > > > >
> > > > > It's the nature of the test that we need an inclusive bound.
> > > > >
> > > > > Consider an object of size 4G - 4K, that is allowed to fit within our
> > > > > 32b
> GTT.
> > > > >
> > > > > 4G - 4k + 4K = 4G == 1 << 32: => vma misplaced
> > > > >
> > > > > 4G - 4k + 4k - 1 = 4G -1 = 0x => vma ok
> > > >
> > > > How do we trigger this code? I run
> > > > gem_exec_params@larger-than-life-
> > > batch but did not see this code is executed.
> > > > Basically how do we triggre first attempt to pin the object in place.
> > >
> > > It's the first pin tried, but the incoming execobj.offset must be
> > > available and the object itself must be ready to be pinned. That's
> > > true for the current tree on all current gen.
> >
> > For gem_exec_params@larger-than-life-batch subtest, I only see
> i915_vma_misplaced() be called when
> EXEC_OBJECT_SUPPORTS_48B_ADDRESS flags is specified, and the test
> passes.
> > I want to catch the bug before you fixed here. So a 4GB object should be
> OK, because before your fix, i915_vma_misplaced() returns false.
> > I did specify execobj.offset=0, but the driver code goes to
> i915_vma_insert() directly and return -ENOSPC.
> >
> > How do I make gem_exec_params@larger-than-life-batch code to catch
> this bug?
>
> Prior to the patch, upstream on current gen
Re: [Intel-gfx] [PATCH i-g-t] i915/gem_softpin: Check the last 32b page is excluded
Quoting Tang, CQ (2020-12-16 21:23:04)
>
>
> > -Original Message-
> > From: Chris Wilson
> > Sent: Wednesday, December 16, 2020 12:53 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Chris Wilson ; Tang, CQ
> > Subject: [PATCH i-g-t] i915/gem_softpin: Check the last 32b page is excluded
> >
> > In order to prevent issues with 32b stateless address, the last page under
> > 4G
> > is excluded for non-48b objects.
> >
> > Signed-off-by: Chris Wilson
> > Cc: CQ Tang
> > ---
> > tests/i915/gem_softpin.c | 37
> > +
> > 1 file changed, 37 insertions(+)
> >
> > diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c index
> > a3e6dcac3..703beb77d 100644
> > --- a/tests/i915/gem_softpin.c
> > +++ b/tests/i915/gem_softpin.c
> > @@ -156,6 +156,39 @@ static void test_zero(int i915)
> > gem_close(i915, object.handle);
> > }
> >
> > +static void test_32b_last_page(int i915) {
> > + uint64_t sz, gtt = gem_aperture_size(i915);
> > + struct drm_i915_gem_exec_object2 object = {
> > + .flags = EXEC_OBJECT_PINNED,
> > + };
> > + struct drm_i915_gem_execbuffer2 execbuf = {
> > + .buffers_ptr = to_user_pointer(),
> > + .buffer_count = 1,
> > + };
> > +
> > + /*
> > + * The last page under 32b is excluded for !48b objects in order to
> > + * prevent issues with stateless addressing.
> > + */
> > +
> > + igt_require(gtt >= 1ull << 32);
> > + object.handle = batch_create(i915, ),
>
> Where is this batch_create() version?
In upstream. Just the regular batch_create() but returning the allocated
size.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cml : Add TGP PCH support
== Series Details == Series: drm/i915/cml : Add TGP PCH support URL : https://patchwork.freedesktop.org/series/85013/ State : success == Summary == CI Bug Log - changes from CI_DRM_9494 -> Patchwork_19163 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/index.html Known issues Here are the changes found in Patchwork_19163 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +22 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#2283]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@gem_linear_blits@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-tgl-y/igt@gem_linear_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/fi-tgl-y/igt@gem_linear_bl...@basic.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][5] ([i915#2291] / [i915#541]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (42 -> 39) -- Missing(3): fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9494 -> Patchwork_19163 CI-20190529: 20190529 CI_DRM_9494: 0daa598dbcfd00141cb7e287d6e1369916097161 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5905: 3d0934900bddeb7a68f1abab4cd05077f0609e32 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19163: c38795c44db9a97d3d14189e885deabea81213fb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c38795c44db9 drm/i915/cml : Add TGP PCH support == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19163/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] i915/gem_softpin: Check the last 32b page is excluded
> -Original Message-
> From: Chris Wilson
> Sent: Wednesday, December 16, 2020 12:53 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson ; Tang, CQ
> Subject: [PATCH i-g-t] i915/gem_softpin: Check the last 32b page is excluded
>
> In order to prevent issues with 32b stateless address, the last page under 4G
> is excluded for non-48b objects.
>
> Signed-off-by: Chris Wilson
> Cc: CQ Tang
> ---
> tests/i915/gem_softpin.c | 37
> +
> 1 file changed, 37 insertions(+)
>
> diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c index
> a3e6dcac3..703beb77d 100644
> --- a/tests/i915/gem_softpin.c
> +++ b/tests/i915/gem_softpin.c
> @@ -156,6 +156,39 @@ static void test_zero(int i915)
> gem_close(i915, object.handle);
> }
>
> +static void test_32b_last_page(int i915) {
> + uint64_t sz, gtt = gem_aperture_size(i915);
> + struct drm_i915_gem_exec_object2 object = {
> + .flags = EXEC_OBJECT_PINNED,
> + };
> + struct drm_i915_gem_execbuffer2 execbuf = {
> + .buffers_ptr = to_user_pointer(),
> + .buffer_count = 1,
> + };
> +
> + /*
> + * The last page under 32b is excluded for !48b objects in order to
> + * prevent issues with stateless addressing.
> + */
> +
> + igt_require(gtt >= 1ull << 32);
> + object.handle = batch_create(i915, ),
Where is this batch_create() version?
--CQ
> +
> + object.offset = 1ull << 32;
> + object.offset -= sz;
> + igt_assert_f(__gem_execbuf(i915, ) == -EINVAL,
> + "execbuf succeeded with object.offset=%llx
> + %"PRIx64"\n",
> + object.offset, sz);
> +
> + object.offset -= 4096;
> + igt_assert_f(__gem_execbuf(i915, ) == 0,
> + "execbuf failed with object.offset=%llx + %"PRIx64"\n",
> + object.offset, sz);
> +
> + gem_close(i915, object.handle);
> +}
> +
> static void test_softpin(int fd)
> {
> const uint32_t size = 1024 * 1024;
> @@ -622,6 +655,10 @@ igt_main
> igt_require(gem_uses_full_ppgtt(fd));
> test_zero(fd);
> }
> + igt_subtest("32b-excludes-last-page") {
> + igt_require(gem_uses_full_ppgtt(fd));
> + test_32b_last_page(fd);
> + }
> igt_subtest("softpin")
> test_softpin(fd);
> igt_subtest("overlap")
> --
> 2.29.2
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[Intel-gfx] [PATCH i-g-t] i915/gem_softpin: Check the last 32b page is excluded
In order to prevent issues with 32b stateless address, the last page
under 4G is excluded for non-48b objects.
Signed-off-by: Chris Wilson
Cc: CQ Tang
---
tests/i915/gem_softpin.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
index a3e6dcac3..703beb77d 100644
--- a/tests/i915/gem_softpin.c
+++ b/tests/i915/gem_softpin.c
@@ -156,6 +156,39 @@ static void test_zero(int i915)
gem_close(i915, object.handle);
}
+static void test_32b_last_page(int i915)
+{
+ uint64_t sz, gtt = gem_aperture_size(i915);
+ struct drm_i915_gem_exec_object2 object = {
+ .flags = EXEC_OBJECT_PINNED,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(),
+ .buffer_count = 1,
+ };
+
+ /*
+* The last page under 32b is excluded for !48b objects in order to
+* prevent issues with stateless addressing.
+*/
+
+ igt_require(gtt >= 1ull << 32);
+ object.handle = batch_create(i915, ),
+
+ object.offset = 1ull << 32;
+ object.offset -= sz;
+ igt_assert_f(__gem_execbuf(i915, ) == -EINVAL,
+"execbuf succeeded with object.offset=%llx + %"PRIx64"\n",
+object.offset, sz);
+
+ object.offset -= 4096;
+ igt_assert_f(__gem_execbuf(i915, ) == 0,
+"execbuf failed with object.offset=%llx + %"PRIx64"\n",
+object.offset, sz);
+
+ gem_close(i915, object.handle);
+}
+
static void test_softpin(int fd)
{
const uint32_t size = 1024 * 1024;
@@ -622,6 +655,10 @@ igt_main
igt_require(gem_uses_full_ppgtt(fd));
test_zero(fd);
}
+ igt_subtest("32b-excludes-last-page") {
+ igt_require(gem_uses_full_ppgtt(fd));
+ test_32b_last_page(fd);
+ }
igt_subtest("softpin")
test_softpin(fd);
igt_subtest("overlap")
--
2.29.2
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Encode fence specific waitqueue behaviour into the wait.flags
== Series Details == Series: drm/i915: Encode fence specific waitqueue behaviour into the wait.flags URL : https://patchwork.freedesktop.org/series/85012/ State : success == Summary == CI Bug Log - changes from CI_DRM_9494 -> Patchwork_19162 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/index.html Known issues Here are the changes found in Patchwork_19162 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +22 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/fi-apl-guc/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][3] ([i915#2283]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@i915_selftest@live@gt_heartbeat: - fi-bsw-kefka: [PASS][4] -> [DMESG-FAIL][5] ([i915#2675] / [i915#541]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html * igt@prime_vgem@basic-read: - fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-tgl-y/igt@prime_v...@basic-read.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/fi-tgl-y/igt@prime_v...@basic-read.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][8] ([i915#2291] / [i915#541]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_timelines: - fi-apl-guc: [INCOMPLETE][10] ([i915#2750]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][12] ([i915#402]) -> [PASS][13] +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html Warnings * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: [DMESG-FAIL][14] ([i915#1886] / [i915#2291]) -> [DMESG-FAIL][15] ([i915#2291]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2675]: https://gitlab.freedesktop.org/drm/intel/issues/2675 [i915#2750]: https://gitlab.freedesktop.org/drm/intel/issues/2750 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (42 -> 39) -- Missing(3): fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9494 -> Patchwork_19162 CI-20190529: 20190529 CI_DRM_9494: 0daa598dbcfd00141cb7e287d6e1369916097161 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5905: 3d0934900bddeb7a68f1abab4cd05077f0609e32 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19162: 34feaeddc57f385045e4d85f870ff38c30b45c2e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 34feaeddc57f drm/i915: Encode fence specific waitqueue behaviour into the wait.flags == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19162/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between misplaced vma check and vma insert
Quoting Tang, CQ (2020-12-16 17:27:40)
>
>
> > -Original Message-
> > From: Chris Wilson
> > Sent: Wednesday, December 16, 2020 12:43 AM
> > To: Tang, CQ ; intel-gfx@lists.freedesktop.org
> > Cc: stable@
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between misplaced
> > vma check and vma insert
> >
> > Quoting Tang, CQ (2020-12-16 00:51:21)
> > >
> > >
> > > > -Original Message-
> > > > From: Chris Wilson
> > > > Sent: Tuesday, December 15, 2020 2:02 PM
> > > > To: Tang, CQ ; intel-gfx@lists.freedesktop.org
> > > > Cc: stable@
> > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between
> > > > misplaced vma check and vma insert
> > > >
> > > > Quoting Tang, CQ (2020-12-15 21:50:53)
> > > > >
> > > > >
> > > > > > -Original Message-
> > > > > > From: Chris Wilson
> > > > > > Sent: Tuesday, December 15, 2020 12:31 PM
> > > > > > To: intel-gfx@lists.freedesktop.org
> > > > > > Cc: Chris Wilson ; Tang, CQ
> > > > > > ; sta...@vger.kernel.org
> > > > > > Subject: [PATCH] drm/i915: Fix mismatch between misplaced vma
> > > > > > check and vma insert
> > > > > >
> > > > > > When inserting a VMA, we restrict the placement to the low 4G
> > > > > > unless the caller opts into using the full range. This was done
> > > > > > to allow usersapce the opportunity to transition slowly from a
> > > > > > 32b address space, and to avoid breaking inherent 32b
> > > > > > assumptions of some
> > > > commands.
> > > > > >
> > > > > > However, for insert we limited ourselves to 4G-4K, but on
> > > > > > verification we allowed the full 4G. This causes some attempts
> > > > > > to bind a new buffer to sporadically fail with -ENOSPC, but at
> > > > > > other times be
> > > > bound successfully.
> > > > > >
> > > > > > commit 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to
> > 4GB
> > > > > > - 1
> > > > > > page") suggests that there is a genuine problem with stateless
> > > > > > addressing that cannot utilize the last page in 4G and so we
> > > > > > purposefully
> > > > excluded it.
> > > > > >
> > > > > > Reported-by: CQ Tang
> > > > > > Fixes: 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to 4GB
> > > > > > - 1
> > > > > > page")
> > > > > > Signed-off-by: Chris Wilson
> > > > > > Cc: CQ Tang
> > > > > > Cc: sta...@vger.kernel.org
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
> > > > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > > index 193996144c84..2ff32daa50bd 100644
> > > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > > @@ -382,7 +382,7 @@ eb_vma_misplaced(const struct
> > > > > > drm_i915_gem_exec_object2 *entry,
> > > > > > return true;
> > > > > >
> > > > > > if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
> > > > > > - (vma->node.start + vma->node.size - 1) >> 32)
> > > > > > + (vma->node.start + vma->node.size + 4095) >> 32)
> > > > >
> > > > > Why 4095 not 4096?
> > > >
> > > > It's the nature of the test that we need an inclusive bound.
> > > >
> > > > Consider an object of size 4G - 4K, that is allowed to fit within our
> > > > 32b GTT.
> > > >
> > > > 4G - 4k + 4K = 4G == 1 << 32: => vma misplaced
> > > >
> > > > 4G - 4k + 4k - 1 = 4G -1 = 0x => vma ok
> > >
> > > How do we trigger this code? I run gem_exec_params@larger-than-life-
> > batch but did not see this code is executed.
> > > Basically how do we triggre first attempt to pin the object in place.
> >
> > It's the first pin tried, but the incoming execobj.offset must be available
> > and
> > the object itself must be ready to be pinned. That's true for the current
> > tree
> > on all current gen.
>
> For gem_exec_params@larger-than-life-batch subtest, I only see
> i915_vma_misplaced() be called when EXEC_OBJECT_SUPPORTS_48B_ADDRESS flags is
> specified, and the test passes.
> I want to catch the bug before you fixed here. So a 4GB object should be OK,
> because before your fix, i915_vma_misplaced() returns false.
> I did specify execobj.offset=0, but the driver code goes to i915_vma_insert()
> directly and return -ENOSPC.
>
> How do I make gem_exec_params@larger-than-life-batch code to catch this bug?
Prior to the patch, upstream on current gen would always take the fast
pin and hit the bug. It will only fail to take that path if it was not
_allowed_ to place the object at offset 0.
To explicitly test that the page is excluded we would use softpin.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/7] drm/i915/gt: Track all timelines created using the HWSP
== Series Details == Series: series starting with [CI,1/7] drm/i915/gt: Track all timelines created using the HWSP URL : https://patchwork.freedesktop.org/series/85007/ State : success == Summary == CI Bug Log - changes from CI_DRM_9494 -> Patchwork_19161 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/index.html Known issues Here are the changes found in Patchwork_19161 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/fi-apl-guc/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@vgem_basic@setversion: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-tgl-y/igt@vgem_ba...@setversion.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/fi-tgl-y/igt@vgem_ba...@setversion.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][4] ([i915#2291] / [i915#541]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_timelines: - fi-apl-guc: [INCOMPLETE][6] ([i915#2750]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2750]: https://gitlab.freedesktop.org/drm/intel/issues/2750 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (42 -> 39) -- Missing(3): fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9494 -> Patchwork_19161 CI-20190529: 20190529 CI_DRM_9494: 0daa598dbcfd00141cb7e287d6e1369916097161 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5905: 3d0934900bddeb7a68f1abab4cd05077f0609e32 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19161: feb9c04ce7cdaf8a4c4475f74167c2ea7e76634e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == feb9c04ce7cd drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines d22bc6bd4011 drm/i915/selftests: Exercise relative timeline modes 36ecd1f81c1a drm/i915/gt: Use indices for writing into relative timelines dd6032fbd46a drm/i915/gt: Add timeline "mode" f6911f320266 drm/i915/gt: Track timeline GGTT offset separately from subpage offset 34fe65da7be6 drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb d259a1a43369 drm/i915/gt: Track all timelines created using the HWSP == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19161/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/7] drm/i915/gt: Track all timelines created using the HWSP
== Series Details == Series: series starting with [CI,1/7] drm/i915/gt: Track all timelines created using the HWSP URL : https://patchwork.freedesktop.org/series/85007/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1449:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1503:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
[Intel-gfx] ✓ Fi.CI.BAT: success for gpu/drm/i915: convert comma to semicolon
== Series Details == Series: gpu/drm/i915: convert comma to semicolon URL : https://patchwork.freedesktop.org/series/85006/ State : success == Summary == CI Bug Log - changes from CI_DRM_9494 -> Patchwork_19160 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/index.html Known issues Here are the changes found in Patchwork_19160 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +22 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/fi-apl-guc/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][3] ([i915#2283]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@debugfs_test@read_all_entries: - fi-apl-guc: [PASS][4] -> [DMESG-WARN][5] ([i915#62]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-apl-guc/igt@debugfs_test@read_all_entries.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/fi-apl-guc/igt@debugfs_test@read_all_entries.html * igt@gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][6] -> [DMESG-WARN][7] ([i915#180] / [i915#62]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html * igt@vgem_basic@create: - fi-tgl-y: [PASS][8] -> [DMESG-WARN][9] ([i915#402]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-tgl-y/igt@vgem_ba...@create.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/fi-tgl-y/igt@vgem_ba...@create.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][10] ([i915#2291] / [i915#541]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_timelines: - fi-apl-guc: [INCOMPLETE][12] ([i915#2750]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9494/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2750]: https://gitlab.freedesktop.org/drm/intel/issues/2750 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (42 -> 39) -- Missing(3): fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9494 -> Patchwork_19160 CI-20190529: 20190529 CI_DRM_9494: 0daa598dbcfd00141cb7e287d6e1369916097161 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5905: 3d0934900bddeb7a68f1abab4cd05077f0609e32 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19160: f7d323039f460825dd44fb183c09384ccd7f15ed @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f7d323039f46 gpu/drm/i915: convert comma to semicolon == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19160/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 15/15] drm/i915/display: Let PCON convert from RGB to YUV if it can
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, December 16, 2020 5:01 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Sharma, Swati2
>
> Subject: [PATCH v6 15/15] drm/i915/display: Let PCON convert from RGB to YUV
> if it can
>
> If PCON has capability to convert RGB->YUV colorspace and also to 444->420
> downsampling then for any YUV420 only mode, we can let the PCON do all the
> conversion.
>
> v2: As suggested by Uma Shankar, considered case for colorspace
> BT709 and BT2020, and default to BT609. Also appended dir 'display' in commit
> message.
>
> v3: Fixed typo in condition for printing one of the error msg.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 68 +++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
> 4 files changed, 58 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index fbc07a93504b..17eaa56c5a99 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3644,6 +3644,7 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> if (!is_mst)
> intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
>
> + intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
> /*
>* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
> @@ -3731,7 +3732,7 @@ static void hsw_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> if (!is_mst)
> intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
> - intel_dp_configure_protocol_converter(intel_dp);
> + intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> true);
> intel_dp_sink_set_fec_ready(intel_dp, crtc_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 4c01c7c23dfd..2009ae9e9678 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1460,6 +1460,7 @@ struct intel_dp {
> int pcon_max_frl_bw;
> u8 max_bpc;
> bool ycbcr_444_to_420;
> + bool rgb_to_ycbcr;
> } dfp;
>
> /* Display stream compression testing */ diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index abc9b772d1c8..366b2e4e7f4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -651,6 +651,10 @@ intel_dp_output_format(struct drm_connector
> *connector,
> !drm_mode_is_420_only(info, mode))
> return INTEL_OUTPUT_FORMAT_RGB;
>
> + if (intel_dp->dfp.rgb_to_ycbcr &&
> + intel_dp->dfp.ycbcr_444_to_420)
> + return INTEL_OUTPUT_FORMAT_RGB;
> +
> if (intel_dp->dfp.ycbcr_444_to_420)
> return INTEL_OUTPUT_FORMAT_YCBCR444;
> else
> @@ -4311,7 +4315,8 @@ static void intel_dp_enable_port(struct intel_dp
> *intel_dp,
> intel_de_posting_read(dev_priv, intel_dp->output_reg); }
>
> -void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp)
> +void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
> +const struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> u8 tmp;
> @@ -4338,14 +4343,34 @@ void intel_dp_configure_protocol_converter(struct
> intel_dp *intel_dp)
> drm_dbg_kms(>drm,
> "Failed to set protocol converter YCbCr 4:2:0
> conversion mode to %s\n",
> enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
> -
> - tmp = 0;
> -
> - if (drm_dp_dpcd_writeb(_dp->aux,
> -DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0)
> + if (intel_dp->dfp.rgb_to_ycbcr) {
> + bool bt2020, bt709;
> +
> + bt2020 =
> drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
> + intel_dp-
> >downstream_ports,
> +
> DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
Next line should match the parenthesis, seems off.
> + bt709 =
> drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
> + intel_dp-
> >downstream_ports,
> +
>
Re: [Intel-gfx] [PATCH v5 07/15] drm/dp_helper: Add helpers to configure PCONs RGB-YCbCr Conversion
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, December 16, 2020 11:01 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Sharma, Swati2
>
> Subject: [PATCH v5 07/15] drm/dp_helper: Add helpers to configure PCONs RGB-
> YCbCr Conversion
>
> DP Specification for DP2.0 to HDMI2.1 Pcon specifies support for conversion of
> colorspace from RGB to YCbCr.
> https://groups.vesa.org/wg/DP/document/previewpdf/15651
>
> This patch adds the relavant registers and helper functions to get the
> capability
> and set the color conversion bits for rgb->ycbcr conversion through PCON.
>
> v2: As suggested in review comments:
> -Fixed bug in the check condition in a drm_helper as reported by Dan
> Carpenter
> and Kernel test robot. (Dan Carepenter) -Modified the color-conversion cap
> helper function, to accomodate
> BT709 and BT2020 colorspace. (Uma Shankar) -Added spec details for the new
> cap for color conversion. (Uma Shankar)
Looks Good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/drm_dp_helper.c | 61 +
> include/drm/drm_dp_helper.h | 19 +-
> 2 files changed, 79 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c index 689fd0d5f6c5..9abd65c694ab 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -949,6 +949,38 @@ bool
> drm_dp_downstream_444_to_420_conversion(const u8
> dpcd[DP_RECEIVER_CAP_SIZE] }
> EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
>
> +/**
> + * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream
> facing port
> + * RGB->YCbCr conversion
> capability
> + * @dpcd: DisplayPort configuration data
> + * @port_cap: downstream facing port capabilities
> + * @colorspc: Colorspace for which conversion cap is sought
> + *
> + * Returns: whether the downstream facing port can convert RGB->YCbCr
> +for a given
> + * colorspace.
> + */
> +bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> +const u8 port_cap[4],
> +u8 color_spc)
> +{
> + if (!drm_dp_is_branch(dpcd))
> + return false;
> +
> + if (dpcd[DP_DPCD_REV] < 0x13)
> + return false;
> +
> + switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
> + case DP_DS_PORT_TYPE_HDMI:
> + if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
> + return false;
> +
> + return port_cap[3] & color_spc;
> + default:
> + return false;
> + }
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
> +
> /**
> * drm_dp_downstream_mode() - return a mode for downstream facing port
> * @dev: DRM device
> @@ -3101,3 +3133,32 @@ int drm_dp_pcon_pps_override_param(struct
> drm_dp_aux *aux, u8 pps_param[6])
> return 0;
> }
> EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
> +
> +/*
> + * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert
> +RGB to Ycbcr
> + * @aux: displayPort AUX channel
> + * @color_spc: Color-space/s for which conversion is to be enabled, 0 for
> disable.
> + *
> + * Returns 0 on success, else returns negative error code.
> + */
> +int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8
> +color_spc) {
> + int ret;
> + u8 buf;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2,
> );
> + if (ret < 0)
> + return ret;
> +
> + if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
> + buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
> + else
> + buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
> +
> + ret = drm_dp_dpcd_writeb(aux,
> DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> baad87fe6b0a..e096ee98842b 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -432,6 +432,17 @@ struct drm_device;
> # define DP_DS_HDMI_YCBCR444_TO_422_CONV(1 << 3)
> # define DP_DS_HDMI_YCBCR444_TO_420_CONV(1 << 4)
>
> +/*
> + * VESA DP-to-HDMI PCON Specification adds caps for colorspace
> + * conversion in DFP cap DPCD 83h. Sec6.1 Table-3.
> + * Based on the available support the source can enable
> + * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2
> + * DPCD 3052h.
> + */
> +# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV(1 << 5)
> +# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV(1 << 6)
> +# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)
> +
[Intel-gfx] [PATCH v7 5/5] HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing
Enabling it to check if it causes regressions in CI but the feature is still not ready to be enabled by default. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 330c03e2b4f7..b8b19270c339 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,7 +54,7 @@ struct drm_printer; param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0600) \ - param(bool, enable_psr2_sel_fetch, false, 0600) \ + param(bool, enable_psr2_sel_fetch, true, 0600) \ param(int, disable_power_well, -1, 0400) \ param(int, enable_ips, 1, 0600) \ param(int, invert_brightness, 0, 0600) \ -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 4/5] drm/i915/display/psr: Program plane's calculated offset to plane SF register
It programs Plane's calculated x, y, offset to Plane SF register. It does the calculation of x and y offsets using skl_calc_main_surface_offset(). v3: Update commit message Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun Tested-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4bed18422c8a..ce74781b5a9a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1186,7 +1186,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; const struct drm_rect *clip; - u32 val; + u32 val, offset; + int ret, x, y; if (!crtc_state->enable_psr2_sel_fetch) return; @@ -1203,9 +1204,14 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, val |= plane_state->uapi.dst.x1; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); - /* TODO: consider tiling and auxiliary surfaces */ - val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16; - val |= plane_state->color_plane[color_plane].x; + /* TODO: consider auxiliary surfaces */ + x = plane_state->uapi.src.x1 >> 16; + y = (plane_state->uapi.src.y1 >> 16) + clip->y1; + ret = skl_calc_main_surface_offset(plane_state, , , ); + if (ret) + drm_warn_once(_priv->drm, "skl_calc_main_surface_offset() returned %i\n", + ret); + val = y << 16 | x; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), val); -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 2/5] drm/i915/display/psr: Use plane damage clips to calculate damaged area
Now using plane damage clips property to calcualte the damaged area.
Selective fetch only supports one region to be fetched so software
needs to calculate a bounding box around all damage clips.
Now that we are not complete fetching each plane, there is another
loop needed as all the plane areas that intersect with the pipe
damaged area needs to be fetched from memory so the complete blending
of all planes can happen.
v2:
- do not shifthing new_plane_state->uapi.dst only src is in 16.16 format
v4:
- setting plane selective fetch area using the whole pipe damage area
- mark the whole plane area damaged if plane visibility or alpha
changed
v5:
- taking in consideration src.y1 in the damage coordinates
- adding to the pipe damaged area planes that were visible but are
invisible in the new state
v6:
- consider old state plane coordinates when visibility changes or it
moved to calculate damaged area
- remove from damaged area the portion not in src clip
v7:
- intersec every damage clip with src to minimize damaged area
Cc: Ville Syrjälä
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 101 ---
1 file changed, 89 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d9a395c486d3..4bed18422c8a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1269,8 +1269,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state
*state,
struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 =
-1 };
struct intel_plane_state *new_plane_state, *old_plane_state;
- struct drm_rect pipe_clip = { .y1 = -1 };
struct intel_plane *plane;
bool full_update = false;
int i, ret;
@@ -1282,9 +1282,17 @@ int intel_psr2_sel_fetch_update(struct
intel_atomic_state *state,
if (ret)
return ret;
+ /*
+* Calculate minimal selective fetch area of each plane and calculate
+* the pipe damaged area.
+* In the next loop the plane selective fetch area will actually be set
+* using whole pipe damaged area.
+*/
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
new_plane_state, i) {
- struct drm_rect *sel_fetch_area, temp;
+ struct drm_rect src, damaged_area = { .y1 = -1 };
+ struct drm_mode_rect *damaged_clips;
+ u32 num_clips, j;
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
continue;
@@ -1300,23 +1308,92 @@ int intel_psr2_sel_fetch_update(struct
intel_atomic_state *state,
break;
}
- if (!new_plane_state->uapi.visible)
- continue;
+ drm_rect_fp_to_int(, _plane_state->uapi.src);
+ damaged_clips =
drm_plane_get_damage_clips(_plane_state->uapi);
+ num_clips =
drm_plane_get_damage_clips_count(_plane_state->uapi);
/*
-* For now doing a selective fetch in the whole plane area,
-* optimizations will come in the future.
+* If visibility or plane moved, mark the whole plane area as
+* damaged as it needs to be complete redraw in the new and old
+* position.
*/
+ if (new_plane_state->uapi.visible !=
old_plane_state->uapi.visible ||
+ !drm_rect_equals(_plane_state->uapi.dst,
+_plane_state->uapi.dst)) {
+ damaged_area.y1 = old_plane_state->uapi.src.y1 >> 16;
+ damaged_area.y1 = old_plane_state->uapi.src.y2 >> 16;
+ damaged_area.y1 += old_plane_state->uapi.dst.y1;
+ damaged_area.y2 += old_plane_state->uapi.dst.y1;
+ clip_area_update(_clip, _area);
+
+ num_clips = 0;
+ damaged_area.y1 = src.y1;
+ damaged_area.y2 = src.y2;
+ } else if (new_plane_state->uapi.alpha !=
old_plane_state->uapi.alpha) {
+ num_clips = 0;
+ damaged_area.y1 = src.y1;
+ damaged_area.y2 = src.y2;
+ } else if (!num_clips &&
+ new_plane_state->uapi.fb !=
old_plane_state->uapi.fb) {
+ /*
+* If the plane don't have damage areas but the
+* framebuffer changed, mark the whole plane area as
+* damaged.
+*/
+
[Intel-gfx] [PATCH v7 3/5] drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_display.c | 78
drivers/gpu/drm/i915/display/intel_display.h | 2 +
2 files changed, 51 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 78452de5e12f..add74ff7eb9b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3821,33 +3821,19 @@ static int intel_plane_max_height(struct intel_plane
*plane,
return INT_MAX;
}
-static int skl_check_main_surface(struct intel_plane_state *plane_state)
+int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
+int *x, int *y, u32 *offset)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
- unsigned int rotation = plane_state->hw.rotation;
- int x = plane_state->uapi.src.x1 >> 16;
- int y = plane_state->uapi.src.y1 >> 16;
- int w = drm_rect_width(_state->uapi.src) >> 16;
- int h = drm_rect_height(_state->uapi.src) >> 16;
- int min_width = intel_plane_min_width(plane, fb, 0, rotation);
- int max_width = intel_plane_max_width(plane, fb, 0, rotation);
- int max_height = intel_plane_max_height(plane, fb, 0, rotation);
- int aux_plane = intel_main_to_aux_plane(fb, 0);
- u32 aux_offset = plane_state->color_plane[aux_plane].offset;
- u32 alignment, offset;
+ const int aux_plane = intel_main_to_aux_plane(fb, 0);
+ const u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ const u32 alignment = intel_surf_alignment(fb, 0);
+ const int w = drm_rect_width(_state->uapi.src) >> 16;
- if (w > max_width || w < min_width || h > max_height) {
- drm_dbg_kms(_priv->drm,
- "requested Y/RGB source size %dx%d outside limits
(min: %dx1 max: %dx%d)\n",
- w, h, min_width, max_width, max_height);
- return -EINVAL;
- }
-
- intel_add_fb_offsets(, , plane_state, 0);
- offset = intel_plane_compute_aligned_offset(, , plane_state, 0);
- alignment = intel_surf_alignment(fb, 0);
+ intel_add_fb_offsets(x, y, plane_state, 0);
+ *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
if (drm_WARN_ON(_priv->drm, alignment && !is_power_of_2(alignment)))
return -EINVAL;
@@ -3856,9 +3842,10 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
* main surface offset, and it must be non-negative. Make
* sure that is what we will get.
*/
- if (aux_plane && offset > aux_offset)
- offset = intel_plane_adjust_aligned_offset(, , plane_state,
0,
- offset, aux_offset &
~(alignment - 1));
+ if (aux_plane && *offset > aux_offset)
+ *offset = intel_plane_adjust_aligned_offset(x, y, plane_state,
0,
+ *offset,
+ aux_offset &
~(alignment - 1));
/*
* When using an X-tiled surface, the plane blows up
@@ -3869,18 +3856,51 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
int cpp = fb->format->cpp[0];
- while ((x + w) * cpp > plane_state->color_plane[0].stride) {
- if (offset == 0) {
+ while ((*x + w) * cpp > plane_state->color_plane[0].stride) {
+ if (*offset == 0) {
drm_dbg_kms(_priv->drm,
"Unable to find suitable display
surface offset due to X-tiling\n");
return -EINVAL;
}
- offset = intel_plane_adjust_aligned_offset(, ,
plane_state, 0,
- offset,
offset - alignment);
+ *offset = intel_plane_adjust_aligned_offset(x, y,
plane_state, 0,
+ *offset,
+ *offset -
alignment);
}
}
+ return 0;
+}
+
+static int skl_check_main_surface(struct intel_plane_state *plane_state)
[Intel-gfx] [PATCH v7 1/5] drm: Add function to convert rect in 16.16 fixed format to regular format
Much more clear to read one function call than four lines doing this
conversion.
v7:
- function renamed
- calculating width and height before truncate
- inlined
Cc: Ville Syrjälä
Cc: dri-de...@lists.freedesktop.org
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
include/drm/drm_rect.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h
index e7f4d24cdd00..7eb84af4a818 100644
--- a/include/drm/drm_rect.h
+++ b/include/drm/drm_rect.h
@@ -206,6 +206,19 @@ static inline bool drm_rect_equals(const struct drm_rect
*r1,
r1->y1 == r2->y1 && r1->y2 == r2->y2;
}
+/**
+ * drm_rect_fp_to_int - Convert a rect in 16.16 fixed point form to int form.
+ * @destination: rect to be stored the converted value
+ * @source: rect in 16.16 fixed point form
+ */
+static inline void drm_rect_fp_to_int(struct drm_rect *destination,
+ const struct drm_rect *source)
+{
+ drm_rect_init(destination, source->x1 >> 16, source->y1 >> 16,
+ drm_rect_width(source) >> 16,
+ drm_rect_height(source) >> 16);
+}
+
bool drm_rect_intersect(struct drm_rect *r, const struct drm_rect *clip);
bool drm_rect_clip_scaled(struct drm_rect *src, struct drm_rect *dst,
const struct drm_rect *clip);
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
== Series Details == Series: drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h URL : https://patchwork.freedesktop.org/series/85001/ State : success == Summary == CI Bug Log - changes from CI_DRM_9491_full -> Patchwork_19159_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19159_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#2369] / [i915#2502]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-skl5/igt@gem_exec_capture@p...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-skl7/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_reloc@basic-many-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][3] ([i915#2389]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-iclb4/igt@gem_exec_reloc@basic-many-act...@vcs1.html * igt@gem_exec_reloc@basic-parallel: - shard-skl: NOTRUN -> [TIMEOUT][4] ([i915#1729]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-skl7/igt@gem_exec_re...@basic-parallel.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled: - shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271]) +25 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-glk2/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-yf-tiled.html - shard-iclb: NOTRUN -> [SKIP][6] ([i915#768]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-iclb1/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-yf-tiled.html * igt@gem_userptr_blits@mmap-offset-invalidate-idle@gtt: - shard-tglb: NOTRUN -> [SKIP][7] ([i915#1317]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-tglb3/igt@gem_userptr_blits@mmap-offset-invalidate-i...@gtt.html * igt@gem_userptr_blits@process-exit-mmap@wb: - shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1699]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-skl8/igt@gem_userptr_blits@process-exit-m...@wb.html * igt@gem_workarounds@suspend-resume-context: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#198] / [i915#2295]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-skl8/igt@gem_workarou...@suspend-resume-context.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-skl10/igt@gem_workarou...@suspend-resume-context.html * igt@gen3_render_tiledx_blits: - shard-iclb: NOTRUN -> [SKIP][11] ([fdo#109289]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-iclb1/igt@gen3_render_tiledx_blits.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][12] -> [DMESG-WARN][13] ([i915#1436] / [i915#716]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-glk7/igt@gen9_exec_pa...@allowed-all.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-glk4/igt@gen9_exec_pa...@allowed-all.html * igt@gen9_exec_parse@batch-without-end: - shard-tglb: NOTRUN -> [SKIP][14] ([fdo#112306]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-tglb3/igt@gen9_exec_pa...@batch-without-end.html * igt@gen9_exec_parse@valid-registers: - shard-iclb: NOTRUN -> [SKIP][15] ([fdo#112306]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-iclb1/igt@gen9_exec_pa...@valid-registers.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2597]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-tglb6/igt@kms_async_fl...@test-time-stamp.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-tglb6/igt@kms_async_fl...@test-time-stamp.html * igt@kms_big_fb@x-tiled-8bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#111614]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-tglb3/igt@kms_big...@x-tiled-8bpp-rotate-270.html * igt@kms_ccs@pipe-c-crc-primary-basic: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111304]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-skl9/igt@kms_...@pipe-c-crc-primary-basic.html * igt@kms_chamelium@vga-hpd: - shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +5 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-skl8/igt@kms_chamel...@vga-hpd.html * igt@kms_color@pipe-b-degamma: - shard-tglb: NOTRUN -> [FAIL][21] ([i915#1149]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/shard-tglb3/igt@kms_co...@pipe-b-degamma.html *
Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between misplaced vma check and vma insert
> -Original Message-
> From: Chris Wilson
> Sent: Wednesday, December 16, 2020 12:43 AM
> To: Tang, CQ ; intel-gfx@lists.freedesktop.org
> Cc: stable@
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between misplaced
> vma check and vma insert
>
> Quoting Tang, CQ (2020-12-16 00:51:21)
> >
> >
> > > -Original Message-
> > > From: Chris Wilson
> > > Sent: Tuesday, December 15, 2020 2:02 PM
> > > To: Tang, CQ ; intel-gfx@lists.freedesktop.org
> > > Cc: stable@
> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between
> > > misplaced vma check and vma insert
> > >
> > > Quoting Tang, CQ (2020-12-15 21:50:53)
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Chris Wilson
> > > > > Sent: Tuesday, December 15, 2020 12:31 PM
> > > > > To: intel-gfx@lists.freedesktop.org
> > > > > Cc: Chris Wilson ; Tang, CQ
> > > > > ; sta...@vger.kernel.org
> > > > > Subject: [PATCH] drm/i915: Fix mismatch between misplaced vma
> > > > > check and vma insert
> > > > >
> > > > > When inserting a VMA, we restrict the placement to the low 4G
> > > > > unless the caller opts into using the full range. This was done
> > > > > to allow usersapce the opportunity to transition slowly from a
> > > > > 32b address space, and to avoid breaking inherent 32b
> > > > > assumptions of some
> > > commands.
> > > > >
> > > > > However, for insert we limited ourselves to 4G-4K, but on
> > > > > verification we allowed the full 4G. This causes some attempts
> > > > > to bind a new buffer to sporadically fail with -ENOSPC, but at
> > > > > other times be
> > > bound successfully.
> > > > >
> > > > > commit 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to
> 4GB
> > > > > - 1
> > > > > page") suggests that there is a genuine problem with stateless
> > > > > addressing that cannot utilize the last page in 4G and so we
> > > > > purposefully
> > > excluded it.
> > > > >
> > > > > Reported-by: CQ Tang
> > > > > Fixes: 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to 4GB
> > > > > - 1
> > > > > page")
> > > > > Signed-off-by: Chris Wilson
> > > > > Cc: CQ Tang
> > > > > Cc: sta...@vger.kernel.org
> > > > > ---
> > > > > drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
> > > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > index 193996144c84..2ff32daa50bd 100644
> > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > @@ -382,7 +382,7 @@ eb_vma_misplaced(const struct
> > > > > drm_i915_gem_exec_object2 *entry,
> > > > > return true;
> > > > >
> > > > > if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
> > > > > - (vma->node.start + vma->node.size - 1) >> 32)
> > > > > + (vma->node.start + vma->node.size + 4095) >> 32)
> > > >
> > > > Why 4095 not 4096?
> > >
> > > It's the nature of the test that we need an inclusive bound.
> > >
> > > Consider an object of size 4G - 4K, that is allowed to fit within our 32b
> > > GTT.
> > >
> > > 4G - 4k + 4K = 4G == 1 << 32: => vma misplaced
> > >
> > > 4G - 4k + 4k - 1 = 4G -1 = 0x => vma ok
> >
> > How do we trigger this code? I run gem_exec_params@larger-than-life-
> batch but did not see this code is executed.
> > Basically how do we triggre first attempt to pin the object in place.
>
> It's the first pin tried, but the incoming execobj.offset must be available
> and
> the object itself must be ready to be pinned. That's true for the current tree
> on all current gen.
For gem_exec_params@larger-than-life-batch subtest, I only see
i915_vma_misplaced() be called when EXEC_OBJECT_SUPPORTS_48B_ADDRESS flags is
specified, and the test passes.
I want to catch the bug before you fixed here. So a 4GB object should be OK,
because before your fix, i915_vma_misplaced() returns false.
I did specify execobj.offset=0, but the driver code goes to i915_vma_insert()
directly and return -ENOSPC.
How do I make gem_exec_params@larger-than-life-batch code to catch this bug?
--CQ
> -Chris
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[Intel-gfx] [PATCH] drm/i915/cml : Add TGP PCH support
We have TGP PCH support for Tigerlake and Rocketlake. Similarly
now TGP PCH can be used with Cometlake CPU.
Cc: Matt Roper
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
drivers/gpu/drm/i915/display/intel_hdmi.c| 3 ++-
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6863236df1d0..10e677978ded 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5451,7 +5451,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
if (IS_DG1(dev_priv))
encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
- else if (IS_ROCKETLAKE(dev_priv))
+ else if (IS_ROCKETLAKE(dev_priv) || (IS_COMETLAKE(dev_priv) &&
+HAS_PCH_TGP(dev_priv)))
encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
else if (INTEL_GEN(dev_priv) >= 12)
encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 78452de5e12f..711e8e21e756 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17644,6 +17644,12 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_F);
icl_dsi_init(dev_priv);
+ } else if (IS_COMETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ intel_ddi_init(dev_priv, PORT_D);
+ intel_ddi_init(dev_priv, PORT_E);
} else if (IS_GEN9_LP(dev_priv)) {
/*
* FIXME: Broxton doesn't support port detection via the
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e10fdb369daa..881646ce47c5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3174,7 +3174,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
*encoder)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
- else if (IS_ROCKETLAKE(dev_priv))
+ else if (IS_ROCKETLAKE(dev_priv) || (IS_COMETLAKE(dev_priv) &&
+HAS_PCH_TGP(dev_priv)))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
--
2.28.0
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[Intel-gfx] [CI] drm/i915: Encode fence specific waitqueue behaviour into the wait.flags
Use the wait_queue_entry.flags to denote the special fence behaviour
(flattening continuations along fence chains, and for propagating
errors) rather than trying to detect ordinary waiters by their
functions.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/i915_sw_fence.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
b/drivers/gpu/drm/i915/i915_sw_fence.c
index 038d4c6884c5..2744558f3050 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -18,10 +18,15 @@
#define I915_SW_FENCE_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
#endif
-#define I915_SW_FENCE_FLAG_ALLOC BIT(3) /* after WQ_FLAG_* for safety */
-
static DEFINE_SPINLOCK(i915_sw_fence_lock);
+#define WQ_FLAG_BITS \
+ BITS_PER_TYPE(typeof_member(struct wait_queue_entry, flags))
+
+/* after WQ_FLAG_* for safety */
+#define I915_SW_FENCE_FLAG_FENCE BIT(WQ_FLAG_BITS - 1)
+#define I915_SW_FENCE_FLAG_ALLOC BIT(WQ_FLAG_BITS - 2)
+
enum {
DEBUG_FENCE_IDLE = 0,
DEBUG_FENCE_NOTIFY,
@@ -154,10 +159,10 @@ static void __i915_sw_fence_wake_up_all(struct
i915_sw_fence *fence,
spin_lock_irqsave_nested(>lock, flags, 1 + !!continuation);
if (continuation) {
list_for_each_entry_safe(pos, next, >head, entry) {
- if (pos->func == autoremove_wake_function)
- pos->func(pos, TASK_NORMAL, 0, continuation);
- else
+ if (pos->flags & I915_SW_FENCE_FLAG_FENCE)
list_move_tail(>entry, continuation);
+ else
+ pos->func(pos, TASK_NORMAL, 0, continuation);
}
} else {
LIST_HEAD(extra);
@@ -166,9 +171,9 @@ static void __i915_sw_fence_wake_up_all(struct
i915_sw_fence *fence,
list_for_each_entry_safe(pos, next, >head, entry) {
int wake_flags;
- wake_flags = fence->error;
- if (pos->func == autoremove_wake_function)
- wake_flags = 0;
+ wake_flags = 0;
+ if (pos->flags & I915_SW_FENCE_FLAG_FENCE)
+ wake_flags = fence->error;
pos->func(pos, TASK_NORMAL, wake_flags, );
}
@@ -332,8 +337,8 @@ static int __i915_sw_fence_await_sw_fence(struct
i915_sw_fence *fence,
struct i915_sw_fence *signaler,
wait_queue_entry_t *wq, gfp_t gfp)
{
+ unsigned int pending;
unsigned long flags;
- int pending;
debug_fence_assert(fence);
might_sleep_if(gfpflags_allow_blocking(gfp));
@@ -349,7 +354,7 @@ static int __i915_sw_fence_await_sw_fence(struct
i915_sw_fence *fence,
if (unlikely(i915_sw_fence_check_if_after(fence, signaler)))
return -EINVAL;
- pending = 0;
+ pending = I915_SW_FENCE_FLAG_FENCE;
if (!wq) {
wq = kmalloc(sizeof(*wq), gfp);
if (!wq) {
--
2.20.1
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[Intel-gfx] [PATCH i-g-t] i915/perf_pmu: Replace init/read-other with a plea
We cannot assume we know how many PMU there are exactly, so pick -1ULL
to represent all invalid metrics. Similarly, we have to rely on explicit
testing for each PMU to prove their existence and correct functioning.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/perf_pmu.c | 56 ---
1 file changed, 15 insertions(+), 41 deletions(-)
diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index e2f975a1a..db375341c 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -1165,38 +1165,12 @@ do { \
igt_assert_eq(errno, EINVAL);
}
-static void init_other(int i915, unsigned int i, bool valid)
+static void open_invalid(int i915)
{
int fd;
- fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
- igt_require(!(fd < 0 && errno == ENODEV));
- if (valid) {
- igt_assert(fd >= 0);
- } else {
- igt_assert(fd < 0);
- return;
- }
-
- close(fd);
-}
-
-static void read_other(int i915, unsigned int i, bool valid)
-{
- int fd;
-
- fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
- igt_require(!(fd < 0 && errno == ENODEV));
- if (valid) {
- igt_assert(fd >= 0);
- } else {
- igt_assert(fd < 0);
- return;
- }
-
- (void)pmu_read_single(fd);
-
- close(fd);
+ fd = perf_i915_open(i915, -1ULL);
+ igt_assert(fd < 0);
}
static bool cpu0_hotplug_support(void)
@@ -2058,6 +2032,12 @@ igt_main
unsigned int num_engines = 0;
int fd = -1;
+ /**
+* All PMU should be accompanied by a test.
+*
+* Including all the I915_PMU_OTHER(x).
+*/
+
igt_fixture {
fd = __drm_open_driver(DRIVER_INTEL);
@@ -2075,6 +2055,12 @@ igt_main
igt_subtest("invalid-init")
invalid_init(fd);
+ /**
+* Double check the invalid metric does fail.
+*/
+ igt_subtest("invalid-open")
+ open_invalid(fd);
+
igt_subtest_with_dynamic("faulting-read") {
for_each_mmap_offset_type(fd, t) {
igt_dynamic_f("%s", t->name)
@@ -2228,18 +2214,6 @@ igt_main
all_busy_check_all(fd, num_engines,
TEST_BUSY | TEST_TRAILING_IDLE);
- /**
-* Test that non-engine counters can be initialized and read. Apart
-* from the invalid metric which should fail.
-*/
- for (unsigned int i = 0; i < num_other_metrics + 1; i++) {
- igt_subtest_f("other-init-%u", i)
- init_other(fd, i, i < num_other_metrics);
-
- igt_subtest_f("other-read-%u", i)
- read_other(fd, i, i < num_other_metrics);
- }
-
/**
* Test counters are not affected by CPU offline/online events.
*/
--
2.29.2
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[Intel-gfx] [PATCH v2 i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class
From: Tvrtko Ursulin
Similarly to how top(1) handles SMP, we can default to showing engines of
a same class as a single bar graph entry.
To achieve this a little bit of hackery is employed. PMU sampling is left
as is and only at the presentation layer we create a fake set of engines,
one for each class, summing and normalizing the load respectively.
v2:
* Fix building the aggregated engines.
* Tidy static variable handling.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 1 +
tools/intel_gpu_top.c | 208 +++---
2 files changed, 196 insertions(+), 13 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index 2e0c3a05acc1..35ab10da9bb4 100644
--- a/man/intel_gpu_top.rst
+++ b/man/intel_gpu_top.rst
@@ -54,6 +54,7 @@ RUNTIME CONTROL
Supported keys:
'q'Exit from the tool.
+'1'Toggle between aggregated engine class and physical engine mode.
DEVICE SELECTION
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 46221c9543eb..9ae30b8020dc 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -76,8 +76,16 @@ struct engine {
struct pmu_counter sema;
};
+struct engine_class {
+ unsigned int class;
+ const char *name;
+ unsigned int num_engines;
+};
+
struct engines {
unsigned int num_engines;
+ unsigned int num_classes;
+ struct engine_class *class;
unsigned int num_counters;
DIR *root;
int fd;
@@ -1118,6 +1126,8 @@ print_imc(struct engines *engines, double t, int lines,
int con_w, int con_h)
return lines;
}
+static bool class_view;
+
static int
print_engines_header(struct engines *engines, double t,
int lines, int con_w, int con_h)
@@ -1133,8 +1143,13 @@ print_engines_header(struct engines *engines, double t,
pops->open_struct("engines");
if (output_mode == INTERACTIVE) {
- const char *a = " ENGINE BUSY ";
const char *b = " MI_SEMA MI_WAIT";
+ const char *a;
+
+ if (class_view)
+ a = " ENGINES BUSY ";
+ else
+ a = " ENGINE BUSY ";
printf("\033[7m%s%*s%s\033[0m\n",
a, (int)(con_w - 1 - strlen(a) - strlen(b)),
@@ -1214,6 +1229,180 @@ print_engines_footer(struct engines *engines, double t,
return lines;
}
+static int class_cmp(const void *_a, const void *_b)
+{
+ const struct engine_class *a = _a;
+ const struct engine_class *b = _b;
+
+ return a->class - b->class;
+}
+
+static void init_engine_classes(struct engines *engines)
+{
+ struct engine_class *classes;
+ unsigned int i, num;
+ int max = -1;
+
+ for (i = 0; i < engines->num_engines; i++) {
+ struct engine *engine = engine_ptr(engines, i);
+
+ if ((int)engine->class > max)
+ max = engine->class;
+ }
+ assert(max >= 0);
+
+ num = max + 1;
+
+ classes = calloc(num, sizeof(*classes));
+ assert(classes);
+
+ for (i = 0; i < engines->num_engines; i++) {
+ struct engine *engine = engine_ptr(engines, i);
+
+ classes[engine->class].num_engines++;
+ }
+
+ for (i = 0; i < num; i++) {
+ classes[i].class = i;
+ classes[i].name = class_display_name(i);
+ }
+
+ qsort(classes, num, sizeof(*classes), class_cmp);
+
+ engines->num_classes = num;
+ engines->class = classes;
+}
+
+static void __pmu_sum(struct pmu_pair *dst, struct pmu_pair *src)
+{
+ dst->prev += src->prev;
+ dst->cur += src->cur;
+}
+
+static void __pmu_normalize(struct pmu_pair *val, unsigned int n)
+{
+ val->prev /= n;
+ val->cur /= n;
+}
+
+static struct engines *init_class_engines(struct engines *engines)
+{
+ unsigned int num_present;
+ struct engines *classes;
+ unsigned int i, j, k;
+
+ init_engine_classes(engines);
+
+ num_present = 0; /* Classes with engines. */
+ for (i = 0; i < engines->num_classes; i++) {
+ if (engines->class[i].num_engines)
+ num_present++;
+ }
+
+ classes = calloc(1, sizeof(struct engines) +
+ num_present * sizeof(struct engine));
+ assert(classes);
+
+ classes->num_engines = num_present;
+ classes->num_classes = engines->num_classes;
+ classes->class = engines->class;
+
+ j = 0;
+ for (i = 0; i < engines->num_classes; i++) {
+ struct engine *engine = engine_ptr(classes, j);
+
+ /* Skip classes with no engines. */
+ if (!engines->class[i].num_engines)
+ continue;
+
+
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v7,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v7,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/85000/ State : success == Summary == CI Bug Log - changes from CI_DRM_9491_full -> Patchwork_19158_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19158_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-glk: [PASS][1] -> [FAIL][2] ([i915#2389]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-glk2/igt@gem_exec_reloc@basic-many-act...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-glk6/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled: - shard-glk: NOTRUN -> [SKIP][3] ([fdo#109271]) +25 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-glk3/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-yf-tiled.html * igt@gem_userptr_blits@mmap-offset-invalidate-idle@gtt: - shard-tglb: NOTRUN -> [SKIP][4] ([i915#1317]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-tglb8/igt@gem_userptr_blits@mmap-offset-invalidate-i...@gtt.html * igt@gem_userptr_blits@process-exit-mmap@wb: - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1699]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-skl5/igt@gem_userptr_blits@process-exit-m...@wb.html * igt@gen9_exec_parse@batch-without-end: - shard-tglb: NOTRUN -> [SKIP][6] ([fdo#112306]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-tglb8/igt@gen9_exec_pa...@batch-without-end.html * igt@gen9_exec_parse@bb-large: - shard-apl: [PASS][7] -> [TIMEOUT][8] ([i915#2502]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-apl3/igt@gen9_exec_pa...@bb-large.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-apl3/igt@gen9_exec_pa...@bb-large.html * igt@kms_big_fb@x-tiled-8bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][9] ([fdo#111614]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-tglb8/igt@kms_big...@x-tiled-8bpp-rotate-270.html * igt@kms_ccs@pipe-c-crc-primary-basic: - shard-skl: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111304]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-skl1/igt@kms_...@pipe-c-crc-primary-basic.html * igt@kms_chamelium@vga-hpd: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-skl5/igt@kms_chamel...@vga-hpd.html * igt@kms_color@pipe-b-degamma: - shard-tglb: NOTRUN -> [FAIL][12] ([i915#1149]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-tglb8/igt@kms_co...@pipe-b-degamma.html * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue: - shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-glk3/igt@kms_color_chamel...@pipe-b-ctm-red-to-blue.html * igt@kms_color_chamelium@pipe-c-ctm-blue-to-red: - shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109284] / [fdo#111827]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-tglb8/igt@kms_color_chamel...@pipe-c-ctm-blue-to-red.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-skl: NOTRUN -> [FAIL][15] ([i915#54]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-256x85-onscreen.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#54]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-64x21-onscreen.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-64x21-onscreen.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2598]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-tglb8/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/shard-tglb5/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1: - shard-skl: [PASS][20] -> [FAIL][21] ([i915#2122]) [20]:
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class
Quoting Tvrtko Ursulin (2020-12-16 16:01:30)
>
> On 16/12/2020 15:51, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-12-16 15:28:09)
> >> +static int
> >> +print_engines(struct engines *engines, double t, int lines, int w, int h)
> >> +{
> >> + static struct engines *classes;
> >> + struct engines *show;
> >> +
> >> + if (class_view)
> >> + classes = show = update_classes(classes, engines);
> >
> > Something is not right here. Oh static, nvm.
>
> Too hacky? Maybe "show = classes = update_classes()"would read better.
show = update_classes(engines);
with update_classes doing the if (once) classes = init_classes(engines) ?
-Chris
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class
On 16/12/2020 15:51, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-12-16 15:28:09)
From: Tvrtko Ursulin
Similarly to how top(1) handles SMP, we can default to showing engines of
a same class as a single bar graph entry.
To achieve this a little bit of hackery is employed. PMU sampling is left
as is and only at the presentation layer we create a fake set of engines,
one for each class, summing and normalizing the load respectively.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 1 +
tools/intel_gpu_top.c | 192 +++---
2 files changed, 180 insertions(+), 13 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index 2e0c3a05acc1..35ab10da9bb4 100644
--- a/man/intel_gpu_top.rst
+++ b/man/intel_gpu_top.rst
@@ -54,6 +54,7 @@ RUNTIME CONTROL
Supported keys:
'q'Exit from the tool.
+'1'Toggle between aggregated engine class and physical engine mode.
DEVICE SELECTION
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 68911940f1d0..8c4280aa19b9 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -76,8 +76,16 @@ struct engine {
struct pmu_counter sema;
};
+struct engine_class {
+ unsigned int class;
+ const char *name;
+ unsigned int num_engines;
+};
+
struct engines {
unsigned int num_engines;
+ unsigned int num_classes;
+ struct engine_class *class;
unsigned int num_counters;
DIR *root;
int fd;
@@ -1118,6 +1126,8 @@ print_imc(struct engines *engines, double t, int lines,
int con_w, int con_h)
return lines;
}
+static bool class_view;
+
static int
print_engines_header(struct engines *engines, double t,
int lines, int con_w, int con_h)
@@ -1133,8 +1143,13 @@ print_engines_header(struct engines *engines, double t,
pops->open_struct("engines");
if (output_mode == INTERACTIVE) {
- const char *a = " ENGINE BUSY ";
const char *b = " MI_SEMA MI_WAIT";
+ const char *a;
+
+ if (class_view)
+ a = " ENGINES BUSY ";
+ else
+ a = " ENGINE BUSY ";
printf("\033[7m%s%*s%s\033[0m\n",
a, (int)(con_w - 1 - strlen(a) - strlen(b)),
@@ -1214,6 +1229,164 @@ print_engines_footer(struct engines *engines, double t,
return lines;
}
+static int class_cmp(const void *_a, const void *_b)
+{
+ const struct engine_class *a = _a;
+ const struct engine_class *b = _b;
+
+ return a->class - b->class;
+}
+
+static void init_engine_classes(struct engines *engines)
+{
+ struct engine_class *classes;
+ unsigned int i, num;
+ int max = -1;
+
+ for (i = 0; i < engines->num_engines; i++) {
+ struct engine *engine = engine_ptr(engines, i);
+
+ if ((int)engine->class > max)
+ max = engine->class;
+ }
+ assert(max >= 0);
+
+ num = max + 1;
+
+ classes = calloc(num, sizeof(*classes));
+ assert(classes);
+
+ for (i = 0; i < engines->num_engines; i++) {
+ struct engine *engine = engine_ptr(engines, i);
+
+ classes[engine->class].num_engines++;
+ }
+
+ for (i = 0; i < num; i++) {
+ classes[i].class = i;
+ classes[i].name = class_display_name(i);
+ }
Do you want to remove empty classes at this point?
I need this array 1:1 with class ids so no. I didn't find yet that
"empty" entries would cause a problem anywhere in the code. Hm actually
there wouldn't be any empty classes, since class generation is driven of
discovered engines.
I need to sprinkle some more asserts and comments around.
+
+ qsort(classes, num, sizeof(*classes), class_cmp);
+
+ engines->num_classes = num;
+ engines->class = classes;
+}
+
+static void __pmu_sum(struct pmu_pair *dst, struct pmu_pair *src)
+{
+ dst->prev += src->prev;
+ dst->cur += src->cur;
+}
+
+static void __pmu_normalize(struct pmu_pair *val, unsigned int n)
+{
+ val->prev /= n;
+ val->cur /= n;
I was expecting just the delta to be normalized. This works as well.
Yeah, this allows basically no changes to existing code.
Maybe a running average algorithm would be better to not overflow the
u64 but I haven't bothered calculating if that is a theoretical
possibility or not.
+}
+
+static struct engines *init_classes(struct engines *engines)
+{
+ struct engines *classes;
+ unsigned int i, j;
+
+ init_engine_classes(engines);
+
+ classes = calloc(1, sizeof(struct engines) +
+ engines->num_classes * sizeof(struct engine));
+
Re: [Intel-gfx] [PATCH v2 i-g-t 1/2] intel_gpu_top: Support exiting the tool by pressing 'q'
Quoting Tvrtko Ursulin (2020-12-16 15:54:20) > From: Tvrtko Ursulin > > Analoguous to top(1) we can enable the user to exit from the tool by > pressing 'q' on the console. > > v2: > * Fix sleep period with closed stdin. (Chris) > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for Add support for DP-HDMI2.1 PCON (rev8)
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev8)
URL : https://patchwork.freedesktop.org/series/82098/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9491_full -> Patchwork_19157_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19157_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19157_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19157_full:
### IGT changes ###
Possible regressions
* igt@kms_cursor_legacy@pipe-a-single-bo:
- shard-hsw: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-hsw7/igt@kms_cursor_leg...@pipe-a-single-bo.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_schedule@u-fairslice-all}:
- shard-tglb: [PASS][2] -> [DMESG-WARN][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-tglb7/igt@gem_exec_sched...@u-fairslice-all.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-tglb5/igt@gem_exec_sched...@u-fairslice-all.html
Known issues
Here are the changes found in Patchwork_19157_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271]) +25 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-glk1/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
- shard-iclb: NOTRUN -> [SKIP][5] ([i915#768]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-iclb3/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@mmap-offset-invalidate-idle@gtt:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#1317]) +3 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-tglb1/igt@gem_userptr_blits@mmap-offset-invalidate-i...@gtt.html
* igt@gem_userptr_blits@process-exit-mmap@wb:
- shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1699]) +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-skl10/igt@gem_userptr_blits@process-exit-m...@wb.html
* igt@gen3_render_tiledx_blits:
- shard-iclb: NOTRUN -> [SKIP][8] ([fdo#109289])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-iclb3/igt@gen3_render_tiledx_blits.html
* igt@gen9_exec_parse@batch-without-end:
- shard-tglb: NOTRUN -> [SKIP][9] ([fdo#112306])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-tglb1/igt@gen9_exec_pa...@batch-without-end.html
* igt@gen9_exec_parse@valid-registers:
- shard-iclb: NOTRUN -> [SKIP][10] ([fdo#112306])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-iclb3/igt@gen9_exec_pa...@valid-registers.html
* igt@i915_selftest@live@execlists:
- shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([i915#1037] /
[i915#2089] / [i915#2268])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/shard-tglb7/igt@i915_selftest@l...@execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-tglb6/igt@i915_selftest@l...@execlists.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][13] ([fdo#111614])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-tglb1/igt@kms_big...@x-tiled-8bpp-rotate-270.html
* igt@kms_ccs@pipe-c-crc-primary-basic:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111304])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-skl9/igt@kms_...@pipe-c-crc-primary-basic.html
* igt@kms_chamelium@vga-hpd:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +5
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-skl10/igt@kms_chamel...@vga-hpd.html
* igt@kms_color@pipe-b-degamma:
- shard-tglb: NOTRUN -> [FAIL][16] ([i915#1149])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-tglb1/igt@kms_co...@pipe-b-degamma.html
* igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109284] / [fdo#111827]) +3
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/shard-iclb3/igt@kms_color_chamel...@pipe-b-ctm-red-to-blue.html
- shard-glk: NOTRUN -> [SKIP][18]
[Intel-gfx] [PATCH v2 i-g-t 1/2] intel_gpu_top: Support exiting the tool by pressing 'q'
From: Tvrtko Ursulin
Analoguous to top(1) we can enable the user to exit from the tool by
pressing 'q' on the console.
v2:
* Fix sleep period with closed stdin. (Chris)
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 6
tools/intel_gpu_top.c | 80 ---
2 files changed, 73 insertions(+), 13 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index 5552e9699d26..2e0c3a05acc1 100644
--- a/man/intel_gpu_top.rst
+++ b/man/intel_gpu_top.rst
@@ -48,6 +48,12 @@ OPTIONS
-d
Select a specific GPU using supported filter.
+RUNTIME CONTROL
+===
+
+Supported keys:
+
+'q'Exit from the tool.
DEVICE SELECTION
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index dbd353673e55..46221c9543eb 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -23,24 +23,26 @@
#include "igt_device_scan.h"
-#include
-#include
-#include
-#include
#include
-#include
#include
-#include
-#include
-#include
+#include
+#include
#include
#include
-#include
-#include
-#include
-#include
#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
#include "igt_perf.h"
@@ -1246,6 +1248,54 @@ static char *tr_pmu_name(struct igt_device_card *card)
return device;
}
+static void interactive_stdin(void)
+{
+ struct termios termios = { };
+ int ret;
+
+ ret = fcntl(0, F_GETFL, NULL);
+ ret |= O_NONBLOCK;
+ ret = fcntl(0, F_SETFL, ret);
+ assert(ret == 0);
+
+ ret = tcgetattr(0, );
+ assert(ret == 0);
+
+ termios.c_lflag &= ~ICANON;
+ termios.c_cc[VMIN] = 1;
+ termios.c_cc[VTIME] = 0; /* Deciseconds only - we'll use poll. */
+
+ ret = tcsetattr(0, TCSAFLUSH, );
+ assert(ret == 0);
+}
+
+static void process_stdin(unsigned int timeout_us)
+{
+ struct pollfd p = { .fd = 0, .events = POLLIN };
+ int ret;
+
+ ret = poll(, 1, timeout_us / 1000);
+ if (ret <= 0) {
+ if (ret < 0)
+ stop_top = true;
+ return;
+ }
+
+ for (;;) {
+ char c;
+
+ ret = read(0, , 1);
+ if (ret <= 0)
+ break;
+
+ switch (c) {
+ case 'q':
+ stop_top = true;
+ break;
+ };
+ }
+}
+
int main(int argc, char **argv)
{
unsigned int period_us = DEFAULT_PERIOD_MS * 1000;
@@ -1315,6 +1365,7 @@ int main(int argc, char **argv)
switch (output_mode) {
case INTERACTIVE:
pops = _pops;
+ interactive_stdin();
break;
case STDOUT:
pops = _pops;
@@ -1427,7 +1478,10 @@ int main(int argc, char **argv)
if (stop_top)
break;
- usleep(period_us);
+ if (output_mode == INTERACTIVE)
+ process_stdin(period_us);
+ else
+ usleep(period_us);
}
free(codename);
--
2.25.1
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class
Quoting Chris Wilson (2020-12-16 15:51:59) > Quoting Tvrtko Ursulin (2020-12-16 15:28:09) > > From: Tvrtko Ursulin > > > > Similarly to how top(1) handles SMP, we can default to showing engines of > > a same class as a single bar graph entry. > > > > To achieve this a little bit of hackery is employed. PMU sampling is left > > as is and only at the presentation layer we create a fake set of engines, > > one for each class, summing and normalizing the load respectively. > > > > Signed-off-by: Tvrtko Ursulin Where were my manners? Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class
Quoting Tvrtko Ursulin (2020-12-16 15:28:09)
> From: Tvrtko Ursulin
>
> Similarly to how top(1) handles SMP, we can default to showing engines of
> a same class as a single bar graph entry.
>
> To achieve this a little bit of hackery is employed. PMU sampling is left
> as is and only at the presentation layer we create a fake set of engines,
> one for each class, summing and normalizing the load respectively.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> man/intel_gpu_top.rst | 1 +
> tools/intel_gpu_top.c | 192 +++---
> 2 files changed, 180 insertions(+), 13 deletions(-)
>
> diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
> index 2e0c3a05acc1..35ab10da9bb4 100644
> --- a/man/intel_gpu_top.rst
> +++ b/man/intel_gpu_top.rst
> @@ -54,6 +54,7 @@ RUNTIME CONTROL
> Supported keys:
>
> 'q'Exit from the tool.
> +'1'Toggle between aggregated engine class and physical engine mode.
>
> DEVICE SELECTION
>
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 68911940f1d0..8c4280aa19b9 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -76,8 +76,16 @@ struct engine {
> struct pmu_counter sema;
> };
>
> +struct engine_class {
> + unsigned int class;
> + const char *name;
> + unsigned int num_engines;
> +};
> +
> struct engines {
> unsigned int num_engines;
> + unsigned int num_classes;
> + struct engine_class *class;
> unsigned int num_counters;
> DIR *root;
> int fd;
> @@ -1118,6 +1126,8 @@ print_imc(struct engines *engines, double t, int lines,
> int con_w, int con_h)
> return lines;
> }
>
> +static bool class_view;
> +
> static int
> print_engines_header(struct engines *engines, double t,
> int lines, int con_w, int con_h)
> @@ -1133,8 +1143,13 @@ print_engines_header(struct engines *engines, double t,
> pops->open_struct("engines");
>
> if (output_mode == INTERACTIVE) {
> - const char *a = " ENGINE BUSY ";
> const char *b = " MI_SEMA MI_WAIT";
> + const char *a;
> +
> + if (class_view)
> + a = " ENGINES BUSY ";
> + else
> + a = " ENGINE BUSY ";
>
> printf("\033[7m%s%*s%s\033[0m\n",
>a, (int)(con_w - 1 - strlen(a) - strlen(b)),
> @@ -1214,6 +1229,164 @@ print_engines_footer(struct engines *engines, double
> t,
> return lines;
> }
>
> +static int class_cmp(const void *_a, const void *_b)
> +{
> + const struct engine_class *a = _a;
> + const struct engine_class *b = _b;
> +
> + return a->class - b->class;
> +}
> +
> +static void init_engine_classes(struct engines *engines)
> +{
> + struct engine_class *classes;
> + unsigned int i, num;
> + int max = -1;
> +
> + for (i = 0; i < engines->num_engines; i++) {
> + struct engine *engine = engine_ptr(engines, i);
> +
> + if ((int)engine->class > max)
> + max = engine->class;
> + }
> + assert(max >= 0);
> +
> + num = max + 1;
> +
> + classes = calloc(num, sizeof(*classes));
> + assert(classes);
> +
> + for (i = 0; i < engines->num_engines; i++) {
> + struct engine *engine = engine_ptr(engines, i);
> +
> + classes[engine->class].num_engines++;
> + }
> +
> + for (i = 0; i < num; i++) {
> + classes[i].class = i;
> + classes[i].name = class_display_name(i);
> + }
Do you want to remove empty classes at this point?
> +
> + qsort(classes, num, sizeof(*classes), class_cmp);
> +
> + engines->num_classes = num;
> + engines->class = classes;
> +}
> +
> +static void __pmu_sum(struct pmu_pair *dst, struct pmu_pair *src)
> +{
> + dst->prev += src->prev;
> + dst->cur += src->cur;
> +}
> +
> +static void __pmu_normalize(struct pmu_pair *val, unsigned int n)
> +{
> + val->prev /= n;
> + val->cur /= n;
I was expecting just the delta to be normalized. This works as well.
> +}
> +
> +static struct engines *init_classes(struct engines *engines)
> +{
> + struct engines *classes;
> + unsigned int i, j;
> +
> + init_engine_classes(engines);
> +
> + classes = calloc(1, sizeof(struct engines) +
> + engines->num_classes * sizeof(struct engine));
> + assert(classes);
> +
> + classes->num_engines = engines->num_classes;
> + classes->num_classes = engines->num_classes;
> + classes->class = engines->class;
> +
> + for (i = 0; i < engines->num_classes; i++) {
> + struct engine *engine = engine_ptr(classes, i);
> +
> +
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/2] intel_gpu_top: Support exiting the tool by pressing 'q'
Quoting Tvrtko Ursulin (2020-12-16 15:28:08)
> From: Tvrtko Ursulin
>
> Analoguous to top(1) we can enable the user to exit from the tool by
> pressing 'q' on the console.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> man/intel_gpu_top.rst | 6
> tools/intel_gpu_top.c | 77 +++
> 2 files changed, 70 insertions(+), 13 deletions(-)
>
> diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
> index 5552e9699d26..2e0c3a05acc1 100644
> --- a/man/intel_gpu_top.rst
> +++ b/man/intel_gpu_top.rst
> @@ -48,6 +48,12 @@ OPTIONS
> -d
> Select a specific GPU using supported filter.
>
> +RUNTIME CONTROL
> +===
> +
> +Supported keys:
> +
> +'q'Exit from the tool.
>
> DEVICE SELECTION
>
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index dbd353673e55..68911940f1d0 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -23,24 +23,26 @@
>
> #include "igt_device_scan.h"
>
> -#include
> -#include
> -#include
> -#include
> #include
> -#include
> #include
> -#include
> -#include
> -#include
> +#include
> +#include
> #include
> #include
> -#include
> -#include
> -#include
> -#include
> #include
> +#include
> +#include
> +#include
> #include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
>
> #include "igt_perf.h"
>
> @@ -1246,6 +1248,54 @@ static char *tr_pmu_name(struct igt_device_card *card)
> return device;
> }
>
> +static void interactive_stdin(void)
> +{
> + struct termios termios = { };
> + int ret;
> +
> + ret = fcntl(0, F_GETFL, NULL);
> + ret |= O_NONBLOCK;
> + ret = fcntl(0, F_SETFL, ret);
> + assert(ret == 0);
I always have to double check that O_NONBLOCK is in F_SETFL and not
F_SETFD.
> +
> + ret = tcgetattr(0, );
> + assert(ret == 0);
> +
> + termios.c_lflag &= ~ICANON;
> + termios.c_cc[VMIN] = 1;
> + termios.c_cc[VTIME] = 0; /* Deciseconds only - we'll use poll. */
> +
> + ret = tcsetattr(0, TCSAFLUSH, );
> + assert(ret == 0);
> +}
> +
> +static void process_stdin(unsigned int timeout_us)
> +{
> + struct pollfd p = { .fd = 0, .events = POLLIN };
> + int ret;
> +
> + ret = poll(, 1, timeout_us / 1000);
Replacing the usleep in the mainloop.
Hmm. Won't this have a problem if this run as a daemon (with stdin
closed)?
> + if (ret <= 0) {
> + if (ret < 0)
> + stop_top = true;
> + return;
> + }
> +
> + for (;;) {
> + char c;
> +
> + ret = read(0, , 1);
> + if (ret <= 0)
> + break;
O_NONBLOCK on 0.
So on each mainloop, we check for a key press, consume all that are in
the buffer, then return to the mainloop.
> +
> + switch (c) {
> + case 'q':
> + stop_top = true;
> + break;
> + };
> + }
> +}
> +
> int main(int argc, char **argv)
> {
> unsigned int period_us = DEFAULT_PERIOD_MS * 1000;
> @@ -1315,6 +1365,7 @@ int main(int argc, char **argv)
> switch (output_mode) {
> case INTERACTIVE:
INTERACTIVE is the default mode when run in a terminal.
> pops = _pops;
> + interactive_stdin();
> break;
> case STDOUT:
> pops = _pops;
> @@ -1427,7 +1478,7 @@ int main(int argc, char **argv)
> if (stop_top)
> break;
>
> - usleep(period_us);
> + process_stdin(period_us);
Just the question about what happens if run with 0 closed...
if (!process_stdin(period_us))
usleep(period_us);
?
> }
>
> free(codename);
> --
> 2.25.1
>
> ___
> igt-dev mailing list
> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
>
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Re: [Intel-gfx] [PATCH] drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
Chris Wilson writes: > Reduce the pollution of intel_engine.h by moving gen8_emit_pipe_control > and friends to gen8_engine_cs.h > > Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/display/intel_overlay.c | 1 + > drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + > .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 1 + > .../gpu/drm/i915/gem/i915_gem_object_blt.c| 1 + > .../i915/gem/selftests/i915_gem_coherency.c | 1 + > .../drm/i915/gem/selftests/i915_gem_mman.c| 1 + > .../drm/i915/gem/selftests/igt_gem_utils.c| 1 + > drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 92 +++ > drivers/gpu/drm/i915/gt/intel_engine.h| 86 - > drivers/gpu/drm/i915/gt/intel_renderstate.c | 3 +- > drivers/gpu/drm/i915/gt/intel_ring.c | 2 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + > drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 1 + > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 + > drivers/gpu/drm/i915/gt/selftest_mocs.c | 1 + > drivers/gpu/drm/i915/gt/selftest_rc6.c| 1 + > drivers/gpu/drm/i915/gt/selftest_reset.c | 1 + > drivers/gpu/drm/i915/gt/selftest_timeline.c | 1 + > drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + > drivers/gpu/drm/i915/gvt/mmio_context.c | 1 + > drivers/gpu/drm/i915/i915_cmd_parser.c| 1 + > drivers/gpu/drm/i915/i915_perf.c | 1 + > drivers/gpu/drm/i915/i915_request.c | 1 + > drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 + > drivers/gpu/drm/i915/selftests/igt_spinner.c | 1 + > 25 files changed, 118 insertions(+), 87 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c > b/drivers/gpu/drm/i915/display/intel_overlay.c > index 52b4f6193b4c..6be5d8946c69 100644 > --- a/drivers/gpu/drm/i915/display/intel_overlay.c > +++ b/drivers/gpu/drm/i915/display/intel_overlay.c > @@ -29,6 +29,7 @@ > #include > > #include "gem/i915_gem_pm.h" > +#include "gt/intel_gpu_commands.h" > #include "gt/intel_ring.h" > > #include "i915_drv.h" > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c > b/drivers/gpu/drm/i915/gem/i915_gem_context.c > index ad136d009d9b..7aa4629f6111 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c > @@ -73,6 +73,7 @@ > #include "gt/intel_engine_heartbeat.h" > #include "gt/intel_engine_user.h" > #include "gt/intel_execlists_submission.h" /* virtual_engine */ > +#include "gt/intel_gpu_commands.h" > #include "gt/intel_ring.h" > > #include "i915_gem_context.h" > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 2ff32daa50bd..0cf9e79325a8 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -15,6 +15,7 @@ > > #include "gem/i915_gem_ioctls.h" > #include "gt/intel_context.h" > +#include "gt/intel_gpu_commands.h" > #include "gt/intel_gt.h" > #include "gt/intel_gt_buffer_pool.h" > #include "gt/intel_gt_pm.h" > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > index aee7ad3cc3c6..10cac9fac79b 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > @@ -6,6 +6,7 @@ > #include "i915_drv.h" > #include "gt/intel_context.h" > #include "gt/intel_engine_pm.h" > +#include "gt/intel_gpu_commands.h" > #include "gt/intel_gt.h" > #include "gt/intel_gt_buffer_pool.h" > #include "gt/intel_ring.h" > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > index 7049a6bbc03d..1117d2a44518 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > @@ -7,6 +7,7 @@ > #include > > #include "gt/intel_engine_pm.h" > +#include "gt/intel_gpu_commands.h" > #include "gt/intel_gt.h" > #include "gt/intel_gt_pm.h" > #include "gt/intel_ring.h" > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > index d27d87a678c8..d429c7643ff2 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > @@ -7,6 +7,7 @@ > #include > > #include "gt/intel_engine_pm.h" > +#include "gt/intel_gpu_commands.h" > #include "gt/intel_gt.h" > #include "gt/intel_gt_pm.h" > #include "gem/i915_gem_region.h" > diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c > b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c > index e21b5023ca7d..d6783061bc72 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c > +++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c > @@ -9,6 +9,7 @@ > #include "gem/i915_gem_context.h" > #include
[Intel-gfx] [PATCH i-g-t 2/2] intel_gpu_top: Aggregate engine busyness per class
From: Tvrtko Ursulin
Similarly to how top(1) handles SMP, we can default to showing engines of
a same class as a single bar graph entry.
To achieve this a little bit of hackery is employed. PMU sampling is left
as is and only at the presentation layer we create a fake set of engines,
one for each class, summing and normalizing the load respectively.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 1 +
tools/intel_gpu_top.c | 192 +++---
2 files changed, 180 insertions(+), 13 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index 2e0c3a05acc1..35ab10da9bb4 100644
--- a/man/intel_gpu_top.rst
+++ b/man/intel_gpu_top.rst
@@ -54,6 +54,7 @@ RUNTIME CONTROL
Supported keys:
'q'Exit from the tool.
+'1'Toggle between aggregated engine class and physical engine mode.
DEVICE SELECTION
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 68911940f1d0..8c4280aa19b9 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -76,8 +76,16 @@ struct engine {
struct pmu_counter sema;
};
+struct engine_class {
+ unsigned int class;
+ const char *name;
+ unsigned int num_engines;
+};
+
struct engines {
unsigned int num_engines;
+ unsigned int num_classes;
+ struct engine_class *class;
unsigned int num_counters;
DIR *root;
int fd;
@@ -1118,6 +1126,8 @@ print_imc(struct engines *engines, double t, int lines,
int con_w, int con_h)
return lines;
}
+static bool class_view;
+
static int
print_engines_header(struct engines *engines, double t,
int lines, int con_w, int con_h)
@@ -1133,8 +1143,13 @@ print_engines_header(struct engines *engines, double t,
pops->open_struct("engines");
if (output_mode == INTERACTIVE) {
- const char *a = " ENGINE BUSY ";
const char *b = " MI_SEMA MI_WAIT";
+ const char *a;
+
+ if (class_view)
+ a = " ENGINES BUSY ";
+ else
+ a = " ENGINE BUSY ";
printf("\033[7m%s%*s%s\033[0m\n",
a, (int)(con_w - 1 - strlen(a) - strlen(b)),
@@ -1214,6 +1229,164 @@ print_engines_footer(struct engines *engines, double t,
return lines;
}
+static int class_cmp(const void *_a, const void *_b)
+{
+ const struct engine_class *a = _a;
+ const struct engine_class *b = _b;
+
+ return a->class - b->class;
+}
+
+static void init_engine_classes(struct engines *engines)
+{
+ struct engine_class *classes;
+ unsigned int i, num;
+ int max = -1;
+
+ for (i = 0; i < engines->num_engines; i++) {
+ struct engine *engine = engine_ptr(engines, i);
+
+ if ((int)engine->class > max)
+ max = engine->class;
+ }
+ assert(max >= 0);
+
+ num = max + 1;
+
+ classes = calloc(num, sizeof(*classes));
+ assert(classes);
+
+ for (i = 0; i < engines->num_engines; i++) {
+ struct engine *engine = engine_ptr(engines, i);
+
+ classes[engine->class].num_engines++;
+ }
+
+ for (i = 0; i < num; i++) {
+ classes[i].class = i;
+ classes[i].name = class_display_name(i);
+ }
+
+ qsort(classes, num, sizeof(*classes), class_cmp);
+
+ engines->num_classes = num;
+ engines->class = classes;
+}
+
+static void __pmu_sum(struct pmu_pair *dst, struct pmu_pair *src)
+{
+ dst->prev += src->prev;
+ dst->cur += src->cur;
+}
+
+static void __pmu_normalize(struct pmu_pair *val, unsigned int n)
+{
+ val->prev /= n;
+ val->cur /= n;
+}
+
+static struct engines *init_classes(struct engines *engines)
+{
+ struct engines *classes;
+ unsigned int i, j;
+
+ init_engine_classes(engines);
+
+ classes = calloc(1, sizeof(struct engines) +
+ engines->num_classes * sizeof(struct engine));
+ assert(classes);
+
+ classes->num_engines = engines->num_classes;
+ classes->num_classes = engines->num_classes;
+ classes->class = engines->class;
+
+ for (i = 0; i < engines->num_classes; i++) {
+ struct engine *engine = engine_ptr(classes, i);
+
+ engine->class = i;
+ engine->instance = -1;
+
+ if (!engines->class[i].num_engines)
+ continue;
+
+ engine->display_name = strdup(class_display_name(i));
+ assert(engine->display_name);
+ engine->short_name = strdup(class_short_name(i));
+ assert(engine->short_name);
+
+ for (j = 0; j < engines->num_engines; j++) {
+ struct
[Intel-gfx] [PATCH i-g-t 1/2] intel_gpu_top: Support exiting the tool by pressing 'q'
From: Tvrtko Ursulin
Analoguous to top(1) we can enable the user to exit from the tool by
pressing 'q' on the console.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 6
tools/intel_gpu_top.c | 77 +++
2 files changed, 70 insertions(+), 13 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index 5552e9699d26..2e0c3a05acc1 100644
--- a/man/intel_gpu_top.rst
+++ b/man/intel_gpu_top.rst
@@ -48,6 +48,12 @@ OPTIONS
-d
Select a specific GPU using supported filter.
+RUNTIME CONTROL
+===
+
+Supported keys:
+
+'q'Exit from the tool.
DEVICE SELECTION
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index dbd353673e55..68911940f1d0 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -23,24 +23,26 @@
#include "igt_device_scan.h"
-#include
-#include
-#include
-#include
#include
-#include
#include
-#include
-#include
-#include
+#include
+#include
#include
#include
-#include
-#include
-#include
-#include
#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
#include "igt_perf.h"
@@ -1246,6 +1248,54 @@ static char *tr_pmu_name(struct igt_device_card *card)
return device;
}
+static void interactive_stdin(void)
+{
+ struct termios termios = { };
+ int ret;
+
+ ret = fcntl(0, F_GETFL, NULL);
+ ret |= O_NONBLOCK;
+ ret = fcntl(0, F_SETFL, ret);
+ assert(ret == 0);
+
+ ret = tcgetattr(0, );
+ assert(ret == 0);
+
+ termios.c_lflag &= ~ICANON;
+ termios.c_cc[VMIN] = 1;
+ termios.c_cc[VTIME] = 0; /* Deciseconds only - we'll use poll. */
+
+ ret = tcsetattr(0, TCSAFLUSH, );
+ assert(ret == 0);
+}
+
+static void process_stdin(unsigned int timeout_us)
+{
+ struct pollfd p = { .fd = 0, .events = POLLIN };
+ int ret;
+
+ ret = poll(, 1, timeout_us / 1000);
+ if (ret <= 0) {
+ if (ret < 0)
+ stop_top = true;
+ return;
+ }
+
+ for (;;) {
+ char c;
+
+ ret = read(0, , 1);
+ if (ret <= 0)
+ break;
+
+ switch (c) {
+ case 'q':
+ stop_top = true;
+ break;
+ };
+ }
+}
+
int main(int argc, char **argv)
{
unsigned int period_us = DEFAULT_PERIOD_MS * 1000;
@@ -1315,6 +1365,7 @@ int main(int argc, char **argv)
switch (output_mode) {
case INTERACTIVE:
pops = _pops;
+ interactive_stdin();
break;
case STDOUT:
pops = _pops;
@@ -1427,7 +1478,7 @@ int main(int argc, char **argv)
if (stop_top)
break;
- usleep(period_us);
+ process_stdin(period_us);
}
free(codename);
--
2.25.1
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[Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness
An important property for multi-client systems is that each client gets
a 'fair' allotment of system time. (Where fairness is at the whim of the
context properties, such as priorities.) This test forks N independent
clients (albeit they happen to share a single vm), and does an equal
amount of work in client and asserts that they take an equal amount of
time.
Though we have never claimed to have a completely fair scheduler, that
is what is expected.
v2: igt_assert_f and more commentary; exclude vip from client stats,
include range of frame intervals from each individual client
v3: Write down what the test actually does!
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Ramalingam C
---
tests/i915/gem_exec_schedule.c | 797 +
1 file changed, 797 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index dd15b2ac7..8be5539aa 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2532,12 +2533,250 @@ static uint64_t div64_u64_round_up(uint64_t x,
uint64_t y)
return (x + y - 1) / y;
}
+static uint64_t ns_to_ctx_ticks(int i915, uint64_t ns)
+{
+ int f = read_timestamp_frequency(i915);
+ if (intel_gen(intel_get_drm_devid(i915)) == 11)
+ f = 1250; /* icl!!! are you feeling alright? CTX vs CS */
+ return div64_u64_round_up(ns * f, NSEC_PER_SEC);
+}
+
static uint64_t ticks_to_ns(int i915, uint64_t ticks)
{
return div64_u64_round_up(ticks * NSEC_PER_SEC,
read_timestamp_frequency(i915));
}
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2)MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1)MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1)MI_MATH_INSTR(0x481, op1)
+#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define MI_MATH_ORMI_MATH_INSTR(0x103, 0x0, 0x0)
+#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
+#define MI_MATH_STOREINV(op1, op2)MI_MATH_INSTR(0x580, op1, op2)
+/* Registers used as operands in MI_MATH_INSTR */
+#define MI_MATH_REG(x)(x)
+#define MI_MATH_REG_SRCA 0x20
+#define MI_MATH_REG_SRCB 0x21
+#define MI_MATH_REG_ACCU 0x31
+#define MI_MATH_REG_ZF0x32
+#define MI_MATH_REG_CF0x33
+
+#define MI_LOAD_REGISTER_REGMI_INSTR(0x2A, 1)
+
+static void delay(int i915,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint64_t addr,
+ uint64_t ns)
+{
+ const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
+ const uint32_t base = gem_engine_mmio_base(i915, e->name);
+#define CS_GPR(x) (base + 0x600 + 8 * (x))
+#define RUNTIME (base + 0x3a8)
+ enum { START_TS, NOW_TS };
+ uint32_t *map, *cs, *jmp;
+
+ igt_require(base);
+
+ /* Loop until CTX_TIMESTAMP - initial > @ns */
+
+ cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE);
+
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(START_TS) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG;
+ *cs++ = RUNTIME;
+ *cs++ = CS_GPR(START_TS);
+
+ while (offset_in_page(cs) & 63)
+ *cs++ = 0;
+ jmp = cs;
+
+ *cs++ = 0x5 << 23; /* MI_ARB_CHECK */
+
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(NOW_TS) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG;
+ *cs++ = RUNTIME;
+ *cs++ = CS_GPR(NOW_TS);
+
+ /* delta = now - start; inverted to match COND_BBE */
+ *cs++ = MI_MATH(4);
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
+ *cs++ = MI_MATH_SUB;
+ *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
+
+ /* Save delta for reading by COND_BBE */
+ *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
+ *cs++ = CS_GPR(NOW_TS);
+ *cs++ = addr + 4000;
+ *cs++ = addr >> 32;
+
+ /* Delay between SRM and COND_BBE to post the writes */
+ for (int n = 0; n < 8; n++) {
+ *cs++ =
[Intel-gfx] [kbuild] Re: [PATCH v4 09/11] drm/i915: migrate skl planes code new file
Hi Jani,
url:
https://github.com/0day-ci/linux/commits/Jani-Nikula/drm-i915-refactor-intel-display/20201216-194754
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-m001-20201216 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
Reported-by: Dan Carpenter
smatch warnings:
drivers/gpu/drm/i915/display/intel_gen9_plane.c:712 skl_update_scaler_plane()
error: we previously assumed 'fb' could be null (see line 696)
vim +/fb +712 drivers/gpu/drm/i915/display/intel_gen9_plane.c
44f5af76b2fd05e Dave Airlie 2020-12-16 672 int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
44f5af76b2fd05e Dave Airlie 2020-12-16 673 struct
intel_plane_state *plane_state)
44f5af76b2fd05e Dave Airlie 2020-12-16 674 {
44f5af76b2fd05e Dave Airlie 2020-12-16 675 struct intel_plane *intel_plane
=
44f5af76b2fd05e Dave Airlie 2020-12-16 676
to_intel_plane(plane_state->uapi.plane);
44f5af76b2fd05e Dave Airlie 2020-12-16 677 struct drm_i915_private
*dev_priv = to_i915(intel_plane->base.dev);
44f5af76b2fd05e Dave Airlie 2020-12-16 678 struct drm_framebuffer *fb =
plane_state->hw.fb;
44f5af76b2fd05e Dave Airlie 2020-12-16 679 int ret;
44f5af76b2fd05e Dave Airlie 2020-12-16 680 bool force_detach = !fb ||
!plane_state->uapi.visible;
44f5af76b2fd05e Dave Airlie 2020-12-16 681 bool need_scaler = false;
44f5af76b2fd05e Dave Airlie 2020-12-16 682
44f5af76b2fd05e Dave Airlie 2020-12-16 683 /* Pre-gen11 and SDR planes
always need a scaler for planar formats. */
44f5af76b2fd05e Dave Airlie 2020-12-16 684 if (!icl_is_hdr_plane(dev_priv,
intel_plane->id) &&
44f5af76b2fd05e Dave Airlie 2020-12-16 685 fb &&
intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
44f5af76b2fd05e Dave Airlie 2020-12-16 686 need_scaler = true;
44f5af76b2fd05e Dave Airlie 2020-12-16 687
44f5af76b2fd05e Dave Airlie 2020-12-16 688 ret =
skl_update_scaler(crtc_state, force_detach,
44f5af76b2fd05e Dave Airlie 2020-12-16 689
drm_plane_index(_plane->base),
44f5af76b2fd05e Dave Airlie 2020-12-16 690
_state->scaler_id,
44f5af76b2fd05e Dave Airlie 2020-12-16 691
drm_rect_width(_state->uapi.src) >> 16,
44f5af76b2fd05e Dave Airlie 2020-12-16 692
drm_rect_height(_state->uapi.src) >> 16,
44f5af76b2fd05e Dave Airlie 2020-12-16 693
drm_rect_width(_state->uapi.dst),
44f5af76b2fd05e Dave Airlie 2020-12-16 694
drm_rect_height(_state->uapi.dst),
44f5af76b2fd05e Dave Airlie 2020-12-16 695 fb ?
fb->format : NULL,
44f5af76b2fd05e Dave Airlie 2020-12-16 @696 fb ?
fb->modifier : 0,
^
This code and all previous code assumes that "fb" can be NULL.
44f5af76b2fd05e Dave Airlie 2020-12-16 697
need_scaler);
44f5af76b2fd05e Dave Airlie 2020-12-16 698
44f5af76b2fd05e Dave Airlie 2020-12-16 699 if (ret ||
plane_state->scaler_id < 0)
^^
Is this an error path? Should we set "ret = -EINVAL;" for this?
44f5af76b2fd05e Dave Airlie 2020-12-16 700 return ret;
44f5af76b2fd05e Dave Airlie 2020-12-16 701
44f5af76b2fd05e Dave Airlie 2020-12-16 702 /* check colorkey */
44f5af76b2fd05e Dave Airlie 2020-12-16 703 if (plane_state->ckey.flags) {
44f5af76b2fd05e Dave Airlie 2020-12-16 704
drm_dbg_kms(_priv->drm,
44f5af76b2fd05e Dave Airlie 2020-12-16 705
"[PLANE:%d:%s] scaling with color key not allowed",
44f5af76b2fd05e Dave Airlie 2020-12-16 706
intel_plane->base.base.id,
44f5af76b2fd05e Dave Airlie 2020-12-16 707
intel_plane->base.name);
44f5af76b2fd05e Dave Airlie 2020-12-16 708 return -EINVAL;
44f5af76b2fd05e Dave Airlie 2020-12-16 709 }
44f5af76b2fd05e Dave Airlie 2020-12-16 710
44f5af76b2fd05e Dave Airlie 2020-12-16 711 /* Check src format */
44f5af76b2fd05e Dave Airlie 2020-12-16 @712 switch (fb->format->format) {
^^
Unchecked dereference.
44f5af76b2fd05e Dave Airlie 2020-12-16 713 case DRM_FORMAT_RGB565:
44f5af76b2fd05e Dave Airlie 2020-12-16 714 case DRM_FORMAT_XBGR:
44f5af76b2fd05e Dave Airlie 2020-12-16 715 case DRM_FORMAT_XRGB:
44f5af76b2fd05e Dave Airlie 2020-12-16 716 case DRM_FORMAT_ABGR:
[Intel-gfx] [CI 2/7] drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb
In preparation for removing the has_initial_breadcrumb field, add a
helper function for the existing callers.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_timeline.c| 6 +++---
drivers/gpu/drm/i915/gt/intel_timeline.h| 6 ++
drivers/gpu/drm/i915/gt/selftest_timeline.c | 5 +++--
5 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 9c6f0ebfa3cf..ebf043692eef 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -354,7 +354,7 @@ int gen8_emit_init_breadcrumb(struct i915_request *rq)
u32 *cs;
GEM_BUG_ON(i915_request_has_initial_breadcrumb(rq));
- if (!i915_request_timeline(rq)->has_initial_breadcrumb)
+ if (!intel_timeline_has_initial_breadcrumb(i915_request_timeline(rq)))
return 0;
cs = intel_ring_begin(rq, 6);
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 4ea741f488a8..4bc80c50dbe9 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -979,7 +979,7 @@ static int ring_request_alloc(struct i915_request *request)
int ret;
GEM_BUG_ON(!intel_context_is_pinned(request->context));
- GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb);
+
GEM_BUG_ON(intel_timeline_has_initial_breadcrumb(i915_request_timeline(request)));
/*
* Flush enough space to reduce the likelihood of waiting after
@@ -1304,7 +1304,7 @@ int intel_ring_submission_setup(struct intel_engine_cs
*engine)
err = PTR_ERR(timeline);
goto err;
}
- GEM_BUG_ON(timeline->has_initial_breadcrumb);
+ GEM_BUG_ON(intel_timeline_has_initial_breadcrumb(timeline));
err = intel_timeline_pin(timeline, NULL);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 35b52913c190..37d439e7eb3c 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -447,14 +447,14 @@ void intel_timeline_exit(struct intel_timeline *tl)
static u32 timeline_advance(struct intel_timeline *tl)
{
GEM_BUG_ON(!atomic_read(>pin_count));
- GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
+ GEM_BUG_ON(tl->seqno & intel_timeline_has_initial_breadcrumb(tl));
- return tl->seqno += 1 + tl->has_initial_breadcrumb;
+ return tl->seqno += 1 + intel_timeline_has_initial_breadcrumb(tl);
}
static void timeline_rollback(struct intel_timeline *tl)
{
- tl->seqno -= 1 + tl->has_initial_breadcrumb;
+ tl->seqno -= 1 + intel_timeline_has_initial_breadcrumb(tl);
}
static noinline int
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h
b/drivers/gpu/drm/i915/gt/intel_timeline.h
index f502a619843f..0e5e9fdade5b 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -61,6 +61,12 @@ static inline void intel_timeline_put(struct intel_timeline
*timeline)
kref_put(>kref, __intel_timeline_free);
}
+static inline bool
+intel_timeline_has_initial_breadcrumb(const struct intel_timeline *tl)
+{
+ return tl->has_initial_breadcrumb;
+}
+
static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
u64 context, u32 seqno)
{
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index e4285d5a0360..a6ff9d1605aa 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -665,7 +665,7 @@ static int live_hwsp_wrap(void *arg)
if (IS_ERR(tl))
return PTR_ERR(tl);
- if (!tl->has_initial_breadcrumb || !tl->hwsp_cacheline)
+ if (!intel_timeline_has_initial_breadcrumb(tl) || !tl->hwsp_cacheline)
goto out_free;
err = intel_timeline_pin(tl, NULL);
@@ -1234,7 +1234,8 @@ static int live_hwsp_rollover_user(void *arg)
goto out;
tl = ce->timeline;
- if (!tl->has_initial_breadcrumb || !tl->hwsp_cacheline)
+ if (!intel_timeline_has_initial_breadcrumb(tl) ||
+ !tl->hwsp_cacheline)
goto out;
timeline_rollback(tl);
--
2.20.1
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[Intel-gfx] [CI 7/7] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines
When we are not using semaphores with a context/engine, we can simply
reuse the same seqno location across wraps, but we still require each
timeline to have its own address. For LRC submission, each context is
prefixed by a per-process HWSP, which provides us with a unique location
for each context-local timeline. A shared timeline that is common to
multiple contexts will continue to use a separate page.
This enables us to create position invariant contexts should we feel the
need to relocate them.
Initially they are automatically used by Broadwell/Braswell as they do
not require independent timelines.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Reviewed-by: Matthew Brost
---
.../drm/i915/gt/intel_execlists_submission.c | 37 +++
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 3ecf3fbcc62d..18a4a7bb379b 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -4767,6 +4767,14 @@ static struct intel_timeline *pinned_timeline(struct
intel_context *ce)
page_unmask_bits(tl));
}
+static struct intel_timeline *pphwsp_timeline(struct intel_context *ce,
+ struct i915_vma *state)
+{
+ return __intel_timeline_create(ce->engine->gt, state,
+ I915_GEM_HWS_SEQNO_ADDR |
+ INTEL_TIMELINE_RELATIVE_CONTEXT);
+}
+
static int __execlists_context_alloc(struct intel_context *ce,
struct intel_engine_cs *engine)
{
@@ -4797,6 +4805,16 @@ static int __execlists_context_alloc(struct
intel_context *ce,
goto error_deref_obj;
}
+ ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
+ if (IS_ERR(ring)) {
+ ret = PTR_ERR(ring);
+ goto error_deref_obj;
+ }
+
+ ret = populate_lr_context(ce, ctx_obj, engine, ring);
+ if (ret)
+ goto error_ring_free;
+
if (!page_mask_bits(ce->timeline)) {
struct intel_timeline *tl;
@@ -4806,29 +4824,18 @@ static int __execlists_context_alloc(struct
intel_context *ce,
*/
if (unlikely(ce->timeline))
tl = pinned_timeline(ce);
- else
+ else if (intel_engine_has_semaphores(engine))
tl = intel_timeline_create(engine->gt);
+ else
+ tl = pphwsp_timeline(ce, vma);
if (IS_ERR(tl)) {
ret = PTR_ERR(tl);
- goto error_deref_obj;
+ goto error_ring_free;
}
ce->timeline = tl;
}
- ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
- if (IS_ERR(ring)) {
- ret = PTR_ERR(ring);
- goto error_deref_obj;
- }
-
- ret = populate_lr_context(ce, ctx_obj, engine, ring);
- if (ret) {
- drm_dbg(>i915->drm,
- "Failed to populate LRC: %d\n", ret);
- goto error_ring_free;
- }
-
ce->ring = ring;
ce->state = vma;
--
2.20.1
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[Intel-gfx] [CI 3/7] drm/i915/gt: Track timeline GGTT offset separately from subpage offset
Currently we know that the timeline status page is at most a page in
size, and so we can preserve the lower 12bits of the offset when
relocating the status page in the GGTT. If we want to use a larger
object, such as the context state, we may not necessarily use a position
within the first page and so need more than 12b.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_timeline.c | 17 +++--
drivers/gpu/drm/i915/gt/intel_timeline_types.h | 1 +
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c| 16
8 files changed, 23 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
index ce38d1bcaba3..2f59dd3bdc18 100644
--- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
@@ -161,7 +161,7 @@ u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32
*cs)
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_CS_STALL);
- *cs++ = i915_request_active_timeline(rq)->hwsp_offset |
+ *cs++ = i915_request_active_timeline(rq)->ggtt_offset |
PIPE_CONTROL_GLOBAL_GTT;
*cs++ = rq->fence.seqno;
@@ -359,7 +359,7 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32
*cs)
PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_CS_STALL);
- *cs++ = i915_request_active_timeline(rq)->hwsp_offset;
+ *cs++ = i915_request_active_timeline(rq)->ggtt_offset;
*cs++ = rq->fence.seqno;
*cs++ = MI_USER_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index ebf043692eef..ed88dc4de72c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -346,7 +346,7 @@ static u32 hwsp_offset(const struct i915_request *rq)
if (cl)
return cl->ggtt_offset;
- return rcu_dereference_protected(rq->timeline, 1)->hwsp_offset;
+ return rcu_dereference_protected(rq->timeline, 1)->ggtt_offset;
}
int gen8_emit_init_breadcrumb(struct i915_request *rq)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d2f6199de730..32cc03205fda 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1346,7 +1346,7 @@ static int print_ring(char *buf, int sz, struct
i915_request *rq)
len = scnprintf(buf, sz,
"ring:{start:%08x, hwsp:%08x, seqno:%08x,
runtime:%llums}, ",
i915_ggtt_offset(rq->ring->vma),
- tl ? tl->hwsp_offset : 0,
+ tl ? tl->ggtt_offset : 0,
hwsp_seqno(rq),
DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1000 * 1000));
@@ -1685,7 +1685,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (tl) {
drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
- tl->hwsp_offset);
+ tl->ggtt_offset);
intel_timeline_put(tl);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 37d439e7eb3c..ad38c19625e8 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -357,13 +357,11 @@ int intel_timeline_pin(struct intel_timeline *tl, struct
i915_gem_ww_ctx *ww)
if (err)
return err;
- tl->hwsp_offset =
- i915_ggtt_offset(tl->hwsp_ggtt) +
- offset_in_page(tl->hwsp_offset);
+ tl->ggtt_offset = i915_ggtt_offset(tl->hwsp_ggtt) + tl->hwsp_offset;
GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
-tl->fence_context, tl->hwsp_offset);
+tl->fence_context, tl->ggtt_offset);
- cacheline_acquire(tl->hwsp_cacheline, tl->hwsp_offset);
+ cacheline_acquire(tl->hwsp_cacheline, tl->ggtt_offset);
if (atomic_fetch_inc(>pin_count)) {
cacheline_release(tl->hwsp_cacheline);
__i915_vma_unpin(tl->hwsp_ggtt);
@@ -531,14 +529,13 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
vaddr = page_mask_bits(cl->vaddr);
tl->hwsp_offset = cacheline * CACHELINE_BYTES;
- tl->hwsp_seqno =
-
[Intel-gfx] [CI 5/7] drm/i915/gt: Use indices for writing into relative timelines
Relative timelines are relative to either the global or per-process
HWSP, and so we can replace the absolute addressing with store-index
variants for position invariance.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 98 +---
drivers/gpu/drm/i915/gt/intel_timeline.h | 12 +++
2 files changed, 82 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index ed88dc4de72c..4f78004f0087 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -502,7 +502,19 @@ gen8_emit_fini_breadcrumb_tail(struct i915_request *rq,
u32 *cs)
static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
{
- return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
+ struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
+ unsigned int flags = MI_FLUSH_DW_OP_STOREDW;
+ u32 offset = hwsp_offset(rq);
+
+ if (intel_timeline_is_relative(tl)) {
+ offset = offset_in_page(offset);
+ flags |= MI_FLUSH_DW_STORE_INDEX;
+ }
+ GEM_BUG_ON(offset & 7);
+ if (!intel_timeline_in_context(tl))
+ offset |= MI_FLUSH_DW_USE_GTT;
+
+ return __gen8_emit_flush_dw(cs, rq->fence.seqno, offset, flags);
}
u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
@@ -512,6 +524,18 @@ u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request
*rq, u32 *cs)
u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
+ struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
+ unsigned int flags = PIPE_CONTROL_FLUSH_ENABLE | PIPE_CONTROL_CS_STALL;
+ u32 offset = hwsp_offset(rq);
+
+ if (intel_timeline_is_relative(tl)) {
+ offset = offset_in_page(offset);
+ flags |= PIPE_CONTROL_STORE_DATA_INDEX;
+ }
+ GEM_BUG_ON(offset & 7);
+ if (!intel_timeline_in_context(tl))
+ flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
cs = gen8_emit_pipe_control(cs,
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
@@ -519,26 +543,33 @@ u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request
*rq, u32 *cs)
0);
/* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
- cs = gen8_emit_ggtt_write_rcs(cs,
- rq->fence.seqno,
- hwsp_offset(rq),
- PIPE_CONTROL_FLUSH_ENABLE |
- PIPE_CONTROL_CS_STALL);
+ cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset, 0, flags);
return gen8_emit_fini_breadcrumb_tail(rq, cs);
}
u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
- cs = gen8_emit_ggtt_write_rcs(cs,
- rq->fence.seqno,
- hwsp_offset(rq),
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_TILE_CACHE_FLUSH |
- PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_DC_FLUSH_ENABLE |
- PIPE_CONTROL_FLUSH_ENABLE);
+ struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
+ u32 offset = hwsp_offset(rq);
+ unsigned int flags;
+
+ flags = (PIPE_CONTROL_CS_STALL |
+PIPE_CONTROL_TILE_CACHE_FLUSH |
+PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+PIPE_CONTROL_DC_FLUSH_ENABLE |
+PIPE_CONTROL_FLUSH_ENABLE);
+
+ if (intel_timeline_is_relative(tl)) {
+ offset = offset_in_page(offset);
+ flags |= PIPE_CONTROL_STORE_DATA_INDEX;
+ }
+ GEM_BUG_ON(offset & 7);
+ if (!intel_timeline_in_context(tl))
+ flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+ cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset, 0, flags);
return gen8_emit_fini_breadcrumb_tail(rq, cs);
}
@@ -601,19 +632,30 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request
*rq, u32 *cs)
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
- cs = gen12_emit_ggtt_write_rcs(cs,
- rq->fence.seqno,
- hwsp_offset(rq),
- PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_TILE_CACHE_FLUSH |
[Intel-gfx] [CI 6/7] drm/i915/selftests: Exercise relative timeline modes
A quick test to verify that the backend accepts each type of timeline
and can use them to track and control request emission.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 105
1 file changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 6f355c8a4f81..d91ee4aa4b98 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -1364,9 +1364,114 @@ static int live_hwsp_recycle(void *arg)
return err;
}
+static int live_hwsp_relative(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ /*
+* Check backend support for different timeline modes.
+*/
+
+ for_each_engine(engine, gt, id) {
+ enum intel_timeline_mode mode;
+
+ if (!engine->schedule)
+ continue;
+
+ for (mode = INTEL_TIMELINE_ABSOLUTE;
+mode <= INTEL_TIMELINE_RELATIVE_ENGINE;
+mode++) {
+ struct intel_timeline *tl;
+ struct i915_request *rq;
+ struct intel_context *ce;
+ const char *msg;
+ int err;
+
+ if (mode == INTEL_TIMELINE_RELATIVE_CONTEXT &&
+ !HAS_EXECLISTS(gt->i915))
+ continue;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_alloc_state(ce);
+ if (err) {
+ intel_context_put(ce);
+ return err;
+ }
+
+ switch (mode) {
+ case INTEL_TIMELINE_ABSOLUTE:
+ tl = intel_timeline_create(gt);
+ msg = "local";
+ break;
+
+ case INTEL_TIMELINE_RELATIVE_CONTEXT:
+ tl = __intel_timeline_create(gt,
+ce->state,
+
INTEL_TIMELINE_RELATIVE_CONTEXT |
+0x400);
+ msg = "ppHWSP";
+ break;
+
+ case INTEL_TIMELINE_RELATIVE_ENGINE:
+ tl = __intel_timeline_create(gt,
+
engine->status_page.vma,
+0x400);
+ msg = "HWSP";
+ break;
+ default:
+ continue;
+ }
+ if (IS_ERR(tl)) {
+ intel_context_put(ce);
+ return PTR_ERR(tl);
+ }
+
+ pr_info("Testing %s timeline on %s\n",
+ msg, engine->name);
+
+ intel_timeline_put(ce->timeline);
+ ce->timeline = tl;
+
+ err = intel_timeline_pin(tl, NULL);
+ if (err) {
+ intel_context_put(ce);
+ return err;
+ }
+ tl->seqno = 0xc000;
+ WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);
+ intel_timeline_unpin(tl);
+
+ rq = intel_context_create_request(ce);
+ intel_context_put(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ GEM_BUG_ON(rcu_access_pointer(rq->timeline) != tl);
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0) {
+ i915_request_put(rq);
+ return -EIO;
+ }
+
+ i915_request_put(rq);
+ }
+ }
+
+ return 0;
+}
+
int intel_timeline_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
+ SUBTEST(live_hwsp_relative),
SUBTEST(live_hwsp_recycle),
SUBTEST(live_hwsp_engine),
SUBTEST(live_hwsp_alternate),
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
[Intel-gfx] [CI 4/7] drm/i915/gt: Add timeline "mode"
Explicitly differentiate between the absolute and relative timelines,
and the global HWSP and ppHWSP relative offsets. When using a timeline
that is relative to a known status page, we can replace the absolute
addressing in the commands with indexed variants.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 21 ---
drivers/gpu/drm/i915/gt/intel_timeline.h | 2 +-
.../gpu/drm/i915/gt/intel_timeline_types.h| 10 +++--
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index ad38c19625e8..139e1c270f4f 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -229,7 +229,6 @@ static int intel_timeline_init(struct intel_timeline
*timeline,
timeline->gt = gt;
- timeline->has_initial_breadcrumb = !hwsp;
timeline->hwsp_cacheline = NULL;
if (!hwsp) {
@@ -246,13 +245,29 @@ static int intel_timeline_init(struct intel_timeline
*timeline,
return PTR_ERR(cl);
}
+ timeline->mode = INTEL_TIMELINE_ABSOLUTE;
timeline->hwsp_cacheline = cl;
timeline->hwsp_offset = cacheline * CACHELINE_BYTES;
vaddr = page_mask_bits(cl->vaddr);
} else {
- timeline->hwsp_offset = offset;
- vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
+ int preferred;
+
+ if (offset & INTEL_TIMELINE_RELATIVE_CONTEXT) {
+ timeline->mode = INTEL_TIMELINE_RELATIVE_CONTEXT;
+ timeline->hwsp_offset =
+ offset & ~INTEL_TIMELINE_RELATIVE_CONTEXT;
+ preferred = i915_coherent_map_type(gt->i915);
+ } else {
+ timeline->mode = INTEL_TIMELINE_RELATIVE_ENGINE;
+ timeline->hwsp_offset = offset;
+ preferred = I915_MAP_WB;
+ }
+
+ vaddr = i915_gem_object_pin_map(hwsp->obj,
+ preferred | I915_MAP_OVERRIDE);
+ if (IS_ERR(vaddr))
+ vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WC);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h
b/drivers/gpu/drm/i915/gt/intel_timeline.h
index 0e5e9fdade5b..6e738a85beda 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -64,7 +64,7 @@ static inline void intel_timeline_put(struct intel_timeline
*timeline)
static inline bool
intel_timeline_has_initial_breadcrumb(const struct intel_timeline *tl)
{
- return tl->has_initial_breadcrumb;
+ return tl->mode == INTEL_TIMELINE_ABSOLUTE;
}
static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
index f187c5aac11c..3c1ab901b702 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
@@ -20,6 +20,12 @@ struct i915_syncmap;
struct intel_gt;
struct intel_timeline_hwsp;
+enum intel_timeline_mode {
+ INTEL_TIMELINE_ABSOLUTE = 0,
+ INTEL_TIMELINE_RELATIVE_CONTEXT = BIT(0),
+ INTEL_TIMELINE_RELATIVE_ENGINE = BIT(1),
+};
+
struct intel_timeline {
u64 fence_context;
u32 seqno;
@@ -45,6 +51,8 @@ struct intel_timeline {
atomic_t pin_count;
atomic_t active_count;
+ enum intel_timeline_mode mode;
+
const u32 *hwsp_seqno;
struct i915_vma *hwsp_ggtt;
u32 hwsp_offset;
@@ -52,8 +60,6 @@ struct intel_timeline {
struct intel_timeline_cacheline *hwsp_cacheline;
- bool has_initial_breadcrumb;
-
/**
* List of breadcrumbs associated with GPU requests currently
* outstanding.
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/7] drm/i915/gt: Track all timelines created using the HWSP
We assume that the contents of the HWSP are lost across suspend, and so
upon resume we must restore critical values such as the timeline seqno.
Keep track of every timeline allocated that uses the HWSP as its storage
and so we can then reset all seqno values by walking that list.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 32 +
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 7
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
.../drm/i915/gt/intel_execlists_submission.c | 11 --
.../gpu/drm/i915/gt/intel_ring_submission.c | 35 +++
drivers/gpu/drm/i915/gt/intel_timeline.c | 19 ++
drivers/gpu/drm/i915/gt/intel_timeline.h | 9 ++---
.../gpu/drm/i915/gt/intel_timeline_types.h| 2 ++
8 files changed, 101 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 97ceaf7116e8..d2f6199de730 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -648,6 +648,8 @@ static int init_status_page(struct intel_engine_cs *engine)
void *vaddr;
int ret;
+ INIT_LIST_HEAD(>status_page.timelines);
+
/*
* Though the HWS register does support 36bit addresses, historically
* we have had hangs and corruption reported due to wild writes if
@@ -830,6 +832,21 @@ create_pinned_context(struct intel_engine_cs *engine,
return ce;
}
+static void destroy_pinned_context(struct intel_context *ce)
+{
+ struct intel_engine_cs *engine = ce->engine;
+ struct i915_vma *hwsp = engine->status_page.vma;
+
+ GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
+
+ mutex_lock(>vm->mutex);
+ list_del(>timeline->engine_link);
+ mutex_unlock(>vm->mutex);
+
+ intel_context_unpin(ce);
+ intel_context_put(ce);
+}
+
static struct intel_context *
create_kernel_context(struct intel_engine_cs *engine)
{
@@ -926,7 +943,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
GEM_BUG_ON(!list_empty(>active.requests));
tasklet_kill(>execlists.tasklet); /* flush the callback */
- cleanup_status_page(engine);
intel_breadcrumbs_free(engine->breadcrumbs);
intel_engine_fini_retire(engine);
@@ -935,11 +951,11 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
if (engine->default_state)
fput(engine->default_state);
- if (engine->kernel_context) {
- intel_context_unpin(engine->kernel_context);
- intel_context_put(engine->kernel_context);
- }
+ if (engine->kernel_context)
+ destroy_pinned_context(engine->kernel_context);
+
GEM_BUG_ON(!llist_empty(>barrier_tasks));
+ cleanup_status_page(engine);
intel_wa_list_free(>ctx_wa_list);
intel_wa_list_free(>wa_list);
@@ -1274,8 +1290,12 @@ void intel_engines_reset_default_submission(struct
intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, gt, id)
+ for_each_engine(engine, gt, id) {
+ if (engine->sanitize)
+ engine->sanitize(engine);
+
engine->set_default_submission(engine);
+ }
}
bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 499b09cb4acf..93028beb2ce0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -60,6 +60,13 @@ static int __engine_unpark(struct intel_wakeref *wf)
/* Scrub the context image after our loss of control */
ce->ops->reset(ce);
+
+ CE_TRACE(ce, "reset { seqno:%x, *hwsp:%x, ring:%x }\n",
+ce->timeline->seqno,
+READ_ONCE(*ce->timeline->hwsp_seqno),
+ce->ring->emit);
+ GEM_BUG_ON(ce->timeline->seqno !=
+ READ_ONCE(*ce->timeline->hwsp_seqno));
}
if (engine->unpark)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index ee6312601c56..02ee1e736982 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -68,6 +68,7 @@ typedef u8 intel_engine_mask_t;
#define ALL_ENGINES ((intel_engine_mask_t)~0ul)
struct intel_hw_status_page {
+ struct list_head timelines;
struct i915_vma *vma;
u32 *addr;
};
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index dcecc2887891..3ecf3fbcc62d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++
Re: [Intel-gfx] [PATCH v6 2/5] drm/i915/display/psr: Use plane damage clips to calculate damaged area
On Wed, 2020-12-16 at 14:10 +, Mun, Gwan-gyeong wrote:
> On Wed, 2020-12-16 at 05:17 -0800, Souza, Jose wrote:
> > On Wed, 2020-12-16 at 10:29 +, Mun, Gwan-gyeong wrote:
> > > On Tue, 2020-12-15 at 05:14 -0800, Souza, Jose wrote:
> > > > On Tue, 2020-12-15 at 13:02 +, Mun, Gwan-gyeong wrote:
> > > > > On Mon, 2020-12-14 at 09:49 -0800, José Roberto de Souza wrote:
> > > > > > Now using plane damage clips property to calcualte the
> > > > > > damaged
> > > > > > area.
> > > > > > Selective fetch only supports one region to be fetched so
> > > > > > software
> > > > > > needs to calculate a bounding box around all damage clips.
> > > > > >
> > > > > > Now that we are not complete fetching each plane, there is
> > > > > > another
> > > > > > loop needed as all the plane areas that intersect with the
> > > > > > pipe
> > > > > > damaged area needs to be fetched from memory so the complete
> > > > > > blending
> > > > > > of all planes can happen.
> > > > > >
> > > > > Hi,
> > > > > > v2:
> > > > > > - do not shifthing new_plane_state->uapi.dst only src is in
> > > > > > 16.16
> > > > > Typo on commit message. shifthing -> shifting
> > > > > > format
> > > > > >
> > > > > > v4:
> > > > > > - setting plane selective fetch area using the whole pipe
> > > > > > damage
> > > > > > area
> > > > > > - mark the whole plane area damaged if plane visibility or
> > > > > > alpha
> > > > > > changed
> > > > > >
> > > > > > v5:
> > > > > > - taking in consideration src.y1 in the damage coordinates
> > > > > > - adding to the pipe damaged area planes that were visible
> > > > > > but
> > > > > > are
> > > > > > invisible in the new state
> > > > > >
> > > > > > v6:
> > > > > > - consider old state plane coordinates when visibility
> > > > > > changes or
> > > > > > it
> > > > > > moved to calculate damaged area
> > > > > > - remove from damaged area the portion not in src clip
> > > > > >
> > > > > > Cc: Ville Syrjälä
> > > > > > Cc: Gwan-gyeong Mun
> > > > > > Signed-off-by: José Roberto de Souza
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 98
> > > > > > +-
> > > > > > --
> > > > > > 1 file changed, 86 insertions(+), 12 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index d9a395c486d3..7daed098fa74 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -1269,8 +1269,8 @@ int intel_psr2_sel_fetch_update(struct
> > > > > > intel_atomic_state *state,
> > > > > > struct intel_crtc *crtc)
> > > > > > {
> > > > > > struct intel_crtc_state *crtc_state =
> > > > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > > > > + struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 =
> > > > > > INT_MAX,
> > > > > > .y2 = -1 };
> > > > > > struct intel_plane_state *new_plane_state,
> > > > > > *old_plane_state;
> > > > > > - struct drm_rect pipe_clip = { .y1 = -1 };
> > > > > > struct intel_plane *plane;
> > > > > > bool full_update = false;
> > > > > > int i, ret;
> > > > > > @@ -1282,9 +1282,17 @@ int intel_psr2_sel_fetch_update(struct
> > > > > > intel_atomic_state *state,
> > > > > > if (ret)
> > > > > > return ret;
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > + /*
> > > > > > +* Calculate minimal selective fetch area of each plane
> > > > > > and
> > > > > > calculate
> > > > > > +* the pipe damaged area.
> > > > > > +* In the next loop the plane selective fetch area will
> > > > > > actually be set
> > > > > > +* using whole pipe damaged area.
> > > > > > +*/
> > > > > > for_each_oldnew_intel_plane_in_state(state, plane,
> > > > > > old_plane_state,
> > > > > > new_plane_state,
> > > > > > i) {
> > > > > > - struct drm_rect *sel_fetch_area, temp;
> > > > > > + struct drm_rect src, damaged_area = { .x1 = 0,
> > > > > > .y1 =
> > > > > > -1, .x2 = INT_MAX, .y2 = -1 };
> > > > > > + struct drm_mode_rect *damaged_clips;
> > > > > > + u32 num_clips, j;
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > if (new_plane_state->uapi.crtc != crtc_state-
> > > > > > > uapi.crtc)
> > > > > > continue;
> > > > > > @@ -1300,23 +1308,89 @@ int
> > > > > > intel_psr2_sel_fetch_update(struct
> > > > > > intel_atomic_state *state,
> > > > > > break;
> > > > > > }
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > - if (!new_plane_state->uapi.visible)
> > > > > >
[Intel-gfx] [PATCH -next] gpu/drm/i915: convert comma to semicolon
Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun --- drivers/gpu/drm/i915/intel_region_lmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c index 40d8f1a95df6..3f3a8925fe36 100644 --- a/drivers/gpu/drm/i915/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/intel_region_lmem.c @@ -115,7 +115,7 @@ intel_setup_fake_lmem(struct drm_i915_private *i915) /* Your mappable aperture belongs to me now! */ mappable_end = pci_resource_len(pdev, 2); - io_start = pci_resource_start(pdev, 2), + io_start = pci_resource_start(pdev, 2); start = i915->params.fake_lmem_start; mem = intel_memory_region_create(i915, -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
== Series Details == Series: drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h URL : https://patchwork.freedesktop.org/series/85001/ State : success == Summary == CI Bug Log - changes from CI_DRM_9491 -> Patchwork_19159 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/index.html Known issues Here are the changes found in Patchwork_19159 that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-ilk-650: [PASS][1] -> [DMESG-WARN][2] ([i915#164]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-ilk-650/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/fi-ilk-650/igt@core_hotunp...@unbind-rebind.html * igt@prime_vgem@basic-userptr: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-tgl-y/igt@prime_v...@basic-userptr.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/fi-tgl-y/igt@prime_v...@basic-userptr.html Possible fixes * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_selftest@live@execlists: - fi-apl-guc: [DMESG-WARN][7] ([i915#1037]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@i915_selftest@l...@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/fi-apl-guc/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_mocs: - fi-apl-guc: [DMESG-WARN][9] -> [PASS][10] +15 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@i915_selftest@live@gt_mocs.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/fi-apl-guc/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@ring_submission: - fi-apl-guc: [DMESG-WARN][11] ([i915#203]) -> [PASS][12] +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@i915_selftest@live@ring_submission.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/fi-apl-guc/igt@i915_selftest@live@ring_submission.html [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037 [i915#164]: https://gitlab.freedesktop.org/drm/intel/issues/164 [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus Build changes - * Linux: CI_DRM_9491 -> Patchwork_19159 CI-20190529: 20190529 CI_DRM_9491: e616452578fec8ec2a04faf0090404a40ce1811c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5904: 2e5ad6b45c20c5b354325e0c818e25ba6087ecc2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19159: ad3765dc76e141dae44311e8aa95b56577cf6dc8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ad3765dc76e1 drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19159/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v6,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/84997/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9490_full -> Patchwork_19155_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19155_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@perf_pmu@rc6-suspend}:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-skl10/igt@perf_...@rc6-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-skl1/igt@perf_...@rc6-suspend.html
Known issues
Here are the changes found in Patchwork_19155_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-parallel:
- shard-skl: NOTRUN -> [TIMEOUT][3] ([i915#1729])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-skl2/igt@gem_exec_re...@basic-parallel.html
* igt@gem_exec_whisper@basic-queues-priority:
- shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#118] / [i915#95])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-glk3/igt@gem_exec_whis...@basic-queues-priority.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-glk2/igt@gem_exec_whis...@basic-queues-priority.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][6] -> [DMESG-WARN][7] ([i915#1436] /
[i915#716])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-skl5/igt@gen9_exec_pa...@allowed-single.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-skl3/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_pm_backlight@bad-brightness:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271]) +11 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-glk3/igt@i915_pm_backli...@bad-brightness.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][9] ([i915#454])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-skl2/igt@i915_pm...@dc6-dpms.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2597])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-tglb7/igt@kms_async_fl...@test-time-stamp.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-tglb7/igt@kms_async_fl...@test-time-stamp.html
* igt@kms_ccs@pipe-c-crc-primary-basic:
- shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111304])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-skl2/igt@kms_...@pipe-c-crc-primary-basic.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-glk3/igt@kms_chamel...@dp-hpd-storm-disable.html
* igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +2
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-skl2/igt@kms_color_chamel...@pipe-b-ctm-red-to-blue.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2346])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-tglb5/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-tglb8/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#79])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-skl10/igt@kms_...@bpc-switch.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/shard-skl1/igt@kms_...@bpc-switch.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#533])
[21]:
Re: [Intel-gfx] [PATCH v6 2/5] drm/i915/display/psr: Use plane damage clips to calculate damaged area
On Wed, 2020-12-16 at 05:17 -0800, Souza, Jose wrote:
> On Wed, 2020-12-16 at 10:29 +, Mun, Gwan-gyeong wrote:
> > On Tue, 2020-12-15 at 05:14 -0800, Souza, Jose wrote:
> > > On Tue, 2020-12-15 at 13:02 +, Mun, Gwan-gyeong wrote:
> > > > On Mon, 2020-12-14 at 09:49 -0800, José Roberto de Souza wrote:
> > > > > Now using plane damage clips property to calcualte the
> > > > > damaged
> > > > > area.
> > > > > Selective fetch only supports one region to be fetched so
> > > > > software
> > > > > needs to calculate a bounding box around all damage clips.
> > > > >
> > > > > Now that we are not complete fetching each plane, there is
> > > > > another
> > > > > loop needed as all the plane areas that intersect with the
> > > > > pipe
> > > > > damaged area needs to be fetched from memory so the complete
> > > > > blending
> > > > > of all planes can happen.
> > > > >
> > > > Hi,
> > > > > v2:
> > > > > - do not shifthing new_plane_state->uapi.dst only src is in
> > > > > 16.16
> > > > Typo on commit message. shifthing -> shifting
> > > > > format
> > > > >
> > > > > v4:
> > > > > - setting plane selective fetch area using the whole pipe
> > > > > damage
> > > > > area
> > > > > - mark the whole plane area damaged if plane visibility or
> > > > > alpha
> > > > > changed
> > > > >
> > > > > v5:
> > > > > - taking in consideration src.y1 in the damage coordinates
> > > > > - adding to the pipe damaged area planes that were visible
> > > > > but
> > > > > are
> > > > > invisible in the new state
> > > > >
> > > > > v6:
> > > > > - consider old state plane coordinates when visibility
> > > > > changes or
> > > > > it
> > > > > moved to calculate damaged area
> > > > > - remove from damaged area the portion not in src clip
> > > > >
> > > > > Cc: Ville Syrjälä
> > > > > Cc: Gwan-gyeong Mun
> > > > > Signed-off-by: José Roberto de Souza
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_psr.c | 98
> > > > > +-
> > > > > --
> > > > > 1 file changed, 86 insertions(+), 12 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index d9a395c486d3..7daed098fa74 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -1269,8 +1269,8 @@ int intel_psr2_sel_fetch_update(struct
> > > > > intel_atomic_state *state,
> > > > > struct intel_crtc *crtc)
> > > > > {
> > > > > struct intel_crtc_state *crtc_state =
> > > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > > > + struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 =
> > > > > INT_MAX,
> > > > > .y2 = -1 };
> > > > > struct intel_plane_state *new_plane_state,
> > > > > *old_plane_state;
> > > > > - struct drm_rect pipe_clip = { .y1 = -1 };
> > > > > struct intel_plane *plane;
> > > > > bool full_update = false;
> > > > > int i, ret;
> > > > > @@ -1282,9 +1282,17 @@ int intel_psr2_sel_fetch_update(struct
> > > > > intel_atomic_state *state,
> > > > > if (ret)
> > > > > return ret;
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > + /*
> > > > > + * Calculate minimal selective fetch area of each plane
> > > > > and
> > > > > calculate
> > > > > + * the pipe damaged area.
> > > > > + * In the next loop the plane selective fetch area will
> > > > > actually be set
> > > > > + * using whole pipe damaged area.
> > > > > + */
> > > > > for_each_oldnew_intel_plane_in_state(state, plane,
> > > > > old_plane_state,
> > > > >new_plane_state,
> > > > > i) {
> > > > > - struct drm_rect *sel_fetch_area, temp;
> > > > > + struct drm_rect src, damaged_area = { .x1 = 0,
> > > > > .y1 =
> > > > > -1, .x2 = INT_MAX, .y2 = -1 };
> > > > > + struct drm_mode_rect *damaged_clips;
> > > > > + u32 num_clips, j;
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > if (new_plane_state->uapi.crtc != crtc_state-
> > > > > > uapi.crtc)
> > > > > continue;
> > > > > @@ -1300,23 +1308,89 @@ int
> > > > > intel_psr2_sel_fetch_update(struct
> > > > > intel_atomic_state *state,
> > > > > break;
> > > > > }
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > - if (!new_plane_state->uapi.visible)
> > > > > - continue;
> > > > > + drm_rect_convert_16_16_to_regular(_plane_st
> > > > > ate-
> > > > > > uapi.src, );
> > > > > + damaged_clips =
> > > > > drm_plane_get_damage_clips(_plane_state->uapi);
> > > > > + num_clips =
> > > > > drm_plane_get_damage_clips_count(_plane_state->uapi);
> > > > >
> > > > >
> > > > >
> > > > >
> >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
== Series Details == Series: drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h URL : https://patchwork.freedesktop.org/series/85001/ State : warning == Summary == $ dim checkpatch origin/drm-tip ad3765dc76e1 drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h -:117: CHECK:LINE_SPACING: Please don't use multiple blank lines #117: FILE: drivers/gpu/drm/i915/gt/gen8_engine_cs.h:41: + total: 0 errors, 0 warnings, 1 checks, 370 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v7,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details ==
Series: series starting with [v7,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/85000/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9491 -> Patchwork_19158
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19158:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}: [SKIP][1] ([fdo#110189]) -> [SKIP][2] +3 similar
issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
Known issues
Here are the changes found in Patchwork_19158 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u: [PASS][3] -> [DMESG-WARN][4] ([i915#2605])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-tgl-y/igt@prime_v...@basic-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/fi-tgl-y/igt@prime_v...@basic-read.html
Possible fixes
* igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
* igt@i915_selftest@live@execlists:
- fi-apl-guc: [DMESG-WARN][9] ([i915#1037]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/fi-apl-guc/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_mocs:
- fi-apl-guc: [DMESG-WARN][11] -> [PASS][12] +15 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@i915_selftest@live@gt_mocs.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/fi-apl-guc/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@ring_submission:
- fi-apl-guc: [DMESG-WARN][13] ([i915#203]) -> [PASS][14] +8
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@i915_selftest@live@ring_submission.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/fi-apl-guc/igt@i915_selftest@live@ring_submission.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 39)
--
Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_9491 -> Patchwork_19158
CI-20190529: 20190529
CI_DRM_9491: e616452578fec8ec2a04faf0090404a40ce1811c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5904: 2e5ad6b45c20c5b354325e0c818e25ba6087ecc2 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19158: 91675f0332c29c6c78ad6e2f87910eeb827f2b97 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
91675f0332c2 drm/i915/display: Support Multiple Transcoders' PSR status on
debugfs
a40676934ae8 drm/i915/display: Support PSR Multiple Transcoders
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19158/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
Reduce the pollution of intel_engine.h by moving gen8_emit_pipe_control and friends to gen8_engine_cs.h Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_overlay.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 1 + .../gpu/drm/i915/gem/i915_gem_object_blt.c| 1 + .../i915/gem/selftests/i915_gem_coherency.c | 1 + .../drm/i915/gem/selftests/i915_gem_mman.c| 1 + .../drm/i915/gem/selftests/igt_gem_utils.c| 1 + drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 92 +++ drivers/gpu/drm/i915/gt/intel_engine.h| 86 - drivers/gpu/drm/i915/gt/intel_renderstate.c | 3 +- drivers/gpu/drm/i915/gt/intel_ring.c | 2 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 + drivers/gpu/drm/i915/gt/selftest_mocs.c | 1 + drivers/gpu/drm/i915/gt/selftest_rc6.c| 1 + drivers/gpu/drm/i915/gt/selftest_reset.c | 1 + drivers/gpu/drm/i915/gt/selftest_timeline.c | 1 + drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/mmio_context.c | 1 + drivers/gpu/drm/i915/i915_cmd_parser.c| 1 + drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/gpu/drm/i915/i915_request.c | 1 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 + drivers/gpu/drm/i915/selftests/igt_spinner.c | 1 + 25 files changed, 118 insertions(+), 87 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index 52b4f6193b4c..6be5d8946c69 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -29,6 +29,7 @@ #include #include "gem/i915_gem_pm.h" +#include "gt/intel_gpu_commands.h" #include "gt/intel_ring.h" #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index ad136d009d9b..7aa4629f6111 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -73,6 +73,7 @@ #include "gt/intel_engine_heartbeat.h" #include "gt/intel_engine_user.h" #include "gt/intel_execlists_submission.h" /* virtual_engine */ +#include "gt/intel_gpu_commands.h" #include "gt/intel_ring.h" #include "i915_gem_context.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 2ff32daa50bd..0cf9e79325a8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -15,6 +15,7 @@ #include "gem/i915_gem_ioctls.h" #include "gt/intel_context.h" +#include "gt/intel_gpu_commands.h" #include "gt/intel_gt.h" #include "gt/intel_gt_buffer_pool.h" #include "gt/intel_gt_pm.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index aee7ad3cc3c6..10cac9fac79b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -6,6 +6,7 @@ #include "i915_drv.h" #include "gt/intel_context.h" #include "gt/intel_engine_pm.h" +#include "gt/intel_gpu_commands.h" #include "gt/intel_gt.h" #include "gt/intel_gt_buffer_pool.h" #include "gt/intel_ring.h" diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index 7049a6bbc03d..1117d2a44518 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -7,6 +7,7 @@ #include #include "gt/intel_engine_pm.h" +#include "gt/intel_gpu_commands.h" #include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" #include "gt/intel_ring.h" diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index d27d87a678c8..d429c7643ff2 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -7,6 +7,7 @@ #include #include "gt/intel_engine_pm.h" +#include "gt/intel_gpu_commands.h" #include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" #include "gem/i915_gem_region.h" diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c index e21b5023ca7d..d6783061bc72 100644 --- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c +++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c @@ -9,6 +9,7 @@ #include "gem/i915_gem_context.h" #include "gem/i915_gem_pm.h" #include "gt/intel_context.h" +#include "gt/intel_gpu_commands.h" #include "gt/intel_gt.h" #include "i915_vma.h" #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h index 3c5771fea235..38142c0d6dde 100644 ---
Re: [Intel-gfx] [PATCH v7 1/2] drm/i915/display: Support PSR Multiple Transcoders
On 2020-12-16 at 14:47:42 +0200, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's intel_psr structure.
> It also causes changes in PSR interrupt handling routine for supporting
> multiple transcoders. But it does not change the scenario and timing of
> enabling and disabling PSR. And it not support multiple pipes with
> a single transcoder PSR case yet.
>
> v2: Fix indentation and add comments
> v3: Remove Blank line
> v4: Rebased
> v5: Rebased and Addressed Anshuman's review comment.
> - Move calling of intel_psr_init() to intel_dp_init_connector()
> v6: Address Anshuman's review comments
>- Remove wrong comments and add comments for a limit of supporting of
> a single pipe PSR
You missed some comment to address provided on v5.
Is debugfs print in drrs_status_per_crtc is not required anymore ?
Also please use drm_{dbg,warn} at every place in this patch.
> v7: Update intel_psr_compute_config() for supporting multiple transcoder
> PSR on BDW+
Could you please send this in a separate patch, remove the PORT_A
restriction so that we can support multiple psr instances.
Thanks,
Anshuman Gupta.
>
> Signed-off-by: Gwan-gyeong Mun
> Cc: José Roberto de Souza
> Cc: Juha-Pekka Heikkila
> Cc: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
> drivers/gpu/drm/i915/display/intel_display.c | 4 -
> .../drm/i915/display/intel_display_debugfs.c | 111 ++--
> .../drm/i915/display/intel_display_types.h| 38 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 588 +-
> drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
> drivers/gpu/drm/i915/i915_drv.h | 38 --
> drivers/gpu/drm/i915/i915_irq.c | 49 +-
> 10 files changed, 490 insertions(+), 384 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6863236df1d0..4b87f72cb9c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4320,7 +4320,10 @@ static void intel_ddi_update_pipe_dp(struct
> intel_atomic_state *state,
>
> intel_ddi_set_dp_msa(crtc_state, conn_state);
>
> + //TODO: move PSR related functions into intel_psr_update()
> + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
> intel_psr_update(intel_dp, crtc_state, conn_state);
> +
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_update(intel_dp, crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 78452de5e12f..a753647b0bcb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15869,8 +15869,6 @@ static void commit_pipe_config(struct
> intel_atomic_state *state,
>
> if (new_crtc_state->update_pipe)
> intel_pipe_fastset(old_crtc_state, new_crtc_state);
> -
> - intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> }
>
> if (dev_priv->display.atomic_update_watermarks)
> @@ -17829,8 +17827,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_dvo_init(dev_priv);
> }
>
> - intel_psr_init(dev_priv);
> -
> for_each_intel_encoder(_priv->drm, encoder) {
> encoder->base.possible_crtcs =
> intel_encoder_possible_crtcs(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..041053167d7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -249,18 +249,17 @@ static int i915_psr_sink_status_show(struct seq_file
> *m, void *data)
> "sink internal error",
> };
> struct drm_connector *connector = m->private;
> - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> struct intel_dp *intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> int ret;
>
> - if (!CAN_PSR(dev_priv)) {
> - seq_puts(m, "PSR Unsupported\n");
> + if (connector->status != connector_status_connected)
> return -ENODEV;
> - }
>
> - if (connector->status != connector_status_connected)
> + if (!CAN_PSR(intel_dp)) {
> + seq_puts(m, "PSR Unsupported\n");
> return -ENODEV;
> + }
>
> ret = drm_dp_dpcd_readb(_dp->aux, DP_PSR_STATUS, );
>
> @@ -280,12 +279,13 @@ static int
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v7,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v7,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/85000/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1448:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1502:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v7,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v7,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/85000/ State : warning == Summary == $ dim checkpatch origin/drm-tip a40676934ae8 drm/i915/display: Support PSR Multiple Transcoders -:1718: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects? #1718: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21: +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support) total: 0 errors, 0 warnings, 1 checks, 1746 lines checked 91675f0332c2 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix mismatch between misplaced vma check and vma insert (rev2)
== Series Details == Series: drm/i915: Fix mismatch between misplaced vma check and vma insert (rev2) URL : https://patchwork.freedesktop.org/series/84975/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9490_full -> Patchwork_19154_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19154_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19154_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19154_full: ### IGT changes ### Possible regressions * igt@gem_exec_params@larger-than-life-batch: - shard-iclb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-iclb2/igt@gem_exec_par...@larger-than-life-batch.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-iclb8/igt@gem_exec_par...@larger-than-life-batch.html - shard-tglb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-tglb6/igt@gem_exec_par...@larger-than-life-batch.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-tglb8/igt@gem_exec_par...@larger-than-life-batch.html Known issues Here are the changes found in Patchwork_19154_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-parallel: - shard-skl: NOTRUN -> [TIMEOUT][5] ([i915#1729]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-skl6/igt@gem_exec_re...@basic-parallel.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2389]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@i915_pm_backlight@bad-brightness: - shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271]) +11 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-glk9/igt@i915_pm_backli...@bad-brightness.html * igt@i915_pm_dc@dc6-dpms: - shard-skl: NOTRUN -> [FAIL][8] ([i915#454]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-skl6/igt@i915_pm...@dc6-dpms.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#151]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-skl3/igt@i915_pm_...@system-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-skl4/igt@i915_pm_...@system-suspend.html * igt@kms_ccs@pipe-c-crc-primary-basic: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111304]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-skl6/igt@kms_...@pipe-c-crc-primary-basic.html * igt@kms_chamelium@dp-hpd-storm-disable: - shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-glk9/igt@kms_chamel...@dp-hpd-storm-disable.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-skl10/igt@kms_co...@pipe-a-ctm-0-75.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-skl7/igt@kms_co...@pipe-a-ctm-0-75.html * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-skl6/igt@kms_color_chamel...@pipe-b-ctm-red-to-blue.html * igt@kms_cursor_crc@pipe-c-cursor-128x128-random: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#54]) +4 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-skl10/igt@kms_cursor_...@pipe-c-cursor-128x128-random.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-128x128-random.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2346]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/shard-tglb5/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19154/shard-tglb2/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html * igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a1: - shard-glk: [PASS][20] -> [FAIL][21] ([i915#2122]) [20]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for DP-HDMI2.1 PCON (rev8)
== Series Details == Series: Add support for DP-HDMI2.1 PCON (rev8) URL : https://patchwork.freedesktop.org/series/82098/ State : success == Summary == CI Bug Log - changes from CI_DRM_9491 -> Patchwork_19157 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/index.html Known issues Here are the changes found in Patchwork_19157 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-apl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#62]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/fi-apl-guc/igt@debugfs_test@read_all_entries.html * igt@gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#180] / [i915#62]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html Possible fixes * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_selftest@live@execlists: - fi-apl-guc: [DMESG-WARN][9] ([i915#1037]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@i915_selftest@l...@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/fi-apl-guc/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_mocs: - fi-apl-guc: [DMESG-WARN][11] -> [PASS][12] +15 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@i915_selftest@live@gt_mocs.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/fi-apl-guc/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@ring_submission: - fi-apl-guc: [DMESG-WARN][13] ([i915#203]) -> [PASS][14] +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-apl-guc/igt@i915_selftest@live@ring_submission.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/fi-apl-guc/igt@i915_selftest@live@ring_submission.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [SKIP][15] ([fdo#109271]) -> [FAIL][16] ([i915#579]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9491/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19157/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (43 -> 39) -- Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9491 -> Patchwork_19157 CI-20190529: 20190529 CI_DRM_9491: e616452578fec8ec2a04faf0090404a40ce1811c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5904: 2e5ad6b45c20c5b354325e0c818e25ba6087ecc2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19157: 6953c88c22dd6f2025a9fa2f3a64f8e81496cf04 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6953c88c22dd drm/i915/display: Let PCON convert from RGB to YUV if it can 5f7ef5bbd279 drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encoding 343952426988 drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 79aff77eff33 drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder 6e91e5eb0f05 drm/i915: Add support for enabling link status and recovery c3405b235b18 drm/i915: Check for FRL training before DP Link training 1f49f0cf119a drm/i915: Add support for starting FRL training for HDMI2.1 via PCON
Re: [Intel-gfx] [PATCH v6 2/5] drm/i915/display/psr: Use plane damage clips to calculate damaged area
On Wed, 2020-12-16 at 10:29 +, Mun, Gwan-gyeong wrote:
> On Tue, 2020-12-15 at 05:14 -0800, Souza, Jose wrote:
> > On Tue, 2020-12-15 at 13:02 +, Mun, Gwan-gyeong wrote:
> > > On Mon, 2020-12-14 at 09:49 -0800, José Roberto de Souza wrote:
> > > > Now using plane damage clips property to calcualte the damaged
> > > > area.
> > > > Selective fetch only supports one region to be fetched so
> > > > software
> > > > needs to calculate a bounding box around all damage clips.
> > > >
> > > > Now that we are not complete fetching each plane, there is
> > > > another
> > > > loop needed as all the plane areas that intersect with the pipe
> > > > damaged area needs to be fetched from memory so the complete
> > > > blending
> > > > of all planes can happen.
> > > >
> > > Hi,
> > > > v2:
> > > > - do not shifthing new_plane_state->uapi.dst only src is in
> > > > 16.16
> > > Typo on commit message. shifthing -> shifting
> > > > format
> > > >
> > > > v4:
> > > > - setting plane selective fetch area using the whole pipe damage
> > > > area
> > > > - mark the whole plane area damaged if plane visibility or alpha
> > > > changed
> > > >
> > > > v5:
> > > > - taking in consideration src.y1 in the damage coordinates
> > > > - adding to the pipe damaged area planes that were visible but
> > > > are
> > > > invisible in the new state
> > > >
> > > > v6:
> > > > - consider old state plane coordinates when visibility changes or
> > > > it
> > > > moved to calculate damaged area
> > > > - remove from damaged area the portion not in src clip
> > > >
> > > > Cc: Ville Syrjälä
> > > > Cc: Gwan-gyeong Mun
> > > > Signed-off-by: José Roberto de Souza
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 98
> > > > +-
> > > > --
> > > > 1 file changed, 86 insertions(+), 12 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index d9a395c486d3..7daed098fa74 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -1269,8 +1269,8 @@ int intel_psr2_sel_fetch_update(struct
> > > > intel_atomic_state *state,
> > > > struct intel_crtc *crtc)
> > > > {
> > > > struct intel_crtc_state *crtc_state =
> > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > > + struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX,
> > > > .y2 = -1 };
> > > > struct intel_plane_state *new_plane_state, *old_plane_state;
> > > > - struct drm_rect pipe_clip = { .y1 = -1 };
> > > > struct intel_plane *plane;
> > > > bool full_update = false;
> > > > int i, ret;
> > > > @@ -1282,9 +1282,17 @@ int intel_psr2_sel_fetch_update(struct
> > > > intel_atomic_state *state,
> > > > if (ret)
> > > > return ret;
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > + /*
> > > > +* Calculate minimal selective fetch area of each plane and
> > > > calculate
> > > > +* the pipe damaged area.
> > > > +* In the next loop the plane selective fetch area will
> > > > actually be set
> > > > +* using whole pipe damaged area.
> > > > +*/
> > > > for_each_oldnew_intel_plane_in_state(state, plane,
> > > > old_plane_state,
> > > > new_plane_state, i) {
> > > > - struct drm_rect *sel_fetch_area, temp;
> > > > + struct drm_rect src, damaged_area = { .x1 = 0, .y1 =
> > > > -1, .x2 = INT_MAX, .y2 = -1 };
> > > > + struct drm_mode_rect *damaged_clips;
> > > > + u32 num_clips, j;
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > if (new_plane_state->uapi.crtc != crtc_state-
> > > > > uapi.crtc)
> > > > continue;
> > > > @@ -1300,23 +1308,89 @@ int intel_psr2_sel_fetch_update(struct
> > > > intel_atomic_state *state,
> > > > break;
> > > > }
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > - if (!new_plane_state->uapi.visible)
> > > > - continue;
> > > > + drm_rect_convert_16_16_to_regular(_plane_state-
> > > > > uapi.src, );
> > > > + damaged_clips =
> > > > drm_plane_get_damage_clips(_plane_state->uapi);
> > > > + num_clips =
> > > > drm_plane_get_damage_clips_count(_plane_state->uapi);
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > > > /*
> > > > -* For now doing a selective fetch in the whole plane
> > > > area,
> > > > -* optimizations will come in the future.
> > > > +* If visibility or plane moved, mark the whole plane
> > > > area as
> > > > +* damaged as it needs to be complete redraw in the
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for DP-HDMI2.1 PCON (rev8)
== Series Details == Series: Add support for DP-HDMI2.1 PCON (rev8) URL : https://patchwork.freedesktop.org/series/82098/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev8)
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev8)
URL : https://patchwork.freedesktop.org/series/82098/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fd6d0019c12b drm/edid: Add additional HFVSDB fields for HDMI2.1
-:61: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email name mismatch:
'From: Swati Sharma ' != 'Signed-off-by: Sharma,
Swati2 '
total: 0 errors, 1 warnings, 0 checks, 36 lines checked
50d2dfdc992e drm/edid: Parse MAX_FRL field from HFVSDB block
-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/drm_edid.c:4948:
+ drm_get_max_frl_rate(max_frl_rate, >max_lanes,
+ >max_frl_rate_per_lane);
-:95: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email name mismatch:
'From: Swati Sharma ' != 'Signed-off-by: Sharma,
Swati2 '
total: 0 errors, 1 warnings, 1 checks, 68 lines checked
554bf7295147 drm/edid: Parse DSC1.2 cap fields from HFVSDB block
-:51: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#51: FILE: drivers/gpu/drm/drm_edid.c:4969:
+ drm_get_max_frl_rate(dsc_max_frl_rate,
_dsc->max_lanes,
+ _dsc->max_frl_rate_per_lane);
-:52: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#52: FILE: drivers/gpu/drm/drm_edid.c:4970:
+ hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] &
DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
total: 0 errors, 1 warnings, 1 checks, 125 lines checked
74c9de49e2e1 drm/dp_helper: Add Helpers for FRL Link Training support for
DP-HDMI2.1 PCON
6645c462c8e2 drm/dp_helper: Add support for link failure detection
-:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#112: FILE: include/drm/drm_dp_helper.h:2055:
+void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
+ struct drm_connector *connector);
total: 0 errors, 0 warnings, 1 checks, 76 lines checked
45f9245e08cd drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon
-:15: WARNING:TYPO_SPELLING: 'Convertor' may be misspelled - perhaps
'Converter'?
#15:
v3: Only setting the DSC bits for the Protocol Convertor control
-:165: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#165: FILE: drivers/gpu/drm/drm_dp_helper.c:3037:
+ * */
-:185: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#185: FILE: drivers/gpu/drm/drm_dp_helper.c:3057:
+ * */
-:210: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#210: FILE: drivers/gpu/drm/drm_dp_helper.c:3082:
+ * */
total: 0 errors, 4 warnings, 0 checks, 343 lines checked
5729fded5d67 drm/dp_helper: Add helpers to configure PCONs RGB-YCbCr Conversion
-:18: WARNING:TYPO_SPELLING: 'accomodate' may be misspelled - perhaps
'accommodate'?
#18:
-Modified the color-conversion cap helper function, to accomodate
total: 0 errors, 1 warnings, 0 checks, 106 lines checked
f6125fc4c21a drm/i915: Capture max frl rate for PCON in dfp cap structure
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#13:
-tweaked the comparison of target bw and pcon frl bw to avoid roundup errors.
total: 0 errors, 1 warnings, 0 checks, 60 lines checked
1f49f0cf119a drm/i915: Add support for starting FRL training for HDMI2.1 via
PCON
-:86: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#86: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4005:
+{
+
-:147: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#147: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4066:
+ wait_for(is_active = drm_dp_pcon_is_frl_ready(_dp->aux) == true,
TIMEOUT_FRL_READY_MS);
-:166: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#166: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4085:
+ wait_for(is_active = drm_dp_pcon_hdmi_link_active(_dp->aux) ==
true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
-:172: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#172: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4091:
+ if (DP_PCON_HDMI_MODE_FRL != drm_dp_pcon_hdmi_link_mode(_dp->aux,
_trained_mask)) {
-:172: WARNING:CONSTANT_COMPARISON: Comparisons should place the constant on
the right side of the test
#172: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4091:
+ if (DP_PCON_HDMI_MODE_FRL != drm_dp_pcon_hdmi_link_mode(_dp->aux,
_trained_mask)) {
-:176: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#176: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4095:
+ drm_dbg(>drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n",
max_frl_bw_mask, frl_trained_mask);
total: 0 errors, 5 warnings, 1 checks, 194 lines checked
c3405b235b18 drm/i915: Check for FRL training before DP Link training
6e91e5eb0f05 drm/i915: Add support for enabling link status and recovery
-:54: WARNING:LONG_LINE: line length
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: refactor intel display
== Series Details == Series: drm/i915: refactor intel display URL : https://patchwork.freedesktop.org/series/84998/ State : failure == Summary == Applying: drm/i915/display: move needs_modeset to an inline in header Applying: drm/i915/display: move to_intel_frontbuffer to header Applying: drm/i915/display: fix misused comma Applying: drm/i915: refactor cursor code out of i915_display.c Applying: drm/i915: refactor some crtc code out of intel display. Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0005 drm/i915: refactor some crtc code out of intel display. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
- Remove checking of Gen12 for i915_psr_status.
- Add check of HAS_PSR()
- Remove meaningless check routine.
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Jani Nikula
Cc: Anshuman Gupta
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 041053167d7f..d2dd61c4ee0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2224,6 +2224,16 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
@@ -2399,6 +2409,12 @@ int intel_connector_debugfs_add(struct drm_connector
*connector)
connector, _psr_sink_status_fops);
}
+ if (HAS_PSR(dev_priv) &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ debugfs_create_file("i915_psr_status", 0444, root,
+ connector, _psr_status_fops);
+ }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 1/2] drm/i915/display: Support PSR Multiple Transcoders
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR. And it not support multiple pipes with
a single transcoder PSR case yet.
v2: Fix indentation and add comments
v3: Remove Blank line
v4: Rebased
v5: Rebased and Addressed Anshuman's review comment.
- Move calling of intel_psr_init() to intel_dp_init_connector()
v6: Address Anshuman's review comments
- Remove wrong comments and add comments for a limit of supporting of
a single pipe PSR
v7: Update intel_psr_compute_config() for supporting multiple transcoder
PSR on BDW+
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Juha-Pekka Heikkila
Cc: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
drivers/gpu/drm/i915/display/intel_display.c | 4 -
.../drm/i915/display/intel_display_debugfs.c | 111 ++--
.../drm/i915/display/intel_display_types.h| 38 ++
drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
drivers/gpu/drm/i915/display/intel_psr.c | 588 +-
drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 38 --
drivers/gpu/drm/i915/i915_irq.c | 49 +-
10 files changed, 490 insertions(+), 384 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6863236df1d0..4b87f72cb9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4320,7 +4320,10 @@ static void intel_ddi_update_pipe_dp(struct
intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
+ //TODO: move PSR related functions into intel_psr_update()
+ intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
intel_psr_update(intel_dp, crtc_state, conn_state);
+
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_update(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 78452de5e12f..a753647b0bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15869,8 +15869,6 @@ static void commit_pipe_config(struct
intel_atomic_state *state,
if (new_crtc_state->update_pipe)
intel_pipe_fastset(old_crtc_state, new_crtc_state);
-
- intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
if (dev_priv->display.atomic_update_watermarks)
@@ -17829,8 +17827,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_dvo_init(dev_priv);
}
- intel_psr_init(dev_priv);
-
for_each_intel_encoder(_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..041053167d7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -249,18 +249,17 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
"sink internal error",
};
struct drm_connector *connector = m->private;
- struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
int ret;
- if (!CAN_PSR(dev_priv)) {
- seq_puts(m, "PSR Unsupported\n");
+ if (connector->status != connector_status_connected)
return -ENODEV;
- }
- if (connector->status != connector_status_connected)
+ if (!CAN_PSR(intel_dp)) {
+ seq_puts(m, "PSR Unsupported\n");
return -ENODEV;
+ }
ret = drm_dp_dpcd_readb(_dp->aux, DP_PSR_STATUS, );
@@ -280,12 +279,13 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static void
-psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
+psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
{
u32 val, status_val;
const char *status = "unknown";
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (dev_priv->psr.psr2_enabled) {
+ if (intel_dp->psr.psr2_enabled) {
static const char * const live_status[] = {
Re: [Intel-gfx] [PATCH v4 08/11] drm/i915: migrate hsw fdi code to new file.
On Wed, Dec 16, 2020 at 01:29:15PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> Daniel asked for this, but it's a bit messy and I'm not sure
> how best to clean it up yet.
>
> Signed-off-by: Dave Airlie
> [Jani: also moved fdi buf trans to intel_fdi.c.]
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 197 +--
> drivers/gpu/drm/i915/display/intel_ddi.h | 14 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 174
> drivers/gpu/drm/i915/display/intel_fdi.h | 7 +
> 5 files changed, 202 insertions(+), 191 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 4934edd51cb0..077ebc7e6396 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -38,6 +38,7 @@
> #include "intel_crt.h"
> #include "intel_ddi.h"
> #include "intel_display_types.h"
> +#include "intel_fdi.h"
> #include "intel_fifo_underrun.h"
> #include "intel_gmbus.h"
> #include "intel_hotplug.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6863236df1d0..deabb1ad6045 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -35,10 +35,11 @@
> #include "intel_ddi.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> -#include "intel_dp_mst.h"
> #include "intel_dp_link_training.h"
> +#include "intel_dp_mst.h"
> #include "intel_dpio_phy.h"
> #include "intel_dsi.h"
> +#include "intel_fdi.h"
> #include "intel_fifo_underrun.h"
> #include "intel_gmbus.h"
> #include "intel_hdcp.h"
> @@ -51,12 +52,6 @@
> #include "intel_tc.h"
> #include "intel_vdsc.h"
>
> -struct ddi_buf_trans {
> - u32 trans1; /* balance leg enable, de-emph level */
> - u32 trans2; /* vref sel, vswing */
> - u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
> -};
I'd suggest not moving any buf_trans stuff into intel_fdi.c.
Rather we want something like intel_ddi_buf_trans.c to house
all of it.
> -
> static const u8 index_to_dp_signal_levels[] = {
> [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
> [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
> @@ -86,18 +81,6 @@ static const struct ddi_buf_trans
> hsw_ddi_translations_dp[] = {
> { 0x80D75FFF, 0x000B, 0x0 },
> };
>
> -static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
> - { 0x00FF, 0x0007000E, 0x0 },
> - { 0x00D75FFF, 0x000F000A, 0x0 },
> - { 0x00C30FFF, 0x00060006, 0x0 },
> - { 0x00AAAFFF, 0x001E, 0x0 },
> - { 0x00FF, 0x000F000A, 0x0 },
> - { 0x00D75FFF, 0x00160004, 0x0 },
> - { 0x00C30FFF, 0x001E, 0x0 },
> - { 0x00FF, 0x00060006, 0x0 },
> - { 0x00D75FFF, 0x001E, 0x0 },
> -};
> -
> static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
> /* Idx NT mV d T mV d db */
> { 0x00FF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
> @@ -138,18 +121,6 @@ static const struct ddi_buf_trans
> bdw_ddi_translations_dp[] = {
> { 0x80D75FFF, 0x001B0002, 0x0 },
> };
>
> -static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
> - { 0x00FF, 0x0001000E, 0x0 },
> - { 0x00D75FFF, 0x0004000A, 0x0 },
> - { 0x00C30FFF, 0x00070006, 0x0 },
> - { 0x00AAAFFF, 0x000C, 0x0 },
> - { 0x00FF, 0x0004000A, 0x0 },
> - { 0x00D75FFF, 0x00090004, 0x0 },
> - { 0x00C30FFF, 0x000C, 0x0 },
> - { 0x00FF, 0x00070006, 0x0 },
> - { 0x00D75FFF, 0x000C, 0x0 },
> -};
> -
> static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
> /* Idx NT mV d T mV df db */
> { 0x00FF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
> @@ -929,22 +900,6 @@ intel_ddi_get_buf_trans_edp(struct intel_encoder
> *encoder, int *n_entries)
> return NULL;
> }
>
> -static const struct ddi_buf_trans *
> -intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
> - int *n_entries)
> -{
> - if (IS_BROADWELL(dev_priv)) {
> - *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
> - return bdw_ddi_translations_fdi;
> - } else if (IS_HASWELL(dev_priv)) {
> - *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
> - return hsw_ddi_translations_fdi;
> - }
> -
> - *n_entries = 0;
> - return NULL;
> -}
> -
> static const struct ddi_buf_trans *
> intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
>int *n_entries)
> @@ -1398,8 +1353,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder
> *encoder,
> * values in advance. This function programs the correct values for
> * DP/eDP/FDI use cases.
>
Re: [Intel-gfx] [PATCH 05/11] drm/i915: refactor some crtc code out of intel display.
On Wed, 16 Dec 2020, Ville Syrjälä wrote: > On Wed, Dec 16, 2020 at 12:03:37PM +0200, Jani Nikula wrote: >> On Fri, 11 Dec 2020, Dave Airlie wrote: >> > From: Dave Airlie >> > >> > There may be more crtc code that can be pulled out, but this >> > is a good start. >> > >> > RFC: maybe call the new file something different >> >> I checked this is just code movement. I did clean up intel_crtc.h >> locally a bit though. (I'll probably re-send the series with a few fixes >> to pass CI.) >> >> I'm not averse to renaming the file later if needed, I'm more concerned >> about choosing a meaningful bunch of functions to take out and put in >> the new file. >> >> Ville, I saw you had some comments about this - is this making sensible >> progress or making further refactoring harder? > > Just means we have to move 90% of the proposed intel_crtc.c > into i9xx_plane.c again. So the plane bits here are just > pointless churn IMO. Fair enough. I just don't want to stall on this again like we've stalled every time there's been proposals to clean up intel_display.c. And it's always about some things that could be moved to a different file or grouped differently or something. I'm pretty close to a point where I'll take *anything* to chop up the file, and then we'll have better clarity with smaller files when the dust settles. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 1/2] drm/i915/display: Support PSR Multiple Transcoders
On 2020-12-16 at 11:38:24 +0200, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's intel_psr structure.
> It also causes changes in PSR interrupt handling routine for supporting
> multiple transcoders. But it does not change the scenario and timing of
> enabling and disabling PSR. And it not support multiple pipes with
> a single transcoder PSR case yet.
>
> v2: Fix indentation and add comments
> v3: Remove Blank line
> v4: Rebased
> v5: Rebased and Addressed Anshuman's review comment.
> - Move calling of intel_psr_init() to intel_dp_init_connector()
> v6: Address Anshuman's review comments
>- Remove wrong comments and add comments for a limit of supporting of
> a single pipe PSR
You missed to addressed few comment.
Is drrs_status_per_crtc debugfs print is not required anymore?
Also please use drm_{dbg,warn} at every place in this patch.
Thanks,
Anshuman Gupta.
>
> Signed-off-by: Gwan-gyeong Mun
> Cc: José Roberto de Souza
> Cc: Juha-Pekka Heikkila
> Cc: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
> drivers/gpu/drm/i915/display/intel_display.c | 4 -
> .../drm/i915/display/intel_display_debugfs.c | 111 ++--
> .../drm/i915/display/intel_display_types.h| 38 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 582 ++
> drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
> drivers/gpu/drm/i915/i915_drv.h | 38 --
> drivers/gpu/drm/i915/i915_irq.c | 49 +-
> 10 files changed, 488 insertions(+), 380 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6863236df1d0..4b87f72cb9c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4320,7 +4320,10 @@ static void intel_ddi_update_pipe_dp(struct
> intel_atomic_state *state,
>
> intel_ddi_set_dp_msa(crtc_state, conn_state);
>
> + //TODO: move PSR related functions into intel_psr_update()
> + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
> intel_psr_update(intel_dp, crtc_state, conn_state);
> +
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_update(intel_dp, crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 78452de5e12f..a753647b0bcb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15869,8 +15869,6 @@ static void commit_pipe_config(struct
> intel_atomic_state *state,
>
> if (new_crtc_state->update_pipe)
> intel_pipe_fastset(old_crtc_state, new_crtc_state);
> -
> - intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> }
>
> if (dev_priv->display.atomic_update_watermarks)
> @@ -17829,8 +17827,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_dvo_init(dev_priv);
> }
>
> - intel_psr_init(dev_priv);
> -
> for_each_intel_encoder(_priv->drm, encoder) {
> encoder->base.possible_crtcs =
> intel_encoder_possible_crtcs(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..041053167d7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -249,18 +249,17 @@ static int i915_psr_sink_status_show(struct seq_file
> *m, void *data)
> "sink internal error",
> };
> struct drm_connector *connector = m->private;
> - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> struct intel_dp *intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> int ret;
>
> - if (!CAN_PSR(dev_priv)) {
> - seq_puts(m, "PSR Unsupported\n");
> + if (connector->status != connector_status_connected)
> return -ENODEV;
> - }
>
> - if (connector->status != connector_status_connected)
> + if (!CAN_PSR(intel_dp)) {
> + seq_puts(m, "PSR Unsupported\n");
> return -ENODEV;
> + }
>
> ret = drm_dp_dpcd_readb(_dp->aux, DP_PSR_STATUS, );
>
> @@ -280,12 +279,13 @@ static int i915_psr_sink_status_show(struct seq_file
> *m, void *data)
> DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
>
> static void
> -psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
> +psr_source_status(struct intel_dp
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v6,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/84997/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9490 -> Patchwork_19155
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19155:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}: [SKIP][1] ([fdo#110189]) -> [SKIP][2] +3 similar
issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
Known issues
Here are the changes found in Patchwork_19155 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@double-flink:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/fi-tgl-y/igt@gem_flink_ba...@double-flink.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/fi-tgl-y/igt@gem_flink_ba...@double-flink.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][5] -> [SKIP][6] ([fdo#109271])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/fi-kbl-guc/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/fi-kbl-guc/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@blt:
- fi-snb-2520m: [PASS][7] -> [DMESG-FAIL][8] ([i915#1409])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/fi-snb-2520m/igt@i915_selftest@l...@blt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/fi-snb-2520m/igt@i915_selftest@l...@blt.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-bdw-5557u: NOTRUN -> [SKIP][9] ([fdo#109271]) +3 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/fi-bdw-5557u/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-y: [DMESG-FAIL][13] ([i915#2601]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][15] ([i915#1161] / [i915#262]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9490/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19155/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1409]: https://gitlab.freedesktop.org/drm/intel/issues/1409
[i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 39)
--
Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_9490 -> Patchwork_19155
CI-20190529: 20190529
CI_DRM_9490: a8d002117655cf836077d0334ae97486eb699ed9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5903: e4a5c72eaa83aa07ff6847e4c166c17dd29722f0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19155: 46edf1f39389b05e11e477ba7cc9e8c50526e8ab @
Re: [Intel-gfx] [PATCH v4 11/11] drm/i915: split fb scalable checks into g4x and skl versions
On Wed, Dec 16, 2020 at 01:29:18PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> This just cleans these up a bit.
>
> Signed-off-by: Dave Airlie
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_gen9_plane.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_sprite.c | 7 +++
> 2 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gen9_plane.c
> b/drivers/gpu/drm/i915/display/intel_gen9_plane.c
> index 8549b262f095..c695ee990a82 100644
> --- a/drivers/gpu/drm/i915/display/intel_gen9_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_gen9_plane.c
> @@ -2139,7 +2139,7 @@ static int skl_check_plane_surface(struct
> intel_plane_state *plane_state)
> return 0;
> }
>
> -static bool intel_fb_scalable(const struct drm_framebuffer *fb)
> +static bool skl_fb_scalable(const struct drm_framebuffer *fb)
> {
> if (!fb)
> return false;
> @@ -2172,7 +2172,7 @@ static int skl_plane_check(struct intel_crtc_state
> *crtc_state,
> return ret;
>
> /* use scaler when colorkey is not required */
> - if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
> + if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
> min_scale = 1;
> max_scale = skl_plane_max_scale(dev_priv, fb);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index cc3bec42d04c..4cb6339d12be 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -1282,19 +1282,18 @@ g4x_plane_get_hw_state(struct intel_plane *plane,
> return ret;
> }
>
> -static bool intel_fb_scalable(const struct drm_framebuffer *fb)
> +static bool g4x_fb_scalable(const struct drm_framebuffer *fb)
> {
> if (!fb)
> return false;
>
> switch (fb->format->format) {
> case DRM_FORMAT_C8:
> - return false;
> case DRM_FORMAT_XRGB16161616F:
> case DRM_FORMAT_ARGB16161616F:
> case DRM_FORMAT_XBGR16161616F:
> case DRM_FORMAT_ABGR16161616F:
> - return INTEL_GEN(to_i915(fb->dev)) >= 11;
> + return false;
We could drop a bunch of the formats here since they're not
supported by the g4x+ sprites anyway. But that could be a followup.
Reviewed-by: Ville Syrjälä
> default:
> return true;
> }
> @@ -1371,7 +1370,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> int max_scale = DRM_PLANE_HELPER_NO_SCALING;
> int ret;
>
> - if (intel_fb_scalable(plane_state->hw.fb)) {
> + if (g4x_fb_scalable(plane_state->hw.fb)) {
> if (INTEL_GEN(dev_priv) < 7) {
> min_scale = 1;
> max_scale = 16 << 16;
> --
> 2.20.1
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 10/11] drm/i915: move pipe update code into crtc.
On Wed, Dec 16, 2020 at 01:29:17PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> Daniel suggested this should move here.
Slightly better than where it is now I guess. I'd kinda like to put it
next to its callers but not sure that wouldn't end up in a mess.
Reviewed-by: Ville Syrjälä
>
> Signed-off-by: Dave Airlie
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 230
> drivers/gpu/drm/i915/display/intel_sprite.c | 228 ---
> 2 files changed, 230 insertions(+), 228 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 0161e18f1a50..9010c55bbc4e 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -10,6 +10,9 @@
> #include
> #include
>
> +#include "i915_trace.h"
> +#include "i915_vgpu.h"
> +
> #include "intel_atomic.h"
> #include "intel_atomic_plane.h"
> #include "intel_color.h"
> @@ -17,7 +20,9 @@
> #include "intel_cursor.h"
> #include "intel_display_debugfs.h"
> #include "intel_display_types.h"
> +#include "intel_dsi.h"
> #include "intel_pipe_crc.h"
> +#include "intel_psr.h"
> #include "intel_sprite.h"
>
> /* Primary plane formats for gen <= 3 */
> @@ -955,3 +960,228 @@ int intel_crtc_init(struct drm_i915_private *dev_priv,
> enum pipe pipe)
>
> return ret;
> }
> +
> +int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> + int usecs)
> +{
> + /* paranoia */
> + if (!adjusted_mode->crtc_htotal)
> + return 1;
> +
> + return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
> + 1000 * adjusted_mode->crtc_htotal);
> +}
> +
> +/**
> + * intel_pipe_update_start() - start update of a set of display registers
> + * @new_crtc_state: the new crtc state
> + *
> + * Mark the start of an update to pipe registers that should be updated
> + * atomically regarding vblank. If the next vblank will happens within
> + * the next 100 us, this function waits until the vblank passes.
> + *
> + * After a successful call to this function, interrupts will be disabled
> + * until a subsequent call to intel_pipe_update_end(). That is done to
> + * avoid random delays.
> + */
> +void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct drm_display_mode *adjusted_mode =
> _crtc_state->hw.adjusted_mode;
> + long timeout = msecs_to_jiffies_timeout(1);
> + int scanline, min, max, vblank_start;
> + wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(>base);
> + bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) ||
> IS_CHERRYVIEW(dev_priv)) &&
> + intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
> + DEFINE_WAIT(wait);
> + u32 psr_status;
> +
> + if (new_crtc_state->uapi.async_flip)
> + return;
> +
> + vblank_start = adjusted_mode->crtc_vblank_start;
> + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> + vblank_start = DIV_ROUND_UP(vblank_start, 2);
> +
> + /* FIXME needs to be calibrated sensibly */
> + min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> + VBLANK_EVASION_TIME_US);
> + max = vblank_start - 1;
> +
> + if (min <= 0 || max <= 0)
> + goto irq_disable;
> +
> + if (drm_WARN_ON(_priv->drm, drm_crtc_vblank_get(>base)))
> + goto irq_disable;
> +
> + /*
> + * Wait for psr to idle out after enabling the VBL interrupts
> + * VBL interrupts will start the PSR exit and prevent a PSR
> + * re-entry as well.
> + */
> + if (intel_psr_wait_for_idle(new_crtc_state, _status))
> + drm_err(_priv->drm,
> + "PSR idle timed out 0x%x, atomic update may fail\n",
> + psr_status);
> +
> + local_irq_disable();
> +
> + crtc->debug.min_vbl = min;
> + crtc->debug.max_vbl = max;
> + trace_intel_pipe_update_start(crtc);
> +
> + for (;;) {
> + /*
> + * prepare_to_wait() has a memory barrier, which guarantees
> + * other CPUs can see the task state update by the time we
> + * read the scanline.
> + */
> + prepare_to_wait(wq, , TASK_UNINTERRUPTIBLE);
> +
> + scanline = intel_get_crtc_scanline(crtc);
> + if (scanline < min || scanline > max)
> + break;
> +
> + if (!timeout) {
> + drm_err(_priv->drm,
> + "Potential atomic update failure on pipe %c\n",
> + pipe_name(crtc->pipe));
> + break;
> + }
> +
> +
Re: [Intel-gfx] [PATCH v4 09/11] drm/i915: migrate skl planes code new file
On Wed, Dec 16, 2020 at 01:29:16PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> Rework the plane init calls to do the gen test one level higher.
>
> Signed-off-by: Dave Airlie
> [Jani: fixed up sparse warnings.]
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/Makefile |1 +
> .../gpu/drm/i915/display/intel_atomic_plane.c | 76 -
> drivers/gpu/drm/i915/display/intel_crtc.c | 16 +-
> drivers/gpu/drm/i915/display/intel_display.c | 1410 +---
> drivers/gpu/drm/i915/display/intel_display.h | 36 +-
> .../drm/i915/display/intel_display_types.h| 21 +
> .../gpu/drm/i915/display/intel_gen9_plane.c | 2832 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 1417 +
> 8 files changed, 2931 insertions(+), 2878 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_gen9_plane.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 42f9c1ca3c08..a4f67c795240 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -211,6 +211,7 @@ i915-y += \
> display/intel_fifo_underrun.o \
> display/intel_frontbuffer.o \
> display/intel_global_state.o \
> + display/intel_gen9_plane.o \
skl_universal_plane.c is what I'd call it.
No corresponding header?
> display/intel_hdcp.o \
> display/intel_hotplug.o \
> display/intel_lpe_audio.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index b5e1ee99535c..10197cc158c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -399,50 +399,6 @@ int intel_plane_atomic_check(struct intel_atomic_state
> *state,
> new_plane_state);
> }
>
> -static struct intel_plane *
> -skl_next_plane_to_commit(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct skl_ddb_entry entries_y[I915_MAX_PLANES],
> - struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
> - unsigned int *update_mask)
> -{
> - struct intel_crtc_state *crtc_state =
> - intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_plane_state *plane_state;
> - struct intel_plane *plane;
> - int i;
> -
> - if (*update_mask == 0)
> - return NULL;
> -
> - for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> - enum plane_id plane_id = plane->id;
> -
> - if (crtc->pipe != plane->pipe ||
> - !(*update_mask & BIT(plane_id)))
> - continue;
> -
> - if
> (skl_ddb_allocation_overlaps(_state->wm.skl.plane_ddb_y[plane_id],
> - entries_y,
> - I915_MAX_PLANES, plane_id) ||
> -
> skl_ddb_allocation_overlaps(_state->wm.skl.plane_ddb_uv[plane_id],
> - entries_uv,
> - I915_MAX_PLANES, plane_id))
> - continue;
> -
> - *update_mask &= ~BIT(plane_id);
> - entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
> - entries_uv[plane_id] =
> crtc_state->wm.skl.plane_ddb_uv[plane_id];
> -
> - return plane;
> - }
> -
> - /* should never happen */
> - drm_WARN_ON(state->base.dev, 1);
> -
> - return NULL;
> -}
> -
I wouldn't bother moving the stuff from intel_atomic_plane.c.
They're much higher level stuff than the rest of the moved code.
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 376cec71b477..c1ddef60e36e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -52,6 +52,7 @@ struct intel_crtc_state;
> struct intel_digital_port;
> struct intel_dp;
> struct intel_encoder;
> +struct intel_initial_plane_config;
> struct intel_load_detect_pipe;
> struct intel_plane;
> struct intel_plane_state;
> @@ -615,23 +616,12 @@ intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
> void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state);
>
> -u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
> void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
> -u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set);
> -void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe
> pipe,
> - int id, int set, enum drm_scaling_filter filter);
> void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
> -u32 glk_plane_color_ctl(const struct
Re: [Intel-gfx] [PATCH v4 06/11] drm/i915: refactor pll code out into intel_dpll.c
On Wed, Dec 16, 2020 at 01:29:13PM +0200, Jani Nikula wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index dfa3966e5fa1..37a9f304cb55 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1811,4 +1811,17 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
> return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
> }
>
> +static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
> +{
> + if (dev_priv->params.panel_use_ssc >= 0)
> + return dev_priv->params.panel_use_ssc != 0;
> + return dev_priv->vbt.lvds_use_ssc
> + && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
> +}
> +
> +static inline u32 i9xx_dpll_compute_fp(struct dpll *dpll)
> +{
> + return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
> +}
Was wondering why this is here, but looks like it's the i830 pipe power
well thing that needs it.
Reviewed-by: Ville Syrjälä
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v6,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v6,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/84997/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1448:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1502:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v6,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v6,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/84997/ State : warning == Summary == $ dim checkpatch origin/drm-tip 144736cb4785 drm/i915/display: Support PSR Multiple Transcoders -:1705: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects? #1705: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21: +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support) total: 0 errors, 0 warnings, 1 checks, 1734 lines checked 46edf1f39389 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
