[Intel-gfx] [PATCH i-g-t] i915/gem_exec_balancer: Exercise non-persistent behaviours
Verify that the virtual engine is destroyed when the context is lost if
persistence is disabled either on the context or system-wide.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_balancer.c | 165 +
1 file changed, 165 insertions(+)
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index 9fd41ba93..5ce0b495c 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -31,6 +31,7 @@
#include "igt.h"
#include "igt_gt.h"
#include "igt_perf.h"
+#include "igt_sysfs.h"
#include "sw_sync.h"
IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing");
@@ -3066,6 +3067,154 @@ static void fairslice(int i915)
}
}
+static int wait_for_status(int fence, int timeout)
+{
+ int err;
+
+ err = sync_fence_wait(fence, timeout);
+ if (err)
+ return err;
+
+ return sync_fence_status(fence);
+}
+
+static void __persistence(int i915,
+ struct i915_engine_class_instance *ci,
+ unsigned int count,
+ bool persistent)
+{
+ igt_spin_t *spin;
+ uint32_t ctx;
+
+ /*
+* A nonpersistent context is terminated immediately upon closure,
+* any inflight request is cancelled.
+*/
+
+ ctx = load_balancer_create(i915, ci, count);
+ if (!persistent)
+ gem_context_set_persistence(i915, ctx, persistent);
+
+ spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_FENCE_OUT);
+ gem_context_destroy(i915, ctx);
+
+ igt_assert_eq(wait_for_status(spin->out_fence, 500), -EIO);
+ igt_spin_free(i915, spin);
+}
+
+static void persistence(int i915)
+{
+ for (int class = 0; class < 32; class++) {
+ struct i915_engine_class_instance *ci;
+ unsigned int count = 0;
+
+ ci = list_engines(i915, 1u << class, &count);
+ if (!ci || count < 2) {
+ free(ci);
+ continue;
+ }
+
+ __persistence(i915, ci, count, false);
+ free(ci);
+ }
+}
+
+static bool set_heartbeat(int i915, const char *name, unsigned int value)
+{
+ unsigned int x;
+
+ if (gem_engine_property_printf(i915, name,
+ "heartbeat_interval_ms",
+ "%d", value) < 0)
+ return false;
+
+ x = ~value;
+ gem_engine_property_scanf(i915, name,
+ "heartbeat_interval_ms",
+ "%d", &x);
+ igt_assert_eq(x, value);
+
+ return true;
+}
+
+static void noheartbeat(int i915)
+{
+ const struct intel_execution_engine2 *e;
+
+ /*
+* Check that non-persistent contexts are also cleaned up if we
+* close the context while they are active, but the engine's
+* heartbeat has already been disabled.
+*/
+
+ __for_each_physical_engine(i915, e)
+ set_heartbeat(i915, e->name, 0);
+
+ for (int class = 0; class < 32; class++) {
+ struct i915_engine_class_instance *ci;
+ unsigned int count = 0;
+
+ ci = list_engines(i915, 1u << class, &count);
+ if (!ci || count < 2) {
+ free(ci);
+ continue;
+ }
+
+ __persistence(i915, ci, count, true);
+ free(ci);
+ }
+
+ igt_require_gem(i915); /* restore default parameters */
+}
+
+static bool enable_hangcheck(int dir, bool state)
+{
+ return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static void nohangcheck(int i915)
+{
+ int params = igt_params_open(i915);
+
+ igt_require(enable_hangcheck(params, false));
+
+ for (int class = 0; class < 32; class++) {
+ struct i915_engine_class_instance *ci;
+ unsigned int count = 0;
+
+ ci = list_engines(i915, 1u << class, &count);
+ if (!ci || count < 2) {
+ free(ci);
+ continue;
+ }
+
+ __persistence(i915, ci, count, true);
+ free(ci);
+ }
+
+ enable_hangcheck(params, true);
+ close(params);
+}
+
+static bool has_persistence(int i915)
+{
+ struct drm_i915_gem_context_param p = {
+ .param = I915_CONTEXT_PARAM_PERSISTENCE,
+ };
+ uint64_t saved;
+
+ if (__gem_context_get_param(i915, &p))
+ return false;
+
+ saved = p.value;
+ p.value = 0;
+ if (__gem_context_set_param(i915, &p))
+ return false;
+
+ p.value = saved;
+ return __gem_context_set_param(i915, &p) == 0;
+}
+
static bool has_context_engines(int i915)
{
struct drm_i915_gem_context_param p = {
@@ -3229,4 +3378,20 @@ igt_main
igt_subtest("h
[Intel-gfx] [PATCH] drm/i915/gt: Only disable preemption on gen8 render engines
The reason why we did not enable preemption on Broadwater was due to
missing GPGPU workarounds. Since this only applies to rcs0, only
restrict rcs0 (and our global capabilities).
While this does not affect exposing a preemption capability to
userspace, it does affect our internal decisions on whether to use
timeslicing and semaphores between individual engines.
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 11 ++-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 33 ---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 2 --
drivers/gpu/drm/i915/intel_device_info.h | 1 -
5 files changed, 10 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index f08ba2d1f6d6..babc19ec5c15 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3102,6 +3102,15 @@ static void execlists_park(struct intel_engine_cs
*engine)
cancel_timer(&engine->execlists.preempt);
}
+static bool can_preempt(struct intel_engine_cs *engine)
+{
+ if (INTEL_GEN(engine->i915) > 8)
+ return true;
+
+ /* GPGPU on bdw requires extra w/a; not implemented */
+ return engine->class != RENDER_CLASS;
+}
+
void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = execlists_submit_request;
@@ -3119,7 +3128,7 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
if (!intel_vgpu_active(engine->i915)) {
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) {
+ if (can_preempt(engine)) {
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
engine->flags |= I915_ENGINE_HAS_TIMESLICES;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 080b63000a4e..3bce12aaa1c2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -1721,12 +1721,6 @@ static int live_preempt(void *arg)
enum intel_engine_id id;
int err = -ENOMEM;
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
- if (!(gt->i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
- pr_err("Logical preemption supported, but not exposed\n");
-
if (igt_spinner_init(&spin_hi, gt))
return -ENOMEM;
@@ -1821,9 +1815,6 @@ static int live_late_preempt(void *arg)
enum intel_engine_id id;
int err = -ENOMEM;
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (igt_spinner_init(&spin_hi, gt))
return -ENOMEM;
@@ -1957,9 +1948,6 @@ static int live_nopreempt(void *arg)
* that may be being observed and not want to be interrupted.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (preempt_client_init(gt, &a))
return -ENOMEM;
if (preempt_client_init(gt, &b))
@@ -2311,9 +2299,6 @@ static int live_preempt_cancel(void *arg)
* GPU. That sounds like preemption! Plus a little bit of bookkeeping.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (preempt_client_init(gt, &data.a))
return -ENOMEM;
if (preempt_client_init(gt, &data.b))
@@ -2373,9 +2358,6 @@ static int live_suppress_self_preempt(void *arg)
* completion event.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (intel_uc_uses_guc_submission(>->uc))
return 0; /* presume black blox */
@@ -2488,9 +2470,6 @@ static int live_chain_preempt(void *arg)
* the previously submitted spinner in B.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (preempt_client_init(gt, &hi))
return -ENOMEM;
@@ -2890,9 +2869,6 @@ static int live_preempt_gang(void *arg)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
/*
* Build as long a chain of preempters as we can, with each
* request higher priority than the last. Once we are ready, we release
@@ -3193,9 +3169,6 @@ static int live_preempt_user(void *arg)
u32 *result;
int err = 0;
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
/*
* In our other tests, we look at preempti
[Intel-gfx] [PATCH] drm/i915/dp: Remove aux xfer timeout debug message
The timeouts are frequent and expected. We will complain if we retry so
often as to lose patience and give up, so the cacophony from individual
complaints is redundant.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8ae769b18879..704e4cebf7f3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1613,8 +1613,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Timeouts occur when the device isn't connected, so they're
* "normal" -- don't fill the kernel log with these */
if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
- drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
- intel_dp->aux.name, status);
ret = -ETIMEDOUT;
goto out;
}
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] pm-qos
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
drivers/gpu/drm/i915/i915_drv.h| 3 ---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b86ba1bdbaa3..1067bd073c95 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1463,6 +1463,9 @@ struct intel_dp {
bool rgb_to_ycbcr;
} dfp;
+ /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
+ struct pm_qos_request pm_qos;
+
/* Display stream compression testing */
bool force_dsc_en;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e38a10d5c128..5e5bcef20e33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -891,9 +891,6 @@ struct drm_i915_private {
bool display_irqs_enabled;
- /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
- struct pm_qos_request pm_qos;
-
/* Sideband mailbox protection */
struct mutex sb_lock;
struct pm_qos_request sb_qos;
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/dp: Track pm_qos per connector
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
Fixes: 9ee32fea5fe8 ("drm/i915: irq-drive the dp aux communication")
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 +---
drivers/gpu/drm/i915/i915_drv.c | 5 -
2 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 357f7921e070..f08e5f1f463d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1512,7 +1512,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* lowest possible wakeup latency and so prevent the cpu from going into
* deep sleep states.
*/
- cpu_latency_qos_update_request(&i915->pm_qos, 0);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
intel_dp_check_edp(intel_dp);
@@ -1643,7 +1643,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
ret = recv_bytes;
out:
- cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
edp_panel_vdd_off(intel_dp, false);
@@ -7527,6 +7527,14 @@ static int intel_dp_connector_atomic_check(struct
drm_connector *conn,
return intel_modeset_synced_crtcs(state, conn);
}
+static void intel_dp_connector_destroy(struct drm_connector *connector)
+{
+ struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
+
+ cpu_latency_qos_remove_request(&intel_dp->pm_qos);
+
+ intel_connector_destroy(connector);
+}
static const struct drm_connector_funcs intel_dp_connector_funcs = {
.force = intel_dp_force,
@@ -7535,7 +7543,7 @@ static const struct drm_connector_funcs
intel_dp_connector_funcs = {
.atomic_set_property = intel_digital_connector_atomic_set_property,
.late_register = intel_dp_connector_register,
.early_unregister = intel_dp_connector_unregister,
- .destroy = intel_connector_destroy,
+ .destroy = intel_dp_connector_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_duplicate_state = intel_digital_connector_duplicate_state,
};
@@ -8621,6 +8629,8 @@ intel_dp_init_connector(struct intel_digital_port
*dig_port,
intel_dp->frl.is_trained = false;
intel_dp->frl.trained_rate_gbps = 0;
+ cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
+
return true;
fail:
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..249f765993f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -578,8 +578,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
pci_set_master(pdev);
- cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
-
intel_gt_init_workarounds(dev_priv);
/* On the 945G/GM, the chipset reports the MSI capability on the
@@ -626,7 +624,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
err_mem_regions:
intel_memory_regions_driver_release(dev_priv);
err_ggtt:
@@ -648,8 +645,6 @@ static void i915_driver_hw_remove(struct drm_i915_private
*dev_priv)
if (pdev->msi_enabled)
pci_disable_msi(pdev);
-
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
}
/**
--
2.20.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/dp: Remove aux xfer timeout debug message
The timeouts are frequent and expected. We will complain if we retry so
often as to lose patience and give up, so the cacophony from individual
complaints is redundant.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f0e8aaac413c..357f7921e070 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1613,8 +1613,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
/* Timeouts occur when the device isn't connected, so they're
* "normal" -- don't fill the kernel log with these */
if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
- drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
- intel_dp->aux.name, status);
ret = -ETIMEDOUT;
goto out;
}
--
2.20.1
___
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[Intel-gfx] [PATCH 2/2] drm/i915/dp: Track pm_qos per connector
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
Fixes: 9ee32fea5fe8 ("drm/i915: irq-drive the dp aux communication")
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Imre Deak
---
.../gpu/drm/i915/display/intel_display_types.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp.c | 16 +---
drivers/gpu/drm/i915/i915_drv.c | 5 -
drivers/gpu/drm/i915/i915_drv.h | 3 ---
4 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b86ba1bdbaa3..1067bd073c95 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1463,6 +1463,9 @@ struct intel_dp {
bool rgb_to_ycbcr;
} dfp;
+ /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
+ struct pm_qos_request pm_qos;
+
/* Display stream compression testing */
bool force_dsc_en;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 357f7921e070..f08e5f1f463d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1512,7 +1512,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* lowest possible wakeup latency and so prevent the cpu from going into
* deep sleep states.
*/
- cpu_latency_qos_update_request(&i915->pm_qos, 0);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
intel_dp_check_edp(intel_dp);
@@ -1643,7 +1643,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
ret = recv_bytes;
out:
- cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
edp_panel_vdd_off(intel_dp, false);
@@ -7527,6 +7527,14 @@ static int intel_dp_connector_atomic_check(struct
drm_connector *conn,
return intel_modeset_synced_crtcs(state, conn);
}
+static void intel_dp_connector_destroy(struct drm_connector *connector)
+{
+ struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
+
+ cpu_latency_qos_remove_request(&intel_dp->pm_qos);
+
+ intel_connector_destroy(connector);
+}
static const struct drm_connector_funcs intel_dp_connector_funcs = {
.force = intel_dp_force,
@@ -7535,7 +7543,7 @@ static const struct drm_connector_funcs
intel_dp_connector_funcs = {
.atomic_set_property = intel_digital_connector_atomic_set_property,
.late_register = intel_dp_connector_register,
.early_unregister = intel_dp_connector_unregister,
- .destroy = intel_connector_destroy,
+ .destroy = intel_dp_connector_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_duplicate_state = intel_digital_connector_duplicate_state,
};
@@ -8621,6 +8629,8 @@ intel_dp_init_connector(struct intel_digital_port
*dig_port,
intel_dp->frl.is_trained = false;
intel_dp->frl.trained_rate_gbps = 0;
+ cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
+
return true;
fail:
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..249f765993f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -578,8 +578,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
pci_set_master(pdev);
- cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
-
intel_gt_init_workarounds(dev_priv);
/* On the 945G/GM, the chipset reports the MSI capability on the
@@ -626,7 +624,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
err_mem_regions:
intel_memory_regions_driver_release(dev_priv);
err_ggtt:
@@ -648,8 +645,6 @@ static void i915_driver_hw_remove(struct drm_i915_private
*dev_priv)
if (pdev->msi_enabled)
pci_disable_msi(pdev);
-
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e38a10d5c128..5e5bcef20e33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -891,9 +891,6 @@ struct drm_i915_private {
bool display_irqs_enabled;
- /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
- struct pm_qos_request pm
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Only disable preemption on gen8 render engines
== Series Details == Series: drm/i915/gt: Only disable preemption on gen8 render engines URL : https://patchwork.freedesktop.org/series/85311/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19225 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19225 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19225, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19225: ### IGT changes ### Possible regressions * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-bsw-nick/igt@i915_selftest@l...@execlists.html - fi-bsw-kefka: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html - fi-bsw-n3050: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html - fi-bdw-5557u: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-bdw-5557u/igt@i915_selftest@l...@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-bdw-5557u/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_engines: - fi-icl-y: [PASS][9] -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-icl-y/igt@i915_selftest@live@gt_engines.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-icl-y/igt@i915_selftest@live@gt_engines.html Known issues Here are the changes found in Patchwork_19225 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-byt-j1900: NOTRUN -> [SKIP][11] ([fdo#109271]) +9 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_rpm@module-reload: - fi-byt-j1900: NOTRUN -> [INCOMPLETE][12] ([i915#142] / [i915#2405]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-byt-j1900/igt@i915_pm_...@module-reload.html * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> [FAIL][14] ([i915#1436]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-bsw-kefka/igt@run...@aborted.html - fi-bsw-nick:NOTRUN -> [FAIL][15] ([i915#1436] / [i915#483]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-bsw-nick/igt@run...@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][16] ([i915#483]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-bdw-5557u/igt@run...@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][17] ([i915#1814]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-byt-j1900/igt@run...@aborted.html - fi-bsw-n3050: NOTRUN -> [FAIL][18] ([i915#1436] / [i915#483]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-bsw-n3050/igt@run...@aborted.html * igt@vgem_basic@debugfs: - fi-tgl-y: [PASS][19] -> [DMESG-WARN][20] ([i915#402]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-tgl-y/igt@vgem_ba...@debugfs.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-tgl-y/igt@vgem_ba...@debugfs.html Possible fixes * igt@prime_vgem@basic-fence-flip: - fi-tgl-y: [DMESG-WARN][21] ([i915#402]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19225/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Remove aux xfer timeout debug message
== Series Details == Series: drm/i915/dp: Remove aux xfer timeout debug message URL : https://patchwork.freedesktop.org/series/85313/ State : success == Summary == CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19226 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/index.html Known issues Here are the changes found in Patchwork_19226 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gem: - fi-bsw-n3050: [PASS][1] -> [DMESG-WARN][2] ([i915#2826]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-bsw-n3050/igt@i915_selftest@l...@gem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/fi-bsw-n3050/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@gem_contexts: - fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4] ([i915#2369]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html * igt@prime_self_import@basic-with_one_bo: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html * igt@runner@aborted: - fi-bsw-n3050: NOTRUN -> [FAIL][7] ([i915#1436] / [i915#483]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/fi-bsw-n3050/igt@run...@aborted.html Possible fixes * igt@prime_vgem@basic-fence-flip: - fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369 [i915#2826]: https://gitlab.freedesktop.org/drm/intel/issues/2826 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483 Participating hosts (42 -> 37) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9533 -> Patchwork_19226 CI-20190529: 20190529 CI_DRM_9533: 1ebc67e5e636a2422ac68d93b87e236dcf645da0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5928: 7813bb74aec408055d564fa6a270526822cfbc0e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19226: 10dcc8bfb71c1a6b5122fcf486ffa184c081c383 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 10dcc8bfb71c drm/i915/dp: Remove aux xfer timeout debug message == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] pm-qos
== Series Details == Series: series starting with [1/2] pm-qos URL : https://patchwork.freedesktop.org/series/85314/ State : warning == Summary == $ dim checkpatch origin/drm-tip a5980931c890 pm-qos -:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one -:34: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 1 warnings, 0 checks, 18 lines checked dc97bbe444ec drm/i915/dp: Track pm_qos per connector -:46: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #46: FILE: drivers/gpu/drm/i915/display/intel_dp.c:7532: } +static void intel_dp_connector_destroy(struct drm_connector *connector) total: 0 errors, 0 warnings, 1 checks, 69 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] pm-qos
== Series Details == Series: series starting with [1/2] pm-qos URL : https://patchwork.freedesktop.org/series/85314/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1326:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:843:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:869:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen
[Intel-gfx] [PATCH] drm/i915: Support secure dispatch on gen6/gen7
Re-enable secure dispatch for gen6/gen7, primarily to workaround the command parser and overly zealous command validation on Haswell. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3b8765f25d86..bde7dc57baaa 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1655,7 +1655,7 @@ tgl_revids_get(struct drm_i915_private *dev_priv) #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) #define HAS_SNOOP(dev_priv)(INTEL_INFO(dev_priv)->has_snoop) #define HAS_EDRAM(dev_priv)((dev_priv)->edram_size_mb) -#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) +#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 8) #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] pm-qos
== Series Details == Series: series starting with [1/2] pm-qos URL : https://patchwork.freedesktop.org/series/85314/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19227 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19227 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19227, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19227: ### IGT changes ### Possible regressions * igt@core_hotunplug@unbind-rebind: - fi-elk-e7500: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-elk-e7500/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-elk-e7500/igt@core_hotunp...@unbind-rebind.html - fi-ivb-3770:[PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-ivb-3770/igt@core_hotunp...@unbind-rebind.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-ivb-3770/igt@core_hotunp...@unbind-rebind.html - fi-ilk-650: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-ilk-650/igt@core_hotunp...@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-ilk-650/igt@core_hotunp...@unbind-rebind.html - fi-bsw-n3050: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-bsw-n3050/igt@core_hotunp...@unbind-rebind.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-bsw-n3050/igt@core_hotunp...@unbind-rebind.html - fi-cfl-guc: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html - fi-bxt-dsi: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-bxt-dsi/igt@core_hotunp...@unbind-rebind.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-bxt-dsi/igt@core_hotunp...@unbind-rebind.html - fi-snb-2520m: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-snb-2520m/igt@core_hotunp...@unbind-rebind.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-snb-2520m/igt@core_hotunp...@unbind-rebind.html - fi-cfl-8700k: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html - fi-byt-j1900: NOTRUN -> [INCOMPLETE][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-byt-j1900/igt@core_hotunp...@unbind-rebind.html - fi-bsw-nick:[PASS][18] -> [INCOMPLETE][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-bsw-nick/igt@core_hotunp...@unbind-rebind.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-bsw-nick/igt@core_hotunp...@unbind-rebind.html - fi-kbl-guc: [PASS][20] -> [INCOMPLETE][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-kbl-guc/igt@core_hotunp...@unbind-rebind.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-kbl-guc/igt@core_hotunp...@unbind-rebind.html - fi-skl-guc: [PASS][22] -> [INCOMPLETE][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-skl-guc/igt@core_hotunp...@unbind-rebind.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-skl-guc/igt@core_hotunp...@unbind-rebind.html - fi-snb-2600:[PASS][24] -> [INCOMPLETE][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-snb-2600/igt@core_hotunp...@unbind-rebind.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-snb-2600/igt@core_hotunp...@unbind-rebind.html - fi-kbl-x1275: [PASS][26] -> [INCOMPLETE][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-kbl-x1275/igt@core_hotunp...@unbind-rebind.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19227/fi-kbl-x1275/igt@core_hotunp...@unbind-rebind.html - fi-glk-dsi: [PASS][28] -> [INCOMPLETE][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html [29]: https://intel-g
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/dp: Remove aux xfer timeout debug message
== Series Details == Series: series starting with [1/2] drm/i915/dp: Remove aux xfer timeout debug message URL : https://patchwork.freedesktop.org/series/85315/ State : warning == Summary == $ dim checkpatch origin/drm-tip d3af34a8e551 drm/i915/dp: Remove aux xfer timeout debug message e8faa209ee7a drm/i915/dp: Track pm_qos per connector -:60: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #60: FILE: drivers/gpu/drm/i915/display/intel_dp.c:7530: } +static void intel_dp_connector_destroy(struct drm_connector *connector) total: 0 errors, 0 warnings, 1 checks, 87 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/dp: Remove aux xfer timeout debug message
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Remove aux xfer timeout debug
message
URL : https://patchwork.freedesktop.org/series/85315/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19228
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19228 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19228, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/index.html
Known issues
Here are the changes found in Patchwork_19228 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][1] ([i915#1302])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-bsw-kefka/igt@run...@aborted.html
- fi-tgl-y: NOTRUN -> [FAIL][2] ([i915#2522])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-tgl-y/igt@run...@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][3] ([i915#2295])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-skl-6600u/igt@run...@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][4] ([i915#2295] / [i915#483] /
[k.org#202107] / [k.org#202109])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-cfl-8109u/igt@run...@aborted.html
- fi-icl-u2: NOTRUN -> [FAIL][5] ([i915#1569] / [i915#2295] /
[i915#2724] / [k.org#202973])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-icl-u2/igt@run...@aborted.html
- fi-kbl-r: NOTRUN -> [FAIL][6] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#2295])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-kbl-r/igt@run...@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][7] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#2295])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-7500u: NOTRUN -> [FAIL][8] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#2295] / [i915#483])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-kbl-7500u/igt@run...@aborted.html
- fi-cml-u2: NOTRUN -> [FAIL][9] ([i915#2295])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-cml-u2/igt@run...@aborted.html
- fi-cml-s: NOTRUN -> [FAIL][10] ([i915#2295])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-cml-s/igt@run...@aborted.html
- fi-icl-y: NOTRUN -> [FAIL][11] ([i915#1569] / [i915#2295] /
[i915#2724] / [i915#483])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-icl-y/igt@run...@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][12] ([i915#2522])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-tgl-u2/igt@run...@aborted.html
Warnings
* igt@runner@aborted:
- fi-kbl-8809g: [FAIL][13] ([i915#1186] / [i915#2426]) -> [FAIL][14]
([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#2295])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-kbl-8809g/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19228/fi-kbl-8809g/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1186]: https://gitlab.freedesktop.org/drm/intel/issues/1186
[i915#1302]: https://gitlab.freedesktop.org/drm/intel/issues/1302
[i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
[i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
[i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
[i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2522]: https://gitlab.freedesktop.org/drm/intel/issues/2522
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[k.org#202107]: https://bugzilla.kernel.org/show_bug.cgi?id=202107
[k.org#202109]: https://bugzilla.kernel.org/show_bug.cgi?id=202109
[k.org#202973]: https://bugzilla.kernel.org/show_bug.cgi?id=202973
Participating hosts (42 -> 19)
--
ERROR: It appears as if the changes made in Patchwork_19228 prevented too
many machines from booting.
Missing(23): fi-apl-guc fi-snb-2520m fi-snb-2600 fi-bxt-dsi fi-bdw-5557u
fi-bsw-n3050 fi-glk-dsi fi-ilk-650 fi-ctg-p8600 fi-hsw-4770 fi-ivb-3770
fi
Re: [Intel-gfx] [PATCH] drm/i915/gt: Taint the reset mutex with the shrinker
Chris Wilson writes: > Declare that, under extreme circumstances, the shrinker may need to wait > upon a request, in which case reset must not itself deadlock in order to > ensure forward progress of the driver. That is since the shrinker may > depend upon a reset, any reset cannot touch the shrinker. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_reset.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c > b/drivers/gpu/drm/i915/gt/intel_reset.c > index b85b6f3dcd60..e14b23c3b1cb 100644 > --- a/drivers/gpu/drm/i915/gt/intel_reset.c > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c > @@ -1394,6 +1394,9 @@ void intel_gt_init_reset(struct intel_gt *gt) > mutex_init(>->reset.mutex); > init_srcu_struct(>->reset.backoff_srcu); > > + /* While undesirable to wait inside the shrinker, complain anyway */ > + i915_gem_shrinker_taints_mutex(gt->i915, >->reset.mutex); > + > /* no GPU until we are ready! */ > __set_bit(I915_WEDGED, >->reset.flags); > } > -- > 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Remove aux xfer timeout debug message
== Series Details ==
Series: drm/i915/dp: Remove aux xfer timeout debug message
URL : https://patchwork.freedesktop.org/series/85313/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9533_full -> Patchwork_19226_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_19226_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][1] -> [SKIP][2] ([i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-tglb2/igt@gem_huc_c...@huc-copy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-tglb6/igt@gem_huc_c...@huc-copy.html
* igt@gen7_exec_parse@basic-offset:
- shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271]) +23 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-skl9/igt@gen7_exec_pa...@basic-offset.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#1436] /
[i915#716])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-glk9/igt@gen9_exec_pa...@allowed-single.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-glk5/igt@gen9_exec_pa...@allowed-single.html
- shard-skl: [PASS][6] -> [DMESG-WARN][7] ([i915#1436] /
[i915#716])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl6/igt@gen9_exec_pa...@allowed-single.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-skl5/igt@gen9_exec_pa...@allowed-single.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer:
- shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111304])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-skl9/igt@kms_...@pipe-c-missing-ccs-buffer.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) +7 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-128x128-random.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-128x128-random.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][11] -> [FAIL][12] ([i915#2370])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-hsw4/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-hsw8/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#79])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html
* igt@kms_flip@plain-flip-ts-check@a-edp1:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#2122])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl2/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-skl1/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl10/igt@kms_...@bpc-switch-dpms.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-skl10/igt@kms_...@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][19] ([fdo#108145] / [i915#265])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][20] -> [FAIL][21] ([fdo#108145] / [i915#265])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#109642] / [fdo#111068])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-iclb2/igt@kms_psr2_su@page_flip.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19226/shard-iclb5/igt@kms_psr2_su@page_flip.html
Possible fixes
* {igt@gem_exec_balancer@fairslice}:
- shard-iclb: [FAIL][24] ([i915#2802]) -> [PASS][25]
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-iclb4/igt@gem_exec_balan.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Support secure dispatch on gen6/gen7
== Series Details == Series: drm/i915: Support secure dispatch on gen6/gen7 URL : https://patchwork.freedesktop.org/series/85323/ State : success == Summary == CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19229 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/index.html Known issues Here are the changes found in Patchwork_19229 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_prime@amd-to-i915: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/fi-kbl-soraka/igt@amdgpu/amd_pr...@amd-to-i915.html * igt@gem_huc_copy@huc-copy: - fi-byt-j1900: NOTRUN -> [SKIP][2] ([fdo#109271]) +27 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html * igt@prime_vgem@basic-userptr: - fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-tgl-y/igt@prime_v...@basic-userptr.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/fi-tgl-y/igt@prime_v...@basic-userptr.html Possible fixes * igt@prime_vgem@basic-fence-flip: - fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 37) -- Additional (1): fi-byt-j1900 Missing(6): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9533 -> Patchwork_19229 CI-20190529: 20190529 CI_DRM_9533: 1ebc67e5e636a2422ac68d93b87e236dcf645da0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5928: 7813bb74aec408055d564fa6a270526822cfbc0e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19229: 78185f484070051b9d68915e80176a94de028ad3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 78185f484070 drm/i915: Support secure dispatch on gen6/gen7 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/54] drm/i915: Drop i915_request.lock requirement for intel_rps_boost()
Chris Wilson writes:
> Since we use a flag within i915_request.flags to indicate when we have
> boosted the request (so that we only apply the boost) once, this can be
> used as the serialisation with i915_request_retire() to avoid having to
> explicitly take the i915_request.lock which is more heavily contended.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 15 ++-
> drivers/gpu/drm/i915/i915_request.c | 4 +---
> 2 files changed, 7 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index f74d5e09e176..e1397b8d3586 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -917,17 +917,15 @@ void intel_rps_park(struct intel_rps *rps)
>
> void intel_rps_boost(struct i915_request *rq)
> {
> - struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps;
> - unsigned long flags;
> -
> - if (i915_request_signaled(rq) || !intel_rps_is_active(rps))
> + if (i915_request_signaled(rq) || i915_request_has_waitboost(rq))
> return;
>
> /* Serializes with i915_request_retire() */
> - spin_lock_irqsave(&rq->lock, flags);
> - if (!i915_request_has_waitboost(rq) &&
> - !dma_fence_is_signaled_locked(&rq->fence)) {
> - set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags);
> + if (!test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags)) {
> + struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps;
> +
> + if (!intel_rps_is_active(rps))
> + return;
>
> GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n",
>rq->fence.context, rq->fence.seqno);
> @@ -938,7 +936,6 @@ void intel_rps_boost(struct i915_request *rq)
>
> atomic_inc(&rps->boosts);
Looks of it, this does not need to be atomic. But topic for another
patch.
> }
> - spin_unlock_irqrestore(&rq->lock, flags);
> }
>
> int intel_rps_set(struct intel_rps *rps, u8 val)
> diff --git a/drivers/gpu/drm/i915/i915_request.c
> b/drivers/gpu/drm/i915/i915_request.c
> index 2d2882344e40..2a7bad88038b 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -307,10 +307,8 @@ bool i915_request_retire(struct i915_request *rq)
> spin_unlock_irq(&rq->lock);
> }
>
> - if (i915_request_has_waitboost(rq)) {
> - GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters));
> + if (test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags))
> atomic_dec(&rq->engine->gt->rps.num_waiters);
This should keep the num_waiters in sync.
Reviewed-by: Mika Kuoppala
> - }
>
> /*
>* We only loosely track inflight requests across preemption,
> --
> 2.20.1
>
> ___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Support secure dispatch on gen6/gen7
== Series Details == Series: drm/i915: Support secure dispatch on gen6/gen7 URL : https://patchwork.freedesktop.org/series/85323/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9533_full -> Patchwork_19229_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19229_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19229_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19229_full: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-snb5/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-snb6/igt@i915_module_l...@reload-with-fault-injection.html Known issues Here are the changes found in Patchwork_19229_full that come from known issues: ### IGT changes ### Issues hit * igt@gen7_exec_parse@basic-offset: - shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271]) +22 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-skl6/igt@gen7_exec_pa...@basic-offset.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][4] -> [DMESG-WARN][5] ([i915#1436] / [i915#716]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl6/igt@gen9_exec_pa...@allowed-single.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-skl7/igt@gen9_exec_pa...@allowed-single.html * igt@i915_pm_rpm@cursor: - shard-iclb: [PASS][6] -> [INCOMPLETE][7] ([i915#189]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-iclb3/igt@i915_pm_...@cursor.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-iclb4/igt@i915_pm_...@cursor.html * igt@kms_ccs@pipe-c-missing-ccs-buffer: - shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111304]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-skl6/igt@kms_...@pipe-c-missing-ccs-buffer.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen: - shard-skl: NOTRUN -> [FAIL][9] ([i915#54]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-256x85-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen: - shard-skl: [PASS][10] -> [FAIL][11] ([i915#54]) +9 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl2/igt@kms_cursor_...@pipe-c-cursor-64x21-offscreen.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-64x21-offscreen.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2598]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#79]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-glk7/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a2.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-glk4/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a2.html * igt@kms_flip@flip-vs-suspend@b-edp1: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([i915#198]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl9/igt@kms_flip@flip-vs-susp...@b-edp1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-skl2/igt@kms_flip@flip-vs-susp...@b-edp1.html * igt@kms_flip@plain-flip-fb-recreate@c-edp1: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#2122]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9533/shard-skl4/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-skl10/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs: - shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2672]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19229/shard-skl10/igt@kms_flip_scaled_...@flip-64bpp-ytile-to-32bpp-ytilercccs.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt
[Intel-gfx] [PATCH] drm/i915/gt: Only disable preemption on gen8 render engines
The reason why we did not enable preemption on Broadwater was due to
missing GPGPU workarounds. Since this only applies to rcs0, only
restrict rcs0 (and our global capabilities).
While this does not affect exposing a preemption capability to
userspace, it does affect our internal decisions on whether to use
timeslicing and semaphores between individual engines.
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 11 -
drivers/gpu/drm/i915/gt/selftest_execlists.c | 40 +++
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_pci.c | 2 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
5 files changed, 15 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index f08ba2d1f6d6..babc19ec5c15 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3102,6 +3102,15 @@ static void execlists_park(struct intel_engine_cs
*engine)
cancel_timer(&engine->execlists.preempt);
}
+static bool can_preempt(struct intel_engine_cs *engine)
+{
+ if (INTEL_GEN(engine->i915) > 8)
+ return true;
+
+ /* GPGPU on bdw requires extra w/a; not implemented */
+ return engine->class != RENDER_CLASS;
+}
+
void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = execlists_submit_request;
@@ -3119,7 +3128,7 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
if (!intel_vgpu_active(engine->i915)) {
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) {
+ if (can_preempt(engine)) {
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
engine->flags |= I915_ENGINE_HAS_TIMESLICES;
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 080b63000a4e..76139d4356ba 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -924,6 +924,9 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
return PTR_ERR(head);
for_each_engine(engine, outer->gt, id) {
+ if (!intel_engine_has_preemption(engine))
+ continue;
+
for (i = 0; i < count; i++) {
struct i915_request *rq;
@@ -943,8 +946,8 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
if (i915_request_wait(head, 0,
2 * outer->gt->info.num_engines * (count + 2) *
(count + 3)) < 0) {
- pr_err("Failed to slice along semaphore chain of length (%d,
%d)!\n",
- count, n);
+ pr_err("%s: Failed to slice along semaphore chain of length
(%d, %d)!\n",
+ outer->name, count, n);
GEM_TRACE_DUMP();
intel_gt_set_wedged(outer->gt);
err = -EIO;
@@ -1721,12 +1724,6 @@ static int live_preempt(void *arg)
enum intel_engine_id id;
int err = -ENOMEM;
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
- if (!(gt->i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
- pr_err("Logical preemption supported, but not exposed\n");
-
if (igt_spinner_init(&spin_hi, gt))
return -ENOMEM;
@@ -1821,9 +1818,6 @@ static int live_late_preempt(void *arg)
enum intel_engine_id id;
int err = -ENOMEM;
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (igt_spinner_init(&spin_hi, gt))
return -ENOMEM;
@@ -1957,9 +1951,6 @@ static int live_nopreempt(void *arg)
* that may be being observed and not want to be interrupted.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (preempt_client_init(gt, &a))
return -ENOMEM;
if (preempt_client_init(gt, &b))
@@ -2311,9 +2302,6 @@ static int live_preempt_cancel(void *arg)
* GPU. That sounds like preemption! Plus a little bit of bookkeeping.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (preempt_client_init(gt, &data.a))
return -ENOMEM;
if (preempt_client_init(gt, &data.b))
@@ -2373,9 +2361,6 @@ static int live_suppress_self_preempt(void *arg)
* completion event.
*/
- if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
- return 0;
-
if (intel_uc_uses_guc_submission(>->uc))
return 0; /*
Re: [Intel-gfx] [PATCH] i915: fix shift warning
Quoting Arnd Bergmann (2020-12-30 15:39:14)
> From: Arnd Bergmann
>
> Randconfig builds on 32-bit machines show lots of warnings for
> the i915 driver for incorrect bit masks like:
mask is a u8.
VCS0 is 2, I915_MAX_VCS 4
(u8 & GENMASK(5, 2)) >> 2
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2584:9: error: shift count >=
> width of type [-Werror,-Wshift-count-overflow]
> return hweight64(VDBOX_MASK(&i915->gt));
>^~~~
> include/asm-generic/bitops/const_hweight.h:29:49: note: expanded from macro
> 'hweight64'
> #define hweight64(w) (__builtin_constant_p(w) ? __const_hweight64(w) :
> __arch_hweight64(w))
So it's upset by hweight64() on the unsigned long?
So hweight_long?
Or use a cast, hweight8((intel_engine_mask_t)VDMASK())?
static __always_inline int engine_count(intel_engine_mask_t mask)
{
return sizeof(mask) == 1 ? hweight8(mask) :
sizeof(mask) == 2 ? hweight16(mask) :
sizeof(mask) == 4 ? hweight32(mask) :
hweight64(mask);
}
-Chris
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[Intel-gfx] [PATCH i-g-t] i915/gem_exec_fence: Fix legacy ring selection
Fix the use of the legacy ring selection after the default context had
an engine map installed.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_fence.c | 30 --
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index a149b0227..ae47a73e5 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -26,7 +26,6 @@
#include
#include "i915/gem.h"
-#include "i915/gem_ring.h"
#include "igt.h"
#include "igt_syncobj.h"
#include "igt_sysfs.h"
@@ -761,7 +760,7 @@ static void test_concurrent(int i915, const struct
intel_execution_engine2 *e)
batch[++i] = MI_BATCH_BUFFER_END;
gem_write(i915, obj[1].handle, 0, batch, sizeof(batch));
- execbuf.rsvd1 = gem_context_create(i915);
+ execbuf.rsvd1 = gem_context_clone_with_engines(i915, 0);
execbuf.rsvd2 = spin->out_fence;
if (gen < 6)
execbuf.flags |= I915_EXEC_SECURE;
@@ -922,6 +921,7 @@ static void test_long_history(int fd, long ring_size,
unsigned flags)
const uint32_t bbe = MI_BATCH_BUFFER_END;
struct drm_i915_gem_exec_object2 obj[2];
struct drm_i915_gem_execbuffer2 execbuf;
+ const struct intel_execution_engine2 *e;
unsigned int engines[I915_EXEC_RING_MASK + 1], nengine, n, s;
unsigned long limit;
int all_fences;
@@ -932,8 +932,8 @@ static void test_long_history(int fd, long ring_size,
unsigned flags)
limit = ring_size / 3;
nengine = 0;
- for_each_physical_ring(e, fd)
- engines[nengine++] = eb_ring(e);
+ __for_each_physical_engine(fd, e)
+ engines[nengine++] = e->flags;
igt_require(nengine);
gem_quiescent_gpu(fd);
@@ -956,7 +956,7 @@ static void test_long_history(int fd, long ring_size,
unsigned flags)
obj[0].handle = igt_cork_plug(&c, fd);
igt_until_timeout(5) {
- execbuf.rsvd1 = gem_context_create(fd);
+ execbuf.rsvd1 = gem_context_clone_with_engines(fd, 0);
for (n = 0; n < nengine; n++) {
struct sync_merge_data merge;
@@ -1265,6 +1265,7 @@ static void test_syncobj_wait(int fd)
struct drm_i915_gem_exec_fence fence = {
.handle = syncobj_create(fd, 0),
};
+ const struct intel_execution_engine2 *e;
unsigned handle[I915_EXEC_RING_MASK + 1];
igt_spin_t *spin;
int n;
@@ -1298,13 +1299,13 @@ static void test_syncobj_wait(int fd)
gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
n = 0;
- for_each_ring(e, fd) {
+ __for_each_physical_engine(fd, e) {
obj.handle = gem_create(fd, 4096);
gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
/* No inter-engine synchronisation, will complete */
- if (eb_ring(e) == I915_EXEC_BLT) {
- execbuf.flags = eb_ring(e);
+ if (e->flags) {
+ execbuf.flags = e->flags;
execbuf.cliprects_ptr = 0;
execbuf.num_cliprects = 0;
gem_execbuf(fd, &execbuf);
@@ -1314,7 +1315,7 @@ static void test_syncobj_wait(int fd)
igt_assert(gem_bo_busy(fd, spin->handle));
/* Now wait upon the blocked engine */
- execbuf.flags = I915_EXEC_FENCE_ARRAY | eb_ring(e);
+ execbuf.flags = I915_EXEC_FENCE_ARRAY | e->flags;
execbuf.cliprects_ptr = to_user_pointer(&fence);
execbuf.num_cliprects = 1;
fence.flags = I915_EXEC_FENCE_WAIT;
@@ -2018,6 +2019,7 @@ static void test_syncobj_timeline_wait(int fd)
.handle = syncobj_create(fd, 0),
};
unsigned handle[I915_EXEC_RING_MASK + 1];
+ const struct intel_execution_engine2 *e;
uint64_t value = 1;
igt_spin_t *spin;
int n;
@@ -2058,13 +2060,13 @@ static void test_syncobj_timeline_wait(int fd)
gem_write(fd, obj.handle, 0, bbe, sizeof(bbe));
n = 0;
- for_each_ring(engine, fd) {
+ __for_each_physical_engine(fd, e) {
obj.handle = gem_create(fd, 4096);
gem_write(fd, obj.handle, 0, bbe, sizeof(bbe));
/* No inter-engine synchronisation, will complete */
- if (engine->flags == I915_EXEC_BLT) {
- execbuf.flags = engine->flags;
+ if (e->flags) {
+ execbuf.flags = e->flags;
execbuf.cliprects_ptr = 0;
execbuf.num_cliprects = 0;
gem_execbuf(fd, &execbuf);
@@ -2074,7 +2076,7 @@ static void test_syncobj_timeline_wait(int fd)
igt_assert(gem_bo_busy(fd, spin->handle));
/* Now wait upon the blocked engine */
- execbuf.flags = I915
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_whisper: Replace ring selection with engine map
Provide complete engine coverage by switching from the legacy ring
selection abi into the engine map.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_whisper.c | 35 ---
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/tests/i915/gem_exec_whisper.c b/tests/i915/gem_exec_whisper.c
index 263db5707..71bd610c6 100644
--- a/tests/i915/gem_exec_whisper.c
+++ b/tests/i915/gem_exec_whisper.c
@@ -28,7 +28,6 @@
*/
#include "i915/gem.h"
-#include "i915/gem_ring.h"
#include "igt.h"
#include "igt_debugfs.h"
#include "igt_rapl.h"
@@ -177,6 +176,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
struct drm_i915_gem_exec_object2 tmp[2];
struct drm_i915_gem_execbuffer2 execbuf;
unsigned engines[I915_EXEC_RING_MASK + 1];
+ const struct intel_execution_engine2 *e;
struct hang hang;
int fds[64];
uint32_t contexts[64];
@@ -203,14 +203,12 @@ static void whisper(int fd, unsigned engine, unsigned
flags)
nengine = 0;
if (engine == ALL_ENGINES) {
- for_each_physical_ring(e, fd) {
- if (gem_can_store_dword(fd, eb_ring(e)))
- engines[nengine++] = eb_ring(e);
+ __for_each_physical_engine(fd, e) {
+ if (gem_class_can_store_dword(fd, e->class))
+ engines[nengine++] = e->flags;
}
} else {
igt_assert(!(flags & ALL));
- igt_require(gem_has_ring(fd, engine));
- igt_require(gem_can_store_dword(fd, engine));
engines[nengine++] = engine;
}
igt_require(nengine);
@@ -297,15 +295,17 @@ static void whisper(int fd, unsigned engine, unsigned
flags)
if (flags & CONTEXTS) {
for (n = 0; n < 64; n++)
- contexts[n] = gem_context_create(fd);
+ contexts[n] =
gem_context_clone_with_engines(fd, 0);
}
if (flags & QUEUES) {
for (n = 0; n < 64; n++)
contexts[n] = gem_queue_create(fd);
}
if (flags & FDS) {
- for (n = 0; n < 64; n++)
+ for (n = 0; n < 64; n++) {
fds[n] = gem_reopen_driver(fd);
+ gem_context_copy_engines(fd, 0, fds[n], 0);
+ }
}
memset(batches, 0, sizeof(batches));
@@ -553,6 +553,7 @@ igt_main
{ "queues-sync", QUEUES | SYNC },
{ NULL }
};
+ const struct intel_execution_engine2 *e;
int fd = -1;
igt_fixture {
@@ -573,14 +574,18 @@ igt_main
whisper(fd, ALL_ENGINES, m->flags | ALL);
}
- for (const struct intel_execution_ring *e = intel_execution_rings;
-e->name; e++) {
- for (const struct mode *m = modes; m->name; m++) {
- if (m->flags & CHAIN)
- continue;
+ for (const struct mode *m = modes; m->name; m++) {
+ if (m->flags & CHAIN)
+ continue;
+
+ igt_subtest_with_dynamic_f("%s", m->name) {
+ __for_each_physical_engine(fd, e) {
+ if (!gem_class_can_store_dword(fd, e->class))
+ continue;
- igt_subtest_f("%s-%s", e->name, m->name)
- whisper(fd, eb_ring(e), m->flags);
+ igt_dynamic_f("%s", e->name)
+ whisper(fd, e->flags, m->flags);
+ }
}
}
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_suspend: Remove legacy ring abi
Cover all engines with the engine map API.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_suspend.c | 69 +--
1 file changed, 25 insertions(+), 44 deletions(-)
diff --git a/tests/i915/gem_exec_suspend.c b/tests/i915/gem_exec_suspend.c
index 42b0ab705..a31dd6625 100644
--- a/tests/i915/gem_exec_suspend.c
+++ b/tests/i915/gem_exec_suspend.c
@@ -31,7 +31,6 @@
#include
#include "i915/gem.h"
-#include "i915/gem_ring.h"
#include "igt.h"
#include "igt_dummyload.h"
#include "igt_gt.h"
@@ -51,7 +50,7 @@
#define CACHED (1<<8)
#define HANG (2<<8)
-static void run_test(int fd, unsigned ring, unsigned flags);
+static void run_test(int fd, unsigned engine, unsigned flags);
static void check_bo(int fd, uint32_t handle)
{
@@ -68,24 +67,7 @@ static void check_bo(int fd, uint32_t handle)
static void test_all(int fd, unsigned flags)
{
- for_each_physical_ring(e, fd)
- if (gem_can_store_dword(fd, eb_ring(e)))
- run_test(fd, eb_ring(e), flags & ~0xff);
-}
-
-static bool has_semaphores(int fd)
-{
- struct drm_i915_getparam gp;
- int val = -1;
-
- memset(&gp, 0, sizeof(gp));
- gp.param = I915_PARAM_HAS_SEMAPHORES;
- gp.value = &val;
-
- drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
- errno = 0;
-
- return val > 0;
+ run_test(fd, ALL_ENGINES, flags & ~0xff);
}
static void run_test(int fd, unsigned engine, unsigned flags)
@@ -101,25 +83,13 @@ static void run_test(int fd, unsigned engine, unsigned
flags)
nengine = 0;
if (engine == ALL_ENGINES) {
- /* If we don't have semaphores, then every ring switch
-* will result in a CPU stall until the previous write
-* has finished. This is likely to hide any issue with
-* the GPU being active across the suspend (because the
-* GPU is then unlikely to be active!)
-*/
- if (has_semaphores(fd)) {
- for_each_physical_ring(e, fd) {
- if (gem_can_store_dword(fd, eb_ring(e)))
- engines[nengine++] = eb_ring(e);
- }
- } else {
- igt_require(gem_has_ring(fd, 0));
- igt_require(gem_can_store_dword(fd, 0));
- engines[nengine++] = 0;
+ const struct intel_execution_engine2 *e;
+
+ __for_each_physical_engine(fd, e) {
+ if (gem_class_can_store_dword(fd, e->class))
+ engines[nengine++] = e->flags;
}
} else {
- igt_require(gem_has_ring(fd, engine));
- igt_require(gem_can_store_dword(fd, engine));
engines[nengine++] = engine;
}
igt_require(nengine);
@@ -301,7 +271,7 @@ igt_main
{ "-S4", HIBERNATE },
{ NULL, 0 }
}, *m;
- const struct intel_execution_ring *e;
+ const struct intel_execution_engine2 *e;
igt_hang_t hang;
int fd;
@@ -326,12 +296,23 @@ igt_main
igt_subtest("basic-S4")
run_test(fd, ALL_ENGINES, HIBERNATE);
- for (e = intel_execution_rings; e->name; e++) {
- for (m = modes; m->suffix; m++) {
- igt_subtest_f("%s-uncached%s", e->name, m->suffix)
- run_test(fd, eb_ring(e), m->mode | UNCACHED);
- igt_subtest_f("%s-cached%s", e->name, m->suffix)
- run_test(fd, eb_ring(e), m->mode | CACHED);
+ for (m = modes; m->suffix; m++) {
+ igt_subtest_with_dynamic_f("uncached-%s", m->suffix) {
+ __for_each_physical_engine(fd, e) {
+ if (!gem_class_can_store_dword(fd, e->class))
+ continue;
+ igt_dynamic_f("%s", e->name)
+ run_test(fd, e->flags, m->mode |
UNCACHED);
+ }
+ }
+
+ igt_subtest_with_dynamic_f("cached-%s", m->suffix) {
+ __for_each_physical_engine(fd, e) {
+ if (!gem_class_can_store_dword(fd, e->class))
+ continue;
+ igt_dynamic_f("%s", e->name)
+ run_test(fd, e->flags, m->mode |
CACHED);
+ }
}
}
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Track pm_qos per connector
On Wed, Dec 30, 2020 at 10:48:34AM +, Chris Wilson wrote:
> Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
> single global pm_qos does not suffice. (One connector may disable the
> dma-latency boost prematurely while the second is still depending on
> it.) Instead of a single global pm_qos, track the pm_qos request for
> each intel_dp.
>
> Fixes: 9ee32fea5fe8 ("drm/i915: irq-drive the dp aux communication")
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc: Imre Deak
Could intel_dp_aux_init/fini() be used?
> ---
> .../gpu/drm/i915/display/intel_display_types.h | 3 +++
> drivers/gpu/drm/i915/display/intel_dp.c | 16 +---
> drivers/gpu/drm/i915/i915_drv.c | 5 -
> drivers/gpu/drm/i915/i915_drv.h | 3 ---
> 4 files changed, 16 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b86ba1bdbaa3..1067bd073c95 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1463,6 +1463,9 @@ struct intel_dp {
> bool rgb_to_ycbcr;
> } dfp;
>
> + /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
> + struct pm_qos_request pm_qos;
> +
> /* Display stream compression testing */
> bool force_dsc_en;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 357f7921e070..f08e5f1f463d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1512,7 +1512,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>* lowest possible wakeup latency and so prevent the cpu from going into
>* deep sleep states.
>*/
> - cpu_latency_qos_update_request(&i915->pm_qos, 0);
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
>
> intel_dp_check_edp(intel_dp);
>
> @@ -1643,7 +1643,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>
> ret = recv_bytes;
> out:
> - cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
>
> if (vdd)
> edp_panel_vdd_off(intel_dp, false);
> @@ -7527,6 +7527,14 @@ static int intel_dp_connector_atomic_check(struct
> drm_connector *conn,
>
> return intel_modeset_synced_crtcs(state, conn);
> }
> +static void intel_dp_connector_destroy(struct drm_connector *connector)
> +{
> + struct intel_dp *intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> +
> + cpu_latency_qos_remove_request(&intel_dp->pm_qos);
> +
> + intel_connector_destroy(connector);
> +}
>
> static const struct drm_connector_funcs intel_dp_connector_funcs = {
> .force = intel_dp_force,
> @@ -7535,7 +7543,7 @@ static const struct drm_connector_funcs
> intel_dp_connector_funcs = {
> .atomic_set_property = intel_digital_connector_atomic_set_property,
> .late_register = intel_dp_connector_register,
> .early_unregister = intel_dp_connector_unregister,
> - .destroy = intel_connector_destroy,
> + .destroy = intel_dp_connector_destroy,
> .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> .atomic_duplicate_state = intel_digital_connector_duplicate_state,
> };
> @@ -8621,6 +8629,8 @@ intel_dp_init_connector(struct intel_digital_port
> *dig_port,
> intel_dp->frl.is_trained = false;
> intel_dp->frl.trained_rate_gbps = 0;
>
> + cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> +
> return true;
>
> fail:
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5708e11d917b..249f765993f7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -578,8 +578,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
>
> pci_set_master(pdev);
>
> - cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
> -
> intel_gt_init_workarounds(dev_priv);
>
> /* On the 945G/GM, the chipset reports the MSI capability on the
> @@ -626,7 +624,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
> err_msi:
> if (pdev->msi_enabled)
> pci_disable_msi(pdev);
> - cpu_latency_qos_remove_request(&dev_priv->pm_qos);
> err_mem_regions:
> intel_memory_regions_driver_release(dev_priv);
> err_ggtt:
> @@ -648,8 +645,6 @@ static void i915_driver_hw_remove(struct drm_i915_private
> *dev_priv)
>
> if (pdev->msi_enabled)
> pci_disable_msi(pdev);
> -
> - cpu_latency_qos_remove_request(&dev_priv->pm_qos);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e38a10d5c128..5e5bcef20e33 100644
>
[Intel-gfx] [PATCH v2] drm/i915/dp: Track pm_qos per connector
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
v2: Move the pm_qos setup/teardown to intel_dp_aux_init/fini
Fixes: 9ee32fea5fe8 ("drm/i915: irq-drive the dp aux communication")
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp.c| 6 --
drivers/gpu/drm/i915/i915_drv.c| 5 -
drivers/gpu/drm/i915/i915_drv.h| 3 ---
4 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b86ba1bdbaa3..1067bd073c95 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1463,6 +1463,9 @@ struct intel_dp {
bool rgb_to_ycbcr;
} dfp;
+ /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
+ struct pm_qos_request pm_qos;
+
/* Display stream compression testing */
bool force_dsc_en;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 357f7921e070..dafb1334f91a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1512,7 +1512,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* lowest possible wakeup latency and so prevent the cpu from going into
* deep sleep states.
*/
- cpu_latency_qos_update_request(&i915->pm_qos, 0);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
intel_dp_check_edp(intel_dp);
@@ -1643,7 +1643,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
ret = recv_bytes;
out:
- cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
edp_panel_vdd_off(intel_dp, false);
@@ -1919,6 +1919,7 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp
*intel_dp, int index)
static void
intel_dp_aux_fini(struct intel_dp *intel_dp)
{
+ cpu_latency_qos_remove_request(&intel_dp->pm_qos);
kfree(intel_dp->aux.name);
}
@@ -1971,6 +1972,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
encoder->base.name);
intel_dp->aux.transfer = intel_dp_aux_transfer;
+ cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
}
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..249f765993f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -578,8 +578,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
pci_set_master(pdev);
- cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
-
intel_gt_init_workarounds(dev_priv);
/* On the 945G/GM, the chipset reports the MSI capability on the
@@ -626,7 +624,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
err_mem_regions:
intel_memory_regions_driver_release(dev_priv);
err_ggtt:
@@ -648,8 +645,6 @@ static void i915_driver_hw_remove(struct drm_i915_private
*dev_priv)
if (pdev->msi_enabled)
pci_disable_msi(pdev);
-
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e38a10d5c128..5e5bcef20e33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -891,9 +891,6 @@ struct drm_i915_private {
bool display_irqs_enabled;
- /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
- struct pm_qos_request pm_qos;
-
/* Sideband mailbox protection */
struct mutex sb_lock;
struct pm_qos_request sb_qos;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/dp: Track pm_qos per connector
On Wed, Dec 30, 2020 at 05:07:34PM +, Chris Wilson wrote:
> Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
> single global pm_qos does not suffice. (One connector may disable the
> dma-latency boost prematurely while the second is still depending on
> it.) Instead of a single global pm_qos, track the pm_qos request for
> each intel_dp.
>
> v2: Move the pm_qos setup/teardown to intel_dp_aux_init/fini
>
> Fixes: 9ee32fea5fe8 ("drm/i915: irq-drive the dp aux communication")
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc: Imre Deak
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
> drivers/gpu/drm/i915/display/intel_dp.c| 6 --
> drivers/gpu/drm/i915/i915_drv.c| 5 -
> drivers/gpu/drm/i915/i915_drv.h| 3 ---
> 4 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b86ba1bdbaa3..1067bd073c95 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1463,6 +1463,9 @@ struct intel_dp {
> bool rgb_to_ycbcr;
> } dfp;
>
> + /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
> + struct pm_qos_request pm_qos;
> +
> /* Display stream compression testing */
> bool force_dsc_en;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 357f7921e070..dafb1334f91a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1512,7 +1512,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>* lowest possible wakeup latency and so prevent the cpu from going into
>* deep sleep states.
>*/
> - cpu_latency_qos_update_request(&i915->pm_qos, 0);
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
>
> intel_dp_check_edp(intel_dp);
>
> @@ -1643,7 +1643,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
>
> ret = recv_bytes;
> out:
> - cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
> + cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
>
> if (vdd)
> edp_panel_vdd_off(intel_dp, false);
> @@ -1919,6 +1919,7 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp
> *intel_dp, int index)
> static void
> intel_dp_aux_fini(struct intel_dp *intel_dp)
> {
> + cpu_latency_qos_remove_request(&intel_dp->pm_qos);
> kfree(intel_dp->aux.name);
> }
>
> @@ -1971,6 +1972,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
> encoder->base.name);
>
> intel_dp->aux.transfer = intel_dp_aux_transfer;
> + cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
> }
>
> bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5708e11d917b..249f765993f7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -578,8 +578,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
>
> pci_set_master(pdev);
>
> - cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
> -
> intel_gt_init_workarounds(dev_priv);
>
> /* On the 945G/GM, the chipset reports the MSI capability on the
> @@ -626,7 +624,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
> err_msi:
> if (pdev->msi_enabled)
> pci_disable_msi(pdev);
> - cpu_latency_qos_remove_request(&dev_priv->pm_qos);
> err_mem_regions:
> intel_memory_regions_driver_release(dev_priv);
> err_ggtt:
> @@ -648,8 +645,6 @@ static void i915_driver_hw_remove(struct drm_i915_private
> *dev_priv)
>
> if (pdev->msi_enabled)
> pci_disable_msi(pdev);
> -
> - cpu_latency_qos_remove_request(&dev_priv->pm_qos);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e38a10d5c128..5e5bcef20e33 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -891,9 +891,6 @@ struct drm_i915_private {
>
> bool display_irqs_enabled;
>
> - /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
> - struct pm_qos_request pm_qos;
> -
> /* Sideband mailbox protection */
> struct mutex sb_lock;
> struct pm_qos_request sb_qos;
> --
> 2.20.1
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/dp: Track pm_qos per connector
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
v2: Move the pm_qos setup/teardown to intel_dp_aux_init/fini
Fixes: 9ee32fea5fe8 ("drm/i915: irq-drive the dp aux communication")
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Imre Deak
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp.c| 6 --
drivers/gpu/drm/i915/i915_drv.c| 5 -
drivers/gpu/drm/i915/i915_drv.h| 3 ---
4 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b86ba1bdbaa3..1067bd073c95 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1463,6 +1463,9 @@ struct intel_dp {
bool rgb_to_ycbcr;
} dfp;
+ /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
+ struct pm_qos_request pm_qos;
+
/* Display stream compression testing */
bool force_dsc_en;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f0e8aaac413c..c23bfa9c34ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1512,7 +1512,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* lowest possible wakeup latency and so prevent the cpu from going into
* deep sleep states.
*/
- cpu_latency_qos_update_request(&i915->pm_qos, 0);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
intel_dp_check_edp(intel_dp);
@@ -1645,7 +1645,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
ret = recv_bytes;
out:
- cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
edp_panel_vdd_off(intel_dp, false);
@@ -1921,6 +1921,7 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp
*intel_dp, int index)
static void
intel_dp_aux_fini(struct intel_dp *intel_dp)
{
+ cpu_latency_qos_remove_request(&intel_dp->pm_qos);
kfree(intel_dp->aux.name);
}
@@ -1973,6 +1974,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
encoder->base.name);
intel_dp->aux.transfer = intel_dp_aux_transfer;
+ cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
}
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..249f765993f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -578,8 +578,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
pci_set_master(pdev);
- cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
-
intel_gt_init_workarounds(dev_priv);
/* On the 945G/GM, the chipset reports the MSI capability on the
@@ -626,7 +624,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
err_mem_regions:
intel_memory_regions_driver_release(dev_priv);
err_ggtt:
@@ -648,8 +645,6 @@ static void i915_driver_hw_remove(struct drm_i915_private
*dev_priv)
if (pdev->msi_enabled)
pci_disable_msi(pdev);
-
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e38a10d5c128..5e5bcef20e33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -891,9 +891,6 @@ struct drm_i915_private {
bool display_irqs_enabled;
- /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
- struct pm_qos_request pm_qos;
-
/* Sideband mailbox protection */
struct mutex sb_lock;
struct pm_qos_request sb_qos;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Only disable preemption on gen8 render engines (rev2)
== Series Details == Series: drm/i915/gt: Only disable preemption on gen8 render engines (rev2) URL : https://patchwork.freedesktop.org/series/85311/ State : success == Summary == CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19230 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/index.html Known issues Here are the changes found in Patchwork_19230 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +14 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@debugfs_test@read_all_entries: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@debugfs_test@read_all_entries.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/fi-tgl-y/igt@debugfs_test@read_all_entries.html Possible fixes * igt@gem_basic@create-fd-close: - fi-tgl-y: [DMESG-WARN][4] ([i915#402]) -> [PASS][5] +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@gem_ba...@create-fd-close.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/fi-tgl-y/igt@gem_ba...@create-fd-close.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [DMESG-WARN][6] ([i915#2411] / [i915#402]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 37) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9534 -> Patchwork_19230 CI-20190529: 20190529 CI_DRM_9534: 797de7a6fea9a997e5b529af8994b2f251779d0a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5930: 9efe3bfcb2b1c3613dddc8761425aa6943fa162d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19230: 9696c59a70b089eb02ad603705488b20f89d7024 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9696c59a70b0 drm/i915/gt: Only disable preemption on gen8 render engines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/dp: Remove aux xfer timeout debug message (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Remove aux xfer timeout debug
message (rev2)
URL : https://patchwork.freedesktop.org/series/85315/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19231
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19231 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19231, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19231:
### IGT changes ###
Possible regressions
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-guc: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-cml-s: [PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-cml-s/igt@core_hotunp...@unbind-rebind.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-cml-s/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-8700k: [PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [PASS][9] -> [DMESG-WARN][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-kbl-guc: [PASS][11] -> [DMESG-WARN][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-kbl-guc/igt@core_hotunp...@unbind-rebind.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-kbl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-glk-dsi: [PASS][13] -> [DMESG-WARN][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html
Warnings
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: [WARN][15] ([i915#2283]) -> [DMESG-WARN][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {fi-ehl-1}: [PASS][17] -> [DMESG-WARN][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-ehl-1/igt@core_hotunp...@unbind-rebind.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-ehl-1/igt@core_hotunp...@unbind-rebind.html
Known issues
Here are the changes found in Patchwork_19231 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][19] ([fdo#109271]) +14 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][20] -> [DMESG-WARN][21] ([i915#402]) +1
similar issue
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@runner@aborted:
- fi-cfl-8700k: NOTRUN -> [FAIL][22] ([i915#2283] / [i915#2295] /
[i915#483])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-cfl-8700k/igt@run...@aborted.html
- fi-icl-u2: NOTRUN -> [FAIL][23] ([i915#2283] / [i915#2295] /
[i915#2724])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19231/fi-icl-u2/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][24] ([i915#2283] / [i915#2295] /
[k.org#
[Intel-gfx] [CI] drm/i915/dp: Track pm_qos per connector
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
v2: Move the pm_qos setup/teardown to intel_dp_aux_init/fini
Fixes: 9ee32fea5fe8 ("drm/i915: irq-drive the dp aux communication")
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Imre Deak
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp.c| 8 ++--
drivers/gpu/drm/i915/i915_drv.c| 5 -
drivers/gpu/drm/i915/i915_drv.h| 3 ---
4 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b86ba1bdbaa3..1067bd073c95 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1463,6 +1463,9 @@ struct intel_dp {
bool rgb_to_ycbcr;
} dfp;
+ /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
+ struct pm_qos_request pm_qos;
+
/* Display stream compression testing */
bool force_dsc_en;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f0e8aaac413c..8a00e609085f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1512,7 +1512,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
* lowest possible wakeup latency and so prevent the cpu from going into
* deep sleep states.
*/
- cpu_latency_qos_update_request(&i915->pm_qos, 0);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
intel_dp_check_edp(intel_dp);
@@ -1645,7 +1645,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
ret = recv_bytes;
out:
- cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
+ cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
if (vdd)
edp_panel_vdd_off(intel_dp, false);
@@ -1921,6 +1921,9 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp
*intel_dp, int index)
static void
intel_dp_aux_fini(struct intel_dp *intel_dp)
{
+ if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
+ cpu_latency_qos_remove_request(&intel_dp->pm_qos);
+
kfree(intel_dp->aux.name);
}
@@ -1973,6 +1976,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
encoder->base.name);
intel_dp->aux.transfer = intel_dp_aux_transfer;
+ cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
}
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..249f765993f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -578,8 +578,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
pci_set_master(pdev);
- cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
-
intel_gt_init_workarounds(dev_priv);
/* On the 945G/GM, the chipset reports the MSI capability on the
@@ -626,7 +624,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
err_mem_regions:
intel_memory_regions_driver_release(dev_priv);
err_ggtt:
@@ -648,8 +645,6 @@ static void i915_driver_hw_remove(struct drm_i915_private
*dev_priv)
if (pdev->msi_enabled)
pci_disable_msi(pdev);
-
- cpu_latency_qos_remove_request(&dev_priv->pm_qos);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e38a10d5c128..5e5bcef20e33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -891,9 +891,6 @@ struct drm_i915_private {
bool display_irqs_enabled;
- /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
- struct pm_qos_request pm_qos;
-
/* Sideband mailbox protection */
struct mutex sb_lock;
struct pm_qos_request sb_qos;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Track pm_qos per connector
== Series Details ==
Series: drm/i915/dp: Track pm_qos per connector
URL : https://patchwork.freedesktop.org/series/85333/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19232
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19232 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19232, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19232:
### IGT changes ###
Possible regressions
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-guc: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-cml-s: [PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-cml-s/igt@core_hotunp...@unbind-rebind.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-cml-s/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-8700k: [PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [PASS][9] -> [DMESG-WARN][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-kbl-guc: [PASS][11] -> [DMESG-WARN][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-kbl-guc/igt@core_hotunp...@unbind-rebind.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-kbl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-glk-dsi: [PASS][13] -> [DMESG-WARN][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html
Warnings
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: [WARN][15] ([i915#2283]) -> [DMESG-WARN][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {fi-ehl-1}: [PASS][17] -> [DMESG-WARN][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-ehl-1/igt@core_hotunp...@unbind-rebind.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-ehl-1/igt@core_hotunp...@unbind-rebind.html
Known issues
Here are the changes found in Patchwork_19232 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][19] ([fdo#109271]) +15 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@gem_close_race@basic-threads:
- fi-tgl-y: [PASS][20] -> [DMESG-WARN][21] ([i915#402])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@gem_close_r...@basic-threads.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-tgl-y/igt@gem_close_r...@basic-threads.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][22] -> [FAIL][23] ([i915#1888])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19232/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@gem:
- fi-bsw-nick:[PASS][24] -> [DMESG-WARN][25] ([i915#2826])
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-bsw-nick/igt@i915_selftest@l...@gem.html
[25]:
https://intel-gfx-
Re: [Intel-gfx] [PATCH 03/56] drm/i915/gt: Cancel submitted requests upon context reset
Chris Wilson writes:
> Since we process schedule-in of a context after submitting the request,
> if we decide to reset the context at that time, we also have to cancel
> the requets we have marked for submission.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 22 ++-
> drivers/gpu/drm/i915/i915_request.c | 2 ++
> 2 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index b79365b5159a..18b23a332835 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -215,22 +215,32 @@ static void mark_eio(struct i915_request *rq)
> }
>
> static struct i915_request *
> -active_request(const struct intel_timeline * const tl, struct i915_request
> *rq)
> +__active_request(const struct intel_timeline * const tl,
> + struct i915_request *rq,
> + int error)
> {
> struct i915_request *active = rq;
>
> - rcu_read_lock();
> - list_for_each_entry_continue_reverse(rq, &tl->requests, link) {
> + list_for_each_entry_from_reverse(rq, &tl->requests, link) {
> if (__i915_request_is_complete(rq))
> break;
>
> + if (error) {
> + i915_request_set_error_once(rq, error);
> + __i915_request_skip(rq);
> + }
> active = rq;
> }
> - rcu_read_unlock();
>
> return active;
> }
>
> +static struct i915_request *
> +active_request(const struct intel_timeline * const tl, struct i915_request
> *rq)
> +{
> + return __active_request(tl, rq, 0);
> +}
> +
> static inline void
> ring_set_paused(const struct intel_engine_cs *engine, int state)
> {
> @@ -487,14 +497,14 @@ static void reset_active(struct i915_request *rq,
>* remain correctly ordered. And we defer to __i915_request_submit()
>* so that all asynchronous waits are correctly handled.
>*/
> - ENGINE_TRACE(engine, "{ rq=%llx:%lld }\n",
> + ENGINE_TRACE(engine, "{ reset rq=%llx:%lld }\n",
>rq->fence.context, rq->fence.seqno);
>
> /* On resubmission of the active request, payload will be scrubbed */
> if (__i915_request_is_complete(rq))
> head = rq->tail;
> else
> - head = active_request(ce->timeline, rq)->head;
> + head = __active_request(ce->timeline, rq, -EIO)->head;
> head = intel_ring_wrap(ce->ring, head);
>
> /* Scrub the context image to prevent replaying the previous batch */
> diff --git a/drivers/gpu/drm/i915/i915_request.c
> b/drivers/gpu/drm/i915/i915_request.c
> index de434697dccd..03ac6eead4db 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -490,6 +490,8 @@ void __i915_request_skip(struct i915_request *rq)
> if (rq->infix == rq->postfix)
> return;
>
> + RQ_TRACE(rq, "error: %d\n", rq->fence.error);
> +
> /*
>* As this request likely depends on state from the lost
>* context, clear out all the user operations leaving the
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Track pm_qos per connector (rev2)
== Series Details == Series: drm/i915/dp: Track pm_qos per connector (rev2) URL : https://patchwork.freedesktop.org/series/85333/ State : success == Summary == CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19233 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/index.html Known issues Here are the changes found in Patchwork_19233 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +14 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][2] -> [INCOMPLETE][3] ([i915#142] / [i915#2405]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-byt-j1900/igt@i915_pm_...@module-reload.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/fi-byt-j1900/igt@i915_pm_...@module-reload.html * igt@prime_vgem@basic-gtt: - fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@prime_v...@basic-gtt.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/fi-tgl-y/igt@prime_v...@basic-gtt.html * igt@runner@aborted: - fi-byt-j1900: NOTRUN -> [FAIL][6] ([i915#1814]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/fi-byt-j1900/igt@run...@aborted.html Possible fixes * igt@gem_basic@create-fd-close: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@gem_ba...@create-fd-close.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/fi-tgl-y/igt@gem_ba...@create-fd-close.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [DMESG-WARN][9] ([i915#2411] / [i915#402]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 36) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bsw-nick fi-bdw-samus Build changes - * Linux: CI_DRM_9534 -> Patchwork_19233 CI-20190529: 20190529 CI_DRM_9534: 797de7a6fea9a997e5b529af8994b2f251779d0a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5930: 9efe3bfcb2b1c3613dddc8761425aa6943fa162d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19233: a7992ba281fa1ed68959996728a37230f6614097 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a7992ba281fa drm/i915/dp: Track pm_qos per connector == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/gt: Cancel submitted requests upon context reset
Since we process schedule-in of a context after submitting the request,
if we decide to reset the context at that time, we also have to cancel
the requets we have marked for submission.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
.../drm/i915/gt/intel_execlists_submission.c | 22 ++-
drivers/gpu/drm/i915/i915_request.c | 2 ++
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index f08ba2d1f6d6..33c5bbaad9fe 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -215,22 +215,32 @@ static void mark_eio(struct i915_request *rq)
}
static struct i915_request *
-active_request(const struct intel_timeline * const tl, struct i915_request *rq)
+__active_request(const struct intel_timeline * const tl,
+struct i915_request *rq,
+int error)
{
struct i915_request *active = rq;
- rcu_read_lock();
- list_for_each_entry_continue_reverse(rq, &tl->requests, link) {
+ list_for_each_entry_from_reverse(rq, &tl->requests, link) {
if (__i915_request_is_complete(rq))
break;
+ if (error) {
+ i915_request_set_error_once(rq, error);
+ __i915_request_skip(rq);
+ }
active = rq;
}
- rcu_read_unlock();
return active;
}
+static struct i915_request *
+active_request(const struct intel_timeline * const tl, struct i915_request *rq)
+{
+ return __active_request(tl, rq, 0);
+}
+
static inline void
ring_set_paused(const struct intel_engine_cs *engine, int state)
{
@@ -487,14 +497,14 @@ static void reset_active(struct i915_request *rq,
* remain correctly ordered. And we defer to __i915_request_submit()
* so that all asynchronous waits are correctly handled.
*/
- ENGINE_TRACE(engine, "{ rq=%llx:%lld }\n",
+ ENGINE_TRACE(engine, "{ reset rq=%llx:%lld }\n",
rq->fence.context, rq->fence.seqno);
/* On resubmission of the active request, payload will be scrubbed */
if (__i915_request_is_complete(rq))
head = rq->tail;
else
- head = active_request(ce->timeline, rq)->head;
+ head = __active_request(ce->timeline, rq, -EIO)->head;
head = intel_ring_wrap(ce->ring, head);
/* Scrub the context image to prevent replaying the previous batch */
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index de434697dccd..03ac6eead4db 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -490,6 +490,8 @@ void __i915_request_skip(struct i915_request *rq)
if (rq->infix == rq->postfix)
return;
+ RQ_TRACE(rq, "error: %d\n", rq->fence.error);
+
/*
* As this request likely depends on state from the lost
* context, clear out all the user operations leaving the
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Only disable preemption on gen8 render engines (rev2)
== Series Details ==
Series: drm/i915/gt: Only disable preemption on gen8 render engines (rev2)
URL : https://patchwork.freedesktop.org/series/85311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9534_full -> Patchwork_19230_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_19230_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-glk8/igt@gem_exec_whis...@basic-contexts-forked-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-glk8/igt@gem_exec_whis...@basic-contexts-forked-all.html
* igt@gem_render_copy@yf-tiled-to-vebox-linear:
- shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271]) +18 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl2/igt@gem_render_c...@yf-tiled-to-vebox-linear.html
* igt@kms_chamelium@vga-hpd:
- shard-skl: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +2
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl2/igt@kms_chamel...@vga-hpd.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl1/igt@kms_co...@pipe-a-ctm-0-75.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl3/igt@kms_co...@pipe-a-ctm-0-75.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
- shard-skl: NOTRUN -> [FAIL][7] ([i915#54])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-256x85-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-skl: [PASS][8] -> [FAIL][9] ([i915#54]) +3 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-skl: [PASS][10] -> [FAIL][11] ([i915#533])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl9/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl3/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk: [PASS][12] -> [FAIL][13] ([fdo#103375])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-glk4/igt@kms_fbcon_...@fbc-suspend.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-glk4/igt@kms_fbcon_...@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][14] -> [INCOMPLETE][15] ([i915#123])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl5/igt@kms_frontbuffer_track...@psr-suspend.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl4/igt@kms_frontbuffer_track...@psr-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl2/igt@kms_pipe_crc_ba...@read-crc-pipe-d.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#1542])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl6/igt@p...@polling-parameterized.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl9/igt@p...@polling-parameterized.html
Possible fixes
* igt@gem_ctx_persistence@replace@rcs0:
- shard-skl: [FAIL][21] -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl9/igt@gem_ctx_persistence@repl...@rcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-skl9/igt@gem_ctx_persistence@repl...@rcs0.html
* {igt@gem_exec_fair@basic-deadline}:
- shard-kbl: [FAIL][23] ([i915#2846]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-kbl4/igt@gem_exec_f...@basic-deadline.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19230/shard-kbl2/igt@gem_exec_f
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Cancel submitted requests upon context reset
== Series Details == Series: drm/i915/gt: Cancel submitted requests upon context reset URL : https://patchwork.freedesktop.org/series/85336/ State : success == Summary == CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19234 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/index.html Known issues Here are the changes found in Patchwork_19234 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +7 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html * igt@gem_exec_suspend@basic-s0: - fi-cfl-8109u: [PASS][2] -> [INCOMPLETE][3] ([i915#2473]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html * igt@i915_selftest@live@execlists: - fi-tgl-u2: [PASS][4] -> [INCOMPLETE][5] ([i915#2268]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-u2/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/fi-tgl-u2/igt@i915_selftest@l...@execlists.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html * igt@runner@aborted: - fi-cfl-8109u: NOTRUN -> [FAIL][8] ([i915#2426]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/fi-cfl-8109u/igt@run...@aborted.html Possible fixes * igt@gem_basic@create-fd-close: - fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@gem_ba...@create-fd-close.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/fi-tgl-y/igt@gem_ba...@create-fd-close.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [DMESG-WARN][11] ([i915#2411] / [i915#402]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2268]: https://gitlab.freedesktop.org/drm/intel/issues/2268 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2473]: https://gitlab.freedesktop.org/drm/intel/issues/2473 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 36) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9534 -> Patchwork_19234 CI-20190529: 20190529 CI_DRM_9534: 797de7a6fea9a997e5b529af8994b2f251779d0a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5930: 9efe3bfcb2b1c3613dddc8761425aa6943fa162d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19234: 4eeadb835e81637dcaa3d8df6ba1477483cd30be @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4eeadb835e81 drm/i915/gt: Cancel submitted requests upon context reset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v16 02/13] drm/i915/pxp: set KCR reg init during the boot time
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 9bc3c7e30654..f566a4fda044 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,12 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+/* KCR register definitions */
+#define KCR_INIT_MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -15,6 +21,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_ctx_init(&pxp->ctx);
+ intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
}
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v16 01/13] drm/i915/pxp: Introduce Intel PXP component
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
arbitrary session). So Mesa can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Kconfig | 22 +++
drivers/gpu/drm/i915/Makefile| 5
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29
drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 23
9 files changed, 151 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..594775c11e19 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,28 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI
+ select INTEL_MEI_ME
+ select INTEL_MEI_TXE
+ select INTEL_MEI_PXP
+ default y
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
+ that helps to establish the hardware protected session and manage
+ the status of the alive software session, as well as its life cycle.
+
+ This patch series is to allow the kernel space to create and
+ manage a single hardware session (a.k.a default session or
+ arbitrary session). So Mesa can allocate the protected buffer,
+ which is encrypted with the leverage of the arbitrary hardware
+ session.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f9ef5199b124..53be29dbc07d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -255,6 +255,11 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 44f1d51e5ae5..d2448be36ded 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -18,6 +18,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_pxp_init(>->pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -638,6 +641,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
if (vm) /* FIXME being called twice on error paths :( */
i915_vm_put(vm);
+ intel_pxp_fini(>->pxp);
intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6d39a4a11bf3..caa3e1403945 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -120,6 +121,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..9bc3c7e30654
--- /dev/null
+++ b/drivers/gpu/drm/i
[Intel-gfx] [RFC-v16 04/13] drm/i915/pxp: Create the arbitrary session after boot
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 131 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 15 +++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 76 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 26
9 files changed, 270 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 57447887d352..2c84f75b41da 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_arb.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c819f3791ee4..3868e8c697f9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index f47bc6bea34f..8fc91e900b16 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,6 +8,22 @@
#include "intel_pxp_types.h"
+enum pxp_session_types {
+ SESSION_TYPE_TYPE0 = 0,
+ SESSION_TYPE_TYPE1 = 1,
+
+ SESSION_TYPE_MAX
+};
+
+enum pxp_protection_modes {
+ PROTECTION_MODE_NONE = 0,
+ PROTECTION_MODE_LM = 2,
+ PROTECTION_MODE_HM = 3,
+ PROTECTION_MODE_SM = 6,
+
+ PROTECTION_MODE_ALL
+};
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
new file mode 100644
index ..4df58915af88
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp_types.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
+
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
+
+static bool is_hw_arb_session_in_play(struct intel_pxp *pxp)
+{
+ u32 regval_sip = 0;
+ intel_wakeref_t wakeref;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
+ regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ }
+
+ return regval_sip & BIT(ARB_SESSION_INDEX);
+}
+
+/* wait hw session_in_play reg to match the current sw state */
+static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+ struct pxp_protected_session *arb = &pxp->ctx.arb_session;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (is_hw_arb_session_in_play(pxp) ==
+ arb->is_in_play) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+static void arb_session_entry_init(struct intel_pxp *pxp)
+{
+ struct pxp_protected_session *arb = &pxp->ctx.arb_session;
+
+ arb->type = ARB_SESSION_TYPE;
+ arb->protection_mode = PROTECTION_MODE_HM;
+ arb->index = ARB_SESSION_INDEX;
+ arb->is_in_play = false;
+}
+
+static int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
+{
+ int ret;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ arb_session_entry_init(pxp);
+ ret = wait_arb_hw_sw_state(pxp);
+
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_mark_session_in_play
[Intel-gfx] [RFC-v16 08/13] drm/i915/pxp: Enable PXP power management
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++
drivers/gpu/drm/i915/i915_drv.c| 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c| 65 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h| 31 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
6 files changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index abe52189986a..d419dfa4923d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -261,6 +261,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_arb.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 274aa0dd7050..09a64d0feafe 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -20,6 +20,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -241,6 +242,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>->uc);
+ intel_pxp_pm_resume(>->pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -275,6 +278,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>->pxp);
intel_uc_suspend(>->uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9299a456adb0..af06c85e6ba7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1344,6 +1346,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(&dev_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..ebe89262485c
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Disable PXP-IOCTLs */
+ pxp->ctx.global_state_in_suspend = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ pxp->ctx.global_state_attacked = false;
+
+ pxp->ctx.flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!pxp->ctx.inited)
+ return 0;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (pxp->ctx.global_state_in_suspend) {
+ ret = intel_pxp_arb_terminate_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to terminate the arb
session\n");
+ goto end;
+ }
+
+ pxp->ctx.global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index ..135bfb59aaf7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifde
[Intel-gfx] [RFC-v16 09/13] drm/i915/pxp: Expose session state for display protection flip
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 8
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 23d4cfc1fb1f..72f7d9d966a8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -158,3 +158,12 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
pxp->current_events |= events;
schedule_work(&pxp->irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->gt.pxp.ctx.inited &&
+ i915->gt.pxp.ctx.flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index cdaa6ce6fdca..976baf9b08e3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -29,6 +29,8 @@ enum pxp_protection_modes {
PROTECTION_MODE_ALL
};
+struct drm_i915_private;
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
@@ -36,6 +38,7 @@ int i915_pxp_global_terminate_complete_callback(struct
intel_pxp *pxp);
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -58,6 +61,11 @@ static inline void intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
#endif
#endif /* __INTEL_PXP_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v16 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 24 -
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 -
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
7 files changed, 139 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 9830342aa6f4..b92072554ab3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -14,6 +14,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -107,6 +108,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>->pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..1e8dfe435ca8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7944,6 +7944,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
@@ -7966,7 +7967,7 @@ enum {
#define GEN11_VECS0_VECS1_INTR_MASK_MMIO(0x1900d0)
#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
-#define GEN11_CRYPTO_RSVD_INTR_MASK_MMIO(0x1900f0)
+#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in
bit31-16 (Engine1 Interrupt Mask) */
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
#define ENGINE1_MASK REG_GENMASK(31, 16)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2f63801748f8..fa15e3ad2f92 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -14,6 +14,70 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16);
+}
+
+static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ int ret;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ pxp->ctx.global_state_attacked = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_attacked) {
+ pxp->ctx.global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_arb_create_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to create arb
session\n");
+ goto end;
+ }
+ }
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>->irq_lock);
+ events = fetch_and_zero(&pxp->current_events);
+ spin_unlock_irq(>->irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(pxp);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(pxp);
+
+ spin_lock_irq(>->irq_lock);
+ intel_pxp_write_irq_mask_reg(gt, 0);
+ spin_unlock_irq(>->irq_lock);
+}
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -40,6 +104,12 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_tee_component_init(pxp);
+ INIT_WORK(&pxp->irq_work, intel_pxp_irq_work);
+
+
[Intel-gfx] [RFC-v16 07/13] drm/i915/pxp: Destroy arb session upon teardown
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 130 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++-
5 files changed, 212 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index fa15e3ad2f92..23d4cfc1fb1f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct
intel_pxp *pxp)
mutex_lock(&pxp->ctx.mutex);
pxp->ctx.global_state_attacked = true;
+ pxp->ctx.flag_display_hm_surface_keys = false;
+
+ ret = intel_pxp_arb_terminate_session(pxp);
mutex_unlock(&pxp->ctx.mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
index 4df58915af88..2038d4638711 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -10,6 +10,7 @@
#include "intel_pxp_arb.h"
#include "intel_pxp.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_cmd.h"
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
@@ -129,3 +130,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
return ret;
}
+
+static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>->i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_cmd_submit()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_terminate_session - Terminate the arb hw session and its
entries.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be
protected by
+ * ctx.mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ struct pxp_protected_session *arb = &pxp->ctx.arb_session;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_arb_session_with_global_termination(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to
intel_pxp_arb_session_with_global_termination\n");
+ return ret;
+ }
+
+ arb->is_in_play = false;
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
index 1eb8db6deb0e..c1ed4ab176aa 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -11,5 +11,6 @@
struct intel_pxp;
int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index d9298cf5e1a7..ae338ab2e629 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -5,13 +5,33 @@
#include "intel_pxp_cmd.h"
#include "i915_drv.h"
+#include "gt/intel_gp
[Intel-gfx] [RFC-v16 05/13] drm/i915/pxp: Func to send hardware session termination
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 158 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 +
5 files changed, 194 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2c84f75b41da..abe52189986a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -259,6 +259,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3868e8c697f9..2f63801748f8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -17,10 +17,23 @@
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int i;
if (INTEL_GEN(gt->i915) < 12)
return;
+ /* Find the first VCS engine present */
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (HAS_ENGINE(gt, _VCS(i))) {
+ pxp->vcs_engine = gt->engine[_VCS(i)];
+ break;
+ }
+ }
+ if (!pxp->vcs_engine) {
+ drm_err(>->i915->drm, "Could not find a VCS engine\n");
+ return;
+ }
+
intel_pxp_ctx_init(&pxp->ctx);
intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index ..d9298cf5e1a7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+struct intel_context *ce,
+struct intel_gt_buffer_pool_node *pool,
+u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>->i915->drm, "Failed to %s, invalid
cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>->i915->drm, "Failed to
i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>->i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ ce = pxp->vcs_engine->kernel_context;
+ if (!ce) {
+ drm_err(>->i915->drm, "VCS engine does not have context\n");
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(>->i915->drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_b
[Intel-gfx] [RFC-v16 10/13] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+
[Intel-gfx] [RFC-v16 12/13] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c7363036765a..12847edec751 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2019,12 +2019,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index b5c908f3f4f2..f991e882bbe0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 1449f54924e0..0917c9431c65 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -134,7 +134,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c53b13c02e59..611a0b5ab51f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
[Intel-gfx] [RFC-v16 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Cc: Matthew Auld matthew.a...@intel.com
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 -
include/uapi/drm/i915_drm.h | 47 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af06c85e6ba7..3dbda949bf71 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1733,7 +1733,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 17a4636ee542..c53b13c02e59 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6edcb2b6c708..e918ccc81c74 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size fo
[Intel-gfx] [RFC-v16 00/13] Introduce Intel PXP component - Mesa single session
PXP (Protected Xe Path) is an i915 component, available on GEN12+ that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. This patch series is to allow the kernel space to create and manage a single hardware session (a.k.a. default session or arbitrary session). So user can allocate the protected buffer, which is encrypted with the leverage of the arbitrary hardware session. v2: - modification based on code review feedbacks received - passing pxp instead of i915 as function argument - remove dead code only for multi-session - move the pxp init call from i915_drv.c to intel_gt.c - remove the tautology naming v3: - rebase to latest drm-tip v4: - Append the split non-mesa patch sereis (commit #14 - #21) into this patch series v5: - include "intel_pxp.h" in intel_pxp_sm.h at commit #14 to fix the build problem. v6: - Fix the null pointer arb_session access bug in intel_pxp_arb.c in "04 [RFC-v5] drm/i915/pxp: Create the arbitrary session after boot" v7: - Use list_for_each_entry_safe instead of list_for_each_entry v8: - Add MEI vtag support for PXP multi-session usage v9: - Fix error handling bug in commit #5 "Func to send hardware session termination". In intel_pxp_cmd.c, we should properly assign "err = PTR_ERR(x)" if hitting the error case "IS_ERR(x)", this is the only change in v9. v10 - Remove the multi session commits #14-#21, for now we would like to keep the multi session patches as downstream. - Adopt the code review suggestion from Wilson in commit #1 v11 - In commit #05 "drm/i915/pxp: Func to send hardware session termination", we should not assume VCS0 is always on. Instead we use available VCS#, could be VCS0, VCS2, etc. v12 - Add "#include in #1 intel_pxp_types.h v13 - Add "#include in #1 intel_pxp_types.h (#v12 didn't actually update the _types.h file...) v14 - Add "if (INTEL_GEN(gt->i915) < 12) return;" in #1 intel_pxp_fini(), just skip for non gen12+ sku v15 In #04: - Make intel_pxp_arb_reserve_session() as static function to fix the sparse warning - Update value of PXP_TEE_ARB_CMD_BIN v16 In #04: - Remove the binary from source code via defining the TEE command header Anshuman Gupta (1): drm/i915/pxp: Add plane decryption support Bommu Krishnaiah (2): drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915/pxp: User interface for Protected buffer Huang, Sean Z (9): drm/i915/pxp: Introduce Intel PXP component drm/i915/pxp: set KCR reg init during the boot time drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Func to send hardware session termination drm/i915/pxp: Enable PXP irq worker and callback stub drm/i915/pxp: Destroy arb session upon teardown drm/i915/pxp: Enable PXP power management drm/i915/pxp: Expose session state for display protection flip Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Kconfig | 22 ++ drivers/gpu/drm/i915/Makefile | 9 + drivers/gpu/drm/i915/display/intel_sprite.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 + drivers/gpu/drm/i915/gt/intel_gt.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/i915_drv.c | 7 +- drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_gem.c | 63 +++- drivers/gpu/drm/i915/i915_reg.h | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 169 +++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 71 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 207 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 16 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 278 ++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 20 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 208 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 60 drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile | 7 + dri
[Intel-gfx] [RFC-v16 13/13] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah
Cc: Huang, Sean Z
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7e208816074..273bdc031e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include
#include
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -767,6 +769,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -803,6 +810,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -813,7 +821,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -889,8 +897,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e8dfe435ca8..0ea7e2a402ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7209,6 +7209,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v16 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 132 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
8 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 53be29dbc07d..57447887d352 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..9299a456adb0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c2d0156e8a5d..aaf452115c2f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1212,6 +1212,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index f566a4fda044..c819f3791ee4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
@@ -23,6 +24,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ intel_pxp_tee_component_init(pxp);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
}
@@ -33,5 +36,7 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (INTEL_GEN(gt->i915) < 12)
return;
+ intel_pxp_tee_component_fini(pxp);
+
intel_pxp_ctx_fini(&pxp->ctx);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..ca6b61099aee
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(&i915->pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size,
true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in,
msg_in_size);
+ if (ret) {
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Track pm_qos per connector (rev2)
== Series Details == Series: drm/i915/dp: Track pm_qos per connector (rev2) URL : https://patchwork.freedesktop.org/series/85333/ State : success == Summary == CI Bug Log - changes from CI_DRM_9534_full -> Patchwork_19233_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19233_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-queued: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-hsw6/igt@gem_ctx_persiste...@engines-queued.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][2] ([i915#2389]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_suspend@basic-s3: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#198]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl5/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-skl5/igt@gem_exec_susp...@basic-s3.html * igt@gem_exec_whisper@basic-forked: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-glk2/igt@gem_exec_whis...@basic-forked.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-glk4/igt@gem_exec_whis...@basic-forked.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][7] -> [SKIP][8] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-tglb3/igt@gem_huc_c...@huc-copy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_render_copy@yf-tiled-to-vebox-linear: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271]) +20 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-skl4/igt@gem_render_c...@yf-tiled-to-vebox-linear.html * igt@i915_selftest@live@execlists: - shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([i915#1037] / [i915#2268]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-tglb8/igt@i915_selftest@l...@execlists.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-tglb2/igt@i915_selftest@l...@execlists.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][12] -> [FAIL][13] ([i915#2521]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl3/igt@kms_async_fl...@alternate-sync-async-flip.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-skl9/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_chamelium@vga-hpd: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-skl4/igt@kms_chamel...@vga-hpd.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl1/igt@kms_co...@pipe-a-ctm-0-75.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-skl2/igt@kms_co...@pipe-a-ctm-0-75.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen: - shard-skl: NOTRUN -> [FAIL][17] ([i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-skl4/igt@kms_cursor_...@pipe-a-cursor-256x85-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-512x170-offscreen: - shard-hsw: NOTRUN -> [SKIP][18] ([fdo#109271]) +18 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-hsw6/igt@kms_cursor_...@pipe-a-cursor-512x170-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#54]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-skl1/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#2346]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19233/shard-skl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html * igt@kms_draw_crc@draw-method-xrgb-mmap-wc-xtiled: - shard-iclb: [PASS][23] -> [FAIL][24] ([i915#52] / [i915#54]) [23]: https://intel-gfx-ci.01.org/tree/drm-ti
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev16)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev16) URL : https://patchwork.freedesktop.org/series/84620/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8aed24199142 drm/i915/pxp: Introduce Intel PXP component -:118: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #118: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 193 lines checked b592a796b743 drm/i915/pxp: set KCR reg init during the boot time e4264e01aa94 drm/i915/pxp: Implement funcs to create the TEE channel -:8: WARNING:TYPO_SPELLING: 'defualt' may be misspelled - perhaps 'default'? #8: (defualt) session. ^^^ -:85: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #85: new file mode 100644 total: 0 errors, 2 warnings, 0 checks, 248 lines checked ab55d9be302d drm/i915/pxp: Create the arbitrary session after boot -:68: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #68: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 332 lines checked ea76770452ca drm/i915/pxp: Func to send hardware session termination -:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #53: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 222 lines checked 65d2240712a3 drm/i915/pxp: Enable PXP irq worker and callback stub -:51: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns #51: FILE: drivers/gpu/drm/i915/i915_reg.h:7970: +#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */ total: 0 errors, 1 warnings, 0 checks, 230 lines checked 38932d6a21c8 drm/i915/pxp: Destroy arb session upon teardown abf3730afd37 drm/i915/pxp: Enable PXP power management -:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #78: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 148 lines checked f29d81563732 drm/i915/pxp: Expose session state for display protection flip d1dc22967a77 mei: pxp: export pavp client to me client bus -:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #32: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 277 lines checked c81e764afe72 drm/i915/uapi: introduce drm_i915_gem_create_ext -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas Lahtinen joonas.lahti...@linux.intel.com' #12: Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com -:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld matthew.a...@intel.com' #13: Cc: Matthew Auld matthew.a...@intel.com -:46: ERROR:CODE_INDENT: code indent should use tabs where possible #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #50: FILE: drivers/gpu/drm/i915/i915_gem.c:269: +static int __create_setparam(struct drm_i915_gem_object_param *args, + struct create_ext *ext_data) -:95: CHECK:LINE_SPACING: Please don't use multiple blank lines #95: FILE: drivers/gpu/drm/i915/i915_gem.c:317: + + -:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #107: FILE: include/uapi/drm/i915_drm.h:395: +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext) -:155: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #155: FILE: include/uapi/drm/i915_drm.h:1736: +#define I915_OBJECT_PARAM (1ull<<32) ^ total: 3 errors, 2 warnings, 3 checks, 136 lines checked ee26ecaf8af3 drm/i915/pxp: User interface for Protected buffer 9f32310f5ad3 drm/i915/pxp: Add plane decryption support ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V2] drm/i915/cml : Add TGP PCH support
On Mon, Dec 28, 2020 at 11:42:35AM +0530, Tejas Upadhyay wrote:
> We have TGP PCH support for Tigerlake and Rocketlake. Similarly
> now TGP PCH can be used with Cometlake CPU.
Based on the 'compatibility' section of bspec 49181, I think the TGP PCH
can technically be compatible with any gen9bc platform, not just CML.
Although it seems unlikely that anyone is going to go back and create
new products with a SKL+TGP pairing or something at this point, it's
still probably best to write this patch based on GEN9_BC rather than
CML.
>
> Changes since V1 :
> - Matched HPD Pin mapping for PORT C and PORT D of CML CPU.
>
> Cc : Matt Roper
> Cc : Ville Syrjälä
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
> drivers/gpu/drm/i915/display/intel_display.c | 5 +
> drivers/gpu/drm/i915/display/intel_hdmi.c| 3 ++-
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 17eaa56c5a99..181d60a5e145 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5301,7 +5301,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private
> *dev_priv,
> static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - if (port >= PORT_TC1)
> + if (IS_COMETLAKE(dev_priv) && port >= PORT_C)
> + return HPD_PORT_TC1 + port + 1 - PORT_TC1;
> + else if (port >= PORT_TC1)
> return HPD_PORT_TC1 + port - PORT_TC1;
> else
> return HPD_PORT_A + port - PORT_A;
> @@ -5455,7 +5457,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
>
> if (IS_DG1(dev_priv))
> encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
> - else if (IS_ROCKETLAKE(dev_priv))
> + else if (IS_ROCKETLAKE(dev_priv) || (IS_COMETLAKE(dev_priv) &&
> + HAS_PCH_TGP(dev_priv)))
> encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
> else if (INTEL_GEN(dev_priv) >= 12)
I'd suggest leaving the RKL condition alone since nothing here has
anything to do with RKL. Instead change the gen12+ condition to
HAS_PCH_TGP() and update the TGP-specific handler to do the port mapping
described on bspec 49181.
Plus I don't think what you have here would map the ports correctly
anyway. gen9 PORT_C/PORT_D would map to HPD_PORT_C/HPD_PORT_TC1 with
the logic here, whereas the bspec says they should map to
HPD_PORT_TC1/HPD_PORT_TC2.
> encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f2c48e5cdb43..47014471658f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16163,6 +16163,11 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_ddi_init(dev_priv, PORT_F);
>
> icl_dsi_init(dev_priv);
> + } else if (IS_COMETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv)) {
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + intel_ddi_init(dev_priv, PORT_C);
> + intel_ddi_init(dev_priv, PORT_D);
As noted before, this relates to gen9bc in general, not just CML.
Is the only reason for this block because TGP's instance of SFUSE_STRAP
doesn't have output presence bits anymore? If you want, you could keep
using the existing gen9bc block for consistency, but make the
SFUSE_STRAP checks themselves conditional on a platform that has the
presence bits. E.g.,
/* ICP+ no longer has port presence bits */
found = INTEL_PCH_TYPE(dev_priv) >= PCH_ICP ?
~0 : intel_de_read(dev_priv, SFUSE_STRAP);
> } else if (IS_GEN9_LP(dev_priv)) {
> /*
>* FIXME: Broxton doesn't support port detection via the
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index c5959590562b..540c9d54b595 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3174,7 +3174,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
> - else if (IS_ROCKETLAKE(dev_priv))
> + else if (IS_ROCKETLAKE(dev_priv) || (IS_COMETLAKE(dev_priv) &&
> + HAS_PCH_TGP(dev_priv)))
> ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
As above, none of the changes in this patch have any relation to RKL, so
it doesn't make sense to update the RKL condition. Instead just add the
gen9bc port mapping logic to icl_port_to_ddc_pin().
Plus, it looks like what
Re: [Intel-gfx] [PATCH] drm/i915/dp: Remove aux xfer timeout debug message
On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> The timeouts are frequent and expected. We will complain if we retry so
> often as to lose patience and give up, so the cacophony from individual
> complaints is redundant.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8ae769b18879..704e4cebf7f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1613,8 +1613,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> /* Timeouts occur when the device isn't connected, so they're
>* "normal" -- don't fill the kernel log with these */
> if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
> - drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
> - intel_dp->aux.name, status);
> ret = -ETIMEDOUT;
> goto out;
> }
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce Intel PXP component - Mesa single session (rev16)
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev16)
URL : https://patchwork.freedesktop.org/series/84620/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19235
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19235 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19235, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19235:
### IGT changes ###
Possible regressions
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@core_hotunp...@unbind-rebind.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/fi-tgl-y/igt@core_hotunp...@unbind-rebind.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {fi-tgl-dsi}: [PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-dsi/igt@core_hotunp...@unbind-rebind.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/fi-tgl-dsi/igt@core_hotunp...@unbind-rebind.html
Known issues
Here are the changes found in Patchwork_19235 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +14 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@gem_mmap_gtt@basic:
- fi-tgl-y: [PASS][8] -> [DMESG-WARN][9] ([i915#402]) +2 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@gem_mmap_...@basic.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/fi-tgl-y/igt@gem_mmap_...@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-bxt-dsi: [PASS][10] -> [DMESG-FAIL][11] ([i915#2291])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@runner@aborted:
- fi-tgl-y: NOTRUN -> [FAIL][12] ([i915#1602])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/fi-tgl-y/igt@run...@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][13] ([i915#1602])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/fi-tgl-u2/igt@run...@aborted.html
Possible fixes
* igt@gem_basic@create-fd-close:
- fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +2
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/fi-tgl-y/igt@gem_ba...@create-fd-close.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19235/fi-tgl-y/igt@gem_ba...@create-fd-close.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (42 -> 37)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9534 -> Patchwork_19235
CI-20190529: 20190529
CI_DRM_9534: 797de7a6fea9a997e5b529af8994b2f251779d0a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5930: 9efe3bfcb2b1c3613dddc8761425aa6943fa162d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19235: 9f32310f5ad30db2ee47c8b477b0c1ba0222c9bf @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9f32310f5ad3 drm/i915/pxp: Add plane decryption support
ee26ecaf8af3 drm/i915/pxp: User interface for Protected buffer
c81e764afe72 drm/i915/uapi: introduce drm_i915_gem_create_ext
d1dc22967a77 mei: pxp: export pavp client to me client bus
f29d81563732 drm/i91
Re: [Intel-gfx] [PATCH] drm/i915/dp: Remove aux xfer timeout debug message
On Wed, 2020-12-30 at 16:02 -0800, Matt Roper wrote:
> On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> > The timeouts are frequent and expected. We will complain if we
> > retry so
> > often as to lose patience and give up, so the cacophony from
> > individual
> > complaints is redundant.
> >
> > Signed-off-by: Chris Wilson
>
> Reviewed-by: Matt Roper
>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> > 1 file changed, 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8ae769b18879..704e4cebf7f3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1613,8 +1613,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> > /* Timeouts occur when the device isn't connected, so they're
> > * "normal" -- don't fill the kernel log with these */
> > if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
> > - drm_dbg_kms(&i915->drm, "%s: timeout (status
> > 0x%08x)\n",
> > - intel_dp->aux.name, status);
AUX timeout logs are very important for TGL TCSS Display debugging. We
actually can get AUX timeout when the display is connected for the
following reasons:
* If AUX orientation is not configured correctly in BIOS
* If USB3 dock is downgraded to USB2 and SBU/AUX lines are disabled
* When LTTPR/Retimer started to act funny and not configured correctly
by EC
* When we have a bug in the PMC mux configuration because of bug in the
following files: drivers/usb/typec/mux/intel_pmc_mux.c and
drivers/platform/x86/intel_scu_ipc.c
* When user space is not cleanly disconnected all MST connectors for
disconnected MST hub with 2+ display. We will be left with enabled
pipes although the cable is disconnected and next connect of type-c
display will give aux timeout:
** User space fix in Chrome:
https://chromium-review.googlesource.com/c/chromium/src/+/2512550/
** WA in driver: https://patchwork.freedesktop.org/patch/395901/
These logs are especially important for Chrome based platforms with
type-C. Seeing these logs we can know who is screwing up (TCSS driver,
CB, or EC).
By removing this log we are left with a generic error from
drm_dp_dpcd_access:
DRM_DEBUG_KMS("%s: Too many retries, giving up. First error: %d\n",
aux->name, err);
I know these Aux timeout logs are annoying, but at least can we use the
same log level used for printing aux transaction in
drm_dp_helper.c/drm_dp_dump_access (DRM_DEBUG_DP)
if (ret > 0)
DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
aux->name, offset, arrow, ret, min(ret,
20), buffer);
else
DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
aux->name, offset, arrow, ret);
Thanks
Khaled
> > ret = -ETIMEDOUT;
> > goto out;
> > }
> > --
> > 2.20.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Cancel submitted requests upon context reset
== Series Details == Series: drm/i915/gt: Cancel submitted requests upon context reset URL : https://patchwork.freedesktop.org/series/85336/ State : success == Summary == CI Bug Log - changes from CI_DRM_9534_full -> Patchwork_19234_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19234_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] ([i915#1373]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-tglb7/igt@gem_ctx_isolation@preservation...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-tglb2/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@close-replace-race: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#1292]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-glk5/igt@gem_ctx_persiste...@close-replace-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-glk9/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_exec_whisper@basic-forked: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-glk2/igt@gem_exec_whis...@basic-forked.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-glk1/igt@gem_exec_whis...@basic-forked.html * igt@gem_render_copy@yf-tiled-to-vebox-linear: - shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271]) +16 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-skl3/igt@gem_render_c...@yf-tiled-to-vebox-linear.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][8] -> [DMESG-WARN][9] ([i915#1436] / [i915#716]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-glk4/igt@gen9_exec_pa...@allowed-all.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-glk8/igt@gen9_exec_pa...@allowed-all.html * igt@kms_atomic_transition@plane-all-modeset-transition@dp-1-pipe-b: - shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([i915#165] / [i915#180] / [i915#78]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-kbl7/igt@kms_atomic_transition@plane-all-modeset-transit...@dp-1-pipe-b.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transit...@dp-1-pipe-b.html * igt@kms_chamelium@vga-hpd: - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-skl3/igt@kms_chamel...@vga-hpd.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +6 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-random: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#165]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-kbl7/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-kbl2/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#198]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl3/igt@kms_fbcon_...@psr-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-skl2/igt@kms_fbcon_...@psr-suspend.html * igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1: - shard-skl: NOTRUN -> [FAIL][19] ([i915#2122]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-skl3/igt@kms_flip@flip-vs-blocking-wf-vbl...@b-edp1.html * igt@kms_flip@plain-flip-fb-recreate@c-edp1: - shard-tglb: [PASS][20] -> [FAIL][21] ([i915#2122]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-tglb2/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-tglb1/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][22] -> [FAIL][23] ([i915#1188]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9534/shard-skl6/igt@kms_...@bpc-switch-suspend.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19234/shard-skl8/igt@kms_...@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-d:
