[Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce Intel PXP component - Mesa single session (rev18)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev18) URL : https://patchwork.freedesktop.org/series/84620/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9540 -> Patchwork_19242 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19242 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19242, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19242: ### IGT changes ### Possible regressions * igt@core_hotunplug@unbind-rebind: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9540/fi-tgl-y/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-tgl-y/igt@core_hotunp...@unbind-rebind.html Suppressed The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@core_hotunplug@unbind-rebind: - {fi-tgl-dsi}: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9540/fi-tgl-dsi/igt@core_hotunp...@unbind-rebind.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-tgl-dsi/igt@core_hotunp...@unbind-rebind.html Known issues Here are the changes found in Patchwork_19242 that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9540/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html * igt@i915_selftest@live@gem_contexts: - fi-skl-6600u: [PASS][7] -> [INCOMPLETE][8] ([i915#198] / [i915#2369]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9540/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@gt_heartbeat: - fi-skl-6600u: [PASS][9] -> [DMESG-WARN][10] ([i915#1909]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9540/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9540/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html * igt@runner@aborted: - fi-tgl-y: NOTRUN -> [FAIL][13] ([i915#1602]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-tgl-y/igt@run...@aborted.html - fi-skl-6600u: NOTRUN -> [FAIL][14] ([i915#1436] / [i915#2295]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-skl-6600u/igt@run...@aborted.html - fi-tgl-u2: NOTRUN -> [FAIL][15] ([i915#1602]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-tgl-u2/igt@run...@aborted.html Possible fixes * igt@gem_flink_basic@bad-flink: - fi-tgl-y: [DMESG-WARN][16] ([i915#402]) -> [PASS][17] +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9540/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19242/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#1909]: https://gitlab.freedesktop.org/drm/intel/issues/1909 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (38 -> 35) -- Missing(3): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Buil
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev18)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev18) URL : https://patchwork.freedesktop.org/series/84620/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5563c334a132 drm/i915/pxp: Introduce Intel PXP component -:118: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #118: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 193 lines checked d18d1ffc3b09 drm/i915/pxp: set KCR reg init during the boot time 62e923b397bf drm/i915/pxp: Implement funcs to create the TEE channel -:8: WARNING:TYPO_SPELLING: 'defualt' may be misspelled - perhaps 'default'? #8: (defualt) session. ^^^ -:85: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #85: new file mode 100644 total: 0 errors, 2 warnings, 0 checks, 253 lines checked b9c23f9d8a3d drm/i915/pxp: Create the arbitrary session after boot -:68: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #68: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 326 lines checked 3aca90a9101d drm/i915/pxp: Func to send hardware session termination -:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #53: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 222 lines checked 54cd7f2eef9f drm/i915/pxp: Enable PXP irq worker and callback stub -:51: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns #51: FILE: drivers/gpu/drm/i915/i915_reg.h:7970: +#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */ total: 0 errors, 1 warnings, 0 checks, 230 lines checked 56d17ead8565 drm/i915/pxp: Destroy arb session upon teardown efae4a518516 drm/i915/pxp: Enable PXP power management -:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #78: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 148 lines checked ad523799bca4 drm/i915/pxp: Expose session state for display protection flip e9ca6f2f5dde mei: pxp: export pavp client to me client bus -:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #32: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 277 lines checked 74c1edd02abd drm/i915/uapi: introduce drm_i915_gem_create_ext -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas Lahtinen joonas.lahti...@linux.intel.com' #12: Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com -:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld matthew.a...@intel.com' #13: Cc: Matthew Auld matthew.a...@intel.com -:46: ERROR:CODE_INDENT: code indent should use tabs where possible #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #50: FILE: drivers/gpu/drm/i915/i915_gem.c:269: +static int __create_setparam(struct drm_i915_gem_object_param *args, + struct create_ext *ext_data) -:95: CHECK:LINE_SPACING: Please don't use multiple blank lines #95: FILE: drivers/gpu/drm/i915/i915_gem.c:317: + + -:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #107: FILE: include/uapi/drm/i915_drm.h:395: +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext) -:155: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #155: FILE: include/uapi/drm/i915_drm.h:1736: +#define I915_OBJECT_PARAM (1ull<<32) ^ total: 3 errors, 2 warnings, 3 checks, 136 lines checked ba4c333f604a drm/i915/pxp: User interface for Protected buffer fecbf74da7aa drm/i915/pxp: Add plane decryption support ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v18 12/13] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah This api allow user mode to create Protected buffer and context creation. Signed-off-by: Bommu Krishnaiah Cc: Telukuntla Sreedhar Cc: Kondapally Kalyan Cc: Gupta Anshuman Cc: Huang Sean Z --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 19 +-- drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 drivers/gpu/drm/i915/i915_gem.c | 23 +++ include/uapi/drm/i915_drm.h | 19 +++ 6 files changed, 66 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 68f58762d5e3..00d7ca3071e7 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -81,6 +81,8 @@ #include "i915_trace.h" #include "i915_user_extensions.h" +#include "pxp/intel_pxp.h" + #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 static struct i915_global_gem_context { @@ -2022,12 +2024,25 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv, case I915_CONTEXT_PARAM_RECOVERABLE: if (args->size) ret = -EINVAL; - else if (args->value) - i915_gem_context_set_recoverable(ctx); + else if (args->value) { + if (!i915_gem_context_is_protected(ctx)) + i915_gem_context_set_recoverable(ctx); + else + ret = -EPERM; + } else i915_gem_context_clear_recoverable(ctx); break; + case I915_CONTEXT_PARAM_PROTECTED_CONTENT: + if (args->size) + ret = -EINVAL; + else if (args->value) + ret = intel_pxp_gem_context_set_protected(ctx->i915, + &ctx->user_flags, + UCONTEXT_PROTECTED); + break; + case I915_CONTEXT_PARAM_PRIORITY: ret = set_priority(ctx, args); break; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h index b5c908f3f4f2..173154fdc311 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h @@ -70,6 +70,11 @@ static inline void i915_gem_context_set_recoverable(struct i915_gem_context *ctx set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags); } +static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx) +{ + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags); +} + static inline void i915_gem_context_clear_recoverable(struct i915_gem_context *ctx) { clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h index 1449f54924e0..0917c9431c65 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h @@ -134,7 +134,7 @@ struct i915_gem_context { #define UCONTEXT_BANNABLE 2 #define UCONTEXT_RECOVERABLE 3 #define UCONTEXT_PERSISTENCE 4 - +#define UCONTEXT_PROTECTED 5 /** * @flags: small set of booleans */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index e2d9b7e1e152..90ac955463f4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -161,6 +161,11 @@ struct drm_i915_gem_object { } mmo; I915_SELFTEST_DECLARE(struct list_head st_link); + /** +* @user_flags: small set of booleans set by the user +*/ + unsigned long user_flags; +#define I915_BO_PROTECTED BIT(0) unsigned long flags; #define I915_BO_ALLOC_CONTIGUOUS BIT(0) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c53b13c02e59..611a0b5ab51f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -184,7 +184,8 @@ static int i915_gem_create(struct drm_file *file, struct intel_memory_region *mr, u64 *size_p, - u32 *handle_p) + u32 *handle_p, + u64 user_flags) { struct drm_i915_gem_object *obj; u32 handle; @@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file, if (IS_ERR(obj)) return PTR_ERR(obj); + obj->user_flags = user_flags; + ret = drm_gem_handle_create(file, &obj->base, &handle); /* drop reference from allocate - handle hold
[Intel-gfx] [RFC-v18 10/13] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart Export PAVP client to work with i915_cp driver, for binding it uses kernel component framework. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 ++ drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c | 230 + drivers/misc/mei/pxp/mei_pxp.h | 18 +++ 6 files changed, 271 insertions(+) create mode 100644 drivers/misc/mei/pxp/Kconfig create mode 100644 drivers/misc/mei/pxp/Makefile create mode 100644 drivers/misc/mei/pxp/mei_pxp.c create mode 100644 drivers/misc/mei/pxp/mei_pxp.h diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index f5fd5b786607..0e0bcd0da852 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -47,3 +47,5 @@ config INTEL_MEI_TXE Intel Bay Trail source "drivers/misc/mei/hdcp/Kconfig" +source "drivers/misc/mei/pxp/Kconfig" + diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index f1c76f7ee804..d8e5165917f2 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o CFLAGS_mei-trace.o = -I$(src) obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/ +obj-$(CONFIG_INTEL_MEI_PXP) += pxp/ diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig new file mode 100644 index ..4029b96afc04 --- /dev/null +++ b/drivers/misc/mei/pxp/Kconfig @@ -0,0 +1,13 @@ + +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2020, Intel Corporation. All rights reserved. +# +config INTEL_MEI_PXP + tristate "Intel PXP services of ME Interface" + select INTEL_MEI_ME + depends on DRM_I915 + help + MEI Support for PXP Services on Intel platforms. + + Enables the ME FW services required for PXP support through + I915 display driver of Intel. diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile new file mode 100644 index ..0329950d5794 --- /dev/null +++ b/drivers/misc/mei/pxp/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2020, Intel Corporation. All rights reserved. +# +# Makefile - PXP client driver for Intel MEI Bus Driver. + +obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c new file mode 100644 index ..5bd61fe445e3 --- /dev/null +++ b/drivers/misc/mei/pxp/mei_pxp.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2020 Intel Corporation + */ + +/** + * DOC: MEI_PXP Client Driver + * + * The mei_pxp driver acts as a translation layer between PXP + * protocol implementer (I915) and ME FW by translating PXP + * negotiation messages to ME FW command payloads and vice versa. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mei_pxp.h" + +/** + * mei_pxp_send_message() - Sends a PXP message to ME FW. + * @dev: device corresponding to the mei_cl_device + * @message: a message buffer to send + * @size: size of the message + * Return: 0 on Success, <0 on Failure + */ +static int +mei_pxp_send_message(struct device *dev, const void *message, size_t size) +{ + struct mei_cl_device *cldev; + ssize_t byte; + + if (!dev || !message) + return -EINVAL; + + cldev = to_mei_cl_device(dev); + + /* temporary drop const qualifier till the API is fixed */ + byte = mei_cldev_send(cldev, (u8 *)message, size); + if (byte < 0) { + dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte); + return byte; + } + + return 0; +} + +/** + * mei_pxp_receive_message() - Receives a PXP message from ME FW. + * @dev: device corresponding to the mei_cl_device + * @buffer: a message buffer to contain the received message + * @size: size of the buffer + * Return: bytes sent on Success, <0 on Failure + */ +static int +mei_pxp_receive_message(struct device *dev, void *buffer, size_t size) +{ + struct mei_cl_device *cldev; + ssize_t byte; + + if (!dev || !buffer) + return -EINVAL; + + cldev = to_mei_cl_device(dev); + + byte = mei_cldev_recv(cldev, buffer, size); + if (byte < 0) { + dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte); + return byte; + } + + return byte; +} + +static const struct i915_pxp_component_ops mei_pxp_ops = { + .owner = THIS_MODULE, + .send = mei_pxp_send_message, + .receive = mei_pxp_receive_message, +}; + +static int mei_component_master_bind(struct device *dev) +{ + struct mei_cl_device *cldev = to_mei_cl_device(dev); + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev); + int ret; + + dev_dbg(dev, "%s\n", __func__); + comp_master->ops = &mei_pxp_ops; +
[Intel-gfx] [RFC-v18 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
Implement the funcs to create the TEE channel, so kernel can send the TEE commands directly to TEE for creating the arbitrary (defualt) session. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Makefile| 3 +- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 137 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++ include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 8 files changed, 211 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h create mode 100644 include/drm/i915_pxp_tee_interface.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 2a58cbd3e6fe..5a6a50b02e4e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -262,7 +262,8 @@ i915-y += i915_perf.o # Protected execution platform (PXP) support i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ - pxp/intel_pxp_context.o + pxp/intel_pxp_context.o \ + pxp/intel_pxp_tee.o # Post-mortem debug and GPU hang state capture i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 249f765993f7..d7cfc79e65c0 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) mutex_init(&dev_priv->wm.wm_mutex); mutex_init(&dev_priv->pps_mutex); mutex_init(&dev_priv->hdcp_comp_mutex); + mutex_init(&dev_priv->pxp_tee_comp_mutex); i915_memcpy_init_early(dev_priv); intel_runtime_pm_init_early(&dev_priv->runtime_pm); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5e5bcef20e33..c2f47daef5a5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1209,6 +1209,12 @@ struct drm_i915_private { /* Mutex to protect the above hdcp component related values. */ struct mutex hdcp_comp_mutex; + struct i915_pxp_comp_master *pxp_tee_master; + bool pxp_tee_comp_added; + + /* Mutex to protect the above pxp_tee component related values. */ + struct mutex pxp_tee_comp_mutex; + I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) /* diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index f566a4fda044..c819f3791ee4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -5,6 +5,7 @@ #include "i915_drv.h" #include "intel_pxp.h" #include "intel_pxp_context.h" +#include "intel_pxp_tee.h" /* KCR register definitions */ #define KCR_INIT_MMIO(0x320f0) @@ -23,6 +24,8 @@ void intel_pxp_init(struct intel_pxp *pxp) intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES); + intel_pxp_tee_component_init(pxp); + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); } @@ -33,5 +36,7 @@ void intel_pxp_fini(struct intel_pxp *pxp) if (INTEL_GEN(gt->i915) < 12) return; + intel_pxp_tee_component_fini(pxp); + intel_pxp_ctx_fini(&pxp->ctx); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c new file mode 100644 index ..5a1ffcc703e2 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ + +#include +#include "drm/i915_pxp_tee_interface.h" +#include "drm/i915_component.h" +#include "i915_drv.h" +#include "intel_pxp.h" +#include "intel_pxp_context.h" +#include "intel_pxp_tee.h" + +static int intel_pxp_tee_io_message(struct intel_pxp *pxp, + void *msg_in, u32 msg_in_size, + void *msg_out, u32 *msg_out_size_ptr, + u32 msg_out_buf_size) +{ + int ret; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + struct drm_i915_private *i915 = gt->i915; + struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master; + + if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr) + return -EINVAL; + + lockdep_assert_held(&i915->pxp_tee_comp_mutex); + + if (drm_debug_enabled(DRM_UT_DRIVER)) + print_hex_dump(KERN_DEBUG, "TEE input message binaries:", + DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size, true); + + ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size); + if (ret) { +
[Intel-gfx] [RFC-v18 08/13] drm/i915/pxp: Enable PXP power management
During the power event S3+ sleep/resume, hardware will lose all the encryption keys for every hardware session, even though the software session state was marked as alive after resume. So to handle such case, PXP should terminate all the hardware sessions and cleanup all the software states after the power cycle. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++ drivers/gpu/drm/i915/i915_drv.c| 4 ++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.c| 65 ++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.h| 31 +++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 + 6 files changed, 106 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 3e09ec7eb0d8..7b7bce0b227f 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -265,6 +265,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp_arb.o \ pxp/intel_pxp_cmd.o \ pxp/intel_pxp_context.o \ + pxp/intel_pxp_pm.o \ pxp/intel_pxp_tee.o # Post-mortem debug and GPU hang state capture diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index c94e8ac884eb..ae0387e419a2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -20,6 +20,7 @@ #include "intel_rc6.h" #include "intel_rps.h" #include "intel_wakeref.h" +#include "pxp/intel_pxp_pm.h" static void user_forcewake(struct intel_gt *gt, bool suspend) { @@ -266,6 +267,8 @@ int intel_gt_resume(struct intel_gt *gt) intel_uc_resume(>->uc); + intel_pxp_pm_resume(>->pxp); + user_forcewake(gt, false); out_fw: @@ -300,6 +303,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt) user_forcewake(gt, true); wait_for_suspend(gt); + intel_pxp_pm_prepare_suspend(>->pxp); intel_uc_suspend(>->uc); } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index d7cfc79e65c0..321db3400924 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -68,6 +68,8 @@ #include "gt/intel_gt_pm.h" #include "gt/intel_rc6.h" +#include "pxp/intel_pxp_pm.h" + #include "i915_debugfs.h" #include "i915_drv.h" #include "i915_ioc32.h" @@ -1339,6 +1341,8 @@ static int i915_drm_resume_early(struct drm_device *dev) intel_power_domains_resume(dev_priv); + intel_pxp_pm_resume_early(&dev_priv->gt.pxp); + enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); return ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c new file mode 100644 index ..ebe89262485c --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ + +#include "intel_pxp_context.h" +#include "intel_pxp_arb.h" +#include "intel_pxp_pm.h" + +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp) +{ + if (!pxp->ctx.inited) + return; + + mutex_lock(&pxp->ctx.mutex); + + /* Disable PXP-IOCTLs */ + pxp->ctx.global_state_in_suspend = true; + + mutex_unlock(&pxp->ctx.mutex); +} + +void intel_pxp_pm_resume_early(struct intel_pxp *pxp) +{ + if (!pxp->ctx.inited) + return; + + mutex_lock(&pxp->ctx.mutex); + + if (pxp->ctx.global_state_in_suspend) { + /* reset the attacked flag even there was a pending */ + pxp->ctx.global_state_attacked = false; + + pxp->ctx.flag_display_hm_surface_keys = false; + } + + mutex_unlock(&pxp->ctx.mutex); +} + +int intel_pxp_pm_resume(struct intel_pxp *pxp) +{ + int ret = 0; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + if (!pxp->ctx.inited) + return 0; + + mutex_lock(&pxp->ctx.mutex); + + /* Re-enable PXP-IOCTLs */ + if (pxp->ctx.global_state_in_suspend) { + ret = intel_pxp_arb_terminate_session(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to terminate the arb session\n"); + goto end; + } + + pxp->ctx.global_state_in_suspend = false; + } + +end: + mutex_unlock(&pxp->ctx.mutex); + + return ret; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h new file mode 100644 index ..135bfb59aaf7 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_PM_H__ +#define __INTEL_PXP_PM_H__ + +#include "i915_drv.h" + +#ifde
[Intel-gfx] [RFC-v18 07/13] drm/i915/pxp: Destroy arb session upon teardown
Teardown is triggered when the display topology changes and no long meets the secure playback requirement, and hardware trashes all the encryption keys for display. So as a result, PXP should handle such case and terminate the type0 sessions, which including arb session Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 130 ++- drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++- 5 files changed, 212 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index fa15e3ad2f92..23d4cfc1fb1f 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp) mutex_lock(&pxp->ctx.mutex); pxp->ctx.global_state_attacked = true; + pxp->ctx.flag_display_hm_surface_keys = false; + + ret = intel_pxp_arb_terminate_session(pxp); mutex_unlock(&pxp->ctx.mutex); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c index 4df58915af88..2038d4638711 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c @@ -10,6 +10,7 @@ #include "intel_pxp_arb.h" #include "intel_pxp.h" #include "intel_pxp_tee.h" +#include "intel_pxp_cmd.h" #define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */ @@ -129,3 +130,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp) return ret; } + +static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp) +{ + u32 *cmd = NULL; + u32 *cmd_ptr = NULL; + int cmd_size_in_dw = 0; + int ret; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + /* Calculate how many bytes need to be alloc */ + cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE, ARB_SESSION_INDEX); + cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL); + cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL); + + cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + /* Program the command */ + cmd_ptr = cmd; + cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE, ARB_SESSION_INDEX); + cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr); + cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr); + + if (cmd_size_in_dw != (cmd_ptr - cmd)) { + ret = -EINVAL; + drm_err(>->i915->drm, "Failed to %s\n", __func__); + goto end; + } + + if (drm_debug_enabled(DRM_UT_DRIVER)) { + print_hex_dump(KERN_DEBUG, "global termination cmd binaries:", + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true); + } + + ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw); + if (ret) { + drm_err(>->i915->drm, "Failed to intel_pxp_cmd_submit()\n"); + goto end; + } + +end: + kfree(cmd); + return ret; +} + +/** + * intel_pxp_arb_terminate_session - Terminate the arb hw session and its entries. + * @pxp: pointer to pxp struct. + * + * This function is NOT intended to be called from the ioctl, and need to be protected by + * ctx.mutex to ensure no SIP change during the call. + * + * Return: status. 0 means terminate is successful. + */ +int intel_pxp_arb_terminate_session(struct intel_pxp *pxp) +{ + int ret; + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + struct pxp_protected_session *arb = &pxp->ctx.arb_session; + + lockdep_assert_held(&pxp->ctx.mutex); + + /* terminate the hw sessions */ + ret = intel_pxp_arb_session_with_global_termination(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to intel_pxp_arb_session_with_global_termination\n"); + return ret; + } + + arb->is_in_play = false; + + return ret; +} + diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h index 1eb8db6deb0e..c1ed4ab176aa 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h @@ -11,5 +11,6 @@ struct intel_pxp; int intel_pxp_arb_create_session(struct intel_pxp *pxp); +int intel_pxp_arb_terminate_session(struct intel_pxp *pxp); #endif /* __INTEL_PXP_ARB_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c index d9298cf5e1a7..ae338ab2e629 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c @@ -5,13 +5,33 @@ #include "intel_pxp_cmd.h" #include "i915_drv.h" +#include "gt/intel_gp
[Intel-gfx] [RFC-v18 04/13] drm/i915/pxp: Create the arbitrary session after boot
Create the arbitrary session, with the fixed session id 0xf, after system boot, for the case that application allocates the protected buffer without establishing any protection session. Because the hardware requires at least one alive session for protected buffer creation. This arbitrary session needs to be re-created after teardown or power event because hardware encryption key won't be valid after such cases. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++ drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 131 +++ drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 15 +++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 70 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 + drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 26 9 files changed, 264 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5a6a50b02e4e..bb6a93cb6cdf 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -262,6 +262,7 @@ i915-y += i915_perf.o # Protected execution platform (PXP) support i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ + pxp/intel_pxp_arb.o \ pxp/intel_pxp_context.o \ pxp/intel_pxp_tee.o diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index c819f3791ee4..3868e8c697f9 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -6,6 +6,7 @@ #include "intel_pxp.h" #include "intel_pxp_context.h" #include "intel_pxp_tee.h" +#include "intel_pxp_arb.h" /* KCR register definitions */ #define KCR_INIT_MMIO(0x320f0) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index f47bc6bea34f..8fc91e900b16 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -8,6 +8,22 @@ #include "intel_pxp_types.h" +enum pxp_session_types { + SESSION_TYPE_TYPE0 = 0, + SESSION_TYPE_TYPE1 = 1, + + SESSION_TYPE_MAX +}; + +enum pxp_protection_modes { + PROTECTION_MODE_NONE = 0, + PROTECTION_MODE_LM = 2, + PROTECTION_MODE_HM = 3, + PROTECTION_MODE_SM = 6, + + PROTECTION_MODE_ALL +}; + #ifdef CONFIG_DRM_I915_PXP void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c new file mode 100644 index ..4df58915af88 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#include "gt/intel_context.h" +#include "gt/intel_engine_pm.h" + +#include "intel_pxp_types.h" +#include "intel_pxp_arb.h" +#include "intel_pxp.h" +#include "intel_pxp_tee.h" + +#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */ + +/* Arbitrary session */ +#define ARB_SESSION_INDEX 0xf +#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0 + +static bool is_hw_arb_session_in_play(struct intel_pxp *pxp) +{ + u32 regval_sip = 0; + intel_wakeref_t wakeref; + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + + with_intel_runtime_pm(>->i915->runtime_pm, wakeref) { + regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP); + } + + return regval_sip & BIT(ARB_SESSION_INDEX); +} + +/* wait hw session_in_play reg to match the current sw state */ +static int wait_arb_hw_sw_state(struct intel_pxp *pxp) +{ + const int max_retry = 10; + const int ms_delay = 10; + int retry = 0; + int ret; + struct pxp_protected_session *arb = &pxp->ctx.arb_session; + + ret = -EINVAL; + for (retry = 0; retry < max_retry; retry++) { + if (is_hw_arb_session_in_play(pxp) == + arb->is_in_play) { + ret = 0; + break; + } + + msleep(ms_delay); + } + + return ret; +} + +static void arb_session_entry_init(struct intel_pxp *pxp) +{ + struct pxp_protected_session *arb = &pxp->ctx.arb_session; + + arb->type = ARB_SESSION_TYPE; + arb->protection_mode = PROTECTION_MODE_HM; + arb->index = ARB_SESSION_INDEX; + arb->is_in_play = false; +} + +static int intel_pxp_arb_reserve_session(struct intel_pxp *pxp) +{ + int ret; + + lockdep_assert_held(&pxp->ctx.mutex); + + arb_session_entry_init(pxp); + ret = wait_arb_hw_sw_state(pxp); + + return ret; +} + +/** + * intel_pxp_arb_mark_session_in_play -
[Intel-gfx] [RFC-v18 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext
From: Bommu Krishnaiah Same old gem_create but with now with extensions support. This is needed to support various upcoming usecases. For now we use the extensions mechanism to support PAVP. Signed-off-by: Bommu Krishnaiah Signed-off-by: Matthew Auld Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com Cc: Matthew Auld matthew.a...@intel.com Cc: Telukuntla Sreedhar --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_gem.c | 42 - include/uapi/drm/i915_drm.h | 47 + 3 files changed, 89 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 321db3400924..ed31e804afaa 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1728,7 +1728,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 17a4636ee542..c53b13c02e59 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -53,6 +53,7 @@ #include "i915_drv.h" #include "i915_trace.h" #include "i915_vgpu.h" +#include "i915_user_extensions.h" #include "intel_pm.h" @@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file, &args->size, &args->handle); } +struct create_ext { +struct drm_i915_private *i915; +}; + +static int __create_setparam(struct drm_i915_gem_object_param *args, + struct create_ext *ext_data) +{ + if (!(args->param & I915_OBJECT_PARAM)) { + DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n"); + return -EINVAL; + } + + return -EINVAL; +} + +static int create_setparam(struct i915_user_extension __user *base, void *data) +{ + struct drm_i915_gem_create_ext_setparam ext; + + if (copy_from_user(&ext, base, sizeof(ext))) + return -EFAULT; + + return __create_setparam(&ext.param, data); +} + +static const i915_user_extension_fn create_extensions[] = { + [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam, +}; + /** * Creates a new mm object and returns a handle to it. * @dev: drm device pointer @@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { struct drm_i915_private *i915 = to_i915(dev); - struct drm_i915_gem_create *args = data; + struct create_ext ext_data = { .i915 = i915 }; + struct drm_i915_gem_create_ext *args = data; + int ret; i915_gem_flush_free_objects(i915); + ret = i915_user_extensions(u64_to_user_ptr(args->extensions), + create_extensions, + ARRAY_SIZE(create_extensions), + &ext_data); + if (ret) + return ret; + + return i915_gem_create(file, intel_memory_region_by_type(i915, INTEL_MEMORY_SYSTEM), diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 1987e2ea79a3..f9a1d26824b6 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext) #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) #define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) @@ -729,6 +730,27 @@ struct drm_i915_gem_create { __u32 pad; }; +struct drm_i915_gem_create_ext { + /** +* Requested size fo
[Intel-gfx] [RFC-v18 05/13] drm/i915/pxp: Func to send hardware session termination
Implement the functions to allow PXP to send a GPU command, in order to terminate the hardware session, so hardware can recycle this session slot for the next usage. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 ++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 158 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 + 5 files changed, 194 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index bb6a93cb6cdf..3e09ec7eb0d8 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -263,6 +263,7 @@ i915-y += i915_perf.o i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp.o \ pxp/intel_pxp_arb.o \ + pxp/intel_pxp_cmd.o \ pxp/intel_pxp_context.o \ pxp/intel_pxp_tee.o diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 3868e8c697f9..2f63801748f8 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -17,10 +17,23 @@ void intel_pxp_init(struct intel_pxp *pxp) { struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + int i; if (INTEL_GEN(gt->i915) < 12) return; + /* Find the first VCS engine present */ + for (i = 0; i < I915_MAX_VCS; i++) { + if (HAS_ENGINE(gt, _VCS(i))) { + pxp->vcs_engine = gt->engine[_VCS(i)]; + break; + } + } + if (!pxp->vcs_engine) { + drm_err(>->i915->drm, "Could not find a VCS engine\n"); + return; + } + intel_pxp_ctx_init(&pxp->ctx); intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c new file mode 100644 index ..d9298cf5e1a7 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#include "intel_pxp_cmd.h" +#include "i915_drv.h" +#include "gt/intel_context.h" +#include "gt/intel_engine_pm.h" + +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp, +struct intel_context *ce, +struct intel_gt_buffer_pool_node *pool, +u32 *cmd_buf, int cmd_size_in_dw) +{ + struct i915_vma *batch = ERR_PTR(-EINVAL); + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + u32 *cmd; + + if (!ce || !ce->engine || !cmd_buf) + return ERR_PTR(-EINVAL); + + if (cmd_size_in_dw * 4 > PAGE_SIZE) { + drm_err(>->i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n", + __func__, cmd_size_in_dw); + return ERR_PTR(-EINVAL); + } + + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC); + if (IS_ERR(cmd)) { + drm_err(>->i915->drm, "Failed to i915_gem_object_pin_map()\n"); + return ERR_PTR(-EINVAL); + } + + memcpy(cmd, cmd_buf, cmd_size_in_dw * 4); + + if (drm_debug_enabled(DRM_UT_DRIVER)) { + print_hex_dump(KERN_DEBUG, "cmd binaries:", + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true); + } + + i915_gem_object_unpin_map(pool->obj); + + batch = i915_vma_instance(pool->obj, ce->vm, NULL); + if (IS_ERR(batch)) { + drm_err(>->i915->drm, "Failed to i915_vma_instance()\n"); + return batch; + } + + return batch; +} + +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw) +{ + int err = -EINVAL; + struct i915_vma *batch; + struct i915_request *rq; + struct intel_context *ce = NULL; + bool is_engine_pm_get = false; + bool is_batch_vma_pin = false; + bool is_skip_req_on_err = false; + bool is_engine_get_pool = false; + struct intel_gt_buffer_pool_node *pool = NULL; + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); + + ce = pxp->vcs_engine->kernel_context; + if (!ce) { + drm_err(>->i915->drm, "VCS engine does not have context\n"); + err = -EINVAL; + goto end; + } + + if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) { + drm_err(>->i915->drm, "Failed to %s bad params\n", __func__); + return -EINVAL; + } + + intel_engine_pm_get(ce->engine); + is_engine_pm_get = true; + + pool = intel_gt_get_b
[Intel-gfx] [RFC-v18 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
Create the irq worker that serves as callback handler, those callback stubs should be called while the hardware key teardown occurs. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 + drivers/gpu/drm/i915/i915_reg.h | 3 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 24 - drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 + drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 - drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++ 7 files changed, 139 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 9830342aa6f4..b92072554ab3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -14,6 +14,7 @@ #include "intel_lrc_reg.h" #include "intel_uncore.h" #include "intel_rps.h" +#include "pxp/intel_pxp.h" static void guc_irq_handler(struct intel_guc *guc, u16 iir) { @@ -107,6 +108,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, if (instance == OTHER_GTPM_INSTANCE) return gen11_rps_irq_handler(>->rps, iir); + if (instance == OTHER_KCR_INSTANCE) + return intel_pxp_irq_handler(>->pxp, iir); + WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", instance, iir); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0023c023f472..1e8dfe435ca8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7944,6 +7944,7 @@ enum { /* irq instances for OTHER_CLASS */ #define OTHER_GUC_INSTANCE 0 #define OTHER_GTPM_INSTANCE1 +#define OTHER_KCR_INSTANCE 4 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) @@ -7966,7 +7967,7 @@ enum { #define GEN11_VECS0_VECS1_INTR_MASK_MMIO(0x1900d0) #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) -#define GEN11_CRYPTO_RSVD_INTR_MASK_MMIO(0x1900f0) +#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */ #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) #define ENGINE1_MASK REG_GENMASK(31, 16) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 2f63801748f8..fa15e3ad2f92 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -14,6 +14,70 @@ /* Setting KCR Init bit is required after system boot */ #define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT)) +static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask) +{ + lockdep_assert_held(>->irq_lock); + + intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16); +} + +static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp) +{ + int ret; + + mutex_lock(&pxp->ctx.mutex); + + pxp->ctx.global_state_attacked = true; + + mutex_unlock(&pxp->ctx.mutex); + + return ret; +} + +static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp) +{ + int ret = 0; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + mutex_lock(&pxp->ctx.mutex); + + if (pxp->ctx.global_state_attacked) { + pxp->ctx.global_state_attacked = false; + + /* Re-create the arb session after teardown handle complete */ + ret = intel_pxp_arb_create_session(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to create arb session\n"); + goto end; + } + } +end: + mutex_unlock(&pxp->ctx.mutex); + return ret; +} + +static void intel_pxp_irq_work(struct work_struct *work) +{ + struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work); + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + u32 events = 0; + + spin_lock_irq(>->irq_lock); + events = fetch_and_zero(&pxp->current_events); + spin_unlock_irq(>->irq_lock); + + if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED || + events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ) + intel_pxp_teardown_required_callback(pxp); + + if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE) + intel_pxp_global_terminate_complete_callback(pxp); + + spin_lock_irq(>->irq_lock); + intel_pxp_write_irq_mask_reg(gt, 0); + spin_unlock_irq(>->irq_lock); +} + void intel_pxp_init(struct intel_pxp *pxp) { struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); @@ -40,6 +104,12 @@ void intel_pxp_init(struct intel_pxp *pxp) intel_pxp_tee_component_init(pxp); + INIT_WORK(&pxp->irq_work, intel_pxp_irq_work); + +
[Intel-gfx] [RFC-v18 13/13] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta Add support to enable/disable PLANE_SURF Decryption Request bit. It requires only to enable plane decryption support when following condition met. 1. PAVP session is enabled. 2. Buffer object is protected. v2: - Rebased to libva_cp-drm-tip_tgl_cp tree. - Used gen fb obj user_flags instead gem_object_metadata. [Krishna] Cc: Bommu Krishnaiah Cc: Huang, Sean Z Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++--- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index cf3589fd0ddb..39f8c922ce66 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -39,6 +39,8 @@ #include #include +#include "pxp/intel_pxp.h" + #include "i915_drv.h" #include "i915_trace.h" #include "i915_vgpu.h" @@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane, PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } +static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj) +{ + return obj->user_flags & I915_BO_PROTECTED ? true : false; +} + static void skl_plane_async_flip(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, @@ -804,6 +811,7 @@ skl_program_plane(struct intel_plane *plane, u32 surf_addr = plane_state->color_plane[color_plane].offset; u32 stride = skl_plane_stride(plane_state, color_plane); const struct drm_framebuffer *fb = plane_state->hw.fb; + const struct drm_i915_gem_object *obj = intel_fb_obj(fb); int aux_plane = intel_main_to_aux_plane(fb, color_plane); int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; @@ -814,7 +822,7 @@ skl_program_plane(struct intel_plane *plane, u8 alpha = plane_state->hw.alpha >> 8; u32 plane_color_ctl = 0, aux_dist = 0; unsigned long irqflags; - u32 keymsk, keymax; + u32 keymsk, keymax, plane_surf; u32 plane_ctl = plane_state->ctl; plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -890,8 +898,15 @@ skl_program_plane(struct intel_plane *plane, * the control register just before the surface register. */ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr; + + if (intel_pxp_gem_object_status(dev_priv) && + intel_fb_obj_protected(obj)) + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED; + else + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED; + + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); if (plane_state->scaler_id >= 0) skl_program_scaler(plane, crtc_state, plane_state); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1e8dfe435ca8..0ea7e2a402ae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7209,6 +7209,7 @@ enum { #define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) #define PLANE_SURF(pipe, plane)\ _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) +#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2) #define _PLANE_OFFSET_1_B 0x711a4 #define _PLANE_OFFSET_2_B 0x712a4 -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v18 00/13] Introduce Intel PXP component - Mesa single session
PXP (Protected Xe Path) is an i915 component, available on GEN12+ that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. This patch series is to allow the kernel space to create and manage a single hardware session (a.k.a. default session or arbitrary session). So user can allocate the protected buffer, which is encrypted with the leverage of the arbitrary hardware session. v2: - modification based on code review feedbacks received - passing pxp instead of i915 as function argument - remove dead code only for multi-session - move the pxp init call from i915_drv.c to intel_gt.c - remove the tautology naming v3: - rebase to latest drm-tip v4: - Append the split non-mesa patch sereis (commit #14 - #21) into this patch series v5: - include "intel_pxp.h" in intel_pxp_sm.h at commit #14 to fix the build problem. v6: - Fix the null pointer arb_session access bug in intel_pxp_arb.c in "04 [RFC-v5] drm/i915/pxp: Create the arbitrary session after boot" v7: - Use list_for_each_entry_safe instead of list_for_each_entry v8: - Add MEI vtag support for PXP multi-session usage v9: - Fix error handling bug in commit #5 "Func to send hardware session termination". In intel_pxp_cmd.c, we should properly assign "err = PTR_ERR(x)" if hitting the error case "IS_ERR(x)", this is the only change in v9. v10 - Remove the multi session commits #14-#21, for now we would like to keep the multi session patches as downstream. - Adopt the code review suggestion from Wilson in commit #1 v11 - In commit #05 "drm/i915/pxp: Func to send hardware session termination", we should not assume VCS0 is always on. Instead we use available VCS#, could be VCS0, VCS2, etc. v12 - Add "#include in #1 intel_pxp_types.h v13 - Add "#include in #1 intel_pxp_types.h (#v12 didn't actually update the _types.h file...) v14 - Add "if (INTEL_GEN(gt->i915) < 12) return;" in #1 intel_pxp_fini(), just skip for non gen12+ sku v15 In #04: - Make intel_pxp_arb_reserve_session() as static function to fix the sparse warning - Update value of PXP_TEE_ARB_CMD_BIN v16 In #04: - Remove the binary from source code via defining the TEE command header v17 In #04, directly return intel_pxp_tee_component_fini() if pxp_tee_comp_added is off v18 - In #09, Add intel_pxp_gem_context_set_protected() to check the arb session before setting protected flag for gem context - In #12, Replace i915_gem_context_set_protected() with intel_pxp_gem_context_set_protected() to check whether the arbitrary session is alive Anshuman Gupta (1): drm/i915/pxp: Add plane decryption support Bommu Krishnaiah (2): drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915/pxp: User interface for Protected buffer Huang, Sean Z (9): drm/i915/pxp: Introduce Intel PXP component drm/i915/pxp: set KCR reg init during the boot time drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Func to send hardware session termination drm/i915/pxp: Enable PXP irq worker and callback stub drm/i915/pxp: Destroy arb session upon teardown drm/i915/pxp: Enable PXP power management drm/i915/pxp: Expose session state for display protection flip Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Kconfig | 22 ++ drivers/gpu/drm/i915/Makefile | 9 + drivers/gpu/drm/i915/display/intel_sprite.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 19 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 + drivers/gpu/drm/i915/gt/intel_gt.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/i915_drv.c | 7 +- drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_gem.c | 63 +++- drivers/gpu/drm/i915/i915_reg.h | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 181 drivers/gpu/drm/i915/pxp/intel_pxp.h | 81 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 207 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 17 ++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 278 ++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 20 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++ drivers/g
[Intel-gfx] [RFC-v18 02/13] drm/i915/pxp: set KCR reg init during the boot time
Set the KCR init during the boot time, which is required by hardware, to allow us doing further protection operation such as sending commands to GPU or TEE. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 9bc3c7e30654..f566a4fda044 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -6,6 +6,12 @@ #include "intel_pxp.h" #include "intel_pxp_context.h" +/* KCR register definitions */ +#define KCR_INIT_MMIO(0x320f0) +#define KCR_INIT_MASK_SHIFT (16) +/* Setting KCR Init bit is required after system boot */ +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT)) + void intel_pxp_init(struct intel_pxp *pxp) { struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); @@ -15,6 +21,8 @@ void intel_pxp_init(struct intel_pxp *pxp) intel_pxp_ctx_init(&pxp->ctx); + intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES); + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); } -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v18 09/13] drm/i915/pxp: Expose session state for display protection flip
Implement the intel_pxp_gem_object_status() to allow i915 display querying the current PXP session state. In the design, display should not perform protection flip on the protected buffers if there is no PXP session alive. And Implement the funciton to set the protected flag for gem context. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 21 + drivers/gpu/drm/i915/pxp/intel_pxp.h | 18 ++ drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 4 ++-- drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 + 4 files changed, 42 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 23d4cfc1fb1f..a28a459532c2 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -158,3 +158,24 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) pxp->current_events |= events; schedule_work(&pxp->irq_work); } + +bool intel_pxp_gem_object_status(struct drm_i915_private *i915) +{ + if (i915->gt.pxp.ctx.inited && + i915->gt.pxp.ctx.flag_display_hm_surface_keys) + return true; + else + return false; +} + +int intel_pxp_gem_context_set_protected(struct drm_i915_private *i915, + unsigned long *user_flags, + u32 protected_bit) +{ + if (!user_flags || !protected_bit || + !intel_pxp_arb_session_is_in_play(&i915->gt.pxp)) + return -EINVAL; + + set_bit(protected_bit, user_flags); + return 0; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index cdaa6ce6fdca..ff1c1c0e720c 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -29,6 +29,8 @@ enum pxp_protection_modes { PROTECTION_MODE_ALL }; +struct drm_i915_private; + #ifdef CONFIG_DRM_I915_PXP void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); int i915_pxp_teardown_required_callback(struct intel_pxp *pxp); @@ -36,6 +38,10 @@ int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp); void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); +bool intel_pxp_gem_object_status(struct drm_i915_private *i915); +int intel_pxp_gem_context_set_protected(struct drm_i915_private *i915, + unsigned long *user_flag, + u32 protected_bit); #else static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) { @@ -58,6 +64,18 @@ static inline void intel_pxp_init(struct intel_pxp *pxp) static inline void intel_pxp_fini(struct intel_pxp *pxp) { } + +static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915) +{ + return false; +} + +static inline int intel_pxp_gem_context_set_protected(struct drm_i915_private *i915, + unsigned long *user_flag, + u32 protected_bit) +{ + return 0; +} #endif #endif /* __INTEL_PXP_H__ */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c index 2038d4638711..1d2ec8ffd7ad 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c @@ -18,7 +18,7 @@ #define ARB_SESSION_INDEX 0xf #define ARB_SESSION_TYPE SESSION_TYPE_TYPE0 -static bool is_hw_arb_session_in_play(struct intel_pxp *pxp) +bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp) { u32 regval_sip = 0; intel_wakeref_t wakeref; @@ -42,7 +42,7 @@ static int wait_arb_hw_sw_state(struct intel_pxp *pxp) ret = -EINVAL; for (retry = 0; retry < max_retry; retry++) { - if (is_hw_arb_session_in_play(pxp) == + if (intel_pxp_arb_session_is_in_play(pxp) == arb->is_in_play) { ret = 0; break; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h index c1ed4ab176aa..42261ef33a03 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h @@ -12,5 +12,6 @@ struct intel_pxp; int intel_pxp_arb_create_session(struct intel_pxp *pxp); int intel_pxp_arb_terminate_session(struct intel_pxp *pxp); +bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp); #endif /* __INTEL_PXP_ARB_H__ */ -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v18 01/13] drm/i915/pxp: Introduce Intel PXP component
PXP (Protected Xe Path) is an i915 componment, available on GEN12+, that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. This patch series is to allow the kernel space to create and manage a single hardware session (a.k.a default session or arbitrary session). So Mesa can allocate the protected buffer, which is encrypted with the leverage of the arbitrary hardware session. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Kconfig | 22 +++ drivers/gpu/drm/i915/Makefile| 5 drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 + drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 + drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 23 9 files changed, 151 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 1e1cb245fca7..594775c11e19 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -130,6 +130,28 @@ config DRM_I915_GVT_KVMGT Choose this option if you want to enable KVMGT support for Intel GVT-g. +config DRM_I915_PXP + bool "Enable Intel PXP support for Intel Gen12+ platform" + depends on DRM_I915 + select INTEL_MEI + select INTEL_MEI_ME + select INTEL_MEI_TXE + select INTEL_MEI_PXP + default y + help + This option selects INTEL_MEI_ME if it isn't already selected to + enabled full PXP Services on Intel platforms. + + PXP (Protected Xe Path) is an i915 componment, available on GEN12+, + that helps to establish the hardware protected session and manage + the status of the alive software session, as well as its life cycle. + + This patch series is to allow the kernel space to create and + manage a single hardware session (a.k.a default session or + arbitrary session). So Mesa can allocate the protected buffer, + which is encrypted with the leverage of the arbitrary hardware + session. + menu "drm/i915 Debugging" depends on DRM_I915 depends on EXPERT diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index f1c7c3246226..2a58cbd3e6fe 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -259,6 +259,11 @@ i915-y += \ i915-y += i915_perf.o +# Protected execution platform (PXP) support +i915-$(CONFIG_DRM_I915_PXP) += \ + pxp/intel_pxp.o \ + pxp/intel_pxp_context.o + # Post-mortem debug and GPU hang state capture i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o i915-$(CONFIG_DRM_I915_SELFTEST) += \ diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index d8e1ab412634..fb8a4740bb40 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -18,6 +18,7 @@ #include "intel_uncore.h" #include "intel_pm.h" #include "shmem_utils.h" +#include "pxp/intel_pxp.h" void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) { @@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt) if (err) goto err_gt; + intel_pxp_init(>->pxp); + goto out_fw; err_gt: __intel_gt_disable(gt); @@ -638,6 +641,7 @@ void intel_gt_driver_release(struct intel_gt *gt) if (vm) /* FIXME being called twice on error paths :( */ i915_vm_put(vm); + intel_pxp_fini(>->pxp); intel_gt_pm_fini(gt); intel_gt_fini_scratch(gt); intel_gt_fini_buffer_pool(gt); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index a83d3e18254d..c4760e2722fd 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -23,6 +23,7 @@ #include "intel_rc6_types.h" #include "intel_rps_types.h" #include "intel_wakeref.h" +#include "pxp/intel_pxp_types.h" struct drm_i915_private; struct i915_ggtt; @@ -145,6 +146,8 @@ struct intel_gt { /* Slice/subslice/EU info */ struct sseu_dev_info sseu; } info; + + struct intel_pxp pxp; }; enum intel_gt_scratch_field { diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c new file mode 100644 index ..9bc3c7e30654 --- /dev/null +++ b/drivers/gpu/drm/i
Re: [Intel-gfx] [PATCH V2] drm/i915/cml : Add TGP PCH support
> -Original Message- > From: Matt Roper > Sent: 01 January 2021 02:32 > To: Surendrakumar Upadhyay, TejaskumarX > > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom > > Subject: Re: [Intel-gfx] [PATCH V2] drm/i915/cml : Add TGP PCH support > > On Thu, Dec 31, 2020 at 12:48:06AM -0800, Surendrakumar Upadhyay, > TejaskumarX wrote: > > > > > > > -Original Message- > > > From: Matt Roper > > > Sent: 31 December 2020 05:31 > > > To: Surendrakumar Upadhyay, TejaskumarX > > > > > > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom > > > > > > Subject: Re: [Intel-gfx] [PATCH V2] drm/i915/cml : Add TGP PCH > > > support > > > > > > On Mon, Dec 28, 2020 at 11:42:35AM +0530, Tejas Upadhyay wrote: > > > > We have TGP PCH support for Tigerlake and Rocketlake. Similarly > > > > now TGP PCH can be used with Cometlake CPU. > > > > > > Based on the 'compatibility' section of bspec 49181, I think the TGP > > > PCH can technically be compatible with any gen9bc platform, not just > CML. > > > Although it seems unlikely that anyone is going to go back and > > > create new products with a SKL+TGP pairing or something at this > > > point, it's still probably best to write this patch based on GEN9_BC > > > rather > than CML. > > > > > > > > > Tejas : This patch is generated to support DELL's requirement where they > are using CML CPU + TGP PCH. But I agree if we want to change CML with > GEN9_BC. Please have a look at https://gitlab.freedesktop.org/drm/intel/- > /issues/2742 and this patch has been verified by DELL as working for all of > their platforms with CML CPU + TGP PCH (Off course it worked after I gave > local workaround of Lee Shawn's patch > https://patchwork.freedesktop.org/patch/401301/?series=83154&rev=5). > Also this patch + > https://patchwork.freedesktop.org/patch/401301/?series=83154&rev=5 (Lee > Shawn's patch reviewed by you) + Adding IS_COMETLAKE check to Lee > Shawn's patch needs to be merged by Jan 4th to complete upstreaming for > CML CPU + TGP PCH. DELL is having critical requirement to finish upstreaming > by Jan 4th. > > The changes from Shawn are to make RKL (a gen12 platform) work with the > older gen9-style CMP PCH. What you're doing here is making a gen9 > platform work with a newer gen12-style TGP PCH. Although those are > converses of each other, I don't think the driver changes should depend on > each other. Shawn's series shouldn't be necessary for your work or vice > versa. I'm not sure when Shawn plans to merge his series; I had some > further changes suggested, so he might be working on those before merging > his work. Tejas : Just to bring your attention here that RKL RVP ddc_pins are not mapped correctly with TGP PCH currently, specially when it comes to remapping of VBT values to platform. I think Shawn's patch is addressing that as well. I have tested RKL RVP we don't have right ddc pin mapping currently thus there was problem in detection of ports. Please check https://jira.devtools.intel.com/browse/VLK-16850 (ignore "port C" wording in VLK, its port TC1). Please suggest if I need to create patch for VBT remap for CML/GEN9BC on top of Shawn's patch or I can send as part of this patchset? > > I'm not sure what leads to the Jan 4th date, but assuming "finish > upstreaming" means that you want the patch to land in a final release kernel > by that date, there's pretty much no way that would be possible at this point. > Getting patches like this reviewed and applied to an Intel tree is only the > first > step along the maintainer chain that eventually leads to a release from Linus > or a stable kernel maintainer. > Plus when a customer says they want something upstream, one of the most > important things for them is that the patch has been fully reviewed and > tested and has a relatively high chance of being correct. We can't rush > patches in to meet deadlines if we think they're only going to work in certain > situations and cause problems for other ones. > > One other thing that I don't see addressed anywhere in this patch is that the > driver doesn't consider gen9 + TGP to be a valid combination and will throw a > warning in intel_pch_type() if detected. Tejas : Yes I am planning to add GEN9 + TGP as valid combo, so it does not throw warning. And about the deadline, we will follow our process for sure. > > > > > > > > > > > Changes since V1 : > > > > - Matched HPD Pin mapping for PORT C and PORT D of CML CPU. > > > > > > > > Cc : Matt Roper Cc : Ville Syrjälä > > > > > > > > Signed-off-by: Tejas Upadhyay > > > > > > > > --- > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +-- > > > > drivers/gpu/drm/i915/display/intel_display.c | 5 + > > > > drivers/gpu/drm/i915/display/intel_hdmi.c| 3 ++- > > > > 3 files changed, 12 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > index 17eaa56c5a99..181d60a5e145 100
Re: [Intel-gfx] [PATCH] [v2] i915: fix shift warning
Quoting Arnd Bergmann (2021-01-03 13:51:44) > From: Arnd Bergmann > > Randconfig builds on 32-bit machines show lots of warnings for > the i915 driver for passing a 32-bit value into __const_hweight64(): > > drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2584:9: error: shift count >= > width of type [-Werror,-Wshift-count-overflow] > return hweight64(VDBOX_MASK(&i915->gt)); >^~~~ > include/asm-generic/bitops/const_hweight.h:29:49: note: expanded from macro > 'hweight64' > #define hweight64(w) (__builtin_constant_p(w) ? __const_hweight64(w) : > __arch_hweight64(w)) > > Change it to hweight_long() to avoid the warning. > > Signed-off-by: Arnd Bergmann Reviewed-by:: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx